diff --git a/drivers/staging/media/Kconfig b/drivers/staging/media/Kconfig index ffb8fa72c3dabdb5abf045d3bc1dcb584e3ede71..5a26eb211c7a80da209b97e9412407ba618e5c21 100644 --- a/drivers/staging/media/Kconfig +++ b/drivers/staging/media/Kconfig @@ -34,4 +34,5 @@ source "drivers/staging/media/lirc/Kconfig" source "drivers/staging/media/st-cec/Kconfig" +source "drivers/staging/media/atomisp/Kconfig" endif diff --git a/drivers/staging/media/Makefile b/drivers/staging/media/Makefile index a28e82cf6447a932c92a807b0aa290dfa56aae04..ab60a89c6593a29b7da1df4c8a01d2f2b4139c3a 100644 --- a/drivers/staging/media/Makefile +++ b/drivers/staging/media/Makefile @@ -5,3 +5,4 @@ obj-$(CONFIG_LIRC_STAGING) += lirc/ obj-$(CONFIG_VIDEO_DM365_VPFE) += davinci_vpfe/ obj-$(CONFIG_VIDEO_OMAP4) += omap4iss/ obj-$(CONFIG_VIDEO_STI_HDMI_CEC) += st-cec/ +obj-$(CONFIG_INTEL_ATOMISP) += atomisp/ diff --git a/drivers/staging/media/atomisp/Kconfig b/drivers/staging/media/atomisp/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..f7d8a841c629a10b842ea419aa03a882abce0e6b --- /dev/null +++ b/drivers/staging/media/atomisp/Kconfig @@ -0,0 +1,11 @@ +menuconfig INTEL_ATOMISP + bool "Enable support to Intel MIPI camera drivers" + depends on X86 + help + Enable support for the Intel ISP2 camera interfaces and MIPI + sensor drivers. + +if INTEL_ATOMISP +source "drivers/staging/media/atomisp/pci/Kconfig" +source "drivers/staging/media/atomisp/i2c/Kconfig" +endif diff --git a/drivers/staging/media/atomisp/Makefile b/drivers/staging/media/atomisp/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..e16752e6af792bc5ad038a1914e4d6fcd65b5d9e --- /dev/null +++ b/drivers/staging/media/atomisp/Makefile @@ -0,0 +1,8 @@ +# +# Makefile for camera drivers. +# + +obj-$(CONFIG_INTEL_ATOMISP) += pci/ +obj-$(CONFIG_INTEL_ATOMISP) += i2c/ +obj-$(CONFIG_INTEL_ATOMISP) += platform/ +LINUXINCLUDE += -I drivers/staging/media/atomisp/include/ diff --git a/drivers/staging/media/atomisp/TODO b/drivers/staging/media/atomisp/TODO new file mode 100644 index 0000000000000000000000000000000000000000..737452cbf8a095c3595a4b40650fdfebbf9787b4 --- /dev/null +++ b/drivers/staging/media/atomisp/TODO @@ -0,0 +1,64 @@ +1. A single AtomISP driver needs to be implemented to support both BYT and + CHT platforms. The current driver is a mechanical and hand combined merge + of the two using an ifdef ISP2401 to select the CHT version, which at the + moment is not enabled. Eventually this should become a runtime if check, + but there are some quite tricky things that need sorting out before that + will be possible. + +2. The file structure needs to get tidied up to resemble a normal Linux + driver. + +3. Lots of the midlayer glue. unused code and abstraction needs removing. + +3. The sensor drivers read MIPI settings from EFI variables or default to the + settings hard-coded in the platform data file for different platforms. + This isn't ideal but may be hard to improve as this is how existing + platforms work. + +4. The sensor drivers use the regulator framework API. In the ideal world it + would be using ACPI but that's not how the existing devices work. + +5. The AtomISP driver includes some special IOCTLS (ATOMISP_IOC_XXXX_XXXX) + that may need some cleaning up. + +6. Correct Coding Style. Please don't send coding style patches for this + driver until the other work is done. + +7. The ISP code depends on the exact FW version. The version defined in + BYT: + drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_firmware.c + static const char *release_version = STR(irci_stable_candrpv_0415_20150521_0458); + CHT: + drivers/staging/media/atomisp/pci/atomisp2/css/sh_css_firmware.c + static const char *release_version = STR(irci_ecr-master_20150911_0724); + + At some point we may need to round up a few driver versions and see if + there are any specific things that can be done to fold in support for + multiple firmware versions. + + +Limitations: + +1. Currently the patch only support some camera sensors + gc2235/gc0310/0v2680/ov2722/ov5693/mt9m114... + +2. To test the patches, you also need the ISP firmware + + for BYT:/lib/firmware/shisp_2400b0_v21.bin + for CHT:/lib/firmware/shisp_2401a0_v21.bin + + The firmware files will usually be found in /etc/firmware on an Android + device but can also be extracted from the upgrade kit if you've managed + to lose them somehow. + +3. Without a 3A libary the capture behaviour is not very good. To take a good + picture, you need tune ISP parameters by IOCTL functions or use a 3A libary + such as libxcam. + +4. The driver is intended to drive the PCI exposed versions of the device. + It will not detect those devices enumerated via ACPI as a field of the + i915 GPU driver. + +5. The driver supports only v2 of the IPU/Camera. It will not work with the + versions of the hardware in other SoCs. + diff --git a/drivers/staging/media/atomisp/i2c/Kconfig b/drivers/staging/media/atomisp/i2c/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..30b0bb94f20d137b7c818aa6a541664300f78ae0 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/Kconfig @@ -0,0 +1,105 @@ +# +# Kconfig for sensor drivers +# + +source "drivers/staging/media/atomisp/i2c/ov5693/Kconfig" +source "drivers/staging/media/atomisp/i2c/imx/Kconfig" + +config VIDEO_OV2722 + tristate "OVT ov2722 sensor support" + depends on I2C && VIDEO_V4L2 + ---help--- + This is a Video4Linux2 sensor-level driver for the OVT + OV2722 raw camera. + + OVT is a 2M raw sensor. + + It currently only works with the atomisp driver. + +config VIDEO_GC2235 + tristate "Galaxy gc2235 sensor support" + depends on I2C && VIDEO_V4L2 + ---help--- + This is a Video4Linux2 sensor-level driver for the OVT + GC2235 raw camera. + + GC2235 is a 2M raw sensor. + + It currently only works with the atomisp driver. + +config VIDEO_OV8858 + tristate "Omnivision ov8858 sensor support" + depends on I2C && VIDEO_V4L2 && VIDEO_ATOMISP + ---help--- + This is a Video4Linux2 sensor-level driver for the Omnivision + ov8858 RAW sensor. + + OV8858 is a 8M raw sensor. + + It currently only works with the atomisp driver. + +config VIDEO_MSRLIST_HELPER + tristate "Helper library to load, parse and apply large register lists." + depends on I2C + ---help--- + This is a helper library to be used from a sensor driver to load, parse + and apply large register lists. + + To compile this driver as a module, choose M here: the + module will be called libmsrlisthelper. + +config VIDEO_MT9M114 + tristate "Aptina mt9m114 sensor support" + depends on I2C && VIDEO_V4L2 + ---help--- + This is a Video4Linux2 sensor-level driver for the Micron + mt9m114 1.3 Mpixel camera. + + mt9m114 is video camera sensor. + + It currently only works with the atomisp driver. + +config VIDEO_AP1302 + tristate "AP1302 external ISP support" + depends on I2C && VIDEO_V4L2 + ---help--- + This is a Video4Linux2 sensor-level driver for the external + ISP AP1302. + + AP1302 is an exteral ISP. + + It currently only works with the atomisp driver. + +config VIDEO_GC0310 + tristate "GC0310 sensor support" + depends on I2C && VIDEO_V4L2 + ---help--- + This is a Video4Linux2 sensor-level driver for the Galaxycore + GC0310 0.3MP sensor. + +config VIDEO_OV2680 + tristate "Omnivision OV2680 sensor support" + depends on I2C && VIDEO_V4L2 + ---help--- + This is a Video4Linux2 sensor-level driver for the Omnivision + OV2680 raw camera. + + ov2680 is a 2M raw sensor. + + It currently only works with the atomisp driver. + +# +# Kconfig for flash drivers +# + +config VIDEO_LM3554 + tristate "LM3554 flash light driver" + depends on VIDEO_V4L2 && I2C + ---help--- + This is a Video4Linux2 sub-dev driver for the LM3554 + flash light driver. + + To compile this driver as a module, choose M here: the + module will be called lm3554 + + diff --git a/drivers/staging/media/atomisp/i2c/Makefile b/drivers/staging/media/atomisp/i2c/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..8ea01904c0eae72b9273919c0214510072e89813 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/Makefile @@ -0,0 +1,23 @@ +# +# Makefile for sensor drivers +# + +obj-$(CONFIG_VIDEO_IMX) += imx/ +obj-$(CONFIG_VIDEO_OV5693) += ov5693/ +obj-$(CONFIG_VIDEO_MT9M114) += mt9m114.o +obj-$(CONFIG_VIDEO_GC2235) += gc2235.o +obj-$(CONFIG_VIDEO_OV2722) += ov2722.o +obj-$(CONFIG_VIDEO_OV2680) += ov2680.o +obj-$(CONFIG_VIDEO_GC0310) += gc0310.o + +obj-$(CONFIG_VIDEO_MSRLIST_HELPER) += libmsrlisthelper.o + +obj-$(CONFIG_VIDEO_AP1302) += ap1302.o + +# Makefile for flash drivers +# + +obj-$(CONFIG_VIDEO_LM3554) += lm3554.o + +ccflags-y += -Werror + diff --git a/drivers/staging/media/atomisp/i2c/ap1302.c b/drivers/staging/media/atomisp/i2c/ap1302.c new file mode 100644 index 0000000000000000000000000000000000000000..121bc97bc22b8d481829dde8d5c01b09b55fd978 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ap1302.c @@ -0,0 +1,1262 @@ +/* + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "ap1302.h" + +#define to_ap1302_device(sub_dev) \ + container_of(sub_dev, struct ap1302_device, sd) + +/* Static definitions */ +static struct regmap_config ap1302_reg16_config = { + .reg_bits = 16, + .val_bits = 16, + .reg_format_endian = REGMAP_ENDIAN_BIG, + .val_format_endian = REGMAP_ENDIAN_BIG, +}; + +static struct regmap_config ap1302_reg32_config = { + .reg_bits = 16, + .val_bits = 32, + .reg_format_endian = REGMAP_ENDIAN_BIG, + .val_format_endian = REGMAP_ENDIAN_BIG, +}; + +static enum ap1302_contexts ap1302_cntx_mapping[] = { + CONTEXT_PREVIEW, /* Invalid atomisp run mode */ + CONTEXT_VIDEO, /* ATOMISP_RUN_MODE_VIDEO */ + CONTEXT_SNAPSHOT, /* ATOMISP_RUN_MODE_STILL_CAPTURE */ + CONTEXT_SNAPSHOT, /* ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE */ + CONTEXT_PREVIEW, /* ATOMISP_RUN_MODE_PREVIEW */ +}; + +static struct ap1302_res_struct ap1302_preview_res[] = { + { + .width = 640, + .height = 480, + .fps = 30, + }, + { + .width = 720, + .height = 480, + .fps = 30, + }, + { + .width = 1280, + .height = 720, + .fps = 30, + }, + { + .width = 1920, + .height = 1080, + .fps = 30, + } +}; + +static struct ap1302_res_struct ap1302_snapshot_res[] = { + { + .width = 640, + .height = 480, + .fps = 30, + }, + { + .width = 720, + .height = 480, + .fps = 30, + }, + { + .width = 1280, + .height = 720, + .fps = 30, + }, + { + .width = 1920, + .height = 1080, + .fps = 30, + } +}; + +static struct ap1302_res_struct ap1302_video_res[] = { + { + .width = 640, + .height = 480, + .fps = 30, + }, + { + .width = 720, + .height = 480, + .fps = 30, + }, + { + .width = 1280, + .height = 720, + .fps = 30, + }, + { + .width = 1920, + .height = 1080, + .fps = 30, + } +}; + +static enum ap1302_contexts stream_to_context[] = { + CONTEXT_SNAPSHOT, + CONTEXT_PREVIEW, + CONTEXT_PREVIEW, + CONTEXT_VIDEO +}; + +static u16 aux_stream_config[CONTEXT_NUM][CONTEXT_NUM] = { + {0, 0, 0}, /* Preview: No aux streams. */ + {1, 0, 2}, /* Snapshot: 1 for postview. 2 for video */ + {1, 0, 0}, /* Video: 1 for preview. */ +}; + +static struct ap1302_context_info context_info[] = { + {CNTX_WIDTH, AP1302_REG16, "width"}, + {CNTX_HEIGHT, AP1302_REG16, "height"}, + {CNTX_ROI_X0, AP1302_REG16, "roi_x0"}, + {CNTX_ROI_X1, AP1302_REG16, "roi_x1"}, + {CNTX_ROI_Y0, AP1302_REG16, "roi_y0"}, + {CNTX_ROI_Y1, AP1302_REG16, "roi_y1"}, + {CNTX_ASPECT, AP1302_REG16, "aspect"}, + {CNTX_LOCK, AP1302_REG16, "lock"}, + {CNTX_ENABLE, AP1302_REG16, "enable"}, + {CNTX_OUT_FMT, AP1302_REG16, "out_fmt"}, + {CNTX_SENSOR_MODE, AP1302_REG16, "sensor_mode"}, + {CNTX_MIPI_CTRL, AP1302_REG16, "mipi_ctrl"}, + {CNTX_MIPI_II_CTRL, AP1302_REG16, "mipi_ii_ctrl"}, + {CNTX_LINE_TIME, AP1302_REG32, "line_time"}, + {CNTX_MAX_FPS, AP1302_REG16, "max_fps"}, + {CNTX_AE_USG, AP1302_REG16, "ae_usg"}, + {CNTX_AE_UPPER_ET, AP1302_REG32, "ae_upper_et"}, + {CNTX_AE_MAX_ET, AP1302_REG32, "ae_max_et"}, + {CNTX_SS, AP1302_REG16, "ss"}, + {CNTX_S1_SENSOR_MODE, AP1302_REG16, "s1_sensor_mode"}, + {CNTX_HINF_CTRL, AP1302_REG16, "hinf_ctrl"}, +}; + +/* This array stores the description list for metadata. + The metadata contains exposure settings and face + detection results. */ +static u16 ap1302_ss_list[] = { + 0xb01c, /* From 0x0186 with size 0x1C are exposure settings. */ + 0x0186, + 0xb002, /* 0x71c0 is for F-number */ + 0x71c0, + 0xb010, /* From 0x03dc with size 0x10 are face general infos. */ + 0x03dc, + 0xb0a0, /* From 0x03e4 with size 0xa0 are face detail infos. */ + 0x03e4, + 0xb020, /* From 0x0604 with size 0x20 are smile rate infos. */ + 0x0604, + 0x0000 +}; + +/* End of static definitions */ + +static int ap1302_i2c_read_reg(struct v4l2_subdev *sd, + u16 reg, u16 len, void *val) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (len == AP1302_REG16) + ret = regmap_read(dev->regmap16, reg, val); + else if (len == AP1302_REG32) + ret = regmap_read(dev->regmap32, reg, val); + else + ret = -EINVAL; + if (ret) { + dev_dbg(&client->dev, "Read reg failed. reg=0x%04X\n", reg); + return ret; + } + if (len == AP1302_REG16) + dev_dbg(&client->dev, "read_reg[0x%04X] = 0x%04X\n", + reg, *(u16 *)val); + else + dev_dbg(&client->dev, "read_reg[0x%04X] = 0x%08X\n", + reg, *(u32 *)val); + return ret; +} + +static int ap1302_i2c_write_reg(struct v4l2_subdev *sd, + u16 reg, u16 len, u32 val) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + if (len == AP1302_REG16) + ret = regmap_write(dev->regmap16, reg, val); + else if (len == AP1302_REG32) + ret = regmap_write(dev->regmap32, reg, val); + else + ret = -EINVAL; + if (ret) { + dev_dbg(&client->dev, "Write reg failed. reg=0x%04X\n", reg); + return ret; + } + if (len == AP1302_REG16) + dev_dbg(&client->dev, "write_reg[0x%04X] = 0x%04X\n", + reg, (u16)val); + else + dev_dbg(&client->dev, "write_reg[0x%04X] = 0x%08X\n", + reg, (u32)val); + return ret; +} + +static u16 +ap1302_calculate_context_reg_addr(enum ap1302_contexts context, u16 offset) +{ + u16 reg_addr; + /* The register offset is defined according to preview/video registers. + Preview and video context have the same register definition. + But snapshot context does not have register S1_SENSOR_MODE. + When setting snapshot registers, if the offset exceeds + S1_SENSOR_MODE, the actual offset needs to minus 2. */ + if (context == CONTEXT_SNAPSHOT) { + if (offset == CNTX_S1_SENSOR_MODE) + return 0; + if (offset > CNTX_S1_SENSOR_MODE) + offset -= 2; + } + if (context == CONTEXT_PREVIEW) + reg_addr = REG_PREVIEW_BASE + offset; + else if (context == CONTEXT_VIDEO) + reg_addr = REG_VIDEO_BASE + offset; + else + reg_addr = REG_SNAPSHOT_BASE + offset; + return reg_addr; +} + +static int ap1302_read_context_reg(struct v4l2_subdev *sd, + enum ap1302_contexts context, u16 offset, u16 len) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + u16 reg_addr = ap1302_calculate_context_reg_addr(context, offset); + if (reg_addr == 0) + return -EINVAL; + return ap1302_i2c_read_reg(sd, reg_addr, len, + ((u8 *)&dev->cntx_config[context]) + offset); +} + +static int ap1302_write_context_reg(struct v4l2_subdev *sd, + enum ap1302_contexts context, u16 offset, u16 len) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + u16 reg_addr = ap1302_calculate_context_reg_addr(context, offset); + if (reg_addr == 0) + return -EINVAL; + return ap1302_i2c_write_reg(sd, reg_addr, len, + *(u32 *)(((u8 *)&dev->cntx_config[context]) + offset)); +} + +static int ap1302_dump_context_reg(struct v4l2_subdev *sd, + enum ap1302_contexts context) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ap1302_device *dev = to_ap1302_device(sd); + int i; + dev_dbg(&client->dev, "Dump registers for context[%d]:\n", context); + for (i = 0; i < ARRAY_SIZE(context_info); i++) { + struct ap1302_context_info *info = &context_info[i]; + u8 *var = (u8 *)&dev->cntx_config[context] + info->offset; + /* Snapshot context does not have s1_sensor_mode register. */ + if (context == CONTEXT_SNAPSHOT && + info->offset == CNTX_S1_SENSOR_MODE) + continue; + ap1302_read_context_reg(sd, context, info->offset, info->len); + if (info->len == AP1302_REG16) + dev_dbg(&client->dev, "context.%s = 0x%04X (%d)\n", + info->name, *(u16 *)var, *(u16 *)var); + else + dev_dbg(&client->dev, "context.%s = 0x%08X (%d)\n", + info->name, *(u32 *)var, *(u32 *)var); + } + return 0; +} + +static int ap1302_request_firmware(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ap1302_device *dev = to_ap1302_device(sd); + int ret; + ret = request_firmware(&dev->fw, "ap1302_fw.bin", &client->dev); + if (ret) + dev_err(&client->dev, + "ap1302_request_firmware failed. ret=%d\n", ret); + return ret; +} + +/* When loading firmware, host writes firmware data from address 0x8000. + When the address reaches 0x9FFF, the next address should return to 0x8000. + This function handles this address window and load firmware data to AP1302. + win_pos indicates the offset within this window. Firmware loading procedure + may call this function several times. win_pos records the current position + that has been written to.*/ +static int ap1302_write_fw_window(struct v4l2_subdev *sd, + u16 *win_pos, const u8 *buf, u32 len) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + int ret; + u32 pos; + u32 sub_len; + for (pos = 0; pos < len; pos += sub_len) { + if (len - pos < AP1302_FW_WINDOW_SIZE - *win_pos) + sub_len = len - pos; + else + sub_len = AP1302_FW_WINDOW_SIZE - *win_pos; + ret = regmap_raw_write(dev->regmap16, + *win_pos + AP1302_FW_WINDOW_OFFSET, + buf + pos, sub_len); + if (ret) + return ret; + *win_pos += sub_len; + if (*win_pos >= AP1302_FW_WINDOW_SIZE) + *win_pos = 0; + } + return 0; +} + +static int ap1302_load_firmware(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ap1302_device *dev = to_ap1302_device(sd); + const struct ap1302_firmware *fw; + const u8 *fw_data; + u16 reg_val = 0; + u16 win_pos = 0; + int ret; + + dev_info(&client->dev, "Start to load firmware.\n"); + if (!dev->fw) { + dev_err(&client->dev, "firmware not requested.\n"); + return -EINVAL; + } + fw = (const struct ap1302_firmware *) dev->fw->data; + if (dev->fw->size != (sizeof(*fw) + fw->total_size)) { + dev_err(&client->dev, "firmware size does not match.\n"); + return -EINVAL; + } + /* The fw binary contains a header of struct ap1302_firmware. + Following the header is the bootdata of AP1302. + The bootdata pointer can be referenced as &fw[1]. */ + fw_data = (u8 *)&fw[1]; + + /* Clear crc register. */ + ret = ap1302_i2c_write_reg(sd, REG_SIP_CRC, AP1302_REG16, 0xFFFF); + if (ret) + return ret; + + /* Load FW data for PLL init stage. */ + ret = ap1302_write_fw_window(sd, &win_pos, fw_data, fw->pll_init_size); + if (ret) + return ret; + + /* Write 2 to bootdata_stage register to apply basic_init_hp + settings and enable PLL. */ + ret = ap1302_i2c_write_reg(sd, REG_BOOTDATA_STAGE, + AP1302_REG16, 0x0002); + if (ret) + return ret; + + /* Wait 1ms for PLL to lock. */ + msleep(20); + + /* Load the rest of bootdata content. */ + ret = ap1302_write_fw_window(sd, &win_pos, fw_data + fw->pll_init_size, + fw->total_size - fw->pll_init_size); + if (ret) + return ret; + + /* Check crc. */ + ret = ap1302_i2c_read_reg(sd, REG_SIP_CRC, AP1302_REG16, ®_val); + if (ret) + return ret; + if (reg_val != fw->crc) { + dev_err(&client->dev, + "crc does not match. T:0x%04X F:0x%04X\n", + fw->crc, reg_val); + return -EAGAIN; + } + + /* Write 0xFFFF to bootdata_stage register to indicate AP1302 that + the whole bootdata content has been loaded. */ + ret = ap1302_i2c_write_reg(sd, REG_BOOTDATA_STAGE, + AP1302_REG16, 0xFFFF); + if (ret) + return ret; + dev_info(&client->dev, "Load firmware successfully.\n"); + + return 0; +} + +static int __ap1302_s_power(struct v4l2_subdev *sd, int on, int load_fw) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret, i; + u16 ss_ptr; + + dev_info(&client->dev, "ap1302_s_power is called.\n"); + ret = dev->platform_data->power_ctrl(sd, on); + if (ret) { + dev_err(&client->dev, + "ap1302_s_power error. on=%d ret=%d\n", on, ret); + return ret; + } + dev->power_on = on; + if (!on || !load_fw) + return 0; + /* Load firmware after power on. */ + ret = ap1302_load_firmware(sd); + if (ret) { + dev_err(&client->dev, + "ap1302_load_firmware failed. ret=%d\n", ret); + return ret; + } + ret = ap1302_i2c_read_reg(sd, REG_SS_HEAD_PT0, AP1302_REG16, &ss_ptr); + if (ret) + return ret; + for (i = 0; i < ARRAY_SIZE(ap1302_ss_list); i++) { + ret = ap1302_i2c_write_reg(sd, ss_ptr + i * 2, + AP1302_REG16, ap1302_ss_list[i]); + if (ret) + return ret; + } + return ret; +} + +static int ap1302_s_power(struct v4l2_subdev *sd, int on) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __ap1302_s_power(sd, on, 1); + dev->sys_activated = 0; + mutex_unlock(&dev->input_lock); + + return ret; +} + +static int ap1302_s_config(struct v4l2_subdev *sd, void *pdata) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct camera_mipi_info *mipi_info; + u16 reg_val = 0; + int ret; + + dev_info(&client->dev, "ap1302_s_config is called.\n"); + if (pdata == NULL) + return -ENODEV; + + dev->platform_data = pdata; + + mutex_lock(&dev->input_lock); + + if (dev->platform_data->platform_init) { + ret = dev->platform_data->platform_init(client); + if (ret) + goto fail_power; + } + + ret = __ap1302_s_power(sd, 1, 0); + if (ret) + goto fail_power; + + /* Detect for AP1302 */ + ret = ap1302_i2c_read_reg(sd, REG_CHIP_VERSION, AP1302_REG16, ®_val); + if (ret || (reg_val != AP1302_CHIP_ID)) { + dev_err(&client->dev, + "Chip version does no match. ret=%d ver=0x%04x\n", + ret, reg_val); + goto fail_config; + } + dev_info(&client->dev, "AP1302 Chip ID is 0x%X\n", reg_val); + + /* Detect revision for AP1302 */ + ret = ap1302_i2c_read_reg(sd, REG_CHIP_REV, AP1302_REG16, ®_val); + if (ret) + goto fail_config; + dev_info(&client->dev, "AP1302 Chip Rev is 0x%X\n", reg_val); + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_config; + + mipi_info = v4l2_get_subdev_hostdata(sd); + if (!mipi_info) + goto fail_config; + dev->num_lanes = mipi_info->num_lanes; + + ret = __ap1302_s_power(sd, 0, 0); + if (ret) + goto fail_power; + + mutex_unlock(&dev->input_lock); + + return ret; + +fail_config: + __ap1302_s_power(sd, 0, 0); +fail_power: + mutex_unlock(&dev->input_lock); + dev_err(&client->dev, "ap1302_s_config failed\n"); + return ret; +} + +static enum ap1302_contexts ap1302_get_context(struct v4l2_subdev *sd) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + return dev->cur_context; +} + +static int ap1302_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_UYVY8_1X16; + + return 0; +} + +static int ap1302_match_resolution(struct ap1302_context_res *res, + struct v4l2_mbus_framefmt *fmt) +{ + s32 w0, h0, mismatch, distance; + s32 w1 = fmt->width; + s32 h1 = fmt->height; + s32 min_distance = INT_MAX; + s32 i, idx = -1; + + if (w1 == 0 || h1 == 0) + return -1; + + for (i = 0; i < res->res_num; i++) { + w0 = res->res_table[i].width; + h0 = res->res_table[i].height; + if (w0 < w1 || h0 < h1) + continue; + mismatch = abs(w0 * h1 - w1 * h0) * 8192 / w1 / h0; + if (mismatch > 8192 * AP1302_MAX_RATIO_MISMATCH / 100) + continue; + distance = (w0 * h1 + w1 * h0) * 8192 / w1 / h1; + if (distance < min_distance) { + min_distance = distance; + idx = i; + } + } + + return idx; +} + +static s32 ap1302_try_mbus_fmt_locked(struct v4l2_subdev *sd, + enum ap1302_contexts context, + struct v4l2_mbus_framefmt *fmt) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + struct ap1302_res_struct *res_table; + s32 res_num, idx = -1; + + res_table = dev->cntx_res[context].res_table; + res_num = dev->cntx_res[context].res_num; + + if ((fmt->width <= res_table[res_num - 1].width) && + (fmt->height <= res_table[res_num - 1].height)) + idx = ap1302_match_resolution(&dev->cntx_res[context], fmt); + if (idx == -1) + idx = res_num - 1; + + fmt->width = res_table[idx].width; + fmt->height = res_table[idx].height; + fmt->code = MEDIA_BUS_FMT_UYVY8_1X16; + return idx; +} + + +static int ap1302_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) + +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ap1302_device *dev = to_ap1302_device(sd); + enum ap1302_contexts context; + struct ap1302_res_struct *res_table; + s32 cur_res; + if (format->pad) + return -EINVAL; + mutex_lock(&dev->input_lock); + context = ap1302_get_context(sd); + res_table = dev->cntx_res[context].res_table; + cur_res = dev->cntx_res[context].cur_res; + fmt->code = MEDIA_BUS_FMT_UYVY8_1X16; + fmt->width = res_table[cur_res].width; + fmt->height = res_table[cur_res].height; + mutex_unlock(&dev->input_lock); + return 0; +} + +static int ap1302_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ap1302_device *dev = to_ap1302_device(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct atomisp_input_stream_info *stream_info = + (struct atomisp_input_stream_info *)fmt->reserved; + enum ap1302_contexts context, main_context; + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + mutex_lock(&dev->input_lock); + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + context = ap1302_get_context(sd); + ap1302_try_mbus_fmt_locked(sd, context, fmt); + cfg->try_fmt = *fmt; + mutex_unlock(&dev->input_lock); + return 0; + } + context = stream_to_context[stream_info->stream]; + dev_dbg(&client->dev, "ap1302_set_mbus_fmt. stream=%d context=%d\n", + stream_info->stream, context); + dev->cntx_res[context].cur_res = + ap1302_try_mbus_fmt_locked(sd, context, fmt); + dev->cntx_config[context].width = fmt->width; + dev->cntx_config[context].height = fmt->height; + ap1302_write_context_reg(sd, context, CNTX_WIDTH, AP1302_REG16); + ap1302_write_context_reg(sd, context, CNTX_HEIGHT, AP1302_REG16); + ap1302_read_context_reg(sd, context, CNTX_OUT_FMT, AP1302_REG16); + dev->cntx_config[context].out_fmt &= ~OUT_FMT_TYPE_MASK; + dev->cntx_config[context].out_fmt |= AP1302_FMT_UYVY422; + ap1302_write_context_reg(sd, context, CNTX_OUT_FMT, AP1302_REG16); + + main_context = ap1302_get_context(sd); + if (context == main_context) { + ap1302_read_context_reg(sd, context, + CNTX_MIPI_CTRL, AP1302_REG16); + dev->cntx_config[context].mipi_ctrl &= ~MIPI_CTRL_IMGVC_MASK; + dev->cntx_config[context].mipi_ctrl |= + (context << MIPI_CTRL_IMGVC_OFFSET); + dev->cntx_config[context].mipi_ctrl &= ~MIPI_CTRL_SSVC_MASK; + dev->cntx_config[context].mipi_ctrl |= + (context << MIPI_CTRL_SSVC_OFFSET); + dev->cntx_config[context].mipi_ctrl &= ~MIPI_CTRL_SSTYPE_MASK; + dev->cntx_config[context].mipi_ctrl |= + (0x12 << MIPI_CTRL_SSTYPE_OFFSET); + ap1302_write_context_reg(sd, context, + CNTX_MIPI_CTRL, AP1302_REG16); + ap1302_read_context_reg(sd, context, + CNTX_SS, AP1302_REG16); + dev->cntx_config[context].ss = AP1302_SS_CTRL; + ap1302_write_context_reg(sd, context, + CNTX_SS, AP1302_REG16); + } else { + /* Configure aux stream */ + ap1302_read_context_reg(sd, context, + CNTX_MIPI_II_CTRL, AP1302_REG16); + dev->cntx_config[context].mipi_ii_ctrl &= ~MIPI_CTRL_IMGVC_MASK; + dev->cntx_config[context].mipi_ii_ctrl |= + (context << MIPI_CTRL_IMGVC_OFFSET); + ap1302_write_context_reg(sd, context, + CNTX_MIPI_II_CTRL, AP1302_REG16); + if (stream_info->enable) { + ap1302_read_context_reg(sd, main_context, + CNTX_OUT_FMT, AP1302_REG16); + dev->cntx_config[context].out_fmt |= + (aux_stream_config[main_context][context] + << OUT_FMT_IIS_OFFSET); + ap1302_write_context_reg(sd, main_context, + CNTX_OUT_FMT, AP1302_REG16); + } + } + stream_info->ch_id = context; + mutex_unlock(&dev->input_lock); + + return 0; +} + + +static int ap1302_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + enum ap1302_contexts context; + struct ap1302_res_struct *res_table; + u32 cur_res; + + mutex_lock(&dev->input_lock); + context = ap1302_get_context(sd); + res_table = dev->cntx_res[context].res_table; + cur_res = dev->cntx_res[context].cur_res; + interval->interval.denominator = res_table[cur_res].fps; + interval->interval.numerator = 1; + mutex_unlock(&dev->input_lock); + return 0; +} + +static int ap1302_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + enum ap1302_contexts context; + struct ap1302_res_struct *res_table; + int index = fse->index; + + mutex_lock(&dev->input_lock); + context = ap1302_get_context(sd); + if (index >= dev->cntx_res[context].res_num) { + mutex_unlock(&dev->input_lock); + return -EINVAL; + } + + res_table = dev->cntx_res[context].res_table; + fse->min_width = res_table[index].width; + fse->min_height = res_table[index].height; + fse->max_width = res_table[index].width; + fse->max_height = res_table[index].height; + mutex_unlock(&dev->input_lock); + + return 0; +} + + +static int ap1302_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + *frames = 0; + return 0; +} + +static int ap1302_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + enum ap1302_contexts context; + u32 reg_val; + int ret; + + mutex_lock(&dev->input_lock); + context = ap1302_get_context(sd); + dev_dbg(&client->dev, "ap1302_s_stream. context=%d enable=%d\n", + context, enable); + /* Switch context */ + ap1302_i2c_read_reg(sd, REG_CTRL, + AP1302_REG16, ®_val); + reg_val &= ~CTRL_CNTX_MASK; + reg_val |= (context<dev, "Start stream. context=%d\n", context); + ap1302_dump_context_reg(sd, context); + if (!dev->sys_activated) { + reg_val = AP1302_SYS_ACTIVATE; + dev->sys_activated = 1; + } else { + reg_val = AP1302_SYS_SWITCH; + } + } else { + dev_info(&client->dev, "Stop stream. context=%d\n", context); + reg_val = AP1302_SYS_SWITCH; + } + ret = ap1302_i2c_write_reg(sd, REG_SYS_START, AP1302_REG16, reg_val); + if (ret) + dev_err(&client->dev, + "AP1302 set stream failed. enable=%d\n", enable); + mutex_unlock(&dev->input_lock); + return ret; +} + +static u16 ap1302_ev_values[] = {0xfd00, 0xfe80, 0x0, 0x180, 0x300}; + +static int ap1302_set_exposure_off(struct v4l2_subdev *sd, s32 val) +{ + val -= AP1302_MIN_EV; + return ap1302_i2c_write_reg(sd, REG_AE_BV_OFF, AP1302_REG16, + ap1302_ev_values[val]); +} + +static u16 ap1302_wb_values[] = { + 0, /* V4L2_WHITE_BALANCE_MANUAL */ + 0xf, /* V4L2_WHITE_BALANCE_AUTO */ + 0x2, /* V4L2_WHITE_BALANCE_INCANDESCENT */ + 0x4, /* V4L2_WHITE_BALANCE_FLUORESCENT */ + 0x5, /* V4L2_WHITE_BALANCE_FLUORESCENT_H */ + 0x1, /* V4L2_WHITE_BALANCE_HORIZON */ + 0x5, /* V4L2_WHITE_BALANCE_DAYLIGHT */ + 0xf, /* V4L2_WHITE_BALANCE_FLASH */ + 0x6, /* V4L2_WHITE_BALANCE_CLOUDY */ + 0x6, /* V4L2_WHITE_BALANCE_SHADE */ +}; + +static int ap1302_set_wb_mode(struct v4l2_subdev *sd, s32 val) +{ + int ret = 0; + u16 reg_val; + + ret = ap1302_i2c_read_reg(sd, REG_AWB_CTRL, AP1302_REG16, ®_val); + if (ret) + return ret; + reg_val &= ~AWB_CTRL_MODE_MASK; + reg_val |= ap1302_wb_values[val] << AWB_CTRL_MODE_OFFSET; + if (val == V4L2_WHITE_BALANCE_FLASH) + reg_val |= AWB_CTRL_FLASH_MASK; + else + reg_val &= ~AWB_CTRL_FLASH_MASK; + ret = ap1302_i2c_write_reg(sd, REG_AWB_CTRL, AP1302_REG16, reg_val); + return ret; +} + +static int ap1302_set_zoom(struct v4l2_subdev *sd, s32 val) +{ + ap1302_i2c_write_reg(sd, REG_DZ_TGT_FCT, AP1302_REG16, + val * 4 + 0x100); + return 0; +} + +static u16 ap1302_sfx_values[] = { + 0x00, /* V4L2_COLORFX_NONE */ + 0x03, /* V4L2_COLORFX_BW */ + 0x0d, /* V4L2_COLORFX_SEPIA */ + 0x07, /* V4L2_COLORFX_NEGATIVE */ + 0x04, /* V4L2_COLORFX_EMBOSS */ + 0x0f, /* V4L2_COLORFX_SKETCH */ + 0x08, /* V4L2_COLORFX_SKY_BLUE */ + 0x09, /* V4L2_COLORFX_GRASS_GREEN */ + 0x0a, /* V4L2_COLORFX_SKIN_WHITEN */ + 0x00, /* V4L2_COLORFX_VIVID */ + 0x00, /* V4L2_COLORFX_AQUA */ + 0x00, /* V4L2_COLORFX_ART_FREEZE */ + 0x00, /* V4L2_COLORFX_SILHOUETTE */ + 0x10, /* V4L2_COLORFX_SOLARIZATION */ + 0x02, /* V4L2_COLORFX_ANTIQUE */ + 0x00, /* V4L2_COLORFX_SET_CBCR */ +}; + +static int ap1302_set_special_effect(struct v4l2_subdev *sd, s32 val) +{ + ap1302_i2c_write_reg(sd, REG_SFX_MODE, AP1302_REG16, + ap1302_sfx_values[val]); + return 0; +} + +static u16 ap1302_scene_mode_values[] = { + 0x00, /* V4L2_SCENE_MODE_NONE */ + 0x07, /* V4L2_SCENE_MODE_BACKLIGHT */ + 0x0a, /* V4L2_SCENE_MODE_BEACH_SNOW */ + 0x06, /* V4L2_SCENE_MODE_CANDLE_LIGHT */ + 0x00, /* V4L2_SCENE_MODE_DAWN_DUSK */ + 0x00, /* V4L2_SCENE_MODE_FALL_COLORS */ + 0x0d, /* V4L2_SCENE_MODE_FIREWORKS */ + 0x02, /* V4L2_SCENE_MODE_LANDSCAPE */ + 0x05, /* V4L2_SCENE_MODE_NIGHT */ + 0x0c, /* V4L2_SCENE_MODE_PARTY_INDOOR */ + 0x01, /* V4L2_SCENE_MODE_PORTRAIT */ + 0x03, /* V4L2_SCENE_MODE_SPORTS */ + 0x0e, /* V4L2_SCENE_MODE_SUNSET */ + 0x0b, /* V4L2_SCENE_MODE_TEXT */ +}; + +static int ap1302_set_scene_mode(struct v4l2_subdev *sd, s32 val) +{ + ap1302_i2c_write_reg(sd, REG_SCENE_CTRL, AP1302_REG16, + ap1302_scene_mode_values[val]); + return 0; +} + +static u16 ap1302_flicker_values[] = { + 0x0, /* OFF */ + 0x3201, /* 50HZ */ + 0x3c01, /* 60HZ */ + 0x2 /* AUTO */ +}; + +static int ap1302_set_flicker_freq(struct v4l2_subdev *sd, s32 val) +{ + ap1302_i2c_write_reg(sd, REG_FLICK_CTRL, AP1302_REG16, + ap1302_flicker_values[val]); + return 0; +} + +static int ap1302_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ap1302_device *dev = container_of( + ctrl->handler, struct ap1302_device, ctrl_handler); + + switch (ctrl->id) { + case V4L2_CID_RUN_MODE: + dev->cur_context = ap1302_cntx_mapping[ctrl->val]; + break; + case V4L2_CID_EXPOSURE: + ap1302_set_exposure_off(&dev->sd, ctrl->val); + break; + case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE: + ap1302_set_wb_mode(&dev->sd, ctrl->val); + break; + case V4L2_CID_ZOOM_ABSOLUTE: + ap1302_set_zoom(&dev->sd, ctrl->val); + break; + case V4L2_CID_COLORFX: + ap1302_set_special_effect(&dev->sd, ctrl->val); + break; + case V4L2_CID_SCENE_MODE: + ap1302_set_scene_mode(&dev->sd, ctrl->val); + break; + case V4L2_CID_POWER_LINE_FREQUENCY: + ap1302_set_flicker_freq(&dev->sd, ctrl->val); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int ap1302_g_register(struct v4l2_subdev *sd, + struct v4l2_dbg_register *reg) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + int ret; + u32 reg_val; + + if (reg->size != AP1302_REG16 && + reg->size != AP1302_REG32) + return -EINVAL; + + mutex_lock(&dev->input_lock); + if (dev->power_on) + ret = ap1302_i2c_read_reg(sd, reg->reg, reg->size, ®_val); + else + ret = -EIO; + mutex_unlock(&dev->input_lock); + if (ret) + return ret; + + reg->val = reg_val; + + return 0; +} + +static int ap1302_s_register(struct v4l2_subdev *sd, + const struct v4l2_dbg_register *reg) +{ + struct ap1302_device *dev = to_ap1302_device(sd); + int ret; + + if (reg->size != AP1302_REG16 && + reg->size != AP1302_REG32) + return -EINVAL; + + mutex_lock(&dev->input_lock); + if (dev->power_on) + ret = ap1302_i2c_write_reg(sd, reg->reg, reg->size, reg->val); + else + ret = -EIO; + mutex_unlock(&dev->input_lock); + return ret; +} + +static long ap1302_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + long ret = 0; + switch (cmd) { + case VIDIOC_DBG_G_REGISTER: + ret = ap1302_g_register(sd, arg); + break; + case VIDIOC_DBG_S_REGISTER: + ret = ap1302_s_register(sd, arg); + break; + default: + ret = -EINVAL; + } + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = ap1302_s_ctrl, +}; + +static const char * const ctrl_run_mode_menu[] = { + NULL, + "Video", + "Still capture", + "Continuous capture", + "Preview", +}; + +static const struct v4l2_ctrl_config ctrls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_RUN_MODE, + .name = "Run Mode", + .type = V4L2_CTRL_TYPE_MENU, + .min = 1, + .def = 4, + .max = 4, + .qmenu = ctrl_run_mode_menu, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE, + .name = "Exposure", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = AP1302_MIN_EV, + .def = 0, + .max = AP1302_MAX_EV, + .step = 1, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE, + .name = "White Balance", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .def = 0, + .max = 9, + .step = 1, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_ZOOM_ABSOLUTE, + .name = "Zoom Absolute", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .def = 0, + .max = 1024, + .step = 1, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_COLORFX, + .name = "Color Special Effect", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .def = 0, + .max = 15, + .step = 1, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_SCENE_MODE, + .name = "Scene Mode", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .def = 0, + .max = 13, + .step = 1, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_POWER_LINE_FREQUENCY, + .name = "Light frequency filter", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .def = 3, + .max = 3, + .step = 1, + }, +}; + +static struct v4l2_subdev_sensor_ops ap1302_sensor_ops = { + .g_skip_frames = ap1302_g_skip_frames, +}; + +static const struct v4l2_subdev_video_ops ap1302_video_ops = { + .s_stream = ap1302_s_stream, + .g_frame_interval = ap1302_g_frame_interval, +}; + +static const struct v4l2_subdev_core_ops ap1302_core_ops = { + .s_power = ap1302_s_power, + .ioctl = ap1302_ioctl, +#ifdef CONFIG_VIDEO_ADV_DEBUG + .g_register = ap1302_g_register, + .s_register = ap1302_s_register, +#endif +}; + +static const struct v4l2_subdev_pad_ops ap1302_pad_ops = { + .enum_mbus_code = ap1302_enum_mbus_code, + .enum_frame_size = ap1302_enum_frame_size, + .get_fmt = ap1302_get_fmt, + .set_fmt = ap1302_set_fmt, +}; + +static const struct v4l2_subdev_ops ap1302_ops = { + .core = &ap1302_core_ops, + .pad = &ap1302_pad_ops, + .video = &ap1302_video_ops, + .sensor = &ap1302_sensor_ops +}; + +static int ap1302_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ap1302_device *dev = to_ap1302_device(sd); + + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); + + release_firmware(dev->fw); + + media_entity_cleanup(&dev->sd.entity); + dev->platform_data->csi_cfg(sd, 0); + v4l2_device_unregister_subdev(sd); + + return 0; +} + +static int ap1302_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct ap1302_device *dev; + int ret; + unsigned int i; + + dev_info(&client->dev, "ap1302 probe called.\n"); + + /* allocate device & init sub device */ + dev = devm_kzalloc(&client->dev, sizeof(*dev), GFP_KERNEL); + if (!dev) { + dev_err(&client->dev, "%s: out of memory\n", __func__); + return -ENOMEM; + } + + mutex_init(&dev->input_lock); + + v4l2_i2c_subdev_init(&(dev->sd), client, &ap1302_ops); + + ret = ap1302_request_firmware(&(dev->sd)); + if (ret) { + dev_err(&client->dev, "Cannot request ap1302 firmware.\n"); + goto out_free; + } + + dev->regmap16 = devm_regmap_init_i2c(client, &ap1302_reg16_config); + if (IS_ERR(dev->regmap16)) { + ret = PTR_ERR(dev->regmap16); + dev_err(&client->dev, + "Failed to allocate 16bit register map: %d\n", ret); + return ret; + } + + dev->regmap32 = devm_regmap_init_i2c(client, &ap1302_reg32_config); + if (IS_ERR(dev->regmap32)) { + ret = PTR_ERR(dev->regmap32); + dev_err(&client->dev, + "Failed to allocate 32bit register map: %d\n", ret); + return ret; + } + + if (client->dev.platform_data) { + ret = ap1302_s_config(&dev->sd, client->dev.platform_data); + if (ret) + goto out_free; + } + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + + dev->cntx_res[CONTEXT_PREVIEW].res_num = ARRAY_SIZE(ap1302_preview_res); + dev->cntx_res[CONTEXT_PREVIEW].res_table = ap1302_preview_res; + dev->cntx_res[CONTEXT_SNAPSHOT].res_num = + ARRAY_SIZE(ap1302_snapshot_res); + dev->cntx_res[CONTEXT_SNAPSHOT].res_table = ap1302_snapshot_res; + dev->cntx_res[CONTEXT_VIDEO].res_num = ARRAY_SIZE(ap1302_video_res); + dev->cntx_res[CONTEXT_VIDEO].res_table = ap1302_video_res; + + ret = v4l2_ctrl_handler_init(&dev->ctrl_handler, ARRAY_SIZE(ctrls)); + if (ret) { + ap1302_remove(client); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(ctrls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &ctrls[i], NULL); + + if (dev->ctrl_handler.error) { + ap1302_remove(client); + return dev->ctrl_handler.error; + } + + /* Use same lock for controls as for everything else. */ + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = &dev->ctrl_handler; + v4l2_ctrl_handler_setup(&dev->ctrl_handler); + + dev->run_mode = v4l2_ctrl_find(&dev->ctrl_handler, V4L2_CID_RUN_MODE); + v4l2_ctrl_s_ctrl(dev->run_mode, ATOMISP_RUN_MODE_PREVIEW); + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) + ap1302_remove(client); + return ret; +out_free: + v4l2_device_unregister_subdev(&dev->sd); + return ret; +} + +static const struct i2c_device_id ap1302_id[] = { + {AP1302_NAME, 0}, + {} +}; +MODULE_DEVICE_TABLE(i2c, ap1302_id); + +static struct i2c_driver ap1302_driver = { + .driver = { + .owner = THIS_MODULE, + .name = AP1302_NAME, + }, + .probe = ap1302_probe, + .remove = ap1302_remove, + .id_table = ap1302_id, +}; + +module_i2c_driver(ap1302_driver); + +MODULE_AUTHOR("Tianshu Qiu "); +MODULE_DESCRIPTION("AP1302 Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/ap1302.h b/drivers/staging/media/atomisp/i2c/ap1302.h new file mode 100644 index 0000000000000000000000000000000000000000..3ccad298c5e3434930eb07e0e1e005b0bc8cb9aa --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ap1302.h @@ -0,0 +1,198 @@ +/* + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __AP1302_H__ +#define __AP1302_H__ + +#include +#include +#include +#include +#include + +#define AP1302_NAME "ap1302" +#define AP1302_CHIP_ID 0x265 +#define AP1302_I2C_MAX_LEN 65534 +#define AP1302_FW_WINDOW_OFFSET 0x8000 +#define AP1302_FW_WINDOW_SIZE 0x2000 + +#define AP1302_REG16 2 +#define AP1302_REG32 4 + +#define REG_CHIP_VERSION 0x0000 +#define REG_CHIP_REV 0x0050 +#define REG_MF_ID 0x0004 +#define REG_ERROR 0x0006 +#define REG_CTRL 0x1000 +#define REG_DZ_TGT_FCT 0x1010 +#define REG_SFX_MODE 0x1016 +#define REG_SS_HEAD_PT0 0x1174 +#define REG_AE_BV_OFF 0x5014 +#define REG_AE_BV_BIAS 0x5016 +#define REG_AWB_CTRL 0x5100 +#define REG_FLICK_CTRL 0x5440 +#define REG_SCENE_CTRL 0x5454 +#define REG_BOOTDATA_STAGE 0x6002 +#define REG_SENSOR_SELECT 0x600C +#define REG_SYS_START 0x601A +#define REG_SIP_CRC 0xF052 + +#define REG_PREVIEW_BASE 0x2000 +#define REG_SNAPSHOT_BASE 0x3000 +#define REG_VIDEO_BASE 0x4000 +#define CNTX_WIDTH 0x00 +#define CNTX_HEIGHT 0x02 +#define CNTX_ROI_X0 0x04 +#define CNTX_ROI_Y0 0x06 +#define CNTX_ROI_X1 0x08 +#define CNTX_ROI_Y1 0x0A +#define CNTX_ASPECT 0x0C +#define CNTX_LOCK 0x0E +#define CNTX_ENABLE 0x10 +#define CNTX_OUT_FMT 0x12 +#define CNTX_SENSOR_MODE 0x14 +#define CNTX_MIPI_CTRL 0x16 +#define CNTX_MIPI_II_CTRL 0x18 +#define CNTX_LINE_TIME 0x1C +#define CNTX_MAX_FPS 0x20 +#define CNTX_AE_USG 0x22 +#define CNTX_AE_UPPER_ET 0x24 +#define CNTX_AE_MAX_ET 0x28 +#define CNTX_SS 0x2C +#define CNTX_S1_SENSOR_MODE 0x2E +#define CNTX_HINF_CTRL 0x30 + +#define CTRL_CNTX_MASK 0x03 +#define CTRL_CNTX_OFFSET 0x00 +#define HINF_CTRL_LANE_MASK 0x07 +#define HINF_CTRL_LANE_OFFSET 0x00 +#define MIPI_CTRL_IMGVC_MASK 0xC0 +#define MIPI_CTRL_IMGVC_OFFSET 0x06 +#define MIPI_CTRL_IMGTYPE_AUTO 0x3F +#define MIPI_CTRL_SSVC_MASK 0xC000 +#define MIPI_CTRL_SSVC_OFFSET 0x0E +#define MIPI_CTRL_SSTYPE_MASK 0x3F00 +#define MIPI_CTRL_SSTYPE_OFFSET 0x08 +#define OUT_FMT_IIS_MASK 0x30 +#define OUT_FMT_IIS_OFFSET 0x08 +#define OUT_FMT_SS_MASK 0x1000 +#define OUT_FMT_SS_OFFSET 0x12 +#define OUT_FMT_TYPE_MASK 0xFF +#define SENSOR_SELECT_MASK 0x03 +#define SENSOR_SELECT_OFFSET 0x00 +#define AWB_CTRL_MODE_MASK 0x0F +#define AWB_CTRL_MODE_OFFSET 0x00 +#define AWB_CTRL_FLASH_MASK 0x100 + +#define AP1302_FMT_UYVY422 0x50 + +#define AP1302_SYS_ACTIVATE 0x8010 +#define AP1302_SYS_SWITCH 0x8140 +#define AP1302_SENSOR_PRI 0x01 +#define AP1302_SENSOR_SEC 0x02 +#define AP1302_SS_CTRL 0x31 + +#define AP1302_MAX_RATIO_MISMATCH 10 /* Unit in percentage */ +#define AP1302_MAX_EV 2 +#define AP1302_MIN_EV -2 + +enum ap1302_contexts { + CONTEXT_PREVIEW = 0, + CONTEXT_SNAPSHOT, + CONTEXT_VIDEO, + CONTEXT_NUM +}; + +/* The context registers are defined according to preview/video registers. + Preview and video context have the same register definition. + But snapshot context does not have register S1_SENSOR_MODE. + When setting snapshot registers, if the offset exceeds + S1_SENSOR_MODE, the actual offset needs to minus 2. */ +struct ap1302_context_config { + u16 width; + u16 height; + u16 roi_x0; + u16 roi_y0; + u16 roi_x1; + u16 roi_y1; + u16 aspect_factor; + u16 lock; + u16 enable; + u16 out_fmt; + u16 sensor_mode; + u16 mipi_ctrl; + u16 mipi_ii_ctrl; + u16 padding; + u32 line_time; + u16 max_fps; + u16 ae_usg; + u32 ae_upper_et; + u32 ae_max_et; + u16 ss; + u16 s1_sensor_mode; + u16 hinf_ctrl; + u32 reserved; +}; + +struct ap1302_res_struct { + u16 width; + u16 height; + u16 fps; +}; + +struct ap1302_context_res { + s32 res_num; + s32 cur_res; + struct ap1302_res_struct *res_table; +}; + +struct ap1302_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct camera_sensor_platform_data *platform_data; + const struct firmware *fw; + struct mutex input_lock; /* serialize sensor's ioctl */ + struct v4l2_mbus_framefmt format; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *run_mode; + struct ap1302_context_config cntx_config[CONTEXT_NUM]; + struct ap1302_context_res cntx_res[CONTEXT_NUM]; + enum ap1302_contexts cur_context; + unsigned int num_lanes; + struct regmap *regmap16; + struct regmap *regmap32; + bool sys_activated; + bool power_on; +}; + +struct ap1302_firmware { + u32 crc; + u32 pll_init_size; + u32 total_size; + u32 reserved; +}; + +struct ap1302_context_info { + u16 offset; + u16 len; + char *name; +}; + +#endif diff --git a/drivers/staging/media/atomisp/i2c/gc0310.c b/drivers/staging/media/atomisp/i2c/gc0310.c new file mode 100644 index 0000000000000000000000000000000000000000..ee1fd59445a5c1d77b1da2c0d653de7e4e98409c --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/gc0310.c @@ -0,0 +1,1495 @@ +/* + * Support for GalaxyCore GC0310 VGA camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gc0310.h" + +/* i2c read/write stuff */ +static int gc0310_read_reg(struct i2c_client *client, + u16 data_length, u8 reg, u8 *val) +{ + int err; + struct i2c_msg msg[2]; + unsigned char data[1]; + + if (!client->adapter) { + dev_err(&client->dev, "%s error, no client->adapter\n", + __func__); + return -ENODEV; + } + + if (data_length != GC0310_8BIT) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + memset(msg, 0 , sizeof(msg)); + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = I2C_MSG_LENGTH; + msg[0].buf = data; + + /* high byte goes out first */ + data[0] = (u8)(reg & 0xff); + + msg[1].addr = client->addr; + msg[1].len = data_length; + msg[1].flags = I2C_M_RD; + msg[1].buf = data; + + err = i2c_transfer(client->adapter, msg, 2); + if (err != 2) { + if (err >= 0) + err = -EIO; + dev_err(&client->dev, + "read from offset 0x%x error %d", reg, err); + return err; + } + + *val = 0; + /* high byte comes first */ + if (data_length == GC0310_8BIT) + *val = (u8)data[0]; + + return 0; +} + +static int gc0310_i2c_write(struct i2c_client *client, u16 len, u8 *data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = len; + msg.buf = data; + ret = i2c_transfer(client->adapter, &msg, 1); + + return ret == num_msg ? 0 : -EIO; +} + +static int gc0310_write_reg(struct i2c_client *client, u16 data_length, + u8 reg, u8 val) +{ + int ret; + unsigned char data[2] = {0}; + u8 *wreg = (u8 *)data; + const u16 len = data_length + sizeof(u8); /* 8-bit address + data */ + + if (data_length != GC0310_8BIT) { + dev_err(&client->dev, + "%s error, invalid data_length\n", __func__); + return -EINVAL; + } + + /* high byte goes out first */ + *wreg = (u8)(reg & 0xff); + + if (data_length == GC0310_8BIT) { + data[1] = (u8)(val); + } + + ret = gc0310_i2c_write(client, len, data); + if (ret) + dev_err(&client->dev, + "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, ret); + + return ret; +} + +/* + * gc0310_write_reg_array - Initializes a list of GC0310 registers + * @client: i2c driver client structure + * @reglist: list of registers to be written + * + * This function initializes a list of registers. When consecutive addresses + * are found in a row on the list, this function creates a buffer and sends + * consecutive data in a single i2c_transfer(). + * + * __gc0310_flush_reg_array, __gc0310_buf_reg_array() and + * __gc0310_write_reg_is_consecutive() are internal functions to + * gc0310_write_reg_array_fast() and should be not used anywhere else. + * + */ + +static int __gc0310_flush_reg_array(struct i2c_client *client, + struct gc0310_write_ctrl *ctrl) +{ + u16 size; + + if (ctrl->index == 0) + return 0; + + size = sizeof(u8) + ctrl->index; /* 8-bit address + data */ + ctrl->buffer.addr = (u8)(ctrl->buffer.addr); + ctrl->index = 0; + + return gc0310_i2c_write(client, size, (u8 *)&ctrl->buffer); +} + +static int __gc0310_buf_reg_array(struct i2c_client *client, + struct gc0310_write_ctrl *ctrl, + const struct gc0310_reg *next) +{ + int size; + + switch (next->type) { + case GC0310_8BIT: + size = 1; + ctrl->buffer.data[ctrl->index] = (u8)next->val; + break; + default: + return -EINVAL; + } + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->reg; + + ctrl->index += size; + + /* + * Buffer cannot guarantee free space for u32? Better flush it to avoid + * possible lack of memory for next item. + */ + if (ctrl->index + sizeof(u8) >= GC0310_MAX_WRITE_BUF_SIZE) + return __gc0310_flush_reg_array(client, ctrl); + + return 0; +} + +static int __gc0310_write_reg_is_consecutive(struct i2c_client *client, + struct gc0310_write_ctrl *ctrl, + const struct gc0310_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->reg; +} + +static int gc0310_write_reg_array(struct i2c_client *client, + const struct gc0310_reg *reglist) +{ + const struct gc0310_reg *next = reglist; + struct gc0310_write_ctrl ctrl; + int err; + + ctrl.index = 0; + for (; next->type != GC0310_TOK_TERM; next++) { + switch (next->type & GC0310_TOK_MASK) { + case GC0310_TOK_DELAY: + err = __gc0310_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceed. + */ + if (!__gc0310_write_reg_is_consecutive(client, &ctrl, + next)) { + err = __gc0310_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __gc0310_buf_reg_array(client, &ctrl, next); + if (err) { + dev_err(&client->dev, "%s: write error, aborted\n", + __func__); + return err; + } + break; + } + } + + return __gc0310_flush_reg_array(client, &ctrl); +} +static int gc0310_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + *val = (GC0310_FOCAL_LENGTH_NUM << 16) | GC0310_FOCAL_LENGTH_DEM; + return 0; +} + +static int gc0310_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /*const f number for imx*/ + *val = (GC0310_F_NUMBER_DEFAULT_NUM << 16) | GC0310_F_NUMBER_DEM; + return 0; +} + +static int gc0310_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + *val = (GC0310_F_NUMBER_DEFAULT_NUM << 24) | + (GC0310_F_NUMBER_DEM << 16) | + (GC0310_F_NUMBER_DEFAULT_NUM << 8) | GC0310_F_NUMBER_DEM; + return 0; +} + +static int gc0310_g_bin_factor_x(struct v4l2_subdev *sd, s32 *val) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + + *val = gc0310_res[dev->fmt_idx].bin_factor_x; + + return 0; +} + +static int gc0310_g_bin_factor_y(struct v4l2_subdev *sd, s32 *val) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + + *val = gc0310_res[dev->fmt_idx].bin_factor_y; + + return 0; +} + +static int gc0310_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct gc0310_resolution *res) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct atomisp_sensor_mode_data *buf = &info->data; + u16 val; + u8 reg_val; + int ret; + unsigned int hori_blanking; + unsigned int vert_blanking; + unsigned int sh_delay; + + if (info == NULL) + return -EINVAL; + + /* pixel clock calculattion */ + dev->vt_pix_clk_freq_mhz = 14400000; // 16.8MHz + buf->vt_pix_clk_freq_mhz = dev->vt_pix_clk_freq_mhz; + pr_info("vt_pix_clk_freq_mhz=%d\n", buf->vt_pix_clk_freq_mhz); + + /* get integration time */ + buf->coarse_integration_time_min = GC0310_COARSE_INTG_TIME_MIN; + buf->coarse_integration_time_max_margin = + GC0310_COARSE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_min = GC0310_FINE_INTG_TIME_MIN; + buf->fine_integration_time_max_margin = + GC0310_FINE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_def = GC0310_FINE_INTG_TIME_MIN; + buf->read_mode = res->bin_mode; + + /* get the cropping and output resolution to ISP for this mode. */ + /* Getting crop_horizontal_start */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_H_CROP_START_H, ®_val); + if (ret) + return ret; + val = (reg_val & 0xFF) << 8; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_H_CROP_START_L, ®_val); + if (ret) + return ret; + buf->crop_horizontal_start = val | (reg_val & 0xFF); + pr_info("crop_horizontal_start=%d\n", buf->crop_horizontal_start); + + /* Getting crop_vertical_start */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_V_CROP_START_H, ®_val); + if (ret) + return ret; + val = (reg_val & 0xFF) << 8; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_V_CROP_START_L, ®_val); + if (ret) + return ret; + buf->crop_vertical_start = val | (reg_val & 0xFF); + pr_info("crop_vertical_start=%d\n", buf->crop_vertical_start); + + /* Getting output_width */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_H_OUTSIZE_H, ®_val); + if (ret) + return ret; + val = (reg_val & 0xFF) << 8; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_H_OUTSIZE_L, ®_val); + if (ret) + return ret; + buf->output_width = val | (reg_val & 0xFF); + pr_info("output_width=%d\n", buf->output_width); + + /* Getting output_height */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_V_OUTSIZE_H, ®_val); + if (ret) + return ret; + val = (reg_val & 0xFF) << 8; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_V_OUTSIZE_L, ®_val); + if (ret) + return ret; + buf->output_height = val | (reg_val & 0xFF); + pr_info("output_height=%d\n", buf->output_height); + + buf->crop_horizontal_end = buf->crop_horizontal_start + buf->output_width - 1; + buf->crop_vertical_end = buf->crop_vertical_start + buf->output_height - 1; + pr_info("crop_horizontal_end=%d\n", buf->crop_horizontal_end); + pr_info("crop_vertical_end=%d\n", buf->crop_vertical_end); + + /* Getting line_length_pck */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_H_BLANKING_H, ®_val); + if (ret) + return ret; + val = (reg_val & 0xFF) << 8; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_H_BLANKING_L, ®_val); + if (ret) + return ret; + hori_blanking = val | (reg_val & 0xFF); + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_SH_DELAY, ®_val); + if (ret) + return ret; + sh_delay = reg_val; + buf->line_length_pck = buf->output_width + hori_blanking + sh_delay + 4; + pr_info("hori_blanking=%d sh_delay=%d line_length_pck=%d\n", hori_blanking, sh_delay, buf->line_length_pck); + + /* Getting frame_length_lines */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_V_BLANKING_H, ®_val); + if (ret) + return ret; + val = (reg_val & 0xFF) << 8; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_V_BLANKING_L, ®_val); + if (ret) + return ret; + vert_blanking = val | (reg_val & 0xFF); + buf->frame_length_lines = buf->output_height + vert_blanking; + pr_info("vert_blanking=%d frame_length_lines=%d\n", vert_blanking, buf->frame_length_lines); + + buf->binning_factor_x = res->bin_factor_x ? + res->bin_factor_x : 1; + buf->binning_factor_y = res->bin_factor_y ? + res->bin_factor_y : 1; + return 0; +} + +static int gc0310_set_gain(struct v4l2_subdev *sd, int gain) + +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u8 again, dgain; + + if (gain < 0x20) + gain = 0x20; + if (gain > 0x80) + gain = 0x80; + + if (gain >= 0x20 && gain < 0x40) { + again = 0x0; /* sqrt(2) */ + dgain = gain; + } else { + again = 0x2; /* 2 * sqrt(2) */ + dgain = gain / 2; + } + + pr_info("gain=0x%x again=0x%x dgain=0x%x\n", gain, again, dgain); + + /* set analog gain */ + ret = gc0310_write_reg(client, GC0310_8BIT, + GC0310_AGC_ADJ, again); + if (ret) + return ret; + + /* set digital gain */ + ret = gc0310_write_reg(client, GC0310_8BIT, + GC0310_DGC_ADJ, dgain); + if (ret) + return ret; + + return 0; +} + +static int __gc0310_set_exposure(struct v4l2_subdev *sd, int coarse_itg, + int gain, int digitgain) + +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + pr_info("coarse_itg=%d gain=%d digitgain=%d\n", coarse_itg, gain, digitgain); + + /* set exposure */ + ret = gc0310_write_reg(client, GC0310_8BIT, + GC0310_AEC_PK_EXPO_L, + coarse_itg & 0xff); + if (ret) + return ret; + + ret = gc0310_write_reg(client, GC0310_8BIT, + GC0310_AEC_PK_EXPO_H, + (coarse_itg >> 8) & 0x0f); + if (ret) + return ret; + + ret = gc0310_set_gain(sd, gain); + if (ret) + return ret; + + return ret; +} + +static int gc0310_set_exposure(struct v4l2_subdev *sd, int exposure, + int gain, int digitgain) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __gc0310_set_exposure(sd, exposure, gain, digitgain); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static long gc0310_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + int exp = exposure->integration_time[0]; + int gain = exposure->gain[0]; + int digitgain = exposure->gain[1]; + + /* we should not accept the invalid value below. */ + if (gain == 0) { + struct i2c_client *client = v4l2_get_subdevdata(sd); + v4l2_err(client, "%s: invalid value\n", __func__); + return -EINVAL; + } + + return gc0310_set_exposure(sd, exp, gain, digitgain); +} + +/* TO DO */ +static int gc0310_v_flip(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +/* TO DO */ +static int gc0310_h_flip(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +static long gc0310_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return gc0310_s_exposure(sd, arg); + default: + return -EINVAL; + } + return 0; +} + +/* This returns the exposure time being used. This should only be used + for filling in EXIF data, not for actual image processing. */ +static int gc0310_q_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u8 reg_v; + int ret; + + /* get exposure */ + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_AEC_PK_EXPO_L, + ®_v); + if (ret) + goto err; + + *value = reg_v; + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_AEC_PK_EXPO_H, + ®_v); + if (ret) + goto err; + + *value = *value + (reg_v << 8); +err: + return ret; +} + +static int gc0310_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct gc0310_device *dev = + container_of(ctrl->handler, struct gc0310_device, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_VFLIP: + dev_dbg(&client->dev, "%s: CID_VFLIP:%d.\n", + __func__, ctrl->val); + ret = gc0310_v_flip(&dev->sd, ctrl->val); + break; + case V4L2_CID_HFLIP: + dev_dbg(&client->dev, "%s: CID_HFLIP:%d.\n", + __func__, ctrl->val); + ret = gc0310_h_flip(&dev->sd, ctrl->val); + break; + default: + ret = -EINVAL; + } + return ret; +} + +static int gc0310_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct gc0310_device *dev = + container_of(ctrl->handler, struct gc0310_device, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = gc0310_q_exposure(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = gc0310_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = gc0310_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = gc0310_g_fnumber_range(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_HORZ: + ret = gc0310_g_bin_factor_x(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_VERT: + ret = gc0310_g_bin_factor_y(&dev->sd, &ctrl->val); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = gc0310_s_ctrl, + .g_volatile_ctrl = gc0310_g_volatile_ctrl +}; + +struct v4l2_ctrl_config gc0310_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .min = 0x0, + .max = 0xffff, + .step = 0x01, + .def = 0x00, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Flip", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_HFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Mirror", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focal length", + .min = GC0310_FOCAL_LENGTH_DEFAULT, + .max = GC0310_FOCAL_LENGTH_DEFAULT, + .step = 0x01, + .def = GC0310_FOCAL_LENGTH_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number", + .min = GC0310_F_NUMBER_DEFAULT, + .max = GC0310_F_NUMBER_DEFAULT, + .step = 0x01, + .def = GC0310_F_NUMBER_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number range", + .min = GC0310_F_NUMBER_RANGE, + .max = GC0310_F_NUMBER_RANGE, + .step = 0x01, + .def = GC0310_F_NUMBER_RANGE, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_HORZ, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "horizontal binning factor", + .min = 0, + .max = GC0310_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_VERT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vertical binning factor", + .min = 0, + .max = GC0310_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, +}; + +static int gc0310_init(struct v4l2_subdev *sd) +{ + int ret; + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct gc0310_device *dev = to_gc0310_sensor(sd); + + pr_info("%s S\n", __func__); + mutex_lock(&dev->input_lock); + + /* set inital registers */ + ret = gc0310_write_reg_array(client, gc0310_reset_register); + + /* restore settings */ + gc0310_res = gc0310_res_preview; + N_RES = N_RES_PREVIEW; + + mutex_unlock(&dev->input_lock); + + pr_info("%s E\n", __func__); + return 0; +} + +static int power_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret = 0; + struct gc0310_device *dev = to_gc0310_sensor(sd); + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->power_ctrl) + return dev->platform_data->power_ctrl(sd, flag); + + if (flag) { + /* The upstream module driver (written to Crystal + * Cove) had this logic to pulse the rails low first. + * This appears to break things on the MRD7 with the + * X-Powers PMIC... + * + * ret = dev->platform_data->v1p8_ctrl(sd, 0); + * ret |= dev->platform_data->v2p8_ctrl(sd, 0); + * mdelay(50); + */ + ret |= dev->platform_data->v1p8_ctrl(sd, 1); + ret |= dev->platform_data->v2p8_ctrl(sd, 1); + usleep_range(10000, 15000); + } + + if (!flag || ret) { + ret |= dev->platform_data->v1p8_ctrl(sd, 0); + ret |= dev->platform_data->v2p8_ctrl(sd, 0); + } + return ret; +} + +static int gpio_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret; + struct gc0310_device *dev = to_gc0310_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->gpio_ctrl) + return dev->platform_data->gpio_ctrl(sd, flag); + + /* GPIO0 == "reset" (active low), GPIO1 == "power down" */ + if (flag) { + /* Pulse reset, then release power down */ + ret = dev->platform_data->gpio0_ctrl(sd, 0); + usleep_range(5000, 10000); + ret |= dev->platform_data->gpio0_ctrl(sd, 1); + usleep_range(10000, 15000); + ret |= dev->platform_data->gpio1_ctrl(sd, 0); + usleep_range(10000, 15000); + } else { + ret = dev->platform_data->gpio1_ctrl(sd, 1); + ret |= dev->platform_data->gpio0_ctrl(sd, 0); + } + return ret; +} + + +static int power_down(struct v4l2_subdev *sd); + +static int power_up(struct v4l2_subdev *sd) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + pr_info("%s S\n", __func__); + if (NULL == dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + /* power control */ + ret = power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* flis clock control */ + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 1); + if (ret) { + ret = gpio_ctrl(sd, 1); + if (ret) + goto fail_gpio; + } + + msleep(100); + + pr_info("%s E\n", __func__); + return 0; + +fail_gpio: + dev->platform_data->flisclk_ctrl(sd, 0); +fail_clk: + power_ctrl(sd, 0); +fail_power: + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (NULL == dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 0); + if (ret) { + ret = gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed 2\n"); + } + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* power control */ + ret = power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "vprog failed.\n"); + + return ret; +} + +static int gc0310_s_power(struct v4l2_subdev *sd, int on) +{ + int ret; + if (on == 0) + return power_down(sd); + else { + ret = power_up(sd); + if (!ret) + return gc0310_init(sd); + } + return ret; +} + +/* + * distance - calculate the distance + * @res: resolution + * @w: width + * @h: height + * + * Get the gap between resolution and w/h. + * res->width/height smaller than w/h wouldn't be considered. + * Returns the value of gap or -1 if fail. + */ +#define LARGEST_ALLOWED_RATIO_MISMATCH 800 +static int distance(struct gc0310_resolution *res, u32 w, u32 h) +{ + unsigned int w_ratio = ((res->width << 13)/w); + unsigned int h_ratio; + int match; + + if (h == 0) + return -1; + h_ratio = ((res->height << 13) / h); + if (h_ratio == 0) + return -1; + match = abs(((w_ratio << 13) / h_ratio) - ((int)8192)); + + if ((w_ratio < (int)8192) || (h_ratio < (int)8192) || + (match > LARGEST_ALLOWED_RATIO_MISMATCH)) + return -1; + + return w_ratio + h_ratio; +} + +/* Return the nearest higher resolution index */ +static int nearest_resolution_index(int w, int h) +{ + int i; + int idx = -1; + int dist; + int min_dist = INT_MAX; + struct gc0310_resolution *tmp_res = NULL; + + for (i = 0; i < N_RES; i++) { + tmp_res = &gc0310_res[i]; + dist = distance(tmp_res, w, h); + if (dist == -1) + continue; + if (dist < min_dist) { + min_dist = dist; + idx = i; + } + } + + return idx; +} + +static int get_resolution_index(int w, int h) +{ + int i; + + for (i = 0; i < N_RES; i++) { + if (w != gc0310_res[i].width) + continue; + if (h != gc0310_res[i].height) + continue; + + return i; + } + + return -1; +} + + +/* TODO: remove it. */ +static int startup(struct v4l2_subdev *sd) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + pr_info("%s S\n", __func__); + + ret = gc0310_write_reg_array(client, gc0310_res[dev->fmt_idx].regs); + if (ret) { + dev_err(&client->dev, "gc0310 write register err.\n"); + return ret; + } + + pr_info("%s E\n", __func__); + return ret; +} + +static int gc0310_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct camera_mipi_info *gc0310_info = NULL; + int ret = 0; + int idx = 0; + pr_info("%s S\n", __func__); + + if (format->pad) + return -EINVAL; + + if (!fmt) + return -EINVAL; + + gc0310_info = v4l2_get_subdev_hostdata(sd); + if (gc0310_info == NULL) + return -EINVAL; + + mutex_lock(&dev->input_lock); + + idx = nearest_resolution_index(fmt->width, fmt->height); + if (idx == -1) { + /* return the largest resolution */ + fmt->width = gc0310_res[N_RES - 1].width; + fmt->height = gc0310_res[N_RES - 1].height; + } else { + fmt->width = gc0310_res[idx].width; + fmt->height = gc0310_res[idx].height; + } + fmt->code = MEDIA_BUS_FMT_SGRBG8_1X8; + + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + cfg->try_fmt = *fmt; + mutex_unlock(&dev->input_lock); + return 0; + } + + dev->fmt_idx = get_resolution_index(fmt->width, fmt->height); + if (dev->fmt_idx == -1) { + dev_err(&client->dev, "get resolution fail\n"); + mutex_unlock(&dev->input_lock); + return -EINVAL; + } + + printk("%s: before gc0310_write_reg_array %s\n", __FUNCTION__, + gc0310_res[dev->fmt_idx].desc); + ret = startup(sd); + if (ret) { + dev_err(&client->dev, "gc0310 startup err\n"); + goto err; + } + + ret = gc0310_get_intg_factor(client, gc0310_info, + &gc0310_res[dev->fmt_idx]); + if (ret) { + dev_err(&client->dev, "failed to get integration_factor\n"); + goto err; + } + + pr_info("%s E\n", __func__); +err: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int gc0310_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct gc0310_device *dev = to_gc0310_sensor(sd); + + if (format->pad) + return -EINVAL; + + if (!fmt) + return -EINVAL; + + fmt->width = gc0310_res[dev->fmt_idx].width; + fmt->height = gc0310_res[dev->fmt_idx].height; + fmt->code = MEDIA_BUS_FMT_SGRBG8_1X8; + + return 0; +} + +static int gc0310_detect(struct i2c_client *client) +{ + struct i2c_adapter *adapter = client->adapter; + u8 high, low; + int ret; + u16 id; + + pr_info("%s S\n", __func__); + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_SC_CMMN_CHIP_ID_H, &high); + if (ret) { + dev_err(&client->dev, "read sensor_id_high failed\n"); + return -ENODEV; + } + ret = gc0310_read_reg(client, GC0310_8BIT, + GC0310_SC_CMMN_CHIP_ID_L, &low); + if (ret) { + dev_err(&client->dev, "read sensor_id_low failed\n"); + return -ENODEV; + } + id = ((((u16) high) << 8) | (u16) low); + pr_info("sensor ID = 0x%x\n", id); + + if (id != GC0310_ID) { + dev_err(&client->dev, "sensor ID error, read id = 0x%x, target id = 0x%x\n", id, GC0310_ID); + return -ENODEV; + } + + dev_dbg(&client->dev, "detect gc0310 success\n"); + + pr_info("%s E\n", __func__); + + return 0; +} + +static int gc0310_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + pr_info("%s S enable=%d\n", __func__, enable); + mutex_lock(&dev->input_lock); + + if (enable) { + /* enable per frame MIPI and sensor ctrl reset */ + ret = gc0310_write_reg(client, GC0310_8BIT, + 0xFE, 0x30); + if (ret) { + mutex_unlock(&dev->input_lock); + return ret; + } + } + + ret = gc0310_write_reg(client, GC0310_8BIT, + GC0310_RESET_RELATED, GC0310_REGISTER_PAGE_3); + if (ret) { + mutex_unlock(&dev->input_lock); + return ret; + } + + ret = gc0310_write_reg(client, GC0310_8BIT, GC0310_SW_STREAM, + enable ? GC0310_START_STREAMING : + GC0310_STOP_STREAMING); + if (ret) { + mutex_unlock(&dev->input_lock); + return ret; + } + + ret = gc0310_write_reg(client, GC0310_8BIT, + GC0310_RESET_RELATED, GC0310_REGISTER_PAGE_0); + if (ret) { + mutex_unlock(&dev->input_lock); + return ret; + } + + mutex_unlock(&dev->input_lock); + pr_info("%s E\n", __func__); + return ret; +} + + +static int gc0310_s_config(struct v4l2_subdev *sd, + int irq, void *platform_data) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + pr_info("%s S\n", __func__); + if (platform_data == NULL) + return -ENODEV; + + dev->platform_data = + (struct camera_sensor_platform_data *)platform_data; + + mutex_lock(&dev->input_lock); + if (dev->platform_data->platform_init) { + ret = dev->platform_data->platform_init(client); + if (ret) { + dev_err(&client->dev, "platform init err\n"); + goto platform_init_failed; + } + } + /* power off the module, then power on it in future + * as first power on by board may not fulfill the + * power on sequqence needed by the module + */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "gc0310 power-off err.\n"); + goto fail_power_off; + } + + ret = power_up(sd); + if (ret) { + dev_err(&client->dev, "gc0310 power-up err.\n"); + goto fail_power_on; + } + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + /* config & detect sensor */ + ret = gc0310_detect(client); + if (ret) { + dev_err(&client->dev, "gc0310_detect err s_config.\n"); + goto fail_csi_cfg; + } + + /* turn off sensor, after probed */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "gc0310 power-off err.\n"); + goto fail_csi_cfg; + } + mutex_unlock(&dev->input_lock); + + pr_info("%s E\n", __func__); + return 0; + +fail_csi_cfg: + dev->platform_data->csi_cfg(sd, 0); +fail_power_on: + power_down(sd); + dev_err(&client->dev, "sensor power-gating failed\n"); +fail_power_off: + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); +platform_init_failed: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int gc0310_g_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + + if (!param) + return -EINVAL; + + if (param->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + dev_err(&client->dev, "unsupported buffer type.\n"); + return -EINVAL; + } + + memset(param, 0, sizeof(*param)); + param->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + if (dev->fmt_idx >= 0 && dev->fmt_idx < N_RES) { + param->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + param->parm.capture.timeperframe.numerator = 1; + param->parm.capture.capturemode = dev->run_mode; + param->parm.capture.timeperframe.denominator = + gc0310_res[dev->fmt_idx].fps; + } + return 0; +} + +static int gc0310_s_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + dev->run_mode = param->parm.capture.capturemode; + + mutex_lock(&dev->input_lock); + switch (dev->run_mode) { + case CI_MODE_VIDEO: + gc0310_res = gc0310_res_video; + N_RES = N_RES_VIDEO; + break; + case CI_MODE_STILL_CAPTURE: + gc0310_res = gc0310_res_still; + N_RES = N_RES_STILL; + break; + default: + gc0310_res = gc0310_res_preview; + N_RES = N_RES_PREVIEW; + } + mutex_unlock(&dev->input_lock); + return 0; +} + +static int gc0310_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + + interval->interval.numerator = 1; + interval->interval.denominator = gc0310_res[dev->fmt_idx].fps; + + return 0; +} + +static int gc0310_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= MAX_FMTS) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_SGRBG8_1X8; + return 0; +} + +static int gc0310_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + int index = fse->index; + + if (index >= N_RES) + return -EINVAL; + + fse->min_width = gc0310_res[index].width; + fse->min_height = gc0310_res[index].height; + fse->max_width = gc0310_res[index].width; + fse->max_height = gc0310_res[index].height; + + return 0; + +} + + +static int gc0310_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + struct gc0310_device *dev = to_gc0310_sensor(sd); + + mutex_lock(&dev->input_lock); + *frames = gc0310_res[dev->fmt_idx].skip_frames; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static const struct v4l2_subdev_sensor_ops gc0310_sensor_ops = { + .g_skip_frames = gc0310_g_skip_frames, +}; + +static const struct v4l2_subdev_video_ops gc0310_video_ops = { + .s_stream = gc0310_s_stream, + .g_parm = gc0310_g_parm, + .s_parm = gc0310_s_parm, + .g_frame_interval = gc0310_g_frame_interval, +}; + +static const struct v4l2_subdev_core_ops gc0310_core_ops = { + .s_power = gc0310_s_power, + .ioctl = gc0310_ioctl, +}; + +static const struct v4l2_subdev_pad_ops gc0310_pad_ops = { + .enum_mbus_code = gc0310_enum_mbus_code, + .enum_frame_size = gc0310_enum_frame_size, + .get_fmt = gc0310_get_fmt, + .set_fmt = gc0310_set_fmt, +}; + +static const struct v4l2_subdev_ops gc0310_ops = { + .core = &gc0310_core_ops, + .video = &gc0310_video_ops, + .pad = &gc0310_pad_ops, + .sensor = &gc0310_sensor_ops, +}; + +static int gc0310_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct gc0310_device *dev = to_gc0310_sensor(sd); + dev_dbg(&client->dev, "gc0310_remove...\n"); + + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); + + dev->platform_data->csi_cfg(sd, 0); + + v4l2_device_unregister_subdev(sd); + media_entity_cleanup(&dev->sd.entity); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + kfree(dev); + + return 0; +} + +static int gc0310_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct gc0310_device *dev; + int ret; + void *pdata; + unsigned int i; + + pr_info("%s S\n", __func__); + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) { + dev_err(&client->dev, "out of memory\n"); + return -ENOMEM; + } + + mutex_init(&dev->input_lock); + + dev->fmt_idx = 0; + v4l2_i2c_subdev_init(&(dev->sd), client, &gc0310_ops); + + if (ACPI_COMPANION(&client->dev)) + pdata = gmin_camera_platform_data(&dev->sd, + ATOMISP_INPUT_FORMAT_RAW_8, + atomisp_bayer_order_grbg); + else + pdata = client->dev.platform_data; + + if (!pdata) { + ret = -EINVAL; + goto out_free; + } + + ret = gc0310_s_config(&dev->sd, client->irq, pdata); + if (ret) + goto out_free; + + ret = atomisp_register_i2c_module(&dev->sd, pdata, RAW_CAMERA); + if (ret) + goto out_free; + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = MEDIA_BUS_FMT_SGRBG8_1X8; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = + v4l2_ctrl_handler_init(&dev->ctrl_handler, + ARRAY_SIZE(gc0310_controls)); + if (ret) { + gc0310_remove(client); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(gc0310_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &gc0310_controls[i], + NULL); + + if (dev->ctrl_handler.error) { + gc0310_remove(client); + return dev->ctrl_handler.error; + } + + /* Use same lock for controls as for everything else. */ + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = &dev->ctrl_handler; + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) + gc0310_remove(client); + + pr_info("%s E\n", __func__); + return ret; +out_free: + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + return ret; +} + +static struct acpi_device_id gc0310_acpi_match[] = { + {"XXGC0310"}, + {}, +}; + +MODULE_DEVICE_TABLE(acpi, gc0310_acpi_match); + +MODULE_DEVICE_TABLE(i2c, gc0310_id); +static struct i2c_driver gc0310_driver = { + .driver = { + .owner = THIS_MODULE, + .name = GC0310_NAME, + .acpi_match_table = ACPI_PTR(gc0310_acpi_match), + }, + .probe = gc0310_probe, + .remove = gc0310_remove, + .id_table = gc0310_id, +}; + +static int init_gc0310(void) +{ + return i2c_add_driver(&gc0310_driver); +} + +static void exit_gc0310(void) +{ + + i2c_del_driver(&gc0310_driver); +} + +module_init(init_gc0310); +module_exit(exit_gc0310); + +MODULE_AUTHOR("Lai, Angie "); +MODULE_DESCRIPTION("A low-level driver for GalaxyCore GC0310 sensors"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/gc0310.h b/drivers/staging/media/atomisp/i2c/gc0310.h new file mode 100644 index 0000000000000000000000000000000000000000..efc930abac214c012324f8cb08b5860ae9690209 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/gc0310.h @@ -0,0 +1,459 @@ +/* + * Support for GalaxyCore GC0310 VGA camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __GC0310_H__ +#define __GC0310_H__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define GC0310_NAME "gc0310" + +/* Defines for register writes and register array processing */ +#define I2C_MSG_LENGTH 1 +#define I2C_RETRY_COUNT 5 + +#define GC0310_FOCAL_LENGTH_NUM 278 /*2.78mm*/ +#define GC0310_FOCAL_LENGTH_DEM 100 +#define GC0310_F_NUMBER_DEFAULT_NUM 26 +#define GC0310_F_NUMBER_DEM 10 + +#define MAX_FMTS 1 + +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define GC0310_FOCAL_LENGTH_DEFAULT 0x1160064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define GC0310_F_NUMBER_DEFAULT 0x1a000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define GC0310_F_NUMBER_RANGE 0x1a0a1a0a +#define GC0310_ID 0xa310 + +#define GC0310_RESET_RELATED 0xFE +#define GC0310_REGISTER_PAGE_0 0x0 +#define GC0310_REGISTER_PAGE_3 0x3 + +#define GC0310_FINE_INTG_TIME_MIN 0 +#define GC0310_FINE_INTG_TIME_MAX_MARGIN 0 +#define GC0310_COARSE_INTG_TIME_MIN 1 +#define GC0310_COARSE_INTG_TIME_MAX_MARGIN 6 + +/* + * GC0310 System control registers + */ +#define GC0310_SW_STREAM 0x10 + +#define GC0310_SC_CMMN_CHIP_ID_H 0xf0 +#define GC0310_SC_CMMN_CHIP_ID_L 0xf1 + +#define GC0310_AEC_PK_EXPO_H 0x03 +#define GC0310_AEC_PK_EXPO_L 0x04 +#define GC0310_AGC_ADJ 0x48 +#define GC0310_DGC_ADJ 0x71 +#if 0 +#define GC0310_GROUP_ACCESS 0x3208 +#endif + +#define GC0310_H_CROP_START_H 0x09 +#define GC0310_H_CROP_START_L 0x0A +#define GC0310_V_CROP_START_H 0x0B +#define GC0310_V_CROP_START_L 0x0C +#define GC0310_H_OUTSIZE_H 0x0F +#define GC0310_H_OUTSIZE_L 0x10 +#define GC0310_V_OUTSIZE_H 0x0D +#define GC0310_V_OUTSIZE_L 0x0E +#define GC0310_H_BLANKING_H 0x05 +#define GC0310_H_BLANKING_L 0x06 +#define GC0310_V_BLANKING_H 0x07 +#define GC0310_V_BLANKING_L 0x08 +#define GC0310_SH_DELAY 0x11 + +#define GC0310_START_STREAMING 0x94 /* 8-bit enable */ +#define GC0310_STOP_STREAMING 0x0 /* 8-bit disable */ + +#define GC0310_BIN_FACTOR_MAX 3 + +struct regval_list { + u16 reg_num; + u8 value; +}; + +struct gc0310_resolution { + u8 *desc; + const struct gc0310_reg *regs; + int res; + int width; + int height; + int fps; + int pix_clk_freq; + u32 skip_frames; + u16 pixels_per_line; + u16 lines_per_frame; + u8 bin_factor_x; + u8 bin_factor_y; + u8 bin_mode; + bool used; +}; + +struct gc0310_format { + u8 *desc; + u32 pixelformat; + struct gc0310_reg *regs; +}; + +/* + * gc0310 device structure. + */ +struct gc0310_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + struct mutex input_lock; + struct v4l2_ctrl_handler ctrl_handler; + + struct camera_sensor_platform_data *platform_data; + int vt_pix_clk_freq_mhz; + int fmt_idx; + int run_mode; + u8 res; + u8 type; +}; + +enum gc0310_tok_type { + GC0310_8BIT = 0x0001, + GC0310_TOK_TERM = 0xf000, /* terminating token for reg list */ + GC0310_TOK_DELAY = 0xfe00, /* delay token for reg list */ + GC0310_TOK_MASK = 0xfff0 +}; + +/** + * struct gc0310_reg - MI sensor register format + * @type: type of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ +struct gc0310_reg { + enum gc0310_tok_type type; + u8 reg; + u8 val; /* @set value for read/mod/write, @mask */ +}; + +#define to_gc0310_sensor(x) container_of(x, struct gc0310_device, sd) + +#define GC0310_MAX_WRITE_BUF_SIZE 30 + +struct gc0310_write_buffer { + u8 addr; + u8 data[GC0310_MAX_WRITE_BUF_SIZE]; +}; + +struct gc0310_write_ctrl { + int index; + struct gc0310_write_buffer buffer; +}; + +static const struct i2c_device_id gc0310_id[] = { + {GC0310_NAME, 0}, + {} +}; + +/* + * Register settings for various resolution + */ +static const struct gc0310_reg gc0310_reset_register[] = { +///////////////////////////////////////////////// +///////////////// system reg ///////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0xfe, 0xf0}, + {GC0310_8BIT, 0xfe, 0xf0}, + {GC0310_8BIT, 0xfe, 0x00}, + + {GC0310_8BIT, 0xfc, 0x0e}, //4e + {GC0310_8BIT, 0xfc, 0x0e}, //16//4e // [0]apwd [6]regf_clk_gate + {GC0310_8BIT, 0xf2, 0x80}, //sync output + {GC0310_8BIT, 0xf3, 0x00}, //1f//01 data output + {GC0310_8BIT, 0xf7, 0x33}, //f9 + {GC0310_8BIT, 0xf8, 0x05}, //00 + {GC0310_8BIT, 0xf9, 0x0e}, // 0x8e //0f + {GC0310_8BIT, 0xfa, 0x11}, + +///////////////////////////////////////////////// +/////////////////// MIPI //////////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0xfe, 0x03}, + {GC0310_8BIT, 0x01, 0x03}, ///mipi 1lane + {GC0310_8BIT, 0x02, 0x22}, // 0x33 + {GC0310_8BIT, 0x03, 0x94}, + {GC0310_8BIT, 0x04, 0x01}, // fifo_prog + {GC0310_8BIT, 0x05, 0x00}, //fifo_prog + {GC0310_8BIT, 0x06, 0x80}, //b0 //YUV ISP data + {GC0310_8BIT, 0x11, 0x2a},//1e //LDI set YUV422 + {GC0310_8BIT, 0x12, 0x90},//00 //04 //00 //04//00 //LWC[7:0] // + {GC0310_8BIT, 0x13, 0x02},//05 //05 //LWC[15:8] + {GC0310_8BIT, 0x15, 0x12}, // 0x10 //DPHYY_MODE read_ready + {GC0310_8BIT, 0x17, 0x01}, + {GC0310_8BIT, 0x40, 0x08}, + {GC0310_8BIT, 0x41, 0x00}, + {GC0310_8BIT, 0x42, 0x00}, + {GC0310_8BIT, 0x43, 0x00}, + {GC0310_8BIT, 0x21, 0x02}, // 0x01 + {GC0310_8BIT, 0x22, 0x02}, // 0x01 + {GC0310_8BIT, 0x23, 0x01}, // 0x05 //Nor:0x05 DOU:0x06 + {GC0310_8BIT, 0x29, 0x00}, + {GC0310_8BIT, 0x2A, 0x25}, // 0x05 //data zero 0x7a de + {GC0310_8BIT, 0x2B, 0x02}, + + {GC0310_8BIT, 0xfe, 0x00}, + +///////////////////////////////////////////////// +///////////////// CISCTL reg ///////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0x00, 0x2f}, //2f//0f//02//01 + {GC0310_8BIT, 0x01, 0x0f}, //06 + {GC0310_8BIT, 0x02, 0x04}, + {GC0310_8BIT, 0x4f, 0x00}, //AEC 0FF + {GC0310_8BIT, 0x03, 0x01}, // 0x03 //04 + {GC0310_8BIT, 0x04, 0xc0}, // 0xe8 //58 + {GC0310_8BIT, 0x05, 0x00}, + {GC0310_8BIT, 0x06, 0xb2}, // 0x0a //HB + {GC0310_8BIT, 0x07, 0x00}, + {GC0310_8BIT, 0x08, 0x0c}, // 0x89 //VB + {GC0310_8BIT, 0x09, 0x00}, //row start + {GC0310_8BIT, 0x0a, 0x00}, // + {GC0310_8BIT, 0x0b, 0x00}, //col start + {GC0310_8BIT, 0x0c, 0x00}, + {GC0310_8BIT, 0x0d, 0x01}, //height + {GC0310_8BIT, 0x0e, 0xf2}, // 0xf7 //height + {GC0310_8BIT, 0x0f, 0x02}, //width + {GC0310_8BIT, 0x10, 0x94}, // 0xa0 //height + {GC0310_8BIT, 0x17, 0x14}, + {GC0310_8BIT, 0x18, 0x1a}, //0a//[4]double reset + {GC0310_8BIT, 0x19, 0x14}, //AD pipeline + {GC0310_8BIT, 0x1b, 0x48}, + {GC0310_8BIT, 0x1e, 0x6b}, //3b//col bias + {GC0310_8BIT, 0x1f, 0x28}, //20//00//08//txlow + {GC0310_8BIT, 0x20, 0x89}, //88//0c//[3:2]DA15 + {GC0310_8BIT, 0x21, 0x49}, //48//[3] txhigh + {GC0310_8BIT, 0x22, 0xb0}, + {GC0310_8BIT, 0x23, 0x04}, //[1:0]vcm_r + {GC0310_8BIT, 0x24, 0x16}, //15 + {GC0310_8BIT, 0x34, 0x20}, //[6:4] rsg high//range + +///////////////////////////////////////////////// +//////////////////// BLK //////////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0x26, 0x23}, //[1]dark_current_en [0]offset_en + {GC0310_8BIT, 0x28, 0xff}, //BLK_limie_value + {GC0310_8BIT, 0x29, 0x00}, //global offset + {GC0310_8BIT, 0x33, 0x18}, //offset_ratio + {GC0310_8BIT, 0x37, 0x20}, //dark_current_ratio + {GC0310_8BIT, 0x2a, 0x00}, + {GC0310_8BIT, 0x2b, 0x00}, + {GC0310_8BIT, 0x2c, 0x00}, + {GC0310_8BIT, 0x2d, 0x00}, + {GC0310_8BIT, 0x2e, 0x00}, + {GC0310_8BIT, 0x2f, 0x00}, + {GC0310_8BIT, 0x30, 0x00}, + {GC0310_8BIT, 0x31, 0x00}, + {GC0310_8BIT, 0x47, 0x80}, //a7 + {GC0310_8BIT, 0x4e, 0x66}, //select_row + {GC0310_8BIT, 0xa8, 0x02}, //win_width_dark, same with crop_win_width + {GC0310_8BIT, 0xa9, 0x80}, + +///////////////////////////////////////////////// +////////////////// ISP reg /////////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0x40, 0x06}, // 0xff //ff //48 + {GC0310_8BIT, 0x41, 0x00}, // 0x21 //00//[0]curve_en + {GC0310_8BIT, 0x42, 0x04}, // 0xcf //0a//[1]awn_en + {GC0310_8BIT, 0x44, 0x18}, // 0x18 //02 + {GC0310_8BIT, 0x46, 0x02}, // 0x03 //sync + {GC0310_8BIT, 0x49, 0x03}, + {GC0310_8BIT, 0x4c, 0x20}, //00[5]pretect exp + {GC0310_8BIT, 0x50, 0x01}, //crop enable + {GC0310_8BIT, 0x51, 0x00}, + {GC0310_8BIT, 0x52, 0x00}, + {GC0310_8BIT, 0x53, 0x00}, + {GC0310_8BIT, 0x54, 0x01}, + {GC0310_8BIT, 0x55, 0x01}, //crop window height + {GC0310_8BIT, 0x56, 0xf0}, + {GC0310_8BIT, 0x57, 0x02}, //crop window width + {GC0310_8BIT, 0x58, 0x90}, + +///////////////////////////////////////////////// +/////////////////// GAIN //////////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0x70, 0x70}, //70 //80//global gain + {GC0310_8BIT, 0x71, 0x20}, // pregain gain + {GC0310_8BIT, 0x72, 0x40}, // post gain + {GC0310_8BIT, 0x5a, 0x84}, //84//analog gain 0 + {GC0310_8BIT, 0x5b, 0xc9}, //c9 + {GC0310_8BIT, 0x5c, 0xed}, //ed//not use pga gain highest level + {GC0310_8BIT, 0x77, 0x40}, // R gain 0x74 //awb gain + {GC0310_8BIT, 0x78, 0x40}, // G gain + {GC0310_8BIT, 0x79, 0x40}, // B gain 0x5f + + {GC0310_8BIT, 0x48, 0x00}, + {GC0310_8BIT, 0xfe, 0x01}, + {GC0310_8BIT, 0x0a, 0x45}, //[7]col gain mode + + {GC0310_8BIT, 0x3e, 0x40}, + {GC0310_8BIT, 0x3f, 0x5c}, + {GC0310_8BIT, 0x40, 0x7b}, + {GC0310_8BIT, 0x41, 0xbd}, + {GC0310_8BIT, 0x42, 0xf6}, + {GC0310_8BIT, 0x43, 0x63}, + {GC0310_8BIT, 0x03, 0x60}, + {GC0310_8BIT, 0x44, 0x03}, + +///////////////////////////////////////////////// +///////////////// dark sun ////////////////// +///////////////////////////////////////////////// + {GC0310_8BIT, 0xfe, 0x01}, + {GC0310_8BIT, 0x45, 0xa4}, // 0xf7 + {GC0310_8BIT, 0x46, 0xf0}, // 0xff //f0//sun vaule th + {GC0310_8BIT, 0x48, 0x03}, //sun mode + {GC0310_8BIT, 0x4f, 0x60}, //sun_clamp + {GC0310_8BIT, 0xfe, 0x00}, + + {GC0310_TOK_TERM, 0, 0}, +}; + +static struct gc0310_reg const gc0310_VGA_30fps[] = { + {GC0310_8BIT, 0xfe, 0x00}, + {GC0310_8BIT, 0x0d, 0x01}, //height + {GC0310_8BIT, 0x0e, 0xf2}, // 0xf7 //height + {GC0310_8BIT, 0x0f, 0x02}, //width + {GC0310_8BIT, 0x10, 0x94}, // 0xa0 //height + + {GC0310_8BIT, 0x50, 0x01}, //crop enable + {GC0310_8BIT, 0x51, 0x00}, + {GC0310_8BIT, 0x52, 0x00}, + {GC0310_8BIT, 0x53, 0x00}, + {GC0310_8BIT, 0x54, 0x01}, + {GC0310_8BIT, 0x55, 0x01}, //crop window height + {GC0310_8BIT, 0x56, 0xf0}, + {GC0310_8BIT, 0x57, 0x02}, //crop window width + {GC0310_8BIT, 0x58, 0x90}, + + {GC0310_8BIT, 0xfe, 0x03}, + {GC0310_8BIT, 0x12, 0x90},//00 //04 //00 //04//00 //LWC[7:0] // + {GC0310_8BIT, 0x13, 0x02},//05 //05 //LWC[15:8] + + {GC0310_8BIT, 0xfe, 0x00}, + + {GC0310_TOK_TERM, 0, 0}, +}; + + +struct gc0310_resolution gc0310_res_preview[] = { + { + .desc = "gc0310_VGA_30fps", + .width = 656, // 648, + .height = 496, // 488, + .fps = 30, + //.pix_clk_freq = 73, + .used = 0, +#if 0 + .pixels_per_line = 0x0314, + .lines_per_frame = 0x0213, +#endif + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 2, + .regs = gc0310_VGA_30fps, + }, +}; +#define N_RES_PREVIEW (ARRAY_SIZE(gc0310_res_preview)) + +struct gc0310_resolution gc0310_res_still[] = { + { + .desc = "gc0310_VGA_30fps", + .width = 656, // 648, + .height = 496, // 488, + .fps = 30, + //.pix_clk_freq = 73, + .used = 0, +#if 0 + .pixels_per_line = 0x0314, + .lines_per_frame = 0x0213, +#endif + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 2, + .regs = gc0310_VGA_30fps, + }, +}; +#define N_RES_STILL (ARRAY_SIZE(gc0310_res_still)) + +struct gc0310_resolution gc0310_res_video[] = { + { + .desc = "gc0310_VGA_30fps", + .width = 656, // 648, + .height = 496, // 488, + .fps = 30, + //.pix_clk_freq = 73, + .used = 0, +#if 0 + .pixels_per_line = 0x0314, + .lines_per_frame = 0x0213, +#endif + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 2, + .regs = gc0310_VGA_30fps, + }, +}; +#define N_RES_VIDEO (ARRAY_SIZE(gc0310_res_video)) + +static struct gc0310_resolution *gc0310_res = gc0310_res_preview; +static int N_RES = N_RES_PREVIEW; +#endif + diff --git a/drivers/staging/media/atomisp/i2c/gc2235.c b/drivers/staging/media/atomisp/i2c/gc2235.c new file mode 100644 index 0000000000000000000000000000000000000000..3dd5e7f60cf0bbfadc131851e491ba32b170d7ca --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/gc2235.c @@ -0,0 +1,1233 @@ +/* + * Support for GalaxyCore GC2235 2M camera sensor. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "gc2235.h" + +/* i2c read/write stuff */ +static int gc2235_read_reg(struct i2c_client *client, + u16 data_length, u16 reg, u16 *val) +{ + int err; + struct i2c_msg msg[2]; + unsigned char data[6]; + + if (!client->adapter) { + dev_err(&client->dev, "%s error, no client->adapter\n", + __func__); + return -ENODEV; + } + + if (data_length != GC2235_8BIT) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + memset(msg, 0 , sizeof(msg)); + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = data; + + /* high byte goes out first */ + data[0] = (u8)(reg & 0xff); + + msg[1].addr = client->addr; + msg[1].len = data_length; + msg[1].flags = I2C_M_RD; + msg[1].buf = data; + + err = i2c_transfer(client->adapter, msg, 2); + if (err != 2) { + if (err >= 0) + err = -EIO; + dev_err(&client->dev, + "read from offset 0x%x error %d", reg, err); + return err; + } + + *val = 0; + /* high byte comes first */ + if (data_length == GC2235_8BIT) + *val = (u8)data[0]; + + return 0; +} + +static int gc2235_i2c_write(struct i2c_client *client, u16 len, u8 *data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = len; + msg.buf = data; + ret = i2c_transfer(client->adapter, &msg, 1); + + return ret == num_msg ? 0 : -EIO; +} + +static int gc2235_write_reg(struct i2c_client *client, u16 data_length, + u8 reg, u8 val) +{ + int ret; + unsigned char data[4] = {0}; + const u16 len = data_length + sizeof(u8); /* 16-bit address + data */ + + if (data_length != GC2235_8BIT) { + dev_err(&client->dev, + "%s error, invalid data_length\n", __func__); + return -EINVAL; + } + + /* high byte goes out first */ + data[0] = reg; + data[1] = val; + + ret = gc2235_i2c_write(client, len, data); + if (ret) + dev_err(&client->dev, + "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, ret); + + return ret; +} + +static int __gc2235_flush_reg_array(struct i2c_client *client, + struct gc2235_write_ctrl *ctrl) +{ + u16 size; + + if (ctrl->index == 0) + return 0; + + size = sizeof(u8) + ctrl->index; /* 8-bit address + data */ + ctrl->index = 0; + + return gc2235_i2c_write(client, size, (u8 *)&ctrl->buffer); +} + +static int __gc2235_buf_reg_array(struct i2c_client *client, + struct gc2235_write_ctrl *ctrl, + const struct gc2235_reg *next) +{ + int size; + + if (next->type != GC2235_8BIT) + return -EINVAL; + + size = 1; + ctrl->buffer.data[ctrl->index] = (u8)next->val; + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->reg; + + ctrl->index += size; + + /* + * Buffer cannot guarantee free space for u32? Better flush it to avoid + * possible lack of memory for next item. + */ + if (ctrl->index + sizeof(u8) >= GC2235_MAX_WRITE_BUF_SIZE) + return __gc2235_flush_reg_array(client, ctrl); + + return 0; +} +static int __gc2235_write_reg_is_consecutive(struct i2c_client *client, + struct gc2235_write_ctrl *ctrl, + const struct gc2235_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->reg; +} +static int gc2235_write_reg_array(struct i2c_client *client, + const struct gc2235_reg *reglist) +{ + const struct gc2235_reg *next = reglist; + struct gc2235_write_ctrl ctrl; + int err; + + ctrl.index = 0; + for (; next->type != GC2235_TOK_TERM; next++) { + switch (next->type & GC2235_TOK_MASK) { + case GC2235_TOK_DELAY: + err = __gc2235_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceed. + */ + if (!__gc2235_write_reg_is_consecutive(client, &ctrl, + next)) { + err = __gc2235_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __gc2235_buf_reg_array(client, &ctrl, next); + if (err) { + dev_err(&client->dev, "%s: write error, aborted\n", + __func__); + return err; + } + break; + } + } + + return __gc2235_flush_reg_array(client, &ctrl); +} + +static int gc2235_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + *val = (GC2235_FOCAL_LENGTH_NUM << 16) | GC2235_FOCAL_LENGTH_DEM; + return 0; +} + +static int gc2235_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /*const f number for imx*/ + *val = (GC2235_F_NUMBER_DEFAULT_NUM << 16) | GC2235_F_NUMBER_DEM; + return 0; +} + +static int gc2235_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + *val = (GC2235_F_NUMBER_DEFAULT_NUM << 24) | + (GC2235_F_NUMBER_DEM << 16) | + (GC2235_F_NUMBER_DEFAULT_NUM << 8) | GC2235_F_NUMBER_DEM; + return 0; +} + + +static int gc2235_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct gc2235_resolution *res) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct atomisp_sensor_mode_data *buf = &info->data; + u16 reg_val, reg_val_h, dummy; + int ret; + + if (info == NULL) + return -EINVAL; + + /* pixel clock calculattion */ + buf->vt_pix_clk_freq_mhz = dev->vt_pix_clk_freq_mhz = 30000000; + + /* get integration time */ + buf->coarse_integration_time_min = GC2235_COARSE_INTG_TIME_MIN; + buf->coarse_integration_time_max_margin = + GC2235_COARSE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_min = GC2235_FINE_INTG_TIME_MIN; + buf->fine_integration_time_max_margin = + GC2235_FINE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_def = GC2235_FINE_INTG_TIME_MIN; + buf->frame_length_lines = res->lines_per_frame; + buf->line_length_pck = res->pixels_per_line; + buf->read_mode = res->bin_mode; + + /* get the cropping and output resolution to ISP for this mode. */ + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_H_CROP_START_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_H_CROP_START_L, ®_val); + if (ret) + return ret; + + buf->crop_horizontal_start = ((u16)reg_val_h << 8) | (u16)reg_val; + + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_V_CROP_START_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_V_CROP_START_L, ®_val); + if (ret) + return ret; + + buf->crop_vertical_start = ((u16)reg_val_h << 8) | (u16)reg_val; + + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_H_OUTSIZE_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_H_OUTSIZE_L, ®_val); + if (ret) + return ret; + buf->output_width = ((u16)reg_val_h << 8) | (u16)reg_val; + + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_V_OUTSIZE_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_V_OUTSIZE_L, ®_val); + if (ret) + return ret; + buf->output_height = ((u16)reg_val_h << 8) | (u16)reg_val; + + buf->crop_horizontal_end = buf->crop_horizontal_start + + buf->output_width - 1; + buf->crop_vertical_end = buf->crop_vertical_start + + buf->output_height - 1; + + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_HB_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_HB_L, ®_val); + if (ret) + return ret; + + dummy = ((u16)reg_val_h << 8) | (u16)reg_val; + + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_SH_DELAY_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_SH_DELAY_L, ®_val); + +#if 0 + buf->line_length_pck = buf->output_width + 16 + dummy + + (((u16)reg_val_h << 8) | (u16)reg_val) + 4; +#endif + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_VB_H, ®_val_h); + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_VB_L, ®_val); + if (ret) + return ret; + +#if 0 + buf->frame_length_lines = buf->output_height + 32 + + (((u16)reg_val_h << 8) | (u16)reg_val); +#endif + buf->binning_factor_x = res->bin_factor_x ? + res->bin_factor_x : 1; + buf->binning_factor_y = res->bin_factor_y ? + res->bin_factor_y : 1; + return 0; +} + +static long __gc2235_set_exposure(struct v4l2_subdev *sd, int coarse_itg, + int gain, int digitgain) + +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 coarse_integration = (u16)coarse_itg; + int ret = 0; + u16 expo_coarse_h, expo_coarse_l, gain_val = 0xF0, gain_val2 = 0xF0; + expo_coarse_h = coarse_integration>>8; + expo_coarse_l = coarse_integration & 0xff; + + ret = gc2235_write_reg(client, GC2235_8BIT, + GC2235_EXPOSURE_H, expo_coarse_h); + ret = gc2235_write_reg(client, GC2235_8BIT, + GC2235_EXPOSURE_L, expo_coarse_l); + + if (gain <= 0x58) { + gain_val = 0x40; + gain_val2 = 0x58; + } else if (gain < 256) { + gain_val = 0x40; + gain_val2 = gain; + } else { + gain_val2 = 64 * gain / 256; + gain_val = 0xff; + } + + ret = gc2235_write_reg(client, GC2235_8BIT, + GC2235_GLOBAL_GAIN, (u8)gain_val); + ret = gc2235_write_reg(client, GC2235_8BIT, + GC2235_PRE_GAIN, (u8)gain_val2); + + return ret; +} + + +static int gc2235_set_exposure(struct v4l2_subdev *sd, int exposure, + int gain, int digitgain) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __gc2235_set_exposure(sd, exposure, gain, digitgain); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static long gc2235_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + int exp = exposure->integration_time[0]; + int gain = exposure->gain[0]; + int digitgain = exposure->gain[1]; + + /* we should not accept the invalid value below. */ + if (gain == 0) { + struct i2c_client *client = v4l2_get_subdevdata(sd); + v4l2_err(client, "%s: invalid value\n", __func__); + return -EINVAL; + } + + return gc2235_set_exposure(sd, exp, gain, digitgain); +} +static long gc2235_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return gc2235_s_exposure(sd, arg); + default: + return -EINVAL; + } + return 0; +} +/* This returns the exposure time being used. This should only be used + for filling in EXIF data, not for actual image processing. */ +static int gc2235_q_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 reg_v, reg_v2; + int ret; + + /* get exposure */ + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_EXPOSURE_L, + ®_v); + if (ret) + goto err; + + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_EXPOSURE_H, + ®_v2); + if (ret) + goto err; + + reg_v += reg_v2 << 8; + + *value = reg_v; +err: + return ret; +} + +static int gc2235_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct gc2235_device *dev = + container_of(ctrl->handler, struct gc2235_device, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = gc2235_q_exposure(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = gc2235_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = gc2235_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = gc2235_g_fnumber_range(&dev->sd, &ctrl->val); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .g_volatile_ctrl = gc2235_g_volatile_ctrl +}; + +struct v4l2_ctrl_config gc2235_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .min = 0x0, + .max = 0xffff, + .step = 0x01, + .def = 0x00, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focal length", + .min = GC2235_FOCAL_LENGTH_DEFAULT, + .max = GC2235_FOCAL_LENGTH_DEFAULT, + .step = 0x01, + .def = GC2235_FOCAL_LENGTH_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number", + .min = GC2235_F_NUMBER_DEFAULT, + .max = GC2235_F_NUMBER_DEFAULT, + .step = 0x01, + .def = GC2235_F_NUMBER_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number range", + .min = GC2235_F_NUMBER_RANGE, + .max = GC2235_F_NUMBER_RANGE, + .step = 0x01, + .def = GC2235_F_NUMBER_RANGE, + .flags = 0, + }, +}; + +static int __gc2235_init(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + + /* restore settings */ + gc2235_res = gc2235_res_preview; + N_RES = N_RES_PREVIEW; + + return gc2235_write_reg_array(client, gc2235_init_settings); +} + +static int is_init; +static int gc2235_init(struct v4l2_subdev *sd) +{ + int ret = 0; + ret = __gc2235_init(sd); + + return ret; +} + +static int power_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret = -1; + struct gc2235_device *dev = to_gc2235_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->power_ctrl) + return dev->platform_data->power_ctrl(sd, flag); + + if (flag) { + ret = dev->platform_data->v1p8_ctrl(sd, 1); + usleep_range(60, 90); + if (ret == 0) + ret |= dev->platform_data->v2p8_ctrl(sd, 1); + } else { + ret = dev->platform_data->v1p8_ctrl(sd, 0); + ret |= dev->platform_data->v2p8_ctrl(sd, 0); + } + return ret; +} + +static int gpio_ctrl(struct v4l2_subdev *sd, bool flag) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + int ret = -1; + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->gpio_ctrl) + return dev->platform_data->gpio_ctrl(sd, flag); + + ret |= dev->platform_data->gpio1_ctrl(sd, !flag); + usleep_range(60, 90); + ret = dev->platform_data->gpio0_ctrl(sd, flag); + + return ret; +} + +static int power_up(struct v4l2_subdev *sd) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (NULL == dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + /* power control */ + ret = power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* according to DS, at least 5ms is needed between DOVDD and PWDN */ + usleep_range(5000, 6000); + + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + usleep_range(5000, 6000); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 1); + if (ret) { + ret = gpio_ctrl(sd, 1); + if (ret) + goto fail_power; + } + + msleep(5); + return 0; + +fail_clk: + gpio_ctrl(sd, 0); +fail_power: + power_ctrl(sd, 0); + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (NULL == dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + /* gpio ctrl */ + ret = gpio_ctrl(sd, 0); + if (ret) { + ret = gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed 2\n"); + } + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* power control */ + ret = power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "vprog failed.\n"); + + return ret; +} + +static int gc2235_s_power(struct v4l2_subdev *sd, int on) +{ + int ret; + + if (on == 0) + ret = power_down(sd); + else { + ret = power_up(sd); + if (!ret) + ret = gc2235_init(sd); + is_init = 1; + } + return ret; +} + +/* + * distance - calculate the distance + * @res: resolution + * @w: width + * @h: height + * + * Get the gap between resolution and w/h. + * res->width/height smaller than w/h wouldn't be considered. + * Returns the value of gap or -1 if fail. + */ +#define LARGEST_ALLOWED_RATIO_MISMATCH 800 +static int distance(struct gc2235_resolution *res, u32 w, u32 h) +{ + unsigned int w_ratio = ((res->width << 13)/w); + unsigned int h_ratio; + int match; + + if (h == 0) + return -1; + h_ratio = ((res->height << 13) / h); + if (h_ratio == 0) + return -1; + match = abs(((w_ratio << 13) / h_ratio) - ((int)8192)); + + if ((w_ratio < (int)8192) || (h_ratio < (int)8192) || + (match > LARGEST_ALLOWED_RATIO_MISMATCH)) + return -1; + + return w_ratio + h_ratio; +} + +/* Return the nearest higher resolution index */ +static int nearest_resolution_index(int w, int h) +{ + int i; + int idx = -1; + int dist; + int min_dist = INT_MAX; + struct gc2235_resolution *tmp_res = NULL; + + for (i = 0; i < N_RES; i++) { + tmp_res = &gc2235_res[i]; + dist = distance(tmp_res, w, h); + if (dist == -1) + continue; + if (dist < min_dist) { + min_dist = dist; + idx = i; + } + } + + return idx; +} + +static int get_resolution_index(int w, int h) +{ + int i; + + for (i = 0; i < N_RES; i++) { + if (w != gc2235_res[i].width) + continue; + if (h != gc2235_res[i].height) + continue; + + return i; + } + + return -1; +} + +static int startup(struct v4l2_subdev *sd) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + if (is_init == 0) { + /* force gc2235 to do a reset in res change, otherwise it + * can not output normal after switching res. and it is not + * necessary for first time run up after power on, for the sack + * of performance + */ + power_down(sd); + power_up(sd); + gc2235_write_reg_array(client, gc2235_init_settings); + } + + ret = gc2235_write_reg_array(client, gc2235_res[dev->fmt_idx].regs); + if (ret) { + dev_err(&client->dev, "gc2235 write register err.\n"); + return ret; + } + is_init = 0; + + return ret; +} + +static int gc2235_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + + struct v4l2_mbus_framefmt *fmt = &format->format; + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct camera_mipi_info *gc2235_info = NULL; + int ret = 0; + int idx; + + gc2235_info = v4l2_get_subdev_hostdata(sd); + if (gc2235_info == NULL) + return -EINVAL; + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + mutex_lock(&dev->input_lock); + idx = nearest_resolution_index(fmt->width, fmt->height); + if (idx == -1) { + /* return the largest resolution */ + fmt->width = gc2235_res[N_RES - 1].width; + fmt->height = gc2235_res[N_RES - 1].height; + } else { + fmt->width = gc2235_res[idx].width; + fmt->height = gc2235_res[idx].height; + } + fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + cfg->try_fmt = *fmt; + mutex_unlock(&dev->input_lock); + return 0; + } + + dev->fmt_idx = get_resolution_index(fmt->width, fmt->height); + if (dev->fmt_idx == -1) { + dev_err(&client->dev, "get resolution fail\n"); + mutex_unlock(&dev->input_lock); + return -EINVAL; + } + + ret = startup(sd); + if (ret) { + dev_err(&client->dev, "gc2235 startup err\n"); + goto err; + } + + ret = gc2235_get_intg_factor(client, gc2235_info, + &gc2235_res[dev->fmt_idx]); + if (ret) + dev_err(&client->dev, "failed to get integration_factor\n"); + +err: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int gc2235_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct gc2235_device *dev = to_gc2235_sensor(sd); + + if (format->pad) + return -EINVAL; + + if (!fmt) + return -EINVAL; + + fmt->width = gc2235_res[dev->fmt_idx].width; + fmt->height = gc2235_res[dev->fmt_idx].height; + fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; + + return 0; +} + +static int gc2235_detect(struct i2c_client *client) +{ + struct i2c_adapter *adapter = client->adapter; + u16 high, low; + int ret; + u16 id; + + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_SENSOR_ID_H, &high); + if (ret) { + dev_err(&client->dev, "sensor_id_high = 0x%x\n", high); + return -ENODEV; + } + ret = gc2235_read_reg(client, GC2235_8BIT, + GC2235_SENSOR_ID_L, &low); + id = ((((u16) high) << 8) | (u16) low); + + if (id != GC2235_ID) { + dev_err(&client->dev, "sensor ID error, 0x%x\n", id); + return -ENODEV; + } + + dev_info(&client->dev, "detect gc2235 success\n"); + return 0; +} + +static int gc2235_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + mutex_lock(&dev->input_lock); + + if (enable) + ret = gc2235_write_reg_array(client, gc2235_stream_on); + else + ret = gc2235_write_reg_array(client, gc2235_stream_off); + + mutex_unlock(&dev->input_lock); + return ret; +} + + +static int gc2235_s_config(struct v4l2_subdev *sd, + int irq, void *platform_data) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (platform_data == NULL) + return -ENODEV; + + dev->platform_data = + (struct camera_sensor_platform_data *)platform_data; + + mutex_lock(&dev->input_lock); + if (dev->platform_data->platform_init) { + ret = dev->platform_data->platform_init(client); + if (ret) { + dev_err(&client->dev, "platform init err\n"); + goto platform_init_failed; + } + } + /* power off the module, then power on it in future + * as first power on by board may not fulfill the + * power on sequqence needed by the module + */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "gc2235 power-off err.\n"); + goto fail_power_off; + } + + ret = power_up(sd); + if (ret) { + dev_err(&client->dev, "gc2235 power-up err.\n"); + goto fail_power_on; + } + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + /* config & detect sensor */ + ret = gc2235_detect(client); + if (ret) { + dev_err(&client->dev, "gc2235_detect err s_config.\n"); + goto fail_csi_cfg; + } + + /* turn off sensor, after probed */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "gc2235 power-off err.\n"); + goto fail_csi_cfg; + } + mutex_unlock(&dev->input_lock); + + return 0; + +fail_csi_cfg: + dev->platform_data->csi_cfg(sd, 0); +fail_power_on: + power_down(sd); + dev_err(&client->dev, "sensor power-gating failed\n"); +fail_power_off: + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); +platform_init_failed: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int gc2235_g_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + + if (!param) + return -EINVAL; + + if (param->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + dev_err(&client->dev, "unsupported buffer type.\n"); + return -EINVAL; + } + + memset(param, 0, sizeof(*param)); + param->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + if (dev->fmt_idx >= 0 && dev->fmt_idx < N_RES) { + param->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + param->parm.capture.timeperframe.numerator = 1; + param->parm.capture.capturemode = dev->run_mode; + param->parm.capture.timeperframe.denominator = + gc2235_res[dev->fmt_idx].fps; + } + return 0; +} + +static int gc2235_s_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + dev->run_mode = param->parm.capture.capturemode; + + mutex_lock(&dev->input_lock); + switch (dev->run_mode) { + case CI_MODE_VIDEO: + gc2235_res = gc2235_res_video; + N_RES = N_RES_VIDEO; + break; + case CI_MODE_STILL_CAPTURE: + gc2235_res = gc2235_res_still; + N_RES = N_RES_STILL; + break; + default: + gc2235_res = gc2235_res_preview; + N_RES = N_RES_PREVIEW; + } + mutex_unlock(&dev->input_lock); + return 0; +} + +static int gc2235_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + + interval->interval.numerator = 1; + interval->interval.denominator = gc2235_res[dev->fmt_idx].fps; + + return 0; +} + +static int gc2235_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= MAX_FMTS) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_SBGGR10_1X10; + return 0; +} + +static int gc2235_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + int index = fse->index; + + if (index >= N_RES) + return -EINVAL; + + fse->min_width = gc2235_res[index].width; + fse->min_height = gc2235_res[index].height; + fse->max_width = gc2235_res[index].width; + fse->max_height = gc2235_res[index].height; + + return 0; + +} + +static int gc2235_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + struct gc2235_device *dev = to_gc2235_sensor(sd); + + mutex_lock(&dev->input_lock); + *frames = gc2235_res[dev->fmt_idx].skip_frames; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static const struct v4l2_subdev_sensor_ops gc2235_sensor_ops = { + .g_skip_frames = gc2235_g_skip_frames, +}; + +static const struct v4l2_subdev_video_ops gc2235_video_ops = { + .s_stream = gc2235_s_stream, + .g_parm = gc2235_g_parm, + .s_parm = gc2235_s_parm, + .g_frame_interval = gc2235_g_frame_interval, +}; + +static const struct v4l2_subdev_core_ops gc2235_core_ops = { + .s_power = gc2235_s_power, + .ioctl = gc2235_ioctl, +}; + +static const struct v4l2_subdev_pad_ops gc2235_pad_ops = { + .enum_mbus_code = gc2235_enum_mbus_code, + .enum_frame_size = gc2235_enum_frame_size, + .get_fmt = gc2235_get_fmt, + .set_fmt = gc2235_set_fmt, +}; + +static const struct v4l2_subdev_ops gc2235_ops = { + .core = &gc2235_core_ops, + .video = &gc2235_video_ops, + .pad = &gc2235_pad_ops, + .sensor = &gc2235_sensor_ops, +}; + +static int gc2235_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct gc2235_device *dev = to_gc2235_sensor(sd); + dev_dbg(&client->dev, "gc2235_remove...\n"); + + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); + + dev->platform_data->csi_cfg(sd, 0); + + v4l2_device_unregister_subdev(sd); + media_entity_cleanup(&dev->sd.entity); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + kfree(dev); + + return 0; +} + +static int gc2235_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct gc2235_device *dev; + void *gcpdev; + int ret; + unsigned int i; + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) { + dev_err(&client->dev, "out of memory\n"); + return -ENOMEM; + } + + mutex_init(&dev->input_lock); + + dev->fmt_idx = 0; + v4l2_i2c_subdev_init(&(dev->sd), client, &gc2235_ops); + + gcpdev = client->dev.platform_data; + if (ACPI_COMPANION(&client->dev)) + gcpdev = gmin_camera_platform_data(&dev->sd, + ATOMISP_INPUT_FORMAT_RAW_10, + atomisp_bayer_order_grbg); + + ret = gc2235_s_config(&dev->sd, client->irq, gcpdev); + if (ret) + goto out_free; + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = MEDIA_BUS_FMT_SBGGR10_1X10; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = + v4l2_ctrl_handler_init(&dev->ctrl_handler, + ARRAY_SIZE(gc2235_controls)); + if (ret) { + gc2235_remove(client); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(gc2235_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &gc2235_controls[i], + NULL); + + if (dev->ctrl_handler.error) { + gc2235_remove(client); + return dev->ctrl_handler.error; + } + + /* Use same lock for controls as for everything else. */ + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = &dev->ctrl_handler; + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) + gc2235_remove(client); + + if (ACPI_HANDLE(&client->dev)) + ret = atomisp_register_i2c_module(&dev->sd, gcpdev, RAW_CAMERA); + + return ret; +out_free: + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + + return ret; +} + +static struct acpi_device_id gc2235_acpi_match[] = { + { "INT33F8" }, + {}, +}; + +MODULE_DEVICE_TABLE(acpi, gc2235_acpi_match); +MODULE_DEVICE_TABLE(i2c, gc2235_id); +static struct i2c_driver gc2235_driver = { + .driver = { + .owner = THIS_MODULE, + .name = GC2235_NAME, + .acpi_match_table = ACPI_PTR(gc2235_acpi_match), + }, + .probe = gc2235_probe, + .remove = gc2235_remove, + .id_table = gc2235_id, +}; + +static int init_gc2235(void) +{ + return i2c_add_driver(&gc2235_driver); +} + +static void exit_gc2235(void) +{ + + i2c_del_driver(&gc2235_driver); +} + +module_init(init_gc2235); +module_exit(exit_gc2235); + +MODULE_AUTHOR("Shuguang Gong "); +MODULE_DESCRIPTION("A low-level driver for GC2235 sensors"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/gc2235.h b/drivers/staging/media/atomisp/i2c/gc2235.h new file mode 100644 index 0000000000000000000000000000000000000000..a67f3f13efe7784a1f565ad7110ab179a9c2d626 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/gc2235.h @@ -0,0 +1,672 @@ +/* + * Support for GalaxyCore GC2235 2M camera sensor. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. + * + */ + +#ifndef __GC2235_H__ +#define __GC2235_H__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define GC2235_NAME "gc2235" + +/* Defines for register writes and register array processing */ +#define I2C_MSG_LENGTH 0x2 +#define I2C_RETRY_COUNT 5 + +#define GC2235_FOCAL_LENGTH_NUM 278 /*2.78mm*/ +#define GC2235_FOCAL_LENGTH_DEM 100 +#define GC2235_F_NUMBER_DEFAULT_NUM 26 +#define GC2235_F_NUMBER_DEM 10 + +#define MAX_FMTS 1 + +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define GC2235_FOCAL_LENGTH_DEFAULT 0x1160064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define GC2235_F_NUMBER_DEFAULT 0x1a000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define GC2235_F_NUMBER_RANGE 0x1a0a1a0a +#define GC2235_ID 0x2235 + +#define GC2235_FINE_INTG_TIME_MIN 0 +#define GC2235_FINE_INTG_TIME_MAX_MARGIN 0 +#define GC2235_COARSE_INTG_TIME_MIN 1 +#define GC2235_COARSE_INTG_TIME_MAX_MARGIN 6 + +/* + * GC2235 System control registers + */ +/* + * GC2235 System control registers + */ +#define GC2235_SENSOR_ID_H 0xF0 +#define GC2235_SENSOR_ID_L 0xF1 +#define GC2235_RESET_RELATED 0xFE +#define GC2235_SW_RESET 0x8 +#define GC2235_MIPI_RESET 0x3 +#define GC2235_RESET_BIT 0x4 +#define GC2235_REGISTER_PAGE_0 0x0 +#define GC2235_REGISTER_PAGE_3 0x3 + +#define GC2235_V_CROP_START_H 0x91 +#define GC2235_V_CROP_START_L 0x92 +#define GC2235_H_CROP_START_H 0x93 +#define GC2235_H_CROP_START_L 0x94 +#define GC2235_V_OUTSIZE_H 0x95 +#define GC2235_V_OUTSIZE_L 0x96 +#define GC2235_H_OUTSIZE_H 0x97 +#define GC2235_H_OUTSIZE_L 0x98 + +#define GC2235_HB_H 0x5 +#define GC2235_HB_L 0x6 +#define GC2235_VB_H 0x7 +#define GC2235_VB_L 0x8 +#define GC2235_SH_DELAY_H 0x11 +#define GC2235_SH_DELAY_L 0x12 + +#define GC2235_CSI2_MODE 0x10 + +#define GC2235_EXPOSURE_H 0x3 +#define GC2235_EXPOSURE_L 0x4 +#define GC2235_GLOBAL_GAIN 0xB0 +#define GC2235_PRE_GAIN 0xB1 +#define GC2235_AWB_R_GAIN 0xB3 +#define GC2235_AWB_G_GAIN 0xB4 +#define GC2235_AWB_B_GAIN 0xB5 + +#define GC2235_START_STREAMING 0x91 +#define GC2235_STOP_STREAMING 0x0 + +struct regval_list { + u16 reg_num; + u8 value; +}; + +struct gc2235_resolution { + u8 *desc; + const struct gc2235_reg *regs; + int res; + int width; + int height; + int fps; + int pix_clk_freq; + u32 skip_frames; + u16 pixels_per_line; + u16 lines_per_frame; + u8 bin_factor_x; + u8 bin_factor_y; + u8 bin_mode; + bool used; +}; + +struct gc2235_format { + u8 *desc; + u32 pixelformat; + struct gc2235_reg *regs; +}; + +/* + * gc2235 device structure. + */ +struct gc2235_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + struct mutex input_lock; + struct v4l2_ctrl_handler ctrl_handler; + + struct camera_sensor_platform_data *platform_data; + int vt_pix_clk_freq_mhz; + int fmt_idx; + int run_mode; + u8 res; + u8 type; +}; + +enum gc2235_tok_type { + GC2235_8BIT = 0x0001, + GC2235_16BIT = 0x0002, + GC2235_32BIT = 0x0004, + GC2235_TOK_TERM = 0xf000, /* terminating token for reg list */ + GC2235_TOK_DELAY = 0xfe00, /* delay token for reg list */ + GC2235_TOK_MASK = 0xfff0 +}; + +/** + * struct gc2235_reg - MI sensor register format + * @type: type of the register + * @reg: 8-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ +struct gc2235_reg { + enum gc2235_tok_type type; + u8 reg; + u32 val; /* @set value for read/mod/write, @mask */ +}; + +#define to_gc2235_sensor(x) container_of(x, struct gc2235_device, sd) + +#define GC2235_MAX_WRITE_BUF_SIZE 30 + +struct gc2235_write_buffer { + u8 addr; + u8 data[GC2235_MAX_WRITE_BUF_SIZE]; +}; + +struct gc2235_write_ctrl { + int index; + struct gc2235_write_buffer buffer; +}; + +static const struct i2c_device_id gc2235_id[] = { + {GC2235_NAME, 0}, + {} +}; + +static struct gc2235_reg const gc2235_stream_on[] = { + { GC2235_8BIT, 0xfe, 0x03}, /* switch to P3 */ + { GC2235_8BIT, 0x10, 0x91}, /* start mipi */ + { GC2235_8BIT, 0xfe, 0x00}, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +static struct gc2235_reg const gc2235_stream_off[] = { + { GC2235_8BIT, 0xfe, 0x03}, /* switch to P3 */ + { GC2235_8BIT, 0x10, 0x01}, /* stop mipi */ + { GC2235_8BIT, 0xfe, 0x00}, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +static struct gc2235_reg const gc2235_init_settings[] = { + /* Sysytem */ + { GC2235_8BIT, 0xfe, 0x80 }, + { GC2235_8BIT, 0xfe, 0x80 }, + { GC2235_8BIT, 0xfe, 0x80 }, + { GC2235_8BIT, 0xf2, 0x00 }, + { GC2235_8BIT, 0xf6, 0x00 }, + { GC2235_8BIT, 0xfc, 0x06 }, + { GC2235_8BIT, 0xf7, 0x15 }, + { GC2235_8BIT, 0xf8, 0x84 }, + { GC2235_8BIT, 0xf9, 0xfe }, + { GC2235_8BIT, 0xfa, 0x00 }, + { GC2235_8BIT, 0xfe, 0x00 }, + /* Analog & cisctl */ + { GC2235_8BIT, 0x03, 0x04 }, + { GC2235_8BIT, 0x04, 0x9E }, + { GC2235_8BIT, 0x05, 0x00 }, + { GC2235_8BIT, 0x06, 0xfd }, + { GC2235_8BIT, 0x07, 0x00 }, + { GC2235_8BIT, 0x08, 0x14 }, + { GC2235_8BIT, 0x0a, 0x02 }, /* row start */ + { GC2235_8BIT, 0x0c, 0x00 }, /* col start */ + { GC2235_8BIT, 0x0d, 0x04 }, /* win height 1232 */ + { GC2235_8BIT, 0x0e, 0xd0 }, + { GC2235_8BIT, 0x0f, 0x06 }, /* win width: 1616 */ + { GC2235_8BIT, 0x10, 0x60 }, + { GC2235_8BIT, 0x17, 0x15 }, /* mirror flip */ + { GC2235_8BIT, 0x18, 0x1a }, + { GC2235_8BIT, 0x19, 0x06 }, + { GC2235_8BIT, 0x1a, 0x01 }, + { GC2235_8BIT, 0x1b, 0x4d }, + { GC2235_8BIT, 0x1e, 0x88 }, + { GC2235_8BIT, 0x1f, 0x48 }, + { GC2235_8BIT, 0x20, 0x03 }, + { GC2235_8BIT, 0x21, 0x7f }, + { GC2235_8BIT, 0x22, 0x83 }, + { GC2235_8BIT, 0x23, 0x42 }, + { GC2235_8BIT, 0x24, 0x16 }, + { GC2235_8BIT, 0x26, 0x01 }, /*analog gain*/ + { GC2235_8BIT, 0x27, 0x30 }, + { GC2235_8BIT, 0x3f, 0x00 }, /* PRC */ + /* blk */ + { GC2235_8BIT, 0x40, 0xa3 }, + { GC2235_8BIT, 0x41, 0x82 }, + { GC2235_8BIT, 0x43, 0x20 }, + { GC2235_8BIT, 0x5e, 0x18 }, + { GC2235_8BIT, 0x5f, 0x18 }, + { GC2235_8BIT, 0x60, 0x18 }, + { GC2235_8BIT, 0x61, 0x18 }, + { GC2235_8BIT, 0x62, 0x18 }, + { GC2235_8BIT, 0x63, 0x18 }, + { GC2235_8BIT, 0x64, 0x18 }, + { GC2235_8BIT, 0x65, 0x18 }, + { GC2235_8BIT, 0x66, 0x20 }, + { GC2235_8BIT, 0x67, 0x20 }, + { GC2235_8BIT, 0x68, 0x20 }, + { GC2235_8BIT, 0x69, 0x20 }, + /* Gain */ + { GC2235_8BIT, 0xb2, 0x00 }, + { GC2235_8BIT, 0xb3, 0x40 }, + { GC2235_8BIT, 0xb4, 0x40 }, + { GC2235_8BIT, 0xb5, 0x40 }, + /* Dark sun */ + { GC2235_8BIT, 0xbc, 0x00 }, + + { GC2235_8BIT, 0xfe, 0x03 }, + { GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */ + { GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; +/* + * Register settings for various resolution + */ +static struct gc2235_reg const gc2235_1296_736_30fps[] = { + { GC2235_8BIT, 0x8b, 0xa0 }, + { GC2235_8BIT, 0x8c, 0x02 }, + + { GC2235_8BIT, 0x07, 0x01 }, /* VBI */ + { GC2235_8BIT, 0x08, 0x44 }, + { GC2235_8BIT, 0x09, 0x00 }, /* row start */ + { GC2235_8BIT, 0x0a, 0xf0 }, + { GC2235_8BIT, 0x0b, 0x00 }, /* col start */ + { GC2235_8BIT, 0x0c, 0xa0 }, + { GC2235_8BIT, 0x0d, 0x02 }, /* win height 736 */ + { GC2235_8BIT, 0x0e, 0xf0 }, + { GC2235_8BIT, 0x0f, 0x05 }, /* win width: 1296 */ + { GC2235_8BIT, 0x10, 0x20 }, + + { GC2235_8BIT, 0x90, 0x01 }, + { GC2235_8BIT, 0x92, 0x08 }, + { GC2235_8BIT, 0x94, 0x08 }, + { GC2235_8BIT, 0x95, 0x02 }, /* crop win height 736 */ + { GC2235_8BIT, 0x96, 0xe0 }, + { GC2235_8BIT, 0x97, 0x05 }, /* crop win width 1296 */ + { GC2235_8BIT, 0x98, 0x10 }, + /* mimi init */ + { GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */ + { GC2235_8BIT, 0x01, 0x07 }, + { GC2235_8BIT, 0x02, 0x11 }, + { GC2235_8BIT, 0x03, 0x11 }, + { GC2235_8BIT, 0x06, 0x80 }, + { GC2235_8BIT, 0x11, 0x2b }, + /* set mipi buffer */ + { GC2235_8BIT, 0x12, 0x54 }, /* val_low = (width * 10 / 8) & 0xFF */ + { GC2235_8BIT, 0x13, 0x06 }, /* val_high = (width * 10 / 8) >> 8 */ + + { GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/ + { GC2235_8BIT, 0x04, 0x10 }, + { GC2235_8BIT, 0x05, 0x00 }, + { GC2235_8BIT, 0x17, 0x01 }, + + { GC2235_8BIT, 0x22, 0x01 }, + { GC2235_8BIT, 0x23, 0x05 }, + { GC2235_8BIT, 0x24, 0x10 }, + { GC2235_8BIT, 0x25, 0x10 }, + { GC2235_8BIT, 0x26, 0x02 }, + { GC2235_8BIT, 0x21, 0x10 }, + { GC2235_8BIT, 0x29, 0x01 }, + { GC2235_8BIT, 0x2a, 0x02 }, + { GC2235_8BIT, 0x2b, 0x02 }, + + { GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */ + { GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +static struct gc2235_reg const gc2235_960_640_30fps[] = { + { GC2235_8BIT, 0x8b, 0xa0 }, + { GC2235_8BIT, 0x8c, 0x02 }, + + { GC2235_8BIT, 0x07, 0x02 }, /* VBI */ + { GC2235_8BIT, 0x08, 0xA4 }, + { GC2235_8BIT, 0x09, 0x01 }, /* row start */ + { GC2235_8BIT, 0x0a, 0x18 }, + { GC2235_8BIT, 0x0b, 0x01 }, /* col start */ + { GC2235_8BIT, 0x0c, 0x40 }, + { GC2235_8BIT, 0x0d, 0x02 }, /* win height 656 */ + { GC2235_8BIT, 0x0e, 0x90 }, + { GC2235_8BIT, 0x0f, 0x03 }, /* win width: 976 */ + { GC2235_8BIT, 0x10, 0xd0 }, + + { GC2235_8BIT, 0x90, 0x01 }, + { GC2235_8BIT, 0x92, 0x02 }, + { GC2235_8BIT, 0x94, 0x06 }, + { GC2235_8BIT, 0x95, 0x02 }, /* crop win height 640 */ + { GC2235_8BIT, 0x96, 0x80 }, + { GC2235_8BIT, 0x97, 0x03 }, /* crop win width 960 */ + { GC2235_8BIT, 0x98, 0xc0 }, + /* mimp init */ + { GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */ + { GC2235_8BIT, 0x01, 0x07 }, + { GC2235_8BIT, 0x02, 0x11 }, + { GC2235_8BIT, 0x03, 0x11 }, + { GC2235_8BIT, 0x06, 0x80 }, + { GC2235_8BIT, 0x11, 0x2b }, + /* set mipi buffer */ + { GC2235_8BIT, 0x12, 0xb0 }, /* val_low = (width * 10 / 8) & 0xFF */ + { GC2235_8BIT, 0x13, 0x04 }, /* val_high = (width * 10 / 8) >> 8 */ + + { GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/ + { GC2235_8BIT, 0x04, 0x10 }, + { GC2235_8BIT, 0x05, 0x00 }, + { GC2235_8BIT, 0x17, 0x01 }, + { GC2235_8BIT, 0x22, 0x01 }, + { GC2235_8BIT, 0x23, 0x05 }, + { GC2235_8BIT, 0x24, 0x10 }, + { GC2235_8BIT, 0x25, 0x10 }, + { GC2235_8BIT, 0x26, 0x02 }, + { GC2235_8BIT, 0x21, 0x10 }, + { GC2235_8BIT, 0x29, 0x01 }, + { GC2235_8BIT, 0x2a, 0x02 }, + { GC2235_8BIT, 0x2b, 0x02 }, + { GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */ + { GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +static struct gc2235_reg const gc2235_1600_900_30fps[] = { + { GC2235_8BIT, 0x8b, 0xa0 }, + { GC2235_8BIT, 0x8c, 0x02 }, + + { GC2235_8BIT, 0x0d, 0x03 }, /* win height 932 */ + { GC2235_8BIT, 0x0e, 0xa4 }, + { GC2235_8BIT, 0x0f, 0x06 }, /* win width: 1632 */ + { GC2235_8BIT, 0x10, 0x50 }, + + { GC2235_8BIT, 0x90, 0x01 }, + { GC2235_8BIT, 0x92, 0x02 }, + { GC2235_8BIT, 0x94, 0x06 }, + { GC2235_8BIT, 0x95, 0x03 }, /* crop win height 900 */ + { GC2235_8BIT, 0x96, 0x84 }, + { GC2235_8BIT, 0x97, 0x06 }, /* crop win width 1600 */ + { GC2235_8BIT, 0x98, 0x40 }, + /* mimi init */ + { GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */ + { GC2235_8BIT, 0x01, 0x07 }, + { GC2235_8BIT, 0x02, 0x11 }, + { GC2235_8BIT, 0x03, 0x11 }, + { GC2235_8BIT, 0x06, 0x80 }, + { GC2235_8BIT, 0x11, 0x2b }, + /* set mipi buffer */ + { GC2235_8BIT, 0x12, 0xd0 }, /* val_low = (width * 10 / 8) & 0xFF */ + { GC2235_8BIT, 0x13, 0x07 }, /* val_high = (width * 10 / 8) >> 8 */ + + { GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/ + { GC2235_8BIT, 0x04, 0x10 }, + { GC2235_8BIT, 0x05, 0x00 }, + { GC2235_8BIT, 0x17, 0x01 }, + { GC2235_8BIT, 0x22, 0x01 }, + { GC2235_8BIT, 0x23, 0x05 }, + { GC2235_8BIT, 0x24, 0x10 }, + { GC2235_8BIT, 0x25, 0x10 }, + { GC2235_8BIT, 0x26, 0x02 }, + { GC2235_8BIT, 0x21, 0x10 }, + { GC2235_8BIT, 0x29, 0x01 }, + { GC2235_8BIT, 0x2a, 0x02 }, + { GC2235_8BIT, 0x2b, 0x02 }, + { GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */ + { GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +static struct gc2235_reg const gc2235_1616_1082_30fps[] = { + { GC2235_8BIT, 0x8b, 0xa0 }, + { GC2235_8BIT, 0x8c, 0x02 }, + + { GC2235_8BIT, 0x0d, 0x04 }, /* win height 1232 */ + { GC2235_8BIT, 0x0e, 0xd0 }, + { GC2235_8BIT, 0x0f, 0x06 }, /* win width: 1616 */ + { GC2235_8BIT, 0x10, 0x50 }, + + { GC2235_8BIT, 0x90, 0x01 }, + { GC2235_8BIT, 0x92, 0x4a }, + { GC2235_8BIT, 0x94, 0x00 }, + { GC2235_8BIT, 0x95, 0x04 }, /* crop win height 1082 */ + { GC2235_8BIT, 0x96, 0x3a }, + { GC2235_8BIT, 0x97, 0x06 }, /* crop win width 1616 */ + { GC2235_8BIT, 0x98, 0x50 }, + /* mimp init */ + { GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */ + { GC2235_8BIT, 0x01, 0x07 }, + { GC2235_8BIT, 0x02, 0x11 }, + { GC2235_8BIT, 0x03, 0x11 }, + { GC2235_8BIT, 0x06, 0x80 }, + { GC2235_8BIT, 0x11, 0x2b }, + /* set mipi buffer */ + { GC2235_8BIT, 0x12, 0xe4 }, /* val_low = (width * 10 / 8) & 0xFF */ + { GC2235_8BIT, 0x13, 0x07 }, /* val_high = (width * 10 / 8) >> 8 */ + + { GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/ + { GC2235_8BIT, 0x04, 0x10 }, + { GC2235_8BIT, 0x05, 0x00 }, + { GC2235_8BIT, 0x17, 0x01 }, + { GC2235_8BIT, 0x22, 0x01 }, + { GC2235_8BIT, 0x23, 0x05 }, + { GC2235_8BIT, 0x24, 0x10 }, + { GC2235_8BIT, 0x25, 0x10 }, + { GC2235_8BIT, 0x26, 0x02 }, + { GC2235_8BIT, 0x21, 0x10 }, + { GC2235_8BIT, 0x29, 0x01 }, + { GC2235_8BIT, 0x2a, 0x02 }, + { GC2235_8BIT, 0x2b, 0x02 }, + { GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */ + { GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +static struct gc2235_reg const gc2235_1616_1216_30fps[] = { + { GC2235_8BIT, 0x8b, 0xa0 }, + { GC2235_8BIT, 0x8c, 0x02 }, + + { GC2235_8BIT, 0x0d, 0x04 }, /* win height 1232 */ + { GC2235_8BIT, 0x0e, 0xd0 }, + { GC2235_8BIT, 0x0f, 0x06 }, /* win width: 1616 */ + { GC2235_8BIT, 0x10, 0x50 }, + + { GC2235_8BIT, 0x90, 0x01 }, + { GC2235_8BIT, 0x92, 0x02 }, + { GC2235_8BIT, 0x94, 0x00 }, + { GC2235_8BIT, 0x95, 0x04 }, /* crop win height 1216 */ + { GC2235_8BIT, 0x96, 0xc0 }, + { GC2235_8BIT, 0x97, 0x06 }, /* crop win width 1616 */ + { GC2235_8BIT, 0x98, 0x50 }, + /* mimi init */ + { GC2235_8BIT, 0xfe, 0x03 }, /* switch to P3 */ + { GC2235_8BIT, 0x01, 0x07 }, + { GC2235_8BIT, 0x02, 0x11 }, + { GC2235_8BIT, 0x03, 0x11 }, + { GC2235_8BIT, 0x06, 0x80 }, + { GC2235_8BIT, 0x11, 0x2b }, + /* set mipi buffer */ + { GC2235_8BIT, 0x12, 0xe4 }, /* val_low = (width * 10 / 8) & 0xFF */ + { GC2235_8BIT, 0x13, 0x07 }, /* val_high = (width * 10 / 8) >> 8 */ + { GC2235_8BIT, 0x15, 0x12 }, /* DPHY mode*/ + { GC2235_8BIT, 0x04, 0x10 }, + { GC2235_8BIT, 0x05, 0x00 }, + { GC2235_8BIT, 0x17, 0x01 }, + { GC2235_8BIT, 0x22, 0x01 }, + { GC2235_8BIT, 0x23, 0x05 }, + { GC2235_8BIT, 0x24, 0x10 }, + { GC2235_8BIT, 0x25, 0x10 }, + { GC2235_8BIT, 0x26, 0x02 }, + { GC2235_8BIT, 0x21, 0x10 }, + { GC2235_8BIT, 0x29, 0x01 }, + { GC2235_8BIT, 0x2a, 0x02 }, + { GC2235_8BIT, 0x2b, 0x02 }, + { GC2235_8BIT, 0x10, 0x01 }, /* disable mipi */ + { GC2235_8BIT, 0xfe, 0x00 }, /* switch to P0 */ + { GC2235_TOK_TERM, 0, 0 } +}; + +struct gc2235_resolution gc2235_res_preview[] = { + + { + .desc = "gc2235_1600_900_30fps", + .width = 1600, + .height = 900, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 2132, + .lines_per_frame = 1068, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1600_900_30fps, + }, + + { + .desc = "gc2235_1600_1066_30fps", + .width = 1616, + .height = 1082, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 2132, + .lines_per_frame = 1368, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1616_1082_30fps, + }, + { + .desc = "gc2235_1600_1200_30fps", + .width = 1616, + .height = 1216, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 2132, + .lines_per_frame = 1368, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1616_1216_30fps, + }, + +}; +#define N_RES_PREVIEW (ARRAY_SIZE(gc2235_res_preview)) + +struct gc2235_resolution gc2235_res_still[] = { + { + .desc = "gc2235_1600_900_30fps", + .width = 1600, + .height = 900, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 2132, + .lines_per_frame = 1068, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1600_900_30fps, + }, + { + .desc = "gc2235_1600_1066_30fps", + .width = 1616, + .height = 1082, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 2132, + .lines_per_frame = 1368, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1616_1082_30fps, + }, + { + .desc = "gc2235_1600_1200_30fps", + .width = 1616, + .height = 1216, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 2132, + .lines_per_frame = 1368, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1616_1216_30fps, + }, + +}; +#define N_RES_STILL (ARRAY_SIZE(gc2235_res_still)) + +struct gc2235_resolution gc2235_res_video[] = { + { + .desc = "gc2235_1296_736_30fps", + .width = 1296, + .height = 736, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 1828, + .lines_per_frame = 888, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_1296_736_30fps, + }, + { + .desc = "gc2235_960_640_30fps", + .width = 960, + .height = 640, + .pix_clk_freq = 30, + .fps = 30, + .used = 0, + .pixels_per_line = 1492, + .lines_per_frame = 792, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = gc2235_960_640_30fps, + }, + +}; +#define N_RES_VIDEO (ARRAY_SIZE(gc2235_res_video)) + +static struct gc2235_resolution *gc2235_res = gc2235_res_preview; +static int N_RES = N_RES_PREVIEW; +#endif diff --git a/drivers/staging/media/atomisp/i2c/imx/Kconfig b/drivers/staging/media/atomisp/i2c/imx/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..a39eeb3b6ad43a06ebce916f89162d313290632e --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/Kconfig @@ -0,0 +1,9 @@ +config VIDEO_IMX + tristate "sony imx sensor support" + depends on I2C && VIDEO_V4L2 && VIDEO_MSRLIST_HELPER && m + ---help--- + This is a Video4Linux2 sensor-level driver for the Sony + IMX RAW sensor. + + It currently depends on internal V4L2 extensions defined in + atomisp driver. diff --git a/drivers/staging/media/atomisp/i2c/imx/Makefile b/drivers/staging/media/atomisp/i2c/imx/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..1d7f7ab94cac3b7ebf454b16a890dab9dc255314 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/Makefile @@ -0,0 +1,8 @@ +obj-$(CONFIG_VIDEO_IMX) += imx1x5.o + +imx1x5-objs := imx.o drv201.o ad5816g.o dw9714.o dw9719.o dw9718.o vcm.o otp.o otp_imx.o otp_brcc064_e2prom.o otp_e2prom.o + +ov8858_driver-objs := ../ov8858.o dw9718.o vcm.o +obj-$(CONFIG_VIDEO_OV8858) += ov8858_driver.o + +ccflags-y += -Werror diff --git a/drivers/staging/media/atomisp/i2c/imx/ad5816g.c b/drivers/staging/media/atomisp/i2c/imx/ad5816g.c new file mode 100644 index 0000000000000000000000000000000000000000..d68ebb49f0024a40874f20b1dac571e487a65f0c --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/ad5816g.c @@ -0,0 +1,225 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ad5816g.h" + +struct ad5816g_device ad5816g_dev; + +static int ad5816g_i2c_rd8(struct i2c_client *client, u8 reg, u8 *val) +{ + struct i2c_msg msg[2]; + u8 buf[2]; + buf[0] = reg; + buf[1] = 0; + + msg[0].addr = AD5816G_VCM_ADDR; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = &buf[0]; + + msg[1].addr = AD5816G_VCM_ADDR; + msg[1].flags = I2C_M_RD; + msg[1].len = 1; + msg[1].buf = &buf[1]; + *val = 0; + if (i2c_transfer(client->adapter, msg, 2) != 2) + return -EIO; + *val = buf[1]; + return 0; +} + +static int ad5816g_i2c_wr8(struct i2c_client *client, u8 reg, u8 val) +{ + struct i2c_msg msg; + u8 buf[2]; + buf[0] = reg; + buf[1] = val; + msg.addr = AD5816G_VCM_ADDR; + msg.flags = 0; + msg.len = 2; + msg.buf = &buf[0]; + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + return 0; +} + +static int ad5816g_i2c_wr16(struct i2c_client *client, u8 reg, u16 val) +{ + struct i2c_msg msg; + u8 buf[3]; + buf[0] = reg; + buf[1] = (u8)(val >> 8); + buf[2] = (u8)(val & 0xff); + msg.addr = AD5816G_VCM_ADDR; + msg.flags = 0; + msg.len = 3; + msg.buf = &buf[0]; + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + return 0; +} + +static int ad5816g_set_arc_mode(struct i2c_client *client) +{ + int ret; + + ret = ad5816g_i2c_wr8(client, AD5816G_CONTROL, AD5816G_ARC_EN); + if (ret) + return ret; + + ret = ad5816g_i2c_wr8(client, AD5816G_MODE, + AD5816G_MODE_2_5M_SWITCH_CLOCK); + if (ret) + return ret; + + ret = ad5816g_i2c_wr8(client, AD5816G_VCM_FREQ, AD5816G_DEF_FREQ); + return ret; +} + +int ad5816g_vcm_power_up(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u8 ad5816g_id; + + /* Enable power */ + ret = ad5816g_dev.platform_data->power_ctrl(sd, 1); + if (ret) + return ret; + /* waiting time AD5816G(vcm) - t1 + t2 + * t1(1ms) -Time from VDD high to first i2c cmd + * t2(100us) - exit power-down mode time + */ + usleep_range(1100, 2200); + /* Detect device */ + ret = ad5816g_i2c_rd8(client, AD5816G_IC_INFO, &ad5816g_id); + if (ret < 0) + goto fail_powerdown; + if (ad5816g_id != AD5816G_ID) { + ret = -ENXIO; + goto fail_powerdown; + } + ret = ad5816g_set_arc_mode(client); + if (ret) + return ret; + + /* set the VCM_THRESHOLD */ + ret = ad5816g_i2c_wr8(client, AD5816G_VCM_THRESHOLD, + AD5816G_DEF_THRESHOLD); + + return ret; + +fail_powerdown: + ad5816g_dev.platform_data->power_ctrl(sd, 0); + return ret; +} + +int ad5816g_vcm_power_down(struct v4l2_subdev *sd) +{ + return ad5816g_dev.platform_data->power_ctrl(sd, 0); +} + + +int ad5816g_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 data = val & VCM_CODE_MASK; + + return ad5816g_i2c_wr16(client, AD5816G_VCM_CODE_MSB, data); +} + +int ad5816g_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + int ret; + + value = clamp(value, 0, AD5816G_MAX_FOCUS_POS); + ret = ad5816g_t_focus_vcm(sd, value); + if (ret == 0) { + ad5816g_dev.number_of_steps = value - ad5816g_dev.focus; + ad5816g_dev.focus = value; + getnstimeofday(&(ad5816g_dev.timestamp_t_focus_abs)); + } + + return ret; +} + +int ad5816g_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + + return ad5816g_t_focus_abs(sd, ad5816g_dev.focus + value); +} + +int ad5816g_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + u32 status = 0; + struct timespec temptime; + const struct timespec timedelay = { + 0, + min_t(u32, abs(ad5816g_dev.number_of_steps) * DELAY_PER_STEP_NS, + DELAY_MAX_PER_STEP_NS), + }; + + ktime_get_ts(&temptime); + + temptime = timespec_sub(temptime, (ad5816g_dev.timestamp_t_focus_abs)); + + if (timespec_compare(&temptime, &timedelay) <= 0) { + status |= ATOMISP_FOCUS_STATUS_MOVING; + status |= ATOMISP_FOCUS_HP_IN_PROGRESS; + } else { + status |= ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE; + status |= ATOMISP_FOCUS_HP_COMPLETE; + } + *value = status; + + return 0; +} + +int ad5816g_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + s32 val; + + ad5816g_q_focus_status(sd, &val); + + if (val & ATOMISP_FOCUS_STATUS_MOVING) + *value = ad5816g_dev.focus - ad5816g_dev.number_of_steps; + else + *value = ad5816g_dev.focus; + + return 0; +} + +int ad5816g_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int ad5816g_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int ad5816g_vcm_init(struct v4l2_subdev *sd) +{ + ad5816g_dev.platform_data = camera_get_af_platform_data(); + return (NULL == ad5816g_dev.platform_data) ? -ENODEV : 0; + +} + + diff --git a/drivers/staging/media/atomisp/i2c/imx/ad5816g.h b/drivers/staging/media/atomisp/i2c/imx/ad5816g.h new file mode 100644 index 0000000000000000000000000000000000000000..7410628c28c30ee78e4bde8f8cd48d9e9ec03fb1 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/ad5816g.h @@ -0,0 +1,49 @@ +#ifndef __AD5816G_H__ +#define __AD5816G_H__ + +#include +#include +#include + +#define AD5816G_VCM_ADDR 0x0e + +/* ad5816g device structure */ +struct ad5816g_device { + const struct camera_af_platform_data *platform_data; + struct timespec timestamp_t_focus_abs; + struct timespec focus_time; /* Time when focus was last time set */ + s32 focus; /* Current focus value */ + s16 number_of_steps; +}; + +#define AD5816G_INVALID_CONFIG 0xffffffff +#define AD5816G_MAX_FOCUS_POS 1023 +#define DELAY_PER_STEP_NS 1000000 +#define DELAY_MAX_PER_STEP_NS (1000000 * 1023) + +/* Register Definitions */ +#define AD5816G_IC_INFO 0x00 +#define AD5816G_IC_VERSION 0x01 +#define AD5816G_CONTROL 0x02 +#define AD5816G_VCM_CODE_MSB 0x03 +#define AD5816G_VCM_CODE_LSB 0x04 +#define AD5816G_STATUS 0x05 +#define AD5816G_MODE 0x06 +#define AD5816G_VCM_FREQ 0x07 +#define AD5816G_VCM_THRESHOLD 0x08 + +/* ARC MODE ENABLE */ +#define AD5816G_ARC_EN 0x02 +/* ARC RES2 MODE */ +#define AD5816G_ARC_RES2 0x01 +/* ARC VCM FREQ - 78.1Hz */ +#define AD5816G_DEF_FREQ 0x7a +/* ARC VCM THRESHOLD - 0x08 << 1 */ +#define AD5816G_DEF_THRESHOLD 0x64 +#define AD5816G_ID 0x24 +#define VCM_CODE_MASK 0x03ff + +#define AD5816G_MODE_2_5M_SWITCH_CLOCK 0x14 + +#endif + diff --git a/drivers/staging/media/atomisp/i2c/imx/common.h b/drivers/staging/media/atomisp/i2c/imx/common.h new file mode 100644 index 0000000000000000000000000000000000000000..7e525cef56ef6bf0abb07e65b7169c20bf903855 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/common.h @@ -0,0 +1,65 @@ +#ifndef __COMMON_H__ +#define __COMMON_H__ + +#define MAX_FPS_OPTIONS_SUPPORTED 3 +#define I2C_MSG_LENGTH 0x2 +#define E2PROM_2ADDR 0x80000000 +#define E2PROM_ADDR_MASK 0x7fffffff + +/* Defines for register writes and register array processing */ +#define IMX_BYTE_MAX 32 +#define IMX_SHORT_MAX 16 +#define I2C_RETRY_COUNT 5 +#define IMX_TOK_MASK 0xfff0 + +enum imx_tok_type { + IMX_8BIT = 0x0001, + IMX_16BIT = 0x0002, + IMX_TOK_TERM = 0xf000, /* terminating token for reg list */ + IMX_TOK_DELAY = 0xfe00 /* delay token for reg list */ +}; + +/** + * struct imx_reg - MI sensor register format + * @type: type of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ +struct imx_reg { + enum imx_tok_type type; + u16 sreg; + u32 val; /* @set value for read/mod/write, @mask */ +}; + +struct imx_fps_setting { + int fps; + unsigned short pixels_per_line; + unsigned short lines_per_frame; + int mipi_freq; /* MIPI lane frequency in kHz */ + const struct imx_reg *regs; /* regs that the fps setting needs */ +}; + +struct imx_resolution { + const struct imx_fps_setting fps_options[MAX_FPS_OPTIONS_SUPPORTED]; + u8 *desc; + const struct imx_reg *regs; + int res; + int width; + int height; + int fps; + unsigned short pixels_per_line; + unsigned short lines_per_frame; + int mipi_freq; /* MIPI lane frequency in kHz */ + unsigned short skip_frames; + u8 bin_factor_x; + u8 bin_factor_y; + bool used; +}; + +#define GROUPED_PARAMETER_HOLD_ENABLE {IMX_8BIT, 0x0104, 0x1} +#define GROUPED_PARAMETER_HOLD_DISABLE {IMX_8BIT, 0x0104, 0x0} + +int imx_write_reg(struct i2c_client *client, u16 data_length, u16 reg, u16 val); +#endif diff --git a/drivers/staging/media/atomisp/i2c/imx/drv201.c b/drivers/staging/media/atomisp/i2c/imx/drv201.c new file mode 100644 index 0000000000000000000000000000000000000000..915e4019cfeb11d95818f0e152fdf8d4c63bf2a1 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/drv201.c @@ -0,0 +1,218 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "drv201.h" + +static struct drv201_device drv201_dev; + +static int drv201_i2c_rd8(struct i2c_client *client, u8 reg, u8 *val) +{ + struct i2c_msg msg[2]; + u8 buf[2]; + buf[0] = reg; + buf[1] = 0; + + msg[0].addr = DRV201_VCM_ADDR; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = &buf[0]; + + msg[1].addr = DRV201_VCM_ADDR; + msg[1].flags = I2C_M_RD; + msg[1].len = 1; + msg[1].buf = &buf[1]; + *val = 0; + if (i2c_transfer(client->adapter, msg, 2) != 2) + return -EIO; + *val = buf[1]; + return 0; +} + +static int drv201_i2c_wr8(struct i2c_client *client, u8 reg, u8 val) +{ + struct i2c_msg msg; + u8 buf[2]; + buf[0] = reg; + buf[1] = val; + msg.addr = DRV201_VCM_ADDR; + msg.flags = 0; + msg.len = 2; + msg.buf = &buf[0]; + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + return 0; +} + +static int drv201_i2c_wr16(struct i2c_client *client, u8 reg, u16 val) +{ + struct i2c_msg msg; + u8 buf[3]; + buf[0] = reg; + buf[1] = (u8)(val >> 8); + buf[2] = (u8)(val & 0xff); + msg.addr = DRV201_VCM_ADDR; + msg.flags = 0; + msg.len = 3; + msg.buf = &buf[0]; + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + return 0; +} + +int drv201_vcm_power_up(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u8 value; + + /* Enable power */ + ret = drv201_dev.platform_data->power_ctrl(sd, 1); + if (ret) + return ret; + /* Wait for VBAT to stabilize */ + udelay(1); + /* + * Jiggle SCL pin to wake up device. + * Drv201 expect SCL from low to high to wake device up. + * So the 1st access to i2c would fail. + * Using following function to wake device up. + */ + drv201_i2c_wr8(client, DRV201_CONTROL, DRV201_RESET); + + /* Need 100us to transit from SHUTDOWN to STANDBY*/ + usleep_range(WAKEUP_DELAY_US, WAKEUP_DELAY_US * 10); + + /* Reset device */ + ret = drv201_i2c_wr8(client, DRV201_CONTROL, DRV201_RESET); + if (ret < 0) + goto fail_powerdown; + + /* Detect device */ + ret = drv201_i2c_rd8(client, DRV201_CONTROL, &value); + if (ret < 0) + goto fail_powerdown; + if (value != DEFAULT_CONTROL_VAL) { + ret = -ENXIO; + goto fail_powerdown; + } + + drv201_dev.focus = DRV201_MAX_FOCUS_POS; + drv201_dev.initialized = true; + + return 0; +fail_powerdown: + drv201_dev.platform_data->power_ctrl(sd, 0); + return ret; +} + +int drv201_vcm_power_down(struct v4l2_subdev *sd) +{ + return drv201_dev.platform_data->power_ctrl(sd, 0); +} + + +int drv201_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 data = val & VCM_CODE_MASK; + + if (!drv201_dev.initialized) + return -ENODEV; + return drv201_i2c_wr16(client, DRV201_VCM_CURRENT, data); +} + +int drv201_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + int ret; + + value = clamp(value, 0, DRV201_MAX_FOCUS_POS); + ret = drv201_t_focus_vcm(sd, value); + if (ret == 0) { + drv201_dev.number_of_steps = value - drv201_dev.focus; + drv201_dev.focus = value; + getnstimeofday(&(drv201_dev.timestamp_t_focus_abs)); + } + + return ret; +} + +int drv201_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + return drv201_t_focus_abs(sd, drv201_dev.focus + value); +} + +int drv201_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + u32 status = 0; + struct timespec temptime; + const struct timespec timedelay = { + 0, + min_t(u32, abs(drv201_dev.number_of_steps)*DELAY_PER_STEP_NS, + DELAY_MAX_PER_STEP_NS), + }; + + ktime_get_ts(&temptime); + + temptime = timespec_sub(temptime, (drv201_dev.timestamp_t_focus_abs)); + + if (timespec_compare(&temptime, &timedelay) <= 0) { + status |= ATOMISP_FOCUS_STATUS_MOVING; + status |= ATOMISP_FOCUS_HP_IN_PROGRESS; + } else { + status |= ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE; + status |= ATOMISP_FOCUS_HP_COMPLETE; + } + *value = status; + + return 0; +} + +int drv201_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + s32 val; + + drv201_q_focus_status(sd, &val); + + if (val & ATOMISP_FOCUS_STATUS_MOVING) + *value = drv201_dev.focus - drv201_dev.number_of_steps; + else + *value = drv201_dev.focus; + + return 0; +} + +int drv201_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int drv201_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int drv201_vcm_init(struct v4l2_subdev *sd) +{ + drv201_dev.platform_data = camera_get_af_platform_data(); + return (NULL == drv201_dev.platform_data) ? -ENODEV : 0; +} + + + diff --git a/drivers/staging/media/atomisp/i2c/imx/drv201.h b/drivers/staging/media/atomisp/i2c/imx/drv201.h new file mode 100644 index 0000000000000000000000000000000000000000..f5f5eecc63a9f71f2c757a648abb39297bc05fd2 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/drv201.h @@ -0,0 +1,38 @@ +#ifndef __DRV201_H__ +#define __DRV201_H__ + +#include +#include +#include + +#define DRV201_VCM_ADDR 0x0e + +/* drv201 device structure */ +struct drv201_device { + const struct camera_af_platform_data *platform_data; + struct timespec timestamp_t_focus_abs; + struct timespec focus_time; /* Time when focus was last time set */ + s32 focus; /* Current focus value */ + s16 number_of_steps; + bool initialized; /* true if drv201 is detected */ +}; + +#define DRV201_INVALID_CONFIG 0xffffffff +#define DRV201_MAX_FOCUS_POS 1023 +#define DELAY_PER_STEP_NS 1000000 +#define DELAY_MAX_PER_STEP_NS (1000000 * 1023) + +#define DRV201_CONTROL 2 +#define DRV201_VCM_CURRENT 3 +#define DRV201_STATUS 5 +#define DRV201_MODE 6 +#define DRV201_VCM_FREQ 7 + +#define DEFAULT_CONTROL_VAL 2 +#define DRV201_RESET 1 +#define WAKEUP_DELAY_US 100 +#define VCM_CODE_MASK 0x03ff + +#endif + + diff --git a/drivers/staging/media/atomisp/i2c/imx/dw9714.c b/drivers/staging/media/atomisp/i2c/imx/dw9714.c new file mode 100644 index 0000000000000000000000000000000000000000..b7dee1b6bb37e510a02b25d32d29d1bb6174a6a9 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/dw9714.c @@ -0,0 +1,235 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "dw9714.h" + +static struct dw9714_device dw9714_dev; +static int dw9714_i2c_write(struct i2c_client *client, u16 data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + u16 val; + + val = cpu_to_be16(data); + msg.addr = DW9714_VCM_ADDR; + msg.flags = 0; + msg.len = DW9714_16BIT; + msg.buf = (u8 *)&val; + + ret = i2c_transfer(client->adapter, &msg, 1); + + return ret == num_msg ? 0 : -EIO; +} + +int dw9714_vcm_power_up(struct v4l2_subdev *sd) +{ + int ret; + + /* Enable power */ + ret = dw9714_dev.platform_data->power_ctrl(sd, 1); + /* waiting time requested by DW9714A(vcm) */ + usleep_range(12000, 12500); + return ret; +} + +int dw9714_vcm_power_down(struct v4l2_subdev *sd) +{ + return dw9714_dev.platform_data->power_ctrl(sd, 0); +} + + +int dw9714_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = -EINVAL; + u8 mclk = vcm_step_mclk(dw9714_dev.vcm_settings.step_setting); + u8 s = vcm_step_s(dw9714_dev.vcm_settings.step_setting); + + /* + * For different mode, VCM_PROTECTION_OFF/ON required by the + * control procedure. For DW9714_DIRECT/DLC mode, slew value is + * VCM_DEFAULT_S(0). + */ + switch (dw9714_dev.vcm_mode) { + case DW9714_DIRECT: + if (dw9714_dev.vcm_settings.update) { + ret = dw9714_i2c_write(client, VCM_PROTECTION_OFF); + if (ret) + return ret; + ret = dw9714_i2c_write(client, DIRECT_VCM); + if (ret) + return ret; + ret = dw9714_i2c_write(client, VCM_PROTECTION_ON); + if (ret) + return ret; + dw9714_dev.vcm_settings.update = false; + } + ret = dw9714_i2c_write(client, + vcm_val(val, VCM_DEFAULT_S)); + break; + case DW9714_LSC: + if (dw9714_dev.vcm_settings.update) { + ret = dw9714_i2c_write(client, VCM_PROTECTION_OFF); + if (ret) + return ret; + ret = dw9714_i2c_write(client, + vcm_dlc_mclk(DLC_DISABLE, mclk)); + if (ret) + return ret; + ret = dw9714_i2c_write(client, + vcm_tsrc(dw9714_dev.vcm_settings.t_src)); + if (ret) + return ret; + ret = dw9714_i2c_write(client, VCM_PROTECTION_ON); + if (ret) + return ret; + dw9714_dev.vcm_settings.update = false; + } + ret = dw9714_i2c_write(client, vcm_val(val, s)); + break; + case DW9714_DLC: + if (dw9714_dev.vcm_settings.update) { + ret = dw9714_i2c_write(client, VCM_PROTECTION_OFF); + if (ret) + return ret; + ret = dw9714_i2c_write(client, + vcm_dlc_mclk(DLC_ENABLE, mclk)); + if (ret) + return ret; + ret = dw9714_i2c_write(client, + vcm_tsrc(dw9714_dev.vcm_settings.t_src)); + if (ret) + return ret; + ret = dw9714_i2c_write(client, VCM_PROTECTION_ON); + if (ret) + return ret; + dw9714_dev.vcm_settings.update = false; + } + ret = dw9714_i2c_write(client, + vcm_val(val, VCM_DEFAULT_S)); + break; + } + return ret; +} + +int dw9714_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + int ret; + + value = clamp(value, 0, DW9714_MAX_FOCUS_POS); + ret = dw9714_t_focus_vcm(sd, value); + if (ret == 0) { + dw9714_dev.number_of_steps = value - dw9714_dev.focus; + dw9714_dev.focus = value; + getnstimeofday(&(dw9714_dev.timestamp_t_focus_abs)); + } + + return ret; +} + +int dw9714_t_focus_abs_init(struct v4l2_subdev *sd) +{ + int ret; + + ret = dw9714_t_focus_vcm(sd, DW9714_DEFAULT_FOCUS_POS); + if (ret == 0) { + dw9714_dev.number_of_steps = + DW9714_DEFAULT_FOCUS_POS - dw9714_dev.focus; + dw9714_dev.focus = DW9714_DEFAULT_FOCUS_POS; + getnstimeofday(&(dw9714_dev.timestamp_t_focus_abs)); + } + + return ret; +} + +int dw9714_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + + return dw9714_t_focus_abs(sd, dw9714_dev.focus + value); +} + +int dw9714_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + u32 status = 0; + struct timespec temptime; + const struct timespec timedelay = { + 0, + min_t(u32, abs(dw9714_dev.number_of_steps)*DELAY_PER_STEP_NS, + DELAY_MAX_PER_STEP_NS), + }; + + ktime_get_ts(&temptime); + + temptime = timespec_sub(temptime, (dw9714_dev.timestamp_t_focus_abs)); + + if (timespec_compare(&temptime, &timedelay) <= 0) { + status |= ATOMISP_FOCUS_STATUS_MOVING; + status |= ATOMISP_FOCUS_HP_IN_PROGRESS; + } else { + status |= ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE; + status |= ATOMISP_FOCUS_HP_COMPLETE; + } + *value = status; + + return 0; +} + +int dw9714_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + s32 val; + + dw9714_q_focus_status(sd, &val); + + if (val & ATOMISP_FOCUS_STATUS_MOVING) + *value = dw9714_dev.focus - dw9714_dev.number_of_steps; + else + *value = dw9714_dev.focus; + + return 0; +} + +int dw9714_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + dw9714_dev.vcm_settings.step_setting = value; + dw9714_dev.vcm_settings.update = true; + + return 0; +} + +int dw9714_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + dw9714_dev.vcm_settings.t_src = value; + dw9714_dev.vcm_settings.update = true; + + return 0; +} + +int dw9714_vcm_init(struct v4l2_subdev *sd) +{ + + /* set VCM to home position and vcm mode to direct*/ + dw9714_dev.vcm_mode = DW9714_DIRECT; + dw9714_dev.vcm_settings.update = false; + dw9714_dev.platform_data = camera_get_af_platform_data(); + return (NULL == dw9714_dev.platform_data) ? -ENODEV : 0; + +} + diff --git a/drivers/staging/media/atomisp/i2c/imx/dw9714.h b/drivers/staging/media/atomisp/i2c/imx/dw9714.h new file mode 100644 index 0000000000000000000000000000000000000000..50f988c1562fdd220359277981e989d9e226a202 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/dw9714.h @@ -0,0 +1,63 @@ +#ifndef __DW9714_H__ +#define __DW9714_H__ + +#include +#include + + +#define DW9714_VCM_ADDR 0x0c + +enum dw9714_tok_type { + DW9714_8BIT = 0x0001, + DW9714_16BIT = 0x0002, +}; + +struct dw9714_vcm_settings { + u16 code; /* bit[9:0]: Data[9:0] */ + u8 t_src; /* bit[4:0]: T_SRC[4:0] */ + u8 step_setting; /* bit[3:0]: S[3:0]/bit[5:4]: MCLK[1:0] */ + bool update; +}; + +enum dw9714_vcm_mode { + DW9714_DIRECT = 0x1, /* direct control */ + DW9714_LSC = 0x2, /* linear slope control */ + DW9714_DLC = 0x3, /* dual level control */ +}; + +/* dw9714 device structure */ +struct dw9714_device { + struct dw9714_vcm_settings vcm_settings; + struct timespec timestamp_t_focus_abs; + enum dw9714_vcm_mode vcm_mode; + s16 number_of_steps; + bool initialized; /* true if dw9714 is detected */ + s32 focus; /* Current focus value */ + struct timespec focus_time; /* Time when focus was last time set */ + __u8 buffer[4]; /* Used for i2c transactions */ + const struct camera_af_platform_data *platform_data; +}; + +#define DW9714_INVALID_CONFIG 0xffffffff +#define DW9714_MAX_FOCUS_POS 1023 +#define DW9714_DEFAULT_FOCUS_POS 290 + + +/* MCLK[1:0] = 01 T_SRC[4:0] = 00001 S[3:0] = 0111 */ +#define DELAY_PER_STEP_NS 1000000 +#define DELAY_MAX_PER_STEP_NS (1000000 * 1023) + +#define DLC_ENABLE 1 +#define DLC_DISABLE 0 +#define VCM_PROTECTION_OFF 0xeca3 +#define VCM_PROTECTION_ON 0xdc51 +#define VCM_DEFAULT_S 0x0 + +#define vcm_step_s(a) (u8)(a & 0xf) +#define vcm_step_mclk(a) (u8)((a >> 4) & 0x3) +#define vcm_dlc_mclk(dlc, mclk) (u16)((dlc << 3) | mclk | 0xa104) +#define vcm_tsrc(tsrc) (u16)(tsrc << 3 | 0xf200) +#define vcm_val(data, s) (u16)(data << 4 | s) +#define DIRECT_VCM vcm_dlc_mclk(0, 0) + +#endif diff --git a/drivers/staging/media/atomisp/i2c/imx/dw9718.c b/drivers/staging/media/atomisp/i2c/imx/dw9718.c new file mode 100644 index 0000000000000000000000000000000000000000..65a1fcf187d5f2395103ae5528f0898023b7f90d --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/dw9718.c @@ -0,0 +1,238 @@ +/* + * Support for dw9718 vcm driver. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include "dw9718.h" + +static struct dw9718_device dw9718_dev; + +static int dw9718_i2c_rd8(struct i2c_client *client, u8 reg, u8 *val) +{ + struct i2c_msg msg[2]; + u8 buf[2] = { reg }; + + msg[0].addr = DW9718_VCM_ADDR; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = buf; + + msg[1].addr = DW9718_VCM_ADDR; + msg[1].flags = I2C_M_RD; + msg[1].len = 1; + msg[1].buf = &buf[1]; + *val = 0; + + if (i2c_transfer(client->adapter, msg, 2) != 2) + return -EIO; + *val = buf[1]; + + return 0; +} + +static int dw9718_i2c_wr8(struct i2c_client *client, u8 reg, u8 val) +{ + struct i2c_msg msg; + u8 buf[2] = { reg, val}; + + msg.addr = DW9718_VCM_ADDR; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + + return 0; +} + +static int dw9718_i2c_wr16(struct i2c_client *client, u8 reg, u16 val) +{ + struct i2c_msg msg; + u8 buf[3] = { reg, (u8)(val >> 8), (u8)(val & 0xff)}; + + msg.addr = DW9718_VCM_ADDR; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + + return 0; +} + +int dw9718_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + value = clamp(value, 0, DW9718_MAX_FOCUS_POS); + ret = dw9718_i2c_wr16(client, DW9718_DATA_M, value); + /*pr_info("%s: value = %d\n", __func__, value);*/ + if (ret < 0) + return ret; + + getnstimeofday(&dw9718_dev.focus_time); + dw9718_dev.focus = value; + + return 0; +} + +int dw9718_vcm_power_up(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u8 value; + + if (dw9718_dev.power_on) + return 0; + + /* Enable power */ + ret = dw9718_dev.platform_data->power_ctrl(sd, 1); + if (ret) { + dev_err(&client->dev, "DW9718_PD power_ctrl failed %d\n", ret); + return ret; + } + /* Wait for VBAT to stabilize */ + udelay(100); + + /* Detect device */ + ret = dw9718_i2c_rd8(client, DW9718_SACT, &value); + if (ret < 0) { + dev_err(&client->dev, "read DW9718_SACT failed %d\n", ret); + goto fail_powerdown; + } + /* + * WORKAROUND: for module P8V12F-203 which are used on + * Cherrytrail Refresh Davis Reef AoB, register SACT is not + * returning default value as spec. But VCM works as expected and + * root cause is still under discussion with vendor. + * workaround here to avoid aborting the power up sequence and just + * give a warning about this error. + */ + if (value != DW9718_SACT_DEFAULT_VAL) + dev_warn(&client->dev, "%s error, incorrect ID\n", __func__); + + /* Initialize according to recommended settings */ + ret = dw9718_i2c_wr8(client, DW9718_CONTROL, + DW9718_CONTROL_SW_LINEAR | + DW9718_CONTROL_S_SAC4 | + DW9718_CONTROL_OCP_DISABLE | + DW9718_CONTROL_UVLO_DISABLE); + if (ret < 0) { + dev_err(&client->dev, "write DW9718_CONTROL failed %d\n", ret); + goto fail_powerdown; + } + ret = dw9718_i2c_wr8(client, DW9718_SACT, + DW9718_SACT_MULT_TWO | + DW9718_SACT_PERIOD_8_8MS); + if (ret < 0) { + dev_err(&client->dev, "write DW9718_SACT failed %d\n", ret); + goto fail_powerdown; + } + + ret = dw9718_t_focus_abs(sd, dw9718_dev.focus); + if (ret) + return ret; + dw9718_dev.initialized = true; + dw9718_dev.power_on = 1; + + return 0; + +fail_powerdown: + dev_err(&client->dev, "%s error, powerup failed\n", __func__); + dw9718_dev.platform_data->power_ctrl(sd, 0); + return ret; +} + +int dw9718_vcm_power_down(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (!dw9718_dev.power_on) + return 0; + + ret = dw9718_dev.platform_data->power_ctrl(sd, 0); + if (ret) { + dev_err(&client->dev, "%s power_ctrl failed\n", + __func__); + return ret; + } + dw9718_dev.power_on = 0; + + return 0; +} + +int dw9718_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + static const struct timespec move_time = { + .tv_sec = 0, + .tv_nsec = 60000000 + }; + struct timespec current_time, finish_time, delta_time; + + getnstimeofday(¤t_time); + finish_time = timespec_add(dw9718_dev.focus_time, move_time); + delta_time = timespec_sub(current_time, finish_time); + if (delta_time.tv_sec >= 0 && delta_time.tv_nsec >= 0) { + *value = ATOMISP_FOCUS_HP_COMPLETE | + ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE; + } else { + *value = ATOMISP_FOCUS_STATUS_MOVING | + ATOMISP_FOCUS_HP_IN_PROGRESS; + } + + return 0; +} + +int dw9718_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + return -EINVAL; +} + +int dw9718_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + return dw9718_t_focus_abs(sd, dw9718_dev.focus + value); +} + +int dw9718_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + *value = dw9718_dev.focus; + return 0; +} +int dw9718_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int dw9718_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int dw9718_vcm_init(struct v4l2_subdev *sd) +{ + dw9718_dev.platform_data = camera_get_af_platform_data(); + dw9718_dev.focus = DW9718_DEFAULT_FOCUS_POSITION; + dw9718_dev.power_on = 0; + return (NULL == dw9718_dev.platform_data) ? -ENODEV : 0; +} diff --git a/drivers/staging/media/atomisp/i2c/imx/dw9718.h b/drivers/staging/media/atomisp/i2c/imx/dw9718.h new file mode 100644 index 0000000000000000000000000000000000000000..fe1fb8a0954c720dc54d025689756251a2b21c3d --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/dw9718.h @@ -0,0 +1,64 @@ +/* + * Support for dw9719 vcm driver. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __DW9718_H__ +#define __DW9718_H__ + +#include +#include + +#define DW9718_VCM_ADDR (0x18 >> 1) + +/* dw9718 device structure */ +struct dw9718_device { + struct timespec timestamp_t_focus_abs; + s16 number_of_steps; + bool initialized; /* true if dw9718 is detected */ + s32 focus; /* Current focus value */ + struct timespec focus_time; /* Time when focus was last time set */ + __u8 buffer[4]; /* Used for i2c transactions */ + const struct camera_af_platform_data *platform_data; + __u8 power_on; +}; + +#define DW9718_MAX_FOCUS_POS 1023 + +/* Register addresses */ +#define DW9718_PD 0x00 +#define DW9718_CONTROL 0x01 +#define DW9718_DATA_M 0x02 +#define DW9718_DATA_L 0x03 +#define DW9718_SW 0x04 +#define DW9718_SACT 0x05 +#define DW9718_FLAG 0x10 + +#define DW9718_CONTROL_SW_LINEAR BIT(0) +#define DW9718_CONTROL_S_SAC4 (BIT(1) | BIT(3)) +#define DW9718_CONTROL_OCP_DISABLE BIT(4) +#define DW9718_CONTROL_UVLO_DISABLE BIT(5) + +#define DW9718_SACT_MULT_TWO 0x00 +#define DW9718_SACT_PERIOD_8_8MS 0x19 +#define DW9718_SACT_DEFAULT_VAL 0x60 + +#define DW9718_DEFAULT_FOCUS_POSITION 300 + +#endif /* __DW9718_H__ */ diff --git a/drivers/staging/media/atomisp/i2c/imx/dw9719.c b/drivers/staging/media/atomisp/i2c/imx/dw9719.c new file mode 100644 index 0000000000000000000000000000000000000000..eca2d76400309b4a4edb666074a7f8adc3bb3d4f --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/dw9719.c @@ -0,0 +1,209 @@ +/* + * Support for dw9719 vcm driver. + * + * Copyright (c) 2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include "dw9719.h" + +static struct dw9719_device dw9719_dev; + +static int dw9719_i2c_rd8(struct i2c_client *client, u8 reg, u8 *val) +{ + struct i2c_msg msg[2]; + u8 buf[2] = { reg }; + + msg[0].addr = DW9719_VCM_ADDR; + msg[0].flags = 0; + msg[0].len = 1; + msg[0].buf = buf; + + msg[1].addr = DW9719_VCM_ADDR; + msg[1].flags = I2C_M_RD; + msg[1].len = 1; + msg[1].buf = &buf[1]; + *val = 0; + + if (i2c_transfer(client->adapter, msg, 2) != 2) + return -EIO; + *val = buf[1]; + + return 0; +} + +static int dw9719_i2c_wr8(struct i2c_client *client, u8 reg, u8 val) +{ + struct i2c_msg msg; + u8 buf[2] = { reg, val }; + + msg.addr = DW9719_VCM_ADDR; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + + return 0; +} + +static int dw9719_i2c_wr16(struct i2c_client *client, u8 reg, u16 val) +{ + struct i2c_msg msg; + u8 buf[3] = { reg, (u8)(val >> 8), (u8)(val & 0xff)}; + + msg.addr = DW9719_VCM_ADDR; + msg.flags = 0; + msg.len = sizeof(buf); + msg.buf = buf; + + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + + return 0; +} + +int dw9719_vcm_power_up(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u8 value; + + /* Enable power */ + ret = dw9719_dev.platform_data->power_ctrl(sd, 1); + /* waiting time requested by DW9714A(vcm) */ + if (ret) + return ret; + /* Wait for VBAT to stabilize */ + udelay(1); + + /* + * Jiggle SCL pin to wake up device. + */ + ret = dw9719_i2c_wr8(client, DW9719_CONTROL, 1); + /* Need 100us to transit from SHUTDOWN to STANDBY*/ + usleep_range(100, 1000); + + /* Enable the ringing compensation */ + ret = dw9719_i2c_wr8(client, DW9719_CONTROL, DW9719_ENABLE_RINGING); + if (ret < 0) + goto fail_powerdown; + + /* Use SAC3 mode */ + ret = dw9719_i2c_wr8(client, DW9719_MODE, DW9719_MODE_SAC3); + if (ret < 0) + goto fail_powerdown; + + /* Set the resonance frequency */ + ret = dw9719_i2c_wr8(client, DW9719_VCM_FREQ, DW9719_DEFAULT_VCM_FREQ); + if (ret < 0) + goto fail_powerdown; + + /* Detect device */ + ret = dw9719_i2c_rd8(client, DW9719_INFO, &value); + if (ret < 0) + goto fail_powerdown; + if (value != DW9719_ID) { + ret = -ENXIO; + goto fail_powerdown; + } + dw9719_dev.focus = 0; + dw9719_dev.initialized = true; + + return 0; + +fail_powerdown: + dw9719_dev.platform_data->power_ctrl(sd, 0); + return ret; +} + +int dw9719_vcm_power_down(struct v4l2_subdev *sd) +{ + return dw9719_dev.platform_data->power_ctrl(sd, 0); +} + +int dw9719_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + static const struct timespec move_time = { + + .tv_sec = 0, + .tv_nsec = 60000000 + }; + struct timespec current_time, finish_time, delta_time; + + getnstimeofday(¤t_time); + finish_time = timespec_add(dw9719_dev.focus_time, move_time); + delta_time = timespec_sub(current_time, finish_time); + if (delta_time.tv_sec >= 0 && delta_time.tv_nsec >= 0) { + *value = ATOMISP_FOCUS_HP_COMPLETE | + ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE; + } else { + *value = ATOMISP_FOCUS_STATUS_MOVING | + ATOMISP_FOCUS_HP_IN_PROGRESS; + } + + return 0; +} + +int dw9719_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + return -EINVAL; +} + +int dw9719_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + value = clamp(value, 0, DW9719_MAX_FOCUS_POS); + ret = dw9719_i2c_wr16(client, DW9719_VCM_CURRENT, value); + if (ret < 0) + return ret; + + getnstimeofday(&dw9719_dev.focus_time); + dw9719_dev.focus = value; + + return 0; +} + +int dw9719_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + return dw9719_t_focus_abs(sd, dw9719_dev.focus + value); +} + +int dw9719_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + *value = dw9719_dev.focus; + return 0; +} +int dw9719_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int dw9719_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + return 0; +} + +int dw9719_vcm_init(struct v4l2_subdev *sd) +{ + dw9719_dev.platform_data = camera_get_af_platform_data(); + return (NULL == dw9719_dev.platform_data) ? -ENODEV : 0; +} diff --git a/drivers/staging/media/atomisp/i2c/imx/dw9719.h b/drivers/staging/media/atomisp/i2c/imx/dw9719.h new file mode 100644 index 0000000000000000000000000000000000000000..cde62752e91553934763ae76c02af0719ae31c45 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/dw9719.h @@ -0,0 +1,58 @@ +/* + * Support for dw9719 vcm driver. + * + * Copyright (c) 2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __DW9719_H__ +#define __DW9719_H__ + +#include +#include + +#define DW9719_VCM_ADDR (0x18 >> 1) + +/* dw9719 device structure */ +struct dw9719_device { + struct timespec timestamp_t_focus_abs; + s16 number_of_steps; + bool initialized; /* true if dw9719 is detected */ + s32 focus; /* Current focus value */ + struct timespec focus_time; /* Time when focus was last time set */ + __u8 buffer[4]; /* Used for i2c transactions */ + const struct camera_af_platform_data *platform_data; +}; + +#define DW9719_INVALID_CONFIG 0xffffffff +#define DW9719_MAX_FOCUS_POS 1023 +#define DELAY_PER_STEP_NS 1000000 +#define DELAY_MAX_PER_STEP_NS (1000000 * 1023) + +#define DW9719_INFO 0 +#define DW9719_ID 0xF1 +#define DW9719_CONTROL 2 +#define DW9719_VCM_CURRENT 3 + +#define DW9719_MODE 6 +#define DW9719_VCM_FREQ 7 + +#define DW9719_MODE_SAC3 0x40 +#define DW9719_DEFAULT_VCM_FREQ 0x04 +#define DW9719_ENABLE_RINGING 0x02 + +#endif diff --git a/drivers/staging/media/atomisp/i2c/imx/imx.c b/drivers/staging/media/atomisp/i2c/imx/imx.c new file mode 100644 index 0000000000000000000000000000000000000000..daa082d99d1fce6f35ae158b7633d43d89a8e769 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx.c @@ -0,0 +1,2510 @@ +/* + * Support for Sony imx 8MP camera sensor. + * + * Copyright (c) 2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "imx.h" + +/* + * The imx135 embedded data info: + * embedded data line num: 2 + * line 0 effective data size(byte): 76 + * line 1 effective data size(byte): 113 + */ +static const uint32_t + imx135_embedded_effective_size[IMX135_EMBEDDED_DATA_LINE_NUM] + = {76, 113}; + +static enum atomisp_bayer_order imx_bayer_order_mapping[] = { + atomisp_bayer_order_rggb, + atomisp_bayer_order_grbg, + atomisp_bayer_order_gbrg, + atomisp_bayer_order_bggr +}; + +static const unsigned int +IMX227_BRACKETING_LUT_FRAME_ENTRY[IMX_MAX_AE_LUT_LENGTH] = { + 0x0E10, 0x0E1E, 0x0E2C, 0x0E3A, 0x0E48}; + +static int +imx_read_reg(struct i2c_client *client, u16 len, u16 reg, u16 *val) +{ + struct i2c_msg msg[2]; + u16 data[IMX_SHORT_MAX]; + int ret, i; + int retry = 0; + + if (len > IMX_BYTE_MAX) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + do { + memset(msg, 0 , sizeof(msg)); + memset(data, 0 , sizeof(data)); + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = I2C_MSG_LENGTH; + msg[0].buf = (u8 *)data; + /* high byte goes first */ + data[0] = cpu_to_be16(reg); + + msg[1].addr = client->addr; + msg[1].len = len; + msg[1].flags = I2C_M_RD; + msg[1].buf = (u8 *)data; + + ret = i2c_transfer(client->adapter, msg, 2); + if (ret != 2) { + dev_err(&client->dev, + "retrying i2c read from offset 0x%x error %d... %d\n", + reg, ret, retry); + msleep(20); + } + } while (ret != 2 && retry++ < I2C_RETRY_COUNT); + + if (ret != 2) + return -EIO; + + /* high byte comes first */ + if (len == IMX_8BIT) { + *val = (u8)data[0]; + } else { + /* 16-bit access is default when len > 1 */ + for (i = 0; i < (len >> 1); i++) + val[i] = be16_to_cpu(data[i]); + } + + return 0; +} + +static int imx_i2c_write(struct i2c_client *client, u16 len, u8 *data) +{ + struct i2c_msg msg; + int ret; + int retry = 0; + + do { + msg.addr = client->addr; + msg.flags = 0; + msg.len = len; + msg.buf = data; + + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret != 1) { + dev_err(&client->dev, + "retrying i2c write transfer... %d\n", retry); + msleep(20); + } + } while (ret != 1 && retry++ < I2C_RETRY_COUNT); + + return ret == 1 ? 0 : -EIO; +} + +int +imx_write_reg(struct i2c_client *client, u16 data_length, u16 reg, u16 val) +{ + int ret; + unsigned char data[4] = {0}; + u16 *wreg = (u16 *)data; + const u16 len = data_length + sizeof(u16); /* 16-bit address + data */ + + if (data_length != IMX_8BIT && data_length != IMX_16BIT) { + v4l2_err(client, "%s error, invalid data_length\n", __func__); + return -EINVAL; + } + + /* high byte goes out first */ + *wreg = cpu_to_be16(reg); + + if (data_length == IMX_8BIT) + data[2] = (u8)(val); + else { + /* IMX_16BIT */ + u16 *wdata = (u16 *)&data[2]; + *wdata = cpu_to_be16(val); + } + + ret = imx_i2c_write(client, len, data); + if (ret) + dev_err(&client->dev, + "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, ret); + + return ret; +} + +/* + * imx_write_reg_array - Initializes a list of imx registers + * @client: i2c driver client structure + * @reglist: list of registers to be written + * + * This function initializes a list of registers. When consecutive addresses + * are found in a row on the list, this function creates a buffer and sends + * consecutive data in a single i2c_transfer(). + * + * __imx_flush_reg_array, __imx_buf_reg_array() and + * __imx_write_reg_is_consecutive() are internal functions to + * imx_write_reg_array_fast() and should be not used anywhere else. + * + */ + +static int __imx_flush_reg_array(struct i2c_client *client, + struct imx_write_ctrl *ctrl) +{ + u16 size; + + if (ctrl->index == 0) + return 0; + + size = sizeof(u16) + ctrl->index; /* 16-bit address + data */ + ctrl->buffer.addr = cpu_to_be16(ctrl->buffer.addr); + ctrl->index = 0; + + return imx_i2c_write(client, size, (u8 *)&ctrl->buffer); +} + +static int __imx_buf_reg_array(struct i2c_client *client, + struct imx_write_ctrl *ctrl, + const struct imx_reg *next) +{ + int size; + u16 *data16; + + switch (next->type) { + case IMX_8BIT: + size = 1; + ctrl->buffer.data[ctrl->index] = (u8)next->val; + break; + case IMX_16BIT: + size = 2; + data16 = (u16 *)&ctrl->buffer.data[ctrl->index]; + *data16 = cpu_to_be16((u16)next->val); + break; + default: + return -EINVAL; + } + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->sreg; + + ctrl->index += size; + + /* + * Buffer cannot guarantee free space for u32? Better flush it to avoid + * possible lack of memory for next item. + */ + if (ctrl->index + sizeof(u16) >= IMX_MAX_WRITE_BUF_SIZE) + return __imx_flush_reg_array(client, ctrl); + + return 0; +} + +static int +__imx_write_reg_is_consecutive(struct i2c_client *client, + struct imx_write_ctrl *ctrl, + const struct imx_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->sreg; +} + +static int imx_write_reg_array(struct i2c_client *client, + const struct imx_reg *reglist) +{ + const struct imx_reg *next = reglist; + struct imx_write_ctrl ctrl; + int err; + + ctrl.index = 0; + for (; next->type != IMX_TOK_TERM; next++) { + switch (next->type & IMX_TOK_MASK) { + case IMX_TOK_DELAY: + err = __imx_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceed. + */ + if (!__imx_write_reg_is_consecutive(client, &ctrl, + next)) { + err = __imx_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __imx_buf_reg_array(client, &ctrl, next); + if (err) { + v4l2_err(client, "%s: write error, aborted\n", + __func__); + return err; + } + break; + } + } + + return __imx_flush_reg_array(client, &ctrl); +} + +static int __imx_min_fps_diff(int fps, const struct imx_fps_setting *fps_list) +{ + int diff = INT_MAX; + int i; + + if (fps == 0) + return 0; + + for (i = 0; i < MAX_FPS_OPTIONS_SUPPORTED; i++) { + if (!fps_list[i].fps) + break; + if (abs(fps_list[i].fps - fps) < diff) + diff = abs(fps_list[i].fps - fps); + } + + return diff; +} + +static int __imx_nearest_fps_index(int fps, + const struct imx_fps_setting *fps_list) +{ + int fps_index = 0; + int i; + + for (i = 0; i < MAX_FPS_OPTIONS_SUPPORTED; i++) { + if (!fps_list[i].fps) + break; + if (abs(fps_list[i].fps - fps) + < abs(fps_list[fps_index].fps - fps)) + fps_index = i; + } + return fps_index; +} + +/* + * This is to choose the nearest fps setting above the requested fps + * fps_list should be in ascendant order. + */ +static int __imx_above_nearest_fps_index(int fps, + const struct imx_fps_setting *fps_list) +{ + int fps_index = 0; + int i; + + for (i = 0; i < MAX_FPS_OPTIONS_SUPPORTED; i++) { + if (!fps_list[i].fps) + break; + if (fps <= fps_list[i].fps) { + fps_index = i; + break; + } + } + + return fps_index; +} + +static int imx_get_lanes(struct v4l2_subdev *sd) +{ + struct camera_mipi_info *imx_info = v4l2_get_subdev_hostdata(sd); + + if (!imx_info) + return -ENOSYS; + if (imx_info->num_lanes < 1 || imx_info->num_lanes > 4 || + imx_info->num_lanes == 3) + return -EINVAL; + + return imx_info->num_lanes; +} + +static int __imx_update_exposure_timing(struct i2c_client *client, u16 exposure, + u16 llp, u16 fll) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx_device *dev = to_imx_sensor(sd); + int ret = 0; + + if (dev->sensor_id != IMX227_ID) { + /* Increase the VTS to match exposure + margin */ + if (exposure > fll - IMX_INTEGRATION_TIME_MARGIN) + fll = exposure + IMX_INTEGRATION_TIME_MARGIN; + } + + ret = imx_write_reg(client, IMX_16BIT, + dev->reg_addr->line_length_pixels, llp); + if (ret) + return ret; + + ret = imx_write_reg(client, IMX_16BIT, + dev->reg_addr->frame_length_lines, fll); + if (ret) + return ret; + + if (exposure) + ret = imx_write_reg(client, IMX_16BIT, + dev->reg_addr->coarse_integration_time, exposure); + + return ret; +} + +static int __imx_update_gain(struct v4l2_subdev *sd, u16 gain) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + /* set global gain */ + ret = imx_write_reg(client, IMX_8BIT, dev->reg_addr->global_gain, gain); + if (ret) + return ret; + + /* set short analog gain */ + if (dev->sensor_id == IMX135_ID) + ret = imx_write_reg(client, IMX_8BIT, IMX_SHORT_AGC_GAIN, gain); + + return ret; +} + +static int __imx_update_digital_gain(struct i2c_client *client, u16 digitgain) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx_device *dev = to_imx_sensor(sd); + struct imx_write_buffer digit_gain; + + digit_gain.addr = cpu_to_be16(dev->reg_addr->dgc_adj); + digit_gain.data[0] = (digitgain >> 8) & 0xFF; + digit_gain.data[1] = digitgain & 0xFF; + + if (dev->sensor_id == IMX219_ID) { + return imx_i2c_write(client, IMX219_DGC_LEN, (u8 *)&digit_gain); + } else if (dev->sensor_id == IMX227_ID) { + return imx_i2c_write(client, IMX227_DGC_LEN, (u8 *)&digit_gain); + } else { + digit_gain.data[2] = (digitgain >> 8) & 0xFF; + digit_gain.data[3] = digitgain & 0xFF; + digit_gain.data[4] = (digitgain >> 8) & 0xFF; + digit_gain.data[5] = digitgain & 0xFF; + digit_gain.data[6] = (digitgain >> 8) & 0xFF; + digit_gain.data[7] = digitgain & 0xFF; + return imx_i2c_write(client, IMX_DGC_LEN, (u8 *)&digit_gain); + } + return 0; +} + +static int imx_set_exposure_gain(struct v4l2_subdev *sd, u16 coarse_itg, + u16 gain, u16 digitgain) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int lanes = imx_get_lanes(sd); + unsigned int digitgain_scaled; + int ret = 0; + + /* Validate exposure: cannot exceed VTS-4 where VTS is 16bit */ + coarse_itg = clamp_t(u16, coarse_itg, 0, IMX_MAX_EXPOSURE_SUPPORTED); + + /* Validate gain: must not exceed maximum 8bit value */ + gain = clamp_t(u16, gain, 0, IMX_MAX_GLOBAL_GAIN_SUPPORTED); + + mutex_lock(&dev->input_lock); + + if (dev->sensor_id == IMX227_ID) { + ret = imx_write_reg_array(client, imx_param_hold); + if (ret) + return ret; + } + + /* For imx175, setting gain must be delayed by one */ + if ((dev->sensor_id == IMX175_ID) && dev->digital_gain) + digitgain_scaled = dev->digital_gain; + else + digitgain_scaled = digitgain; + /* imx132 with two lanes needs more gain to saturate at max */ + if (dev->sensor_id == IMX132_ID && lanes > 1) { + digitgain_scaled *= IMX132_2LANES_GAINFACT; + digitgain_scaled >>= IMX132_2LANES_GAINFACT_SHIFT; + } + /* Validate digital gain: must not exceed 12 bit value*/ + digitgain_scaled = clamp_t(unsigned int, digitgain_scaled, + 0, IMX_MAX_DIGITAL_GAIN_SUPPORTED); + + ret = __imx_update_exposure_timing(client, coarse_itg, + dev->pixels_per_line, dev->lines_per_frame); + if (ret) + goto out; + dev->coarse_itg = coarse_itg; + + if (dev->sensor_id == IMX175_ID) + ret = __imx_update_gain(sd, dev->gain); + else + ret = __imx_update_gain(sd, gain); + if (ret) + goto out; + dev->gain = gain; + + ret = __imx_update_digital_gain(client, digitgain_scaled); + if (ret) + goto out; + dev->digital_gain = digitgain; + +out: + if (dev->sensor_id == IMX227_ID) + ret = imx_write_reg_array(client, imx_param_update); + mutex_unlock(&dev->input_lock); + return ret; +} + +static long imx_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + return imx_set_exposure_gain(sd, exposure->integration_time[0], + exposure->gain[0], exposure->gain[1]); +} + +/* FIXME -To be updated with real OTP reading */ +static int imx_g_priv_int_data(struct v4l2_subdev *sd, + struct v4l2_private_int_data *priv) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + u8 __user *to = priv->data; + u32 read_size = priv->size; + int ret; + + /* No need to copy data if size is 0 */ + if (!read_size) + goto out; + + if (IS_ERR(dev->otp_data)) { + dev_err(&client->dev, "OTP data not available"); + return PTR_ERR(dev->otp_data); + } + /* Correct read_size value only if bigger than maximum */ + if (read_size > dev->otp_driver->size) + read_size = dev->otp_driver->size; + + ret = copy_to_user(to, dev->otp_data, read_size); + if (ret) { + dev_err(&client->dev, "%s: failed to copy OTP data to user\n", + __func__); + return -EFAULT; + } +out: + /* Return correct size */ + priv->size = dev->otp_driver->size; + + return 0; +} + +static int __imx_init(struct v4l2_subdev *sd, u32 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + int lanes = imx_get_lanes(sd); + int ret; + + if (dev->sensor_id == IMX_ID_DEFAULT) + return 0; + + /* The default is no flip at sensor initialization */ + dev->h_flip->cur.val = 0; + dev->v_flip->cur.val = 0; + /* Sets the default FPS */ + dev->fps_index = 0; + dev->curr_res_table = dev->mode_tables->res_preview; + dev->entries_curr_table = dev->mode_tables->n_res_preview; + + ret = imx_write_reg_array(client, dev->mode_tables->init_settings); + if (ret) + return ret; + + if (dev->sensor_id == IMX132_ID && lanes > 0) { + static const u8 imx132_rglanesel[] = { + IMX132_RGLANESEL_1LANE, /* 1 lane */ + IMX132_RGLANESEL_2LANES, /* 2 lanes */ + IMX132_RGLANESEL_1LANE, /* undefined */ + IMX132_RGLANESEL_4LANES, /* 4 lanes */ + }; + ret = imx_write_reg(client, IMX_8BIT, + IMX132_RGLANESEL, imx132_rglanesel[lanes - 1]); + } + + return ret; +} + +static int imx_init(struct v4l2_subdev *sd, u32 val) +{ + struct imx_device *dev = to_imx_sensor(sd); + int ret = 0; + + mutex_lock(&dev->input_lock); + ret = __imx_init(sd, val); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static long imx_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return imx_s_exposure(sd, arg); + case ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA: + return imx_g_priv_int_data(sd, arg); + default: + return -EINVAL; + } + return 0; +} + +static int power_up(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + int ret; + + /* power control */ + ret = dev->platform_data->power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* flis clock control */ + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + + /* gpio ctrl */ + ret = dev->platform_data->gpio_ctrl(sd, 1); + if (ret) { + dev_err(&client->dev, "gpio failed\n"); + goto fail_gpio; + } + + return 0; +fail_gpio: + dev->platform_data->gpio_ctrl(sd, 0); +fail_clk: + dev->platform_data->flisclk_ctrl(sd, 0); +fail_power: + dev->platform_data->power_ctrl(sd, 0); + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* gpio ctrl */ + ret = dev->platform_data->gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed\n"); + + /* power control */ + ret = dev->platform_data->power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "vprog failed.\n"); + + return ret; +} + +static int __imx_s_power(struct v4l2_subdev *sd, int on) +{ + struct imx_device *dev = to_imx_sensor(sd); + int ret = 0; + int r = 0; + + if (on == 0) { + ret = power_down(sd); + if (dev->vcm_driver && dev->vcm_driver->power_down) + r = dev->vcm_driver->power_down(sd); + if (ret == 0) + ret = r; + dev->power = 0; + } else { + if (dev->vcm_driver && dev->vcm_driver->power_up) + ret = dev->vcm_driver->power_up(sd); + if (ret) + return ret; + ret = power_up(sd); + if (!ret) { + dev->power = 1; + return __imx_init(sd, 0); + } + } + + return ret; +} + +static int imx_s_power(struct v4l2_subdev *sd, int on) +{ + int ret; + struct imx_device *dev = to_imx_sensor(sd); + + mutex_lock(&dev->input_lock); + ret = __imx_s_power(sd, on); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static int imx_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct imx_reg *reglist) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx_device *dev = to_imx_sensor(sd); + int lanes = imx_get_lanes(sd); + u32 vt_pix_clk_div; + u32 vt_sys_clk_div; + u32 pre_pll_clk_div; + u32 pll_multiplier; + + const int ext_clk_freq_hz = 19200000; + struct atomisp_sensor_mode_data *buf = &info->data; + int ret; + u16 data[IMX_INTG_BUF_COUNT]; + + u32 vt_pix_clk_freq_mhz; + u32 coarse_integration_time_min; + u32 coarse_integration_time_max_margin; + u32 read_mode; + u32 div; + + if (info == NULL) + return -EINVAL; + + memset(data, 0, IMX_INTG_BUF_COUNT * sizeof(u16)); + ret = imx_read_reg(client, 1, IMX_VT_PIX_CLK_DIV, data); + if (ret) + return ret; + vt_pix_clk_div = data[0] & IMX_MASK_5BIT; + + if (dev->sensor_id == IMX132_ID || dev->sensor_id == IMX208_ID) { + static const int rgpltd[] = { 2, 4, 1, 1 }; + ret = imx_read_reg(client, 1, IMX132_208_VT_RGPLTD, data); + if (ret) + return ret; + vt_sys_clk_div = rgpltd[data[0] & IMX_MASK_2BIT]; + } else { + ret = imx_read_reg(client, 1, IMX_VT_SYS_CLK_DIV, data); + if (ret) + return ret; + vt_sys_clk_div = data[0] & IMX_MASK_2BIT; + } + ret = imx_read_reg(client, 1, IMX_PRE_PLL_CLK_DIV, data); + if (ret) + return ret; + pre_pll_clk_div = data[0] & IMX_MASK_4BIT; + + ret = imx_read_reg(client, 2, + (dev->sensor_id == IMX132_ID || + dev->sensor_id == IMX219_ID || + dev->sensor_id == IMX208_ID) ? + IMX132_208_219_PLL_MULTIPLIER : IMX_PLL_MULTIPLIER, data); + if (ret) + return ret; + pll_multiplier = data[0] & IMX_MASK_11BIT; + + memset(data, 0, IMX_INTG_BUF_COUNT * sizeof(u16)); + ret = imx_read_reg(client, 4, IMX_COARSE_INTG_TIME_MIN, data); + if (ret) + return ret; + coarse_integration_time_min = data[0]; + coarse_integration_time_max_margin = data[1]; + + /* Get the cropping and output resolution to ISP for this mode. */ + ret = imx_read_reg(client, 2, dev->reg_addr->horizontal_start_h, data); + if (ret) + return ret; + buf->crop_horizontal_start = data[0]; + + ret = imx_read_reg(client, 2, dev->reg_addr->vertical_start_h, data); + if (ret) + return ret; + buf->crop_vertical_start = data[0]; + + ret = imx_read_reg(client, 2, dev->reg_addr->horizontal_end_h, data); + if (ret) + return ret; + buf->crop_horizontal_end = data[0]; + + ret = imx_read_reg(client, 2, dev->reg_addr->vertical_end_h, data); + if (ret) + return ret; + buf->crop_vertical_end = data[0]; + + ret = imx_read_reg(client, 2, + dev->reg_addr->horizontal_output_size_h, data); + if (ret) + return ret; + buf->output_width = data[0]; + + ret = imx_read_reg(client, 2, + dev->reg_addr->vertical_output_size_h, data); + if (ret) + return ret; + buf->output_height = data[0]; + + memset(data, 0, IMX_INTG_BUF_COUNT * sizeof(u16)); + if (dev->sensor_id == IMX132_ID || dev->sensor_id == IMX208_ID || + dev->sensor_id == IMX219_ID) + read_mode = 0; + else { + if (dev->sensor_id == IMX227_ID) + ret = imx_read_reg(client, 1, IMX227_READ_MODE, data); + else + ret = imx_read_reg(client, 1, IMX_READ_MODE, data); + + if (ret) + return ret; + read_mode = data[0] & IMX_MASK_2BIT; + } + + div = pre_pll_clk_div*vt_sys_clk_div*vt_pix_clk_div; + if (div == 0) + return -EINVAL; + + if (dev->sensor_id == IMX132_ID || dev->sensor_id == IMX208_ID) + vt_pix_clk_freq_mhz = ext_clk_freq_hz / div; + else if (dev->sensor_id == IMX227_ID) + /* according to IMX227 datasheet: + * vt_pix_freq_mhz = * num_of_vt_lanes(4) * ivt_pix_clk_freq_mhz + */ + vt_pix_clk_freq_mhz = + (u64)4 * ext_clk_freq_hz * pll_multiplier / div; + else + vt_pix_clk_freq_mhz = 2 * ext_clk_freq_hz / div; + + vt_pix_clk_freq_mhz *= pll_multiplier; + if (dev->sensor_id == IMX132_ID && lanes > 0) + vt_pix_clk_freq_mhz *= lanes; + + dev->vt_pix_clk_freq_mhz = vt_pix_clk_freq_mhz; + + buf->vt_pix_clk_freq_mhz = vt_pix_clk_freq_mhz; + buf->coarse_integration_time_min = coarse_integration_time_min; + buf->coarse_integration_time_max_margin = + coarse_integration_time_max_margin; + + buf->fine_integration_time_min = IMX_FINE_INTG_TIME; + buf->fine_integration_time_max_margin = IMX_FINE_INTG_TIME; + buf->fine_integration_time_def = IMX_FINE_INTG_TIME; + buf->frame_length_lines = dev->lines_per_frame; + buf->line_length_pck = dev->pixels_per_line; + buf->read_mode = read_mode; + + if (dev->sensor_id == IMX132_ID || dev->sensor_id == IMX208_ID || + dev->sensor_id == IMX219_ID) { + buf->binning_factor_x = 1; + buf->binning_factor_y = 1; + } else { + if (dev->sensor_id == IMX227_ID) + ret = imx_read_reg(client, 1, IMX227_BINNING_ENABLE, + data); + else + ret = imx_read_reg(client, 1, IMX_BINNING_ENABLE, data); + + if (ret) + return ret; + /* 1:binning enabled, 0:disabled */ + if (data[0] == 1) { + if (dev->sensor_id == IMX227_ID) + ret = imx_read_reg(client, 1, + IMX227_BINNING_TYPE, data); + else + ret = imx_read_reg(client, 1, + IMX_BINNING_TYPE, data); + + if (ret) + return ret; + buf->binning_factor_x = data[0] >> 4 & 0x0f; + if (!buf->binning_factor_x) + buf->binning_factor_x = 1; + buf->binning_factor_y = data[0] & 0xf; + if (!buf->binning_factor_y) + buf->binning_factor_y = 1; + /* WOWRKAROUND, NHD setting for IMX227 should have 4x4 + * binning but the register setting does not reflect + * this, I am asking vendor why this happens. this is + * workaround for INTEL BZ 216560. + */ + if (dev->sensor_id == IMX227_ID) { + if (dev->curr_res_table[dev->fmt_idx].width == + 376 && + dev->curr_res_table[dev->fmt_idx].height == + 656) { + buf->binning_factor_x = 4; + buf->binning_factor_y = 4; + } + } + } else { + buf->binning_factor_x = 1; + buf->binning_factor_y = 1; + } + } + + return 0; +} + +/* This returns the exposure time being used. This should only be used + for filling in EXIF data, not for actual image processing. */ +static int imx_q_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + u16 coarse; + int ret; + + /* the fine integration time is currently not calculated */ + ret = imx_read_reg(client, IMX_16BIT, + dev->reg_addr->coarse_integration_time, &coarse); + *value = coarse; + + return ret; +} + +static int imx_test_pattern(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + int ret; + + if (dev->power == 0) + return 0; + + ret = imx_write_reg(client, IMX_16BIT, IMX_TEST_PATTERN_COLOR_R, + (u16)(dev->tp_r->val >> 22)); + if (ret) + return ret; + + ret = imx_write_reg(client, IMX_16BIT, IMX_TEST_PATTERN_COLOR_GR, + (u16)(dev->tp_gr->val >> 22)); + if (ret) + return ret; + + ret = imx_write_reg(client, IMX_16BIT, IMX_TEST_PATTERN_COLOR_GB, + (u16)(dev->tp_gb->val >> 22)); + if (ret) + return ret; + + ret = imx_write_reg(client, IMX_16BIT, IMX_TEST_PATTERN_COLOR_B, + (u16)(dev->tp_b->val >> 22)); + if (ret) + return ret; + + return imx_write_reg(client, IMX_16BIT, IMX_TEST_PATTERN_MODE, + (u16)(dev->tp_mode->val)); +} + +static u32 imx_translate_bayer_order(enum atomisp_bayer_order code) +{ + switch (code) { + case atomisp_bayer_order_rggb: + return MEDIA_BUS_FMT_SRGGB10_1X10; + case atomisp_bayer_order_grbg: + return MEDIA_BUS_FMT_SGRBG10_1X10; + case atomisp_bayer_order_bggr: + return MEDIA_BUS_FMT_SBGGR10_1X10; + case atomisp_bayer_order_gbrg: + return MEDIA_BUS_FMT_SGBRG10_1X10; + } + return 0; +} + +static int imx_v_flip(struct v4l2_subdev *sd, s32 value) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct camera_mipi_info *imx_info = NULL; + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u16 val; + + if (dev->power == 0) + return -EIO; + + ret = imx_write_reg_array(client, dev->param_hold); + if (ret) + return ret; + + ret = imx_read_reg(client, IMX_8BIT, + dev->reg_addr->img_orientation, &val); + if (ret) + return ret; + if (value) + val |= IMX_VFLIP_BIT; + else + val &= ~IMX_VFLIP_BIT; + + ret = imx_write_reg(client, IMX_8BIT, + dev->reg_addr->img_orientation, val); + if (ret) + return ret; + + imx_info = v4l2_get_subdev_hostdata(sd); + if (imx_info) { + val &= (IMX_VFLIP_BIT|IMX_HFLIP_BIT); + imx_info->raw_bayer_order = imx_bayer_order_mapping[val]; + dev->format.code = imx_translate_bayer_order( + imx_info->raw_bayer_order); + } + + return imx_write_reg_array(client, dev->param_update); +} + +static int imx_h_flip(struct v4l2_subdev *sd, s32 value) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct camera_mipi_info *imx_info = NULL; + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u16 val; + + if (dev->power == 0) + return -EIO; + + ret = imx_write_reg_array(client, dev->param_hold); + if (ret) + return ret; + ret = imx_read_reg(client, IMX_8BIT, + dev->reg_addr->img_orientation, &val); + if (ret) + return ret; + if (value) + val |= IMX_HFLIP_BIT; + else + val &= ~IMX_HFLIP_BIT; + ret = imx_write_reg(client, IMX_8BIT, + dev->reg_addr->img_orientation, val); + if (ret) + return ret; + + imx_info = v4l2_get_subdev_hostdata(sd); + if (imx_info) { + val &= (IMX_VFLIP_BIT|IMX_HFLIP_BIT); + imx_info->raw_bayer_order = imx_bayer_order_mapping[val]; + dev->format.code = imx_translate_bayer_order( + imx_info->raw_bayer_order); + } + + return imx_write_reg_array(client, dev->param_update); +} + +static int imx_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + *val = (IMX_FOCAL_LENGTH_NUM << 16) | IMX_FOCAL_LENGTH_DEM; + return 0; +} + +static int imx_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /*const f number for imx*/ + *val = (IMX_F_NUMBER_DEFAULT_NUM << 16) | IMX_F_NUMBER_DEM; + return 0; +} + +static int imx_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + *val = (IMX_F_NUMBER_DEFAULT_NUM << 24) | + (IMX_F_NUMBER_DEM << 16) | + (IMX_F_NUMBER_DEFAULT_NUM << 8) | IMX_F_NUMBER_DEM; + return 0; +} + +static int imx_g_bin_factor_x(struct v4l2_subdev *sd, s32 *val) +{ + struct imx_device *dev = to_imx_sensor(sd); + + *val = dev->curr_res_table[dev->fmt_idx].bin_factor_x; + + return 0; +} + +static int imx_g_bin_factor_y(struct v4l2_subdev *sd, s32 *val) +{ + struct imx_device *dev = to_imx_sensor(sd); + + *val = dev->curr_res_table[dev->fmt_idx].bin_factor_y; + + return 0; +} + +int imx_vcm_power_up(struct v4l2_subdev *sd) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->power_up) + return dev->vcm_driver->power_up(sd); + return 0; +} + +int imx_vcm_power_down(struct v4l2_subdev *sd) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->power_down) + return dev->vcm_driver->power_down(sd); + return 0; +} + +int imx_vcm_init(struct v4l2_subdev *sd) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->init) + return dev->vcm_driver->init(sd); + return 0; +} + +int imx_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->t_focus_vcm) + return dev->vcm_driver->t_focus_vcm(sd, val); + return 0; +} + +int imx_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->t_focus_abs) + return dev->vcm_driver->t_focus_abs(sd, value); + return 0; +} +int imx_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->t_focus_rel) + return dev->vcm_driver->t_focus_rel(sd, value); + return 0; +} + +int imx_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->q_focus_status) + return dev->vcm_driver->q_focus_status(sd, value); + return 0; +} + +int imx_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->q_focus_abs) + return dev->vcm_driver->q_focus_abs(sd, value); + return 0; +} + +int imx_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->t_vcm_slew) + return dev->vcm_driver->t_vcm_slew(sd, value); + return 0; +} + +int imx_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (dev->vcm_driver && dev->vcm_driver->t_vcm_timing) + return dev->vcm_driver->t_vcm_timing(sd, value); + return 0; +} + +static int imx_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct imx_device *dev = container_of( + ctrl->handler, struct imx_device, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_TEST_PATTERN: + ret = imx_test_pattern(&dev->sd); + break; + case V4L2_CID_VFLIP: + dev_dbg(&client->dev, "%s: CID_VFLIP:%d.\n", + __func__, ctrl->val); + ret = imx_v_flip(&dev->sd, ctrl->val); + break; + case V4L2_CID_HFLIP: + dev_dbg(&client->dev, "%s: CID_HFLIP:%d.\n", + __func__, ctrl->val); + ret = imx_h_flip(&dev->sd, ctrl->val); + break; + case V4L2_CID_FOCUS_ABSOLUTE: + ret = imx_t_focus_abs(&dev->sd, ctrl->val); + break; + case V4L2_CID_FOCUS_RELATIVE: + ret = imx_t_focus_rel(&dev->sd, ctrl->val); + break; + case V4L2_CID_VCM_SLEW: + ret = imx_t_vcm_slew(&dev->sd, ctrl->val); + break; + case V4L2_CID_VCM_TIMEING: + ret = imx_t_vcm_timing(&dev->sd, ctrl->val); + break; + } + + return ret; +} + +static int imx_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct imx_device *dev = container_of( + ctrl->handler, struct imx_device, ctrl_handler); + int ret = 0; + unsigned int val; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = imx_q_exposure(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCUS_ABSOLUTE: + ret = imx_q_focus_abs(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCUS_STATUS: + ret = imx_q_focus_status(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = imx_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = imx_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = imx_g_fnumber_range(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_HORZ: + ret = imx_g_bin_factor_x(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_VERT: + ret = imx_g_bin_factor_y(&dev->sd, &ctrl->val); + break; + case V4L2_CID_VBLANK: + ctrl->val = dev->lines_per_frame - + dev->curr_res_table[dev->fmt_idx].height; + break; + case V4L2_CID_HBLANK: + ctrl->val = dev->pixels_per_line - + dev->curr_res_table[dev->fmt_idx].width; + break; + case V4L2_CID_PIXEL_RATE: + ctrl->val = dev->vt_pix_clk_freq_mhz; + break; + case V4L2_CID_LINK_FREQ: + val = dev->curr_res_table[dev->fmt_idx]. + fps_options[dev->fps_index].mipi_freq; + if (val == 0) + val = dev->curr_res_table[dev->fmt_idx].mipi_freq; + if (val == 0) + return -EINVAL; + ctrl->val = val * 1000; /* To Hz */ + break; + default: + return -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = imx_s_ctrl, + .g_volatile_ctrl = imx_g_volatile_ctrl +}; + +static const struct v4l2_ctrl_config imx_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .min = 0x0, + .max = 0xffff, + .step = 0x01, + .def = 0x00, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_TEST_PATTERN, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test pattern", + .min = 0, + .max = 0xffff, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_TEST_PATTERN_COLOR_R, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test pattern solid color R", + .min = INT_MIN, + .max = INT_MAX, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_TEST_PATTERN_COLOR_GR, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test pattern solid color GR", + .min = INT_MIN, + .max = INT_MAX, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_TEST_PATTERN_COLOR_GB, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test pattern solid color GB", + .min = INT_MIN, + .max = INT_MAX, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_TEST_PATTERN_COLOR_B, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test pattern solid color B", + .min = INT_MIN, + .max = INT_MAX, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Flip", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_HFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Mirror", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focus move absolute", + .min = 0, + .max = IMX_MAX_FOCUS_POS, + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_RELATIVE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focus move relative", + .min = IMX_MAX_FOCUS_NEG, + .max = IMX_MAX_FOCUS_POS, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_STATUS, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focus status", + .min = 0, + .max = 100, /* allow enum to grow in the future */ + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VCM_SLEW, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vcm slew", + .min = 0, + .max = IMX_VCM_SLEW_STEP_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VCM_TIMEING, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vcm step time", + .min = 0, + .max = IMX_VCM_SLEW_TIME_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focal length", + .min = IMX_FOCAL_LENGTH_DEFAULT, + .max = IMX_FOCAL_LENGTH_DEFAULT, + .step = 0x01, + .def = IMX_FOCAL_LENGTH_DEFAULT, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number", + .min = IMX_F_NUMBER_DEFAULT, + .max = IMX_F_NUMBER_DEFAULT, + .step = 0x01, + .def = IMX_F_NUMBER_DEFAULT, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number range", + .min = IMX_F_NUMBER_RANGE, + .max = IMX_F_NUMBER_RANGE, + .step = 0x01, + .def = IMX_F_NUMBER_RANGE, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_HORZ, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "horizontal binning factor", + .min = 0, + .max = IMX_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_VERT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vertical binning factor", + .min = 0, + .max = IMX_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_LINK_FREQ, + .name = "Link Frequency", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 1, + .max = 1500000 * 1000, + .step = 1, + .def = 1, + .flags = V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_PIXEL_RATE, + .name = "Pixel Rate", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = INT_MAX, + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_HBLANK, + .name = "Horizontal Blanking", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = SHRT_MAX, + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VBLANK, + .name = "Vertical Blanking", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = SHRT_MAX, + .step = 1, + .def = 0, + .flags = V4L2_CTRL_FLAG_VOLATILE, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_HFLIP, + .name = "Horizontal Flip", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = 1, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VFLIP, + .name = "Vertical Flip", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = 1, + .step = 1, + .def = 0, + .flags = 0, + }, +}; + +/* + * distance - calculate the distance + * @res: resolution + * @w: width + * @h: height + * + * Get the gap between resolution and w/h. + * res->width/height smaller than w/h wouldn't be considered. + * Returns the value of gap or -1 if fail. + */ +#define LARGEST_ALLOWED_RATIO_MISMATCH 600 +static int distance(struct imx_resolution const *res, u32 w, u32 h, + bool keep_ratio) +{ + unsigned int w_ratio; + unsigned int h_ratio; + int match; + unsigned int allowed_ratio_mismatch = LARGEST_ALLOWED_RATIO_MISMATCH; + + if (!keep_ratio) + allowed_ratio_mismatch = ~0; + + if (w == 0) + return -1; + w_ratio = (res->width << 13) / w; + if (h == 0) + return -1; + h_ratio = (res->height << 13) / h; + if (h_ratio == 0) + return -1; + match = abs(((w_ratio << 13) / h_ratio) - ((int)8192)); + + if ((w_ratio < (int)8192) || (h_ratio < (int)8192) || + (match > allowed_ratio_mismatch)) + return -1; + + return w_ratio + h_ratio; +} + +/* Return the nearest higher resolution index */ +static int nearest_resolution_index(struct v4l2_subdev *sd, int w, int h) +{ + int i; + int idx = -1; + int dist; + int fps_diff; + int min_fps_diff = INT_MAX; + int min_dist = INT_MAX; + const struct imx_resolution *tmp_res = NULL; + struct imx_device *dev = to_imx_sensor(sd); + bool again = 1; +retry: + for (i = 0; i < dev->entries_curr_table; i++) { + tmp_res = &dev->curr_res_table[i]; + dist = distance(tmp_res, w, h, again); + if (dist == -1) + continue; + if (dist < min_dist) { + min_dist = dist; + idx = i; + } + if (dist == min_dist) { + fps_diff = __imx_min_fps_diff(dev->targetfps, + tmp_res->fps_options); + if (fps_diff < min_fps_diff) { + min_fps_diff = fps_diff; + idx = i; + } + } + } + + /* + * FIXME! + * only IMX135 for Saltbay and IMX227 use this algorithm + */ + if (idx == -1 && again == true && dev->new_res_sel_method) { + again = false; + goto retry; + } + return idx; +} + +/* Call with ctrl_handler.lock hold */ +static int __adjust_hvblank(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + u16 new_frame_length_lines, new_line_length_pck; + int ret; + + /* + * No need to adjust h/v blank if not set dbg value + * Note that there is no other checking on the h/v blank value, + * as h/v blank can be set to any value above zero for debug purpose + */ + if (!dev->v_blank->val || !dev->h_blank->val) + return 0; + + new_frame_length_lines = dev->curr_res_table[dev->fmt_idx].height + + dev->v_blank->val; + new_line_length_pck = dev->curr_res_table[dev->fmt_idx].width + + dev->h_blank->val; + + ret = imx_write_reg(client, IMX_16BIT, + dev->reg_addr->line_length_pixels, new_line_length_pck); + if (ret) + return ret; + ret = imx_write_reg(client, IMX_16BIT, + dev->reg_addr->frame_length_lines, new_frame_length_lines); + if (ret) + return ret; + + dev->lines_per_frame = new_frame_length_lines; + dev->pixels_per_line = new_line_length_pck; + + return 0; +} + +static int imx_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct imx_device *dev = to_imx_sensor(sd); + struct camera_mipi_info *imx_info = NULL; + struct i2c_client *client = v4l2_get_subdevdata(sd); + const struct imx_resolution *res; + int lanes = imx_get_lanes(sd); + int ret; + u16 data, val; + int idx; + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + + imx_info = v4l2_get_subdev_hostdata(sd); + if (imx_info == NULL) + return -EINVAL; + if ((fmt->width > imx_max_res[dev->sensor_id].res_max_width) + || (fmt->height > imx_max_res[dev->sensor_id].res_max_height)) { + fmt->width = imx_max_res[dev->sensor_id].res_max_width; + fmt->height = imx_max_res[dev->sensor_id].res_max_height; + } else { + idx = nearest_resolution_index(sd, fmt->width, fmt->height); + + /* + * nearest_resolution_index() doesn't return smaller + * resolutions. If it fails, it means the requested + * resolution is higher than wecan support. Fallback + * to highest possible resolution in this case. + */ + if (idx == -1) + idx = dev->entries_curr_table - 1; + + fmt->width = dev->curr_res_table[idx].width; + fmt->height = dev->curr_res_table[idx].height; + } + + fmt->code = dev->format.code; + if(format->which == V4L2_SUBDEV_FORMAT_TRY) { + cfg->try_fmt = *fmt; + return 0; + } + mutex_lock(&dev->input_lock); + + dev->fmt_idx = nearest_resolution_index(sd, fmt->width, fmt->height); + if (dev->fmt_idx == -1) { + ret = -EINVAL; + goto out; + } + res = &dev->curr_res_table[dev->fmt_idx]; + + /* Adjust the FPS selection based on the resolution selected */ + dev->fps_index = __imx_nearest_fps_index(dev->targetfps, + res->fps_options); + dev->fps = res->fps_options[dev->fps_index].fps; + dev->regs = res->fps_options[dev->fps_index].regs; + if (!dev->regs) + dev->regs = res->regs; + + ret = imx_write_reg_array(client, dev->regs); + if (ret) + goto out; + + if (dev->sensor_id == IMX132_ID && lanes > 0) { + static const u8 imx132_rgpltd[] = { + 2, /* 1 lane: /1 */ + 0, /* 2 lanes: /2 */ + 0, /* undefined */ + 1, /* 4 lanes: /4 */ + }; + ret = imx_write_reg(client, IMX_8BIT, IMX132_208_VT_RGPLTD, + imx132_rgpltd[lanes - 1]); + if (ret) + goto out; + } + + dev->pixels_per_line = res->fps_options[dev->fps_index].pixels_per_line; + dev->lines_per_frame = res->fps_options[dev->fps_index].lines_per_frame; + + /* dbg h/v blank time */ + __adjust_hvblank(sd); + + ret = __imx_update_exposure_timing(client, dev->coarse_itg, + dev->pixels_per_line, dev->lines_per_frame); + if (ret) + goto out; + + ret = __imx_update_gain(sd, dev->gain); + if (ret) + goto out; + + ret = __imx_update_digital_gain(client, dev->digital_gain); + if (ret) + goto out; + + ret = imx_write_reg_array(client, dev->param_update); + if (ret) + goto out; + + ret = imx_get_intg_factor(client, imx_info, dev->regs); + if (ret) + goto out; + + ret = imx_read_reg(client, IMX_8BIT, + dev->reg_addr->img_orientation, &val); + if (ret) + goto out; + val &= (IMX_VFLIP_BIT|IMX_HFLIP_BIT); + imx_info->raw_bayer_order = imx_bayer_order_mapping[val]; + dev->format.code = imx_translate_bayer_order( + imx_info->raw_bayer_order); + + /* + * Fill meta data info. add imx135 metadata setting for RAW10 format + */ + switch (dev->sensor_id) { + case IMX135_ID: + ret = imx_read_reg(client, 2, + IMX135_OUTPUT_DATA_FORMAT_REG, &data); + if (ret) + goto out; + /* + * The IMX135 can support various resolutions like + * RAW6/8/10/12/14. + * 1.The data format is RAW10: + * matadata width = current resolution width(pixel) * 10 / 8 + * 2.The data format is RAW6 or RAW8: + * matadata width = current resolution width(pixel); + * 3.other data format(RAW12/14 etc): + * TBD. + */ + if (data == IMX135_OUTPUT_FORMAT_RAW10) + /* the data format is RAW10. */ + imx_info->metadata_width = res->width * 10 / 8; + else + /* The data format is RAW6/8/12/14/ etc. */ + imx_info->metadata_width = res->width; + + imx_info->metadata_height = IMX135_EMBEDDED_DATA_LINE_NUM; + + if (imx_info->metadata_effective_width == NULL) + imx_info->metadata_effective_width = + imx135_embedded_effective_size; + + break; + case IMX227_ID: + ret = imx_read_reg(client, 2, IMX227_OUTPUT_DATA_FORMAT_REG, + &data); + if (ret) + goto out; + if (data == IMX227_OUTPUT_FORMAT_RAW10) + /* the data format is RAW10. */ + imx_info->metadata_width = res->width * 10 / 8; + else + /* The data format is RAW6/8/12/14/ etc. */ + imx_info->metadata_width = res->width; + + imx_info->metadata_height = IMX227_EMBEDDED_DATA_LINE_NUM; + + if (imx_info->metadata_effective_width == NULL) + imx_info->metadata_effective_width = + imx227_embedded_effective_size; + + break; + default: + imx_info->metadata_width = 0; + imx_info->metadata_height = 0; + imx_info->metadata_effective_width = NULL; + break; + } + +out: + mutex_unlock(&dev->input_lock); + return ret; +} + + +static int imx_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct imx_device *dev = to_imx_sensor(sd); + + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + + mutex_lock(&dev->input_lock); + fmt->width = dev->curr_res_table[dev->fmt_idx].width; + fmt->height = dev->curr_res_table[dev->fmt_idx].height; + fmt->code = dev->format.code; + mutex_unlock(&dev->input_lock); + return 0; +} + +static int imx_detect(struct i2c_client *client, u16 *id, u8 *revision) +{ + struct i2c_adapter *adapter = client->adapter; + + /* i2c check */ + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + + /* check sensor chip ID */ + if (imx_read_reg(client, IMX_16BIT, IMX132_175_208_219_CHIP_ID, id)) { + v4l2_err(client, "sensor_id = 0x%x\n", *id); + return -ENODEV; + } + + if (*id == IMX132_ID || *id == IMX175_ID || + *id == IMX208_ID || *id == IMX219_ID) + goto found; + + if (imx_read_reg(client, IMX_16BIT, IMX134_135_227_CHIP_ID, id)) { + v4l2_err(client, "sensor_id = 0x%x\n", *id); + return -ENODEV; + } + if (*id != IMX134_ID && *id != IMX135_ID && *id != IMX227_ID) { + v4l2_err(client, "no imx sensor found\n"); + return -ENODEV; + } +found: + v4l2_info(client, "sensor_id = 0x%x\n", *id); + + /* TODO - need to be updated */ + *revision = 0; + + return 0; +} + +static void __imx_print_timing(struct v4l2_subdev *sd) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 width = dev->curr_res_table[dev->fmt_idx].width; + u16 height = dev->curr_res_table[dev->fmt_idx].height; + + dev_dbg(&client->dev, "Dump imx timing in stream on:\n"); + dev_dbg(&client->dev, "width: %d:\n", width); + dev_dbg(&client->dev, "height: %d:\n", height); + dev_dbg(&client->dev, "pixels_per_line: %d:\n", dev->pixels_per_line); + dev_dbg(&client->dev, "line per frame: %d:\n", dev->lines_per_frame); + dev_dbg(&client->dev, "pix freq: %d:\n", dev->vt_pix_clk_freq_mhz); + dev_dbg(&client->dev, "init fps: %d:\n", dev->vt_pix_clk_freq_mhz / + dev->pixels_per_line / dev->lines_per_frame); + dev_dbg(&client->dev, "HBlank: %d nS:\n", + 1000 * (dev->pixels_per_line - width) / + (dev->vt_pix_clk_freq_mhz / 1000000)); + dev_dbg(&client->dev, "VBlank: %d uS:\n", + (dev->lines_per_frame - height) * dev->pixels_per_line / + (dev->vt_pix_clk_freq_mhz / 1000000)); +} + +/* + * imx stream on/off + */ +static int imx_s_stream(struct v4l2_subdev *sd, int enable) +{ + int ret; + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct imx_device *dev = to_imx_sensor(sd); + + mutex_lock(&dev->input_lock); + if (enable) { + /* Noise reduction & dead pixel applied before streaming */ + if (dev->fw == NULL) { + dev_warn(&client->dev, "No MSR loaded from library"); + } else { + ret = apply_msr_data(client, dev->fw); + if (ret) { + mutex_unlock(&dev->input_lock); + return ret; + } + } + ret = imx_test_pattern(sd); + if (ret) { + v4l2_err(client, "Configure test pattern failed.\n"); + mutex_unlock(&dev->input_lock); + return ret; + } + __imx_print_timing(sd); + ret = imx_write_reg_array(client, imx_streaming); + if (ret != 0) { + v4l2_err(client, "write_reg_array err\n"); + mutex_unlock(&dev->input_lock); + return ret; + } + dev->streaming = 1; + if (dev->vcm_driver && dev->vcm_driver->t_focus_abs_init) + dev->vcm_driver->t_focus_abs_init(sd); + } else { + ret = imx_write_reg_array(client, imx_soft_standby); + if (ret != 0) { + v4l2_err(client, "write_reg_array err\n"); + mutex_unlock(&dev->input_lock); + return ret; + } + dev->streaming = 0; + dev->targetfps = 0; + } + mutex_unlock(&dev->input_lock); + + return 0; +} + +static int __update_imx_device_settings(struct imx_device *dev, u16 sensor_id) +{ + /* IMX on other platform is not supported yet */ + return -EINVAL; +} + +static int imx_s_config(struct v4l2_subdev *sd, + int irq, void *pdata) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + u8 sensor_revision; + u16 sensor_id; + int ret; + if (pdata == NULL) + return -ENODEV; + + dev->platform_data = pdata; + + mutex_lock(&dev->input_lock); + + if (dev->platform_data->platform_init) { + ret = dev->platform_data->platform_init(client); + if (ret) { + mutex_unlock(&dev->input_lock); + dev_err(&client->dev, "imx platform init err\n"); + return ret; + } + } + /* + * power off the module first. + * + * As first power on by board have undecided state of power/gpio pins. + */ + ret = __imx_s_power(sd, 0); + if (ret) { + v4l2_err(client, "imx power-down err.\n"); + mutex_unlock(&dev->input_lock); + return ret; + } + + ret = __imx_s_power(sd, 1); + if (ret) { + v4l2_err(client, "imx power-up err.\n"); + mutex_unlock(&dev->input_lock); + return ret; + } + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + /* config & detect sensor */ + ret = imx_detect(client, &sensor_id, &sensor_revision); + if (ret) { + v4l2_err(client, "imx_detect err s_config.\n"); + goto fail_detect; + } + + dev->sensor_id = sensor_id; + dev->sensor_revision = sensor_revision; + + /* Resolution settings depend on sensor type and platform */ + ret = __update_imx_device_settings(dev, dev->sensor_id); + if (ret) + goto fail_detect; + /* Read sensor's OTP data */ + dev->otp_data = dev->otp_driver->otp_read(sd, + dev->otp_driver->dev_addr, dev->otp_driver->start_addr, + dev->otp_driver->size); + + /* power off sensor */ + ret = __imx_s_power(sd, 0); + + mutex_unlock(&dev->input_lock); + if (ret) + v4l2_err(client, "imx power-down err.\n"); + + return ret; + +fail_detect: + dev->platform_data->csi_cfg(sd, 0); +fail_csi_cfg: + __imx_s_power(sd, 0); + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); + mutex_unlock(&dev->input_lock); + dev_err(&client->dev, "sensor power-gating failed\n"); + return ret; +} + +static int +imx_enum_mbus_code(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct imx_device *dev = to_imx_sensor(sd); + if (code->index >= MAX_FMTS) + return -EINVAL; + + mutex_lock(&dev->input_lock); + code->code = dev->format.code; + mutex_unlock(&dev->input_lock); + return 0; +} + +static int +imx_enum_frame_size(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + int index = fse->index; + struct imx_device *dev = to_imx_sensor(sd); + + mutex_lock(&dev->input_lock); + if (index >= dev->entries_curr_table) { + mutex_unlock(&dev->input_lock); + return -EINVAL; + } + + fse->min_width = dev->curr_res_table[index].width; + fse->min_height = dev->curr_res_table[index].height; + fse->max_width = dev->curr_res_table[index].width; + fse->max_height = dev->curr_res_table[index].height; + mutex_unlock(&dev->input_lock); + return 0; +} + +static int +imx_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *param) +{ + struct imx_device *dev = to_imx_sensor(sd); + + mutex_lock(&dev->input_lock); + dev->run_mode = param->parm.capture.capturemode; + + switch (dev->run_mode) { + case CI_MODE_VIDEO: + dev->curr_res_table = dev->mode_tables->res_video; + dev->entries_curr_table = dev->mode_tables->n_res_video; + break; + case CI_MODE_STILL_CAPTURE: + dev->curr_res_table = dev->mode_tables->res_still; + dev->entries_curr_table = dev->mode_tables->n_res_still; + break; + default: + dev->curr_res_table = dev->mode_tables->res_preview; + dev->entries_curr_table = dev->mode_tables->n_res_preview; + } + mutex_unlock(&dev->input_lock); + return 0; +} + +int +imx_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct imx_device *dev = to_imx_sensor(sd); + + mutex_lock(&dev->input_lock); + interval->interval.denominator = dev->fps; + interval->interval.numerator = 1; + mutex_unlock(&dev->input_lock); + return 0; +} + +static int __imx_s_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct imx_device *dev = to_imx_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + const struct imx_resolution *res = + &dev->curr_res_table[dev->fmt_idx]; + struct camera_mipi_info *imx_info = NULL; + unsigned short pixels_per_line; + unsigned short lines_per_frame; + unsigned int fps_index; + int fps; + int ret = 0; + + + imx_info = v4l2_get_subdev_hostdata(sd); + if (imx_info == NULL) + return -EINVAL; + + if (!interval->interval.numerator) + interval->interval.numerator = 1; + + fps = interval->interval.denominator / interval->interval.numerator; + + if (!fps) + return -EINVAL; + + dev->targetfps = fps; + /* No need to proceed further if we are not streaming */ + if (!dev->streaming) + return 0; + + /* Ignore if we are already using the required FPS. */ + if (fps == dev->fps) + return 0; + + /* + * Start here, sensor is already streaming, so adjust fps dynamically + */ + fps_index = __imx_above_nearest_fps_index(fps, res->fps_options); + if (fps > res->fps_options[fps_index].fps) { + /* + * if does not have high fps setting, not support increase fps + * by adjust lines per frame. + */ + dev_err(&client->dev, "Could not support fps: %d.\n", fps); + return -EINVAL; + } + + if (res->fps_options[fps_index].regs && + res->fps_options[fps_index].regs != dev->regs) { + /* + * if need a new setting, but the new setting has difference + * with current setting, not use this one, as may have + * unexpected result, e.g. PLL, IQ. + */ + dev_dbg(&client->dev, + "Sensor is streaming, not apply new sensor setting\n"); + if (fps > res->fps_options[dev->fps_index].fps) { + /* + * Does not support increase fps based on low fps + * setting, as the high fps setting could not be used, + * and fps requested is above current setting fps. + */ + dev_warn(&client->dev, + "Could not support fps: %d, keep current: %d.\n", + fps, dev->fps); + return 0; + } + } else { + dev->fps_index = fps_index; + dev->fps = res->fps_options[dev->fps_index].fps; + } + + /* Update the new frametimings based on FPS */ + pixels_per_line = res->fps_options[dev->fps_index].pixels_per_line; + lines_per_frame = res->fps_options[dev->fps_index].lines_per_frame; + + if (fps > res->fps_options[fps_index].fps) { + /* + * if does not have high fps setting, not support increase fps + * by adjust lines per frame. + */ + dev_warn(&client->dev, "Could not support fps: %d. Use:%d.\n", + fps, res->fps_options[fps_index].fps); + goto done; + } + + /* if the new setting does not match exactly */ + if (dev->fps != fps) { +#define MAX_LINES_PER_FRAME 0xffff + dev_dbg(&client->dev, "adjusting fps using lines_per_frame\n"); + /* + * FIXME! + * 1: check DS on max value of lines_per_frame + * 2: consider use pixel per line for more range? + */ + if (dev->lines_per_frame * dev->fps / fps > + MAX_LINES_PER_FRAME) { + dev_warn(&client->dev, + "adjust lines_per_frame out of range, try to use max value.\n"); + lines_per_frame = MAX_LINES_PER_FRAME; + } else { + lines_per_frame = lines_per_frame * dev->fps / fps; + } + } +done: + /* Update the new frametimings based on FPS */ + dev->pixels_per_line = pixels_per_line; + dev->lines_per_frame = lines_per_frame; + + /* Update the new values so that user side knows the current settings */ + ret = __imx_update_exposure_timing(client, + dev->coarse_itg, dev->pixels_per_line, dev->lines_per_frame); + if (ret) + return ret; + + dev->fps = fps; + + ret = imx_get_intg_factor(client, imx_info, dev->regs); + if (ret) + return ret; + + interval->interval.denominator = res->fps_options[dev->fps_index].fps; + interval->interval.numerator = 1; + __imx_print_timing(sd); + + return ret; +} + +static int imx_s_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct imx_device *dev = to_imx_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __imx_s_frame_interval(sd, interval); + mutex_unlock(&dev->input_lock); + + return ret; +} +static int imx_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + struct imx_device *dev = to_imx_sensor(sd); + + mutex_lock(&dev->input_lock); + *frames = dev->curr_res_table[dev->fmt_idx].skip_frames; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static const struct v4l2_subdev_sensor_ops imx_sensor_ops = { + .g_skip_frames = imx_g_skip_frames, +}; + +static const struct v4l2_subdev_video_ops imx_video_ops = { + .s_stream = imx_s_stream, + .s_parm = imx_s_parm, + .g_frame_interval = imx_g_frame_interval, + .s_frame_interval = imx_s_frame_interval, +}; + +static const struct v4l2_subdev_core_ops imx_core_ops = { + .s_power = imx_s_power, + .ioctl = imx_ioctl, + .init = imx_init, +}; + +static const struct v4l2_subdev_pad_ops imx_pad_ops = { + .enum_mbus_code = imx_enum_mbus_code, + .enum_frame_size = imx_enum_frame_size, + .get_fmt = imx_get_fmt, + .set_fmt = imx_set_fmt, +}; + +static const struct v4l2_subdev_ops imx_ops = { + .core = &imx_core_ops, + .video = &imx_video_ops, + .pad = &imx_pad_ops, + .sensor = &imx_sensor_ops, +}; + +static const struct media_entity_operations imx_entity_ops = { + .link_setup = NULL, +}; + +static int imx_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct imx_device *dev = to_imx_sensor(sd); + + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); + + media_entity_cleanup(&dev->sd.entity); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + dev->platform_data->csi_cfg(sd, 0); + v4l2_device_unregister_subdev(sd); + release_msr_list(client, dev->fw); + kfree(dev); + + return 0; +} + +static int __imx_init_ctrl_handler(struct imx_device *dev) +{ + struct v4l2_ctrl_handler *hdl; + int i; + + hdl = &dev->ctrl_handler; + + v4l2_ctrl_handler_init(&dev->ctrl_handler, ARRAY_SIZE(imx_controls)); + + for (i = 0; i < ARRAY_SIZE(imx_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, + &imx_controls[i], NULL); + + dev->pixel_rate = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_PIXEL_RATE); + dev->h_blank = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_HBLANK); + dev->v_blank = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_VBLANK); + dev->link_freq = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_LINK_FREQ); + dev->h_flip = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_HFLIP); + dev->v_flip = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_VFLIP); + dev->tp_mode = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_TEST_PATTERN); + dev->tp_r = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_TEST_PATTERN_COLOR_R); + dev->tp_gr = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_TEST_PATTERN_COLOR_GR); + dev->tp_gb = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_TEST_PATTERN_COLOR_GB); + dev->tp_b = v4l2_ctrl_find(&dev->ctrl_handler, + V4L2_CID_TEST_PATTERN_COLOR_B); + + if (dev->ctrl_handler.error || dev->pixel_rate == NULL + || dev->h_blank == NULL || dev->v_blank == NULL + || dev->h_flip == NULL || dev->v_flip == NULL + || dev->link_freq == NULL) { + return dev->ctrl_handler.error; + } + + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = hdl; + v4l2_ctrl_handler_setup(&dev->ctrl_handler); + + return 0; +} + +static void imx_update_reg_info(struct imx_device *dev) +{ + if (dev->sensor_id == IMX219_ID) { + dev->reg_addr = &imx219_addr; + dev->param_hold = imx219_param_hold; + dev->param_update = imx219_param_update; + } else { + dev->reg_addr = &imx_addr; + dev->param_hold = imx_param_hold; + dev->param_update = imx_param_update; + } +} + +static int imx_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct imx_device *dev; + struct camera_mipi_info *imx_info = NULL; + int ret; + char *msr_file_name = NULL; + + /* allocate sensor device & init sub device */ + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) { + v4l2_err(client, "%s: out of memory\n", __func__); + return -ENOMEM; + } + + mutex_init(&dev->input_lock); + + dev->i2c_id = id->driver_data; + dev->fmt_idx = 0; + dev->sensor_id = IMX_ID_DEFAULT; + dev->vcm_driver = &imx_vcms[IMX_ID_DEFAULT]; + dev->digital_gain = 256; + + v4l2_i2c_subdev_init(&(dev->sd), client, &imx_ops); + + if (client->dev.platform_data) { + ret = imx_s_config(&dev->sd, client->irq, + client->dev.platform_data); + if (ret) + goto out_free; + } + imx_info = v4l2_get_subdev_hostdata(&dev->sd); + + /* + * sd->name is updated with sensor driver name by the v4l2. + * change it to sensor name in this case. + */ + imx_update_reg_info(dev); + snprintf(dev->sd.name, sizeof(dev->sd.name), "%s%x %d-%04x", + IMX_SUBDEV_PREFIX, dev->sensor_id, + i2c_adapter_id(client->adapter), client->addr); + + ret = __imx_init_ctrl_handler(dev); + if (ret) + goto out_ctrl_handler_free; + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = imx_translate_bayer_order( + imx_info->raw_bayer_order); + dev->sd.entity.ops = &imx_entity_ops; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) { + imx_remove(client); + return ret; + } + + /* Load the Noise reduction, Dead pixel registers from cpf file*/ + if (dev->platform_data->msr_file_name != NULL) + msr_file_name = dev->platform_data->msr_file_name(); + if (msr_file_name) { + ret = load_msr_list(client, msr_file_name, &dev->fw); + if (ret) { + imx_remove(client); + return ret; + } + } else { + dev_warn(&client->dev, "Drvb file not present"); + } + + return ret; + +out_ctrl_handler_free: + v4l2_ctrl_handler_free(&dev->ctrl_handler); + +out_free: + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + return ret; +} + +static const struct i2c_device_id imx_ids[] = { + {IMX_NAME_175, IMX175_ID}, + {IMX_NAME_135, IMX135_ID}, + {IMX_NAME_135_FUJI, IMX135_FUJI_ID}, + {IMX_NAME_134, IMX134_ID}, + {IMX_NAME_132, IMX132_ID}, + {IMX_NAME_208, IMX208_ID}, + {IMX_NAME_219, IMX219_ID}, + {IMX_NAME_227, IMX227_ID}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, imx_ids); + +static struct i2c_driver imx_driver = { + .driver = { + .owner = THIS_MODULE, + .name = IMX_DRIVER, + }, + .probe = imx_probe, + .remove = imx_remove, + .id_table = imx_ids, +}; + +static __init int init_imx(void) +{ + return i2c_add_driver(&imx_driver); +} + +static __exit void exit_imx(void) +{ + i2c_del_driver(&imx_driver); +} + +module_init(init_imx); +module_exit(exit_imx); + +MODULE_DESCRIPTION("A low-level driver for Sony IMX sensors"); +MODULE_AUTHOR("Shenbo Huang "); +MODULE_LICENSE("GPL"); + diff --git a/drivers/staging/media/atomisp/i2c/imx/imx.h b/drivers/staging/media/atomisp/i2c/imx/imx.h new file mode 100644 index 0000000000000000000000000000000000000000..3b91887867d80e97a7bca1c6f61fd7f080e02a67 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx.h @@ -0,0 +1,766 @@ +/* + * Support for Sony IMX camera sensor. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __IMX_H__ +#define __IMX_H__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "imx175.h" +#include "imx135.h" +#include "imx134.h" +#include "imx132.h" +#include "imx208.h" +#include "imx219.h" +#include "imx227.h" + +#define IMX_MCLK 192 + +/* TODO - This should be added into include/linux/videodev2.h */ +#ifndef V4L2_IDENT_IMX +#define V4L2_IDENT_IMX 8245 +#endif + +#define IMX_MAX_AE_LUT_LENGTH 5 +/* + * imx System control registers + */ +#define IMX_MASK_5BIT 0x1F +#define IMX_MASK_4BIT 0xF +#define IMX_MASK_3BIT 0x7 +#define IMX_MASK_2BIT 0x3 +#define IMX_MASK_8BIT 0xFF +#define IMX_MASK_11BIT 0x7FF +#define IMX_INTG_BUF_COUNT 2 + +#define IMX_FINE_INTG_TIME 0x1E8 + +#define IMX_VT_PIX_CLK_DIV 0x0301 +#define IMX_VT_SYS_CLK_DIV 0x0303 +#define IMX_PRE_PLL_CLK_DIV 0x0305 +#define IMX227_IOP_PRE_PLL_CLK_DIV 0x030D +#define IMX227_PLL_MULTIPLIER 0x0306 +#define IMX227_IOP_PLL_MULTIPLIER 0x030E +#define IMX227_PLL_MULTI_DRIVE 0x0310 +#define IMX227_OP_PIX_CLK_DIV 0x0309 +#define IMX227_OP_SYS_CLK_DIV 0x030B +#define IMX_PLL_MULTIPLIER 0x030C +#define IMX_OP_PIX_DIV 0x0309 +#define IMX_OP_SYS_DIV 0x030B +#define IMX_FRAME_LENGTH_LINES 0x0340 +#define IMX_LINE_LENGTH_PIXELS 0x0342 +#define IMX_COARSE_INTG_TIME_MIN 0x1004 +#define IMX_COARSE_INTG_TIME_MAX 0x1006 +#define IMX_BINNING_ENABLE 0x0390 +#define IMX227_BINNING_ENABLE 0x0900 +#define IMX_BINNING_TYPE 0x0391 +#define IMX227_BINNING_TYPE 0x0901 +#define IMX_READ_MODE 0x0390 +#define IMX227_READ_MODE 0x0900 + +#define IMX_HORIZONTAL_START_H 0x0344 +#define IMX_VERTICAL_START_H 0x0346 +#define IMX_HORIZONTAL_END_H 0x0348 +#define IMX_VERTICAL_END_H 0x034a +#define IMX_HORIZONTAL_OUTPUT_SIZE_H 0x034c +#define IMX_VERTICAL_OUTPUT_SIZE_H 0x034e + +/* Post Divider setting register for imx132 and imx208 */ +#define IMX132_208_VT_RGPLTD 0x30A4 + +/* Multiplier setting register for imx132, imx208, and imx219 */ +#define IMX132_208_219_PLL_MULTIPLIER 0x0306 + +#define IMX_COARSE_INTEGRATION_TIME 0x0202 +#define IMX_TEST_PATTERN_MODE 0x0600 +#define IMX_TEST_PATTERN_COLOR_R 0x0602 +#define IMX_TEST_PATTERN_COLOR_GR 0x0604 +#define IMX_TEST_PATTERN_COLOR_B 0x0606 +#define IMX_TEST_PATTERN_COLOR_GB 0x0608 +#define IMX_IMG_ORIENTATION 0x0101 +#define IMX_VFLIP_BIT 2 +#define IMX_HFLIP_BIT 1 +#define IMX_GLOBAL_GAIN 0x0205 +#define IMX_SHORT_AGC_GAIN 0x0233 +#define IMX_DGC_ADJ 0x020E +#define IMX_DGC_LEN 10 +#define IMX227_DGC_LEN 4 +#define IMX_MAX_EXPOSURE_SUPPORTED 0xfffb +#define IMX_MAX_GLOBAL_GAIN_SUPPORTED 0x00ff +#define IMX_MAX_DIGITAL_GAIN_SUPPORTED 0x0fff + +#define MAX_FMTS 1 +#define IMX_OTP_DATA_SIZE 1280 + +#define IMX_SUBDEV_PREFIX "imx" +#define IMX_DRIVER "imx1x5" + +/* Sensor ids from identification register */ +#define IMX_NAME_134 "imx134" +#define IMX_NAME_135 "imx135" +#define IMX_NAME_175 "imx175" +#define IMX_NAME_132 "imx132" +#define IMX_NAME_208 "imx208" +#define IMX_NAME_219 "imx219" +#define IMX_NAME_227 "imx227" +#define IMX175_ID 0x0175 +#define IMX135_ID 0x0135 +#define IMX134_ID 0x0134 +#define IMX132_ID 0x0132 +#define IMX208_ID 0x0208 +#define IMX219_ID 0x0219 +#define IMX227_ID 0x0227 + +/* Sensor id based on i2c_device_id table + * (Fuji module can not be detected based on sensor registers) */ +#define IMX135_FUJI_ID 0x0136 +#define IMX_NAME_135_FUJI "imx135fuji" + +/* imx175 - use dw9714 vcm */ +#define IMX175_MERRFLD 0x175 +#define IMX175_VALLEYVIEW 0x176 +#define IMX135_SALTBAY 0x135 +#define IMX135_VICTORIABAY 0x136 +#define IMX132_SALTBAY 0x132 +#define IMX134_VALLEYVIEW 0x134 +#define IMX208_MOFD_PD2 0x208 +#define IMX219_MFV0_PRH 0x219 +#define IMX227_SAND 0x227 + +/* otp - specific settings */ +#define E2PROM_ADDR 0xa0 +#define E2PROM_LITEON_12P1BA869D_ADDR 0xa0 +#define E2PROM_ABICO_SS89A839_ADDR 0xa8 +#define DEFAULT_OTP_SIZE 1280 +#define IMX135_OTP_SIZE 1280 +#define IMX219_OTP_SIZE 2048 +#define IMX227_OTP_SIZE 2560 +#define E2PROM_LITEON_12P1BA869D_SIZE 544 + +#define IMX_ID_DEFAULT 0x0000 +#define IMX132_175_208_219_CHIP_ID 0x0000 +#define IMX134_135_CHIP_ID 0x0016 +#define IMX134_135_227_CHIP_ID 0x0016 + +#define IMX175_RES_WIDTH_MAX 3280 +#define IMX175_RES_HEIGHT_MAX 2464 +#define IMX135_RES_WIDTH_MAX 4208 +#define IMX135_RES_HEIGHT_MAX 3120 +#define IMX132_RES_WIDTH_MAX 1936 +#define IMX132_RES_HEIGHT_MAX 1096 +#define IMX134_RES_WIDTH_MAX 3280 +#define IMX134_RES_HEIGHT_MAX 2464 +#define IMX208_RES_WIDTH_MAX 1936 +#define IMX208_RES_HEIGHT_MAX 1096 +#define IMX219_RES_WIDTH_MAX 3280 +#define IMX219_RES_HEIGHT_MAX 2464 +#define IMX227_RES_WIDTH_MAX 2400 +#define IMX227_RES_HEIGHT_MAX 2720 + +/* Defines for lens/VCM */ +#define IMX_FOCAL_LENGTH_NUM 369 /*3.69mm*/ +#define IMX_FOCAL_LENGTH_DEM 100 +#define IMX_F_NUMBER_DEFAULT_NUM 22 +#define IMX_F_NUMBER_DEM 10 +#define IMX_INVALID_CONFIG 0xffffffff +#define IMX_MAX_FOCUS_POS 1023 +#define IMX_MAX_FOCUS_NEG (-1023) +#define IMX_VCM_SLEW_STEP_MAX 0x3f +#define IMX_VCM_SLEW_TIME_MAX 0x1f + +#define IMX_BIN_FACTOR_MAX 4 +#define IMX_INTEGRATION_TIME_MARGIN 4 +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define IMX_FOCAL_LENGTH_DEFAULT 0x1710064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define IMX_F_NUMBER_DEFAULT 0x16000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define IMX_F_NUMBER_RANGE 0x160a160a + +struct imx_vcm { + int (*power_up)(struct v4l2_subdev *sd); + int (*power_down)(struct v4l2_subdev *sd); + int (*init)(struct v4l2_subdev *sd); + int (*t_focus_vcm)(struct v4l2_subdev *sd, u16 val); + int (*t_focus_abs)(struct v4l2_subdev *sd, s32 value); + int (*t_focus_abs_init)(struct v4l2_subdev *sd); + int (*t_focus_rel)(struct v4l2_subdev *sd, s32 value); + int (*q_focus_status)(struct v4l2_subdev *sd, s32 *value); + int (*q_focus_abs)(struct v4l2_subdev *sd, s32 *value); + int (*t_vcm_slew)(struct v4l2_subdev *sd, s32 value); + int (*t_vcm_timing)(struct v4l2_subdev *sd, s32 value); +}; + +struct imx_otp { + void * (*otp_read)(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); + u32 start_addr; + u32 size; + u8 dev_addr; +}; + +struct max_res { + int res_max_width; + int res_max_height; +}; + +struct max_res imx_max_res[] = { + [IMX175_ID] = { + .res_max_width = IMX175_RES_WIDTH_MAX, + .res_max_height = IMX175_RES_HEIGHT_MAX, + }, + [IMX135_ID] = { + .res_max_width = IMX135_RES_WIDTH_MAX, + .res_max_height = IMX135_RES_HEIGHT_MAX, + }, + [IMX132_ID] = { + .res_max_width = IMX132_RES_WIDTH_MAX, + .res_max_height = IMX132_RES_HEIGHT_MAX, + }, + [IMX134_ID] = { + .res_max_width = IMX134_RES_WIDTH_MAX, + .res_max_height = IMX134_RES_HEIGHT_MAX, + }, + [IMX208_ID] = { + .res_max_width = IMX208_RES_WIDTH_MAX, + .res_max_height = IMX208_RES_HEIGHT_MAX, + }, + [IMX219_ID] = { + .res_max_width = IMX219_RES_WIDTH_MAX, + .res_max_height = IMX219_RES_HEIGHT_MAX, + }, + [IMX227_ID] = { + .res_max_width = IMX227_RES_WIDTH_MAX, + .res_max_height = IMX227_RES_HEIGHT_MAX, + }, +}; + +struct imx_settings { + struct imx_reg const *init_settings; + struct imx_resolution *res_preview; + struct imx_resolution *res_still; + struct imx_resolution *res_video; + int n_res_preview; + int n_res_still; + int n_res_video; +}; + +struct imx_settings imx_sets[] = { + [IMX175_MERRFLD] = { + .init_settings = imx175_init_settings, + .res_preview = imx175_res_preview, + .res_still = imx175_res_still, + .res_video = imx175_res_video, + .n_res_preview = ARRAY_SIZE(imx175_res_preview), + .n_res_still = ARRAY_SIZE(imx175_res_still), + .n_res_video = ARRAY_SIZE(imx175_res_video), + }, + [IMX175_VALLEYVIEW] = { + .init_settings = imx175_init_settings, + .res_preview = imx175_res_preview, + .res_still = imx175_res_still, + .res_video = imx175_res_video, + .n_res_preview = ARRAY_SIZE(imx175_res_preview), + .n_res_still = ARRAY_SIZE(imx175_res_still), + .n_res_video = ARRAY_SIZE(imx175_res_video), + }, + [IMX135_SALTBAY] = { + .init_settings = imx135_init_settings, + .res_preview = imx135_res_preview, + .res_still = imx135_res_still, + .res_video = imx135_res_video, + .n_res_preview = ARRAY_SIZE(imx135_res_preview), + .n_res_still = ARRAY_SIZE(imx135_res_still), + .n_res_video = ARRAY_SIZE(imx135_res_video), + }, + [IMX135_VICTORIABAY] = { + .init_settings = imx135_init_settings, + .res_preview = imx135_res_preview_mofd, + .res_still = imx135_res_still_mofd, + .res_video = imx135_res_video, + .n_res_preview = ARRAY_SIZE(imx135_res_preview_mofd), + .n_res_still = ARRAY_SIZE(imx135_res_still_mofd), + .n_res_video = ARRAY_SIZE(imx135_res_video), + }, + [IMX132_SALTBAY] = { + .init_settings = imx132_init_settings, + .res_preview = imx132_res_preview, + .res_still = imx132_res_still, + .res_video = imx132_res_video, + .n_res_preview = ARRAY_SIZE(imx132_res_preview), + .n_res_still = ARRAY_SIZE(imx132_res_still), + .n_res_video = ARRAY_SIZE(imx132_res_video), + }, + [IMX134_VALLEYVIEW] = { + .init_settings = imx134_init_settings, + .res_preview = imx134_res_preview, + .res_still = imx134_res_still, + .res_video = imx134_res_video, + .n_res_preview = ARRAY_SIZE(imx134_res_preview), + .n_res_still = ARRAY_SIZE(imx134_res_still), + .n_res_video = ARRAY_SIZE(imx134_res_video), + }, + [IMX208_MOFD_PD2] = { + .init_settings = imx208_init_settings, + .res_preview = imx208_res_preview, + .res_still = imx208_res_still, + .res_video = imx208_res_video, + .n_res_preview = ARRAY_SIZE(imx208_res_preview), + .n_res_still = ARRAY_SIZE(imx208_res_still), + .n_res_video = ARRAY_SIZE(imx208_res_video), + }, + [IMX219_MFV0_PRH] = { + .init_settings = imx219_init_settings, + .res_preview = imx219_res_preview, + .res_still = imx219_res_still, + .res_video = imx219_res_video, + .n_res_preview = ARRAY_SIZE(imx219_res_preview), + .n_res_still = ARRAY_SIZE(imx219_res_still), + .n_res_video = ARRAY_SIZE(imx219_res_video), + }, + [IMX227_SAND] = { + .init_settings = imx227_init_settings, + .res_preview = imx227_res_preview, + .res_still = imx227_res_still, + .res_video = imx227_res_video, + .n_res_preview = ARRAY_SIZE(imx227_res_preview), + .n_res_still = ARRAY_SIZE(imx227_res_still), + .n_res_video = ARRAY_SIZE(imx227_res_video), + }, +}; + +struct imx_reg_addr { + u16 frame_length_lines; + u16 line_length_pixels; + u16 horizontal_start_h; + u16 vertical_start_h; + u16 horizontal_end_h; + u16 vertical_end_h; + u16 horizontal_output_size_h; + u16 vertical_output_size_h; + u16 coarse_integration_time; + u16 img_orientation; + u16 global_gain; + u16 dgc_adj; +}; + +struct imx_reg_addr imx_addr = { + IMX_FRAME_LENGTH_LINES, + IMX_LINE_LENGTH_PIXELS, + IMX_HORIZONTAL_START_H, + IMX_VERTICAL_START_H, + IMX_HORIZONTAL_END_H, + IMX_VERTICAL_END_H, + IMX_HORIZONTAL_OUTPUT_SIZE_H, + IMX_VERTICAL_OUTPUT_SIZE_H, + IMX_COARSE_INTEGRATION_TIME, + IMX_IMG_ORIENTATION, + IMX_GLOBAL_GAIN, + IMX_DGC_ADJ, +}; + +struct imx_reg_addr imx219_addr = { + IMX219_FRAME_LENGTH_LINES, + IMX219_LINE_LENGTH_PIXELS, + IMX219_HORIZONTAL_START_H, + IMX219_VERTICAL_START_H, + IMX219_HORIZONTAL_END_H, + IMX219_VERTICAL_END_H, + IMX219_HORIZONTAL_OUTPUT_SIZE_H, + IMX219_VERTICAL_OUTPUT_SIZE_H, + IMX219_COARSE_INTEGRATION_TIME, + IMX219_IMG_ORIENTATION, + IMX219_GLOBAL_GAIN, + IMX219_DGC_ADJ, +}; + +#define v4l2_format_capture_type_entry(_width, _height, \ + _pixelformat, _bytesperline, _colorspace) \ + {\ + .type = V4L2_BUF_TYPE_VIDEO_CAPTURE,\ + .fmt.pix.width = (_width),\ + .fmt.pix.height = (_height),\ + .fmt.pix.pixelformat = (_pixelformat),\ + .fmt.pix.bytesperline = (_bytesperline),\ + .fmt.pix.colorspace = (_colorspace),\ + .fmt.pix.sizeimage = (_height)*(_bytesperline),\ + } + +#define s_output_format_entry(_width, _height, _pixelformat, \ + _bytesperline, _colorspace, _fps) \ + {\ + .v4l2_fmt = v4l2_format_capture_type_entry(_width, \ + _height, _pixelformat, _bytesperline, \ + _colorspace),\ + .fps = (_fps),\ + } + +#define s_output_format_reg_entry(_width, _height, _pixelformat, \ + _bytesperline, _colorspace, _fps, _reg_setting) \ + {\ + .s_fmt = s_output_format_entry(_width, _height,\ + _pixelformat, _bytesperline, \ + _colorspace, _fps),\ + .reg_setting = (_reg_setting),\ + } + +/* imx device structure */ +struct imx_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + struct camera_sensor_platform_data *platform_data; + struct mutex input_lock; /* serialize sensor's ioctl */ + int fmt_idx; + int status; + int streaming; + int power; + int run_mode; + int vt_pix_clk_freq_mhz; + int fps_index; + u32 focus; + u16 sensor_id; /* Sensor id from registers */ + u16 i2c_id; /* Sensor id from i2c_device_id */ + u16 coarse_itg; + u16 fine_itg; + u16 digital_gain; + u16 gain; + u16 pixels_per_line; + u16 lines_per_frame; + u8 targetfps; + u8 fps; + const struct imx_reg *regs; + u8 res; + u8 type; + u8 sensor_revision; + u8 *otp_data; + struct imx_settings *mode_tables; + struct imx_vcm *vcm_driver; + struct imx_otp *otp_driver; + const struct imx_resolution *curr_res_table; + int entries_curr_table; + const struct firmware *fw; + struct imx_reg_addr *reg_addr; + const struct imx_reg *param_hold; + const struct imx_reg *param_update; + + /* used for h/b blank tuning */ + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *pixel_rate; + struct v4l2_ctrl *h_blank; + struct v4l2_ctrl *v_blank; + struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *h_flip; + struct v4l2_ctrl *v_flip; + + /* Test pattern control */ + struct v4l2_ctrl *tp_mode; + struct v4l2_ctrl *tp_r; + struct v4l2_ctrl *tp_gr; + struct v4l2_ctrl *tp_gb; + struct v4l2_ctrl *tp_b; + + /* FIXME! */ + bool new_res_sel_method; +}; + +#define to_imx_sensor(x) container_of(x, struct imx_device, sd) + +#define IMX_MAX_WRITE_BUF_SIZE 32 +struct imx_write_buffer { + u16 addr; + u8 data[IMX_MAX_WRITE_BUF_SIZE]; +}; + +struct imx_write_ctrl { + int index; + struct imx_write_buffer buffer; +}; + +static const struct imx_reg imx_soft_standby[] = { + {IMX_8BIT, 0x0100, 0x00}, + {IMX_TOK_TERM, 0, 0} +}; + +static const struct imx_reg imx_streaming[] = { + {IMX_8BIT, 0x0100, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static const struct imx_reg imx_param_hold[] = { + {IMX_8BIT, 0x0104, 0x01}, /* GROUPED_PARAMETER_HOLD */ + {IMX_TOK_TERM, 0, 0} +}; + +static const struct imx_reg imx_param_update[] = { + {IMX_8BIT, 0x0104, 0x00}, /* GROUPED_PARAMETER_HOLD */ + {IMX_TOK_TERM, 0, 0} +}; + +static const struct imx_reg imx219_param_hold[] = { + {IMX_TOK_TERM, 0, 0} +}; + +static const struct imx_reg imx219_param_update[] = { + {IMX_TOK_TERM, 0, 0} +}; + +extern int ad5816g_vcm_power_up(struct v4l2_subdev *sd); +extern int ad5816g_vcm_power_down(struct v4l2_subdev *sd); +extern int ad5816g_vcm_init(struct v4l2_subdev *sd); + +extern int ad5816g_t_focus_vcm(struct v4l2_subdev *sd, u16 val); +extern int ad5816g_t_focus_abs(struct v4l2_subdev *sd, s32 value); +extern int ad5816g_t_focus_rel(struct v4l2_subdev *sd, s32 value); +extern int ad5816g_q_focus_status(struct v4l2_subdev *sd, s32 *value); +extern int ad5816g_q_focus_abs(struct v4l2_subdev *sd, s32 *value); +extern int ad5816g_t_vcm_slew(struct v4l2_subdev *sd, s32 value); +extern int ad5816g_t_vcm_timing(struct v4l2_subdev *sd, s32 value); + +extern int drv201_vcm_power_up(struct v4l2_subdev *sd); +extern int drv201_vcm_power_down(struct v4l2_subdev *sd); +extern int drv201_vcm_init(struct v4l2_subdev *sd); + +extern int drv201_t_focus_vcm(struct v4l2_subdev *sd, u16 val); +extern int drv201_t_focus_abs(struct v4l2_subdev *sd, s32 value); +extern int drv201_t_focus_rel(struct v4l2_subdev *sd, s32 value); +extern int drv201_q_focus_status(struct v4l2_subdev *sd, s32 *value); +extern int drv201_q_focus_abs(struct v4l2_subdev *sd, s32 *value); +extern int drv201_t_vcm_slew(struct v4l2_subdev *sd, s32 value); +extern int drv201_t_vcm_timing(struct v4l2_subdev *sd, s32 value); + +extern int dw9714_vcm_power_up(struct v4l2_subdev *sd); +extern int dw9714_vcm_power_down(struct v4l2_subdev *sd); +extern int dw9714_vcm_init(struct v4l2_subdev *sd); + +extern int dw9714_t_focus_vcm(struct v4l2_subdev *sd, u16 val); +extern int dw9714_t_focus_abs(struct v4l2_subdev *sd, s32 value); +extern int dw9714_t_focus_abs_init(struct v4l2_subdev *sd); +extern int dw9714_t_focus_rel(struct v4l2_subdev *sd, s32 value); +extern int dw9714_q_focus_status(struct v4l2_subdev *sd, s32 *value); +extern int dw9714_q_focus_abs(struct v4l2_subdev *sd, s32 *value); +extern int dw9714_t_vcm_slew(struct v4l2_subdev *sd, s32 value); +extern int dw9714_t_vcm_timing(struct v4l2_subdev *sd, s32 value); + +extern int dw9719_vcm_power_up(struct v4l2_subdev *sd); +extern int dw9719_vcm_power_down(struct v4l2_subdev *sd); +extern int dw9719_vcm_init(struct v4l2_subdev *sd); + +extern int dw9719_t_focus_vcm(struct v4l2_subdev *sd, u16 val); +extern int dw9719_t_focus_abs(struct v4l2_subdev *sd, s32 value); +extern int dw9719_t_focus_rel(struct v4l2_subdev *sd, s32 value); +extern int dw9719_q_focus_status(struct v4l2_subdev *sd, s32 *value); +extern int dw9719_q_focus_abs(struct v4l2_subdev *sd, s32 *value); +extern int dw9719_t_vcm_slew(struct v4l2_subdev *sd, s32 value); +extern int dw9719_t_vcm_timing(struct v4l2_subdev *sd, s32 value); + +extern int dw9718_vcm_power_up(struct v4l2_subdev *sd); +extern int dw9718_vcm_power_down(struct v4l2_subdev *sd); +extern int dw9718_vcm_init(struct v4l2_subdev *sd); + +extern int dw9718_t_focus_vcm(struct v4l2_subdev *sd, u16 val); +extern int dw9718_t_focus_abs(struct v4l2_subdev *sd, s32 value); +extern int dw9718_t_focus_rel(struct v4l2_subdev *sd, s32 value); +extern int dw9718_q_focus_status(struct v4l2_subdev *sd, s32 *value); +extern int dw9718_q_focus_abs(struct v4l2_subdev *sd, s32 *value); +extern int dw9718_t_vcm_slew(struct v4l2_subdev *sd, s32 value); +extern int dw9718_t_vcm_timing(struct v4l2_subdev *sd, s32 value); + +extern int vcm_power_up(struct v4l2_subdev *sd); +extern int vcm_power_down(struct v4l2_subdev *sd); + +struct imx_vcm imx_vcms[] = { + [IMX175_MERRFLD] = { + .power_up = drv201_vcm_power_up, + .power_down = drv201_vcm_power_down, + .init = drv201_vcm_init, + .t_focus_vcm = drv201_t_focus_vcm, + .t_focus_abs = drv201_t_focus_abs, + .t_focus_abs_init = NULL, + .t_focus_rel = drv201_t_focus_rel, + .q_focus_status = drv201_q_focus_status, + .q_focus_abs = drv201_q_focus_abs, + .t_vcm_slew = drv201_t_vcm_slew, + .t_vcm_timing = drv201_t_vcm_timing, + }, + [IMX175_VALLEYVIEW] = { + .power_up = dw9714_vcm_power_up, + .power_down = dw9714_vcm_power_down, + .init = dw9714_vcm_init, + .t_focus_vcm = dw9714_t_focus_vcm, + .t_focus_abs = dw9714_t_focus_abs, + .t_focus_abs_init = NULL, + .t_focus_rel = dw9714_t_focus_rel, + .q_focus_status = dw9714_q_focus_status, + .q_focus_abs = dw9714_q_focus_abs, + .t_vcm_slew = dw9714_t_vcm_slew, + .t_vcm_timing = dw9714_t_vcm_timing, + }, + [IMX135_SALTBAY] = { + .power_up = ad5816g_vcm_power_up, + .power_down = ad5816g_vcm_power_down, + .init = ad5816g_vcm_init, + .t_focus_vcm = ad5816g_t_focus_vcm, + .t_focus_abs = ad5816g_t_focus_abs, + .t_focus_abs_init = NULL, + .t_focus_rel = ad5816g_t_focus_rel, + .q_focus_status = ad5816g_q_focus_status, + .q_focus_abs = ad5816g_q_focus_abs, + .t_vcm_slew = ad5816g_t_vcm_slew, + .t_vcm_timing = ad5816g_t_vcm_timing, + }, + [IMX135_VICTORIABAY] = { + .power_up = dw9719_vcm_power_up, + .power_down = dw9719_vcm_power_down, + .init = dw9719_vcm_init, + .t_focus_vcm = dw9719_t_focus_vcm, + .t_focus_abs = dw9719_t_focus_abs, + .t_focus_abs_init = NULL, + .t_focus_rel = dw9719_t_focus_rel, + .q_focus_status = dw9719_q_focus_status, + .q_focus_abs = dw9719_q_focus_abs, + .t_vcm_slew = dw9719_t_vcm_slew, + .t_vcm_timing = dw9719_t_vcm_timing, + }, + [IMX134_VALLEYVIEW] = { + .power_up = dw9714_vcm_power_up, + .power_down = dw9714_vcm_power_down, + .init = dw9714_vcm_init, + .t_focus_vcm = dw9714_t_focus_vcm, + .t_focus_abs = dw9714_t_focus_abs, + .t_focus_abs_init = dw9714_t_focus_abs_init, + .t_focus_rel = dw9714_t_focus_rel, + .q_focus_status = dw9714_q_focus_status, + .q_focus_abs = dw9714_q_focus_abs, + .t_vcm_slew = dw9714_t_vcm_slew, + .t_vcm_timing = dw9714_t_vcm_timing, + }, + [IMX219_MFV0_PRH] = { + .power_up = dw9718_vcm_power_up, + .power_down = dw9718_vcm_power_down, + .init = dw9718_vcm_init, + .t_focus_vcm = dw9718_t_focus_vcm, + .t_focus_abs = dw9718_t_focus_abs, + .t_focus_abs_init = NULL, + .t_focus_rel = dw9718_t_focus_rel, + .q_focus_status = dw9718_q_focus_status, + .q_focus_abs = dw9718_q_focus_abs, + .t_vcm_slew = dw9718_t_vcm_slew, + .t_vcm_timing = dw9718_t_vcm_timing, + }, + [IMX_ID_DEFAULT] = { + .power_up = NULL, + .power_down = NULL, + .t_focus_abs_init = NULL, + }, +}; + +extern void *dummy_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); +extern void *imx_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); +extern void *e2prom_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); +extern void *brcc064_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); +extern void *imx227_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); +extern void *e2prom_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size); +struct imx_otp imx_otps[] = { + [IMX175_MERRFLD] = { + .otp_read = imx_otp_read, + .dev_addr = E2PROM_ADDR, + .start_addr = 0, + .size = DEFAULT_OTP_SIZE, + }, + [IMX175_VALLEYVIEW] = { + .otp_read = e2prom_otp_read, + .dev_addr = E2PROM_ABICO_SS89A839_ADDR, + .start_addr = E2PROM_2ADDR, + .size = DEFAULT_OTP_SIZE, + }, + [IMX135_SALTBAY] = { + .otp_read = e2prom_otp_read, + .dev_addr = E2PROM_ADDR, + .start_addr = 0, + .size = DEFAULT_OTP_SIZE, + }, + [IMX135_VICTORIABAY] = { + .otp_read = imx_otp_read, + .size = DEFAULT_OTP_SIZE, + }, + [IMX134_VALLEYVIEW] = { + .otp_read = e2prom_otp_read, + .dev_addr = E2PROM_LITEON_12P1BA869D_ADDR, + .start_addr = 0, + .size = E2PROM_LITEON_12P1BA869D_SIZE, + }, + [IMX132_SALTBAY] = { + .otp_read = dummy_otp_read, + .size = DEFAULT_OTP_SIZE, + }, + [IMX208_MOFD_PD2] = { + .otp_read = dummy_otp_read, + .size = DEFAULT_OTP_SIZE, + }, + [IMX219_MFV0_PRH] = { + .otp_read = brcc064_otp_read, + .dev_addr = E2PROM_ADDR, + .start_addr = 0, + .size = IMX219_OTP_SIZE, + }, + [IMX227_SAND] = { + .otp_read = imx227_otp_read, + .size = IMX227_OTP_SIZE, + }, + [IMX_ID_DEFAULT] = { + .otp_read = dummy_otp_read, + .size = DEFAULT_OTP_SIZE, + }, +}; + +#endif + diff --git a/drivers/staging/media/atomisp/i2c/imx/imx132.h b/drivers/staging/media/atomisp/i2c/imx/imx132.h new file mode 100644 index 0000000000000000000000000000000000000000..98f047b8a1ba16191c3d002da1663a7ad6fccfa2 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx132.h @@ -0,0 +1,566 @@ +/* + * Support for Sony IMX camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __IMX132_H__ +#define __IMX132_H__ +#include "common.h" + +/********************** registers define ********************************/ +#define IMX132_RGLANESEL 0x3301 /* Number of lanes */ +#define IMX132_RGLANESEL_1LANE 0x01 +#define IMX132_RGLANESEL_2LANES 0x00 +#define IMX132_RGLANESEL_4LANES 0x03 + +#define IMX132_2LANES_GAINFACT 2096 /* 524/256 * 2^10 */ +#define IMX132_2LANES_GAINFACT_SHIFT 10 + +/********************** settings for imx from vendor*********************/ +static struct imx_reg imx132_1080p_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* Global Settings */ + {IMX_8BIT, 0x3087, 0x53}, + {IMX_8BIT, 0x308B, 0x5A}, + {IMX_8BIT, 0x3094, 0x11}, + {IMX_8BIT, 0x309D, 0xA4}, + {IMX_8BIT, 0x30AA, 0x01}, + {IMX_8BIT, 0x30C6, 0x00}, + {IMX_8BIT, 0x30C7, 0x00}, + {IMX_8BIT, 0x3118, 0x2F}, + {IMX_8BIT, 0x312A, 0x00}, + {IMX_8BIT, 0x312B, 0x0B}, + {IMX_8BIT, 0x312C, 0x0B}, + {IMX_8BIT, 0x312D, 0x13}, + /* PLL setting */ + {IMX_8BIT, 0x0305, 0x02}, + {IMX_8BIT, 0x0307, 0x50}, + {IMX_8BIT, 0x30A4, 0x02}, + {IMX_8BIT, 0x303C, 0x3C}, + /* Mode setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x14}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x32}, + {IMX_8BIT, 0x0348, 0x07}, + {IMX_8BIT, 0x0349, 0xA3}, + {IMX_8BIT, 0x034A, 0x04}, + {IMX_8BIT, 0x034B, 0x79}, + {IMX_8BIT, 0x034C, 0x07}, + {IMX_8BIT, 0x034D, 0x90}, + {IMX_8BIT, 0x034E, 0x04}, + {IMX_8BIT, 0x034F, 0x48}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x303D, 0x10}, + {IMX_8BIT, 0x303E, 0x5A}, + {IMX_8BIT, 0x3040, 0x00}, + {IMX_8BIT, 0x3041, 0x00}, + {IMX_8BIT, 0x3048, 0x00}, + {IMX_8BIT, 0x304C, 0x2F}, + {IMX_8BIT, 0x304D, 0x02}, + {IMX_8BIT, 0x3064, 0x92}, + {IMX_8BIT, 0x306A, 0x10}, + {IMX_8BIT, 0x309B, 0x00}, + {IMX_8BIT, 0x309E, 0x41}, + {IMX_8BIT, 0x30A0, 0x10}, + {IMX_8BIT, 0x30A1, 0x0B}, + {IMX_8BIT, 0x30B2, 0x00}, + {IMX_8BIT, 0x30D5, 0x00}, + {IMX_8BIT, 0x30D6, 0x00}, + {IMX_8BIT, 0x30D7, 0x00}, + {IMX_8BIT, 0x30D8, 0x00}, + {IMX_8BIT, 0x30D9, 0x00}, + {IMX_8BIT, 0x30DA, 0x00}, + {IMX_8BIT, 0x30DB, 0x00}, + {IMX_8BIT, 0x30DC, 0x00}, + {IMX_8BIT, 0x30DD, 0x00}, + {IMX_8BIT, 0x30DE, 0x00}, + {IMX_8BIT, 0x3102, 0x0C}, + {IMX_8BIT, 0x3103, 0x33}, + {IMX_8BIT, 0x3104, 0x18}, + {IMX_8BIT, 0x3105, 0x00}, + {IMX_8BIT, 0x3106, 0x65}, + {IMX_8BIT, 0x3107, 0x00}, + {IMX_8BIT, 0x3108, 0x06}, + {IMX_8BIT, 0x3109, 0x04}, + {IMX_8BIT, 0x310A, 0x04}, + {IMX_8BIT, 0x315C, 0x3D}, + {IMX_8BIT, 0x315D, 0x3C}, + {IMX_8BIT, 0x316E, 0x3E}, + {IMX_8BIT, 0x316F, 0x3D}, + /* Global timing */ + {IMX_8BIT, 0x3304, 0x07}, /* RGTLPX[5:0] TLPX */ + {IMX_8BIT, 0x3305, 0x06}, /* RGTCLKPREPARE[3:0] TCLK-PREPARE */ + {IMX_8BIT, 0x3306, 0x19}, /* RGTCLKZERO[5:0] TCLK-ZERO */ + {IMX_8BIT, 0x3307, 0x03}, /* RGTCLKPRE[5:0] TCLK-PRE */ + {IMX_8BIT, 0x3308, 0x0F}, /* RGTCLKPOST[5:0] TCLK-POST */ + {IMX_8BIT, 0x3309, 0x07}, /* RGTCLKTRAIL[3:0] TCLK-TRAIL */ + {IMX_8BIT, 0x330A, 0x0C}, /* RGTHSEXIT[5:0] THS-EXIT */ + {IMX_8BIT, 0x330B, 0x06}, /* RGTHSPREPARE[3:0] THS-PREPARE */ + {IMX_8BIT, 0x330C, 0x0B}, /* RGTHSZERO[5:0] THS-ZERO */ + {IMX_8BIT, 0x330D, 0x07}, /* RGTHSTRAIL[3:0] THS-TRAIL */ + {IMX_8BIT, 0x330E, 0x03}, + {IMX_8BIT, 0x3318, 0x62}, + {IMX_8BIT, 0x3322, 0x09}, + {IMX_8BIT, 0x3342, 0x00}, + {IMX_8BIT, 0x3348, 0xE0}, + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx132_1456x1096_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* Global Settings */ + {IMX_8BIT, 0x3087, 0x53}, + {IMX_8BIT, 0x308B, 0x5A}, + {IMX_8BIT, 0x3094, 0x11}, + {IMX_8BIT, 0x309D, 0xA4}, + {IMX_8BIT, 0x30AA, 0x01}, + {IMX_8BIT, 0x30C6, 0x00}, + {IMX_8BIT, 0x30C7, 0x00}, + {IMX_8BIT, 0x3118, 0x2F}, + {IMX_8BIT, 0x312A, 0x00}, + {IMX_8BIT, 0x312B, 0x0B}, + {IMX_8BIT, 0x312C, 0x0B}, + {IMX_8BIT, 0x312D, 0x13}, + /* PLL setting */ + {IMX_8BIT, 0x0305, 0x02}, + {IMX_8BIT, 0x0307, 0x50}, + {IMX_8BIT, 0x30A4, 0x02}, + {IMX_8BIT, 0x303C, 0x3C}, + /* Mode setting */ + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0x04}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x32}, + {IMX_8BIT, 0x0348, 0x06}, + {IMX_8BIT, 0x0349, 0xB3}, + {IMX_8BIT, 0x034A, 0x04}, + {IMX_8BIT, 0x034B, 0x79}, + {IMX_8BIT, 0x034C, 0x05}, + {IMX_8BIT, 0x034D, 0xB0}, + {IMX_8BIT, 0x034E, 0x04}, + {IMX_8BIT, 0x034F, 0x48}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x303D, 0x10}, + {IMX_8BIT, 0x303E, 0x5A}, + {IMX_8BIT, 0x3040, 0x00}, + {IMX_8BIT, 0x3041, 0x00}, + {IMX_8BIT, 0x3048, 0x00}, + {IMX_8BIT, 0x304C, 0x2F}, + {IMX_8BIT, 0x304D, 0x02}, + {IMX_8BIT, 0x3064, 0x92}, + {IMX_8BIT, 0x306A, 0x10}, + {IMX_8BIT, 0x309B, 0x00}, + {IMX_8BIT, 0x309E, 0x41}, + {IMX_8BIT, 0x30A0, 0x10}, + {IMX_8BIT, 0x30A1, 0x0B}, + {IMX_8BIT, 0x30B2, 0x00}, + {IMX_8BIT, 0x30D5, 0x00}, + {IMX_8BIT, 0x30D6, 0x00}, + {IMX_8BIT, 0x30D7, 0x00}, + {IMX_8BIT, 0x30D8, 0x00}, + {IMX_8BIT, 0x30D9, 0x00}, + {IMX_8BIT, 0x30DA, 0x00}, + {IMX_8BIT, 0x30DB, 0x00}, + {IMX_8BIT, 0x30DC, 0x00}, + {IMX_8BIT, 0x30DD, 0x00}, + {IMX_8BIT, 0x30DE, 0x00}, + {IMX_8BIT, 0x3102, 0x0C}, + {IMX_8BIT, 0x3103, 0x33}, + {IMX_8BIT, 0x3104, 0x18}, + {IMX_8BIT, 0x3105, 0x00}, + {IMX_8BIT, 0x3106, 0x65}, + {IMX_8BIT, 0x3107, 0x00}, + {IMX_8BIT, 0x3108, 0x06}, + {IMX_8BIT, 0x3109, 0x04}, + {IMX_8BIT, 0x310A, 0x04}, + {IMX_8BIT, 0x315C, 0x3D}, + {IMX_8BIT, 0x315D, 0x3C}, + {IMX_8BIT, 0x316E, 0x3E}, + {IMX_8BIT, 0x316F, 0x3D}, + /* Global timing */ + {IMX_8BIT, 0x3304, 0x07}, /* RGTLPX[5:0] TLPX */ + {IMX_8BIT, 0x3305, 0x06}, /* RGTCLKPREPARE[3:0] TCLK-PREPARE */ + {IMX_8BIT, 0x3306, 0x19}, /* RGTCLKZERO[5:0] TCLK-ZERO */ + {IMX_8BIT, 0x3307, 0x03}, /* RGTCLKPRE[5:0] TCLK-PRE */ + {IMX_8BIT, 0x3308, 0x0F}, /* RGTCLKPOST[5:0] TCLK-POST */ + {IMX_8BIT, 0x3309, 0x07}, /* RGTCLKTRAIL[3:0] TCLK-TRAIL */ + {IMX_8BIT, 0x330A, 0x0C}, /* RGTHSEXIT[5:0] THS-EXIT */ + {IMX_8BIT, 0x330B, 0x06}, /* RGTHSPREPARE[3:0] THS-PREPARE */ + {IMX_8BIT, 0x330C, 0x0B}, /* RGTHSZERO[5:0] THS-ZERO */ + {IMX_8BIT, 0x330D, 0x07}, /* RGTHSTRAIL[3:0] THS-TRAIL */ + {IMX_8BIT, 0x330E, 0x03}, + {IMX_8BIT, 0x3318, 0x62}, + {IMX_8BIT, 0x3322, 0x09}, + {IMX_8BIT, 0x3342, 0x00}, + {IMX_8BIT, 0x3348, 0xE0}, + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx132_1636x1096_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* Global Settings */ + {IMX_8BIT, 0x3087, 0x53}, + {IMX_8BIT, 0x308B, 0x5A}, + {IMX_8BIT, 0x3094, 0x11}, + {IMX_8BIT, 0x309D, 0xA4}, + {IMX_8BIT, 0x30AA, 0x01}, + {IMX_8BIT, 0x30C6, 0x00}, + {IMX_8BIT, 0x30C7, 0x00}, + {IMX_8BIT, 0x3118, 0x2F}, + {IMX_8BIT, 0x312A, 0x00}, + {IMX_8BIT, 0x312B, 0x0B}, + {IMX_8BIT, 0x312C, 0x0B}, + {IMX_8BIT, 0x312D, 0x13}, + /* PLL setting */ + {IMX_8BIT, 0x0305, 0x02}, + {IMX_8BIT, 0x0307, 0x50}, + {IMX_8BIT, 0x30A4, 0x02}, + {IMX_8BIT, 0x303C, 0x3C}, + /* Mode setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0xAA}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x32}, + {IMX_8BIT, 0x0348, 0x07}, + {IMX_8BIT, 0x0349, 0x0D}, + {IMX_8BIT, 0x034A, 0x04}, + {IMX_8BIT, 0x034B, 0x79}, + {IMX_8BIT, 0x034C, 0x06}, + {IMX_8BIT, 0x034D, 0x64}, + {IMX_8BIT, 0x034E, 0x04}, + {IMX_8BIT, 0x034F, 0x48}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x303D, 0x10}, + {IMX_8BIT, 0x303E, 0x5A}, + {IMX_8BIT, 0x3040, 0x00}, + {IMX_8BIT, 0x3041, 0x00}, + {IMX_8BIT, 0x3048, 0x00}, + {IMX_8BIT, 0x304C, 0x2F}, + {IMX_8BIT, 0x304D, 0x02}, + {IMX_8BIT, 0x3064, 0x92}, + {IMX_8BIT, 0x306A, 0x10}, + {IMX_8BIT, 0x309B, 0x00}, + {IMX_8BIT, 0x309E, 0x41}, + {IMX_8BIT, 0x30A0, 0x10}, + {IMX_8BIT, 0x30A1, 0x0B}, + {IMX_8BIT, 0x30B2, 0x00}, + {IMX_8BIT, 0x30D5, 0x00}, + {IMX_8BIT, 0x30D6, 0x00}, + {IMX_8BIT, 0x30D7, 0x00}, + {IMX_8BIT, 0x30D8, 0x00}, + {IMX_8BIT, 0x30D9, 0x00}, + {IMX_8BIT, 0x30DA, 0x00}, + {IMX_8BIT, 0x30DB, 0x00}, + {IMX_8BIT, 0x30DC, 0x00}, + {IMX_8BIT, 0x30DD, 0x00}, + {IMX_8BIT, 0x30DE, 0x00}, + {IMX_8BIT, 0x3102, 0x0C}, + {IMX_8BIT, 0x3103, 0x33}, + {IMX_8BIT, 0x3104, 0x18}, + {IMX_8BIT, 0x3105, 0x00}, + {IMX_8BIT, 0x3106, 0x65}, + {IMX_8BIT, 0x3107, 0x00}, + {IMX_8BIT, 0x3108, 0x06}, + {IMX_8BIT, 0x3109, 0x04}, + {IMX_8BIT, 0x310A, 0x04}, + {IMX_8BIT, 0x315C, 0x3D}, + {IMX_8BIT, 0x315D, 0x3C}, + {IMX_8BIT, 0x316E, 0x3E}, + {IMX_8BIT, 0x316F, 0x3D}, + /* Global timing */ + {IMX_8BIT, 0x3304, 0x07}, /* RGTLPX[5:0] TLPX */ + {IMX_8BIT, 0x3305, 0x06}, /* RGTCLKPREPARE[3:0] TCLK-PREPARE */ + {IMX_8BIT, 0x3306, 0x19}, /* RGTCLKZERO[5:0] TCLK-ZERO */ + {IMX_8BIT, 0x3307, 0x03}, /* RGTCLKPRE[5:0] TCLK-PRE */ + {IMX_8BIT, 0x3308, 0x0F}, /* RGTCLKPOST[5:0] TCLK-POST */ + {IMX_8BIT, 0x3309, 0x07}, /* RGTCLKTRAIL[3:0] TCLK-TRAIL */ + {IMX_8BIT, 0x330A, 0x0C}, /* RGTHSEXIT[5:0] THS-EXIT */ + {IMX_8BIT, 0x330B, 0x06}, /* RGTHSPREPARE[3:0] THS-PREPARE */ + {IMX_8BIT, 0x330C, 0x0B}, /* RGTHSZERO[5:0] THS-ZERO */ + {IMX_8BIT, 0x330D, 0x07}, /* RGTHSTRAIL[3:0] THS-TRAIL */ + {IMX_8BIT, 0x330E, 0x03}, + {IMX_8BIT, 0x3318, 0x62}, + {IMX_8BIT, 0x3322, 0x09}, + {IMX_8BIT, 0x3342, 0x00}, + {IMX_8BIT, 0x3348, 0xE0}, + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx132_1336x1096_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* Global Settings */ + {IMX_8BIT, 0x3087, 0x53}, + {IMX_8BIT, 0x308B, 0x5A}, + {IMX_8BIT, 0x3094, 0x11}, + {IMX_8BIT, 0x309D, 0xA4}, + {IMX_8BIT, 0x30AA, 0x01}, + {IMX_8BIT, 0x30C6, 0x00}, + {IMX_8BIT, 0x30C7, 0x00}, + {IMX_8BIT, 0x3118, 0x2F}, + {IMX_8BIT, 0x312A, 0x00}, + {IMX_8BIT, 0x312B, 0x0B}, + {IMX_8BIT, 0x312C, 0x0B}, + {IMX_8BIT, 0x312D, 0x13}, + /* PLL setting */ + {IMX_8BIT, 0x0305, 0x02}, + {IMX_8BIT, 0x0307, 0x50}, + {IMX_8BIT, 0x30A4, 0x02}, + {IMX_8BIT, 0x303C, 0x3C}, + /* Mode setting */ + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0x2C}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x32}, + {IMX_8BIT, 0x0348, 0x06}, + {IMX_8BIT, 0x0349, 0x77}, + {IMX_8BIT, 0x034A, 0x04}, + {IMX_8BIT, 0x034B, 0x79}, + {IMX_8BIT, 0x034C, 0x05}, + {IMX_8BIT, 0x034D, 0x38}, + {IMX_8BIT, 0x034E, 0x04}, + {IMX_8BIT, 0x034F, 0x48}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x303D, 0x10}, + {IMX_8BIT, 0x303E, 0x5A}, + {IMX_8BIT, 0x3040, 0x00}, + {IMX_8BIT, 0x3041, 0x00}, + {IMX_8BIT, 0x3048, 0x00}, + {IMX_8BIT, 0x304C, 0x2F}, + {IMX_8BIT, 0x304D, 0x02}, + {IMX_8BIT, 0x3064, 0x92}, + {IMX_8BIT, 0x306A, 0x10}, + {IMX_8BIT, 0x309B, 0x00}, + {IMX_8BIT, 0x309E, 0x41}, + {IMX_8BIT, 0x30A0, 0x10}, + {IMX_8BIT, 0x30A1, 0x0B}, + {IMX_8BIT, 0x30B2, 0x00}, + {IMX_8BIT, 0x30D5, 0x00}, + {IMX_8BIT, 0x30D6, 0x00}, + {IMX_8BIT, 0x30D7, 0x00}, + {IMX_8BIT, 0x30D8, 0x00}, + {IMX_8BIT, 0x30D9, 0x00}, + {IMX_8BIT, 0x30DA, 0x00}, + {IMX_8BIT, 0x30DB, 0x00}, + {IMX_8BIT, 0x30DC, 0x00}, + {IMX_8BIT, 0x30DD, 0x00}, + {IMX_8BIT, 0x30DE, 0x00}, + {IMX_8BIT, 0x3102, 0x0C}, + {IMX_8BIT, 0x3103, 0x33}, + {IMX_8BIT, 0x3104, 0x18}, + {IMX_8BIT, 0x3105, 0x00}, + {IMX_8BIT, 0x3106, 0x65}, + {IMX_8BIT, 0x3107, 0x00}, + {IMX_8BIT, 0x3108, 0x06}, + {IMX_8BIT, 0x3109, 0x04}, + {IMX_8BIT, 0x310A, 0x04}, + {IMX_8BIT, 0x315C, 0x3D}, + {IMX_8BIT, 0x315D, 0x3C}, + {IMX_8BIT, 0x316E, 0x3E}, + {IMX_8BIT, 0x316F, 0x3D}, + /* Global timing */ + {IMX_8BIT, 0x3304, 0x07}, /* RGTLPX[5:0] TLPX */ + {IMX_8BIT, 0x3305, 0x06}, /* RGTCLKPREPARE[3:0] TCLK-PREPARE */ + {IMX_8BIT, 0x3306, 0x19}, /* RGTCLKZERO[5:0] TCLK-ZERO */ + {IMX_8BIT, 0x3307, 0x03}, /* RGTCLKPRE[5:0] TCLK-PRE */ + {IMX_8BIT, 0x3308, 0x0F}, /* RGTCLKPOST[5:0] TCLK-POST */ + {IMX_8BIT, 0x3309, 0x07}, /* RGTCLKTRAIL[3:0] TCLK-TRAIL */ + {IMX_8BIT, 0x330A, 0x0C}, /* RGTHSEXIT[5:0] THS-EXIT */ + {IMX_8BIT, 0x330B, 0x06}, /* RGTHSPREPARE[3:0] THS-PREPARE */ + {IMX_8BIT, 0x330C, 0x0B}, /* RGTHSZERO[5:0] THS-ZERO */ + {IMX_8BIT, 0x330D, 0x07}, /* RGTHSTRAIL[3:0] THS-TRAIL */ + {IMX_8BIT, 0x330E, 0x03}, + {IMX_8BIT, 0x3318, 0x62}, + {IMX_8BIT, 0x3322, 0x09}, + {IMX_8BIT, 0x3342, 0x00}, + {IMX_8BIT, 0x3348, 0xE0}, + + {IMX_TOK_TERM, 0, 0}, +}; + +/********************** settings for imx - reference *********************/ +static struct imx_reg const imx132_init_settings[] = { + /* sw reset */ + { IMX_8BIT, 0x0100, 0x00 }, + { IMX_8BIT, 0x0103, 0x01 }, + { IMX_TOK_DELAY, 0, 5}, + { IMX_8BIT, 0x0103, 0x00 }, + GROUPED_PARAMETER_HOLD_ENABLE, + /* Global Settings */ + {IMX_8BIT, 0x3087, 0x53}, + {IMX_8BIT, 0x308B, 0x5A}, + {IMX_8BIT, 0x3094, 0x11}, + {IMX_8BIT, 0x309D, 0xA4}, + {IMX_8BIT, 0x30AA, 0x01}, + {IMX_8BIT, 0x30C6, 0x00}, + {IMX_8BIT, 0x30C7, 0x00}, + {IMX_8BIT, 0x3118, 0x2F}, + {IMX_8BIT, 0x312A, 0x00}, + {IMX_8BIT, 0x312B, 0x0B}, + {IMX_8BIT, 0x312C, 0x0B}, + {IMX_8BIT, 0x312D, 0x13}, + GROUPED_PARAMETER_HOLD_DISABLE, + { IMX_TOK_TERM, 0, 0} +}; + +struct imx_resolution imx132_res_preview[] = { + { + .desc = "imx132_1080p_30fps", + .regs = imx132_1080p_30fps, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08F2, + .lines_per_frame = 0x045C, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .skip_frames = 2, + .mipi_freq = 384000, + }, +}; + +struct imx_resolution imx132_res_still[] = { + { + .desc = "imx132_1080p_30fps", + .regs = imx132_1080p_30fps, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08F2, + .lines_per_frame = 0x045C, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .skip_frames = 2, + .mipi_freq = 384000, + }, +}; + +struct imx_resolution imx132_res_video[] = { + { + .desc = "imx132_1336x1096_30fps", + .regs = imx132_1336x1096_30fps, + .width = 1336, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08F2, + .lines_per_frame = 0x045C, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .skip_frames = 2, + .mipi_freq = 384000, + }, + { + .desc = "imx132_1456x1096_30fps", + .regs = imx132_1456x1096_30fps, + .width = 1456, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08F2, + .lines_per_frame = 0x045C, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .skip_frames = 2, + .mipi_freq = 384000, + }, + { + .desc = "imx132_1636x1096_30fps", + .regs = imx132_1636x1096_30fps, + .width = 1636, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08F2, + .lines_per_frame = 0x045C, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .skip_frames = 2, + .mipi_freq = 384000, + }, + { + .desc = "imx132_1080p_30fps", + .regs = imx132_1080p_30fps, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08F2, + .lines_per_frame = 0x045C, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .skip_frames = 2, + .mipi_freq = 384000, + }, +}; +#endif + diff --git a/drivers/staging/media/atomisp/i2c/imx/imx134.h b/drivers/staging/media/atomisp/i2c/imx/imx134.h new file mode 100644 index 0000000000000000000000000000000000000000..cf35197ed77fb68f8edf4bef0a17721c24605e0f --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx134.h @@ -0,0 +1,2464 @@ +#ifndef __IMX134_H__ +#define __IMX134_H__ + +/********************** imx134 setting - version 1 *********************/ +static struct imx_reg const imx134_init_settings[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* Basic settings */ + { IMX_8BIT, 0x0105, 0x01 }, + { IMX_8BIT, 0x0220, 0x01 }, + { IMX_8BIT, 0x3302, 0x11 }, + { IMX_8BIT, 0x3833, 0x20 }, + { IMX_8BIT, 0x3893, 0x00 }, + { IMX_8BIT, 0x3906, 0x08 }, + { IMX_8BIT, 0x3907, 0x01 }, + { IMX_8BIT, 0x391B, 0x01 }, + { IMX_8BIT, 0x3C09, 0x01 }, + { IMX_8BIT, 0x600A, 0x00 }, + + /* Analog settings */ + { IMX_8BIT, 0x3008, 0xB0 }, + { IMX_8BIT, 0x320A, 0x01 }, + { IMX_8BIT, 0x320D, 0x10 }, + { IMX_8BIT, 0x3216, 0x2E }, + { IMX_8BIT, 0x322C, 0x02 }, + { IMX_8BIT, 0x3409, 0x0C }, + { IMX_8BIT, 0x340C, 0x2D }, + { IMX_8BIT, 0x3411, 0x39 }, + { IMX_8BIT, 0x3414, 0x1E }, + { IMX_8BIT, 0x3427, 0x04 }, + { IMX_8BIT, 0x3480, 0x1E }, + { IMX_8BIT, 0x3484, 0x1E }, + { IMX_8BIT, 0x3488, 0x1E }, + { IMX_8BIT, 0x348C, 0x1E }, + { IMX_8BIT, 0x3490, 0x1E }, + { IMX_8BIT, 0x3494, 0x1E }, + { IMX_8BIT, 0x3511, 0x8F }, + { IMX_8BIT, 0x3617, 0x2D }, + + GROUPED_PARAMETER_HOLD_DISABLE, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane 3280x2464 8M 30fps, vendor provide */ +static struct imx_reg const imx134_8M_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* clock setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, + { IMX_8BIT, 0x0391, 0x11 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, /* down scaling 16/16 = 1 */ + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0345, 0x00 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0347, 0x00 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3279 */ + { IMX_8BIT, 0x0349, 0xCF }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2463 */ + { IMX_8BIT, 0x034B, 0x9F }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x0C }, /* x_output_size[15:8]: 3280*/ + { IMX_8BIT, 0x034D, 0xD0 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x09 }, /* y_output_size[15:8]:2464 */ + { IMX_8BIT, 0x034F, 0xA0 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x0C }, + { IMX_8BIT, 0x0355, 0xD0 }, + { IMX_8BIT, 0x0356, 0x09 }, + { IMX_8BIT, 0x0357, 0xA0 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x0C }, + { IMX_8BIT, 0x3311, 0xD0 }, + { IMX_8BIT, 0x3312, 0x09 }, + { IMX_8BIT, 0x3313, 0xA0 }, + { IMX_8BIT, 0x331C, 0x01 }, + { IMX_8BIT, 0x331D, 0xAE }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global timing setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration time setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane, 1/2 binning 30fps 1640x1232, vendor provide */ +static struct imx_reg const imx134_1640_1232_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning */ + { IMX_8BIT, 0x0391, 0x22 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* no resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0345, 0x00 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0347, 0x00 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3279 */ + { IMX_8BIT, 0x0349, 0xCF }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2463 */ + { IMX_8BIT, 0x034B, 0x9F }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x06 }, /* x_output_size[15:8]:1640 */ + { IMX_8BIT, 0x034D, 0x68 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x04 }, /* y_output_size[15:8]:1232 */ + { IMX_8BIT, 0x034F, 0xD0 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x06 }, + { IMX_8BIT, 0x0355, 0x68 }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0xD0 }, + + { IMX_8BIT, 0x301D, 0x30 }, + + { IMX_8BIT, 0x3310, 0x06 }, + { IMX_8BIT, 0x3311, 0x68 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0xD0 }, + + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0x06 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane, 1/4 binning 30fps 820x616, vendor provide */ +static struct imx_reg const imx134_820_616_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning */ + { IMX_8BIT, 0x0391, 0x44 }, /* 4x4 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* no resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0345, 0x00 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0347, 0x00 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3279 */ + { IMX_8BIT, 0x0349, 0xCF }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2463 */ + { IMX_8BIT, 0x034B, 0x9F }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x03 }, /* x_output_size[15:8]:820 */ + { IMX_8BIT, 0x034D, 0x34 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x02 }, /* y_output_size[15:8]:616 */ + { IMX_8BIT, 0x034F, 0x68 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x03 }, + { IMX_8BIT, 0x0355, 0x34 }, + { IMX_8BIT, 0x0356, 0x02 }, + { IMX_8BIT, 0x0357, 0x68 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x03 }, + { IMX_8BIT, 0x3311, 0x34 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0x68 }, + { IMX_8BIT, 0x331C, 0x02 }, + { IMX_8BIT, 0x331D, 0xD0 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane, 1/4 binning 30fps 820x552 */ +static struct imx_reg const imx134_820_552_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning */ + { IMX_8BIT, 0x0391, 0x44 }, /* 4x4 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* no resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0345, 0x00 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:128 */ + { IMX_8BIT, 0x0347, 0x80 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3280-1 */ + { IMX_8BIT, 0x0349, 0xCF }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2208+128-1 */ + { IMX_8BIT, 0x034B, 0x1F }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x03 }, /* x_output_size[15:8]: */ + { IMX_8BIT, 0x034D, 0x34 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x02 }, /* y_output_size[15:8]:616 */ + { IMX_8BIT, 0x034F, 0x28 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x03 }, + { IMX_8BIT, 0x0355, 0x34 }, + { IMX_8BIT, 0x0356, 0x02 }, + { IMX_8BIT, 0x0357, 0x28 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x03 }, + { IMX_8BIT, 0x3311, 0x34 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0x28 }, + { IMX_8BIT, 0x331C, 0x02 }, + { IMX_8BIT, 0x331D, 0xD0 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane, 1/4 binning 30fps 720x592 */ +static struct imx_reg const imx134_720_592_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning */ + { IMX_8BIT, 0x0391, 0x44 }, /* 4x4 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* no resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:200 */ + { IMX_8BIT, 0x0345, 0xC8 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:40 */ + { IMX_8BIT, 0x0347, 0x28 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:2880+200-1 */ + { IMX_8BIT, 0x0349, 0x07 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2368+40-1 */ + { IMX_8BIT, 0x034B, 0x67 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x02 }, /* x_output_size[15:8]: */ + { IMX_8BIT, 0x034D, 0xD0 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x02 }, /* y_output_size[15:8]:616 */ + { IMX_8BIT, 0x034F, 0x50 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x02 }, + { IMX_8BIT, 0x0355, 0xD0 }, + { IMX_8BIT, 0x0356, 0x02 }, + { IMX_8BIT, 0x0357, 0x50 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x02 }, + { IMX_8BIT, 0x3311, 0xD0 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0x50 }, + { IMX_8BIT, 0x331C, 0x02 }, + { IMX_8BIT, 0x331D, 0xD0 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +static struct imx_reg const imx134_752_616_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning */ + { IMX_8BIT, 0x0391, 0x44 }, /* 4x4 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* no resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:136 */ + { IMX_8BIT, 0x0345, 0x88 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0347, 0x00 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3145+134-1 */ + { IMX_8BIT, 0x0349, 0x47 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2463 */ + { IMX_8BIT, 0x034B, 0x9F }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x02 }, /* x_output_size[15:8]: 752*/ + { IMX_8BIT, 0x034D, 0xF0 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x02 }, /* y_output_size[15:8]:616 */ + { IMX_8BIT, 0x034F, 0x68 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + + { IMX_8BIT, 0x0354, 0x02 }, + { IMX_8BIT, 0x0355, 0xF0 }, + { IMX_8BIT, 0x0356, 0x02 }, + { IMX_8BIT, 0x0357, 0x68 }, + + { IMX_8BIT, 0x301D, 0x30 }, + + { IMX_8BIT, 0x3310, 0x02 }, + { IMX_8BIT, 0x3311, 0xF0 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0x68 }, + + { IMX_8BIT, 0x331C, 0x02 }, + { IMX_8BIT, 0x331D, 0xD0 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 1424x1168 */ +static struct imx_reg const imx134_1424_1168_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, /* binning */ + { IMX_8BIT, 0x0391, 0x11 }, /* no binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x22 }, /* 34/16=2.125 */ + { IMX_8BIT, 0x4082, 0x00 }, /* ?? */ + { IMX_8BIT, 0x4083, 0x00 }, /* ?? */ + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:136 */ + { IMX_8BIT, 0x0345, 0x80 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:0 */ + { IMX_8BIT, 0x0347, 0x00 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3145+134-1 */ + { IMX_8BIT, 0x0349, 0x51 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2463 */ + { IMX_8BIT, 0x034B, 0xB1 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x05 }, /* x_output_size[15:8]: 1424*/ + { IMX_8BIT, 0x034D, 0x90 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x04 }, /* y_output_size[15:8]:1168 */ + { IMX_8BIT, 0x034F, 0x90 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + + { IMX_8BIT, 0x0354, 0x0B }, + { IMX_8BIT, 0x0355, 0xD2 }, + { IMX_8BIT, 0x0356, 0x09 }, + { IMX_8BIT, 0x0357, 0xB2 }, + + { IMX_8BIT, 0x301D, 0x30 }, + + { IMX_8BIT, 0x3310, 0x05 }, + { IMX_8BIT, 0x3311, 0x90 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0x90 }, + + { IMX_8BIT, 0x331C, 0x02 }, + { IMX_8BIT, 0x331D, 0xD0 }, + { IMX_8BIT, 0x4084, 0x05 }, + { IMX_8BIT, 0x4085, 0x90 }, + { IMX_8BIT, 0x4086, 0x04 }, + { IMX_8BIT, 0x4087, 0x90 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane, 1/4 binning, 16/35 down scaling, 30fps, dvs */ +static struct imx_reg const imx134_240_196_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /*4x4 binning */ + { IMX_8BIT, 0x0391, 0x44 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x23 }, /* down scaling = 16/35 */ + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x02 }, /* x_addr_start[15:8]:590 */ + { IMX_8BIT, 0x0345, 0x4E }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:366 */ + { IMX_8BIT, 0x0347, 0x6E }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0A }, /* x_addr_end[15:8]:2104+590-1 */ + { IMX_8BIT, 0x0349, 0x85 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:1720+366-1 */ + { IMX_8BIT, 0x034B, 0x25 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x00 }, /* x_output_size[15:8]: 240*/ + { IMX_8BIT, 0x034D, 0xF0 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x00 }, /* y_output_size[15:8]:196 */ + { IMX_8BIT, 0x034F, 0xC4 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x02 }, /* crop_x: 526 */ + { IMX_8BIT, 0x0355, 0x0E }, + { IMX_8BIT, 0x0356, 0x01 }, /* crop_y: 430 */ + { IMX_8BIT, 0x0357, 0xAE }, + + { IMX_8BIT, 0x301D, 0x30 }, + + { IMX_8BIT, 0x3310, 0x00 }, + { IMX_8BIT, 0x3311, 0xF0 }, + { IMX_8BIT, 0x3312, 0x00 }, + { IMX_8BIT, 0x3313, 0xC4 }, + + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0x4C }, + + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0xF0 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0xC4 }, + + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x0A }, + { IMX_8BIT, 0x0203, 0x88 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane, 1/2 binning, 16/38 downscaling, 30fps, dvs */ +static struct imx_reg const imx134_448_366_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* 2x2 binning */ + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x26 }, /* down scaling = 16/38 */ + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x02 }, /* x_addr_start[15:8]:590 */ + { IMX_8BIT, 0x0345, 0x4E }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:366 */ + { IMX_8BIT, 0x0347, 0x6E }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0A }, /* x_addr_end[15:8]:2128+590-1 */ + { IMX_8BIT, 0x0349, 0x9D }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:1740+366-1 */ + { IMX_8BIT, 0x034B, 0x39 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x01 }, /* x_output_size[15:8]: 448*/ + { IMX_8BIT, 0x034D, 0xC0 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x01 }, /* y_output_size[15:8]:366 */ + { IMX_8BIT, 0x034F, 0x6E }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x04 }, /* crop_x: 1064 */ + { IMX_8BIT, 0x0355, 0x28 }, + { IMX_8BIT, 0x0356, 0x03 }, /* crop_y: 870 */ + { IMX_8BIT, 0x0357, 0x66 }, + + { IMX_8BIT, 0x301D, 0x30 }, + + { IMX_8BIT, 0x3310, 0x01 }, + { IMX_8BIT, 0x3311, 0xC0 }, + { IMX_8BIT, 0x3312, 0x01 }, + { IMX_8BIT, 0x3313, 0x6E }, + + { IMX_8BIT, 0x331C, 0x02 }, + { IMX_8BIT, 0x331D, 0xD0 }, + + { IMX_8BIT, 0x4084, 0x01 }, + { IMX_8BIT, 0x4085, 0xC0 }, + { IMX_8BIT, 0x4086, 0x01 }, + { IMX_8BIT, 0x4087, 0x6E }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane 2336x1312, 30fps, for 1080p dvs, vendor provide */ +static struct imx_reg const imx134_2336_1312_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, /* disable binning */ + { IMX_8BIT, 0x0391, 0x11 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x16 }, /* down scaling = 16/22 = 8/11 */ + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:34 */ + { IMX_8BIT, 0x0345, 0x22 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:332 */ + { IMX_8BIT, 0x0347, 0x4C }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3245 */ + { IMX_8BIT, 0x0349, 0xAD }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2135 */ + { IMX_8BIT, 0x034B, 0x57 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x09 }, /* x_output_size[15:8]:2336 */ + { IMX_8BIT, 0x034D, 0x20 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x05 }, /* y_output_size[15:8]:1312 */ + { IMX_8BIT, 0x034F, 0x20 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x0C }, + { IMX_8BIT, 0x0355, 0x8C }, + { IMX_8BIT, 0x0356, 0x07 }, + { IMX_8BIT, 0x0357, 0x0C }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x09 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x05 }, + { IMX_8BIT, 0x3313, 0x20 }, + { IMX_8BIT, 0x331C, 0x03 }, + { IMX_8BIT, 0x331D, 0xEB }, + { IMX_8BIT, 0x4084, 0x09 }, + { IMX_8BIT, 0x4085, 0x20 }, + { IMX_8BIT, 0x4086, 0x05 }, + { IMX_8BIT, 0x4087, 0x20 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane 1920x1080, 30fps, for 720p still capture */ +static struct imx_reg const imx134_1936_1096_30fps_v1[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, /* disable binning */ + { IMX_8BIT, 0x0391, 0x11 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x1A }, /* downscaling 16/26*/ + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:64 */ + { IMX_8BIT, 0x0345, 0x40 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:340 */ + { IMX_8BIT, 0x0347, 0x54 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3209 */ + { IMX_8BIT, 0x0349, 0x89 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2121 */ + { IMX_8BIT, 0x034B, 0x49 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x07 }, /* x_output_size[15:8]:1936 */ + { IMX_8BIT, 0x034D, 0x90 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x04 }, /* y_output_size[15:8]:1096 */ + { IMX_8BIT, 0x034F, 0x48 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x0C }, /* crop x:3146 */ + { IMX_8BIT, 0x0355, 0x4A }, + { IMX_8BIT, 0x0356, 0x06 }, /* xrop y:1782 */ + { IMX_8BIT, 0x0357, 0xF6 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x07 }, + { IMX_8BIT, 0x3311, 0x80 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0x38 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0x1E }, + { IMX_8BIT, 0x4084, 0x07 }, + { IMX_8BIT, 0x4085, 0x80 }, + { IMX_8BIT, 0x4086, 0x04 }, + { IMX_8BIT, 0x4087, 0x38 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane 1920x1080, 30fps, for 720p still capture, vendor provide */ +static struct imx_reg const imx134_1936_1096_30fps_v2[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, /* disable binning */ + { IMX_8BIT, 0x0391, 0x11 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x1B }, /* downscaling 16/27*/ + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* Optionnal Function setting */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:64 */ + { IMX_8BIT, 0x0345, 0x06 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:340 */ + { IMX_8BIT, 0x0347, 0x34 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3209 */ + { IMX_8BIT, 0x0349, 0xC9 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2121 */ + { IMX_8BIT, 0x034B, 0x6F }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x07 }, /* x_output_size[15:8]:1936 */ + { IMX_8BIT, 0x034D, 0x90 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x04 }, /* y_output_size[15:8]:1096 */ + { IMX_8BIT, 0x034F, 0x48 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x0C }, /* crop x:3146 */ + { IMX_8BIT, 0x0355, 0xC4 }, + { IMX_8BIT, 0x0356, 0x07 }, /* xrop y:1782 */ + { IMX_8BIT, 0x0357, 0x3A }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x07 }, /* decide by mode and output size */ + { IMX_8BIT, 0x3311, 0x90 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0x48 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0x1E }, + { IMX_8BIT, 0x4084, 0x07 }, + { IMX_8BIT, 0x4085, 0x90 }, + { IMX_8BIT, 0x4086, 0x04 }, + { IMX_8BIT, 0x4087, 0x48 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Setting */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane 1296x736, 30fps, for 720p still capture, vendor provide */ +static struct imx_reg const imx134_1296_736_30fps_v2[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning */ + { IMX_8BIT, 0x0391, 0x22 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x14 }, + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* OptionnalFunction settig */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:40 */ + { IMX_8BIT, 0x0345, 0x14 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:332 */ + { IMX_8BIT, 0x0347, 0x38 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3239 */ + { IMX_8BIT, 0x0349, 0xBB }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2131 */ + { IMX_8BIT, 0x034B, 0x67 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x05 }, /* x_output_size[15:8]:1280 */ + { IMX_8BIT, 0x034D, 0x10 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x02 }, /* y_output_size[15:8]:720 */ + { IMX_8BIT, 0x034F, 0xE0 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x06 }, + { IMX_8BIT, 0x0355, 0x54 }, + { IMX_8BIT, 0x0356, 0x03 }, + { IMX_8BIT, 0x0357, 0x98 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x05 }, + { IMX_8BIT, 0x3311, 0x10 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0xE0 }, + { IMX_8BIT, 0x331C, 0x01 }, + { IMX_8BIT, 0x331D, 0x10 }, + { IMX_8BIT, 0x4084, 0x05 }, + { IMX_8BIT, 0x4085, 0x10 }, + { IMX_8BIT, 0x4086, 0x02 }, + { IMX_8BIT, 0x4087, 0xE0 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Settin */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +/* 4 lane 1280x720, 30fps, for 720p dvs, vendor provide */ +static struct imx_reg const imx134_1568_880_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xA9 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning*/ + { IMX_8BIT, 0x0391, 0x22 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, /* down scaling 16/16 = 1 */ + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* OptionnalFunction settig */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:72 */ + { IMX_8BIT, 0x0345, 0x48 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:356 */ + { IMX_8BIT, 0x0347, 0x64 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3207 */ + { IMX_8BIT, 0x0349, 0x87 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2115 */ + { IMX_8BIT, 0x034B, 0x43 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x06 }, /* x_output_size[15:8]:1568 */ + { IMX_8BIT, 0x034D, 0x20 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x03 }, /* y_output_size[15:8]:880 */ + { IMX_8BIT, 0x034F, 0x70 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x06 }, + { IMX_8BIT, 0x0355, 0x20 }, + { IMX_8BIT, 0x0356, 0x03 }, + { IMX_8BIT, 0x0357, 0x70 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x06 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x03 }, + { IMX_8BIT, 0x3313, 0x70 }, + { IMX_8BIT, 0x331C, 0x03 }, + { IMX_8BIT, 0x331D, 0xF2 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xAF }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Settin */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +static struct imx_reg const imx134_1568_876_60fps_0625[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0x8F }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning*/ + { IMX_8BIT, 0x0391, 0x22 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, /* down scaling 16/16 = 1 */ + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* OptionnalFunction settig */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:72 */ + { IMX_8BIT, 0x0345, 0x48 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:356 */ + { IMX_8BIT, 0x0347, 0x64 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3207 */ + { IMX_8BIT, 0x0349, 0x87 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2115 */ + { IMX_8BIT, 0x034B, 0x3B }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x06 }, /* x_output_size[15:8]:1568 */ + { IMX_8BIT, 0x034D, 0x20 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x03 }, /* y_output_size[15:8]:880 */ + { IMX_8BIT, 0x034F, 0x6C }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x06 }, + { IMX_8BIT, 0x0355, 0x20 }, + { IMX_8BIT, 0x0356, 0x03 }, + { IMX_8BIT, 0x0357, 0x6C }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x06 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x03 }, + { IMX_8BIT, 0x3313, 0x6C }, + { IMX_8BIT, 0x331C, 0x03 }, + { IMX_8BIT, 0x331D, 0xF2 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x6F }, + { IMX_8BIT, 0x0831, 0x27 }, + { IMX_8BIT, 0x0832, 0x4F }, + { IMX_8BIT, 0x0833, 0x2F }, + { IMX_8BIT, 0x0834, 0x2F }, + { IMX_8BIT, 0x0835, 0x2F }, + { IMX_8BIT, 0x0836, 0x9F }, + { IMX_8BIT, 0x0837, 0x37 }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Settin */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + + +/* 4 lane for 720p dvs, vendor provide */ +static struct imx_reg const imx134_1568_880[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xC8 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning*/ + { IMX_8BIT, 0x0391, 0x22 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, /* down scaling 16/16 = 1 */ + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* OptionnalFunction settig */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:72 */ + { IMX_8BIT, 0x0345, 0x48 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x01 }, /* y_addr_start[15:8]:356 */ + { IMX_8BIT, 0x0347, 0x64 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3207 */ + { IMX_8BIT, 0x0349, 0x87 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x08 }, /* y_addr_end[15:8]:2115 */ + { IMX_8BIT, 0x034B, 0x43 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x06 }, /* x_output_size[15:8]:1568 */ + { IMX_8BIT, 0x034D, 0x20 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x03 }, /* y_output_size[15:8]:880 */ + { IMX_8BIT, 0x034F, 0x70 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x06 }, + { IMX_8BIT, 0x0355, 0x20 }, + { IMX_8BIT, 0x0356, 0x03 }, + { IMX_8BIT, 0x0357, 0x70 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x06 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x03 }, + { IMX_8BIT, 0x3313, 0x70 }, + { IMX_8BIT, 0x331C, 0x03 }, + { IMX_8BIT, 0x331D, 0xF2 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x5F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x37 }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xBF }, + { IMX_8BIT, 0x0837, 0x3F }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + + /* Integration Time Settin */ + { IMX_8BIT, 0x0202, 0x09 }, + { IMX_8BIT, 0x0203, 0xD2 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; +/* 4 lane for 480p dvs, default 60fps, vendor provide */ +static struct imx_reg const imx134_880_592[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xC8 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, /* binning*/ + { IMX_8BIT, 0x0391, 0x22 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x1D }, /* downscaling ratio = 16/29 */ + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* OptionnalFunction settig */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* x_addr_start[15:8]:44 */ + { IMX_8BIT, 0x0345, 0x2C }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x00 }, /* y_addr_start[15:8]:160 */ + { IMX_8BIT, 0x0347, 0xA0 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0C }, /* x_addr_end[15:8]:3235 */ + { IMX_8BIT, 0x0349, 0xA3 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x09 }, /* y_addr_end[15:8]:2307 */ + { IMX_8BIT, 0x034B, 0x03 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x03 }, /* x_output_size[15:8]:880 */ + { IMX_8BIT, 0x034D, 0x70 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x02 }, /* y_output_size[15:8]:592 */ + { IMX_8BIT, 0x034F, 0x50 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x06 }, + { IMX_8BIT, 0x0355, 0x3C }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0x32 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x03 }, + { IMX_8BIT, 0x3311, 0x70 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0x50 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0x4C }, + { IMX_8BIT, 0x4084, 0x03 }, + { IMX_8BIT, 0x4085, 0x70 }, + { IMX_8BIT, 0x4086, 0x02 }, + { IMX_8BIT, 0x4087, 0x50 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x5F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x37 }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xBF }, + { IMX_8BIT, 0x0837, 0x3F }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + + /* Integration Time Settin */ + { IMX_8BIT, 0x0202, 0x05 }, + { IMX_8BIT, 0x0203, 0x42 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; +static struct imx_reg const imx134_2336_1308_60fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + /* mode set clear */ + { IMX_8BIT, 0x3A43, 0x01 }, + /* Clock Setting */ + { IMX_8BIT, 0x011E, 0x13 }, + { IMX_8BIT, 0x011F, 0x33 }, + { IMX_8BIT, 0x0301, 0x05 }, + { IMX_8BIT, 0x0303, 0x01 }, + { IMX_8BIT, 0x0305, 0x0C }, + { IMX_8BIT, 0x0309, 0x05 }, + { IMX_8BIT, 0x030B, 0x01 }, + { IMX_8BIT, 0x030C, 0x01 }, + { IMX_8BIT, 0x030D, 0xC8 }, + { IMX_8BIT, 0x030E, 0x01 }, + { IMX_8BIT, 0x3A06, 0x11 }, + + /* Mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, /* binning*/ + { IMX_8BIT, 0x0391, 0x11 }, /* 2x2 binning */ + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, /* H/V resize */ + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, /* down scaling 16/16 = 1 */ + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + + /* OptionnalFunction settig */ + { IMX_8BIT, 0x0700, 0x00 }, + { IMX_8BIT, 0x3A63, 0x00 }, + { IMX_8BIT, 0x4100, 0xF8 }, + { IMX_8BIT, 0x4203, 0xFF }, + { IMX_8BIT, 0x4344, 0x00 }, + { IMX_8BIT, 0x441C, 0x01 }, + + /* Size setting */ + { IMX_8BIT, 0x0344, 0x01 }, /* x_addr_start[15:8]:72 */ + { IMX_8BIT, 0x0345, 0xD8 }, /* x_addr_start[7:0] */ + { IMX_8BIT, 0x0346, 0x02 }, /* y_addr_start[15:8]:356 */ + { IMX_8BIT, 0x0347, 0x44 }, /* y_addr_start[7:0] */ + { IMX_8BIT, 0x0348, 0x0A }, /* x_addr_end[15:8]:3207 */ + { IMX_8BIT, 0x0349, 0xF7 }, /* x_addr_end[7:0] */ + { IMX_8BIT, 0x034A, 0x07 }, /* y_addr_end[15:8]:2107 */ + { IMX_8BIT, 0x034B, 0x5F+4 }, /* y_addr_end[7:0] */ + { IMX_8BIT, 0x034C, 0x09 }, /* x_output_size[15:8]:1568 */ + { IMX_8BIT, 0x034D, 0x20 }, /* x_output_size[7:0] */ + { IMX_8BIT, 0x034E, 0x05 }, /* y_output_size[15:8]:876 */ + { IMX_8BIT, 0x034F, 0x1C+4 }, /* y_output_size[7:0] */ + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x09 }, + { IMX_8BIT, 0x0355, 0x20 }, + { IMX_8BIT, 0x0356, 0x05 }, + { IMX_8BIT, 0x0357, 0x1C+4 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x09 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x05 }, + { IMX_8BIT, 0x3313, 0x1C+4 }, + { IMX_8BIT, 0x331C, 0x03 }, + { IMX_8BIT, 0x331D, 0xE8 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + + /* Global Timing Setting */ + { IMX_8BIT, 0x0830, 0x77 }, + { IMX_8BIT, 0x0831, 0x2F }, + { IMX_8BIT, 0x0832, 0x5F }, + { IMX_8BIT, 0x0833, 0x37 }, + { IMX_8BIT, 0x0834, 0x37 }, + { IMX_8BIT, 0x0835, 0x37 }, + { IMX_8BIT, 0x0836, 0xBF }, + { IMX_8BIT, 0x0837, 0x3F }, + { IMX_8BIT, 0x0839, 0x1F }, + { IMX_8BIT, 0x083A, 0x17 }, + { IMX_8BIT, 0x083B, 0x02 }, + + /* Integration Time Settin */ + { IMX_8BIT, 0x0202, 0x05 }, + { IMX_8BIT, 0x0203, 0x42 }, + + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00 }, + { IMX_8BIT, 0x0231, 0x00 }, + { IMX_8BIT, 0x0233, 0x00 }, + { IMX_8BIT, 0x0234, 0x00 }, + { IMX_8BIT, 0x0235, 0x40 }, + { IMX_8BIT, 0x0238, 0x00 }, + { IMX_8BIT, 0x0239, 0x04 }, + { IMX_8BIT, 0x023B, 0x00 }, + { IMX_8BIT, 0x023C, 0x01 }, + { IMX_8BIT, 0x33B0, 0x04 }, + { IMX_8BIT, 0x33B1, 0x00 }, + { IMX_8BIT, 0x33B3, 0x00 }, + { IMX_8BIT, 0x33B4, 0x01 }, + { IMX_8BIT, 0x3800, 0x00 }, + { IMX_TOK_TERM, 0, 0 } +}; + +struct imx_resolution imx134_res_preview[] = { + { + .desc = "imx134_CIF_30fps", + .regs = imx134_720_592_30fps, + .width = 720, + .height = 592, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + }, + { + .desc = "imx134_820_552_30fps_preview", + .regs = imx134_820_552_30fps, + .width = 820, + .height = 552, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + }, + { + .desc = "imx134_820_616_preview_30fps", + .regs = imx134_820_616_30fps, + .width = 820, + .height = 616, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + }, + { + .desc = "imx134_1080p_preview_30fps", + .regs = imx134_1936_1096_30fps_v2, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, + { + .desc = "imx134_1640_1232_preview_30fps", + .regs = imx134_1640_1232_30fps, + .width = 1640, + .height = 1232, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_8M_preview_30fps", + .regs = imx134_8M_30fps, + .width = 3280, + .height = 2464, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, +}; + +struct imx_resolution imx134_res_still[] = { + { + .desc = "imx134_CIF_30fps", + .regs = imx134_1424_1168_30fps, + .width = 1424, + .height = 1168, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_VGA_still_30fps", + .regs = imx134_1640_1232_30fps, + .width = 1640, + .height = 1232, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_1080p_still_30fps", + .regs = imx134_1936_1096_30fps_v2, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, + { + .desc = "imx134_1640_1232_still_30fps", + .regs = imx134_1640_1232_30fps, + .width = 1640, + .height = 1232, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_8M_still_30fps", + .regs = imx134_8M_30fps, + .width = 3280, + .height = 2464, + .fps_options = { + { + /* WORKAROUND for FW performance limitation */ + .fps = 8, + .pixels_per_line = 6400, + .lines_per_frame = 5312, + }, + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, +}; + +struct imx_resolution imx134_res_video[] = { + { + .desc = "imx134_QCIF_DVS_30fps", + .regs = imx134_240_196_30fps, + .width = 240, + .height = 196, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + }, + { + .desc = "imx134_CIF_DVS_30fps", + .regs = imx134_448_366_30fps, + .width = 448, + .height = 366, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_VGA_30fps", + .regs = imx134_820_616_30fps, + .width = 820, + .height = 616, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + }, + { + .desc = "imx134_480p", + .regs = imx134_880_592, + .width = 880, + .height = 592, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2700, + }, + { + .fps = 60, + .pixels_per_line = 3600, + .lines_per_frame = 1350, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_1568_880", + .regs = imx134_1568_880, + .width = 1568, + .height = 880, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2700, + }, + { + .fps = 60, + .pixels_per_line = 3600, + .lines_per_frame = 1350, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + }, + { + .desc = "imx134_1080p_dvs_30fps", + .regs = imx134_2336_1312_30fps, + .width = 2336, + .height = 1312, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, + { + .desc = "imx134_1080p_dvs_60fps", + .regs = imx134_2336_1308_60fps, + .width = 2336, + .height = 1312, + .fps_options = { + { + .fps = 60, + .pixels_per_line = 3600, + .lines_per_frame = 1350, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, + { + /*This setting only be used for SDV mode*/ + .desc = "imx134_8M_sdv_30fps", + .regs = imx134_8M_30fps, + .width = 3280, + .height = 2464, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3600, + .lines_per_frame = 2518, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + }, +}; + +#endif + diff --git a/drivers/staging/media/atomisp/i2c/imx/imx135.h b/drivers/staging/media/atomisp/i2c/imx/imx135.h new file mode 100644 index 0000000000000000000000000000000000000000..58b43af909f287ebb9bd9e69a9cedb3f11f97ce9 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx135.h @@ -0,0 +1,3374 @@ +/* + * Support for Sony IMX camera sensor. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __IMX135_H__ +#define __IMX135_H__ + +#include "common.h" + +#define IMX_SC_CMMN_CHIP_ID_H 0x0016 +#define IMX_SC_CMMN_CHIP_ID_L 0x0017 + +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define IMX_FOCAL_LENGTH_DEFAULT 0x1710064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define IMX_F_NUMBER_DEFAULT 0x16000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define IMX_F_NUMBER_RANGE 0x160a160a + +#define GROUPED_PARAMETER_HOLD_ENABLE {IMX_8BIT, 0x0104, 0x1} +#define GROUPED_PARAMETER_HOLD_DISABLE {IMX_8BIT, 0x0104, 0x0} + +#define IMX135_EMBEDDED_DATA_LINE_NUM 2 +#define IMX135_OUTPUT_DATA_FORMAT_REG 0x0112 +#define IMX135_OUTPUT_FORMAT_RAW10 0x0a0a +/* + * We use three different MIPI rates for our modes based on the resolution and + * FPS requirements. So we have three PLL configurationa and these are based + * on the EMC friendly MIPI values. + * + * Maximum clock: Pix clock @ 360.96MHz MIPI @ 451.2MHz 902.4mbps + * Reduced clock: Pix clock @ 273.00MHz MIPI @ 342.0MHz 684.0mbps + * Binning modes: Pix clock @ 335.36MHz MIPI @ 209.6MHz 419.2mbps + * Global Timing registers are based on the data rates and these are part of + * the below clock definitions. + */ +/* MIPI 499.2MHz 998.4mbps PIXCLK: 399.36MHz */ +#define PLL_SETTINGS_FOR_MIPI_499_2MHZ_SALTBAY \ + {IMX_8BIT, 0x011e, 0x13}, \ + {IMX_8BIT, 0x011f, 0x33}, \ + {IMX_8BIT, 0x0301, 0x05}, \ + {IMX_8BIT, 0x0303, 0x01}, \ + {IMX_8BIT, 0x0305, 0x0c}, \ + {IMX_8BIT, 0x0309, 0x05}, \ + {IMX_8BIT, 0x030b, 0x01}, \ + {IMX_8BIT, 0x030c, 0x02}, \ + {IMX_8BIT, 0x030d, 0x70}, \ + {IMX_8BIT, 0x030e, 0x01}, \ + {IMX_8BIT, 0x3a06, 0x11}, \ + {IMX_8BIT, 0x0830, 0x7f}, \ + {IMX_8BIT, 0x0831, 0x37}, \ + {IMX_8BIT, 0x0832, 0x67}, \ + {IMX_8BIT, 0x0833, 0x3f}, \ + {IMX_8BIT, 0x0834, 0x3f}, \ + {IMX_8BIT, 0x0835, 0x47}, \ + {IMX_8BIT, 0x0836, 0xdf}, \ + {IMX_8BIT, 0x0837, 0x47}, \ + {IMX_8BIT, 0x0839, 0x1f}, \ + {IMX_8BIT, 0x083a, 0x17}, \ + {IMX_8BIT, 0x083b, 0x02} + +/* MIPI 451.2MHz 902.4mbps PIXCLK: 360.96MHz */ +#define PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY \ + {IMX_8BIT, 0x011e, 0x13}, \ + {IMX_8BIT, 0x011f, 0x33}, \ + {IMX_8BIT, 0x0301, 0x05}, \ + {IMX_8BIT, 0x0303, 0x01}, \ + {IMX_8BIT, 0x0305, 0x0c}, \ + {IMX_8BIT, 0x0309, 0x05}, \ + {IMX_8BIT, 0x030b, 0x01}, \ + {IMX_8BIT, 0x030c, 0x02}, \ + {IMX_8BIT, 0x030d, 0x34}, \ + {IMX_8BIT, 0x030e, 0x01}, \ + {IMX_8BIT, 0x3a06, 0x11}, \ + {IMX_8BIT, 0x0830, 0x7f}, \ + {IMX_8BIT, 0x0831, 0x37}, \ + {IMX_8BIT, 0x0832, 0x67}, \ + {IMX_8BIT, 0x0833, 0x3f}, \ + {IMX_8BIT, 0x0834, 0x3f}, \ + {IMX_8BIT, 0x0835, 0x47}, \ + {IMX_8BIT, 0x0836, 0xdf}, \ + {IMX_8BIT, 0x0837, 0x47}, \ + {IMX_8BIT, 0x0839, 0x1f}, \ + {IMX_8BIT, 0x083a, 0x17}, \ + {IMX_8BIT, 0x083b, 0x02} + +/* MIPI 209.6MHz, 419.2mbps PIXCLK: 335.36 MHz */ +#define PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY \ + {IMX_8BIT, 0x011e, 0x13}, \ + {IMX_8BIT, 0x011f, 0x33}, \ + {IMX_8BIT, 0x0301, 0x05}, \ + {IMX_8BIT, 0x0303, 0x01}, \ + {IMX_8BIT, 0x0305, 0x06}, \ + {IMX_8BIT, 0x0309, 0x05}, \ + {IMX_8BIT, 0x030b, 0x02}, \ + {IMX_8BIT, 0x030c, 0x01}, \ + {IMX_8BIT, 0x030d, 0x06}, \ + {IMX_8BIT, 0x030e, 0x01}, \ + {IMX_8BIT, 0x3a06, 0x12}, \ + {IMX_8BIT, 0x0830, 0x5f}, \ + {IMX_8BIT, 0x0831, 0x1f}, \ + {IMX_8BIT, 0x0832, 0x3f}, \ + {IMX_8BIT, 0x0833, 0x1f}, \ + {IMX_8BIT, 0x0834, 0x1f}, \ + {IMX_8BIT, 0x0835, 0x17}, \ + {IMX_8BIT, 0x0836, 0x67}, \ + {IMX_8BIT, 0x0837, 0x27}, \ + {IMX_8BIT, 0x0839, 0x1f}, \ + {IMX_8BIT, 0x083a, 0x17}, \ + {IMX_8BIT, 0x083b, 0x02} + +/* MIPI 342MHz 684mbps PIXCLK: 273.6MHz */ +#define PLL_SETTINGS_FOR_MIPI_342MHZ_SALTBAY \ + {IMX_8BIT, 0x011e, 0x13}, \ + {IMX_8BIT, 0x011f, 0x33}, \ + {IMX_8BIT, 0x0301, 0x05}, \ + {IMX_8BIT, 0x0303, 0x01}, \ + {IMX_8BIT, 0x0305, 0x08}, \ + {IMX_8BIT, 0x0309, 0x05}, \ + {IMX_8BIT, 0x030b, 0x01}, \ + {IMX_8BIT, 0x030c, 0x01}, \ + {IMX_8BIT, 0x030d, 0x1d}, \ + {IMX_8BIT, 0x030e, 0x01}, \ + {IMX_8BIT, 0x3a06, 0x11}, \ + {IMX_8BIT, 0x0830, 0x77}, \ + {IMX_8BIT, 0x0831, 0x2f}, \ + {IMX_8BIT, 0x0832, 0x4f}, \ + {IMX_8BIT, 0x0833, 0x37}, \ + {IMX_8BIT, 0x0834, 0x2f}, \ + {IMX_8BIT, 0x0835, 0x37}, \ + {IMX_8BIT, 0x0836, 0xa7}, \ + {IMX_8BIT, 0x0837, 0x37}, \ + {IMX_8BIT, 0x0839, 0x1f}, \ + {IMX_8BIT, 0x083a, 0x17}, \ + {IMX_8BIT, 0x083b, 0x02} + +/* Basic settings: Applied only once after the sensor power up */ +static struct imx_reg const imx135_init_settings[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + { IMX_8BIT, 0x0220, 0x01}, + { IMX_8BIT, 0x3008, 0xB0}, + { IMX_8BIT, 0x320A, 0x01}, + { IMX_8BIT, 0x320D, 0x10}, + { IMX_8BIT, 0x3216, 0x2E}, + { IMX_8BIT, 0x3230, 0x0A}, + { IMX_8BIT, 0x3228, 0x05}, + { IMX_8BIT, 0x3229, 0x02}, + { IMX_8BIT, 0x322C, 0x02}, + { IMX_8BIT, 0x3302, 0x10}, + { IMX_8BIT, 0x3390, 0x45}, + { IMX_8BIT, 0x3409, 0x0C}, + { IMX_8BIT, 0x340B, 0xF5}, + { IMX_8BIT, 0x340C, 0x2D}, + { IMX_8BIT, 0x3412, 0x41}, + { IMX_8BIT, 0x3413, 0xAD}, + { IMX_8BIT, 0x3414, 0x1E}, + { IMX_8BIT, 0x3427, 0x04}, + { IMX_8BIT, 0x3480, 0x1E}, + { IMX_8BIT, 0x3484, 0x1E}, + { IMX_8BIT, 0x3488, 0x1E}, + { IMX_8BIT, 0x348C, 0x1E}, + { IMX_8BIT, 0x3490, 0x1E}, + { IMX_8BIT, 0x3494, 0x1E}, + { IMX_8BIT, 0x349C, 0x38}, + { IMX_8BIT, 0x34A3, 0x38}, + { IMX_8BIT, 0x3511, 0x8F}, + { IMX_8BIT, 0x3518, 0x00}, + { IMX_8BIT, 0x3519, 0x94}, + { IMX_8BIT, 0x3833, 0x20}, + { IMX_8BIT, 0x3893, 0x01}, + { IMX_8BIT, 0x38C2, 0x08}, + { IMX_8BIT, 0x38C3, 0x08}, + { IMX_8BIT, 0x3C09, 0x01}, + { IMX_8BIT, 0x4000, 0x0E}, + { IMX_8BIT, 0x4300, 0x00}, + { IMX_8BIT, 0x4316, 0x12}, + { IMX_8BIT, 0x4317, 0x22}, + { IMX_8BIT, 0x4318, 0x00}, + { IMX_8BIT, 0x4319, 0x00}, + { IMX_8BIT, 0x431A, 0x00}, + { IMX_8BIT, 0x4324, 0x03}, + { IMX_8BIT, 0x4325, 0x20}, + { IMX_8BIT, 0x4326, 0x03}, + { IMX_8BIT, 0x4327, 0x84}, + { IMX_8BIT, 0x4328, 0x03}, + { IMX_8BIT, 0x4329, 0x20}, + { IMX_8BIT, 0x432A, 0x03}, + { IMX_8BIT, 0x432B, 0x84}, + { IMX_8BIT, 0x432C, 0x01}, + { IMX_8BIT, 0x4401, 0x3F}, + { IMX_8BIT, 0x4402, 0xFF}, + { IMX_8BIT, 0x4412, 0x3F}, + { IMX_8BIT, 0x4413, 0xFF}, + { IMX_8BIT, 0x441D, 0x28}, + { IMX_8BIT, 0x4444, 0x00}, + { IMX_8BIT, 0x4445, 0x00}, + { IMX_8BIT, 0x4446, 0x3F}, + { IMX_8BIT, 0x4447, 0xFF}, + { IMX_8BIT, 0x4452, 0x00}, + { IMX_8BIT, 0x4453, 0xA0}, + { IMX_8BIT, 0x4454, 0x08}, + { IMX_8BIT, 0x4455, 0x00}, + { IMX_8BIT, 0x4458, 0x18}, + { IMX_8BIT, 0x4459, 0x18}, + { IMX_8BIT, 0x445A, 0x3F}, + { IMX_8BIT, 0x445B, 0x3A}, + { IMX_8BIT, 0x4462, 0x00}, + { IMX_8BIT, 0x4463, 0x00}, + { IMX_8BIT, 0x4464, 0x00}, + { IMX_8BIT, 0x4465, 0x00}, + { IMX_8BIT, 0x446E, 0x01}, + { IMX_8BIT, 0x4500, 0x1F}, + { IMX_8BIT, 0x600a, 0x00}, + { IMX_8BIT, 0x380a, 0x00}, + { IMX_8BIT, 0x380b, 0x00}, + { IMX_8BIT, 0x4103, 0x00}, + { IMX_8BIT, 0x4243, 0x9a}, + { IMX_8BIT, 0x4330, 0x01}, + { IMX_8BIT, 0x4331, 0x90}, + { IMX_8BIT, 0x4332, 0x02}, + { IMX_8BIT, 0x4333, 0x58}, + { IMX_8BIT, 0x4334, 0x03}, + { IMX_8BIT, 0x4335, 0x20}, + { IMX_8BIT, 0x4336, 0x03}, + { IMX_8BIT, 0x4337, 0x84}, + { IMX_8BIT, 0x433C, 0x01}, + { IMX_8BIT, 0x4340, 0x02}, + { IMX_8BIT, 0x4341, 0x58}, + { IMX_8BIT, 0x4342, 0x03}, + { IMX_8BIT, 0x4343, 0x52}, + { IMX_8BIT, 0x4364, 0x0b}, + { IMX_8BIT, 0x4368, 0x00}, + { IMX_8BIT, 0x4369, 0x0f}, + { IMX_8BIT, 0x436a, 0x03}, + { IMX_8BIT, 0x436b, 0xa8}, + { IMX_8BIT, 0x436c, 0x00}, + { IMX_8BIT, 0x436d, 0x00}, + { IMX_8BIT, 0x436e, 0x00}, + { IMX_8BIT, 0x436f, 0x06}, + { IMX_8BIT, 0x4281, 0x21}, + { IMX_8BIT, 0x4282, 0x18}, + { IMX_8BIT, 0x4283, 0x04}, + { IMX_8BIT, 0x4284, 0x08}, + { IMX_8BIT, 0x4287, 0x7f}, + { IMX_8BIT, 0x4288, 0x08}, + { IMX_8BIT, 0x428c, 0x08}, + { IMX_8BIT, 0x4297, 0x00}, + { IMX_8BIT, 0x4299, 0x7E}, + { IMX_8BIT, 0x42A4, 0xFB}, + { IMX_8BIT, 0x42A5, 0x7E}, + { IMX_8BIT, 0x42A6, 0xDF}, + { IMX_8BIT, 0x42A7, 0xB7}, + { IMX_8BIT, 0x42AF, 0x03}, + { IMX_8BIT, 0x4207, 0x03}, + { IMX_8BIT, 0x4218, 0x00}, + { IMX_8BIT, 0x421B, 0x20}, + { IMX_8BIT, 0x421F, 0x04}, + { IMX_8BIT, 0x4222, 0x02}, + { IMX_8BIT, 0x4223, 0x22}, + { IMX_8BIT, 0x422E, 0x54}, + { IMX_8BIT, 0x422F, 0xFB}, + { IMX_8BIT, 0x4230, 0xFF}, + { IMX_8BIT, 0x4231, 0xFE}, + { IMX_8BIT, 0x4232, 0xFF}, + { IMX_8BIT, 0x4235, 0x58}, + { IMX_8BIT, 0x4236, 0xF7}, + { IMX_8BIT, 0x4237, 0xFD}, + { IMX_8BIT, 0x4239, 0x4E}, + { IMX_8BIT, 0x423A, 0xFC}, + { IMX_8BIT, 0x423B, 0xFD}, + { IMX_8BIT, 0x4300, 0x00}, + { IMX_8BIT, 0x4316, 0x12}, + { IMX_8BIT, 0x4317, 0x22}, + { IMX_8BIT, 0x4318, 0x00}, + { IMX_8BIT, 0x4319, 0x00}, + { IMX_8BIT, 0x431A, 0x00}, + { IMX_8BIT, 0x4324, 0x03}, + { IMX_8BIT, 0x4325, 0x20}, + { IMX_8BIT, 0x4326, 0x03}, + { IMX_8BIT, 0x4327, 0x84}, + { IMX_8BIT, 0x4328, 0x03}, + { IMX_8BIT, 0x4329, 0x20}, + { IMX_8BIT, 0x432A, 0x03}, + { IMX_8BIT, 0x432B, 0x20}, + { IMX_8BIT, 0x432C, 0x01}, + { IMX_8BIT, 0x432D, 0x01}, + { IMX_8BIT, 0x4338, 0x02}, + { IMX_8BIT, 0x4339, 0x00}, + { IMX_8BIT, 0x433A, 0x00}, + { IMX_8BIT, 0x433B, 0x02}, + { IMX_8BIT, 0x435A, 0x03}, + { IMX_8BIT, 0x435B, 0x84}, + { IMX_8BIT, 0x435E, 0x01}, + { IMX_8BIT, 0x435F, 0xFF}, + { IMX_8BIT, 0x4360, 0x01}, + { IMX_8BIT, 0x4361, 0xF4}, + { IMX_8BIT, 0x4362, 0x03}, + { IMX_8BIT, 0x4363, 0x84}, + { IMX_8BIT, 0x437B, 0x01}, + { IMX_8BIT, 0x4400, 0x00}, /* STATS off ISP do not support STATS*/ + { IMX_8BIT, 0x4401, 0x3F}, + { IMX_8BIT, 0x4402, 0xFF}, + { IMX_8BIT, 0x4404, 0x13}, + { IMX_8BIT, 0x4405, 0x26}, + { IMX_8BIT, 0x4406, 0x07}, + { IMX_8BIT, 0x4408, 0x20}, + { IMX_8BIT, 0x4409, 0xE5}, + { IMX_8BIT, 0x440A, 0xFB}, + { IMX_8BIT, 0x440C, 0xF6}, + { IMX_8BIT, 0x440D, 0xEA}, + { IMX_8BIT, 0x440E, 0x20}, + { IMX_8BIT, 0x4410, 0x00}, + { IMX_8BIT, 0x4411, 0x00}, + { IMX_8BIT, 0x4412, 0x3F}, + { IMX_8BIT, 0x4413, 0xFF}, + { IMX_8BIT, 0x4414, 0x1F}, + { IMX_8BIT, 0x4415, 0xFF}, + { IMX_8BIT, 0x4416, 0x20}, + { IMX_8BIT, 0x4417, 0x00}, + { IMX_8BIT, 0x4418, 0x1F}, + { IMX_8BIT, 0x4419, 0xFF}, + { IMX_8BIT, 0x441A, 0x20}, + { IMX_8BIT, 0x441B, 0x00}, + { IMX_8BIT, 0x441D, 0x40}, + { IMX_8BIT, 0x441E, 0x1E}, + { IMX_8BIT, 0x441F, 0x38}, + { IMX_8BIT, 0x4420, 0x01}, + { IMX_8BIT, 0x4444, 0x00}, + { IMX_8BIT, 0x4445, 0x00}, + { IMX_8BIT, 0x4446, 0x1D}, + { IMX_8BIT, 0x4447, 0xF9}, + { IMX_8BIT, 0x4452, 0x00}, + { IMX_8BIT, 0x4453, 0xA0}, + { IMX_8BIT, 0x4454, 0x08}, + { IMX_8BIT, 0x4455, 0x00}, + { IMX_8BIT, 0x4456, 0x0F}, + { IMX_8BIT, 0x4457, 0xFF}, + { IMX_8BIT, 0x4458, 0x18}, + { IMX_8BIT, 0x4459, 0x18}, + { IMX_8BIT, 0x445A, 0x3F}, + { IMX_8BIT, 0x445B, 0x3A}, + { IMX_8BIT, 0x445C, 0x00}, + { IMX_8BIT, 0x445D, 0x28}, + { IMX_8BIT, 0x445E, 0x01}, + { IMX_8BIT, 0x445F, 0x90}, + { IMX_8BIT, 0x4460, 0x00}, + { IMX_8BIT, 0x4461, 0x60}, + { IMX_8BIT, 0x4462, 0x00}, + { IMX_8BIT, 0x4463, 0x00}, + { IMX_8BIT, 0x4464, 0x00}, + { IMX_8BIT, 0x4465, 0x00}, + { IMX_8BIT, 0x446C, 0x00}, + { IMX_8BIT, 0x446D, 0x00}, + { IMX_8BIT, 0x446E, 0x00}, + { IMX_8BIT, 0x452A, 0x02}, + { IMX_8BIT, 0x0712, 0x01}, + { IMX_8BIT, 0x0713, 0x00}, + { IMX_8BIT, 0x0714, 0x01}, + { IMX_8BIT, 0x0715, 0x00}, + { IMX_8BIT, 0x0716, 0x01}, + { IMX_8BIT, 0x0717, 0x00}, + { IMX_8BIT, 0x0718, 0x01}, + { IMX_8BIT, 0x0719, 0x00}, + { IMX_8BIT, 0x4500, 0x1F }, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + { IMX_8BIT, 0x0205, 0x00}, + { IMX_8BIT, 0x020E, 0x01}, + { IMX_8BIT, 0x020F, 0x00}, + { IMX_8BIT, 0x0210, 0x02}, + { IMX_8BIT, 0x0211, 0x00}, + { IMX_8BIT, 0x0212, 0x02}, + { IMX_8BIT, 0x0213, 0x00}, + { IMX_8BIT, 0x0214, 0x01}, + { IMX_8BIT, 0x0215, 0x00}, + /* HDR Setting */ + { IMX_8BIT, 0x0230, 0x00}, + { IMX_8BIT, 0x0231, 0x00}, + { IMX_8BIT, 0x0233, 0x00}, + { IMX_8BIT, 0x0234, 0x00}, + { IMX_8BIT, 0x0235, 0x40}, + { IMX_8BIT, 0x0238, 0x00}, + { IMX_8BIT, 0x0239, 0x04}, + { IMX_8BIT, 0x023B, 0x00}, + { IMX_8BIT, 0x023C, 0x01}, + { IMX_8BIT, 0x33B0, 0x04}, + { IMX_8BIT, 0x33B1, 0x00}, + { IMX_8BIT, 0x33B3, 0x00}, + { IMX_8BIT, 0x33B4, 0x01}, + { IMX_8BIT, 0x3800, 0x00}, + GROUPED_PARAMETER_HOLD_DISABLE, + { IMX_TOK_TERM, 0, 0} +}; + +/********* Preview, continuous capture and still modes *****************/ + +static struct imx_reg const imx135_13m[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size Setting */ + {IMX_8BIT, 0x0344, 0x00}, /* 0, 0, 4207,3119 4208x3120 */ + {IMX_8BIT, 0x0345, 0x00}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x00}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x6F}, + {IMX_8BIT, 0x034A, 0x0C}, + {IMX_8BIT, 0x034B, 0x2F}, + {IMX_8BIT, 0x034C, 0x10}, + {IMX_8BIT, 0x034D, 0x70}, + {IMX_8BIT, 0x034E, 0x0C}, + {IMX_8BIT, 0x034F, 0x30}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, /* 4208x3120 */ + {IMX_8BIT, 0x0355, 0x70}, + {IMX_8BIT, 0x0356, 0x0C}, + {IMX_8BIT, 0x0357, 0x30}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x10}, + {IMX_8BIT, 0x3311, 0x70}, + {IMX_8BIT, 0x3312, 0x0C}, + {IMX_8BIT, 0x3313, 0x30}, + {IMX_8BIT, 0x331C, 0x00}, + {IMX_8BIT, 0x331D, 0x10}, + {IMX_8BIT, 0x4084, 0x00}, /* If scaling, Fill this */ + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +/* 13MP reduced pixel clock MIPI 342MHz is EMC friendly*/ +static struct imx_reg const imx135_13m_for_mipi_342[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_342MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size Setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x00}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x00}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x6F}, + {IMX_8BIT, 0x034A, 0x0C}, + {IMX_8BIT, 0x034B, 0x2F}, + {IMX_8BIT, 0x034C, 0x10}, + {IMX_8BIT, 0x034D, 0x70}, + {IMX_8BIT, 0x034E, 0x0C}, + {IMX_8BIT, 0x034F, 0x30}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, + {IMX_8BIT, 0x0355, 0x70}, + {IMX_8BIT, 0x0356, 0x0C}, + {IMX_8BIT, 0x0357, 0x30}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x10}, + {IMX_8BIT, 0x3311, 0x70}, + {IMX_8BIT, 0x3312, 0x0C}, + {IMX_8BIT, 0x3313, 0x30}, + {IMX_8BIT, 0x331C, 0x00}, + {IMX_8BIT, 0x331D, 0x10}, + {IMX_8BIT, 0x4084, 0x00}, /* If scaling, Fill this */ + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_10m[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, /* 0, 376, 4207, 2743 */ + {IMX_8BIT, 0x0345, 0x00}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x78}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x6f}, + {IMX_8BIT, 0x034A, 0x0a}, + {IMX_8BIT, 0x034B, 0xb7}, + {IMX_8BIT, 0x034C, 0x10}, /* 4208x2368 */ + {IMX_8BIT, 0x034D, 0x70}, + {IMX_8BIT, 0x034E, 0x09}, + {IMX_8BIT, 0x034F, 0x40}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, + {IMX_8BIT, 0x0355, 0x70}, + {IMX_8BIT, 0x0356, 0x09}, + {IMX_8BIT, 0x0357, 0x40}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x10}, + {IMX_8BIT, 0x3311, 0x70}, + {IMX_8BIT, 0x3312, 0x09}, + {IMX_8BIT, 0x3313, 0x40}, + {IMX_8BIT, 0x331C, 0x01}, + {IMX_8BIT, 0x331D, 0x68}, + {IMX_8BIT, 0x4084, 0x00}, + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_10m_for_mipi_342[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_342MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, /* 0, 376, 4207, 2743 */ + {IMX_8BIT, 0x0345, 0x00}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x78}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x6f}, + {IMX_8BIT, 0x034A, 0x0a}, + {IMX_8BIT, 0x034B, 0xb7}, + {IMX_8BIT, 0x034C, 0x10}, /* 4208x2368 */ + {IMX_8BIT, 0x034D, 0x70}, + {IMX_8BIT, 0x034E, 0x09}, + {IMX_8BIT, 0x034F, 0x40}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, + {IMX_8BIT, 0x0355, 0x70}, + {IMX_8BIT, 0x0356, 0x09}, + {IMX_8BIT, 0x0357, 0x40}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x10}, + {IMX_8BIT, 0x3311, 0x70}, + {IMX_8BIT, 0x3312, 0x09}, + {IMX_8BIT, 0x3313, 0x40}, + {IMX_8BIT, 0x331C, 0x01}, + {IMX_8BIT, 0x331D, 0x68}, + {IMX_8BIT, 0x4084, 0x00}, + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * It is 8.5 DS from (3:2)8m cropped setting. + * + * The 8m(3:2) cropped setting is 2992x2448 effective res. + * The ISP effect cropped setting should be 1408x1152 effect res. + * + * Consider ISP 16x16 padding: + * sensor outputs 368x304 + * cropped region is 3128x2584 + */ +static struct imx_reg const imx135_368x304_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, /* no binning */ + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, /* resize */ + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x88}, /* 136/16=8.5 */ + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x02}, /* X_ADD_STA */ + {IMX_8BIT, 0x0345, 0x1C}, /* 540 */ + {IMX_8BIT, 0x0346, 0x01}, /* Y_ADD_STA */ + {IMX_8BIT, 0x0347, 0x0C}, /* 268 */ + {IMX_8BIT, 0x0348, 0x0E}, /* X_ADD_END */ + {IMX_8BIT, 0x0349, 0x53}, /* 3667 */ + {IMX_8BIT, 0x034A, 0x0B}, /* Y_ADD_END */ + {IMX_8BIT, 0x034B, 0x23}, /* 2851 */ + {IMX_8BIT, 0x034C, 0x01}, /* X_OUT_SIZE */ + {IMX_8BIT, 0x034D, 0x70}, /* 368 */ + {IMX_8BIT, 0x034E, 0x01}, /* Y_OUT_SIZE */ + {IMX_8BIT, 0x034F, 0x30}, /* 304 */ + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x0C}, /* Cut out siz same as the size after crop */ + {IMX_8BIT, 0x0355, 0x38}, + {IMX_8BIT, 0x0356, 0x0A}, + {IMX_8BIT, 0x0357, 0x18}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x01}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0x70}, + {IMX_8BIT, 0x3312, 0x01}, + {IMX_8BIT, 0x3313, 0x30}, + {IMX_8BIT, 0x331C, 0x02}, /* ?? */ + {IMX_8BIT, 0x331D, 0xD0}, + {IMX_8BIT, 0x4084, 0x01}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x70}, + {IMX_8BIT, 0x4086, 0x01}, + {IMX_8BIT, 0x4087, 0x30}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * It is 1/4 binning from 8m cropped setting. + * + * The 8m cropped setting is 3264x2448 effective res. + * The xga cropped setting should be 816x612 effect res. + * + * Consider ISP 16x16 padding: + * sensor outputs 832x628 + * cropped region is 3328x2512 + */ +static struct imx_reg const imx135_xga_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x01}, + {IMX_8BIT, 0x0391, 0x44}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, +/* {IMX_8BIT, 0x4203, 0xFF}, */ + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01}, /* X_ADD_STA */ + {IMX_8BIT, 0x0345, 0xB8}, /* 440 */ + {IMX_8BIT, 0x0346, 0x01}, /* Y_ADD_STA */ + {IMX_8BIT, 0x0347, 0x30}, /* 304 */ + {IMX_8BIT, 0x0348, 0x0E}, /* X_ADD_END */ + {IMX_8BIT, 0x0349, 0xB7}, /* 4207-440=3767 */ + {IMX_8BIT, 0x034A, 0x0A}, /* Y_ADD_END */ + {IMX_8BIT, 0x034B, 0xFF}, /* 3119-304=2815 */ + {IMX_8BIT, 0x034C, 0x03}, /* X_OUT_SIZE */ + {IMX_8BIT, 0x034D, 0x40}, /* 832 */ + {IMX_8BIT, 0x034E, 0x02}, /* Y_OUT_SIZE */ + {IMX_8BIT, 0x034F, 0x74}, /* 628 */ + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x03}, /* Cut out size same as the size after crop */ + {IMX_8BIT, 0x0355, 0x40}, + {IMX_8BIT, 0x0356, 0x02}, + {IMX_8BIT, 0x0357, 0x74}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x03}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0x40}, + {IMX_8BIT, 0x3312, 0x02}, + {IMX_8BIT, 0x3313, 0x74}, + {IMX_8BIT, 0x331C, 0x02}, /* ?? */ + {IMX_8BIT, 0x331D, 0x21}, + {IMX_8BIT, 0x4084, 0x03}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x40}, + {IMX_8BIT, 0x4086, 0x02}, + {IMX_8BIT, 0x4087, 0x74}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * It is 28/16 DS from (16:9)8m cropped setting. + * + * The 8m(16:9) cropped setting is 3360x1890 effective res. + * - this is larger then the expected 3264x1836 FOV + * + * Consider ISP 16x16 padding: + * sensor outputs 1936x1096 + * cropped region is 3388x1918 + */ +static struct imx_reg const imx135_1936x1096_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, /* no binning */ + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, /* resize */ + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x1C}, /* 28/16 */ + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01}, /* X_ADD_STA */ + {IMX_8BIT, 0x0345, 0x9A}, /* 410 */ + {IMX_8BIT, 0x0346, 0x02}, /* Y_ADD_STA */ + {IMX_8BIT, 0x0347, 0x58}, /* 600 */ + {IMX_8BIT, 0x0348, 0x0E}, /* X_ADD_END */ + {IMX_8BIT, 0x0349, 0xD5}, /* 3797 */ + {IMX_8BIT, 0x034A, 0x09}, /* Y_ADD_END */ + {IMX_8BIT, 0x034B, 0xD5}, /* 2517 */ + {IMX_8BIT, 0x034C, 0x07}, /* X_OUT_SIZE */ + {IMX_8BIT, 0x034D, 0x90}, /* 1936 */ + {IMX_8BIT, 0x034E, 0x04}, /* Y_OUT_SIZE */ + {IMX_8BIT, 0x034F, 0x48}, /* 1096 */ + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x0D}, /* Cut out siz same as the size after crop */ + {IMX_8BIT, 0x0355, 0x3C}, + {IMX_8BIT, 0x0356, 0x07}, + {IMX_8BIT, 0x0357, 0x7E}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x07}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0x90}, + {IMX_8BIT, 0x3312, 0x04}, + {IMX_8BIT, 0x3313, 0x48}, + {IMX_8BIT, 0x331C, 0x00}, /* ?? */ + {IMX_8BIT, 0x331D, 0xAA}, + {IMX_8BIT, 0x4084, 0x07}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x90}, + {IMX_8BIT, 0x4086, 0x04}, + {IMX_8BIT, 0x4087, 0x48}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * It is 2.125 DS from (3:2)8m cropped setting. + * + * The 8m(3:2) cropped setting is 2992x2448 effective res. + * The ISP effect cropped setting should be 1408x1152 effect res. + * + * Consider ISP 16x16 padding: + * sensor outputs 1424x1168 + * cropped region is 3026x2482 + */ +static struct imx_reg const imx135_1424x1168_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, /* no binning */ + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, /* resize */ + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x22}, /* 34/16=2.125 */ + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x02}, /* X_ADD_STA */ + {IMX_8BIT, 0x0345, 0x4E}, /* 590 */ + {IMX_8BIT, 0x0346, 0x01}, /* Y_ADD_STA */ + {IMX_8BIT, 0x0347, 0x3E}, /* 318 */ + {IMX_8BIT, 0x0348, 0x0E}, /* X_ADD_END */ + {IMX_8BIT, 0x0349, 0x1F}, /* 3615 */ + {IMX_8BIT, 0x034A, 0x0A}, /* Y_ADD_END */ + {IMX_8BIT, 0x034B, 0xEF}, /* 2799 */ + {IMX_8BIT, 0x034C, 0x05}, /* X_OUT_SIZE */ + {IMX_8BIT, 0x034D, 0x90}, /* 1424 */ + {IMX_8BIT, 0x034E, 0x04}, /* Y_OUT_SIZE */ + {IMX_8BIT, 0x034F, 0x90}, /* 1168 */ + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x0B}, /* Cut out siz same as the size after crop */ + {IMX_8BIT, 0x0355, 0xD2}, + {IMX_8BIT, 0x0356, 0x09}, + {IMX_8BIT, 0x0357, 0xB2}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x05}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0x90}, + {IMX_8BIT, 0x3312, 0x04}, + {IMX_8BIT, 0x3313, 0x90}, + {IMX_8BIT, 0x331C, 0x00}, /* ?? */ + {IMX_8BIT, 0x331D, 0xAA}, + {IMX_8BIT, 0x4084, 0x05}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x90}, + {IMX_8BIT, 0x4086, 0x04}, + {IMX_8BIT, 0x4087, 0x90}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * It is 1/2 binning from 8m cropped setting. + * + * The 8m cropped setting is 3264x2448 effective res. + * The 2m cropped setting should be 1632x1224 effect res. + * + * Consider ISP 16x16 padding: + * sensor outputs 1648x1240 + * cropped region is 3296x2480 + */ +static struct imx_reg const imx135_2m_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x01}, + {IMX_8BIT, 0x0391, 0x22}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01}, /* X_ADD_STA */ + {IMX_8BIT, 0x0345, 0xC8}, /* 464(1D0) -> 456(1C8)*/ + {IMX_8BIT, 0x0346, 0x01}, /* Y_ADD_STA */ + {IMX_8BIT, 0x0347, 0x40}, /* 320 */ + {IMX_8BIT, 0x0348, 0x0E}, /* X_ADD_END */ + {IMX_8BIT, 0x0349, 0xA7}, /* 4207-456=3751 */ + {IMX_8BIT, 0x034A, 0x0A}, /* Y_ADD_END */ + {IMX_8BIT, 0x034B, 0xEF}, /* 3119-320=2799 */ + {IMX_8BIT, 0x034C, 0x06}, /* X_OUT_SIZE */ + {IMX_8BIT, 0x034D, 0x70}, /* 1648 */ + {IMX_8BIT, 0x034E, 0x04}, /* Y_OUT_SIZE */ + {IMX_8BIT, 0x034F, 0xD8}, /* 1240 */ + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x06}, /* Cut out size same as the size after crop */ + {IMX_8BIT, 0x0355, 0x70}, + {IMX_8BIT, 0x0356, 0x04}, + {IMX_8BIT, 0x0357, 0xD8}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x06}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0x70}, + {IMX_8BIT, 0x3312, 0x04}, + {IMX_8BIT, 0x3313, 0xD8}, + {IMX_8BIT, 0x331C, 0x00}, /* ?? */ + {IMX_8BIT, 0x331D, 0xAA}, + {IMX_8BIT, 0x4084, 0x00}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * 8M Cropped 16:9 setting + * + * Effect res: 3264x1836 + * Sensor out: 3280x1852 + */ +static struct imx_reg const imx135_6m_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0xD0}, + {IMX_8BIT, 0x0346, 0x02}, /* 634 */ + {IMX_8BIT, 0x0347, 0x7A}, + {IMX_8BIT, 0x0348, 0x0E}, + {IMX_8BIT, 0x0349, 0x9F}, + {IMX_8BIT, 0x034A, 0x09}, /* 2485 */ + {IMX_8BIT, 0x034B, 0xB5}, + {IMX_8BIT, 0x034C, 0x0C}, /* 3280 */ + {IMX_8BIT, 0x034D, 0xD0}, + {IMX_8BIT, 0x034E, 0x07}, /* 1852 */ + {IMX_8BIT, 0x034F, 0x3C}, + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x0C}, /* Cut out size same as the size after crop */ + {IMX_8BIT, 0x0355, 0xD0}, + {IMX_8BIT, 0x0356, 0x07}, + {IMX_8BIT, 0x0357, 0x3C}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x0C}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0xD0}, + {IMX_8BIT, 0x3312, 0x07}, + {IMX_8BIT, 0x3313, 0x3C}, + {IMX_8BIT, 0x331C, 0x00}, /* ?? */ + {IMX_8BIT, 0x331D, 0x10}, + {IMX_8BIT, 0x4084, 0x00}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_8m_cropped[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0xD0}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x48}, + {IMX_8BIT, 0x0348, 0x0E}, + {IMX_8BIT, 0x0349, 0x9F}, + {IMX_8BIT, 0x034A, 0x0A}, + {IMX_8BIT, 0x034B, 0xE7}, + {IMX_8BIT, 0x034C, 0x0C}, /* 3280 */ + {IMX_8BIT, 0x034D, 0xD0}, + {IMX_8BIT, 0x034E, 0x09}, /* 2464 */ + {IMX_8BIT, 0x034F, 0xA0}, + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x0C}, /* Cut out size same as the size after crop */ + {IMX_8BIT, 0x0355, 0xD0}, + {IMX_8BIT, 0x0356, 0x09}, + {IMX_8BIT, 0x0357, 0xA0}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x0C}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0xD0}, + {IMX_8BIT, 0x3312, 0x09}, + {IMX_8BIT, 0x3313, 0xA0}, + {IMX_8BIT, 0x331C, 0x00}, /* ?? */ + {IMX_8BIT, 0x331D, 0x10}, + {IMX_8BIT, 0x4084, 0x00}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_8m_scaled_from_12m[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, /* Scaling */ + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x14}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x36}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x14}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x39}, + {IMX_8BIT, 0x034A, 0x0C}, + {IMX_8BIT, 0x034B, 0x1B}, + {IMX_8BIT, 0x034C, 0x0C}, /* 3280x2464 */ + {IMX_8BIT, 0x034D, 0xD0}, + {IMX_8BIT, 0x034E, 0x09}, + {IMX_8BIT, 0x034F, 0xA0}, + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, /* Cut out size same as the size after crop */ + {IMX_8BIT, 0x0355, 0x04}, + {IMX_8BIT, 0x0356, 0x0C}, + {IMX_8BIT, 0x0357, 0x08}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x0C}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0xD0}, + {IMX_8BIT, 0x3312, 0x09}, + {IMX_8BIT, 0x3313, 0xA0}, + {IMX_8BIT, 0x331C, 0x02}, /* ?? */ + {IMX_8BIT, 0x331D, 0xA0}, + {IMX_8BIT, 0x4084, 0x0C}, /* Scaling related? */ + {IMX_8BIT, 0x4085, 0xD0}, + {IMX_8BIT, 0x4086, 0x09}, + {IMX_8BIT, 0x4087, 0xA0}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_8m_scaled_from_12m_for_mipi342[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_342MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, /* Scaling */ + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x14}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x36}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x14}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x39}, + {IMX_8BIT, 0x034A, 0x0C}, + {IMX_8BIT, 0x034B, 0x1B}, + {IMX_8BIT, 0x034C, 0x0C}, /* 3280x2464 */ + {IMX_8BIT, 0x034D, 0xD0}, + {IMX_8BIT, 0x034E, 0x09}, + {IMX_8BIT, 0x034F, 0xA0}, + {IMX_8BIT, 0x0350, 0x00}, /* No Dig crop */ + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, /* Cut out size same as the size after crop */ + {IMX_8BIT, 0x0355, 0x04}, + {IMX_8BIT, 0x0356, 0x0C}, + {IMX_8BIT, 0x0357, 0x08}, + {IMX_8BIT, 0x301D, 0x30}, /* ?? */ + {IMX_8BIT, 0x3310, 0x0C}, /* Write H and V size same as output size? */ + {IMX_8BIT, 0x3311, 0xD0}, + {IMX_8BIT, 0x3312, 0x09}, + {IMX_8BIT, 0x3313, 0xA0}, + {IMX_8BIT, 0x331C, 0x02}, /* ?? */ + {IMX_8BIT, 0x331D, 0xA0}, + {IMX_8BIT, 0x4084, 0x0C}, /* Resize IMG Hand V size-> Scaling related?*/ + {IMX_8BIT, 0x4085, 0xD0}, + {IMX_8BIT, 0x4086, 0x09}, + {IMX_8BIT, 0x4087, 0xA0}, + {IMX_8BIT, 0x4400, 0x00}, /* STATS off */ + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_6m[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x14}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, /* 36, 194, 1039, a9f 4100x2316 */ + {IMX_8BIT, 0x0345, 0x36}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x94}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x39}, + {IMX_8BIT, 0x034A, 0x0A}, + {IMX_8BIT, 0x034B, 0x9F}, + {IMX_8BIT, 0x034C, 0x0C}, /* 3280x1852 */ + {IMX_8BIT, 0x034D, 0xD0}, + {IMX_8BIT, 0x034E, 0x07}, + {IMX_8BIT, 0x034F, 0x3C}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, /* 4100x2316 */ + {IMX_8BIT, 0x0355, 0x04}, + {IMX_8BIT, 0x0356, 0x09}, + {IMX_8BIT, 0x0357, 0x0C}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x0C}, + {IMX_8BIT, 0x3311, 0xD0}, + {IMX_8BIT, 0x3312, 0x07}, + {IMX_8BIT, 0x3313, 0x3C}, + {IMX_8BIT, 0x331C, 0x02}, + {IMX_8BIT, 0x331D, 0xA0}, + {IMX_8BIT, 0x4084, 0x0C}, + {IMX_8BIT, 0x4085, 0xD0}, + {IMX_8BIT, 0x4086, 0x07}, + {IMX_8BIT, 0x4087, 0x3C}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_6m_for_mipi_342[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_342MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x00}, + {IMX_8BIT, 0x0391, 0x11}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x14}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, /* 36, 194, 1039, a9f 4100x2316 */ + {IMX_8BIT, 0x0345, 0x36}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x94}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x39}, + {IMX_8BIT, 0x034A, 0x0A}, + {IMX_8BIT, 0x034B, 0x9F}, + {IMX_8BIT, 0x034C, 0x0C}, /* 3280x1852 */ + {IMX_8BIT, 0x034D, 0xD0}, + {IMX_8BIT, 0x034E, 0x07}, + {IMX_8BIT, 0x034F, 0x3C}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x10}, /* 4100x2316 */ + {IMX_8BIT, 0x0355, 0x04}, + {IMX_8BIT, 0x0356, 0x09}, + {IMX_8BIT, 0x0357, 0x0C}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x0C}, + {IMX_8BIT, 0x3311, 0xD0}, + {IMX_8BIT, 0x3312, 0x07}, + {IMX_8BIT, 0x3313, 0x3C}, + {IMX_8BIT, 0x331C, 0x02}, + {IMX_8BIT, 0x331D, 0xA0}, + {IMX_8BIT, 0x4084, 0x0C}, + {IMX_8BIT, 0x4085, 0xD0}, + {IMX_8BIT, 0x4086, 0x07}, + {IMX_8BIT, 0x4087, 0x3C}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +/* + * FOV is: 3280x2464, larger then 3264x2448. + * Sensor output: 336x256 + * Cropping region: 3444x2624 + */ +static struct imx_reg const imx135_336x256[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x01}, + {IMX_8BIT, 0x0391, 0x22}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, /* 2x binning */ + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x52}, /* scaling: 82/16 */ + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01}, /* x_start: 374 */ + {IMX_8BIT, 0x0345, 0x76}, + {IMX_8BIT, 0x0346, 0x00}, /* y_start: 248 */ + {IMX_8BIT, 0x0347, 0xF8}, + {IMX_8BIT, 0x0348, 0x0E}, /* x_end: 3817 */ + {IMX_8BIT, 0x0349, 0xE9}, + {IMX_8BIT, 0x034A, 0x0B}, /* y_end: 2871 */ + {IMX_8BIT, 0x034B, 0x37}, + {IMX_8BIT, 0x034C, 0x01}, /* x_out: 336 */ + {IMX_8BIT, 0x034D, 0x50}, + {IMX_8BIT, 0x034E, 0x01}, /* y_out: 256 */ + {IMX_8BIT, 0x034F, 0x00}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x06}, /* dig x_out: 1722 */ + {IMX_8BIT, 0x0355, 0xBA}, + {IMX_8BIT, 0x0356, 0x05}, /* dig y_out: 1312 */ + {IMX_8BIT, 0x0357, 0x20}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x01}, /* ?: x_out */ + {IMX_8BIT, 0x3311, 0x50}, + {IMX_8BIT, 0x3312, 0x01}, /* ?: y_out */ + {IMX_8BIT, 0x3313, 0x00}, + {IMX_8BIT, 0x331C, 0x02}, + {IMX_8BIT, 0x331D, 0x4E}, + {IMX_8BIT, 0x4084, 0x01}, /* ?: x_out */ + {IMX_8BIT, 0x4085, 0x50}, + {IMX_8BIT, 0x4086, 0x01}, /* ?: y_out */ + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_1m[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x01}, + {IMX_8BIT, 0x0391, 0x22}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x1F}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x58}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x28}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x17}, + {IMX_8BIT, 0x034A, 0x0C}, + {IMX_8BIT, 0x034B, 0x07}, + {IMX_8BIT, 0x034C, 0x04}, + {IMX_8BIT, 0x034D, 0x10}, + {IMX_8BIT, 0x034E, 0x03}, + {IMX_8BIT, 0x034F, 0x10}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x07}, + {IMX_8BIT, 0x0355, 0xE0}, + {IMX_8BIT, 0x0356, 0x05}, + {IMX_8BIT, 0x0357, 0xF0}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x04}, + {IMX_8BIT, 0x3311, 0x10}, + {IMX_8BIT, 0x3312, 0x03}, + {IMX_8BIT, 0x3313, 0x10}, + {IMX_8BIT, 0x331C, 0x02}, + {IMX_8BIT, 0x331D, 0x4E}, + {IMX_8BIT, 0x4084, 0x04}, + {IMX_8BIT, 0x4085, 0x10}, + {IMX_8BIT, 0x4086, 0x03}, + {IMX_8BIT, 0x4087, 0x10}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg const imx135_3m_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x01}, /* Binning */ + {IMX_8BIT, 0x0391, 0x22}, /* 2x2 binning */ + {IMX_8BIT, 0x0392, 0x00}, /* average */ + {IMX_8BIT, 0x0401, 0x00}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x10}, + {IMX_8BIT, 0x4082, 0x01}, + {IMX_8BIT, 0x4083, 0x01}, + {IMX_8BIT, 0x4203, 0xFF}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x28}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x08}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x47}, + {IMX_8BIT, 0x034A, 0x0C}, + {IMX_8BIT, 0x034B, 0x27}, + {IMX_8BIT, 0x034C, 0x08}, + {IMX_8BIT, 0x034D, 0x10}, + {IMX_8BIT, 0x034E, 0x06}, + {IMX_8BIT, 0x034F, 0x10}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x08}, + {IMX_8BIT, 0x0355, 0x10}, + {IMX_8BIT, 0x0356, 0x06}, + {IMX_8BIT, 0x0357, 0x10}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x08}, + {IMX_8BIT, 0x3311, 0x10}, + {IMX_8BIT, 0x3312, 0x06}, + {IMX_8BIT, 0x3313, 0x10}, + {IMX_8BIT, 0x331C, 0x00}, + {IMX_8BIT, 0x331D, 0xAA}, + {IMX_8BIT, 0x4084, 0x00}, + {IMX_8BIT, 0x4085, 0x00}, + {IMX_8BIT, 0x4086, 0x00}, + {IMX_8BIT, 0x4087, 0x00}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +/* 1080P 1936x1104 */ +static struct imx_reg const imx135_1080p_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03}, + {IMX_8BIT, 0x0112, 0x0A}, + {IMX_8BIT, 0x0113, 0x0A}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0387, 0x01}, + {IMX_8BIT, 0x0390, 0x01}, + {IMX_8BIT, 0x0391, 0x22}, + {IMX_8BIT, 0x0392, 0x00}, + {IMX_8BIT, 0x0401, 0x02}, + {IMX_8BIT, 0x0404, 0x00}, + {IMX_8BIT, 0x0405, 0x11}, + {IMX_8BIT, 0x4082, 0x00}, + {IMX_8BIT, 0x4083, 0x00}, + {IMX_8BIT, 0x7006, 0x04}, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x2E}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x84}, + {IMX_8BIT, 0x0348, 0x10}, + {IMX_8BIT, 0x0349, 0x41}, + {IMX_8BIT, 0x034A, 0x0A}, + {IMX_8BIT, 0x034B, 0xAF}, + {IMX_8BIT, 0x034C, 0x07}, + {IMX_8BIT, 0x034D, 0x90}, + {IMX_8BIT, 0x034E, 0x04}, + {IMX_8BIT, 0x034F, 0x50}, + {IMX_8BIT, 0x0350, 0x00}, + {IMX_8BIT, 0x0351, 0x00}, + {IMX_8BIT, 0x0352, 0x00}, + {IMX_8BIT, 0x0353, 0x00}, + {IMX_8BIT, 0x0354, 0x08}, + {IMX_8BIT, 0x0355, 0x0A}, + {IMX_8BIT, 0x0356, 0x04}, + {IMX_8BIT, 0x0357, 0x96}, + {IMX_8BIT, 0x301D, 0x30}, + {IMX_8BIT, 0x3310, 0x07}, + {IMX_8BIT, 0x3311, 0x90}, + {IMX_8BIT, 0x3312, 0x04}, + {IMX_8BIT, 0x3313, 0x50}, + {IMX_8BIT, 0x331C, 0x01}, + {IMX_8BIT, 0x331D, 0x00}, + {IMX_8BIT, 0x4084, 0x07}, + {IMX_8BIT, 0x4085, 0x90}, + {IMX_8BIT, 0x4086, 0x04}, + {IMX_8BIT, 0x4087, 0x50}, + {IMX_8BIT, 0x4400, 0x00}, + {IMX_TOK_TERM, 0, 0}, +}; + +static const struct imx_reg imx135_1080p_nodvs_fullfov_max_clock[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 168,464,4039,2655: 3872x2192 */ + { IMX_8BIT, 0x0345, 0xA8 }, + { IMX_8BIT, 0x0346, 0x01 }, + { IMX_8BIT, 0x0347, 0xD0 }, + { IMX_8BIT, 0x0348, 0x0F }, + { IMX_8BIT, 0x0349, 0xC7 }, + { IMX_8BIT, 0x034A, 0x0A }, + { IMX_8BIT, 0x034B, 0x5F }, + { IMX_8BIT, 0x034C, 0x07 }, /*1936 x 1096 */ + { IMX_8BIT, 0x034D, 0x90 }, + { IMX_8BIT, 0x034E, 0x04 }, + { IMX_8BIT, 0x034F, 0x48 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x07 }, /*1936 x 1096 */ + { IMX_8BIT, 0x0355, 0x90 }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0x48 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x07 }, + { IMX_8BIT, 0x3311, 0x90 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0x48 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0xB0 }, + { IMX_8BIT, 0x4084, 0x07 }, + { IMX_8BIT, 0x4085, 0x90 }, + { IMX_8BIT, 0x4086, 0x04 }, + { IMX_8BIT, 0x4087, 0x48 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/* 1080P NODVS 1936x1096 */ +static const struct imx_reg imx135_1080p_nodvs_max_clock[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x11 }, + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 46,396,4161,2727: 4116x2332 */ + { IMX_8BIT, 0x0345, 0x2E }, + { IMX_8BIT, 0x0346, 0x01 }, + { IMX_8BIT, 0x0347, 0x8C }, + { IMX_8BIT, 0x0348, 0x10 }, + { IMX_8BIT, 0x0349, 0x41 }, + { IMX_8BIT, 0x034A, 0x0A }, + { IMX_8BIT, 0x034B, 0xA7 }, + { IMX_8BIT, 0x034C, 0x07 }, /*1936 x 1096 */ + { IMX_8BIT, 0x034D, 0x90 }, + { IMX_8BIT, 0x034E, 0x04 }, + { IMX_8BIT, 0x034F, 0x48 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x08 }, /* 2058x1166 */ + { IMX_8BIT, 0x0355, 0x0A }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0x8E }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x07 }, + { IMX_8BIT, 0x3311, 0x90 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0x48 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0xB0 }, + { IMX_8BIT, 0x4084, 0x07 }, + { IMX_8BIT, 0x4085, 0x90 }, + { IMX_8BIT, 0x4086, 0x04 }, + { IMX_8BIT, 0x4087, 0x48 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/* 1080P 10%DVS 2104x1184 */ +static const struct imx_reg imx135_1080p_10_dvs_max_clock[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x00 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x10 }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 0,376,4207,2743: 4208x2368 */ + { IMX_8BIT, 0x0345, 0x00 }, + { IMX_8BIT, 0x0346, 0x01 }, + { IMX_8BIT, 0x0347, 0x78 }, + { IMX_8BIT, 0x0348, 0x10 }, + { IMX_8BIT, 0x0349, 0x6F }, + { IMX_8BIT, 0x034A, 0x0A }, + { IMX_8BIT, 0x034B, 0xB7 }, + { IMX_8BIT, 0x034C, 0x08 }, /* 2104 x 1184 */ + { IMX_8BIT, 0x034D, 0x38 }, + { IMX_8BIT, 0x034E, 0x04 }, + { IMX_8BIT, 0x034F, 0xA0 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x08 }, /* 2104 x 1184 */ + { IMX_8BIT, 0x0355, 0x38 }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0xA0 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x08 }, + { IMX_8BIT, 0x3311, 0x38 }, + { IMX_8BIT, 0x3312, 0x04 }, + { IMX_8BIT, 0x3313, 0xA0 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0xB0 }, + { IMX_8BIT, 0x4084, 0x00 }, + { IMX_8BIT, 0x4085, 0x00 }, + { IMX_8BIT, 0x4086, 0x00 }, + { IMX_8BIT, 0x4087, 0x00 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +static const struct imx_reg imx135_720pdvs_max_clock[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x15 }, + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 46,404,4161,2715: 4116x2312 */ + { IMX_8BIT, 0x0345, 0x2E }, + { IMX_8BIT, 0x0346, 0x01 }, + { IMX_8BIT, 0x0347, 0x94 }, + { IMX_8BIT, 0x0348, 0x10 }, + { IMX_8BIT, 0x0349, 0x41 }, + { IMX_8BIT, 0x034A, 0x0A }, + { IMX_8BIT, 0x034B, 0x9B }, + { IMX_8BIT, 0x034C, 0x06 }, /*1568 x 880 */ + { IMX_8BIT, 0x034D, 0x20 }, + { IMX_8BIT, 0x034E, 0x03 }, + { IMX_8BIT, 0x034F, 0x70 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x08 }, /*2058 x 1156 */ + { IMX_8BIT, 0x0355, 0x0A }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0x84 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x06 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x03 }, + { IMX_8BIT, 0x3313, 0x70 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0x4C }, + { IMX_8BIT, 0x4084, 0x06 }, + { IMX_8BIT, 0x4085, 0x20 }, + { IMX_8BIT, 0x4086, 0x03 }, + { IMX_8BIT, 0x4087, 0x70 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/******************* Video Modes ******************/ + +/* 1080P DVS 2336x1320 */ +static const struct imx_reg imx135_2336x1320_max_clock[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_451_2MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, + { IMX_8BIT, 0x0391, 0x11 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x1C }, + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 60,404,4147,2715: 4088x2312 */ + { IMX_8BIT, 0x0345, 0x3C }, + { IMX_8BIT, 0x0346, 0x01 }, + { IMX_8BIT, 0x0347, 0x94 }, + { IMX_8BIT, 0x0348, 0x10 }, + { IMX_8BIT, 0x0349, 0x33 }, + { IMX_8BIT, 0x034A, 0x0A }, + { IMX_8BIT, 0x034B, 0x9B }, + { IMX_8BIT, 0x034C, 0x09 }, /*2336 x 1320 */ + { IMX_8BIT, 0x034D, 0x20 }, + { IMX_8BIT, 0x034E, 0x05 }, + { IMX_8BIT, 0x034F, 0x28 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x0F }, /* 4088x2312 */ + { IMX_8BIT, 0x0355, 0xF8 }, + { IMX_8BIT, 0x0356, 0x09 }, + { IMX_8BIT, 0x0357, 0x08 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x09 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x05 }, + { IMX_8BIT, 0x3313, 0x28 }, + { IMX_8BIT, 0x331C, 0x04 }, + { IMX_8BIT, 0x331D, 0xE2 }, + { IMX_8BIT, 0x4084, 0x09 }, + { IMX_8BIT, 0x4085, 0x20 }, + { IMX_8BIT, 0x4086, 0x05 }, + { IMX_8BIT, 0x4087, 0x28 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/* 1080P DVS 2336x1320 Cropped */ +static const struct imx_reg imx135_2336x1320_cropped_mipi499[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_499_2MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x00 }, + { IMX_8BIT, 0x0391, 0x11 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x1C }, + { IMX_8BIT, 0x4082, 0x01 }, + { IMX_8BIT, 0x4083, 0x01 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x03 }, /* 936,900,3271,2219: 2336x1320 */ + { IMX_8BIT, 0x0345, 0xA8 }, + { IMX_8BIT, 0x0346, 0x03 }, + { IMX_8BIT, 0x0347, 0x84 }, + { IMX_8BIT, 0x0348, 0x0C }, + { IMX_8BIT, 0x0349, 0xC7 }, + { IMX_8BIT, 0x034A, 0x08 }, + { IMX_8BIT, 0x034B, 0xAB }, + { IMX_8BIT, 0x034C, 0x09 }, /* 2336 x 1320 */ + { IMX_8BIT, 0x034D, 0x20 }, + { IMX_8BIT, 0x034E, 0x05 }, + { IMX_8BIT, 0x034F, 0x28 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x09 }, /* 2336 x 1320 */ + { IMX_8BIT, 0x0355, 0x20 }, + { IMX_8BIT, 0x0356, 0x05 }, + { IMX_8BIT, 0x0357, 0x28 }, + { IMX_8BIT, 0x301D, 0x30 }, + { IMX_8BIT, 0x3310, 0x09 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x05 }, + { IMX_8BIT, 0x3313, 0x28 }, + { IMX_8BIT, 0x331C, 0x00 }, + { IMX_8BIT, 0x331D, 0xB4 }, + { IMX_8BIT, 0x4084, 0x09 }, + { IMX_8BIT, 0x4085, 0x20 }, + { IMX_8BIT, 0x4086, 0x05 }, + { IMX_8BIT, 0x4087, 0x28 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/* 720P DVS 1568 x 880 */ +static const struct imx_reg imx135_720p_dvs_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x15 }, + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 46,404,4161,2715: 4116x2312 */ + { IMX_8BIT, 0x0345, 0x2e }, + { IMX_8BIT, 0x0346, 0x01 }, + { IMX_8BIT, 0x0347, 0x94 }, + { IMX_8BIT, 0x0348, 0x10 }, + { IMX_8BIT, 0x0349, 0x41 }, + { IMX_8BIT, 0x034A, 0x0A }, + { IMX_8BIT, 0x034B, 0x9B }, + { IMX_8BIT, 0x034C, 0x06 }, /*1568 x 880 */ + { IMX_8BIT, 0x034D, 0x20 }, + { IMX_8BIT, 0x034E, 0x03 }, + { IMX_8BIT, 0x034F, 0x70 }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x08 }, /* 2058x1156 */ + { IMX_8BIT, 0x0355, 0x0a }, + { IMX_8BIT, 0x0356, 0x04 }, + { IMX_8BIT, 0x0357, 0x84 }, + { IMX_8BIT, 0x301D, 0x30 }, /* TODO! */ + { IMX_8BIT, 0x3310, 0x06 }, + { IMX_8BIT, 0x3311, 0x20 }, + { IMX_8BIT, 0x3312, 0x03 }, + { IMX_8BIT, 0x3313, 0x70 }, + { IMX_8BIT, 0x331C, 0x01 }, /* TODO! */ + { IMX_8BIT, 0x331D, 0xd6 }, /* TODO! */ + { IMX_8BIT, 0x4084, 0x06 }, + { IMX_8BIT, 0x4085, 0x20 }, + { IMX_8BIT, 0x4086, 0x03 }, + { IMX_8BIT, 0x4087, 0x70 }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/* wvga: H : 1640 V : 1024 */ +static const struct imx_reg imx135_wvga_dvs_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x22 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x02 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x14 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, + {IMX_8BIT, 0x0345, 0x36 }, + {IMX_8BIT, 0x0346, 0x01 }, + {IMX_8BIT, 0x0347, 0x18 }, + {IMX_8BIT, 0x0348, 0x10 }, + {IMX_8BIT, 0x0349, 0x39 }, + {IMX_8BIT, 0x034A, 0x0B }, + {IMX_8BIT, 0x034B, 0x17 }, + {IMX_8BIT, 0x034C, 0x06 }, + {IMX_8BIT, 0x034D, 0x68 }, + {IMX_8BIT, 0x034E, 0x04 }, + {IMX_8BIT, 0x034F, 0x00 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x08 }, + {IMX_8BIT, 0x0355, 0x02 }, + {IMX_8BIT, 0x0356, 0x05 }, + {IMX_8BIT, 0x0357, 0x00 }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x06 }, + {IMX_8BIT, 0x3311, 0x68 }, + {IMX_8BIT, 0x3312, 0x04 }, + {IMX_8BIT, 0x3313, 0x00 }, + {IMX_8BIT, 0x331C, 0x01 }, + {IMX_8BIT, 0x331D, 0xBD }, + {IMX_8BIT, 0x4084, 0x06 }, + {IMX_8BIT, 0x4085, 0x68 }, + {IMX_8BIT, 0x4086, 0x04 }, + {IMX_8BIT, 0x4087, 0x00 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* 480P 1036 x 696 */ +static const struct imx_reg imx135_480p_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x00 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x10 },/* No scal */ + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 52,20,4155, 3099 4144x2784*/ + {IMX_8BIT, 0x0345, 0x20 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0xA8 }, + {IMX_8BIT, 0x0348, 0x10 }, + {IMX_8BIT, 0x0349, 0x4F }, + {IMX_8BIT, 0x034A, 0x0B }, + {IMX_8BIT, 0x034B, 0x88 }, + {IMX_8BIT, 0x034C, 0x04 }, /* 1036 * 696 */ + {IMX_8BIT, 0x034D, 0x0C }, + {IMX_8BIT, 0x034E, 0x02 }, + {IMX_8BIT, 0x034F, 0xB8 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x04 }, /* 1036x696 */ + {IMX_8BIT, 0x0355, 0x0C }, + {IMX_8BIT, 0x0356, 0x02 }, + {IMX_8BIT, 0x0357, 0xB8 }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x04 }, + {IMX_8BIT, 0x3311, 0x0C }, + {IMX_8BIT, 0x3312, 0x02 }, + {IMX_8BIT, 0x3313, 0xB8 }, + {IMX_8BIT, 0x331C, 0x02 }, + {IMX_8BIT, 0x331D, 0x21 }, + {IMX_8BIT, 0x4084, 0x04 }, + {IMX_8BIT, 0x4085, 0x0C }, + {IMX_8BIT, 0x4086, 0x02 }, + {IMX_8BIT, 0x4087, 0xB8 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* 480P DVS 936 x 602 */ +static const struct imx_reg imx135_480p_dvs_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* mode setting */ + { IMX_8BIT, 0x0108, 0x03 }, + { IMX_8BIT, 0x0112, 0x0A }, + { IMX_8BIT, 0x0113, 0x0A }, + { IMX_8BIT, 0x0381, 0x01 }, + { IMX_8BIT, 0x0383, 0x01 }, + { IMX_8BIT, 0x0385, 0x01 }, + { IMX_8BIT, 0x0387, 0x01 }, + { IMX_8BIT, 0x0390, 0x01 }, + { IMX_8BIT, 0x0391, 0x22 }, + { IMX_8BIT, 0x0392, 0x00 }, + { IMX_8BIT, 0x0401, 0x02 }, + { IMX_8BIT, 0x0404, 0x00 }, + { IMX_8BIT, 0x0405, 0x23 }, + { IMX_8BIT, 0x4082, 0x00 }, + { IMX_8BIT, 0x4083, 0x00 }, + { IMX_8BIT, 0x7006, 0x04 }, + /* size setting */ + { IMX_8BIT, 0x0344, 0x00 }, /* 56,244,4151,2877: 4096x2634 */ + { IMX_8BIT, 0x0345, 0x38 }, + { IMX_8BIT, 0x0346, 0x00 }, + { IMX_8BIT, 0x0347, 0xf4 }, + { IMX_8BIT, 0x0348, 0x10 }, + { IMX_8BIT, 0x0349, 0x37 }, + { IMX_8BIT, 0x034A, 0x0b }, + { IMX_8BIT, 0x034B, 0x3d }, + { IMX_8BIT, 0x034C, 0x03 }, /* 936 x 602 */ + { IMX_8BIT, 0x034D, 0xa8 }, + { IMX_8BIT, 0x034E, 0x02 }, + { IMX_8BIT, 0x034F, 0x5a }, + { IMX_8BIT, 0x0350, 0x00 }, + { IMX_8BIT, 0x0351, 0x00 }, + { IMX_8BIT, 0x0352, 0x00 }, + { IMX_8BIT, 0x0353, 0x00 }, + { IMX_8BIT, 0x0354, 0x08 }, /* 2058x1156 */ + { IMX_8BIT, 0x0355, 0x00 }, + { IMX_8BIT, 0x0356, 0x05 }, + { IMX_8BIT, 0x0357, 0x25 }, + { IMX_8BIT, 0x301D, 0x30 }, /* TODO! */ + { IMX_8BIT, 0x3310, 0x03 }, + { IMX_8BIT, 0x3311, 0xa8 }, + { IMX_8BIT, 0x3312, 0x02 }, + { IMX_8BIT, 0x3313, 0x5a }, + { IMX_8BIT, 0x331C, 0x01 }, /* TODO! */ + { IMX_8BIT, 0x331D, 0xd6 }, + { IMX_8BIT, 0x4084, 0x03 }, + { IMX_8BIT, 0x4085, 0xa8 }, + { IMX_8BIT, 0x4086, 0x02 }, + { IMX_8BIT, 0x4087, 0x5a }, + { IMX_8BIT, 0x4400, 0x00 }, + { IMX_TOK_TERM, 0, 0} +}; + +/* VGA: H : 1036 V : 780 */ +static const struct imx_reg imx135_vga_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x00 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x10 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 52,20,4155, 3099 4144x3120*/ + {IMX_8BIT, 0x0345, 0x20 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x00 }, + {IMX_8BIT, 0x0348, 0x10 }, + {IMX_8BIT, 0x0349, 0x4F }, + {IMX_8BIT, 0x034A, 0x0C }, + {IMX_8BIT, 0x034B, 0x2F }, + {IMX_8BIT, 0x034C, 0x04 }, /* 1036x780 */ + {IMX_8BIT, 0x034D, 0x0C }, + {IMX_8BIT, 0x034E, 0x03 }, + {IMX_8BIT, 0x034F, 0x0C }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x04 }, /* 1036x780 */ + {IMX_8BIT, 0x0355, 0x0C }, + {IMX_8BIT, 0x0356, 0x03 }, + {IMX_8BIT, 0x0357, 0x0C }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x04 }, + {IMX_8BIT, 0x3311, 0x0C }, + {IMX_8BIT, 0x3312, 0x03 }, + {IMX_8BIT, 0x3313, 0x0C }, + {IMX_8BIT, 0x331C, 0x02 }, + {IMX_8BIT, 0x331D, 0x21 }, + {IMX_8BIT, 0x4084, 0x04 }, + {IMX_8BIT, 0x4085, 0x0C }, + {IMX_8BIT, 0x4086, 0x03 }, + {IMX_8BIT, 0x4087, 0x0C }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* VGA: H : 820 V : 616 */ +static const struct imx_reg imx135_vga_dvs_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x02 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x14 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 52,20,4155, 3099 4104x3080*/ + {IMX_8BIT, 0x0345, 0x34 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x14 }, + {IMX_8BIT, 0x0348, 0x10 }, + {IMX_8BIT, 0x0349, 0x3B }, + {IMX_8BIT, 0x034A, 0x0C }, + {IMX_8BIT, 0x034B, 0x1B }, + {IMX_8BIT, 0x034C, 0x03 }, /* 820x616 */ + {IMX_8BIT, 0x034D, 0x34 }, + {IMX_8BIT, 0x034E, 0x02 }, + {IMX_8BIT, 0x034F, 0x68 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x04 }, /* 1026x770 */ + {IMX_8BIT, 0x0355, 0x02 }, + {IMX_8BIT, 0x0356, 0x03 }, + {IMX_8BIT, 0x0357, 0x02 }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x03 }, + {IMX_8BIT, 0x3311, 0x34 }, + {IMX_8BIT, 0x3312, 0x02 }, + {IMX_8BIT, 0x3313, 0x68 }, + {IMX_8BIT, 0x331C, 0x02 }, + {IMX_8BIT, 0x331D, 0x21 }, + {IMX_8BIT, 0x4084, 0x03 }, + {IMX_8BIT, 0x4085, 0x34 }, + {IMX_8BIT, 0x4086, 0x02 }, + {IMX_8BIT, 0x4087, 0x68 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* VGA: H : 436 V : 360 */ +static const struct imx_reg imx135_436x360_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x02 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x22 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 212,0,3995,3119 3784x3120 */ + {IMX_8BIT, 0x0345, 0xD4 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x00 }, + {IMX_8BIT, 0x0348, 0x0F }, + {IMX_8BIT, 0x0349, 0x9B }, + {IMX_8BIT, 0x034A, 0x0C }, + {IMX_8BIT, 0x034B, 0x2F }, + + {IMX_8BIT, 0x034C, 0x01 }, /* 436x360 */ + {IMX_8BIT, 0x034D, 0xB4 }, + {IMX_8BIT, 0x034E, 0x01 }, + {IMX_8BIT, 0x034F, 0x68 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x12 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x0C }, + + {IMX_8BIT, 0x0354, 0x03 }, /* 928x768 crop from 946x780*/ + {IMX_8BIT, 0x0355, 0xA0 }, + {IMX_8BIT, 0x0356, 0x03 }, + {IMX_8BIT, 0x0357, 0x00 }, + + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x01 }, + {IMX_8BIT, 0x3311, 0xB4 }, + {IMX_8BIT, 0x3312, 0x01 }, + {IMX_8BIT, 0x3313, 0x68 }, + {IMX_8BIT, 0x331C, 0x02 }, + {IMX_8BIT, 0x331D, 0x21 }, + {IMX_8BIT, 0x4084, 0x01 }, + {IMX_8BIT, 0x4085, 0xB4 }, + {IMX_8BIT, 0x4086, 0x01 }, + {IMX_8BIT, 0x4087, 0x68 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* QVGA: H : 408 V : 308 */ +static const struct imx_reg imx135_qvga__dvs_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x02 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x28 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 64,20,4143,3099 4080x3080 */ + {IMX_8BIT, 0x0345, 0x40 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x14 }, + {IMX_8BIT, 0x0348, 0x10 }, + {IMX_8BIT, 0x0349, 0x2F }, + {IMX_8BIT, 0x034A, 0x0C }, + {IMX_8BIT, 0x034B, 0x1B }, + {IMX_8BIT, 0x034C, 0x01 }, /* 408x308 */ + {IMX_8BIT, 0x034D, 0x98 }, + {IMX_8BIT, 0x034E, 0x01 }, + {IMX_8BIT, 0x034F, 0x34 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x03 }, /* 1020x770 */ + {IMX_8BIT, 0x0355, 0xFC }, + {IMX_8BIT, 0x0356, 0x03 }, + {IMX_8BIT, 0x0357, 0x02 }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x01 }, + {IMX_8BIT, 0x3311, 0x98 }, + {IMX_8BIT, 0x3312, 0x01 }, + {IMX_8BIT, 0x3313, 0x34 }, + {IMX_8BIT, 0x331C, 0x01 }, + {IMX_8BIT, 0x331D, 0x68 }, + {IMX_8BIT, 0x4084, 0x01 }, + {IMX_8BIT, 0x4085, 0x98 }, + {IMX_8BIT, 0x4086, 0x01 }, + {IMX_8BIT, 0x4087, 0x34 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* CIF H : 368 V : 304 */ +static const struct imx_reg imx135_cif_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x02 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x28 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x01 }, /* 264,42,3943,3081 3680x3040 */ + {IMX_8BIT, 0x0345, 0x08 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x2a }, + {IMX_8BIT, 0x0348, 0x0F }, + {IMX_8BIT, 0x0349, 0x67 }, + {IMX_8BIT, 0x034A, 0x0c }, + {IMX_8BIT, 0x034B, 0x09 }, + {IMX_8BIT, 0x034C, 0x01 }, /* 368x304 */ + {IMX_8BIT, 0x034D, 0x70 }, + {IMX_8BIT, 0x034E, 0x01 }, + {IMX_8BIT, 0x034F, 0x30 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x03 }, /* 920x760 */ + {IMX_8BIT, 0x0355, 0x98 }, + {IMX_8BIT, 0x0356, 0x02 }, + {IMX_8BIT, 0x0357, 0xf8 }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x01 }, + {IMX_8BIT, 0x3311, 0x70 }, + {IMX_8BIT, 0x3312, 0x01 }, + {IMX_8BIT, 0x3313, 0x30 }, + {IMX_8BIT, 0x331C, 0x02 }, /* TODO! binning 4x4 must be 021c? */ + {IMX_8BIT, 0x331D, 0x1C }, + {IMX_8BIT, 0x4084, 0x01 }, + {IMX_8BIT, 0x4085, 0x70 }, + {IMX_8BIT, 0x4086, 0x01 }, + {IMX_8BIT, 0x4087, 0x30 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* CIF H : 1888 V : 1548 */ +static const struct imx_reg imx135_cif_binning_1888x1548[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x22 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x00 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x10 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 264,42, 3776x3096 */ + {IMX_8BIT, 0x0345, 0xD8 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x0C }, + {IMX_8BIT, 0x0348, 0x0F }, + {IMX_8BIT, 0x0349, 0x97 }, + {IMX_8BIT, 0x034A, 0x0C }, + {IMX_8BIT, 0x034B, 0x23 }, + {IMX_8BIT, 0x034C, 0x07 }, /* 1888x1548 */ + {IMX_8BIT, 0x034D, 0x60 }, + {IMX_8BIT, 0x034E, 0x06 }, + {IMX_8BIT, 0x034F, 0x0C }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x07 }, /* 1888x1548 */ + {IMX_8BIT, 0x0355, 0x60 }, + {IMX_8BIT, 0x0356, 0x06 }, + {IMX_8BIT, 0x0357, 0x0C }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x07 }, + {IMX_8BIT, 0x3311, 0x60 }, + {IMX_8BIT, 0x3312, 0x06 }, + {IMX_8BIT, 0x3313, 0x0C }, + {IMX_8BIT, 0x331C, 0x02 }, /* TODO! binning 4x4 must be 021c? */ + {IMX_8BIT, 0x331D, 0x1C }, + {IMX_8BIT, 0x4084, 0x07 }, + {IMX_8BIT, 0x4085, 0x60 }, + {IMX_8BIT, 0x4086, 0x06 }, + {IMX_8BIT, 0x4087, 0x0C }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* QCIF H : 216 V : 176 */ +static const struct imx_reg imx135_qcif_dvs_binning[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + PLL_SETTINGS_FOR_MIPI_209_6MHZ_SALTBAY, + /* Mode setting */ + {IMX_8BIT, 0x0108, 0x03 }, + {IMX_8BIT, 0x0112, 0x0A }, + {IMX_8BIT, 0x0113, 0x0A }, + {IMX_8BIT, 0x0381, 0x01 }, + {IMX_8BIT, 0x0383, 0x01 }, + {IMX_8BIT, 0x0385, 0x01 }, + {IMX_8BIT, 0x0387, 0x01 }, + {IMX_8BIT, 0x0390, 0x01 }, + {IMX_8BIT, 0x0391, 0x44 }, + {IMX_8BIT, 0x0392, 0x00 }, + {IMX_8BIT, 0x0401, 0x02 }, + {IMX_8BIT, 0x0404, 0x00 }, + {IMX_8BIT, 0x0405, 0x46 }, + {IMX_8BIT, 0x4082, 0x00 }, + {IMX_8BIT, 0x4083, 0x00 }, + {IMX_8BIT, 0x7006, 0x04 }, + /* Size setting */ + {IMX_8BIT, 0x0344, 0x00 }, /* 212,20,3995,3099 3784x3080 */ + {IMX_8BIT, 0x0345, 0xD4 }, + {IMX_8BIT, 0x0346, 0x00 }, + {IMX_8BIT, 0x0347, 0x14 }, + {IMX_8BIT, 0x0348, 0x0F }, + {IMX_8BIT, 0x0349, 0x9B }, + {IMX_8BIT, 0x034A, 0x0C }, + {IMX_8BIT, 0x034B, 0x1B }, + {IMX_8BIT, 0x034C, 0x00 }, /* 216x176 */ + {IMX_8BIT, 0x034D, 0xD8 }, + {IMX_8BIT, 0x034E, 0x00 }, + {IMX_8BIT, 0x034F, 0xB0 }, + {IMX_8BIT, 0x0350, 0x00 }, + {IMX_8BIT, 0x0351, 0x00 }, + {IMX_8BIT, 0x0352, 0x00 }, + {IMX_8BIT, 0x0353, 0x00 }, + {IMX_8BIT, 0x0354, 0x03 }, /* 946x770 */ + {IMX_8BIT, 0x0355, 0xB2 }, + {IMX_8BIT, 0x0356, 0x03 }, + {IMX_8BIT, 0x0357, 0x02 }, + {IMX_8BIT, 0x301D, 0x30 }, + {IMX_8BIT, 0x3310, 0x00 }, + {IMX_8BIT, 0x3311, 0xD8 }, + {IMX_8BIT, 0x3312, 0x00 }, + {IMX_8BIT, 0x3313, 0xB0 }, + {IMX_8BIT, 0x331C, 0x02 }, /* TODO! binning 4x4 must be 021c */ + {IMX_8BIT, 0x331D, 0x1C }, + {IMX_8BIT, 0x4084, 0x00 }, + {IMX_8BIT, 0x4085, 0xD8 }, + {IMX_8BIT, 0x4086, 0x00 }, + {IMX_8BIT, 0x4087, 0xB0 }, + {IMX_8BIT, 0x4400, 0x00 }, + {IMX_TOK_TERM, 0, 0} +}; + +/* + * ISP Scaling is now supported in offine capture use cases. Because of that + * we need only few modes to cover the different aspect ratios from the + * sensor and the ISP will scale it based on the requested resolution from HAL. + * + * There is a performance impact when continuous view finder option is chose + * for resolutions above 8MP. So 8MP and 6MP resolution are kept, so that lower + * than these take 8MP or 6MP espectively for down scaling based on the + * aspect ratio. + */ +struct imx_resolution imx135_res_preview_mofd[] = { + { + .desc = "imx135_cif_binning_preview", + .regs = imx135_cif_binning, + .width = 368, + .height = 304, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 9114, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_vga_binning_preview", + .regs = imx135_vga_binning, + .width = 1036, + .height = 780, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_480p_preview", + .regs = imx135_480p_binning, + .width = 1036, + .height = 696, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_1080p_binning_preview", + .regs = imx135_1080p_binning, + .width = 1936, + .height = 1104, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_3m__cont_cap", + .regs = imx135_3m_binning, + .width = 2064, + .height = 1552, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_6m_cont_cap", + .regs = imx135_6m, + .width = 3280, + .height = 1852, + .fps_options = { + { /* Binning Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_8m_scaled_from_12m__cont_cap", + .regs = imx135_8m_scaled_from_12m, + .width = 3280, + .height = 2464, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 24, + .pixels_per_line = 4572, + .lines_per_frame = 3280, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_10m__cont_cap", + .regs = imx135_10m, + .width = 4208, + .height = 2368, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2632, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_13m__cont_cap", + .regs = imx135_13m, + .width = 4208, + .height = 3120, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 24, + .pixels_per_line = 4572, + .lines_per_frame = 3290, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, +}; + +struct imx_resolution imx135_res_preview[] = { + { + .desc = "imx135_xga_cropped_video", + .regs = imx135_xga_cropped, + .width = 832, + .height = 628, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_2m_cropped_video", + .regs = imx135_2m_cropped, + .width = 1648, + .height = 1240, + .fps_options = { + { /* Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_1936x1096_cropped", + .regs = imx135_1936x1096_cropped, + .width = 1936, + .height = 1096, + .fps_options = { + { /* Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_8m_cropped_video", + .regs = imx135_8m_cropped, + .width = 3280, + .height = 2464, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, +}; + +/* + * ISP Scaling is now supported in online capture use cases. Because of that + * we need only few modes to cover the different aspect ratios from the + * sensor and the ISP will scale it based on the requested resolution from HAL. + * + * There is a performance impact when continuous view finder option is chose + * for resolutions above 8MP. So 8MP and 6MP resolution are kept, so that lower + * than these take 8MP or 6MP espectively for down scaling based on the + * aspect ratio. + */ +struct imx_resolution imx135_res_still_mofd[] = { + { + .desc = "imx135_cif_binning_still", + .regs = imx135_cif_binning_1888x1548, + .width = 1888, + .height = 1548, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 209600, + }, + { + .desc = "imx135_vga_binning_preview", + .regs = imx135_vga_binning, + .width = 1036, + .height = 780, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_480p_preview", + .regs = imx135_480p_binning, + .width = 1036, + .height = 696, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_1080p_binning_still", + .regs = imx135_1080p_binning, + .width = 1936, + .height = 1104, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 15, + .pixels_per_line = 9114, + .lines_per_frame = 2453, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_3m__still", + .regs = imx135_3m_binning, + .width = 2064, + .height = 1552, + .fps_options = { + { /* Binning Pixel clock: 335.36MHz */ + .fps = 15, + .pixels_per_line = 9114, + .lines_per_frame = 2453, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 209600, + }, + { + .desc = "imx135_6m_for_mipi_342_still", + .regs = imx135_6m_for_mipi_342, + .width = 3280, + .height = 1852, + .fps_options = { + { /* Pixel clock: 273.6MHz */ + .fps = 11, + .pixels_per_line = 9114, + .lines_per_frame = 2664, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 342000, + }, + { + .desc = "imx135_8m_scaled_from_12m_for_mipi342_still", + .regs = imx135_8m_scaled_from_12m_for_mipi342, + .width = 3280, + .height = 2464, + .fps_options = { + { /* Pixel clock: 273.6MHz */ + .fps = 8, + .pixels_per_line = 7672, + .lines_per_frame = 4458, + }, + { /* Pixel clock: 273.6MHz */ + .fps = 15, + .pixels_per_line = 5500, + .lines_per_frame = 3314, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 342000, + }, + { + .desc = "imx135_10m_for_mipi_342_still", + .regs = imx135_10m_for_mipi_342, + .width = 4208, + .height = 2368, + .fps_options = { + { /* Pixel clock: 273.6MHz */ + .fps = 11, + .pixels_per_line = 9144, + .lines_per_frame = 2664, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 342000, + }, + { + .desc = "imx135_13m_still", + .regs = imx135_13m_for_mipi_342, + .width = 4208, + .height = 3120, + .fps_options = { + { /* Pixel clock: 273.6MHz */ + .fps = 5, + .pixels_per_line = 9144, + .lines_per_frame = 5990, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 342000, + }, +}; + +struct imx_resolution imx135_res_still[] = { + { + .desc = "imx135_qvga", + .regs = imx135_336x256, + .width = 336, + .height = 256, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_cif", + .regs = imx135_368x304_cropped, + .width = 368, + .height = 304, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_xga_cropped_video", + .regs = imx135_xga_cropped, + .width = 832, + .height = 628, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_2M_for_11:9", + .regs = imx135_1424x1168_cropped, + .width = 1424, + .height = 1168, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_2m_cropped_video", + .regs = imx135_2m_cropped, + .width = 1648, + .height = 1240, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 15, + .pixels_per_line = 6466, + .lines_per_frame = 3710, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_6m_cropped_video", + .regs = imx135_6m_cropped, + .width = 3280, + .height = 1852, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 8, + .pixels_per_line = 8850, + .lines_per_frame = 5080, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_8m_cropped_video", + .regs = imx135_8m_cropped, + .width = 3280, + .height = 2464, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 8, + .pixels_per_line = 8850, + .lines_per_frame = 5080, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, +}; + +/* + * ISP scaling is not supported in case of video modes. So we need to have + * separate sensor mode for video use cases + */ +struct imx_resolution imx135_res_video[] = { + /* For binning modes pix clock is 335.36 MHz. */ + { + .desc = "imx135_qcif_dvs_binning_video", + .regs = imx135_qcif_dvs_binning, + .width = 216, + .height = 176, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_cif_binning_video", + .regs = imx135_cif_binning, + .width = 368, + .height = 304, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_qvga__dvs_binning_video", + .regs = imx135_qvga__dvs_binning, + .width = 408, + .height = 308, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_436x360_binning_video", + .regs = imx135_436x360_binning, + .width = 436, + .height = 360, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_vga_dvs_binning_video", + .regs = imx135_vga_dvs_binning, + .width = 820, + .height = 616, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 9144, + .lines_per_frame = 1226, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 209600, + }, + { + .desc = "imx135_480p_dvs_binning_video", + .regs = imx135_480p_dvs_binning, + .width = 936, + .height = 602, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 209600, + }, + { + .desc = "imx135_720P_dvs_video", + .regs = imx135_720pdvs_max_clock, + .width = 1568, + .height = 880, + .fps_options = { + {/* Pixel Clock : 360.96 MHz */ + .fps = 30, + .pixels_per_line = 5850, + .lines_per_frame = 2000, + }, + {/* Pixel Clock : 360.96 MHz */ + .fps = 60, + .pixels_per_line = 4572, + .lines_per_frame = 1310, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 451200, + }, + { + .desc = "imx135_wvga_dvs_binning_video", + .regs = imx135_wvga_dvs_binning, + .width = 1640, + .height = 1024, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 5464, + .lines_per_frame = 2046, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 209600, + }, + { + .desc = "imx135_1936_1096_fullfov_max_clock", + .regs = imx135_1080p_nodvs_max_clock, + .width = 1936, + .height = 1096, + .fps_options = { + {/* Pixel Clock : 360.96 MHz */ + .fps = 30, + .pixels_per_line = 5850, + .lines_per_frame = 2000, + }, + {/* Pixel Clock : 360.96 MHz */ + .fps = 60, + .pixels_per_line = 4572, + .lines_per_frame = 1310, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 451200, + }, + { + .desc = "imx135_1080P_dvs_video", + .regs = imx135_2336x1320_max_clock, + .width = 2336, + .height = 1320, + .fps_options = { + {/* Pixel Clock : 360.96 MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2632, + .regs = imx135_2336x1320_max_clock, + .mipi_freq = 451200, + }, + {/* Pixel Clock : 399.36MHz */ + .fps = 60, + .pixels_per_line = 4754, + .lines_per_frame = 1400, + .regs = imx135_2336x1320_cropped_mipi499, + .mipi_freq = 499200, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_6m_cont_cap", + .regs = imx135_6m, + .width = 3280, + .height = 1852, + .fps_options = { + { /* Binning Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, + { + .desc = "imx135_8m_cropped_video", + .regs = imx135_8m_cropped, + .width = 3280, + .height = 2464, + .fps_options = { + { /* Pixel clock: 360.96MHz */ + .fps = 30, + .pixels_per_line = 4572, + .lines_per_frame = 2624, + }, + { + } + }, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .mipi_freq = 451200, + }, +}; + +#endif diff --git a/drivers/staging/media/atomisp/i2c/imx/imx175.h b/drivers/staging/media/atomisp/i2c/imx/imx175.h new file mode 100644 index 0000000000000000000000000000000000000000..5f409ccedc85e249dadeda8b015d7c4f7302a911 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx175.h @@ -0,0 +1,1959 @@ +#ifndef __IMX175_H__ +#define __IMX175_H__ +#include "common.h" + +/************************** settings for imx *************************/ +static struct imx_reg const imx_STILL_8M_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x09}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xC4}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x66}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x0C}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0xD0}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x09}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0xA0}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_8M_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x0B}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xB8}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x16}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x44}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x0C}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0xD0}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x09}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0xA0}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_3M_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEF}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x09}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xC4}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x66}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x08}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x06}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x10}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x19}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_3M_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEF}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x0B}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xB8}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x16}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x44}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x08}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x06}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x10}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x19}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + + +static struct imx_reg const imx_STILL_5M_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEF}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x09}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xC4}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x66}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x0A}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x07}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x90}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x14}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_5M_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEF}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x0B}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xB8}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x16}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x44}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x0A}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x07}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x90}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x14}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_6M_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEF}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x09}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xC4}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x66}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x32}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x6D}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x0C}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0xD0}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x07}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x3C}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_6M_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEF}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x0B}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xB8}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x16}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x44}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x32}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x6D}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x0C}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0xD0}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x07}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x3C}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_2M_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x8C}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x09}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xC4}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x66}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x68}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x04}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0xD0}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_2M_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x0A}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x8C}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x2c}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x0B}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xB8}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x16}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x44}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x68}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x04}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0xD0}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x77}, + {IMX_8BIT, 0x3371, 0x2F}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x2F}, + {IMX_8BIT, 0x3375, 0x37}, + {IMX_8BIT, 0x3376, 0x9F}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x09}, + {IMX_8BIT, 0x33D7, 0xA0}, + + {IMX_8BIT, 0x030e, 0x01}, + {IMX_8BIT, 0x41c0, 0x01}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_PREVIEW_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x44}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x06}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x05}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x48}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x70}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x03}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x34}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x02}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x68}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x02}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x03}, + {IMX_8BIT, 0x33D5, 0x34}, + {IMX_8BIT, 0x33D6, 0x02}, + {IMX_8BIT, 0x33D7, 0x68}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_WIDE_PREVIEW_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x44}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x06}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x0D}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x70}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x10}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x00}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x14}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x8C}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x68}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x03}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0xBC}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x06}, + {IMX_8BIT, 0x33D5, 0x68}, + {IMX_8BIT, 0x33D6, 0x03}, + {IMX_8BIT, 0x33D7, 0xBC}, + {IMX_TOK_TERM, 0, 0} +}; + +/*****************************video************************/ +static struct imx_reg const imx_1080p_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x06}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x4C}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x12}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x06}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xA4}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x11}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0xC6}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x01}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0xDB}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x02}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x42}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0A}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xEA}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x07}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x61}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x09}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x05}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x20}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x6F}, + {IMX_8BIT, 0x3371, 0x27}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x27}, + {IMX_8BIT, 0x3375, 0x2F}, + {IMX_8BIT, 0x3376, 0x97}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x07}, + {IMX_8BIT, 0x33D7, 0x38}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_1080p_no_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x08}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xD5}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x12}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x07}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xD0}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0F}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x3C}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x34}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x6B}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x07}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x94}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x04}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x44}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x1B}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x6F}, + {IMX_8BIT, 0x3371, 0x27}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x27}, + {IMX_8BIT, 0x3375, 0x2F}, + {IMX_8BIT, 0x3376, 0x97}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x07}, + {IMX_8BIT, 0x33D7, 0x38}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_1080p_no_dvs_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x08}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xD5}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x12}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x09}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xA6}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x18}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x9C}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x34}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x6B}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x07}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x94}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x04}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x44}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x1B}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x6F}, + {IMX_8BIT, 0x3371, 0x27}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x27}, + {IMX_8BIT, 0x3375, 0x2F}, + {IMX_8BIT, 0x3376, 0x97}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x07}, + {IMX_8BIT, 0x33D7, 0x38}, + {IMX_TOK_TERM, 0, 0} +}; +/*****************************video************************/ +static struct imx_reg const imx_720p_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x12}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x06}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x00}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x13}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x9C}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x01}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0xD7}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x02}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x3E}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0A}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xEE}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x07}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x65}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x03}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x70}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x00}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x18}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x6F}, + {IMX_8BIT, 0x3371, 0x27}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x27}, + {IMX_8BIT, 0x3375, 0x2F}, + {IMX_8BIT, 0x3376, 0x97}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x07}, + {IMX_8BIT, 0x33D7, 0x38}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_480p_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x12}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x06}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x00}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x13}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x9C}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x01}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0xD4}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0xC8}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0A}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xF1}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x07}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0xDB}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x03}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x70}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x02}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x50}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x02}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x15}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x6F}, + {IMX_8BIT, 0x3371, 0x27}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x27}, + {IMX_8BIT, 0x3375, 0x2F}, + {IMX_8BIT, 0x3376, 0x97}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x07}, + {IMX_8BIT, 0x33D7, 0x38}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_720p_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x44}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x04}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x05}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x48}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x14}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x28}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x48}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x64}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0x87}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x3B}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x20}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x03}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x6C}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x06}, + {IMX_8BIT, 0x33D5, 0x20}, + {IMX_8BIT, 0x33D6, 0x03}, + {IMX_8BIT, 0x33D7, 0x6C}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_STILL_720p_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x44}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x04}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x08}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0xCA}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x18}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x38}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x48}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x64}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0x87}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x3B}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x20}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x03}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x6C}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x06}, + {IMX_8BIT, 0x33D5, 0x20}, + {IMX_8BIT, 0x33D6, 0x03}, + {IMX_8BIT, 0x33D7, 0x6C}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_WVGA_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xEC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x09}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x01}, + {IMX_8BIT, 0x030D, 0x12}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x06}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x00}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x13}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x9C}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0xD0}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x08}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0xCF}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x06}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x68}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x04}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x00}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x01}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x57}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x6F}, + {IMX_8BIT, 0x3371, 0x27}, + {IMX_8BIT, 0x3372, 0x4F}, + {IMX_8BIT, 0x3373, 0x2F}, + {IMX_8BIT, 0x3374, 0x27}, + {IMX_8BIT, 0x3375, 0x2F}, + {IMX_8BIT, 0x3376, 0x97}, + {IMX_8BIT, 0x3377, 0x37}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x0C}, + {IMX_8BIT, 0x33D5, 0xD0}, + {IMX_8BIT, 0x33D6, 0x07}, + {IMX_8BIT, 0x33D7, 0x38}, + {IMX_TOK_TERM, 0, 0} +}; +static struct imx_reg const imx_CIF_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x04}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x06}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x00}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x11}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0xDB}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x01}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x70}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x01}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x30}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x02}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x06}, + {IMX_8BIT, 0x33D5, 0x20}, + {IMX_8BIT, 0x33D6, 0x03}, + {IMX_8BIT, 0x33D7, 0x6C}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_VGA_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x04}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x06}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x00}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x11}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x94}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x03}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x34}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x02}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x68}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x02}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x06}, + {IMX_8BIT, 0x33D5, 0x20}, + {IMX_8BIT, 0x33D6, 0x03}, + {IMX_8BIT, 0x33D7, 0x6C}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_VGA_strong_dvs_15fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0xFC}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x04}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x07}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x9E}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x1C}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0xB6}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x0C}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0xCF}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x09}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x9F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x03}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x34}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x02}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x68}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x02}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x06}, + {IMX_8BIT, 0x33D5, 0x20}, + {IMX_8BIT, 0x33D6, 0x03}, + {IMX_8BIT, 0x33D7, 0x6C}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_QVGA_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x44}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x06}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x05}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x48}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x70}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x03}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0x38}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x02}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x68}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x09}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0x97}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x07}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x37}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x01}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0x98}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x01}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0x34}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x02}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x01}, + {IMX_8BIT, 0x33D5, 0x98}, + {IMX_8BIT, 0x33D6, 0x01}, + {IMX_8BIT, 0x33D7, 0x34}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_QCIF_strong_dvs_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + /* shutter */ + {IMX_8BIT, 0x0202, 0x05}, /* coarse _integration_time[15:8] */ + {IMX_8BIT, 0x0203, 0x44}, /* coarse _integration_time[7:0] */ + /* pll */ + {IMX_8BIT, 0x0301, 0x05}, /* vt_pix_clk_div[7:0] */ + {IMX_8BIT, 0x0303, 0x01}, /* vt_sys_clk_div[7:0] */ + {IMX_8BIT, 0x0305, 0x06}, /* pre_pll_clk_div[7:0] */ + {IMX_8BIT, 0x0309, 0x05}, /* op_pix_clk_div[7:0] */ + {IMX_8BIT, 0x030B, 0x01}, /* op_sys_clk_div[7:0] */ + {IMX_8BIT, 0x030C, 0x00}, + {IMX_8BIT, 0x030D, 0x6D}, + /* image sizing */ + {IMX_8BIT, 0x0340, 0x05}, /* frame_length_lines[15:8] */ + {IMX_8BIT, 0x0341, 0x48}, /* frame_length_lines[7:0] */ + {IMX_8BIT, 0x0342, 0x0D}, /* line_length_pck[15:8] */ + {IMX_8BIT, 0x0343, 0x70}, /* line_length_pck[7:0] */ + {IMX_8BIT, 0x0344, 0x04}, /* x_addr_start[15:8] */ + {IMX_8BIT, 0x0345, 0xB8}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x03}, /* y_addr_start[15:8] */ + {IMX_8BIT, 0x0347, 0x70}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x08}, /* x_addr_end[15:8] */ + {IMX_8BIT, 0x0349, 0x17}, /* x_addr_end[7:0] */ + {IMX_8BIT, 0x034A, 0x06}, /* y_addr_end[15:8] */ + {IMX_8BIT, 0x034B, 0x2F}, /* y_addr_end[7:0] */ + {IMX_8BIT, 0x034C, 0x00}, /* x_output_size[15:8] */ + {IMX_8BIT, 0x034D, 0xD8}, /* x_output_size[7:0] */ + {IMX_8BIT, 0x034E, 0x00}, /* y_output_size[15:8] */ + {IMX_8BIT, 0x034F, 0xB0}, /* y_output_size[7:0] */ + /* binning & scaling */ + {IMX_8BIT, 0x0390, 0x02}, /* binning mode */ + {IMX_8BIT, 0x0401, 0x00}, /* scaling mode*/ + {IMX_8BIT, 0x0405, 0x10}, /* scale_m[7:0] */ + /* timer */ + {IMX_8BIT, 0x3344, 0x37}, + {IMX_8BIT, 0x3345, 0x1F}, + /* timing */ + {IMX_8BIT, 0x3370, 0x5F}, + {IMX_8BIT, 0x3371, 0x17}, + {IMX_8BIT, 0x3372, 0x37}, + {IMX_8BIT, 0x3373, 0x17}, + {IMX_8BIT, 0x3374, 0x17}, + {IMX_8BIT, 0x3375, 0x0F}, + {IMX_8BIT, 0x3376, 0x57}, + {IMX_8BIT, 0x3377, 0x27}, + {IMX_8BIT, 0x33C8, 0x01}, + {IMX_8BIT, 0x33D4, 0x00}, + {IMX_8BIT, 0x33D5, 0xD8}, + {IMX_8BIT, 0x33D6, 0x00}, + {IMX_8BIT, 0x33D7, 0xB0}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx175_init_settings[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0103, 0x01}, + /* misc control */ + {IMX_8BIT, 0x3020, 0x10}, + {IMX_8BIT, 0x302D, 0x02}, + {IMX_8BIT, 0x302F, 0x80}, + {IMX_8BIT, 0x3032, 0xA3}, + {IMX_8BIT, 0x3033, 0x20}, + {IMX_8BIT, 0x3034, 0x24}, + {IMX_8BIT, 0x3041, 0x15}, + {IMX_8BIT, 0x3042, 0x87}, + {IMX_8BIT, 0x3050, 0x35}, + {IMX_8BIT, 0x3056, 0x57}, + {IMX_8BIT, 0x305D, 0x41}, + {IMX_8BIT, 0x3097, 0x69}, + {IMX_8BIT, 0x3109, 0x41}, + {IMX_8BIT, 0x3148, 0x3F}, + {IMX_8BIT, 0x330F, 0x07}, + /* csi & inck */ + {IMX_8BIT, 0x3364, 0x00}, + {IMX_8BIT, 0x3368, 0x13}, + {IMX_8BIT, 0x3369, 0x33}, + /* znr */ + {IMX_8BIT, 0x4100, 0x0E}, + {IMX_8BIT, 0x4104, 0x32}, + {IMX_8BIT, 0x4105, 0x32}, + {IMX_8BIT, 0x4108, 0x01}, + {IMX_8BIT, 0x4109, 0x7C}, + {IMX_8BIT, 0x410A, 0x00}, + {IMX_8BIT, 0x410B, 0x00}, + GROUPED_PARAMETER_HOLD_DISABLE, + {IMX_TOK_TERM, 0, 0} +}; +/* TODO settings of preview/still/video will be updated with new use case */ +struct imx_resolution imx175_res_preview[] = { + { + .desc = "CIF_strong_dvs_30fps", + .regs = imx_CIF_strong_dvs_30fps, + .width = 368, + .height = 304, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x11DB, + .lines_per_frame = 0x0600, + }, + { + } + }, + .mipi_freq = 261500, + + }, + { + .desc = "VGA_strong_dvs_30fps", + .regs = imx_VGA_strong_dvs_30fps, + .width = 820, + .height = 616, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x11DB, + .lines_per_frame = 0x0600, + }, + { + } + }, + .mipi_freq = 261500, + }, + { + .desc = "WIDE_PREVIEW_30fps", + .regs = imx_WIDE_PREVIEW_30fps, + .width = 1640, + .height = 956, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x1000, + .lines_per_frame = 0x0D70, + }, + { + } + }, + .mipi_freq = 174500, + }, + { + .desc = "STILL_720p_30fps", + .regs = imx_STILL_720p_30fps, + .width = 1568, + .height = 876, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x1428, + .lines_per_frame = 0x0548, + }, + { + } + }, + .mipi_freq = 261500, + }, + { + .desc = "STILL_2M_30fps", + .regs = imx_STILL_2M_30fps, + .width = 1640, + .height = 1232, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D66, + .lines_per_frame = 0x09C4, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "1080p_strong_dvs_30fps", + .regs = imx_1080p_no_dvs_30fps, + .width = 1940, + .height = 1092, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0F3C, + .lines_per_frame = 0x07D0, + }, + { + } + }, + .mipi_freq = 292500, + }, + { + .desc = "STILL_3M_30fps", + .regs = imx_STILL_3M_30fps, + .width = 2064, + .height = 1552, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D66, + .lines_per_frame = 0x09C4, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "STILL_5M_30fps", + .regs = imx_STILL_5M_30fps, + .width = 2576, + .height = 1936, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D66, + .lines_per_frame = 0x09C4, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "STILL_6M_30fps", + .regs = imx_STILL_6M_30fps, + .width = 3280, + .height = 1852, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D66, + .lines_per_frame = 0x09C4, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "STILL_8M_30fps", + .regs = imx_STILL_8M_30fps, + .width = 3280, + .height = 2464, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D66, + .lines_per_frame = 0x09C4, + }, + { + } + }, + .mipi_freq = 320000, + }, +}; + +struct imx_resolution imx175_res_still[] = { + { + .desc = "CIF_strong_dvs_30fps", + .regs = imx_CIF_strong_dvs_30fps, + .width = 368, + .height = 304, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x11DB, + .lines_per_frame = 0x0600, + }, + { + } + }, + .mipi_freq = 261000, + }, + { + .desc = "VGA_strong_dvs_15fps", + .regs = imx_VGA_strong_dvs_15fps, + .width = 820, + .height = 616, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1C86, + .lines_per_frame = 0x079E, + }, + { + } + }, + .mipi_freq = 261500, + }, + { + .desc = "imx_STILL_720p_15fps", + .regs = imx_STILL_720p_15fps, + .width = 1568, + .height = 876, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1838, + .lines_per_frame = 0x08CA, + }, + { + } + }, + .mipi_freq = 261500, + }, + { + .desc = "STILL_2M_15fps", + .regs = imx_STILL_2M_15fps, + .width = 1640, + .height = 1232, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1646, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "1080p_strong_dvs_15fps", + .regs = imx_1080p_no_dvs_15fps, + .width = 1940, + .height = 1092, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x189C, + .lines_per_frame = 0x09A6, + }, + { + } + }, + .mipi_freq = 292500, + }, + { + .desc = "STILL_3M_15fps", + .regs = imx_STILL_3M_15fps, + .width = 2064, + .height = 1552, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1646, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "STILL_5M_15fps", + .regs = imx_STILL_5M_15fps, + .width = 2576, + .height = 1936, + .fps = 15, + .pixels_per_line = 0x1646, /* consistent with regs arrays */ + .lines_per_frame = 0x0BB8, /* consistent with regs arrays */ + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1646, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "STILL_6M_15fps", + .regs = imx_STILL_6M_15fps, + .width = 3280, + .height = 1852, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1646, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + .mipi_freq = 320000, + }, + { + .desc = "STILL_8M_15fps", + .regs = imx_STILL_8M_15fps, + .width = 3280, + .height = 2464, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 15, + .pixels_per_line = 0x1646, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + .mipi_freq = 320000, + }, +}; + +struct imx_resolution imx175_res_video[] = { + { + .desc = "QCIF_strong_dvs_30fps", + .regs = imx_QCIF_strong_dvs_30fps, + .width = 216, + .height = 176, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D70, + .lines_per_frame = 0x0548, + }, + { + } + }, + .mipi_freq = 174500, + }, + { + .desc = "QVGA_strong_dvs_30fps", + .regs = imx_QVGA_strong_dvs_30fps, + .width = 408, + .height = 308, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D70, + .lines_per_frame = 0x0548, + }, + { + } + }, + .mipi_freq = 174500, + }, + { + .desc = "VGA_strong_dvs_30fps", + .regs = imx_VGA_strong_dvs_30fps, + .width = 820, + .height = 616, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x1194, + .lines_per_frame = 0x0600, + }, + { + } + }, + .mipi_freq = 261500, + }, + { + .desc = "720p_strong_dvs_30fps", + .regs = imx_720p_strong_dvs_30fps, + .width = 1552, + .height = 880, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x139C, + .lines_per_frame = 0x0600, + }, + { + .fps = 60, + .pixels_per_line = 0xD70, + .lines_per_frame = 0x444, + }, + { + } + }, + .mipi_freq = 292500, + }, + { + .desc = "480p_strong_dvs_30fps", + .regs = imx_480p_strong_dvs_30fps, + .width = 880, + .height = 592, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x139C, + .lines_per_frame = 0x0600, + }, + { + } + }, + .mipi_freq = 292500, + }, + { + .desc = "WVGA_strong_dvs_30fps", + .regs = imx_WVGA_strong_dvs_30fps, + .width = 1640, + .height = 1024, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x139C, + .lines_per_frame = 0x0600, + }, + { + } + }, + .mipi_freq = 292500, + }, + { + .desc = "1080p_strong_dvs_30fps", + .regs = imx_1080p_strong_dvs_30fps, + .width = 2320, + .height = 1312, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x11C6, + .lines_per_frame = 0x06A4, + }, + { + } + }, + .mipi_freq = 292500, + }, +}; + +#endif diff --git a/drivers/staging/media/atomisp/i2c/imx/imx208.h b/drivers/staging/media/atomisp/i2c/imx/imx208.h new file mode 100644 index 0000000000000000000000000000000000000000..fed387f42f999ffc92cdd9c757c8697a9dbfe9a3 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx208.h @@ -0,0 +1,550 @@ +/* + * Support for Sony IMX camera sensor. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __IMX208_H__ +#define __IMX208_H__ +#include "common.h" + +/********************** settings for imx from vendor*********************/ +static struct imx_reg imx208_1080p_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0305, 0x02}, /* PREPLLCK DIV */ + {IMX_8BIT, 0x0307, 0x54}, /* PLL MPY */ + {IMX_8BIT, 0x303C, 0x3C}, /* PLL oscillation stable wait time */ + {IMX_8BIT, 0x30A4, 0x02}, /* Default */ + {IMX_8BIT, 0x0112, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0113, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0340, 0x04}, /* frame length line [15:8] */ + {IMX_8BIT, 0x0341, 0xAA}, /* frame length line [7:0] */ + {IMX_8BIT, 0x0342, 0x08}, /* line length pck [15:8] */ + {IMX_8BIT, 0x0343, 0xC8}, /* line length pck [7:0] */ + {IMX_8BIT, 0x0344, 0x00}, /* x_addr_start[12:8] */ + {IMX_8BIT, 0x0345, 0x00}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[12:8] */ + {IMX_8BIT, 0x0347, 0x00}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x07}, /* x_addr_end [12:8] */ + {IMX_8BIT, 0x0349, 0x8F}, /* x_addr_end [7:0] */ + {IMX_8BIT, 0x034A, 0x04}, /* y_addr_end [12:8] */ + {IMX_8BIT, 0x034B, 0x47}, /* y_addr_end [7:0] */ + {IMX_8BIT, 0x034C, 0x07}, /* x_output_size [ 12:8] */ + {IMX_8BIT, 0x034D, 0x90}, /* x_output_size [7:0] */ + {IMX_8BIT, 0x034E, 0x04}, /* y_output_size [11:8] */ + {IMX_8BIT, 0x034F, 0x48}, /* y_output_size [7:0] */ + {IMX_8BIT, 0x0381, 0x01}, /* x_even_inc */ + {IMX_8BIT, 0x0383, 0x01}, /* x_odd_inc */ + {IMX_8BIT, 0x0385, 0x01}, /* y_even_inc */ + {IMX_8BIT, 0x0387, 0x01}, /* y_odd_inc */ + {IMX_8BIT, 0x3048, 0x00}, /* VMODEFDS binning operation */ + {IMX_8BIT, 0x304E, 0x0A}, /* VTPXCK_DIV */ + {IMX_8BIT, 0x3050, 0x02}, /* OPSYCK_DIV */ + {IMX_8BIT, 0x309B, 0x00}, /* RGDAFDSUMEN */ + {IMX_8BIT, 0x30D5, 0x00}, /* HADDEN ( binning ) */ + {IMX_8BIT, 0x3301, 0x01}, /* RGLANESEL */ + {IMX_8BIT, 0x3318, 0x61}, /* MIPI Global Timing */ + {IMX_8BIT, 0x0202, 0x01}, /* coarse integration time */ + {IMX_8BIT, 0x0203, 0x90}, /* coarse integration time */ + {IMX_8BIT, 0x0205, 0x00}, /* ana global gain */ + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx208_1296x736_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0305, 0x02}, /* PREPLLCK DIV */ + {IMX_8BIT, 0x0307, 0x54}, /* PLL MPY */ + {IMX_8BIT, 0x303C, 0x3C}, /* PLL oscillation stable wait time */ + {IMX_8BIT, 0x30A4, 0x02}, /* Default */ + {IMX_8BIT, 0x0112, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0113, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0340, 0x04}, /* frame length line [15:8] */ + {IMX_8BIT, 0x0341, 0xAA}, /* frame length line [7:0] */ + {IMX_8BIT, 0x0342, 0x08}, /* line length pck [15:8] */ + {IMX_8BIT, 0x0343, 0xC8}, /* line length pck [7:0] */ + {IMX_8BIT, 0x0344, 0x01}, /* x_addr_start[12:8] */ + {IMX_8BIT, 0x0345, 0x40}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[12:8] */ + {IMX_8BIT, 0x0347, 0xB4}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x06}, /* x_addr_end [12:8] */ + {IMX_8BIT, 0x0349, 0x4F}, /* x_addr_end [7:0] */ + {IMX_8BIT, 0x034A, 0x03}, /* y_addr_end [12:8] */ + {IMX_8BIT, 0x034B, 0x93}, /* y_addr_end [7:0] */ + {IMX_8BIT, 0x034C, 0x05}, /* x_output_size [ 12:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size [7:0] */ + {IMX_8BIT, 0x034E, 0x02}, /* y_output_size [11:8] */ + {IMX_8BIT, 0x034F, 0xE0}, /* y_output_size [7:0] */ + {IMX_8BIT, 0x0381, 0x01}, /* x_even_inc */ + {IMX_8BIT, 0x0383, 0x01}, /* x_odd_inc */ + {IMX_8BIT, 0x0385, 0x01}, /* y_even_inc */ + {IMX_8BIT, 0x0387, 0x01}, /* y_odd_inc */ + {IMX_8BIT, 0x3048, 0x00}, /* VMODEFDS binning operation */ + {IMX_8BIT, 0x304E, 0x0A}, /* VTPXCK_DIV */ + {IMX_8BIT, 0x3050, 0x02}, /* OPSYCK_DIV */ + {IMX_8BIT, 0x309B, 0x00}, /* RGDAFDSUMEN */ + {IMX_8BIT, 0x30D5, 0x00}, /* HADDEN ( binning ) */ + {IMX_8BIT, 0x3301, 0x01}, /* RGLANESEL */ + {IMX_8BIT, 0x3318, 0x61}, /* MIPI Global Timing */ + {IMX_8BIT, 0x0202, 0x01}, /* coarse integration time */ + {IMX_8BIT, 0x0203, 0x90}, /* coarse integration time */ + {IMX_8BIT, 0x0205, 0x00}, /* ana global gain */ + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx208_1296x976_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0305, 0x02}, /* PREPLLCK DIV */ + {IMX_8BIT, 0x0307, 0x54}, /* PLL MPY */ + {IMX_8BIT, 0x303C, 0x3C}, /* PLL oscillation stable wait time */ + {IMX_8BIT, 0x30A4, 0x02}, /* Default */ + {IMX_8BIT, 0x0112, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0113, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0340, 0x04}, /* frame length line [15:8] */ + {IMX_8BIT, 0x0341, 0xAA}, /* frame length line [7:0] */ + {IMX_8BIT, 0x0342, 0x08}, /* line length pck [15:8] */ + {IMX_8BIT, 0x0343, 0xC8}, /* line length pck [7:0] */ + {IMX_8BIT, 0x0344, 0x01}, /* x_addr_start[12:8] */ + {IMX_8BIT, 0x0345, 0x40}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[12:8] */ + {IMX_8BIT, 0x0347, 0x3C}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x06}, /* x_addr_end [12:8] */ + {IMX_8BIT, 0x0349, 0x4F}, /* x_addr_end [7:0] */ + {IMX_8BIT, 0x034A, 0x04}, /* y_addr_end [12:8] */ + {IMX_8BIT, 0x034B, 0x0B}, /* y_addr_end [7:0] */ + {IMX_8BIT, 0x034C, 0x05}, /* x_output_size [ 12:8] */ + {IMX_8BIT, 0x034D, 0x10}, /* x_output_size [7:0] */ + {IMX_8BIT, 0x034E, 0x03}, /* y_output_size [11:8] */ + {IMX_8BIT, 0x034F, 0xD0}, /* y_output_size [7:0] */ + {IMX_8BIT, 0x0381, 0x01}, /* x_even_inc */ + {IMX_8BIT, 0x0383, 0x01}, /* x_odd_inc */ + {IMX_8BIT, 0x0385, 0x01}, /* y_even_inc */ + {IMX_8BIT, 0x0387, 0x01}, /* y_odd_inc */ + {IMX_8BIT, 0x3048, 0x00}, /* VMODEFDS binning operation */ + {IMX_8BIT, 0x304E, 0x0A}, /* VTPXCK_DIV */ + {IMX_8BIT, 0x3050, 0x02}, /* OPSYCK_DIV */ + {IMX_8BIT, 0x309B, 0x00}, /* RGDAFDSUMEN */ + {IMX_8BIT, 0x30D5, 0x00}, /* HADDEN ( binning ) */ + {IMX_8BIT, 0x3301, 0x01}, /* RGLANESEL */ + {IMX_8BIT, 0x3318, 0x61}, /* MIPI Global Timing */ + {IMX_8BIT, 0x0202, 0x01}, /* coarse integration time */ + {IMX_8BIT, 0x0203, 0x90}, /* coarse integration time */ + {IMX_8BIT, 0x0205, 0x00}, /* ana global gain */ + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx208_336x256_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0305, 0x02}, /* PREPLLCK DIV */ + {IMX_8BIT, 0x0307, 0x54}, /* PLL MPY */ + {IMX_8BIT, 0x303C, 0x3C}, /* PLL oscillation stable wait time */ + {IMX_8BIT, 0x30A4, 0x02}, /* Default */ + {IMX_8BIT, 0x0112, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0113, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0340, 0x04}, /* frame length line [15:8] */ + {IMX_8BIT, 0x0341, 0xAA}, /* frame length line [7:0] */ + {IMX_8BIT, 0x0342, 0x08}, /* line length pck [15:8] */ + {IMX_8BIT, 0x0343, 0xC8}, /* line length pck [7:0] */ + {IMX_8BIT, 0x0344, 0x02}, /* x_addr_start[12:8] */ + {IMX_8BIT, 0x0345, 0x78}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x01}, /* y_addr_start[12:8] */ + {IMX_8BIT, 0x0347, 0x24}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x05}, /* x_addr_end [12:8] */ + {IMX_8BIT, 0x0349, 0x17}, /* x_addr_end [7:0] */ + {IMX_8BIT, 0x034A, 0x03}, /* y_addr_end [12:8] */ + {IMX_8BIT, 0x034B, 0x23}, /* y_addr_end [7:0] */ + {IMX_8BIT, 0x034C, 0x01}, /* x_output_size [ 12:8] */ + {IMX_8BIT, 0x034D, 0x50}, /* x_output_size [7:0] */ + {IMX_8BIT, 0x034E, 0x01}, /* y_output_size [11:8] */ + {IMX_8BIT, 0x034F, 0x00}, /* y_output_size [7:0] */ + {IMX_8BIT, 0x0381, 0x01}, /* x_even_inc */ + {IMX_8BIT, 0x0383, 0x03}, /* x_odd_inc */ + {IMX_8BIT, 0x0385, 0x01}, /* y_even_inc */ + {IMX_8BIT, 0x0387, 0x03}, /* y_odd_inc */ + {IMX_8BIT, 0x3048, 0x01}, /* VMODEFDS binning operation */ + {IMX_8BIT, 0x304E, 0x0A}, /* VTPXCK_DIV */ + {IMX_8BIT, 0x3050, 0x02}, /* OPSYCK_DIV */ + {IMX_8BIT, 0x309B, 0x00}, /* RGDAFDSUMEN */ + {IMX_8BIT, 0x30D5, 0x03}, /* HADDEN ( binning ) */ + {IMX_8BIT, 0x3301, 0x01}, /* RGLANESEL */ + {IMX_8BIT, 0x3318, 0x66}, /* MIPI Global Timing */ + {IMX_8BIT, 0x0202, 0x01}, /* coarse integration time */ + {IMX_8BIT, 0x0203, 0x90}, /* coarse integration time */ + {IMX_8BIT, 0x0205, 0x00}, /* ana global gain */ + + {IMX_TOK_TERM, 0, 0}, +}; + +static struct imx_reg imx208_192x160_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0305, 0x02}, /* PREPLLCK DIV */ + {IMX_8BIT, 0x0307, 0x54}, /* PLL MPY */ + {IMX_8BIT, 0x303C, 0x3C}, /* PLL oscillation stable wait time */ + {IMX_8BIT, 0x30A4, 0x02}, /* Default */ + {IMX_8BIT, 0x0112, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0113, 0x0A}, /* CCP_data_format : RAW 10bit */ + {IMX_8BIT, 0x0340, 0x04}, /* frame length line [15:8] */ + {IMX_8BIT, 0x0341, 0xAA}, /* frame length line [7:0] */ + {IMX_8BIT, 0x0342, 0x08}, /* line length pck [15:8] */ + {IMX_8BIT, 0x0343, 0xC8}, /* line length pck [7:0] */ + {IMX_8BIT, 0x0344, 0x02}, /* x_addr_start[12:8] */ + {IMX_8BIT, 0x0345, 0x48}, /* x_addr_start[7:0] */ + {IMX_8BIT, 0x0346, 0x00}, /* y_addr_start[12:8] */ + {IMX_8BIT, 0x0347, 0xE4}, /* y_addr_start[7:0] */ + {IMX_8BIT, 0x0348, 0x05}, /* x_addr_end [12:8] */ + {IMX_8BIT, 0x0349, 0x47}, /* x_addr_end [7:0] */ + {IMX_8BIT, 0x034A, 0x03}, /* y_addr_end [12:8] */ + {IMX_8BIT, 0x034B, 0x63}, /* y_addr_end [7:0] */ + {IMX_8BIT, 0x034C, 0x00}, /* x_output_size [ 12:8] */ + {IMX_8BIT, 0x034D, 0xC0}, /* x_output_size [7:0] */ + {IMX_8BIT, 0x034E, 0x00}, /* y_output_size [11:8] */ + {IMX_8BIT, 0x034F, 0xA0}, /* y_output_size [7:0] */ + {IMX_8BIT, 0x0381, 0x03}, /* x_even_inc */ + {IMX_8BIT, 0x0383, 0x05}, /* x_odd_inc */ + {IMX_8BIT, 0x0385, 0x03}, /* y_even_inc */ + {IMX_8BIT, 0x0387, 0x05}, /* y_odd_inc */ + {IMX_8BIT, 0x3048, 0x01}, /* VMODEFDS binning operation */ + {IMX_8BIT, 0x304E, 0x0A}, /* VTPXCK_DIV */ + {IMX_8BIT, 0x3050, 0x02}, /* OPSYCK_DIV */ + {IMX_8BIT, 0x309B, 0x00}, /* RGDAFDSUMEN */ + {IMX_8BIT, 0x30D5, 0x03}, /* HADDEN ( binning ) */ + {IMX_8BIT, 0x3301, 0x11}, /* RGLANESEL */ + {IMX_8BIT, 0x3318, 0x74}, /* MIPI Global Timing */ + {IMX_8BIT, 0x0202, 0x01}, /* coarse integration time */ + {IMX_8BIT, 0x0203, 0x90}, /* coarse integration time */ + {IMX_8BIT, 0x0205, 0x00}, /* ana global gain */ + + {IMX_TOK_TERM, 0, 0}, +}; +/********************** settings for imx - reference *********************/ +static struct imx_reg const imx208_init_settings[] = { + { IMX_TOK_TERM, 0, 0} +}; + +struct imx_resolution imx208_res_preview[] = { + { + .desc = "imx208_1080p_30fps", + .regs = imx208_1080p_30fps, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_1296x976_30fps", + .regs = imx208_1296x976_30fps, + .width = 1296, + .height = 976, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_1296x736_30fps", + .regs = imx208_1296x736_30fps, + .width = 1296, + .height = 736, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_336x256_30fps", + .regs = imx208_336x256_30fps, + .width = 336, + .height = 256, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .skip_frames = 2, + .mipi_freq = 201600, + }, + { + .desc = "imx208_192x160_30fps", + .regs = imx208_192x160_30fps, + .width = 192, + .height = 160, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .skip_frames = 2, + .mipi_freq = 100800, + }, +}; + +struct imx_resolution imx208_res_still[] = { + { + .desc = "imx208_1080p_30fps", + .regs = imx208_1080p_30fps, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_1296x976_30fps", + .regs = imx208_1296x976_30fps, + .width = 1296, + .height = 976, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_1296x736_30fps", + .regs = imx208_1296x736_30fps, + .width = 1296, + .height = 736, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_336x256_30fps", + .regs = imx208_336x256_30fps, + .width = 336, + .height = 256, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .skip_frames = 2, + .mipi_freq = 201600, + }, + { + .desc = "imx208_192x160_30fps", + .regs = imx208_192x160_30fps, + .width = 192, + .height = 160, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .skip_frames = 2, + .mipi_freq = 100800, + }, +}; + +struct imx_resolution imx208_res_video[] = { + { + .desc = "imx208_1080p_30fps", + .regs = imx208_1080p_30fps, + .width = 1936, + .height = 1096, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_1296x976_30fps", + .regs = imx208_1296x976_30fps, + .width = 1296, + .height = 976, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_1296x736_30fps", + .regs = imx208_1296x736_30fps, + .width = 1296, + .height = 736, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 1, + .bin_factor_y = 1, + .used = 0, + .skip_frames = 2, + .mipi_freq = 403200, + }, + { + .desc = "imx208_336x256_30fps", + .regs = imx208_336x256_30fps, + .width = 336, + .height = 256, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 2, + .bin_factor_y = 2, + .used = 0, + .skip_frames = 2, + .mipi_freq = 201600, + }, + { + .desc = "imx208_192x160_30fps", + .regs = imx208_192x160_30fps, + .width = 192, + .height = 160, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x08C8, + .lines_per_frame = 0x04AA, + }, + { + } + }, + .bin_factor_x = 4, + .bin_factor_y = 4, + .used = 0, + .skip_frames = 2, + .mipi_freq = 100800, + }, +}; +#endif + diff --git a/drivers/staging/media/atomisp/i2c/imx/imx219.h b/drivers/staging/media/atomisp/i2c/imx/imx219.h new file mode 100644 index 0000000000000000000000000000000000000000..52df582c56d84898b1724760fbdb061879bc7280 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx219.h @@ -0,0 +1,227 @@ +#ifndef __IMX219_H__ +#define __IMX219_H__ +#include "common.h" + +#define IMX219_FRAME_LENGTH_LINES 0x0160 +#define IMX219_LINE_LENGTH_PIXELS 0x0162 +#define IMX219_HORIZONTAL_START_H 0x0164 +#define IMX219_VERTICAL_START_H 0x0168 +#define IMX219_HORIZONTAL_END_H 0x0166 +#define IMX219_VERTICAL_END_H 0x016A +#define IMX219_HORIZONTAL_OUTPUT_SIZE_H 0x016c +#define IMX219_VERTICAL_OUTPUT_SIZE_H 0x016E +#define IMX219_COARSE_INTEGRATION_TIME 0x015A +#define IMX219_IMG_ORIENTATION 0x0172 +#define IMX219_GLOBAL_GAIN 0x0157 +#define IMX219_DGC_ADJ 0x0158 + +#define IMX219_DGC_LEN 4 + +/************************** settings for imx *************************/ +static struct imx_reg const imx219_STILL_8M_30fps[] = { + {IMX_8BIT, 0x30EB, 0x05}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x30EB, 0x0C}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x300A, 0xFF}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x300B, 0xFF}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x30EB, 0x05}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x30EB, 0x09}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x0114, 0x03}, /*CSI_LANE_MODE[1:0}*/ + {IMX_8BIT, 0x0128, 0x00}, /*DPHY_CNTRL*/ + {IMX_8BIT, 0x012A, 0x13}, /*EXCK_FREQ[15:8]*/ + {IMX_8BIT, 0x012B, 0x34}, /*EXCK_FREQ[7:0]*/ + {IMX_8BIT, 0x0160, 0x0A}, /*FRM_LENGTH_A[15:8]*/ + {IMX_8BIT, 0x0161, 0x94}, /*FRM_LENGTH_A[7:0]*/ + {IMX_8BIT, 0x0162, 0x0D}, /*LINE_LENGTH_A[15:8]*/ + {IMX_8BIT, 0x0163, 0x78}, /*LINE_LENGTH_A[7:0]*/ + {IMX_8BIT, 0x0164, 0x00}, /*X_ADD_STA_A[11:8]*/ + {IMX_8BIT, 0x0165, 0x00}, /*X_ADD_STA_A[7:0]*/ + {IMX_8BIT, 0x0166, 0x0C}, /*X_ADD_END_A[11:8]*/ + {IMX_8BIT, 0x0167, 0xCF}, /*X_ADD_END_A[7:0]*/ + {IMX_8BIT, 0x0168, 0x00}, /*Y_ADD_STA_A[11:8]*/ + {IMX_8BIT, 0x0169, 0x00}, /*Y_ADD_STA_A[7:0]*/ + {IMX_8BIT, 0x016A, 0x09}, /*Y_ADD_END_A[11:8]*/ + {IMX_8BIT, 0x016B, 0x9F}, /*Y_ADD_END_A[7:0]*/ + {IMX_8BIT, 0x016C, 0x0C}, /*X_OUTPUT_SIZE_A[11:8]*/ + {IMX_8BIT, 0x016D, 0xD0}, /*X_OUTPUT_SIZE_A[7:0]*/ + {IMX_8BIT, 0x016E, 0x09}, /*Y_OUTPUT_SIZE_A[11:8]*/ + {IMX_8BIT, 0x016F, 0xA0}, /*Y_OUTPUT_SIZE_A[7:0]*/ + {IMX_8BIT, 0x0170, 0x01}, /*X_ODD_INC_A[2:0]*/ + {IMX_8BIT, 0x0171, 0x01}, /*Y_ODD_INC_A[2:0]*/ + {IMX_8BIT, 0x0174, 0x00}, /*BINNING_MODE_H_A*/ + {IMX_8BIT, 0x0175, 0x00}, /*BINNING_MODE_V_A*/ + {IMX_8BIT, 0x018C, 0x0A}, /*CSI_DATA_FORMAT_A[15:8]*/ + {IMX_8BIT, 0x018D, 0x0A}, /*CSI_DATA_FORMAT_A[7:0]*/ + {IMX_8BIT, 0x0301, 0x05}, /*VTPXCK_DIV*/ + {IMX_8BIT, 0x0303, 0x01}, /*VTSYCK_DIV*/ + {IMX_8BIT, 0x0304, 0x02}, /*PREPLLCK_VT_DIV[3:0]*/ + {IMX_8BIT, 0x0305, 0x02}, /*PREPLLCK_OP_DIV[3:0]*/ + {IMX_8BIT, 0x0306, 0x00}, /*PLL_VT_MPY[10:8]*/ + {IMX_8BIT, 0x0307, 0x49}, /*PLL_VT_MPY[7:0]*/ + {IMX_8BIT, 0x0309, 0x0A}, /*OPPXCK_DIV[4:0]*/ + {IMX_8BIT, 0x030B, 0x01}, /*OPSYCK_DIV*/ + {IMX_8BIT, 0x030C, 0x00}, /*PLL_OP_MPY[10:8]*/ + {IMX_8BIT, 0x030D, 0x4C}, /*PLL_OP_MPY[7:0]*/ + {IMX_8BIT, 0x4767, 0x0F}, /*CIS Tuning*/ + {IMX_8BIT, 0x4750, 0x14}, /*CIS Tuning*/ + {IMX_8BIT, 0x47B4, 0x14}, /*CIS Tuning*/ + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx219_STILL_6M_30fps[] = { + {IMX_8BIT, 0x30EB, 0x05}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x30EB, 0x0C}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x300A, 0xFF}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x300B, 0xFF}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x30EB, 0x05}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x30EB, 0x09}, /*Access Code for address over 0x3000*/ + {IMX_8BIT, 0x0114, 0x03}, /*CSI_LANE_MODE[1:0}*/ + {IMX_8BIT, 0x0128, 0x00}, /*DPHY_CNTRL*/ + {IMX_8BIT, 0x012A, 0x13}, /*EXCK_FREQ[15:8]*/ + {IMX_8BIT, 0x012B, 0x34}, /*EXCK_FREQ[7:0]*/ + {IMX_8BIT, 0x0160, 0x07}, /*FRM_LENGTH_A[15:8]*/ + {IMX_8BIT, 0x0161, 0x64}, /*FRM_LENGTH_A[7:0]*/ + {IMX_8BIT, 0x0162, 0x0D}, /*LINE_LENGTH_A[15:8]*/ + {IMX_8BIT, 0x0163, 0x78}, /*LINE_LENGTH_A[7:0]*/ + {IMX_8BIT, 0x0164, 0x00}, /*X_ADD_STA_A[11:8]*/ + {IMX_8BIT, 0x0165, 0x00}, /*X_ADD_STA_A[7:0]*/ + {IMX_8BIT, 0x0166, 0x0C}, /*X_ADD_END_A[11:8]*/ + {IMX_8BIT, 0x0167, 0xCF}, /*X_ADD_END_A[7:0]*/ + {IMX_8BIT, 0x0168, 0x01}, /*Y_ADD_STA_A[11:8]*/ + {IMX_8BIT, 0x0169, 0x32}, /*Y_ADD_STA_A[7:0]*/ + {IMX_8BIT, 0x016A, 0x08}, /*Y_ADD_END_A[11:8]*/ + {IMX_8BIT, 0x016B, 0x6D}, /*Y_ADD_END_A[7:0]*/ + {IMX_8BIT, 0x016C, 0x0C}, /*X_OUTPUT_SIZE_A[11:8]*/ + {IMX_8BIT, 0x016D, 0xD0}, /*X_OUTPUT_SIZE_A[7:0]*/ + {IMX_8BIT, 0x016E, 0x07}, /*Y_OUTPUT_SIZE_A[11:8]*/ + {IMX_8BIT, 0x016F, 0x3C}, /*Y_OUTPUT_SIZE_A[7:0]*/ + {IMX_8BIT, 0x0170, 0x01}, /*X_ODD_INC_A[2:0]*/ + {IMX_8BIT, 0x0171, 0x01}, /*Y_ODD_INC_A[2:0]*/ + {IMX_8BIT, 0x0174, 0x00}, /*BINNING_MODE_H_A*/ + {IMX_8BIT, 0x0175, 0x00}, /*BINNING_MODE_V_A*/ + {IMX_8BIT, 0x018C, 0x0A}, /*CSI_DATA_FORMAT_A[15:8]*/ + {IMX_8BIT, 0x018D, 0x0A}, /*CSI_DATA_FORMAT_A[7:0]*/ + {IMX_8BIT, 0x0301, 0x05}, /*VTPXCK_DIV*/ + {IMX_8BIT, 0x0303, 0x01}, /*VTSYCK_DIV*/ + {IMX_8BIT, 0x0304, 0x02}, /*PREPLLCK_VT_DIV[3:0]*/ + {IMX_8BIT, 0x0305, 0x02}, /*PREPLLCK_OP_DIV[3:0]*/ + {IMX_8BIT, 0x0306, 0x00}, /*PLL_VT_MPY[10:8]*/ + {IMX_8BIT, 0x0307, 0x33}, /*PLL_VT_MPY[7:0]*/ + {IMX_8BIT, 0x0309, 0x0A}, /*OPPXCK_DIV[4:0]*/ + {IMX_8BIT, 0x030B, 0x01}, /*OPSYCK_DIV*/ + {IMX_8BIT, 0x030C, 0x00}, /*PLL_OP_MPY[10:8]*/ + {IMX_8BIT, 0x030D, 0x36}, /*PLL_OP_MPY[7:0]*/ + {IMX_8BIT, 0x4767, 0x0F}, /*CIS Tuning*/ + {IMX_8BIT, 0x4750, 0x14}, /*CIS Tuning*/ + {IMX_8BIT, 0x47B4, 0x14}, /*CIS Tuning*/ + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx219_init_settings[] = { + {IMX_TOK_TERM, 0, 0} +}; + +struct imx_resolution imx219_res_preview[] = { + { + .desc = "STILL_6M_30fps", + .regs = imx219_STILL_6M_30fps, + .width = 3280, + .height = 1852, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D78, + .lines_per_frame = 0x0764, + }, + { + } + }, + .mipi_freq = 259000, + }, + { + .desc = "STILL_8M_30fps", + .regs = imx219_STILL_8M_30fps, + .width = 3280, + .height = 2464, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D78, + .lines_per_frame = 0x0A94, + }, + { + } + }, + .mipi_freq = 365000, + }, +}; + +struct imx_resolution imx219_res_still[] = { + { + .desc = "STILL_6M_30fps", + .regs = imx219_STILL_6M_30fps, + .width = 3280, + .height = 1852, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D78, + .lines_per_frame = 0x0764, + }, + { + } + }, + .mipi_freq = 259000, + }, + { + .desc = "STILL_8M_30fps", + .regs = imx219_STILL_8M_30fps, + .width = 3280, + .height = 2464, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D78, + .lines_per_frame = 0x0A94, + }, + { + } + }, + .mipi_freq = 365000, + }, +}; + +struct imx_resolution imx219_res_video[] = { + { + .desc = "STILL_6M_30fps", + .regs = imx219_STILL_6M_30fps, + .width = 3280, + .height = 1852, + .bin_factor_x = 0, + .bin_factor_y = 0, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0D78, + .lines_per_frame = 0x0764, + }, + { + } + }, + .mipi_freq = 259000, + }, +}; + +#endif diff --git a/drivers/staging/media/atomisp/i2c/imx/imx227.h b/drivers/staging/media/atomisp/i2c/imx/imx227.h new file mode 100644 index 0000000000000000000000000000000000000000..10e5b86f6687641f0aad18059bcdd72b989accd8 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/imx227.h @@ -0,0 +1,726 @@ +#ifndef __IMX227_H__ +#define __IMX227_H__ + +#include "common.h" + +#define IMX227_EMBEDDED_DATA_LINE_NUM 2 +#define IMX227_OUTPUT_DATA_FORMAT_REG 0x0112 +#define IMX227_OUTPUT_FORMAT_RAW10 0x0a0a + +/* AE Bracketing Registers */ +#define IMX227_BRACKETING_LUT_MODE_BIT_CONTINUE_STREAMING 0x1 +#define IMX227_BRACKETING_LUT_MODE_BIT_LOOP_MODE 0x2 + +#define IMX227_BRACKETING_LUT_CONTROL 0x0E00 +#define IMX227_BRACKETING_LUT_MODE 0x0E01 +#define IMX227_BRACKETING_LUT_ENTRY_CONTROL 0x0E02 + +/* + * The imx135 embedded data info: + * embedded data line num: 2 + * line 0 effective data size(byte): 76 + * line 1 effective data size(byte): 113 + */ +static const uint32_t +imx227_embedded_effective_size[IMX227_EMBEDDED_DATA_LINE_NUM] = {160, 62}; + +/************************** settings for imx *************************/ +/* Full Output Mode */ +static struct imx_reg const imx_STILL_6_5M_25fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x6259, 0x06}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xd0}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3f}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* 4:3 Output Mode */ +static struct imx_reg const imx_STILL_5_5M_3X4_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0xb0}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x00}, + {IMX_8BIT, 0x0348, 0x08}, + {IMX_8BIT, 0x0349, 0xaf}, + {IMX_8BIT, 0x034a, 0x0a}, + {IMX_8BIT, 0x034b, 0x9f}, + {IMX_8BIT, 0x034c, 0x08}, + {IMX_8BIT, 0x034d, 0x00}, + {IMX_8BIT, 0x034e, 0x0a}, + {IMX_8BIT, 0x034f, 0xa0}, + + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xd8}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3f}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* Square Output Mode */ +static struct imx_reg const imx_STILL_5_7M_1X1_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0344, 0x00}, + {IMX_8BIT, 0x0345, 0x00}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0xa0}, + {IMX_8BIT, 0x0348, 0x09}, + {IMX_8BIT, 0x0349, 0x5f}, + {IMX_8BIT, 0x034a, 0x09}, + {IMX_8BIT, 0x034b, 0xff}, + {IMX_8BIT, 0x034c, 0x09}, + {IMX_8BIT, 0x034d, 0x60}, + {IMX_8BIT, 0x034e, 0x09}, + {IMX_8BIT, 0x034f, 0x60}, + + {IMX_8BIT, 0x6259, 0x06}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xd4}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3f}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* Full Frame 1080P Mode (use ISP scaler)*/ +static struct imx_reg const imx_VIDEO_4M_9X16_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xdc}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3f}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* Cropped 1080P Mode */ +static struct imx_reg const imx_VIDEO_2M_9X16_45fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0112, 0x0a}, + {IMX_8BIT, 0x0113, 0x0a}, + {IMX_8BIT, 0x0344, 0x02}, + {IMX_8BIT, 0x0345, 0x8a}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0x88}, + {IMX_8BIT, 0x0348, 0x06}, + {IMX_8BIT, 0x0349, 0xd1}, + {IMX_8BIT, 0x034a, 0x09}, + {IMX_8BIT, 0x034b, 0x17}, + {IMX_8BIT, 0x034c, 0x04}, + {IMX_8BIT, 0x034d, 0x48}, + {IMX_8BIT, 0x034e, 0x07}, + {IMX_8BIT, 0x034f, 0x90}, + + {IMX_8BIT, 0x0380, 0x00}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0382, 0x00}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0384, 0x00}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0386, 0x00}, + {IMX_8BIT, 0x0387, 0x01}, + + {IMX_8BIT, 0x0408, 0x00}, + {IMX_8BIT, 0x0409, 0x00}, + {IMX_8BIT, 0x040a, 0x00}, + {IMX_8BIT, 0x040b, 0x00}, + {IMX_8BIT, 0x040c, 0x04}, + {IMX_8BIT, 0x040d, 0x48}, + {IMX_8BIT, 0x040e, 0x07}, + {IMX_8BIT, 0x040f, 0x90}, + + {IMX_8BIT, 0x0900, 0x00}, + {IMX_8BIT, 0x0901, 0x00}, + + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xdc}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3c}, /* preset_en */ + + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* Moment mode */ +static struct imx_reg const imx_VIDEO_1_3M_3X4_60fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xd9}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3f}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* High Speed 3:4 mode */ +static struct imx_reg const imx_VIDEO_VGA_3X4_120fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x9004, 0xca}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3f}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + + +/* Binned 720P mode */ +static struct imx_reg const imx_VIDEO_1M_9X16_60fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0112, 0x0a}, + {IMX_8BIT, 0x0113, 0x0a}, + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0xd0}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x40}, + {IMX_8BIT, 0x0348, 0x07}, + {IMX_8BIT, 0x0349, 0x8f}, + {IMX_8BIT, 0x034a, 0x0a}, + {IMX_8BIT, 0x034b, 0x5f}, + {IMX_8BIT, 0x034c, 0x02}, + {IMX_8BIT, 0x034d, 0xe0}, + {IMX_8BIT, 0x034e, 0x05}, + {IMX_8BIT, 0x034f, 0x10}, + + {IMX_8BIT, 0x0380, 0x00}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0382, 0x00}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0384, 0x00}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0386, 0x00}, + {IMX_8BIT, 0x0387, 0x01}, + + {IMX_8BIT, 0x0408, 0x00}, + {IMX_8BIT, 0x0409, 0x00}, + {IMX_8BIT, 0x040a, 0x00}, + {IMX_8BIT, 0x040b, 0x00}, + {IMX_8BIT, 0x040c, 0x02}, + {IMX_8BIT, 0x040d, 0xe0}, + {IMX_8BIT, 0x040e, 0x05}, + {IMX_8BIT, 0x040f, 0x10}, + + {IMX_8BIT, 0x0900, 0x01}, + {IMX_8BIT, 0x0901, 0x22}, + + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xdd}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3c}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +/* Binned 496x868 mode */ +static struct imx_reg const imx_VIDEO_496x868_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0112, 0x0a}, + {IMX_8BIT, 0x0113, 0x0a}, + {IMX_8BIT, 0x0344, 0x02}, + {IMX_8BIT, 0x0345, 0xc0}, + {IMX_8BIT, 0x0346, 0x01}, + {IMX_8BIT, 0x0347, 0xec}, + {IMX_8BIT, 0x0348, 0x06}, + {IMX_8BIT, 0x0349, 0x9f}, + {IMX_8BIT, 0x034a, 0x08}, + {IMX_8BIT, 0x034b, 0xb3}, + {IMX_8BIT, 0x034c, 0x01}, + {IMX_8BIT, 0x034d, 0xf0}, + {IMX_8BIT, 0x034e, 0x03}, + {IMX_8BIT, 0x034f, 0x64}, + + {IMX_8BIT, 0x0380, 0x00}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0382, 0x00}, + {IMX_8BIT, 0x0383, 0x01}, + {IMX_8BIT, 0x0384, 0x00}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0386, 0x00}, + {IMX_8BIT, 0x0387, 0x01}, + + {IMX_8BIT, 0x0408, 0x00}, + {IMX_8BIT, 0x0409, 0x00}, + {IMX_8BIT, 0x040a, 0x00}, + {IMX_8BIT, 0x040b, 0x00}, + {IMX_8BIT, 0x040c, 0x01}, + {IMX_8BIT, 0x040d, 0xf0}, + {IMX_8BIT, 0x040e, 0x03}, + {IMX_8BIT, 0x040f, 0x64}, + + {IMX_8BIT, 0x0900, 0x01}, + {IMX_8BIT, 0x0901, 0x22}, + + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xdd}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3c}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + + +/* Hangout mode */ +static struct imx_reg const imx_PREVIEW_374X652_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0112, 0x0a}, + {IMX_8BIT, 0x0113, 0x0a}, + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0xc0}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x30}, + {IMX_8BIT, 0x0348, 0x07}, + {IMX_8BIT, 0x0349, 0x9f}, + {IMX_8BIT, 0x034a, 0x0a}, + {IMX_8BIT, 0x034b, 0x6f}, + {IMX_8BIT, 0x034c, 0x01}, + {IMX_8BIT, 0x034d, 0x78}, + {IMX_8BIT, 0x034e, 0x02}, + {IMX_8BIT, 0x034f, 0x90}, + + {IMX_8BIT, 0x0380, 0x00}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0382, 0x00}, + {IMX_8BIT, 0x0383, 0x03}, + {IMX_8BIT, 0x0384, 0x00}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0386, 0x00}, + {IMX_8BIT, 0x0387, 0x03}, + + {IMX_8BIT, 0x0408, 0x00}, + {IMX_8BIT, 0x0409, 0x00}, + {IMX_8BIT, 0x040a, 0x00}, + {IMX_8BIT, 0x040b, 0x02}, + {IMX_8BIT, 0x040c, 0x01}, + {IMX_8BIT, 0x040d, 0x76}, + {IMX_8BIT, 0x040e, 0x02}, + {IMX_8BIT, 0x040f, 0x8c}, + + {IMX_8BIT, 0x0900, 0x01}, + {IMX_8BIT, 0x0901, 0x22}, + + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xde}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3c}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + +static struct imx_reg const imx_VIDEO_NHD_9X16_30fps[] = { + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0112, 0x0a}, + {IMX_8BIT, 0x0113, 0x0a}, + {IMX_8BIT, 0x0344, 0x01}, + {IMX_8BIT, 0x0345, 0xc0}, + {IMX_8BIT, 0x0346, 0x00}, + {IMX_8BIT, 0x0347, 0x30}, + {IMX_8BIT, 0x0348, 0x07}, + {IMX_8BIT, 0x0349, 0x9f}, + {IMX_8BIT, 0x034a, 0x0a}, + {IMX_8BIT, 0x034b, 0x6f}, + {IMX_8BIT, 0x034c, 0x01}, + {IMX_8BIT, 0x034d, 0x78}, + {IMX_8BIT, 0x034e, 0x02}, + {IMX_8BIT, 0x034f, 0x90}, + + {IMX_8BIT, 0x0380, 0x00}, + {IMX_8BIT, 0x0381, 0x01}, + {IMX_8BIT, 0x0382, 0x00}, + {IMX_8BIT, 0x0383, 0x03}, + {IMX_8BIT, 0x0384, 0x00}, + {IMX_8BIT, 0x0385, 0x01}, + {IMX_8BIT, 0x0386, 0x00}, + {IMX_8BIT, 0x0387, 0x03}, + + {IMX_8BIT, 0x0408, 0x00}, + {IMX_8BIT, 0x0409, 0x00}, + {IMX_8BIT, 0x040a, 0x00}, + {IMX_8BIT, 0x040b, 0x00}, + {IMX_8BIT, 0x040c, 0x01}, + {IMX_8BIT, 0x040d, 0x78}, + {IMX_8BIT, 0x040e, 0x02}, + {IMX_8BIT, 0x040f, 0x90}, + + {IMX_8BIT, 0x0900, 0x01}, + {IMX_8BIT, 0x0901, 0x22}, + + {IMX_8BIT, 0x6259, 0x05}, /* latency ctrl */ + {IMX_8BIT, 0x9004, 0xde}, /* preset_sel */ + {IMX_8BIT, 0x9005, 0x3c}, /* preset_en */ + {IMX_8BIT, 0x0136, 0x13}, + {IMX_8BIT, 0x0137, 0x33}, + {IMX_TOK_TERM, 0, 0} +}; + + +static struct imx_reg const imx227_init_settings[] = { + {IMX_8BIT, 0x0100, 0x00}, /* mode_select */ + GROUPED_PARAMETER_HOLD_ENABLE, + {IMX_8BIT, 0x0306, 0x00}, + {IMX_8BIT, 0x0307, 0xBB}, + {IMX_8BIT, 0x030E, 0x03}, + {IMX_8BIT, 0x030F, 0x0D}, + {IMX_8BIT, 0x463b, 0x30}, + {IMX_8BIT, 0x463e, 0x05}, + {IMX_8BIT, 0x4612, 0x66}, + {IMX_8BIT, 0x4815, 0x65}, + {IMX_8BIT, 0x4991, 0x00}, + {IMX_8BIT, 0x4992, 0x01}, + {IMX_8BIT, 0x4993, 0xff}, + {IMX_8BIT, 0x458b, 0x00}, + {IMX_8BIT, 0x452a, 0x02}, + {IMX_8BIT, 0x4a7c, 0x00}, + {IMX_8BIT, 0x4a7d, 0x1c}, + {IMX_8BIT, 0x4a7e, 0x00}, + {IMX_8BIT, 0x4a7f, 0x17}, + {IMX_8BIT, 0x462C, 0x2E}, + {IMX_8BIT, 0x461B, 0x28}, + {IMX_8BIT, 0x4663, 0x29}, + {IMX_8BIT, 0x461A, 0x7C}, + {IMX_8BIT, 0x4619, 0x28}, + {IMX_8BIT, 0x4667, 0x22}, + {IMX_8BIT, 0x466B, 0x23}, + {IMX_8BIT, 0x40AD, 0xFF}, + {IMX_8BIT, 0x40BE, 0x00}, + {IMX_8BIT, 0x40BF, 0x6E}, + {IMX_8BIT, 0x40CE, 0x00}, + {IMX_8BIT, 0x40CF, 0x0A}, + {IMX_8BIT, 0x40CA, 0x00}, + {IMX_8BIT, 0x40CB, 0x1F}, + {IMX_8BIT, 0x4D16, 0x00}, + {IMX_8BIT, 0x6204, 0x01}, + {IMX_8BIT, 0x6209, 0x00}, + {IMX_8BIT, 0x621F, 0x01}, + {IMX_8BIT, 0x621E, 0x10}, + GROUPED_PARAMETER_HOLD_DISABLE, + {IMX_TOK_TERM, 0, 0} +}; + +/* TODO settings of preview/still/video will be updated with new use case */ +struct imx_resolution imx227_res_preview[] = { + { + .desc = "imx_PREVIEW_374X652_30fps", + .regs = imx_PREVIEW_374X652_30fps, + .width = 374, + .height = 652, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C0A, + }, + { + } + }, + }, + { + .desc = "imx_VIDEO_496x868_30fps", + .regs = imx_VIDEO_496x868_30fps, + .width = 496, + .height = 868, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C08, + }, + { + } + }, + }, + { + .desc = "imx_STILL_5_5M_3X4_30fps", + .regs = imx_STILL_5_5M_3X4_30fps, + .width = 2048, + .height = 2720, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0ED8, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + + }, + { + .desc = "imx_STILL_5_7M_1X1_30fps", + .regs = imx_STILL_5_7M_1X1_30fps, + .width = 2400, + .height = 2400, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x1130, + .lines_per_frame = 0x0A1E, + }, + { + } + }, + + }, + { + .desc = "imx_STILL_6_5M_25fps", + .regs = imx_STILL_6_5M_25fps, + .width = 2400, + .height = 2720, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 25, + .pixels_per_line = 0x1130, + .lines_per_frame = 0x0C24, + }, + { + } + }, + } +}; + +struct imx_resolution imx227_res_still[] = { + { + .desc = "imx_STILL_5_5M_3X4_30fps", + .regs = imx_STILL_5_5M_3X4_30fps, + .width = 2048, + .height = 2720, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 6, + .pixels_per_line = 0x2130, + .lines_per_frame = 0x1A22, + }, + { + .fps = 30, + .pixels_per_line = 0x0ED8, + .lines_per_frame = 0x0BB8, + }, + { + } + }, + + }, + { + .desc = "imx_STILL_5_7M_1X1_30fps", + .regs = imx_STILL_5_7M_1X1_30fps, + .width = 2400, + .height = 2400, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 6, + .pixels_per_line = 0x266E, + .lines_per_frame = 0x1704, + }, + { + .fps = 30, + .pixels_per_line = 0x1130, + .lines_per_frame = 0x0A1E, + }, + { + } + }, + + }, + { + .desc = "imx_STILL_6_5M_25fps", + .regs = imx_STILL_6_5M_25fps, + .width = 2400, + .height = 2720, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 25, + .pixels_per_line = 0x1130, + .lines_per_frame = 0x0C24, + }, + { + } + }, + }, +}; + +struct imx_resolution imx227_res_video[] = { + { + .desc = "imx_VIDEO_4M_9X16_30fps", + .regs = imx_VIDEO_4M_9X16_30fps, + .width = 1536, + .height = 2720, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C08, + }, + { + } + }, + + }, + { + .desc = "imx_VIDEO_2M_9X16_45fps", + .regs = imx_VIDEO_2M_9X16_45fps, + .width = 1096, + .height = 1936, + .bin_factor_x = 0, + .bin_factor_y = 0, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C08, + }, + { + .fps = 45, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0800, + }, + { + } + }, + + }, + { + .desc = "imx_VIDEO_1_3M_3X4_60fps", + .regs = imx_VIDEO_1_3M_3X4_60fps, + .width = 1024, + .height = 1360, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 60, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0604, + }, + { + } + }, + }, + { + .desc = "imx_VIDEO_496x868_30fps", + .regs = imx_VIDEO_496x868_30fps, + .width = 496, + .height = 868, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C08, + }, + { + } + }, + }, + { + .desc = "imx_VIDEO_1M_9X16_60fps", + .regs = imx_VIDEO_1M_9X16_60fps, + .width = 736, + .height = 1296, + .bin_factor_x = 1, + .bin_factor_y = 1, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 60, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0604, + }, + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C10, + }, + { + } + }, + }, + { + .desc = "imx_VIDEO_VGA_3X4_120fps", + .regs = imx_VIDEO_VGA_3X4_120fps, + .width = 512, + .height = 680, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 120, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0302, + }, + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C08, + }, + { + } + }, + }, + { + .desc = "imx_VIDEO_NHD_9X16_30fps", + .regs = imx_VIDEO_NHD_9X16_30fps, + .width = 376, + .height = 656, + .bin_factor_x = 2, + .bin_factor_y = 2, + .mipi_freq = 499000, + .used = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 0x0E70, + .lines_per_frame = 0x0C0A, + }, + { + } + }, + }, +}; + +#endif /* __IMX227_H__ */ diff --git a/drivers/staging/media/atomisp/i2c/imx/otp.c b/drivers/staging/media/atomisp/i2c/imx/otp.c new file mode 100644 index 0000000000000000000000000000000000000000..4622750380468c53984dd4bdfdb79d9ee35e6320 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/otp.c @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +void *dummy_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u8 *buf; + + buf = devm_kzalloc(&client->dev, size, GFP_KERNEL); + if (!buf) + return ERR_PTR(-ENOMEM); + + return buf; +} diff --git a/drivers/staging/media/atomisp/i2c/imx/otp_brcc064_e2prom.c b/drivers/staging/media/atomisp/i2c/imx/otp_brcc064_e2prom.c new file mode 100644 index 0000000000000000000000000000000000000000..242e934a60308363a0820a61d67b585ea6a39d36 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/otp_brcc064_e2prom.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +/* + * Read EEPROM data from brcc064 and store + * it into a kmalloced buffer. On error return NULL. + * @size: set to the size of the returned EEPROM data. + */ +void *brcc064_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + unsigned int e2prom_i2c_addr = dev_addr >> 1; + static const unsigned int max_read_size = 30; + int addr; + u32 s_addr = start_addr & E2PROM_ADDR_MASK; + unsigned char *buffer; + + buffer = devm_kzalloc(&client->dev, size, GFP_KERNEL); + if (!buffer) + return NULL; + + for (addr = s_addr; addr < size; addr += max_read_size) { + struct i2c_msg msg[2]; + unsigned int i2c_addr = e2prom_i2c_addr; + u16 addr_buf; + int r; + + msg[0].flags = 0; + msg[0].addr = i2c_addr; + addr_buf = cpu_to_be16(addr & 0xFFFF); + msg[0].len = 2; + msg[0].buf = (u8 *)&addr_buf; + + msg[1].addr = i2c_addr; + msg[1].flags = I2C_M_RD; + msg[1].len = min(max_read_size, size - addr); + msg[1].buf = &buffer[addr]; + + r = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg)); + if (r != ARRAY_SIZE(msg)) { + kfree(buffer); + dev_err(&client->dev, "read failed at 0x%03x\n", addr); + return NULL; + } + } + return buffer; + +} + + diff --git a/drivers/staging/media/atomisp/i2c/imx/otp_e2prom.c b/drivers/staging/media/atomisp/i2c/imx/otp_e2prom.c new file mode 100644 index 0000000000000000000000000000000000000000..ce4e7ab7781c6a9b26d5c5d3998155f85611d2e7 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/otp_e2prom.c @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +/* + * Read EEPROM data from the gerneral e2prom chip(eg. + * CAT24C08, CAT24C128, le24l042cs, and store + * it into a kmalloced buffer. On error return NULL. + * @size: set to the size of the returned EEPROM data. + */ +void *e2prom_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + unsigned int e2prom_i2c_addr = dev_addr >> 1; + static const unsigned int max_read_size = 30; + int addr; + u32 s_addr = start_addr & E2PROM_ADDR_MASK; + bool two_addr = (start_addr & E2PROM_2ADDR) >> 31; + char *buffer; + + buffer = devm_kzalloc(&client->dev, size, GFP_KERNEL); + if (!buffer) + return NULL; + + for (addr = s_addr; addr < size; addr += max_read_size) { + struct i2c_msg msg[2]; + unsigned int i2c_addr = e2prom_i2c_addr; + u16 addr_buf; + int r; + + msg[0].flags = 0; + if (two_addr) { + msg[0].addr = i2c_addr; + addr_buf = cpu_to_be16(addr & 0xFFFF); + msg[0].len = 2; + msg[0].buf = (u8 *)&addr_buf; + } else { + i2c_addr |= (addr >> 8) & 0x7; + msg[0].addr = i2c_addr; + addr_buf = addr & 0xFF; + msg[0].len = 1; + msg[0].buf = (u8 *)&addr_buf; + } + + msg[1].addr = i2c_addr; + msg[1].flags = I2C_M_RD; + msg[1].len = min(max_read_size, size - addr); + msg[1].buf = &buffer[addr]; + + r = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg)); + if (r != ARRAY_SIZE(msg)) { + kfree(buffer); + dev_err(&client->dev, "read failed at 0x%03x\n", addr); + return NULL; + } + } + return buffer; +} + + diff --git a/drivers/staging/media/atomisp/i2c/imx/otp_imx.c b/drivers/staging/media/atomisp/i2c/imx/otp_imx.c new file mode 100644 index 0000000000000000000000000000000000000000..1ca27c26ef754fc8d040cf3d91341ba99885518c --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/otp_imx.c @@ -0,0 +1,191 @@ +/* + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "common.h" + +/* Defines for OTP Data Registers */ +#define IMX_OTP_START_ADDR 0x3B04 +#define IMX_OTP_PAGE_SIZE 64 +#define IMX_OTP_READY_REG 0x3B01 +#define IMX_OTP_PAGE_REG 0x3B02 +#define IMX_OTP_MODE_REG 0x3B00 +#define IMX_OTP_PAGE_MAX 20 +#define IMX_OTP_READY_REG_DONE 1 +#define IMX_OTP_READ_ONETIME 32 +#define IMX_OTP_MODE_READ 1 +#define IMX227_OTP_START_ADDR 0x0A04 +#define IMX227_OTP_ENABLE_REG 0x0A00 +#define IMX227_OTP_READY_REG 0x0A01 +#define IMX227_OTP_PAGE_REG 0x0A02 +#define IMX227_OTP_READY_REG_DONE 1 +#define IMX227_OTP_MODE_READ 1 + +static int +imx_read_otp_data(struct i2c_client *client, u16 len, u16 reg, void *val) +{ + struct i2c_msg msg[2]; + u16 data[IMX_SHORT_MAX] = { 0 }; + int err; + + if (len > IMX_BYTE_MAX) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + memset(msg, 0 , sizeof(msg)); + memset(data, 0 , sizeof(data)); + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = I2C_MSG_LENGTH; + msg[0].buf = (u8 *)data; + /* high byte goes first */ + data[0] = cpu_to_be16(reg); + + msg[1].addr = client->addr; + msg[1].len = len; + msg[1].flags = I2C_M_RD; + msg[1].buf = (u8 *)data; + + err = i2c_transfer(client->adapter, msg, 2); + if (err != 2) { + if (err >= 0) + err = -EIO; + goto error; + } + + memcpy(val, data, len); + return 0; + +error: + dev_err(&client->dev, "read from offset 0x%x error %d", reg, err); + return err; +} + +static int imx_read_otp_reg_array(struct i2c_client *client, u16 size, u16 addr, + u8 *buf) +{ + u16 index; + int ret; + + for (index = 0; index + IMX_OTP_READ_ONETIME <= size; + index += IMX_OTP_READ_ONETIME) { + ret = imx_read_otp_data(client, IMX_OTP_READ_ONETIME, + addr + index, &buf[index]); + if (ret) + return ret; + } + return 0; +} + +void *imx_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u8 *buf; + int ret; + int i; + + buf = devm_kzalloc(&client->dev, size, GFP_KERNEL); + if (!buf) + return ERR_PTR(-ENOMEM); + + for (i = 0; i < IMX_OTP_PAGE_MAX; i++) { + + /*set page NO.*/ + ret = imx_write_reg(client, IMX_8BIT, + IMX_OTP_PAGE_REG, i & 0xff); + if (ret) + goto fail; + + /*set read mode*/ + ret = imx_write_reg(client, IMX_8BIT, + IMX_OTP_MODE_REG, IMX_OTP_MODE_READ); + if (ret) + goto fail; + + /* Reading the OTP data array */ + ret = imx_read_otp_reg_array(client, IMX_OTP_PAGE_SIZE, + IMX_OTP_START_ADDR, buf + i * IMX_OTP_PAGE_SIZE); + if (ret) + goto fail; + } + + return buf; +fail: + /* Driver has failed to find valid data */ + dev_err(&client->dev, "sensor found no valid OTP data\n"); + return ERR_PTR(ret); +} + +void *imx227_otp_read(struct v4l2_subdev *sd, u8 dev_addr, + u32 start_addr, u32 size) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u8 *buf; + int ret; + int i; + + buf = devm_kzalloc(&client->dev, size, GFP_KERNEL); + if (!buf) + return ERR_PTR(-ENOMEM); + + for (i = 0; i < IMX_OTP_PAGE_MAX; i++) { + + /*set page NO.*/ + ret = imx_write_reg(client, IMX_8BIT, + IMX227_OTP_PAGE_REG, i & 0xff); + if (ret) + goto fail; + + /*set read mode*/ + ret = imx_write_reg(client, IMX_8BIT, + IMX227_OTP_ENABLE_REG, IMX227_OTP_MODE_READ); + if (ret) + goto fail; + + /* Reading the OTP data array */ + ret = imx_read_otp_reg_array(client, IMX_OTP_PAGE_SIZE, + IMX227_OTP_START_ADDR, buf + i * IMX_OTP_PAGE_SIZE); + if (ret) + goto fail; + } + + return buf; +fail: + /* Driver has failed to find valid data */ + dev_err(&client->dev, "sensor found no valid OTP data\n"); + return ERR_PTR(ret); +} + diff --git a/drivers/staging/media/atomisp/i2c/imx/vcm.c b/drivers/staging/media/atomisp/i2c/imx/vcm.c new file mode 100644 index 0000000000000000000000000000000000000000..983651352e88d4fb32176879dd6efcfb30531a4e --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/imx/vcm.c @@ -0,0 +1,45 @@ +/* + * Copyright (c) 2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include +#include +#include +#include +#include + +int vcm_power_up(struct v4l2_subdev *sd) +{ + const struct camera_af_platform_data *vcm_platform_data; + + vcm_platform_data = camera_get_af_platform_data(); + if (NULL == vcm_platform_data) + return -ENODEV; + /* Enable power */ + return vcm_platform_data->power_ctrl(sd, 1); +} + +int vcm_power_down(struct v4l2_subdev *sd) +{ + const struct camera_af_platform_data *vcm_platform_data; + + vcm_platform_data = camera_get_af_platform_data(); + if (NULL == vcm_platform_data) + return -ENODEV; + return vcm_platform_data->power_ctrl(sd, 0); +} + diff --git a/drivers/staging/media/atomisp/i2c/libmsrlisthelper.c b/drivers/staging/media/atomisp/i2c/libmsrlisthelper.c new file mode 100644 index 0000000000000000000000000000000000000000..e04cefd702f8440f8ea31ae4cedf66cd75230e98 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/libmsrlisthelper.c @@ -0,0 +1,209 @@ +/* + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include + +/* Tagged binary data container structure definitions. */ +struct tbd_header { + uint32_t tag; /*!< Tag identifier, also checks endianness */ + uint32_t size; /*!< Container size including this header */ + uint32_t version; /*!< Version, format 0xYYMMDDVV */ + uint32_t revision; /*!< Revision, format 0xYYMMDDVV */ + uint32_t config_bits; /*!< Configuration flag bits set */ + uint32_t checksum; /*!< Global checksum, header included */ +} __packed; + +struct tbd_record_header { + uint32_t size; /*!< Size of record including header */ + uint8_t format_id; /*!< tbd_format_t enumeration values used */ + uint8_t packing_key; /*!< Packing method; 0 = no packing */ + uint16_t class_id; /*!< tbd_class_t enumeration values used */ +} __packed; + +struct tbd_data_record_header { + uint16_t next_offset; + uint16_t flags; + uint16_t data_offset; + uint16_t data_size; +} __packed; + +#define TBD_CLASS_DRV_ID 2 + +static int set_msr_configuration(struct i2c_client *client, uint8_t *bufptr, + unsigned int size) +{ + /* The configuration data contains any number of sequences where + * the first byte (that is, uint8_t) that marks the number of bytes + * in the sequence to follow, is indeed followed by the indicated + * number of bytes of actual data to be written to sensor. + * By convention, the first two bytes of actual data should be + * understood as an address in the sensor address space (hibyte + * followed by lobyte) where the remaining data in the sequence + * will be written. */ + + uint8_t *ptr = bufptr; + while (ptr < bufptr + size) { + struct i2c_msg msg = { + .addr = client->addr, + .flags = 0, + }; + int ret; + + /* How many bytes */ + msg.len = *ptr++; + /* Where the bytes are located */ + msg.buf = ptr; + ptr += msg.len; + + if (ptr > bufptr + size) + /* Accessing data beyond bounds is not tolerated */ + return -EINVAL; + + ret = i2c_transfer(client->adapter, &msg, 1); + if (ret < 0) { + dev_err(&client->dev, "i2c write error: %d", ret); + return ret; + } + } + return 0; +} + +static int parse_and_apply(struct i2c_client *client, uint8_t *buffer, + unsigned int size) +{ + uint8_t *endptr8 = buffer + size; + struct tbd_data_record_header *header = + (struct tbd_data_record_header *)buffer; + + /* There may be any number of datasets present */ + unsigned int dataset = 0; + + do { + /* In below, four variables are read from buffer */ + if ((uint8_t *)header + sizeof(*header) > endptr8) + return -EINVAL; + + /* All data should be located within given buffer */ + if ((uint8_t *)header + header->data_offset + + header->data_size > endptr8) + return -EINVAL; + + /* We have a new valid dataset */ + dataset++; + /* See whether there is MSR data */ + /* If yes, update the reg info */ + if (header->data_size && (header->flags & 1)) { + int ret; + + dev_info(&client->dev, + "New MSR data for sensor driver (dataset %02d) size:%d\n", + dataset, header->data_size); + ret = set_msr_configuration(client, + buffer + header->data_offset, + header->data_size); + if (ret) + return ret; + } + header = (struct tbd_data_record_header *)(buffer + + header->next_offset); + } while (header->next_offset); + + return 0; +} + +int apply_msr_data(struct i2c_client *client, const struct firmware *fw) +{ + struct tbd_header *header; + struct tbd_record_header *record; + + if (!fw) { + dev_warn(&client->dev, "Drv data is not loaded.\n"); + return -EINVAL; + } + + if (sizeof(*header) > fw->size) + return -EINVAL; + + header = (struct tbd_header *)fw->data; + /* Check that we have drvb block. */ + if (memcmp(&header->tag, "DRVB", 4)) + return -EINVAL; + + /* Check the size */ + if (header->size != fw->size) + return -EINVAL; + + if (sizeof(*header) + sizeof(*record) > fw->size) + return -EINVAL; + + record = (struct tbd_record_header *)(header + 1); + /* Check that class id mathes tbd's drv id. */ + if (record->class_id != TBD_CLASS_DRV_ID) + return -EINVAL; + + /* Size 0 shall not be treated as an error */ + if (!record->size) + return 0; + + return parse_and_apply(client, (uint8_t *)(record + 1), record->size); +} +EXPORT_SYMBOL_GPL(apply_msr_data); + +int load_msr_list(struct i2c_client *client, char *name, + const struct firmware **fw) +{ + int ret = request_firmware(fw, name, &client->dev); + if (ret) { + dev_err(&client->dev, + "Error %d while requesting firmware %s\n", + ret, name); + return ret; + } + dev_info(&client->dev, "Received %lu bytes drv data\n", + (unsigned long)(*fw)->size); + + return 0; +} +EXPORT_SYMBOL_GPL(load_msr_list); + +void release_msr_list(struct i2c_client *client, const struct firmware *fw) +{ + release_firmware(fw); +} +EXPORT_SYMBOL_GPL(release_msr_list); + +static int init_msrlisthelper(void) +{ + return 0; +} + +static void exit_msrlisthelper(void) +{ +} + +module_init(init_msrlisthelper); +module_exit(exit_msrlisthelper); + +MODULE_AUTHOR("Jukka Kaartinen "); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/lm3554.c b/drivers/staging/media/atomisp/i2c/lm3554.c new file mode 100644 index 0000000000000000000000000000000000000000..928af05e8f175a6bfad7c9ad325a3680045a7ac0 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/lm3554.c @@ -0,0 +1,1010 @@ +/* + * LED flash driver for LM3554 + * + * Copyright (c) 2010-2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +/* Registers */ + +#define LM3554_TORCH_BRIGHTNESS_REG 0xA0 +#define LM3554_TORCH_MODE_SHIFT 0 +#define LM3554_TORCH_CURRENT_SHIFT 3 +#define LM3554_INDICATOR_CURRENT_SHIFT 6 + +#define LM3554_FLASH_BRIGHTNESS_REG 0xB0 +#define LM3554_FLASH_MODE_SHIFT 0 +#define LM3554_FLASH_CURRENT_SHIFT 3 +#define LM3554_STROBE_SENSITIVITY_SHIFT 7 + +#define LM3554_FLASH_DURATION_REG 0xC0 +#define LM3554_FLASH_TIMEOUT_SHIFT 0 +#define LM3554_CURRENT_LIMIT_SHIFT 5 + +#define LM3554_FLAGS_REG 0xD0 +#define LM3554_FLAG_TIMEOUT (1 << 0) +#define LM3554_FLAG_THERMAL_SHUTDOWN (1 << 1) +#define LM3554_FLAG_LED_FAULT (1 << 2) +#define LM3554_FLAG_TX1_INTERRUPT (1 << 3) +#define LM3554_FLAG_TX2_INTERRUPT (1 << 4) +#define LM3554_FLAG_LED_THERMAL_FAULT (1 << 5) +#define LM3554_FLAG_UNUSED (1 << 6) +#define LM3554_FLAG_INPUT_VOLTAGE_LOW (1 << 7) + +#define LM3554_CONFIG_REG_1 0xE0 +#define LM3554_ENVM_TX2_SHIFT 5 +#define LM3554_TX2_POLARITY_SHIFT 6 + +struct lm3554 { + struct v4l2_subdev sd; + + struct mutex power_lock; + struct v4l2_ctrl_handler ctrl_handler; + int power_count; + + unsigned int mode; + int timeout; + u8 torch_current; + u8 indicator_current; + u8 flash_current; + + struct timer_list flash_off_delay; + struct lm3554_platform_data *pdata; +}; + +#define to_lm3554(p_sd) container_of(p_sd, struct lm3554, sd) + +/* Return negative errno else zero on success */ +static int lm3554_write(struct lm3554 *flash, u8 addr, u8 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(&flash->sd); + int ret; + + ret = i2c_smbus_write_byte_data(client, addr, val); + + dev_dbg(&client->dev, "Write Addr:%02X Val:%02X %s\n", addr, val, + ret < 0 ? "fail" : "ok"); + + return ret; +} + +/* Return negative errno else a data byte received from the device. */ +static int lm3554_read(struct lm3554 *flash, u8 addr) +{ + struct i2c_client *client = v4l2_get_subdevdata(&flash->sd); + int ret; + + ret = i2c_smbus_read_byte_data(client, addr); + + dev_dbg(&client->dev, "Read Addr:%02X Val:%02X %s\n", addr, ret, + ret < 0 ? "fail" : "ok"); + + return ret; +} + +/* ----------------------------------------------------------------------------- + * Hardware configuration + */ + +static int lm3554_set_mode(struct lm3554 *flash, unsigned int mode) +{ + u8 val; + int ret; + + val = (mode << LM3554_FLASH_MODE_SHIFT) | + (flash->flash_current << LM3554_FLASH_CURRENT_SHIFT); + + ret = lm3554_write(flash, LM3554_FLASH_BRIGHTNESS_REG, val); + if (ret == 0) + flash->mode = mode; + return ret; +} + +static int lm3554_set_torch(struct lm3554 *flash) +{ + u8 val; + + val = (flash->mode << LM3554_TORCH_MODE_SHIFT) | + (flash->torch_current << LM3554_TORCH_CURRENT_SHIFT) | + (flash->indicator_current << LM3554_INDICATOR_CURRENT_SHIFT); + + return lm3554_write(flash, LM3554_TORCH_BRIGHTNESS_REG, val); +} + +static int lm3554_set_flash(struct lm3554 *flash) +{ + u8 val; + + val = (flash->mode << LM3554_FLASH_MODE_SHIFT) | + (flash->flash_current << LM3554_FLASH_CURRENT_SHIFT); + + return lm3554_write(flash, LM3554_FLASH_BRIGHTNESS_REG, val); +} + +static int lm3554_set_duration(struct lm3554 *flash) +{ + u8 val; + + val = (flash->timeout << LM3554_FLASH_TIMEOUT_SHIFT) | + (flash->pdata->current_limit << LM3554_CURRENT_LIMIT_SHIFT); + + return lm3554_write(flash, LM3554_FLASH_DURATION_REG, val); +} + +static int lm3554_set_config1(struct lm3554 *flash) +{ + u8 val; + + val = (flash->pdata->envm_tx2 << LM3554_ENVM_TX2_SHIFT) | + (flash->pdata->tx2_polarity << LM3554_TX2_POLARITY_SHIFT); + return lm3554_write(flash, LM3554_CONFIG_REG_1, val); +} + +/* ----------------------------------------------------------------------------- + * Hardware trigger + */ +static void lm3554_flash_off_delay(long unsigned int arg) +{ + struct v4l2_subdev *sd = i2c_get_clientdata((struct i2c_client *)arg); + struct lm3554 *flash = to_lm3554(sd); + struct lm3554_platform_data *pdata = flash->pdata; + + gpio_set_value(pdata->gpio_strobe, 0); +} + +static int lm3554_hw_strobe(struct i2c_client *client, bool strobe) +{ + int ret, timer_pending; + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct lm3554 *flash = to_lm3554(sd); + struct lm3554_platform_data *pdata = flash->pdata; + + /* + * An abnormal high flash current is observed when strobe off the + * flash. Workaround here is firstly set flash current to lower level, + * wait a short moment, and then strobe off the flash. + */ + + timer_pending = del_timer_sync(&flash->flash_off_delay); + + /* Flash off */ + if (!strobe) { + /* set current to 70mA and wait a while */ + ret = lm3554_write(flash, LM3554_FLASH_BRIGHTNESS_REG, 0); + if (ret < 0) + goto err; + mod_timer(&flash->flash_off_delay, + jiffies + msecs_to_jiffies(LM3554_TIMER_DELAY)); + return 0; + } + + /* Flash on */ + + /* + * If timer is killed before run, flash is not strobe off, + * so must strobe off here + */ + if (timer_pending) + gpio_set_value(pdata->gpio_strobe, 0); + + /* Restore flash current settings */ + ret = lm3554_set_flash(flash); + if (ret < 0) + goto err; + + /* Strobe on Flash */ + gpio_set_value(pdata->gpio_strobe, 1); + + return 0; +err: + dev_err(&client->dev, "failed to %s flash strobe (%d)\n", + strobe ? "on" : "off", ret); + return ret; +} + +/* ----------------------------------------------------------------------------- + * V4L2 controls + */ + +static int lm3554_read_status(struct lm3554 *flash) +{ + int ret; + struct i2c_client *client = v4l2_get_subdevdata(&flash->sd); + + /* NOTE: reading register clear fault status */ + ret = lm3554_read(flash, LM3554_FLAGS_REG); + if (ret < 0) + return ret; + + /* + * Accordingly to datasheet we read back '1' in bit 6. + * Clear it first. + */ + ret &= ~LM3554_FLAG_UNUSED; + + /* + * Do not take TX1/TX2 signal as an error + * because MSIC will not turn off flash, but turn to + * torch mode according to gsm modem signal by hardware. + */ + ret &= ~(LM3554_FLAG_TX1_INTERRUPT | LM3554_FLAG_TX2_INTERRUPT); + + if (ret > 0) + dev_dbg(&client->dev, "LM3554 flag status: %02x\n", ret); + + return ret; +} + +static int lm3554_s_flash_timeout(struct v4l2_subdev *sd, u32 val) +{ + struct lm3554 *flash = to_lm3554(sd); + + val = clamp(val, LM3554_MIN_TIMEOUT, LM3554_MAX_TIMEOUT); + val = val / LM3554_TIMEOUT_STEPSIZE - 1; + + flash->timeout = val; + + return lm3554_set_duration(flash); +} + +static int lm3554_g_flash_timeout(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + + *val = (u32)(flash->timeout + 1) * LM3554_TIMEOUT_STEPSIZE; + + return 0; +} + +static int lm3554_s_flash_intensity(struct v4l2_subdev *sd, u32 intensity) +{ + struct lm3554 *flash = to_lm3554(sd); + + intensity = LM3554_CLAMP_PERCENTAGE(intensity); + intensity = LM3554_PERCENT_TO_VALUE(intensity, LM3554_FLASH_STEP); + + flash->flash_current = intensity; + + return lm3554_set_flash(flash); +} + +static int lm3554_g_flash_intensity(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + + *val = LM3554_VALUE_TO_PERCENT((u32)flash->flash_current, + LM3554_FLASH_STEP); + + return 0; +} + +static int lm3554_s_torch_intensity(struct v4l2_subdev *sd, u32 intensity) +{ + struct lm3554 *flash = to_lm3554(sd); + + intensity = LM3554_CLAMP_PERCENTAGE(intensity); + intensity = LM3554_PERCENT_TO_VALUE(intensity, LM3554_TORCH_STEP); + + flash->torch_current = intensity; + + return lm3554_set_torch(flash); +} + +static int lm3554_g_torch_intensity(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + + *val = LM3554_VALUE_TO_PERCENT((u32)flash->torch_current, + LM3554_TORCH_STEP); + + return 0; +} + +static int lm3554_s_indicator_intensity(struct v4l2_subdev *sd, u32 intensity) +{ + struct lm3554 *flash = to_lm3554(sd); + + intensity = LM3554_CLAMP_PERCENTAGE(intensity); + intensity = LM3554_PERCENT_TO_VALUE(intensity, LM3554_INDICATOR_STEP); + + flash->indicator_current = intensity; + + return lm3554_set_torch(flash); +} + +static int lm3554_g_indicator_intensity(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + + *val = LM3554_VALUE_TO_PERCENT((u32)flash->indicator_current, + LM3554_INDICATOR_STEP); + + return 0; +} + +static int lm3554_s_flash_strobe(struct v4l2_subdev *sd, u32 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + + return lm3554_hw_strobe(client, val); +} + +static int lm3554_s_flash_mode(struct v4l2_subdev *sd, u32 new_mode) +{ + struct lm3554 *flash = to_lm3554(sd); + unsigned int mode; + + switch (new_mode) { + case ATOMISP_FLASH_MODE_OFF: + mode = LM3554_MODE_SHUTDOWN; + break; + case ATOMISP_FLASH_MODE_FLASH: + mode = LM3554_MODE_FLASH; + break; + case ATOMISP_FLASH_MODE_INDICATOR: + mode = LM3554_MODE_INDICATOR; + break; + case ATOMISP_FLASH_MODE_TORCH: + mode = LM3554_MODE_TORCH; + break; + default: + return -EINVAL; + } + + return lm3554_set_mode(flash, mode); +} + +static int lm3554_g_flash_mode(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + *val = flash->mode; + return 0; +} + +static int lm3554_g_flash_status(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + int value; + + value = lm3554_read_status(flash); + if (value < 0) + return value; + + if (value & LM3554_FLAG_TIMEOUT) + *val = ATOMISP_FLASH_STATUS_TIMEOUT; + else if (value > 0) + *val = ATOMISP_FLASH_STATUS_HW_ERROR; + else + *val = ATOMISP_FLASH_STATUS_OK; + + return 0; +} + +#ifndef CSS15 +static int lm3554_g_flash_status_register(struct v4l2_subdev *sd, s32 *val) +{ + struct lm3554 *flash = to_lm3554(sd); + int ret; + + ret = lm3554_read(flash, LM3554_FLAGS_REG); + + if (ret < 0) + return ret; + + *val = ret; + return 0; +} +#endif + +static int lm3554_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct lm3554 *dev = + container_of(ctrl->handler, struct lm3554, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_FLASH_TIMEOUT: + ret = lm3554_s_flash_timeout(&dev->sd, ctrl->val); + break; + case V4L2_CID_FLASH_INTENSITY: + ret = lm3554_s_flash_intensity(&dev->sd, ctrl->val); + break; + case V4L2_CID_FLASH_TORCH_INTENSITY: + ret = lm3554_s_torch_intensity(&dev->sd, ctrl->val); + break; + case V4L2_CID_FLASH_INDICATOR_INTENSITY: + ret = lm3554_s_indicator_intensity(&dev->sd, ctrl->val); + break; + case V4L2_CID_FLASH_STROBE: + ret = lm3554_s_flash_strobe(&dev->sd, ctrl->val); + break; + case V4L2_CID_FLASH_MODE: + ret = lm3554_s_flash_mode(&dev->sd, ctrl->val); + break; + default: + ret = -EINVAL; + } + return ret; +} + +static int lm3554_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct lm3554 *dev = + container_of(ctrl->handler, struct lm3554, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_FLASH_TIMEOUT: + ret = lm3554_g_flash_timeout(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FLASH_INTENSITY: + ret = lm3554_g_flash_intensity(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FLASH_TORCH_INTENSITY: + ret = lm3554_g_torch_intensity(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FLASH_INDICATOR_INTENSITY: + ret = lm3554_g_indicator_intensity(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FLASH_MODE: + ret = lm3554_g_flash_mode(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FLASH_STATUS: + ret = lm3554_g_flash_status(&dev->sd, &ctrl->val); + break; +#ifndef CSS15 + case V4L2_CID_FLASH_STATUS_REGISTER: + ret = lm3554_g_flash_status_register(&dev->sd, &ctrl->val); + break; +#endif + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = lm3554_s_ctrl, + .g_volatile_ctrl = lm3554_g_volatile_ctrl +}; + +struct v4l2_ctrl_config lm3554_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_TIMEOUT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Flash Timeout", + .min = 0x0, + .max = LM3554_MAX_TIMEOUT, + .step = 0x01, + .def = LM3554_DEFAULT_TIMEOUT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_INTENSITY, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Flash Intensity", + .min = LM3554_MIN_PERCENT, + .max = LM3554_MAX_PERCENT, + .step = 0x01, + .def = LM3554_FLASH_DEFAULT_BRIGHTNESS, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_TORCH_INTENSITY, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Torch Intensity", + .min = LM3554_MIN_PERCENT, + .max = LM3554_MAX_PERCENT, + .step = 0x01, + .def = LM3554_TORCH_DEFAULT_BRIGHTNESS, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_INDICATOR_INTENSITY, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Indicator Intensity", + .min = LM3554_MIN_PERCENT, + .max = LM3554_MAX_PERCENT, + .step = 0x01, + .def = LM3554_INDICATOR_DEFAULT_BRIGHTNESS, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_STROBE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Flash Strobe", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_MODE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Flash Mode", + .min = 0, + .max = 100, + .step = 1, + .def = ATOMISP_FLASH_MODE_OFF, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_STATUS, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Flash Status", + .min = 0, + .max = 100, + .step = 1, + .def = ATOMISP_FLASH_STATUS_OK, + .flags = 0, + }, +#ifndef CSS15 + { + .ops = &ctrl_ops, + .id = V4L2_CID_FLASH_STATUS_REGISTER, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Flash Status Register", + .min = 0, + .max = 100, + .step = 1, + .def = 0, + .flags = 0, + }, +#endif +}; + +/* ----------------------------------------------------------------------------- + * V4L2 subdev core operations + */ + +/* Put device into known state. */ +static int lm3554_setup(struct lm3554 *flash) +{ + struct i2c_client *client = v4l2_get_subdevdata(&flash->sd); + int ret; + + /* clear the flags register */ + ret = lm3554_read(flash, LM3554_FLAGS_REG); + if (ret < 0) + return ret; + + dev_dbg(&client->dev, "Fault info: %02x\n", ret); + + ret = lm3554_set_config1(flash); + if (ret < 0) + return ret; + + ret = lm3554_set_duration(flash); + if (ret < 0) + return ret; + + ret = lm3554_set_torch(flash); + if (ret < 0) + return ret; + + ret = lm3554_set_flash(flash); + if (ret < 0) + return ret; + + /* read status */ + ret = lm3554_read_status(flash); + if (ret < 0) + return ret; + + return ret ? -EIO : 0; +} + +static int __lm3554_s_power(struct lm3554 *flash, int power) +{ + struct lm3554_platform_data *pdata = flash->pdata; + int ret; + + /*initialize flash driver*/ + gpio_set_value(pdata->gpio_reset, power); + usleep_range(100, 100 + 1); + + if (power) { + /* Setup default values. This makes sure that the chip + * is in a known state. + */ + ret = lm3554_setup(flash); + if (ret < 0) { + __lm3554_s_power(flash, 0); + return ret; + } + } + + return 0; +} + +static int lm3554_s_power(struct v4l2_subdev *sd, int power) +{ + struct lm3554 *flash = to_lm3554(sd); + int ret = 0; + + mutex_lock(&flash->power_lock); + + if (flash->power_count == !power) { + ret = __lm3554_s_power(flash, !!power); + if (ret < 0) + goto done; + } + + flash->power_count += power ? 1 : -1; + WARN_ON(flash->power_count < 0); + +done: + mutex_unlock(&flash->power_lock); + return ret; +} + +static const struct v4l2_subdev_core_ops lm3554_core_ops = { + .s_power = lm3554_s_power, +}; + +static const struct v4l2_subdev_ops lm3554_ops = { + .core = &lm3554_core_ops, +}; + +static int lm3554_detect(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct i2c_adapter *adapter = client->adapter; + struct lm3554 *flash = to_lm3554(sd); + int ret; + + if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { + dev_err(&client->dev, "lm3554_detect i2c error\n"); + return -ENODEV; + } + + /* Power up the flash driver and reset it */ + ret = lm3554_s_power(&flash->sd, 1); + if (ret < 0) { + dev_err(&client->dev, "Failed to power on lm3554 LED flash\n"); + } else { + dev_dbg(&client->dev, "Successfully detected lm3554 LED flash\n"); + lm3554_s_power(&flash->sd, 0); + } + + return ret; +} + +static int lm3554_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + return lm3554_s_power(sd, 1); +} + +static int lm3554_close(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) +{ + return lm3554_s_power(sd, 0); +} + +static const struct v4l2_subdev_internal_ops lm3554_internal_ops = { + .registered = lm3554_detect, + .open = lm3554_open, + .close = lm3554_close, +}; + +/* ----------------------------------------------------------------------------- + * I2C driver + */ +#ifdef CONFIG_PM + +static int lm3554_suspend(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *subdev = i2c_get_clientdata(client); + struct lm3554 *flash = to_lm3554(subdev); + int rval; + + if (flash->power_count == 0) + return 0; + + rval = __lm3554_s_power(flash, 0); + + dev_dbg(&client->dev, "Suspend %s\n", rval < 0 ? "failed" : "ok"); + + return rval; +} + +static int lm3554_resume(struct device *dev) +{ + struct i2c_client *client = to_i2c_client(dev); + struct v4l2_subdev *subdev = i2c_get_clientdata(client); + struct lm3554 *flash = to_lm3554(subdev); + int rval; + + if (flash->power_count == 0) + return 0; + + rval = __lm3554_s_power(flash, 1); + + dev_dbg(&client->dev, "Resume %s\n", rval < 0 ? "fail" : "ok"); + + return rval; +} + +#else + +#define lm3554_suspend NULL +#define lm3554_resume NULL + +#endif /* CONFIG_PM */ + +static int lm3554_gpio_init(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct lm3554 *flash = to_lm3554(sd); + struct lm3554_platform_data *pdata = flash->pdata; + int ret; + + if (!gpio_is_valid(pdata->gpio_reset)) + return -EINVAL; + + ret = gpio_direction_output(pdata->gpio_reset, 0); + if (ret < 0) + goto err_gpio_reset; + dev_info(&client->dev, "flash led reset successfully\n"); + + if (!gpio_is_valid(pdata->gpio_strobe)) { + ret = -EINVAL; + goto err_gpio_dir_reset; + } + + ret = gpio_direction_output(pdata->gpio_strobe, 0); + if (ret < 0) + goto err_gpio_strobe; + + return 0; + +err_gpio_strobe: + gpio_free(pdata->gpio_strobe); +err_gpio_dir_reset: + gpio_direction_output(pdata->gpio_reset, 0); +err_gpio_reset: + gpio_free(pdata->gpio_reset); + + return ret; +} + +static int lm3554_gpio_uninit(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct lm3554 *flash = to_lm3554(sd); + struct lm3554_platform_data *pdata = flash->pdata; + int ret; + + ret = gpio_direction_output(pdata->gpio_strobe, 0); + if (ret < 0) + return ret; + + ret = gpio_direction_output(pdata->gpio_reset, 0); + if (ret < 0) + return ret; + + gpio_free(pdata->gpio_strobe); + gpio_free(pdata->gpio_reset); + return 0; +} + +void *lm3554_platform_data_func(struct i2c_client *client) +{ + static struct lm3554_platform_data platform_data; + + if (ACPI_COMPANION(&client->dev)) { + platform_data.gpio_reset = + desc_to_gpio(gpiod_get_index(&(client->dev), + NULL, 2, GPIOD_OUT_LOW)); + platform_data.gpio_strobe = + desc_to_gpio(gpiod_get_index(&(client->dev), + NULL, 0, GPIOD_OUT_LOW)); + platform_data.gpio_torch = + desc_to_gpio(gpiod_get_index(&(client->dev), + NULL, 1, GPIOD_OUT_LOW)); + } else { + platform_data.gpio_reset = -1; + platform_data.gpio_strobe = -1; + platform_data.gpio_torch = -1; + } + + dev_info(&client->dev, "camera pdata: lm3554: reset: %d strobe %d torch %d\n", + platform_data.gpio_reset, platform_data.gpio_strobe, + platform_data.gpio_torch); + + /* Set to TX2 mode, then ENVM/TX2 pin is a power amplifier sync input: + * ENVM/TX pin asserted, flash forced into torch; + * ENVM/TX pin desserted, flash set back; + */ + platform_data.envm_tx2 = 1; + platform_data.tx2_polarity = 0; + + /* set peak current limit to be 1000mA */ + platform_data.current_limit = 0; + + return &platform_data; +} + +static int lm3554_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + int err = 0; + struct lm3554 *flash; + unsigned int i; + int ret; + + flash = kzalloc(sizeof(*flash), GFP_KERNEL); + if (!flash) { + dev_err(&client->dev, "out of memory\n"); + return -ENOMEM; + } + + flash->pdata = client->dev.platform_data; + + if (!flash->pdata || ACPI_COMPANION(&client->dev)) + flash->pdata = lm3554_platform_data_func(client); + + v4l2_i2c_subdev_init(&flash->sd, client, &lm3554_ops); + flash->sd.internal_ops = &lm3554_internal_ops; + flash->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + flash->mode = ATOMISP_FLASH_MODE_OFF; + flash->timeout = LM3554_MAX_TIMEOUT / LM3554_TIMEOUT_STEPSIZE - 1; + ret = + v4l2_ctrl_handler_init(&flash->ctrl_handler, + ARRAY_SIZE(lm3554_controls)); + if (ret) { + dev_err(&client->dev, "error initialize a ctrl_handler.\n"); + goto fail2; + } + + for (i = 0; i < ARRAY_SIZE(lm3554_controls); i++) + v4l2_ctrl_new_custom(&flash->ctrl_handler, &lm3554_controls[i], + NULL); + + if (flash->ctrl_handler.error) { + + dev_err(&client->dev, "ctrl_handler error.\n"); + goto fail2; + } + + flash->sd.ctrl_handler = &flash->ctrl_handler; + err = media_entity_pads_init(&flash->sd.entity, 0, NULL); + if (err) { + dev_err(&client->dev, "error initialize a media entity.\n"); + goto fail1; + } + + flash->sd.entity.function = MEDIA_ENT_F_FLASH; + + mutex_init(&flash->power_lock); + + setup_timer(&flash->flash_off_delay, lm3554_flash_off_delay, + (unsigned long)client); + + err = lm3554_gpio_init(client); + if (err) { + dev_err(&client->dev, "gpio request/direction_output fail"); + goto fail2; + } + if (ACPI_HANDLE(&client->dev)) + err = atomisp_register_i2c_module(&flash->sd, NULL, LED_FLASH); + return 0; +fail2: + media_entity_cleanup(&flash->sd.entity); + v4l2_ctrl_handler_free(&flash->ctrl_handler); +fail1: + v4l2_device_unregister_subdev(&flash->sd); + kfree(flash); + + return err; +} + +static int lm3554_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct lm3554 *flash = to_lm3554(sd); + int ret; + + media_entity_cleanup(&flash->sd.entity); + v4l2_ctrl_handler_free(&flash->ctrl_handler); + v4l2_device_unregister_subdev(sd); + + atomisp_gmin_remove_subdev(sd); + + del_timer_sync(&flash->flash_off_delay); + + ret = lm3554_gpio_uninit(client); + if (ret < 0) + goto fail; + + kfree(flash); + + return 0; +fail: + dev_err(&client->dev, "gpio request/direction_output fail"); + return ret; +} + +static const struct i2c_device_id lm3554_id[] = { + {LM3554_NAME, 0}, + {}, +}; + +MODULE_DEVICE_TABLE(i2c, lm3554_id); + +static const struct dev_pm_ops lm3554_pm_ops = { + .suspend = lm3554_suspend, + .resume = lm3554_resume, +}; + +static struct acpi_device_id lm3554_acpi_match[] = { + { "INTCF1C" }, + {}, +}; + +MODULE_DEVICE_TABLE(acpi, lm3554_acpi_match); + +static struct i2c_driver lm3554_driver = { + .driver = { + .owner = THIS_MODULE, + .name = LM3554_NAME, + .pm = &lm3554_pm_ops, + .acpi_match_table = ACPI_PTR(lm3554_acpi_match), + }, + .probe = lm3554_probe, + .remove = lm3554_remove, + .id_table = lm3554_id, +}; + +static __init int init_lm3554(void) +{ + return i2c_add_driver(&lm3554_driver); +} + +static __exit void exit_lm3554(void) +{ + i2c_del_driver(&lm3554_driver); +} + +module_init(init_lm3554); +module_exit(exit_lm3554); +MODULE_AUTHOR("Jing Tao "); +MODULE_DESCRIPTION("LED flash driver for LM3554"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/mt9m114.c b/drivers/staging/media/atomisp/i2c/mt9m114.c new file mode 100644 index 0000000000000000000000000000000000000000..16630f201202ce5b5f7cd10dc1c58925eb2d671d --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/mt9m114.c @@ -0,0 +1,1969 @@ +/* + * Support for mt9m114 Camera Sensor. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "mt9m114.h" + +#define to_mt9m114_sensor(sd) container_of(sd, struct mt9m114_device, sd) + +/* + * TODO: use debug parameter to actually define when debug messages should + * be printed. + */ +static int debug; +static int aaalock; +module_param(debug, int, 0644); +MODULE_PARM_DESC(debug, "Debug level (0-1)"); + +static int mt9m114_t_vflip(struct v4l2_subdev *sd, int value); +static int mt9m114_t_hflip(struct v4l2_subdev *sd, int value); +static int mt9m114_wait_state(struct i2c_client *client, int timeout); + +static int +mt9m114_read_reg(struct i2c_client *client, u16 data_length, u32 reg, u32 *val) +{ + int err; + struct i2c_msg msg[2]; + unsigned char data[4]; + + if (!client->adapter) { + v4l2_err(client, "%s error, no client->adapter\n", __func__); + return -ENODEV; + } + + if (data_length != MISENSOR_8BIT && data_length != MISENSOR_16BIT + && data_length != MISENSOR_32BIT) { + v4l2_err(client, "%s error, invalid data length\n", __func__); + return -EINVAL; + } + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = MSG_LEN_OFFSET; + msg[0].buf = data; + + /* high byte goes out first */ + data[0] = (u16) (reg >> 8); + data[1] = (u16) (reg & 0xff); + + msg[1].addr = client->addr; + msg[1].len = data_length; + msg[1].flags = I2C_M_RD; + msg[1].buf = data; + + err = i2c_transfer(client->adapter, msg, 2); + + if (err >= 0) { + *val = 0; + /* high byte comes first */ + if (data_length == MISENSOR_8BIT) + *val = data[0]; + else if (data_length == MISENSOR_16BIT) + *val = data[1] + (data[0] << 8); + else + *val = data[3] + (data[2] << 8) + + (data[1] << 16) + (data[0] << 24); + + return 0; + } + + dev_err(&client->dev, "read from offset 0x%x error %d", reg, err); + return err; +} + +static int +mt9m114_write_reg(struct i2c_client *client, u16 data_length, u16 reg, u32 val) +{ + int num_msg; + struct i2c_msg msg; + unsigned char data[6] = {0}; + u16 *wreg; + int retry = 0; + + if (!client->adapter) { + v4l2_err(client, "%s error, no client->adapter\n", __func__); + return -ENODEV; + } + + if (data_length != MISENSOR_8BIT && data_length != MISENSOR_16BIT + && data_length != MISENSOR_32BIT) { + v4l2_err(client, "%s error, invalid data_length\n", __func__); + return -EINVAL; + } + + memset(&msg, 0, sizeof(msg)); + +again: + msg.addr = client->addr; + msg.flags = 0; + msg.len = 2 + data_length; + msg.buf = data; + + /* high byte goes out first */ + wreg = (u16 *)data; + *wreg = cpu_to_be16(reg); + + if (data_length == MISENSOR_8BIT) { + data[2] = (u8)(val); + } else if (data_length == MISENSOR_16BIT) { + u16 *wdata = (u16 *)&data[2]; + *wdata = be16_to_cpu((u16)val); + } else { + /* MISENSOR_32BIT */ + u32 *wdata = (u32 *)&data[2]; + *wdata = be32_to_cpu(val); + } + + num_msg = i2c_transfer(client->adapter, &msg, 1); + + /* + * HACK: Need some delay here for Rev 2 sensors otherwise some + * registers do not seem to load correctly. + */ + mdelay(1); + + if (num_msg >= 0) + return 0; + + dev_err(&client->dev, "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, num_msg); + if (retry <= I2C_RETRY_COUNT) { + dev_dbg(&client->dev, "retrying... %d", retry); + retry++; + msleep(20); + goto again; + } + + return num_msg; +} + +/** + * misensor_rmw_reg - Read/Modify/Write a value to a register in the sensor + * device + * @client: i2c driver client structure + * @data_length: 8/16/32-bits length + * @reg: register address + * @mask: masked out bits + * @set: bits set + * + * Read/modify/write a value to a register in the sensor device. + * Returns zero if successful, or non-zero otherwise. + */ +static int +misensor_rmw_reg(struct i2c_client *client, u16 data_length, u16 reg, + u32 mask, u32 set) +{ + int err; + u32 val; + + /* Exit when no mask */ + if (mask == 0) + return 0; + + /* @mask must not exceed data length */ + switch (data_length) { + case MISENSOR_8BIT: + if (mask & ~0xff) + return -EINVAL; + break; + case MISENSOR_16BIT: + if (mask & ~0xffff) + return -EINVAL; + break; + case MISENSOR_32BIT: + break; + default: + /* Wrong @data_length */ + return -EINVAL; + } + + err = mt9m114_read_reg(client, data_length, reg, &val); + if (err) { + v4l2_err(client, "misensor_rmw_reg error exit, read failed\n"); + return -EINVAL; + } + + val &= ~mask; + + /* + * Perform the OR function if the @set exists. + * Shift @set value to target bit location. @set should set only + * bits included in @mask. + * + * REVISIT: This function expects @set to be non-shifted. Its shift + * value is then defined to be equal to mask's LSB position. + * How about to inform values in their right offset position and avoid + * this unneeded shift operation? + */ + set <<= ffs(mask) - 1; + val |= set & mask; + + err = mt9m114_write_reg(client, data_length, reg, val); + if (err) { + v4l2_err(client, "misensor_rmw_reg error exit, write failed\n"); + return -EINVAL; + } + + return 0; +} + + +static int __mt9m114_flush_reg_array(struct i2c_client *client, + struct mt9m114_write_ctrl *ctrl) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + int retry = 0; + + if (ctrl->index == 0) + return 0; + +again: + msg.addr = client->addr; + msg.flags = 0; + msg.len = 2 + ctrl->index; + ctrl->buffer.addr = cpu_to_be16(ctrl->buffer.addr); + msg.buf = (u8 *)&ctrl->buffer; + + ret = i2c_transfer(client->adapter, &msg, num_msg); + if (ret != num_msg) { + if (++retry <= I2C_RETRY_COUNT) { + dev_dbg(&client->dev, "retrying... %d\n", retry); + msleep(20); + goto again; + } + dev_err(&client->dev, "%s: i2c transfer error\n", __func__); + return -EIO; + } + + ctrl->index = 0; + + /* + * REVISIT: Previously we had a delay after writing data to sensor. + * But it was removed as our tests have shown it is not necessary + * anymore. + */ + + return 0; +} + +static int __mt9m114_buf_reg_array(struct i2c_client *client, + struct mt9m114_write_ctrl *ctrl, + const struct misensor_reg *next) +{ + u16 *data16; + u32 *data32; + int err; + + /* Insufficient buffer? Let's flush and get more free space. */ + if (ctrl->index + next->length >= MT9M114_MAX_WRITE_BUF_SIZE) { + err = __mt9m114_flush_reg_array(client, ctrl); + if (err) + return err; + } + + switch (next->length) { + case MISENSOR_8BIT: + ctrl->buffer.data[ctrl->index] = (u8)next->val; + break; + case MISENSOR_16BIT: + data16 = (u16 *)&ctrl->buffer.data[ctrl->index]; + *data16 = cpu_to_be16((u16)next->val); + break; + case MISENSOR_32BIT: + data32 = (u32 *)&ctrl->buffer.data[ctrl->index]; + *data32 = cpu_to_be32(next->val); + break; + default: + return -EINVAL; + } + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->reg; + + ctrl->index += next->length; + + return 0; +} + +static int +__mt9m114_write_reg_is_consecutive(struct i2c_client *client, + struct mt9m114_write_ctrl *ctrl, + const struct misensor_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->reg; +} + +/* + * mt9m114_write_reg_array - Initializes a list of mt9m114 registers + * @client: i2c driver client structure + * @reglist: list of registers to be written + * @poll: completion polling requirement + * This function initializes a list of registers. When consecutive addresses + * are found in a row on the list, this function creates a buffer and sends + * consecutive data in a single i2c_transfer(). + * + * __mt9m114_flush_reg_array, __mt9m114_buf_reg_array() and + * __mt9m114_write_reg_is_consecutive() are internal functions to + * mt9m114_write_reg_array() and should be not used anywhere else. + * + */ +static int mt9m114_write_reg_array(struct i2c_client *client, + const struct misensor_reg *reglist, + int poll) +{ + const struct misensor_reg *next = reglist; + struct mt9m114_write_ctrl ctrl; + int err; + + if (poll == PRE_POLLING) { + err = mt9m114_wait_state(client, MT9M114_WAIT_STAT_TIMEOUT); + if (err) + return err; + } + + ctrl.index = 0; + for (; next->length != MISENSOR_TOK_TERM; next++) { + switch (next->length & MISENSOR_TOK_MASK) { + case MISENSOR_TOK_DELAY: + err = __mt9m114_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + case MISENSOR_TOK_RMW: + err = __mt9m114_flush_reg_array(client, &ctrl); + err |= misensor_rmw_reg(client, + next->length & + ~MISENSOR_TOK_RMW, + next->reg, next->val, + next->val2); + if (err) { + dev_err(&client->dev, "%s read err. aborted\n", + __func__); + return -EINVAL; + } + break; + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceed. + */ + if (!__mt9m114_write_reg_is_consecutive(client, &ctrl, + next)) { + err = __mt9m114_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __mt9m114_buf_reg_array(client, &ctrl, next); + if (err) { + v4l2_err(client, "%s: write error, aborted\n", + __func__); + return err; + } + break; + } + } + + err = __mt9m114_flush_reg_array(client, &ctrl); + if (err) + return err; + + if (poll == POST_POLLING) + return mt9m114_wait_state(client, MT9M114_WAIT_STAT_TIMEOUT); + + return 0; +} + +static int mt9m114_wait_state(struct i2c_client *client, int timeout) +{ + int ret; + unsigned int val; + + while (timeout-- > 0) { + ret = mt9m114_read_reg(client, MISENSOR_16BIT, 0x0080, &val); + if (ret) + return ret; + if ((val & 0x2) == 0) + return 0; + msleep(20); + } + + return -EINVAL; + +} + +static int mt9m114_set_suspend(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + return mt9m114_write_reg_array(client, + mt9m114_standby_reg, POST_POLLING); +} + +static int mt9m114_init_common(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + ret = mt9m114_write_reg_array(client, mt9m114_common, PRE_POLLING); + if (ret) + return ret; + return ret; +} + +static int power_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret; + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->power_ctrl) + return dev->platform_data->power_ctrl(sd, flag); + + if (flag) { + ret = dev->platform_data->v2p8_ctrl(sd, 1); + if (ret == 0) { + ret = dev->platform_data->v1p8_ctrl(sd, 1); + if (ret) + ret = dev->platform_data->v2p8_ctrl(sd, 0); + } + } else { + ret = dev->platform_data->v2p8_ctrl(sd, 0); + ret = dev->platform_data->v1p8_ctrl(sd, 0); + } + return ret; +} + +static int gpio_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret; + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->gpio_ctrl) + return dev->platform_data->gpio_ctrl(sd, flag); + + /* Note: current modules wire only one GPIO signal (RESET#), + * but the schematic wires up two to the connector. BIOS + * versions have been unfortunately inconsistent with which + * ACPI index RESET# is on, so hit both */ + + if (flag) { + ret = dev->platform_data->gpio0_ctrl(sd, 0); + ret = dev->platform_data->gpio1_ctrl(sd, 0); + msleep(60); + ret |= dev->platform_data->gpio0_ctrl(sd, 1); + ret |= dev->platform_data->gpio1_ctrl(sd, 1); + } else { + ret = dev->platform_data->gpio0_ctrl(sd, 0); + ret = dev->platform_data->gpio1_ctrl(sd, 0); + } + return ret; +} + +static int power_up(struct v4l2_subdev *sd) +{ + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (NULL == dev->platform_data) { + dev_err(&client->dev, "no camera_sensor_platform_data"); + return -ENODEV; + } + + /* power control */ + ret = power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* flis clock control */ + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 1); + if (ret) + dev_err(&client->dev, "gpio failed 1\n"); + /* + * according to DS, 44ms is needed between power up and first i2c + * commend + */ + msleep(50); + + return 0; + +fail_clk: + dev->platform_data->flisclk_ctrl(sd, 0); +fail_power: + power_ctrl(sd, 0); + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (NULL == dev->platform_data) { + dev_err(&client->dev, "no camera_sensor_platform_data"); + return -ENODEV; + } + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed 1\n"); + + /* power control */ + ret = power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "vprog failed.\n"); + + /*according to DS, 20ms is needed after power down*/ + msleep(20); + + return ret; +} + +static int mt9m114_s_power(struct v4l2_subdev *sd, int power) +{ + if (power == 0) + return power_down(sd); + else { + if (power_up(sd)) + return -EINVAL; + + return mt9m114_init_common(sd); + } +} + +/* + * distance - calculate the distance + * @res: resolution + * @w: width + * @h: height + * + * Get the gap between resolution and w/h. + * res->width/height smaller than w/h wouldn't be considered. + * Returns the value of gap or -1 if fail. + */ +#define LARGEST_ALLOWED_RATIO_MISMATCH 600 +static int distance(struct mt9m114_res_struct const *res, u32 w, u32 h) +{ + unsigned int w_ratio; + unsigned int h_ratio; + int match; + + if (w == 0) + return -1; + w_ratio = (res->width << 13) / w; + if (h == 0) + return -1; + h_ratio = (res->height << 13) / h; + if (h_ratio == 0) + return -1; + match = abs(((w_ratio << 13) / h_ratio) - ((int)8192)); + + if ((w_ratio < (int)8192) || (h_ratio < (int)8192) || + (match > LARGEST_ALLOWED_RATIO_MISMATCH)) + return -1; + + return w_ratio + h_ratio; +} + +/* Return the nearest higher resolution index */ +static int nearest_resolution_index(int w, int h) +{ + int i; + int idx = -1; + int dist; + int min_dist = INT_MAX; + const struct mt9m114_res_struct *tmp_res = NULL; + + for (i = 0; i < ARRAY_SIZE(mt9m114_res); i++) { + tmp_res = &mt9m114_res[i]; + dist = distance(tmp_res, w, h); + if (dist == -1) + continue; + if (dist < min_dist) { + min_dist = dist; + idx = i; + } + } + + return idx; +} + +static int mt9m114_try_res(u32 *w, u32 *h) +{ + int idx = 0; + + if ((*w > MT9M114_RES_960P_SIZE_H) + || (*h > MT9M114_RES_960P_SIZE_V)) { + *w = MT9M114_RES_960P_SIZE_H; + *h = MT9M114_RES_960P_SIZE_V; + } else { + idx = nearest_resolution_index(*w, *h); + + /* + * nearest_resolution_index() doesn't return smaller + * resolutions. If it fails, it means the requested + * resolution is higher than wecan support. Fallback + * to highest possible resolution in this case. + */ + if (idx == -1) + idx = ARRAY_SIZE(mt9m114_res) - 1; + + *w = mt9m114_res[idx].width; + *h = mt9m114_res[idx].height; + } + + return 0; +} + +static struct mt9m114_res_struct *mt9m114_to_res(u32 w, u32 h) +{ + int index; + + for (index = 0; index < N_RES; index++) { + if ((mt9m114_res[index].width == w) && + (mt9m114_res[index].height == h)) + break; + } + + /* No mode found */ + if (index >= N_RES) + return NULL; + + return &mt9m114_res[index]; +} + +static int mt9m114_res2size(unsigned int res, int *h_size, int *v_size) +{ + unsigned short hsize; + unsigned short vsize; + + switch (res) { + case MT9M114_RES_736P: + hsize = MT9M114_RES_736P_SIZE_H; + vsize = MT9M114_RES_736P_SIZE_V; + break; + case MT9M114_RES_864P: + hsize = MT9M114_RES_864P_SIZE_H; + vsize = MT9M114_RES_864P_SIZE_V; + break; + case MT9M114_RES_960P: + hsize = MT9M114_RES_960P_SIZE_H; + vsize = MT9M114_RES_960P_SIZE_V; + break; + default: + WARN(1, "%s: Resolution 0x%08x unknown\n", __func__, res); + return -EINVAL; + } + + if (h_size != NULL) + *h_size = hsize; + if (v_size != NULL) + *v_size = vsize; + + return 0; +} + +static int mt9m114_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct mt9m114_res_struct *res) +{ + struct atomisp_sensor_mode_data *buf = &info->data; + u32 reg_val; + int ret; + + if (info == NULL) + return -EINVAL; + + ret = mt9m114_read_reg(client, MISENSOR_32BIT, + REG_PIXEL_CLK, ®_val); + if (ret) + return ret; + buf->vt_pix_clk_freq_mhz = reg_val; + + /* get integration time */ + buf->coarse_integration_time_min = MT9M114_COARSE_INTG_TIME_MIN; + buf->coarse_integration_time_max_margin = + MT9M114_COARSE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_min = MT9M114_FINE_INTG_TIME_MIN; + buf->fine_integration_time_max_margin = + MT9M114_FINE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_def = MT9M114_FINE_INTG_TIME_MIN; + + buf->frame_length_lines = res->lines_per_frame; + buf->line_length_pck = res->pixels_per_line; + buf->read_mode = res->bin_mode; + + /* get the cropping and output resolution to ISP for this mode. */ + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_H_START, ®_val); + if (ret) + return ret; + buf->crop_horizontal_start = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_V_START, ®_val); + if (ret) + return ret; + buf->crop_vertical_start = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_H_END, ®_val); + if (ret) + return ret; + buf->crop_horizontal_end = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_V_END, ®_val); + if (ret) + return ret; + buf->crop_vertical_end = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_WIDTH, ®_val); + if (ret) + return ret; + buf->output_width = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_HEIGHT, ®_val); + if (ret) + return ret; + buf->output_height = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_TIMING_HTS, ®_val); + if (ret) + return ret; + buf->line_length_pck = reg_val; + + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_TIMING_VTS, ®_val); + if (ret) + return ret; + buf->frame_length_lines = reg_val; + + buf->binning_factor_x = res->bin_factor_x ? + res->bin_factor_x : 1; + buf->binning_factor_y = res->bin_factor_y ? + res->bin_factor_y : 1; + return 0; +} + +static int mt9m114_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + int width, height; + int ret; + if (format->pad) + return -EINVAL; + fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; + + ret = mt9m114_res2size(dev->res, &width, &height); + if (ret) + return ret; + fmt->width = width; + fmt->height = height; + + return 0; +} + +static int mt9m114_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct i2c_client *c = v4l2_get_subdevdata(sd); + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + struct mt9m114_res_struct *res_index; + u32 width = fmt->width; + u32 height = fmt->height; + struct camera_mipi_info *mt9m114_info = NULL; + + int ret; + if (format->pad) + return -EINVAL; + dev->streamon = 0; + dev->first_exp = MT9M114_DEFAULT_FIRST_EXP; + + mt9m114_info = v4l2_get_subdev_hostdata(sd); + if (mt9m114_info == NULL) + return -EINVAL; + + mt9m114_try_res(&width, &height); + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + cfg->try_fmt = *fmt; + return 0; + } + res_index = mt9m114_to_res(width, height); + + /* Sanity check */ + if (unlikely(!res_index)) { + WARN_ON(1); + return -EINVAL; + } + + switch (res_index->res) { + case MT9M114_RES_736P: + ret = mt9m114_write_reg_array(c, mt9m114_736P_init, NO_POLLING); + ret += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_R_MODE_MASK, MISENSOR_NORMAL_SET); + break; + case MT9M114_RES_864P: + ret = mt9m114_write_reg_array(c, mt9m114_864P_init, NO_POLLING); + ret += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_R_MODE_MASK, MISENSOR_NORMAL_SET); + break; + case MT9M114_RES_960P: + ret = mt9m114_write_reg_array(c, mt9m114_976P_init, NO_POLLING); + /* set sensor read_mode to Normal */ + ret += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_R_MODE_MASK, MISENSOR_NORMAL_SET); + break; + default: + v4l2_err(sd, "set resolution: %d failed!\n", res_index->res); + return -EINVAL; + } + + if (ret) + return -EINVAL; + + ret = mt9m114_write_reg_array(c, mt9m114_chgstat_reg, POST_POLLING); + if (ret < 0) + return ret; + + if (mt9m114_set_suspend(sd)) + return -EINVAL; + + if (dev->res != res_index->res) { + int index; + + /* Switch to different size */ + if (width <= 640) { + dev->nctx = 0x00; /* Set for context A */ + } else { + /* + * Context B is used for resolutions larger than 640x480 + * Using YUV for Context B. + */ + dev->nctx = 0x01; /* set for context B */ + } + + /* + * Marked current sensor res as being "used" + * + * REVISIT: We don't need to use an "used" field on each mode + * list entry to know which mode is selected. If this + * information is really necessary, how about to use a single + * variable on sensor dev struct? + */ + for (index = 0; index < N_RES; index++) { + if ((width == mt9m114_res[index].width) && + (height == mt9m114_res[index].height)) { + mt9m114_res[index].used = 1; + continue; + } + mt9m114_res[index].used = 0; + } + } + ret = mt9m114_get_intg_factor(c, mt9m114_info, + &mt9m114_res[res_index->res]); + if (ret) { + dev_err(&c->dev, "failed to get integration_factor\n"); + return -EINVAL; + } + /* + * mt9m114 - we don't poll for context switch + * because it does not happen with streaming disabled. + */ + dev->res = res_index->res; + + fmt->width = width; + fmt->height = height; + fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; + return 0; +} + +/* TODO: Update to SOC functions, remove exposure and gain */ +static int mt9m114_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + *val = (MT9M114_FOCAL_LENGTH_NUM << 16) | MT9M114_FOCAL_LENGTH_DEM; + return 0; +} + +static int mt9m114_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /*const f number for mt9m114*/ + *val = (MT9M114_F_NUMBER_DEFAULT_NUM << 16) | MT9M114_F_NUMBER_DEM; + return 0; +} + +static int mt9m114_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + *val = (MT9M114_F_NUMBER_DEFAULT_NUM << 24) | + (MT9M114_F_NUMBER_DEM << 16) | + (MT9M114_F_NUMBER_DEFAULT_NUM << 8) | MT9M114_F_NUMBER_DEM; + return 0; +} + +/* Horizontal flip the image. */ +static int mt9m114_g_hflip(struct v4l2_subdev *sd, s32 *val) +{ + struct i2c_client *c = v4l2_get_subdevdata(sd); + int ret; + u32 data; + ret = mt9m114_read_reg(c, MISENSOR_16BIT, + (u32)MISENSOR_READ_MODE, &data); + if (ret) + return ret; + *val = !!(data & MISENSOR_HFLIP_MASK); + + return 0; +} + +static int mt9m114_g_vflip(struct v4l2_subdev *sd, s32 *val) +{ + struct i2c_client *c = v4l2_get_subdevdata(sd); + int ret; + u32 data; + + ret = mt9m114_read_reg(c, MISENSOR_16BIT, + (u32)MISENSOR_READ_MODE, &data); + if (ret) + return ret; + *val = !!(data & MISENSOR_VFLIP_MASK); + + return 0; +} + +static long mt9m114_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + int ret = 0; + unsigned int coarse_integration = 0; + unsigned int fine_integration = 0; + unsigned int FLines = 0; + unsigned int FrameLengthLines = 0; /* ExposureTime.FrameLengthLines; */ + unsigned int AnalogGain, DigitalGain; + u32 AnalogGainToWrite = 0; + u16 exposure_local[3]; + + dev_dbg(&client->dev, "%s(0x%X 0x%X 0x%X)\n", __func__, + exposure->integration_time[0], exposure->gain[0], + exposure->gain[1]); + + coarse_integration = exposure->integration_time[0]; + /* fine_integration = ExposureTime.FineIntegrationTime; */ + /* FrameLengthLines = ExposureTime.FrameLengthLines; */ + FLines = mt9m114_res[dev->res].lines_per_frame; + AnalogGain = exposure->gain[0]; + DigitalGain = exposure->gain[1]; + if (!dev->streamon) { + /*Save the first exposure values while stream is off*/ + dev->first_exp = coarse_integration; + dev->first_gain = AnalogGain; + dev->first_diggain = DigitalGain; + } + /* DigitalGain = 0x400 * (((u16) DigitalGain) >> 8) + + ((unsigned int)(0x400 * (((u16) DigitalGain) & 0xFF)) >>8); */ + + /* set frame length */ + if (FLines < coarse_integration + 6) + FLines = coarse_integration + 6; + if (FLines < FrameLengthLines) + FLines = FrameLengthLines; + ret = mt9m114_write_reg(client, MISENSOR_16BIT, 0x300A, FLines); + if (ret) { + v4l2_err(client, "%s: fail to set FLines\n", __func__); + return -EINVAL; + } + + /* set coarse/fine integration */ + exposure_local[0] = REG_EXPO_COARSE; + exposure_local[1] = (u16)coarse_integration; + exposure_local[2] = (u16)fine_integration; + /* 3A provide real exposure time. + should not translate to any value here. */ + ret = mt9m114_write_reg(client, MISENSOR_16BIT, + REG_EXPO_COARSE, (u16)(coarse_integration)); + if (ret) { + v4l2_err(client, "%s: fail to set exposure time\n", __func__); + return -EINVAL; + } + + /* + // set analog/digital gain + switch(AnalogGain) + { + case 0: + AnalogGainToWrite = 0x0; + break; + case 1: + AnalogGainToWrite = 0x20; + break; + case 2: + AnalogGainToWrite = 0x60; + break; + case 4: + AnalogGainToWrite = 0xA0; + break; + case 8: + AnalogGainToWrite = 0xE0; + break; + default: + AnalogGainToWrite = 0x20; + break; + } + */ + if (DigitalGain >= 16 || DigitalGain <= 1) + DigitalGain = 1; + /* AnalogGainToWrite = + (u16)((DigitalGain << 12) | AnalogGainToWrite); */ + AnalogGainToWrite = (u16)((DigitalGain << 12) | (u16)AnalogGain); + ret = mt9m114_write_reg(client, MISENSOR_16BIT, + REG_GAIN, AnalogGainToWrite); + if (ret) { + v4l2_err(client, "%s: fail to set AnalogGainToWrite\n", + __func__); + return -EINVAL; + } + + return ret; +} + +static long mt9m114_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return mt9m114_s_exposure(sd, arg); + default: + return -EINVAL; + } + + return 0; +} + +/* This returns the exposure time being used. This should only be used + for filling in EXIF data, not for actual image processing. */ +static int mt9m114_g_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u32 coarse; + int ret; + + /* the fine integration time is currently not calculated */ + ret = mt9m114_read_reg(client, MISENSOR_16BIT, + REG_EXPO_COARSE, &coarse); + if (ret) + return ret; + + *value = coarse; + return 0; +} +#ifndef CSS15 +/* + * This function will return the sensor supported max exposure zone number. + * the sensor which supports max exposure zone number is 1. + */ +static int mt9m114_g_exposure_zone_num(struct v4l2_subdev *sd, s32 *val) +{ + *val = 1; + + return 0; +} + +/* + * set exposure metering, average/center_weighted/spot/matrix. + */ +static int mt9m114_s_exposure_metering(struct v4l2_subdev *sd, s32 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + switch (val) { + case V4L2_EXPOSURE_METERING_SPOT: + ret = mt9m114_write_reg_array(client, mt9m114_exp_average, + NO_POLLING); + if (ret) { + dev_err(&client->dev, "write exp_average reg err.\n"); + return ret; + } + break; + case V4L2_EXPOSURE_METERING_CENTER_WEIGHTED: + default: + ret = mt9m114_write_reg_array(client, mt9m114_exp_center, + NO_POLLING); + if (ret) { + dev_err(&client->dev, "write exp_default reg err"); + return ret; + } + } + + return 0; +} + +/* + * This function is for touch exposure feature. + */ +static int mt9m114_s_exposure_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_selection *sel) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + struct misensor_reg exp_reg; + int width, height; + int grid_width, grid_height; + int grid_left, grid_top, grid_right, grid_bottom; + int win_left, win_top, win_right, win_bottom; + int i, j; + int ret; + + if (sel->which != V4L2_SUBDEV_FORMAT_TRY && + sel->which != V4L2_SUBDEV_FORMAT_ACTIVE) + return -EINVAL; + + grid_left = sel->r.left; + grid_top = sel->r.top; + grid_right = sel->r.left + sel->r.width - 1; + grid_bottom = sel->r.top + sel->r.height - 1; + + ret = mt9m114_res2size(dev->res, &width, &height); + if (ret) + return ret; + + grid_width = width / 5; + grid_height = height / 5; + + if (grid_width && grid_height) { + win_left = grid_left / grid_width; + win_top = grid_top / grid_height; + win_right = grid_right / grid_width; + win_bottom = grid_bottom / grid_height; + } else { + dev_err(&client->dev, "Incorrect exp grid.\n"); + return -EINVAL; + } + + clamp_t(int, win_left, 0, 4); + clamp_t(int, win_top, 0, 4); + clamp_t(int, win_right, 0, 4); + clamp_t(int, win_bottom, 0, 4); + + ret = mt9m114_write_reg_array(client, mt9m114_exp_average, NO_POLLING); + if (ret) { + dev_err(&client->dev, "write exp_average reg err.\n"); + return ret; + } + + for (i = win_top; i <= win_bottom; i++) { + for (j = win_left; j <= win_right; j++) { + exp_reg = mt9m114_exp_win[i][j]; + + ret = mt9m114_write_reg(client, exp_reg.length, + exp_reg.reg, exp_reg.val); + if (ret) { + dev_err(&client->dev, "write exp_reg err.\n"); + return ret; + } + } + } + + return 0; +} +#endif + +static int mt9m114_g_bin_factor_x(struct v4l2_subdev *sd, s32 *val) +{ + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + + *val = mt9m114_res[dev->res].bin_factor_x; + + return 0; +} + +static int mt9m114_g_bin_factor_y(struct v4l2_subdev *sd, s32 *val) +{ + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + + *val = mt9m114_res[dev->res].bin_factor_y; + + return 0; +} + +static int mt9m114_s_ev(struct v4l2_subdev *sd, s32 val) +{ + struct i2c_client *c = v4l2_get_subdevdata(sd); + s32 luma = 0x37; + int err; + + /* EV value only support -2 to 2 + * 0: 0x37, 1:0x47, 2:0x57, -1:0x27, -2:0x17 + */ + if (val < -2 || val > 2) + return -EINVAL; + luma += 0x10 * val; + dev_dbg(&c->dev, "%s val:%d luma:0x%x\n", __func__, val, luma); + err = mt9m114_write_reg(c, MISENSOR_16BIT, 0x098E, 0xC87A); + if (err) { + dev_err(&c->dev, "%s logic addr access error\n", __func__); + return err; + } + err = mt9m114_write_reg(c, MISENSOR_8BIT, 0xC87A, (u32)luma); + if (err) { + dev_err(&c->dev, "%s write target_average_luma failed\n", + __func__); + return err; + } + udelay(10); + + return 0; +} + +static int mt9m114_g_ev(struct v4l2_subdev *sd, s32 *val) +{ + struct i2c_client *c = v4l2_get_subdevdata(sd); + int err; + u32 luma; + + err = mt9m114_write_reg(c, MISENSOR_16BIT, 0x098E, 0xC87A); + if (err) { + dev_err(&c->dev, "%s logic addr access error\n", __func__); + return err; + } + err = mt9m114_read_reg(c, MISENSOR_8BIT, 0xC87A, &luma); + if (err) { + dev_err(&c->dev, "%s read target_average_luma failed\n", + __func__); + return err; + } + luma -= 0x17; + luma /= 0x10; + *val = (s32)luma - 2; + dev_dbg(&c->dev, "%s val:%d\n", __func__, *val); + + return 0; +} + +/* Fake interface + * mt9m114 now can not support 3a_lock +*/ +static int mt9m114_s_3a_lock(struct v4l2_subdev *sd, s32 val) +{ + aaalock = val; + return 0; +} + +static int mt9m114_g_3a_lock(struct v4l2_subdev *sd, s32 *val) +{ + if (aaalock) + return V4L2_LOCK_EXPOSURE | V4L2_LOCK_WHITE_BALANCE + | V4L2_LOCK_FOCUS; + return 0; +} + +static int mt9m114_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct mt9m114_device *dev = + container_of(ctrl->handler, struct mt9m114_device, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_VFLIP: + dev_dbg(&client->dev, "%s: CID_VFLIP:%d.\n", + __func__, ctrl->val); + ret = mt9m114_t_vflip(&dev->sd, ctrl->val); + break; + case V4L2_CID_HFLIP: + dev_dbg(&client->dev, "%s: CID_HFLIP:%d.\n", + __func__, ctrl->val); + ret = mt9m114_t_hflip(&dev->sd, ctrl->val); + break; +#ifndef CSS15 + case V4L2_CID_EXPOSURE_METERING: + ret = mt9m114_s_exposure_metering(&dev->sd, ctrl->val); + break; +#endif + case V4L2_CID_EXPOSURE: + ret = mt9m114_s_ev(&dev->sd, ctrl->val); + break; + case V4L2_CID_3A_LOCK: + ret = mt9m114_s_3a_lock(&dev->sd, ctrl->val); + break; + default: + ret = -EINVAL; + } + return ret; +} + +static int mt9m114_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct mt9m114_device *dev = + container_of(ctrl->handler, struct mt9m114_device, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_VFLIP: + ret = mt9m114_g_vflip(&dev->sd, &ctrl->val); + break; + case V4L2_CID_HFLIP: + ret = mt9m114_g_hflip(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = mt9m114_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = mt9m114_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = mt9m114_g_fnumber_range(&dev->sd, &ctrl->val); + break; + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = mt9m114_g_exposure(&dev->sd, &ctrl->val); + break; +#ifndef CSS15 + case V4L2_CID_EXPOSURE_ZONE_NUM: + ret = mt9m114_g_exposure_zone_num(&dev->sd, &ctrl->val); + break; +#endif + case V4L2_CID_BIN_FACTOR_HORZ: + ret = mt9m114_g_bin_factor_x(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_VERT: + ret = mt9m114_g_bin_factor_y(&dev->sd, &ctrl->val); + break; + case V4L2_CID_EXPOSURE: + ret = mt9m114_g_ev(&dev->sd, &ctrl->val); + break; + case V4L2_CID_3A_LOCK: + ret = mt9m114_g_3a_lock(&dev->sd, &ctrl->val); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = mt9m114_s_ctrl, + .g_volatile_ctrl = mt9m114_g_volatile_ctrl +}; + +static struct v4l2_ctrl_config mt9m114_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_VFLIP, + .name = "Image v-Flip", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_HFLIP, + .name = "Image h-Flip", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .name = "focal length", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = MT9M114_FOCAL_LENGTH_DEFAULT, + .max = MT9M114_FOCAL_LENGTH_DEFAULT, + .step = 1, + .def = MT9M114_FOCAL_LENGTH_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .name = "f-number", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = MT9M114_F_NUMBER_DEFAULT, + .max = MT9M114_F_NUMBER_DEFAULT, + .step = 1, + .def = MT9M114_F_NUMBER_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .name = "f-number range", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = MT9M114_F_NUMBER_RANGE, + .max = MT9M114_F_NUMBER_RANGE, + .step = 1, + .def = MT9M114_F_NUMBER_RANGE, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .name = "exposure", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = 0xffff, + .step = 1, + .def = 0, + .flags = 0, + }, +#ifndef CSS15 + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ZONE_NUM, + .name = "one-time exposure zone number", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = 0xffff, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_METERING, + .name = "metering", + .type = V4L2_CTRL_TYPE_MENU, + .min = 0, + .max = 3, + .step = 1, + .def = 1, + .flags = 0, + }, +#endif + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_HORZ, + .name = "horizontal binning factor", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = MT9M114_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_VERT, + .name = "vertical binning factor", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 0, + .max = MT9M114_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE, + .name = "exposure biasx", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = -2, + .max = 2, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_3A_LOCK, + .name = "3a lock", + .type = V4L2_CTRL_TYPE_BITMASK, + .min = 0, + .max = V4L2_LOCK_EXPOSURE | V4L2_LOCK_WHITE_BALANCE | V4L2_LOCK_FOCUS, + .step = 1, + .def = 0, + .flags = 0, + }, +}; + +static int mt9m114_detect(struct mt9m114_device *dev, struct i2c_client *client) +{ + struct i2c_adapter *adapter = client->adapter; + u32 retvalue; + + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) { + dev_err(&client->dev, "%s: i2c error", __func__); + return -ENODEV; + } + mt9m114_read_reg(client, MISENSOR_16BIT, (u32)MT9M114_PID, &retvalue); + dev->real_model_id = retvalue; + + if (retvalue != MT9M114_MOD_ID) { + dev_err(&client->dev, "%s: failed: client->addr = %x\n", + __func__, client->addr); + return -ENODEV; + } + + return 0; +} + +static int +mt9m114_s_config(struct v4l2_subdev *sd, int irq, void *platform_data) +{ + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (NULL == platform_data) + return -ENODEV; + + dev->platform_data = + (struct camera_sensor_platform_data *)platform_data; + + if (dev->platform_data->platform_init) { + ret = dev->platform_data->platform_init(client); + if (ret) { + v4l2_err(client, "mt9m114 platform init err\n"); + return ret; + } + } + ret = power_up(sd); + if (ret) { + v4l2_err(client, "mt9m114 power-up err"); + return ret; + } + + /* config & detect sensor */ + ret = mt9m114_detect(dev, client); + if (ret) { + v4l2_err(client, "mt9m114_detect err s_config.\n"); + goto fail_detect; + } + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + ret = mt9m114_set_suspend(sd); + if (ret) { + v4l2_err(client, "mt9m114 suspend err"); + return ret; + } + + ret = power_down(sd); + if (ret) { + v4l2_err(client, "mt9m114 power down err"); + return ret; + } + + return ret; + +fail_csi_cfg: + dev->platform_data->csi_cfg(sd, 0); +fail_detect: + power_down(sd); + dev_err(&client->dev, "sensor power-gating failed\n"); + return ret; +} + +/* Horizontal flip the image. */ +static int mt9m114_t_hflip(struct v4l2_subdev *sd, int value) +{ + struct i2c_client *c = v4l2_get_subdevdata(sd); + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + int err; + /* set for direct mode */ + err = mt9m114_write_reg(c, MISENSOR_16BIT, 0x098E, 0xC850); + if (value) { + /* enable H flip ctx A */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC850, 0x01, 0x01); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC851, 0x01, 0x01); + /* ctx B */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC888, 0x01, 0x01); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC889, 0x01, 0x01); + + err += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_HFLIP_MASK, MISENSOR_FLIP_EN); + + dev->bpat = MT9M114_BPAT_GRGRBGBG; + } else { + /* disable H flip ctx A */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC850, 0x01, 0x00); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC851, 0x01, 0x00); + /* ctx B */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC888, 0x01, 0x00); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC889, 0x01, 0x00); + + err += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_HFLIP_MASK, MISENSOR_FLIP_DIS); + + dev->bpat = MT9M114_BPAT_BGBGGRGR; + } + + err += mt9m114_write_reg(c, MISENSOR_8BIT, 0x8404, 0x06); + udelay(10); + + return !!err; +} + +/* Vertically flip the image */ +static int mt9m114_t_vflip(struct v4l2_subdev *sd, int value) +{ + struct i2c_client *c = v4l2_get_subdevdata(sd); + int err; + /* set for direct mode */ + err = mt9m114_write_reg(c, MISENSOR_16BIT, 0x098E, 0xC850); + if (value >= 1) { + /* enable H flip - ctx A */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC850, 0x02, 0x01); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC851, 0x02, 0x01); + /* ctx B */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC888, 0x02, 0x01); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC889, 0x02, 0x01); + + err += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_VFLIP_MASK, MISENSOR_FLIP_EN); + } else { + /* disable H flip - ctx A */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC850, 0x02, 0x00); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC851, 0x02, 0x00); + /* ctx B */ + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC888, 0x02, 0x00); + err += misensor_rmw_reg(c, MISENSOR_8BIT, 0xC889, 0x02, 0x00); + + err += misensor_rmw_reg(c, MISENSOR_16BIT, MISENSOR_READ_MODE, + MISENSOR_VFLIP_MASK, MISENSOR_FLIP_DIS); + } + + err += mt9m114_write_reg(c, MISENSOR_8BIT, 0x8404, 0x06); + udelay(10); + + return !!err; +} +static int mt9m114_s_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + return 0; +} + +static int mt9m114_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + + interval->interval.numerator = 1; + interval->interval.denominator = mt9m114_res[dev->res].fps; + + return 0; +} + +static int mt9m114_s_stream(struct v4l2_subdev *sd, int enable) +{ + int ret; + struct i2c_client *c = v4l2_get_subdevdata(sd); + struct mt9m114_device *dev = to_mt9m114_sensor(sd); + struct atomisp_exposure exposure; + + if (enable) { + ret = mt9m114_write_reg_array(c, mt9m114_chgstat_reg, + POST_POLLING); + if (ret < 0) + return ret; + + if (dev->first_exp > MT9M114_MAX_FIRST_EXP) { + exposure.integration_time[0] = dev->first_exp; + exposure.gain[0] = dev->first_gain; + exposure.gain[1] = dev->first_diggain; + mt9m114_s_exposure(sd, &exposure); + } + dev->streamon = 1; + + } else { + dev->streamon = 0; + ret = mt9m114_set_suspend(sd); + } + + return ret; +} + +static int mt9m114_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index) + return -EINVAL; + code->code = MEDIA_BUS_FMT_SGRBG10_1X10; + + return 0; +} + +static int mt9m114_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + + unsigned int index = fse->index; + + if (index >= N_RES) + return -EINVAL; + + fse->min_width = mt9m114_res[index].width; + fse->min_height = mt9m114_res[index].height; + fse->max_width = mt9m114_res[index].width; + fse->max_height = mt9m114_res[index].height; + + return 0; +} + +static int mt9m114_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + int index; + struct mt9m114_device *snr = to_mt9m114_sensor(sd); + + if (frames == NULL) + return -EINVAL; + + for (index = 0; index < N_RES; index++) { + if (mt9m114_res[index].res == snr->res) + break; + } + + if (index >= N_RES) + return -EINVAL; + + *frames = mt9m114_res[index].skip_frames; + + return 0; +} + +static const struct v4l2_subdev_video_ops mt9m114_video_ops = { + .s_parm = mt9m114_s_parm, + .s_stream = mt9m114_s_stream, + .g_frame_interval = mt9m114_g_frame_interval, +}; + +static struct v4l2_subdev_sensor_ops mt9m114_sensor_ops = { + .g_skip_frames = mt9m114_g_skip_frames, +}; + +static const struct v4l2_subdev_core_ops mt9m114_core_ops = { + .s_power = mt9m114_s_power, + .ioctl = mt9m114_ioctl, +}; + +/* REVISIT: Do we need pad operations? */ +static const struct v4l2_subdev_pad_ops mt9m114_pad_ops = { + .enum_mbus_code = mt9m114_enum_mbus_code, + .enum_frame_size = mt9m114_enum_frame_size, + .get_fmt = mt9m114_get_fmt, + .set_fmt = mt9m114_set_fmt, +#ifndef CSS15 + .set_selection = mt9m114_s_exposure_selection, +#endif +}; + +static const struct v4l2_subdev_ops mt9m114_ops = { + .core = &mt9m114_core_ops, + .video = &mt9m114_video_ops, + .pad = &mt9m114_pad_ops, + .sensor = &mt9m114_sensor_ops, +}; + +static const struct media_entity_operations mt9m114_entity_ops = { + .link_setup = NULL, +}; + +static int mt9m114_remove(struct i2c_client *client) +{ + struct mt9m114_device *dev; + struct v4l2_subdev *sd = i2c_get_clientdata(client); + + dev = container_of(sd, struct mt9m114_device, sd); + dev->platform_data->csi_cfg(sd, 0); + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); + v4l2_device_unregister_subdev(sd); + media_entity_cleanup(&dev->sd.entity); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + kfree(dev); + return 0; +} + +static int mt9m114_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct mt9m114_device *dev; + int ret = 0; + unsigned int i; + void *pdata; + + /* Setup sensor configuration structure */ + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) { + dev_err(&client->dev, "out of memory\n"); + return -ENOMEM; + } + + v4l2_i2c_subdev_init(&dev->sd, client, &mt9m114_ops); + pdata = client->dev.platform_data; + if (ACPI_COMPANION(&client->dev)) + pdata = gmin_camera_platform_data(&dev->sd, + ATOMISP_INPUT_FORMAT_RAW_10, + atomisp_bayer_order_grbg); + if (pdata) + ret = mt9m114_s_config(&dev->sd, client->irq, pdata); + if (!pdata || ret) { + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + return ret; + } + + ret = atomisp_register_i2c_module(&dev->sd, pdata, RAW_CAMERA); + if (ret) { + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + /* Coverity CID 298095 - return on error */ + return ret; + } + + /*TODO add format code here*/ + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = MEDIA_BUS_FMT_SGRBG10_1X10; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + + ret = + v4l2_ctrl_handler_init(&dev->ctrl_handler, + ARRAY_SIZE(mt9m114_controls)); + if (ret) { + mt9m114_remove(client); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(mt9m114_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &mt9m114_controls[i], + NULL); + + if (dev->ctrl_handler.error) { + mt9m114_remove(client); + return dev->ctrl_handler.error; + } + + /* Use same lock for controls as for everything else. */ + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = &dev->ctrl_handler; + + /* REVISIT: Do we need media controller? */ + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) { + mt9m114_remove(client); + return ret; + } + return 0; +} + +MODULE_DEVICE_TABLE(i2c, mt9m114_id); + +static struct acpi_device_id mt9m114_acpi_match[] = { + { "INT33F0" }, + { "CRMT1040" }, + {}, +}; + +MODULE_DEVICE_TABLE(acpi, mt9m114_acpi_match); + +static struct i2c_driver mt9m114_driver = { + .driver = { + .owner = THIS_MODULE, + .name = "mt9m114", + .acpi_match_table = ACPI_PTR(mt9m114_acpi_match), + }, + .probe = mt9m114_probe, + .remove = mt9m114_remove, + .id_table = mt9m114_id, +}; + +static __init int init_mt9m114(void) +{ + return i2c_add_driver(&mt9m114_driver); +} + +static __exit void exit_mt9m114(void) +{ + i2c_del_driver(&mt9m114_driver); +} + +module_init(init_mt9m114); +module_exit(exit_mt9m114); + +MODULE_AUTHOR("Shuguang Gong "); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/mt9m114.h b/drivers/staging/media/atomisp/i2c/mt9m114.h new file mode 100644 index 0000000000000000000000000000000000000000..3f51fb1a7ac704be0ce9500ab46327927ff3b5ae --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/mt9m114.h @@ -0,0 +1,1786 @@ +/* + * Support for mt9m114 Camera Sensor. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __A1040_H__ +#define __A1040_H__ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define V4L2_IDENT_MT9M114 8245 + +#define MT9P111_REV3 +#define FULLINISUPPORT + +/* #defines for register writes and register array processing */ +#define MISENSOR_8BIT 1 +#define MISENSOR_16BIT 2 +#define MISENSOR_32BIT 4 + +#define MISENSOR_FWBURST0 0x80 +#define MISENSOR_FWBURST1 0x81 +#define MISENSOR_FWBURST4 0x84 +#define MISENSOR_FWBURST 0x88 + +#define MISENSOR_TOK_TERM 0xf000 /* terminating token for reg list */ +#define MISENSOR_TOK_DELAY 0xfe00 /* delay token for reg list */ +#define MISENSOR_TOK_FWLOAD 0xfd00 /* token indicating load FW */ +#define MISENSOR_TOK_POLL 0xfc00 /* token indicating poll instruction */ +#define MISENSOR_TOK_RMW 0x0010 /* RMW operation */ +#define MISENSOR_TOK_MASK 0xfff0 +#define MISENSOR_AWB_STEADY (1<<0) /* awb steady */ +#define MISENSOR_AE_READY (1<<3) /* ae status ready */ + +/* mask to set sensor read_mode via misensor_rmw_reg */ +#define MISENSOR_R_MODE_MASK 0x0330 +/* mask to set sensor vert_flip and horz_mirror */ +#define MISENSOR_VFLIP_MASK 0x0002 +#define MISENSOR_HFLIP_MASK 0x0001 +#define MISENSOR_FLIP_EN 1 +#define MISENSOR_FLIP_DIS 0 + +/* bits set to set sensor read_mode via misensor_rmw_reg */ +#define MISENSOR_SKIPPING_SET 0x0011 +#define MISENSOR_SUMMING_SET 0x0033 +#define MISENSOR_NORMAL_SET 0x0000 + +/* sensor register that control sensor read-mode and mirror */ +#define MISENSOR_READ_MODE 0xC834 +/* sensor ae-track status register */ +#define MISENSOR_AE_TRACK_STATUS 0xA800 +/* sensor awb status register */ +#define MISENSOR_AWB_STATUS 0xAC00 +/* sensor coarse integration time register */ +#define MISENSOR_COARSE_INTEGRATION_TIME 0xC83C + +/* registers */ +#define REG_SW_RESET 0x301A +#define REG_SW_STREAM 0xDC00 +#define REG_SCCB_CTRL 0x3100 +#define REG_SC_CMMN_CHIP_ID 0x0000 +#define REG_V_START 0xc800 /* 16bits */ +#define REG_H_START 0xc802 /* 16bits */ +#define REG_V_END 0xc804 /* 16bits */ +#define REG_H_END 0xc806 /* 16bits */ +#define REG_PIXEL_CLK 0xc808 /* 32bits */ +#define REG_TIMING_VTS 0xc812 /* 16bits */ +#define REG_TIMING_HTS 0xc814 /* 16bits */ +#define REG_WIDTH 0xC868 /* 16bits */ +#define REG_HEIGHT 0xC86A /* 16bits */ +#define REG_EXPO_COARSE 0x3012 /* 16bits */ +#define REG_EXPO_FINE 0x3014 /* 16bits */ +#define REG_GAIN 0x305E +#define REG_ANALOGGAIN 0x305F +#define REG_ADDR_ACESSS 0x098E /* logical_address_access */ +#define REG_COMM_Register 0x0080 /* command_register */ + +#define SENSOR_DETECTED 1 +#define SENSOR_NOT_DETECTED 0 + +#define I2C_RETRY_COUNT 5 +#define MSG_LEN_OFFSET 2 + +#ifndef MIPI_CONTROL +#define MIPI_CONTROL 0x3400 /* MIPI_Control */ +#endif + +/* GPIO pin on Moorestown */ +#define GPIO_SCLK_25 44 +#define GPIO_STB_PIN 47 + +#define GPIO_STDBY_PIN 49 /* ab:new */ +#define GPIO_RESET_PIN 50 + +/* System control register for Aptina A-1040SOC*/ +#define MT9M114_PID 0x0 + +/* MT9P111_DEVICE_ID */ +#define MT9M114_MOD_ID 0x2481 + +#define MT9M114_FINE_INTG_TIME_MIN 0 +#define MT9M114_FINE_INTG_TIME_MAX_MARGIN 0 +#define MT9M114_COARSE_INTG_TIME_MIN 1 +#define MT9M114_COARSE_INTG_TIME_MAX_MARGIN 6 + + +/* ulBPat; */ + +#define MT9M114_BPAT_RGRGGBGB (1 << 0) +#define MT9M114_BPAT_GRGRBGBG (1 << 1) +#define MT9M114_BPAT_GBGBRGRG (1 << 2) +#define MT9M114_BPAT_BGBGGRGR (1 << 3) + +#define MT9M114_FOCAL_LENGTH_NUM 208 /*2.08mm*/ +#define MT9M114_FOCAL_LENGTH_DEM 100 +#define MT9M114_F_NUMBER_DEFAULT_NUM 24 +#define MT9M114_F_NUMBER_DEM 10 +#define MT9M114_WAIT_STAT_TIMEOUT 100 +#define MT9M114_FLICKER_MODE_50HZ 1 +#define MT9M114_FLICKER_MODE_60HZ 2 +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define MT9M114_FOCAL_LENGTH_DEFAULT 0xD00064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define MT9M114_F_NUMBER_DEFAULT 0x18000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define MT9M114_F_NUMBER_RANGE 0x180a180a + +/* Supported resolutions */ +enum { + MT9M114_RES_736P, + MT9M114_RES_864P, + MT9M114_RES_960P, +}; +#define MT9M114_RES_960P_SIZE_H 1296 +#define MT9M114_RES_960P_SIZE_V 976 +#define MT9M114_RES_720P_SIZE_H 1280 +#define MT9M114_RES_720P_SIZE_V 720 +#define MT9M114_RES_576P_SIZE_H 1024 +#define MT9M114_RES_576P_SIZE_V 576 +#define MT9M114_RES_480P_SIZE_H 768 +#define MT9M114_RES_480P_SIZE_V 480 +#define MT9M114_RES_VGA_SIZE_H 640 +#define MT9M114_RES_VGA_SIZE_V 480 +#define MT9M114_RES_QVGA_SIZE_H 320 +#define MT9M114_RES_QVGA_SIZE_V 240 +#define MT9M114_RES_QCIF_SIZE_H 176 +#define MT9M114_RES_QCIF_SIZE_V 144 + +#define MT9M114_RES_720_480p_768_SIZE_H 736 +#define MT9M114_RES_720_480p_768_SIZE_V 496 +#define MT9M114_RES_736P_SIZE_H 1296 +#define MT9M114_RES_736P_SIZE_V 736 +#define MT9M114_RES_864P_SIZE_H 1296 +#define MT9M114_RES_864P_SIZE_V 864 +#define MT9M114_RES_976P_SIZE_H 1296 +#define MT9M114_RES_976P_SIZE_V 976 + +#define MT9M114_BIN_FACTOR_MAX 3 + +#define MT9M114_DEFAULT_FIRST_EXP 0x10 +#define MT9M114_MAX_FIRST_EXP 0x302 + +/* completion status polling requirements, usage based on Aptina .INI Rev2 */ +enum poll_reg { + NO_POLLING, + PRE_POLLING, + POST_POLLING, +}; +/* + * struct misensor_reg - MI sensor register format + * @length: length of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * Define a structure for sensor register initialization values + */ +struct misensor_reg { + u32 length; + u32 reg; + u32 val; /* value or for read/mod/write, AND mask */ + u32 val2; /* optional; for rmw, OR mask */ +}; + +/* + * struct misensor_fwreg - Firmware burst command + * @type: FW burst or 8/16 bit register + * @addr: 16-bit offset to register or other values depending on type + * @valx: data value for burst (or other commands) + * + * Define a structure for sensor register initialization values + */ +struct misensor_fwreg { + u32 type; /* type of value, register or FW burst string */ + u32 addr; /* target address */ + u32 val0; + u32 val1; + u32 val2; + u32 val3; + u32 val4; + u32 val5; + u32 val6; + u32 val7; +}; + +struct regval_list { + u16 reg_num; + u8 value; +}; + +struct mt9m114_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + + struct camera_sensor_platform_data *platform_data; + struct mutex input_lock; /* serialize sensor's ioctl */ + struct v4l2_ctrl_handler ctrl_handler; + int real_model_id; + int nctx; + int power; + + unsigned int bus_width; + unsigned int mode; + unsigned int field_inv; + unsigned int field_sel; + unsigned int ycseq; + unsigned int conv422; + unsigned int bpat; + unsigned int hpol; + unsigned int vpol; + unsigned int edge; + unsigned int bls; + unsigned int gamma; + unsigned int cconv; + unsigned int res; + unsigned int dwn_sz; + unsigned int blc; + unsigned int agc; + unsigned int awb; + unsigned int aec; + /* extention SENSOR version 2 */ + unsigned int cie_profile; + + /* extention SENSOR version 3 */ + unsigned int flicker_freq; + + /* extension SENSOR version 4 */ + unsigned int smia_mode; + unsigned int mipi_mode; + + /* Add name here to load shared library */ + unsigned int type; + + /*Number of MIPI lanes*/ + unsigned int mipi_lanes; + /*WA for low light AE*/ + unsigned int first_exp; + unsigned int first_gain; + unsigned int first_diggain; + char name[32]; + + u8 lightfreq; + u8 streamon; +}; + +struct mt9m114_format_struct { + u8 *desc; + u32 pixelformat; + struct regval_list *regs; +}; + +struct mt9m114_res_struct { + u8 *desc; + int res; + int width; + int height; + int fps; + int skip_frames; + bool used; + struct regval_list *regs; + u16 pixels_per_line; + u16 lines_per_frame; + u8 bin_factor_x; + u8 bin_factor_y; + u8 bin_mode; +}; + +/* 2 bytes used for address: 256 bytes total */ +#define MT9M114_MAX_WRITE_BUF_SIZE 254 +struct mt9m114_write_buffer { + u16 addr; + u8 data[MT9M114_MAX_WRITE_BUF_SIZE]; +}; + +struct mt9m114_write_ctrl { + int index; + struct mt9m114_write_buffer buffer; +}; + +/* + * Modes supported by the mt9m114 driver. + * Please, keep them in ascending order. + */ +static struct mt9m114_res_struct mt9m114_res[] = { + { + .desc = "720P", + .res = MT9M114_RES_736P, + .width = 1296, + .height = 736, + .fps = 30, + .used = 0, + .regs = NULL, + .skip_frames = 1, + + .pixels_per_line = 0x0640, + .lines_per_frame = 0x0307, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + }, + { + .desc = "848P", + .res = MT9M114_RES_864P, + .width = 1296, + .height = 864, + .fps = 30, + .used = 0, + .regs = NULL, + .skip_frames = 1, + + .pixels_per_line = 0x0640, + .lines_per_frame = 0x03E8, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + }, + { + .desc = "960P", + .res = MT9M114_RES_960P, + .width = 1296, + .height = 976, + .fps = 30, + .used = 0, + .regs = NULL, + .skip_frames = 1, + + .pixels_per_line = 0x0644, /* consistent with regs arrays */ + .lines_per_frame = 0x03E5, /* consistent with regs arrays */ + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + }, +}; +#define N_RES (ARRAY_SIZE(mt9m114_res)) + +static const struct i2c_device_id mt9m114_id[] = { + {"mt9m114", 0}, + {} +}; + +static struct misensor_reg const mt9m114_exitstandby[] = { + {MISENSOR_16BIT, 0x098E, 0xDC00}, + /* exit-standby */ + {MISENSOR_8BIT, 0xDC00, 0x54}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_exp_win[5][5] = { + { + {MISENSOR_8BIT, 0xA407, 0x64}, + {MISENSOR_8BIT, 0xA408, 0x64}, + {MISENSOR_8BIT, 0xA409, 0x64}, + {MISENSOR_8BIT, 0xA40A, 0x64}, + {MISENSOR_8BIT, 0xA40B, 0x64}, + }, + { + {MISENSOR_8BIT, 0xA40C, 0x64}, + {MISENSOR_8BIT, 0xA40D, 0x64}, + {MISENSOR_8BIT, 0xA40E, 0x64}, + {MISENSOR_8BIT, 0xA40F, 0x64}, + {MISENSOR_8BIT, 0xA410, 0x64}, + }, + { + {MISENSOR_8BIT, 0xA411, 0x64}, + {MISENSOR_8BIT, 0xA412, 0x64}, + {MISENSOR_8BIT, 0xA413, 0x64}, + {MISENSOR_8BIT, 0xA414, 0x64}, + {MISENSOR_8BIT, 0xA415, 0x64}, + }, + { + {MISENSOR_8BIT, 0xA416, 0x64}, + {MISENSOR_8BIT, 0xA417, 0x64}, + {MISENSOR_8BIT, 0xA418, 0x64}, + {MISENSOR_8BIT, 0xA419, 0x64}, + {MISENSOR_8BIT, 0xA41A, 0x64}, + }, + { + {MISENSOR_8BIT, 0xA41B, 0x64}, + {MISENSOR_8BIT, 0xA41C, 0x64}, + {MISENSOR_8BIT, 0xA41D, 0x64}, + {MISENSOR_8BIT, 0xA41E, 0x64}, + {MISENSOR_8BIT, 0xA41F, 0x64}, + }, +}; + +static struct misensor_reg const mt9m114_exp_average[] = { + {MISENSOR_8BIT, 0xA407, 0x00}, + {MISENSOR_8BIT, 0xA408, 0x00}, + {MISENSOR_8BIT, 0xA409, 0x00}, + {MISENSOR_8BIT, 0xA40A, 0x00}, + {MISENSOR_8BIT, 0xA40B, 0x00}, + {MISENSOR_8BIT, 0xA40C, 0x00}, + {MISENSOR_8BIT, 0xA40D, 0x00}, + {MISENSOR_8BIT, 0xA40E, 0x00}, + {MISENSOR_8BIT, 0xA40F, 0x00}, + {MISENSOR_8BIT, 0xA410, 0x00}, + {MISENSOR_8BIT, 0xA411, 0x00}, + {MISENSOR_8BIT, 0xA412, 0x00}, + {MISENSOR_8BIT, 0xA413, 0x00}, + {MISENSOR_8BIT, 0xA414, 0x00}, + {MISENSOR_8BIT, 0xA415, 0x00}, + {MISENSOR_8BIT, 0xA416, 0x00}, + {MISENSOR_8BIT, 0xA417, 0x00}, + {MISENSOR_8BIT, 0xA418, 0x00}, + {MISENSOR_8BIT, 0xA419, 0x00}, + {MISENSOR_8BIT, 0xA41A, 0x00}, + {MISENSOR_8BIT, 0xA41B, 0x00}, + {MISENSOR_8BIT, 0xA41C, 0x00}, + {MISENSOR_8BIT, 0xA41D, 0x00}, + {MISENSOR_8BIT, 0xA41E, 0x00}, + {MISENSOR_8BIT, 0xA41F, 0x00}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_exp_center[] = { + {MISENSOR_8BIT, 0xA407, 0x19}, + {MISENSOR_8BIT, 0xA408, 0x19}, + {MISENSOR_8BIT, 0xA409, 0x19}, + {MISENSOR_8BIT, 0xA40A, 0x19}, + {MISENSOR_8BIT, 0xA40B, 0x19}, + {MISENSOR_8BIT, 0xA40C, 0x19}, + {MISENSOR_8BIT, 0xA40D, 0x4B}, + {MISENSOR_8BIT, 0xA40E, 0x4B}, + {MISENSOR_8BIT, 0xA40F, 0x4B}, + {MISENSOR_8BIT, 0xA410, 0x19}, + {MISENSOR_8BIT, 0xA411, 0x19}, + {MISENSOR_8BIT, 0xA412, 0x4B}, + {MISENSOR_8BIT, 0xA413, 0x64}, + {MISENSOR_8BIT, 0xA414, 0x4B}, + {MISENSOR_8BIT, 0xA415, 0x19}, + {MISENSOR_8BIT, 0xA416, 0x19}, + {MISENSOR_8BIT, 0xA417, 0x4B}, + {MISENSOR_8BIT, 0xA418, 0x4B}, + {MISENSOR_8BIT, 0xA419, 0x4B}, + {MISENSOR_8BIT, 0xA41A, 0x19}, + {MISENSOR_8BIT, 0xA41B, 0x19}, + {MISENSOR_8BIT, 0xA41C, 0x19}, + {MISENSOR_8BIT, 0xA41D, 0x19}, + {MISENSOR_8BIT, 0xA41E, 0x19}, + {MISENSOR_8BIT, 0xA41F, 0x19}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_suspend[] = { + {MISENSOR_16BIT, 0x098E, 0xDC00}, + {MISENSOR_8BIT, 0xDC00, 0x40}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_streaming[] = { + {MISENSOR_16BIT, 0x098E, 0xDC00}, + {MISENSOR_8BIT, 0xDC00, 0x34}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_standby_reg[] = { + {MISENSOR_16BIT, 0x098E, 0xDC00}, + {MISENSOR_8BIT, 0xDC00, 0x50}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_wakeup_reg[] = { + {MISENSOR_16BIT, 0x098E, 0xDC00}, + {MISENSOR_8BIT, 0xDC00, 0x54}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_chgstat_reg[] = { + {MISENSOR_16BIT, 0x098E, 0xDC00}, + {MISENSOR_8BIT, 0xDC00, 0x28}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +/* [1296x976_30fps] - Intel */ +static struct misensor_reg const mt9m114_960P_init[] = { + {MISENSOR_16BIT, 0x098E, 0x1000}, + {MISENSOR_8BIT, 0xC97E, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {MISENSOR_16BIT, 0xC980, 0x0128}, /* cam_sysctl_pll_divider_m_n = 276 */ + {MISENSOR_16BIT, 0xC982, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {MISENSOR_16BIT, 0xC800, 0x0000}, /* cam_sensor_cfg_y_addr_start = 0 */ + {MISENSOR_16BIT, 0xC802, 0x0000}, /* cam_sensor_cfg_x_addr_start = 0 */ + {MISENSOR_16BIT, 0xC804, 0x03CF}, /* cam_sensor_cfg_y_addr_end = 971 */ + {MISENSOR_16BIT, 0xC806, 0x050F}, /* cam_sensor_cfg_x_addr_end = 1291 */ + {MISENSOR_16BIT, 0xC808, 0x02DC}, /* cam_sensor_cfg_pixclk = 48000000 */ + {MISENSOR_16BIT, 0xC80A, 0x6C00}, + {MISENSOR_16BIT, 0xC80C, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + /* cam_sensor_cfg_fine_integ_time_min = 219 */ + {MISENSOR_16BIT, 0xC80E, 0x00DB}, + /* cam_sensor_cfg_fine_integ_time_max = 1459 */ + {MISENSOR_16BIT, 0xC810, 0x05B3}, + /* cam_sensor_cfg_frame_length_lines = 1006 */ + {MISENSOR_16BIT, 0xC812, 0x03F6}, + /* cam_sensor_cfg_line_length_pck = 1590 */ + {MISENSOR_16BIT, 0xC814, 0x063E}, + /* cam_sensor_cfg_fine_correction = 96 */ + {MISENSOR_16BIT, 0xC816, 0x0060}, + /* cam_sensor_cfg_cpipe_last_row = 963 */ + {MISENSOR_16BIT, 0xC818, 0x03C3}, + {MISENSOR_16BIT, 0xC826, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {MISENSOR_16BIT, 0xC834, 0x0000}, /* cam_sensor_control_read_mode = 0 */ + {MISENSOR_16BIT, 0xC854, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {MISENSOR_16BIT, 0xC856, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {MISENSOR_16BIT, 0xC858, 0x0508}, /* cam_crop_window_width = 1280 */ + {MISENSOR_16BIT, 0xC85A, 0x03C8}, /* cam_crop_window_height = 960 */ + {MISENSOR_8BIT, 0xC85C, 0x03}, /* cam_crop_cropmode = 3 */ + {MISENSOR_16BIT, 0xC868, 0x0508}, /* cam_output_width = 1280 */ + {MISENSOR_16BIT, 0xC86A, 0x03C8}, /* cam_output_height = 960 */ + {MISENSOR_TOK_TERM, 0, 0}, +}; + +/* [1296x976_30fps_768Mbps] */ +static struct misensor_reg const mt9m114_976P_init[] = { + {MISENSOR_16BIT, 0x98E, 0x1000}, + {MISENSOR_8BIT, 0xC97E, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {MISENSOR_16BIT, 0xC980, 0x0128}, /* cam_sysctl_pll_divider_m_n = 276 */ + {MISENSOR_16BIT, 0xC982, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {MISENSOR_16BIT, 0xC800, 0x0000}, /* cam_sensor_cfg_y_addr_start = 0 */ + {MISENSOR_16BIT, 0xC802, 0x0000}, /* cam_sensor_cfg_x_addr_start = 0 */ + {MISENSOR_16BIT, 0xC804, 0x03CF}, /* cam_sensor_cfg_y_addr_end = 975 */ + {MISENSOR_16BIT, 0xC806, 0x050F}, /* cam_sensor_cfg_x_addr_end = 1295 */ + {MISENSOR_32BIT, 0xC808, 0x2DC6C00},/* cam_sensor_cfg_pixclk = 480000*/ + {MISENSOR_16BIT, 0xC80C, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + /* cam_sensor_cfg_fine_integ_time_min = 219 */ + {MISENSOR_16BIT, 0xC80E, 0x00DB}, + /* 0x062E //cam_sensor_cfg_fine_integ_time_max = 1459 */ + {MISENSOR_16BIT, 0xC810, 0x05B3}, + /* 0x074C //cam_sensor_cfg_frame_length_lines = 1006 */ + {MISENSOR_16BIT, 0xC812, 0x03E5}, + /* 0x06B1 /cam_sensor_cfg_line_length_pck = 1590 */ + {MISENSOR_16BIT, 0xC814, 0x0644}, + /* cam_sensor_cfg_fine_correction = 96 */ + {MISENSOR_16BIT, 0xC816, 0x0060}, + /* cam_sensor_cfg_cpipe_last_row = 963 */ + {MISENSOR_16BIT, 0xC818, 0x03C3}, + {MISENSOR_16BIT, 0xC826, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {MISENSOR_16BIT, 0xC834, 0x0000}, /* cam_sensor_control_read_mode = 0 */ + {MISENSOR_16BIT, 0xC854, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {MISENSOR_16BIT, 0xC856, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {MISENSOR_16BIT, 0xC858, 0x0508}, /* cam_crop_window_width = 1288 */ + {MISENSOR_16BIT, 0xC85A, 0x03C8}, /* cam_crop_window_height = 968 */ + {MISENSOR_8BIT, 0xC85C, 0x03}, /* cam_crop_cropmode = 3 */ + {MISENSOR_16BIT, 0xC868, 0x0508}, /* cam_output_width = 1288 */ + {MISENSOR_16BIT, 0xC86A, 0x03C8}, /* cam_output_height = 968 */ + {MISENSOR_8BIT, 0xC878, 0x00}, /* 0x0E //cam_aet_aemode = 0 */ + {MISENSOR_TOK_TERM, 0, 0} +}; + +/* [1296x864_30fps] */ +static struct misensor_reg const mt9m114_864P_init[] = { + {MISENSOR_16BIT, 0x98E, 0x1000}, + {MISENSOR_8BIT, 0xC97E, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {MISENSOR_16BIT, 0xC980, 0x0128}, /* cam_sysctl_pll_divider_m_n = 276 */ + {MISENSOR_16BIT, 0xC982, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {MISENSOR_16BIT, 0xC800, 0x0038}, /* cam_sensor_cfg_y_addr_start = 56 */ + {MISENSOR_16BIT, 0xC802, 0x0000}, /* cam_sensor_cfg_x_addr_start = 0 */ + {MISENSOR_16BIT, 0xC804, 0x0397}, /* cam_sensor_cfg_y_addr_end = 919 */ + {MISENSOR_16BIT, 0xC806, 0x050F}, /* cam_sensor_cfg_x_addr_end = 1295 */ + /* cam_sensor_cfg_pixclk = 48000000 */ + {MISENSOR_32BIT, 0xC808, 0x2DC6C00}, + {MISENSOR_16BIT, 0xC80C, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + /* cam_sensor_cfg_fine_integ_time_min = 219 */ + {MISENSOR_16BIT, 0xC80E, 0x00DB}, + /* cam_sensor_cfg_fine_integ_time_max = 1469 */ + {MISENSOR_16BIT, 0xC810, 0x05BD}, + /* cam_sensor_cfg_frame_length_lines = 1000 */ + {MISENSOR_16BIT, 0xC812, 0x03E8}, + /* cam_sensor_cfg_line_length_pck = 1600 */ + {MISENSOR_16BIT, 0xC814, 0x0640}, + /* cam_sensor_cfg_fine_correction = 96 */ + {MISENSOR_16BIT, 0xC816, 0x0060}, + /* cam_sensor_cfg_cpipe_last_row = 859 */ + {MISENSOR_16BIT, 0xC818, 0x035B}, + {MISENSOR_16BIT, 0xC826, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {MISENSOR_16BIT, 0xC834, 0x0000}, /* cam_sensor_control_read_mode = 0 */ + {MISENSOR_16BIT, 0xC854, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {MISENSOR_16BIT, 0xC856, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {MISENSOR_16BIT, 0xC858, 0x0508}, /* cam_crop_window_width = 1288 */ + {MISENSOR_16BIT, 0xC85A, 0x0358}, /* cam_crop_window_height = 856 */ + {MISENSOR_8BIT, 0xC85C, 0x03}, /* cam_crop_cropmode = 3 */ + {MISENSOR_16BIT, 0xC868, 0x0508}, /* cam_output_width = 1288 */ + {MISENSOR_16BIT, 0xC86A, 0x0358}, /* cam_output_height = 856 */ + {MISENSOR_8BIT, 0xC878, 0x00}, /* 0x0E //cam_aet_aemode = 0 */ + {MISENSOR_TOK_TERM, 0, 0} +}; + +/* [1296x736_30fps] */ +static struct misensor_reg const mt9m114_736P_init[] = { + {MISENSOR_16BIT, 0x98E, 0x1000}, + {MISENSOR_8BIT, 0xC97E, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {MISENSOR_16BIT, 0xC980, 0x011F}, /* cam_sysctl_pll_divider_m_n = 287 */ + {MISENSOR_16BIT, 0xC982, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {MISENSOR_16BIT, 0xC800, 0x0078}, /* cam_sensor_cfg_y_addr_start = 120*/ + {MISENSOR_16BIT, 0xC802, 0x0000}, /* cam_sensor_cfg_x_addr_start = 0 */ + {MISENSOR_16BIT, 0xC804, 0x0357}, /* cam_sensor_cfg_y_addr_end = 855 */ + {MISENSOR_16BIT, 0xC806, 0x050F}, /* cam_sensor_cfg_x_addr_end = 1295 */ + {MISENSOR_32BIT, 0xC808, 0x237A07F}, /* cam_sensor_cfg_pixclk=37199999*/ + {MISENSOR_16BIT, 0xC80C, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + /* cam_sensor_cfg_fine_integ_time_min = 219 */ + {MISENSOR_16BIT, 0xC80E, 0x00DB}, + /* 0x062E //cam_sensor_cfg_fine_integ_time_max = 1469 */ + {MISENSOR_16BIT, 0xC810, 0x05BD}, + /* 0x074C //cam_sensor_cfg_frame_length_lines = 775 */ + {MISENSOR_16BIT, 0xC812, 0x0307}, + /* 0x06B1 /cam_sensor_cfg_line_length_pck = 1600 */ + {MISENSOR_16BIT, 0xC814, 0x0640}, + /* cam_sensor_cfg_fine_correction = 96 */ + {MISENSOR_16BIT, 0xC816, 0x0060}, + /* cam_sensor_cfg_cpipe_last_row = 731 */ + {MISENSOR_16BIT, 0xC818, 0x02DB}, + {MISENSOR_16BIT, 0xC826, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {MISENSOR_16BIT, 0xC834, 0x0000}, /* cam_sensor_control_read_mode = 0 */ + {MISENSOR_16BIT, 0xC854, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {MISENSOR_16BIT, 0xC856, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {MISENSOR_16BIT, 0xC858, 0x0508}, /* cam_crop_window_width = 1288 */ + {MISENSOR_16BIT, 0xC85A, 0x02D8}, /* cam_crop_window_height = 728 */ + {MISENSOR_8BIT, 0xC85C, 0x03}, /* cam_crop_cropmode = 3 */ + {MISENSOR_16BIT, 0xC868, 0x0508}, /* cam_output_width = 1288 */ + {MISENSOR_16BIT, 0xC86A, 0x02D8}, /* cam_output_height = 728 */ + {MISENSOR_8BIT, 0xC878, 0x00}, /* 0x0E //cam_aet_aemode = 0 */ + {MISENSOR_TOK_TERM, 0, 0} +}; + +/* [736x496_30fps_768Mbps] */ +static struct misensor_reg const mt9m114_720_480P_init[] = { + {MISENSOR_16BIT, 0x98E, 0x1000}, + {MISENSOR_8BIT, 0xC97E, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {MISENSOR_16BIT, 0xC980, 0x0128}, /* cam_sysctl_pll_divider_m_n = 276 */ + {MISENSOR_16BIT, 0xC982, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {MISENSOR_16BIT, 0xC800, 0x00F0}, /* cam_sensor_cfg_y_addr_start = 240*/ + {MISENSOR_16BIT, 0xC802, 0x0118}, /* cam_sensor_cfg_x_addr_start = 280*/ + {MISENSOR_16BIT, 0xC804, 0x02DF}, /* cam_sensor_cfg_y_addr_end = 735 */ + {MISENSOR_16BIT, 0xC806, 0x03F7}, /* cam_sensor_cfg_x_addr_end = 1015 */ + /* cam_sensor_cfg_pixclk = 48000000 */ + {MISENSOR_32BIT, 0xC808, 0x2DC6C00}, + {MISENSOR_16BIT, 0xC80C, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + /* cam_sensor_cfg_fine_integ_time_min = 219 */ + {MISENSOR_16BIT, 0xC80E, 0x00DB}, + /* 0x062E //cam_sensor_cfg_fine_integ_time_max = 1459 */ + {MISENSOR_16BIT, 0xC810, 0x05B3}, + /* 0x074C //cam_sensor_cfg_frame_length_lines = 997 */ + {MISENSOR_16BIT, 0xC812, 0x03E5}, + /* 0x06B1 /cam_sensor_cfg_line_length_pck = 1604 */ + {MISENSOR_16BIT, 0xC814, 0x0644}, + /* cam_sensor_cfg_fine_correction = 96 */ + {MISENSOR_16BIT, 0xC816, 0x0060}, + {MISENSOR_16BIT, 0xC818, 0x03C3}, /* cam_sensor_cfg_cpipe_last_row=963*/ + {MISENSOR_16BIT, 0xC826, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {MISENSOR_16BIT, 0xC834, 0x0000}, /* cam_sensor_control_read_mode = 0*/ + {MISENSOR_16BIT, 0xC854, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {MISENSOR_16BIT, 0xC856, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {MISENSOR_16BIT, 0xC858, 0x02D8}, /* cam_crop_window_width = 728 */ + {MISENSOR_16BIT, 0xC85A, 0x01E8}, /* cam_crop_window_height = 488 */ + {MISENSOR_8BIT, 0xC85C, 0x03}, /* cam_crop_cropmode = 3 */ + {MISENSOR_16BIT, 0xC868, 0x02D8}, /* cam_output_width = 728 */ + {MISENSOR_16BIT, 0xC86A, 0x01E8}, /* cam_output_height = 488 */ + {MISENSOR_8BIT, 0xC878, 0x00}, /* 0x0E //cam_aet_aemode = 0 */ + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_common[] = { + /* reset */ + {MISENSOR_16BIT, 0x301A, 0x0234}, + /* LOAD = Step2-PLL_Timing //PLL and Timing */ + {MISENSOR_16BIT, 0x098E, 0x1000}, /* LOGICAL_ADDRESS_ACCESS */ + {MISENSOR_8BIT, 0xC97E, 0x01}, /* cam_sysctl_pll_enable = 1 */ + {MISENSOR_16BIT, 0xC980, 0x0128}, /* cam_sysctl_pll_divider_m_n = 276 */ + {MISENSOR_16BIT, 0xC982, 0x0700}, /* cam_sysctl_pll_divider_p = 1792 */ + {MISENSOR_16BIT, 0xC800, 0x0000}, /* cam_sensor_cfg_y_addr_start = 216*/ + {MISENSOR_16BIT, 0xC802, 0x0000}, /* cam_sensor_cfg_x_addr_start = 168*/ + {MISENSOR_16BIT, 0xC804, 0x03CD}, /* cam_sensor_cfg_y_addr_end = 761 */ + {MISENSOR_16BIT, 0xC806, 0x050D}, /* cam_sensor_cfg_x_addr_end = 1127 */ + {MISENSOR_16BIT, 0xC808, 0x02DC}, /* cam_sensor_cfg_pixclk = 24000000 */ + {MISENSOR_16BIT, 0xC80A, 0x6C00}, + {MISENSOR_16BIT, 0xC80C, 0x0001}, /* cam_sensor_cfg_row_speed = 1 */ + /* cam_sensor_cfg_fine_integ_time_min = 219 */ + {MISENSOR_16BIT, 0xC80E, 0x01C3}, + /* cam_sensor_cfg_fine_integ_time_max = 1149 */ + {MISENSOR_16BIT, 0xC810, 0x03F7}, + /* cam_sensor_cfg_frame_length_lines = 625 */ + {MISENSOR_16BIT, 0xC812, 0x0500}, + /* cam_sensor_cfg_line_length_pck = 1280 */ + {MISENSOR_16BIT, 0xC814, 0x04E2}, + /* cam_sensor_cfg_fine_correction = 96 */ + {MISENSOR_16BIT, 0xC816, 0x00E0}, + /* cam_sensor_cfg_cpipe_last_row = 541 */ + {MISENSOR_16BIT, 0xC818, 0x01E3}, + {MISENSOR_16BIT, 0xC826, 0x0020}, /* cam_sensor_cfg_reg_0_data = 32 */ + {MISENSOR_16BIT, 0xC834, 0x0330}, /* cam_sensor_control_read_mode = 0 */ + {MISENSOR_16BIT, 0xC854, 0x0000}, /* cam_crop_window_xoffset = 0 */ + {MISENSOR_16BIT, 0xC856, 0x0000}, /* cam_crop_window_yoffset = 0 */ + {MISENSOR_16BIT, 0xC858, 0x0280}, /* cam_crop_window_width = 952 */ + {MISENSOR_16BIT, 0xC85A, 0x01E0}, /* cam_crop_window_height = 538 */ + {MISENSOR_8BIT, 0xC85C, 0x03}, /* cam_crop_cropmode = 3 */ + {MISENSOR_16BIT, 0xC868, 0x0280}, /* cam_output_width = 952 */ + {MISENSOR_16BIT, 0xC86A, 0x01E0}, /* cam_output_height = 538 */ + /* LOAD = Step3-Recommended + * Patch,Errata and Sensor optimization Setting */ + {MISENSOR_16BIT, 0x316A, 0x8270}, /* DAC_TXLO_ROW */ + {MISENSOR_16BIT, 0x316C, 0x8270}, /* DAC_TXLO */ + {MISENSOR_16BIT, 0x3ED0, 0x2305}, /* DAC_LD_4_5 */ + {MISENSOR_16BIT, 0x3ED2, 0x77CF}, /* DAC_LD_6_7 */ + {MISENSOR_16BIT, 0x316E, 0x8202}, /* DAC_ECL */ + {MISENSOR_16BIT, 0x3180, 0x87FF}, /* DELTA_DK_CONTROL */ + {MISENSOR_16BIT, 0x30D4, 0x6080}, /* COLUMN_CORRECTION */ + {MISENSOR_16BIT, 0xA802, 0x0008}, /* AE_TRACK_MODE */ + {MISENSOR_16BIT, 0x3E14, 0xFF39}, /* SAMP_COL_PUP2 */ + {MISENSOR_16BIT, 0x31E0, 0x0003}, /* PIX_DEF_ID */ + /* LOAD = Step8-Features //Ports, special features, etc. */ + {MISENSOR_16BIT, 0x098E, 0x0000}, /* LOGICAL_ADDRESS_ACCESS */ + {MISENSOR_16BIT, 0x001E, 0x0777}, /* PAD_SLEW */ + {MISENSOR_16BIT, 0x098E, 0x0000}, /* LOGICAL_ADDRESS_ACCESS */ + {MISENSOR_16BIT, 0xC984, 0x8001}, /* CAM_PORT_OUTPUT_CONTROL */ + {MISENSOR_16BIT, 0xC988, 0x0F00}, /* CAM_PORT_MIPI_TIMING_T_HS_ZERO */ + /* CAM_PORT_MIPI_TIMING_T_HS_EXIT_HS_TRAIL */ + {MISENSOR_16BIT, 0xC98A, 0x0B07}, + /* CAM_PORT_MIPI_TIMING_T_CLK_POST_CLK_PRE */ + {MISENSOR_16BIT, 0xC98C, 0x0D01}, + /* CAM_PORT_MIPI_TIMING_T_CLK_TRAIL_CLK_ZERO */ + {MISENSOR_16BIT, 0xC98E, 0x071D}, + {MISENSOR_16BIT, 0xC990, 0x0006}, /* CAM_PORT_MIPI_TIMING_T_LPX */ + {MISENSOR_16BIT, 0xC992, 0x0A0C}, /* CAM_PORT_MIPI_TIMING_INIT_TIMING */ + {MISENSOR_16BIT, 0x3C5A, 0x0009}, /* MIPI_DELAY_TRIM */ + {MISENSOR_16BIT, 0xC86C, 0x0210}, /* CAM_OUTPUT_FORMAT */ + {MISENSOR_16BIT, 0xA804, 0x0000}, /* AE_TRACK_ALGO */ + /* default exposure */ + {MISENSOR_16BIT, 0x3012, 0x0110}, /* COMMAND_REGISTER */ + {MISENSOR_TOK_TERM, 0, 0}, + +}; + +static struct misensor_reg const mt9m114_antiflicker_50hz[] = { + {MISENSOR_16BIT, 0x098E, 0xC88B}, + {MISENSOR_8BIT, 0xC88B, 0x32}, + {MISENSOR_8BIT, 0xDC00, 0x28}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_antiflicker_60hz[] = { + {MISENSOR_16BIT, 0x098E, 0xC88B}, + {MISENSOR_8BIT, 0xC88B, 0x3C}, + {MISENSOR_8BIT, 0xDC00, 0x28}, + {MISENSOR_16BIT, 0x0080, 0x8002}, + {MISENSOR_TOK_TERM, 0, 0} +}; + +static struct misensor_reg const mt9m114_iq[] = { + /* [Step3-Recommended] [Sensor optimization] */ + {MISENSOR_16BIT, 0x316A, 0x8270}, + {MISENSOR_16BIT, 0x316C, 0x8270}, + {MISENSOR_16BIT, 0x3ED0, 0x2305}, + {MISENSOR_16BIT, 0x3ED2, 0x77CF}, + {MISENSOR_16BIT, 0x316E, 0x8202}, + {MISENSOR_16BIT, 0x3180, 0x87FF}, + {MISENSOR_16BIT, 0x30D4, 0x6080}, + {MISENSOR_16BIT, 0xA802, 0x0008}, + + /* This register is from vender to avoid low light color noise */ + {MISENSOR_16BIT, 0x31E0, 0x0001}, + + /* LOAD=Errata item 1 */ + {MISENSOR_16BIT, 0x3E14, 0xFF39}, + + /* LOAD=Errata item 2 */ + {MISENSOR_16BIT, 0x301A, 0x8234}, + + /* + * LOAD=Errata item 3 + * LOAD=Patch 0202; + * Feature Recommended; Black level correction fix + */ + {MISENSOR_16BIT, 0x0982, 0x0001}, + {MISENSOR_16BIT, 0x098A, 0x5000}, + {MISENSOR_16BIT, 0xD000, 0x70CF}, + {MISENSOR_16BIT, 0xD002, 0xFFFF}, + {MISENSOR_16BIT, 0xD004, 0xC5D4}, + {MISENSOR_16BIT, 0xD006, 0x903A}, + {MISENSOR_16BIT, 0xD008, 0x2144}, + {MISENSOR_16BIT, 0xD00A, 0x0C00}, + {MISENSOR_16BIT, 0xD00C, 0x2186}, + {MISENSOR_16BIT, 0xD00E, 0x0FF3}, + {MISENSOR_16BIT, 0xD010, 0xB844}, + {MISENSOR_16BIT, 0xD012, 0xB948}, + {MISENSOR_16BIT, 0xD014, 0xE082}, + {MISENSOR_16BIT, 0xD016, 0x20CC}, + {MISENSOR_16BIT, 0xD018, 0x80E2}, + {MISENSOR_16BIT, 0xD01A, 0x21CC}, + {MISENSOR_16BIT, 0xD01C, 0x80A2}, + {MISENSOR_16BIT, 0xD01E, 0x21CC}, + {MISENSOR_16BIT, 0xD020, 0x80E2}, + {MISENSOR_16BIT, 0xD022, 0xF404}, + {MISENSOR_16BIT, 0xD024, 0xD801}, + {MISENSOR_16BIT, 0xD026, 0xF003}, + {MISENSOR_16BIT, 0xD028, 0xD800}, + {MISENSOR_16BIT, 0xD02A, 0x7EE0}, + {MISENSOR_16BIT, 0xD02C, 0xC0F1}, + {MISENSOR_16BIT, 0xD02E, 0x08BA}, + + {MISENSOR_16BIT, 0xD030, 0x0600}, + {MISENSOR_16BIT, 0xD032, 0xC1A1}, + {MISENSOR_16BIT, 0xD034, 0x76CF}, + {MISENSOR_16BIT, 0xD036, 0xFFFF}, + {MISENSOR_16BIT, 0xD038, 0xC130}, + {MISENSOR_16BIT, 0xD03A, 0x6E04}, + {MISENSOR_16BIT, 0xD03C, 0xC040}, + {MISENSOR_16BIT, 0xD03E, 0x71CF}, + {MISENSOR_16BIT, 0xD040, 0xFFFF}, + {MISENSOR_16BIT, 0xD042, 0xC790}, + {MISENSOR_16BIT, 0xD044, 0x8103}, + {MISENSOR_16BIT, 0xD046, 0x77CF}, + {MISENSOR_16BIT, 0xD048, 0xFFFF}, + {MISENSOR_16BIT, 0xD04A, 0xC7C0}, + {MISENSOR_16BIT, 0xD04C, 0xE001}, + {MISENSOR_16BIT, 0xD04E, 0xA103}, + {MISENSOR_16BIT, 0xD050, 0xD800}, + {MISENSOR_16BIT, 0xD052, 0x0C6A}, + {MISENSOR_16BIT, 0xD054, 0x04E0}, + {MISENSOR_16BIT, 0xD056, 0xB89E}, + {MISENSOR_16BIT, 0xD058, 0x7508}, + {MISENSOR_16BIT, 0xD05A, 0x8E1C}, + {MISENSOR_16BIT, 0xD05C, 0x0809}, + {MISENSOR_16BIT, 0xD05E, 0x0191}, + + {MISENSOR_16BIT, 0xD060, 0xD801}, + {MISENSOR_16BIT, 0xD062, 0xAE1D}, + {MISENSOR_16BIT, 0xD064, 0xE580}, + {MISENSOR_16BIT, 0xD066, 0x20CA}, + {MISENSOR_16BIT, 0xD068, 0x0022}, + {MISENSOR_16BIT, 0xD06A, 0x20CF}, + {MISENSOR_16BIT, 0xD06C, 0x0522}, + {MISENSOR_16BIT, 0xD06E, 0x0C5C}, + {MISENSOR_16BIT, 0xD070, 0x04E2}, + {MISENSOR_16BIT, 0xD072, 0x21CA}, + {MISENSOR_16BIT, 0xD074, 0x0062}, + {MISENSOR_16BIT, 0xD076, 0xE580}, + {MISENSOR_16BIT, 0xD078, 0xD901}, + {MISENSOR_16BIT, 0xD07A, 0x79C0}, + {MISENSOR_16BIT, 0xD07C, 0xD800}, + {MISENSOR_16BIT, 0xD07E, 0x0BE6}, + {MISENSOR_16BIT, 0xD080, 0x04E0}, + {MISENSOR_16BIT, 0xD082, 0xB89E}, + {MISENSOR_16BIT, 0xD084, 0x70CF}, + {MISENSOR_16BIT, 0xD086, 0xFFFF}, + {MISENSOR_16BIT, 0xD088, 0xC8D4}, + {MISENSOR_16BIT, 0xD08A, 0x9002}, + {MISENSOR_16BIT, 0xD08C, 0x0857}, + {MISENSOR_16BIT, 0xD08E, 0x025E}, + + {MISENSOR_16BIT, 0xD090, 0xFFDC}, + {MISENSOR_16BIT, 0xD092, 0xE080}, + {MISENSOR_16BIT, 0xD094, 0x25CC}, + {MISENSOR_16BIT, 0xD096, 0x9022}, + {MISENSOR_16BIT, 0xD098, 0xF225}, + {MISENSOR_16BIT, 0xD09A, 0x1700}, + {MISENSOR_16BIT, 0xD09C, 0x108A}, + {MISENSOR_16BIT, 0xD09E, 0x73CF}, + {MISENSOR_16BIT, 0xD0A0, 0xFF00}, + {MISENSOR_16BIT, 0xD0A2, 0x3174}, + {MISENSOR_16BIT, 0xD0A4, 0x9307}, + {MISENSOR_16BIT, 0xD0A6, 0x2A04}, + {MISENSOR_16BIT, 0xD0A8, 0x103E}, + {MISENSOR_16BIT, 0xD0AA, 0x9328}, + {MISENSOR_16BIT, 0xD0AC, 0x2942}, + {MISENSOR_16BIT, 0xD0AE, 0x7140}, + {MISENSOR_16BIT, 0xD0B0, 0x2A04}, + {MISENSOR_16BIT, 0xD0B2, 0x107E}, + {MISENSOR_16BIT, 0xD0B4, 0x9349}, + {MISENSOR_16BIT, 0xD0B6, 0x2942}, + {MISENSOR_16BIT, 0xD0B8, 0x7141}, + {MISENSOR_16BIT, 0xD0BA, 0x2A04}, + {MISENSOR_16BIT, 0xD0BC, 0x10BE}, + {MISENSOR_16BIT, 0xD0BE, 0x934A}, + + {MISENSOR_16BIT, 0xD0C0, 0x2942}, + {MISENSOR_16BIT, 0xD0C2, 0x714B}, + {MISENSOR_16BIT, 0xD0C4, 0x2A04}, + {MISENSOR_16BIT, 0xD0C6, 0x10BE}, + {MISENSOR_16BIT, 0xD0C8, 0x130C}, + {MISENSOR_16BIT, 0xD0CA, 0x010A}, + {MISENSOR_16BIT, 0xD0CC, 0x2942}, + {MISENSOR_16BIT, 0xD0CE, 0x7142}, + {MISENSOR_16BIT, 0xD0D0, 0x2250}, + {MISENSOR_16BIT, 0xD0D2, 0x13CA}, + {MISENSOR_16BIT, 0xD0D4, 0x1B0C}, + {MISENSOR_16BIT, 0xD0D6, 0x0284}, + {MISENSOR_16BIT, 0xD0D8, 0xB307}, + {MISENSOR_16BIT, 0xD0DA, 0xB328}, + {MISENSOR_16BIT, 0xD0DC, 0x1B12}, + {MISENSOR_16BIT, 0xD0DE, 0x02C4}, + {MISENSOR_16BIT, 0xD0E0, 0xB34A}, + {MISENSOR_16BIT, 0xD0E2, 0xED88}, + {MISENSOR_16BIT, 0xD0E4, 0x71CF}, + {MISENSOR_16BIT, 0xD0E6, 0xFF00}, + {MISENSOR_16BIT, 0xD0E8, 0x3174}, + {MISENSOR_16BIT, 0xD0EA, 0x9106}, + {MISENSOR_16BIT, 0xD0EC, 0xB88F}, + {MISENSOR_16BIT, 0xD0EE, 0xB106}, + + {MISENSOR_16BIT, 0xD0F0, 0x210A}, + {MISENSOR_16BIT, 0xD0F2, 0x8340}, + {MISENSOR_16BIT, 0xD0F4, 0xC000}, + {MISENSOR_16BIT, 0xD0F6, 0x21CA}, + {MISENSOR_16BIT, 0xD0F8, 0x0062}, + {MISENSOR_16BIT, 0xD0FA, 0x20F0}, + {MISENSOR_16BIT, 0xD0FC, 0x0040}, + {MISENSOR_16BIT, 0xD0FE, 0x0B02}, + {MISENSOR_16BIT, 0xD100, 0x0320}, + {MISENSOR_16BIT, 0xD102, 0xD901}, + {MISENSOR_16BIT, 0xD104, 0x07F1}, + {MISENSOR_16BIT, 0xD106, 0x05E0}, + {MISENSOR_16BIT, 0xD108, 0xC0A1}, + {MISENSOR_16BIT, 0xD10A, 0x78E0}, + {MISENSOR_16BIT, 0xD10C, 0xC0F1}, + {MISENSOR_16BIT, 0xD10E, 0x71CF}, + {MISENSOR_16BIT, 0xD110, 0xFFFF}, + {MISENSOR_16BIT, 0xD112, 0xC7C0}, + {MISENSOR_16BIT, 0xD114, 0xD840}, + {MISENSOR_16BIT, 0xD116, 0xA900}, + {MISENSOR_16BIT, 0xD118, 0x71CF}, + {MISENSOR_16BIT, 0xD11A, 0xFFFF}, + {MISENSOR_16BIT, 0xD11C, 0xD02C}, + {MISENSOR_16BIT, 0xD11E, 0xD81E}, + + {MISENSOR_16BIT, 0xD120, 0x0A5A}, + {MISENSOR_16BIT, 0xD122, 0x04E0}, + {MISENSOR_16BIT, 0xD124, 0xDA00}, + {MISENSOR_16BIT, 0xD126, 0xD800}, + {MISENSOR_16BIT, 0xD128, 0xC0D1}, + {MISENSOR_16BIT, 0xD12A, 0x7EE0}, + + {MISENSOR_16BIT, 0x098E, 0x0000}, + {MISENSOR_16BIT, 0xE000, 0x010C}, + {MISENSOR_16BIT, 0xE002, 0x0202}, + {MISENSOR_16BIT, 0xE004, 0x4103}, + {MISENSOR_16BIT, 0xE006, 0x0202}, + {MISENSOR_16BIT, 0x0080, 0xFFF0}, + {MISENSOR_16BIT, 0x0080, 0xFFF1}, + + /* LOAD=Patch 0302; Feature Recommended; Adaptive Sensitivity */ + {MISENSOR_16BIT, 0x0982, 0x0001}, + {MISENSOR_16BIT, 0x098A, 0x512C}, + {MISENSOR_16BIT, 0xD12C, 0x70CF}, + {MISENSOR_16BIT, 0xD12E, 0xFFFF}, + {MISENSOR_16BIT, 0xD130, 0xC5D4}, + {MISENSOR_16BIT, 0xD132, 0x903A}, + {MISENSOR_16BIT, 0xD134, 0x2144}, + {MISENSOR_16BIT, 0xD136, 0x0C00}, + {MISENSOR_16BIT, 0xD138, 0x2186}, + {MISENSOR_16BIT, 0xD13A, 0x0FF3}, + {MISENSOR_16BIT, 0xD13C, 0xB844}, + {MISENSOR_16BIT, 0xD13E, 0x262F}, + {MISENSOR_16BIT, 0xD140, 0xF008}, + {MISENSOR_16BIT, 0xD142, 0xB948}, + {MISENSOR_16BIT, 0xD144, 0x21CC}, + {MISENSOR_16BIT, 0xD146, 0x8021}, + {MISENSOR_16BIT, 0xD148, 0xD801}, + {MISENSOR_16BIT, 0xD14A, 0xF203}, + {MISENSOR_16BIT, 0xD14C, 0xD800}, + {MISENSOR_16BIT, 0xD14E, 0x7EE0}, + {MISENSOR_16BIT, 0xD150, 0xC0F1}, + {MISENSOR_16BIT, 0xD152, 0x71CF}, + {MISENSOR_16BIT, 0xD154, 0xFFFF}, + {MISENSOR_16BIT, 0xD156, 0xC610}, + {MISENSOR_16BIT, 0xD158, 0x910E}, + {MISENSOR_16BIT, 0xD15A, 0x208C}, + {MISENSOR_16BIT, 0xD15C, 0x8014}, + {MISENSOR_16BIT, 0xD15E, 0xF418}, + {MISENSOR_16BIT, 0xD160, 0x910F}, + {MISENSOR_16BIT, 0xD162, 0x208C}, + {MISENSOR_16BIT, 0xD164, 0x800F}, + {MISENSOR_16BIT, 0xD166, 0xF414}, + {MISENSOR_16BIT, 0xD168, 0x9116}, + {MISENSOR_16BIT, 0xD16A, 0x208C}, + {MISENSOR_16BIT, 0xD16C, 0x800A}, + {MISENSOR_16BIT, 0xD16E, 0xF410}, + {MISENSOR_16BIT, 0xD170, 0x9117}, + {MISENSOR_16BIT, 0xD172, 0x208C}, + {MISENSOR_16BIT, 0xD174, 0x8807}, + {MISENSOR_16BIT, 0xD176, 0xF40C}, + {MISENSOR_16BIT, 0xD178, 0x9118}, + {MISENSOR_16BIT, 0xD17A, 0x2086}, + {MISENSOR_16BIT, 0xD17C, 0x0FF3}, + {MISENSOR_16BIT, 0xD17E, 0xB848}, + {MISENSOR_16BIT, 0xD180, 0x080D}, + {MISENSOR_16BIT, 0xD182, 0x0090}, + {MISENSOR_16BIT, 0xD184, 0xFFEA}, + {MISENSOR_16BIT, 0xD186, 0xE081}, + {MISENSOR_16BIT, 0xD188, 0xD801}, + {MISENSOR_16BIT, 0xD18A, 0xF203}, + {MISENSOR_16BIT, 0xD18C, 0xD800}, + {MISENSOR_16BIT, 0xD18E, 0xC0D1}, + {MISENSOR_16BIT, 0xD190, 0x7EE0}, + {MISENSOR_16BIT, 0xD192, 0x78E0}, + {MISENSOR_16BIT, 0xD194, 0xC0F1}, + {MISENSOR_16BIT, 0xD196, 0x71CF}, + {MISENSOR_16BIT, 0xD198, 0xFFFF}, + {MISENSOR_16BIT, 0xD19A, 0xC610}, + {MISENSOR_16BIT, 0xD19C, 0x910E}, + {MISENSOR_16BIT, 0xD19E, 0x208C}, + {MISENSOR_16BIT, 0xD1A0, 0x800A}, + {MISENSOR_16BIT, 0xD1A2, 0xF418}, + {MISENSOR_16BIT, 0xD1A4, 0x910F}, + {MISENSOR_16BIT, 0xD1A6, 0x208C}, + {MISENSOR_16BIT, 0xD1A8, 0x8807}, + {MISENSOR_16BIT, 0xD1AA, 0xF414}, + {MISENSOR_16BIT, 0xD1AC, 0x9116}, + {MISENSOR_16BIT, 0xD1AE, 0x208C}, + {MISENSOR_16BIT, 0xD1B0, 0x800A}, + {MISENSOR_16BIT, 0xD1B2, 0xF410}, + {MISENSOR_16BIT, 0xD1B4, 0x9117}, + {MISENSOR_16BIT, 0xD1B6, 0x208C}, + {MISENSOR_16BIT, 0xD1B8, 0x8807}, + {MISENSOR_16BIT, 0xD1BA, 0xF40C}, + {MISENSOR_16BIT, 0xD1BC, 0x9118}, + {MISENSOR_16BIT, 0xD1BE, 0x2086}, + {MISENSOR_16BIT, 0xD1C0, 0x0FF3}, + {MISENSOR_16BIT, 0xD1C2, 0xB848}, + {MISENSOR_16BIT, 0xD1C4, 0x080D}, + {MISENSOR_16BIT, 0xD1C6, 0x0090}, + {MISENSOR_16BIT, 0xD1C8, 0xFFD9}, + {MISENSOR_16BIT, 0xD1CA, 0xE080}, + {MISENSOR_16BIT, 0xD1CC, 0xD801}, + {MISENSOR_16BIT, 0xD1CE, 0xF203}, + {MISENSOR_16BIT, 0xD1D0, 0xD800}, + {MISENSOR_16BIT, 0xD1D2, 0xF1DF}, + {MISENSOR_16BIT, 0xD1D4, 0x9040}, + {MISENSOR_16BIT, 0xD1D6, 0x71CF}, + {MISENSOR_16BIT, 0xD1D8, 0xFFFF}, + {MISENSOR_16BIT, 0xD1DA, 0xC5D4}, + {MISENSOR_16BIT, 0xD1DC, 0xB15A}, + {MISENSOR_16BIT, 0xD1DE, 0x9041}, + {MISENSOR_16BIT, 0xD1E0, 0x73CF}, + {MISENSOR_16BIT, 0xD1E2, 0xFFFF}, + {MISENSOR_16BIT, 0xD1E4, 0xC7D0}, + {MISENSOR_16BIT, 0xD1E6, 0xB140}, + {MISENSOR_16BIT, 0xD1E8, 0x9042}, + {MISENSOR_16BIT, 0xD1EA, 0xB141}, + {MISENSOR_16BIT, 0xD1EC, 0x9043}, + {MISENSOR_16BIT, 0xD1EE, 0xB142}, + {MISENSOR_16BIT, 0xD1F0, 0x9044}, + {MISENSOR_16BIT, 0xD1F2, 0xB143}, + {MISENSOR_16BIT, 0xD1F4, 0x9045}, + {MISENSOR_16BIT, 0xD1F6, 0xB147}, + {MISENSOR_16BIT, 0xD1F8, 0x9046}, + {MISENSOR_16BIT, 0xD1FA, 0xB148}, + {MISENSOR_16BIT, 0xD1FC, 0x9047}, + {MISENSOR_16BIT, 0xD1FE, 0xB14B}, + {MISENSOR_16BIT, 0xD200, 0x9048}, + {MISENSOR_16BIT, 0xD202, 0xB14C}, + {MISENSOR_16BIT, 0xD204, 0x9049}, + {MISENSOR_16BIT, 0xD206, 0x1958}, + {MISENSOR_16BIT, 0xD208, 0x0084}, + {MISENSOR_16BIT, 0xD20A, 0x904A}, + {MISENSOR_16BIT, 0xD20C, 0x195A}, + {MISENSOR_16BIT, 0xD20E, 0x0084}, + {MISENSOR_16BIT, 0xD210, 0x8856}, + {MISENSOR_16BIT, 0xD212, 0x1B36}, + {MISENSOR_16BIT, 0xD214, 0x8082}, + {MISENSOR_16BIT, 0xD216, 0x8857}, + {MISENSOR_16BIT, 0xD218, 0x1B37}, + {MISENSOR_16BIT, 0xD21A, 0x8082}, + {MISENSOR_16BIT, 0xD21C, 0x904C}, + {MISENSOR_16BIT, 0xD21E, 0x19A7}, + {MISENSOR_16BIT, 0xD220, 0x009C}, + {MISENSOR_16BIT, 0xD222, 0x881A}, + {MISENSOR_16BIT, 0xD224, 0x7FE0}, + {MISENSOR_16BIT, 0xD226, 0x1B54}, + {MISENSOR_16BIT, 0xD228, 0x8002}, + {MISENSOR_16BIT, 0xD22A, 0x78E0}, + {MISENSOR_16BIT, 0xD22C, 0x71CF}, + {MISENSOR_16BIT, 0xD22E, 0xFFFF}, + {MISENSOR_16BIT, 0xD230, 0xC350}, + {MISENSOR_16BIT, 0xD232, 0xD828}, + {MISENSOR_16BIT, 0xD234, 0xA90B}, + {MISENSOR_16BIT, 0xD236, 0x8100}, + {MISENSOR_16BIT, 0xD238, 0x01C5}, + {MISENSOR_16BIT, 0xD23A, 0x0320}, + {MISENSOR_16BIT, 0xD23C, 0xD900}, + {MISENSOR_16BIT, 0xD23E, 0x78E0}, + {MISENSOR_16BIT, 0xD240, 0x220A}, + {MISENSOR_16BIT, 0xD242, 0x1F80}, + {MISENSOR_16BIT, 0xD244, 0xFFFF}, + {MISENSOR_16BIT, 0xD246, 0xD4E0}, + {MISENSOR_16BIT, 0xD248, 0xC0F1}, + {MISENSOR_16BIT, 0xD24A, 0x0811}, + {MISENSOR_16BIT, 0xD24C, 0x0051}, + {MISENSOR_16BIT, 0xD24E, 0x2240}, + {MISENSOR_16BIT, 0xD250, 0x1200}, + {MISENSOR_16BIT, 0xD252, 0xFFE1}, + {MISENSOR_16BIT, 0xD254, 0xD801}, + {MISENSOR_16BIT, 0xD256, 0xF006}, + {MISENSOR_16BIT, 0xD258, 0x2240}, + {MISENSOR_16BIT, 0xD25A, 0x1900}, + {MISENSOR_16BIT, 0xD25C, 0xFFDE}, + {MISENSOR_16BIT, 0xD25E, 0xD802}, + {MISENSOR_16BIT, 0xD260, 0x1A05}, + {MISENSOR_16BIT, 0xD262, 0x1002}, + {MISENSOR_16BIT, 0xD264, 0xFFF2}, + {MISENSOR_16BIT, 0xD266, 0xF195}, + {MISENSOR_16BIT, 0xD268, 0xC0F1}, + {MISENSOR_16BIT, 0xD26A, 0x0E7E}, + {MISENSOR_16BIT, 0xD26C, 0x05C0}, + {MISENSOR_16BIT, 0xD26E, 0x75CF}, + {MISENSOR_16BIT, 0xD270, 0xFFFF}, + {MISENSOR_16BIT, 0xD272, 0xC84C}, + {MISENSOR_16BIT, 0xD274, 0x9502}, + {MISENSOR_16BIT, 0xD276, 0x77CF}, + {MISENSOR_16BIT, 0xD278, 0xFFFF}, + {MISENSOR_16BIT, 0xD27A, 0xC344}, + {MISENSOR_16BIT, 0xD27C, 0x2044}, + {MISENSOR_16BIT, 0xD27E, 0x008E}, + {MISENSOR_16BIT, 0xD280, 0xB8A1}, + {MISENSOR_16BIT, 0xD282, 0x0926}, + {MISENSOR_16BIT, 0xD284, 0x03E0}, + {MISENSOR_16BIT, 0xD286, 0xB502}, + {MISENSOR_16BIT, 0xD288, 0x9502}, + {MISENSOR_16BIT, 0xD28A, 0x952E}, + {MISENSOR_16BIT, 0xD28C, 0x7E05}, + {MISENSOR_16BIT, 0xD28E, 0xB5C2}, + {MISENSOR_16BIT, 0xD290, 0x70CF}, + {MISENSOR_16BIT, 0xD292, 0xFFFF}, + {MISENSOR_16BIT, 0xD294, 0xC610}, + {MISENSOR_16BIT, 0xD296, 0x099A}, + {MISENSOR_16BIT, 0xD298, 0x04A0}, + {MISENSOR_16BIT, 0xD29A, 0xB026}, + {MISENSOR_16BIT, 0xD29C, 0x0E02}, + {MISENSOR_16BIT, 0xD29E, 0x0560}, + {MISENSOR_16BIT, 0xD2A0, 0xDE00}, + {MISENSOR_16BIT, 0xD2A2, 0x0A12}, + {MISENSOR_16BIT, 0xD2A4, 0x0320}, + {MISENSOR_16BIT, 0xD2A6, 0xB7C4}, + {MISENSOR_16BIT, 0xD2A8, 0x0B36}, + {MISENSOR_16BIT, 0xD2AA, 0x03A0}, + {MISENSOR_16BIT, 0xD2AC, 0x70C9}, + {MISENSOR_16BIT, 0xD2AE, 0x9502}, + {MISENSOR_16BIT, 0xD2B0, 0x7608}, + {MISENSOR_16BIT, 0xD2B2, 0xB8A8}, + {MISENSOR_16BIT, 0xD2B4, 0xB502}, + {MISENSOR_16BIT, 0xD2B6, 0x70CF}, + {MISENSOR_16BIT, 0xD2B8, 0x0000}, + {MISENSOR_16BIT, 0xD2BA, 0x5536}, + {MISENSOR_16BIT, 0xD2BC, 0x7860}, + {MISENSOR_16BIT, 0xD2BE, 0x2686}, + {MISENSOR_16BIT, 0xD2C0, 0x1FFB}, + {MISENSOR_16BIT, 0xD2C2, 0x9502}, + {MISENSOR_16BIT, 0xD2C4, 0x78C5}, + {MISENSOR_16BIT, 0xD2C6, 0x0631}, + {MISENSOR_16BIT, 0xD2C8, 0x05E0}, + {MISENSOR_16BIT, 0xD2CA, 0xB502}, + {MISENSOR_16BIT, 0xD2CC, 0x72CF}, + {MISENSOR_16BIT, 0xD2CE, 0xFFFF}, + {MISENSOR_16BIT, 0xD2D0, 0xC5D4}, + {MISENSOR_16BIT, 0xD2D2, 0x923A}, + {MISENSOR_16BIT, 0xD2D4, 0x73CF}, + {MISENSOR_16BIT, 0xD2D6, 0xFFFF}, + {MISENSOR_16BIT, 0xD2D8, 0xC7D0}, + {MISENSOR_16BIT, 0xD2DA, 0xB020}, + {MISENSOR_16BIT, 0xD2DC, 0x9220}, + {MISENSOR_16BIT, 0xD2DE, 0xB021}, + {MISENSOR_16BIT, 0xD2E0, 0x9221}, + {MISENSOR_16BIT, 0xD2E2, 0xB022}, + {MISENSOR_16BIT, 0xD2E4, 0x9222}, + {MISENSOR_16BIT, 0xD2E6, 0xB023}, + {MISENSOR_16BIT, 0xD2E8, 0x9223}, + {MISENSOR_16BIT, 0xD2EA, 0xB024}, + {MISENSOR_16BIT, 0xD2EC, 0x9227}, + {MISENSOR_16BIT, 0xD2EE, 0xB025}, + {MISENSOR_16BIT, 0xD2F0, 0x9228}, + {MISENSOR_16BIT, 0xD2F2, 0xB026}, + {MISENSOR_16BIT, 0xD2F4, 0x922B}, + {MISENSOR_16BIT, 0xD2F6, 0xB027}, + {MISENSOR_16BIT, 0xD2F8, 0x922C}, + {MISENSOR_16BIT, 0xD2FA, 0xB028}, + {MISENSOR_16BIT, 0xD2FC, 0x1258}, + {MISENSOR_16BIT, 0xD2FE, 0x0101}, + {MISENSOR_16BIT, 0xD300, 0xB029}, + {MISENSOR_16BIT, 0xD302, 0x125A}, + {MISENSOR_16BIT, 0xD304, 0x0101}, + {MISENSOR_16BIT, 0xD306, 0xB02A}, + {MISENSOR_16BIT, 0xD308, 0x1336}, + {MISENSOR_16BIT, 0xD30A, 0x8081}, + {MISENSOR_16BIT, 0xD30C, 0xA836}, + {MISENSOR_16BIT, 0xD30E, 0x1337}, + {MISENSOR_16BIT, 0xD310, 0x8081}, + {MISENSOR_16BIT, 0xD312, 0xA837}, + {MISENSOR_16BIT, 0xD314, 0x12A7}, + {MISENSOR_16BIT, 0xD316, 0x0701}, + {MISENSOR_16BIT, 0xD318, 0xB02C}, + {MISENSOR_16BIT, 0xD31A, 0x1354}, + {MISENSOR_16BIT, 0xD31C, 0x8081}, + {MISENSOR_16BIT, 0xD31E, 0x7FE0}, + {MISENSOR_16BIT, 0xD320, 0xA83A}, + {MISENSOR_16BIT, 0xD322, 0x78E0}, + {MISENSOR_16BIT, 0xD324, 0xC0F1}, + {MISENSOR_16BIT, 0xD326, 0x0DC2}, + {MISENSOR_16BIT, 0xD328, 0x05C0}, + {MISENSOR_16BIT, 0xD32A, 0x7608}, + {MISENSOR_16BIT, 0xD32C, 0x09BB}, + {MISENSOR_16BIT, 0xD32E, 0x0010}, + {MISENSOR_16BIT, 0xD330, 0x75CF}, + {MISENSOR_16BIT, 0xD332, 0xFFFF}, + {MISENSOR_16BIT, 0xD334, 0xD4E0}, + {MISENSOR_16BIT, 0xD336, 0x8D21}, + {MISENSOR_16BIT, 0xD338, 0x8D00}, + {MISENSOR_16BIT, 0xD33A, 0x2153}, + {MISENSOR_16BIT, 0xD33C, 0x0003}, + {MISENSOR_16BIT, 0xD33E, 0xB8C0}, + {MISENSOR_16BIT, 0xD340, 0x8D45}, + {MISENSOR_16BIT, 0xD342, 0x0B23}, + {MISENSOR_16BIT, 0xD344, 0x0000}, + {MISENSOR_16BIT, 0xD346, 0xEA8F}, + {MISENSOR_16BIT, 0xD348, 0x0915}, + {MISENSOR_16BIT, 0xD34A, 0x001E}, + {MISENSOR_16BIT, 0xD34C, 0xFF81}, + {MISENSOR_16BIT, 0xD34E, 0xE808}, + {MISENSOR_16BIT, 0xD350, 0x2540}, + {MISENSOR_16BIT, 0xD352, 0x1900}, + {MISENSOR_16BIT, 0xD354, 0xFFDE}, + {MISENSOR_16BIT, 0xD356, 0x8D00}, + {MISENSOR_16BIT, 0xD358, 0xB880}, + {MISENSOR_16BIT, 0xD35A, 0xF004}, + {MISENSOR_16BIT, 0xD35C, 0x8D00}, + {MISENSOR_16BIT, 0xD35E, 0xB8A0}, + {MISENSOR_16BIT, 0xD360, 0xAD00}, + {MISENSOR_16BIT, 0xD362, 0x8D05}, + {MISENSOR_16BIT, 0xD364, 0xE081}, + {MISENSOR_16BIT, 0xD366, 0x20CC}, + {MISENSOR_16BIT, 0xD368, 0x80A2}, + {MISENSOR_16BIT, 0xD36A, 0xDF00}, + {MISENSOR_16BIT, 0xD36C, 0xF40A}, + {MISENSOR_16BIT, 0xD36E, 0x71CF}, + {MISENSOR_16BIT, 0xD370, 0xFFFF}, + {MISENSOR_16BIT, 0xD372, 0xC84C}, + {MISENSOR_16BIT, 0xD374, 0x9102}, + {MISENSOR_16BIT, 0xD376, 0x7708}, + {MISENSOR_16BIT, 0xD378, 0xB8A6}, + {MISENSOR_16BIT, 0xD37A, 0x2786}, + {MISENSOR_16BIT, 0xD37C, 0x1FFE}, + {MISENSOR_16BIT, 0xD37E, 0xB102}, + {MISENSOR_16BIT, 0xD380, 0x0B42}, + {MISENSOR_16BIT, 0xD382, 0x0180}, + {MISENSOR_16BIT, 0xD384, 0x0E3E}, + {MISENSOR_16BIT, 0xD386, 0x0180}, + {MISENSOR_16BIT, 0xD388, 0x0F4A}, + {MISENSOR_16BIT, 0xD38A, 0x0160}, + {MISENSOR_16BIT, 0xD38C, 0x70C9}, + {MISENSOR_16BIT, 0xD38E, 0x8D05}, + {MISENSOR_16BIT, 0xD390, 0xE081}, + {MISENSOR_16BIT, 0xD392, 0x20CC}, + {MISENSOR_16BIT, 0xD394, 0x80A2}, + {MISENSOR_16BIT, 0xD396, 0xF429}, + {MISENSOR_16BIT, 0xD398, 0x76CF}, + {MISENSOR_16BIT, 0xD39A, 0xFFFF}, + {MISENSOR_16BIT, 0xD39C, 0xC84C}, + {MISENSOR_16BIT, 0xD39E, 0x082D}, + {MISENSOR_16BIT, 0xD3A0, 0x0051}, + {MISENSOR_16BIT, 0xD3A2, 0x70CF}, + {MISENSOR_16BIT, 0xD3A4, 0xFFFF}, + {MISENSOR_16BIT, 0xD3A6, 0xC90C}, + {MISENSOR_16BIT, 0xD3A8, 0x8805}, + {MISENSOR_16BIT, 0xD3AA, 0x09B6}, + {MISENSOR_16BIT, 0xD3AC, 0x0360}, + {MISENSOR_16BIT, 0xD3AE, 0xD908}, + {MISENSOR_16BIT, 0xD3B0, 0x2099}, + {MISENSOR_16BIT, 0xD3B2, 0x0802}, + {MISENSOR_16BIT, 0xD3B4, 0x9634}, + {MISENSOR_16BIT, 0xD3B6, 0xB503}, + {MISENSOR_16BIT, 0xD3B8, 0x7902}, + {MISENSOR_16BIT, 0xD3BA, 0x1523}, + {MISENSOR_16BIT, 0xD3BC, 0x1080}, + {MISENSOR_16BIT, 0xD3BE, 0xB634}, + {MISENSOR_16BIT, 0xD3C0, 0xE001}, + {MISENSOR_16BIT, 0xD3C2, 0x1D23}, + {MISENSOR_16BIT, 0xD3C4, 0x1002}, + {MISENSOR_16BIT, 0xD3C6, 0xF00B}, + {MISENSOR_16BIT, 0xD3C8, 0x9634}, + {MISENSOR_16BIT, 0xD3CA, 0x9503}, + {MISENSOR_16BIT, 0xD3CC, 0x6038}, + {MISENSOR_16BIT, 0xD3CE, 0xB614}, + {MISENSOR_16BIT, 0xD3D0, 0x153F}, + {MISENSOR_16BIT, 0xD3D2, 0x1080}, + {MISENSOR_16BIT, 0xD3D4, 0xE001}, + {MISENSOR_16BIT, 0xD3D6, 0x1D3F}, + {MISENSOR_16BIT, 0xD3D8, 0x1002}, + {MISENSOR_16BIT, 0xD3DA, 0xFFA4}, + {MISENSOR_16BIT, 0xD3DC, 0x9602}, + {MISENSOR_16BIT, 0xD3DE, 0x7F05}, + {MISENSOR_16BIT, 0xD3E0, 0xD800}, + {MISENSOR_16BIT, 0xD3E2, 0xB6E2}, + {MISENSOR_16BIT, 0xD3E4, 0xAD05}, + {MISENSOR_16BIT, 0xD3E6, 0x0511}, + {MISENSOR_16BIT, 0xD3E8, 0x05E0}, + {MISENSOR_16BIT, 0xD3EA, 0xD800}, + {MISENSOR_16BIT, 0xD3EC, 0xC0F1}, + {MISENSOR_16BIT, 0xD3EE, 0x0CFE}, + {MISENSOR_16BIT, 0xD3F0, 0x05C0}, + {MISENSOR_16BIT, 0xD3F2, 0x0A96}, + {MISENSOR_16BIT, 0xD3F4, 0x05A0}, + {MISENSOR_16BIT, 0xD3F6, 0x7608}, + {MISENSOR_16BIT, 0xD3F8, 0x0C22}, + {MISENSOR_16BIT, 0xD3FA, 0x0240}, + {MISENSOR_16BIT, 0xD3FC, 0xE080}, + {MISENSOR_16BIT, 0xD3FE, 0x20CA}, + {MISENSOR_16BIT, 0xD400, 0x0F82}, + {MISENSOR_16BIT, 0xD402, 0x0000}, + {MISENSOR_16BIT, 0xD404, 0x190B}, + {MISENSOR_16BIT, 0xD406, 0x0C60}, + {MISENSOR_16BIT, 0xD408, 0x05A2}, + {MISENSOR_16BIT, 0xD40A, 0x21CA}, + {MISENSOR_16BIT, 0xD40C, 0x0022}, + {MISENSOR_16BIT, 0xD40E, 0x0C56}, + {MISENSOR_16BIT, 0xD410, 0x0240}, + {MISENSOR_16BIT, 0xD412, 0xE806}, + {MISENSOR_16BIT, 0xD414, 0x0E0E}, + {MISENSOR_16BIT, 0xD416, 0x0220}, + {MISENSOR_16BIT, 0xD418, 0x70C9}, + {MISENSOR_16BIT, 0xD41A, 0xF048}, + {MISENSOR_16BIT, 0xD41C, 0x0896}, + {MISENSOR_16BIT, 0xD41E, 0x0440}, + {MISENSOR_16BIT, 0xD420, 0x0E96}, + {MISENSOR_16BIT, 0xD422, 0x0400}, + {MISENSOR_16BIT, 0xD424, 0x0966}, + {MISENSOR_16BIT, 0xD426, 0x0380}, + {MISENSOR_16BIT, 0xD428, 0x75CF}, + {MISENSOR_16BIT, 0xD42A, 0xFFFF}, + {MISENSOR_16BIT, 0xD42C, 0xD4E0}, + {MISENSOR_16BIT, 0xD42E, 0x8D00}, + {MISENSOR_16BIT, 0xD430, 0x084D}, + {MISENSOR_16BIT, 0xD432, 0x001E}, + {MISENSOR_16BIT, 0xD434, 0xFF47}, + {MISENSOR_16BIT, 0xD436, 0x080D}, + {MISENSOR_16BIT, 0xD438, 0x0050}, + {MISENSOR_16BIT, 0xD43A, 0xFF57}, + {MISENSOR_16BIT, 0xD43C, 0x0841}, + {MISENSOR_16BIT, 0xD43E, 0x0051}, + {MISENSOR_16BIT, 0xD440, 0x8D04}, + {MISENSOR_16BIT, 0xD442, 0x9521}, + {MISENSOR_16BIT, 0xD444, 0xE064}, + {MISENSOR_16BIT, 0xD446, 0x790C}, + {MISENSOR_16BIT, 0xD448, 0x702F}, + {MISENSOR_16BIT, 0xD44A, 0x0CE2}, + {MISENSOR_16BIT, 0xD44C, 0x05E0}, + {MISENSOR_16BIT, 0xD44E, 0xD964}, + {MISENSOR_16BIT, 0xD450, 0x72CF}, + {MISENSOR_16BIT, 0xD452, 0xFFFF}, + {MISENSOR_16BIT, 0xD454, 0xC700}, + {MISENSOR_16BIT, 0xD456, 0x9235}, + {MISENSOR_16BIT, 0xD458, 0x0811}, + {MISENSOR_16BIT, 0xD45A, 0x0043}, + {MISENSOR_16BIT, 0xD45C, 0xFF3D}, + {MISENSOR_16BIT, 0xD45E, 0x080D}, + {MISENSOR_16BIT, 0xD460, 0x0051}, + {MISENSOR_16BIT, 0xD462, 0xD801}, + {MISENSOR_16BIT, 0xD464, 0xFF77}, + {MISENSOR_16BIT, 0xD466, 0xF025}, + {MISENSOR_16BIT, 0xD468, 0x9501}, + {MISENSOR_16BIT, 0xD46A, 0x9235}, + {MISENSOR_16BIT, 0xD46C, 0x0911}, + {MISENSOR_16BIT, 0xD46E, 0x0003}, + {MISENSOR_16BIT, 0xD470, 0xFF49}, + {MISENSOR_16BIT, 0xD472, 0x080D}, + {MISENSOR_16BIT, 0xD474, 0x0051}, + {MISENSOR_16BIT, 0xD476, 0xD800}, + {MISENSOR_16BIT, 0xD478, 0xFF72}, + {MISENSOR_16BIT, 0xD47A, 0xF01B}, + {MISENSOR_16BIT, 0xD47C, 0x0886}, + {MISENSOR_16BIT, 0xD47E, 0x03E0}, + {MISENSOR_16BIT, 0xD480, 0xD801}, + {MISENSOR_16BIT, 0xD482, 0x0EF6}, + {MISENSOR_16BIT, 0xD484, 0x03C0}, + {MISENSOR_16BIT, 0xD486, 0x0F52}, + {MISENSOR_16BIT, 0xD488, 0x0340}, + {MISENSOR_16BIT, 0xD48A, 0x0DBA}, + {MISENSOR_16BIT, 0xD48C, 0x0200}, + {MISENSOR_16BIT, 0xD48E, 0x0AF6}, + {MISENSOR_16BIT, 0xD490, 0x0440}, + {MISENSOR_16BIT, 0xD492, 0x0C22}, + {MISENSOR_16BIT, 0xD494, 0x0400}, + {MISENSOR_16BIT, 0xD496, 0x0D72}, + {MISENSOR_16BIT, 0xD498, 0x0440}, + {MISENSOR_16BIT, 0xD49A, 0x0DC2}, + {MISENSOR_16BIT, 0xD49C, 0x0200}, + {MISENSOR_16BIT, 0xD49E, 0x0972}, + {MISENSOR_16BIT, 0xD4A0, 0x0440}, + {MISENSOR_16BIT, 0xD4A2, 0x0D3A}, + {MISENSOR_16BIT, 0xD4A4, 0x0220}, + {MISENSOR_16BIT, 0xD4A6, 0xD820}, + {MISENSOR_16BIT, 0xD4A8, 0x0BFA}, + {MISENSOR_16BIT, 0xD4AA, 0x0260}, + {MISENSOR_16BIT, 0xD4AC, 0x70C9}, + {MISENSOR_16BIT, 0xD4AE, 0x0451}, + {MISENSOR_16BIT, 0xD4B0, 0x05C0}, + {MISENSOR_16BIT, 0xD4B2, 0x78E0}, + {MISENSOR_16BIT, 0xD4B4, 0xD900}, + {MISENSOR_16BIT, 0xD4B6, 0xF00A}, + {MISENSOR_16BIT, 0xD4B8, 0x70CF}, + {MISENSOR_16BIT, 0xD4BA, 0xFFFF}, + {MISENSOR_16BIT, 0xD4BC, 0xD520}, + {MISENSOR_16BIT, 0xD4BE, 0x7835}, + {MISENSOR_16BIT, 0xD4C0, 0x8041}, + {MISENSOR_16BIT, 0xD4C2, 0x8000}, + {MISENSOR_16BIT, 0xD4C4, 0xE102}, + {MISENSOR_16BIT, 0xD4C6, 0xA040}, + {MISENSOR_16BIT, 0xD4C8, 0x09F1}, + {MISENSOR_16BIT, 0xD4CA, 0x8114}, + {MISENSOR_16BIT, 0xD4CC, 0x71CF}, + {MISENSOR_16BIT, 0xD4CE, 0xFFFF}, + {MISENSOR_16BIT, 0xD4D0, 0xD4E0}, + {MISENSOR_16BIT, 0xD4D2, 0x70CF}, + {MISENSOR_16BIT, 0xD4D4, 0xFFFF}, + {MISENSOR_16BIT, 0xD4D6, 0xC594}, + {MISENSOR_16BIT, 0xD4D8, 0xB03A}, + {MISENSOR_16BIT, 0xD4DA, 0x7FE0}, + {MISENSOR_16BIT, 0xD4DC, 0xD800}, + {MISENSOR_16BIT, 0xD4DE, 0x0000}, + {MISENSOR_16BIT, 0xD4E0, 0x0000}, + {MISENSOR_16BIT, 0xD4E2, 0x0500}, + {MISENSOR_16BIT, 0xD4E4, 0x0500}, + {MISENSOR_16BIT, 0xD4E6, 0x0200}, + {MISENSOR_16BIT, 0xD4E8, 0x0330}, + {MISENSOR_16BIT, 0xD4EA, 0x0000}, + {MISENSOR_16BIT, 0xD4EC, 0x0000}, + {MISENSOR_16BIT, 0xD4EE, 0x03CD}, + {MISENSOR_16BIT, 0xD4F0, 0x050D}, + {MISENSOR_16BIT, 0xD4F2, 0x01C5}, + {MISENSOR_16BIT, 0xD4F4, 0x03B3}, + {MISENSOR_16BIT, 0xD4F6, 0x00E0}, + {MISENSOR_16BIT, 0xD4F8, 0x01E3}, + {MISENSOR_16BIT, 0xD4FA, 0x0280}, + {MISENSOR_16BIT, 0xD4FC, 0x01E0}, + {MISENSOR_16BIT, 0xD4FE, 0x0109}, + {MISENSOR_16BIT, 0xD500, 0x0080}, + {MISENSOR_16BIT, 0xD502, 0x0500}, + {MISENSOR_16BIT, 0xD504, 0x0000}, + {MISENSOR_16BIT, 0xD506, 0x0000}, + {MISENSOR_16BIT, 0xD508, 0x0000}, + {MISENSOR_16BIT, 0xD50A, 0x0000}, + {MISENSOR_16BIT, 0xD50C, 0x0000}, + {MISENSOR_16BIT, 0xD50E, 0x0000}, + {MISENSOR_16BIT, 0xD510, 0x0000}, + {MISENSOR_16BIT, 0xD512, 0x0000}, + {MISENSOR_16BIT, 0xD514, 0x0000}, + {MISENSOR_16BIT, 0xD516, 0x0000}, + {MISENSOR_16BIT, 0xD518, 0x0000}, + {MISENSOR_16BIT, 0xD51A, 0x0000}, + {MISENSOR_16BIT, 0xD51C, 0x0000}, + {MISENSOR_16BIT, 0xD51E, 0x0000}, + {MISENSOR_16BIT, 0xD520, 0xFFFF}, + {MISENSOR_16BIT, 0xD522, 0xC9B4}, + {MISENSOR_16BIT, 0xD524, 0xFFFF}, + {MISENSOR_16BIT, 0xD526, 0xD324}, + {MISENSOR_16BIT, 0xD528, 0xFFFF}, + {MISENSOR_16BIT, 0xD52A, 0xCA34}, + {MISENSOR_16BIT, 0xD52C, 0xFFFF}, + {MISENSOR_16BIT, 0xD52E, 0xD3EC}, + {MISENSOR_16BIT, 0x098E, 0x0000}, + {MISENSOR_16BIT, 0xE000, 0x04B4}, + {MISENSOR_16BIT, 0xE002, 0x0302}, + {MISENSOR_16BIT, 0xE004, 0x4103}, + {MISENSOR_16BIT, 0xE006, 0x0202}, + {MISENSOR_16BIT, 0x0080, 0xFFF0}, + {MISENSOR_16BIT, 0x0080, 0xFFF1}, + + /* PGA parameter and APGA + * [Step4-APGA] [TP101_MT9M114_APGA] + */ + {MISENSOR_16BIT, 0x098E, 0x495E}, + {MISENSOR_16BIT, 0xC95E, 0x0000}, + {MISENSOR_16BIT, 0x3640, 0x02B0}, + {MISENSOR_16BIT, 0x3642, 0x8063}, + {MISENSOR_16BIT, 0x3644, 0x78D0}, + {MISENSOR_16BIT, 0x3646, 0x50CC}, + {MISENSOR_16BIT, 0x3648, 0x3511}, + {MISENSOR_16BIT, 0x364A, 0x0110}, + {MISENSOR_16BIT, 0x364C, 0xBD8A}, + {MISENSOR_16BIT, 0x364E, 0x0CD1}, + {MISENSOR_16BIT, 0x3650, 0x24ED}, + {MISENSOR_16BIT, 0x3652, 0x7C11}, + {MISENSOR_16BIT, 0x3654, 0x0150}, + {MISENSOR_16BIT, 0x3656, 0x124C}, + {MISENSOR_16BIT, 0x3658, 0x3130}, + {MISENSOR_16BIT, 0x365A, 0x508C}, + {MISENSOR_16BIT, 0x365C, 0x21F1}, + {MISENSOR_16BIT, 0x365E, 0x0090}, + {MISENSOR_16BIT, 0x3660, 0xBFCA}, + {MISENSOR_16BIT, 0x3662, 0x0A11}, + {MISENSOR_16BIT, 0x3664, 0x4F4B}, + {MISENSOR_16BIT, 0x3666, 0x28B1}, + {MISENSOR_16BIT, 0x3680, 0x50A9}, + {MISENSOR_16BIT, 0x3682, 0xA04B}, + {MISENSOR_16BIT, 0x3684, 0x0E2D}, + {MISENSOR_16BIT, 0x3686, 0x73EC}, + {MISENSOR_16BIT, 0x3688, 0x164F}, + {MISENSOR_16BIT, 0x368A, 0xF829}, + {MISENSOR_16BIT, 0x368C, 0xC1A8}, + {MISENSOR_16BIT, 0x368E, 0xB0EC}, + {MISENSOR_16BIT, 0x3690, 0xE76A}, + {MISENSOR_16BIT, 0x3692, 0x69AF}, + {MISENSOR_16BIT, 0x3694, 0x378C}, + {MISENSOR_16BIT, 0x3696, 0xA70D}, + {MISENSOR_16BIT, 0x3698, 0x884F}, + {MISENSOR_16BIT, 0x369A, 0xEE8B}, + {MISENSOR_16BIT, 0x369C, 0x5DEF}, + {MISENSOR_16BIT, 0x369E, 0x27CC}, + {MISENSOR_16BIT, 0x36A0, 0xCAAC}, + {MISENSOR_16BIT, 0x36A2, 0x840E}, + {MISENSOR_16BIT, 0x36A4, 0xDAA9}, + {MISENSOR_16BIT, 0x36A6, 0xF00C}, + {MISENSOR_16BIT, 0x36C0, 0x1371}, + {MISENSOR_16BIT, 0x36C2, 0x272F}, + {MISENSOR_16BIT, 0x36C4, 0x2293}, + {MISENSOR_16BIT, 0x36C6, 0xE6D0}, + {MISENSOR_16BIT, 0x36C8, 0xEC32}, + {MISENSOR_16BIT, 0x36CA, 0x11B1}, + {MISENSOR_16BIT, 0x36CC, 0x7BAF}, + {MISENSOR_16BIT, 0x36CE, 0x5813}, + {MISENSOR_16BIT, 0x36D0, 0xB871}, + {MISENSOR_16BIT, 0x36D2, 0x8913}, + {MISENSOR_16BIT, 0x36D4, 0x4610}, + {MISENSOR_16BIT, 0x36D6, 0x7EEE}, + {MISENSOR_16BIT, 0x36D8, 0x0DF3}, + {MISENSOR_16BIT, 0x36DA, 0xB84F}, + {MISENSOR_16BIT, 0x36DC, 0xB532}, + {MISENSOR_16BIT, 0x36DE, 0x1171}, + {MISENSOR_16BIT, 0x36E0, 0x13CF}, + {MISENSOR_16BIT, 0x36E2, 0x22F3}, + {MISENSOR_16BIT, 0x36E4, 0xE090}, + {MISENSOR_16BIT, 0x36E6, 0x8133}, + {MISENSOR_16BIT, 0x3700, 0x88AE}, + {MISENSOR_16BIT, 0x3702, 0x00EA}, + {MISENSOR_16BIT, 0x3704, 0x344F}, + {MISENSOR_16BIT, 0x3706, 0xEC88}, + {MISENSOR_16BIT, 0x3708, 0x3E91}, + {MISENSOR_16BIT, 0x370A, 0xF12D}, + {MISENSOR_16BIT, 0x370C, 0xB0EF}, + {MISENSOR_16BIT, 0x370E, 0x77CD}, + {MISENSOR_16BIT, 0x3710, 0x7930}, + {MISENSOR_16BIT, 0x3712, 0x5C12}, + {MISENSOR_16BIT, 0x3714, 0x500C}, + {MISENSOR_16BIT, 0x3716, 0x22CE}, + {MISENSOR_16BIT, 0x3718, 0x2370}, + {MISENSOR_16BIT, 0x371A, 0x258F}, + {MISENSOR_16BIT, 0x371C, 0x3D30}, + {MISENSOR_16BIT, 0x371E, 0x370C}, + {MISENSOR_16BIT, 0x3720, 0x03ED}, + {MISENSOR_16BIT, 0x3722, 0x9AD0}, + {MISENSOR_16BIT, 0x3724, 0x7ECF}, + {MISENSOR_16BIT, 0x3726, 0x1093}, + {MISENSOR_16BIT, 0x3740, 0x2391}, + {MISENSOR_16BIT, 0x3742, 0xAAD0}, + {MISENSOR_16BIT, 0x3744, 0x28F2}, + {MISENSOR_16BIT, 0x3746, 0xBA4F}, + {MISENSOR_16BIT, 0x3748, 0xC536}, + {MISENSOR_16BIT, 0x374A, 0x1472}, + {MISENSOR_16BIT, 0x374C, 0xD110}, + {MISENSOR_16BIT, 0x374E, 0x2933}, + {MISENSOR_16BIT, 0x3750, 0xD0D1}, + {MISENSOR_16BIT, 0x3752, 0x9F37}, + {MISENSOR_16BIT, 0x3754, 0x34D1}, + {MISENSOR_16BIT, 0x3756, 0x1C6C}, + {MISENSOR_16BIT, 0x3758, 0x3FD2}, + {MISENSOR_16BIT, 0x375A, 0xCB72}, + {MISENSOR_16BIT, 0x375C, 0xBA96}, + {MISENSOR_16BIT, 0x375E, 0x1551}, + {MISENSOR_16BIT, 0x3760, 0xB74F}, + {MISENSOR_16BIT, 0x3762, 0x1672}, + {MISENSOR_16BIT, 0x3764, 0x84F1}, + {MISENSOR_16BIT, 0x3766, 0xC2D6}, + {MISENSOR_16BIT, 0x3782, 0x01E0}, + {MISENSOR_16BIT, 0x3784, 0x0280}, + {MISENSOR_16BIT, 0x37C0, 0xA6EA}, + {MISENSOR_16BIT, 0x37C2, 0x874B}, + {MISENSOR_16BIT, 0x37C4, 0x85CB}, + {MISENSOR_16BIT, 0x37C6, 0x968A}, + {MISENSOR_16BIT, 0x098E, 0x0000}, + {MISENSOR_16BIT, 0xC960, 0x0AF0}, + {MISENSOR_16BIT, 0xC962, 0x79E2}, + {MISENSOR_16BIT, 0xC964, 0x5EC8}, + {MISENSOR_16BIT, 0xC966, 0x791F}, + {MISENSOR_16BIT, 0xC968, 0x76EE}, + {MISENSOR_16BIT, 0xC96A, 0x0FA0}, + {MISENSOR_16BIT, 0xC96C, 0x7DFA}, + {MISENSOR_16BIT, 0xC96E, 0x7DAF}, + {MISENSOR_16BIT, 0xC970, 0x7E02}, + {MISENSOR_16BIT, 0xC972, 0x7E0A}, + {MISENSOR_16BIT, 0xC974, 0x1964}, + {MISENSOR_16BIT, 0xC976, 0x7CDC}, + {MISENSOR_16BIT, 0xC978, 0x7838}, + {MISENSOR_16BIT, 0xC97A, 0x7C2F}, + {MISENSOR_16BIT, 0xC97C, 0x7792}, + {MISENSOR_16BIT, 0xC95E, 0x0003}, + + /* [Step4-APGA] */ + {MISENSOR_16BIT, 0x098E, 0x0000}, + {MISENSOR_16BIT, 0xC95E, 0x0003}, + + /* [Step5-AWB_CCM]1: LOAD=CCM */ + {MISENSOR_16BIT, 0xC892, 0x0267}, + {MISENSOR_16BIT, 0xC894, 0xFF1A}, + {MISENSOR_16BIT, 0xC896, 0xFFB3}, + {MISENSOR_16BIT, 0xC898, 0xFF80}, + {MISENSOR_16BIT, 0xC89A, 0x0166}, + {MISENSOR_16BIT, 0xC89C, 0x0003}, + {MISENSOR_16BIT, 0xC89E, 0xFF9A}, + {MISENSOR_16BIT, 0xC8A0, 0xFEB4}, + {MISENSOR_16BIT, 0xC8A2, 0x024D}, + {MISENSOR_16BIT, 0xC8A4, 0x01BF}, + {MISENSOR_16BIT, 0xC8A6, 0xFF01}, + {MISENSOR_16BIT, 0xC8A8, 0xFFF3}, + {MISENSOR_16BIT, 0xC8AA, 0xFF75}, + {MISENSOR_16BIT, 0xC8AC, 0x0198}, + {MISENSOR_16BIT, 0xC8AE, 0xFFFD}, + {MISENSOR_16BIT, 0xC8B0, 0xFF9A}, + {MISENSOR_16BIT, 0xC8B2, 0xFEE7}, + {MISENSOR_16BIT, 0xC8B4, 0x02A8}, + {MISENSOR_16BIT, 0xC8B6, 0x01D9}, + {MISENSOR_16BIT, 0xC8B8, 0xFF26}, + {MISENSOR_16BIT, 0xC8BA, 0xFFF3}, + {MISENSOR_16BIT, 0xC8BC, 0xFFB3}, + {MISENSOR_16BIT, 0xC8BE, 0x0132}, + {MISENSOR_16BIT, 0xC8C0, 0xFFE8}, + {MISENSOR_16BIT, 0xC8C2, 0xFFDA}, + {MISENSOR_16BIT, 0xC8C4, 0xFECD}, + {MISENSOR_16BIT, 0xC8C6, 0x02C2}, + {MISENSOR_16BIT, 0xC8C8, 0x0075}, + {MISENSOR_16BIT, 0xC8CA, 0x011C}, + {MISENSOR_16BIT, 0xC8CC, 0x009A}, + {MISENSOR_16BIT, 0xC8CE, 0x0105}, + {MISENSOR_16BIT, 0xC8D0, 0x00A4}, + {MISENSOR_16BIT, 0xC8D2, 0x00AC}, + {MISENSOR_16BIT, 0xC8D4, 0x0A8C}, + {MISENSOR_16BIT, 0xC8D6, 0x0F0A}, + {MISENSOR_16BIT, 0xC8D8, 0x1964}, + + /* LOAD=AWB */ + {MISENSOR_16BIT, 0xC914, 0x0000}, + {MISENSOR_16BIT, 0xC916, 0x0000}, + {MISENSOR_16BIT, 0xC918, 0x04FF}, + {MISENSOR_16BIT, 0xC91A, 0x02CF}, + {MISENSOR_16BIT, 0xC904, 0x0033}, + {MISENSOR_16BIT, 0xC906, 0x0040}, + {MISENSOR_8BIT, 0xC8F2, 0x03}, + {MISENSOR_8BIT, 0xC8F3, 0x02}, + {MISENSOR_16BIT, 0xC906, 0x003C}, + {MISENSOR_16BIT, 0xC8F4, 0x0000}, + {MISENSOR_16BIT, 0xC8F6, 0x0000}, + {MISENSOR_16BIT, 0xC8F8, 0x0000}, + {MISENSOR_16BIT, 0xC8FA, 0xE724}, + {MISENSOR_16BIT, 0xC8FC, 0x1583}, + {MISENSOR_16BIT, 0xC8FE, 0x2045}, + {MISENSOR_16BIT, 0xC900, 0x05DC}, + {MISENSOR_16BIT, 0xC902, 0x007C}, + {MISENSOR_8BIT, 0xC90C, 0x80}, + {MISENSOR_8BIT, 0xC90D, 0x80}, + {MISENSOR_8BIT, 0xC90E, 0x80}, + {MISENSOR_8BIT, 0xC90F, 0x88}, + {MISENSOR_8BIT, 0xC910, 0x80}, + {MISENSOR_8BIT, 0xC911, 0x80}, + + /* LOAD=Step7-CPIPE_Preference */ + {MISENSOR_16BIT, 0xC926, 0x0020}, + {MISENSOR_16BIT, 0xC928, 0x009A}, + {MISENSOR_16BIT, 0xC946, 0x0070}, + {MISENSOR_16BIT, 0xC948, 0x00F3}, + {MISENSOR_16BIT, 0xC952, 0x0020}, + {MISENSOR_16BIT, 0xC954, 0x009A}, + {MISENSOR_8BIT, 0xC92A, 0x80}, + {MISENSOR_8BIT, 0xC92B, 0x4B}, + {MISENSOR_8BIT, 0xC92C, 0x00}, + {MISENSOR_8BIT, 0xC92D, 0xFF}, + {MISENSOR_8BIT, 0xC92E, 0x3C}, + {MISENSOR_8BIT, 0xC92F, 0x02}, + {MISENSOR_8BIT, 0xC930, 0x06}, + {MISENSOR_8BIT, 0xC931, 0x64}, + {MISENSOR_8BIT, 0xC932, 0x01}, + {MISENSOR_8BIT, 0xC933, 0x0C}, + {MISENSOR_8BIT, 0xC934, 0x3C}, + {MISENSOR_8BIT, 0xC935, 0x3C}, + {MISENSOR_8BIT, 0xC936, 0x3C}, + {MISENSOR_8BIT, 0xC937, 0x0F}, + {MISENSOR_8BIT, 0xC938, 0x64}, + {MISENSOR_8BIT, 0xC939, 0x64}, + {MISENSOR_8BIT, 0xC93A, 0x64}, + {MISENSOR_8BIT, 0xC93B, 0x32}, + {MISENSOR_16BIT, 0xC93C, 0x0020}, + {MISENSOR_16BIT, 0xC93E, 0x009A}, + {MISENSOR_16BIT, 0xC940, 0x00DC}, + {MISENSOR_8BIT, 0xC942, 0x38}, + {MISENSOR_8BIT, 0xC943, 0x30}, + {MISENSOR_8BIT, 0xC944, 0x50}, + {MISENSOR_8BIT, 0xC945, 0x19}, + {MISENSOR_16BIT, 0xC94A, 0x0230}, + {MISENSOR_16BIT, 0xC94C, 0x0010}, + {MISENSOR_16BIT, 0xC94E, 0x01CD}, + {MISENSOR_8BIT, 0xC950, 0x05}, + {MISENSOR_8BIT, 0xC951, 0x40}, + {MISENSOR_8BIT, 0xC87B, 0x1B}, + {MISENSOR_8BIT, 0xC878, 0x0E}, + {MISENSOR_16BIT, 0xC890, 0x0080}, + {MISENSOR_16BIT, 0xC886, 0x0100}, + {MISENSOR_16BIT, 0xC87C, 0x005A}, + {MISENSOR_8BIT, 0xB42A, 0x05}, + {MISENSOR_8BIT, 0xA80A, 0x20}, + + /* Speed up AE/AWB */ + {MISENSOR_16BIT, 0x098E, 0x2802}, + {MISENSOR_16BIT, 0xA802, 0x0008}, + {MISENSOR_8BIT, 0xC908, 0x01}, + {MISENSOR_8BIT, 0xC879, 0x01}, + {MISENSOR_8BIT, 0xC909, 0x02}, + {MISENSOR_8BIT, 0xA80A, 0x18}, + {MISENSOR_8BIT, 0xA80B, 0x18}, + {MISENSOR_8BIT, 0xAC16, 0x18}, + {MISENSOR_8BIT, 0xC878, 0x0E}, + + {MISENSOR_TOK_TERM, 0, 0} +}; + +#endif diff --git a/drivers/staging/media/atomisp/i2c/ov2680.c b/drivers/staging/media/atomisp/i2c/ov2680.c new file mode 100644 index 0000000000000000000000000000000000000000..3f1495e31070685a867bf14449fc7bce5ec21229 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov2680.c @@ -0,0 +1,1562 @@ +/* + * Support for OmniVision OV2680 1080p HD camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ov2680.h" + +#define ov2680_debug(...) //dev_err(__VA_ARGS__) +static int h_flag = 0; +static int v_flag = 0; +static enum atomisp_bayer_order ov2680_bayer_order_mapping[] = { + atomisp_bayer_order_bggr, + atomisp_bayer_order_grbg, + atomisp_bayer_order_gbrg, + atomisp_bayer_order_rggb, +}; + +/* i2c read/write stuff */ +static int ov2680_read_reg(struct i2c_client *client, + u16 data_length, u16 reg, u16 *val) +{ + int err; + struct i2c_msg msg[2]; + unsigned char data[6]; + + if (!client->adapter) { + dev_err(&client->dev, "%s error, no client->adapter\n", + __func__); + return -ENODEV; + } + + if (data_length != OV2680_8BIT && data_length != OV2680_16BIT + && data_length != OV2680_32BIT) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + memset(msg, 0 , sizeof(msg)); + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = I2C_MSG_LENGTH; + msg[0].buf = data; + + /* high byte goes out first */ + data[0] = (u8)(reg >> 8); + data[1] = (u8)(reg & 0xff); + + msg[1].addr = client->addr; + msg[1].len = data_length; + msg[1].flags = I2C_M_RD; + msg[1].buf = data; + + err = i2c_transfer(client->adapter, msg, 2); + if (err != 2) { + if (err >= 0) + err = -EIO; + dev_err(&client->dev, + "read from offset 0x%x error %d", reg, err); + return err; + } + + *val = 0; + /* high byte comes first */ + if (data_length == OV2680_8BIT) + *val = (u8)data[0]; + else if (data_length == OV2680_16BIT) + *val = be16_to_cpu(*(u16 *)&data[0]); + else + *val = be32_to_cpu(*(u32 *)&data[0]); + //ov2680_debug(&client->dev, "++++i2c read adr%x = %x\n", reg,*val); + return 0; +} + +static int ov2680_i2c_write(struct i2c_client *client, u16 len, u8 *data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = len; + msg.buf = data; + ret = i2c_transfer(client->adapter, &msg, 1); + //ov2680_debug(&client->dev, "+++i2c write reg=%x->%x\n", data[0]*256 +data[1],data[2]); + return ret == num_msg ? 0 : -EIO; +} + +static int ov2680_write_reg(struct i2c_client *client, u16 data_length, + u16 reg, u16 val) +{ + int ret; + unsigned char data[4] = {0}; + u16 *wreg = (u16 *)data; + const u16 len = data_length + sizeof(u16); /* 16-bit address + data */ + + if (data_length != OV2680_8BIT && data_length != OV2680_16BIT) { + dev_err(&client->dev, + "%s error, invalid data_length\n", __func__); + return -EINVAL; + } + + /* high byte goes out first */ + *wreg = cpu_to_be16(reg); + + if (data_length == OV2680_8BIT) { + data[2] = (u8)(val); + } else { + /* OV2680_16BIT */ + u16 *wdata = (u16 *)&data[2]; + *wdata = cpu_to_be16(val); + } + + ret = ov2680_i2c_write(client, len, data); + if (ret) + dev_err(&client->dev, + "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, ret); + + return ret; +} + +/* + * ov2680_write_reg_array - Initializes a list of OV2680 registers + * @client: i2c driver client structure + * @reglist: list of registers to be written + * + * This function initializes a list of registers. When consecutive addresses + * are found in a row on the list, this function creates a buffer and sends + * consecutive data in a single i2c_transfer(). + * + * __ov2680_flush_reg_array, __ov2680_buf_reg_array() and + * __ov2680_write_reg_is_consecutive() are internal functions to + * ov2680_write_reg_array_fast() and should be not used anywhere else. + * + */ + +static int __ov2680_flush_reg_array(struct i2c_client *client, + struct ov2680_write_ctrl *ctrl) +{ + u16 size; + + if (ctrl->index == 0) + return 0; + + size = sizeof(u16) + ctrl->index; /* 16-bit address + data */ + ctrl->buffer.addr = cpu_to_be16(ctrl->buffer.addr); + ctrl->index = 0; + + return ov2680_i2c_write(client, size, (u8 *)&ctrl->buffer); +} + +static int __ov2680_buf_reg_array(struct i2c_client *client, + struct ov2680_write_ctrl *ctrl, + const struct ov2680_reg *next) +{ + int size; + u16 *data16; + + switch (next->type) { + case OV2680_8BIT: + size = 1; + ctrl->buffer.data[ctrl->index] = (u8)next->val; + break; + case OV2680_16BIT: + size = 2; + data16 = (u16 *)&ctrl->buffer.data[ctrl->index]; + *data16 = cpu_to_be16((u16)next->val); + break; + default: + return -EINVAL; + } + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->reg; + + ctrl->index += size; + + /* + * Buffer cannot guarantee free space for u32? Better flush it to avoid + * possible lack of memory for next item. + */ + if (ctrl->index + sizeof(u16) >= OV2680_MAX_WRITE_BUF_SIZE) + return __ov2680_flush_reg_array(client, ctrl); + + return 0; +} + +static int __ov2680_write_reg_is_consecutive(struct i2c_client *client, + struct ov2680_write_ctrl *ctrl, + const struct ov2680_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->reg; +} + +static int ov2680_write_reg_array(struct i2c_client *client, + const struct ov2680_reg *reglist) +{ + const struct ov2680_reg *next = reglist; + struct ov2680_write_ctrl ctrl; + int err; + ov2680_debug(&client->dev, "++++write reg array\n"); + ctrl.index = 0; + for (; next->type != OV2680_TOK_TERM; next++) { + switch (next->type & OV2680_TOK_MASK) { + case OV2680_TOK_DELAY: + err = __ov2680_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceed. + */ + ov2680_debug(&client->dev, "+++ov2680_write_reg_array reg=%x->%x\n", next->reg,next->val); + if (!__ov2680_write_reg_is_consecutive(client, &ctrl, + next)) { + err = __ov2680_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __ov2680_buf_reg_array(client, &ctrl, next); + if (err) { + dev_err(&client->dev, "%s: write error, aborted\n", + __func__); + return err; + } + break; + } + } + + return __ov2680_flush_reg_array(client, &ctrl); +} +static int ov2680_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + + *val = (OV2680_FOCAL_LENGTH_NUM << 16) | OV2680_FOCAL_LENGTH_DEM; + return 0; +} + +static int ov2680_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /*const f number for ov2680*/ + + *val = (OV2680_F_NUMBER_DEFAULT_NUM << 16) | OV2680_F_NUMBER_DEM; + return 0; +} + +static int ov2680_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + + *val = (OV2680_F_NUMBER_DEFAULT_NUM << 24) | + (OV2680_F_NUMBER_DEM << 16) | + (OV2680_F_NUMBER_DEFAULT_NUM << 8) | OV2680_F_NUMBER_DEM; + return 0; +} + +static int ov2680_g_bin_factor_x(struct v4l2_subdev *sd, s32 *val) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + ov2680_debug(dev, "++++ov2680_g_bin_factor_x\n"); + *val = ov2680_res[dev->fmt_idx].bin_factor_x; + + return 0; +} + +static int ov2680_g_bin_factor_y(struct v4l2_subdev *sd, s32 *val) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + + *val = ov2680_res[dev->fmt_idx].bin_factor_y; + ov2680_debug(dev, "++++ov2680_g_bin_factor_y\n"); + return 0; +} + + +static int ov2680_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct ov2680_resolution *res) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct atomisp_sensor_mode_data *buf = &info->data; + unsigned int pix_clk_freq_hz; + u16 reg_val; + int ret; + ov2680_debug(dev, "++++ov2680_get_intg_factor\n"); + if (info == NULL) + return -EINVAL; + + /* pixel clock */ + pix_clk_freq_hz = res->pix_clk_freq * 1000000; + + dev->vt_pix_clk_freq_mhz = pix_clk_freq_hz; + buf->vt_pix_clk_freq_mhz = pix_clk_freq_hz; + + /* get integration time */ + buf->coarse_integration_time_min = OV2680_COARSE_INTG_TIME_MIN; + buf->coarse_integration_time_max_margin = + OV2680_COARSE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_min = OV2680_FINE_INTG_TIME_MIN; + buf->fine_integration_time_max_margin = + OV2680_FINE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_def = OV2680_FINE_INTG_TIME_MIN; + buf->frame_length_lines = res->lines_per_frame; + buf->line_length_pck = res->pixels_per_line; + buf->read_mode = res->bin_mode; + + /* get the cropping and output resolution to ISP for this mode. */ + ret = ov2680_read_reg(client, OV2680_16BIT, + OV2680_HORIZONTAL_START_H, ®_val); + if (ret) + return ret; + buf->crop_horizontal_start = reg_val; + + ret = ov2680_read_reg(client, OV2680_16BIT, + OV2680_VERTICAL_START_H, ®_val); + if (ret) + return ret; + buf->crop_vertical_start = reg_val; + + ret = ov2680_read_reg(client, OV2680_16BIT, + OV2680_HORIZONTAL_END_H, ®_val); + if (ret) + return ret; + buf->crop_horizontal_end = reg_val; + + ret = ov2680_read_reg(client, OV2680_16BIT, + OV2680_VERTICAL_END_H, ®_val); + if (ret) + return ret; + buf->crop_vertical_end = reg_val; + + ret = ov2680_read_reg(client, OV2680_16BIT, + OV2680_HORIZONTAL_OUTPUT_SIZE_H, ®_val); + if (ret) + return ret; + buf->output_width = reg_val; + + ret = ov2680_read_reg(client, OV2680_16BIT, + OV2680_VERTICAL_OUTPUT_SIZE_H, ®_val); + if (ret) + return ret; + buf->output_height = reg_val; + + buf->binning_factor_x = res->bin_factor_x ? + (res->bin_factor_x*2) : 1; + buf->binning_factor_y = res->bin_factor_y ? + (res->bin_factor_y*2) : 1; + return 0; +} + +static long __ov2680_set_exposure(struct v4l2_subdev *sd, int coarse_itg, + int gain, int digitgain) + +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov2680_device *dev = to_ov2680_sensor(sd); + u16 vts,hts; + int ret,exp_val; + + ov2680_debug(dev, "+++++++__ov2680_set_exposure coarse_itg %d, gain %d, digitgain %d++\n",coarse_itg, gain, digitgain); + + hts = ov2680_res[dev->fmt_idx].pixels_per_line; + vts = ov2680_res[dev->fmt_idx].lines_per_frame; + + /* group hold */ + ret = ov2680_write_reg(client, OV2680_8BIT, + OV2680_GROUP_ACCESS, 0x00); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV2680_GROUP_ACCESS); + return ret; + } + + /* Increase the VTS to match exposure + MARGIN */ + if (coarse_itg > vts - OV2680_INTEGRATION_TIME_MARGIN) + vts = (u16) coarse_itg + OV2680_INTEGRATION_TIME_MARGIN; + + ret = ov2680_write_reg(client, OV2680_16BIT, OV2680_TIMING_VTS_H, vts); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV2680_TIMING_VTS_H); + return ret; + } + + /* set exposure */ + + /* Lower four bit should be 0*/ + exp_val = coarse_itg << 4; + ret = ov2680_write_reg(client, OV2680_8BIT, + OV2680_EXPOSURE_L, exp_val & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV2680_EXPOSURE_L); + return ret; + } + + ret = ov2680_write_reg(client, OV2680_8BIT, + OV2680_EXPOSURE_M, (exp_val >> 8) & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV2680_EXPOSURE_M); + return ret; + } + + ret = ov2680_write_reg(client, OV2680_8BIT, + OV2680_EXPOSURE_H, (exp_val >> 16) & 0x0F); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV2680_EXPOSURE_H); + return ret; + } + + /* Analog gain */ + ret = ov2680_write_reg(client, OV2680_16BIT, OV2680_AGC_H, gain); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV2680_AGC_H); + return ret; + } + /* Digital gain */ + if (digitgain) { + ret = ov2680_write_reg(client, OV2680_16BIT, + OV2680_MWB_RED_GAIN_H, digitgain); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV2680_MWB_RED_GAIN_H); + return ret; + } + + ret = ov2680_write_reg(client, OV2680_16BIT, + OV2680_MWB_GREEN_GAIN_H, digitgain); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV2680_MWB_RED_GAIN_H); + return ret; + } + + ret = ov2680_write_reg(client, OV2680_16BIT, + OV2680_MWB_BLUE_GAIN_H, digitgain); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV2680_MWB_RED_GAIN_H); + return ret; + } + } + + /* End group */ + ret = ov2680_write_reg(client, OV2680_8BIT, + OV2680_GROUP_ACCESS, 0x10); + if (ret) + return ret; + + /* Delay launch group */ + ret = ov2680_write_reg(client, OV2680_8BIT, + OV2680_GROUP_ACCESS, 0xa0); + if (ret) + return ret; + return ret; +} + +static int ov2680_set_exposure(struct v4l2_subdev *sd, int exposure, + int gain, int digitgain) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __ov2680_set_exposure(sd, exposure, gain, digitgain); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static long ov2680_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + u16 coarse_itg = exposure->integration_time[0]; + u16 analog_gain = exposure->gain[0]; + u16 digital_gain = exposure->gain[1]; + + /* we should not accept the invalid value below */ + if (analog_gain == 0) { + struct i2c_client *client = v4l2_get_subdevdata(sd); + v4l2_err(client, "%s: invalid value\n", __func__); + return -EINVAL; + } + + // EXPOSURE CONTROL DISABLED FOR INITIAL CHECKIN, TUNING DOESN'T WORK + return ov2680_set_exposure(sd, coarse_itg, analog_gain, digital_gain); +} + + + + + +static long ov2680_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return ov2680_s_exposure(sd, arg); + + default: + return -EINVAL; + } + return 0; +} + +/* This returns the exposure time being used. This should only be used + for filling in EXIF data, not for actual image processing. */ +static int ov2680_q_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 reg_v, reg_v2; + int ret; + + /* get exposure */ + ret = ov2680_read_reg(client, OV2680_8BIT, + OV2680_EXPOSURE_L, + ®_v); + if (ret) + goto err; + + ret = ov2680_read_reg(client, OV2680_8BIT, + OV2680_EXPOSURE_M, + ®_v2); + if (ret) + goto err; + + reg_v += reg_v2 << 8; + ret = ov2680_read_reg(client, OV2680_8BIT, + OV2680_EXPOSURE_H, + ®_v2); + if (ret) + goto err; + + *value = reg_v + (((u32)reg_v2 << 16)); +err: + return ret; +} + +static u32 ov2680_translate_bayer_order(enum atomisp_bayer_order code) +{ + switch (code) { + case atomisp_bayer_order_rggb: + return MEDIA_BUS_FMT_SRGGB10_1X10; + case atomisp_bayer_order_grbg: + return MEDIA_BUS_FMT_SGRBG10_1X10; + case atomisp_bayer_order_bggr: + return MEDIA_BUS_FMT_SBGGR10_1X10; + case atomisp_bayer_order_gbrg: + return MEDIA_BUS_FMT_SGBRG10_1X10; + } + return 0; +} + +static int ov2680_v_flip(struct v4l2_subdev *sd, s32 value) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct camera_mipi_info *ov2680_info = NULL; + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u16 val; + u8 index; + ov2680_debug(&client->dev, "@%s: value:%d\n", __func__, value); + ret = ov2680_read_reg(client, OV2680_8BIT, OV2680_FLIP_REG, &val); + if (ret) + return ret; + if (value) { + val |= OV2680_FLIP_MIRROR_BIT_ENABLE; + } else { + val &= ~OV2680_FLIP_MIRROR_BIT_ENABLE; + } + ret = ov2680_write_reg(client, OV2680_8BIT, + OV2680_FLIP_REG, val); + if (ret) + return ret; + index = (v_flag>0?OV2680_FLIP_BIT:0) | (h_flag>0?OV2680_MIRROR_BIT:0); + ov2680_info = v4l2_get_subdev_hostdata(sd); + if (ov2680_info) { + ov2680_info->raw_bayer_order = ov2680_bayer_order_mapping[index]; + dev->format.code = ov2680_translate_bayer_order( + ov2680_info->raw_bayer_order); + } + return ret; +} + +static int ov2680_h_flip(struct v4l2_subdev *sd, s32 value) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct camera_mipi_info *ov2680_info = NULL; + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u16 val; + u8 index; + ov2680_debug(&client->dev, "@%s: value:%d\n", __func__, value); + + ret = ov2680_read_reg(client, OV2680_8BIT, OV2680_MIRROR_REG, &val); + if (ret) + return ret; + if (value) { + val |= OV2680_FLIP_MIRROR_BIT_ENABLE; + } else { + val &= ~OV2680_FLIP_MIRROR_BIT_ENABLE; + } + ret = ov2680_write_reg(client, OV2680_8BIT, + OV2680_MIRROR_REG, val); + if (ret) + return ret; + index = (v_flag>0?OV2680_FLIP_BIT:0) | (h_flag>0?OV2680_MIRROR_BIT:0); + ov2680_info = v4l2_get_subdev_hostdata(sd); + if (ov2680_info) { + ov2680_info->raw_bayer_order = ov2680_bayer_order_mapping[index]; + dev->format.code = ov2680_translate_bayer_order( + ov2680_info->raw_bayer_order); + } + return ret; +} + +static int ov2680_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov2680_device *dev = + container_of(ctrl->handler, struct ov2680_device, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_VFLIP: + dev_dbg(&client->dev, "%s: CID_VFLIP:%d.\n", + __func__, ctrl->val); + ret = ov2680_v_flip(&dev->sd, ctrl->val); + break; + case V4L2_CID_HFLIP: + dev_dbg(&client->dev, "%s: CID_HFLIP:%d.\n", + __func__, ctrl->val); + ret = ov2680_h_flip(&dev->sd, ctrl->val); + break; + default: + ret = -EINVAL; + } + return ret; +} + +static int ov2680_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov2680_device *dev = + container_of(ctrl->handler, struct ov2680_device, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = ov2680_q_exposure(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = ov2680_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = ov2680_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = ov2680_g_fnumber_range(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_HORZ: + ret = ov2680_g_bin_factor_x(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_VERT: + ret = ov2680_g_bin_factor_y(&dev->sd, &ctrl->val); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = ov2680_s_ctrl, + .g_volatile_ctrl = ov2680_g_volatile_ctrl +}; + +struct v4l2_ctrl_config ov2680_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .min = 0x0, + .max = 0xffff, + .step = 0x01, + .def = 0x00, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focal length", + .min = OV2680_FOCAL_LENGTH_DEFAULT, + .max = OV2680_FOCAL_LENGTH_DEFAULT, + .step = 0x01, + .def = OV2680_FOCAL_LENGTH_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number", + .min = OV2680_F_NUMBER_DEFAULT, + .max = OV2680_F_NUMBER_DEFAULT, + .step = 0x01, + .def = OV2680_F_NUMBER_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number range", + .min = OV2680_F_NUMBER_RANGE, + .max = OV2680_F_NUMBER_RANGE, + .step = 0x01, + .def = OV2680_F_NUMBER_RANGE, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_HORZ, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "horizontal binning factor", + .min = 0, + .max = OV2680_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_VERT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vertical binning factor", + .min = 0, + .max = OV2680_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Flip", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_HFLIP, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Mirror", + .min = 0, + .max = 1, + .step = 1, + .def = 0, + }, +}; + +static int ov2680_init_registers(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + ret = ov2680_write_reg(client, OV2680_8BIT, OV2680_SW_RESET, 0x01); + ret |= ov2680_write_reg_array(client, ov2680_global_setting); + + return ret; +} + +static int ov2680_init(struct v4l2_subdev *sd) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + + int ret; + + mutex_lock(&dev->input_lock); + + /* restore settings */ + ov2680_res = ov2680_res_preview; + N_RES = N_RES_PREVIEW; + + ret = ov2680_init_registers(sd); + + mutex_unlock(&dev->input_lock); + + return ret; +} + +static int power_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret = 0; + struct ov2680_device *dev = to_ov2680_sensor(sd); + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->power_ctrl) + return dev->platform_data->power_ctrl(sd, flag); + + if (flag) { + ret |= dev->platform_data->v1p8_ctrl(sd, 1); + ret |= dev->platform_data->v2p8_ctrl(sd, 1); + usleep_range(10000, 15000); + } + + if (!flag || ret) { + ret |= dev->platform_data->v1p8_ctrl(sd, 0); + ret |= dev->platform_data->v2p8_ctrl(sd, 0); + } + return ret; +} + +static int gpio_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret; + struct ov2680_device *dev = to_ov2680_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->gpio_ctrl) + return dev->platform_data->gpio_ctrl(sd, flag); + + /* The OV2680 documents only one GPIO input (#XSHUTDN), but + * existing integrations often wire two (reset/power_down) + * because that is the way other sensors work. There is no + * way to tell how it is wired internally, so existing + * firmwares expose both and we drive them symmetrically. */ + if (flag) { + ret = dev->platform_data->gpio0_ctrl(sd, 1); + usleep_range(10000, 15000); + ret |= dev->platform_data->gpio1_ctrl(sd, 1); + usleep_range(10000, 15000); + } else { + ret = dev->platform_data->gpio1_ctrl(sd, 0); + ret |= dev->platform_data->gpio0_ctrl(sd, 0); + } + return ret; +} + +static int power_up(struct v4l2_subdev *sd) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (NULL == dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + /* power control */ + ret = power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* according to DS, at least 5ms is needed between DOVDD and PWDN */ + usleep_range(5000, 6000); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 1); + if (ret) { + ret = gpio_ctrl(sd, 1); + if (ret) + goto fail_power; + } + + /* flis clock control */ + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + + /* according to DS, 20ms is needed between PWDN and i2c access */ + msleep(20); + + return 0; + +fail_clk: + gpio_ctrl(sd, 0); +fail_power: + power_ctrl(sd, 0); + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + h_flag = 0; + v_flag = 0; + if (NULL == dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 0); + if (ret) { + ret = gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed 2\n"); + } + + /* power control */ + ret = power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "vprog failed.\n"); + + return ret; +} + +static int ov2680_s_power(struct v4l2_subdev *sd, int on) +{ + int ret; + + if (on == 0){ + ret = power_down(sd); + } else { + ret = power_up(sd); + if (!ret) + return ov2680_init(sd); + } + return ret; +} + +/* + * distance - calculate the distance + * @res: resolution + * @w: width + * @h: height + * + * Get the gap between resolution and w/h. + * res->width/height smaller than w/h wouldn't be considered. + * Returns the value of gap or -1 if fail. + */ +#define LARGEST_ALLOWED_RATIO_MISMATCH 600 +static int distance(struct ov2680_resolution *res, u32 w, u32 h) +{ + unsigned int w_ratio = ((res->width << 13)/w); + unsigned int h_ratio; + int match; + + if (h == 0) + return -1; + h_ratio = ((res->height << 13) / h); + if (h_ratio == 0) + return -1; + match = abs(((w_ratio << 13) / h_ratio) - ((int)8192)); + + + if ((w_ratio < (int)8192) || (h_ratio < (int)8192) || + (match > LARGEST_ALLOWED_RATIO_MISMATCH)) + return -1; + + return w_ratio + h_ratio; +} + +/* Return the nearest higher resolution index */ +static int nearest_resolution_index(int w, int h) +{ + int i; + int idx = -1; + int dist; + int min_dist = INT_MAX; + struct ov2680_resolution *tmp_res = NULL; + + for (i = 0; i < N_RES; i++) { + tmp_res = &ov2680_res[i]; + dist = distance(tmp_res, w, h); + if (dist == -1) + continue; + if (dist < min_dist) { + min_dist = dist; + idx = i; + } + } + + return idx; +} + +static int get_resolution_index(int w, int h) +{ + int i; + + for (i = 0; i < N_RES; i++) { + if (w != ov2680_res[i].width) + continue; + if (h != ov2680_res[i].height) + continue; + + return i; + } + + return -1; +} + +static int ov2680_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct camera_mipi_info *ov2680_info = NULL; + int ret = 0; + int idx = 0; + ov2680_debug(&client->dev, "+++++ov2680_s_mbus_fmt+++++l\n"); + if (format->pad) + return -EINVAL; + + if (!fmt) + return -EINVAL; + + ov2680_info = v4l2_get_subdev_hostdata(sd); + if (ov2680_info == NULL) + return -EINVAL; + + mutex_lock(&dev->input_lock); + idx = nearest_resolution_index(fmt->width, fmt->height); + if (idx == -1) { + /* return the largest resolution */ + fmt->width = ov2680_res[N_RES - 1].width; + fmt->height = ov2680_res[N_RES - 1].height; + } else { + fmt->width = ov2680_res[idx].width; + fmt->height = ov2680_res[idx].height; + } + fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + cfg->try_fmt = *fmt; + mutex_unlock(&dev->input_lock); + return 0; + } + dev->fmt_idx = get_resolution_index(fmt->width, fmt->height); + ov2680_debug(&client->dev, "+++++get_resolution_index=%d+++++l\n", + dev->fmt_idx); + if (dev->fmt_idx == -1) { + dev_err(&client->dev, "get resolution fail\n"); + mutex_unlock(&dev->input_lock); + return -EINVAL; + } + v4l2_info(client, "__s_mbus_fmt i=%d, w=%d, h=%d\n", dev->fmt_idx, + fmt->width, fmt->height); + ov2680_debug(&client->dev, "__s_mbus_fmt i=%d, w=%d, h=%d\n", + dev->fmt_idx, fmt->width, fmt->height); + + ret = ov2680_write_reg_array(client, ov2680_res[dev->fmt_idx].regs); + if (ret) + dev_err(&client->dev, "ov2680 write resolution register err\n"); + + ret = ov2680_get_intg_factor(client, ov2680_info, + &ov2680_res[dev->fmt_idx]); + if (ret) { + dev_err(&client->dev, "failed to get integration_factor\n"); + goto err; + } + + /*recall flip functions to avoid flip registers + * were overrided by default setting + */ + if (h_flag) + ov2680_h_flip(sd, h_flag); + if (v_flag) + ov2680_v_flip(sd, v_flag); + + v4l2_info(client, "\n%s idx %d \n", __func__, dev->fmt_idx); + + /*ret = startup(sd); + if (ret) + dev_err(&client->dev, "ov2680 startup err\n"); + */ +err: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int ov2680_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov2680_device *dev = to_ov2680_sensor(sd); + + if (format->pad) + return -EINVAL; + + if (!fmt) + return -EINVAL; + + fmt->width = ov2680_res[dev->fmt_idx].width; + fmt->height = ov2680_res[dev->fmt_idx].height; + fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; + + return 0; +} + +static int ov2680_detect(struct i2c_client *client) +{ + struct i2c_adapter *adapter = client->adapter; + u16 high, low; + int ret; + u16 id; + u8 revision; + + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + + ret = ov2680_read_reg(client, OV2680_8BIT, + OV2680_SC_CMMN_CHIP_ID_H, &high); + if (ret) { + dev_err(&client->dev, "sensor_id_high = 0x%x\n", high); + return -ENODEV; + } + ret = ov2680_read_reg(client, OV2680_8BIT, + OV2680_SC_CMMN_CHIP_ID_L, &low); + id = ((((u16) high) << 8) | (u16) low); + + if (id != OV2680_ID) { + dev_err(&client->dev, "sensor ID error 0x%x\n", id); + return -ENODEV; + } + + ret = ov2680_read_reg(client, OV2680_8BIT, + OV2680_SC_CMMN_SUB_ID, &high); + revision = (u8) high & 0x0f; + + dev_err(&client->dev, "sensor_revision id = 0x%x\n", id); + dev_err(&client->dev, "detect ov2680 success\n"); + dev_err(&client->dev, "################5##########\n"); + return 0; +} + +static int ov2680_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + mutex_lock(&dev->input_lock); + if(enable ) + ov2680_debug(&client->dev, "ov2680_s_stream one \n"); + else + ov2680_debug(&client->dev, "ov2680_s_stream off \n"); + + ret = ov2680_write_reg(client, OV2680_8BIT, OV2680_SW_STREAM, + enable ? OV2680_START_STREAMING : + OV2680_STOP_STREAMING); +#if 0 + /* restore settings */ + ov2680_res = ov2680_res_preview; + N_RES = N_RES_PREVIEW; +#endif + + //otp valid at stream on state + //if(!dev->otp_data) + // dev->otp_data = ov2680_otp_read(sd); + + mutex_unlock(&dev->input_lock); + + return ret; +} + + +static int ov2680_s_config(struct v4l2_subdev *sd, + int irq, void *platform_data) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (platform_data == NULL) + return -ENODEV; + + dev->platform_data = + (struct camera_sensor_platform_data *)platform_data; + + mutex_lock(&dev->input_lock); + /* power off the module, then power on it in future + * as first power on by board may not fulfill the + * power on sequqence needed by the module + */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "ov2680 power-off err.\n"); + goto fail_power_off; + } + + ret = power_up(sd); + if (ret) { + dev_err(&client->dev, "ov2680 power-up err.\n"); + goto fail_power_on; + } + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + /* config & detect sensor */ + ret = ov2680_detect(client); + if (ret) { + dev_err(&client->dev, "ov2680_detect err s_config.\n"); + goto fail_csi_cfg; + } + + /* turn off sensor, after probed */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "ov2680 power-off err.\n"); + goto fail_csi_cfg; + } + mutex_unlock(&dev->input_lock); + + return 0; + +fail_csi_cfg: + dev->platform_data->csi_cfg(sd, 0); +fail_power_on: + power_down(sd); + dev_err(&client->dev, "sensor power-gating failed\n"); +fail_power_off: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int ov2680_g_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + + if (!param) + return -EINVAL; + + if (param->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + dev_err(&client->dev, "unsupported buffer type.\n"); + return -EINVAL; + } + + memset(param, 0, sizeof(*param)); + param->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + if (dev->fmt_idx >= 0 && dev->fmt_idx < N_RES) { + param->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + param->parm.capture.timeperframe.numerator = 1; + param->parm.capture.capturemode = dev->run_mode; + param->parm.capture.timeperframe.denominator = + ov2680_res[dev->fmt_idx].fps; + } + return 0; +} + +static int ov2680_s_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + dev->run_mode = param->parm.capture.capturemode; + + v4l2_info(client, "\n%s:run_mode :%x\n", __func__, dev->run_mode); + + mutex_lock(&dev->input_lock); + switch (dev->run_mode) { + case CI_MODE_VIDEO: + ov2680_res = ov2680_res_video; + N_RES = N_RES_VIDEO; + break; + case CI_MODE_STILL_CAPTURE: + ov2680_res = ov2680_res_still; + N_RES = N_RES_STILL; + break; + default: + ov2680_res = ov2680_res_preview; + N_RES = N_RES_PREVIEW; + } + mutex_unlock(&dev->input_lock); + return 0; +} + +static int ov2680_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + + interval->interval.numerator = 1; + interval->interval.denominator = ov2680_res[dev->fmt_idx].fps; + + return 0; +} + +static int ov2680_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= MAX_FMTS) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_SBGGR10_1X10; + return 0; +} + +static int ov2680_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + int index = fse->index; + + if (index >= N_RES) + return -EINVAL; + + fse->min_width = ov2680_res[index].width; + fse->min_height = ov2680_res[index].height; + fse->max_width = ov2680_res[index].width; + fse->max_height = ov2680_res[index].height; + + return 0; + +} + +static int ov2680_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + struct ov2680_device *dev = to_ov2680_sensor(sd); + + mutex_lock(&dev->input_lock); + *frames = ov2680_res[dev->fmt_idx].skip_frames; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static const struct v4l2_subdev_video_ops ov2680_video_ops = { + .s_stream = ov2680_s_stream, + .g_parm = ov2680_g_parm, + .s_parm = ov2680_s_parm, + .g_frame_interval = ov2680_g_frame_interval, +}; + +static const struct v4l2_subdev_sensor_ops ov2680_sensor_ops = { + .g_skip_frames = ov2680_g_skip_frames, +}; + +static const struct v4l2_subdev_core_ops ov2680_core_ops = { + .s_power = ov2680_s_power, + .ioctl = ov2680_ioctl, +}; + +static const struct v4l2_subdev_pad_ops ov2680_pad_ops = { + .enum_mbus_code = ov2680_enum_mbus_code, + .enum_frame_size = ov2680_enum_frame_size, + .get_fmt = ov2680_get_fmt, + .set_fmt = ov2680_set_fmt, +}; + +static const struct v4l2_subdev_ops ov2680_ops = { + .core = &ov2680_core_ops, + .video = &ov2680_video_ops, + .pad = &ov2680_pad_ops, + .sensor = &ov2680_sensor_ops, +}; + +static int ov2680_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov2680_device *dev = to_ov2680_sensor(sd); + dev_dbg(&client->dev, "ov2680_remove...\n"); + + dev->platform_data->csi_cfg(sd, 0); + + v4l2_device_unregister_subdev(sd); + media_entity_cleanup(&dev->sd.entity); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + kfree(dev); + + return 0; +} + +static int ov2680_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct ov2680_device *dev; + int ret; + void *pdata; + unsigned int i; + + printk("++++ov2680_probe++++\n"); + dev_info(&client->dev, "++++ov2680_probe++++\n"); + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) { + dev_err(&client->dev, "out of memory\n"); + return -ENOMEM; + } + + mutex_init(&dev->input_lock); + + dev->fmt_idx = 0; + v4l2_i2c_subdev_init(&(dev->sd), client, &ov2680_ops); + + if (ACPI_COMPANION(&client->dev)) + pdata = gmin_camera_platform_data(&dev->sd, + ATOMISP_INPUT_FORMAT_RAW_10, + atomisp_bayer_order_bggr); + else + pdata = client->dev.platform_data; + + if (!pdata) { + ret = -EINVAL; + goto out_free; + } + + ret = ov2680_s_config(&dev->sd, client->irq, pdata); + if (ret) + goto out_free; + + ret = atomisp_register_i2c_module(&dev->sd, pdata, RAW_CAMERA); + if (ret) + goto out_free; + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = MEDIA_BUS_FMT_SBGGR10_1X10; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = + v4l2_ctrl_handler_init(&dev->ctrl_handler, + ARRAY_SIZE(ov2680_controls)); + if (ret) { + ov2680_remove(client); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(ov2680_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &ov2680_controls[i], + NULL); + + if (dev->ctrl_handler.error) { + ov2680_remove(client); + return dev->ctrl_handler.error; + } + + /* Use same lock for controls as for everything else. */ + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = &dev->ctrl_handler; + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) + { + ov2680_remove(client); + ov2680_debug(&client->dev, "+++ remove ov2680 \n"); + } + return ret; +out_free: + ov2680_debug(&client->dev, "+++ out free \n"); + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + return ret; +} + +static struct acpi_device_id ov2680_acpi_match[] = { + {"XXOV2680"}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, ov2680_acpi_match); + + +MODULE_DEVICE_TABLE(i2c, ov2680_id); +static struct i2c_driver ov2680_driver = { + .driver = { + .owner = THIS_MODULE, + .name = OV2680_NAME, + .acpi_match_table = ACPI_PTR(ov2680_acpi_match), + + }, + .probe = ov2680_probe, + .remove = ov2680_remove, + .id_table = ov2680_id, +}; + +static int init_ov2680(void) +{ + return i2c_add_driver(&ov2680_driver); +} + +static void exit_ov2680(void) +{ + + i2c_del_driver(&ov2680_driver); +} + +module_init(init_ov2680); +module_exit(exit_ov2680); + +MODULE_AUTHOR("Jacky Wang "); +MODULE_DESCRIPTION("A low-level driver for OmniVision 2680 sensors"); +MODULE_LICENSE("GPL"); + diff --git a/drivers/staging/media/atomisp/i2c/ov2680.h b/drivers/staging/media/atomisp/i2c/ov2680.h new file mode 100644 index 0000000000000000000000000000000000000000..5ee2cfcc1684a890c806af5b88019b750e0f9eb2 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov2680.h @@ -0,0 +1,940 @@ +/* + * Support for OmniVision OV2680 5M camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __OV2680_H__ +#define __OV2680_H__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define OV2680_NAME "ov2680" +#define OV2680B_NAME "ov2680b" +#define OV2680F_NAME "ov2680f" + +/* Defines for register writes and register array processing */ +#define I2C_MSG_LENGTH 0x2 +#define I2C_RETRY_COUNT 5 + +#define OV2680_FOCAL_LENGTH_NUM 334 /*3.34mm*/ +#define OV2680_FOCAL_LENGTH_DEM 100 +#define OV2680_F_NUMBER_DEFAULT_NUM 24 +#define OV2680_F_NUMBER_DEM 10 + +#define OV2680_BIN_FACTOR_MAX 4 + +#define MAX_FMTS 1 + +/* sensor_mode_data read_mode adaptation */ +#define OV2680_READ_MODE_BINNING_ON 0x0400 +#define OV2680_READ_MODE_BINNING_OFF 0x00 +#define OV2680_INTEGRATION_TIME_MARGIN 8 + +#define OV2680_MAX_EXPOSURE_VALUE 0xFFF1 +#define OV2680_MAX_GAIN_VALUE 0xFF + +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define OV2680_FOCAL_LENGTH_DEFAULT 0x1B70064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define OV2680_F_NUMBER_DEFAULT 0x18000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define OV2680_F_NUMBER_RANGE 0x180a180a +#define OV2680_ID 0x2680 + +#define OV2680_FINE_INTG_TIME_MIN 0 +#define OV2680_FINE_INTG_TIME_MAX_MARGIN 0 +#define OV2680_COARSE_INTG_TIME_MIN 1 +#define OV2680_COARSE_INTG_TIME_MAX_MARGIN 6 + +/* + * OV2680 System control registers + */ +#define OV2680_SW_SLEEP 0x0100 +#define OV2680_SW_RESET 0x0103 +#define OV2680_SW_STREAM 0x0100 + +#define OV2680_SC_CMMN_CHIP_ID_H 0x300A +#define OV2680_SC_CMMN_CHIP_ID_L 0x300B +#define OV2680_SC_CMMN_SCCB_ID 0x302B /* 0x300C*/ +#define OV2680_SC_CMMN_SUB_ID 0x302A /* process, version*/ + +#define OV2680_GROUP_ACCESS 0x3208 /*Bit[7:4] Group control, Bit[3:0] Group ID*/ + +#define OV2680_EXPOSURE_H 0x3500 /*Bit[3:0] Bit[19:16] of exposure, remaining 16 bits lies in Reg0x3501&Reg0x3502*/ +#define OV2680_EXPOSURE_M 0x3501 +#define OV2680_EXPOSURE_L 0x3502 +#define OV2680_AGC_H 0x350A /*Bit[1:0] means Bit[9:8] of gain*/ +#define OV2680_AGC_L 0x350B /*Bit[7:0] of gain*/ + +#define OV2680_HORIZONTAL_START_H 0x3800 /*Bit[11:8]*/ +#define OV2680_HORIZONTAL_START_L 0x3801 /*Bit[7:0]*/ +#define OV2680_VERTICAL_START_H 0x3802 /*Bit[11:8]*/ +#define OV2680_VERTICAL_START_L 0x3803 /*Bit[7:0]*/ +#define OV2680_HORIZONTAL_END_H 0x3804 /*Bit[11:8]*/ +#define OV2680_HORIZONTAL_END_L 0x3805 /*Bit[7:0]*/ +#define OV2680_VERTICAL_END_H 0x3806 /*Bit[11:8]*/ +#define OV2680_VERTICAL_END_L 0x3807 /*Bit[7:0]*/ +#define OV2680_HORIZONTAL_OUTPUT_SIZE_H 0x3808 /*Bit[3:0]*/ +#define OV2680_HORIZONTAL_OUTPUT_SIZE_L 0x3809 /*Bit[7:0]*/ +#define OV2680_VERTICAL_OUTPUT_SIZE_H 0x380a /*Bit[3:0]*/ +#define OV2680_VERTICAL_OUTPUT_SIZE_L 0x380b /*Bit[7:0]*/ +#define OV2680_TIMING_HTS_H 0x380C /*High 8-bit, and low 8-bit HTS address is 0x380d*/ +#define OV2680_TIMING_HTS_L 0x380D /*High 8-bit, and low 8-bit HTS address is 0x380d*/ +#define OV2680_TIMING_VTS_H 0x380e /*High 8-bit, and low 8-bit HTS address is 0x380f*/ +#define OV2680_TIMING_VTS_L 0x380f /*High 8-bit, and low 8-bit HTS address is 0x380f*/ +#define OV2680_FRAME_OFF_NUM 0x4202 + +/*Flip/Mirror*/ +#define OV2680_FLIP_REG 0x3820 +#define OV2680_MIRROR_REG 0x3821 +#define OV2680_FLIP_BIT 1 +#define OV2680_MIRROR_BIT 2 +#define OV2680_FLIP_MIRROR_BIT_ENABLE 4 + +#define OV2680_MWB_RED_GAIN_H 0x5004/*0x3400*/ +#define OV2680_MWB_GREEN_GAIN_H 0x5006/*0x3402*/ +#define OV2680_MWB_BLUE_GAIN_H 0x5008/*0x3404*/ +#define OV2680_MWB_GAIN_MAX 0x0fff + +#define OV2680_START_STREAMING 0x01 +#define OV2680_STOP_STREAMING 0x00 + + +#define OV2680_INVALID_CONFIG 0xffffffff + + +struct regval_list { + u16 reg_num; + u8 value; +}; + +struct ov2680_resolution { + u8 *desc; + const struct ov2680_reg *regs; + int res; + int width; + int height; + int fps; + int pix_clk_freq; + u32 skip_frames; + u16 pixels_per_line; + u16 lines_per_frame; + u8 bin_factor_x; + u8 bin_factor_y; + u8 bin_mode; + bool used; +}; + +struct ov2680_format { + u8 *desc; + u32 pixelformat; + struct ov2680_reg *regs; +}; + + /* + * ov2680 device structure. + */ + struct ov2680_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + struct mutex input_lock; + struct v4l2_ctrl_handler ctrl_handler; + struct camera_sensor_platform_data *platform_data; + struct timespec timestamp_t_focus_abs; + int vt_pix_clk_freq_mhz; + int fmt_idx; + int run_mode; + u8 res; + u8 type; + }; + + enum ov2680_tok_type { + OV2680_8BIT = 0x0001, + OV2680_16BIT = 0x0002, + OV2680_32BIT = 0x0004, + OV2680_TOK_TERM = 0xf000, /* terminating token for reg list */ + OV2680_TOK_DELAY = 0xfe00, /* delay token for reg list */ + OV2680_TOK_MASK = 0xfff0 + }; + + /** + * struct ov2680_reg - MI sensor register format + * @type: type of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ + struct ov2680_reg { + enum ov2680_tok_type type; + u16 reg; + u32 val; /* @set value for read/mod/write, @mask */ + }; + + #define to_ov2680_sensor(x) container_of(x, struct ov2680_device, sd) + + #define OV2680_MAX_WRITE_BUF_SIZE 30 + + struct ov2680_write_buffer { + u16 addr; + u8 data[OV2680_MAX_WRITE_BUF_SIZE]; + }; + + struct ov2680_write_ctrl { + int index; + struct ov2680_write_buffer buffer; + }; + + static const struct i2c_device_id ov2680_id[] = { + {OV2680B_NAME, 0}, + {OV2680F_NAME, 0}, + {} + }; + + static struct ov2680_reg const ov2680_global_setting[] = { + {OV2680_8BIT, 0x0103, 0x01}, + {OV2680_8BIT, 0x3002, 0x00}, + {OV2680_8BIT, 0x3016, 0x1c}, + {OV2680_8BIT, 0x3018, 0x44}, + {OV2680_8BIT, 0x3020, 0x00}, + {OV2680_8BIT, 0x3080, 0x02}, + {OV2680_8BIT, 0x3082, 0x45}, + {OV2680_8BIT, 0x3084, 0x09}, + {OV2680_8BIT, 0x3085, 0x04}, + {OV2680_8BIT, 0x3503, 0x03}, + {OV2680_8BIT, 0x350b, 0x36}, + {OV2680_8BIT, 0x3600, 0xb4}, + {OV2680_8BIT, 0x3603, 0x39}, + {OV2680_8BIT, 0x3604, 0x24}, + {OV2680_8BIT, 0x3605, 0x00}, + {OV2680_8BIT, 0x3620, 0x26}, + {OV2680_8BIT, 0x3621, 0x37}, + {OV2680_8BIT, 0x3622, 0x04}, + {OV2680_8BIT, 0x3628, 0x00}, + {OV2680_8BIT, 0x3705, 0x3c}, + {OV2680_8BIT, 0x370c, 0x50}, + {OV2680_8BIT, 0x370d, 0xc0}, + {OV2680_8BIT, 0x3718, 0x88}, + {OV2680_8BIT, 0x3720, 0x00}, + {OV2680_8BIT, 0x3721, 0x00}, + {OV2680_8BIT, 0x3722, 0x00}, + {OV2680_8BIT, 0x3723, 0x00}, + {OV2680_8BIT, 0x3738, 0x00}, + {OV2680_8BIT, 0x3717, 0x58}, + {OV2680_8BIT, 0x3781, 0x80}, + {OV2680_8BIT, 0x3789, 0x60}, + {OV2680_8BIT, 0x3800, 0x00}, + {OV2680_8BIT, 0x3819, 0x04}, + {OV2680_8BIT, 0x4000, 0x81}, + {OV2680_8BIT, 0x4001, 0x40}, + {OV2680_8BIT, 0x4602, 0x02}, + {OV2680_8BIT, 0x481f, 0x36}, + {OV2680_8BIT, 0x4825, 0x36}, + {OV2680_8BIT, 0x4837, 0x18}, + {OV2680_8BIT, 0x5002, 0x30}, + {OV2680_8BIT, 0x5004, 0x04},//manual awb 1x + {OV2680_8BIT, 0x5005, 0x00}, + {OV2680_8BIT, 0x5006, 0x04}, + {OV2680_8BIT, 0x5007, 0x00}, + {OV2680_8BIT, 0x5008, 0x04}, + {OV2680_8BIT, 0x5009, 0x00}, + {OV2680_8BIT, 0x5080, 0x00}, + {OV2680_8BIT, 0x3701, 0x64}, //add on 14/05/13 + {OV2680_8BIT, 0x3784, 0x0c}, //based OV2680_R1A_AM10.ovt add on 14/06/13 + {OV2680_8BIT, 0x5780, 0x3e}, //based OV2680_R1A_AM10.ovt,Adjust DPC setting (57xx) on 14/06/13 + {OV2680_8BIT, 0x5781, 0x0f}, + {OV2680_8BIT, 0x5782, 0x04}, + {OV2680_8BIT, 0x5783, 0x02}, + {OV2680_8BIT, 0x5784, 0x01}, + {OV2680_8BIT, 0x5785, 0x01}, + {OV2680_8BIT, 0x5786, 0x00}, + {OV2680_8BIT, 0x5787, 0x04}, + {OV2680_8BIT, 0x5788, 0x02}, + {OV2680_8BIT, 0x5789, 0x00}, + {OV2680_8BIT, 0x578a, 0x01}, + {OV2680_8BIT, 0x578b, 0x02}, + {OV2680_8BIT, 0x578c, 0x03}, + {OV2680_8BIT, 0x578d, 0x03}, + {OV2680_8BIT, 0x578e, 0x08}, + {OV2680_8BIT, 0x578f, 0x0c}, + {OV2680_8BIT, 0x5790, 0x08}, + {OV2680_8BIT, 0x5791, 0x04}, + {OV2680_8BIT, 0x5792, 0x00}, + {OV2680_8BIT, 0x5793, 0x00}, + {OV2680_8BIT, 0x5794, 0x03}, //based OV2680_R1A_AM10.ovt,Adjust DPC setting (57xx) on 14/06/13 + {OV2680_8BIT, 0x0100, 0x00}, //stream off + + {OV2680_TOK_TERM, 0, 0} + }; + + + /* + * 176x144 30fps VBlanking 1lane 10Bit (binning) + */ + static struct ov2680_reg const ov2680_QCIF_30fps[] = { + {OV2680_8BIT, 0x3086, 0x01}, + {OV2680_8BIT, 0x3501, 0x24}, + {OV2680_8BIT, 0x3502, 0x40}, + {OV2680_8BIT, 0x370a, 0x23}, + {OV2680_8BIT, 0x3801, 0xa0}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x78}, + {OV2680_8BIT, 0x3804, 0x05}, + {OV2680_8BIT, 0x3805, 0xaf}, + {OV2680_8BIT, 0x3806, 0x04}, + {OV2680_8BIT, 0x3807, 0x47}, + {OV2680_8BIT, 0x3808, 0x00}, + {OV2680_8BIT, 0x3809, 0xC0}, + {OV2680_8BIT, 0x380a, 0x00}, + {OV2680_8BIT, 0x380b, 0xa0}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xb0}, + {OV2680_8BIT, 0x380e, 0x02}, + {OV2680_8BIT, 0x380f, 0x84}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x04}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x04}, + {OV2680_8BIT, 0x3814, 0x31}, + {OV2680_8BIT, 0x3815, 0x31}, + {OV2680_8BIT, 0x4000, 0x81}, + {OV2680_8BIT, 0x4001, 0x40}, + {OV2680_8BIT, 0x4008, 0x00}, + {OV2680_8BIT, 0x4009, 0x03}, + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {OV2680_8BIT, 0x5704, 0x10}, + {OV2680_8BIT, 0x5705, 0xa0}, + {OV2680_8BIT, 0x5706, 0x0c}, + {OV2680_8BIT, 0x5707, 0x78}, + {OV2680_8BIT, 0x3820, 0xc2}, + {OV2680_8BIT, 0x3821, 0x01}, + // {OV2680_8BIT, 0x5090, 0x0c}, + {OV2680_TOK_TERM, 0, 0} + }; + + /* + * 352x288 30fps VBlanking 1lane 10Bit (binning) + */ + static struct ov2680_reg const ov2680_CIF_30fps[] = { + {OV2680_8BIT, 0x3086, 0x01}, + {OV2680_8BIT, 0x3501, 0x24}, + {OV2680_8BIT, 0x3502, 0x40}, + {OV2680_8BIT, 0x370a, 0x23}, + {OV2680_8BIT, 0x3801, 0xa0}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x78}, + {OV2680_8BIT, 0x3804, 0x03}, + {OV2680_8BIT, 0x3805, 0x8f}, + {OV2680_8BIT, 0x3806, 0x02}, + {OV2680_8BIT, 0x3807, 0xe7}, + {OV2680_8BIT, 0x3808, 0x01}, + {OV2680_8BIT, 0x3809, 0x70}, + {OV2680_8BIT, 0x380a, 0x01}, + {OV2680_8BIT, 0x380b, 0x30}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xb0}, + {OV2680_8BIT, 0x380e, 0x02}, + {OV2680_8BIT, 0x380f, 0x84}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x04}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x04}, + {OV2680_8BIT, 0x3814, 0x31}, + {OV2680_8BIT, 0x3815, 0x31}, + {OV2680_8BIT, 0x4008, 0x00}, + {OV2680_8BIT, 0x4009, 0x03}, + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {OV2680_8BIT, 0x5704, 0x10}, + {OV2680_8BIT, 0x5705, 0xa0}, + {OV2680_8BIT, 0x5706, 0x0c}, + {OV2680_8BIT, 0x5707, 0x78}, + {OV2680_8BIT, 0x3820, 0xc2}, + {OV2680_8BIT, 0x3821, 0x01}, + // {OV2680_8BIT, 0x5090, 0x0c}, + {OV2680_TOK_TERM, 0, 0} + }; + + /* + * 336x256 30fps VBlanking 1lane 10Bit (binning) + */ + static struct ov2680_reg const ov2680_QVGA_30fps[] = { + {OV2680_8BIT, 0x3086, 0x01}, + {OV2680_8BIT, 0x3501, 0x24}, + {OV2680_8BIT, 0x3502, 0x40}, + {OV2680_8BIT, 0x370a, 0x23}, + {OV2680_8BIT, 0x3801, 0xa0}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x78}, + {OV2680_8BIT, 0x3804, 0x03}, + {OV2680_8BIT, 0x3805, 0x4f}, + {OV2680_8BIT, 0x3806, 0x02}, + {OV2680_8BIT, 0x3807, 0x87}, + {OV2680_8BIT, 0x3808, 0x01}, + {OV2680_8BIT, 0x3809, 0x50}, + {OV2680_8BIT, 0x380a, 0x01}, + {OV2680_8BIT, 0x380b, 0x00}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xb0}, + {OV2680_8BIT, 0x380e, 0x02}, + {OV2680_8BIT, 0x380f, 0x84}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x04}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x04}, + {OV2680_8BIT, 0x3814, 0x31}, + {OV2680_8BIT, 0x3815, 0x31}, + {OV2680_8BIT, 0x4008, 0x00}, + {OV2680_8BIT, 0x4009, 0x03}, + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {OV2680_8BIT, 0x5704, 0x10}, + {OV2680_8BIT, 0x5705, 0xa0}, + {OV2680_8BIT, 0x5706, 0x0c}, + {OV2680_8BIT, 0x5707, 0x78}, + {OV2680_8BIT, 0x3820, 0xc2}, + {OV2680_8BIT, 0x3821, 0x01}, + // {OV2680_8BIT, 0x5090, 0x0c}, + {OV2680_TOK_TERM, 0, 0} + }; + + + /* + * 656x496 30fps VBlanking 1lane 10Bit (binning) + */ + static struct ov2680_reg const ov2680_656x496_30fps[] = { + {OV2680_8BIT, 0x3086, 0x01}, + {OV2680_8BIT, 0x3501, 0x24}, + {OV2680_8BIT, 0x3502, 0x40}, + {OV2680_8BIT, 0x370a, 0x23}, + {OV2680_8BIT, 0x3801, 0xa0}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x78}, + {OV2680_8BIT, 0x3804, 0x05}, + {OV2680_8BIT, 0x3805, 0xcf}, + {OV2680_8BIT, 0x3806, 0x04}, + {OV2680_8BIT, 0x3807, 0x67}, + {OV2680_8BIT, 0x3808, 0x02}, + {OV2680_8BIT, 0x3809, 0x90}, + {OV2680_8BIT, 0x380a, 0x01}, + {OV2680_8BIT, 0x380b, 0xf0}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xb0}, + {OV2680_8BIT, 0x380e, 0x02}, + {OV2680_8BIT, 0x380f, 0x84}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x04}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x04}, + {OV2680_8BIT, 0x3814, 0x31}, + {OV2680_8BIT, 0x3815, 0x31}, + {OV2680_8BIT, 0x4008, 0x00}, + {OV2680_8BIT, 0x4009, 0x03}, + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {OV2680_8BIT, 0x5704, 0x10}, + {OV2680_8BIT, 0x5705, 0xa0}, + {OV2680_8BIT, 0x5706, 0x0c}, + {OV2680_8BIT, 0x5707, 0x78}, + {OV2680_8BIT, 0x3820, 0xc2}, + {OV2680_8BIT, 0x3821, 0x01}, + // {OV2680_8BIT, 0x5090, 0x0c}, + {OV2680_TOK_TERM, 0, 0} + }; + /* + * 800x600 30fps VBlanking 1lane 10Bit (binning) + */ + static struct ov2680_reg const ov2680_720x592_30fps[] = { + {OV2680_8BIT, 0x3086, 0x01}, + {OV2680_8BIT, 0x3501, 0x26}, + {OV2680_8BIT, 0x3502, 0x40}, + {OV2680_8BIT, 0x370a, 0x23}, + {OV2680_8BIT, 0x3801, 0x00}, // X_ADDR_START; + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x00}, // Y_ADDR_START; + {OV2680_8BIT, 0x3804, 0x05}, + {OV2680_8BIT, 0x3805, 0xaf}, // X_ADDR_END; + {OV2680_8BIT, 0x3806, 0x04}, + {OV2680_8BIT, 0x3807, 0xaf}, // Y_ADDR_END; + {OV2680_8BIT, 0x3808, 0x02}, + {OV2680_8BIT, 0x3809, 0xd0}, // X_OUTPUT_SIZE; + {OV2680_8BIT, 0x380a, 0x02}, + {OV2680_8BIT, 0x380b, 0x50}, // Y_OUTPUT_SIZE; + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xac}, // HTS; + {OV2680_8BIT, 0x380e, 0x02}, + {OV2680_8BIT, 0x380f, 0x84}, // VTS; + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x00}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x00}, + {OV2680_8BIT, 0x3814, 0x31}, + {OV2680_8BIT, 0x3815, 0x31}, + {OV2680_8BIT, 0x4008, 0x00}, + {OV2680_8BIT, 0x4009, 0x03}, + {OV2680_8BIT, 0x5708, 0x00}, + {OV2680_8BIT, 0x5704, 0x02}, + {OV2680_8BIT, 0x5705, 0xd0}, // X_WIN; + {OV2680_8BIT, 0x5706, 0x02}, + {OV2680_8BIT, 0x5707, 0x50}, // Y_WIN; + {OV2680_8BIT, 0x3820, 0xc2}, // FLIP_FORMAT; + {OV2680_8BIT, 0x3821, 0x01}, // MIRROR_FORMAT; + {OV2680_8BIT, 0x5090, 0x00}, // PRE ISP CTRL16, default value is 0x0C; + // BIT[3]: Mirror order, BG or GB; + // BIT[2]: Flip order, BR or RB; + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_TOK_TERM, 0, 0} + }; + + /* + * 800x600 30fps VBlanking 1lane 10Bit (binning) + */ + static struct ov2680_reg const ov2680_800x600_30fps[] = { + {OV2680_8BIT, 0x3086, 0x01}, + {OV2680_8BIT, 0x3501, 0x26}, + {OV2680_8BIT, 0x3502, 0x40}, + {OV2680_8BIT, 0x370a, 0x23}, + {OV2680_8BIT, 0x3801, 0x00}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x00}, + {OV2680_8BIT, 0x3804, 0x06}, + {OV2680_8BIT, 0x3805, 0x4f}, + {OV2680_8BIT, 0x3806, 0x04}, + {OV2680_8BIT, 0x3807, 0xbf}, + {OV2680_8BIT, 0x3808, 0x03}, + {OV2680_8BIT, 0x3809, 0x20}, + {OV2680_8BIT, 0x380a, 0x02}, + {OV2680_8BIT, 0x380b, 0x58}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xac}, + {OV2680_8BIT, 0x380e, 0x02}, + {OV2680_8BIT, 0x380f, 0x84}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x00}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x00}, + {OV2680_8BIT, 0x3814, 0x31}, + {OV2680_8BIT, 0x3815, 0x31}, + {OV2680_8BIT, 0x5708, 0x00}, + {OV2680_8BIT, 0x5704, 0x03}, + {OV2680_8BIT, 0x5705, 0x20}, + {OV2680_8BIT, 0x5706, 0x02}, + {OV2680_8BIT, 0x5707, 0x58}, + {OV2680_8BIT, 0x3820, 0xc2}, + {OV2680_8BIT, 0x3821, 0x01}, + {OV2680_8BIT, 0x5090, 0x00}, + {OV2680_8BIT, 0x4008, 0x00}, + {OV2680_8BIT, 0x4009, 0x03}, + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_TOK_TERM, 0, 0} + }; + + /* + * 720p=1280*720 30fps VBlanking 1lane 10Bit (no-Scaling) + */ + static struct ov2680_reg const ov2680_720p_30fps[] = { + {OV2680_8BIT, 0x3086, 0x00}, + {OV2680_8BIT, 0x3501, 0x48}, + {OV2680_8BIT, 0x3502, 0xe0}, + {OV2680_8BIT, 0x370a, 0x21}, + {OV2680_8BIT, 0x3801, 0xa0}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0xf2}, + {OV2680_8BIT, 0x3804, 0x05}, + {OV2680_8BIT, 0x3805, 0xbf}, + {OV2680_8BIT, 0x3806, 0x03}, + {OV2680_8BIT, 0x3807, 0xdd}, + {OV2680_8BIT, 0x3808, 0x05}, + {OV2680_8BIT, 0x3809, 0x10}, + {OV2680_8BIT, 0x380a, 0x02}, + {OV2680_8BIT, 0x380b, 0xe0}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xa8}, + {OV2680_8BIT, 0x380e, 0x05}, + {OV2680_8BIT, 0x380f, 0x0e}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x08}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x06}, + {OV2680_8BIT, 0x3814, 0x11}, + {OV2680_8BIT, 0x3815, 0x11}, + {OV2680_8BIT, 0x4008, 0x02}, + {OV2680_8BIT, 0x4009, 0x09}, + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {OV2680_8BIT, 0x5704, 0x10}, + {OV2680_8BIT, 0x5705, 0xa0}, + {OV2680_8BIT, 0x5706, 0x0c}, + {OV2680_8BIT, 0x5707, 0x78}, + {OV2680_8BIT, 0x3820, 0xc0}, + {OV2680_8BIT, 0x3821, 0x00}, + // {OV2680_8BIT, 0x5090, 0x0c}, + {OV2680_TOK_TERM, 0, 0} + }; + + /* + * 1296x976 30fps VBlanking 1lane 10Bit(no-scaling) + */ + static struct ov2680_reg const ov2680_1296x976_30fps[] = { + {OV2680_8BIT, 0x3086, 0x00}, + {OV2680_8BIT, 0x3501, 0x48}, + {OV2680_8BIT, 0x3502, 0xe0}, + {OV2680_8BIT, 0x370a, 0x21}, + {OV2680_8BIT, 0x3801, 0xa0}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x78}, + {OV2680_8BIT, 0x3804, 0x05}, + {OV2680_8BIT, 0x3805, 0xbf}, + {OV2680_8BIT, 0x3806, 0x04}, + {OV2680_8BIT, 0x3807, 0x57}, + {OV2680_8BIT, 0x3808, 0x05}, + {OV2680_8BIT, 0x3809, 0x10}, + {OV2680_8BIT, 0x380a, 0x03}, + {OV2680_8BIT, 0x380b, 0xd0}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xa8}, + {OV2680_8BIT, 0x380e, 0x05}, + {OV2680_8BIT, 0x380f, 0x0e}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x08}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x08}, + {OV2680_8BIT, 0x3814, 0x11}, + {OV2680_8BIT, 0x3815, 0x11}, + {OV2680_8BIT, 0x4008, 0x02}, + {OV2680_8BIT, 0x4009, 0x09}, + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {OV2680_8BIT, 0x5704, 0x10}, + {OV2680_8BIT, 0x5705, 0xa0}, + {OV2680_8BIT, 0x5706, 0x0c}, + {OV2680_8BIT, 0x5707, 0x78}, + {OV2680_8BIT, 0x3820, 0xc0}, + {OV2680_8BIT, 0x3821, 0x00}, //miror/flip + // {OV2680_8BIT, 0x5090, 0x0c}, + {OV2680_TOK_TERM, 0, 0} + }; + + /* + * 1456*1096 30fps VBlanking 1lane 10bit(no-scaling) + */ + static struct ov2680_reg const ov2680_1456x1096_30fps[]= { + {OV2680_8BIT, 0x3086, 0x00}, + {OV2680_8BIT, 0x3501, 0x48}, + {OV2680_8BIT, 0x3502, 0xe0}, + {OV2680_8BIT, 0x370a, 0x21}, + {OV2680_8BIT, 0x3801, 0x90}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x78}, + {OV2680_8BIT, 0x3804, 0x06}, + {OV2680_8BIT, 0x3805, 0x4f}, + {OV2680_8BIT, 0x3806, 0x04}, + {OV2680_8BIT, 0x3807, 0xC0}, + {OV2680_8BIT, 0x3808, 0x05}, + {OV2680_8BIT, 0x3809, 0xb0}, + {OV2680_8BIT, 0x380a, 0x04}, + {OV2680_8BIT, 0x380b, 0x48}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xa8}, + {OV2680_8BIT, 0x380e, 0x05}, + {OV2680_8BIT, 0x380f, 0x0e}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x08}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x00}, + {OV2680_8BIT, 0x3814, 0x11}, + {OV2680_8BIT, 0x3815, 0x11}, + {OV2680_8BIT, 0x4008, 0x02}, + {OV2680_8BIT, 0x4009, 0x09}, + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_8BIT, 0x5708, 0x00}, //add for full size flip off and mirror off 2014/09/11 + {OV2680_8BIT, 0x5704, 0x10}, + {OV2680_8BIT, 0x5705, 0xa0}, + {OV2680_8BIT, 0x5706, 0x0c}, + {OV2680_8BIT, 0x5707, 0x78}, + {OV2680_8BIT, 0x3820, 0xc0}, + {OV2680_8BIT, 0x3821, 0x00}, + // {OV2680_8BIT, 0x5090, 0x0c}, + {OV2680_TOK_TERM, 0, 0} + }; + + /* + *1616x916 30fps VBlanking 1lane 10bit + */ + + static struct ov2680_reg const ov2680_1616x916_30fps[] = { + + {OV2680_8BIT, 0x3086, 0x00}, + {OV2680_8BIT, 0x3501, 0x48}, + {OV2680_8BIT, 0x3502, 0xe0}, + {OV2680_8BIT, 0x370a, 0x21}, + {OV2680_8BIT, 0x3801, 0x00}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x96}, + {OV2680_8BIT, 0x3804, 0x06}, + {OV2680_8BIT, 0x3805, 0x4f}, + {OV2680_8BIT, 0x3806, 0x04}, + {OV2680_8BIT, 0x3807, 0x39}, + {OV2680_8BIT, 0x3808, 0x06}, + {OV2680_8BIT, 0x3809, 0x50}, + {OV2680_8BIT, 0x380a, 0x03}, + {OV2680_8BIT, 0x380b, 0x94}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xa8}, + {OV2680_8BIT, 0x380e, 0x05}, + {OV2680_8BIT, 0x380f, 0x0e}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x00}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x08}, + {OV2680_8BIT, 0x3814, 0x11}, + {OV2680_8BIT, 0x3815, 0x11}, + {OV2680_8BIT, 0x4008, 0x02}, + {OV2680_8BIT, 0x4009, 0x09}, + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_8BIT, 0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11 + {OV2680_8BIT, 0x5704, 0x06}, + {OV2680_8BIT, 0x5705, 0x50}, + {OV2680_8BIT, 0x5706, 0x03}, + {OV2680_8BIT, 0x5707, 0x94}, + {OV2680_8BIT, 0x3820, 0xc0}, + {OV2680_8BIT, 0x3821, 0x00}, + // {OV2680_8BIT, 0x5090, 0x0C}, + {OV2680_TOK_TERM, 0, 0} + }; + + /* + * 1612x1212 30fps VBlanking 1lane 10Bit + */ + static struct ov2680_reg const ov2680_1616x1082_30fps[] = { + {OV2680_8BIT, 0x3086, 0x00}, + {OV2680_8BIT, 0x3501, 0x48}, + {OV2680_8BIT, 0x3502, 0xe0}, + {OV2680_8BIT, 0x370a, 0x21}, + {OV2680_8BIT, 0x3801, 0x00}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x86}, + {OV2680_8BIT, 0x3804, 0x06}, + {OV2680_8BIT, 0x3805, 0x4f}, + {OV2680_8BIT, 0x3806, 0x04}, + {OV2680_8BIT, 0x3807, 0xbf}, + {OV2680_8BIT, 0x3808, 0x06}, + {OV2680_8BIT, 0x3809, 0x50}, + {OV2680_8BIT, 0x380a, 0x04}, + {OV2680_8BIT, 0x380b, 0x3a}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xa8}, + {OV2680_8BIT, 0x380e, 0x05}, + {OV2680_8BIT, 0x380f, 0x0e}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x00}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x00}, + {OV2680_8BIT, 0x3814, 0x11}, + {OV2680_8BIT, 0x3815, 0x11}, + {OV2680_8BIT, 0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11 + {OV2680_8BIT, 0x5704, 0x06}, + {OV2680_8BIT, 0x5705, 0x50}, + {OV2680_8BIT, 0x5706, 0x04}, + {OV2680_8BIT, 0x5707, 0x3a}, + {OV2680_8BIT, 0x3820, 0xc0}, + {OV2680_8BIT, 0x3821, 0x00}, + // {OV2680_8BIT, 0x5090, 0x0C}, + {OV2680_8BIT, 0x4008, 0x02}, + {OV2680_8BIT, 0x4009, 0x09}, + {OV2680_8BIT, 0x5081, 0x41}, + {OV2680_TOK_TERM, 0, 0} + }; + /* + * 1616x1216 30fps VBlanking 1lane 10Bit + */ + static struct ov2680_reg const ov2680_1616x1216_30fps[] = { + {OV2680_8BIT, 0x3086, 0x00}, + {OV2680_8BIT, 0x3501, 0x48}, + {OV2680_8BIT, 0x3502, 0xe0}, + {OV2680_8BIT, 0x370a, 0x21}, + {OV2680_8BIT, 0x3801, 0x00}, + {OV2680_8BIT, 0x3802, 0x00}, + {OV2680_8BIT, 0x3803, 0x00}, + {OV2680_8BIT, 0x3804, 0x06}, + {OV2680_8BIT, 0x3805, 0x4f}, + {OV2680_8BIT, 0x3806, 0x04}, + {OV2680_8BIT, 0x3807, 0xbf}, + {OV2680_8BIT, 0x3808, 0x06}, + {OV2680_8BIT, 0x3809, 0x50},//50},//4line for mirror and flip + {OV2680_8BIT, 0x380a, 0x04}, + {OV2680_8BIT, 0x380b, 0xc0},//c0}, + {OV2680_8BIT, 0x380c, 0x06}, + {OV2680_8BIT, 0x380d, 0xa8}, + {OV2680_8BIT, 0x380e, 0x05}, + {OV2680_8BIT, 0x380f, 0x0e}, + {OV2680_8BIT, 0x3810, 0x00}, + {OV2680_8BIT, 0x3811, 0x00}, + {OV2680_8BIT, 0x3812, 0x00}, + {OV2680_8BIT, 0x3813, 0x00}, + {OV2680_8BIT, 0x3814, 0x11}, + {OV2680_8BIT, 0x3815, 0x11}, + {OV2680_8BIT, 0x4008, 0x00}, + {OV2680_8BIT, 0x4009, 0x0b}, + {OV2680_8BIT, 0x5081, 0x01}, + {OV2680_8BIT, 0x5708, 0x01}, //add for full size flip off and mirror off 2014/09/11 + {OV2680_8BIT, 0x5704, 0x06}, + {OV2680_8BIT, 0x5705, 0x50}, + {OV2680_8BIT, 0x5706, 0x04}, + {OV2680_8BIT, 0x5707, 0xcc}, + {OV2680_8BIT, 0x3820, 0xc0}, + {OV2680_8BIT, 0x3821, 0x00}, + // {OV2680_8BIT, 0x5090, 0x0C}, + {OV2680_TOK_TERM, 0, 0} + }; + + static struct ov2680_resolution ov2680_res_preview[] = { + { + .desc = "ov2680_1616x1216_30fps", + .width = 1616, + .height = 1216, + .pix_clk_freq = 66, + .fps = 30, + .used = 0, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_1616x1216_30fps, + }, + { + .desc = "ov2680_1616x916_30fps", + .width = 1616, + .height = 916, + .fps = 30, + .pix_clk_freq = 66, + .used = 0, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_1616x916_30fps, + }, +}; +#define N_RES_PREVIEW (ARRAY_SIZE(ov2680_res_preview)) + +static struct ov2680_resolution ov2680_res_still[] = { + { + .desc = "ov2680_1616x1216_30fps", + .width = 1616, + .height = 1216, + .pix_clk_freq = 66, + .fps = 30, + .used = 0, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_1616x1216_30fps, + }, + { + .desc = "ov2680_1616x916_30fps", + .width = 1616, + .height = 916, + .fps = 30, + .pix_clk_freq = 66, + .used = 0, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_1616x916_30fps, + }, +}; +#define N_RES_STILL (ARRAY_SIZE(ov2680_res_still)) + +static struct ov2680_resolution ov2680_res_video[] = { + { + .desc = "ov2680_1616x1216_30fps", + .width = 1616, + .height = 1216, + .pix_clk_freq = 66, + .fps = 30, + .used = 0, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_1616x1216_30fps, + }, + { + .desc = "ov2680_720p_30fps", + .width = 1616, + .height = 916, + .fps = 30, + .pix_clk_freq = 66, + .used = 0, + .pixels_per_line = 1698,//1704, + .lines_per_frame = 1294, + .bin_factor_x = 0, + .bin_factor_y = 0, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2680_1616x916_30fps, + }, +}; +#define N_RES_VIDEO (ARRAY_SIZE(ov2680_res_video)) + +static struct ov2680_resolution *ov2680_res = ov2680_res_preview; +static int N_RES = N_RES_PREVIEW; + + +#endif diff --git a/drivers/staging/media/atomisp/i2c/ov2722.c b/drivers/staging/media/atomisp/i2c/ov2722.c new file mode 100644 index 0000000000000000000000000000000000000000..ec4938d670cc0d2f7edb09af848a2d2ed08dd5ed --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov2722.c @@ -0,0 +1,1377 @@ +/* + * Support for OmniVision OV2722 1080p HD camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ov2722.h" + +/* i2c read/write stuff */ +static int ov2722_read_reg(struct i2c_client *client, + u16 data_length, u16 reg, u16 *val) +{ + int err; + struct i2c_msg msg[2]; + unsigned char data[6]; + + if (!client->adapter) { + dev_err(&client->dev, "%s error, no client->adapter\n", + __func__); + return -ENODEV; + } + + if (data_length != OV2722_8BIT && data_length != OV2722_16BIT + && data_length != OV2722_32BIT) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + memset(msg, 0 , sizeof(msg)); + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = I2C_MSG_LENGTH; + msg[0].buf = data; + + /* high byte goes out first */ + data[0] = (u8)(reg >> 8); + data[1] = (u8)(reg & 0xff); + + msg[1].addr = client->addr; + msg[1].len = data_length; + msg[1].flags = I2C_M_RD; + msg[1].buf = data; + + err = i2c_transfer(client->adapter, msg, 2); + if (err != 2) { + if (err >= 0) + err = -EIO; + dev_err(&client->dev, + "read from offset 0x%x error %d", reg, err); + return err; + } + + *val = 0; + /* high byte comes first */ + if (data_length == OV2722_8BIT) + *val = (u8)data[0]; + else if (data_length == OV2722_16BIT) + *val = be16_to_cpu(*(u16 *)&data[0]); + else + *val = be32_to_cpu(*(u32 *)&data[0]); + + return 0; +} + +static int ov2722_i2c_write(struct i2c_client *client, u16 len, u8 *data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = len; + msg.buf = data; + ret = i2c_transfer(client->adapter, &msg, 1); + + return ret == num_msg ? 0 : -EIO; +} + +static int ov2722_write_reg(struct i2c_client *client, u16 data_length, + u16 reg, u16 val) +{ + int ret; + unsigned char data[4] = {0}; + u16 *wreg = (u16 *)data; + const u16 len = data_length + sizeof(u16); /* 16-bit address + data */ + + if (data_length != OV2722_8BIT && data_length != OV2722_16BIT) { + dev_err(&client->dev, + "%s error, invalid data_length\n", __func__); + return -EINVAL; + } + + /* high byte goes out first */ + *wreg = cpu_to_be16(reg); + + if (data_length == OV2722_8BIT) { + data[2] = (u8)(val); + } else { + /* OV2722_16BIT */ + u16 *wdata = (u16 *)&data[2]; + *wdata = cpu_to_be16(val); + } + + ret = ov2722_i2c_write(client, len, data); + if (ret) + dev_err(&client->dev, + "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, ret); + + return ret; +} + +/* + * ov2722_write_reg_array - Initializes a list of OV2722 registers + * @client: i2c driver client structure + * @reglist: list of registers to be written + * + * This function initializes a list of registers. When consecutive addresses + * are found in a row on the list, this function creates a buffer and sends + * consecutive data in a single i2c_transfer(). + * + * __ov2722_flush_reg_array, __ov2722_buf_reg_array() and + * __ov2722_write_reg_is_consecutive() are internal functions to + * ov2722_write_reg_array_fast() and should be not used anywhere else. + * + */ + +static int __ov2722_flush_reg_array(struct i2c_client *client, + struct ov2722_write_ctrl *ctrl) +{ + u16 size; + + if (ctrl->index == 0) + return 0; + + size = sizeof(u16) + ctrl->index; /* 16-bit address + data */ + ctrl->buffer.addr = cpu_to_be16(ctrl->buffer.addr); + ctrl->index = 0; + + return ov2722_i2c_write(client, size, (u8 *)&ctrl->buffer); +} + +static int __ov2722_buf_reg_array(struct i2c_client *client, + struct ov2722_write_ctrl *ctrl, + const struct ov2722_reg *next) +{ + int size; + u16 *data16; + + switch (next->type) { + case OV2722_8BIT: + size = 1; + ctrl->buffer.data[ctrl->index] = (u8)next->val; + break; + case OV2722_16BIT: + size = 2; + data16 = (u16 *)&ctrl->buffer.data[ctrl->index]; + *data16 = cpu_to_be16((u16)next->val); + break; + default: + return -EINVAL; + } + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->reg; + + ctrl->index += size; + + /* + * Buffer cannot guarantee free space for u32? Better flush it to avoid + * possible lack of memory for next item. + */ + if (ctrl->index + sizeof(u16) >= OV2722_MAX_WRITE_BUF_SIZE) + return __ov2722_flush_reg_array(client, ctrl); + + return 0; +} + +static int __ov2722_write_reg_is_consecutive(struct i2c_client *client, + struct ov2722_write_ctrl *ctrl, + const struct ov2722_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->reg; +} + +static int ov2722_write_reg_array(struct i2c_client *client, + const struct ov2722_reg *reglist) +{ + const struct ov2722_reg *next = reglist; + struct ov2722_write_ctrl ctrl; + int err; + + ctrl.index = 0; + for (; next->type != OV2722_TOK_TERM; next++) { + switch (next->type & OV2722_TOK_MASK) { + case OV2722_TOK_DELAY: + err = __ov2722_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceed. + */ + if (!__ov2722_write_reg_is_consecutive(client, &ctrl, + next)) { + err = __ov2722_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __ov2722_buf_reg_array(client, &ctrl, next); + if (err) { + dev_err(&client->dev, "%s: write error, aborted\n", + __func__); + return err; + } + break; + } + } + + return __ov2722_flush_reg_array(client, &ctrl); +} +static int ov2722_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + *val = (OV2722_FOCAL_LENGTH_NUM << 16) | OV2722_FOCAL_LENGTH_DEM; + return 0; +} + +static int ov2722_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /*const f number for imx*/ + *val = (OV2722_F_NUMBER_DEFAULT_NUM << 16) | OV2722_F_NUMBER_DEM; + return 0; +} + +static int ov2722_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + *val = (OV2722_F_NUMBER_DEFAULT_NUM << 24) | + (OV2722_F_NUMBER_DEM << 16) | + (OV2722_F_NUMBER_DEFAULT_NUM << 8) | OV2722_F_NUMBER_DEM; + return 0; +} + +static int ov2722_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct ov2722_resolution *res) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov2722_device *dev = NULL; + struct atomisp_sensor_mode_data *buf = &info->data; + const unsigned int ext_clk_freq_hz = 19200000; + const unsigned int pll_invariant_div = 10; + unsigned int pix_clk_freq_hz; + u16 pre_pll_clk_div; + u16 pll_multiplier; + u16 op_pix_clk_div; + u16 reg_val; + int ret; + + if (info == NULL) + return -EINVAL; + + dev = to_ov2722_sensor(sd); + + /* pixel clock calculattion */ + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_SC_CMMN_PLL_CTRL3, &pre_pll_clk_div); + if (ret) + return ret; + + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_SC_CMMN_PLL_MULTIPLIER, &pll_multiplier); + if (ret) + return ret; + + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_SC_CMMN_PLL_DEBUG_OPT, &op_pix_clk_div); + if (ret) + return ret; + + pre_pll_clk_div = (pre_pll_clk_div & 0x70) >> 4; + if (0 == pre_pll_clk_div) + return -EINVAL; + + pll_multiplier = pll_multiplier & 0x7f; + op_pix_clk_div = op_pix_clk_div & 0x03; + pix_clk_freq_hz = ext_clk_freq_hz / pre_pll_clk_div * pll_multiplier + * op_pix_clk_div/pll_invariant_div; + + dev->vt_pix_clk_freq_mhz = pix_clk_freq_hz; + buf->vt_pix_clk_freq_mhz = pix_clk_freq_hz; + + /* get integration time */ + buf->coarse_integration_time_min = OV2722_COARSE_INTG_TIME_MIN; + buf->coarse_integration_time_max_margin = + OV2722_COARSE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_min = OV2722_FINE_INTG_TIME_MIN; + buf->fine_integration_time_max_margin = + OV2722_FINE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_def = OV2722_FINE_INTG_TIME_MIN; + buf->frame_length_lines = res->lines_per_frame; + buf->line_length_pck = res->pixels_per_line; + buf->read_mode = res->bin_mode; + + /* get the cropping and output resolution to ISP for this mode. */ + ret = ov2722_read_reg(client, OV2722_16BIT, + OV2722_H_CROP_START_H, ®_val); + if (ret) + return ret; + buf->crop_horizontal_start = reg_val; + + ret = ov2722_read_reg(client, OV2722_16BIT, + OV2722_V_CROP_START_H, ®_val); + if (ret) + return ret; + buf->crop_vertical_start = reg_val; + + ret = ov2722_read_reg(client, OV2722_16BIT, + OV2722_H_CROP_END_H, ®_val); + if (ret) + return ret; + buf->crop_horizontal_end = reg_val; + + ret = ov2722_read_reg(client, OV2722_16BIT, + OV2722_V_CROP_END_H, ®_val); + if (ret) + return ret; + buf->crop_vertical_end = reg_val; + + ret = ov2722_read_reg(client, OV2722_16BIT, + OV2722_H_OUTSIZE_H, ®_val); + if (ret) + return ret; + buf->output_width = reg_val; + + ret = ov2722_read_reg(client, OV2722_16BIT, + OV2722_V_OUTSIZE_H, ®_val); + if (ret) + return ret; + buf->output_height = reg_val; + + buf->binning_factor_x = res->bin_factor_x ? + res->bin_factor_x : 1; + buf->binning_factor_y = res->bin_factor_y ? + res->bin_factor_y : 1; + return 0; +} + +static long __ov2722_set_exposure(struct v4l2_subdev *sd, int coarse_itg, + int gain, int digitgain) + +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov2722_device *dev = to_ov2722_sensor(sd); + u16 hts, vts; + int ret; + + dev_dbg(&client->dev, "set_exposure without group hold\n"); + + /* clear VTS_DIFF on manual mode */ + ret = ov2722_write_reg(client, OV2722_16BIT, OV2722_VTS_DIFF_H, 0); + if (ret) + return ret; + + hts = dev->pixels_per_line; + vts = dev->lines_per_frame; + + if ((coarse_itg + OV2722_COARSE_INTG_TIME_MAX_MARGIN) > vts) + vts = coarse_itg + OV2722_COARSE_INTG_TIME_MAX_MARGIN; + + coarse_itg <<= 4; + digitgain <<= 2; + + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_VTS_H, vts); + if (ret) + return ret; + + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_HTS_H, hts); + if (ret) + return ret; + + /* set exposure */ + ret = ov2722_write_reg(client, OV2722_8BIT, + OV2722_AEC_PK_EXPO_L, + coarse_itg & 0xff); + if (ret) + return ret; + + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_AEC_PK_EXPO_H, + (coarse_itg >> 8) & 0xfff); + if (ret) + return ret; + + /* set analog gain */ + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_AGC_ADJ_H, gain); + if (ret) + return ret; + + /* set digital gain */ + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_MWB_GAIN_R_H, digitgain); + if (ret) + return ret; + + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_MWB_GAIN_G_H, digitgain); + if (ret) + return ret; + + ret = ov2722_write_reg(client, OV2722_16BIT, + OV2722_MWB_GAIN_B_H, digitgain); + + return ret; +} + +static int ov2722_set_exposure(struct v4l2_subdev *sd, int exposure, + int gain, int digitgain) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __ov2722_set_exposure(sd, exposure, gain, digitgain); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static long ov2722_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + int exp = exposure->integration_time[0]; + int gain = exposure->gain[0]; + int digitgain = exposure->gain[1]; + + /* we should not accept the invalid value below. */ + if (gain == 0) { + struct i2c_client *client = v4l2_get_subdevdata(sd); + v4l2_err(client, "%s: invalid value\n", __func__); + return -EINVAL; + } + + return ov2722_set_exposure(sd, exp, gain, digitgain); +} + +static long ov2722_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return ov2722_s_exposure(sd, arg); + default: + return -EINVAL; + } + return 0; +} + +/* This returns the exposure time being used. This should only be used + for filling in EXIF data, not for actual image processing. */ +static int ov2722_q_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 reg_v, reg_v2; + int ret; + + /* get exposure */ + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_AEC_PK_EXPO_L, + ®_v); + if (ret) + goto err; + + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_AEC_PK_EXPO_M, + ®_v2); + if (ret) + goto err; + + reg_v += reg_v2 << 8; + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_AEC_PK_EXPO_H, + ®_v2); + if (ret) + goto err; + + *value = reg_v + (((u32)reg_v2 << 16)); +err: + return ret; +} + +static int ov2722_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov2722_device *dev = + container_of(ctrl->handler, struct ov2722_device, ctrl_handler); + int ret = 0; + unsigned int val; + switch (ctrl->id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = ov2722_q_exposure(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = ov2722_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = ov2722_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = ov2722_g_fnumber_range(&dev->sd, &ctrl->val); + break; + case V4L2_CID_LINK_FREQ: + val = ov2722_res[dev->fmt_idx].mipi_freq; + if (val == 0) + return -EINVAL; + + ctrl->val = val * 1000; /* To Hz */ + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .g_volatile_ctrl = ov2722_g_volatile_ctrl +}; + +struct v4l2_ctrl_config ov2722_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .min = 0x0, + .max = 0xffff, + .step = 0x01, + .def = 0x00, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focal length", + .min = OV2722_FOCAL_LENGTH_DEFAULT, + .max = OV2722_FOCAL_LENGTH_DEFAULT, + .step = 0x01, + .def = OV2722_FOCAL_LENGTH_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number", + .min = OV2722_F_NUMBER_DEFAULT, + .max = OV2722_F_NUMBER_DEFAULT, + .step = 0x01, + .def = OV2722_F_NUMBER_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number range", + .min = OV2722_F_NUMBER_RANGE, + .max = OV2722_F_NUMBER_RANGE, + .step = 0x01, + .def = OV2722_F_NUMBER_RANGE, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_LINK_FREQ, + .name = "Link Frequency", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = 1, + .max = 1500000 * 1000, + .step = 1, + .def = 1, + .flags = V4L2_CTRL_FLAG_VOLATILE | V4L2_CTRL_FLAG_READ_ONLY, + }, +}; + +static int ov2722_init(struct v4l2_subdev *sd) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + + mutex_lock(&dev->input_lock); + + /* restore settings */ + ov2722_res = ov2722_res_preview; + N_RES = N_RES_PREVIEW; + + mutex_unlock(&dev->input_lock); + + return 0; +} + +static int power_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret = -1; + struct ov2722_device *dev = to_ov2722_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->power_ctrl) + return dev->platform_data->power_ctrl(sd, flag); + + if (flag) { + ret = dev->platform_data->v1p8_ctrl(sd, 1); + if (ret == 0) { + ret = dev->platform_data->v2p8_ctrl(sd, 1); + if (ret) + dev->platform_data->v1p8_ctrl(sd, 0); + } + } else { + ret = dev->platform_data->v1p8_ctrl(sd, 0); + ret |= dev->platform_data->v2p8_ctrl(sd, 0); + } + + return ret; +} + +static int gpio_ctrl(struct v4l2_subdev *sd, bool flag) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + int ret = -1; + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->gpio_ctrl) + return dev->platform_data->gpio_ctrl(sd, flag); + + /* Note: the GPIO order is asymmetric: always RESET# + * before PWDN# when turning it on or off. */ + ret = dev->platform_data->gpio0_ctrl(sd, flag); + /* + *ov2722 PWDN# active high when pull down,opposite to the convention + */ + ret |= dev->platform_data->gpio1_ctrl(sd, !flag); + return ret; +} + +static int power_up(struct v4l2_subdev *sd) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (NULL == dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + /* power control */ + ret = power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* according to DS, at least 5ms is needed between DOVDD and PWDN */ + usleep_range(5000, 6000); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 1); + if (ret) { + ret = gpio_ctrl(sd, 0); + if (ret) + goto fail_power; + } + + /* flis clock control */ + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + + /* according to DS, 20ms is needed between PWDN and i2c access */ + msleep(20); + + return 0; + +fail_clk: + gpio_ctrl(sd, 0); +fail_power: + power_ctrl(sd, 0); + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (NULL == dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 0); + if (ret) { + ret = gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed 2\n"); + } + + /* power control */ + ret = power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "vprog failed.\n"); + + return ret; +} + +static int ov2722_s_power(struct v4l2_subdev *sd, int on) +{ + int ret; + if (on == 0) + return power_down(sd); + else { + ret = power_up(sd); + if (!ret) + return ov2722_init(sd); + } + return ret; +} + +/* + * distance - calculate the distance + * @res: resolution + * @w: width + * @h: height + * + * Get the gap between resolution and w/h. + * res->width/height smaller than w/h wouldn't be considered. + * Returns the value of gap or -1 if fail. + */ +#define LARGEST_ALLOWED_RATIO_MISMATCH 800 +static int distance(struct ov2722_resolution *res, u32 w, u32 h) +{ + unsigned int w_ratio = ((res->width << 13)/w); + unsigned int h_ratio; + int match; + + if (h == 0) + return -1; + h_ratio = ((res->height << 13) / h); + if (h_ratio == 0) + return -1; + match = abs(((w_ratio << 13) / h_ratio) - ((int)8192)); + + if ((w_ratio < (int)8192) || (h_ratio < (int)8192) || + (match > LARGEST_ALLOWED_RATIO_MISMATCH)) + return -1; + + return w_ratio + h_ratio; +} + +/* Return the nearest higher resolution index */ +static int nearest_resolution_index(int w, int h) +{ + int i; + int idx = -1; + int dist; + int min_dist = INT_MAX; + struct ov2722_resolution *tmp_res = NULL; + + for (i = 0; i < N_RES; i++) { + tmp_res = &ov2722_res[i]; + dist = distance(tmp_res, w, h); + if (dist == -1) + continue; + if (dist < min_dist) { + min_dist = dist; + idx = i; + } + } + + return idx; +} + +static int get_resolution_index(int w, int h) +{ + int i; + + for (i = 0; i < N_RES; i++) { + if (w != ov2722_res[i].width) + continue; + if (h != ov2722_res[i].height) + continue; + + return i; + } + + return -1; +} + +/* TODO: remove it. */ +static int startup(struct v4l2_subdev *sd) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + ret = ov2722_write_reg(client, OV2722_8BIT, + OV2722_SW_RESET, 0x01); + if (ret) { + dev_err(&client->dev, "ov2722 reset err.\n"); + return ret; + } + + ret = ov2722_write_reg_array(client, ov2722_res[dev->fmt_idx].regs); + if (ret) { + dev_err(&client->dev, "ov2722 write register err.\n"); + return ret; + } + + return ret; +} + +static int ov2722_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov2722_device *dev = to_ov2722_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct camera_mipi_info *ov2722_info = NULL; + int ret = 0; + int idx; + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + ov2722_info = v4l2_get_subdev_hostdata(sd); + if (ov2722_info == NULL) + return -EINVAL; + + mutex_lock(&dev->input_lock); + idx = nearest_resolution_index(fmt->width, fmt->height); + if (idx == -1) { + /* return the largest resolution */ + fmt->width = ov2722_res[N_RES - 1].width; + fmt->height = ov2722_res[N_RES - 1].height; + } else { + fmt->width = ov2722_res[idx].width; + fmt->height = ov2722_res[idx].height; + } + fmt->code = MEDIA_BUS_FMT_SGRBG10_1X10; + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + cfg->try_fmt = *fmt; + mutex_unlock(&dev->input_lock); + return 0; + } + + dev->fmt_idx = get_resolution_index(fmt->width, fmt->height); + if (dev->fmt_idx == -1) { + dev_err(&client->dev, "get resolution fail\n"); + mutex_unlock(&dev->input_lock); + return -EINVAL; + } + + dev->pixels_per_line = ov2722_res[dev->fmt_idx].pixels_per_line; + dev->lines_per_frame = ov2722_res[dev->fmt_idx].lines_per_frame; + + ret = startup(sd); + if (ret) { + int i = 0; + dev_err(&client->dev, "ov2722 startup err, retry to power up\n"); + for (i = 0; i < OV2722_POWER_UP_RETRY_NUM; i++) { + dev_err(&client->dev, + "ov2722 retry to power up %d/%d times, result: ", + i+1, OV2722_POWER_UP_RETRY_NUM); + power_down(sd); + ret = power_up(sd); + if (ret) { + dev_err(&client->dev, "power up failed, continue\n"); + continue; + } + ret = startup(sd); + if (ret) { + dev_err(&client->dev, " startup FAILED!\n"); + } else { + dev_err(&client->dev, " startup SUCCESS!\n"); + break; + } + } + if (ret) { + dev_err(&client->dev, "ov2722 startup err\n"); + goto err; + } + } + + ret = ov2722_get_intg_factor(client, ov2722_info, + &ov2722_res[dev->fmt_idx]); + if (ret) + dev_err(&client->dev, "failed to get integration_factor\n"); + +err: + mutex_unlock(&dev->input_lock); + return ret; +} +static int ov2722_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov2722_device *dev = to_ov2722_sensor(sd); + + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + + fmt->width = ov2722_res[dev->fmt_idx].width; + fmt->height = ov2722_res[dev->fmt_idx].height; + fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; + + return 0; +} + +static int ov2722_detect(struct i2c_client *client) +{ + struct i2c_adapter *adapter = client->adapter; + u16 high, low; + int ret; + u16 id; + u8 revision; + + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_SC_CMMN_CHIP_ID_H, &high); + if (ret) { + dev_err(&client->dev, "sensor_id_high = 0x%x\n", high); + return -ENODEV; + } + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_SC_CMMN_CHIP_ID_L, &low); + id = ((((u16) high) << 8) | (u16) low); + + if ((id != OV2722_ID) && (id != OV2720_ID)) { + dev_err(&client->dev, "sensor ID error\n"); + return -ENODEV; + } + + ret = ov2722_read_reg(client, OV2722_8BIT, + OV2722_SC_CMMN_SUB_ID, &high); + revision = (u8) high & 0x0f; + + dev_dbg(&client->dev, "sensor_revision = 0x%x\n", revision); + dev_dbg(&client->dev, "detect ov2722 success\n"); + return 0; +} + +static int ov2722_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + mutex_lock(&dev->input_lock); + + ret = ov2722_write_reg(client, OV2722_8BIT, OV2722_SW_STREAM, + enable ? OV2722_START_STREAMING : + OV2722_STOP_STREAMING); + + mutex_unlock(&dev->input_lock); + return ret; +} + +static int ov2722_s_config(struct v4l2_subdev *sd, + int irq, void *platform_data) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (platform_data == NULL) + return -ENODEV; + + dev->platform_data = + (struct camera_sensor_platform_data *)platform_data; + + mutex_lock(&dev->input_lock); + if (dev->platform_data->platform_init) { + ret = dev->platform_data->platform_init(client); + if (ret) { + dev_err(&client->dev, "platform init err\n"); + goto platform_init_failed; + } + } + + /* power off the module, then power on it in future + * as first power on by board may not fulfill the + * power on sequqence needed by the module + */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "ov2722 power-off err.\n"); + goto fail_power_off; + } + + ret = power_up(sd); + if (ret) { + dev_err(&client->dev, "ov2722 power-up err.\n"); + goto fail_power_on; + } + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + /* config & detect sensor */ + ret = ov2722_detect(client); + if (ret) { + dev_err(&client->dev, "ov2722_detect err s_config.\n"); + goto fail_csi_cfg; + } + + /* turn off sensor, after probed */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "ov2722 power-off err.\n"); + goto fail_csi_cfg; + } + mutex_unlock(&dev->input_lock); + + return 0; + +fail_csi_cfg: + dev->platform_data->csi_cfg(sd, 0); +fail_power_on: + power_down(sd); + dev_err(&client->dev, "sensor power-gating failed\n"); +fail_power_off: + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); +platform_init_failed: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int ov2722_g_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + + if (!param) + return -EINVAL; + + if (param->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + dev_err(&client->dev, "unsupported buffer type.\n"); + return -EINVAL; + } + + memset(param, 0, sizeof(*param)); + param->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + if (dev->fmt_idx >= 0 && dev->fmt_idx < N_RES) { + param->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + param->parm.capture.timeperframe.numerator = 1; + param->parm.capture.capturemode = dev->run_mode; + param->parm.capture.timeperframe.denominator = + ov2722_res[dev->fmt_idx].fps; + } + return 0; +} + +static int ov2722_s_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + dev->run_mode = param->parm.capture.capturemode; + + mutex_lock(&dev->input_lock); + switch (dev->run_mode) { + case CI_MODE_VIDEO: + ov2722_res = ov2722_res_video; + N_RES = N_RES_VIDEO; + break; + case CI_MODE_STILL_CAPTURE: + ov2722_res = ov2722_res_still; + N_RES = N_RES_STILL; + break; + default: + ov2722_res = ov2722_res_preview; + N_RES = N_RES_PREVIEW; + } + mutex_unlock(&dev->input_lock); + return 0; +} + +static int ov2722_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + + interval->interval.numerator = 1; + interval->interval.denominator = ov2722_res[dev->fmt_idx].fps; + + return 0; +} + +static int ov2722_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= MAX_FMTS) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_SBGGR10_1X10; + return 0; +} + +static int ov2722_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + int index = fse->index; + + if (index >= N_RES) + return -EINVAL; + + fse->min_width = ov2722_res[index].width; + fse->min_height = ov2722_res[index].height; + fse->max_width = ov2722_res[index].width; + fse->max_height = ov2722_res[index].height; + + return 0; + +} + + +static int ov2722_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + struct ov2722_device *dev = to_ov2722_sensor(sd); + + mutex_lock(&dev->input_lock); + *frames = ov2722_res[dev->fmt_idx].skip_frames; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static const struct v4l2_subdev_sensor_ops ov2722_sensor_ops = { + .g_skip_frames = ov2722_g_skip_frames, +}; + +static const struct v4l2_subdev_video_ops ov2722_video_ops = { + .s_stream = ov2722_s_stream, + .g_parm = ov2722_g_parm, + .s_parm = ov2722_s_parm, + .g_frame_interval = ov2722_g_frame_interval, +}; + +static const struct v4l2_subdev_core_ops ov2722_core_ops = { + .s_power = ov2722_s_power, + .ioctl = ov2722_ioctl, +}; + +static const struct v4l2_subdev_pad_ops ov2722_pad_ops = { + .enum_mbus_code = ov2722_enum_mbus_code, + .enum_frame_size = ov2722_enum_frame_size, + .get_fmt = ov2722_get_fmt, + .set_fmt = ov2722_set_fmt, +}; + +static const struct v4l2_subdev_ops ov2722_ops = { + .core = &ov2722_core_ops, + .video = &ov2722_video_ops, + .pad = &ov2722_pad_ops, + .sensor = &ov2722_sensor_ops, +}; + +static int ov2722_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov2722_device *dev = to_ov2722_sensor(sd); + dev_dbg(&client->dev, "ov2722_remove...\n"); + + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); + + dev->platform_data->csi_cfg(sd, 0); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + v4l2_device_unregister_subdev(sd); + + atomisp_gmin_remove_subdev(sd); + + media_entity_cleanup(&dev->sd.entity); + kfree(dev); + + return 0; +} + +static int __ov2722_init_ctrl_handler(struct ov2722_device *dev) +{ + struct v4l2_ctrl_handler *hdl; + unsigned int i; + hdl = &dev->ctrl_handler; + v4l2_ctrl_handler_init(&dev->ctrl_handler, ARRAY_SIZE(ov2722_controls)); + for (i = 0; i < ARRAY_SIZE(ov2722_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &ov2722_controls[i], + NULL); + + dev->link_freq = v4l2_ctrl_find(&dev->ctrl_handler, V4L2_CID_LINK_FREQ); + + if (dev->ctrl_handler.error || dev->link_freq == NULL) + return dev->ctrl_handler.error; + + dev->sd.ctrl_handler = hdl; + + return 0; +} + +static int ov2722_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct ov2722_device *dev; + void *ovpdev; + int ret; + struct acpi_device *adev; + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) { + dev_err(&client->dev, "out of memory\n"); + return -ENOMEM; + } + + mutex_init(&dev->input_lock); + + dev->fmt_idx = 0; + v4l2_i2c_subdev_init(&(dev->sd), client, &ov2722_ops); + + ovpdev = client->dev.platform_data; + adev = ACPI_COMPANION(&client->dev); + if (adev) { + adev->power.flags.power_resources = 0; + ovpdev = gmin_camera_platform_data(&dev->sd, + ATOMISP_INPUT_FORMAT_RAW_10, + atomisp_bayer_order_grbg); + } + + ret = ov2722_s_config(&dev->sd, client->irq, ovpdev); + if (ret) + goto out_free; + + ret = __ov2722_init_ctrl_handler(dev); + if (ret) + goto out_ctrl_handler_free; + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = MEDIA_BUS_FMT_SBGGR10_1X10; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) + ov2722_remove(client); + + if (ACPI_HANDLE(&client->dev)) + ret = atomisp_register_i2c_module(&dev->sd, ovpdev, RAW_CAMERA); + + return ret; + +out_ctrl_handler_free: + v4l2_ctrl_handler_free(&dev->ctrl_handler); + +out_free: + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + return ret; +} + +MODULE_DEVICE_TABLE(i2c, ov2722_id); + +static struct acpi_device_id ov2722_acpi_match[] = { + { "INT33FB" }, + {}, +}; + +MODULE_DEVICE_TABLE(acpi, ov2722_acpi_match); + +static struct i2c_driver ov2722_driver = { + .driver = { + .owner = THIS_MODULE, + .name = OV2722_NAME, + .acpi_match_table = ACPI_PTR(ov2722_acpi_match), + }, + .probe = ov2722_probe, + .remove = ov2722_remove, + .id_table = ov2722_id, +}; + +static int init_ov2722(void) +{ + return i2c_add_driver(&ov2722_driver); +} + +static void exit_ov2722(void) +{ + + i2c_del_driver(&ov2722_driver); +} + +module_init(init_ov2722); +module_exit(exit_ov2722); + +MODULE_AUTHOR("Wei Liu "); +MODULE_DESCRIPTION("A low-level driver for OmniVision 2722 sensors"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/ov2722.h b/drivers/staging/media/atomisp/i2c/ov2722.h new file mode 100644 index 0000000000000000000000000000000000000000..e8f17f2708061b51993bdc69c8ad67e28fba6ad4 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov2722.h @@ -0,0 +1,1267 @@ +/* + * Support for OmniVision OV2722 1080p HD camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __OV2722_H__ +#define __OV2722_H__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define OV2722_NAME "ov2722" + +#define OV2722_POWER_UP_RETRY_NUM 5 + +/* Defines for register writes and register array processing */ +#define I2C_MSG_LENGTH 0x2 +#define I2C_RETRY_COUNT 5 + +#define OV2722_FOCAL_LENGTH_NUM 278 /*2.78mm*/ +#define OV2722_FOCAL_LENGTH_DEM 100 +#define OV2722_F_NUMBER_DEFAULT_NUM 26 +#define OV2722_F_NUMBER_DEM 10 + +#define MAX_FMTS 1 + +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define OV2722_FOCAL_LENGTH_DEFAULT 0x1160064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define OV2722_F_NUMBER_DEFAULT 0x1a000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define OV2722_F_NUMBER_RANGE 0x1a0a1a0a +#define OV2720_ID 0x2720 +#define OV2722_ID 0x2722 + +#define OV2722_FINE_INTG_TIME_MIN 0 +#define OV2722_FINE_INTG_TIME_MAX_MARGIN 0 +#define OV2722_COARSE_INTG_TIME_MIN 1 +#define OV2722_COARSE_INTG_TIME_MAX_MARGIN 4 + +/* + * OV2722 System control registers + */ +#define OV2722_SW_SLEEP 0x0100 +#define OV2722_SW_RESET 0x0103 +#define OV2722_SW_STREAM 0x0100 + +#define OV2722_SC_CMMN_CHIP_ID_H 0x300A +#define OV2722_SC_CMMN_CHIP_ID_L 0x300B +#define OV2722_SC_CMMN_SCCB_ID 0x300C +#define OV2722_SC_CMMN_SUB_ID 0x302A /* process, version*/ + +#define OV2722_SC_CMMN_PAD_OEN0 0x3000 +#define OV2722_SC_CMMN_PAD_OEN1 0x3001 +#define OV2722_SC_CMMN_PAD_OEN2 0x3002 +#define OV2722_SC_CMMN_PAD_OUT0 0x3008 +#define OV2722_SC_CMMN_PAD_OUT1 0x3009 +#define OV2722_SC_CMMN_PAD_OUT2 0x300D +#define OV2722_SC_CMMN_PAD_SEL0 0x300E +#define OV2722_SC_CMMN_PAD_SEL1 0x300F +#define OV2722_SC_CMMN_PAD_SEL2 0x3010 + +#define OV2722_SC_CMMN_PAD_PK 0x3011 +#define OV2722_SC_CMMN_A_PWC_PK_O_13 0x3013 +#define OV2722_SC_CMMN_A_PWC_PK_O_14 0x3014 + +#define OV2722_SC_CMMN_CLKRST0 0x301A +#define OV2722_SC_CMMN_CLKRST1 0x301B +#define OV2722_SC_CMMN_CLKRST2 0x301C +#define OV2722_SC_CMMN_CLKRST3 0x301D +#define OV2722_SC_CMMN_CLKRST4 0x301E +#define OV2722_SC_CMMN_CLKRST5 0x3005 +#define OV2722_SC_CMMN_PCLK_DIV_CTRL 0x3007 +#define OV2722_SC_CMMN_CLOCK_SEL 0x3020 +#define OV2722_SC_SOC_CLKRST5 0x3040 + +#define OV2722_SC_CMMN_PLL_CTRL0 0x3034 +#define OV2722_SC_CMMN_PLL_CTRL1 0x3035 +#define OV2722_SC_CMMN_PLL_CTRL2 0x3039 +#define OV2722_SC_CMMN_PLL_CTRL3 0x3037 +#define OV2722_SC_CMMN_PLL_MULTIPLIER 0x3036 +#define OV2722_SC_CMMN_PLL_DEBUG_OPT 0x3038 +#define OV2722_SC_CMMN_PLLS_CTRL0 0x303A +#define OV2722_SC_CMMN_PLLS_CTRL1 0x303B +#define OV2722_SC_CMMN_PLLS_CTRL2 0x303C +#define OV2722_SC_CMMN_PLLS_CTRL3 0x303D + +#define OV2722_SC_CMMN_MIPI_PHY_16 0x3016 +#define OV2722_SC_CMMN_MIPI_PHY_17 0x3017 +#define OV2722_SC_CMMN_MIPI_SC_CTRL_18 0x3018 +#define OV2722_SC_CMMN_MIPI_SC_CTRL_19 0x3019 +#define OV2722_SC_CMMN_MIPI_SC_CTRL_21 0x3021 +#define OV2722_SC_CMMN_MIPI_SC_CTRL_22 0x3022 + +#define OV2722_AEC_PK_EXPO_H 0x3500 +#define OV2722_AEC_PK_EXPO_M 0x3501 +#define OV2722_AEC_PK_EXPO_L 0x3502 +#define OV2722_AEC_MANUAL_CTRL 0x3503 +#define OV2722_AGC_ADJ_H 0x3508 +#define OV2722_AGC_ADJ_L 0x3509 +#define OV2722_VTS_DIFF_H 0x350c +#define OV2722_VTS_DIFF_L 0x350d +#define OV2722_GROUP_ACCESS 0x3208 +#define OV2722_HTS_H 0x380c +#define OV2722_HTS_L 0x380d +#define OV2722_VTS_H 0x380e +#define OV2722_VTS_L 0x380f + +#define OV2722_MWB_GAIN_R_H 0x5186 +#define OV2722_MWB_GAIN_R_L 0x5187 +#define OV2722_MWB_GAIN_G_H 0x5188 +#define OV2722_MWB_GAIN_G_L 0x5189 +#define OV2722_MWB_GAIN_B_H 0x518a +#define OV2722_MWB_GAIN_B_L 0x518b + +#define OV2722_H_CROP_START_H 0x3800 +#define OV2722_H_CROP_START_L 0x3801 +#define OV2722_V_CROP_START_H 0x3802 +#define OV2722_V_CROP_START_L 0x3803 +#define OV2722_H_CROP_END_H 0x3804 +#define OV2722_H_CROP_END_L 0x3805 +#define OV2722_V_CROP_END_H 0x3806 +#define OV2722_V_CROP_END_L 0x3807 +#define OV2722_H_OUTSIZE_H 0x3808 +#define OV2722_H_OUTSIZE_L 0x3809 +#define OV2722_V_OUTSIZE_H 0x380a +#define OV2722_V_OUTSIZE_L 0x380b + +#define OV2722_START_STREAMING 0x01 +#define OV2722_STOP_STREAMING 0x00 + +struct regval_list { + u16 reg_num; + u8 value; +}; + +struct ov2722_resolution { + u8 *desc; + const struct ov2722_reg *regs; + int res; + int width; + int height; + int fps; + int pix_clk_freq; + u32 skip_frames; + u16 pixels_per_line; + u16 lines_per_frame; + u8 bin_factor_x; + u8 bin_factor_y; + u8 bin_mode; + bool used; + int mipi_freq; +}; + +struct ov2722_format { + u8 *desc; + u32 pixelformat; + struct ov2722_reg *regs; +}; + +/* + * ov2722 device structure. + */ +struct ov2722_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + struct mutex input_lock; + + struct camera_sensor_platform_data *platform_data; + int vt_pix_clk_freq_mhz; + int fmt_idx; + int run_mode; + u16 pixels_per_line; + u16 lines_per_frame; + u8 res; + u8 type; + + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *link_freq; +}; + +enum ov2722_tok_type { + OV2722_8BIT = 0x0001, + OV2722_16BIT = 0x0002, + OV2722_32BIT = 0x0004, + OV2722_TOK_TERM = 0xf000, /* terminating token for reg list */ + OV2722_TOK_DELAY = 0xfe00, /* delay token for reg list */ + OV2722_TOK_MASK = 0xfff0 +}; + +/** + * struct ov2722_reg - MI sensor register format + * @type: type of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ +struct ov2722_reg { + enum ov2722_tok_type type; + u16 reg; + u32 val; /* @set value for read/mod/write, @mask */ +}; + +#define to_ov2722_sensor(x) container_of(x, struct ov2722_device, sd) + +#define OV2722_MAX_WRITE_BUF_SIZE 30 + +struct ov2722_write_buffer { + u16 addr; + u8 data[OV2722_MAX_WRITE_BUF_SIZE]; +}; + +struct ov2722_write_ctrl { + int index; + struct ov2722_write_buffer buffer; +}; + +static const struct i2c_device_id ov2722_id[] = { + {OV2722_NAME, 0}, + {} +}; + +/* + * Register settings for various resolution + */ +static struct ov2722_reg const ov2722_QVGA_30fps[] = { + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x0c}, + {OV2722_8BIT, 0x373a, 0x1c}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x0c}, + {OV2722_8BIT, 0x3705, 0x06}, + {OV2722_8BIT, 0x3730, 0x0e}, + {OV2722_8BIT, 0x3704, 0x1c}, + {OV2722_8BIT, 0x3f06, 0x00}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0x46}, + {OV2722_8BIT, 0x371e, 0x00}, + {OV2722_8BIT, 0x371f, 0x63}, + {OV2722_8BIT, 0x3708, 0x61}, + {OV2722_8BIT, 0x3709, 0x12}, + {OV2722_8BIT, 0x3800, 0x01}, + {OV2722_8BIT, 0x3801, 0x42}, /* H crop start: 322 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x20}, /* V crop start: 32 */ + {OV2722_8BIT, 0x3804, 0x06}, + {OV2722_8BIT, 0x3805, 0x95}, /* H crop end: 1685 */ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x27}, /* V crop end: 1063 */ + {OV2722_8BIT, 0x3808, 0x01}, + {OV2722_8BIT, 0x3809, 0x50}, /* H output size: 336 */ + {OV2722_8BIT, 0x380a, 0x01}, + {OV2722_8BIT, 0x380b, 0x00}, /* V output size: 256 */ + + /* H blank timing */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0xc0}, + {OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/ + {OV2722_8BIT, 0x3814, 0x71}, + {OV2722_8BIT, 0x3815, 0x71}, + {OV2722_8BIT, 0x3612, 0x49}, + {OV2722_8BIT, 0x3618, 0x00}, + {OV2722_8BIT, 0x3a08, 0x01}, + {OV2722_8BIT, 0x3a09, 0xc3}, + {OV2722_8BIT, 0x3a0a, 0x01}, + {OV2722_8BIT, 0x3a0b, 0x77}, + {OV2722_8BIT, 0x3a0d, 0x00}, + {OV2722_8BIT, 0x3a0e, 0x00}, + {OV2722_8BIT, 0x4520, 0x09}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3000, 0xff}, + {OV2722_8BIT, 0x3001, 0xff}, + {OV2722_8BIT, 0x3002, 0xf0}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x63}, + {OV2722_8BIT, 0x3634, 0x24}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xff}, + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ + {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ + {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ + {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x26}, + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + + /* Added for power optimization */ + {OV2722_8BIT, 0x3000, 0x00}, + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3011, 0x22}, + {OV2722_8BIT, 0x3a00, 0x58}, + {OV2722_8BIT, 0x3503, 0x17}, + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x46}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x10}, + {OV2722_TOK_TERM, 0, 0}, + +}; + +static struct ov2722_reg const ov2722_480P_30fps[] = { + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x18}, + {OV2722_8BIT, 0x373a, 0x3c}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x1d}, + {OV2722_8BIT, 0x3705, 0x12}, + {OV2722_8BIT, 0x3730, 0x1f}, + {OV2722_8BIT, 0x3704, 0x3f}, + {OV2722_8BIT, 0x3f06, 0x1d}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0x83}, + {OV2722_8BIT, 0x371e, 0x00}, + {OV2722_8BIT, 0x371f, 0xbd}, + {OV2722_8BIT, 0x3708, 0x63}, + {OV2722_8BIT, 0x3709, 0x52}, + {OV2722_8BIT, 0x3800, 0x00}, + {OV2722_8BIT, 0x3801, 0xf2}, /* H crop start: 322 - 80 = 242*/ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x20}, /* V crop start: 32*/ + {OV2722_8BIT, 0x3804, 0x06}, + {OV2722_8BIT, 0x3805, 0xBB}, /* H crop end: 1643 + 80 = 1723*/ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x03}, /* V crop end: 1027*/ + {OV2722_8BIT, 0x3808, 0x02}, + {OV2722_8BIT, 0x3809, 0xE0}, /* H output size: 656 +80 = 736*/ + {OV2722_8BIT, 0x380a, 0x01}, + {OV2722_8BIT, 0x380b, 0xF0}, /* V output size: 496 */ + + /* H blank timing */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/ + {OV2722_8BIT, 0x3814, 0x31}, + {OV2722_8BIT, 0x3815, 0x31}, + {OV2722_8BIT, 0x3612, 0x4b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x02}, + {OV2722_8BIT, 0x3a09, 0x67}, + {OV2722_8BIT, 0x3a0a, 0x02}, + {OV2722_8BIT, 0x3a0b, 0x00}, + {OV2722_8BIT, 0x3a0d, 0x00}, + {OV2722_8BIT, 0x3a0e, 0x00}, + {OV2722_8BIT, 0x4520, 0x0a}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3000, 0xff}, + {OV2722_8BIT, 0x3001, 0xff}, + {OV2722_8BIT, 0x3002, 0xf0}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x63}, + {OV2722_8BIT, 0x3634, 0x24}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xff}, + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ + {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ + {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ + {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x26}, + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + + /* Added for power optimization */ + {OV2722_8BIT, 0x3000, 0x00}, + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3011, 0x22}, + {OV2722_8BIT, 0x3a00, 0x58}, + {OV2722_8BIT, 0x3503, 0x17}, + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x46}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x10}, + {OV2722_TOK_TERM, 0, 0}, +}; + +static struct ov2722_reg const ov2722_VGA_30fps[] = { + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x18}, + {OV2722_8BIT, 0x373a, 0x3c}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x1d}, + {OV2722_8BIT, 0x3705, 0x12}, + {OV2722_8BIT, 0x3730, 0x1f}, + {OV2722_8BIT, 0x3704, 0x3f}, + {OV2722_8BIT, 0x3f06, 0x1d}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0x83}, + {OV2722_8BIT, 0x371e, 0x00}, + {OV2722_8BIT, 0x371f, 0xbd}, + {OV2722_8BIT, 0x3708, 0x63}, + {OV2722_8BIT, 0x3709, 0x52}, + {OV2722_8BIT, 0x3800, 0x01}, + {OV2722_8BIT, 0x3801, 0x42}, /* H crop start: 322 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x20}, /* V crop start: 32*/ + {OV2722_8BIT, 0x3804, 0x06}, + {OV2722_8BIT, 0x3805, 0x6B}, /* H crop end: 1643*/ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x03}, /* V crop end: 1027*/ + {OV2722_8BIT, 0x3808, 0x02}, + {OV2722_8BIT, 0x3809, 0x90}, /* H output size: 656 */ + {OV2722_8BIT, 0x380a, 0x01}, + {OV2722_8BIT, 0x380b, 0xF0}, /* V output size: 496 */ + + /* H blank timing */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x04}, /* H window offset: 5 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x01}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* flip isp*/ + {OV2722_8BIT, 0x3814, 0x31}, + {OV2722_8BIT, 0x3815, 0x31}, + {OV2722_8BIT, 0x3612, 0x4b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x02}, + {OV2722_8BIT, 0x3a09, 0x67}, + {OV2722_8BIT, 0x3a0a, 0x02}, + {OV2722_8BIT, 0x3a0b, 0x00}, + {OV2722_8BIT, 0x3a0d, 0x00}, + {OV2722_8BIT, 0x3a0e, 0x00}, + {OV2722_8BIT, 0x4520, 0x0a}, + {OV2722_8BIT, 0x4837, 0x29}, + {OV2722_8BIT, 0x3000, 0xff}, + {OV2722_8BIT, 0x3001, 0xff}, + {OV2722_8BIT, 0x3002, 0xf0}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x63}, + {OV2722_8BIT, 0x3634, 0x24}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xff}, + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ + {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ + {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ + {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x26}, + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + + /* Added for power optimization */ + {OV2722_8BIT, 0x3000, 0x00}, + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3011, 0x22}, + {OV2722_8BIT, 0x3a00, 0x58}, + {OV2722_8BIT, 0x3503, 0x17}, + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x46}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x10}, + {OV2722_TOK_TERM, 0, 0}, +}; + +static struct ov2722_reg const ov2722_1632_1092_30fps[] = { + {OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for + a whole frame complete.(vblank) */ + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x24}, + {OV2722_8BIT, 0x373a, 0x60}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x2e}, + {OV2722_8BIT, 0x3705, 0x10}, + {OV2722_8BIT, 0x3730, 0x30}, + {OV2722_8BIT, 0x3704, 0x62}, + {OV2722_8BIT, 0x3f06, 0x3a}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0xc4}, + {OV2722_8BIT, 0x371e, 0x01}, + {OV2722_8BIT, 0x371f, 0x0d}, + {OV2722_8BIT, 0x3708, 0x61}, + {OV2722_8BIT, 0x3709, 0x12}, + {OV2722_8BIT, 0x3800, 0x00}, + {OV2722_8BIT, 0x3801, 0x9E}, /* H crop start: 158 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */ + {OV2722_8BIT, 0x3804, 0x07}, + {OV2722_8BIT, 0x3805, 0x05}, /* H crop end: 1797 */ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */ + + {OV2722_8BIT, 0x3808, 0x06}, + {OV2722_8BIT, 0x3809, 0x60}, /* H output size: 1632 */ + {OV2722_8BIT, 0x380a, 0x04}, + {OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0xd4}, /* H timing: 2260 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xdc}, /* V timing: 1244 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ + {OV2722_8BIT, 0x3814, 0x11}, + {OV2722_8BIT, 0x3815, 0x11}, + {OV2722_8BIT, 0x3612, 0x0b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x01}, + {OV2722_8BIT, 0x3a09, 0x50}, + {OV2722_8BIT, 0x3a0a, 0x01}, + {OV2722_8BIT, 0x3a0b, 0x18}, + {OV2722_8BIT, 0x3a0d, 0x03}, + {OV2722_8BIT, 0x3a0e, 0x03}, + {OV2722_8BIT, 0x4520, 0x00}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x23}, + {OV2722_8BIT, 0x3634, 0x54}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */ + {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, + {OV2722_8BIT, 0x5184, 0xb0}, + {OV2722_8BIT, 0x5185, 0xb0}, + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x2c}, /* 422.4 MHz */ + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */ + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x3F}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x00}, + {OV2722_TOK_TERM, 0, 0} +}; + +static struct ov2722_reg const ov2722_1452_1092_30fps[] = { + {OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for + a whole frame complete.(vblank) */ + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x24}, + {OV2722_8BIT, 0x373a, 0x60}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x2e}, + {OV2722_8BIT, 0x3705, 0x10}, + {OV2722_8BIT, 0x3730, 0x30}, + {OV2722_8BIT, 0x3704, 0x62}, + {OV2722_8BIT, 0x3f06, 0x3a}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0xc4}, + {OV2722_8BIT, 0x371e, 0x01}, + {OV2722_8BIT, 0x371f, 0x0d}, + {OV2722_8BIT, 0x3708, 0x61}, + {OV2722_8BIT, 0x3709, 0x12}, + {OV2722_8BIT, 0x3800, 0x00}, + {OV2722_8BIT, 0x3801, 0xF8}, /* H crop start: 248 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */ + {OV2722_8BIT, 0x3804, 0x06}, + {OV2722_8BIT, 0x3805, 0xab}, /* H crop end: 1707 */ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */ + {OV2722_8BIT, 0x3808, 0x05}, + {OV2722_8BIT, 0x3809, 0xac}, /* H output size: 1452 */ + {OV2722_8BIT, 0x380a, 0x04}, + {OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0xd4}, /* H timing: 2260 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xdc}, /* V timing: 1244 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ + {OV2722_8BIT, 0x3814, 0x11}, + {OV2722_8BIT, 0x3815, 0x11}, + {OV2722_8BIT, 0x3612, 0x0b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x01}, + {OV2722_8BIT, 0x3a09, 0x50}, + {OV2722_8BIT, 0x3a0a, 0x01}, + {OV2722_8BIT, 0x3a0b, 0x18}, + {OV2722_8BIT, 0x3a0d, 0x03}, + {OV2722_8BIT, 0x3a0e, 0x03}, + {OV2722_8BIT, 0x4520, 0x00}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x23}, + {OV2722_8BIT, 0x3634, 0x54}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */ + {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, + {OV2722_8BIT, 0x5184, 0xb0}, + {OV2722_8BIT, 0x5185, 0xb0}, + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x2c}, /* 422.4 MHz */ + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */ + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x3F}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x00}, + {OV2722_TOK_TERM, 0, 0} +}; +static struct ov2722_reg const ov2722_1M3_30fps[] = { + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x24}, + {OV2722_8BIT, 0x373a, 0x60}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x2e}, + {OV2722_8BIT, 0x3705, 0x10}, + {OV2722_8BIT, 0x3730, 0x30}, + {OV2722_8BIT, 0x3704, 0x62}, + {OV2722_8BIT, 0x3f06, 0x3a}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0xc4}, + {OV2722_8BIT, 0x371e, 0x01}, + {OV2722_8BIT, 0x371f, 0x0d}, + {OV2722_8BIT, 0x3708, 0x61}, + {OV2722_8BIT, 0x3709, 0x12}, + {OV2722_8BIT, 0x3800, 0x01}, + {OV2722_8BIT, 0x3801, 0x4a}, /* H crop start: 330 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x03}, /* V crop start: 3 */ + {OV2722_8BIT, 0x3804, 0x06}, + {OV2722_8BIT, 0x3805, 0xe1}, /* H crop end: 1761 */ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x47}, /* V crop end: 1095 */ + {OV2722_8BIT, 0x3808, 0x05}, + {OV2722_8BIT, 0x3809, 0x88}, /* H output size: 1416 */ + {OV2722_8BIT, 0x380a, 0x04}, + {OV2722_8BIT, 0x380b, 0x0a}, /* V output size: 1034 */ + + /* H blank timing */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0x00}, /* H total size: 2048 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xa0}, /* V total size: 1184 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x05}, /* H window offset: 5 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* flip isp */ + {OV2722_8BIT, 0x3814, 0x11}, + {OV2722_8BIT, 0x3815, 0x11}, + {OV2722_8BIT, 0x3612, 0x0b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x01}, + {OV2722_8BIT, 0x3a09, 0x50}, + {OV2722_8BIT, 0x3a0a, 0x01}, + {OV2722_8BIT, 0x3a0b, 0x18}, + {OV2722_8BIT, 0x3a0d, 0x03}, + {OV2722_8BIT, 0x3a0e, 0x03}, + {OV2722_8BIT, 0x4520, 0x00}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3000, 0xff}, + {OV2722_8BIT, 0x3001, 0xff}, + {OV2722_8BIT, 0x3002, 0xf0}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x23}, + {OV2722_8BIT, 0x3634, 0x54}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, /* v_en, h_en, blc_en */ + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xcf}, + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, /* AWB red */ + {OV2722_8BIT, 0x5184, 0xb0}, /* AWB green */ + {OV2722_8BIT, 0x5185, 0xb0}, /* AWB blue */ + {OV2722_8BIT, 0x5180, 0x03}, /* AWB manual mode */ + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x4800, 0x24}, /* clk lane gate enable */ + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x26}, + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + + /* Added for power optimization */ + {OV2722_8BIT, 0x3000, 0x00}, + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3503, 0x17}, + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x46}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x10}, + {OV2722_TOK_TERM, 0, 0}, +}; + +static struct ov2722_reg const ov2722_1080p_30fps[] = { + {OV2722_8BIT, 0x3021, 0x03}, /* For stand wait for a whole + frame complete.(vblank) */ + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x24}, + {OV2722_8BIT, 0x373a, 0x60}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x2e}, + {OV2722_8BIT, 0x3705, 0x2b}, + {OV2722_8BIT, 0x3730, 0x30}, + {OV2722_8BIT, 0x3704, 0x62}, + {OV2722_8BIT, 0x3f06, 0x3a}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0xc4}, + {OV2722_8BIT, 0x371e, 0x01}, + {OV2722_8BIT, 0x371f, 0x28}, + {OV2722_8BIT, 0x3708, 0x61}, + {OV2722_8BIT, 0x3709, 0x12}, + {OV2722_8BIT, 0x3800, 0x00}, + {OV2722_8BIT, 0x3801, 0x08}, /* H crop start: 8 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0x01}, /* V crop start: 1 */ + {OV2722_8BIT, 0x3804, 0x07}, + {OV2722_8BIT, 0x3805, 0x9b}, /* H crop end: 1947 */ + {OV2722_8BIT, 0x3806, 0x04}, + {OV2722_8BIT, 0x3807, 0x45}, /* V crop end: 1093 */ + {OV2722_8BIT, 0x3808, 0x07}, + {OV2722_8BIT, 0x3809, 0x8c}, /* H output size: 1932 */ + {OV2722_8BIT, 0x380a, 0x04}, + {OV2722_8BIT, 0x380b, 0x44}, /* V output size: 1092 */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0x14}, /* H timing: 2068 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0x5a}, /* V timing: 1114 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ + {OV2722_8BIT, 0x3814, 0x11}, + {OV2722_8BIT, 0x3815, 0x11}, + {OV2722_8BIT, 0x3612, 0x4b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x01}, + {OV2722_8BIT, 0x3a09, 0x50}, + {OV2722_8BIT, 0x3a0a, 0x01}, + {OV2722_8BIT, 0x3a0b, 0x18}, + {OV2722_8BIT, 0x3a0d, 0x03}, + {OV2722_8BIT, 0x3a0e, 0x03}, + {OV2722_8BIT, 0x4520, 0x00}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3000, 0xff}, + {OV2722_8BIT, 0x3001, 0xff}, + {OV2722_8BIT, 0x3002, 0xf0}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0x53}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x63}, + {OV2722_8BIT, 0x3634, 0x24}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xcd}, /* manual 3a */ + {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x3503, 0x17}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, + {OV2722_8BIT, 0x5184, 0xb0}, + {OV2722_8BIT, 0x5185, 0xb0}, + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x24}, /* 345.6 MHz */ + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3011, 0x22}, + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x3F}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x00}, + {OV2722_TOK_TERM, 0, 0} +}; + +static struct ov2722_reg const ov2722_720p_30fps[] = { + {OV2722_8BIT, 0x3021, 0x03}, + {OV2722_8BIT, 0x3718, 0x10}, + {OV2722_8BIT, 0x3702, 0x24}, + {OV2722_8BIT, 0x373a, 0x60}, + {OV2722_8BIT, 0x3715, 0x01}, + {OV2722_8BIT, 0x3703, 0x2e}, + {OV2722_8BIT, 0x3705, 0x10}, + {OV2722_8BIT, 0x3730, 0x30}, + {OV2722_8BIT, 0x3704, 0x62}, + {OV2722_8BIT, 0x3f06, 0x3a}, + {OV2722_8BIT, 0x371c, 0x00}, + {OV2722_8BIT, 0x371d, 0xc4}, + {OV2722_8BIT, 0x371e, 0x01}, + {OV2722_8BIT, 0x371f, 0x0d}, + {OV2722_8BIT, 0x3708, 0x61}, + {OV2722_8BIT, 0x3709, 0x12}, + {OV2722_8BIT, 0x3800, 0x01}, + {OV2722_8BIT, 0x3801, 0x40}, /* H crop start: 320 */ + {OV2722_8BIT, 0x3802, 0x00}, + {OV2722_8BIT, 0x3803, 0xb1}, /* V crop start: 177 */ + {OV2722_8BIT, 0x3804, 0x06}, + {OV2722_8BIT, 0x3805, 0x55}, /* H crop end: 1621 */ + {OV2722_8BIT, 0x3806, 0x03}, + {OV2722_8BIT, 0x3807, 0x95}, /* V crop end: 918 */ + {OV2722_8BIT, 0x3808, 0x05}, + {OV2722_8BIT, 0x3809, 0x10}, /* H output size: 0x0788==1928 */ + {OV2722_8BIT, 0x380a, 0x02}, + {OV2722_8BIT, 0x380b, 0xe0}, /* output size: 0x02DE==734 */ + {OV2722_8BIT, 0x380c, 0x08}, + {OV2722_8BIT, 0x380d, 0x00}, /* H timing: 2048 */ + {OV2722_8BIT, 0x380e, 0x04}, + {OV2722_8BIT, 0x380f, 0xa3}, /* V timing: 1187 */ + {OV2722_8BIT, 0x3810, 0x00}, + {OV2722_8BIT, 0x3811, 0x03}, /* H window offset: 3 */ + {OV2722_8BIT, 0x3812, 0x00}, + {OV2722_8BIT, 0x3813, 0x02}, /* V window offset: 2 */ + {OV2722_8BIT, 0x3820, 0x80}, + {OV2722_8BIT, 0x3821, 0x06}, /* mirror */ + {OV2722_8BIT, 0x3814, 0x11}, + {OV2722_8BIT, 0x3815, 0x11}, + {OV2722_8BIT, 0x3612, 0x0b}, + {OV2722_8BIT, 0x3618, 0x04}, + {OV2722_8BIT, 0x3a08, 0x01}, + {OV2722_8BIT, 0x3a09, 0x50}, + {OV2722_8BIT, 0x3a0a, 0x01}, + {OV2722_8BIT, 0x3a0b, 0x18}, + {OV2722_8BIT, 0x3a0d, 0x03}, + {OV2722_8BIT, 0x3a0e, 0x03}, + {OV2722_8BIT, 0x4520, 0x00}, + {OV2722_8BIT, 0x4837, 0x1b}, + {OV2722_8BIT, 0x3600, 0x08}, + {OV2722_8BIT, 0x3621, 0xc0}, + {OV2722_8BIT, 0x3632, 0xd2}, /* added for power opt */ + {OV2722_8BIT, 0x3633, 0x23}, + {OV2722_8BIT, 0x3634, 0x54}, + {OV2722_8BIT, 0x3f01, 0x0c}, + {OV2722_8BIT, 0x5001, 0xc1}, + {OV2722_8BIT, 0x3614, 0xf0}, + {OV2722_8BIT, 0x3630, 0x2d}, + {OV2722_8BIT, 0x370b, 0x62}, + {OV2722_8BIT, 0x3706, 0x61}, + {OV2722_8BIT, 0x4000, 0x02}, + {OV2722_8BIT, 0x4002, 0xc5}, + {OV2722_8BIT, 0x4005, 0x08}, + {OV2722_8BIT, 0x404f, 0x84}, + {OV2722_8BIT, 0x4051, 0x00}, + {OV2722_8BIT, 0x5000, 0xcf}, /* manual 3a */ + {OV2722_8BIT, 0x301d, 0xf0}, /* enable group hold */ + {OV2722_8BIT, 0x3a18, 0x00}, + {OV2722_8BIT, 0x3a19, 0x80}, + {OV2722_8BIT, 0x4521, 0x00}, + {OV2722_8BIT, 0x5183, 0xb0}, + {OV2722_8BIT, 0x5184, 0xb0}, + {OV2722_8BIT, 0x5185, 0xb0}, + {OV2722_8BIT, 0x370c, 0x0c}, + {OV2722_8BIT, 0x3035, 0x00}, + {OV2722_8BIT, 0x3036, 0x26}, /* {0x3036, 0x2c}, //422.4 MHz */ + {OV2722_8BIT, 0x3037, 0xa1}, + {OV2722_8BIT, 0x303e, 0x19}, + {OV2722_8BIT, 0x3038, 0x06}, + {OV2722_8BIT, 0x3018, 0x04}, + {OV2722_8BIT, 0x3000, 0x00}, /* added for power optimization */ + {OV2722_8BIT, 0x3001, 0x00}, + {OV2722_8BIT, 0x3002, 0x00}, + {OV2722_8BIT, 0x3a0f, 0x40}, + {OV2722_8BIT, 0x3a10, 0x38}, + {OV2722_8BIT, 0x3a1b, 0x48}, + {OV2722_8BIT, 0x3a1e, 0x30}, + {OV2722_8BIT, 0x3a11, 0x90}, + {OV2722_8BIT, 0x3a1f, 0x10}, + {OV2722_8BIT, 0x3503, 0x17}, /* manual 3a */ + {OV2722_8BIT, 0x3500, 0x00}, + {OV2722_8BIT, 0x3501, 0x3F}, + {OV2722_8BIT, 0x3502, 0x00}, + {OV2722_8BIT, 0x3508, 0x00}, + {OV2722_8BIT, 0x3509, 0x00}, + {OV2722_TOK_TERM, 0, 0}, +}; + +struct ov2722_resolution ov2722_res_preview[] = { + { + .desc = "ov2722_1632_1092_30fps", + .width = 1632, + .height = 1092, + .fps = 30, + .pix_clk_freq = 85, + .used = 0, + .pixels_per_line = 2260, + .lines_per_frame = 1244, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1632_1092_30fps, + .mipi_freq = 422400, + }, + { + .desc = "ov2722_1452_1092_30fps", + .width = 1452, + .height = 1092, + .fps = 30, + .pix_clk_freq = 85, + .used = 0, + .pixels_per_line = 2260, + .lines_per_frame = 1244, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1452_1092_30fps, + .mipi_freq = 422400, + }, + { + .desc = "ov2722_1080P_30fps", + .width = 1932, + .height = 1092, + .pix_clk_freq = 69, + .fps = 30, + .used = 0, + .pixels_per_line = 2068, + .lines_per_frame = 1114, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1080p_30fps, + .mipi_freq = 345600, + }, +}; +#define N_RES_PREVIEW (ARRAY_SIZE(ov2722_res_preview)) + +struct ov2722_resolution ov2722_res_still[] = { + { + .desc = "ov2722_480P_30fps", + .width = 1632, + .height = 1092, + .fps = 30, + .pix_clk_freq = 85, + .used = 0, + .pixels_per_line = 2260, + .lines_per_frame = 1244, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1632_1092_30fps, + .mipi_freq = 422400, + }, + { + .desc = "ov2722_1452_1092_30fps", + .width = 1452, + .height = 1092, + .fps = 30, + .pix_clk_freq = 85, + .used = 0, + .pixels_per_line = 2260, + .lines_per_frame = 1244, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1452_1092_30fps, + .mipi_freq = 422400, + }, + { + .desc = "ov2722_1080P_30fps", + .width = 1932, + .height = 1092, + .pix_clk_freq = 69, + .fps = 30, + .used = 0, + .pixels_per_line = 2068, + .lines_per_frame = 1114, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1080p_30fps, + .mipi_freq = 345600, + }, +}; +#define N_RES_STILL (ARRAY_SIZE(ov2722_res_still)) + +struct ov2722_resolution ov2722_res_video[] = { + { + .desc = "ov2722_QVGA_30fps", + .width = 336, + .height = 256, + .fps = 30, + .pix_clk_freq = 73, + .used = 0, + .pixels_per_line = 2048, + .lines_per_frame = 1184, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_QVGA_30fps, + .mipi_freq = 364800, + }, + { + .desc = "ov2722_480P_30fps", + .width = 736, + .height = 496, + .fps = 30, + .pix_clk_freq = 73, + .used = 0, + .pixels_per_line = 2048, + .lines_per_frame = 1184, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_480P_30fps, + }, + { + .desc = "ov2722_1080P_30fps", + .width = 1932, + .height = 1092, + .pix_clk_freq = 69, + .fps = 30, + .used = 0, + .pixels_per_line = 2068, + .lines_per_frame = 1114, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .skip_frames = 3, + .regs = ov2722_1080p_30fps, + .mipi_freq = 345600, + }, +}; +#define N_RES_VIDEO (ARRAY_SIZE(ov2722_res_video)) + +static struct ov2722_resolution *ov2722_res = ov2722_res_preview; +static int N_RES = N_RES_PREVIEW; +#endif diff --git a/drivers/staging/media/atomisp/i2c/ov5693/Kconfig b/drivers/staging/media/atomisp/i2c/ov5693/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..9fb1bffbe9b3daf8d4811dce4a822a447b24872f --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov5693/Kconfig @@ -0,0 +1,11 @@ +config VIDEO_OV5693 + tristate "Omnivision ov5693 sensor support" + depends on I2C && VIDEO_V4L2 + ---help--- + This is a Video4Linux2 sensor-level driver for the Micron + ov5693 5 Mpixel camera. + + ov5693 is video camera sensor. + + It currently only works with the atomisp driver. + diff --git a/drivers/staging/media/atomisp/i2c/ov5693/Makefile b/drivers/staging/media/atomisp/i2c/ov5693/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..fceb9e9b881bac608e81ae76ed50dad139e2432e --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov5693/Makefile @@ -0,0 +1,3 @@ +obj-$(CONFIG_VIDEO_OV5693) += ov5693.o + +ccflags-y += -Werror diff --git a/drivers/staging/media/atomisp/i2c/ov5693/ad5823.h b/drivers/staging/media/atomisp/i2c/ov5693/ad5823.h new file mode 100644 index 0000000000000000000000000000000000000000..2dd894989cd9793d8d7d652e7fb3bd3d6a56c787 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov5693/ad5823.h @@ -0,0 +1,67 @@ +/* + * Support for AD5823 VCM. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __AD5823_H__ +#define __AD5823_H__ + +#include + + +#define AD5823_VCM_ADDR 0x0c + +#define AD5823_REG_RESET 0x01 +#define AD5823_REG_MODE 0x02 +#define AD5823_REG_VCM_MOVE_TIME 0x03 +#define AD5823_REG_VCM_CODE_MSB 0x04 +#define AD5823_REG_VCM_CODE_LSB 0x05 +#define AD5823_REG_VCM_THRESHOLD_MSB 0x06 +#define AD5823_REG_VCM_THRESHOLD_LSB 0x07 + +#define AD5823_REG_LENGTH 0x1 + +#define AD5823_RING_CTRL_ENABLE 0x04 +#define AD5823_RING_CTRL_DISABLE 0x00 + +#define AD5823_RESONANCE_PERIOD 100000 +#define AD5823_RESONANCE_COEF 512 +#define AD5823_HIGH_FREQ_RANGE 0x80 + +#define VCM_CODE_MSB_MASK 0xfc +#define AD5823_INIT_FOCUS_POS 350 + +enum ad5823_tok_type { + AD5823_8BIT = 0x1, + AD5823_16BIT = 0x2, +}; + +enum ad5823_vcm_mode { + AD5823_ARC_RES0 = 0x0, /* Actuator response control RES1 */ + AD5823_ARC_RES1 = 0x1, /* Actuator response control RES0.5 */ + AD5823_ARC_RES2 = 0x2, /* Actuator response control RES2 */ + AD5823_ESRC = 0x3, /* Enhanced slew rate control */ + AD5823_DIRECT = 0x4, /* Direct control */ +}; + +#define AD5823_INVALID_CONFIG 0xffffffff +#define AD5823_MAX_FOCUS_POS 1023 +#define DELAY_PER_STEP_NS 1000000 +#define DELAY_MAX_PER_STEP_NS (1000000 * 1023) +#endif diff --git a/drivers/staging/media/atomisp/i2c/ov5693/ov5693.c b/drivers/staging/media/atomisp/i2c/ov5693/ov5693.c new file mode 100644 index 0000000000000000000000000000000000000000..790b881cb7cab0ad941a65014d24fc349516dd3d --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov5693/ov5693.c @@ -0,0 +1,2090 @@ +/* + * Support for OmniVision OV5693 1080p HD camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ov5693.h" +#include "ad5823.h" + +#define __cci_delay(t) \ + do { \ + if ((t) < 10) { \ + usleep_range((t) * 1000, ((t) + 1) * 1000); \ + } else { \ + msleep((t)); \ + } \ + } while (0) + +/* Value 30ms reached through experimentation on byt ecs. + * The DS specifies a much lower value but when using a smaller value + * the I2C bus sometimes locks up permanently when starting the camera. + * This issue could not be reproduced on cht, so we can reduce the + * delay value to a lower value when insmod. + */ +static uint up_delay = 30; +module_param(up_delay, uint, 0644); +MODULE_PARM_DESC(up_delay, "Delay prior to the first CCI transaction for ov5693"); + +static int vcm_ad_i2c_wr8(struct i2c_client *client, u8 reg, u8 val) +{ + int err; + struct i2c_msg msg; + u8 buf[2]; + + buf[0] = reg; + buf[1] = val; + + msg.addr = VCM_ADDR; + msg.flags = 0; + msg.len = 2; + msg.buf = &buf[0]; + + err = i2c_transfer(client->adapter, &msg, 1); + if (err != 1) { + dev_err(&client->dev, "%s: vcm i2c fail, err code = %d\n", + __func__, err); + return -EIO; + } + return 0; +} +/*TODO: remove this unuseful i2c writer helper*/ +/* +static int vcm_ad_i2c_wr16(struct i2c_client *client, u8 reg, u16 val) +{ + int err; + struct i2c_msg msg; + u8 buf[3]; + buf[0] = reg; + buf[1] = (u8)(val >> 8); + buf[2] = (u8)(val & 0xff); + msg.addr = VCM_ADDR; + msg.flags = 0; + msg.len = 3; + msg.buf = &buf[0]; + + err = i2c_transfer(client->adapter, &msg, 1); + if (err != 1) { + dev_err(&client->dev, "%s: vcm i2c fail, err code = %d\n", + __func__, err); + return -EIO; + } + return 0; +} +*/ +static int ad5823_i2c_write(struct i2c_client *client, u8 reg, u8 val) +{ + struct i2c_msg msg; + u8 buf[2]; + buf[0] = reg; + buf[1] = val; + msg.addr = AD5823_VCM_ADDR; + msg.flags = 0; + msg.len = 0x02; + msg.buf = &buf[0]; + + if (i2c_transfer(client->adapter, &msg, 1) != 1) + return -EIO; + return 0; +} + +static int ad5823_i2c_read(struct i2c_client *client, u8 reg, u8 *val) +{ + struct i2c_msg msg[2]; + u8 buf[2]; + buf[0] = reg; + buf[1] = 0; + + msg[0].addr = AD5823_VCM_ADDR; + msg[0].flags = 0; + msg[0].len = 0x01; + msg[0].buf = &buf[0]; + + msg[1].addr = 0x0c; + msg[1].flags = I2C_M_RD; + msg[1].len = 0x01; + msg[1].buf = &buf[1]; + *val = 0; + if (i2c_transfer(client->adapter, msg, 2) != 2) + return -EIO; + *val = buf[1]; + return 0; +} + + +static const uint32_t ov5693_embedded_effective_size = 28; + +/* i2c read/write stuff */ +static int ov5693_read_reg(struct i2c_client *client, + u16 data_length, u16 reg, u16 *val) +{ + int err; + struct i2c_msg msg[2]; + unsigned char data[6]; + + if (!client->adapter) { + dev_err(&client->dev, "%s error, no client->adapter\n", + __func__); + return -ENODEV; + } + + if (data_length != OV5693_8BIT && data_length != OV5693_16BIT + && data_length != OV5693_32BIT) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + memset(msg, 0 , sizeof(msg)); + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = I2C_MSG_LENGTH; + msg[0].buf = data; + + /* high byte goes out first */ + data[0] = (u8)(reg >> 8); + data[1] = (u8)(reg & 0xff); + + msg[1].addr = client->addr; + msg[1].len = data_length; + msg[1].flags = I2C_M_RD; + msg[1].buf = data; + + err = i2c_transfer(client->adapter, msg, 2); + if (err != 2) { + if (err >= 0) + err = -EIO; + dev_err(&client->dev, + "read from offset 0x%x error %d", reg, err); + return err; + } + + *val = 0; + /* high byte comes first */ + if (data_length == OV5693_8BIT) + *val = (u8)data[0]; + else if (data_length == OV5693_16BIT) + *val = be16_to_cpu(*(u16 *)&data[0]); + else + *val = be32_to_cpu(*(u32 *)&data[0]); + + return 0; +} + +static int ov5693_i2c_write(struct i2c_client *client, u16 len, u8 *data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = len; + msg.buf = data; + ret = i2c_transfer(client->adapter, &msg, 1); + + return ret == num_msg ? 0 : -EIO; +} + +static int vcm_dw_i2c_write(struct i2c_client *client, u16 data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + u16 val; + + val = cpu_to_be16(data); + msg.addr = VCM_ADDR; + msg.flags = 0; + msg.len = OV5693_16BIT; + msg.buf = (u8 *)&val; + + ret = i2c_transfer(client->adapter, &msg, 1); + + return ret == num_msg ? 0 : -EIO; +} + +/* Theory: per datasheet, the two VCMs both allow for a 2-byte read. + * The DW9714 doesn't actually specify what this does (it has a + * two-byte write-only protocol, but specifies the read sequence as + * legal), but it returns the same data (zeroes) always, after an + * undocumented initial NAK. The AD5823 has a one-byte address + * register to which all writes go, and subsequent reads will cycle + * through the 8 bytes of registers. Notably, the default values (the + * device is always power-cycled affirmatively, so we can rely on + * these) in AD5823 are not pairwise repetitions of the same 16 bit + * word. So all we have to do is sequentially read two bytes at a + * time and see if we detect a difference in any of the first four + * pairs. */ +static int vcm_detect(struct i2c_client *client) +{ + int i, ret; + struct i2c_msg msg; + u16 data0 = 0, data; + for (i = 0; i < 4; i++) { + msg.addr = VCM_ADDR; + msg.flags = I2C_M_RD; + msg.len = sizeof(data); + msg.buf = (u8 *)&data; + ret = i2c_transfer(client->adapter, &msg, 1); + + /* DW9714 always fails the first read and returns + * zeroes for subsequent ones */ + if (i == 0 && ret == -EREMOTEIO) { + data0 = 0; + continue; + } + + if (i == 0) + data0 = data; + + if (data != data0) + return VCM_AD5823; + } + return ret == 1 ? VCM_DW9714 : ret; +} + +static int ov5693_write_reg(struct i2c_client *client, u16 data_length, + u16 reg, u16 val) +{ + int ret; + unsigned char data[4] = {0}; + u16 *wreg = (u16 *)data; + const u16 len = data_length + sizeof(u16); /* 16-bit address + data */ + + if (data_length != OV5693_8BIT && data_length != OV5693_16BIT) { + dev_err(&client->dev, + "%s error, invalid data_length\n", __func__); + return -EINVAL; + } + + /* high byte goes out first */ + *wreg = cpu_to_be16(reg); + + if (data_length == OV5693_8BIT) { + data[2] = (u8)(val); + } else { + /* OV5693_16BIT */ + u16 *wdata = (u16 *)&data[2]; + *wdata = cpu_to_be16(val); + } + + ret = ov5693_i2c_write(client, len, data); + if (ret) + dev_err(&client->dev, + "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, ret); + + return ret; +} + +/* + * ov5693_write_reg_array - Initializes a list of OV5693 registers + * @client: i2c driver client structure + * @reglist: list of registers to be written + * + * This function initializes a list of registers. When consecutive addresses + * are found in a row on the list, this function creates a buffer and sends + * consecutive data in a single i2c_transfer(). + * + * __ov5693_flush_reg_array, __ov5693_buf_reg_array() and + * __ov5693_write_reg_is_consecutive() are internal functions to + * ov5693_write_reg_array_fast() and should be not used anywhere else. + * + */ + +static int __ov5693_flush_reg_array(struct i2c_client *client, + struct ov5693_write_ctrl *ctrl) +{ + u16 size; + + if (ctrl->index == 0) + return 0; + + size = sizeof(u16) + ctrl->index; /* 16-bit address + data */ + ctrl->buffer.addr = cpu_to_be16(ctrl->buffer.addr); + ctrl->index = 0; + + return ov5693_i2c_write(client, size, (u8 *)&ctrl->buffer); +} + +static int __ov5693_buf_reg_array(struct i2c_client *client, + struct ov5693_write_ctrl *ctrl, + const struct ov5693_reg *next) +{ + int size; + u16 *data16; + + switch (next->type) { + case OV5693_8BIT: + size = 1; + ctrl->buffer.data[ctrl->index] = (u8)next->val; + break; + case OV5693_16BIT: + size = 2; + data16 = (u16 *)&ctrl->buffer.data[ctrl->index]; + *data16 = cpu_to_be16((u16)next->val); + break; + default: + return -EINVAL; + } + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->reg; + + ctrl->index += size; + + /* + * Buffer cannot guarantee free space for u32? Better flush it to avoid + * possible lack of memory for next item. + */ + if (ctrl->index + sizeof(u16) >= OV5693_MAX_WRITE_BUF_SIZE) + return __ov5693_flush_reg_array(client, ctrl); + + return 0; +} + +static int __ov5693_write_reg_is_consecutive(struct i2c_client *client, + struct ov5693_write_ctrl *ctrl, + const struct ov5693_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->reg; +} + +static int ov5693_write_reg_array(struct i2c_client *client, + const struct ov5693_reg *reglist) +{ + const struct ov5693_reg *next = reglist; + struct ov5693_write_ctrl ctrl; + int err; + + ctrl.index = 0; + for (; next->type != OV5693_TOK_TERM; next++) { + switch (next->type & OV5693_TOK_MASK) { + case OV5693_TOK_DELAY: + err = __ov5693_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceed. + */ + if (!__ov5693_write_reg_is_consecutive(client, &ctrl, + next)) { + err = __ov5693_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __ov5693_buf_reg_array(client, &ctrl, next); + if (err) { + dev_err(&client->dev, + "%s: write error, aborted\n", + __func__); + return err; + } + break; + } + } + + return __ov5693_flush_reg_array(client, &ctrl); +} +static int ov5693_g_focal(struct v4l2_subdev *sd, s32 *val) +{ + *val = (OV5693_FOCAL_LENGTH_NUM << 16) | OV5693_FOCAL_LENGTH_DEM; + return 0; +} + +static int ov5693_g_fnumber(struct v4l2_subdev *sd, s32 *val) +{ + /*const f number for imx*/ + *val = (OV5693_F_NUMBER_DEFAULT_NUM << 16) | OV5693_F_NUMBER_DEM; + return 0; +} + +static int ov5693_g_fnumber_range(struct v4l2_subdev *sd, s32 *val) +{ + *val = (OV5693_F_NUMBER_DEFAULT_NUM << 24) | + (OV5693_F_NUMBER_DEM << 16) | + (OV5693_F_NUMBER_DEFAULT_NUM << 8) | OV5693_F_NUMBER_DEM; + return 0; +} + +static int ov5693_g_bin_factor_x(struct v4l2_subdev *sd, s32 *val) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + + *val = ov5693_res[dev->fmt_idx].bin_factor_x; + + return 0; +} + +static int ov5693_g_bin_factor_y(struct v4l2_subdev *sd, s32 *val) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + + *val = ov5693_res[dev->fmt_idx].bin_factor_y; + + return 0; +} + +static int ov5693_get_intg_factor(struct i2c_client *client, + struct camera_mipi_info *info, + const struct ov5693_resolution *res) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct atomisp_sensor_mode_data *buf = &info->data; + unsigned int pix_clk_freq_hz; + u16 reg_val; + int ret; + + if (info == NULL) + return -EINVAL; + + /* pixel clock */ + pix_clk_freq_hz = res->pix_clk_freq * 1000000; + + dev->vt_pix_clk_freq_mhz = pix_clk_freq_hz; + buf->vt_pix_clk_freq_mhz = pix_clk_freq_hz; + + /* get integration time */ + buf->coarse_integration_time_min = OV5693_COARSE_INTG_TIME_MIN; + buf->coarse_integration_time_max_margin = + OV5693_COARSE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_min = OV5693_FINE_INTG_TIME_MIN; + buf->fine_integration_time_max_margin = + OV5693_FINE_INTG_TIME_MAX_MARGIN; + + buf->fine_integration_time_def = OV5693_FINE_INTG_TIME_MIN; + buf->frame_length_lines = res->lines_per_frame; + buf->line_length_pck = res->pixels_per_line; + buf->read_mode = res->bin_mode; + + /* get the cropping and output resolution to ISP for this mode. */ + ret = ov5693_read_reg(client, OV5693_16BIT, + OV5693_HORIZONTAL_START_H, ®_val); + if (ret) + return ret; + buf->crop_horizontal_start = reg_val; + + ret = ov5693_read_reg(client, OV5693_16BIT, + OV5693_VERTICAL_START_H, ®_val); + if (ret) + return ret; + buf->crop_vertical_start = reg_val; + + ret = ov5693_read_reg(client, OV5693_16BIT, + OV5693_HORIZONTAL_END_H, ®_val); + if (ret) + return ret; + buf->crop_horizontal_end = reg_val; + + ret = ov5693_read_reg(client, OV5693_16BIT, + OV5693_VERTICAL_END_H, ®_val); + if (ret) + return ret; + buf->crop_vertical_end = reg_val; + + ret = ov5693_read_reg(client, OV5693_16BIT, + OV5693_HORIZONTAL_OUTPUT_SIZE_H, ®_val); + if (ret) + return ret; + buf->output_width = reg_val; + + ret = ov5693_read_reg(client, OV5693_16BIT, + OV5693_VERTICAL_OUTPUT_SIZE_H, ®_val); + if (ret) + return ret; + buf->output_height = reg_val; + + buf->binning_factor_x = res->bin_factor_x ? + res->bin_factor_x : 1; + buf->binning_factor_y = res->bin_factor_y ? + res->bin_factor_y : 1; + return 0; +} + +static long __ov5693_set_exposure(struct v4l2_subdev *sd, int coarse_itg, + int gain, int digitgain) + +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov5693_device *dev = to_ov5693_sensor(sd); + u16 vts, hts; + int ret, exp_val; + + hts = ov5693_res[dev->fmt_idx].pixels_per_line; + vts = ov5693_res[dev->fmt_idx].lines_per_frame; + /*If coarse_itg is larger than 1<<15, can not write to reg directly. + The way is to write coarse_itg/2 to the reg, meanwhile write 2*hts + to the reg. */ + if (coarse_itg > (1 << 15)) { + hts = hts * 2; + coarse_itg = (int)coarse_itg / 2; + } + /* group hold */ + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_GROUP_ACCESS, 0x00); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_GROUP_ACCESS); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_TIMING_HTS_H, (hts >> 8) & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_TIMING_HTS_H); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_TIMING_HTS_L, hts & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_TIMING_HTS_L); + return ret; + } + /* Increase the VTS to match exposure + MARGIN */ + if (coarse_itg > vts - OV5693_INTEGRATION_TIME_MARGIN) + vts = (u16) coarse_itg + OV5693_INTEGRATION_TIME_MARGIN; + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_TIMING_VTS_H, (vts >> 8) & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_TIMING_VTS_H); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_TIMING_VTS_L, vts & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_TIMING_VTS_L); + return ret; + } + + /* set exposure */ + + /* Lower four bit should be 0*/ + exp_val = coarse_itg << 4; + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_EXPOSURE_L, exp_val & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_EXPOSURE_L); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_EXPOSURE_M, (exp_val >> 8) & 0xFF); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_EXPOSURE_M); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_EXPOSURE_H, (exp_val >> 16) & 0x0F); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_EXPOSURE_H); + return ret; + } + + /* Analog gain */ + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_AGC_L, gain & 0xff); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_AGC_L); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_AGC_H, (gain >> 8) & 0xff); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_AGC_H); + return ret; + } + + /* Digital gain */ + if (digitgain) { + ret = ov5693_write_reg(client, OV5693_16BIT, + OV5693_MWB_RED_GAIN_H, digitgain); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_MWB_RED_GAIN_H); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_16BIT, + OV5693_MWB_GREEN_GAIN_H, digitgain); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_MWB_RED_GAIN_H); + return ret; + } + + ret = ov5693_write_reg(client, OV5693_16BIT, + OV5693_MWB_BLUE_GAIN_H, digitgain); + if (ret) { + dev_err(&client->dev, "%s: write %x error, aborted\n", + __func__, OV5693_MWB_RED_GAIN_H); + return ret; + } + } + + /* End group */ + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_GROUP_ACCESS, 0x10); + if (ret) + return ret; + + /* Delay launch group */ + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_GROUP_ACCESS, 0xa0); + if (ret) + return ret; + return ret; +} + +static int ov5693_set_exposure(struct v4l2_subdev *sd, int exposure, + int gain, int digitgain) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __ov5693_set_exposure(sd, exposure, gain, digitgain); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static long ov5693_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + u16 coarse_itg = exposure->integration_time[0]; + u16 analog_gain = exposure->gain[0]; + u16 digital_gain = exposure->gain[1]; + + /* we should not accept the invalid value below */ + if (analog_gain == 0) { + struct i2c_client *client = v4l2_get_subdevdata(sd); + v4l2_err(client, "%s: invalid value\n", __func__); + return -EINVAL; + } + return ov5693_set_exposure(sd, coarse_itg, analog_gain, digital_gain); +} + +static int ov5693_read_otp_reg_array(struct i2c_client *client, u16 size, + u16 addr, u8 * buf) +{ + u16 index; + int ret; + u16 *pVal = 0; + + for (index = 0; index <= size; index++) { + pVal = (u16 *) (buf + index); + ret = + ov5693_read_reg(client, OV5693_8BIT, addr + index, + pVal); + if (ret) + return ret; + } + + return 0; +} + +static int __ov5693_otp_read(struct v4l2_subdev *sd, u8 * buf) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov5693_device *dev = to_ov5693_sensor(sd); + int ret; + int i; + u8 *b = buf; + dev->otp_size = 0; + for (i = 1; i < OV5693_OTP_BANK_MAX; i++) { + /*set bank NO and OTP read mode. */ + ret = ov5693_write_reg(client, OV5693_8BIT, OV5693_OTP_BANK_REG, (i | 0xc0)); //[7:6] 2'b11 [5:0] bank no + if (ret) { + dev_err(&client->dev, "failed to prepare OTP page\n"); + return ret; + } + //pr_debug("write 0x%x->0x%x\n",OV5693_OTP_BANK_REG,(i|0xc0)); + + /*enable read */ + ret = ov5693_write_reg(client, OV5693_8BIT, OV5693_OTP_READ_REG, OV5693_OTP_MODE_READ); // enable :1 + if (ret) { + dev_err(&client->dev, + "failed to set OTP reading mode page"); + return ret; + } + //pr_debug("write 0x%x->0x%x\n",OV5693_OTP_READ_REG,OV5693_OTP_MODE_READ); + + /* Reading the OTP data array */ + ret = ov5693_read_otp_reg_array(client, OV5693_OTP_BANK_SIZE, + OV5693_OTP_START_ADDR, + b); + if (ret) { + dev_err(&client->dev, "failed to read OTP data\n"); + return ret; + } + + //pr_debug("BANK[%2d] %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x %02x\n", i, *b, *(b+1), *(b+2), *(b+3), *(b+4), *(b+5), *(b+6), *(b+7), *(b+8), *(b+9), *(b+10), *(b+11), *(b+12), *(b+13), *(b+14), *(b+15)); + + //Intel OTP map, try to read 320byts first. + if (21 == i) { + if ((*b) == 0) { + dev->otp_size = 320; + break; + } else { + b = buf; + continue; + } + } else if (24 == i) { //if the first 320bytes data doesn't not exist, try to read the next 32bytes data. + if ((*b) == 0) { + dev->otp_size = 32; + break; + } else { + b = buf; + continue; + } + } else if (27 == i) { //if the prvious 32bytes data doesn't exist, try to read the next 32bytes data again. + if ((*b) == 0) { + dev->otp_size = 32; + break; + } else { + dev->otp_size = 0; // no OTP data. + break; + } + } + + b = b + OV5693_OTP_BANK_SIZE; + } + return 0; +} + +/* + * Read otp data and store it into a kmalloced buffer. + * The caller must kfree the buffer when no more needed. + * @size: set to the size of the returned otp data. + */ +static void *ov5693_otp_read(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u8 *buf; + int ret; + + buf = devm_kzalloc(&client->dev, (OV5693_OTP_DATA_SIZE + 16), GFP_KERNEL); + if (!buf) + return ERR_PTR(-ENOMEM); + + //otp valid after mipi on and sw stream on + ret = ov5693_write_reg(client, OV5693_8BIT, OV5693_FRAME_OFF_NUM, 0x00); + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_SW_STREAM, OV5693_START_STREAMING); + + ret = __ov5693_otp_read(sd, buf); + + //mipi off and sw stream off after otp read + ret = ov5693_write_reg(client, OV5693_8BIT, OV5693_FRAME_OFF_NUM, 0x0f); + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_SW_STREAM, OV5693_STOP_STREAMING); + + /* Driver has failed to find valid data */ + if (ret) { + dev_err(&client->dev, "sensor found no valid OTP data\n"); + return ERR_PTR(ret); + } + + return buf; +} + +static int ov5693_g_priv_int_data(struct v4l2_subdev *sd, + struct v4l2_private_int_data *priv) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov5693_device *dev = to_ov5693_sensor(sd); + u8 __user *to = priv->data; + u32 read_size = priv->size; + int ret; + + /* No need to copy data if size is 0 */ + if (!read_size) + goto out; + + if (IS_ERR(dev->otp_data)) { + dev_err(&client->dev, "OTP data not available"); + return PTR_ERR(dev->otp_data); + } + + /* Correct read_size value only if bigger than maximum */ + if (read_size > OV5693_OTP_DATA_SIZE) + read_size = OV5693_OTP_DATA_SIZE; + + ret = copy_to_user(to, dev->otp_data, read_size); + if (ret) { + dev_err(&client->dev, "%s: failed to copy OTP data to user\n", + __func__); + return -EFAULT; + } + + pr_debug("%s read_size:%d\n", __func__, read_size); + +out: + /* Return correct size */ + priv->size = dev->otp_size; + + return 0; + +} + +static long ov5693_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return ov5693_s_exposure(sd, arg); + case ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA: + return ov5693_g_priv_int_data(sd, arg); + default: + return -EINVAL; + } + return 0; +} + +/* This returns the exposure time being used. This should only be used + for filling in EXIF data, not for actual image processing. */ +static int ov5693_q_exposure(struct v4l2_subdev *sd, s32 *value) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 reg_v, reg_v2; + int ret; + + /* get exposure */ + ret = ov5693_read_reg(client, OV5693_8BIT, + OV5693_EXPOSURE_L, + ®_v); + if (ret) + goto err; + + ret = ov5693_read_reg(client, OV5693_8BIT, + OV5693_EXPOSURE_M, + ®_v2); + if (ret) + goto err; + + reg_v += reg_v2 << 8; + ret = ov5693_read_reg(client, OV5693_8BIT, + OV5693_EXPOSURE_H, + ®_v2); + if (ret) + goto err; + + *value = reg_v + (((u32)reg_v2 << 16)); +err: + return ret; +} + +int ad5823_t_focus_vcm(struct v4l2_subdev *sd, u16 val) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = -EINVAL; + u8 vcm_code; + + ret = ad5823_i2c_read(client, AD5823_REG_VCM_CODE_MSB, &vcm_code); + if (ret) + return ret; + + /* set reg VCM_CODE_MSB Bit[1:0] */ + vcm_code = (vcm_code & VCM_CODE_MSB_MASK) | + ((val >> 8) & ~VCM_CODE_MSB_MASK); + ret = ad5823_i2c_write(client, AD5823_REG_VCM_CODE_MSB, vcm_code); + if (ret) + return ret; + + /* set reg VCM_CODE_LSB Bit[7:0] */ + ret = ad5823_i2c_write(client, AD5823_REG_VCM_CODE_LSB, (val & 0xff)); + if (ret) + return ret; + + /* set required vcm move time */ + vcm_code = AD5823_RESONANCE_PERIOD / AD5823_RESONANCE_COEF + - AD5823_HIGH_FREQ_RANGE; + ret = ad5823_i2c_write(client, AD5823_REG_VCM_MOVE_TIME, vcm_code); + + return ret; +} + +int ad5823_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + int ret; + + value = min(value, AD5823_MAX_FOCUS_POS); + ret = ad5823_t_focus_vcm(sd, value); + + return ret; +} + +static int ov5693_t_focus_abs(struct v4l2_subdev *sd, s32 value) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + dev_dbg(&client->dev, "%s: FOCUS_POS: 0x%x\n", __func__, value); + value = clamp(value, 0, OV5693_VCM_MAX_FOCUS_POS); + if (dev->vcm == VCM_DW9714) { + if (dev->vcm_update) { + ret = vcm_dw_i2c_write(client, VCM_PROTECTION_OFF); + if (ret) + return ret; + ret = vcm_dw_i2c_write(client, DIRECT_VCM); + if (ret) + return ret; + ret = vcm_dw_i2c_write(client, VCM_PROTECTION_ON); + if (ret) + return ret; + dev->vcm_update = false; + } + ret = vcm_dw_i2c_write(client, + vcm_val(value, VCM_DEFAULT_S)); + } else if (dev->vcm == VCM_AD5823) { + ad5823_t_focus_abs(sd, value); + } + if (ret == 0) { + dev->number_of_steps = value - dev->focus; + dev->focus = value; + getnstimeofday(&(dev->timestamp_t_focus_abs)); + } else + dev_err(&client->dev, + "%s: i2c failed. ret %d\n", __func__, ret); + + return ret; +} + +static int ov5693_t_focus_rel(struct v4l2_subdev *sd, s32 value) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + return ov5693_t_focus_abs(sd, dev->focus + value); +} + +#define DELAY_PER_STEP_NS 1000000 +#define DELAY_MAX_PER_STEP_NS (1000000 * 1023) +static int ov5693_q_focus_status(struct v4l2_subdev *sd, s32 *value) +{ + u32 status = 0; + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct timespec temptime; + const struct timespec timedelay = { + 0, + min((u32)abs(dev->number_of_steps) * DELAY_PER_STEP_NS, + (u32)DELAY_MAX_PER_STEP_NS), + }; + + getnstimeofday(&temptime); + temptime = timespec_sub(temptime, (dev->timestamp_t_focus_abs)); + if (timespec_compare(&temptime, &timedelay) <= 0) { + status |= ATOMISP_FOCUS_STATUS_MOVING; + status |= ATOMISP_FOCUS_HP_IN_PROGRESS; + } else { + status |= ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE; + status |= ATOMISP_FOCUS_HP_COMPLETE; + } + + *value = status; + + return 0; +} + +static int ov5693_q_focus_abs(struct v4l2_subdev *sd, s32 *value) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + s32 val; + + ov5693_q_focus_status(sd, &val); + + if (val & ATOMISP_FOCUS_STATUS_MOVING) + *value = dev->focus - dev->number_of_steps; + else + *value = dev->focus; + + return 0; +} + +static int ov5693_t_vcm_slew(struct v4l2_subdev *sd, s32 value) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + dev->number_of_steps = value; + dev->vcm_update = true; + return 0; +} + +static int ov5693_t_vcm_timing(struct v4l2_subdev *sd, s32 value) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + dev->number_of_steps = value; + dev->vcm_update = true; + return 0; +} + +static int ov5693_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov5693_device *dev = + container_of(ctrl->handler, struct ov5693_device, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_FOCUS_ABSOLUTE: + dev_dbg(&client->dev, "%s: CID_FOCUS_ABSOLUTE:%d.\n", + __func__, ctrl->val); + ret = ov5693_t_focus_abs(&dev->sd, ctrl->val); + break; + case V4L2_CID_FOCUS_RELATIVE: + dev_dbg(&client->dev, "%s: CID_FOCUS_RELATIVE:%d.\n", + __func__, ctrl->val); + ret = ov5693_t_focus_rel(&dev->sd, ctrl->val); + break; + case V4L2_CID_VCM_SLEW: + ret = ov5693_t_vcm_slew(&dev->sd, ctrl->val); + break; + case V4L2_CID_VCM_TIMEING: + ret = ov5693_t_vcm_timing(&dev->sd, ctrl->val); + break; + default: + ret = -EINVAL; + } + return ret; +} + +static int ov5693_g_volatile_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov5693_device *dev = + container_of(ctrl->handler, struct ov5693_device, ctrl_handler); + int ret = 0; + + switch (ctrl->id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + ret = ov5693_q_exposure(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCAL_ABSOLUTE: + ret = ov5693_g_focal(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_ABSOLUTE: + ret = ov5693_g_fnumber(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FNUMBER_RANGE: + ret = ov5693_g_fnumber_range(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCUS_ABSOLUTE: + ret = ov5693_q_focus_abs(&dev->sd, &ctrl->val); + break; + case V4L2_CID_FOCUS_STATUS: + ret = ov5693_q_focus_status(&dev->sd, &ctrl->val); + + case V4L2_CID_BIN_FACTOR_HORZ: + ret = ov5693_g_bin_factor_x(&dev->sd, &ctrl->val); + break; + case V4L2_CID_BIN_FACTOR_VERT: + ret = ov5693_g_bin_factor_y(&dev->sd, &ctrl->val); + break; + default: + ret = -EINVAL; + } + + return ret; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = ov5693_s_ctrl, + .g_volatile_ctrl = ov5693_g_volatile_ctrl +}; + +struct v4l2_ctrl_config ov5693_controls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .min = 0x0, + .max = 0xffff, + .step = 0x01, + .def = 0x00, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focal length", + .min = OV5693_FOCAL_LENGTH_DEFAULT, + .max = OV5693_FOCAL_LENGTH_DEFAULT, + .step = 0x01, + .def = OV5693_FOCAL_LENGTH_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number", + .min = OV5693_F_NUMBER_DEFAULT, + .max = OV5693_F_NUMBER_DEFAULT, + .step = 0x01, + .def = OV5693_F_NUMBER_DEFAULT, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "f-number range", + .min = OV5693_F_NUMBER_RANGE, + .max = OV5693_F_NUMBER_RANGE, + .step = 0x01, + .def = OV5693_F_NUMBER_RANGE, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_ABSOLUTE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focus move absolute", + .min = 0, + .max = OV5693_VCM_MAX_FOCUS_POS, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_RELATIVE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focus move relative", + .min = OV5693_VCM_MAX_FOCUS_NEG, + .max = OV5693_VCM_MAX_FOCUS_POS, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_STATUS, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "focus status", + .min = 0, + .max = 100, /* allow enum to grow in the future */ + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VCM_SLEW, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vcm slew", + .min = 0, + .max = OV5693_VCM_SLEW_STEP_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_VCM_TIMEING, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vcm step time", + .min = 0, + .max = OV5693_VCM_SLEW_TIME_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_HORZ, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "horizontal binning factor", + .min = 0, + .max = OV5693_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, + { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_VERT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "vertical binning factor", + .min = 0, + .max = OV5693_BIN_FACTOR_MAX, + .step = 1, + .def = 0, + .flags = 0, + }, +}; + +static int ov5693_init(struct v4l2_subdev *sd) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + pr_info("%s\n", __func__); + mutex_lock(&dev->input_lock); + dev->vcm_update = false; + + if (dev->vcm == VCM_AD5823) { + ret = vcm_ad_i2c_wr8(client, 0x01, 0x01); /* vcm init test */ + if (ret) + dev_err(&client->dev, + "vcm reset failed\n"); + /*change the mode*/ + ret = ad5823_i2c_write(client, AD5823_REG_VCM_CODE_MSB, + AD5823_RING_CTRL_ENABLE); + if (ret) + dev_err(&client->dev, + "vcm enable ringing failed\n"); + ret = ad5823_i2c_write(client, AD5823_REG_MODE, + AD5823_ARC_RES1); + if (ret) + dev_err(&client->dev, + "vcm change mode failed\n"); + } + + /*change initial focus value for ad5823*/ + if (dev->vcm == VCM_AD5823) { + dev->focus = AD5823_INIT_FOCUS_POS; + ov5693_t_focus_abs(sd, AD5823_INIT_FOCUS_POS); + } else { + dev->focus = 0; + ov5693_t_focus_abs(sd, 0); + } + + mutex_unlock(&dev->input_lock); + + return 0; +} + +static int power_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret; + struct ov5693_device *dev = to_ov5693_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->power_ctrl) + return dev->platform_data->power_ctrl(sd, flag); + + /* This driver assumes "internal DVDD, PWDNB tied to DOVDD". + * In this set up only gpio0 (XSHUTDN) should be available + * but in some products (for example ECS) gpio1 (PWDNB) is + * also available. If gpio1 is available we emulate it being + * tied to DOVDD here. */ + if (flag) { + ret = dev->platform_data->v2p8_ctrl(sd, 1); + dev->platform_data->gpio1_ctrl(sd, 1); + if (ret == 0) { + ret = dev->platform_data->v1p8_ctrl(sd, 1); + if (ret) { + dev->platform_data->gpio1_ctrl(sd, 0); + ret = dev->platform_data->v2p8_ctrl(sd, 0); + } + } + } else { + dev->platform_data->gpio1_ctrl(sd, 0); + ret = dev->platform_data->v1p8_ctrl(sd, 0); + ret |= dev->platform_data->v2p8_ctrl(sd, 0); + } + + return ret; +} + +static int gpio_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret; + struct ov5693_device *dev = to_ov5693_sensor(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->gpio_ctrl) + return dev->platform_data->gpio_ctrl(sd, flag); + + ret = dev->platform_data->gpio0_ctrl(sd, flag); + + return ret; +} + +static int __power_up(struct v4l2_subdev *sd) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + if (NULL == dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + /* power control */ + ret = power_ctrl(sd, 1); + if (ret) + goto fail_power; + + /* according to DS, at least 5ms is needed between DOVDD and PWDN */ + /* add this delay time to 10~11ms*/ + usleep_range(10000, 11000); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 1); + if (ret) { + ret = gpio_ctrl(sd, 1); + if (ret) + goto fail_power; + } + + /* flis clock control */ + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) + goto fail_clk; + + __cci_delay(up_delay); + + return 0; + +fail_clk: + gpio_ctrl(sd, 0); +fail_power: + power_ctrl(sd, 0); + dev_err(&client->dev, "sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + dev->focus = OV5693_INVALID_CONFIG; + if (NULL == dev->platform_data) { + dev_err(&client->dev, + "no camera_sensor_platform_data"); + return -ENODEV; + } + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk failed\n"); + + /* gpio ctrl */ + ret = gpio_ctrl(sd, 0); + if (ret) { + ret = gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio failed 2\n"); + } + + /* power control */ + ret = power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "vprog failed.\n"); + + return ret; +} + +static int power_up(struct v4l2_subdev *sd) +{ + static const int retry_count = 4; + int i, ret; + + for (i = 0; i < retry_count; i++) { + ret = __power_up(sd); + if (!ret) + return 0; + + power_down(sd); + } + return ret; +} + +static int ov5693_s_power(struct v4l2_subdev *sd, int on) +{ + int ret; + + pr_info("%s: on %d\n", __func__, on); + if (on == 0) + return power_down(sd); + else { + ret = power_up(sd); + if (!ret) { + ret = ov5693_init(sd); + /* restore settings */ + ov5693_res = ov5693_res_preview; + N_RES = N_RES_PREVIEW; + } + } + return ret; +} + +/* + * distance - calculate the distance + * @res: resolution + * @w: width + * @h: height + * + * Get the gap between res_w/res_h and w/h. + * distance = (res_w/res_h - w/h) / (w/h) * 8192 + * res->width/height smaller than w/h wouldn't be considered. + * The gap of ratio larger than 1/8 wouldn't be considered. + * Returns the value of gap or -1 if fail. + */ +#define LARGEST_ALLOWED_RATIO_MISMATCH 1024 +static int distance(struct ov5693_resolution *res, u32 w, u32 h) +{ + int ratio; + int distance; + + if (w == 0 || h == 0 || + res->width < w || res->height < h) + return -1; + + ratio = (res->width << 13); + ratio /= w; + ratio *= h; + ratio /= res->height; + + distance = abs(ratio - 8192); + + if (distance > LARGEST_ALLOWED_RATIO_MISMATCH) + return -1; + + return distance; +} + +/* Return the nearest higher resolution index + * Firstly try to find the approximate aspect ratio resolution + * If we find multiple same AR resolutions, choose the + * minimal size. + */ +static int nearest_resolution_index(int w, int h) +{ + int i; + int idx = -1; + int dist; + int min_dist = INT_MAX; + int min_res_w = INT_MAX; + struct ov5693_resolution *tmp_res = NULL; + + for (i = 0; i < N_RES; i++) { + tmp_res = &ov5693_res[i]; + dist = distance(tmp_res, w, h); + if (dist == -1) + continue; + if (dist < min_dist) { + min_dist = dist; + idx = i; + min_res_w = ov5693_res[i].width; + continue; + } + if (dist == min_dist && ov5693_res[i].width < min_res_w) + idx = i; + } + + return idx; +} + +static int get_resolution_index(int w, int h) +{ + int i; + + for (i = 0; i < N_RES; i++) { + if (w != ov5693_res[i].width) + continue; + if (h != ov5693_res[i].height) + continue; + + return i; + } + + return -1; +} + +/* TODO: remove it. */ +static int startup(struct v4l2_subdev *sd) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + ret = ov5693_write_reg(client, OV5693_8BIT, + OV5693_SW_RESET, 0x01); + if (ret) { + dev_err(&client->dev, "ov5693 reset err.\n"); + return ret; + } + + ret = ov5693_write_reg_array(client, ov5693_global_setting); + if (ret) { + dev_err(&client->dev, "ov5693 write register err.\n"); + return ret; + } + + ret = ov5693_write_reg_array(client, ov5693_res[dev->fmt_idx].regs); + if (ret) { + dev_err(&client->dev, "ov5693 write register err.\n"); + return ret; + } + + return ret; +} + +static int ov5693_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct camera_mipi_info *ov5693_info = NULL; + int ret = 0; + int idx; + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + ov5693_info = v4l2_get_subdev_hostdata(sd); + if (ov5693_info == NULL) + return -EINVAL; + + mutex_lock(&dev->input_lock); + idx = nearest_resolution_index(fmt->width, fmt->height); + if (idx == -1) { + /* return the largest resolution */ + fmt->width = ov5693_res[N_RES - 1].width; + fmt->height = ov5693_res[N_RES - 1].height; + } else { + fmt->width = ov5693_res[idx].width; + fmt->height = ov5693_res[idx].height; + } + + fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + cfg->try_fmt = *fmt; + mutex_unlock(&dev->input_lock); + return 0; + } + + dev->fmt_idx = get_resolution_index(fmt->width, fmt->height); + if (dev->fmt_idx == -1) { + dev_err(&client->dev, "get resolution fail\n"); + mutex_unlock(&dev->input_lock); + return -EINVAL; + } + + ret = startup(sd); + if (ret) { + int i = 0; + dev_err(&client->dev, "ov5693 startup err, retry to power up\n"); + for (i = 0; i < OV5693_POWER_UP_RETRY_NUM; i++) { + dev_err(&client->dev, + "ov5693 retry to power up %d/%d times, result: ", + i+1, OV5693_POWER_UP_RETRY_NUM); + power_down(sd); + ret = power_up(sd); + if (!ret) { + mutex_unlock(&dev->input_lock); + ov5693_init(sd); + mutex_lock(&dev->input_lock); + } else { + dev_err(&client->dev, "power up failed, continue\n"); + continue; + } + ret = startup(sd); + if (ret) { + dev_err(&client->dev, " startup FAILED!\n"); + } else { + dev_err(&client->dev, " startup SUCCESS!\n"); + break; + } + } + } + + /* + * After sensor settings are set to HW, sometimes stream is started. + * This would cause ISP timeout because ISP is not ready to receive + * data yet. So add stop streaming here. + */ + ret = ov5693_write_reg(client, OV5693_8BIT, OV5693_SW_STREAM, + OV5693_STOP_STREAMING); + if (ret) + dev_warn(&client->dev, "ov5693 stream off err\n"); + + ret = ov5693_get_intg_factor(client, ov5693_info, + &ov5693_res[dev->fmt_idx]); + if (ret) { + dev_err(&client->dev, "failed to get integration_factor\n"); + goto err; + } + + ov5693_info->metadata_width = fmt->width * 10 / 8; + ov5693_info->metadata_height = 1; + ov5693_info->metadata_effective_width = &ov5693_embedded_effective_size; + +err: + mutex_unlock(&dev->input_lock); + return ret; +} +static int ov5693_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov5693_device *dev = to_ov5693_sensor(sd); + if (format->pad) + return -EINVAL; + + if (!fmt) + return -EINVAL; + + fmt->width = ov5693_res[dev->fmt_idx].width; + fmt->height = ov5693_res[dev->fmt_idx].height; + fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; + + return 0; +} + +static int ov5693_detect(struct i2c_client *client) +{ + struct i2c_adapter *adapter = client->adapter; + u16 high, low; + int ret; + u16 id; + u8 revision; + + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + + ret = ov5693_read_reg(client, OV5693_8BIT, + OV5693_SC_CMMN_CHIP_ID_H, &high); + if (ret) { + dev_err(&client->dev, "sensor_id_high = 0x%x\n", high); + return -ENODEV; + } + ret = ov5693_read_reg(client, OV5693_8BIT, + OV5693_SC_CMMN_CHIP_ID_L, &low); + id = ((((u16) high) << 8) | (u16) low); + + if (id != OV5693_ID) { + dev_err(&client->dev, "sensor ID error 0x%x\n", id); + return -ENODEV; + } + + ret = ov5693_read_reg(client, OV5693_8BIT, + OV5693_SC_CMMN_SUB_ID, &high); + revision = (u8) high & 0x0f; + + dev_dbg(&client->dev, "sensor_revision = 0x%x\n", revision); + dev_dbg(&client->dev, "detect ov5693 success\n"); + return 0; +} + +static int ov5693_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + mutex_lock(&dev->input_lock); + + ret = ov5693_write_reg(client, OV5693_8BIT, OV5693_SW_STREAM, + enable ? OV5693_START_STREAMING : + OV5693_STOP_STREAMING); + + mutex_unlock(&dev->input_lock); + + return ret; +} + + +static int ov5693_s_config(struct v4l2_subdev *sd, + int irq, void *platform_data) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret = 0; + + if (platform_data == NULL) + return -ENODEV; + + dev->platform_data = + (struct camera_sensor_platform_data *)platform_data; + + mutex_lock(&dev->input_lock); + /* power off the module, then power on it in future + * as first power on by board may not fulfill the + * power on sequqence needed by the module + */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "ov5693 power-off err.\n"); + goto fail_power_off; + } + + ret = power_up(sd); + if (ret) { + dev_err(&client->dev, "ov5693 power-up err.\n"); + goto fail_power_on; + } + + if (!dev->vcm) + dev->vcm = vcm_detect(client); + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + /* config & detect sensor */ + ret = ov5693_detect(client); + if (ret) { + dev_err(&client->dev, "ov5693_detect err s_config.\n"); + goto fail_csi_cfg; + } + + dev->otp_data = ov5693_otp_read(sd); + + /* turn off sensor, after probed */ + ret = power_down(sd); + if (ret) { + dev_err(&client->dev, "ov5693 power-off err.\n"); + goto fail_csi_cfg; + } + mutex_unlock(&dev->input_lock); + + return ret; + +fail_csi_cfg: + dev->platform_data->csi_cfg(sd, 0); +fail_power_on: + power_down(sd); + dev_err(&client->dev, "sensor power-gating failed\n"); +fail_power_off: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int ov5693_g_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + + if (!param) + return -EINVAL; + + if (param->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + dev_err(&client->dev, "unsupported buffer type.\n"); + return -EINVAL; + } + + memset(param, 0, sizeof(*param)); + param->type = V4L2_BUF_TYPE_VIDEO_CAPTURE; + + if (dev->fmt_idx >= 0 && dev->fmt_idx < N_RES) { + param->parm.capture.capability = V4L2_CAP_TIMEPERFRAME; + param->parm.capture.timeperframe.numerator = 1; + param->parm.capture.capturemode = dev->run_mode; + param->parm.capture.timeperframe.denominator = + ov5693_res[dev->fmt_idx].fps; + } + return 0; +} + +static int ov5693_s_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + dev->run_mode = param->parm.capture.capturemode; + + mutex_lock(&dev->input_lock); + switch (dev->run_mode) { + case CI_MODE_VIDEO: + ov5693_res = ov5693_res_video; + N_RES = N_RES_VIDEO; + break; + case CI_MODE_STILL_CAPTURE: + ov5693_res = ov5693_res_still; + N_RES = N_RES_STILL; + break; + default: + ov5693_res = ov5693_res_preview; + N_RES = N_RES_PREVIEW; + } + mutex_unlock(&dev->input_lock); + return 0; +} + +static int ov5693_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct ov5693_device *dev = to_ov5693_sensor(sd); + + interval->interval.numerator = 1; + interval->interval.denominator = ov5693_res[dev->fmt_idx].fps; + + return 0; +} + +static int ov5693_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= MAX_FMTS) + return -EINVAL; + + code->code = MEDIA_BUS_FMT_SBGGR10_1X10; + return 0; +} + +static int ov5693_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + int index = fse->index; + + if (index >= N_RES) + return -EINVAL; + + fse->min_width = ov5693_res[index].width; + fse->min_height = ov5693_res[index].height; + fse->max_width = ov5693_res[index].width; + fse->max_height = ov5693_res[index].height; + + return 0; + +} + +static const struct v4l2_subdev_video_ops ov5693_video_ops = { + .s_stream = ov5693_s_stream, + .g_parm = ov5693_g_parm, + .s_parm = ov5693_s_parm, + .g_frame_interval = ov5693_g_frame_interval, +}; + +static const struct v4l2_subdev_core_ops ov5693_core_ops = { + .s_power = ov5693_s_power, + .ioctl = ov5693_ioctl, +}; + +static const struct v4l2_subdev_pad_ops ov5693_pad_ops = { + .enum_mbus_code = ov5693_enum_mbus_code, + .enum_frame_size = ov5693_enum_frame_size, + .get_fmt = ov5693_get_fmt, + .set_fmt = ov5693_set_fmt, +}; + +static const struct v4l2_subdev_ops ov5693_ops = { + .core = &ov5693_core_ops, + .video = &ov5693_video_ops, + .pad = &ov5693_pad_ops, +}; + +static int ov5693_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov5693_device *dev = to_ov5693_sensor(sd); + dev_dbg(&client->dev, "ov5693_remove...\n"); + + dev->platform_data->csi_cfg(sd, 0); + + v4l2_device_unregister_subdev(sd); + + atomisp_gmin_remove_subdev(sd); + + media_entity_cleanup(&dev->sd.entity); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + kfree(dev); + + return 0; +} + +static int ov5693_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct ov5693_device *dev; + int i2c; + int ret = 0; + void *pdata = client->dev.platform_data; + struct acpi_device *adev; + unsigned int i; + + /* Firmware workaround: Some modules use a "secondary default" + * address of 0x10 which doesn't appear on schematics, and + * some BIOS versions haven't gotten the memo. Work around + * via config. */ + i2c = gmin_get_var_int(&client->dev, "I2CAddr", -1); + if (i2c != -1) { + dev_info(&client->dev, + "Overriding firmware-provided I2C address (0x%x) with 0x%x\n", + client->addr, i2c); + client->addr = i2c; + } + + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) { + dev_err(&client->dev, "out of memory\n"); + return -ENOMEM; + } + + mutex_init(&dev->input_lock); + + dev->fmt_idx = 0; + v4l2_i2c_subdev_init(&(dev->sd), client, &ov5693_ops); + + adev = ACPI_COMPANION(&client->dev); + if (adev) { + adev->power.flags.power_resources = 0; + pdata = gmin_camera_platform_data(&dev->sd, + ATOMISP_INPUT_FORMAT_RAW_10, + atomisp_bayer_order_bggr); + } + + if (!pdata) + goto out_free; + + ret = ov5693_s_config(&dev->sd, client->irq, pdata); + if (ret) + goto out_free; + + ret = atomisp_register_i2c_module(&dev->sd, pdata, RAW_CAMERA); + if (ret) + goto out_free; + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = MEDIA_BUS_FMT_SBGGR10_1X10; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + ret = + v4l2_ctrl_handler_init(&dev->ctrl_handler, + ARRAY_SIZE(ov5693_controls)); + if (ret) { + ov5693_remove(client); + return ret; + } + + for (i = 0; i < ARRAY_SIZE(ov5693_controls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &ov5693_controls[i], + NULL); + + if (dev->ctrl_handler.error) { + ov5693_remove(client); + return dev->ctrl_handler.error; + } + + /* Use same lock for controls as for everything else. */ + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = &dev->ctrl_handler; + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) + ov5693_remove(client); + + return ret; +out_free: + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + return ret; +} + +MODULE_DEVICE_TABLE(i2c, ov5693_id); + +static struct acpi_device_id ov5693_acpi_match[] = { + {"INT33BE"}, + {}, +}; +MODULE_DEVICE_TABLE(acpi, ov5693_acpi_match); + +static struct i2c_driver ov5693_driver = { + .driver = { + .owner = THIS_MODULE, + .name = OV5693_NAME, + .acpi_match_table = ACPI_PTR(ov5693_acpi_match), + }, + .probe = ov5693_probe, + .remove = ov5693_remove, + .id_table = ov5693_id, +}; + +static int init_ov5693(void) +{ + return i2c_add_driver(&ov5693_driver); +} + +static void exit_ov5693(void) +{ + + i2c_del_driver(&ov5693_driver); +} + +module_init(init_ov5693); +module_exit(exit_ov5693); + +MODULE_DESCRIPTION("A low-level driver for OmniVision 5693 sensors"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/ov5693/ov5693.h b/drivers/staging/media/atomisp/i2c/ov5693/ov5693.h new file mode 100644 index 0000000000000000000000000000000000000000..14ed4d1a1f4ebc64f4b10565062184a962063a8a --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov5693/ov5693.h @@ -0,0 +1,1381 @@ +/* + * Support for OmniVision OV5693 5M camera sensor. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __OV5693_H__ +#define __OV5693_H__ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define OV5693_NAME "ov5693" + +#define OV5693_POWER_UP_RETRY_NUM 5 + +/* Defines for register writes and register array processing */ +#define I2C_MSG_LENGTH 0x2 +#define I2C_RETRY_COUNT 5 + +#define OV5693_FOCAL_LENGTH_NUM 334 /*3.34mm*/ +#define OV5693_FOCAL_LENGTH_DEM 100 +#define OV5693_F_NUMBER_DEFAULT_NUM 24 +#define OV5693_F_NUMBER_DEM 10 + +#define MAX_FMTS 1 + +/* sensor_mode_data read_mode adaptation */ +#define OV5693_READ_MODE_BINNING_ON 0x0400 +#define OV5693_READ_MODE_BINNING_OFF 0x00 +#define OV5693_INTEGRATION_TIME_MARGIN 8 + +#define OV5693_MAX_EXPOSURE_VALUE 0xFFF1 +#define OV5693_MAX_GAIN_VALUE 0xFF + +/* + * focal length bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define OV5693_FOCAL_LENGTH_DEFAULT 0x1B70064 + +/* + * current f-number bits definition: + * bits 31-16: numerator, bits 15-0: denominator + */ +#define OV5693_F_NUMBER_DEFAULT 0x18000a + +/* + * f-number range bits definition: + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ +#define OV5693_F_NUMBER_RANGE 0x180a180a +#define OV5693_ID 0x5690 + +#define OV5693_FINE_INTG_TIME_MIN 0 +#define OV5693_FINE_INTG_TIME_MAX_MARGIN 0 +#define OV5693_COARSE_INTG_TIME_MIN 1 +#define OV5693_COARSE_INTG_TIME_MAX_MARGIN 6 + +#define OV5693_BIN_FACTOR_MAX 4 +/* + * OV5693 System control registers + */ +#define OV5693_SW_SLEEP 0x0100 +#define OV5693_SW_RESET 0x0103 +#define OV5693_SW_STREAM 0x0100 + +#define OV5693_SC_CMMN_CHIP_ID_H 0x300A +#define OV5693_SC_CMMN_CHIP_ID_L 0x300B +#define OV5693_SC_CMMN_SCCB_ID 0x300C +#define OV5693_SC_CMMN_SUB_ID 0x302A /* process, version*/ +/*Bit[7:4] Group control, Bit[3:0] Group ID*/ +#define OV5693_GROUP_ACCESS 0x3208 +/* +*Bit[3:0] Bit[19:16] of exposure, +*remaining 16 bits lies in Reg0x3501&Reg0x3502 +*/ +#define OV5693_EXPOSURE_H 0x3500 +#define OV5693_EXPOSURE_M 0x3501 +#define OV5693_EXPOSURE_L 0x3502 +/*Bit[1:0] means Bit[9:8] of gain*/ +#define OV5693_AGC_H 0x350A +#define OV5693_AGC_L 0x350B /*Bit[7:0] of gain*/ + +#define OV5693_HORIZONTAL_START_H 0x3800 /*Bit[11:8]*/ +#define OV5693_HORIZONTAL_START_L 0x3801 /*Bit[7:0]*/ +#define OV5693_VERTICAL_START_H 0x3802 /*Bit[11:8]*/ +#define OV5693_VERTICAL_START_L 0x3803 /*Bit[7:0]*/ +#define OV5693_HORIZONTAL_END_H 0x3804 /*Bit[11:8]*/ +#define OV5693_HORIZONTAL_END_L 0x3805 /*Bit[7:0]*/ +#define OV5693_VERTICAL_END_H 0x3806 /*Bit[11:8]*/ +#define OV5693_VERTICAL_END_L 0x3807 /*Bit[7:0]*/ +#define OV5693_HORIZONTAL_OUTPUT_SIZE_H 0x3808 /*Bit[3:0]*/ +#define OV5693_HORIZONTAL_OUTPUT_SIZE_L 0x3809 /*Bit[7:0]*/ +#define OV5693_VERTICAL_OUTPUT_SIZE_H 0x380a /*Bit[3:0]*/ +#define OV5693_VERTICAL_OUTPUT_SIZE_L 0x380b /*Bit[7:0]*/ +/*High 8-bit, and low 8-bit HTS address is 0x380d*/ +#define OV5693_TIMING_HTS_H 0x380C +/*High 8-bit, and low 8-bit HTS address is 0x380d*/ +#define OV5693_TIMING_HTS_L 0x380D +/*High 8-bit, and low 8-bit HTS address is 0x380f*/ +#define OV5693_TIMING_VTS_H 0x380e +/*High 8-bit, and low 8-bit HTS address is 0x380f*/ +#define OV5693_TIMING_VTS_L 0x380f + +#define OV5693_MWB_RED_GAIN_H 0x3400 +#define OV5693_MWB_GREEN_GAIN_H 0x3402 +#define OV5693_MWB_BLUE_GAIN_H 0x3404 +#define OV5693_MWB_GAIN_MAX 0x0fff + +#define OV5693_START_STREAMING 0x01 +#define OV5693_STOP_STREAMING 0x00 + +#define VCM_ADDR 0x0c +#define VCM_CODE_MSB 0x04 + +#define OV5693_INVALID_CONFIG 0xffffffff + +#define OV5693_VCM_SLEW_STEP 0x30F0 +#define OV5693_VCM_SLEW_STEP_MAX 0x7 +#define OV5693_VCM_SLEW_STEP_MASK 0x7 +#define OV5693_VCM_CODE 0x30F2 +#define OV5693_VCM_SLEW_TIME 0x30F4 +#define OV5693_VCM_SLEW_TIME_MAX 0xffff +#define OV5693_VCM_ENABLE 0x8000 + +#define OV5693_VCM_MAX_FOCUS_NEG -1023 +#define OV5693_VCM_MAX_FOCUS_POS 1023 + +#define DLC_ENABLE 1 +#define DLC_DISABLE 0 +#define VCM_PROTECTION_OFF 0xeca3 +#define VCM_PROTECTION_ON 0xdc51 +#define VCM_DEFAULT_S 0x0 +#define vcm_step_s(a) (u8)(a & 0xf) +#define vcm_step_mclk(a) (u8)((a >> 4) & 0x3) +#define vcm_dlc_mclk(dlc, mclk) (u16)((dlc << 3) | mclk | 0xa104) +#define vcm_tsrc(tsrc) (u16)(tsrc << 3 | 0xf200) +#define vcm_val(data, s) (u16)(data << 4 | s) +#define DIRECT_VCM vcm_dlc_mclk(0, 0) + +/* Defines for OTP Data Registers */ +#define OV5693_FRAME_OFF_NUM 0x4202 +#define OV5693_OTP_BYTE_MAX 32 //change to 32 as needed by otpdata +#define OV5693_OTP_SHORT_MAX 16 +#define OV5693_OTP_START_ADDR 0x3D00 +#define OV5693_OTP_END_ADDR 0x3D0F +#define OV5693_OTP_DATA_SIZE 320 +#define OV5693_OTP_PROGRAM_REG 0x3D80 +#define OV5693_OTP_READ_REG 0x3D81 // 1:Enable 0:disable +#define OV5693_OTP_BANK_REG 0x3D84 //otp bank and mode +#define OV5693_OTP_READY_REG_DONE 1 +#define OV5693_OTP_BANK_MAX 28 +#define OV5693_OTP_BANK_SIZE 16 //16 bytes per bank +#define OV5693_OTP_READ_ONETIME 16 +#define OV5693_OTP_MODE_READ 1 + +struct regval_list { + u16 reg_num; + u8 value; +}; + +struct ov5693_resolution { + u8 *desc; + const struct ov5693_reg *regs; + int res; + int width; + int height; + int fps; + int pix_clk_freq; + u16 pixels_per_line; + u16 lines_per_frame; + u8 bin_factor_x; + u8 bin_factor_y; + u8 bin_mode; + bool used; +}; + +struct ov5693_format { + u8 *desc; + u32 pixelformat; + struct ov5693_reg *regs; +}; + +enum vcm_type { + VCM_UNKNOWN, + VCM_AD5823, + VCM_DW9714, +}; + +/* + * ov5693 device structure. + */ +struct ov5693_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + struct mutex input_lock; + struct v4l2_ctrl_handler ctrl_handler; + + struct camera_sensor_platform_data *platform_data; + struct timespec timestamp_t_focus_abs; + int vt_pix_clk_freq_mhz; + int fmt_idx; + int run_mode; + int otp_size; + u8 *otp_data; + u32 focus; + s16 number_of_steps; + u8 res; + u8 type; + bool vcm_update; + enum vcm_type vcm; +}; + +enum ov5693_tok_type { + OV5693_8BIT = 0x0001, + OV5693_16BIT = 0x0002, + OV5693_32BIT = 0x0004, + OV5693_TOK_TERM = 0xf000, /* terminating token for reg list */ + OV5693_TOK_DELAY = 0xfe00, /* delay token for reg list */ + OV5693_TOK_MASK = 0xfff0 +}; + +/** + * struct ov5693_reg - MI sensor register format + * @type: type of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ +struct ov5693_reg { + enum ov5693_tok_type type; + u16 reg; + u32 val; /* @set value for read/mod/write, @mask */ +}; + +#define to_ov5693_sensor(x) container_of(x, struct ov5693_device, sd) + +#define OV5693_MAX_WRITE_BUF_SIZE 30 + +struct ov5693_write_buffer { + u16 addr; + u8 data[OV5693_MAX_WRITE_BUF_SIZE]; +}; + +struct ov5693_write_ctrl { + int index; + struct ov5693_write_buffer buffer; +}; + +static const struct i2c_device_id ov5693_id[] = { + {OV5693_NAME, 0}, + {} +}; + +static struct ov5693_reg const ov5693_global_setting[] = { + {OV5693_8BIT, 0x0103, 0x01}, + {OV5693_8BIT, 0x3001, 0x0a}, + {OV5693_8BIT, 0x3002, 0x80}, + {OV5693_8BIT, 0x3006, 0x00}, + {OV5693_8BIT, 0x3011, 0x21}, + {OV5693_8BIT, 0x3012, 0x09}, + {OV5693_8BIT, 0x3013, 0x10}, + {OV5693_8BIT, 0x3014, 0x00}, + {OV5693_8BIT, 0x3015, 0x08}, + {OV5693_8BIT, 0x3016, 0xf0}, + {OV5693_8BIT, 0x3017, 0xf0}, + {OV5693_8BIT, 0x3018, 0xf0}, + {OV5693_8BIT, 0x301b, 0xb4}, + {OV5693_8BIT, 0x301d, 0x02}, + {OV5693_8BIT, 0x3021, 0x00}, + {OV5693_8BIT, 0x3022, 0x01}, + {OV5693_8BIT, 0x3028, 0x44}, + {OV5693_8BIT, 0x3098, 0x02}, + {OV5693_8BIT, 0x3099, 0x19}, + {OV5693_8BIT, 0x309a, 0x02}, + {OV5693_8BIT, 0x309b, 0x01}, + {OV5693_8BIT, 0x309c, 0x00}, + {OV5693_8BIT, 0x30a0, 0xd2}, + {OV5693_8BIT, 0x30a2, 0x01}, + {OV5693_8BIT, 0x30b2, 0x00}, + {OV5693_8BIT, 0x30b3, 0x7d}, + {OV5693_8BIT, 0x30b4, 0x03}, + {OV5693_8BIT, 0x30b5, 0x04}, + {OV5693_8BIT, 0x30b6, 0x01}, + {OV5693_8BIT, 0x3104, 0x21}, + {OV5693_8BIT, 0x3106, 0x00}, + {OV5693_8BIT, 0x3400, 0x04}, + {OV5693_8BIT, 0x3401, 0x00}, + {OV5693_8BIT, 0x3402, 0x04}, + {OV5693_8BIT, 0x3403, 0x00}, + {OV5693_8BIT, 0x3404, 0x04}, + {OV5693_8BIT, 0x3405, 0x00}, + {OV5693_8BIT, 0x3406, 0x01}, + {OV5693_8BIT, 0x3500, 0x00}, + {OV5693_8BIT, 0x3503, 0x07}, + {OV5693_8BIT, 0x3504, 0x00}, + {OV5693_8BIT, 0x3505, 0x00}, + {OV5693_8BIT, 0x3506, 0x00}, + {OV5693_8BIT, 0x3507, 0x02}, + {OV5693_8BIT, 0x3508, 0x00}, + {OV5693_8BIT, 0x3509, 0x10}, + {OV5693_8BIT, 0x350a, 0x00}, + {OV5693_8BIT, 0x350b, 0x40}, + {OV5693_8BIT, 0x3601, 0x0a}, + {OV5693_8BIT, 0x3602, 0x38}, + {OV5693_8BIT, 0x3612, 0x80}, + {OV5693_8BIT, 0x3620, 0x54}, + {OV5693_8BIT, 0x3621, 0xc7}, + {OV5693_8BIT, 0x3622, 0x0f}, + {OV5693_8BIT, 0x3625, 0x10}, + {OV5693_8BIT, 0x3630, 0x55}, + {OV5693_8BIT, 0x3631, 0xf4}, + {OV5693_8BIT, 0x3632, 0x00}, + {OV5693_8BIT, 0x3633, 0x34}, + {OV5693_8BIT, 0x3634, 0x02}, + {OV5693_8BIT, 0x364d, 0x0d}, + {OV5693_8BIT, 0x364f, 0xdd}, + {OV5693_8BIT, 0x3660, 0x04}, + {OV5693_8BIT, 0x3662, 0x10}, + {OV5693_8BIT, 0x3663, 0xf1}, + {OV5693_8BIT, 0x3665, 0x00}, + {OV5693_8BIT, 0x3666, 0x20}, + {OV5693_8BIT, 0x3667, 0x00}, + {OV5693_8BIT, 0x366a, 0x80}, + {OV5693_8BIT, 0x3680, 0xe0}, + {OV5693_8BIT, 0x3681, 0x00}, + {OV5693_8BIT, 0x3700, 0x42}, + {OV5693_8BIT, 0x3701, 0x14}, + {OV5693_8BIT, 0x3702, 0xa0}, + {OV5693_8BIT, 0x3703, 0xd8}, + {OV5693_8BIT, 0x3704, 0x78}, + {OV5693_8BIT, 0x3705, 0x02}, + {OV5693_8BIT, 0x370a, 0x00}, + {OV5693_8BIT, 0x370b, 0x20}, + {OV5693_8BIT, 0x370c, 0x0c}, + {OV5693_8BIT, 0x370d, 0x11}, + {OV5693_8BIT, 0x370e, 0x00}, + {OV5693_8BIT, 0x370f, 0x40}, + {OV5693_8BIT, 0x3710, 0x00}, + {OV5693_8BIT, 0x371a, 0x1c}, + {OV5693_8BIT, 0x371b, 0x05}, + {OV5693_8BIT, 0x371c, 0x01}, + {OV5693_8BIT, 0x371e, 0xa1}, + {OV5693_8BIT, 0x371f, 0x0c}, + {OV5693_8BIT, 0x3721, 0x00}, + {OV5693_8BIT, 0x3724, 0x10}, + {OV5693_8BIT, 0x3726, 0x00}, + {OV5693_8BIT, 0x372a, 0x01}, + {OV5693_8BIT, 0x3730, 0x10}, + {OV5693_8BIT, 0x3738, 0x22}, + {OV5693_8BIT, 0x3739, 0xe5}, + {OV5693_8BIT, 0x373a, 0x50}, + {OV5693_8BIT, 0x373b, 0x02}, + {OV5693_8BIT, 0x373c, 0x41}, + {OV5693_8BIT, 0x373f, 0x02}, + {OV5693_8BIT, 0x3740, 0x42}, + {OV5693_8BIT, 0x3741, 0x02}, + {OV5693_8BIT, 0x3742, 0x18}, + {OV5693_8BIT, 0x3743, 0x01}, + {OV5693_8BIT, 0x3744, 0x02}, + {OV5693_8BIT, 0x3747, 0x10}, + {OV5693_8BIT, 0x374c, 0x04}, + {OV5693_8BIT, 0x3751, 0xf0}, + {OV5693_8BIT, 0x3752, 0x00}, + {OV5693_8BIT, 0x3753, 0x00}, + {OV5693_8BIT, 0x3754, 0xc0}, + {OV5693_8BIT, 0x3755, 0x00}, + {OV5693_8BIT, 0x3756, 0x1a}, + {OV5693_8BIT, 0x3758, 0x00}, + {OV5693_8BIT, 0x3759, 0x0f}, + {OV5693_8BIT, 0x376b, 0x44}, + {OV5693_8BIT, 0x375c, 0x04}, + {OV5693_8BIT, 0x3774, 0x10}, + {OV5693_8BIT, 0x3776, 0x00}, + {OV5693_8BIT, 0x377f, 0x08}, + {OV5693_8BIT, 0x3780, 0x22}, + {OV5693_8BIT, 0x3781, 0x0c}, + {OV5693_8BIT, 0x3784, 0x2c}, + {OV5693_8BIT, 0x3785, 0x1e}, + {OV5693_8BIT, 0x378f, 0xf5}, + {OV5693_8BIT, 0x3791, 0xb0}, + {OV5693_8BIT, 0x3795, 0x00}, + {OV5693_8BIT, 0x3796, 0x64}, + {OV5693_8BIT, 0x3797, 0x11}, + {OV5693_8BIT, 0x3798, 0x30}, + {OV5693_8BIT, 0x3799, 0x41}, + {OV5693_8BIT, 0x379a, 0x07}, + {OV5693_8BIT, 0x379b, 0xb0}, + {OV5693_8BIT, 0x379c, 0x0c}, + {OV5693_8BIT, 0x37c5, 0x00}, + {OV5693_8BIT, 0x37c6, 0x00}, + {OV5693_8BIT, 0x37c7, 0x00}, + {OV5693_8BIT, 0x37c9, 0x00}, + {OV5693_8BIT, 0x37ca, 0x00}, + {OV5693_8BIT, 0x37cb, 0x00}, + {OV5693_8BIT, 0x37de, 0x00}, + {OV5693_8BIT, 0x37df, 0x00}, + {OV5693_8BIT, 0x3800, 0x00}, + {OV5693_8BIT, 0x3801, 0x00}, + {OV5693_8BIT, 0x3802, 0x00}, + {OV5693_8BIT, 0x3804, 0x0a}, + {OV5693_8BIT, 0x3805, 0x3f}, + {OV5693_8BIT, 0x3810, 0x00}, + {OV5693_8BIT, 0x3812, 0x00}, + {OV5693_8BIT, 0x3823, 0x00}, + {OV5693_8BIT, 0x3824, 0x00}, + {OV5693_8BIT, 0x3825, 0x00}, + {OV5693_8BIT, 0x3826, 0x00}, + {OV5693_8BIT, 0x3827, 0x00}, + {OV5693_8BIT, 0x382a, 0x04}, + {OV5693_8BIT, 0x3a04, 0x06}, + {OV5693_8BIT, 0x3a05, 0x14}, + {OV5693_8BIT, 0x3a06, 0x00}, + {OV5693_8BIT, 0x3a07, 0xfe}, + {OV5693_8BIT, 0x3b00, 0x00}, + {OV5693_8BIT, 0x3b02, 0x00}, + {OV5693_8BIT, 0x3b03, 0x00}, + {OV5693_8BIT, 0x3b04, 0x00}, + {OV5693_8BIT, 0x3b05, 0x00}, + {OV5693_8BIT, 0x3e07, 0x20}, + {OV5693_8BIT, 0x4000, 0x08}, + {OV5693_8BIT, 0x4001, 0x04}, + {OV5693_8BIT, 0x4002, 0x45}, + {OV5693_8BIT, 0x4004, 0x08}, + {OV5693_8BIT, 0x4005, 0x18}, + {OV5693_8BIT, 0x4006, 0x20}, + {OV5693_8BIT, 0x4008, 0x24}, + {OV5693_8BIT, 0x4009, 0x10}, + {OV5693_8BIT, 0x400c, 0x00}, + {OV5693_8BIT, 0x400d, 0x00}, + {OV5693_8BIT, 0x4058, 0x00}, + {OV5693_8BIT, 0x404e, 0x37}, + {OV5693_8BIT, 0x404f, 0x8f}, + {OV5693_8BIT, 0x4058, 0x00}, + {OV5693_8BIT, 0x4101, 0xb2}, + {OV5693_8BIT, 0x4303, 0x00}, + {OV5693_8BIT, 0x4304, 0x08}, + {OV5693_8BIT, 0x4307, 0x31}, + {OV5693_8BIT, 0x4311, 0x04}, + {OV5693_8BIT, 0x4315, 0x01}, + {OV5693_8BIT, 0x4511, 0x05}, + {OV5693_8BIT, 0x4512, 0x01}, + {OV5693_8BIT, 0x4806, 0x00}, + {OV5693_8BIT, 0x4816, 0x52}, + {OV5693_8BIT, 0x481f, 0x30}, + {OV5693_8BIT, 0x4826, 0x2c}, + {OV5693_8BIT, 0x4831, 0x64}, + {OV5693_8BIT, 0x4d00, 0x04}, + {OV5693_8BIT, 0x4d01, 0x71}, + {OV5693_8BIT, 0x4d02, 0xfd}, + {OV5693_8BIT, 0x4d03, 0xf5}, + {OV5693_8BIT, 0x4d04, 0x0c}, + {OV5693_8BIT, 0x4d05, 0xcc}, + {OV5693_8BIT, 0x4837, 0x0a}, + {OV5693_8BIT, 0x5000, 0x06}, + {OV5693_8BIT, 0x5001, 0x01}, + {OV5693_8BIT, 0x5003, 0x20}, + {OV5693_8BIT, 0x5046, 0x0a}, + {OV5693_8BIT, 0x5013, 0x00}, + {OV5693_8BIT, 0x5046, 0x0a}, + {OV5693_8BIT, 0x5780, 0x1c}, + {OV5693_8BIT, 0x5786, 0x20}, + {OV5693_8BIT, 0x5787, 0x10}, + {OV5693_8BIT, 0x5788, 0x18}, + {OV5693_8BIT, 0x578a, 0x04}, + {OV5693_8BIT, 0x578b, 0x02}, + {OV5693_8BIT, 0x578c, 0x02}, + {OV5693_8BIT, 0x578e, 0x06}, + {OV5693_8BIT, 0x578f, 0x02}, + {OV5693_8BIT, 0x5790, 0x02}, + {OV5693_8BIT, 0x5791, 0xff}, + {OV5693_8BIT, 0x5842, 0x01}, + {OV5693_8BIT, 0x5843, 0x2b}, + {OV5693_8BIT, 0x5844, 0x01}, + {OV5693_8BIT, 0x5845, 0x92}, + {OV5693_8BIT, 0x5846, 0x01}, + {OV5693_8BIT, 0x5847, 0x8f}, + {OV5693_8BIT, 0x5848, 0x01}, + {OV5693_8BIT, 0x5849, 0x0c}, + {OV5693_8BIT, 0x5e00, 0x00}, + {OV5693_8BIT, 0x5e10, 0x0c}, + {OV5693_8BIT, 0x0100, 0x00}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* + * 654x496 30fps 17ms VBlanking 2lane 10Bit (Scaling) + */ +static struct ov5693_reg const ov5693_654x496[] = { + {OV5693_8BIT, 0x3501, 0x3d}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe6}, + {OV5693_8BIT, 0x3709, 0xc7}, + {OV5693_8BIT, 0x3803, 0x00}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xa3}, + {OV5693_8BIT, 0x3808, 0x02}, + {OV5693_8BIT, 0x3809, 0x90}, + {OV5693_8BIT, 0x380a, 0x01}, + {OV5693_8BIT, 0x380b, 0xf0}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x08}, + {OV5693_8BIT, 0x3813, 0x02}, + {OV5693_8BIT, 0x3814, 0x31}, + {OV5693_8BIT, 0x3815, 0x31}, + {OV5693_8BIT, 0x3820, 0x04}, + {OV5693_8BIT, 0x3821, 0x1f}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* + * 1296x976 30fps 17ms VBlanking 2lane 10Bit (Scaling) +*DS from 2592x1952 +*/ +static struct ov5693_reg const ov5693_1296x976[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + + {OV5693_8BIT, 0x3800, 0x00}, + {OV5693_8BIT, 0x3801, 0x00}, + {OV5693_8BIT, 0x3802, 0x00}, + {OV5693_8BIT, 0x3803, 0x00}, + + {OV5693_8BIT, 0x3804, 0x0a}, + {OV5693_8BIT, 0x3805, 0x3f}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xA3}, + + {OV5693_8BIT, 0x3808, 0x05}, + {OV5693_8BIT, 0x3809, 0x10}, + {OV5693_8BIT, 0x380a, 0x03}, + {OV5693_8BIT, 0x380b, 0xD0}, + + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + + {OV5693_8BIT, 0x3810, 0x00}, + {OV5693_8BIT, 0x3811, 0x10}, + {OV5693_8BIT, 0x3812, 0x00}, + {OV5693_8BIT, 0x3813, 0x02}, + + {OV5693_8BIT, 0x3814, 0x11}, /*X subsample control*/ + {OV5693_8BIT, 0x3815, 0x11}, /*Y subsample control*/ + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x5041, 0x84}, /* scale is auto enabled */ + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} + +}; + + +/* + * 336x256 30fps 17ms VBlanking 2lane 10Bit (Scaling) + DS from 2564x1956 + */ +static struct ov5693_reg const ov5693_336x256[] = { + {OV5693_8BIT, 0x3501, 0x3d}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe6}, + {OV5693_8BIT, 0x3709, 0xc7}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xa3}, + {OV5693_8BIT, 0x3808, 0x01}, + {OV5693_8BIT, 0x3809, 0x50}, + {OV5693_8BIT, 0x380a, 0x01}, + {OV5693_8BIT, 0x380b, 0x00}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x1E}, + {OV5693_8BIT, 0x3814, 0x31}, + {OV5693_8BIT, 0x3815, 0x31}, + {OV5693_8BIT, 0x3820, 0x04}, + {OV5693_8BIT, 0x3821, 0x1f}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* + * 336x256 30fps 17ms VBlanking 2lane 10Bit (Scaling) + DS from 2368x1956 + */ +static struct ov5693_reg const ov5693_368x304[] = { + {OV5693_8BIT, 0x3501, 0x3d}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe6}, + {OV5693_8BIT, 0x3709, 0xc7}, + {OV5693_8BIT, 0x3808, 0x01}, + {OV5693_8BIT, 0x3809, 0x70}, + {OV5693_8BIT, 0x380a, 0x01}, + {OV5693_8BIT, 0x380b, 0x30}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x80}, + {OV5693_8BIT, 0x3814, 0x31}, + {OV5693_8BIT, 0x3815, 0x31}, + {OV5693_8BIT, 0x3820, 0x04}, + {OV5693_8BIT, 0x3821, 0x1f}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* + * ov5693_192x160 30fps 17ms VBlanking 2lane 10Bit (Scaling) + DS from 2460x1956 + */ +static struct ov5693_reg const ov5693_192x160[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x80}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3804, 0x0a}, + {OV5693_8BIT, 0x3805, 0x3f}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xA3}, + {OV5693_8BIT, 0x3808, 0x00}, + {OV5693_8BIT, 0x3809, 0xC0}, + {OV5693_8BIT, 0x380a, 0x00}, + {OV5693_8BIT, 0x380b, 0xA0}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x40}, + {OV5693_8BIT, 0x3813, 0x00}, + {OV5693_8BIT, 0x3814, 0x31}, + {OV5693_8BIT, 0x3815, 0x31}, + {OV5693_8BIT, 0x3820, 0x04}, + {OV5693_8BIT, 0x3821, 0x1f}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + + +static struct ov5693_reg const ov5693_736x496[] = { + {OV5693_8BIT, 0x3501, 0x3d}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe6}, + {OV5693_8BIT, 0x3709, 0xc7}, + {OV5693_8BIT, 0x3803, 0x68}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0x3b}, + {OV5693_8BIT, 0x3808, 0x02}, + {OV5693_8BIT, 0x3809, 0xe0}, + {OV5693_8BIT, 0x380a, 0x01}, + {OV5693_8BIT, 0x380b, 0xf0}, + {OV5693_8BIT, 0x380c, 0x0a}, /*hts*/ + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, /*vts*/ + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x08}, + {OV5693_8BIT, 0x3813, 0x02}, + {OV5693_8BIT, 0x3814, 0x31}, + {OV5693_8BIT, 0x3815, 0x31}, + {OV5693_8BIT, 0x3820, 0x04}, + {OV5693_8BIT, 0x3821, 0x1f}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* +static struct ov5693_reg const ov5693_736x496[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe6}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3803, 0x00}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xa3}, + {OV5693_8BIT, 0x3808, 0x02}, + {OV5693_8BIT, 0x3809, 0xe0}, + {OV5693_8BIT, 0x380a, 0x01}, + {OV5693_8BIT, 0x380b, 0xf0}, + {OV5693_8BIT, 0x380c, 0x0d}, + {OV5693_8BIT, 0x380d, 0xb0}, + {OV5693_8BIT, 0x380e, 0x05}, + {OV5693_8BIT, 0x380f, 0xf2}, + {OV5693_8BIT, 0x3811, 0x08}, + {OV5693_8BIT, 0x3813, 0x02}, + {OV5693_8BIT, 0x3814, 0x31}, + {OV5693_8BIT, 0x3815, 0x31}, + {OV5693_8BIT, 0x3820, 0x01}, + {OV5693_8BIT, 0x3821, 0x1f}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; +*/ +/* + * 976x556 30fps 8.8ms VBlanking 2lane 10Bit (Scaling) + */ +static struct ov5693_reg const ov5693_976x556[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3803, 0xf0}, + {OV5693_8BIT, 0x3806, 0x06}, + {OV5693_8BIT, 0x3807, 0xa7}, + {OV5693_8BIT, 0x3808, 0x03}, + {OV5693_8BIT, 0x3809, 0xd0}, + {OV5693_8BIT, 0x380a, 0x02}, + {OV5693_8BIT, 0x380b, 0x2C}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x10}, + {OV5693_8BIT, 0x3813, 0x02}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +/*DS from 2624x1492*/ +static struct ov5693_reg const ov5693_1296x736[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + + {OV5693_8BIT, 0x3800, 0x00}, + {OV5693_8BIT, 0x3801, 0x00}, + {OV5693_8BIT, 0x3802, 0x00}, + {OV5693_8BIT, 0x3803, 0x00}, + + {OV5693_8BIT, 0x3804, 0x0a}, + {OV5693_8BIT, 0x3805, 0x3f}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xA3}, + + {OV5693_8BIT, 0x3808, 0x05}, + {OV5693_8BIT, 0x3809, 0x10}, + {OV5693_8BIT, 0x380a, 0x02}, + {OV5693_8BIT, 0x380b, 0xe0}, + + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + + {OV5693_8BIT, 0x3813, 0xE8}, + + {OV5693_8BIT, 0x3814, 0x11}, /*X subsample control*/ + {OV5693_8BIT, 0x3815, 0x11}, /*Y subsample control*/ + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x5041, 0x84}, /* scale is auto enabled */ + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +static struct ov5693_reg const ov5693_1636p_30fps[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3803, 0xf0}, + {OV5693_8BIT, 0x3806, 0x06}, + {OV5693_8BIT, 0x3807, 0xa7}, + {OV5693_8BIT, 0x3808, 0x06}, + {OV5693_8BIT, 0x3809, 0x64}, + {OV5693_8BIT, 0x380a, 0x04}, + {OV5693_8BIT, 0x380b, 0x48}, + {OV5693_8BIT, 0x380c, 0x0a}, /*hts*/ + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, /*vts*/ + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x02}, + {OV5693_8BIT, 0x3813, 0x02}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +static struct ov5693_reg const ov5693_1616x1216_30fps[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x80}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3800, 0x00}, /*{3800,3801} Array X start*/ + {OV5693_8BIT, 0x3801, 0x08}, /* 04 //{3800,3801} Array X start*/ + {OV5693_8BIT, 0x3802, 0x00}, /*{3802,3803} Array Y start*/ + {OV5693_8BIT, 0x3803, 0x04}, /* 00 //{3802,3803} Array Y start*/ + {OV5693_8BIT, 0x3804, 0x0a}, /*{3804,3805} Array X end*/ + {OV5693_8BIT, 0x3805, 0x37}, /* 3b //{3804,3805} Array X end*/ + {OV5693_8BIT, 0x3806, 0x07}, /*{3806,3807} Array Y end*/ + {OV5693_8BIT, 0x3807, 0x9f}, /* a3 //{3806,3807} Array Y end*/ + {OV5693_8BIT, 0x3808, 0x06}, /*{3808,3809} Final output H size*/ + {OV5693_8BIT, 0x3809, 0x50}, /*{3808,3809} Final output H size*/ + {OV5693_8BIT, 0x380a, 0x04}, /*{380a,380b} Final output V size*/ + {OV5693_8BIT, 0x380b, 0xc0}, /*{380a,380b} Final output V size*/ + {OV5693_8BIT, 0x380c, 0x0a}, /*{380c,380d} HTS*/ + {OV5693_8BIT, 0x380d, 0x80}, /*{380c,380d} HTS*/ + {OV5693_8BIT, 0x380e, 0x07}, /*{380e,380f} VTS*/ + {OV5693_8BIT, 0x380f, 0xc0}, /* bc //{380e,380f} VTS*/ + {OV5693_8BIT, 0x3810, 0x00}, /*{3810,3811} windowing X offset*/ + {OV5693_8BIT, 0x3811, 0x10}, /*{3810,3811} windowing X offset*/ + {OV5693_8BIT, 0x3812, 0x00}, /*{3812,3813} windowing Y offset*/ + {OV5693_8BIT, 0x3813, 0x06}, /*{3812,3813} windowing Y offset*/ + {OV5693_8BIT, 0x3814, 0x11}, /*X subsample control*/ + {OV5693_8BIT, 0x3815, 0x11}, /*Y subsample control*/ + {OV5693_8BIT, 0x3820, 0x00}, /*FLIP/Binnning control*/ + {OV5693_8BIT, 0x3821, 0x1e}, /*MIRROR control*/ + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x5041, 0x84}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + + +/* + * 1940x1096 30fps 8.8ms VBlanking 2lane 10bit (Scaling) + */ +static struct ov5693_reg const ov5693_1940x1096[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3803, 0xf0}, + {OV5693_8BIT, 0x3806, 0x06}, + {OV5693_8BIT, 0x3807, 0xa7}, + {OV5693_8BIT, 0x3808, 0x07}, + {OV5693_8BIT, 0x3809, 0x94}, + {OV5693_8BIT, 0x380a, 0x04}, + {OV5693_8BIT, 0x380b, 0x48}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x02}, + {OV5693_8BIT, 0x3813, 0x02}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x80}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +static struct ov5693_reg const ov5693_2592x1456_30fps[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3800, 0x00}, + {OV5693_8BIT, 0x3801, 0x00}, + {OV5693_8BIT, 0x3802, 0x00}, + {OV5693_8BIT, 0x3803, 0xf0}, + {OV5693_8BIT, 0x3804, 0x0a}, + {OV5693_8BIT, 0x3805, 0x3f}, + {OV5693_8BIT, 0x3806, 0x06}, + {OV5693_8BIT, 0x3807, 0xa4}, + {OV5693_8BIT, 0x3808, 0x0a}, + {OV5693_8BIT, 0x3809, 0x20}, + {OV5693_8BIT, 0x380a, 0x05}, + {OV5693_8BIT, 0x380b, 0xb0}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x10}, + {OV5693_8BIT, 0x3813, 0x00}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_TOK_TERM, 0, 0} +}; + +static struct ov5693_reg const ov5693_2576x1456_30fps[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3800, 0x00}, + {OV5693_8BIT, 0x3801, 0x00}, + {OV5693_8BIT, 0x3802, 0x00}, + {OV5693_8BIT, 0x3803, 0xf0}, + {OV5693_8BIT, 0x3804, 0x0a}, + {OV5693_8BIT, 0x3805, 0x3f}, + {OV5693_8BIT, 0x3806, 0x06}, + {OV5693_8BIT, 0x3807, 0xa4}, + {OV5693_8BIT, 0x3808, 0x0a}, + {OV5693_8BIT, 0x3809, 0x10}, + {OV5693_8BIT, 0x380a, 0x05}, + {OV5693_8BIT, 0x380b, 0xb0}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x18}, + {OV5693_8BIT, 0x3813, 0x00}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* + * 2592x1944 30fps 0.6ms VBlanking 2lane 10Bit + */ +static struct ov5693_reg const ov5693_2592x1944_30fps[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3803, 0x00}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xa3}, + {OV5693_8BIT, 0x3808, 0x0a}, + {OV5693_8BIT, 0x3809, 0x20}, + {OV5693_8BIT, 0x380a, 0x07}, + {OV5693_8BIT, 0x380b, 0x98}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x10}, + {OV5693_8BIT, 0x3813, 0x00}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* + * 11:9 Full FOV Output, expected FOV Res: 2346x1920 + * ISP Effect Res: 1408x1152 + * Sensor out: 1424x1168, DS From: 2380x1952 + * + * WA: Left Offset: 8, Hor scal: 64 + */ +static struct ov5693_reg const ov5693_1424x1168_30fps[] = { + {OV5693_8BIT, 0x3501, 0x3b}, /* long exposure[15:8] */ + {OV5693_8BIT, 0x3502, 0x80}, /* long exposure[7:0] */ + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3800, 0x00}, /* TIMING_X_ADDR_START */ + {OV5693_8BIT, 0x3801, 0x50}, /* 80 */ + {OV5693_8BIT, 0x3802, 0x00}, /* TIMING_Y_ADDR_START */ + {OV5693_8BIT, 0x3803, 0x02}, /* 2 */ + {OV5693_8BIT, 0x3804, 0x09}, /* TIMING_X_ADDR_END */ + {OV5693_8BIT, 0x3805, 0xdd}, /* 2525 */ + {OV5693_8BIT, 0x3806, 0x07}, /* TIMING_Y_ADDR_END */ + {OV5693_8BIT, 0x3807, 0xa1}, /* 1953 */ + {OV5693_8BIT, 0x3808, 0x05}, /* TIMING_X_OUTPUT_SIZE */ + {OV5693_8BIT, 0x3809, 0x90}, /* 1424 */ + {OV5693_8BIT, 0x380a, 0x04}, /* TIMING_Y_OUTPUT_SIZE */ + {OV5693_8BIT, 0x380b, 0x90}, /* 1168 */ + {OV5693_8BIT, 0x380c, 0x0a}, /* TIMING_HTS */ + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, /* TIMING_VTS */ + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3810, 0x00}, /* TIMING_ISP_X_WIN */ + {OV5693_8BIT, 0x3811, 0x02}, /* 2 */ + {OV5693_8BIT, 0x3812, 0x00}, /* TIMING_ISP_Y_WIN */ + {OV5693_8BIT, 0x3813, 0x00}, /* 0 */ + {OV5693_8BIT, 0x3814, 0x11}, /* TIME_X_INC */ + {OV5693_8BIT, 0x3815, 0x11}, /* TIME_Y_INC */ + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x5041, 0x84}, /* scale is auto enabled */ + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +/* + * 3:2 Full FOV Output, expected FOV Res: 2560x1706 + * ISP Effect Res: 720x480 + * Sensor out: 736x496, DS From 2616x1764 + */ +static struct ov5693_reg const ov5693_736x496_30fps[] = { + {OV5693_8BIT, 0x3501, 0x3b}, /* long exposure[15:8] */ + {OV5693_8BIT, 0x3502, 0x80}, /* long exposure[7:0] */ + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3800, 0x00}, /* TIMING_X_ADDR_START */ + {OV5693_8BIT, 0x3801, 0x02}, /* 2 */ + {OV5693_8BIT, 0x3802, 0x00}, /* TIMING_Y_ADDR_START */ + {OV5693_8BIT, 0x3803, 0x62}, /* 98 */ + {OV5693_8BIT, 0x3804, 0x0a}, /* TIMING_X_ADDR_END */ + {OV5693_8BIT, 0x3805, 0x3b}, /* 2619 */ + {OV5693_8BIT, 0x3806, 0x07}, /* TIMING_Y_ADDR_END */ + {OV5693_8BIT, 0x3807, 0x43}, /* 1859 */ + {OV5693_8BIT, 0x3808, 0x02}, /* TIMING_X_OUTPUT_SIZE */ + {OV5693_8BIT, 0x3809, 0xe0}, /* 736 */ + {OV5693_8BIT, 0x380a, 0x01}, /* TIMING_Y_OUTPUT_SIZE */ + {OV5693_8BIT, 0x380b, 0xf0}, /* 496 */ + {OV5693_8BIT, 0x380c, 0x0a}, /* TIMING_HTS */ + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, /* TIMING_VTS */ + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3810, 0x00}, /* TIMING_ISP_X_WIN */ + {OV5693_8BIT, 0x3811, 0x02}, /* 2 */ + {OV5693_8BIT, 0x3812, 0x00}, /* TIMING_ISP_Y_WIN */ + {OV5693_8BIT, 0x3813, 0x00}, /* 0 */ + {OV5693_8BIT, 0x3814, 0x11}, /* TIME_X_INC */ + {OV5693_8BIT, 0x3815, 0x11}, /* TIME_Y_INC */ + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x5041, 0x84}, /* scale is auto enabled */ + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +static struct ov5693_reg const ov5693_2576x1936_30fps[] = { + {OV5693_8BIT, 0x3501, 0x7b}, + {OV5693_8BIT, 0x3502, 0x00}, + {OV5693_8BIT, 0x3708, 0xe2}, + {OV5693_8BIT, 0x3709, 0xc3}, + {OV5693_8BIT, 0x3803, 0x00}, + {OV5693_8BIT, 0x3806, 0x07}, + {OV5693_8BIT, 0x3807, 0xa3}, + {OV5693_8BIT, 0x3808, 0x0a}, + {OV5693_8BIT, 0x3809, 0x10}, + {OV5693_8BIT, 0x380a, 0x07}, + {OV5693_8BIT, 0x380b, 0x90}, + {OV5693_8BIT, 0x380c, 0x0a}, + {OV5693_8BIT, 0x380d, 0x80}, + {OV5693_8BIT, 0x380e, 0x07}, + {OV5693_8BIT, 0x380f, 0xc0}, + {OV5693_8BIT, 0x3811, 0x18}, + {OV5693_8BIT, 0x3813, 0x00}, + {OV5693_8BIT, 0x3814, 0x11}, + {OV5693_8BIT, 0x3815, 0x11}, + {OV5693_8BIT, 0x3820, 0x00}, + {OV5693_8BIT, 0x3821, 0x1e}, + {OV5693_8BIT, 0x5002, 0x00}, + {OV5693_8BIT, 0x0100, 0x01}, + {OV5693_TOK_TERM, 0, 0} +}; + +struct ov5693_resolution ov5693_res_preview[] = { + { + .desc = "ov5693_736x496_30fps", + .width = 736, + .height = 496, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_736x496_30fps, + }, + { + .desc = "ov5693_1616x1216_30fps", + .width = 1616, + .height = 1216, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_1616x1216_30fps, + }, + { + .desc = "ov5693_5M_30fps", + .width = 2576, + .height = 1456, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_2576x1456_30fps, + }, + { + .desc = "ov5693_5M_30fps", + .width = 2576, + .height = 1936, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_2576x1936_30fps, + }, +}; +#define N_RES_PREVIEW (ARRAY_SIZE(ov5693_res_preview)) + +struct ov5693_resolution ov5693_res_still[] = { + { + .desc = "ov5693_736x496_30fps", + .width = 736, + .height = 496, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_736x496_30fps, + }, + { + .desc = "ov5693_1424x1168_30fps", + .width = 1424, + .height = 1168, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_1424x1168_30fps, + }, + { + .desc = "ov5693_1616x1216_30fps", + .width = 1616, + .height = 1216, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_1616x1216_30fps, + }, + { + .desc = "ov5693_5M_30fps", + .width = 2592, + .height = 1456, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_2592x1456_30fps, + }, + { + .desc = "ov5693_5M_30fps", + .width = 2592, + .height = 1944, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_2592x1944_30fps, + }, +}; +#define N_RES_STILL (ARRAY_SIZE(ov5693_res_still)) + +struct ov5693_resolution ov5693_res_video[] = { + { + .desc = "ov5693_736x496_30fps", + .width = 736, + .height = 496, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 2, + .bin_factor_y = 2, + .bin_mode = 1, + .regs = ov5693_736x496, + }, + { + .desc = "ov5693_336x256_30fps", + .width = 336, + .height = 256, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 2, + .bin_factor_y = 2, + .bin_mode = 1, + .regs = ov5693_336x256, + }, + { + .desc = "ov5693_368x304_30fps", + .width = 368, + .height = 304, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 2, + .bin_factor_y = 2, + .bin_mode = 1, + .regs = ov5693_368x304, + }, + { + .desc = "ov5693_192x160_30fps", + .width = 192, + .height = 160, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 2, + .bin_factor_y = 2, + .bin_mode = 1, + .regs = ov5693_192x160, + }, + { + .desc = "ov5693_1296x736_30fps", + .width = 1296, + .height = 736, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 2, + .bin_factor_y = 2, + .bin_mode = 0, + .regs = ov5693_1296x736, + }, + { + .desc = "ov5693_1296x976_30fps", + .width = 1296, + .height = 976, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 2, + .bin_factor_y = 2, + .bin_mode = 0, + .regs = ov5693_1296x976, + }, + { + .desc = "ov5693_1636P_30fps", + .width = 1636, + .height = 1096, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_1636p_30fps, + }, + { + .desc = "ov5693_1080P_30fps", + .width = 1940, + .height = 1096, + .fps = 30, + .pix_clk_freq = 160, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_1940x1096, + }, + { + .desc = "ov5693_5M_30fps", + .width = 2592, + .height = 1456, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_2592x1456_30fps, + }, + { + .desc = "ov5693_5M_30fps", + .width = 2592, + .height = 1944, + .pix_clk_freq = 160, + .fps = 30, + .used = 0, + .pixels_per_line = 2688, + .lines_per_frame = 1984, + .bin_factor_x = 1, + .bin_factor_y = 1, + .bin_mode = 0, + .regs = ov5693_2592x1944_30fps, + }, +}; +#define N_RES_VIDEO (ARRAY_SIZE(ov5693_res_video)) + +static struct ov5693_resolution *ov5693_res = ov5693_res_preview; +static int N_RES = N_RES_PREVIEW; +#endif diff --git a/drivers/staging/media/atomisp/i2c/ov8858.c b/drivers/staging/media/atomisp/i2c/ov8858.c new file mode 100644 index 0000000000000000000000000000000000000000..eccb4a3b1c62524f3ce4c5461da7d9edb52c42bf --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov8858.c @@ -0,0 +1,2224 @@ +/* + * Support for OmniVision ov8858 camera sensor. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include +#include +#include +#include +#ifdef CONFIG_PLATFORM_BTNS +#include "ov8858_btns.h" +#else +#include "ov8858.h" +#endif +static int ov8858_i2c_read(struct i2c_client *client, u16 len, u16 addr, + u8 *buf) +{ + struct i2c_msg msg[2]; + u8 address[2]; + int err; + + if (!client->adapter) { + dev_err(&client->dev, "%s error, no adapter\n", __func__); + return -ENODEV; + } + + dev_dbg(&client->dev, "%s: len = %d, addr = 0x%04x\n", + __func__, len, addr); + + memset(msg, 0, sizeof(msg)); + + address[0] = (addr >> 8) & 0xff; + address[1] = addr & 0xff; + + msg[0].addr = client->addr; + msg[0].flags = 0; + msg[0].len = I2C_MSG_LENGTH; + msg[0].buf = address; + + msg[1].addr = client->addr; + msg[1].len = len; + msg[1].flags = I2C_M_RD; + msg[1].buf = buf; + + err = i2c_transfer(client->adapter, msg, ARRAY_SIZE(msg)); + if (err != 2) { + if (err >= 0) + err = -EIO; + goto error; + } + + return 0; +error: + dev_err(&client->dev, "reading from address 0x%x error %d", addr, err); + return err; +} + +static int ov8858_read_reg(struct i2c_client *client, u16 type, u16 reg, + u16 *val) +{ + u8 data[OV8858_SHORT_MAX]; + int err; + + dev_dbg(&client->dev, "%s: type = %d, reg = 0x%04x\n", + __func__, type, reg); + + /* read only 8 and 16 bit values */ + if (type != OV8858_8BIT && type != OV8858_16BIT) { + dev_err(&client->dev, "%s error, invalid data length\n", + __func__); + return -EINVAL; + } + + memset(data, 0, sizeof(data)); + + err = ov8858_i2c_read(client, type, reg, data); + if (err) + goto error; + + /* high byte comes first */ + if (type == OV8858_8BIT) + *val = (u8)data[0]; + else + *val = data[0] << 8 | data[1]; + + dev_dbg(&client->dev, "%s: val = 0x%04x\n", __func__, *val); + + return 0; + +error: + dev_err(&client->dev, "read from offset 0x%x error %d", reg, err); + return err; +} + +static int ov8858_i2c_write(struct i2c_client *client, u16 len, u8 *data) +{ + struct i2c_msg msg; + const int num_msg = 1; + int ret; + + msg.addr = client->addr; + msg.flags = 0; + msg.len = len; + msg.buf = data; + + ret = i2c_transfer(client->adapter, &msg, 1); + + return ret == num_msg ? 0 : -EIO; +} + +static int +ov8858_write_reg(struct i2c_client *client, u16 data_length, u16 reg, u16 val) +{ + int ret; + unsigned char data[4] = {0}; + u16 *wreg; + const u16 len = data_length + sizeof(u16); /* 16-bit address + data */ + + dev_dbg(&client->dev, + "%s: data_length = %d, reg = 0x%04x, val = 0x%04x\n", + __func__, data_length, reg, val); + + if (!client->adapter) { + dev_err(&client->dev, "%s error, no adapter\n", __func__); + return -ENODEV; + } + + if (data_length != OV8858_8BIT && data_length != OV8858_16BIT) { + dev_err(&client->dev, "%s error, invalid length\n", __func__); + return -EINVAL; + } + + /* high byte goes out first */ + wreg = (u16 *)data; + *wreg = cpu_to_be16(reg); + + if (data_length == OV8858_8BIT) { + data[2] = (u8)(val); + } else { + /* OV8858_16BIT */ + u16 *wdata = (u16 *)&data[2]; + *wdata = be16_to_cpu(val); + } + + ret = ov8858_i2c_write(client, len, data); + if (ret) + dev_err(&client->dev, + "write error: wrote 0x%x to offset 0x%x error %d", + val, reg, ret); + + return ret; +} + +/* + * ov8858_write_reg_array - Initializes a list of registers + * @client: i2c driver client structure + * @reglist: list of registers to be written + * + * This function initializes a list of registers. When consecutive addresses + * are found in a row on the list, this function creates a buffer and sends + * consecutive data in a single i2c_transfer(). + * + * __ov8858_flush_reg_array(), __ov8858_buf_reg_array() and + * __ov8858_write_reg_is_consecutive() are internal functions to + * ov8858_write_reg_array() and should be not used anywhere else. + * + */ +static int __ov8858_flush_reg_array(struct i2c_client *client, + struct ov8858_write_ctrl *ctrl) +{ + u16 size; + if (ctrl->index == 0) + return 0; + + size = sizeof(u16) + ctrl->index; /* 16-bit address + data */ + ctrl->buffer.addr = cpu_to_be16(ctrl->buffer.addr); + ctrl->index = 0; + + return ov8858_i2c_write(client, size, (u8 *)&ctrl->buffer); +} + +static int __ov8858_buf_reg_array(struct i2c_client *client, + struct ov8858_write_ctrl *ctrl, + const struct ov8858_reg *next) +{ + int size; + u16 *data16; + + switch (next->type) { + case OV8858_8BIT: + size = 1; + ctrl->buffer.data[ctrl->index] = (u8)next->val; + break; + case OV8858_16BIT: + size = 2; + data16 = (u16 *)&ctrl->buffer.data[ctrl->index]; + *data16 = cpu_to_be16((u16)next->val); + break; + default: + return -EINVAL; + } + + /* When first item is added, we need to store its starting address */ + if (ctrl->index == 0) + ctrl->buffer.addr = next->sreg; + + ctrl->index += size; + + /* + * Buffer cannot guarantee free space for u32? Better flush it to avoid + * possible lack of memory for next item. + */ + if (ctrl->index + sizeof(u16) >= OV8858_MAX_WRITE_BUF_SIZE) + __ov8858_flush_reg_array(client, ctrl); + + return 0; +} + +static int +__ov8858_write_reg_is_consecutive(struct i2c_client *client, + struct ov8858_write_ctrl *ctrl, + const struct ov8858_reg *next) +{ + if (ctrl->index == 0) + return 1; + + return ctrl->buffer.addr + ctrl->index == next->sreg; +} + +static int ov8858_write_reg_array(struct i2c_client *client, + const struct ov8858_reg *reglist) +{ + const struct ov8858_reg *next = reglist; + struct ov8858_write_ctrl ctrl; + int err; + + ctrl.index = 0; + for (; next->type != OV8858_TOK_TERM; next++) { + switch (next->type & OV8858_TOK_MASK) { + case OV8858_TOK_DELAY: + err = __ov8858_flush_reg_array(client, &ctrl); + if (err) + return err; + msleep(next->val); + break; + + default: + /* + * If next address is not consecutive, data needs to be + * flushed before proceeding + */ + if (!__ov8858_write_reg_is_consecutive(client, + &ctrl, next)) { + err = __ov8858_flush_reg_array(client, &ctrl); + if (err) + return err; + } + err = __ov8858_buf_reg_array(client, &ctrl, next); + if (err) { + dev_err(&client->dev, "%s: write error\n", + __func__); + return err; + } + break; + } + } + + return __ov8858_flush_reg_array(client, &ctrl); +} + +static int __ov8858_min_fps_diff(int fps, + const struct ov8858_fps_setting *fps_list) +{ + int diff = INT_MAX; + int i; + + if (fps == 0) + return 0; + + for (i = 0; i < MAX_FPS_OPTIONS_SUPPORTED; i++) { + if (!fps_list[i].fps) + break; + if (abs(fps_list[i].fps - fps) < diff) + diff = abs(fps_list[i].fps - fps); + } + + return diff; +} + +static int __ov8858_nearest_fps_index(int fps, + const struct ov8858_fps_setting *fps_list) +{ + int fps_index = 0; + int i; + + for (i = 0; i < MAX_FPS_OPTIONS_SUPPORTED; i++) { + if (!fps_list[i].fps) + break; + if (abs(fps_list[i].fps - fps) + < abs(fps_list[fps_index].fps - fps)) + fps_index = i; + } + return fps_index; +} + +static int __ov8858_update_frame_timing(struct v4l2_subdev *sd, + u16 *hts, u16 *vts) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + + + dev_dbg(&client->dev, "%s OV8858_TIMING_HTS=0x%04x\n", + __func__, *hts); + + /* HTS = pixel_per_line / 2 */ + ret = ov8858_write_reg(client, OV8858_16BIT, + OV8858_TIMING_HTS, *hts >> 1); + if (ret) + return ret; + dev_dbg(&client->dev, "%s OV8858_TIMING_VTS=0x%04x\n", + __func__, *vts); + + return ov8858_write_reg(client, OV8858_16BIT, OV8858_TIMING_VTS, *vts); +} + +static int __ov8858_set_exposure(struct v4l2_subdev *sd, int exposure, int gain, + int dig_gain, u16 *hts, u16 *vts) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int exp_val, ret; + dev_dbg(&client->dev, "%s, exposure = %d, gain=%d, dig_gain=%d\n", + __func__, exposure, gain, dig_gain); + + if (dev->limit_exposure_flag) { + if (exposure > *vts - OV8858_INTEGRATION_TIME_MARGIN) + exposure = *vts - OV8858_INTEGRATION_TIME_MARGIN; + } else { + if (*vts < exposure + OV8858_INTEGRATION_TIME_MARGIN) + *vts = (u16) exposure + OV8858_INTEGRATION_TIME_MARGIN; + } + + ret = __ov8858_update_frame_timing(sd, hts, vts); + if (ret) + return ret; + + /* For ov8858, the low 4 bits are fraction bits and must be kept 0 */ + exp_val = exposure << 4; + ret = ov8858_write_reg(client, OV8858_8BIT, + OV8858_LONG_EXPO+2, exp_val & 0xFF); + if (ret) + return ret; + + ret = ov8858_write_reg(client, OV8858_8BIT, + OV8858_LONG_EXPO+1, (exp_val >> 8) & 0xFF); + if (ret) + return ret; + + ret = ov8858_write_reg(client, OV8858_8BIT, + OV8858_LONG_EXPO, (exp_val >> 16) & 0x0F); + if (ret) + return ret; + + /* Digital gain : to all MWB channel gains */ + if (dig_gain) { + ret = ov8858_write_reg(client, OV8858_16BIT, + OV8858_MWB_RED_GAIN_H, dig_gain); + if (ret) + return ret; + + ret = ov8858_write_reg(client, OV8858_16BIT, + OV8858_MWB_GREEN_GAIN_H, dig_gain); + if (ret) + return ret; + + ret = ov8858_write_reg(client, OV8858_16BIT, + OV8858_MWB_BLUE_GAIN_H, dig_gain); + if (ret) + return ret; + } + + ret = ov8858_write_reg(client, OV8858_16BIT, OV8858_LONG_GAIN, + gain & 0x07ff); + if (ret) + return ret; + + dev->gain = gain; + dev->exposure = exposure; + dev->digital_gain = dig_gain; + + return 0; +} + +static int ov8858_set_exposure(struct v4l2_subdev *sd, int exposure, int gain, + int dig_gain) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + const struct ov8858_resolution *res; + u16 hts, vts; + int ret; + + mutex_lock(&dev->input_lock); + + /* Validate exposure: cannot exceed 16bit value */ + exposure = clamp_t(int, exposure, 0, OV8858_MAX_EXPOSURE_VALUE); + + /* Validate gain: must not exceed maximum 8bit value */ + gain = clamp_t(int, gain, 0, OV8858_MAX_GAIN_VALUE); + + /* Validate digital gain: must not exceed 12 bit value*/ + dig_gain = clamp_t(int, dig_gain, 0, OV8858_MWB_GAIN_MAX); + + res = &dev->curr_res_table[dev->fmt_idx]; + /* + * Vendor: HTS reg value is half the total pixel line + */ + hts = res->fps_options[dev->fps_index].pixels_per_line; + vts = res->fps_options[dev->fps_index].lines_per_frame; + + ret = __ov8858_set_exposure(sd, exposure, gain, dig_gain, &hts, &vts); + + mutex_unlock(&dev->input_lock); + + return ret; +} + +/* + When exposure gain value set to sensor, the sensor changed value. + So we need the function to get real value + */ +static int ov8858_g_update_exposure(struct v4l2_subdev *sd, + struct atomisp_update_exposure *exposure) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int gain = exposure->gain; + + dev_dbg(&client->dev, "%s: gain: %d, digi_gain: %d\n", __func__, + exposure->gain, exposure->digi_gain); + exposure->update_digi_gain = dev->digital_gain; + /* This real gain value fetching function is provided by vendor */ + exposure->update_gain = (((gain & 0x700) >> 8) + 1) * (gain & 0xFF); + + return 0; +} + +static int ov8858_s_exposure(struct v4l2_subdev *sd, + struct atomisp_exposure *exposure) +{ + return ov8858_set_exposure(sd, exposure->integration_time[0], + exposure->gain[0], exposure->gain[1]); +} + +static int ov8858_priv_int_data_init(struct v4l2_subdev *sd) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + u32 size = OV8858_OTP_END_ADDR - OV8858_OTP_START_ADDR + 1; + int r; + u16 isp_ctrl2 = 0; + + if (!dev->otp_data) { + dev->otp_data = devm_kzalloc(&client->dev, size, GFP_KERNEL); + if (!dev->otp_data) { + dev_err(&client->dev, "%s: can't allocate memory", + __func__); + r = -ENOMEM; + goto error3; + } + + /* Streaming has to be on */ + r = ov8858_write_reg(client, OV8858_8BIT, OV8858_STREAM_MODE, + 0x01); + if (r) + goto error2; + + /* Turn off Dead Pixel Correction */ + r = ov8858_read_reg(client, OV8858_8BIT, + OV8858_OTP_ISP_CTRL2, &isp_ctrl2); + if (r) + goto error1; + + r = ov8858_write_reg(client, OV8858_8BIT, OV8858_OTP_ISP_CTRL2, + isp_ctrl2 & ~OV8858_OTP_DPC_ENABLE); + if (r) + goto error1; + + /* Enable partial OTP read mode */ + r = ov8858_write_reg(client, OV8858_8BIT, OV8858_OTP_MODE_CTRL, + OV8858_OTP_MODE_PROGRAM_DISABLE | + OV8858_OTP_MODE_MANUAL); + if (r) + goto error1; + + /* Set address range of OTP memory to read */ + r = ov8858_write_reg(client, OV8858_16BIT, + OV8858_OTP_START_ADDR_REG, + OV8858_OTP_START_ADDR); + if (r) + goto error1; + + r = ov8858_write_reg(client, OV8858_16BIT, + OV8858_OTP_END_ADDR_REG, + OV8858_OTP_END_ADDR); + if (r) + goto error1; + + /* Load the OTP data into the OTP buffer */ + r = ov8858_write_reg(client, OV8858_8BIT, OV8858_OTP_LOAD_CTRL, + OV8858_OTP_LOAD_ENABLE); + if (r) + goto error1; + + /* Wait for the data to load into the buffer */ + usleep_range(5000, 5500); + + /* Read the OTP data from the buffer */ + r = ov8858_i2c_read(client, size, OV8858_OTP_START_ADDR, + dev->otp_data); + if (r) + goto error1; + + /* Turn on Dead Pixel Correction */ + r = ov8858_write_reg(client, OV8858_8BIT, OV8858_OTP_ISP_CTRL2, + isp_ctrl2 | OV8858_OTP_DPC_ENABLE); + if (r) + goto error1; + + /* Stop streaming */ + r = ov8858_write_reg(client, 1, OV8858_STREAM_MODE, 0x00); + if (r) { + dev_err(&client->dev, "%s: cannot turn off streaming\n", + __func__); + goto error1; + } + } + + + return 0; + +error1: + /* Turn on Dead Pixel Correction and set streaming off */ + ov8858_write_reg(client, OV8858_8BIT, OV8858_OTP_ISP_CTRL2, + isp_ctrl2 | OV8858_OTP_DPC_ENABLE); + ov8858_write_reg(client, 1, OV8858_STREAM_MODE, 0x00); +error2: + devm_kfree(&client->dev, dev->otp_data); + dev->otp_data = NULL; +error3: + dev_err(&client->dev, "%s: OTP reading failed\n", __func__); + return r; +} + +static int ov8858_g_priv_int_data(struct v4l2_subdev *sd, + struct v4l2_private_int_data *priv) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + u32 size = OV8858_OTP_END_ADDR - OV8858_OTP_START_ADDR + 1; + int r; + + mutex_lock(&dev->input_lock); + + if (!dev->otp_data) { + dev_err(&client->dev, "%s: otp data is NULL\n", __func__); + mutex_unlock(&dev->input_lock); + return -EFAULT; + } + + if (copy_to_user(priv->data, dev->otp_data, + min_t(__u32, priv->size, size))) { + r = -EFAULT; + dev_err(&client->dev, "%s: OTP reading failed\n", __func__); + mutex_unlock(&dev->input_lock); + return r; + } + + priv->size = size; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static int __ov8858_init(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov8858_device *dev = to_ov8858_sensor(sd); + int ret; + dev_dbg(&client->dev, "%s\n", __func__); + + /* Sets the default FPS */ + dev->fps_index = 0; + + /* Set default exposure values (initially start values) */ + dev->exposure = 256; + dev->gain = 16; + dev->digital_gain = 1024; + dev->limit_exposure_flag = false; + + dev_dbg(&client->dev, "%s: Writing basic settings to ov8858\n", + __func__); + ret = ov8858_write_reg_array(client, ov8858_BasicSettings); + if (ret) + return ret; + + return ov8858_priv_int_data_init(sd); +} + +static int ov8858_init(struct v4l2_subdev *sd, u32 val) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __ov8858_init(sd); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static void ov8858_uninit(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct v4l2_ctrl *ctrl; + dev_dbg(&client->dev, "%s:\n", __func__); + + dev->exposure = 0; + dev->gain = 0; + dev->digital_gain = 0; + dev->limit_exposure_flag = false; + mutex_unlock(&dev->input_lock); + ctrl = v4l2_ctrl_find(sd->ctrl_handler, + V4L2_CID_EXPOSURE_AUTO_PRIORITY); + if (ctrl) + v4l2_ctrl_s_ctrl(ctrl, V4L2_EXPOSURE_AUTO); + mutex_lock(&dev->input_lock); +} + +static int ov8858_g_comp_delay(struct v4l2_subdev *sd, unsigned int *usec) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov8858_device *dev = to_ov8858_sensor(sd); + int ret = 0, exposure; + u16 vts, data; + + if (dev->exposure == 0) { + ret = ov8858_read_reg(client, OV8858_16BIT, + OV8858_LONG_EXPO + 1, &data); + if (ret) + return ret; + exposure = data; + exposure >>= 4; + } else { + exposure = dev->exposure; + } + + ret = ov8858_read_reg(client, OV8858_16BIT, OV8858_TIMING_VTS, &vts); + if (ret || vts == 0) + vts = OV8858_DEPTH_VTS_CONST; + + *usec = (exposure * 33333 / vts); + if (*usec > OV8858_DEPTH_COMP_CONST) + *usec = *usec - OV8858_DEPTH_COMP_CONST; + else + *usec = OV8858_DEPTH_COMP_CONST; + + return 0; +} + +static long ov8858_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + switch (cmd) { + case ATOMISP_IOC_S_EXPOSURE: + return ov8858_s_exposure(sd, (struct atomisp_exposure *)arg); + case ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA: + return ov8858_g_priv_int_data(sd, arg); + case ATOMISP_IOC_G_DEPTH_SYNC_COMP: + return ov8858_g_comp_delay(sd, (unsigned int *)arg); + case ATOMISP_IOC_G_UPDATE_EXPOSURE: + return ov8858_g_update_exposure(sd, + (struct atomisp_update_exposure *)arg); + default: + dev_dbg(&client->dev, "Unhandled command 0x%X\n", cmd); + return -EINVAL; + } +} + +static int __power_ctrl(struct v4l2_subdev *sd, bool flag) +{ + int ret = 0; + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + + if (!dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->power_ctrl) + return dev->platform_data->power_ctrl(sd, flag); + + if (dev->platform_data->v1p2_ctrl) { + ret = dev->platform_data->v1p2_ctrl(sd, flag); + if (ret) { + dev_err(&client->dev, + "failed to power %s 1.2v power rail\n", + flag ? "up" : "down"); + return ret; + } + } + + if (dev->platform_data->v2p8_ctrl) { + ret = dev->platform_data->v2p8_ctrl(sd, flag); + if (ret) { + dev_err(&client->dev, + "failed to power %s 2.8v power rail\n", + flag ? "up" : "down"); + return ret; + } + } + + if (dev->platform_data->v1p8_ctrl) { + ret = dev->platform_data->v1p8_ctrl(sd, flag); + if (ret) { + dev_err(&client->dev, + "failed to power %s 1.8v power rail\n", + flag ? "up" : "down"); + if (dev->platform_data->v2p8_ctrl) + dev->platform_data->v2p8_ctrl(sd, 0); + return ret; + } + } + + if (flag) + msleep(20); /* Wait for power lines to stabilize */ + return ret; +} + +static int __gpio_ctrl(struct v4l2_subdev *sd, bool flag) +{ + struct i2c_client *client; + struct ov8858_device *dev; + + if (!sd) + return -EINVAL; + + client = v4l2_get_subdevdata(sd); + dev = to_ov8858_sensor(sd); + + if (!client || !dev || !dev->platform_data) + return -ENODEV; + + /* Non-gmin platforms use the legacy callback */ + if (dev->platform_data->gpio_ctrl) + return dev->platform_data->gpio_ctrl(sd, flag); + + if (dev->platform_data->gpio0_ctrl) + return dev->platform_data->gpio0_ctrl(sd, flag); + + dev_err(&client->dev, "failed to find platform gpio callback\n"); + + return -EINVAL; +} + +static int power_up(struct v4l2_subdev *sd) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov8858_device *dev = to_ov8858_sensor(sd); + int ret; + dev_dbg(&client->dev, "%s\n", __func__); + + /* Enable power */ + ret = __power_ctrl(sd, 1); + if (ret) { + dev_err(&client->dev, "power rail on failed %d.\n", ret); + goto fail_power; + } + + /* Enable clock */ + ret = dev->platform_data->flisclk_ctrl(sd, 1); + if (ret) { + dev_err(&client->dev, "flisclk on failed %d\n", ret); + goto fail_clk; + } + + /* Release reset */ + ret = __gpio_ctrl(sd, 1); + if (ret) { + dev_err(&client->dev, "gpio on failed %d\n", ret); + goto fail_gpio; + } + + /* Minumum delay is 8192 clock cycles before first i2c transaction, + * which is 1.37 ms at the lowest allowed clock rate 6 MHz */ + usleep_range(2000, 2500); + return 0; + +fail_gpio: + dev->platform_data->flisclk_ctrl(sd, 0); +fail_clk: + __power_ctrl(sd, 0); +fail_power: + dev_err(&client->dev, "Sensor power-up failed\n"); + + return ret; +} + +static int power_down(struct v4l2_subdev *sd) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + dev_dbg(&client->dev, "%s\n", __func__); + + ret = dev->platform_data->flisclk_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "flisclk off failed\n"); + + ret = __gpio_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "gpio off failed\n"); + + ret = __power_ctrl(sd, 0); + if (ret) + dev_err(&client->dev, "power rail off failed.\n"); + + return ret; +} + +static int __ov8858_s_power(struct v4l2_subdev *sd, int on) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + int ret, r = 0; + + if (on == 0) { + ov8858_uninit(sd); + if (dev->vcm_driver && dev->vcm_driver->power_down) + r = dev->vcm_driver->power_down(sd); + ret = power_down(sd); + if (r != 0 && ret == 0) + ret = r; + } else { + ret = power_up(sd); + if (ret) + power_down(sd); + if (dev->vcm_driver && dev->vcm_driver->power_up) { + ret = dev->vcm_driver->power_up(sd); + if (ret) { + power_down(sd); + return ret; + } + } + return __ov8858_init(sd); + } + + return ret; +} + +static int ov8858_s_power(struct v4l2_subdev *sd, int on) +{ + int ret; + struct ov8858_device *dev = to_ov8858_sensor(sd); + + mutex_lock(&dev->input_lock); + ret = __ov8858_s_power(sd, on); + mutex_unlock(&dev->input_lock); + + /* + * FIXME: Compatibility with old behaviour: return to preview + * when the device is power cycled. + */ + if (!ret && on) + v4l2_ctrl_s_ctrl(dev->run_mode, ATOMISP_RUN_MODE_PREVIEW); + + return ret; +} + +/* + * Return value of the specified register, first try getting it from + * the register list and if not found, get from the sensor via i2c. + */ +static int ov8858_get_register(struct v4l2_subdev *sd, int reg, int type, + const struct ov8858_reg *reglist) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + const struct ov8858_reg *next; + u16 val; + + /* Try if the values are in the register list */ + for (next = reglist; next->type != OV8858_TOK_TERM; next++) { + if (next->sreg == reg) { + if (type == OV8858_8BIT) + return next->val; + + if (type == OV8858_16BIT && + next[1].type != OV8858_TOK_TERM) + return next[0].val << 8 | next[1].val; + } + } + + /* If not, read from sensor */ + if (ov8858_read_reg(client, type, reg, &val)) { + dev_err(&client->dev, "failed to read register 0x%08x\n", reg); + return -EIO; + } + + return val; +} + +static inline int ov8858_get_register_16bit(struct v4l2_subdev *sd, int reg, + const struct ov8858_reg *reglist) +{ + return ov8858_get_register(sd, reg, OV8858_16BIT, reglist); +} + +static inline int ov8858_get_register_8bit(struct v4l2_subdev *sd, int reg, + const struct ov8858_reg *reglist) +{ + return ov8858_get_register(sd, reg, OV8858_8BIT, reglist); +} + +static int __ov8858_get_pll1_values(struct v4l2_subdev *sd, + int *value, + const struct ov8858_reg *reglist) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + unsigned int prediv_idx; + unsigned int multiplier; + unsigned int sys_prediv; + unsigned int prediv_coef[] = {2, 3, 4, 5, 6, 8, 12, 16}; + int ret; + + ret = ov8858_get_register_8bit(sd, OV8858_PLL1_PREDIV0, reglist); + if (ret < 0) + return ret; + + if (ret & OV8858_PLL1_PREDIV0_MASK) + *value /= 2; + + ret = ov8858_get_register_8bit(sd, OV8858_PLL1_PREDIV, reglist); + + if (ret < 0) + return ret; + + prediv_idx = ret & OV8858_PLL1_PREDIV_MASK; + *value = *value * 2 / prediv_coef[prediv_idx]; + + ret = ov8858_get_register_16bit(sd, OV8858_PLL1_MULTIPLIER, reglist); + if (ret < 0) + return ret; + + multiplier = ret; + *value *= multiplier & OV8858_PLL1_MULTIPLIER_MASK; + ret = ov8858_get_register_8bit(sd, OV8858_PLL1_SYS_PRE_DIV, reglist); + + if (ret < 0) + return ret; + + sys_prediv = ret & OV8858_PLL1_SYS_PRE_DIV_MASK; + *value /= (sys_prediv + 3); + ret = ov8858_get_register_8bit(sd, OV8858_PLL1_SYS_DIVIDER, reglist); + + if (ret < 0) + return ret; + + if (ret & OV8858_PLL1_SYS_DIVIDER_MASK) + *value /= 2; + + dev_dbg(&client->dev, "%s: *value: %d\n", __func__, *value); + + return 0; +} + +static int __ov8858_get_pll2a_values(struct v4l2_subdev *sd, int *value, + const struct ov8858_reg *reglist) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + unsigned int prediv_idx; + unsigned int multiplier; + unsigned int prediv_coef[] = {2, 3, 4, 5, 6, 8, 12, 16}; + int ret; + + ret = ov8858_get_register_8bit(sd, OV8858_PLL2_PREDIV0, reglist); + if (ret < 0) + return ret; + + if (ret & OV8858_PLL2_PREDIV0_MASK) + *value /= 2; + + ret = ov8858_get_register_8bit(sd, OV8858_PLL2_PREDIV, reglist); + if (ret < 0) + return ret; + + prediv_idx = (ret & OV8858_PLL2_PREDIV_MASK); + *value = *value * 2 / prediv_coef[prediv_idx]; + + ret = ov8858_get_register_16bit(sd, OV8858_PLL2_MULTIPLIER, reglist); + if (ret < 0) + return ret; + + multiplier = ret; + *value *= multiplier & OV8858_PLL2_MULTIPLIER_MASK; + dev_dbg(&client->dev, "%s: *value: %d\n", __func__, *value); + + return 0; +} +static int __ov8858_get_pll2b_values(struct v4l2_subdev *sd, int *value, + const struct ov8858_reg *reglist) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + unsigned int dac_divider; + int ret; + + ret = ov8858_get_register_8bit(sd, OV8858_PLL2_DAC_DIVIDER, reglist); + if (ret < 0) + return ret; + + dac_divider = (ret & OV8858_PLL2_DAC_DIVIDER_MASK) + 1; + *value /= dac_divider; + + dev_dbg(&client->dev, "%s: *value: %d\n", __func__, *value); + + return 0; +} +static int __ov8858_get_pll2c_values(struct v4l2_subdev *sd, int *value, + const struct ov8858_reg *reglist) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + unsigned int sys_pre_div; + unsigned int sys_divider_idx; + unsigned int sys_divider_coef[] = {2, 3, 4, 5, 6, 7, 8, 10}; + int ret; + + ret = ov8858_get_register_8bit(sd, OV8858_PLL2_SYS_PRE_DIV, reglist); + if (ret < 0) + return ret; + + sys_pre_div = (ret & OV8858_PLL2_SYS_PRE_DIV_MASK) + 1; + *value /= sys_pre_div; + + ret = ov8858_get_register_8bit(sd, OV8858_PLL2_SYS_DIVIDER, reglist); + if (ret < 0) + return ret; + + sys_divider_idx = ret & OV8858_PLL2_SYS_DIVIDER_MASK; + *value *= 2 / sys_divider_coef[sys_divider_idx]; + + dev_dbg(&client->dev, "%s: *value: %d\n", __func__, *value); + + return 0; +} + +static int ov8858_get_intg_factor(struct v4l2_subdev *sd, + struct camera_mipi_info *info, + const struct ov8858_reg *reglist) +{ + const unsigned int ext_clk = 19200000; /* Hz */ + struct atomisp_sensor_mode_data *m = &info->data; + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct device *d = &client->dev; + const struct ov8858_resolution *res = + &dev->curr_res_table[dev->fmt_idx]; + unsigned int pll_sclksel1; + unsigned int pll_sclksel2; + unsigned int sys_pre_div; + unsigned int sclk_pdiv; + unsigned int sclk = ext_clk; + u16 hts; + int ret; + + memset(&info->data, 0, sizeof(info->data)); + + ret = ov8858_get_register_8bit(sd, OV8858_PLL_SCLKSEL1, reglist); + if (ret < 0) + return ret; + + dev_dbg(d, "%s: OV8858_PLL_SCLKSEL1: 0x%02x\n", __func__, ret); + pll_sclksel1 = ret & OV8858_PLL_SCLKSEL1_MASK; + + ret = ov8858_get_register_8bit(sd, OV8858_PLL_SCLKSEL2, reglist); + if (ret < 0) + return ret; + + dev_dbg(d, "%s: OV8858_PLL_SCLKSEL2: 0x%02x\n", __func__, ret); + pll_sclksel2 = ret & OV8858_PLL_SCLKSEL2_MASK; + + if (pll_sclksel2) { + ret = __ov8858_get_pll2a_values(sd, &sclk, reglist); + if (ret < 0) + return ret; + ret = __ov8858_get_pll2b_values(sd, &sclk, reglist); + if (ret < 0) + return ret; + } else if (pll_sclksel1) { + ret = __ov8858_get_pll2a_values(sd, &sclk, reglist); + if (ret < 0) + return ret; + ret = __ov8858_get_pll2c_values(sd, &sclk, reglist); + if (ret < 0) + return ret; + } else { + ret = __ov8858_get_pll1_values(sd, &sclk, reglist); + if (ret < 0) + return ret; + } + + ret = ov8858_get_register_8bit(sd, OV8858_SRB_HOST_INPUT_DIS, reglist); + if (ret < 0) + return ret; + + dev_dbg(d, "%s: OV8858_SRB_HOST_INPUT_DIS: 0x%02x\n", __func__, ret); + + sys_pre_div = ret & OV8858_SYS_PRE_DIV_MASK; + sys_pre_div >>= OV8858_SYS_PRE_DIV_OFFSET; + + if (sys_pre_div == 1) + sclk /= 2; + else if (sys_pre_div == 2) + sclk /= 4; + + sclk_pdiv = ret & OV8858_SCLK_PDIV_MASK; + sclk_pdiv >>= OV8858_SCLK_PDIV_OFFSET; + + if (sclk_pdiv > 1) + sclk /= sclk_pdiv; + + dev_dbg(d, "%s: sclk: %d\n", __func__, sclk); + + dev->vt_pix_clk_freq_mhz = sclk; + m->vt_pix_clk_freq_mhz = sclk; + + /* HTS and VTS */ + m->frame_length_lines = + res->fps_options[dev->fps_index].lines_per_frame; + m->line_length_pck = res->fps_options[dev->fps_index].pixels_per_line; + + m->coarse_integration_time_min = 0; + m->coarse_integration_time_max_margin = OV8858_INTEGRATION_TIME_MARGIN; + ret = ov8858_read_reg(client, OV8858_16BIT, OV8858_TIMING_HTS, &hts); + if (ret < 0) + return ret; + m->hts = hts; + dev_dbg(&client->dev, "%s: get HTS %d\n", __func__, hts); + + /* OV Sensor do not use fine integration time. */ + m->fine_integration_time_min = 0; + m->fine_integration_time_max_margin = 0; + + /* + * read_mode indicate whether binning is used for calculating + * the correct exposure value from the user side. So adapt the + * read mode values accordingly. + */ + m->read_mode = res->bin_factor_x ? + OV8858_READ_MODE_BINNING_ON : OV8858_READ_MODE_BINNING_OFF; + + ret = ov8858_get_register_8bit(sd, OV8858_H_INC_ODD, res->regs); + if (ret < 0) + return ret; + m->binning_factor_x = (ret + 1) / 2; + + ret = ov8858_get_register_8bit(sd, OV8858_V_INC_ODD, res->regs); + if (ret < 0) + return ret; + m->binning_factor_y = (ret + 1) / 2; + + /* Get the cropping and output resolution to ISP for this mode. */ + ret = ov8858_get_register_16bit(sd, OV8858_HORIZONTAL_START_H, + res->regs); + if (ret < 0) + return ret; + + m->crop_horizontal_start = ret; + + ret = ov8858_get_register_16bit(sd, OV8858_VERTICAL_START_H, res->regs); + if (ret < 0) + return ret; + + m->crop_vertical_start = ret; + + ret = ov8858_get_register_16bit(sd, OV8858_HORIZONTAL_END_H, res->regs); + if (ret < 0) + return ret; + + m->crop_horizontal_end = ret; + + ret = ov8858_get_register_16bit(sd, OV8858_VERTICAL_END_H, res->regs); + if (ret < 0) + return ret; + + m->crop_vertical_end = ret; + + ret = ov8858_get_register_16bit(sd, OV8858_HORIZONTAL_OUTPUT_SIZE_H, + res->regs); + if (ret < 0) + return ret; + + m->output_width = ret; + + ret = ov8858_get_register_16bit(sd, OV8858_VERTICAL_OUTPUT_SIZE_H, + res->regs); + if (ret < 0) + return ret; + + m->output_height = ret; + + return 0; +} + +/* + * distance - calculate the distance + * @res: resolution + * @w: width + * @h: height + * + * Get the gap between res_w/res_h and w/h. + * distance = (res_w/res_h - w/h) / (w/h) * 8192 + * res->width/height smaller than w/h wouldn't be considered. + * The gap of ratio larger than 1/8 wouldn't be considered. + * Returns the value of gap or -1 if fail. + */ +#define LARGEST_ALLOWED_RATIO_MISMATCH 1024 +static int distance(struct ov8858_resolution const *res, const u32 w, + const u32 h) +{ + int ratio; + int distance; + + if (w == 0 || h == 0 || + res->width < w || res->height < h) + return -1; + + ratio = (res->width << 13); + ratio /= w; + ratio *= h; + ratio /= res->height; + + distance = abs(ratio - 8192); + + if (distance > LARGEST_ALLOWED_RATIO_MISMATCH) + return -1; + return distance; +} + +/* + * Returns the nearest higher resolution index. + * @w: width + * @h: height + * matching is done based on enveloping resolution and + * aspect ratio. If the aspect ratio cannot be matched + * to any index, -1 is returned. + */ +static int nearest_resolution_index(struct v4l2_subdev *sd, int w, int h) +{ + int i; + int idx = -1; + int dist; + int fps_diff; + int min_fps_diff = INT_MAX; + int min_dist = INT_MAX; + int min_res_w = INT_MAX; + const struct ov8858_resolution *tmp_res = NULL; + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct ov8858_device *dev = to_ov8858_sensor(sd); + dev_dbg(&client->dev, "%s: w=%d, h=%d\n", __func__, w, h); + + for (i = 0; i < dev->entries_curr_table; i++) { + tmp_res = &dev->curr_res_table[i]; + dist = distance(tmp_res, w, h); + dev_dbg(&client->dev, + "%s[%d]: %dx%d distance=%d\n", tmp_res->desc, + i, tmp_res->width, tmp_res->height, dist); + if (dist == -1) + continue; + if (dist < min_dist) { + min_dist = dist; + min_res_w = tmp_res->width; + min_fps_diff = __ov8858_min_fps_diff(dev->fps, + tmp_res->fps_options); + idx = i; + } + if (dist == min_dist) { + fps_diff = __ov8858_min_fps_diff(dev->fps, + tmp_res->fps_options); + if (fps_diff < min_fps_diff) { + min_fps_diff = fps_diff; + idx = i; + } + if (tmp_res->width < min_res_w) { + min_res_w = tmp_res->width; + idx = i; + } + } + } + + return idx; +} + +static int ov8858_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct camera_mipi_info *ov8858_info = NULL; + struct i2c_client *client = v4l2_get_subdevdata(sd); + const struct ov8858_resolution *res; + int ret; + int idx; + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + + ov8858_info = v4l2_get_subdev_hostdata(sd); + if (ov8858_info == NULL) + return -EINVAL; + + mutex_lock(&dev->input_lock); + + if ((fmt->width > OV8858_RES_WIDTH_MAX) || + (fmt->height > OV8858_RES_HEIGHT_MAX)) { + fmt->width = OV8858_RES_WIDTH_MAX; + fmt->height = OV8858_RES_HEIGHT_MAX; + } else { + idx = nearest_resolution_index(sd, fmt->width, fmt->height); + + /* + * nearest_resolution_index() doesn't return smaller + * resolutions. If it fails, it means the requested resolution + * is higher than we can support. Fallback to highest possible + * resolution in this case. + */ + if (idx == -1) + idx = dev->entries_curr_table - 1; + + fmt->width = dev->curr_res_table[idx].width; + fmt->height = dev->curr_res_table[idx].height; + } + + fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + cfg->try_fmt = *fmt; + mutex_unlock(&dev->input_lock); + return 0; + } + + dev->fmt_idx = nearest_resolution_index(sd, fmt->width, fmt->height); + if (dev->fmt_idx == -1) { + ret = -EINVAL; + goto out; + } + res = &dev->curr_res_table[dev->fmt_idx]; + dev_dbg(&client->dev, "%s: selected width = %d, height = %d\n", + __func__, res->width, res->height); + + /* Adjust the FPS selection based on the resolution selected */ + dev->fps_index = __ov8858_nearest_fps_index(dev->fps, res->fps_options); + dev->fps = res->fps_options[dev->fps_index].fps; + dev->regs = res->fps_options[dev->fps_index].regs; + if (!dev->regs) + dev->regs = res->regs; + + ret = ov8858_write_reg_array(client, dev->regs); + if (ret) + goto out; + + dev->pixels_per_line = res->fps_options[dev->fps_index].pixels_per_line; + dev->lines_per_frame = res->fps_options[dev->fps_index].lines_per_frame; + + /* ov8858 only support RGB RAW10 output */ + ov8858_info->metadata_width = res->width * 10 / 8; + ov8858_info->metadata_height = 2; + ov8858_info->metadata_format = ATOMISP_INPUT_FORMAT_EMBEDDED; + + /* Set the initial exposure */ + ret = __ov8858_set_exposure(sd, dev->exposure, dev->gain, + dev->digital_gain, &dev->pixels_per_line, + &dev->lines_per_frame); + if (ret) + goto out; + + ret = ov8858_get_intg_factor(sd, ov8858_info, dev->regs); + +out: + mutex_unlock(&dev->input_lock); + + return ret; +} + +static int ov8858_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct ov8858_device *dev = to_ov8858_sensor(sd); + + if (format->pad) + return -EINVAL; + if (!fmt) + return -EINVAL; + + mutex_lock(&dev->input_lock); + fmt->width = dev->curr_res_table[dev->fmt_idx].width; + fmt->height = dev->curr_res_table[dev->fmt_idx].height; + fmt->code = MEDIA_BUS_FMT_SBGGR10_1X10; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static int ov8858_detect(struct i2c_client *client, u16 *id) +{ + struct i2c_adapter *adapter = client->adapter; + u16 id_hi = 0; + u16 id_low = 0; + int ret; + + /* i2c check */ + if (!i2c_check_functionality(adapter, I2C_FUNC_I2C)) + return -ENODEV; + + dev_dbg(&client->dev, "%s: I2C functionality ok\n", __func__); + ret = ov8858_read_reg(client, OV8858_8BIT, OV8858_CHIP_ID_HIGH, &id_hi); + if (ret) + return ret; + dev_dbg(&client->dev, "%s: id_high = 0x%04x\n", __func__, id_hi); + ret = ov8858_read_reg(client, OV8858_8BIT, OV8858_CHIP_ID_LOW, &id_low); + if (ret) + return ret; + dev_dbg(&client->dev, "%s: id_low = 0x%04x\n", __func__, id_low); + *id = (id_hi << 8) | id_low; + + dev_dbg(&client->dev, "%s: chip_id = 0x%04x\n", __func__, *id); + + dev_info(&client->dev, "%s: chip_id = 0x%04x\n", __func__, *id); + if (*id != OV8858_CHIP_ID) + return -ENODEV; + + /* Stream off now. */ + return ov8858_write_reg(client, OV8858_8BIT, OV8858_STREAM_MODE, 0); +} + +static void __ov8858_print_timing(struct v4l2_subdev *sd) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 width = dev->curr_res_table[dev->fmt_idx].width; + u16 height = dev->curr_res_table[dev->fmt_idx].height; + + dev_dbg(&client->dev, "Dump ov8858 timing in stream on:\n"); + dev_dbg(&client->dev, "width: %d:\n", width); + dev_dbg(&client->dev, "height: %d:\n", height); + dev_dbg(&client->dev, "pixels_per_line: %d:\n", dev->pixels_per_line); + dev_dbg(&client->dev, "line per frame: %d:\n", dev->lines_per_frame); + dev_dbg(&client->dev, "pix freq: %d:\n", dev->vt_pix_clk_freq_mhz); + /* updated formula: pixels_per_line = 2 * HTS */ + /* updated formula: fps = SCLK / (VTS * HTS) */ + dev_dbg(&client->dev, "init fps: %d:\n", dev->vt_pix_clk_freq_mhz / + (dev->pixels_per_line / 2) / dev->lines_per_frame); + dev_dbg(&client->dev, "HBlank: %d nS:\n", + 1000 * (dev->pixels_per_line - width) / + (dev->vt_pix_clk_freq_mhz / 1000000)); + dev_dbg(&client->dev, "VBlank: %d uS:\n", + (dev->lines_per_frame - height) * dev->pixels_per_line / + (dev->vt_pix_clk_freq_mhz / 1000000)); +} + +/* + * ov8858 stream on/off + */ +static int ov8858_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + int ret; + u16 val; + dev_dbg(&client->dev, "%s: enable = %d\n", __func__, enable); + + /* Set orientation */ + ret = ov8858_read_reg(client, OV8858_8BIT, OV8858_FORMAT2, &val); + if (ret) + return ret; + + ret = ov8858_write_reg(client, OV8858_8BIT, OV8858_FORMAT2, + dev->hflip ? val | OV8858_FLIP_ENABLE : + val & ~OV8858_FLIP_ENABLE); + if (ret) + return ret; + + ret = ov8858_read_reg(client, OV8858_8BIT, OV8858_FORMAT1, &val); + if (ret) + return ret; + + ret = ov8858_write_reg(client, OV8858_8BIT, OV8858_FORMAT1, + dev->vflip ? val | OV8858_FLIP_ENABLE : + val & ~OV8858_FLIP_ENABLE); + if (ret) + return ret; + + mutex_lock(&dev->input_lock); + if (enable) { + __ov8858_print_timing(sd); + ret = ov8858_write_reg_array(client, ov8858_streaming); + if (ret != 0) { + dev_err(&client->dev, "write_reg_array err\n"); + goto out; + } + dev->streaming = 1; + } else { + ret = ov8858_write_reg_array(client, ov8858_soft_standby); + if (ret != 0) { + dev_err(&client->dev, "write_reg_array err\n"); + goto out; + } + dev->streaming = 0; + dev->fps_index = 0; + dev->fps = 0; + } +out: + mutex_unlock(&dev->input_lock); + return ret; +} + +static int __update_ov8858_device_settings(struct ov8858_device *dev, + u16 sensor_id) +{ + if (sensor_id == OV8858_CHIP_ID) +#ifdef CONFIG_PLATFORM_BTNS + dev->vcm_driver = &ov8858_vcms[OV8858_ID_DEFAULT]; +#else + dev->vcm_driver = &ov8858_vcms[OV8858_SUNNY]; +#endif + else + return -ENODEV; + + if (dev->vcm_driver && dev->vcm_driver->init) + return dev->vcm_driver->init(&dev->sd); + + return 0; +} + +static int ov8858_s_config(struct v4l2_subdev *sd, + int irq, void *pdata) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + u16 sensor_id; + int ret; + + if (pdata == NULL) + return -ENODEV; + + dev->platform_data = pdata; + + mutex_lock(&dev->input_lock); + + if (dev->platform_data->platform_init) { + ret = dev->platform_data->platform_init(client); + if (ret) { + mutex_unlock(&dev->input_lock); + dev_err(&client->dev, "platform init error %d!\n", ret); + return ret; + } + } + + ret = __ov8858_s_power(sd, 1); + if (ret) { + dev_err(&client->dev, "power-up error %d!\n", ret); + mutex_unlock(&dev->input_lock); + return ret; + } + + ret = dev->platform_data->csi_cfg(sd, 1); + if (ret) + goto fail_csi_cfg; + + /* config & detect sensor */ + ret = ov8858_detect(client, &sensor_id); + if (ret) { + dev_err(&client->dev, "detect error %d!\n", ret); + goto fail_detect; + } + + dev->sensor_id = sensor_id; + + /* power off sensor */ + ret = __ov8858_s_power(sd, 0); + if (ret) { + dev->platform_data->csi_cfg(sd, 0); + dev_err(&client->dev, "__ov8858_s_power-down error %d!\n", ret); + goto fail_update; + } + + /* Resolution settings depend on sensor type and platform */ + ret = __update_ov8858_device_settings(dev, dev->sensor_id); + if (ret) { + dev->platform_data->csi_cfg(sd, 0); + dev_err(&client->dev, "__update_ov8858_device_settings error %d!\n", ret); + goto fail_update; + } + + mutex_unlock(&dev->input_lock); + return ret; + +fail_detect: + dev->platform_data->csi_cfg(sd, 0); +fail_csi_cfg: + __ov8858_s_power(sd, 0); +fail_update: + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); + mutex_unlock(&dev->input_lock); + dev_err(&client->dev, "sensor power-gating failed\n"); + return ret; +} + +static int +ov8858_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index) + return -EINVAL; + code->code = MEDIA_BUS_FMT_SBGGR10_1X10; + + return 0; +} + +static int +ov8858_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + int index = fse->index; + struct ov8858_device *dev = to_ov8858_sensor(sd); + + mutex_lock(&dev->input_lock); + if (index >= dev->entries_curr_table) { + mutex_unlock(&dev->input_lock); + return -EINVAL; + } + + fse->min_width = dev->curr_res_table[index].width; + fse->min_height = dev->curr_res_table[index].height; + fse->max_width = dev->curr_res_table[index].width; + fse->max_height = dev->curr_res_table[index].height; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static int ov8858_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov8858_device *dev = container_of( + ctrl->handler, struct ov8858_device, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); + + /* input_lock is taken by the control framework, so it + * doesn't need to be taken here. + */ + + switch (ctrl->id) { + case V4L2_CID_RUN_MODE: + switch (ctrl->val) { + case ATOMISP_RUN_MODE_VIDEO: + dev->curr_res_table = ov8858_res_video; + dev->entries_curr_table = ARRAY_SIZE(ov8858_res_video); + break; + case ATOMISP_RUN_MODE_STILL_CAPTURE: + dev->curr_res_table = ov8858_res_still; + dev->entries_curr_table = ARRAY_SIZE(ov8858_res_still); + break; + default: + dev->curr_res_table = ov8858_res_preview; + dev->entries_curr_table = + ARRAY_SIZE(ov8858_res_preview); + } + + dev->fmt_idx = 0; + dev->fps_index = 0; + + return 0; + case V4L2_CID_FOCUS_ABSOLUTE: + if (dev->vcm_driver && dev->vcm_driver->t_focus_abs) + return dev->vcm_driver->t_focus_abs(&dev->sd, + ctrl->val); + return 0; + case V4L2_CID_EXPOSURE_AUTO_PRIORITY: + if (ctrl->val == V4L2_EXPOSURE_AUTO) + dev->limit_exposure_flag = false; + else if (ctrl->val == V4L2_EXPOSURE_APERTURE_PRIORITY) + dev->limit_exposure_flag = true; + return 0; + case V4L2_CID_HFLIP: + dev->hflip = ctrl->val; + return 0; + case V4L2_CID_VFLIP: + dev->vflip = ctrl->val; + return 0; + default: + dev_err(&client->dev, "%s: Error: Invalid ctrl: 0x%X\n", + __func__, ctrl->id); + return -EINVAL; + } +} + +static int ov8858_g_ctrl(struct v4l2_ctrl *ctrl) +{ + struct ov8858_device *dev = container_of( + ctrl->handler, struct ov8858_device, ctrl_handler); + struct i2c_client *client = v4l2_get_subdevdata(&dev->sd); + int r_odd, r_even; + int i = dev->fmt_idx; + + switch (ctrl->id) { + case V4L2_CID_FOCUS_STATUS: + if (dev->vcm_driver && dev->vcm_driver->q_focus_status) + return dev->vcm_driver->q_focus_status(&dev->sd, + &(ctrl->val)); + return 0; + case V4L2_CID_BIN_FACTOR_HORZ: + r_odd = ov8858_get_register_8bit(&dev->sd, OV8858_H_INC_ODD, + dev->curr_res_table[i].regs); + if (r_odd < 0) + return r_odd; + r_even = ov8858_get_register_8bit(&dev->sd, OV8858_H_INC_EVEN, + dev->curr_res_table[i].regs); + if (r_even < 0) + return r_even; + ctrl->val = fls(r_odd + (r_even)) - 2; + return 0; + + case V4L2_CID_BIN_FACTOR_VERT: + r_odd = ov8858_get_register_8bit(&dev->sd, OV8858_V_INC_ODD, + dev->curr_res_table[i].regs); + if (r_odd < 0) + return r_odd; + r_even = ov8858_get_register_8bit(&dev->sd, OV8858_V_INC_EVEN, + dev->curr_res_table[i].regs); + if (r_even < 0) + return r_even; + ctrl->val = fls(r_odd + (r_even)) - 2; + return 0; + case V4L2_CID_HFLIP: + ctrl->val = dev->hflip; + break; + case V4L2_CID_VFLIP: + ctrl->val = dev->vflip; + break; + case V4L2_CID_EXPOSURE_ABSOLUTE: + ctrl->val = dev->exposure; + break; + default: + dev_warn(&client->dev, + "%s: Error: Invalid ctrl: 0x%X\n", __func__, ctrl->id); + return -EINVAL; + } + + return 0; +} + +static int +ov8858_g_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + const struct ov8858_resolution *res = + &dev->curr_res_table[dev->fmt_idx]; + + mutex_lock(&dev->input_lock); + interval->interval.denominator = res->fps_options[dev->fps_index].fps; + interval->interval.numerator = 1; + mutex_unlock(&dev->input_lock); + return 0; +} + +static int __ov8858_s_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + struct i2c_client *client = v4l2_get_subdevdata(sd); + const struct ov8858_resolution *res = + &dev->curr_res_table[dev->fmt_idx]; + struct camera_mipi_info *info = NULL; + unsigned int fps_index; + int ret = 0; + int fps; + + info = v4l2_get_subdev_hostdata(sd); + if (info == NULL) + return -EINVAL; + + if (!interval->interval.numerator) + interval->interval.numerator = 1; + + fps = interval->interval.denominator / interval->interval.numerator; + + /* No need to proceed further if we are not streaming */ + if (!dev->streaming) { + /* Save the new FPS and use it while selecting setting */ + dev->fps = fps; + return 0; + } + + /* Ignore if we are already using the required FPS. */ + if (fps == res->fps_options[dev->fps_index].fps) + return 0; + + fps_index = __ov8858_nearest_fps_index(fps, res->fps_options); + + if (res->fps_options[fps_index].regs && + res->fps_options[fps_index].regs != dev->regs) { + dev_err(&client->dev, + "Sensor is streaming, can't apply new configuration\n"); + return -EBUSY; + } + + dev->fps_index = fps_index; + dev->fps = res->fps_options[dev->fps_index].fps; + + /* Update the new frametimings based on FPS */ + dev->pixels_per_line = + res->fps_options[dev->fps_index].pixels_per_line; + dev->lines_per_frame = + res->fps_options[dev->fps_index].lines_per_frame; + + /* update frametiming. Conside the curren exposure/gain as well */ + ret = __ov8858_update_frame_timing(sd, + &dev->pixels_per_line, &dev->lines_per_frame); + if (ret) + return ret; + + /* Update the new values so that user side knows the current settings */ + ret = ov8858_get_intg_factor(sd, info, dev->regs); + if (ret) + return ret; + + interval->interval.denominator = res->fps_options[dev->fps_index].fps; + interval->interval.numerator = 1; + __ov8858_print_timing(sd); + + return ret; +} + +static int ov8858_s_frame_interval(struct v4l2_subdev *sd, + struct v4l2_subdev_frame_interval *interval) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + int ret; + + mutex_lock(&dev->input_lock); + ret = __ov8858_s_frame_interval(sd, interval); + mutex_unlock(&dev->input_lock); + + return ret; +} + +static int ov8858_g_skip_frames(struct v4l2_subdev *sd, u32 *frames) +{ + struct ov8858_device *dev = to_ov8858_sensor(sd); + + mutex_lock(&dev->input_lock); + *frames = dev->curr_res_table[dev->fmt_idx].skip_frames; + mutex_unlock(&dev->input_lock); + + return 0; +} + +static const struct v4l2_subdev_sensor_ops ov8858_sensor_ops = { + .g_skip_frames = ov8858_g_skip_frames, +}; + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = ov8858_s_ctrl, + .g_volatile_ctrl = ov8858_g_ctrl, +}; + +static const struct v4l2_subdev_video_ops ov8858_video_ops = { + .s_stream = ov8858_s_stream, + .g_frame_interval = ov8858_g_frame_interval, + .s_frame_interval = ov8858_s_frame_interval, +}; + +static const struct v4l2_subdev_core_ops ov8858_core_ops = { + .s_power = ov8858_s_power, + .ioctl = ov8858_ioctl, + .init = ov8858_init, +}; + +static const struct v4l2_subdev_pad_ops ov8858_pad_ops = { + .enum_mbus_code = ov8858_enum_mbus_code, + .enum_frame_size = ov8858_enum_frame_size, + .get_fmt = ov8858_get_fmt, + .set_fmt = ov8858_set_fmt, +}; + +static const struct v4l2_subdev_ops ov8858_ops = { + .core = &ov8858_core_ops, + .video = &ov8858_video_ops, + .pad = &ov8858_pad_ops, + .sensor = &ov8858_sensor_ops, +}; + +static const struct media_entity_operations ov_entity_ops = { + .link_setup = NULL, +}; + +static int ov8858_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd = i2c_get_clientdata(client); + struct ov8858_device *dev = to_ov8858_sensor(sd); + if (dev->platform_data->platform_deinit) + dev->platform_data->platform_deinit(); + + media_entity_cleanup(&dev->sd.entity); + v4l2_ctrl_handler_free(&dev->ctrl_handler); + dev->platform_data->csi_cfg(sd, 0); + v4l2_device_unregister_subdev(sd); + kfree(dev); + + return 0; +} + +static const char * const ctrl_run_mode_menu[] = { + NULL, + "Video", + "Still capture", + "Continuous capture", + "Preview", +}; + +static const struct v4l2_ctrl_config ctrl_run_mode = { + .ops = &ctrl_ops, + .id = V4L2_CID_RUN_MODE, + .name = "run mode", + .type = V4L2_CTRL_TYPE_MENU, + .min = 1, + .def = 4, + .max = 4, + .qmenu = ctrl_run_mode_menu, +}; + +static const struct v4l2_ctrl_config ctrls[] = { + { + .ops = &ctrl_ops, + .id = V4L2_CID_VFLIP, + .name = "Vertical flip", + .type = V4L2_CTRL_TYPE_BOOLEAN, + .min = false, + .max = true, + .step = 1, + }, { + .ops = &ctrl_ops, + .id = V4L2_CID_HFLIP, + .name = "Horizontal flip", + .type = V4L2_CTRL_TYPE_BOOLEAN, + .min = false, + .max = true, + .step = 1, + }, { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_ABSOLUTE, + .name = "Absolute exposure", + .type = V4L2_CTRL_TYPE_INTEGER, + .max = 0xffff, + .min = 0x0, + .step = 1, + .def = 0x00, + .flags = V4L2_CTRL_FLAG_READ_ONLY | V4L2_CTRL_FLAG_VOLATILE, + }, { + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_ABSOLUTE, + .name = "Focus absolute", + .type = V4L2_CTRL_TYPE_INTEGER, + .step = 1, + .max = OV8858_MAX_FOCUS_POS, + }, { + /* This one is junk: see the spec for proper use of this CID. */ + .ops = &ctrl_ops, + .id = V4L2_CID_FOCUS_STATUS, + .name = "Focus status", + .type = V4L2_CTRL_TYPE_INTEGER, + .step = 1, + .max = 100, + .flags = V4L2_CTRL_FLAG_READ_ONLY | V4L2_CTRL_FLAG_VOLATILE, + }, { + /* This is crap. For compatibility use only. */ + .ops = &ctrl_ops, + .id = V4L2_CID_FOCAL_ABSOLUTE, + .name = "Focal lenght", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = (OV8858_FOCAL_LENGTH_NUM << 16) | + OV8858_FOCAL_LENGTH_DEM, + .max = (OV8858_FOCAL_LENGTH_NUM << 16) | + OV8858_FOCAL_LENGTH_DEM, + .step = 1, + .def = (OV8858_FOCAL_LENGTH_NUM << 16) | + OV8858_FOCAL_LENGTH_DEM, + .flags = V4L2_CTRL_FLAG_READ_ONLY, + }, { + /* This one is crap, too. For compatibility use only. */ + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_ABSOLUTE, + .name = "F-number", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = (OV8858_F_NUMBER_DEFAULT_NUM << 16) | + OV8858_F_NUMBER_DEM, + .max = (OV8858_F_NUMBER_DEFAULT_NUM << 16) | + OV8858_F_NUMBER_DEM, + .step = 1, + .def = (OV8858_F_NUMBER_DEFAULT_NUM << 16) | + OV8858_F_NUMBER_DEM, + .flags = V4L2_CTRL_FLAG_READ_ONLY, + }, { + /* + * The most utter crap. _Never_ use this, even for + * compatibility reasons! + */ + .ops = &ctrl_ops, + .id = V4L2_CID_FNUMBER_RANGE, + .name = "F-number range", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = (OV8858_F_NUMBER_DEFAULT_NUM << 24) | + (OV8858_F_NUMBER_DEM << 16) | + (OV8858_F_NUMBER_DEFAULT_NUM << 8) | + OV8858_F_NUMBER_DEM, + .max = (OV8858_F_NUMBER_DEFAULT_NUM << 24) | + (OV8858_F_NUMBER_DEM << 16) | + (OV8858_F_NUMBER_DEFAULT_NUM << 8) | + OV8858_F_NUMBER_DEM, + .step = 1, + .def = (OV8858_F_NUMBER_DEFAULT_NUM << 24) | + (OV8858_F_NUMBER_DEM << 16) | + (OV8858_F_NUMBER_DEFAULT_NUM << 8) | + OV8858_F_NUMBER_DEM, + .flags = V4L2_CTRL_FLAG_READ_ONLY, + }, { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_HORZ, + .name = "Horizontal binning factor", + .type = V4L2_CTRL_TYPE_INTEGER, + .max = OV8858_BIN_FACTOR_MAX, + .step = 1, + .flags = V4L2_CTRL_FLAG_READ_ONLY | V4L2_CTRL_FLAG_VOLATILE, + }, { + .ops = &ctrl_ops, + .id = V4L2_CID_BIN_FACTOR_VERT, + .name = "Vertical binning factor", + .type = V4L2_CTRL_TYPE_INTEGER, + .max = OV8858_BIN_FACTOR_MAX, + .step = 1, + .flags = V4L2_CTRL_FLAG_READ_ONLY | V4L2_CTRL_FLAG_VOLATILE, + }, { + .ops = &ctrl_ops, + .id = V4L2_CID_EXPOSURE_AUTO_PRIORITY, + .name = "Exposure auto priority", + .type = V4L2_CTRL_TYPE_INTEGER, + .min = V4L2_EXPOSURE_AUTO, + .max = V4L2_EXPOSURE_APERTURE_PRIORITY, + .step = 1, + } +}; + +static int ov8858_probe(struct i2c_client *client, + const struct i2c_device_id *id) +{ + struct ov8858_device *dev; + unsigned int i; + int ret = 0; + struct camera_sensor_platform_data *pdata; + + dev_dbg(&client->dev, "%s:\n", __func__); + + /* allocate sensor device & init sub device */ + dev = kzalloc(sizeof(*dev), GFP_KERNEL); + if (!dev) { + dev_err(&client->dev, "%s: out of memory\n", __func__); + return -ENOMEM; + } + + mutex_init(&dev->input_lock); + + if (id) + dev->i2c_id = id->driver_data; + dev->fmt_idx = 0; + dev->sensor_id = OV_ID_DEFAULT; + dev->vcm_driver = &ov8858_vcms[OV8858_ID_DEFAULT]; + + v4l2_i2c_subdev_init(&(dev->sd), client, &ov8858_ops); + + if (ACPI_COMPANION(&client->dev)) { + pdata = gmin_camera_platform_data(&dev->sd, + ATOMISP_INPUT_FORMAT_RAW_10, + atomisp_bayer_order_bggr); + if (!pdata) { + dev_err(&client->dev, + "%s: failed to get acpi platform data\n", + __func__); + goto out_free; + } + ret = ov8858_s_config(&dev->sd, client->irq, pdata); + if (ret) { + dev_err(&client->dev, + "%s: failed to set config\n", __func__); + goto out_free; + } + ret = atomisp_register_i2c_module(&dev->sd, pdata, RAW_CAMERA); + if (ret) { + dev_err(&client->dev, + "%s: failed to register subdev\n", __func__); + goto out_free; + } + } + /* + * sd->name is updated with sensor driver name by the v4l2. + * change it to sensor name in this case. + */ + snprintf(dev->sd.name, sizeof(dev->sd.name), "%s%x %d-%04x", + OV_SUBDEV_PREFIX, dev->sensor_id, + i2c_adapter_id(client->adapter), client->addr); + + dev->sd.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + dev->pad.flags = MEDIA_PAD_FL_SOURCE; + dev->format.code = MEDIA_BUS_FMT_SBGGR10_1X10; + dev->sd.entity.ops = &ov_entity_ops; + dev->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; + + ret = v4l2_ctrl_handler_init(&dev->ctrl_handler, ARRAY_SIZE(ctrls) + 1); + if (ret) { + ov8858_remove(client); + return ret; + } + + dev->run_mode = v4l2_ctrl_new_custom(&dev->ctrl_handler, + &ctrl_run_mode, NULL); + + for (i = 0; i < ARRAY_SIZE(ctrls); i++) + v4l2_ctrl_new_custom(&dev->ctrl_handler, &ctrls[i], NULL); + + if (dev->ctrl_handler.error) { + ov8858_remove(client); + return dev->ctrl_handler.error; + } + + /* Use same lock for controls as for everything else. */ + dev->ctrl_handler.lock = &dev->input_lock; + dev->sd.ctrl_handler = &dev->ctrl_handler; + v4l2_ctrl_handler_setup(&dev->ctrl_handler); + + ret = media_entity_pads_init(&dev->sd.entity, 1, &dev->pad); + if (ret) { + ov8858_remove(client); + return ret; + } + + return 0; + +out_free: + v4l2_device_unregister_subdev(&dev->sd); + kfree(dev); + return ret; +} + +static const struct i2c_device_id ov8858_id[] = { + {OV8858_NAME, 0}, + {} +}; + +MODULE_DEVICE_TABLE(i2c, ov8858_id); + +static struct acpi_device_id ov8858_acpi_match[] = { + {"INT3477"}, + {}, +}; + +static struct i2c_driver ov8858_driver = { + .driver = { + .owner = THIS_MODULE, + .name = OV8858_NAME, + .acpi_match_table = ACPI_PTR(ov8858_acpi_match), + }, + .probe = ov8858_probe, + .remove = ov8858_remove, + .id_table = ov8858_id, +}; + +static __init int ov8858_init_mod(void) +{ + int ret; + ret = i2c_add_driver(&ov8858_driver); + return ret; +} + +static __exit void ov8858_exit_mod(void) +{ + i2c_del_driver(&ov8858_driver); +} + +module_init(ov8858_init_mod); +module_exit(ov8858_exit_mod); + +MODULE_DESCRIPTION("A low-level driver for Omnivision OV8858 sensors"); +MODULE_LICENSE("GPL"); diff --git a/drivers/staging/media/atomisp/i2c/ov8858.h b/drivers/staging/media/atomisp/i2c/ov8858.h new file mode 100644 index 0000000000000000000000000000000000000000..13c8fb12d9f6294fca237c715b73e50c871e54e3 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov8858.h @@ -0,0 +1,1482 @@ +/* + * Support for the Omnivision OV8858 camera sensor. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __OV8858_H__ +#define __OV8858_H__ +#include +#include + +#define I2C_MSG_LENGTH 0x2 + +/* + * This should be added into include/linux/videodev2.h + * NOTE: This is most likely not used anywhere. + */ +#define V4L2_IDENT_OV8858 V4L2_IDENT_UNKNOWN + +/* + * Indexes for VCM driver lists + */ +#define OV8858_ID_DEFAULT 0 +#define OV8858_SUNNY 1 + +#define OV8858_OTP_START_ADDR 0x7010 +#define OV8858_OTP_END_ADDR 0x7186 + +/* + * ov8858 System control registers + */ + +#define OV8858_OTP_LOAD_CTRL 0x3D81 +#define OV8858_OTP_MODE_CTRL 0x3D84 +#define OV8858_OTP_START_ADDR_REG 0x3D88 +#define OV8858_OTP_END_ADDR_REG 0x3D8A +#define OV8858_OTP_ISP_CTRL2 0x5002 + +#define OV8858_OTP_MODE_MANUAL BIT(6) +#define OV8858_OTP_MODE_PROGRAM_DISABLE BIT(7) +#define OV8858_OTP_LOAD_ENABLE BIT(0) +#define OV8858_OTP_DPC_ENABLE BIT(3) + +#define OV8858_PLL1_PREDIV0 0x030A +#define OV8858_PLL1_PREDIV 0x0300 +#define OV8858_PLL1_MULTIPLIER 0x0301 +#define OV8858_PLL1_SYS_PRE_DIV 0x0305 +#define OV8858_PLL1_SYS_DIVIDER 0x0306 + +#define OV8858_PLL1_PREDIV0_MASK BIT(0) +#define OV8858_PLL1_PREDIV_MASK (BIT(0) | BIT(1) | BIT(2)) +#define OV8858_PLL1_MULTIPLIER_MASK 0x01FF +#define OV8858_PLL1_SYS_PRE_DIV_MASK (BIT(0) | BIT(1)) +#define OV8858_PLL1_SYS_DIVIDER_MASK BIT(0) + +#define OV8858_PLL2_PREDIV0 0x0312 +#define OV8858_PLL2_PREDIV 0x030B +#define OV8858_PLL2_MULTIPLIER 0x030C +#define OV8858_PLL2_DAC_DIVIDER 0x0312 +#define OV8858_PLL2_SYS_PRE_DIV 0x030F +#define OV8858_PLL2_SYS_DIVIDER 0x030E + +#define OV8858_PLL2_PREDIV0_MASK BIT(4) +#define OV8858_PLL2_PREDIV_MASK (BIT(0) | BIT(1) | BIT(2)) +#define OV8858_PLL2_MULTIPLIER_MASK 0x01FF +#define OV8858_PLL2_DAC_DIVIDER_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define OV8858_PLL2_SYS_PRE_DIV_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define OV8858_PLL2_SYS_DIVIDER_MASK (BIT(0) | BIT(1) | BIT(2)) + +#define OV8858_PLL_SCLKSEL1 0x3032 +#define OV8858_PLL_SCLKSEL2 0x3033 +#define OV8858_SRB_HOST_INPUT_DIS 0x3106 + +#define OV8858_PLL_SCLKSEL1_MASK BIT(7) +#define OV8858_PLL_SCLKSEL2_MASK BIT(1) + +#define OV8858_SYS_PRE_DIV_OFFSET 2 +#define OV8858_SYS_PRE_DIV_MASK (BIT(2) | BIT(3)) +#define OV8858_SCLK_PDIV_OFFSET 4 +#define OV8858_SCLK_PDIV_MASK (BIT(4) | BIT(5) | BIT(6) | BIT(7)) + +#define OV8858_TIMING_HTS 0x380C +#define OV8858_TIMING_VTS 0x380E + +#define OV8858_HORIZONTAL_START_H 0x3800 +#define OV8858_VERTICAL_START_H 0x3802 +#define OV8858_HORIZONTAL_END_H 0x3804 +#define OV8858_VERTICAL_END_H 0x3806 +#define OV8858_HORIZONTAL_OUTPUT_SIZE_H 0x3808 +#define OV8858_VERTICAL_OUTPUT_SIZE_H 0x380A + +#define OV8858_GROUP_ACCESS 0x3208 +#define OV8858_GROUP_ZERO 0x00 +#define OV8858_GROUP_ACCESS_HOLD_START 0x00 +#define OV8858_GROUP_ACCESS_HOLD_END 0x10 +#define OV8858_GROUP_ACCESS_DELAY_LAUNCH 0xA0 +#define OV8858_GROUP_ACCESS_QUICK_LAUNCH 0xE0 + +#define OV_SUBDEV_PREFIX "ov" +#define OV_ID_DEFAULT 0x0000 +#define OV8858_NAME "ov8858" +#define OV8858_CHIP_ID 0x8858 + +#define OV8858_LONG_EXPO 0x3500 +#define OV8858_LONG_GAIN 0x3508 +#define OV8858_LONG_DIGI_GAIN 0x350A +#define OV8858_SHORT_GAIN 0x350C +#define OV8858_SHORT_DIGI_GAIN 0x350E + +#define OV8858_FORMAT1 0x3820 +#define OV8858_FORMAT2 0x3821 + +#define OV8858_FLIP_ENABLE 0x06 + +#define OV8858_MWB_RED_GAIN_H 0x5032 +#define OV8858_MWB_GREEN_GAIN_H 0x5034 +#define OV8858_MWB_BLUE_GAIN_H 0x5036 +#define OV8858_MWB_GAIN_MAX 0x0FFF + +#define OV8858_CHIP_ID_HIGH 0x300B +#define OV8858_CHIP_ID_LOW 0x300C +#define OV8858_STREAM_MODE 0x0100 + +#define OV8858_FOCAL_LENGTH_NUM 294 /* 2.94mm */ +#define OV8858_FOCAL_LENGTH_DEM 100 +#define OV8858_F_NUMBER_DEFAULT_NUM 24 /* 2.4 */ +#define OV8858_F_NUMBER_DEM 10 + +#define OV8858_H_INC_ODD 0x3814 +#define OV8858_H_INC_EVEN 0x3815 +#define OV8858_V_INC_ODD 0x382A +#define OV8858_V_INC_EVEN 0x382B + +#define OV8858_READ_MODE_BINNING_ON 0x0400 /* ToDo: Check this */ +#define OV8858_READ_MODE_BINNING_OFF 0x00 /* ToDo: Check this */ +#define OV8858_BIN_FACTOR_MAX 2 +#define OV8858_INTEGRATION_TIME_MARGIN 14 + +#define OV8858_MAX_VTS_VALUE 0xFFFF +#define OV8858_MAX_EXPOSURE_VALUE \ + (OV8858_MAX_VTS_VALUE - OV8858_INTEGRATION_TIME_MARGIN) +#define OV8858_MAX_GAIN_VALUE 0x07FF + +#define OV8858_MAX_FOCUS_POS 1023 + +#define OV8858_TEST_PATTERN_REG 0x5E00 + +struct ov8858_vcm { + int (*power_up)(struct v4l2_subdev *sd); + int (*power_down)(struct v4l2_subdev *sd); + int (*init)(struct v4l2_subdev *sd); + int (*t_focus_vcm)(struct v4l2_subdev *sd, u16 val); + int (*t_focus_abs)(struct v4l2_subdev *sd, s32 value); + int (*t_focus_rel)(struct v4l2_subdev *sd, s32 value); + int (*q_focus_status)(struct v4l2_subdev *sd, s32 *value); + int (*q_focus_abs)(struct v4l2_subdev *sd, s32 *value); + int (*t_vcm_slew)(struct v4l2_subdev *sd, s32 value); + int (*t_vcm_timing)(struct v4l2_subdev *sd, s32 value); +}; + +/* + * Defines for register writes and register array processing + * */ +#define OV8858_BYTE_MAX 32 +#define OV8858_SHORT_MAX 16 +#define OV8858_TOK_MASK 0xFFF0 + +#define MAX_FPS_OPTIONS_SUPPORTED 3 + +#define OV8858_DEPTH_COMP_CONST 2200 +#define OV8858_DEPTH_VTS_CONST 2573 + +enum ov8858_tok_type { + OV8858_8BIT = 0x0001, + OV8858_16BIT = 0x0002, + OV8858_TOK_TERM = 0xF000, /* terminating token for reg list */ + OV8858_TOK_DELAY = 0xFE00 /* delay token for reg list */ +}; + +/* + * If register address or register width is not 32 bit width, + * user needs to convert it manually + */ +struct s_register_setting { + u32 reg; + u32 val; +}; + +/** + * struct ov8858_reg - MI sensor register format + * @type: type of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ +struct ov8858_reg { + enum ov8858_tok_type type; + u16 sreg; + u32 val; /* @set value for read/mod/write, @mask */ +}; + +struct ov8858_fps_setting { + int fps; + unsigned short pixels_per_line; + unsigned short lines_per_frame; + const struct ov8858_reg *regs; /* regs that the fps setting needs */ +}; + +struct ov8858_resolution { + u8 *desc; + const struct ov8858_reg *regs; + int res; + int width; + int height; + bool used; + u8 bin_factor_x; + u8 bin_factor_y; + unsigned short skip_frames; + const struct ov8858_fps_setting fps_options[MAX_FPS_OPTIONS_SUPPORTED]; +}; + +/* + * ov8858 device structure + * */ +struct ov8858_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + + struct camera_sensor_platform_data *platform_data; + struct mutex input_lock; /* serialize sensor's ioctl */ + int fmt_idx; + int streaming; + int vt_pix_clk_freq_mhz; + int fps_index; + u16 sensor_id; /* Sensor id from registers */ + u16 i2c_id; /* Sensor id from i2c_device_id */ + int exposure; + int gain; + u16 digital_gain; + u16 pixels_per_line; + u16 lines_per_frame; + u8 fps; + u8 *otp_data; + /* Prevent the framerate from being lowered in low light scenes. */ + int limit_exposure_flag; + bool hflip; + bool vflip; + + const struct ov8858_reg *regs; + struct ov8858_vcm *vcm_driver; + const struct ov8858_resolution *curr_res_table; + int entries_curr_table; + + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *run_mode; +}; + +#define to_ov8858_sensor(x) container_of(x, struct ov8858_device, sd) + +#define OV8858_MAX_WRITE_BUF_SIZE 32 +struct ov8858_write_buffer { + u16 addr; + u8 data[OV8858_MAX_WRITE_BUF_SIZE]; +}; + +struct ov8858_write_ctrl { + int index; + struct ov8858_write_buffer buffer; +}; + +static const struct ov8858_reg ov8858_soft_standby[] = { + {OV8858_8BIT, 0x0100, 0x00}, + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_streaming[] = { + {OV8858_8BIT, 0x0100, 0x01}, + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_param_hold[] = { + {OV8858_8BIT, OV8858_GROUP_ACCESS, + OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_HOLD_START}, + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_param_update[] = { + {OV8858_8BIT, OV8858_GROUP_ACCESS, + OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_HOLD_END}, + {OV8858_8BIT, OV8858_GROUP_ACCESS, + OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_DELAY_LAUNCH}, + {OV8858_TOK_TERM, 0, 0} +}; + +extern int dw9718_vcm_power_up(struct v4l2_subdev *sd); +extern int dw9718_vcm_power_down(struct v4l2_subdev *sd); +extern int dw9718_vcm_init(struct v4l2_subdev *sd); +extern int dw9718_t_focus_vcm(struct v4l2_subdev *sd, u16 val); +extern int dw9718_t_focus_abs(struct v4l2_subdev *sd, s32 value); +extern int dw9718_t_focus_rel(struct v4l2_subdev *sd, s32 value); +extern int dw9718_q_focus_status(struct v4l2_subdev *sd, s32 *value); +extern int dw9718_q_focus_abs(struct v4l2_subdev *sd, s32 *value); +extern int dw9718_t_vcm_slew(struct v4l2_subdev *sd, s32 value); +extern int dw9718_t_vcm_timing(struct v4l2_subdev *sd, s32 value); + +extern int vcm_power_up(struct v4l2_subdev *sd); +extern int vcm_power_down(struct v4l2_subdev *sd); + +static struct ov8858_vcm ov8858_vcms[] = { + [OV8858_SUNNY] = { + .power_up = dw9718_vcm_power_up, + .power_down = dw9718_vcm_power_down, + .init = dw9718_vcm_init, + .t_focus_vcm = dw9718_t_focus_vcm, + .t_focus_abs = dw9718_t_focus_abs, + .t_focus_rel = dw9718_t_focus_rel, + .q_focus_status = dw9718_q_focus_status, + .q_focus_abs = dw9718_q_focus_abs, + .t_vcm_slew = dw9718_t_vcm_slew, + .t_vcm_timing = dw9718_t_vcm_timing, + }, + [OV8858_ID_DEFAULT] = { + .power_up = NULL, + .power_down = NULL, + }, +}; + + +#define OV8858_RES_WIDTH_MAX 3280 +#define OV8858_RES_HEIGHT_MAX 2464 + +static struct ov8858_reg ov8858_BasicSettings[] = { + {OV8858_8BIT, 0x0103, 0x01}, /* software_reset */ + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + /* PLL settings */ + {OV8858_8BIT, 0x0300, 0x05}, /* pll1_pre_div = /4 */ + {OV8858_8BIT, 0x0302, 0xAF}, /* pll1_multiplier = 175 */ + {OV8858_8BIT, 0x0303, 0x00}, /* pll1_divm = /(1 + 0) */ + {OV8858_8BIT, 0x0304, 0x03}, /* pll1_div_mipi = /8 */ + {OV8858_8BIT, 0x030B, 0x02}, /* pll2_pre_div = /2 */ + {OV8858_8BIT, 0x030D, 0x4E}, /* pll2_r_divp = 78 */ + {OV8858_8BIT, 0x030E, 0x00}, /* pll2_r_divs = /1 */ + {OV8858_8BIT, 0x030F, 0x04}, /* pll2_r_divsp = /(1 + 4) */ + /* pll2_pre_div0 = /1, pll2_r_divdac = /(1 + 1) */ + {OV8858_8BIT, 0x0312, 0x01}, + {OV8858_8BIT, 0x031E, 0x0C}, /* pll1_no_lat = 1, mipi_bitsel_man = 0 */ + + /* PAD OEN2, VSYNC out enable=0x80, disable=0x00 */ + {OV8858_8BIT, 0x3002, 0x80}, + /* PAD OUT2, VSYNC pulse direction low-to-high = 1 */ + {OV8858_8BIT, 0x3007, 0x01}, + /* PAD SEL2, VSYNC out value = 0 */ + {OV8858_8BIT, 0x300D, 0x00}, + /* PAD OUT2, VSYNC out select = 0 */ + {OV8858_8BIT, 0x3010, 0x00}, + + /* Npump clock div = /2, Ppump clock div = /4 */ + {OV8858_8BIT, 0x3015, 0x01}, + /* + * mipi_lane_mode = 1+3, mipi_lvds_sel = 1 = MIPI enable, + * r_phy_pd_mipi_man = 0, lane_dis_option = 0 + */ + {OV8858_8BIT, 0x3018, 0x72}, + /* Clock switch output = normal, pclk_div = /1 */ + {OV8858_8BIT, 0x3020, 0x93}, + /* + * lvds_mode_o = 0, clock lane disable when pd_mipi = 0, + * pd_mipi enable when rst_sync = 1 + */ + {OV8858_8BIT, 0x3022, 0x01}, + {OV8858_8BIT, 0x3031, 0x0A}, /* mipi_bit_sel = 10 */ + {OV8858_8BIT, 0x3034, 0x00}, /* Unknown */ + /* sclk_div = /1, sclk_pre_div = /1, chip debug = 1 */ + {OV8858_8BIT, 0x3106, 0x01}, + + {OV8858_8BIT, 0x3305, 0xF1}, /* Unknown */ + {OV8858_8BIT, 0x3307, 0x04}, /* Unknown */ + {OV8858_8BIT, 0x3308, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3309, 0x28}, /* Unknown */ + {OV8858_8BIT, 0x330A, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x330B, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x330C, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x330D, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x330E, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x330F, 0x40}, /* Unknown */ + + {OV8858_8BIT, 0x3500, 0x00}, /* long exposure = 0x9A20 */ + {OV8858_8BIT, 0x3501, 0x9A}, /* long exposure = 0x9A20 */ + {OV8858_8BIT, 0x3502, 0x20}, /* long exposure = 0x9A20 */ + /* + * Digital fraction gain delay option = Delay 1 frame, + * Gain change delay option = Delay 1 frame, + * Gain delay option = Delay 1 frame, + * Gain manual as sensor gain = Input gain as real gain format, + * Exposure delay option (must be 0 = Delay 1 frame, + * Exposure change delay option (must be 0) = Delay 1 frame + */ + {OV8858_8BIT, 0x3503, 0x00}, + {OV8858_8BIT, 0x3505, 0x80}, /* gain conversation option */ + /* + * [10:7] are integer gain, [6:0] are fraction gain. For example: + * 0x80 is 1x gain, 0x100 is 2x gain, 0x1C0 is 3.5x gain + */ + {OV8858_8BIT, 0x3508, 0x02}, /* long gain = 0x0200 */ + {OV8858_8BIT, 0x3509, 0x00}, /* long gain = 0x0200 */ + {OV8858_8BIT, 0x350C, 0x00}, /* short gain = 0x0080 */ + {OV8858_8BIT, 0x350D, 0x80}, /* short gain = 0x0080 */ + {OV8858_8BIT, 0x3510, 0x00}, /* short exposure = 0x000200 */ + {OV8858_8BIT, 0x3511, 0x02}, /* short exposure = 0x000200 */ + {OV8858_8BIT, 0x3512, 0x00}, /* short exposure = 0x000200 */ + + {OV8858_8BIT, 0x3600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3601, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3602, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3603, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3604, 0x22}, /* Unknown */ + {OV8858_8BIT, 0x3605, 0x30}, /* Unknown */ + {OV8858_8BIT, 0x3606, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3607, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x3608, 0x11}, /* Unknown */ + {OV8858_8BIT, 0x3609, 0x28}, /* Unknown */ + {OV8858_8BIT, 0x360A, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x360B, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x360C, 0xDC}, /* Unknown */ + {OV8858_8BIT, 0x360D, 0x40}, /* Unknown */ + {OV8858_8BIT, 0x360E, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x360F, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x3610, 0x07}, /* Unknown */ + {OV8858_8BIT, 0x3611, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x3612, 0x88}, /* Unknown */ + {OV8858_8BIT, 0x3613, 0x80}, /* Unknown */ + {OV8858_8BIT, 0x3614, 0x58}, /* Unknown */ + {OV8858_8BIT, 0x3615, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3616, 0x4A}, /* Unknown */ + {OV8858_8BIT, 0x3617, 0x90}, /* Unknown */ + {OV8858_8BIT, 0x3618, 0x56}, /* Unknown */ + {OV8858_8BIT, 0x3619, 0x70}, /* Unknown */ + {OV8858_8BIT, 0x361A, 0x99}, /* Unknown */ + {OV8858_8BIT, 0x361B, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x361C, 0x07}, /* Unknown */ + {OV8858_8BIT, 0x361D, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x361E, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x361F, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3633, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3634, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3635, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3636, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3638, 0xFF}, /* Unknown */ + {OV8858_8BIT, 0x3645, 0x13}, /* Unknown */ + {OV8858_8BIT, 0x3646, 0x83}, /* Unknown */ + {OV8858_8BIT, 0x364A, 0x07}, /* Unknown */ + + {OV8858_8BIT, 0x3700, 0x30}, /* Unknown */ + {OV8858_8BIT, 0x3701, 0x18}, /* Unknown */ + {OV8858_8BIT, 0x3702, 0x50}, /* Unknown */ + {OV8858_8BIT, 0x3703, 0x32}, /* Unknown */ + {OV8858_8BIT, 0x3704, 0x28}, /* Unknown */ + {OV8858_8BIT, 0x3705, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3706, 0x6A}, /* Unknown */ + {OV8858_8BIT, 0x3707, 0x08}, /* Unknown */ + {OV8858_8BIT, 0x3708, 0x48}, /* Unknown */ + {OV8858_8BIT, 0x3709, 0x66}, /* Unknown */ + {OV8858_8BIT, 0x370A, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x370B, 0x6A}, /* Unknown */ + {OV8858_8BIT, 0x370C, 0x07}, /* Unknown */ + {OV8858_8BIT, 0x3712, 0x44}, /* Unknown */ + {OV8858_8BIT, 0x3714, 0x24}, /* Unknown */ + {OV8858_8BIT, 0x3718, 0x14}, /* Unknown */ + {OV8858_8BIT, 0x3719, 0x31}, /* Unknown */ + {OV8858_8BIT, 0x371E, 0x31}, /* Unknown */ + {OV8858_8BIT, 0x371F, 0x7F}, /* Unknown */ + {OV8858_8BIT, 0x3720, 0x0A}, /* Unknown */ + {OV8858_8BIT, 0x3721, 0x0A}, /* Unknown */ + {OV8858_8BIT, 0x3724, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3725, 0x02}, /* Unknown */ + {OV8858_8BIT, 0x3726, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3728, 0x0A}, /* Unknown */ + {OV8858_8BIT, 0x3729, 0x03}, /* Unknown */ + {OV8858_8BIT, 0x372A, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x372B, 0xA6}, /* Unknown */ + {OV8858_8BIT, 0x372C, 0xA6}, /* Unknown */ + {OV8858_8BIT, 0x372D, 0xA6}, /* Unknown */ + {OV8858_8BIT, 0x372E, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x372F, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x3730, 0x02}, /* Unknown */ + {OV8858_8BIT, 0x3731, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3732, 0x28}, /* Unknown */ + {OV8858_8BIT, 0x3733, 0x10}, /* Unknown */ + {OV8858_8BIT, 0x3734, 0x40}, /* Unknown */ + {OV8858_8BIT, 0x3736, 0x30}, /* Unknown */ + {OV8858_8BIT, 0x373A, 0x0A}, /* Unknown */ + {OV8858_8BIT, 0x373B, 0x0B}, /* Unknown */ + {OV8858_8BIT, 0x373C, 0x14}, /* Unknown */ + {OV8858_8BIT, 0x373E, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3755, 0x10}, /* Unknown */ + {OV8858_8BIT, 0x3758, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3759, 0x4C}, /* Unknown */ + {OV8858_8BIT, 0x375A, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x375B, 0x26}, /* Unknown */ + {OV8858_8BIT, 0x375C, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x375D, 0x04}, /* Unknown */ + {OV8858_8BIT, 0x375E, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x375F, 0x28}, /* Unknown */ + {OV8858_8BIT, 0x3760, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3761, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3762, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3763, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3766, 0xFF}, /* Unknown */ + {OV8858_8BIT, 0x3768, 0x22}, /* Unknown */ + {OV8858_8BIT, 0x3769, 0x44}, /* Unknown */ + {OV8858_8BIT, 0x376A, 0x44}, /* Unknown */ + {OV8858_8BIT, 0x376B, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x376F, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3772, 0x46}, /* Unknown */ + {OV8858_8BIT, 0x3773, 0x04}, /* Unknown */ + {OV8858_8BIT, 0x3774, 0x2C}, /* Unknown */ + {OV8858_8BIT, 0x3775, 0x13}, /* Unknown */ + {OV8858_8BIT, 0x3776, 0x08}, /* Unknown */ + {OV8858_8BIT, 0x3777, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x37A0, 0x88}, /* Unknown */ + {OV8858_8BIT, 0x37A1, 0x7A}, /* Unknown */ + {OV8858_8BIT, 0x37A2, 0x7A}, /* Unknown */ + {OV8858_8BIT, 0x37A3, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37A4, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37A5, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37A6, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37A7, 0x88}, /* Unknown */ + {OV8858_8BIT, 0x37A8, 0x98}, /* Unknown */ + {OV8858_8BIT, 0x37A9, 0x98}, /* Unknown */ + {OV8858_8BIT, 0x37AA, 0x88}, /* Unknown */ + {OV8858_8BIT, 0x37AB, 0x5C}, /* Unknown */ + {OV8858_8BIT, 0x37AC, 0x5C}, /* Unknown */ + {OV8858_8BIT, 0x37AD, 0x55}, /* Unknown */ + {OV8858_8BIT, 0x37AE, 0x19}, /* Unknown */ + {OV8858_8BIT, 0x37AF, 0x19}, /* Unknown */ + {OV8858_8BIT, 0x37B0, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B1, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B2, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B3, 0x84}, /* Unknown */ + {OV8858_8BIT, 0x37B4, 0x84}, /* Unknown */ + {OV8858_8BIT, 0x37B5, 0x66}, /* Unknown */ + {OV8858_8BIT, 0x37B6, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B7, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B8, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B9, 0xFF}, /* Unknown */ + + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */ + {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high */ + {OV8858_8BIT, 0x3809, 0xC0}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x09}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x90}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ + {OV8858_8BIT, 0x3810, 0x00}, /* h_win offset high */ + {OV8858_8BIT, 0x3811, 0x04}, /* h_win offset low */ + {OV8858_8BIT, 0x3812, 0x00}, /* v_win offset high */ + {OV8858_8BIT, 0x3813, 0x02}, /* v_win offset low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3837, 0x18}, /* Unknown */ + {OV8858_8BIT, 0x3841, 0xFF}, /* AUTO_SIZE_CTRL */ + {OV8858_8BIT, 0x3846, 0x48}, /* Unknown */ + + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3D8C, 0x73}, /* OTP_SETTING_STT_ADDRESS */ + {OV8858_8BIT, 0x3D8D, 0xDE}, /* OTP_SETTING_STT_ADDRESS */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x3F0A, 0x80}, /* PSRAM control register */ + + {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ + {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ + {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ + {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ + {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ + {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ + {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ + {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ + {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ + {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4022, 0x0B}, /* Anchor left end = 0x0BC3 */ + {OV8858_8BIT, 0x4023, 0xC3}, /* Anchor left end = 0x0BC3 */ + {OV8858_8BIT, 0x4024, 0x0C}, /* Anchor right start = 0x0C36 */ + {OV8858_8BIT, 0x4025, 0x36}, /* Anchor right start = 0x0C36 */ + {OV8858_8BIT, 0x4026, 0x0C}, /* Anchor right end = 0x0C37 */ + {OV8858_8BIT, 0x4027, 0x37}, /* Anchor right end = 0x0C37 */ + {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ + {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ + {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ + {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ + {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ + {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ + {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */ + {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ + + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4300, 0xFF}, /* clip_max[11:4] = 0xFFF */ + {OV8858_8BIT, 0x4301, 0x00}, /* clip_min[11:4] = 0 */ + {OV8858_8BIT, 0x4302, 0x0F}, /* clip_min/max[3:0] */ + {OV8858_8BIT, 0x4307, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x4316, 0x00}, /* CTRL16 = default */ + {OV8858_8BIT, 0x4503, 0x18}, /* Unknown */ + {OV8858_8BIT, 0x4500, 0x38}, /* Unknown */ + {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ + /* wkup_dly = Mark1 wakeup delay/2^10 = 0x25 */ + {OV8858_8BIT, 0x4808, 0x25}, + {OV8858_8BIT, 0x4816, 0x52}, /* Embedded data type*/ + {OV8858_8BIT, 0x481F, 0x32}, /* clk_prepare_min = 0x32 */ + {OV8858_8BIT, 0x4825, 0x3A}, /* lpx_p_min = 0x3A */ + {OV8858_8BIT, 0x4826, 0x40}, /* hs_prepare_min = 0x40 */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_8BIT, 0x4850, 0x10}, /* LANE SEL01 */ + {OV8858_8BIT, 0x4851, 0x32}, /* LANE SEL02 */ + + {OV8858_8BIT, 0x4B00, 0x2A}, /* Unknown */ + {OV8858_8BIT, 0x4B0D, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4D00, 0x04}, /* TPM_CTRL_REG */ + {OV8858_8BIT, 0x4D01, 0x18}, /* TPM_CTRL_REG */ + {OV8858_8BIT, 0x4D02, 0xC3}, /* TPM_CTRL_REG */ + {OV8858_8BIT, 0x4D03, 0xFF}, /* TPM_CTRL_REG */ + {OV8858_8BIT, 0x4D04, 0xFF}, /* TPM_CTRL_REG */ + {OV8858_8BIT, 0x4D05, 0xFF}, /* TPM_CTRL_REG */ + + /* + * Lens correction (LENC) function enable = 0 + * Slave sensor AWB Gain function enable = 1 + * Slave sensor AWB Statistics function enable = 1 + * Master sensor AWB Gain function enable = 1 + * Master sensor AWB Statistics function enable = 1 + * Black DPC function enable = 1 + * White DPC function enable =1 + */ + {OV8858_8BIT, 0x5000, 0x7E}, + {OV8858_8BIT, 0x5001, 0x01}, /* BLC function enable = 1 */ + /* + * Horizontal scale function enable = 0 + * WBMATCH bypass mode = Select slave sensor's gain + * WBMATCH function enable = 0 + * Master MWB gain support RGBC = 0 + * OTP_DPC function enable = 1 + * Manual mode of VarioPixel function enable = 0 + * Manual enable of VarioPixel function enable = 0 + * Use VSYNC to latch ISP modules's function enable signals = 0 + */ + {OV8858_8BIT, 0x5002, 0x08}, + /* + * Bypass all ISP modules after BLC module = 0 + * DPC_DBC buffer control enable = 1 + * WBMATCH VSYNC selection = Select master sensor's VSYNC fall + * Select master AWB gain to embed line = AWB gain before manual mode + * Enable BLC's input flip_i signal = 0 + */ + {OV8858_8BIT, 0x5003, 0x20}, + {OV8858_8BIT, 0x5041, 0x1D}, /* ISP CTRL41 - embedded data=on */ + {OV8858_8BIT, 0x5046, 0x12}, /* ISP CTRL46 = default */ + /* + * Tail enable = 1 + * Saturate cross cluster enable = 1 + * Remove cross cluster enable = 1 + * Enable to remove connected defect pixels in same channel = 1 + * Enable to remove connected defect pixels in different channel = 1 + * Smooth enable, use average G for recovery = 1 + * Black/white sensor mode enable = 0 + * Manual mode enable = 0 + */ + {OV8858_8BIT, 0x5780, 0xFC}, + {OV8858_8BIT, 0x5784, 0x0C}, /* DPC CTRL04 */ + {OV8858_8BIT, 0x5787, 0x40}, /* DPC CTRL07 */ + {OV8858_8BIT, 0x5788, 0x08}, /* DPC CTRL08 */ + {OV8858_8BIT, 0x578A, 0x02}, /* DPC CTRL0A */ + {OV8858_8BIT, 0x578B, 0x01}, /* DPC CTRL0B */ + {OV8858_8BIT, 0x578C, 0x01}, /* DPC CTRL0C */ + {OV8858_8BIT, 0x578E, 0x02}, /* DPC CTRL0E */ + {OV8858_8BIT, 0x578F, 0x01}, /* DPC CTRL0F */ + {OV8858_8BIT, 0x5790, 0x01}, /* DPC CTRL10 */ + {OV8858_8BIT, 0x5901, 0x00}, /* VAP CTRL01 = default */ + /* WINC CTRL08 = embedded data in 1st line*/ + {OV8858_8BIT, 0x5A08, 0x00}, + {OV8858_8BIT, 0x5B00, 0x02}, /* OTP CTRL00 */ + {OV8858_8BIT, 0x5B01, 0x10}, /* OTP CTRL01 */ + {OV8858_8BIT, 0x5B02, 0x03}, /* OTP CTRL02 */ + {OV8858_8BIT, 0x5B03, 0xCF}, /* OTP CTRL03 */ + {OV8858_8BIT, 0x5B05, 0x6C}, /* OTP CTRL05 = default */ + {OV8858_8BIT, 0x5E00, 0x00}, /* PRE CTRL00 = default */ + {OV8858_8BIT, 0x5E01, 0x41}, /* PRE_CTRL01 = default */ + + {OV8858_TOK_TERM, 0, 0} +}; + +/*****************************STILL********************************/ + +static const struct ov8858_reg ov8858_8M[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */ + {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low 3283 */ + {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3280 x 2464 */ + {OV8858_8BIT, 0x3809, 0xD0}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x09}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0xa0}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ + {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ + {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ + {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ + {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ + {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ + {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ + {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ + {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ + {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4022, 0x0B}, /* Anchor left end = 0x0BC3 */ + {OV8858_8BIT, 0x4023, 0xC3}, /* Anchor left end = 0x0BC3 */ + {OV8858_8BIT, 0x4024, 0x0C}, /* Anchor right start = 0x0C36 */ + {OV8858_8BIT, 0x4025, 0x36}, /* Anchor right start = 0x0C36 */ + {OV8858_8BIT, 0x4026, 0x0C}, /* Anchor right end = 0x0C37 */ + {OV8858_8BIT, 0x4027, 0x37}, /* Anchor right end = 0x0C37 */ + {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ + {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ + {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ + {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ + {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ + {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ + {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */ + {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_3276x1848[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x10}, /* h_crop_start low 0c->10*/ + {OV8858_8BIT, 0x3802, 0x01}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x42}, /* v_crop_start low 3e->42*/ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x08}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0x71}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3276 x 1848 */ + {OV8858_8BIT, 0x3809, 0xCC}, /* h_output_size low d0->cc*/ + {OV8858_8BIT, 0x380A, 0x07}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x38}, /* v_output_size low 3c->38*/ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ + {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ + {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ + {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ + {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ + {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ + {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ + {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ + {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ + {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4022, 0x0B}, /* Anchor left end = 0x0BC3 */ + {OV8858_8BIT, 0x4023, 0xC3}, /* Anchor left end = 0x0BC3 */ + {OV8858_8BIT, 0x4024, 0x0C}, /* Anchor right start = 0x0C36 */ + {OV8858_8BIT, 0x4025, 0x36}, /* Anchor right start = 0x0C36 */ + {OV8858_8BIT, 0x4026, 0x0C}, /* Anchor right end = 0x0C37 */ + {OV8858_8BIT, 0x4027, 0x37}, /* Anchor right end = 0x0C37 */ + {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ + {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ + {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ + {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ + {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ + {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ + {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */ + {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_6M[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */ + {OV8858_8BIT, 0x3802, 0x01}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x3E}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x08}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0x71}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3280 x 1852 */ + {OV8858_8BIT, 0x3809, 0xD0}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x07}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x3C}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ + {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ + {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ + {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ + {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ + {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ + {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ + {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ + {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ + {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4022, 0x0B}, /* Anchor left end = 0x0BC3 */ + {OV8858_8BIT, 0x4023, 0xC3}, /* Anchor left end = 0x0BC3 */ + {OV8858_8BIT, 0x4024, 0x0C}, /* Anchor right start = 0x0C36 */ + {OV8858_8BIT, 0x4025, 0x36}, /* Anchor right start = 0x0C36 */ + {OV8858_8BIT, 0x4026, 0x0C}, /* Anchor right end = 0x0C37 */ + {OV8858_8BIT, 0x4027, 0x37}, /* Anchor right end = 0x0C37 */ + {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ + {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ + {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ + {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ + {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ + {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ + {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */ + {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_1080P_60[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x17}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x02}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x26}, /* h_crop_start low */ + {OV8858_8BIT, 0x3802, 0x02}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x8C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0A}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0x9D}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x07}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0x0A}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x07}, /* h_output_size high*/ + {OV8858_8BIT, 0x3809, 0x90}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x04}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0xEC}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ + {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ + {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ + {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ + {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ + {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ + {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ + {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ + {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ + {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4022, 0x07}, /* Anchor left end = 0x072D */ + {OV8858_8BIT, 0x4023, 0x2D}, /* Anchor left end = 0x072D */ + {OV8858_8BIT, 0x4024, 0x07}, /* Anchor right start = 0x079E */ + {OV8858_8BIT, 0x4025, 0x9E}, /* Anchor right start = 0x079E */ + {OV8858_8BIT, 0x4026, 0x07}, /* Anchor right end = 0x079F */ + {OV8858_8BIT, 0x4027, 0x9F}, /* Anchor right end = 0x079F */ + {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ + {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ + {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ + {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ + {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ + {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ + {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */ + {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0xef}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x16}, /* pclk_period = 0x16 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_1080P_30[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x17}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x02}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x26}, /* h_crop_start low */ + {OV8858_8BIT, 0x3802, 0x02}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x8C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0A}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0x9D}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x07}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0x0A}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x07}, /* h_output_size high*/ + {OV8858_8BIT, 0x3809, 0x90}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ + {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ + {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ + {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ + {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ + {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ + {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ + {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ + {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ + {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4022, 0x07}, /* Anchor left end = 0x072D */ + {OV8858_8BIT, 0x4023, 0x2D}, /* Anchor left end = 0x072D */ + {OV8858_8BIT, 0x4024, 0x07}, /* Anchor right start = 0x079E */ + {OV8858_8BIT, 0x4025, 0x9E}, /* Anchor right start = 0x079E */ + {OV8858_8BIT, 0x4026, 0x07}, /* Anchor right end = 0x079F */ + {OV8858_8BIT, 0x4027, 0x9F}, /* Anchor right end = 0x079F */ + {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ + {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ + {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ + {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ + {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ + {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ + {OV8858_8BIT, 0x402E, 0x0C}, /* Bottom black line start = 12 */ + {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0xef}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x16}, /* pclk_period = 0x16 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_1640x1232[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */ + {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high 3283 */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 1232 */ + {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0xD0}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x67}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */ + {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ + {OV8858_8BIT, 0x4001, 0x10}, /* BLC CTRL01 */ + {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ + {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ + {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ + {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ + {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ + {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ + {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ + {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4022, 0x04}, /* Anchor left end = 0x04B9 */ + {OV8858_8BIT, 0x4023, 0xB9}, /* Anchor left end = 0x04B9 */ + {OV8858_8BIT, 0x4024, 0x05}, /* Anchor right start = 0x052A */ + {OV8858_8BIT, 0x4025, 0x2A}, /* Anchor right start = 0x052A */ + {OV8858_8BIT, 0x4026, 0x05}, /* Anchor right end = 0x052B */ + {OV8858_8BIT, 0x4027, 0x2B}, /* Anchor right end = 0x052B */ + {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ + {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ + {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ + {OV8858_8BIT, 0x402B, 0x04}, /* Top black line number = 8 */ + {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ + {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ + {OV8858_8BIT, 0x402E, 0x08}, /* Bottom black line start = 8 */ + {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_1640x1096[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */ + {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high 3283 */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 1096 */ + {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x67}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */ + {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ + {OV8858_8BIT, 0x4001, 0x10}, /* BLC CTRL01 */ + {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ + {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ + {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ + {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ + {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ + {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ + {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ + {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4022, 0x04}, /* Anchor left end = 0x04B9 */ + {OV8858_8BIT, 0x4023, 0xB9}, /* Anchor left end = 0x04B9 */ + {OV8858_8BIT, 0x4024, 0x05}, /* Anchor right start = 0x052A */ + {OV8858_8BIT, 0x4025, 0x2A}, /* Anchor right start = 0x052A */ + {OV8858_8BIT, 0x4026, 0x05}, /* Anchor right end = 0x052B */ + {OV8858_8BIT, 0x4027, 0x2B}, /* Anchor right end = 0x052B */ + {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ + {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ + {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ + {OV8858_8BIT, 0x402B, 0x04}, /* Top black line number = 8 */ + {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ + {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ + {OV8858_8BIT, 0x402E, 0x08}, /* Bottom black line start = 8 */ + {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + + +static const struct ov8858_reg ov8858_1640x926[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */ + {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 926 */ + {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x03}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x9E}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x67}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */ + {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ + {OV8858_8BIT, 0x4001, 0x10}, /* BLC CTRL01 */ + {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ + {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ + {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ + {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ + {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ + {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ + {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ + {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4022, 0x04}, /* Anchor left end = 0x04B9 */ + {OV8858_8BIT, 0x4023, 0xB9}, /* Anchor left end = 0x04B9 */ + {OV8858_8BIT, 0x4024, 0x05}, /* Anchor right start = 0x052A */ + {OV8858_8BIT, 0x4025, 0x2A}, /* Anchor right start = 0x052A */ + {OV8858_8BIT, 0x4026, 0x05}, /* Anchor right end = 0x052B */ + {OV8858_8BIT, 0x4027, 0x2B}, /* Anchor right end = 0x052B */ + {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ + {OV8858_8BIT, 0x4029, 0x02}, /* Top zero line number = 2 */ + {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ + {OV8858_8BIT, 0x402B, 0x04}, /* Top black line number = 8 */ + {OV8858_8BIT, 0x402C, 0x02}, /* Bottom zero start line = 2 */ + {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ + {OV8858_8BIT, 0x402E, 0x08}, /* Bottom black line start = 8 */ + {OV8858_8BIT, 0x402F, 0x02}, /* Bottom black line number = 2 */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static struct ov8858_resolution ov8858_res_preview[] = { + { + .desc = "ov8858_1640x926_PREVIEW", + .width = 1640, + .height = 926, + .used = 0, + .regs = ov8858_1640x926, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_1640x1232_PREVIEW", + .width = 1640, + .height = 1232, + .used = 0, + .regs = ov8858_1640x1232, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_3276x1848_PREVIEW", + .width = 3276, + .height = 1848, + .used = 0, + .regs = ov8858_3276x1848, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_8M_PREVIEW", + .width = 3280, + .height = 2464, + .used = 0, + .regs = ov8858_8M, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, +}; + +static struct ov8858_resolution ov8858_res_still[] = { + { + .desc = "ov8858_1640x1232_STILL", + .width = 1640, + .height = 1232, + .used = 0, + .regs = ov8858_1640x1232, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_1640x926_STILL", + .width = 1640, + .height = 926, + .used = 0, + .regs = ov8858_1640x926, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_3276X1848_STILL", + .width = 3276, + .height = 1848, + .used = 0, + .regs = ov8858_3276x1848, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_8M_STILL", + .width = 3280, + .height = 2464, + .used = 0, + .regs = ov8858_8M, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + /* Pixel clock: 149.76MHZ */ + .fps = 10, + .pixels_per_line = 3880, + .lines_per_frame = 3859, + }, + { + } + }, + }, +}; + +static struct ov8858_resolution ov8858_res_video[] = { + { + .desc = "ov8858_1640x926_VIDEO", + .width = 1640, + .height = 926, + .used = 0, + .regs = ov8858_1640x926, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_1640x1232_VIDEO", + .width = 1640, + .height = 1232, + .used = 0, + .regs = ov8858_1640x1232, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_1640x1096_VIDEO", + .width = 1640, + .height = 1096, + .used = 0, + .regs = ov8858_1640x1096, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_6M_VIDEO", + .width = 3280, + .height = 1852, + .used = 0, + .regs = ov8858_6M, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_8M_VIDEO", + .width = 3280, + .height = 2464, + .used = 0, + .regs = ov8858_8M, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, +}; + +#endif /* __OV8858_H__ */ diff --git a/drivers/staging/media/atomisp/i2c/ov8858_btns.h b/drivers/staging/media/atomisp/i2c/ov8858_btns.h new file mode 100644 index 0000000000000000000000000000000000000000..c0cd47698fe4a6cb67264243771f8fc9ef53ba23 --- /dev/null +++ b/drivers/staging/media/atomisp/i2c/ov8858_btns.h @@ -0,0 +1,1284 @@ +/* + * Support for the Omnivision OV8858 camera sensor. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __OV8858_H__ +#define __OV8858_H__ +#include +#include + +#define I2C_MSG_LENGTH 0x2 + +/* + * This should be added into include/linux/videodev2.h + * NOTE: This is most likely not used anywhere. + */ +#define V4L2_IDENT_OV8858 V4L2_IDENT_UNKNOWN + +/* + * Indexes for VCM driver lists + */ +#define OV8858_ID_DEFAULT 0 +#define OV8858_SUNNY 1 + +#define OV8858_OTP_START_ADDR 0x7010 +#define OV8858_OTP_END_ADDR 0x7186 + +/* + * ov8858 System control registers + */ + +#define OV8858_OTP_LOAD_CTRL 0x3D81 +#define OV8858_OTP_MODE_CTRL 0x3D84 +#define OV8858_OTP_START_ADDR_REG 0x3D88 +#define OV8858_OTP_END_ADDR_REG 0x3D8A +#define OV8858_OTP_ISP_CTRL2 0x5002 + +#define OV8858_OTP_MODE_MANUAL BIT(6) +#define OV8858_OTP_MODE_PROGRAM_DISABLE BIT(7) +#define OV8858_OTP_LOAD_ENABLE BIT(0) +#define OV8858_OTP_DPC_ENABLE BIT(3) + +#define OV8858_PLL1_PREDIV0 0x030A +#define OV8858_PLL1_PREDIV 0x0300 +#define OV8858_PLL1_MULTIPLIER 0x0301 +#define OV8858_PLL1_SYS_PRE_DIV 0x0305 +#define OV8858_PLL1_SYS_DIVIDER 0x0306 + +#define OV8858_PLL1_PREDIV0_MASK BIT(0) +#define OV8858_PLL1_PREDIV_MASK (BIT(0) | BIT(1) | BIT(2)) +#define OV8858_PLL1_MULTIPLIER_MASK 0x01FF +#define OV8858_PLL1_SYS_PRE_DIV_MASK (BIT(0) | BIT(1)) +#define OV8858_PLL1_SYS_DIVIDER_MASK BIT(0) + +#define OV8858_PLL2_PREDIV0 0x0312 +#define OV8858_PLL2_PREDIV 0x030B +#define OV8858_PLL2_MULTIPLIER 0x030C +#define OV8858_PLL2_DAC_DIVIDER 0x0312 +#define OV8858_PLL2_SYS_PRE_DIV 0x030F +#define OV8858_PLL2_SYS_DIVIDER 0x030E + +#define OV8858_PLL2_PREDIV0_MASK BIT(4) +#define OV8858_PLL2_PREDIV_MASK (BIT(0) | BIT(1) | BIT(2)) +#define OV8858_PLL2_MULTIPLIER_MASK 0x01FF +#define OV8858_PLL2_DAC_DIVIDER_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define OV8858_PLL2_SYS_PRE_DIV_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(3)) +#define OV8858_PLL2_SYS_DIVIDER_MASK (BIT(0) | BIT(1) | BIT(2)) + +#define OV8858_PLL_SCLKSEL1 0x3032 +#define OV8858_PLL_SCLKSEL2 0x3033 +#define OV8858_SRB_HOST_INPUT_DIS 0x3106 + +#define OV8858_PLL_SCLKSEL1_MASK BIT(7) +#define OV8858_PLL_SCLKSEL2_MASK BIT(1) + +#define OV8858_SYS_PRE_DIV_OFFSET 2 +#define OV8858_SYS_PRE_DIV_MASK (BIT(2) | BIT(3)) +#define OV8858_SCLK_PDIV_OFFSET 4 +#define OV8858_SCLK_PDIV_MASK (BIT(4) | BIT(5) | BIT(6) | BIT(7)) + +#define OV8858_TIMING_HTS 0x380C +#define OV8858_TIMING_VTS 0x380E + +#define OV8858_HORIZONTAL_START_H 0x3800 +#define OV8858_VERTICAL_START_H 0x3802 +#define OV8858_HORIZONTAL_END_H 0x3804 +#define OV8858_VERTICAL_END_H 0x3806 +#define OV8858_HORIZONTAL_OUTPUT_SIZE_H 0x3808 +#define OV8858_VERTICAL_OUTPUT_SIZE_H 0x380A + +#define OV8858_GROUP_ACCESS 0x3208 +#define OV8858_GROUP_ZERO 0x00 +#define OV8858_GROUP_ACCESS_HOLD_START 0x00 +#define OV8858_GROUP_ACCESS_HOLD_END 0x10 +#define OV8858_GROUP_ACCESS_DELAY_LAUNCH 0xA0 +#define OV8858_GROUP_ACCESS_QUICK_LAUNCH 0xE0 + +#define OV_SUBDEV_PREFIX "ov" +#define OV_ID_DEFAULT 0x0000 +#define OV8858_NAME "ov8858" +#define OV8858_CHIP_ID 0x8858 + +#define OV8858_LONG_EXPO 0x3500 +#define OV8858_LONG_GAIN 0x3508 +#define OV8858_LONG_DIGI_GAIN 0x350A +#define OV8858_SHORT_GAIN 0x350C +#define OV8858_SHORT_DIGI_GAIN 0x350E + +#define OV8858_FORMAT1 0x3820 +#define OV8858_FORMAT2 0x3821 + +#define OV8858_FLIP_ENABLE 0x06 + +#define OV8858_MWB_RED_GAIN_H 0x5032 +#define OV8858_MWB_GREEN_GAIN_H 0x5034 +#define OV8858_MWB_BLUE_GAIN_H 0x5036 +#define OV8858_MWB_GAIN_MAX 0x0FFF + +#define OV8858_CHIP_ID_HIGH 0x300B +#define OV8858_CHIP_ID_LOW 0x300C +#define OV8858_STREAM_MODE 0x0100 + +#define OV8858_FOCAL_LENGTH_NUM 294 /* 2.94mm */ +#define OV8858_FOCAL_LENGTH_DEM 100 +#define OV8858_F_NUMBER_DEFAULT_NUM 24 /* 2.4 */ +#define OV8858_F_NUMBER_DEM 10 + +#define OV8858_H_INC_ODD 0x3814 +#define OV8858_H_INC_EVEN 0x3815 +#define OV8858_V_INC_ODD 0x382A +#define OV8858_V_INC_EVEN 0x382B + +#define OV8858_READ_MODE_BINNING_ON 0x0400 /* ToDo: Check this */ +#define OV8858_READ_MODE_BINNING_OFF 0x00 /* ToDo: Check this */ +#define OV8858_BIN_FACTOR_MAX 2 +#define OV8858_INTEGRATION_TIME_MARGIN 14 + +#define OV8858_MAX_VTS_VALUE 0xFFFF +#define OV8858_MAX_EXPOSURE_VALUE \ + (OV8858_MAX_VTS_VALUE - OV8858_INTEGRATION_TIME_MARGIN) +#define OV8858_MAX_GAIN_VALUE 0x07FF + +#define OV8858_MAX_FOCUS_POS 1023 + +#define OV8858_TEST_PATTERN_REG 0x5E00 + +struct ov8858_vcm { + int (*power_up)(struct v4l2_subdev *sd); + int (*power_down)(struct v4l2_subdev *sd); + int (*init)(struct v4l2_subdev *sd); + int (*t_focus_vcm)(struct v4l2_subdev *sd, u16 val); + int (*t_focus_abs)(struct v4l2_subdev *sd, s32 value); + int (*t_focus_rel)(struct v4l2_subdev *sd, s32 value); + int (*q_focus_status)(struct v4l2_subdev *sd, s32 *value); + int (*q_focus_abs)(struct v4l2_subdev *sd, s32 *value); + int (*t_vcm_slew)(struct v4l2_subdev *sd, s32 value); + int (*t_vcm_timing)(struct v4l2_subdev *sd, s32 value); +}; + +/* + * Defines for register writes and register array processing + * */ +#define OV8858_BYTE_MAX 32 +#define OV8858_SHORT_MAX 16 +#define OV8858_TOK_MASK 0xFFF0 + +#define MAX_FPS_OPTIONS_SUPPORTED 3 + +#define OV8858_DEPTH_COMP_CONST 2200 +#define OV8858_DEPTH_VTS_CONST 2573 + +enum ov8858_tok_type { + OV8858_8BIT = 0x0001, + OV8858_16BIT = 0x0002, + OV8858_TOK_TERM = 0xF000, /* terminating token for reg list */ + OV8858_TOK_DELAY = 0xFE00 /* delay token for reg list */ +}; + +/* + * If register address or register width is not 32 bit width, + * user needs to convert it manually + */ +struct s_register_setting { + u32 reg; + u32 val; +}; + +/** + * struct ov8858_reg - MI sensor register format + * @type: type of the register + * @reg: 16-bit offset to register + * @val: 8/16/32-bit register value + * + * Define a structure for sensor register initialization values + */ +struct ov8858_reg { + enum ov8858_tok_type type; + u16 sreg; + u32 val; /* @set value for read/mod/write, @mask */ +}; + +struct ov8858_fps_setting { + int fps; + unsigned short pixels_per_line; + unsigned short lines_per_frame; + const struct ov8858_reg *regs; /* regs that the fps setting needs */ +}; + +struct ov8858_resolution { + u8 *desc; + const struct ov8858_reg *regs; + int res; + int width; + int height; + bool used; + u8 bin_factor_x; + u8 bin_factor_y; + unsigned short skip_frames; + const struct ov8858_fps_setting fps_options[MAX_FPS_OPTIONS_SUPPORTED]; +}; + +/* + * ov8858 device structure + * */ +struct ov8858_device { + struct v4l2_subdev sd; + struct media_pad pad; + struct v4l2_mbus_framefmt format; + + struct camera_sensor_platform_data *platform_data; + struct mutex input_lock; /* serialize sensor's ioctl */ + int fmt_idx; + int streaming; + int vt_pix_clk_freq_mhz; + int fps_index; + u16 sensor_id; /* Sensor id from registers */ + u16 i2c_id; /* Sensor id from i2c_device_id */ + int exposure; + int gain; + u16 digital_gain; + u16 pixels_per_line; + u16 lines_per_frame; + u8 fps; + u8 *otp_data; + /* Prevent the framerate from being lowered in low light scenes. */ + int limit_exposure_flag; + bool hflip; + bool vflip; + + const struct ov8858_reg *regs; + struct ov8858_vcm *vcm_driver; + const struct ov8858_resolution *curr_res_table; + int entries_curr_table; + + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *run_mode; +}; + +#define to_ov8858_sensor(x) container_of(x, struct ov8858_device, sd) + +#define OV8858_MAX_WRITE_BUF_SIZE 32 +struct ov8858_write_buffer { + u16 addr; + u8 data[OV8858_MAX_WRITE_BUF_SIZE]; +}; + +struct ov8858_write_ctrl { + int index; + struct ov8858_write_buffer buffer; +}; + +static const struct ov8858_reg ov8858_soft_standby[] = { + {OV8858_8BIT, 0x0100, 0x00}, + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_streaming[] = { + {OV8858_8BIT, 0x0100, 0x01}, + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_param_hold[] = { + {OV8858_8BIT, OV8858_GROUP_ACCESS, + OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_HOLD_START}, + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_param_update[] = { + {OV8858_8BIT, OV8858_GROUP_ACCESS, + OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_HOLD_END}, + {OV8858_8BIT, OV8858_GROUP_ACCESS, + OV8858_GROUP_ZERO | OV8858_GROUP_ACCESS_DELAY_LAUNCH}, + {OV8858_TOK_TERM, 0, 0} +}; + +extern int dw9718_vcm_power_up(struct v4l2_subdev *sd); +extern int dw9718_vcm_power_down(struct v4l2_subdev *sd); +extern int dw9718_vcm_init(struct v4l2_subdev *sd); +extern int dw9718_t_focus_vcm(struct v4l2_subdev *sd, u16 val); +extern int dw9718_t_focus_abs(struct v4l2_subdev *sd, s32 value); +extern int dw9718_t_focus_rel(struct v4l2_subdev *sd, s32 value); +extern int dw9718_q_focus_status(struct v4l2_subdev *sd, s32 *value); +extern int dw9718_q_focus_abs(struct v4l2_subdev *sd, s32 *value); +extern int dw9718_t_vcm_slew(struct v4l2_subdev *sd, s32 value); +extern int dw9718_t_vcm_timing(struct v4l2_subdev *sd, s32 value); + +extern int vcm_power_up(struct v4l2_subdev *sd); +extern int vcm_power_down(struct v4l2_subdev *sd); + +static struct ov8858_vcm ov8858_vcms[] = { + [OV8858_SUNNY] = { + .power_up = dw9718_vcm_power_up, + .power_down = dw9718_vcm_power_down, + .init = dw9718_vcm_init, + .t_focus_vcm = dw9718_t_focus_vcm, + .t_focus_abs = dw9718_t_focus_abs, + .t_focus_rel = dw9718_t_focus_rel, + .q_focus_status = dw9718_q_focus_status, + .q_focus_abs = dw9718_q_focus_abs, + .t_vcm_slew = dw9718_t_vcm_slew, + .t_vcm_timing = dw9718_t_vcm_timing, + }, + [OV8858_ID_DEFAULT] = { + .power_up = NULL, + .power_down = NULL, + }, +}; + + +#define OV8858_RES_WIDTH_MAX 3280 +#define OV8858_RES_HEIGHT_MAX 2464 + +static struct ov8858_reg ov8858_BasicSettings[] = { + {OV8858_8BIT, 0x0103, 0x01}, /* software_reset */ + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + /* PLL settings */ + {OV8858_8BIT, 0x0300, 0x05}, /* pll1_pre_div = /4 */ + {OV8858_8BIT, 0x0302, 0xAF}, /* pll1_multiplier = 175 */ + {OV8858_8BIT, 0x0303, 0x00}, /* pll1_divm = /(1 + 0) */ + {OV8858_8BIT, 0x0304, 0x03}, /* pll1_div_mipi = /8 */ + {OV8858_8BIT, 0x030B, 0x02}, /* pll2_pre_div = /2 */ + {OV8858_8BIT, 0x030D, 0x4E}, /* pll2_r_divp = 78 */ + {OV8858_8BIT, 0x030E, 0x00}, /* pll2_r_divs = /1 */ + {OV8858_8BIT, 0x030F, 0x04}, /* pll2_r_divsp = /(1 + 4) */ + /* pll2_pre_div0 = /1, pll2_r_divdac = /(1 + 1) */ + {OV8858_8BIT, 0x0312, 0x01}, + {OV8858_8BIT, 0x031E, 0x0C}, /* pll1_no_lat = 1, mipi_bitsel_man = 0 */ + + /* PAD OEN2, VSYNC out enable=0x80, disable=0x00 */ + {OV8858_8BIT, 0x3002, 0x80}, + /* PAD OUT2, VSYNC pulse direction low-to-high = 1 */ + {OV8858_8BIT, 0x3007, 0x01}, + /* PAD SEL2, VSYNC out value = 0 */ + {OV8858_8BIT, 0x300D, 0x00}, + /* PAD OUT2, VSYNC out select = 0 */ + {OV8858_8BIT, 0x3010, 0x00}, + + /* Npump clock div = /2, Ppump clock div = /4 */ + {OV8858_8BIT, 0x3015, 0x01}, + /* + * mipi_lane_mode = 1+3, mipi_lvds_sel = 1 = MIPI enable, + * r_phy_pd_mipi_man = 0, lane_dis_option = 0 + */ + {OV8858_8BIT, 0x3018, 0x72}, + /* Clock switch output = normal, pclk_div = /1 */ + {OV8858_8BIT, 0x3020, 0x93}, + /* + * lvds_mode_o = 0, clock lane disable when pd_mipi = 0, + * pd_mipi enable when rst_sync = 1 + */ + {OV8858_8BIT, 0x3022, 0x01}, + {OV8858_8BIT, 0x3031, 0x0A}, /* mipi_bit_sel = 10 */ + {OV8858_8BIT, 0x3034, 0x00}, /* Unknown */ + /* sclk_div = /1, sclk_pre_div = /1, chip debug = 1 */ + {OV8858_8BIT, 0x3106, 0x01}, + + {OV8858_8BIT, 0x3305, 0xF1}, /* Unknown */ + {OV8858_8BIT, 0x3307, 0x04}, /* Unknown */ + {OV8858_8BIT, 0x3308, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3309, 0x28}, /* Unknown */ + {OV8858_8BIT, 0x330A, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x330B, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x330C, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x330D, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x330E, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x330F, 0x40}, /* Unknown */ + + {OV8858_8BIT, 0x3500, 0x00}, /* long exposure = 0x9A20 */ + {OV8858_8BIT, 0x3501, 0x9A}, /* long exposure = 0x9A20 */ + {OV8858_8BIT, 0x3502, 0x20}, /* long exposure = 0x9A20 */ + /* + * Digital fraction gain delay option = Delay 1 frame, + * Gain change delay option = Delay 1 frame, + * Gain delay option = Delay 1 frame, + * Gain manual as sensor gain = Input gain as real gain format, + * Exposure delay option (must be 0 = Delay 1 frame, + * Exposure change delay option (must be 0) = Delay 1 frame + */ + {OV8858_8BIT, 0x3503, 0x00}, + {OV8858_8BIT, 0x3505, 0x80}, /* gain conversation option */ + /* + * [10:7] are integer gain, [6:0] are fraction gain. For example: + * 0x80 is 1x gain, 0x100 is 2x gain, 0x1C0 is 3.5x gain + */ + {OV8858_8BIT, 0x3508, 0x02}, /* long gain = 0x0200 */ + {OV8858_8BIT, 0x3509, 0x00}, /* long gain = 0x0200 */ + {OV8858_8BIT, 0x350C, 0x00}, /* short gain = 0x0080 */ + {OV8858_8BIT, 0x350D, 0x80}, /* short gain = 0x0080 */ + {OV8858_8BIT, 0x3510, 0x00}, /* short exposure = 0x000200 */ + {OV8858_8BIT, 0x3511, 0x02}, /* short exposure = 0x000200 */ + {OV8858_8BIT, 0x3512, 0x00}, /* short exposure = 0x000200 */ + + {OV8858_8BIT, 0x3600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3601, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3602, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3603, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3604, 0x22}, /* Unknown */ + {OV8858_8BIT, 0x3605, 0x30}, /* Unknown */ + {OV8858_8BIT, 0x3606, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3607, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x3608, 0x11}, /* Unknown */ + {OV8858_8BIT, 0x3609, 0x28}, /* Unknown */ + {OV8858_8BIT, 0x360A, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x360B, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x360C, 0xDC}, /* Unknown */ + {OV8858_8BIT, 0x360D, 0x40}, /* Unknown */ + {OV8858_8BIT, 0x360E, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x360F, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x3610, 0x07}, /* Unknown */ + {OV8858_8BIT, 0x3611, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x3612, 0x88}, /* Unknown */ + {OV8858_8BIT, 0x3613, 0x80}, /* Unknown */ + {OV8858_8BIT, 0x3614, 0x58}, /* Unknown */ + {OV8858_8BIT, 0x3615, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3616, 0x4A}, /* Unknown */ + {OV8858_8BIT, 0x3617, 0x90}, /* Unknown */ + {OV8858_8BIT, 0x3618, 0x56}, /* Unknown */ + {OV8858_8BIT, 0x3619, 0x70}, /* Unknown */ + {OV8858_8BIT, 0x361A, 0x99}, /* Unknown */ + {OV8858_8BIT, 0x361B, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x361C, 0x07}, /* Unknown */ + {OV8858_8BIT, 0x361D, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x361E, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x361F, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3633, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3634, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3635, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3636, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3638, 0xFF}, /* Unknown */ + {OV8858_8BIT, 0x3645, 0x13}, /* Unknown */ + {OV8858_8BIT, 0x3646, 0x83}, /* Unknown */ + {OV8858_8BIT, 0x364A, 0x07}, /* Unknown */ + + {OV8858_8BIT, 0x3700, 0x30}, /* Unknown */ + {OV8858_8BIT, 0x3701, 0x18}, /* Unknown */ + {OV8858_8BIT, 0x3702, 0x50}, /* Unknown */ + {OV8858_8BIT, 0x3703, 0x32}, /* Unknown */ + {OV8858_8BIT, 0x3704, 0x28}, /* Unknown */ + {OV8858_8BIT, 0x3705, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3706, 0x6A}, /* Unknown */ + {OV8858_8BIT, 0x3707, 0x08}, /* Unknown */ + {OV8858_8BIT, 0x3708, 0x48}, /* Unknown */ + {OV8858_8BIT, 0x3709, 0x66}, /* Unknown */ + {OV8858_8BIT, 0x370A, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x370B, 0x6A}, /* Unknown */ + {OV8858_8BIT, 0x370C, 0x07}, /* Unknown */ + {OV8858_8BIT, 0x3712, 0x44}, /* Unknown */ + {OV8858_8BIT, 0x3714, 0x24}, /* Unknown */ + {OV8858_8BIT, 0x3718, 0x14}, /* Unknown */ + {OV8858_8BIT, 0x3719, 0x31}, /* Unknown */ + {OV8858_8BIT, 0x371E, 0x31}, /* Unknown */ + {OV8858_8BIT, 0x371F, 0x7F}, /* Unknown */ + {OV8858_8BIT, 0x3720, 0x0A}, /* Unknown */ + {OV8858_8BIT, 0x3721, 0x0A}, /* Unknown */ + {OV8858_8BIT, 0x3724, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3725, 0x02}, /* Unknown */ + {OV8858_8BIT, 0x3726, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3728, 0x0A}, /* Unknown */ + {OV8858_8BIT, 0x3729, 0x03}, /* Unknown */ + {OV8858_8BIT, 0x372A, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x372B, 0xA6}, /* Unknown */ + {OV8858_8BIT, 0x372C, 0xA6}, /* Unknown */ + {OV8858_8BIT, 0x372D, 0xA6}, /* Unknown */ + {OV8858_8BIT, 0x372E, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x372F, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x3730, 0x02}, /* Unknown */ + {OV8858_8BIT, 0x3731, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x3732, 0x28}, /* Unknown */ + {OV8858_8BIT, 0x3733, 0x10}, /* Unknown */ + {OV8858_8BIT, 0x3734, 0x40}, /* Unknown */ + {OV8858_8BIT, 0x3736, 0x30}, /* Unknown */ + {OV8858_8BIT, 0x373A, 0x0A}, /* Unknown */ + {OV8858_8BIT, 0x373B, 0x0B}, /* Unknown */ + {OV8858_8BIT, 0x373C, 0x14}, /* Unknown */ + {OV8858_8BIT, 0x373E, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3755, 0x10}, /* Unknown */ + {OV8858_8BIT, 0x3758, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3759, 0x4C}, /* Unknown */ + {OV8858_8BIT, 0x375A, 0x0C}, /* Unknown */ + {OV8858_8BIT, 0x375B, 0x26}, /* Unknown */ + {OV8858_8BIT, 0x375C, 0x20}, /* Unknown */ + {OV8858_8BIT, 0x375D, 0x04}, /* Unknown */ + {OV8858_8BIT, 0x375E, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x375F, 0x28}, /* Unknown */ + {OV8858_8BIT, 0x3760, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3761, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3762, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3763, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3766, 0xFF}, /* Unknown */ + {OV8858_8BIT, 0x3768, 0x22}, /* Unknown */ + {OV8858_8BIT, 0x3769, 0x44}, /* Unknown */ + {OV8858_8BIT, 0x376A, 0x44}, /* Unknown */ + {OV8858_8BIT, 0x376B, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x376F, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3772, 0x46}, /* Unknown */ + {OV8858_8BIT, 0x3773, 0x04}, /* Unknown */ + {OV8858_8BIT, 0x3774, 0x2C}, /* Unknown */ + {OV8858_8BIT, 0x3775, 0x13}, /* Unknown */ + {OV8858_8BIT, 0x3776, 0x08}, /* Unknown */ + {OV8858_8BIT, 0x3777, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x37A0, 0x88}, /* Unknown */ + {OV8858_8BIT, 0x37A1, 0x7A}, /* Unknown */ + {OV8858_8BIT, 0x37A2, 0x7A}, /* Unknown */ + {OV8858_8BIT, 0x37A3, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37A4, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37A5, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37A6, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37A7, 0x88}, /* Unknown */ + {OV8858_8BIT, 0x37A8, 0x98}, /* Unknown */ + {OV8858_8BIT, 0x37A9, 0x98}, /* Unknown */ + {OV8858_8BIT, 0x37AA, 0x88}, /* Unknown */ + {OV8858_8BIT, 0x37AB, 0x5C}, /* Unknown */ + {OV8858_8BIT, 0x37AC, 0x5C}, /* Unknown */ + {OV8858_8BIT, 0x37AD, 0x55}, /* Unknown */ + {OV8858_8BIT, 0x37AE, 0x19}, /* Unknown */ + {OV8858_8BIT, 0x37AF, 0x19}, /* Unknown */ + {OV8858_8BIT, 0x37B0, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B1, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B2, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B3, 0x84}, /* Unknown */ + {OV8858_8BIT, 0x37B4, 0x84}, /* Unknown */ + {OV8858_8BIT, 0x37B5, 0x66}, /* Unknown */ + {OV8858_8BIT, 0x37B6, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B7, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B8, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x37B9, 0xFF}, /* Unknown */ + + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */ + {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high */ + {OV8858_8BIT, 0x3809, 0xC0}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x09}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x90}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ + {OV8858_8BIT, 0x3810, 0x00}, /* h_win offset high */ + {OV8858_8BIT, 0x3811, 0x04}, /* h_win offset low */ + {OV8858_8BIT, 0x3812, 0x00}, /* v_win offset high */ + {OV8858_8BIT, 0x3813, 0x02}, /* v_win offset low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3837, 0x18}, /* Unknown */ + {OV8858_8BIT, 0x3841, 0xFF}, /* AUTO_SIZE_CTRL */ + {OV8858_8BIT, 0x3846, 0x48}, /* Unknown */ + + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3D8C, 0x73}, /* OTP_SETTING_STT_ADDRESS */ + {OV8858_8BIT, 0x3D8D, 0xDE}, /* OTP_SETTING_STT_ADDRESS */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x3F0A, 0x80}, /* PSRAM control register */ + + {OV8858_8BIT, 0x4000, 0xF1}, /* BLC CTRL00 = default */ + {OV8858_8BIT, 0x4001, 0x00}, /* BLC CTRL01 */ + {OV8858_8BIT, 0x4002, 0x27}, /* BLC offset = 0x27 */ + {OV8858_8BIT, 0x4005, 0x10}, /* BLC target = 0x0010 */ + {OV8858_8BIT, 0x4009, 0x81}, /* BLC CTRL09 */ + {OV8858_8BIT, 0x400B, 0x0C}, /* BLC CTRL0B = default */ + {OV8858_8BIT, 0x400A, 0x01}, + {OV8858_8BIT, 0x4011, 0x20}, /* BLC CTRL11 = 0x20 */ + {OV8858_8BIT, 0x401B, 0x00}, /* Zero line R coeff. = 0x0000 */ + {OV8858_8BIT, 0x401D, 0x00}, /* Zero line T coeff. = 0x0000 */ + {OV8858_8BIT, 0x401F, 0x00}, /* BLC CTRL1F */ + {OV8858_8BIT, 0x4020, 0x00}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4021, 0x04}, /* Anchor left start = 0x0004 */ + {OV8858_8BIT, 0x4022, 0x0C}, /* Anchor left end = 0x0C60 */ + {OV8858_8BIT, 0x4023, 0x60}, /* Anchor left end = 0x0C60 */ + {OV8858_8BIT, 0x4024, 0x0F}, /* Anchor right start = 0x0F36 */ + {OV8858_8BIT, 0x4025, 0x36}, /* Anchor right start = 0x0F36 */ + {OV8858_8BIT, 0x4026, 0x0F}, /* Anchor right end = 0x0F37 */ + {OV8858_8BIT, 0x4027, 0x37}, /* Anchor right end = 0x0F37 */ + {OV8858_8BIT, 0x4028, 0x00}, /* Top zero line start = 0 */ + {OV8858_8BIT, 0x4029, 0x04}, /* Top zero line number = 4 */ + {OV8858_8BIT, 0x402A, 0x04}, /* Top black line start = 4 */ + {OV8858_8BIT, 0x402B, 0x08}, /* Top black line number = 8 */ + {OV8858_8BIT, 0x402C, 0x00}, /* Bottom zero start line = 0 */ + {OV8858_8BIT, 0x402D, 0x02}, /* Bottom zero line number = 2 */ + {OV8858_8BIT, 0x402E, 0x04}, /* Bottom black line start = 4 */ + {OV8858_8BIT, 0x402F, 0x08}, /* Bottom black line number = 8 */ + + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4300, 0xFF}, /* clip_max[11:4] = 0xFFF */ + {OV8858_8BIT, 0x4301, 0x00}, /* clip_min[11:4] = 0 */ + {OV8858_8BIT, 0x4302, 0x0F}, /* clip_min/max[3:0] */ + {OV8858_8BIT, 0x4307, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x4316, 0x00}, /* CTRL16 = default */ + {OV8858_8BIT, 0x4503, 0x18}, /* Unknown */ + {OV8858_8BIT, 0x4500, 0x38}, /* Unknown */ + {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ + /* wkup_dly = Mark1 wakeup delay/2^10 = 0x25 */ + {OV8858_8BIT, 0x4808, 0x25}, + {OV8858_8BIT, 0x4816, 0x52}, /* Embedded data type*/ + {OV8858_8BIT, 0x481F, 0x32}, /* clk_prepare_min = 0x32 */ + {OV8858_8BIT, 0x4825, 0x3A}, /* lpx_p_min = 0x3A */ + {OV8858_8BIT, 0x4826, 0x40}, /* hs_prepare_min = 0x40 */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_8BIT, 0x4850, 0x10}, /* LANE SEL01 */ + {OV8858_8BIT, 0x4851, 0x32}, /* LANE SEL02 */ + + {OV8858_8BIT, 0x4B00, 0x2A}, /* Unknown */ + {OV8858_8BIT, 0x4B0D, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4D00, 0x04}, /* TPM_CTRL_REG */ + {OV8858_8BIT, 0x4D01, 0x18}, /* TPM_CTRL_REG */ + {OV8858_8BIT, 0x4D02, 0xC3}, /* TPM_CTRL_REG */ + {OV8858_8BIT, 0x4D03, 0xFF}, /* TPM_CTRL_REG */ + {OV8858_8BIT, 0x4D04, 0xFF}, /* TPM_CTRL_REG */ + {OV8858_8BIT, 0x4D05, 0xFF}, /* TPM_CTRL_REG */ + + /* + * Lens correction (LENC) function enable = 0 + * Slave sensor AWB Gain function enable = 1 + * Slave sensor AWB Statistics function enable = 1 + * Master sensor AWB Gain function enable = 1 + * Master sensor AWB Statistics function enable = 1 + * Black DPC function enable = 1 + * White DPC function enable =1 + */ + {OV8858_8BIT, 0x5000, 0x7E}, + {OV8858_8BIT, 0x5001, 0x01}, /* BLC function enable = 1 */ + /* + * Horizontal scale function enable = 0 + * WBMATCH bypass mode = Select slave sensor's gain + * WBMATCH function enable = 0 + * Master MWB gain support RGBC = 0 + * OTP_DPC function enable = 1 + * Manual mode of VarioPixel function enable = 0 + * Manual enable of VarioPixel function enable = 0 + * Use VSYNC to latch ISP modules's function enable signals = 0 + */ + {OV8858_8BIT, 0x5002, 0x08}, + /* + * Bypass all ISP modules after BLC module = 0 + * DPC_DBC buffer control enable = 1 + * WBMATCH VSYNC selection = Select master sensor's VSYNC fall + * Select master AWB gain to embed line = AWB gain before manual mode + * Enable BLC's input flip_i signal = 0 + */ + {OV8858_8BIT, 0x5003, 0x20}, + {OV8858_8BIT, 0x5041, 0x1D}, /* ISP CTRL41 - embedded data=on */ + {OV8858_8BIT, 0x5046, 0x12}, /* ISP CTRL46 = default */ + /* + * Tail enable = 1 + * Saturate cross cluster enable = 1 + * Remove cross cluster enable = 1 + * Enable to remove connected defect pixels in same channel = 1 + * Enable to remove connected defect pixels in different channel = 1 + * Smooth enable, use average G for recovery = 1 + * Black/white sensor mode enable = 0 + * Manual mode enable = 0 + */ + {OV8858_8BIT, 0x5780, 0xFC}, + {OV8858_8BIT, 0x5784, 0x0C}, /* DPC CTRL04 */ + {OV8858_8BIT, 0x5787, 0x40}, /* DPC CTRL07 */ + {OV8858_8BIT, 0x5788, 0x08}, /* DPC CTRL08 */ + {OV8858_8BIT, 0x578A, 0x02}, /* DPC CTRL0A */ + {OV8858_8BIT, 0x578B, 0x01}, /* DPC CTRL0B */ + {OV8858_8BIT, 0x578C, 0x01}, /* DPC CTRL0C */ + {OV8858_8BIT, 0x578E, 0x02}, /* DPC CTRL0E */ + {OV8858_8BIT, 0x578F, 0x01}, /* DPC CTRL0F */ + {OV8858_8BIT, 0x5790, 0x01}, /* DPC CTRL10 */ + {OV8858_8BIT, 0x5901, 0x00}, /* VAP CTRL01 = default */ + /* WINC CTRL08 = embedded data in 1st line*/ + {OV8858_8BIT, 0x5A08, 0x00}, + {OV8858_8BIT, 0x5B00, 0x02}, /* OTP CTRL00 */ + {OV8858_8BIT, 0x5B01, 0x10}, /* OTP CTRL01 */ + {OV8858_8BIT, 0x5B02, 0x03}, /* OTP CTRL02 */ + {OV8858_8BIT, 0x5B03, 0xCF}, /* OTP CTRL03 */ + {OV8858_8BIT, 0x5B05, 0x6C}, /* OTP CTRL05 = default */ + {OV8858_8BIT, 0x5E00, 0x00}, /* PRE CTRL00 = default */ + {OV8858_8BIT, 0x5E01, 0x41}, /* PRE_CTRL01 = default */ + + {OV8858_TOK_TERM, 0, 0} +}; + +/*****************************STILL********************************/ + +static const struct ov8858_reg ov8858_8M[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */ + {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low 3283 */ + {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3280 x 2464 */ + {OV8858_8BIT, 0x3809, 0xD0}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x09}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0xa0}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_3276x1848[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x10}, /* h_crop_start low 0c->10*/ + {OV8858_8BIT, 0x3802, 0x01}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x42}, /* v_crop_start low 3e->42*/ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x08}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0x71}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3276 x 1848 */ + {OV8858_8BIT, 0x3809, 0xCC}, /* h_output_size low d0->cc*/ + {OV8858_8BIT, 0x380A, 0x07}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x38}, /* v_output_size low 3c->38*/ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_6M[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */ + {OV8858_8BIT, 0x3802, 0x01}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x3E}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x08}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0x71}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x0C}, /* h_output_size high 3280 x 1852 */ + {OV8858_8BIT, 0x3809, 0xD0}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x07}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x3C}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0x97}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_1080P_60[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x17}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x02}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x26}, /* h_crop_start low */ + {OV8858_8BIT, 0x3802, 0x02}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x8C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0A}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0x9D}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x07}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0x0A}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x07}, /* h_output_size high*/ + {OV8858_8BIT, 0x3809, 0x90}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x04}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0xEC}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0xef}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x16}, /* pclk_period = 0x16 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_1080P_30[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x17}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x02}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x26}, /* h_crop_start low */ + {OV8858_8BIT, 0x3802, 0x02}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x8C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0A}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0x9D}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x07}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0x0A}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x07}, /* h_output_size high*/ + {OV8858_8BIT, 0x3809, 0x90}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x0A}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0x0D}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x01}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x40}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x01}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x06}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x01}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x14}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x10}, /* PSRAM control register */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0xef}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x16}, /* pclk_period = 0x16 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_1640x1232[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */ + {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high 3283 */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 1232 */ + {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0xD0}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x67}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static const struct ov8858_reg ov8858_1640x1096[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low 12 */ + {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high 3283 */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 1096 */ + {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x04}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x48}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x67}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + + +static const struct ov8858_reg ov8858_1640x926[] = { + {OV8858_8BIT, 0x0100, 0x00}, /* software_standby */ + {OV8858_8BIT, 0x3778, 0x16}, /* Unknown */ + {OV8858_8BIT, 0x3800, 0x00}, /* h_crop_start high */ + {OV8858_8BIT, 0x3801, 0x0C}, /* h_crop_start low */ + {OV8858_8BIT, 0x3802, 0x00}, /* v_crop_start high */ + {OV8858_8BIT, 0x3803, 0x0C}, /* v_crop_start low */ + {OV8858_8BIT, 0x3804, 0x0C}, /* h_crop_end high */ + {OV8858_8BIT, 0x3805, 0xD3}, /* h_crop_end low */ + {OV8858_8BIT, 0x3806, 0x09}, /* v_crop_end high */ + {OV8858_8BIT, 0x3807, 0xA3}, /* v_crop_end low */ + {OV8858_8BIT, 0x3808, 0x06}, /* h_output_size high 1640 x 926 */ + {OV8858_8BIT, 0x3809, 0x68}, /* h_output_size low */ + {OV8858_8BIT, 0x380A, 0x03}, /* v_output_size high */ + {OV8858_8BIT, 0x380B, 0x9E}, /* v_output_size low */ + {OV8858_8BIT, 0x380C, 0x07}, /* horizontal timing size high */ + {OV8858_8BIT, 0x380D, 0x94}, /* horizontal timing size low */ + {OV8858_8BIT, 0x380E, 0x09}, /* vertical timing size high */ + {OV8858_8BIT, 0x380F, 0xAA}, /* vertical timing size low */ + {OV8858_8BIT, 0x3814, 0x03}, /* h_odd_inc */ + {OV8858_8BIT, 0x3815, 0x01}, /* h_even_inc */ + {OV8858_8BIT, 0x3820, 0x00}, /* format1 */ + {OV8858_8BIT, 0x3821, 0x67}, /* format2 */ + {OV8858_8BIT, 0x382A, 0x03}, /* v_odd_inc */ + {OV8858_8BIT, 0x382B, 0x01}, /* v_even_inc */ + {OV8858_8BIT, 0x3830, 0x08}, /* Unknown */ + {OV8858_8BIT, 0x3836, 0x02}, /* Unknown */ + {OV8858_8BIT, 0x3D85, 0x16}, /* OTP_REG85 */ + {OV8858_8BIT, 0x3F08, 0x08}, /* PSRAM control register */ + {OV8858_8BIT, 0x4034, 0x3F}, /* Unknown */ + {OV8858_8BIT, 0x403D, 0x04}, /* BLC CTRL3D */ + {OV8858_8BIT, 0x4600, 0x00}, /* Unknown */ + {OV8858_8BIT, 0x4601, 0xCB}, /* Unknown */ + {OV8858_8BIT, 0x4837, 0x14}, /* pclk_period = 0x14 */ + {OV8858_TOK_TERM, 0, 0} +}; + +static struct ov8858_resolution ov8858_res_preview[] = { + { + .desc = "ov8858_1640x926_PREVIEW", + .width = 1640, + .height = 926, + .used = 0, + .regs = ov8858_1640x926, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_1640x1232_PREVIEW", + .width = 1640, + .height = 1232, + .used = 0, + .regs = ov8858_1640x1232, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_1936x1096_PREVIEW", + .width = 1936, + .height = 1096, + .used = 0, + .regs = ov8858_1080P_30, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_3276x1848_PREVIEW", + .width = 3276, + .height = 1848, + .used = 0, + .regs = ov8858_3276x1848, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_8M_PREVIEW", + .width = 3280, + .height = 2464, + .used = 0, + .regs = ov8858_8M, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, +}; + +static struct ov8858_resolution ov8858_res_still[] = { + { + .desc = "ov8858_1640x1232_STILL", + .width = 1640, + .height = 1232, + .used = 0, + .regs = ov8858_1640x1232, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 0, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_1640x926_STILL", + .width = 1640, + .height = 926, + .used = 0, + .regs = ov8858_1640x926, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_3276X1848_STILL", + .width = 3276, + .height = 1848, + .used = 0, + .regs = ov8858_3276x1848, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_8M_STILL", + .width = 3280, + .height = 2464, + .used = 0, + .regs = ov8858_8M, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + /* Pixel clock: 149.76MHZ */ + .fps = 10, + .pixels_per_line = 3880, + .lines_per_frame = 3859, + }, + { + } + }, + }, +}; + +static struct ov8858_resolution ov8858_res_video[] = { + { + .desc = "ov8858_1640x926_VIDEO", + .width = 1640, + .height = 926, + .used = 0, + .regs = ov8858_1640x926, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_1640x1232_VIDEO", + .width = 1640, + .height = 1232, + .used = 0, + .regs = ov8858_1640x1232, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_1640x1096_VIDEO", + .width = 1640, + .height = 1096, + .used = 0, + .regs = ov8858_1640x1096, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, + { + .desc = "ov8858_1080P_30_VIDEO", + .width = 1936, + .height = 1096, + .used = 0, + .regs = ov8858_1080P_30, + .bin_factor_x = 0, + .bin_factor_y = 0, + .skip_frames = 1, + .fps_options = { + { + .fps = 30, + .pixels_per_line = 3880, + .lines_per_frame = 2573, + }, + { + } + }, + }, +}; + +#endif /* __OV8858_H__ */ diff --git a/drivers/staging/media/atomisp/include/asm/intel_mid_pcihelpers.h b/drivers/staging/media/atomisp/include/asm/intel_mid_pcihelpers.h new file mode 100644 index 0000000000000000000000000000000000000000..c5e22bba455a8a4a9137b9102367c780ad384b92 --- /dev/null +++ b/drivers/staging/media/atomisp/include/asm/intel_mid_pcihelpers.h @@ -0,0 +1,37 @@ +/* + * Access to message bus through three registers + * in CUNIT(0:0:0) PCI configuration space. + * MSGBUS_CTRL_REG(0xD0): + * 31:24 = message bus opcode + * 23:16 = message bus port + * 15:8 = message bus address, low 8 bits. + * 7:4 = message bus byte enables + * MSGBUS_CTRL_EXT_REG(0xD8): + * 31:8 = message bus address, high 24 bits. + * MSGBUS_DATA_REG(0xD4): + * hold the data for write or read + */ +#define PCI_ROOT_MSGBUS_CTRL_REG 0xD0 +#define PCI_ROOT_MSGBUS_DATA_REG 0xD4 +#define PCI_ROOT_MSGBUS_CTRL_EXT_REG 0xD8 +#define PCI_ROOT_MSGBUS_READ 0x10 +#define PCI_ROOT_MSGBUS_WRITE 0x11 +#define PCI_ROOT_MSGBUS_DWORD_ENABLE 0xf0 + +/* In BYT platform for all internal PCI devices d3 delay + * of 3 ms is sufficient. Default value of 10 ms is overkill. + */ +#define INTERNAL_PCI_PM_D3_WAIT 3 + +#define ISP_SUB_CLASS 0x80 +#define SUB_CLASS_MASK 0xFF00 + +u32 intel_mid_msgbus_read32_raw(u32 cmd); +u32 intel_mid_msgbus_read32(u8 port, u32 addr); +void intel_mid_msgbus_write32_raw(u32 cmd, u32 data); +void intel_mid_msgbus_write32(u8 port, u32 addr, u32 data); +u32 intel_mid_msgbus_read32_raw_ext(u32 cmd, u32 cmd_ext); +void intel_mid_msgbus_write32_raw_ext(u32 cmd, u32 cmd_ext, u32 data); +u32 intel_mid_soc_stepping(void); +int intel_mid_dw_i2c_acquire_ownership(void); +int intel_mid_dw_i2c_release_ownership(void); diff --git a/drivers/staging/media/atomisp/include/linux/atomisp.h b/drivers/staging/media/atomisp/include/linux/atomisp.h new file mode 100644 index 0000000000000000000000000000000000000000..35865462ccf9da318a21b4bf6895c6c370fdb8bb --- /dev/null +++ b/drivers/staging/media/atomisp/include/linux/atomisp.h @@ -0,0 +1,1367 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#ifdef CSS15 +#include +#else + +#ifndef _ATOM_ISP_H +#define _ATOM_ISP_H + +#include +#include + +/* struct media_device_info.driver_version */ +#define ATOMISP_CSS_VERSION_MASK 0x00ffffff +#define ATOMISP_CSS_VERSION_15 KERNEL_VERSION(1, 5, 0) +#define ATOMISP_CSS_VERSION_20 KERNEL_VERSION(2, 0, 0) +#define ATOMISP_CSS_VERSION_21 KERNEL_VERSION(2, 1, 0) + +/* struct media_device_info.hw_revision */ +#define ATOMISP_HW_REVISION_MASK 0x0000ff00 +#define ATOMISP_HW_REVISION_SHIFT 8 +#define ATOMISP_HW_REVISION_ISP2300 0x00 +#define ATOMISP_HW_REVISION_ISP2400 0x10 +#define ATOMISP_HW_REVISION_ISP2401_LEGACY 0x11 +#define ATOMISP_HW_REVISION_ISP2401 0x20 + +#define ATOMISP_HW_STEPPING_MASK 0x000000ff +#define ATOMISP_HW_STEPPING_A0 0x00 +#define ATOMISP_HW_STEPPING_B0 0x10 + +/*ISP binary running mode*/ +#define CI_MODE_PREVIEW 0x8000 +#define CI_MODE_VIDEO 0x4000 +#define CI_MODE_STILL_CAPTURE 0x2000 +#define CI_MODE_CONTINUOUS 0x1000 +#define CI_MODE_NONE 0x0000 + +#define OUTPUT_MODE_FILE 0x0100 +#define OUTPUT_MODE_TEXT 0x0200 + +/* + * Camera HAL sets this flag in v4l2_buffer reserved2 to indicate this + * buffer has a per-frame parameter. + */ +#define ATOMISP_BUFFER_HAS_PER_FRAME_SETTING 0x80000000 + +/* Custom format for RAW capture from M10MO 0x3130314d */ +#define V4L2_PIX_FMT_CUSTOM_M10MO_RAW v4l2_fourcc('M', '1', '0', '1') + +/* Custom media bus formats being used in atomisp */ +#define V4L2_MBUS_FMT_CUSTOM_YUV420 0x8001 +#define V4L2_MBUS_FMT_CUSTOM_YVU420 0x8002 +#define V4L2_MBUS_FMT_CUSTOM_YUV422P 0x8003 +#define V4L2_MBUS_FMT_CUSTOM_YUV444 0x8004 +#define V4L2_MBUS_FMT_CUSTOM_NV12 0x8005 +#define V4L2_MBUS_FMT_CUSTOM_NV21 0x8006 +#define V4L2_MBUS_FMT_CUSTOM_NV16 0x8007 +#define V4L2_MBUS_FMT_CUSTOM_YUYV 0x8008 +#define V4L2_MBUS_FMT_CUSTOM_SBGGR16 0x8009 +#define V4L2_MBUS_FMT_CUSTOM_RGB32 0x800a + +/* Custom media bus format for M10MO RAW capture */ +#define V4L2_MBUS_FMT_CUSTOM_M10MO_RAW 0x800b + +/* Configuration used by Bayer noise reduction and YCC noise reduction */ +struct atomisp_nr_config { + /* [gain] Strength of noise reduction for Bayer NR (Used by Bayer NR) */ + unsigned int bnr_gain; + /* [gain] Strength of noise reduction for YCC NR (Used by YCC NR) */ + unsigned int ynr_gain; + /* [intensity] Sensitivity of Edge (Used by Bayer NR) */ + unsigned int direction; + /* [intensity] coring threshold for Cb (Used by YCC NR) */ + unsigned int threshold_cb; + /* [intensity] coring threshold for Cr (Used by YCC NR) */ + unsigned int threshold_cr; +}; + +/* Temporal noise reduction configuration */ +struct atomisp_tnr_config { + unsigned int gain; /* [gain] Strength of NR */ + unsigned int threshold_y;/* [intensity] Motion sensitivity for Y */ + unsigned int threshold_uv;/* [intensity] Motion sensitivity for U/V */ +}; + +/* Histogram. This contains num_elements values of type unsigned int. + * The data pointer is a DDR pointer (virtual address). + */ +struct atomisp_histogram { + unsigned int num_elements; + void __user *data; +}; + +enum atomisp_ob_mode { + atomisp_ob_mode_none, + atomisp_ob_mode_fixed, + atomisp_ob_mode_raster +}; + +/* Optical black level configuration */ +struct atomisp_ob_config { + /* Obtical black level mode (Fixed / Raster) */ + enum atomisp_ob_mode mode; + /* [intensity] optical black level for GR (relevant for fixed mode) */ + unsigned int level_gr; + /* [intensity] optical black level for R (relevant for fixed mode) */ + unsigned int level_r; + /* [intensity] optical black level for B (relevant for fixed mode) */ + unsigned int level_b; + /* [intensity] optical black level for GB (relevant for fixed mode) */ + unsigned int level_gb; + /* [BQ] 0..63 start position of OB area (relevant for raster mode) */ + unsigned short start_position; + /* [BQ] start..63 end position of OB area (relevant for raster mode) */ + unsigned short end_position; +}; + +/* Edge enhancement (sharpen) configuration */ +struct atomisp_ee_config { + /* [gain] The strength of sharpness. u5_11 */ + unsigned int gain; + /* [intensity] The threshold that divides noises from edge. u8_8 */ + unsigned int threshold; + /* [gain] The strength of sharpness in pell-mell area. u5_11 */ + unsigned int detail_gain; +}; + +struct atomisp_3a_output { + int ae_y; + int awb_cnt; + int awb_gr; + int awb_r; + int awb_b; + int awb_gb; + int af_hpf1; + int af_hpf2; +}; + +enum atomisp_calibration_type { + calibration_type1, + calibration_type2, + calibration_type3 +}; + +struct atomisp_calibration_group { + unsigned int size; + unsigned int type; + unsigned short *calb_grp_values; +}; + +struct atomisp_gc_config { + __u16 gain_k1; + __u16 gain_k2; +}; + +struct atomisp_3a_config { + unsigned int ae_y_coef_r; /* [gain] Weight of R for Y */ + unsigned int ae_y_coef_g; /* [gain] Weight of G for Y */ + unsigned int ae_y_coef_b; /* [gain] Weight of B for Y */ + unsigned int awb_lg_high_raw; /* [intensity] + AWB level gate high for raw */ + unsigned int awb_lg_low; /* [intensity] AWB level gate low */ + unsigned int awb_lg_high; /* [intensity] AWB level gate high */ + int af_fir1_coef[7]; /* [factor] AF FIR coefficients of fir1 */ + int af_fir2_coef[7]; /* [factor] AF FIR coefficients of fir2 */ +}; + +struct atomisp_dvs_grid_info { + uint32_t enable; + uint32_t width; + uint32_t aligned_width; + uint32_t height; + uint32_t aligned_height; + uint32_t bqs_per_grid_cell; + uint32_t num_hor_coefs; + uint32_t num_ver_coefs; +}; + +struct atomisp_dvs_envelop { + unsigned int width; + unsigned int height; +}; + +struct atomisp_grid_info { + uint32_t enable; + uint32_t use_dmem; + uint32_t has_histogram; + uint32_t s3a_width; + uint32_t s3a_height; + uint32_t aligned_width; + uint32_t aligned_height; + uint32_t s3a_bqs_per_grid_cell; + uint32_t deci_factor_log2; + uint32_t elem_bit_depth; +}; + +struct atomisp_dis_vector { + int x; + int y; +}; + + +/** DVS 2.0 Coefficient types. This structure contains 4 pointers to + * arrays that contain the coeffients for each type. + */ +struct atomisp_dvs2_coef_types { + short __user *odd_real; /**< real part of the odd coefficients*/ + short __user *odd_imag; /**< imaginary part of the odd coefficients*/ + short __user *even_real;/**< real part of the even coefficients*/ + short __user *even_imag;/**< imaginary part of the even coefficients*/ +}; + +/* + * DVS 2.0 Statistic types. This structure contains 4 pointers to + * arrays that contain the statistics for each type. + */ +struct atomisp_dvs2_stat_types { + int __user *odd_real; /**< real part of the odd statistics*/ + int __user *odd_imag; /**< imaginary part of the odd statistics*/ + int __user *even_real;/**< real part of the even statistics*/ + int __user *even_imag;/**< imaginary part of the even statistics*/ +}; + +struct atomisp_dis_coefficients { + struct atomisp_dvs_grid_info grid_info; + struct atomisp_dvs2_coef_types hor_coefs; + struct atomisp_dvs2_coef_types ver_coefs; +}; + +struct atomisp_dvs2_statistics { + struct atomisp_dvs_grid_info grid_info; + struct atomisp_dvs2_stat_types hor_prod; + struct atomisp_dvs2_stat_types ver_prod; +}; + +struct atomisp_dis_statistics { + struct atomisp_dvs2_statistics dvs2_stat; + uint32_t exp_id; +}; + +struct atomisp_3a_rgby_output { + uint32_t r; + uint32_t g; + uint32_t b; + uint32_t y; +}; + +/* + * Because we have 2 pipes at max to output metadata, therefore driver will use + * ATOMISP_MAIN_METADATA to specify the metadata from the pipe which keeps + * streaming always and use ATOMISP_SEC_METADATA to specify the metadata from + * the pipe which is streaming by request like capture pipe of ZSL or SDV mode + * as secondary metadata. And for the use case which has only one pipe + * streaming like online capture, ATOMISP_MAIN_METADATA will be used. + */ +enum atomisp_metadata_type { + ATOMISP_MAIN_METADATA = 0, + ATOMISP_SEC_METADATA, + ATOMISP_METADATA_TYPE_NUM, +}; + +struct atomisp_metadata_with_type { + /* to specify which type of metadata to get */ + enum atomisp_metadata_type type; + void __user *data; + uint32_t width; + uint32_t height; + uint32_t stride; /* in bytes */ + uint32_t exp_id; /* exposure ID */ + uint32_t *effective_width; /* mipi packets valid data size */ +}; + +struct atomisp_metadata { + void __user *data; + uint32_t width; + uint32_t height; + uint32_t stride; /* in bytes */ + uint32_t exp_id; /* exposure ID */ + uint32_t *effective_width; /* mipi packets valid data size */ +}; + +struct atomisp_ext_isp_ctrl { + uint32_t id; + uint32_t data; +}; + +struct atomisp_3a_statistics { + struct atomisp_grid_info grid_info; + struct atomisp_3a_output __user *data; + struct atomisp_3a_rgby_output __user *rgby_data; + uint32_t exp_id; /* exposure ID */ + uint32_t isp_config_id; /* isp config ID */ +}; + +/** + * struct atomisp_cont_capture_conf - continuous capture parameters + * @num_captures: number of still images to capture + * @skip_frames: number of frames to skip between 2 captures + * @offset: offset in ring buffer to start capture + * + * For example, to capture 1 frame from past, current, and 1 from future + * and skip one frame between each capture, parameters would be: + * num_captures:3 + * skip_frames:1 + * offset:-2 + */ + +struct atomisp_cont_capture_conf { + int num_captures; + unsigned int skip_frames; + int offset; + __u32 reserved[5]; +}; + +struct atomisp_ae_window { + int x_left; + int x_right; + int y_top; + int y_bottom; + int weight; +}; + +/* White Balance (Gain Adjust) */ +struct atomisp_wb_config { + unsigned int integer_bits; + unsigned int gr; /* unsigned .<16-integer_bits> */ + unsigned int r; /* unsigned .<16-integer_bits> */ + unsigned int b; /* unsigned .<16-integer_bits> */ + unsigned int gb; /* unsigned .<16-integer_bits> */ +}; + +/* Color Space Conversion settings */ +struct atomisp_cc_config { + unsigned int fraction_bits; + int matrix[3 * 3]; /* RGB2YUV Color matrix, signed + <13-fraction_bits>. */ +}; + +/* De pixel noise configuration */ +struct atomisp_de_config { + unsigned int pixelnoise; + unsigned int c1_coring_threshold; + unsigned int c2_coring_threshold; +}; + +/* Chroma enhancement */ +struct atomisp_ce_config { + unsigned char uv_level_min; + unsigned char uv_level_max; +}; + +/* Defect pixel correction configuration */ +struct atomisp_dp_config { + /* [intensity] The threshold of defect Pixel Correction, representing + * the permissible difference of intensity between one pixel and its + * surrounding pixels. Smaller values result in more frequent pixel + * corrections. u0_16 + */ + unsigned int threshold; + /* [gain] The sensitivity of mis-correction. ISP will miss a lot of + * defects if the value is set too large. u8_8 + */ + unsigned int gain; + unsigned int gr; + unsigned int r; + unsigned int b; + unsigned int gb; +}; + +/* XNR threshold */ +struct atomisp_xnr_config { + __u16 threshold; +}; + +/* metadata config */ +struct atomisp_metadata_config { + uint32_t metadata_height; + uint32_t metadata_stride; +}; + +/* + * Generic resolution structure. + */ +struct atomisp_resolution { + uint32_t width; /**< Width */ + uint32_t height; /**< Height */ +}; + +/* + * This specifies the coordinates (x,y) + */ +struct atomisp_zoom_point { + int32_t x; /**< x coordinate */ + int32_t y; /**< y coordinate */ +}; + +/* + * This specifies the region + */ +struct atomisp_zoom_region { + struct atomisp_zoom_point origin; /* Starting point coordinates for the region */ + struct atomisp_resolution resolution; /* Region resolution */ +}; + +struct atomisp_dz_config { + uint32_t dx; /**< Horizontal zoom factor */ + uint32_t dy; /**< Vertical zoom factor */ + struct atomisp_zoom_region zoom_region; /**< region for zoom */ +}; + +struct atomisp_parm { + struct atomisp_grid_info info; + struct atomisp_dvs_grid_info dvs_grid; + struct atomisp_dvs_envelop dvs_envelop; + struct atomisp_wb_config wb_config; + struct atomisp_cc_config cc_config; + struct atomisp_ob_config ob_config; + struct atomisp_de_config de_config; + struct atomisp_dz_config dz_config; + struct atomisp_ce_config ce_config; + struct atomisp_dp_config dp_config; + struct atomisp_nr_config nr_config; + struct atomisp_ee_config ee_config; + struct atomisp_tnr_config tnr_config; + struct atomisp_metadata_config metadata_config; +}; + +struct dvs2_bq_resolution { + int width_bq; /* width [BQ] */ + int height_bq; /* height [BQ] */ +}; + +struct atomisp_dvs2_bq_resolutions { + /* GDC source image size [BQ] */ + struct dvs2_bq_resolution source_bq; + /* GDC output image size [BQ] */ + struct dvs2_bq_resolution output_bq; + /* GDC effective envelope size [BQ] */ + struct dvs2_bq_resolution envelope_bq; + /* isp pipe filter size [BQ] */ + struct dvs2_bq_resolution ispfilter_bq; + /* GDC shit size [BQ] */ + struct dvs2_bq_resolution gdc_shift_bq; +}; + +struct atomisp_dvs_6axis_config { + uint32_t exp_id; + uint32_t width_y; + uint32_t height_y; + uint32_t width_uv; + uint32_t height_uv; + uint32_t *xcoords_y; + uint32_t *ycoords_y; + uint32_t *xcoords_uv; + uint32_t *ycoords_uv; +}; + +struct atomisp_formats_config { + uint32_t video_full_range_flag; +}; + +struct atomisp_parameters { + struct atomisp_wb_config *wb_config; /* White Balance config */ + struct atomisp_cc_config *cc_config; /* Color Correction config */ + struct atomisp_tnr_config *tnr_config; /* Temporal Noise Reduction */ + struct atomisp_ecd_config *ecd_config; /* Eigen Color Demosaicing */ + struct atomisp_ynr_config *ynr_config; /* Y(Luma) Noise Reduction */ + struct atomisp_fc_config *fc_config; /* Fringe Control */ + struct atomisp_formats_config *formats_config; /* Formats Control */ + struct atomisp_cnr_config *cnr_config; /* Chroma Noise Reduction */ + struct atomisp_macc_config *macc_config; /* MACC */ + struct atomisp_ctc_config *ctc_config; /* Chroma Tone Control */ + struct atomisp_aa_config *aa_config; /* Anti-Aliasing */ + struct atomisp_aa_config *baa_config; /* Anti-Aliasing */ + struct atomisp_ce_config *ce_config; + struct atomisp_dvs_6axis_config *dvs_6axis_config; + struct atomisp_ob_config *ob_config; /* Objective Black config */ + struct atomisp_dp_config *dp_config; /* Dead Pixel config */ + struct atomisp_nr_config *nr_config; /* Noise Reduction config */ + struct atomisp_ee_config *ee_config; /* Edge Enhancement config */ + struct atomisp_de_config *de_config; /* Demosaic config */ + struct atomisp_gc_config *gc_config; /* Gamma Correction config */ + struct atomisp_anr_config *anr_config; /* Advanced Noise Reduction */ + struct atomisp_3a_config *a3a_config; /* 3A Statistics config */ + struct atomisp_xnr_config *xnr_config; /* eXtra Noise Reduction */ + struct atomisp_dz_config *dz_config; /* Digital Zoom */ + struct atomisp_cc_config *yuv2rgb_cc_config; /* Color + Correction config */ + struct atomisp_cc_config *rgb2yuv_cc_config; /* Color + Correction config */ + struct atomisp_macc_table *macc_table; + struct atomisp_gamma_table *gamma_table; + struct atomisp_ctc_table *ctc_table; + struct atomisp_xnr_table *xnr_table; + struct atomisp_rgb_gamma_table *r_gamma_table; + struct atomisp_rgb_gamma_table *g_gamma_table; + struct atomisp_rgb_gamma_table *b_gamma_table; + struct atomisp_vector *motion_vector; /* For 2-axis DVS */ + struct atomisp_shading_table *shading_table; + struct atomisp_morph_table *morph_table; + struct atomisp_dvs_coefficients *dvs_coefs; /* DVS 1.0 coefficients */ + struct atomisp_dvs2_coefficients *dvs2_coefs; /* DVS 2.0 coefficients */ + struct atomisp_capture_config *capture_config; + struct atomisp_anr_thres *anr_thres; + + void *lin_2500_config; /* Skylake: Linearization config */ + void *obgrid_2500_config; /* Skylake: OBGRID config */ + void *bnr_2500_config; /* Skylake: bayer denoise config */ + void *shd_2500_config; /* Skylake: shading config */ + void *dm_2500_config; /* Skylake: demosaic config */ + void *rgbpp_2500_config; /* Skylake: RGBPP config */ + void *dvs_stat_2500_config; /* Skylake: DVS STAT config */ + void *lace_stat_2500_config; /* Skylake: LACE STAT config */ + void *yuvp1_2500_config; /* Skylake: yuvp1 config */ + void *yuvp2_2500_config; /* Skylake: yuvp2 config */ + void *tnr_2500_config; /* Skylake: TNR config */ + void *dpc_2500_config; /* Skylake: DPC config */ + void *awb_2500_config; /* Skylake: auto white balance config */ + void *awb_fr_2500_config; /* Skylake: auto white balance filter response config */ + void *anr_2500_config; /* Skylake: ANR config */ + void *af_2500_config; /* Skylake: auto focus config */ + void *ae_2500_config; /* Skylake: auto exposure config */ + void *bds_2500_config; /* Skylake: bayer downscaler config */ + void *dvs_2500_config; /* Skylake: digital video stabilization config */ + void *res_mgr_2500_config; + + /* + * Output frame pointer the config is to be applied to (optional), + * set to NULL to make this config is applied as global. + */ + void *output_frame; + /* + * Unique ID to track which config was actually applied to a particular + * frame, driver will send this id back with output frame together. + */ + uint32_t isp_config_id; + + /* + * Switch to control per_frame setting: + * 0: this is a global setting + * 1: this is a per_frame setting + * PLEASE KEEP THIS AT THE END OF THE STRUCTURE!! + */ + uint32_t per_frame_setting; +}; + +#define ATOMISP_GAMMA_TABLE_SIZE 1024 +struct atomisp_gamma_table { + unsigned short data[ATOMISP_GAMMA_TABLE_SIZE]; +}; + +/* Morphing table for advanced ISP. + * Each line of width elements takes up COORD_TABLE_EXT_WIDTH elements + * in memory. + */ +#define ATOMISP_MORPH_TABLE_NUM_PLANES 6 +struct atomisp_morph_table { + unsigned int enabled; + + unsigned int height; + unsigned int width; /* number of valid elements per line */ + unsigned short __user *coordinates_x[ATOMISP_MORPH_TABLE_NUM_PLANES]; + unsigned short __user *coordinates_y[ATOMISP_MORPH_TABLE_NUM_PLANES]; +}; + +#define ATOMISP_NUM_SC_COLORS 4 +#define ATOMISP_SC_FLAG_QUERY (1 << 0) + +struct atomisp_shading_table { + __u32 enable; + + __u32 sensor_width; + __u32 sensor_height; + __u32 width; + __u32 height; + __u32 fraction_bits; + + __u16 *data[ATOMISP_NUM_SC_COLORS]; +}; + +struct atomisp_makernote_info { + /* bits 31-16: numerator, bits 15-0: denominator */ + unsigned int focal_length; + /* bits 31-16: numerator, bits 15-0: denominator*/ + unsigned int f_number_curr; + /* + * bits 31-24: max f-number numerator + * bits 23-16: max f-number denominator + * bits 15-8: min f-number numerator + * bits 7-0: min f-number denominator + */ + unsigned int f_number_range; +}; + +/* parameter for MACC */ +#define ATOMISP_NUM_MACC_AXES 16 +struct atomisp_macc_table { + short data[4 * ATOMISP_NUM_MACC_AXES]; +}; + +struct atomisp_macc_config { + int color_effect; + struct atomisp_macc_table table; +}; + +/* Parameter for ctc parameter control */ +#define ATOMISP_CTC_TABLE_SIZE 1024 +struct atomisp_ctc_table { + unsigned short data[ATOMISP_CTC_TABLE_SIZE]; +}; + +/* Parameter for overlay image loading */ +struct atomisp_overlay { + /* the frame containing the overlay data The overlay frame width should + * be the multiples of 2*ISP_VEC_NELEMS. The overlay frame height + * should be the multiples of 2. + */ + struct v4l2_framebuffer *frame; + /* Y value of overlay background */ + unsigned char bg_y; + /* U value of overlay background */ + char bg_u; + /* V value of overlay background */ + char bg_v; + /* the blending percent of input data for Y subpixels */ + unsigned char blend_input_perc_y; + /* the blending percent of input data for U subpixels */ + unsigned char blend_input_perc_u; + /* the blending percent of input data for V subpixels */ + unsigned char blend_input_perc_v; + /* the blending percent of overlay data for Y subpixels */ + unsigned char blend_overlay_perc_y; + /* the blending percent of overlay data for U subpixels */ + unsigned char blend_overlay_perc_u; + /* the blending percent of overlay data for V subpixels */ + unsigned char blend_overlay_perc_v; + /* the overlay start x pixel position on output frame It should be the + multiples of 2*ISP_VEC_NELEMS. */ + unsigned int overlay_start_x; + /* the overlay start y pixel position on output frame It should be the + multiples of 2. */ + unsigned int overlay_start_y; +}; + +/* Sensor resolution specific data for AE calculation.*/ +struct atomisp_sensor_mode_data { + unsigned int coarse_integration_time_min; + unsigned int coarse_integration_time_max_margin; + unsigned int fine_integration_time_min; + unsigned int fine_integration_time_max_margin; + unsigned int fine_integration_time_def; + unsigned int frame_length_lines; + unsigned int line_length_pck; + unsigned int read_mode; + unsigned int vt_pix_clk_freq_mhz; + unsigned int crop_horizontal_start; /* Sensor crop start cord. (x0,y0)*/ + unsigned int crop_vertical_start; + unsigned int crop_horizontal_end; /* Sensor crop end cord. (x1,y1)*/ + unsigned int crop_vertical_end; + unsigned int output_width; /* input size to ISP after binning/scaling */ + unsigned int output_height; + uint8_t binning_factor_x; /* horizontal binning factor used */ + uint8_t binning_factor_y; /* vertical binning factor used */ + uint16_t hts; +}; + +struct atomisp_exposure { + unsigned int integration_time[8]; + unsigned int shutter_speed[8]; + unsigned int gain[4]; + unsigned int aperture; +}; + +/* For texture streaming. */ +struct atomisp_bc_video_package { + int ioctl_cmd; + int device_id; + int inputparam; + int outputparam; +}; + +enum atomisp_focus_hp { + ATOMISP_FOCUS_HP_IN_PROGRESS = (1U << 2), + ATOMISP_FOCUS_HP_COMPLETE = (2U << 2), + ATOMISP_FOCUS_HP_FAILED = (3U << 2) +}; + +/* Masks */ +#define ATOMISP_FOCUS_STATUS_MOVING (1U << 0) +#define ATOMISP_FOCUS_STATUS_ACCEPTS_NEW_MOVE (1U << 1) +#define ATOMISP_FOCUS_STATUS_HOME_POSITION (3U << 2) + +enum atomisp_camera_port { + ATOMISP_CAMERA_PORT_SECONDARY, + ATOMISP_CAMERA_PORT_PRIMARY, + ATOMISP_CAMERA_PORT_TERTIARY, + ATOMISP_CAMERA_NR_PORTS +}; + +/* Flash modes. Default is off. + * Setting a flash to TORCH or INDICATOR mode will automatically + * turn it on. Setting it to FLASH mode will not turn on the flash + * until the FLASH_STROBE command is sent. */ +enum atomisp_flash_mode { + ATOMISP_FLASH_MODE_OFF, + ATOMISP_FLASH_MODE_FLASH, + ATOMISP_FLASH_MODE_TORCH, + ATOMISP_FLASH_MODE_INDICATOR, +}; + +/* Flash statuses, used by atomisp driver to check before starting + * flash and after having started flash. */ +enum atomisp_flash_status { + ATOMISP_FLASH_STATUS_OK, + ATOMISP_FLASH_STATUS_HW_ERROR, + ATOMISP_FLASH_STATUS_INTERRUPTED, + ATOMISP_FLASH_STATUS_TIMEOUT, +}; + +/* Frame status. This is used to detect corrupted frames and flash + * exposed frames. Usually, the first 2 frames coming out of the sensor + * are corrupted. When using flash, the frame before and the frame after + * the flash exposed frame may be partially exposed by flash. The ISP + * statistics for these frames should not be used by the 3A library. + * The frame status value can be found in the "reserved" field in the + * v4l2_buffer struct. */ +enum atomisp_frame_status { + ATOMISP_FRAME_STATUS_OK, + ATOMISP_FRAME_STATUS_CORRUPTED, + ATOMISP_FRAME_STATUS_FLASH_EXPOSED, + ATOMISP_FRAME_STATUS_FLASH_PARTIAL, + ATOMISP_FRAME_STATUS_FLASH_FAILED, +}; + +enum atomisp_acc_type { + ATOMISP_ACC_STANDALONE, /* Stand-alone acceleration */ + ATOMISP_ACC_OUTPUT, /* Accelerator stage on output frame */ + ATOMISP_ACC_VIEWFINDER /* Accelerator stage on viewfinder frame */ +}; + +enum atomisp_acc_arg_type { + ATOMISP_ACC_ARG_SCALAR_IN, /* Scalar input argument */ + ATOMISP_ACC_ARG_SCALAR_OUT, /* Scalar output argument */ + ATOMISP_ACC_ARG_SCALAR_IO, /* Scalar in/output argument */ + ATOMISP_ACC_ARG_PTR_IN, /* Pointer input argument */ + ATOMISP_ACC_ARG_PTR_OUT, /* Pointer output argument */ + ATOMISP_ACC_ARG_PTR_IO, /* Pointer in/output argument */ + ATOMISP_ARG_PTR_NOFLUSH, /* Pointer argument will not be flushed */ + ATOMISP_ARG_PTR_STABLE, /* Pointer input argument that is stable */ + ATOMISP_ACC_ARG_FRAME /* Frame argument */ +}; + +/** ISP memories, isp2400 */ +enum atomisp_acc_memory { + ATOMISP_ACC_MEMORY_PMEM0 = 0, + ATOMISP_ACC_MEMORY_DMEM0, + /* for backward compatibility */ + ATOMISP_ACC_MEMORY_DMEM = ATOMISP_ACC_MEMORY_DMEM0, + ATOMISP_ACC_MEMORY_VMEM0, + ATOMISP_ACC_MEMORY_VAMEM0, + ATOMISP_ACC_MEMORY_VAMEM1, + ATOMISP_ACC_MEMORY_VAMEM2, + ATOMISP_ACC_MEMORY_HMEM0, + ATOMISP_ACC_NR_MEMORY +}; + +enum atomisp_ext_isp_id { + EXT_ISP_CID_ISO = 0, + EXT_ISP_CID_CAPTURE_HDR, + EXT_ISP_CID_CAPTURE_LLS, + EXT_ISP_CID_FOCUS_MODE, + EXT_ISP_CID_FOCUS_EXECUTION, + EXT_ISP_CID_TOUCH_POSX, + EXT_ISP_CID_TOUCH_POSY, + EXT_ISP_CID_CAF_STATUS, + EXT_ISP_CID_AF_STATUS, + EXT_ISP_CID_GET_AF_MODE, + EXT_ISP_CID_CAPTURE_BURST, + EXT_ISP_CID_FLASH_MODE, + EXT_ISP_CID_ZOOM, + EXT_ISP_CID_SHOT_MODE +}; + +#define EXT_ISP_FOCUS_MODE_NORMAL 0 +#define EXT_ISP_FOCUS_MODE_MACRO 1 +#define EXT_ISP_FOCUS_MODE_TOUCH_AF 2 +#define EXT_ISP_FOCUS_MODE_PREVIEW_CAF 3 +#define EXT_ISP_FOCUS_MODE_MOVIE_CAF 4 +#define EXT_ISP_FOCUS_MODE_FACE_CAF 5 +#define EXT_ISP_FOCUS_MODE_TOUCH_MACRO 6 +#define EXT_ISP_FOCUS_MODE_TOUCH_CAF 7 + +#define EXT_ISP_FOCUS_STOP 0 +#define EXT_ISP_FOCUS_SEARCH 1 +#define EXT_ISP_PAN_FOCUSING 2 + +#define EXT_ISP_CAF_RESTART_CHECK 1 +#define EXT_ISP_CAF_STATUS_FOCUSING 2 +#define EXT_ISP_CAF_STATUS_SUCCESS 3 +#define EXT_ISP_CAF_STATUS_FAIL 4 + +#define EXT_ISP_AF_STATUS_INVALID 1 +#define EXT_ISP_AF_STATUS_FOCUSING 2 +#define EXT_ISP_AF_STATUS_SUCCESS 3 +#define EXT_ISP_AF_STATUS_FAIL 4 + +enum atomisp_burst_capture_options { + EXT_ISP_BURST_CAPTURE_CTRL_START = 0, + EXT_ISP_BURST_CAPTURE_CTRL_STOP +}; + +#define EXT_ISP_FLASH_MODE_OFF 0 +#define EXT_ISP_FLASH_MODE_ON 1 +#define EXT_ISP_FLASH_MODE_AUTO 2 +#define EXT_ISP_LED_TORCH_OFF 3 +#define EXT_ISP_LED_TORCH_ON 4 + +#define EXT_ISP_SHOT_MODE_AUTO 0 +#define EXT_ISP_SHOT_MODE_BEAUTY_FACE 1 +#define EXT_ISP_SHOT_MODE_BEST_PHOTO 2 +#define EXT_ISP_SHOT_MODE_DRAMA 3 +#define EXT_ISP_SHOT_MODE_BEST_FACE 4 +#define EXT_ISP_SHOT_MODE_ERASER 5 +#define EXT_ISP_SHOT_MODE_PANORAMA 6 +#define EXT_ISP_SHOT_MODE_RICH_TONE_HDR 7 +#define EXT_ISP_SHOT_MODE_NIGHT 8 +#define EXT_ISP_SHOT_MODE_SOUND_SHOT 9 +#define EXT_ISP_SHOT_MODE_ANIMATED_PHOTO 10 +#define EXT_ISP_SHOT_MODE_SPORTS 11 + +struct atomisp_sp_arg { + enum atomisp_acc_arg_type type; /* Type of SP argument */ + void *value; /* Value of SP argument */ + unsigned int size; /* Size of SP argument */ +}; + +/* Acceleration API */ + +/* For CSS 1.0 only */ +struct atomisp_acc_fw_arg { + unsigned int fw_handle; + unsigned int index; + void __user *value; + size_t size; +}; + +/* + * Set arguments after first mapping with ATOMISP_IOC_ACC_S_MAPPED_ARG. + */ +struct atomisp_acc_s_mapped_arg { + unsigned int fw_handle; + __u32 memory; /* one of enum atomisp_acc_memory */ + size_t length; + unsigned long css_ptr; +}; + +struct atomisp_acc_fw_abort { + unsigned int fw_handle; + /* Timeout in us */ + unsigned int timeout; +}; + +struct atomisp_acc_fw_load { + unsigned int size; + unsigned int fw_handle; + void __user *data; +}; + +/* + * Load firmware to specified pipeline. + */ +struct atomisp_acc_fw_load_to_pipe { + __u32 flags; /* Flags, see below for valid values */ + unsigned int fw_handle; /* Handle, filled by kernel. */ + __u32 size; /* Firmware binary size */ + void __user *data; /* Pointer to firmware */ + __u32 type; /* Binary type */ + __u32 reserved[3]; /* Set to zero */ +}; +/* + * Set Senor run mode + */ +struct atomisp_s_runmode { + __u32 mode; +}; + +#define ATOMISP_ACC_FW_LOAD_FL_PREVIEW (1 << 0) +#define ATOMISP_ACC_FW_LOAD_FL_COPY (1 << 1) +#define ATOMISP_ACC_FW_LOAD_FL_VIDEO (1 << 2) +#define ATOMISP_ACC_FW_LOAD_FL_CAPTURE (1 << 3) +#define ATOMISP_ACC_FW_LOAD_FL_ACC (1 << 4) +#define ATOMISP_ACC_FW_LOAD_FL_ENABLE (1 << 16) + +#define ATOMISP_ACC_FW_LOAD_TYPE_NONE 0 /* Normal binary: don't use */ +#define ATOMISP_ACC_FW_LOAD_TYPE_OUTPUT 1 /* Stage on output */ +#define ATOMISP_ACC_FW_LOAD_TYPE_VIEWFINDER 2 /* Stage on viewfinder */ +#define ATOMISP_ACC_FW_LOAD_TYPE_STANDALONE 3 /* Stand-alone acceleration */ + +struct atomisp_acc_map { + __u32 flags; /* Flags, see list below */ + __u32 length; /* Length of data in bytes */ + void __user *user_ptr; /* Pointer into user space */ + unsigned long css_ptr; /* Pointer into CSS address space */ + __u32 reserved[4]; /* Set to zero */ +}; + +#define ATOMISP_MAP_FLAG_NOFLUSH 0x0001 /* Do not flush cache */ +#define ATOMISP_MAP_FLAG_CACHED 0x0002 /* Enable cache */ + +struct atomisp_acc_state { + __u32 flags; /* Flags, see list below */ +#define ATOMISP_STATE_FLAG_ENABLE ATOMISP_ACC_FW_LOAD_FL_ENABLE + unsigned int fw_handle; +}; + +struct atomisp_update_exposure { + unsigned int gain; + unsigned int digi_gain; + unsigned int update_gain; + unsigned int update_digi_gain; +}; + +/* + * V4L2 private internal data interface. + * ----------------------------------------------------------------------------- + * struct v4l2_private_int_data - request private data stored in video device + * internal memory. + * @size: sanity check to ensure userspace's buffer fits whole private data. + * If not, kernel will make partial copy (or nothing if @size == 0). + * @size is always corrected for the minimum necessary if IOCTL returns + * no error. + * @data: pointer to userspace buffer. + */ +struct v4l2_private_int_data { + __u32 size; + void __user *data; + __u32 reserved[2]; +}; + +enum atomisp_sensor_ae_bracketing_mode { + SENSOR_AE_BRACKETING_MODE_OFF = 0, + SENSOR_AE_BRACKETING_MODE_SINGLE, /* back to SW standby after bracketing */ + SENSOR_AE_BRACKETING_MODE_SINGLE_TO_STREAMING, /* back to normal streaming after bracketing */ + SENSOR_AE_BRACKETING_MODE_LOOP, /* continue AE bracketing in loop mode */ +}; + +struct atomisp_sensor_ae_bracketing_info { + unsigned int modes; /* bit mask to indicate supported modes */ + unsigned int lut_depth; +}; + +struct atomisp_sensor_ae_bracketing_lut_entry { + __u16 coarse_integration_time; + __u16 analog_gain; + __u16 digital_gain; +}; + +struct atomisp_sensor_ae_bracketing_lut { + struct atomisp_sensor_ae_bracketing_lut_entry *lut; + unsigned int lut_size; +}; + +/*Private IOCTLs for ISP */ +#define ATOMISP_IOC_G_XNR \ + _IOR('v', BASE_VIDIOC_PRIVATE + 0, int) +#define ATOMISP_IOC_S_XNR \ + _IOW('v', BASE_VIDIOC_PRIVATE + 0, int) +#define ATOMISP_IOC_G_NR \ + _IOR('v', BASE_VIDIOC_PRIVATE + 1, struct atomisp_nr_config) +#define ATOMISP_IOC_S_NR \ + _IOW('v', BASE_VIDIOC_PRIVATE + 1, struct atomisp_nr_config) +#define ATOMISP_IOC_G_TNR \ + _IOR('v', BASE_VIDIOC_PRIVATE + 2, struct atomisp_tnr_config) +#define ATOMISP_IOC_S_TNR \ + _IOW('v', BASE_VIDIOC_PRIVATE + 2, struct atomisp_tnr_config) +#define ATOMISP_IOC_G_HISTOGRAM \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 3, struct atomisp_histogram) +#define ATOMISP_IOC_S_HISTOGRAM \ + _IOW('v', BASE_VIDIOC_PRIVATE + 3, struct atomisp_histogram) +#define ATOMISP_IOC_G_BLACK_LEVEL_COMP \ + _IOR('v', BASE_VIDIOC_PRIVATE + 4, struct atomisp_ob_config) +#define ATOMISP_IOC_S_BLACK_LEVEL_COMP \ + _IOW('v', BASE_VIDIOC_PRIVATE + 4, struct atomisp_ob_config) +#define ATOMISP_IOC_G_EE \ + _IOR('v', BASE_VIDIOC_PRIVATE + 5, struct atomisp_ee_config) +#define ATOMISP_IOC_S_EE \ + _IOW('v', BASE_VIDIOC_PRIVATE + 5, struct atomisp_ee_config) +/* Digital Image Stabilization: + * 1. get dis statistics: reads DIS statistics from ISP (every frame) + * 2. set dis coefficients: set DIS filter coefficients (one time) + * 3. set dis motion vecotr: set motion vector (result of DIS, every frame) + */ +#define ATOMISP_IOC_G_DIS_STAT \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 6, struct atomisp_dis_statistics) + +#define ATOMISP_IOC_G_DVS2_BQ_RESOLUTIONS \ + _IOR('v', BASE_VIDIOC_PRIVATE + 6, struct atomisp_dvs2_bq_resolutions) + +#define ATOMISP_IOC_S_DIS_COEFS \ + _IOW('v', BASE_VIDIOC_PRIVATE + 6, struct atomisp_dis_coefficients) + +#define ATOMISP_IOC_S_DIS_VECTOR \ + _IOW('v', BASE_VIDIOC_PRIVATE + 6, struct atomisp_dvs_6axis_config) + +#define ATOMISP_IOC_G_3A_STAT \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 7, struct atomisp_3a_statistics) +#define ATOMISP_IOC_G_ISP_PARM \ + _IOR('v', BASE_VIDIOC_PRIVATE + 8, struct atomisp_parm) +#define ATOMISP_IOC_S_ISP_PARM \ + _IOW('v', BASE_VIDIOC_PRIVATE + 8, struct atomisp_parm) +#define ATOMISP_IOC_G_ISP_GAMMA \ + _IOR('v', BASE_VIDIOC_PRIVATE + 9, struct atomisp_gamma_table) +#define ATOMISP_IOC_S_ISP_GAMMA \ + _IOW('v', BASE_VIDIOC_PRIVATE + 9, struct atomisp_gamma_table) +#define ATOMISP_IOC_G_ISP_GDC_TAB \ + _IOR('v', BASE_VIDIOC_PRIVATE + 10, struct atomisp_morph_table) +#define ATOMISP_IOC_S_ISP_GDC_TAB \ + _IOW('v', BASE_VIDIOC_PRIVATE + 10, struct atomisp_morph_table) +#define ATOMISP_IOC_ISP_MAKERNOTE \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 11, struct atomisp_makernote_info) + +/* macc parameter control*/ +#define ATOMISP_IOC_G_ISP_MACC \ + _IOR('v', BASE_VIDIOC_PRIVATE + 12, struct atomisp_macc_config) +#define ATOMISP_IOC_S_ISP_MACC \ + _IOW('v', BASE_VIDIOC_PRIVATE + 12, struct atomisp_macc_config) + +/* Defect pixel detection & Correction */ +#define ATOMISP_IOC_G_ISP_BAD_PIXEL_DETECTION \ + _IOR('v', BASE_VIDIOC_PRIVATE + 13, struct atomisp_dp_config) +#define ATOMISP_IOC_S_ISP_BAD_PIXEL_DETECTION \ + _IOW('v', BASE_VIDIOC_PRIVATE + 13, struct atomisp_dp_config) + +/* False Color Correction */ +#define ATOMISP_IOC_G_ISP_FALSE_COLOR_CORRECTION \ + _IOR('v', BASE_VIDIOC_PRIVATE + 14, struct atomisp_de_config) +#define ATOMISP_IOC_S_ISP_FALSE_COLOR_CORRECTION \ + _IOW('v', BASE_VIDIOC_PRIVATE + 14, struct atomisp_de_config) + +/* ctc parameter control */ +#define ATOMISP_IOC_G_ISP_CTC \ + _IOR('v', BASE_VIDIOC_PRIVATE + 15, struct atomisp_ctc_table) +#define ATOMISP_IOC_S_ISP_CTC \ + _IOW('v', BASE_VIDIOC_PRIVATE + 15, struct atomisp_ctc_table) + +/* white balance Correction */ +#define ATOMISP_IOC_G_ISP_WHITE_BALANCE \ + _IOR('v', BASE_VIDIOC_PRIVATE + 16, struct atomisp_wb_config) +#define ATOMISP_IOC_S_ISP_WHITE_BALANCE \ + _IOW('v', BASE_VIDIOC_PRIVATE + 16, struct atomisp_wb_config) + +/* fpn table loading */ +#define ATOMISP_IOC_S_ISP_FPN_TABLE \ + _IOW('v', BASE_VIDIOC_PRIVATE + 17, struct v4l2_framebuffer) + +/* overlay image loading */ +#define ATOMISP_IOC_G_ISP_OVERLAY \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 18, struct atomisp_overlay) +#define ATOMISP_IOC_S_ISP_OVERLAY \ + _IOW('v', BASE_VIDIOC_PRIVATE + 18, struct atomisp_overlay) + +/* bcd driver bridge */ +#define ATOMISP_IOC_CAMERA_BRIDGE \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 19, struct atomisp_bc_video_package) + +/* Sensor resolution specific info for AE */ +#define ATOMISP_IOC_G_SENSOR_MODE_DATA \ + _IOR('v', BASE_VIDIOC_PRIVATE + 20, struct atomisp_sensor_mode_data) + +#define ATOMISP_IOC_S_EXPOSURE \ + _IOW('v', BASE_VIDIOC_PRIVATE + 21, struct atomisp_exposure) + +/* sensor calibration registers group */ +#define ATOMISP_IOC_G_SENSOR_CALIBRATION_GROUP \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 22, struct atomisp_calibration_group) + +/* white balance Correction */ +#define ATOMISP_IOC_G_3A_CONFIG \ + _IOR('v', BASE_VIDIOC_PRIVATE + 23, struct atomisp_3a_config) +#define ATOMISP_IOC_S_3A_CONFIG \ + _IOW('v', BASE_VIDIOC_PRIVATE + 23, struct atomisp_3a_config) + +/* Accelerate ioctls */ +#define ATOMISP_IOC_ACC_LOAD \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 24, struct atomisp_acc_fw_load) + +#define ATOMISP_IOC_ACC_UNLOAD \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 24, unsigned int) + +/* For CSS 1.0 only */ +#define ATOMISP_IOC_ACC_S_ARG \ + _IOW('v', BASE_VIDIOC_PRIVATE + 24, struct atomisp_acc_fw_arg) + +#define ATOMISP_IOC_ACC_START \ + _IOW('v', BASE_VIDIOC_PRIVATE + 24, unsigned int) + +#define ATOMISP_IOC_ACC_WAIT \ + _IOW('v', BASE_VIDIOC_PRIVATE + 25, unsigned int) + +#define ATOMISP_IOC_ACC_ABORT \ + _IOW('v', BASE_VIDIOC_PRIVATE + 25, struct atomisp_acc_fw_abort) + +#define ATOMISP_IOC_ACC_DESTAB \ + _IOW('v', BASE_VIDIOC_PRIVATE + 25, struct atomisp_acc_fw_arg) + +/* sensor OTP memory read */ +#define ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 26, struct v4l2_private_int_data) + +/* LCS (shading) table write */ +#define ATOMISP_IOC_S_ISP_SHD_TAB \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 27, struct atomisp_shading_table) + +/* Gamma Correction */ +#define ATOMISP_IOC_G_ISP_GAMMA_CORRECTION \ + _IOR('v', BASE_VIDIOC_PRIVATE + 28, struct atomisp_gc_config) + +#define ATOMISP_IOC_S_ISP_GAMMA_CORRECTION \ + _IOW('v', BASE_VIDIOC_PRIVATE + 28, struct atomisp_gc_config) + +/* motor internal memory read */ +#define ATOMISP_IOC_G_MOTOR_PRIV_INT_DATA \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 29, struct v4l2_private_int_data) + +/* + * Ioctls to map and unmap user buffers to CSS address space for acceleration. + * User fills fields length and user_ptr and sets other fields to zero, + * kernel may modify the flags and sets css_ptr. + */ +#define ATOMISP_IOC_ACC_MAP \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 30, struct atomisp_acc_map) + +/* User fills fields length, user_ptr, and css_ptr and zeroes other fields. */ +#define ATOMISP_IOC_ACC_UNMAP \ + _IOW('v', BASE_VIDIOC_PRIVATE + 30, struct atomisp_acc_map) + +#define ATOMISP_IOC_ACC_S_MAPPED_ARG \ + _IOW('v', BASE_VIDIOC_PRIVATE + 30, struct atomisp_acc_s_mapped_arg) + +#define ATOMISP_IOC_ACC_LOAD_TO_PIPE \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 31, struct atomisp_acc_fw_load_to_pipe) + +#define ATOMISP_IOC_S_PARAMETERS \ + _IOW('v', BASE_VIDIOC_PRIVATE + 32, struct atomisp_parameters) + +#define ATOMISP_IOC_S_CONT_CAPTURE_CONFIG \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 33, struct atomisp_cont_capture_conf) + +#define ATOMISP_IOC_G_METADATA \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 34, struct atomisp_metadata) + +#define ATOMISP_IOC_G_METADATA_BY_TYPE \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 34, struct atomisp_metadata_with_type) + +#define ATOMISP_IOC_EXT_ISP_CTRL \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 35, struct atomisp_ext_isp_ctrl) + +#define ATOMISP_IOC_EXP_ID_UNLOCK \ + _IOW('v', BASE_VIDIOC_PRIVATE + 36, int) + +#define ATOMISP_IOC_EXP_ID_CAPTURE \ + _IOW('v', BASE_VIDIOC_PRIVATE + 37, int) + +#define ATOMISP_IOC_S_ENABLE_DZ_CAPT_PIPE \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 38, unsigned int) + +#define ATOMISP_IOC_G_FORMATS_CONFIG \ + _IOR('v', BASE_VIDIOC_PRIVATE + 39, struct atomisp_formats_config) + +#define ATOMISP_IOC_S_FORMATS_CONFIG \ + _IOW('v', BASE_VIDIOC_PRIVATE + 39, struct atomisp_formats_config) + +#define ATOMISP_IOC_S_EXPOSURE_WINDOW \ + _IOW('v', BASE_VIDIOC_PRIVATE + 40, struct atomisp_ae_window) + +#define ATOMISP_IOC_S_ACC_STATE \ + _IOW('v', BASE_VIDIOC_PRIVATE + 41, struct atomisp_acc_state) + +#define ATOMISP_IOC_G_ACC_STATE \ + _IOR('v', BASE_VIDIOC_PRIVATE + 41, struct atomisp_acc_state) + +#define ATOMISP_IOC_INJECT_A_FAKE_EVENT \ + _IOW('v', BASE_VIDIOC_PRIVATE + 42, int) + +#define ATOMISP_IOC_G_SENSOR_AE_BRACKETING_INFO \ + _IOR('v', BASE_VIDIOC_PRIVATE + 43, struct atomisp_sensor_ae_bracketing_info) + +#define ATOMISP_IOC_S_SENSOR_AE_BRACKETING_MODE \ + _IOW('v', BASE_VIDIOC_PRIVATE + 43, unsigned int) + +#define ATOMISP_IOC_G_SENSOR_AE_BRACKETING_MODE \ + _IOR('v', BASE_VIDIOC_PRIVATE + 43, unsigned int) + +#define ATOMISP_IOC_S_SENSOR_AE_BRACKETING_LUT \ + _IOW('v', BASE_VIDIOC_PRIVATE + 43, struct atomisp_sensor_ae_bracketing_lut) + +#define ATOMISP_IOC_G_INVALID_FRAME_NUM \ + _IOR('v', BASE_VIDIOC_PRIVATE + 44, unsigned int) + +#define ATOMISP_IOC_S_ARRAY_RESOLUTION \ + _IOW('v', BASE_VIDIOC_PRIVATE + 45, struct atomisp_resolution) + +/* for depth mode sensor frame sync compensation */ +#define ATOMISP_IOC_G_DEPTH_SYNC_COMP \ + _IOR('v', BASE_VIDIOC_PRIVATE + 46, unsigned int) + +#define ATOMISP_IOC_S_SENSOR_EE_CONFIG \ + _IOW('v', BASE_VIDIOC_PRIVATE + 47, unsigned int) + +#define ATOMISP_IOC_S_SENSOR_RUNMODE \ + _IOW('v', BASE_VIDIOC_PRIVATE + 48, struct atomisp_s_runmode) + +#define ATOMISP_IOC_G_UPDATE_EXPOSURE \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 49, struct atomisp_update_exposure) + +/* + * Reserved ioctls. We have customer implementing it internally. + * We can't use both numbers to not cause ABI conflict. + * Anyway, those ioctls are hacks and not implemented by us: + * + * #define ATOMISP_IOC_G_SENSOR_REG \ + * _IOW('v', BASE_VIDIOC_PRIVATE + 55, struct atomisp_sensor_regs) + * #define ATOMISP_IOC_S_SENSOR_REG \ + * _IOW('v', BASE_VIDIOC_PRIVATE + 56, struct atomisp_sensor_regs) + */ + +/* ISP Private control IDs */ +#define V4L2_CID_ATOMISP_BAD_PIXEL_DETECTION \ + (V4L2_CID_PRIVATE_BASE + 0) +#define V4L2_CID_ATOMISP_POSTPROCESS_GDC_CAC \ + (V4L2_CID_PRIVATE_BASE + 1) +#define V4L2_CID_ATOMISP_VIDEO_STABLIZATION \ + (V4L2_CID_PRIVATE_BASE + 2) +#define V4L2_CID_ATOMISP_FIXED_PATTERN_NR \ + (V4L2_CID_PRIVATE_BASE + 3) +#define V4L2_CID_ATOMISP_FALSE_COLOR_CORRECTION \ + (V4L2_CID_PRIVATE_BASE + 4) +#define V4L2_CID_ATOMISP_LOW_LIGHT \ + (V4L2_CID_PRIVATE_BASE + 5) + +/* Camera class: + * Exposure, Flash and privacy (indicator) light controls, to be upstreamed */ +#define V4L2_CID_CAMERA_LASTP1 (V4L2_CID_CAMERA_CLASS_BASE + 1024) + +#define V4L2_CID_FOCAL_ABSOLUTE (V4L2_CID_CAMERA_LASTP1 + 0) +#define V4L2_CID_FNUMBER_ABSOLUTE (V4L2_CID_CAMERA_LASTP1 + 1) +#define V4L2_CID_FNUMBER_RANGE (V4L2_CID_CAMERA_LASTP1 + 2) + +/* Flash related CIDs, see also: + * http://linuxtv.org/downloads/v4l-dvb-apis/extended-controls.html\ + * #flash-controls */ + +/* Request a number of flash-exposed frames. The frame status can be + * found in the reserved field in the v4l2_buffer struct. */ +#define V4L2_CID_REQUEST_FLASH (V4L2_CID_CAMERA_LASTP1 + 3) +/* Query flash driver status. See enum atomisp_flash_status above. */ +#define V4L2_CID_FLASH_STATUS (V4L2_CID_CAMERA_LASTP1 + 5) +/* Set the flash mode (see enum atomisp_flash_mode) */ +#define V4L2_CID_FLASH_MODE (V4L2_CID_CAMERA_LASTP1 + 10) + +/* VCM slew control */ +#define V4L2_CID_VCM_SLEW (V4L2_CID_CAMERA_LASTP1 + 11) +/* VCM step time */ +#define V4L2_CID_VCM_TIMEING (V4L2_CID_CAMERA_LASTP1 + 12) + +/* Query Focus Status */ +#define V4L2_CID_FOCUS_STATUS (V4L2_CID_CAMERA_LASTP1 + 14) + +/* Query sensor's binning factor */ +#define V4L2_CID_BIN_FACTOR_HORZ (V4L2_CID_CAMERA_LASTP1 + 15) +#define V4L2_CID_BIN_FACTOR_VERT (V4L2_CID_CAMERA_LASTP1 + 16) + +/* number of frames to skip at stream start */ +#define V4L2_CID_G_SKIP_FRAMES (V4L2_CID_CAMERA_LASTP1 + 17) + +/* Query sensor's 2A status */ +#define V4L2_CID_2A_STATUS (V4L2_CID_CAMERA_LASTP1 + 18) +#define V4L2_2A_STATUS_AE_READY (1 << 0) +#define V4L2_2A_STATUS_AWB_READY (1 << 1) + +#define V4L2_CID_FMT_AUTO (V4L2_CID_CAMERA_LASTP1 + 19) + +#define V4L2_CID_RUN_MODE (V4L2_CID_CAMERA_LASTP1 + 20) +#define ATOMISP_RUN_MODE_VIDEO 1 +#define ATOMISP_RUN_MODE_STILL_CAPTURE 2 +#define ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE 3 +#define ATOMISP_RUN_MODE_PREVIEW 4 +#define ATOMISP_RUN_MODE_SDV 5 + +#define V4L2_CID_ENABLE_VFPP (V4L2_CID_CAMERA_LASTP1 + 21) +#define V4L2_CID_ATOMISP_CONTINUOUS_MODE (V4L2_CID_CAMERA_LASTP1 + 22) +#define V4L2_CID_ATOMISP_CONTINUOUS_RAW_BUFFER_SIZE \ + (V4L2_CID_CAMERA_LASTP1 + 23) +#define V4L2_CID_ATOMISP_CONTINUOUS_VIEWFINDER \ + (V4L2_CID_CAMERA_LASTP1 + 24) + +#define V4L2_CID_VFPP (V4L2_CID_CAMERA_LASTP1 + 25) +#define ATOMISP_VFPP_ENABLE 0 +#define ATOMISP_VFPP_DISABLE_SCALER 1 +#define ATOMISP_VFPP_DISABLE_LOWLAT 2 + +/* Query real flash status register value */ +#define V4L2_CID_FLASH_STATUS_REGISTER (V4L2_CID_CAMERA_LASTP1 + 26) + +#define V4L2_CID_START_ZSL_CAPTURE (V4L2_CID_CAMERA_LASTP1 + 28) +/* Lock and unlock raw buffer */ +#define V4L2_CID_ENABLE_RAW_BUFFER_LOCK (V4L2_CID_CAMERA_LASTP1 + 29) + +#define V4L2_CID_DEPTH_MODE (V4L2_CID_CAMERA_LASTP1 + 30) + +#define V4L2_CID_EXPOSURE_ZONE_NUM (V4L2_CID_CAMERA_LASTP1 + 31) +/* Disable digital zoom */ +#define V4L2_CID_DISABLE_DZ (V4L2_CID_CAMERA_LASTP1 + 32) + +#define V4L2_CID_TEST_PATTERN_COLOR_R (V4L2_CID_CAMERA_LASTP1 + 33) +#define V4L2_CID_TEST_PATTERN_COLOR_GR (V4L2_CID_CAMERA_LASTP1 + 34) +#define V4L2_CID_TEST_PATTERN_COLOR_GB (V4L2_CID_CAMERA_LASTP1 + 35) +#define V4L2_CID_TEST_PATTERN_COLOR_B (V4L2_CID_CAMERA_LASTP1 + 36) + +#define V4L2_CID_ATOMISP_SELECT_ISP_VERSION (V4L2_CID_CAMERA_LASTP1 + 38) + +#define V4L2_BUF_FLAG_BUFFER_INVALID 0x0400 +#define V4L2_BUF_FLAG_BUFFER_VALID 0x0800 + +#define V4L2_BUF_TYPE_VIDEO_CAPTURE_ION (V4L2_BUF_TYPE_PRIVATE + 1024) + +#define V4L2_EVENT_ATOMISP_3A_STATS_READY (V4L2_EVENT_PRIVATE_START + 1) +#define V4L2_EVENT_ATOMISP_METADATA_READY (V4L2_EVENT_PRIVATE_START + 2) +#define V4L2_EVENT_ATOMISP_RAW_BUFFERS_ALLOC_DONE (V4L2_EVENT_PRIVATE_START + 3) +#define V4L2_EVENT_ATOMISP_ACC_COMPLETE (V4L2_EVENT_PRIVATE_START + 4) +#define V4L2_EVENT_ATOMISP_PAUSE_BUFFER (V4L2_EVENT_PRIVATE_START + 5) +#define V4L2_EVENT_ATOMISP_CSS_RESET (V4L2_EVENT_PRIVATE_START + 6) +/* Nonstandard color effects for V4L2_CID_COLORFX */ +enum { + V4L2_COLORFX_SKIN_WHITEN_LOW = 1001, + V4L2_COLORFX_SKIN_WHITEN_HIGH = 1002, + V4L2_COLORFX_WARM = 1003, + V4L2_COLORFX_COLD = 1004, + V4L2_COLORFX_WASHED = 1005, + V4L2_COLORFX_RED = 1006, + V4L2_COLORFX_GREEN = 1007, + V4L2_COLORFX_BLUE = 1008, + V4L2_COLORFX_PINK = 1009, + V4L2_COLORFX_YELLOW = 1010, + V4L2_COLORFX_PURPLE = 1011, +}; + +#endif /* _ATOM_ISP_H */ +#endif /* CSS15*/ diff --git a/drivers/staging/media/atomisp/include/linux/atomisp_gmin_platform.h b/drivers/staging/media/atomisp/include/linux/atomisp_gmin_platform.h new file mode 100644 index 0000000000000000000000000000000000000000..623e7e2b2cd625e590980a3ce8fa7c24621c4007 --- /dev/null +++ b/drivers/staging/media/atomisp/include/linux/atomisp_gmin_platform.h @@ -0,0 +1,40 @@ +/* + * Support for Intel MID SoC Camera Imaging ISP subsystem. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#ifndef ATOMISP_GMIN_PLATFORM_H_ +#define ATOMISP_GMIN_PLATFORM_H_ + +#include + +const struct atomisp_camera_caps *atomisp_get_default_camera_caps(void); +const struct atomisp_platform_data *atomisp_get_platform_data(void); +const struct camera_af_platform_data *camera_get_af_platform_data(void); +int atomisp_register_i2c_module(struct v4l2_subdev *subdev, + struct camera_sensor_platform_data *plat_data, + enum intel_v4l2_subdev_type type); +struct v4l2_subdev *atomisp_gmin_find_subdev(struct i2c_adapter *adapter, + struct i2c_board_info *board_info); +int atomisp_gmin_remove_subdev(struct v4l2_subdev *sd); +int gmin_get_config_var(struct device *dev, const char *var, char *out, size_t *out_len); +int gmin_get_var_int(struct device *dev, const char *var, int def); +int camera_sensor_csi(struct v4l2_subdev *sd, u32 port, + u32 lanes, u32 format, u32 bayer_order, int flag); +struct camera_sensor_platform_data *gmin_camera_platform_data( + struct v4l2_subdev *subdev, + enum atomisp_input_format csi_format, + enum atomisp_bayer_order csi_bayer); + +int atomisp_gmin_register_vcm_control(struct camera_vcm_control *); + +#endif diff --git a/drivers/staging/media/atomisp/include/linux/atomisp_platform.h b/drivers/staging/media/atomisp/include/linux/atomisp_platform.h new file mode 100644 index 0000000000000000000000000000000000000000..dbac2b777dad0c3a01953110a5831672dcda4f50 --- /dev/null +++ b/drivers/staging/media/atomisp/include/linux/atomisp_platform.h @@ -0,0 +1,262 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#ifndef ATOMISP_PLATFORM_H_ +#define ATOMISP_PLATFORM_H_ + +#include +#include +#include +#include "atomisp.h" + +#define MAX_SENSORS_PER_PORT 4 +#define MAX_STREAMS_PER_CHANNEL 2 + +#define CAMERA_MODULE_ID_LEN 64 + +enum atomisp_bayer_order { + atomisp_bayer_order_grbg, + atomisp_bayer_order_rggb, + atomisp_bayer_order_bggr, + atomisp_bayer_order_gbrg +}; + +enum atomisp_input_stream_id { + ATOMISP_INPUT_STREAM_GENERAL = 0, + ATOMISP_INPUT_STREAM_CAPTURE = 0, + ATOMISP_INPUT_STREAM_POSTVIEW, + ATOMISP_INPUT_STREAM_PREVIEW, + ATOMISP_INPUT_STREAM_VIDEO, + ATOMISP_INPUT_STREAM_NUM +}; + +enum atomisp_input_format { + ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY,/* 8 bits per subpixel (legacy) */ + ATOMISP_INPUT_FORMAT_YUV420_8, /* 8 bits per subpixel */ + ATOMISP_INPUT_FORMAT_YUV420_10,/* 10 bits per subpixel */ + ATOMISP_INPUT_FORMAT_YUV420_16,/* 16 bits per subpixel */ + ATOMISP_INPUT_FORMAT_YUV422_8, /* UYVY..UVYV, 8 bits per subpixel */ + ATOMISP_INPUT_FORMAT_YUV422_10,/* UYVY..UVYV, 10 bits per subpixel */ + ATOMISP_INPUT_FORMAT_YUV422_16,/* UYVY..UVYV, 16 bits per subpixel */ + ATOMISP_INPUT_FORMAT_RGB_444, /* BGR..BGR, 4 bits per subpixel */ + ATOMISP_INPUT_FORMAT_RGB_555, /* BGR..BGR, 5 bits per subpixel */ + ATOMISP_INPUT_FORMAT_RGB_565, /* BGR..BGR, 5 bits B and R, 6 bits G */ + ATOMISP_INPUT_FORMAT_RGB_666, /* BGR..BGR, 6 bits per subpixel */ + ATOMISP_INPUT_FORMAT_RGB_888, /* BGR..BGR, 8 bits per subpixel */ + ATOMISP_INPUT_FORMAT_RAW_6, /* RAW data, 6 bits per pixel */ + ATOMISP_INPUT_FORMAT_RAW_7, /* RAW data, 7 bits per pixel */ + ATOMISP_INPUT_FORMAT_RAW_8, /* RAW data, 8 bits per pixel */ + ATOMISP_INPUT_FORMAT_RAW_10, /* RAW data, 10 bits per pixel */ + ATOMISP_INPUT_FORMAT_RAW_12, /* RAW data, 12 bits per pixel */ + ATOMISP_INPUT_FORMAT_RAW_14, /* RAW data, 14 bits per pixel */ + ATOMISP_INPUT_FORMAT_RAW_16, /* RAW data, 16 bits per pixel */ + ATOMISP_INPUT_FORMAT_BINARY_8, /* Binary byte stream. */ + + /* CSI2-MIPI specific format: Generic short packet data. It is used to + * keep the timing information for the opening/closing of shutters, + * triggering of flashes and etc. + */ + ATOMISP_INPUT_FORMAT_GENERIC_SHORT1, /* Generic Short Packet Code 1 */ + ATOMISP_INPUT_FORMAT_GENERIC_SHORT2, /* Generic Short Packet Code 2 */ + ATOMISP_INPUT_FORMAT_GENERIC_SHORT3, /* Generic Short Packet Code 3 */ + ATOMISP_INPUT_FORMAT_GENERIC_SHORT4, /* Generic Short Packet Code 4 */ + ATOMISP_INPUT_FORMAT_GENERIC_SHORT5, /* Generic Short Packet Code 5 */ + ATOMISP_INPUT_FORMAT_GENERIC_SHORT6, /* Generic Short Packet Code 6 */ + ATOMISP_INPUT_FORMAT_GENERIC_SHORT7, /* Generic Short Packet Code 7 */ + ATOMISP_INPUT_FORMAT_GENERIC_SHORT8, /* Generic Short Packet Code 8 */ + + /* CSI2-MIPI specific format: YUV data. + */ + ATOMISP_INPUT_FORMAT_YUV420_8_SHIFT, /* YUV420 8-bit (Chroma Shifted + Pixel Sampling) */ + ATOMISP_INPUT_FORMAT_YUV420_10_SHIFT, /* YUV420 8-bit (Chroma Shifted + Pixel Sampling) */ + + /* CSI2-MIPI specific format: Generic long packet data + */ + ATOMISP_INPUT_FORMAT_EMBEDDED, /* Embedded 8-bit non Image Data */ + + /* CSI2-MIPI specific format: User defined byte-based data. For example, + * the data transmitter (e.g. the SoC sensor) can keep the JPEG data as + * the User Defined Data Type 4 and the MPEG data as the + * User Defined Data Type 7. + */ + ATOMISP_INPUT_FORMAT_USER_DEF1, /* User defined 8-bit data type 1 */ + ATOMISP_INPUT_FORMAT_USER_DEF2, /* User defined 8-bit data type 2 */ + ATOMISP_INPUT_FORMAT_USER_DEF3, /* User defined 8-bit data type 3 */ + ATOMISP_INPUT_FORMAT_USER_DEF4, /* User defined 8-bit data type 4 */ + ATOMISP_INPUT_FORMAT_USER_DEF5, /* User defined 8-bit data type 5 */ + ATOMISP_INPUT_FORMAT_USER_DEF6, /* User defined 8-bit data type 6 */ + ATOMISP_INPUT_FORMAT_USER_DEF7, /* User defined 8-bit data type 7 */ + ATOMISP_INPUT_FORMAT_USER_DEF8, /* User defined 8-bit data type 8 */ +}; + +enum intel_v4l2_subdev_type { + RAW_CAMERA = 1, + SOC_CAMERA = 2, + CAMERA_MOTOR = 3, + LED_FLASH = 4, + XENON_FLASH = 5, + FILE_INPUT = 6, + TEST_PATTERN = 7, +}; + +struct intel_v4l2_subdev_id { + char name[17]; + enum intel_v4l2_subdev_type type; + enum atomisp_camera_port port; +}; + +struct intel_v4l2_subdev_i2c_board_info { + struct i2c_board_info board_info; + int i2c_adapter_id; +}; + +struct intel_v4l2_subdev_table { + struct intel_v4l2_subdev_i2c_board_info v4l2_subdev; + enum intel_v4l2_subdev_type type; + enum atomisp_camera_port port; + struct v4l2_subdev *subdev; +}; + +struct atomisp_platform_data { + struct intel_v4l2_subdev_table *subdevs; +}; + +/* Describe the capacities of one single sensor. */ +struct atomisp_sensor_caps { + /* The number of streams this sensor can output. */ + int stream_num; + bool is_slave; +}; + +/* Describe the capacities of sensors connected to one camera port. */ +struct atomisp_camera_caps { + /* The number of sensors connected to this camera port. */ + int sensor_num; + /* The capacities of each sensor. */ + struct atomisp_sensor_caps sensor[MAX_SENSORS_PER_PORT]; + /* Define whether stream control is required for multiple streams. */ + bool multi_stream_ctrl; +}; + +/* + * Sensor of external ISP can send multiple steams with different mipi data + * type in the same virtual channel. This information needs to come from the + * sensor or external ISP + */ +struct atomisp_isys_config_info { + u8 input_format; + u16 width; + u16 height; +}; + +struct atomisp_input_stream_info { + enum atomisp_input_stream_id stream; + u8 enable; + /* Sensor driver fills ch_id with the id + of the virtual channel. */ + u8 ch_id; + /* Tells how many streams in this virtual channel. If 0 ignore rest + * and the input format will be from mipi_info */ + u8 isys_configs; + /* + * if more isys_configs is more than 0, sensor needs to configure the + * input format differently. width and height can be 0. If width and + * height is not zero, then the corresponsing data needs to be set + */ + struct atomisp_isys_config_info isys_info[MAX_STREAMS_PER_CHANNEL]; +}; + +struct camera_vcm_control; +struct camera_vcm_ops { + int (*power_up)(struct v4l2_subdev *sd, struct camera_vcm_control *vcm); + int (*power_down)(struct v4l2_subdev *sd, + struct camera_vcm_control *vcm); + int (*queryctrl)(struct v4l2_subdev *sd, struct v4l2_queryctrl *qc, + struct camera_vcm_control *vcm); + int (*g_ctrl)(struct v4l2_subdev *sd, struct v4l2_control *ctrl, + struct camera_vcm_control *vcm); + int (*s_ctrl)(struct v4l2_subdev *sd, struct v4l2_control *ctrl, + struct camera_vcm_control *vcm); +}; + +struct camera_vcm_control { + char camera_module[CAMERA_MODULE_ID_LEN]; + struct camera_vcm_ops *ops; + struct list_head list; +}; + +struct camera_sensor_platform_data { + int (*gpio_ctrl)(struct v4l2_subdev *subdev, int flag); + int (*flisclk_ctrl)(struct v4l2_subdev *subdev, int flag); + int (*power_ctrl)(struct v4l2_subdev *subdev, int flag); + int (*csi_cfg)(struct v4l2_subdev *subdev, int flag); + bool (*low_fps)(void); + int (*platform_init)(struct i2c_client *); + int (*platform_deinit)(void); + char *(*msr_file_name)(void); + struct atomisp_camera_caps *(*get_camera_caps)(void); + int (*gpio_intr_ctrl)(struct v4l2_subdev *subdev); + + /* New G-Min power and GPIO interface, replaces + * power/gpio_ctrl with methods to control individual + * lines as implemented on all known camera modules. */ + int (*gpio0_ctrl)(struct v4l2_subdev *subdev, int on); + int (*gpio1_ctrl)(struct v4l2_subdev *subdev, int on); + int (*v1p8_ctrl)(struct v4l2_subdev *subdev, int on); + int (*v2p8_ctrl)(struct v4l2_subdev *subdev, int on); + int (*v1p2_ctrl)(struct v4l2_subdev *subdev, int on); + struct camera_vcm_control * (*get_vcm_ctrl)(struct v4l2_subdev *subdev, + char *module_id); +}; + +struct camera_af_platform_data { + int (*power_ctrl)(struct v4l2_subdev *subdev, int flag); +}; + +const struct camera_af_platform_data *camera_get_af_platform_data(void); + +struct camera_mipi_info { + enum atomisp_camera_port port; + unsigned int num_lanes; + enum atomisp_input_format input_format; + enum atomisp_bayer_order raw_bayer_order; + struct atomisp_sensor_mode_data data; + enum atomisp_input_format metadata_format; + uint32_t metadata_width; + uint32_t metadata_height; + const uint32_t *metadata_effective_width; +}; + +extern const struct atomisp_platform_data *atomisp_get_platform_data(void); +extern const struct atomisp_camera_caps *atomisp_get_default_camera_caps(void); + +/* API from old platform_camera.h, new CPUID implementation */ +#define __IS_SOC(x) (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL && \ + boot_cpu_data.x86 == 6 && \ + boot_cpu_data.x86_model == x) + +#define IS_MFLD __IS_SOC(0x27) +#define IS_BYT __IS_SOC(0x37) +#define IS_CHT __IS_SOC(0x4C) +#define IS_MOFD __IS_SOC(0x5A) + +#endif /* ATOMISP_PLATFORM_H_ */ diff --git a/drivers/staging/media/atomisp/include/linux/intel_mid_pm.h b/drivers/staging/media/atomisp/include/linux/intel_mid_pm.h new file mode 100644 index 0000000000000000000000000000000000000000..b084d716a2189a96b5436714015e920dc967ab5b --- /dev/null +++ b/drivers/staging/media/atomisp/include/linux/intel_mid_pm.h @@ -0,0 +1,233 @@ +/* + * intel_mid_pm.h + * Copyright (c) 2010, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + */ +#include + +#ifndef INTEL_MID_PM_H +#define INTEL_MID_PM_H + +#include +#include +#include + + +/* Chip ID of Intel Atom SOC*/ +#define INTEL_ATOM_MRST 0x26 +#define INTEL_ATOM_MFLD 0x27 +#define INTEL_ATOM_CLV 0x35 +#define INTEL_ATOM_MRFLD 0x4a +#define INTEL_ATOM_BYT 0x37 +#define INTEL_ATOM_MOORFLD 0x5a +#define INTEL_ATOM_CHT 0x4c + +static inline int platform_is(u8 model) +{ + return boot_cpu_data.x86_model == model; +} + +/* Register Type definitions */ +#define OSPM_REG_TYPE 0x0 +#define APM_REG_TYPE 0x1 +#define OSPM_MAX_POWER_ISLANDS 16 +#define OSPM_ISLAND_UP 0x0 +#define OSPM_ISLAND_DOWN 0x1 +/*Soft reset*/ +#define OSPM_ISLAND_SR 0x2 + +/* North complex power islands definitions for APM block*/ +#define APM_GRAPHICS_ISLAND 0x1 +#define APM_VIDEO_DEC_ISLAND 0x2 +#define APM_VIDEO_ENC_ISLAND 0x4 +#define APM_GL3_CACHE_ISLAND 0x8 +#define APM_ISP_ISLAND 0x10 +#define APM_IPH_ISLAND 0x20 + +/* North complex power islands definitions for OSPM block*/ +#define OSPM_DISPLAY_A_ISLAND 0x2 +#define OSPM_DISPLAY_B_ISLAND 0x80 +#define OSPM_DISPLAY_C_ISLAND 0x100 +#define OSPM_MIPI_ISLAND 0x200 + +/* North Complex power islands definitions for Tangier */ +#define TNG_ISP_ISLAND 0x1 +/* North Complex Register definitions for Tangier */ +#define ISP_SS_PM0 0x39 + +#define C4_STATE_IDX 3 +#define C6_STATE_IDX 4 +#define S0I1_STATE_IDX 5 +#define LPMP3_STATE_IDX 6 +#define S0I3_STATE_IDX 7 + +#define C4_HINT (0x30) +#define C6_HINT (0x52) + +#define CSTATE_EXIT_LATENCY_C1 1 +#define CSTATE_EXIT_LATENCY_C2 20 +#define CSTATE_EXIT_LATENCY_C4 100 +#define CSTATE_EXIT_LATENCY_C6 140 +#define CSTATE_EXIT_LATENCY_C7 1200 + +/* Since entry latency is substantial + * put exit_latency = entry+exit latency + */ +#ifdef CONFIG_REMOVEME_INTEL_ATOM_MRFLD_POWER +#define CSTATE_EXIT_LATENCY_S0i1 1200 +#define CSTATE_EXIT_LATENCY_S0i2 2000 +#define CSTATE_EXIT_LATENCY_S0i3 10000 +#else +#define CSTATE_EXIT_LATENCY_LPMP3 1040 +#define CSTATE_EXIT_LATENCY_S0i1 1040 +#define CSTATE_EXIT_LATENCY_S0i3 2800 +#endif +#define BYT_S0I1_STATE 0x60 +#define BYT_S0I2_STATE 0x62 +#define BYT_LPMP3_STATE 0x62 +#define BYT_S0I3_STATE 0x64 + +enum s3_parts { + PROC_FRZ, + DEV_SUS, + NB_CPU_OFF, + NB_CPU_ON, + DEV_RES, + PROC_UNFRZ, + MAX_S3_PARTS +}; + +#ifdef CONFIG_ATOM_SOC_POWER +#define LOG_PMU_EVENTS + +/* Error codes for pmu */ +#define PMU_SUCCESS 0 +#define PMU_FAILED -1 +#define PMU_BUSY_STATUS 0 +#define PMU_MODE_ID 1 +#define SET_MODE 1 +#define SET_AOAC_S0i1 2 +#define SET_AOAC_S0i3 3 +#define SET_LPAUDIO 4 +#define SET_AOAC_S0i2 7 + +#ifdef CONFIG_REMOVEME_INTEL_ATOM_MRFLD_POWER +#define MID_S0I1_STATE 0x60 +#define MID_S0I2_STATE 0x62 +#define MID_LPMP3_STATE 0x62 +#define MID_S0I3_STATE 0x64 +#else +#define MID_S0I1_STATE 0x1 +#define MID_LPMP3_STATE 0x3 +#define MID_S0I2_STATE 0x7 +#define MID_S0I3_STATE 0x7 +#endif + +#define MID_S0IX_STATE 0xf +#define MID_S3_STATE 0x1f +#define MID_FAST_ON_OFF_STATE 0x3f + +/* combinations */ +#define MID_LPI1_STATE 0x1f +#define MID_LPI3_STATE 0x7f +#define MID_I1I3_STATE 0xff + +#define REMOVE_LP_FROM_LPIX 4 + +/* Power number for MID_POWER */ +#define C0_POWER_USAGE 450 +#define C6_POWER_USAGE 200 +#define LPMP3_POWER_USAGE 130 +#define S0I1_POWER_USAGE 50 +#define S0I3_POWER_USAGE 31 + +extern unsigned int enable_s3; +extern unsigned int enable_s0ix; + +extern void pmu_s0ix_demotion_stat(int req_state, int grant_state); +extern unsigned int pmu_get_new_cstate(unsigned int cstate, int *index); +extern int get_target_platform_state(unsigned long *eax); +extern int mid_s0ix_enter(int); +extern int pmu_set_devices_in_d0i0(void); +extern int pmu_pci_set_power_state(struct pci_dev *pdev, pci_power_t state); +extern pci_power_t pmu_pci_choose_state(struct pci_dev *pdev); + +extern void time_stamp_in_suspend_flow(int mark, bool start); +extern void time_stamp_for_sleep_state_latency(int sleep_state, + bool start, bool entry); +extern int mid_state_to_sys_state(int mid_state); +extern void pmu_power_off(void); +extern void pmu_set_s0ix_complete(void); +extern bool pmu_is_s0ix_in_progress(void); +extern int pmu_nc_set_power_state + (int islands, int state_type, int reg_type); +extern int pmu_nc_get_power_state(int island, int reg_type); +extern int pmu_set_emmc_to_d0i0_atomic(void); + +#ifdef LOG_PMU_EVENTS +extern void pmu_log_ipc(u32 command); +extern void pmu_log_ipc_irq(void); +#else +static inline void pmu_log_ipc(u32 command) { return; }; +static inline void pmu_log_ipc_irq(void) { return; }; +#endif +extern void dump_nc_power_history(void); + +extern bool mid_pmu_is_wake_source(u32 lss_number); + +extern void (*nc_report_power_state) (u32, int); +#else + +/* + * If CONFIG_ATOM_SOC_POWER is not defined + * fall back to C6 + */ + +#define MID_S0I1_STATE C6_HINT +#define MID_LPMP3_STATE C6_HINT +#define MID_S0I3_STATE C6_HINT +#define MID_S3_STATE C6_HINT +#define MID_FAST_ON_OFF_STATE C6_HINT + +/* Power usage unknown if MID_POWER not defined */ +#define C0_POWER_USAGE 0 +#define C6_POWER_USAGE 0 +#define LPMP3_POWER_USAGE 0 +#define S0I1_POWER_USAGE 0 +#define S0I3_POWER_USAGE 0 + +#define TEMP_DTS_ID 43 + +static inline int pmu_nc_set_power_state + (int islands, int state_type, int reg_type) { return 0; } +static inline int pmu_nc_get_power_state(int island, int reg_type) { return 0; } + +static inline void pmu_set_s0ix_complete(void) { return; } +static inline bool pmu_is_s0ix_in_progress(void) { return false; }; +static inline unsigned int pmu_get_new_cstate + (unsigned int cstate, int *index) { return cstate; }; + +/*returns function not implemented*/ +static inline void time_stamp_in_suspend_flow(int mark, bool start) {} +static inline void time_stamp_for_sleep_state_latency(int sleep_state, + bool start, bool entry) {} +static inline int mid_state_to_sys_state(int mid_state) { return 0; } + +static inline int pmu_set_devices_in_d0i0(void) { return 0; } +static inline void pmu_log_ipc(u32 command) { return; }; +static inline void pmu_log_ipc_irq(void) { return; }; +static inline int pmu_set_emmc_to_d0i0_atomic(void) { return -ENOSYS; } +static inline void pmu_power_off(void) { return; } +static inline bool mid_pmu_is_wake_source(u32 lss_number) { return false; } +#endif /* #ifdef CONFIG_ATOM_SOC_POWER */ + +#endif /* #ifndef INTEL_MID_PM_H */ diff --git a/drivers/staging/media/atomisp/include/linux/libmsrlisthelper.h b/drivers/staging/media/atomisp/include/linux/libmsrlisthelper.h new file mode 100644 index 0000000000000000000000000000000000000000..589f4eae38ca6334410fdf85b3832614a098413b --- /dev/null +++ b/drivers/staging/media/atomisp/include/linux/libmsrlisthelper.h @@ -0,0 +1,32 @@ +/* + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#ifndef __LIBMSRLISTHELPER_H__ +#define __LIBMSRLISTHELPER_H__ + +struct i2c_client; +struct firmware; + +extern int load_msr_list(struct i2c_client *client, char *path, + const struct firmware **fw); +extern int apply_msr_data(struct i2c_client *client, const struct firmware *fw); +extern void release_msr_list(struct i2c_client *client, + const struct firmware *fw); + + +#endif /* ifndef __LIBMSRLISTHELPER_H__ */ diff --git a/drivers/staging/media/atomisp/include/linux/vlv2_plat_clock.h b/drivers/staging/media/atomisp/include/linux/vlv2_plat_clock.h new file mode 100644 index 0000000000000000000000000000000000000000..ed709bdd6498486040f68199dafc39400590780d --- /dev/null +++ b/drivers/staging/media/atomisp/include/linux/vlv2_plat_clock.h @@ -0,0 +1,30 @@ +/* + * vlv2_plat_clock.h + * + * Copyright (C) 2013 Intel Corp + * Author: Asutosh Pathak + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +#ifndef __VLV2_PLAT_CLOCK_H +#define __VLV2_PLAT_CLOCK_H + +int vlv2_plat_set_clock_freq(int clock_num, int freq_type); +int vlv2_plat_get_clock_freq(int clock_num); + +int vlv2_plat_configure_clock(int clock_num, u32 conf); +int vlv2_plat_get_clock_status(int clock_num); + +#endif /* __VLV2_PLAT_CLOCK_H */ diff --git a/drivers/staging/media/atomisp/include/media/lm3554.h b/drivers/staging/media/atomisp/include/media/lm3554.h new file mode 100644 index 0000000000000000000000000000000000000000..7d6a8c05dd5286efc0cdbe174fd3957f4adf2f7d --- /dev/null +++ b/drivers/staging/media/atomisp/include/media/lm3554.h @@ -0,0 +1,136 @@ +/* + * include/media/lm3554.h + * + * Copyright (c) 2010-2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#ifndef _LM3554_H_ +#define _LM3554_H_ + +#include +#include + +#define LM3554_NAME "lm3554" +#define LM3554_ID 3554 + +#define v4l2_queryctrl_entry_integer(_id, _name,\ + _minimum, _maximum, _step, \ + _default_value, _flags) \ + {\ + .id = (_id), \ + .type = V4L2_CTRL_TYPE_INTEGER, \ + .name = _name, \ + .minimum = (_minimum), \ + .maximum = (_maximum), \ + .step = (_step), \ + .default_value = (_default_value),\ + .flags = (_flags),\ + } +#define v4l2_queryctrl_entry_boolean(_id, _name,\ + _default_value, _flags) \ + {\ + .id = (_id), \ + .type = V4L2_CTRL_TYPE_BOOLEAN, \ + .name = _name, \ + .minimum = 0, \ + .maximum = 1, \ + .step = 1, \ + .default_value = (_default_value),\ + .flags = (_flags),\ + } + +#define s_ctrl_id_entry_integer(_id, _name, \ + _minimum, _maximum, _step, \ + _default_value, _flags, \ + _s_ctrl, _g_ctrl) \ + {\ + .qc = v4l2_queryctrl_entry_integer(_id, _name,\ + _minimum, _maximum, _step,\ + _default_value, _flags), \ + .s_ctrl = _s_ctrl, \ + .g_ctrl = _g_ctrl, \ + } + +#define s_ctrl_id_entry_boolean(_id, _name, \ + _default_value, _flags, \ + _s_ctrl, _g_ctrl) \ + {\ + .qc = v4l2_queryctrl_entry_boolean(_id, _name,\ + _default_value, _flags), \ + .s_ctrl = _s_ctrl, \ + .g_ctrl = _g_ctrl, \ + } + +/* Value settings for Flash Time-out Duration*/ +#define LM3554_DEFAULT_TIMEOUT 512U +#define LM3554_MIN_TIMEOUT 32U +#define LM3554_MAX_TIMEOUT 1024U +#define LM3554_TIMEOUT_STEPSIZE 32U + +/* Flash modes */ +#define LM3554_MODE_SHUTDOWN 0 +#define LM3554_MODE_INDICATOR 1 +#define LM3554_MODE_TORCH 2 +#define LM3554_MODE_FLASH 3 + +/* timer delay time */ +#define LM3554_TIMER_DELAY 5 + +/* Percentage <-> value macros */ +#define LM3554_MIN_PERCENT 0U +#define LM3554_MAX_PERCENT 100U +#define LM3554_CLAMP_PERCENTAGE(val) \ + clamp(val, LM3554_MIN_PERCENT, LM3554_MAX_PERCENT) + +#define LM3554_VALUE_TO_PERCENT(v, step) (((((unsigned long)(v))*(step))+50)/100) +#define LM3554_PERCENT_TO_VALUE(p, step) (((((unsigned long)(p))*100)+(step>>1))/(step)) + +/* Product specific limits + * TODO: get these from platform data */ +#define LM3554_FLASH_MAX_LVL 0x0F /* 1191mA */ + +/* Flash brightness, input is percentage, output is [0..15] */ +#define LM3554_FLASH_STEP \ + ((100ul*(LM3554_MAX_PERCENT)+((LM3554_FLASH_MAX_LVL)>>1))/((LM3554_FLASH_MAX_LVL))) +#define LM3554_FLASH_DEFAULT_BRIGHTNESS \ + LM3554_VALUE_TO_PERCENT(13, LM3554_FLASH_STEP) + +/* Torch brightness, input is percentage, output is [0..7] */ +#define LM3554_TORCH_STEP 1250 +#define LM3554_TORCH_DEFAULT_BRIGHTNESS \ + LM3554_VALUE_TO_PERCENT(2, LM3554_TORCH_STEP) + +/* Indicator brightness, input is percentage, output is [0..3] */ +#define LM3554_INDICATOR_STEP 2500 +#define LM3554_INDICATOR_DEFAULT_BRIGHTNESS \ + LM3554_VALUE_TO_PERCENT(1, LM3554_INDICATOR_STEP) + +/* + * lm3554_platform_data - Flash controller platform data + */ +struct lm3554_platform_data { + int gpio_torch; + int gpio_strobe; + int gpio_reset; + + unsigned int current_limit; + unsigned int envm_tx2; + unsigned int tx2_polarity; +}; + +#endif /* _LM3554_H_ */ + diff --git a/drivers/staging/media/atomisp/include/media/lm3642.h b/drivers/staging/media/atomisp/include/media/lm3642.h new file mode 100644 index 0000000000000000000000000000000000000000..545d95763335c973b900b9d4be41761bdce5d0a6 --- /dev/null +++ b/drivers/staging/media/atomisp/include/media/lm3642.h @@ -0,0 +1,153 @@ +/* + * include/media/lm3642.h + * + * Copyright (c) 2010-2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. + */ + +#ifndef _LM3642_H_ +#define _LM3642_H_ + +#include +#include + +#define LM3642_NAME "lm3642" +#define LM3642_ID 3642 + +#define v4l2_queryctrl_entry_integer(_id, _name,\ + _minimum, _maximum, _step, \ + _default_value, _flags) \ + {\ + .id = (_id), \ + .type = V4L2_CTRL_TYPE_INTEGER, \ + .name = _name, \ + .minimum = (_minimum), \ + .maximum = (_maximum), \ + .step = (_step), \ + .default_value = (_default_value),\ + .flags = (_flags),\ + } +#define v4l2_queryctrl_entry_boolean(_id, _name,\ + _default_value, _flags) \ + {\ + .id = (_id), \ + .type = V4L2_CTRL_TYPE_BOOLEAN, \ + .name = _name, \ + .minimum = 0, \ + .maximum = 1, \ + .step = 1, \ + .default_value = (_default_value),\ + .flags = (_flags),\ + } + +#define s_ctrl_id_entry_integer(_id, _name, \ + _minimum, _maximum, _step, \ + _default_value, _flags, \ + _s_ctrl, _g_ctrl) \ + {\ + .qc = v4l2_queryctrl_entry_integer(_id, _name,\ + _minimum, _maximum, _step,\ + _default_value, _flags), \ + .s_ctrl = _s_ctrl, \ + .g_ctrl = _g_ctrl, \ + } + +#define s_ctrl_id_entry_boolean(_id, _name, \ + _default_value, _flags, \ + _s_ctrl, _g_ctrl) \ + {\ + .qc = v4l2_queryctrl_entry_boolean(_id, _name,\ + _default_value, _flags), \ + .s_ctrl = _s_ctrl, \ + .g_ctrl = _g_ctrl, \ + } + + +/* Default Values */ +#define LM3642_DEFAULT_TIMEOUT 300U +#define LM3642_DEFAULT_RAMP_TIME 0x10 /* 1.024ms */ +#define LM3642_DEFAULT_INDICATOR_CURRENT 0x01 /* 1.88A */ +#define LM3642_DEFAULT_FLASH_CURRENT 0x0f /* 1500mA */ + +/* Value settings for Flash Time-out Duration*/ +#define LM3642_MIN_TIMEOUT 100U +#define LM3642_MAX_TIMEOUT 800U +#define LM3642_TIMEOUT_STEPSIZE 100U + +/* Flash modes */ +#define LM3642_MODE_SHUTDOWN 0 +#define LM3642_MODE_INDICATOR 1 +#define LM3642_MODE_TORCH 2 +#define LM3642_MODE_FLASH 3 + +/* timer delay time */ +#define LM3642_TIMER_DELAY 5 + +/* Percentage <-> value macros */ +#define LM3642_MIN_PERCENT 0U +#define LM3642_MAX_PERCENT 100U +#define LM3642_CLAMP_PERCENTAGE(val) \ + clamp(val, LM3642_MIN_PERCENT, LM3642_MAX_PERCENT) + +#define LM3642_VALUE_TO_PERCENT(v, step) \ + (((((unsigned long)((v)+1))*(step))+50)/100) +#define LM3642_PERCENT_TO_VALUE(p, step) \ + (((((unsigned long)(p))*100)+((step)>>1))/(step)-1) + +/* Product specific limits + * TODO: get these from platform data */ +#define LM3642_FLASH_MAX_LVL 0x0F /* 1500mA */ +#define LM3642_TORCH_MAX_LVL 0x07 /* 187mA */ +#define LM3642_INDICATOR_MAX_LVL 0x01 /* 1.88A */ + +/* Flash brightness, input is percentage, output is [0..15] */ +#define LM3642_FLASH_STEP \ + ((100ul*(LM3642_MAX_PERCENT) \ + +((LM3642_FLASH_MAX_LVL+1)>>1)) \ + /((LM3642_FLASH_MAX_LVL+1))) +#define LM3642_FLASH_DEFAULT_BRIGHTNESS \ + LM3642_VALUE_TO_PERCENT(15, LM3642_FLASH_STEP) + +/* Torch brightness, input is percentage, output is [0..7] */ +#define LM3642_TORCH_STEP \ + ((100ul*(LM3642_MAX_PERCENT) \ + +((LM3642_TORCH_MAX_LVL+1)>>1)) \ + /((LM3642_TORCH_MAX_LVL+1))) +#define LM3642_TORCH_DEFAULT_BRIGHTNESS \ + LM3642_VALUE_TO_PERCENT(0, LM3642_TORCH_STEP) + +/* Indicator brightness, input is percentage, output is [0..1] */ +#define LM3642_INDICATOR_STEP \ + ((100ul*(LM3642_MAX_PERCENT) \ + +((LM3642_INDICATOR_MAX_LVL+1)>>1)) \ + /((LM3642_INDICATOR_MAX_LVL+1))) +#define LM3642_INDICATOR_DEFAULT_BRIGHTNESS \ + LM3642_VALUE_TO_PERCENT(1, LM3642_INDICATOR_STEP) + +/* + * lm3642_platform_data - Flash controller platform data + */ +struct lm3642_platform_data { + int gpio_torch; + int gpio_strobe; + int (*power_ctrl)(struct v4l2_subdev *subdev, int on); + + unsigned int torch_en; + unsigned int flash_en; + unsigned int tx_en; + unsigned int ivfm_en; +}; + +#endif /* _LM3642_H_ */ + diff --git a/drivers/staging/media/atomisp/pci/Kconfig b/drivers/staging/media/atomisp/pci/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..e8f67835d03d5156ec1e8f5146347ae799a85dbc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/Kconfig @@ -0,0 +1,13 @@ +# +# Kconfig for ISP driver +# + +config VIDEO_ATOMISP + tristate "Intel Atom Image Signal Processor Driver" + depends on VIDEO_V4L2 + select VIDEOBUF_VMALLOC + ---help--- + Say Y here if your platform supports Intel Atom SoC + camera imaging subsystem. + To compile this driver as a module, choose M here: the + module will be called atomisp diff --git a/drivers/staging/media/atomisp/pci/Makefile b/drivers/staging/media/atomisp/pci/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..61ad1fbb1ee60f4301d314cda7eb9ca0bdcd5a2c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for ISP driver +# + +obj-$(CONFIG_VIDEO_ATOMISP) += atomisp2/ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/Makefile b/drivers/staging/media/atomisp/pci/atomisp2/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..53cf881eb3fb1756e2a31ac8877eda57eb358aa1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/Makefile @@ -0,0 +1,380 @@ +atomisp-objs += \ + ./atomisp_drvfs.o \ + ./atomisp_file.o \ + ./css2400/sh_css_mipi.o \ + ./css2400/runtime/pipeline/src/pipeline.o \ + ./css2400/runtime/spctrl/src/spctrl.o \ + ./css2400/runtime/rmgr/src/rmgr.o \ + ./css2400/runtime/rmgr/src/rmgr_vbuf.o \ + ./css2400/runtime/isp_param/src/isp_param.o \ + ./css2400/runtime/inputfifo/src/inputfifo.o \ + ./css2400/runtime/queue/src/queue_access.o \ + ./css2400/runtime/queue/src/queue.o \ + ./css2400/runtime/frame/src/frame.o \ + ./css2400/runtime/eventq/src/eventq.o \ + ./css2400/runtime/binary/src/binary.o \ + ./css2400/runtime/timer/src/timer.o \ + ./css2400/runtime/isys/src/csi_rx_rmgr.o \ + ./css2400/runtime/isys/src/isys_stream2mmio_rmgr.o \ + ./css2400/runtime/isys/src/virtual_isys.o \ + ./css2400/runtime/isys/src/rx.o \ + ./css2400/runtime/isys/src/isys_dma_rmgr.o \ + ./css2400/runtime/isys/src/ibuf_ctrl_rmgr.o \ + ./css2400/runtime/isys/src/isys_init.o \ + ./css2400/runtime/bufq/src/bufq.o \ + ./css2400/runtime/ifmtr/src/ifmtr.o \ + ./css2400/runtime/debug/src/ia_css_debug.o \ + ./css2400/runtime/event/src/event.o \ + ./css2400/sh_css_sp.o \ + ./css2400/css_2400_system/spmem_dump.o \ + ./css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_states.o \ + ./css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_configs.o \ + ./css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_params.o \ + ./css2400/sh_css_stream_format.o \ + ./css2400/sh_css_hrt.o \ + ./css2400/sh_css_properties.o \ + ./css2400/memory_realloc.o \ + ./css2400/hive_isp_css_shared/host/tag.o \ + ./css2400/sh_css_params.o \ + ./css2400/sh_css.o \ + ./css2400/isp/kernels/hdr/ia_css_hdr.host.o \ + ./css2400/isp/kernels/uds/uds_1.0/ia_css_uds.host.o \ + ./css2400/isp/kernels/ynr/ynr_2/ia_css_ynr2.host.o \ + ./css2400/isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.o \ + ./css2400/isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.o \ + ./css2400/isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.o \ + ./css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.o \ + ./css2400/isp/kernels/vf/vf_1.0/ia_css_vf.host.o \ + ./css2400/isp/kernels/raw/raw_1.0/ia_css_raw.host.o \ + ./css2400/isp/kernels/ref/ref_1.0/ia_css_ref.host.o \ + ./css2400/isp/kernels/qplane/qplane_2/ia_css_qplane.host.o \ + ./css2400/isp/kernels/norm/norm_1.0/ia_css_norm.host.o \ + ./css2400/isp/kernels/output/output_1.0/ia_css_output.host.o \ + ./css2400/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.o \ + ./css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5_table.host.o \ + ./css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5.host.o \ + ./css2400/isp/kernels/macc/macc_1.0/ia_css_macc.host.o \ + ./css2400/isp/kernels/macc/macc_1.0/ia_css_macc_table.host.o \ + ./css2400/isp/kernels/csc/csc_1.0/ia_css_csc.host.o \ + ./css2400/isp/kernels/iefd2_6/ia_css_iefd2_6_default.host.o \ + ./css2400/isp/kernels/iefd2_6/ia_css_iefd2_6.host.o \ + ./css2400/isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.o \ + ./css2400/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.o \ + ./css2400/isp/kernels/dpc2/ia_css_dpc2.host.o \ + ./css2400/isp/kernels/dpc2/ia_css_dpc2_default.host.o \ + ./css2400/isp/kernels/fc/fc_1.0/ia_css_formats.host.o \ + ./css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc.host.o \ + ./css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc_table.host.o \ + ./css2400/isp/kernels/ctc/ctc2/ia_css_ctc2.host.o \ + ./css2400/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.o \ + ./css2400/isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds.host.o \ + ./css2400/isp/kernels/bh/bh_2/ia_css_bh.host.o \ + ./css2400/isp/kernels/bnlm/ia_css_bnlm_default.host.o \ + ./css2400/isp/kernels/bnlm/ia_css_bnlm.host.o \ + ./css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.o \ + ./css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf_default.host.o \ + ./css2400/isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.o \ + ./css2400/isp/kernels/anr/anr_1.0/ia_css_anr.host.o \ + ./css2400/isp/kernels/anr/anr_2/ia_css_anr2_table.host.o \ + ./css2400/isp/kernels/anr/anr_2/ia_css_anr2.host.o \ + ./css2400/isp/kernels/dp/dp_1.0/ia_css_dp.host.o \ + ./css2400/isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.o \ + ./css2400/isp/kernels/sdis/sdis_2/ia_css_sdis2.host.o \ + ./css2400/isp/kernels/cnr/cnr_2/ia_css_cnr2.host.o \ + ./css2400/isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.o \ + ./css2400/isp/kernels/satm/ia_css_satm.host.o \ + ./css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.o \ + ./css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_table.host.o \ + ./css2400/isp/kernels/xnr/xnr3_0_5/ia_css_xnr3_0_5.host.o \ + ./css2400/isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.o \ + ./css2400/isp/kernels/xnr/xnr3_0_11/ia_css_xnr3_0_11.host.o \ + ./css2400/isp/kernels/de/de_1.0/ia_css_de.host.o \ + ./css2400/isp/kernels/de/de_2/ia_css_de2.host.o \ + ./css2400/isp/kernels/gc/gc_2/ia_css_gc2.host.o \ + ./css2400/isp/kernels/gc/gc_2/ia_css_gc2_table.host.o \ + ./css2400/isp/kernels/gc/gc_1.0/ia_css_gc.host.o \ + ./css2400/isp/kernels/gc/gc_1.0/ia_css_gc_table.host.o \ + ./css2400/isp/kernels/crop/crop_1.0/ia_css_crop.host.o \ + ./css2400/isp/kernels/io_ls/bayer_io_ls/ia_css_bayer_io.host.o \ + ./css2400/isp/kernels/aa/aa_2/ia_css_aa2.host.o \ + ./css2400/isp/kernels/pdaf/ia_css_pdaf.host.o \ + ./css2400/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.o \ + ./css2400/isp/kernels/ob/ob_1.0/ia_css_ob.host.o \ + ./css2400/isp/kernels/ob/ob2/ia_css_ob2.host.o \ + ./css2400/isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.o \ + ./css2400/isp/kernels/wb/wb_1.0/ia_css_wb.host.o \ + ./css2400/isp/kernels/eed1_8/ia_css_eed1_8_default.host.o \ + ./css2400/isp/kernels/eed1_8/ia_css_eed1_8.host.o \ + ./css2400/isp/kernels/sc/sc_1.0/ia_css_sc.host.o \ + ./css2400/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io.host.o \ + ./css2400/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io.host.o \ + ./css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.o \ + ./css2400/sh_css_lace_stat.o \ + ./css2400/sh_css_pipe.o \ + ./css2400/ia_css_device_access.o \ + ./css2400/sh_css_host_data.o \ + ./css2400/sh_css_mmu.o \ + ./css2400/sh_css_metadata.o \ + ./css2400/base/refcount/src/refcount.o \ + ./css2400/base/circbuf/src/circbuf.o \ + ./css2400/sh_css_irq.o \ + ./css2400/camera/pipe/src/pipe_binarydesc.o \ + ./css2400/camera/pipe/src/pipe_util.o \ + ./css2400/camera/pipe/src/pipe_stagedesc.o \ + ./css2400/camera/util/src/util.o \ + ./css2400/sh_css_metrics.o \ + ./css2400/sh_css_version.o \ + ./css2400/ia_css_memory_access.o \ + ./css2400/sh_css_param_shading.o \ + ./css2400/sh_css_morph.o \ + ./css2400/sh_css_firmware.o \ + ./css2400/hive_isp_css_common/host/isp.o \ + ./css2400/hive_isp_css_common/host/gdc.o \ + ./css2400/hive_isp_css_common/host/sp.o \ + ./css2400/hive_isp_css_common/host/vmem.o \ + ./css2400/hive_isp_css_common/host/dma.o \ + ./css2400/hive_isp_css_common/host/input_formatter.o \ + ./css2400/hive_isp_css_common/host/debug.o \ + ./css2400/hive_isp_css_common/host/hmem.o \ + ./css2400/hive_isp_css_common/host/gp_device.o \ + ./css2400/hive_isp_css_common/host/fifo_monitor.o \ + ./css2400/hive_isp_css_common/host/gp_timer.o \ + ./css2400/hive_isp_css_common/host/irq.o \ + ./css2400/hive_isp_css_common/host/input_system.o \ + ./css2400/hive_isp_css_common/host/timed_ctrl.o \ + ./css2400/hive_isp_css_common/host/mmu.o \ + ./css2400/hive_isp_css_common/host/event_fifo.o \ + ./css2400/sh_css_param_dvs.o \ + ./css2400/sh_css_shading.o \ + ./css2400/sh_css_stream.o \ + ./mmu/sh_mmu_mrfld.o \ + ./mmu/isp_mmu.o \ + ./atomisp_acc.o \ + ./atomisp_compat_css20.o \ + ./atomisp_fops.o \ + ./atomisp_subdev.o \ + ./atomisp_ioctl.o \ + ./atomisp_compat_ioctl32.o \ + ./atomisp_csi2.o \ + ./atomisp_cmd.o \ + ./atomisp_tpg.o \ + ./hmm/hmm_vm.o \ + ./hmm/hmm.o \ + ./hmm/hmm_bo.o \ + ./hmm/hmm_reserved_pool.o \ + ./hmm/hmm_dynamic_pool.o \ + ./hrt/hive_isp_css_mm_hrt.o \ + ./atomisp_v4l2.o + +extra= \ + ./hrt/hive_isp_css_mm_hrt.o \ + ./hrt/memory_access.o \ + ./hrt/device_access.o \ + ./hmm/hmm_dynamic_pool.o \ + ./hmm/hmm_vm.o \ + ./hmm/hmm_reserved_pool.o \ + ./hmm/hmm_bo_dev.o \ + ./hmm/hmm.o \ + ./hmm/hmm_bo.o + +# These will be needed when clean merge CHT support nicely into the driver +# Keep them here handy for when we get to that point +# + +obj-cht= \ + ./css2400/css_2401_system/spmem_dump.o \ + ./css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_states.o \ + ./css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_configs.o \ + ./css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_params.o \ + ./css2400/css_2401_csi2p_system/spmem_dump.o \ + ./css2400/css_2401_csi2p_system/host/isys_stream2mmio.o \ + ./css2400/css_2401_csi2p_system/host/ibuf_ctrl.o \ + ./css2400/css_2401_csi2p_system/host/isys_irq.o \ + ./css2400/css_2401_csi2p_system/host/isys_dma.o \ + ./css2400/css_2401_csi2p_system/host/csi_rx.o \ + ./css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_states.o \ + ./css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_configs.o \ + ./css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_params.o \ + +# -I$(atomisp)/css2400/css_2401_csi2p_system/ \ +# -I$(atomisp)/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ \ +# -I$(atomisp)/css2400/css_2401_csi2p_system/host/ \ +# -I$(atomisp)/css2400/css_2401_csi2p_system/hrt/ \ +# -I$(atomisp)/css2400/css_2401_system/hive_isp_css_2401_system_generated/ \ +# -I$(atomisp)/css2400/css_2401_system/hrt/ \ + + + +obj-$(CONFIG_VIDEO_ATOMISP) += atomisp.o + +atomisp = $(srctree)/drivers/staging/media/atomisp/pci/atomisp2 + +INCLUDES += \ + -I$(atomisp)/ \ + -I$(atomisp)/css2400/ \ + -I$(atomisp)/hrt/ \ + -I$(atomisp)/include/ \ + -I$(atomisp)/include/hmm/ \ + -I$(atomisp)/include/mmu/ \ + -I$(atomisp)/css2400/base/circbuf/interface/ \ + -I$(atomisp)/css2400/base/refcount/interface/ \ + -I$(atomisp)/css2400/camera/pipe/interface/ \ + -I$(atomisp)/css2400/camera/util/interface/ \ + -I$(atomisp)/css2400/css_2400_system/ \ + -I$(atomisp)/css2400/css_2400_system/hive_isp_css_2400_system_generated/ \ + -I$(atomisp)/css2400/css_2400_system/hrt/ \ + -I$(atomisp)/css2400/hive_isp_css_common/ \ + -I$(atomisp)/css2400/hive_isp_css_common/host/ \ + -I$(atomisp)/css2400/hive_isp_css_include/ \ + -I$(atomisp)/css2400/hive_isp_css_include/device_access/ \ + -I$(atomisp)/css2400/hive_isp_css_include/host/ \ + -I$(atomisp)/css2400/hive_isp_css_include/memory_access/ \ + -I$(atomisp)/css2400/hive_isp_css_shared/ \ + -I$(atomisp)/css2400/hive_isp_css_shared/host/ \ + -I$(atomisp)/css2400/isp/kernels/ \ + -I$(atomisp)/css2400/isp/kernels/aa/aa_2/ \ + -I$(atomisp)/css2400/isp/kernels/anr/anr_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/anr/anr_2/ \ + -I$(atomisp)/css2400/isp/kernels/bayer_ls/bayer_ls_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/bh/bh_2/ \ + -I$(atomisp)/css2400/isp/kernels/bnlm/ \ + -I$(atomisp)/css2400/isp/kernels/bnr/ \ + -I$(atomisp)/css2400/isp/kernels/bnr/bnr_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/bnr/bnr2_2/ \ + -I$(atomisp)/css2400/isp/kernels/cnr/ \ + -I$(atomisp)/css2400/isp/kernels/cnr/cnr_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/cnr/cnr_2/ \ + -I$(atomisp)/css2400/isp/kernels/conversion/ \ + -I$(atomisp)/css2400/isp/kernels/conversion/conversion_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/copy_output/ \ + -I$(atomisp)/css2400/isp/kernels/copy_output/copy_output_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/crop/ \ + -I$(atomisp)/css2400/isp/kernels/crop/crop_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/csc/ \ + -I$(atomisp)/css2400/isp/kernels/csc/csc_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/ctc/ \ + -I$(atomisp)/css2400/isp/kernels/ctc/ctc_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/ctc/ctc1_5/ \ + -I$(atomisp)/css2400/isp/kernels/ctc/ctc2/ \ + -I$(atomisp)/css2400/isp/kernels/de/ \ + -I$(atomisp)/css2400/isp/kernels/de/de_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/de/de_2/ \ + -I$(atomisp)/css2400/isp/kernels/dpc2/ \ + -I$(atomisp)/css2400/isp/kernels/dp/ \ + -I$(atomisp)/css2400/isp/kernels/dp/dp_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/dvs/ \ + -I$(atomisp)/css2400/isp/kernels/dvs/dvs_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/eed1_8/ \ + -I$(atomisp)/css2400/isp/kernels/fc/ \ + -I$(atomisp)/css2400/isp/kernels/fc/fc_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/fixedbds/ \ + -I$(atomisp)/css2400/isp/kernels/fixedbds/fixedbds_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/fpn/ \ + -I$(atomisp)/css2400/isp/kernels/fpn/fpn_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/gc/ \ + -I$(atomisp)/css2400/isp/kernels/gc/gc_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/gc/gc_2/ \ + -I$(atomisp)/css2400/isp/kernels/hdr/ \ + -I$(atomisp)/css2400/isp/kernels/iefd2_6/ \ + -I$(atomisp)/css2400/isp/kernels/io_ls/ \ + -I$(atomisp)/css2400/isp/kernels/io_ls/bayer_io_ls/ \ + -I$(atomisp)/css2400/isp/kernels/io_ls/common/ \ + -I$(atomisp)/css2400/isp/kernels/io_ls/plane_io_ls/ \ + -I$(atomisp)/css2400/isp/kernels/io_ls/yuv420_io_ls/ \ + -I$(atomisp)/css2400/isp/kernels/io_ls/yuv444_io_ls/ \ + -I$(atomisp)/css2400/isp/kernels/ipu2_io_ls/ \ + -I$(atomisp)/css2400/isp/kernels/ipu2_io_ls/bayer_io_ls/ \ + -I$(atomisp)/css2400/isp/kernels/ipu2_io_ls/common/ \ + -I$(atomisp)/css2400/isp/kernels/ipu2_io_ls/plane_io_ls/ \ + -I$(atomisp)/css2400/isp/kernels/ipu2_io_ls/yuv420_io_ls/ \ + -I$(atomisp)/css2400/isp/kernels/ipu2_io_ls/yuv444_io_ls/ \ + -I$(atomisp)/css2400/isp/kernels/iterator/ \ + -I$(atomisp)/css2400/isp/kernels/iterator/iterator_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/macc/ \ + -I$(atomisp)/css2400/isp/kernels/macc/macc_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/macc/macc1_5/ \ + -I$(atomisp)/css2400/isp/kernels/norm/ \ + -I$(atomisp)/css2400/isp/kernels/norm/norm_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/ob/ \ + -I$(atomisp)/css2400/isp/kernels/ob/ob_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/ob/ob2/ \ + -I$(atomisp)/css2400/isp/kernels/output/ \ + -I$(atomisp)/css2400/isp/kernels/output/output_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/pdaf/ \ + -I$(atomisp)/css2400/isp/kernels/qplane/ \ + -I$(atomisp)/css2400/isp/kernels/qplane/qplane_2/ \ + -I$(atomisp)/css2400/isp/kernels/raw_aa_binning/ \ + -I$(atomisp)/css2400/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/raw/ \ + -I$(atomisp)/css2400/isp/kernels/raw/raw_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/ref/ \ + -I$(atomisp)/css2400/isp/kernels/ref/ref_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/s3a/ \ + -I$(atomisp)/css2400/isp/kernels/s3a/s3a_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/s3a_stat_ls/ \ + -I$(atomisp)/css2400/isp/kernels/satm/ \ + -I$(atomisp)/css2400/isp/kernels/scale/ \ + -I$(atomisp)/css2400/isp/kernels/scale/scale_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/sc/ \ + -I$(atomisp)/css2400/isp/kernels/sc/sc_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/sdis/ \ + -I$(atomisp)/css2400/isp/kernels/sdis/common/ \ + -I$(atomisp)/css2400/isp/kernels/sdis/sdis_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/sdis/sdis_2/ \ + -I$(atomisp)/css2400/isp/kernels/tdf/ \ + -I$(atomisp)/css2400/isp/kernels/tdf/tdf_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/tnr/ \ + -I$(atomisp)/css2400/isp/kernels/tnr/tnr_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/tnr/tnr3/ \ + -I$(atomisp)/css2400/isp/kernels/uds/ \ + -I$(atomisp)/css2400/isp/kernels/uds/uds_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/vf/ \ + -I$(atomisp)/css2400/isp/kernels/vf/vf_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/wb/ \ + -I$(atomisp)/css2400/isp/kernels/wb/wb_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/xnr/ \ + -I$(atomisp)/css2400/isp/kernels/xnr/xnr_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/xnr/xnr_3.0/ \ + -I$(atomisp)/css2400/isp/kernels/xnr/xnr3_0_11 \ + -I$(atomisp)/css2400/isp/kernels/xnr/xnr3_0_5/ \ + -I$(atomisp)/css2400/isp/kernels/ynr/ \ + -I$(atomisp)/css2400/isp/kernels/ynr/ynr_1.0/ \ + -I$(atomisp)/css2400/isp/kernels/ynr/ynr_2/ \ + -I$(atomisp)/css2400/isp/kernels/yuv_ls \ + -I$(atomisp)/css2400/isp/kernels/yuv_ls/yuv_ls_1.0/ \ + -I$(atomisp)/css2400/isp/modes/interface/ \ + -I$(atomisp)/css2400/runtime/binary/interface/ \ + -I$(atomisp)/css2400/runtime/bufq/interface/ \ + -I$(atomisp)/css2400/runtime/debug/interface/ \ + -I$(atomisp)/css2400/runtime/event/interface/ \ + -I$(atomisp)/css2400/runtime/eventq/interface/ \ + -I$(atomisp)/css2400/runtime/frame/interface/ \ + -I$(atomisp)/css2400/runtime/ifmtr/interface/ \ + -I$(atomisp)/css2400/runtime/inputfifo/interface/ \ + -I$(atomisp)/css2400/runtime/isp_param/interface/ \ + -I$(atomisp)/css2400/runtime/isys/interface/ \ + -I$(atomisp)/css2400/runtime/isys/src/ \ + -I$(atomisp)/css2400/runtime/pipeline/interface/ \ + -I$(atomisp)/css2400/runtime/queue/interface/ \ + -I$(atomisp)/css2400/runtime/queue/src/ \ + -I$(atomisp)/css2400/runtime/rmgr/interface/ \ + -I$(atomisp)/css2400/runtime/spctrl/interface/ \ + -I$(atomisp)/css2400/runtime/tagger/interface/ + +ifeq ($(CONFIG_ION),y) +INCLUDES += -I$(srctree)/drivers/staging/android/ion +endif + +DEFINES := -DHRT_HW -DHRT_ISP_CSS_CUSTOM_HOST -DHRT_USE_VIR_ADDRS -DHRT_KERNEL -D__HOST__ +DEFINES += -DUSE_DYNAMIC_BIN +DEFINES += -DISP_POWER_GATING +DEFINES += -DUSE_INTERRUPTS +#DEFINES += -DUSE_SSSE3 +DEFINES += -DPUNIT_CAMERA_BUSY +DEFINES += -DUSE_KMEM_CACHE + +DEFINES += -DATOMISP_POSTFIX=\"css2400b0_v21\" -DISP2400B0 +DEFINES += -DSYSTEM_hive_isp_css_2400_system -DISP2400 + +ccflags-y += $(INCLUDES) $(DEFINES) -fno-common -Werror + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp-regs.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp-regs.h new file mode 100644 index 0000000000000000000000000000000000000000..513a430ee01ae53a1203decbc80de32aa88e8bbd --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp-regs.h @@ -0,0 +1,209 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef ATOMISP_REGS_H +#define ATOMISP_REGS_H + +/* common register definitions */ +#define PUNIT_PORT 0x04 +#define CCK_PORT 0x14 + +#define PCICMDSTS 0x01 +#define INTR 0x0f +#define MSI_CAPID 0x24 +#define MSI_ADDRESS 0x25 +#define MSI_DATA 0x26 +#define INTR_CTL 0x27 + +#define PCI_MSI_CAPID 0x90 +#define PCI_MSI_ADDR 0x94 +#define PCI_MSI_DATA 0x98 +#define PCI_INTERRUPT_CTRL 0x9C +#define PCI_I_CONTROL 0xfc + +/* MRFLD specific register definitions */ +#define MRFLD_CSI_AFE 0x39 +#define MRFLD_CSI_CONTROL 0x3a +#define MRFLD_CSI_RCOMP 0x3d + +#define MRFLD_PCI_PMCS 0x84 +#define MRFLD_PCI_CSI_ACCESS_CTRL_VIOL 0xd4 +#define MRFLD_PCI_CSI_AFE_HS_CONTROL 0xdc +#define MRFLD_PCI_CSI_AFE_RCOMP_CONTROL 0xe0 +#define MRFLD_PCI_CSI_CONTROL 0xe8 +#define MRFLD_PCI_CSI_AFE_TRIM_CONTROL 0xe4 +#define MRFLD_PCI_CSI_DEADLINE_CONTROL 0xec +#define MRFLD_PCI_CSI_RCOMP_CONTROL 0xf4 + +/* Select Arasan (legacy)/Intel input system */ +#define MRFLD_PCI_CSI_CONTROL_PARPATHEN BIT(24) +/* Enable CSI interface (ANN B0/K0) */ +#define MRFLD_PCI_CSI_CONTROL_CSI_READY BIT(25) + +/* + * Enables the combining of adjacent 32-byte read requests to the same + * cache line. When cleared, each 32-byte read request is sent as a + * separate request on the IB interface. + */ +#define MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING 0x1 + +/* + * Register: MRFLD_PCI_CSI_RCOMP_CONTROL + * If cleared, the high speed clock going to the digital logic is gated when + * RCOMP update is happening. The clock is gated for a minimum of 100 nsec. + * If this bit is set, then the high speed clock is not gated during the + * update cycle. + */ +#define MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE 0x800000 + +/* + * Enables the combining of adjacent 32-byte write requests to the same + * cache line. When cleared, each 32-byte write request is sent as a + * separate request on the IB interface. + */ +#define MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING 0x2 + +#define MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK 0xc + +#define MRFLD_PCI_CSI1_HSRXCLKTRIM 0x2 +#define MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT 16 +#define MRFLD_PCI_CSI2_HSRXCLKTRIM 0x3 +#define MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT 24 +#define MRFLD_PCI_CSI3_HSRXCLKTRIM 0x2 +#define MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT 28 +#define MRFLD_PCI_CSI_HSRXCLKTRIM_MASK 0xf + +/* + * This register is IUINT MMIO register, it is used to select the CSI + * receiver backend. + * 1: SH CSI backend + * 0: Arasan CSI backend + */ +#define MRFLD_CSI_RECEIVER_SELECTION_REG 0x8081c + +#define MRFLD_INTR_CLEAR_REG 0x50c +#define MRFLD_INTR_STATUS_REG 0x508 +#define MRFLD_INTR_ENABLE_REG 0x510 + +#define MRFLD_MAX_ZOOM_FACTOR 1024 + +/* MRFLD ISP POWER related */ +#define MRFLD_ISPSSPM0 0x39 +#define MRFLD_ISPSSPM0_ISPSSC_OFFSET 0 +#define MRFLD_ISPSSPM0_ISPSSS_OFFSET 24 +#define MRFLD_ISPSSPM0_ISPSSC_MASK 0x3 +#define MRFLD_ISPSSPM0_IUNIT_POWER_ON 0 +#define MRFLD_ISPSSPM0_IUNIT_POWER_OFF 0x3 +#define MRFLD_ISPSSDVFS 0x13F +#define MRFLD_BIT0 0x0001 +#define MRFLD_BIT1 0x0002 + +/* MRFLD CSI lane configuration related */ +#define MRFLD_PORT_CONFIG_NUM 8 +#define MRFLD_PORT_NUM 3 +#define MRFLD_PORT1_ENABLE_SHIFT 0 +#define MRFLD_PORT2_ENABLE_SHIFT 1 +#define MRFLD_PORT3_ENABLE_SHIFT 2 +#define MRFLD_PORT1_LANES_SHIFT 3 +#define MRFLD_PORT2_LANES_SHIFT 7 +#define MRFLD_PORT3_LANES_SHIFT 8 +#define MRFLD_PORT_CONFIG_MASK 0x000f03ff +#define MRFLD_PORT_CONFIGCODE_SHIFT 16 +#define MRFLD_ALL_CSI_PORTS_OFF_MASK 0x7 + +#define CHV_PORT3_LANES_SHIFT 9 +#define CHV_PORT_CONFIG_MASK 0x1f07ff + +#define ISPSSPM1 0x3a +#define ISP_FREQ_STAT_MASK (0x1f << ISP_FREQ_STAT_OFFSET) +#define ISP_REQ_FREQ_MASK 0x1f +#define ISP_FREQ_VALID_MASK (0x1 << ISP_FREQ_VALID_OFFSET) +#define ISP_FREQ_STAT_OFFSET 0x18 +#define ISP_REQ_GUAR_FREQ_OFFSET 0x8 +#define ISP_REQ_FREQ_OFFSET 0x0 +#define ISP_FREQ_VALID_OFFSET 0x7 +#define ISP_FREQ_RULE_ANY 0x0 + +#define ISP_FREQ_457MHZ 0x1C9 +#define ISP_FREQ_400MHZ 0x190 +#define ISP_FREQ_356MHZ 0x164 +#define ISP_FREQ_320MHZ 0x140 +#define ISP_FREQ_266MHZ 0x10a +#define ISP_FREQ_200MHZ 0xc8 +#define ISP_FREQ_100MHZ 0x64 + +#define HPLL_FREQ_800MHZ 0x320 +#define HPLL_FREQ_1600MHZ 0x640 +#define HPLL_FREQ_2000MHZ 0x7D0 + +#define CCK_FUSE_REG_0 0x08 +#define CCK_FUSE_HPLL_FREQ_MASK 0x03 + +#if defined(ISP2401) +#define ISP_FREQ_MAX ISP_FREQ_320MHZ +#else +#define ISP_FREQ_MAX ISP_FREQ_400MHZ +#endif + +/* ISP2401 CSI2+ receiver delay settings */ +#define CSI2_PORT_A_BASE 0xC0000 +#define CSI2_PORT_B_BASE 0xC2000 +#define CSI2_PORT_C_BASE 0xC4000 + +#define CSI2_LANE_CL_BASE 0x418 +#define CSI2_LANE_D0_BASE 0x420 +#define CSI2_LANE_D1_BASE 0x428 +#define CSI2_LANE_D2_BASE 0x430 +#define CSI2_LANE_D3_BASE 0x438 + +#define CSI2_REG_RX_CSI_DLY_CNT_TERMEN 0 +#define CSI2_REG_RX_CSI_DLY_CNT_SETTLE 0x4 + +#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC0418 +#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC041C +#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC0420 +#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC0424 +#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC0428 +#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC042C +#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE2 0xC0430 +#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE2 0xC0434 +#define CSI2_PORT_A_RX_CSI_DLY_CNT_TERMEN_DLANE3 0xC0438 +#define CSI2_PORT_A_RX_CSI_DLY_CNT_SETTLE_DLANE3 0xC043C + +#define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC2418 +#define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC241C +#define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC2420 +#define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC2424 +#define CSI2_PORT_B_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC2428 +#define CSI2_PORT_B_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC242C + +#define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_CLANE 0xC4418 +#define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_CLANE 0xC441C +#define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_DLANE0 0xC4420 +#define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_DLANE0 0xC4424 +#define CSI2_PORT_C_RX_CSI_DLY_CNT_TERMEN_DLANE1 0xC4428 +#define CSI2_PORT_C_RX_CSI_DLY_CNT_SETTLE_DLANE1 0xC442C + +#define DMA_BURST_SIZE_REG 0xCD408 + +#define ISP_DFS_TRY_TIMES 2 + +#endif /* ATOMISP_REGS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_acc.c b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_acc.c new file mode 100644 index 0000000000000000000000000000000000000000..4c35a785c7d5991d8b5fded94da27cec620a1c8f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_acc.c @@ -0,0 +1,610 @@ +/* + * Support for Clovertrail PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +/* + * This file implements loadable acceleration firmware API, + * including ioctls to map and unmap acceleration parameters and buffers. + */ + +#include +#include + +#include "atomisp_acc.h" +#include "atomisp_internal.h" +#include "atomisp_compat.h" +#include "atomisp_cmd.h" + +#include "hrt/hive_isp_css_mm_hrt.h" +#include "memory_access/memory_access.h" +#include "ia_css.h" + +static const struct { + unsigned int flag; + enum atomisp_css_pipe_id pipe_id; +} acc_flag_to_pipe[] = { + { ATOMISP_ACC_FW_LOAD_FL_PREVIEW, CSS_PIPE_ID_PREVIEW }, + { ATOMISP_ACC_FW_LOAD_FL_COPY, CSS_PIPE_ID_COPY }, + { ATOMISP_ACC_FW_LOAD_FL_VIDEO, CSS_PIPE_ID_VIDEO }, + { ATOMISP_ACC_FW_LOAD_FL_CAPTURE, CSS_PIPE_ID_CAPTURE }, + { ATOMISP_ACC_FW_LOAD_FL_ACC, CSS_PIPE_ID_ACC } +}; + +/* + * Allocate struct atomisp_acc_fw along with space for firmware. + * The returned struct atomisp_acc_fw is cleared (firmware region is not). + */ +static struct atomisp_acc_fw *acc_alloc_fw(unsigned int fw_size) +{ + struct atomisp_acc_fw *acc_fw; + + acc_fw = kzalloc(sizeof(*acc_fw), GFP_KERNEL); + if (!acc_fw) + return NULL; + + acc_fw->fw = vmalloc(fw_size); + if (!acc_fw->fw) { + kfree(acc_fw); + return NULL; + } + + return acc_fw; +} + +static void acc_free_fw(struct atomisp_acc_fw *acc_fw) +{ + vfree(acc_fw->fw); + kfree(acc_fw); +} + +static struct atomisp_acc_fw * +acc_get_fw(struct atomisp_sub_device *asd, unsigned int handle) +{ + struct atomisp_acc_fw *acc_fw; + + list_for_each_entry(acc_fw, &asd->acc.fw, list) + if (acc_fw->handle == handle) + return acc_fw; + + return NULL; +} + +static struct atomisp_map *acc_get_map(struct atomisp_sub_device *asd, + unsigned long css_ptr, size_t length) +{ + struct atomisp_map *atomisp_map; + + list_for_each_entry(atomisp_map, &asd->acc.memory_maps, list) { + if (atomisp_map->ptr == css_ptr && + atomisp_map->length == length) + return atomisp_map; + } + return NULL; +} + +static int acc_stop_acceleration(struct atomisp_sub_device *asd) +{ + int ret; + + ret = atomisp_css_stop_acc_pipe(asd); + atomisp_css_destroy_acc_pipe(asd); + + return ret; +} + +void atomisp_acc_cleanup(struct atomisp_device *isp) +{ + int i; + + for (i = 0; i < isp->num_of_streams; i++) + ida_destroy(&isp->asd[i].acc.ida); +} + +void atomisp_acc_release(struct atomisp_sub_device *asd) +{ + struct atomisp_acc_fw *acc_fw, *ta; + struct atomisp_map *atomisp_map, *tm; + + /* Stop acceleration if already running */ + if (asd->acc.pipeline) + acc_stop_acceleration(asd); + + /* Unload all loaded acceleration binaries */ + list_for_each_entry_safe(acc_fw, ta, &asd->acc.fw, list) { + list_del(&acc_fw->list); + ida_remove(&asd->acc.ida, acc_fw->handle); + acc_free_fw(acc_fw); + } + + /* Free all mapped memory blocks */ + list_for_each_entry_safe(atomisp_map, tm, &asd->acc.memory_maps, list) { + list_del(&atomisp_map->list); + mmgr_free(atomisp_map->ptr); + kfree(atomisp_map); + } +} + +int atomisp_acc_load_to_pipe(struct atomisp_sub_device *asd, + struct atomisp_acc_fw_load_to_pipe *user_fw) +{ + static const unsigned int pipeline_flags = + ATOMISP_ACC_FW_LOAD_FL_PREVIEW | ATOMISP_ACC_FW_LOAD_FL_COPY | + ATOMISP_ACC_FW_LOAD_FL_VIDEO | + ATOMISP_ACC_FW_LOAD_FL_CAPTURE | ATOMISP_ACC_FW_LOAD_FL_ACC; + + struct atomisp_acc_fw *acc_fw; + int handle; + + if (!user_fw->data || user_fw->size < sizeof(*acc_fw->fw)) + return -EINVAL; + + /* Binary has to be enabled at least for one pipeline */ + if (!(user_fw->flags & pipeline_flags)) + return -EINVAL; + + /* We do not support other flags yet */ + if (user_fw->flags & ~pipeline_flags) + return -EINVAL; + + if (user_fw->type < ATOMISP_ACC_FW_LOAD_TYPE_OUTPUT || + user_fw->type > ATOMISP_ACC_FW_LOAD_TYPE_STANDALONE) + return -EINVAL; + + if (asd->acc.pipeline || asd->acc.extension_mode) + return -EBUSY; + + acc_fw = acc_alloc_fw(user_fw->size); + if (!acc_fw) + return -ENOMEM; + + if (copy_from_user(acc_fw->fw, user_fw->data, user_fw->size)) { + acc_free_fw(acc_fw); + return -EFAULT; + } + + if (!ida_pre_get(&asd->acc.ida, GFP_KERNEL) || + ida_get_new_above(&asd->acc.ida, 1, &handle)) { + acc_free_fw(acc_fw); + return -ENOSPC; + } + + user_fw->fw_handle = handle; + acc_fw->handle = handle; + acc_fw->flags = user_fw->flags; + acc_fw->type = user_fw->type; + acc_fw->fw->handle = handle; + + /* + * correct isp firmware type in order ISP firmware can be appended + * to correct pipe properly + */ + if (acc_fw->fw->type == ia_css_isp_firmware) { + static const int type_to_css[] = { + [ATOMISP_ACC_FW_LOAD_TYPE_OUTPUT] = + IA_CSS_ACC_OUTPUT, + [ATOMISP_ACC_FW_LOAD_TYPE_VIEWFINDER] = + IA_CSS_ACC_VIEWFINDER, + [ATOMISP_ACC_FW_LOAD_TYPE_STANDALONE] = + IA_CSS_ACC_STANDALONE, + }; + acc_fw->fw->info.isp.type = type_to_css[acc_fw->type]; + } + + list_add_tail(&acc_fw->list, &asd->acc.fw); + return 0; +} + +int atomisp_acc_load(struct atomisp_sub_device *asd, + struct atomisp_acc_fw_load *user_fw) +{ + struct atomisp_acc_fw_load_to_pipe ltp = {0}; + int r; + + ltp.flags = ATOMISP_ACC_FW_LOAD_FL_ACC; + ltp.type = ATOMISP_ACC_FW_LOAD_TYPE_STANDALONE; + ltp.size = user_fw->size; + ltp.data = user_fw->data; + r = atomisp_acc_load_to_pipe(asd, <p); + user_fw->fw_handle = ltp.fw_handle; + return r; +} + +int atomisp_acc_unload(struct atomisp_sub_device *asd, unsigned int *handle) +{ + struct atomisp_acc_fw *acc_fw; + + if (asd->acc.pipeline || asd->acc.extension_mode) + return -EBUSY; + + acc_fw = acc_get_fw(asd, *handle); + if (!acc_fw) + return -EINVAL; + + list_del(&acc_fw->list); + ida_remove(&asd->acc.ida, acc_fw->handle); + acc_free_fw(acc_fw); + + return 0; +} + +int atomisp_acc_start(struct atomisp_sub_device *asd, unsigned int *handle) +{ + struct atomisp_device *isp = asd->isp; + struct atomisp_acc_fw *acc_fw; + int ret; + unsigned int nbin; + + if (asd->acc.pipeline || asd->acc.extension_mode) + return -EBUSY; + + /* Invalidate caches. FIXME: should flush only necessary buffers */ + wbinvd(); + + ret = atomisp_css_create_acc_pipe(asd); + if (ret) + return ret; + + nbin = 0; + list_for_each_entry(acc_fw, &asd->acc.fw, list) { + if (*handle != 0 && *handle != acc_fw->handle) + continue; + + if (acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_STANDALONE) + continue; + + /* Add the binary into the pipeline */ + ret = atomisp_css_load_acc_binary(asd, acc_fw->fw, nbin); + if (ret < 0) { + dev_err(isp->dev, "acc_load_binary failed\n"); + goto err_stage; + } + + ret = atomisp_css_set_acc_parameters(acc_fw); + if (ret < 0) { + dev_err(isp->dev, "acc_set_parameters failed\n"); + goto err_stage; + } + nbin++; + } + if (nbin < 1) { + /* Refuse creating pipelines with no binaries */ + dev_err(isp->dev, "%s: no acc binary available\n", __func__); + ret = -EINVAL; + goto err_stage; + } + + ret = atomisp_css_start_acc_pipe(asd); + if (ret) { + dev_err(isp->dev, "%s: atomisp_acc_start_acc_pipe failed\n", + __func__); + goto err_stage; + } + + return 0; + +err_stage: + atomisp_css_destroy_acc_pipe(asd); + return ret; +} + +int atomisp_acc_wait(struct atomisp_sub_device *asd, unsigned int *handle) +{ + struct atomisp_device *isp = asd->isp; + int ret; + + if (!asd->acc.pipeline) + return -ENOENT; + + if (*handle && !acc_get_fw(asd, *handle)) + return -EINVAL; + + ret = atomisp_css_wait_acc_finish(asd); + if (acc_stop_acceleration(asd) == -EIO) { + atomisp_reset(isp); + return -EINVAL; + } + + return ret; +} + +void atomisp_acc_done(struct atomisp_sub_device *asd, unsigned int handle) +{ + struct v4l2_event event = { 0 }; + + event.type = V4L2_EVENT_ATOMISP_ACC_COMPLETE; + event.u.frame_sync.frame_sequence = atomic_read(&asd->sequence); + event.id = handle; + + v4l2_event_queue(asd->subdev.devnode, &event); +} + +int atomisp_acc_map(struct atomisp_sub_device *asd, struct atomisp_acc_map *map) +{ + struct atomisp_map *atomisp_map; + ia_css_ptr cssptr; + int pgnr; + + if (map->css_ptr) + return -EINVAL; + + if (asd->acc.pipeline) + return -EBUSY; + + if (map->user_ptr) { + /* Buffer to map must be page-aligned */ + if ((unsigned long)map->user_ptr & ~PAGE_MASK) { + dev_err(asd->isp->dev, + "%s: mapped buffer address %p is not page aligned\n", + __func__, map->user_ptr); + return -EINVAL; + } + + pgnr = DIV_ROUND_UP(map->length, PAGE_SIZE); + cssptr = hrt_isp_css_mm_alloc_user_ptr( + map->length, map->user_ptr, + pgnr, HRT_USR_PTR, + (map->flags & ATOMISP_MAP_FLAG_CACHED)); + } else { + /* Allocate private buffer. */ + if (map->flags & ATOMISP_MAP_FLAG_CACHED) + cssptr = hrt_isp_css_mm_calloc_cached(map->length); + else + cssptr = hrt_isp_css_mm_calloc(map->length); + } + + if (!cssptr) + return -ENOMEM; + + atomisp_map = kmalloc(sizeof(*atomisp_map), GFP_KERNEL); + if (!atomisp_map) { + mmgr_free(cssptr); + return -ENOMEM; + } + atomisp_map->ptr = cssptr; + atomisp_map->length = map->length; + list_add(&atomisp_map->list, &asd->acc.memory_maps); + + dev_dbg(asd->isp->dev, "%s: userptr %p, css_address 0x%x, size %d\n", + __func__, map->user_ptr, cssptr, map->length); + map->css_ptr = cssptr; + return 0; +} + +int atomisp_acc_unmap(struct atomisp_sub_device *asd, struct atomisp_acc_map *map) +{ + struct atomisp_map *atomisp_map; + + if (asd->acc.pipeline) + return -EBUSY; + + atomisp_map = acc_get_map(asd, map->css_ptr, map->length); + if (!atomisp_map) + return -EINVAL; + + list_del(&atomisp_map->list); + mmgr_free(atomisp_map->ptr); + kfree(atomisp_map); + return 0; +} + +int atomisp_acc_s_mapped_arg(struct atomisp_sub_device *asd, + struct atomisp_acc_s_mapped_arg *arg) +{ + struct atomisp_acc_fw *acc_fw; + + if (arg->memory >= ATOMISP_ACC_NR_MEMORY) + return -EINVAL; + + if (asd->acc.pipeline) + return -EBUSY; + + acc_fw = acc_get_fw(asd, arg->fw_handle); + if (!acc_fw) + return -EINVAL; + + if (arg->css_ptr != 0 || arg->length != 0) { + /* Unless the parameter is cleared, check that it exists */ + if (!acc_get_map(asd, arg->css_ptr, arg->length)) + return -EINVAL; + } + + acc_fw->args[arg->memory].length = arg->length; + acc_fw->args[arg->memory].css_ptr = arg->css_ptr; + + dev_dbg(asd->isp->dev, "%s: mem %d, address %p, size %ld\n", + __func__, arg->memory, (void *)arg->css_ptr, + (unsigned long)arg->length); + return 0; +} + +/* + * Appends the loaded acceleration binary extensions to the + * current ISP mode. Must be called just before sh_css_start(). + */ +int atomisp_acc_load_extensions(struct atomisp_sub_device *asd) +{ + struct atomisp_acc_fw *acc_fw; + bool ext_loaded = false; + bool continuous = asd->continuous_mode->val && + asd->run_mode->val == ATOMISP_RUN_MODE_PREVIEW; + int ret = 0, i = -1; + struct atomisp_device *isp = asd->isp; + + if (asd->acc.pipeline || asd->acc.extension_mode) + return -EBUSY; + + /* Invalidate caches. FIXME: should flush only necessary buffers */ + wbinvd(); + + list_for_each_entry(acc_fw, &asd->acc.fw, list) { + if (acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_OUTPUT && + acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_VIEWFINDER) + continue; + + for (i = 0; i < ARRAY_SIZE(acc_flag_to_pipe); i++) { + /* QoS (ACC pipe) acceleration stages are currently + * allowed only in continuous mode. Skip them for + * all other modes. */ + if (!continuous && + acc_flag_to_pipe[i].flag == + ATOMISP_ACC_FW_LOAD_FL_ACC) + continue; + + if (acc_fw->flags & acc_flag_to_pipe[i].flag) { + ret = atomisp_css_load_acc_extension(asd, + acc_fw->fw, + acc_flag_to_pipe[i].pipe_id, + acc_fw->type); + if (ret) { + i--; + goto error; + } + + ext_loaded = true; + } + } + + ret = atomisp_css_set_acc_parameters(acc_fw); + if (ret < 0) + goto error; + } + + if (!ext_loaded) + return ret; + + ret = atomisp_css_update_stream(asd); + if (ret) { + dev_err(isp->dev, "%s: update stream failed.\n", __func__); + goto error; + } + + asd->acc.extension_mode = true; + return 0; + +error: + for (; i >= 0; i--) { + if (acc_fw->flags & acc_flag_to_pipe[i].flag) { + atomisp_css_unload_acc_extension(asd, acc_fw->fw, + acc_flag_to_pipe[i].pipe_id); + } + } + + list_for_each_entry_continue_reverse(acc_fw, &asd->acc.fw, list) { + if (acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_OUTPUT && + acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_VIEWFINDER) + continue; + + for (i = ARRAY_SIZE(acc_flag_to_pipe) - 1; i >= 0; i--) { + if (!continuous && + acc_flag_to_pipe[i].flag == + ATOMISP_ACC_FW_LOAD_FL_ACC) + continue; + if (acc_fw->flags & acc_flag_to_pipe[i].flag) { + atomisp_css_unload_acc_extension(asd, + acc_fw->fw, + acc_flag_to_pipe[i].pipe_id); + } + } + } + return ret; +} + +void atomisp_acc_unload_extensions(struct atomisp_sub_device *asd) +{ + struct atomisp_acc_fw *acc_fw; + int i; + + if (!asd->acc.extension_mode) + return; + + list_for_each_entry_reverse(acc_fw, &asd->acc.fw, list) { + if (acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_OUTPUT && + acc_fw->type != ATOMISP_ACC_FW_LOAD_TYPE_VIEWFINDER) + continue; + + for (i = ARRAY_SIZE(acc_flag_to_pipe) - 1; i >= 0; i--) { + if (acc_fw->flags & acc_flag_to_pipe[i].flag) { + atomisp_css_unload_acc_extension(asd, + acc_fw->fw, + acc_flag_to_pipe[i].pipe_id); + } + } + } + + asd->acc.extension_mode = false; +} + +int atomisp_acc_set_state(struct atomisp_sub_device *asd, + struct atomisp_acc_state *arg) +{ + struct atomisp_acc_fw *acc_fw; + bool enable = (arg->flags & ATOMISP_STATE_FLAG_ENABLE) != 0; + struct ia_css_pipe *pipe; + enum ia_css_err r; + int i; + + if (!asd->acc.extension_mode) + return -EBUSY; + + if (arg->flags & ~ATOMISP_STATE_FLAG_ENABLE) + return -EINVAL; + + acc_fw = acc_get_fw(asd, arg->fw_handle); + if (!acc_fw) + return -EINVAL; + + if (enable) + wbinvd(); + + for (i = 0; i < ARRAY_SIZE(acc_flag_to_pipe); i++) { + if (acc_fw->flags & acc_flag_to_pipe[i].flag) { + pipe = asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]. + pipes[acc_flag_to_pipe[i].pipe_id]; + r = ia_css_pipe_set_qos_ext_state(pipe, acc_fw->handle, + enable); + if (r != IA_CSS_SUCCESS) + return -EBADRQC; + } + } + + if (enable) + acc_fw->flags |= ATOMISP_ACC_FW_LOAD_FL_ENABLE; + else + acc_fw->flags &= ~ATOMISP_ACC_FW_LOAD_FL_ENABLE; + + return 0; +} + +int atomisp_acc_get_state(struct atomisp_sub_device *asd, + struct atomisp_acc_state *arg) +{ + struct atomisp_acc_fw *acc_fw; + + if (!asd->acc.extension_mode) + return -EBUSY; + + acc_fw = acc_get_fw(asd, arg->fw_handle); + if (!acc_fw) + return -EINVAL; + + arg->flags = acc_fw->flags; + + return 0; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_acc.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_acc.h new file mode 100644 index 0000000000000000000000000000000000000000..6a2d1f99cab4f732caa7a2a687a5deb41bd9392b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_acc.h @@ -0,0 +1,124 @@ +/* + * Support for Clovertrail PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __ATOMISP_ACC_H__ +#define __ATOMISP_ACC_H__ + +#include +#include "atomisp_internal.h" + +#include "ia_css_types.h" + +/* + * Interface functions for AtomISP driver acceleration API implementation. + */ + +struct atomisp_sub_device; + +void atomisp_acc_cleanup(struct atomisp_device *isp); + +/* + * Free up any allocated resources. + * Must be called each time when the device is closed. + * Note that there isn't corresponding open() call; + * this function may be called sequentially multiple times. + * Must be called to free up resources before driver is unloaded. + */ +void atomisp_acc_release(struct atomisp_sub_device *asd); + +/* Load acceleration binary. DEPRECATED. */ +int atomisp_acc_load(struct atomisp_sub_device *asd, + struct atomisp_acc_fw_load *fw); + +/* Load acceleration binary with specified properties */ +int atomisp_acc_load_to_pipe(struct atomisp_sub_device *asd, + struct atomisp_acc_fw_load_to_pipe *fw); + +/* Unload specified acceleration binary */ +int atomisp_acc_unload(struct atomisp_sub_device *asd, + unsigned int *handle); + +/* + * Map a memory region into ISP memory space. + */ +int atomisp_acc_map(struct atomisp_sub_device *asd, + struct atomisp_acc_map *map); + +/* + * Unmap a mapped memory region. + */ +int atomisp_acc_unmap(struct atomisp_sub_device *asd, + struct atomisp_acc_map *map); + +/* + * Set acceleration binary argument to a previously mapped memory region. + */ +int atomisp_acc_s_mapped_arg(struct atomisp_sub_device *asd, + struct atomisp_acc_s_mapped_arg *arg); + + +/* + * Start acceleration. + * Return immediately, acceleration is left running in background. + * Specify either acceleration binary or pipeline which to start. + */ +int atomisp_acc_start(struct atomisp_sub_device *asd, + unsigned int *handle); + +/* + * Wait until acceleration finishes. + * This MUST be called after each acceleration has been started. + * Specify either acceleration binary or pipeline handle. + */ +int atomisp_acc_wait(struct atomisp_sub_device *asd, + unsigned int *handle); + +/* + * Used by ISR to notify ACC stage finished. + * This is internally used and does not export as IOCTL. + */ +void atomisp_acc_done(struct atomisp_sub_device *asd, unsigned int handle); + +/* + * Appends the loaded acceleration binary extensions to the + * current ISP mode. Must be called just before atomisp_css_start(). + */ +int atomisp_acc_load_extensions(struct atomisp_sub_device *asd); + +/* + * Must be called after streaming is stopped: + * unloads any loaded acceleration extensions. + */ +void atomisp_acc_unload_extensions(struct atomisp_sub_device *asd); + +/* + * Set acceleration firmware flags. + */ +int atomisp_acc_set_state(struct atomisp_sub_device *asd, + struct atomisp_acc_state *arg); + +/* + * Get acceleration firmware flags. + */ +int atomisp_acc_get_state(struct atomisp_sub_device *asd, + struct atomisp_acc_state *arg); + +#endif /* __ATOMISP_ACC_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_cmd.c b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_cmd.c new file mode 100644 index 0000000000000000000000000000000000000000..e99f7b84fc4eeaeded285bbe1a8321717f146adc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_cmd.c @@ -0,0 +1,6804 @@ +#ifdef ISP2401 + +#endif +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#define CREATE_TRACE_POINTS +#include "atomisp_trace_event.h" + +#include "atomisp_cmd.h" +#include "atomisp_common.h" +#include "atomisp_fops.h" +#include "atomisp_internal.h" +#include "atomisp_ioctl.h" +#include "atomisp-regs.h" +#include "atomisp_tables.h" +#include "atomisp_acc.h" +#include "atomisp_compat.h" +#include "atomisp_subdev.h" +#include "atomisp_dfs_tables.h" + +#include "hrt/hive_isp_css_mm_hrt.h" + +#include "sh_css_hrt.h" +#include "sh_css_defs.h" +#include "system_global.h" +#include "sh_css_internal.h" +#include "sh_css_sp.h" +#include "gp_device.h" +#include "device_access.h" +#include "irq.h" + +#include "ia_css_types.h" +#include "ia_css_stream.h" +#include "error_support.h" +#include "hrt/bits.h" + + +/* We should never need to run the flash for more than 2 frames. + * At 15fps this means 133ms. We set the timeout a bit longer. + * Each flash driver is supposed to set its own timeout, but + * just in case someone else changed the timeout, we set it + * here to make sure we don't damage the flash hardware. */ +#define FLASH_TIMEOUT 800 /* ms */ + +union host { + struct { + void *kernel_ptr; + void __user *user_ptr; + int size; + } scalar; + struct { + void *hmm_ptr; + } ptr; +}; + +/* + * atomisp_kernel_malloc: chooses whether kmalloc() or vmalloc() is preferable. + * + * It is also a wrap functions to pass into css framework. + */ +void *atomisp_kernel_malloc(size_t bytes) +{ + /* vmalloc() is preferable if allocating more than 1 page */ + if (bytes > PAGE_SIZE) + return vmalloc(bytes); + + return kmalloc(bytes, GFP_KERNEL); +} + +/* + * atomisp_kernel_zalloc: chooses whether set 0 to the allocated memory. + * + * It is also a wrap functions to pass into css framework. + */ +void *atomisp_kernel_zalloc(size_t bytes, bool zero_mem) +{ + void *ptr = atomisp_kernel_malloc(bytes); + + if (ptr && zero_mem) + memset(ptr, 0, bytes); + + return ptr; +} + +/* + * Free buffer allocated with atomisp_kernel_malloc()/atomisp_kernel_zalloc + * helper + */ +void atomisp_kernel_free(void *ptr) +{ + /* Verify if buffer was allocated by vmalloc() or kmalloc() */ + if (is_vmalloc_addr(ptr)) + vfree(ptr); + else + kfree(ptr); +} + +/* + * get sensor:dis71430/ov2720 related info from v4l2_subdev->priv data field. + * subdev->priv is set in mrst.c + */ +struct camera_mipi_info *atomisp_to_sensor_mipi_info(struct v4l2_subdev *sd) +{ + return (struct camera_mipi_info *)v4l2_get_subdev_hostdata(sd); +} + +/* + * get struct atomisp_video_pipe from v4l2 video_device + */ +struct atomisp_video_pipe *atomisp_to_video_pipe(struct video_device *dev) +{ + return (struct atomisp_video_pipe *) + container_of(dev, struct atomisp_video_pipe, vdev); +} + +/* + * get struct atomisp_acc_pipe from v4l2 video_device + */ +struct atomisp_acc_pipe *atomisp_to_acc_pipe(struct video_device *dev) +{ + return (struct atomisp_acc_pipe *) + container_of(dev, struct atomisp_acc_pipe, vdev); +} + +static unsigned short atomisp_get_sensor_fps(struct atomisp_sub_device *asd) +{ + struct v4l2_subdev_frame_interval frame_interval; + struct atomisp_device *isp = asd->isp; + unsigned short fps; + + if (v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + video, g_frame_interval, &frame_interval)) { + fps = 0; + } else { + if (frame_interval.interval.numerator) + fps = frame_interval.interval.denominator / + frame_interval.interval.numerator; + else + fps = 0; + } + return fps; +} + +/* + * DFS progress is shown as follows: + * 1. Target frequency is calculated according to FPS/Resolution/ISP running + * mode. + * 2. Ratio is calculated using formula: 2 * HPLL / target frequency - 1 + * with proper rounding. + * 3. Set ratio to ISPFREQ40, 1 to FREQVALID and ISPFREQGUAR40 + * to 200MHz in ISPSSPM1. + * 4. Wait for FREQVALID to be cleared by P-Unit. + * 5. Wait for field ISPFREQSTAT40 in ISPSSPM1 turn to ratio set in 3. + */ +static int write_target_freq_to_hw(struct atomisp_device *isp, + unsigned int new_freq) +{ + unsigned int ratio, timeout, guar_ratio; + u32 isp_sspm1 = 0; + int i; + if (!isp->hpll_freq) { + dev_err(isp->dev, "failed to get hpll_freq. no change to freq\n"); + return -EINVAL; + } + + isp_sspm1 = intel_mid_msgbus_read32(PUNIT_PORT, ISPSSPM1); + if (isp_sspm1 & ISP_FREQ_VALID_MASK) { + dev_dbg(isp->dev, "clearing ISPSSPM1 valid bit.\n"); + intel_mid_msgbus_write32(PUNIT_PORT, ISPSSPM1, + isp_sspm1 & ~(1 << ISP_FREQ_VALID_OFFSET)); + } + + ratio = (2 * isp->hpll_freq + new_freq / 2) / new_freq - 1; + guar_ratio = (2 * isp->hpll_freq + 200 / 2) / 200 - 1; + + isp_sspm1 = intel_mid_msgbus_read32(PUNIT_PORT, ISPSSPM1); + isp_sspm1 &= ~(0x1F << ISP_REQ_FREQ_OFFSET); + + for (i = 0; i < ISP_DFS_TRY_TIMES; i++) { + intel_mid_msgbus_write32(PUNIT_PORT, ISPSSPM1, + isp_sspm1 + | ratio << ISP_REQ_FREQ_OFFSET + | 1 << ISP_FREQ_VALID_OFFSET + | guar_ratio << ISP_REQ_GUAR_FREQ_OFFSET); + + isp_sspm1 = intel_mid_msgbus_read32(PUNIT_PORT, ISPSSPM1); + + timeout = 20; + while ((isp_sspm1 & ISP_FREQ_VALID_MASK) && timeout) { + isp_sspm1 = intel_mid_msgbus_read32(PUNIT_PORT, ISPSSPM1); + dev_dbg(isp->dev, "waiting for ISPSSPM1 valid bit to be 0.\n"); + udelay(100); + timeout--; + } + + if (timeout != 0) + break; + } + + if (timeout == 0) { + dev_err(isp->dev, "DFS failed due to HW error.\n"); + return -EINVAL; + } + + isp_sspm1 = intel_mid_msgbus_read32(PUNIT_PORT, ISPSSPM1); + timeout = 10; + while (((isp_sspm1 >> ISP_FREQ_STAT_OFFSET) != ratio) && timeout) { + isp_sspm1 = intel_mid_msgbus_read32(PUNIT_PORT, ISPSSPM1); + dev_dbg(isp->dev, "waiting for ISPSSPM1 status bit to be 0x%x.\n", + new_freq); + udelay(100); + timeout--; + } + if (timeout == 0) { + dev_err(isp->dev, "DFS target freq is rejected by HW.\n"); + return -EINVAL; + } + + return 0; +} +int atomisp_freq_scaling(struct atomisp_device *isp, + enum atomisp_dfs_mode mode, + bool force) +{ + /* FIXME! Only use subdev[0] status yet */ + struct atomisp_sub_device *asd = &isp->asd[0]; + unsigned int new_freq; + struct atomisp_freq_scaling_rule curr_rules; + int i, ret; + unsigned short fps = 0; + + if (isp->sw_contex.power_state != ATOM_ISP_POWER_UP) { + dev_err(isp->dev, "DFS cannot proceed due to no power.\n"); + return -EINVAL; + } + +#ifdef ISP2401 + if ((isp->pdev->device & ATOMISP_PCI_DEVICE_SOC_MASK) == + ATOMISP_PCI_DEVICE_SOC_CHT && ATOMISP_USE_YUVPP(asd)) + isp->dfs = &dfs_config_cht_soc; + +#endif + if (isp->dfs->lowest_freq == 0 || isp->dfs->max_freq_at_vmin == 0 || + isp->dfs->highest_freq == 0 || isp->dfs->dfs_table_size == 0 || + !isp->dfs->dfs_table) { + dev_err(isp->dev, "DFS configuration is invalid.\n"); + return -EINVAL; + } + + if (mode == ATOMISP_DFS_MODE_LOW) { + new_freq = isp->dfs->lowest_freq; + goto done; + } + + if (mode == ATOMISP_DFS_MODE_MAX) { + new_freq = isp->dfs->highest_freq; + goto done; + } + + fps = atomisp_get_sensor_fps(asd); + if (fps == 0) + return -EINVAL; + + curr_rules.width = asd->fmt[asd->capture_pad].fmt.width; + curr_rules.height = asd->fmt[asd->capture_pad].fmt.height; + curr_rules.fps = fps; + curr_rules.run_mode = asd->run_mode->val; + /* + * For continuous mode, we need to make the capture setting applied + * since preview mode, because there is no chance to do this when + * starting image capture. + */ + if (asd->continuous_mode->val) { + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) + curr_rules.run_mode = ATOMISP_RUN_MODE_SDV; + else + curr_rules.run_mode = + ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE; + } + + /* search for the target frequency by looping freq rules*/ + for (i = 0; i < isp->dfs->dfs_table_size; i++) { + if (curr_rules.width != isp->dfs->dfs_table[i].width && + isp->dfs->dfs_table[i].width != ISP_FREQ_RULE_ANY) + continue; + if (curr_rules.height != isp->dfs->dfs_table[i].height && + isp->dfs->dfs_table[i].height != ISP_FREQ_RULE_ANY) + continue; + if (curr_rules.fps != isp->dfs->dfs_table[i].fps && + isp->dfs->dfs_table[i].fps != ISP_FREQ_RULE_ANY) + continue; + if (curr_rules.run_mode != isp->dfs->dfs_table[i].run_mode && + isp->dfs->dfs_table[i].run_mode != ISP_FREQ_RULE_ANY) + continue; + break; + } + + if (i == isp->dfs->dfs_table_size) + new_freq = isp->dfs->max_freq_at_vmin; + else + new_freq = isp->dfs->dfs_table[i].isp_freq; + +done: + dev_dbg(isp->dev, "DFS target frequency=%d.\n", new_freq); + + if ((new_freq == isp->sw_contex.running_freq) && !force) + return 0; + + dev_dbg(isp->dev, "Programming DFS frequency to %d\n", new_freq); + + ret = write_target_freq_to_hw(isp, new_freq); + if (!ret) { + isp->sw_contex.running_freq = new_freq; + trace_ipu_pstate(new_freq, -1); + } + return ret; +} + +/* + * reset and restore ISP + */ +int atomisp_reset(struct atomisp_device *isp) +{ + /* Reset ISP by power-cycling it */ + int ret = 0; + + dev_dbg(isp->dev, "%s\n", __func__); + atomisp_css_suspend(isp); + ret = atomisp_runtime_suspend(isp->dev); + if (ret < 0) + dev_err(isp->dev, "atomisp_runtime_suspend failed, %d\n", ret); + ret = atomisp_mrfld_power_down(isp); + if (ret < 0) { + dev_err(isp->dev, "can not disable ISP power\n"); + } else { + ret = atomisp_mrfld_power_up(isp); + if (ret < 0) + dev_err(isp->dev, "can not enable ISP power\n"); + ret = atomisp_runtime_resume(isp->dev); + if (ret < 0) + dev_err(isp->dev, "atomisp_runtime_resume failed, %d\n", ret); + } + ret = atomisp_css_resume(isp); + if (ret) + isp->isp_fatal_error = true; + + return ret; +} + +/* + * interrupt enable/disable functions + */ +static void enable_isp_irq(enum hrt_isp_css_irq irq, bool enable) +{ + if (enable) { + irq_enable_channel(IRQ0_ID, irq); + /*sh_css_hrt_irq_enable(irq, true, false);*/ + switch (irq) { /*We only have sp interrupt right now*/ + case hrt_isp_css_irq_sp: + /*sh_css_hrt_irq_enable_sp(true);*/ + cnd_sp_irq_enable(SP0_ID, true); + break; + default: + break; + } + + } else { + /*sh_css_hrt_irq_disable(irq);*/ + irq_disable_channel(IRQ0_ID, irq); + switch (irq) { + case hrt_isp_css_irq_sp: + /*sh_css_hrt_irq_enable_sp(false);*/ + cnd_sp_irq_enable(SP0_ID, false); + break; + default: + break; + } + } +} + +/* + * interrupt clean function + */ +static void clear_isp_irq(enum hrt_isp_css_irq irq) +{ + irq_clear_all(IRQ0_ID); +} + +void atomisp_msi_irq_init(struct atomisp_device *isp, struct pci_dev *dev) +{ + u32 msg32; + u16 msg16; + + pci_read_config_dword(dev, PCI_MSI_CAPID, &msg32); + msg32 |= 1 << MSI_ENABLE_BIT; + pci_write_config_dword(dev, PCI_MSI_CAPID, msg32); + + msg32 = (1 << INTR_IER) | (1 << INTR_IIR); + pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, msg32); + + pci_read_config_word(dev, PCI_COMMAND, &msg16); + msg16 |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | + PCI_COMMAND_INTX_DISABLE); + pci_write_config_word(dev, PCI_COMMAND, msg16); +} + +void atomisp_msi_irq_uninit(struct atomisp_device *isp, struct pci_dev *dev) +{ + u32 msg32; + u16 msg16; + + pci_read_config_dword(dev, PCI_MSI_CAPID, &msg32); + msg32 &= ~(1 << MSI_ENABLE_BIT); + pci_write_config_dword(dev, PCI_MSI_CAPID, msg32); + + msg32 = 0x0; + pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, msg32); + + pci_read_config_word(dev, PCI_COMMAND, &msg16); + msg16 &= ~(PCI_COMMAND_MASTER); + pci_write_config_word(dev, PCI_COMMAND, msg16); +} + +static void atomisp_sof_event(struct atomisp_sub_device *asd) +{ + struct v4l2_event event = {0}; + + event.type = V4L2_EVENT_FRAME_SYNC; + event.u.frame_sync.frame_sequence = atomic_read(&asd->sof_count); + + v4l2_event_queue(asd->subdev.devnode, &event); +} + +void atomisp_eof_event(struct atomisp_sub_device *asd, uint8_t exp_id) +{ + struct v4l2_event event = {0}; + + event.type = V4L2_EVENT_FRAME_END; + event.u.frame_sync.frame_sequence = exp_id; + + v4l2_event_queue(asd->subdev.devnode, &event); +} + +static void atomisp_3a_stats_ready_event(struct atomisp_sub_device *asd, uint8_t exp_id) +{ + struct v4l2_event event = {0}; + + event.type = V4L2_EVENT_ATOMISP_3A_STATS_READY; + event.u.frame_sync.frame_sequence = exp_id; + + v4l2_event_queue(asd->subdev.devnode, &event); +} + +static void atomisp_metadata_ready_event(struct atomisp_sub_device *asd, + enum atomisp_metadata_type md_type) +{ + struct v4l2_event event = {0}; + + event.type = V4L2_EVENT_ATOMISP_METADATA_READY; + event.u.data[0] = md_type; + + v4l2_event_queue(asd->subdev.devnode, &event); +} + +static void atomisp_reset_event(struct atomisp_sub_device *asd) +{ + struct v4l2_event event = {0}; + + event.type = V4L2_EVENT_ATOMISP_CSS_RESET; + + v4l2_event_queue(asd->subdev.devnode, &event); +} + + +static void print_csi_rx_errors(enum ia_css_csi2_port port, + struct atomisp_device *isp) +{ + u32 infos = 0; + + atomisp_css_rx_get_irq_info(port, &infos); + + dev_err(isp->dev, "CSI Receiver port %d errors:\n", port); + if (infos & CSS_RX_IRQ_INFO_BUFFER_OVERRUN) + dev_err(isp->dev, " buffer overrun"); + if (infos & CSS_RX_IRQ_INFO_ERR_SOT) + dev_err(isp->dev, " start-of-transmission error"); + if (infos & CSS_RX_IRQ_INFO_ERR_SOT_SYNC) + dev_err(isp->dev, " start-of-transmission sync error"); + if (infos & CSS_RX_IRQ_INFO_ERR_CONTROL) + dev_err(isp->dev, " control error"); + if (infos & CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE) + dev_err(isp->dev, " 2 or more ECC errors"); + if (infos & CSS_RX_IRQ_INFO_ERR_CRC) + dev_err(isp->dev, " CRC mismatch"); + if (infos & CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID) + dev_err(isp->dev, " unknown error"); + if (infos & CSS_RX_IRQ_INFO_ERR_FRAME_SYNC) + dev_err(isp->dev, " frame sync error"); + if (infos & CSS_RX_IRQ_INFO_ERR_FRAME_DATA) + dev_err(isp->dev, " frame data error"); + if (infos & CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT) + dev_err(isp->dev, " data timeout"); + if (infos & CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC) + dev_err(isp->dev, " unknown escape command entry"); + if (infos & CSS_RX_IRQ_INFO_ERR_LINE_SYNC) + dev_err(isp->dev, " line sync error"); +} + +/* Clear irq reg */ +static void clear_irq_reg(struct atomisp_device *isp) +{ + u32 msg_ret; + pci_read_config_dword(isp->pdev, PCI_INTERRUPT_CTRL, &msg_ret); + msg_ret |= 1 << INTR_IIR; + pci_write_config_dword(isp->pdev, PCI_INTERRUPT_CTRL, msg_ret); +} + +static struct atomisp_sub_device * +__get_asd_from_port(struct atomisp_device *isp, mipi_port_ID_t port) +{ + int i; + + /* Check which isp subdev to send eof */ + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd = &isp->asd[i]; + struct camera_mipi_info *mipi_info = + atomisp_to_sensor_mipi_info( + isp->inputs[asd->input_curr].camera); + if (isp->asd[i].streaming == ATOMISP_DEVICE_STREAMING_ENABLED && + __get_mipi_port(isp, mipi_info->port) == port) { + return &isp->asd[i]; + } + } + + return NULL; +} + +/* interrupt handling function*/ +irqreturn_t atomisp_isr(int irq, void *dev) +{ + struct atomisp_device *isp = (struct atomisp_device *)dev; + struct atomisp_sub_device *asd; + struct atomisp_css_event eof_event; + unsigned int irq_infos = 0; + unsigned long flags; + unsigned int i; + int err; + + spin_lock_irqsave(&isp->lock, flags); + if (isp->sw_contex.power_state != ATOM_ISP_POWER_UP || + isp->css_initialized == false) { + spin_unlock_irqrestore(&isp->lock, flags); + return IRQ_HANDLED; + } + err = atomisp_css_irq_translate(isp, &irq_infos); + if (err) { + spin_unlock_irqrestore(&isp->lock, flags); + return IRQ_NONE; + } + + dev_dbg(isp->dev, "irq:0x%x\n", irq_infos); + + clear_irq_reg(isp); + + if (!atomisp_streaming_count(isp) && !atomisp_is_acc_enabled(isp)) + goto out_nowake; + + for (i = 0; i < isp->num_of_streams; i++) { + asd = &isp->asd[i]; + + if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED) + continue; + /* + * Current SOF only support one stream, so the SOF only valid + * either solely one stream is running + */ + if (irq_infos & CSS_IRQ_INFO_CSS_RECEIVER_SOF) { + atomic_inc(&asd->sof_count); + atomisp_sof_event(asd); + + /* If sequence_temp and sequence are the same + * there where no frames lost so we can increase + * sequence_temp. + * If not then processing of frame is still in progress + * and driver needs to keep old sequence_temp value. + * NOTE: There is assumption here that ISP will not + * start processing next frame from sensor before old + * one is completely done. */ + if (atomic_read(&asd->sequence) == atomic_read( + &asd->sequence_temp)) + atomic_set(&asd->sequence_temp, + atomic_read(&asd->sof_count)); + } + if (irq_infos & CSS_IRQ_INFO_EVENTS_READY) + atomic_set(&asd->sequence, + atomic_read(&asd->sequence_temp)); + } + + if (irq_infos & CSS_IRQ_INFO_CSS_RECEIVER_SOF) + irq_infos &= ~CSS_IRQ_INFO_CSS_RECEIVER_SOF; + + if ((irq_infos & CSS_IRQ_INFO_INPUT_SYSTEM_ERROR) || + (irq_infos & CSS_IRQ_INFO_IF_ERROR)) { + /* handle mipi receiver error */ + u32 rx_infos; + enum ia_css_csi2_port port; + + for (port = IA_CSS_CSI2_PORT0; port <= IA_CSS_CSI2_PORT2; + port++) { + print_csi_rx_errors(port, isp); + atomisp_css_rx_get_irq_info(port, &rx_infos); + atomisp_css_rx_clear_irq_info(port, rx_infos); + } + } + + if (irq_infos & IA_CSS_IRQ_INFO_ISYS_EVENTS_READY) { + while (ia_css_dequeue_isys_event(&(eof_event.event)) == + IA_CSS_SUCCESS) { + /* EOF Event does not have the css_pipe returned */ + asd = __get_asd_from_port(isp, eof_event.event.port); + if (!asd) { + dev_err(isp->dev, "%s:no subdev.event:%d", __func__, + eof_event.event.type); + continue; + } + + atomisp_eof_event(asd, eof_event.event.exp_id); +#ifndef ISP2401 + dev_dbg(isp->dev, "%s EOF exp_id %d\n", __func__, + eof_event.event.exp_id); +#else + dev_dbg(isp->dev, "%s EOF exp_id %d, asd %d\n", + __func__, eof_event.event.exp_id, asd->index); +#endif + } + + irq_infos &= ~IA_CSS_IRQ_INFO_ISYS_EVENTS_READY; + if (irq_infos == 0) + goto out_nowake; + } + + spin_unlock_irqrestore(&isp->lock, flags); + + return IRQ_WAKE_THREAD; + +out_nowake: + spin_unlock_irqrestore(&isp->lock, flags); + + return IRQ_HANDLED; +} + +void atomisp_clear_css_buffer_counters(struct atomisp_sub_device *asd) +{ + int i; + memset(asd->s3a_bufs_in_css, 0, sizeof(asd->s3a_bufs_in_css)); + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) + memset(asd->metadata_bufs_in_css[i], 0, + sizeof(asd->metadata_bufs_in_css[i])); + asd->dis_bufs_in_css = 0; + asd->video_out_capture.buffers_in_css = 0; + asd->video_out_vf.buffers_in_css = 0; + asd->video_out_preview.buffers_in_css = 0; + asd->video_out_video_capture.buffers_in_css = 0; +} + +#ifndef ISP2401 +bool atomisp_buffers_queued(struct atomisp_sub_device *asd) +#else +bool atomisp_buffers_queued_pipe(struct atomisp_video_pipe *pipe) +#endif +{ +#ifndef ISP2401 + return asd->video_out_capture.buffers_in_css || + asd->video_out_vf.buffers_in_css || + asd->video_out_preview.buffers_in_css || + asd->video_out_video_capture.buffers_in_css ? + true : false; +#else + return pipe->buffers_in_css ? true : false; +#endif +} + +/* 0x100000 is the start of dmem inside SP */ +#define SP_DMEM_BASE 0x100000 + +void dump_sp_dmem(struct atomisp_device *isp, unsigned int addr, + unsigned int size) +{ + unsigned int data = 0; + unsigned int size32 = DIV_ROUND_UP(size, sizeof(u32)); + + dev_dbg(isp->dev, "atomisp_io_base:%p\n", atomisp_io_base); + dev_dbg(isp->dev, "%s, addr:0x%x, size: %d, size32: %d\n", __func__, + addr, size, size32); + if (size32 * 4 + addr > 0x4000) { + dev_err(isp->dev, "illegal size (%d) or addr (0x%x)\n", + size32, addr); + return; + } + addr += SP_DMEM_BASE; + do { + data = _hrt_master_port_uload_32(addr); + + dev_dbg(isp->dev, "%s, \t [0x%x]:0x%x\n", __func__, addr, data); + addr += sizeof(unsigned int); + size32 -= 1; + } while (size32 > 0); +} + +static struct videobuf_buffer *atomisp_css_frame_to_vbuf( + struct atomisp_video_pipe *pipe, struct atomisp_css_frame *frame) +{ + struct videobuf_vmalloc_memory *vm_mem; + struct atomisp_css_frame *handle; + int i; + + for (i = 0; pipe->capq.bufs[i]; i++) { + vm_mem = pipe->capq.bufs[i]->priv; + handle = vm_mem->vaddr; + if (handle && handle->data == frame->data) + return pipe->capq.bufs[i]; + } + + return NULL; +} + +static void get_buf_timestamp(struct timeval *tv) +{ + struct timespec ts; + ktime_get_ts(&ts); + tv->tv_sec = ts.tv_sec; + tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC; +} + +static void atomisp_flush_video_pipe(struct atomisp_sub_device *asd, + struct atomisp_video_pipe *pipe) +{ + unsigned long irqflags; + int i; + + if (!pipe->users) + return; + + for (i = 0; pipe->capq.bufs[i]; i++) { + spin_lock_irqsave(&pipe->irq_lock, irqflags); + if (pipe->capq.bufs[i]->state == VIDEOBUF_ACTIVE || + pipe->capq.bufs[i]->state == VIDEOBUF_QUEUED) { + get_buf_timestamp(&pipe->capq.bufs[i]->ts); + pipe->capq.bufs[i]->field_count = + atomic_read(&asd->sequence) << 1; + dev_dbg(asd->isp->dev, "release buffers on device %s\n", + pipe->vdev.name); + if (pipe->capq.bufs[i]->state == VIDEOBUF_QUEUED) + list_del_init(&pipe->capq.bufs[i]->queue); + pipe->capq.bufs[i]->state = VIDEOBUF_ERROR; + wake_up(&pipe->capq.bufs[i]->done); + } + spin_unlock_irqrestore(&pipe->irq_lock, irqflags); + } +} + +/* Returns queued buffers back to video-core */ +void atomisp_flush_bufs_and_wakeup(struct atomisp_sub_device *asd) +{ + atomisp_flush_video_pipe(asd, &asd->video_out_capture); + atomisp_flush_video_pipe(asd, &asd->video_out_vf); + atomisp_flush_video_pipe(asd, &asd->video_out_preview); + atomisp_flush_video_pipe(asd, &asd->video_out_video_capture); +} + +/* clean out the parameters that did not apply */ +void atomisp_flush_params_queue(struct atomisp_video_pipe *pipe) +{ + struct atomisp_css_params_with_list *param; + + while (!list_empty(&pipe->per_frame_params)) { + param = list_entry(pipe->per_frame_params.next, + struct atomisp_css_params_with_list, list); + list_del(¶m->list); + atomisp_free_css_parameters(¶m->params); + atomisp_kernel_free(param); + } +} + +/* Re-queue per-frame parameters */ +static void atomisp_recover_params_queue(struct atomisp_video_pipe *pipe) +{ + struct atomisp_css_params_with_list *param; + int i; + + for (i = 0; i < VIDEO_MAX_FRAME; i++) { + param = pipe->frame_params[i]; + if (param) + list_add_tail(¶m->list, &pipe->per_frame_params); + pipe->frame_params[i] = NULL; + } + atomisp_handle_parameter_and_buffer(pipe); +} + +/* find atomisp_video_pipe with css pipe id, buffer type and atomisp run_mode */ +static struct atomisp_video_pipe *__atomisp_get_pipe( + struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_pipe_id css_pipe_id, + enum atomisp_css_buffer_type buf_type) +{ + struct atomisp_device *isp = asd->isp; + + if (css_pipe_id == CSS_PIPE_ID_COPY && + isp->inputs[asd->input_curr].camera_caps-> + sensor[asd->sensor_curr].stream_num > 1) { + switch (stream_id) { + case ATOMISP_INPUT_STREAM_PREVIEW: + return &asd->video_out_preview; + case ATOMISP_INPUT_STREAM_POSTVIEW: + return &asd->video_out_vf; + case ATOMISP_INPUT_STREAM_VIDEO: + return &asd->video_out_video_capture; + case ATOMISP_INPUT_STREAM_CAPTURE: + default: + return &asd->video_out_capture; + } + } + + /* video is same in online as in continuouscapture mode */ + if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_LOWLAT) { + /* + * Disable vf_pp and run CSS in still capture mode. In this + * mode, CSS does not cause extra latency with buffering, but + * scaling is not available. + */ + return &asd->video_out_capture; + } else if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_SCALER) { + /* + * Disable vf_pp and run CSS in video mode. This allows using + * ISP scaling but it has one frame delay due to CSS internal + * buffering. + */ + return &asd->video_out_video_capture; + } else if (css_pipe_id == CSS_PIPE_ID_YUVPP) { + /* + * to SOC camera, yuvpp pipe is run for capture/video/SDV/ZSL. + */ + if (asd->continuous_mode->val) { + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) { + /* SDV case */ + switch (buf_type) { + case CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME: + return &asd->video_out_video_capture; + case CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME: + return &asd->video_out_preview; + case CSS_BUFFER_TYPE_OUTPUT_FRAME: + return &asd->video_out_capture; + default: + return &asd->video_out_vf; + } + } else if (asd->run_mode->val == ATOMISP_RUN_MODE_PREVIEW) { + /* ZSL case */ + switch (buf_type) { + case CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME: + return &asd->video_out_preview; + case CSS_BUFFER_TYPE_OUTPUT_FRAME: + return &asd->video_out_capture; + default: + return &asd->video_out_vf; + } + } + } else if (buf_type == CSS_BUFFER_TYPE_OUTPUT_FRAME) { + switch (asd->run_mode->val) { + case ATOMISP_RUN_MODE_VIDEO: + return &asd->video_out_video_capture; + case ATOMISP_RUN_MODE_PREVIEW: + return &asd->video_out_preview; + default: + return &asd->video_out_capture; + } + } else if (buf_type == CSS_BUFFER_TYPE_VF_OUTPUT_FRAME) { + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) + return &asd->video_out_preview; + else + return &asd->video_out_vf; + } + } else if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) { + /* For online video or SDV video pipe. */ + if (css_pipe_id == CSS_PIPE_ID_VIDEO || + css_pipe_id == CSS_PIPE_ID_COPY || + css_pipe_id == CSS_PIPE_ID_YUVPP) { + if (buf_type == CSS_BUFFER_TYPE_OUTPUT_FRAME) + return &asd->video_out_video_capture; + return &asd->video_out_preview; + } + } else if (asd->run_mode->val == ATOMISP_RUN_MODE_PREVIEW) { + /* For online preview or ZSL preview pipe. */ + if (css_pipe_id == CSS_PIPE_ID_PREVIEW || + css_pipe_id == CSS_PIPE_ID_COPY || + css_pipe_id == CSS_PIPE_ID_YUVPP) + return &asd->video_out_preview; + } + /* For capture pipe. */ + if (buf_type == CSS_BUFFER_TYPE_VF_OUTPUT_FRAME) + return &asd->video_out_vf; + return &asd->video_out_capture; +} + +enum atomisp_metadata_type +atomisp_get_metadata_type(struct atomisp_sub_device *asd, + enum ia_css_pipe_id pipe_id) +{ + if (!asd->continuous_mode->val) + return ATOMISP_MAIN_METADATA; + + if (pipe_id == IA_CSS_PIPE_ID_CAPTURE) /* online capture pipe */ + return ATOMISP_SEC_METADATA; + else + return ATOMISP_MAIN_METADATA; +} + +void atomisp_buf_done(struct atomisp_sub_device *asd, int error, + enum atomisp_css_buffer_type buf_type, + enum atomisp_css_pipe_id css_pipe_id, + bool q_buffers, enum atomisp_input_stream_id stream_id) +{ + struct videobuf_buffer *vb = NULL; + struct atomisp_video_pipe *pipe = NULL; + struct atomisp_css_buffer buffer; + bool requeue = false; + int err; + unsigned long irqflags; + struct atomisp_css_frame *frame = NULL; + struct atomisp_s3a_buf *s3a_buf = NULL, *_s3a_buf_tmp; + struct atomisp_dis_buf *dis_buf = NULL, *_dis_buf_tmp; + struct atomisp_metadata_buf *md_buf = NULL, *_md_buf_tmp; + enum atomisp_metadata_type md_type; + struct atomisp_device *isp = asd->isp; + struct v4l2_control ctrl; +#ifdef ISP2401 + bool reset_wdt_timer = false; +#endif + + if ( + buf_type != CSS_BUFFER_TYPE_METADATA && + buf_type != CSS_BUFFER_TYPE_3A_STATISTICS && + buf_type != CSS_BUFFER_TYPE_DIS_STATISTICS && + buf_type != CSS_BUFFER_TYPE_OUTPUT_FRAME && + buf_type != CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME && + buf_type != CSS_BUFFER_TYPE_RAW_OUTPUT_FRAME && + buf_type != CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME && + buf_type != CSS_BUFFER_TYPE_VF_OUTPUT_FRAME) { + dev_err(isp->dev, "%s, unsupported buffer type: %d\n", + __func__, buf_type); + return; + } + + memset(&buffer, 0, sizeof(struct atomisp_css_buffer)); + buffer.css_buffer.type = buf_type; + err = atomisp_css_dequeue_buffer(asd, stream_id, css_pipe_id, + buf_type, &buffer); + if (err) { + dev_err(isp->dev, + "atomisp_css_dequeue_buffer failed: 0x%x\n", err); + return; + } + + /* need to know the atomisp pipe for frame buffers */ + pipe = __atomisp_get_pipe(asd, stream_id, css_pipe_id, buf_type); + if (pipe == NULL) { + dev_err(isp->dev, "error getting atomisp pipe\n"); + return; + } + + switch (buf_type) { + case CSS_BUFFER_TYPE_3A_STATISTICS: + list_for_each_entry_safe(s3a_buf, _s3a_buf_tmp, + &asd->s3a_stats_in_css, list) { + if (s3a_buf->s3a_data == + buffer.css_buffer.data.stats_3a) { + list_del_init(&s3a_buf->list); + list_add_tail(&s3a_buf->list, + &asd->s3a_stats_ready); + break; + } + } + + asd->s3a_bufs_in_css[css_pipe_id]--; + atomisp_3a_stats_ready_event(asd, buffer.css_buffer.exp_id); + dev_dbg(isp->dev, "%s: s3a stat with exp_id %d is ready\n", + __func__, s3a_buf->s3a_data->exp_id); + break; + case CSS_BUFFER_TYPE_METADATA: + if (error) + break; + + md_type = atomisp_get_metadata_type(asd, css_pipe_id); + list_for_each_entry_safe(md_buf, _md_buf_tmp, + &asd->metadata_in_css[md_type], list) { + if (md_buf->metadata == + buffer.css_buffer.data.metadata) { + list_del_init(&md_buf->list); + list_add_tail(&md_buf->list, + &asd->metadata_ready[md_type]); + break; + } + } + asd->metadata_bufs_in_css[stream_id][css_pipe_id]--; + atomisp_metadata_ready_event(asd, md_type); + dev_dbg(isp->dev, "%s: metadata with exp_id %d is ready\n", + __func__, md_buf->metadata->exp_id); + break; + case CSS_BUFFER_TYPE_DIS_STATISTICS: + list_for_each_entry_safe(dis_buf, _dis_buf_tmp, + &asd->dis_stats_in_css, list) { + if (dis_buf->dis_data == + buffer.css_buffer.data.stats_dvs) { + spin_lock_irqsave(&asd->dis_stats_lock, + irqflags); + list_del_init(&dis_buf->list); + list_add(&dis_buf->list, &asd->dis_stats); + asd->params.dis_proj_data_valid = true; + spin_unlock_irqrestore(&asd->dis_stats_lock, + irqflags); + break; + } + } + asd->dis_bufs_in_css--; + dev_dbg(isp->dev, "%s: dis stat with exp_id %d is ready\n", + __func__, dis_buf->dis_data->exp_id); + break; + case CSS_BUFFER_TYPE_VF_OUTPUT_FRAME: + case CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME: +#ifdef ISP2401 + reset_wdt_timer = true; +#endif + pipe->buffers_in_css--; + frame = buffer.css_buffer.data.frame; + if (!frame) { + WARN_ON(1); + break; + } + if (!frame->valid) + error = true; + + /* FIXME: + * YUVPP doesn't set postview exp_id correctlly in SDV mode. + * This is a WORKAROUND to set exp_id. see HSDES-1503911606. + */ + if (IS_BYT && buf_type == CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME && + asd->continuous_mode->val && ATOMISP_USE_YUVPP(asd)) + frame->exp_id = (asd->postview_exp_id++) % + (ATOMISP_MAX_EXP_ID + 1); + + dev_dbg(isp->dev, "%s: vf frame with exp_id %d is ready\n", + __func__, frame->exp_id); + if (asd->params.flash_state == ATOMISP_FLASH_ONGOING) { + if (frame->flash_state + == CSS_FRAME_FLASH_STATE_PARTIAL) + dev_dbg(isp->dev, "%s thumb partially flashed\n", + __func__); + else if (frame->flash_state + == CSS_FRAME_FLASH_STATE_FULL) + dev_dbg(isp->dev, "%s thumb completely flashed\n", + __func__); + else + dev_dbg(isp->dev, "%s thumb no flash in this frame\n", + __func__); + } + vb = atomisp_css_frame_to_vbuf(pipe, frame); + WARN_ON(!vb); + if (vb) + pipe->frame_config_id[vb->i] = frame->isp_config_id; +#ifndef ISP2401 + if (css_pipe_id == IA_CSS_PIPE_ID_CAPTURE && + asd->pending_capture_request > 0) { + err = atomisp_css_offline_capture_configure(asd, +#else + if (css_pipe_id == IA_CSS_PIPE_ID_CAPTURE) { + if (asd->pending_capture_request > 0) { + err = atomisp_css_offline_capture_configure(asd, +#endif + asd->params.offline_parm.num_captures, + asd->params.offline_parm.skip_frames, + asd->params.offline_parm.offset); +#ifndef ISP2401 + asd->pending_capture_request--; + dev_dbg(isp->dev, "Trigger capture again for new buffer. err=%d\n", + err); +#else + asd->pending_capture_request--; + asd->re_trigger_capture = false; + dev_dbg(isp->dev, "Trigger capture again for new buffer. err=%d\n", + err); + } else { + asd->re_trigger_capture = true; + } +#endif + } + break; + case CSS_BUFFER_TYPE_OUTPUT_FRAME: + case CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME: +#ifdef ISP2401 + reset_wdt_timer = true; +#endif + pipe->buffers_in_css--; + frame = buffer.css_buffer.data.frame; + if (!frame) { + WARN_ON(1); + break; + } + + if (!frame->valid) + error = true; + + /* FIXME: + * YUVPP doesn't set preview exp_id correctlly in ZSL mode. + * This is a WORKAROUND to set exp_id. see HSDES-1503911606. + */ + if (IS_BYT && buf_type == CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME && + asd->continuous_mode->val && ATOMISP_USE_YUVPP(asd)) + frame->exp_id = (asd->preview_exp_id++) % + (ATOMISP_MAX_EXP_ID + 1); + + dev_dbg(isp->dev, "%s: main frame with exp_id %d is ready\n", + __func__, frame->exp_id); + vb = atomisp_css_frame_to_vbuf(pipe, frame); + if (!vb) { + WARN_ON(1); + break; + } + + /* free the parameters */ + if (pipe->frame_params[vb->i]) { + if (asd->params.dvs_6axis == + pipe->frame_params[vb->i]->params.dvs_6axis) + asd->params.dvs_6axis = NULL; + atomisp_free_css_parameters( + &pipe->frame_params[vb->i]->params); + atomisp_kernel_free(pipe->frame_params[vb->i]); + pipe->frame_params[vb->i] = NULL; + } + + pipe->frame_config_id[vb->i] = frame->isp_config_id; + ctrl.id = V4L2_CID_FLASH_MODE; + if (asd->params.flash_state == ATOMISP_FLASH_ONGOING) { + if (frame->flash_state + == CSS_FRAME_FLASH_STATE_PARTIAL) { + asd->frame_status[vb->i] = + ATOMISP_FRAME_STATUS_FLASH_PARTIAL; + dev_dbg(isp->dev, "%s partially flashed\n", + __func__); + } else if (frame->flash_state + == CSS_FRAME_FLASH_STATE_FULL) { + asd->frame_status[vb->i] = + ATOMISP_FRAME_STATUS_FLASH_EXPOSED; + asd->params.num_flash_frames--; + dev_dbg(isp->dev, "%s completely flashed\n", + __func__); + } else { + asd->frame_status[vb->i] = + ATOMISP_FRAME_STATUS_OK; + dev_dbg(isp->dev, + "%s no flash in this frame\n", + __func__); + } + + /* Check if flashing sequence is done */ + if (asd->frame_status[vb->i] == + ATOMISP_FRAME_STATUS_FLASH_EXPOSED) + asd->params.flash_state = ATOMISP_FLASH_DONE; + } else if (isp->flash) { + if (v4l2_g_ctrl(isp->flash->ctrl_handler, &ctrl) == + 0 && ctrl.value == ATOMISP_FLASH_MODE_TORCH) { + ctrl.id = V4L2_CID_FLASH_TORCH_INTENSITY; + if (v4l2_g_ctrl(isp->flash->ctrl_handler, &ctrl) + == 0 && ctrl.value > 0) { + asd->frame_status[vb->i] = + ATOMISP_FRAME_STATUS_FLASH_EXPOSED; + } else { + asd->frame_status[vb->i] = + ATOMISP_FRAME_STATUS_OK; + } + } else + asd->frame_status[vb->i] = + ATOMISP_FRAME_STATUS_OK; + } else { + asd->frame_status[vb->i] = ATOMISP_FRAME_STATUS_OK; + } + + asd->params.last_frame_status = asd->frame_status[vb->i]; + + if (asd->continuous_mode->val) { + if (css_pipe_id == CSS_PIPE_ID_PREVIEW || + css_pipe_id == CSS_PIPE_ID_VIDEO) { + asd->latest_preview_exp_id = frame->exp_id; + } else if (css_pipe_id == + CSS_PIPE_ID_CAPTURE) { + if (asd->run_mode->val == + ATOMISP_RUN_MODE_VIDEO) + dev_dbg(isp->dev, "SDV capture raw buffer id: %u\n", + frame->exp_id); + else + dev_dbg(isp->dev, "ZSL capture raw buffer id: %u\n", + frame->exp_id); + } + } + /* + * Only after enabled the raw buffer lock + * and in continuous mode. + * in preview/video pipe, each buffer will + * be locked automatically, so record it here. + */ + if (((css_pipe_id == CSS_PIPE_ID_PREVIEW) || + (css_pipe_id == CSS_PIPE_ID_VIDEO)) && + asd->enable_raw_buffer_lock->val && + asd->continuous_mode->val) { + atomisp_set_raw_buffer_bitmap(asd, frame->exp_id); + WARN_ON(frame->exp_id > ATOMISP_MAX_EXP_ID); + } + + if (asd->params.css_update_params_needed) { + atomisp_apply_css_parameters(asd, + &asd->params.css_param); + if (asd->params.css_param.update_flag.dz_config) + atomisp_css_set_dz_config(asd, + &asd->params.css_param.dz_config); + /* New global dvs 6axis config should be blocked + * here if there's a buffer with per-frame parameters + * pending in CSS frame buffer queue. + * This is to aviod zooming vibration since global + * parameters take effect immediately while + * per-frame parameters are taken after previous + * buffers in CSS got processed. + */ + if (asd->params.dvs_6axis) + atomisp_css_set_dvs_6axis(asd, + asd->params.dvs_6axis); + else + asd->params.css_update_params_needed = false; + /* The update flag should not be cleaned here + * since it is still going to be used to make up + * following per-frame parameters. + * This will introduce more copy work since each + * time when updating global parameters, the whole + * parameter set are applied. + * FIXME: A new set of parameter copy functions can + * be added to make up per-frame parameters based on + * solid structures stored in asd->params.css_param + * instead of using shadow pointers in update flag. + */ + atomisp_css_update_isp_params(asd); + } + break; + default: + break; + } + if (vb) { + get_buf_timestamp(&vb->ts); + vb->field_count = atomic_read(&asd->sequence) << 1; + /*mark videobuffer done for dequeue*/ + spin_lock_irqsave(&pipe->irq_lock, irqflags); + vb->state = !error ? VIDEOBUF_DONE : VIDEOBUF_ERROR; + spin_unlock_irqrestore(&pipe->irq_lock, irqflags); + + /* + * Frame capture done, wake up any process block on + * current active buffer + * possibly hold by videobuf_dqbuf() + */ + wake_up(&vb->done); + } +#ifndef ISP2401 + +#else + atomic_set(&pipe->wdt_count, 0); +#endif + /* + * Requeue should only be done for 3a and dis buffers. + * Queue/dequeue order will change if driver recycles image buffers. + */ + if (requeue) { + err = atomisp_css_queue_buffer(asd, + stream_id, css_pipe_id, + buf_type, &buffer); + if (err) + dev_err(isp->dev, "%s, q to css fails: %d\n", + __func__, err); + return; + } + if (!error && q_buffers) + atomisp_qbuffers_to_css(asd); +#ifdef ISP2401 + + /* If there are no buffers queued then + * delete wdt timer. */ + if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED) + return; + if (!atomisp_buffers_queued_pipe(pipe)) + atomisp_wdt_stop_pipe(pipe, false); + else if (reset_wdt_timer) + /* SOF irq should not reset wdt timer. */ + atomisp_wdt_refresh_pipe(pipe, + ATOMISP_WDT_KEEP_CURRENT_DELAY); +#endif +} + +void atomisp_delayed_init_work(struct work_struct *work) +{ + struct atomisp_sub_device *asd = container_of(work, + struct atomisp_sub_device, + delayed_init_work); + /* + * to SOC camera, use yuvpp pipe and no support continuous mode. + */ + if (!ATOMISP_USE_YUVPP(asd)) { + struct v4l2_event event = {0}; + + atomisp_css_allocate_continuous_frames(false, asd); + atomisp_css_update_continuous_frames(asd); + + event.type = V4L2_EVENT_ATOMISP_RAW_BUFFERS_ALLOC_DONE; + v4l2_event_queue(asd->subdev.devnode, &event); + } + + /* signal streamon after delayed init is done */ + asd->delayed_init = ATOMISP_DELAYED_INIT_DONE; + complete(&asd->init_done); +} + +static void __atomisp_css_recover(struct atomisp_device *isp, bool isp_timeout) +{ + enum atomisp_css_pipe_id css_pipe_id; + bool stream_restart[MAX_STREAM_NUM] = {0}; + bool depth_mode = false; + int i, ret, depth_cnt = 0; + + if (!isp->sw_contex.file_input) + atomisp_css_irq_enable(isp, + CSS_IRQ_INFO_CSS_RECEIVER_SOF, false); + + BUG_ON(isp->num_of_streams > MAX_STREAM_NUM); + + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd = &isp->asd[i]; + struct ia_css_pipeline *acc_pipeline; + struct ia_css_pipe *acc_pipe = NULL; + + if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED && + !asd->stream_prepared) + continue; + + /* + * AtomISP::waitStageUpdate is blocked when WDT happens. + * By calling acc_done() for all loaded fw_handles, + * HAL will be unblocked. + */ + acc_pipe = asd->stream_env[i].pipes[CSS_PIPE_ID_ACC]; + if (acc_pipe != NULL) { + acc_pipeline = ia_css_pipe_get_pipeline(acc_pipe); + if (acc_pipeline) { + struct ia_css_pipeline_stage *stage; + for (stage = acc_pipeline->stages; stage; + stage = stage->next) { + const struct ia_css_fw_info *fw; + fw = stage->firmware; + atomisp_acc_done(asd, fw->handle); + } + } + } + + depth_cnt++; + + if (asd->delayed_init == ATOMISP_DELAYED_INIT_QUEUED) + cancel_work_sync(&asd->delayed_init_work); + + complete(&asd->init_done); + asd->delayed_init = ATOMISP_DELAYED_INIT_NOT_QUEUED; + + stream_restart[asd->index] = true; + + asd->streaming = ATOMISP_DEVICE_STREAMING_STOPPING; + + /* stream off sensor */ + ret = v4l2_subdev_call( + isp->inputs[asd->input_curr]. + camera, video, s_stream, 0); + if (ret) + dev_warn(isp->dev, + "can't stop streaming on sensor!\n"); + + atomisp_acc_unload_extensions(asd); + + atomisp_clear_css_buffer_counters(asd); + + css_pipe_id = atomisp_get_css_pipe_id(asd); + atomisp_css_stop(asd, css_pipe_id, true); + + asd->streaming = ATOMISP_DEVICE_STREAMING_DISABLED; + + asd->preview_exp_id = 1; + asd->postview_exp_id = 1; + /* notify HAL the CSS reset */ + dev_dbg(isp->dev, + "send reset event to %s\n", asd->subdev.devnode->name); + atomisp_reset_event(asd); + } + + /* clear irq */ + enable_isp_irq(hrt_isp_css_irq_sp, false); + clear_isp_irq(hrt_isp_css_irq_sp); + + /* Set the SRSE to 3 before resetting */ + pci_write_config_dword(isp->pdev, PCI_I_CONTROL, isp->saved_regs.i_control | + MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK); + + /* reset ISP and restore its state */ + isp->isp_timeout = true; + atomisp_reset(isp); + isp->isp_timeout = false; + + if (!isp_timeout) { + for (i = 0; i < isp->num_of_streams; i++) { + if (isp->asd[i].depth_mode->val) + return; + } + } + + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd = &isp->asd[i]; + + if (!stream_restart[i]) + continue; + + if (isp->inputs[asd->input_curr].type != FILE_INPUT) + atomisp_css_input_set_mode(asd, + CSS_INPUT_MODE_SENSOR); + + css_pipe_id = atomisp_get_css_pipe_id(asd); + if (atomisp_css_start(asd, css_pipe_id, true)) + dev_warn(isp->dev, + "start SP failed, so do not set streaming to be enable!\n"); + else + asd->streaming = ATOMISP_DEVICE_STREAMING_ENABLED; + + atomisp_csi2_configure(asd); + } + + if (!isp->sw_contex.file_input) { + atomisp_css_irq_enable(isp, CSS_IRQ_INFO_CSS_RECEIVER_SOF, + atomisp_css_valid_sof(isp)); + + if (atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_AUTO, true) < 0) + dev_dbg(isp->dev, "dfs failed!\n"); + } else { + if (atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_MAX, true) < 0) + dev_dbg(isp->dev, "dfs failed!\n"); + } + + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd; + + asd = &isp->asd[i]; + + if (!stream_restart[i]) + continue; + + if (asd->continuous_mode->val && + asd->delayed_init == ATOMISP_DELAYED_INIT_NOT_QUEUED) { + reinit_completion(&asd->init_done); + asd->delayed_init = ATOMISP_DELAYED_INIT_QUEUED; + queue_work(asd->delayed_init_workq, + &asd->delayed_init_work); + } + /* + * dequeueing buffers is not needed. CSS will recycle + * buffers that it has. + */ + atomisp_flush_bufs_and_wakeup(asd); + + /* Requeue unprocessed per-frame parameters. */ + atomisp_recover_params_queue(&asd->video_out_capture); + atomisp_recover_params_queue(&asd->video_out_preview); + atomisp_recover_params_queue(&asd->video_out_video_capture); + + if ((asd->depth_mode->val) && + (depth_cnt == ATOMISP_DEPTH_SENSOR_STREAMON_COUNT)) { + depth_mode = true; + continue; + } + + ret = v4l2_subdev_call( + isp->inputs[asd->input_curr].camera, video, + s_stream, 1); + if (ret) + dev_warn(isp->dev, + "can't start streaming on sensor!\n"); + + } + + if (depth_mode) { + if (atomisp_stream_on_master_slave_sensor(isp, true)) + dev_warn(isp->dev, + "master slave sensor stream on failed!\n"); + } +} + +void atomisp_wdt_work(struct work_struct *work) +{ + struct atomisp_device *isp = container_of(work, struct atomisp_device, + wdt_work); + int i; +#ifdef ISP2401 + unsigned int pipe_wdt_cnt[MAX_STREAM_NUM][4] = { {0} }; + bool css_recover = true; +#endif + + rt_mutex_lock(&isp->mutex); + if (!atomisp_streaming_count(isp)) { + atomic_set(&isp->wdt_work_queued, 0); + rt_mutex_unlock(&isp->mutex); + return; + } + +#ifndef ISP2401 + dev_err(isp->dev, "timeout %d of %d\n", + atomic_read(&isp->wdt_count) + 1, + ATOMISP_ISP_MAX_TIMEOUT_COUNT); +#else + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd = &isp->asd[i]; + pipe_wdt_cnt[i][0] += + atomic_read(&asd->video_out_capture.wdt_count); + pipe_wdt_cnt[i][1] += + atomic_read(&asd->video_out_vf.wdt_count); + pipe_wdt_cnt[i][2] += + atomic_read(&asd->video_out_preview.wdt_count); + pipe_wdt_cnt[i][3] += + atomic_read(&asd->video_out_video_capture.wdt_count); + css_recover = + (pipe_wdt_cnt[i][0] <= ATOMISP_ISP_MAX_TIMEOUT_COUNT && + pipe_wdt_cnt[i][1] <= ATOMISP_ISP_MAX_TIMEOUT_COUNT && + pipe_wdt_cnt[i][2] <= ATOMISP_ISP_MAX_TIMEOUT_COUNT && + pipe_wdt_cnt[i][3] <= ATOMISP_ISP_MAX_TIMEOUT_COUNT) + ? true : false; + dev_err(isp->dev, "pipe on asd%d timeout cnt: (%d, %d, %d, %d) of %d, recover = %d\n", + asd->index, pipe_wdt_cnt[i][0], pipe_wdt_cnt[i][1], + pipe_wdt_cnt[i][2], pipe_wdt_cnt[i][3], + ATOMISP_ISP_MAX_TIMEOUT_COUNT, css_recover); + } +#endif + +#ifndef ISP2401 + if (atomic_inc_return(&isp->wdt_count) < + ATOMISP_ISP_MAX_TIMEOUT_COUNT) { +#else + if (css_recover) { +#endif + unsigned int old_dbglevel = dbg_level; + atomisp_css_debug_dump_sp_sw_debug_info(); + atomisp_css_debug_dump_debug_info(__func__); + dbg_level = old_dbglevel; + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd = &isp->asd[i]; + + if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED) + continue; + dev_err(isp->dev, "%s, vdev %s buffers in css: %d\n", + __func__, + asd->video_out_capture.vdev.name, + asd->video_out_capture. + buffers_in_css); + dev_err(isp->dev, + "%s, vdev %s buffers in css: %d\n", + __func__, + asd->video_out_vf.vdev.name, + asd->video_out_vf. + buffers_in_css); + dev_err(isp->dev, + "%s, vdev %s buffers in css: %d\n", + __func__, + asd->video_out_preview.vdev.name, + asd->video_out_preview. + buffers_in_css); + dev_err(isp->dev, + "%s, vdev %s buffers in css: %d\n", + __func__, + asd->video_out_video_capture.vdev.name, + asd->video_out_video_capture. + buffers_in_css); + dev_err(isp->dev, + "%s, s3a buffers in css preview pipe:%d\n", + __func__, + asd->s3a_bufs_in_css[CSS_PIPE_ID_PREVIEW]); + dev_err(isp->dev, + "%s, s3a buffers in css capture pipe:%d\n", + __func__, + asd->s3a_bufs_in_css[CSS_PIPE_ID_CAPTURE]); + dev_err(isp->dev, + "%s, s3a buffers in css video pipe:%d\n", + __func__, + asd->s3a_bufs_in_css[CSS_PIPE_ID_VIDEO]); + dev_err(isp->dev, + "%s, dis buffers in css: %d\n", + __func__, asd->dis_bufs_in_css); + dev_err(isp->dev, + "%s, metadata buffers in css preview pipe:%d\n", + __func__, + asd->metadata_bufs_in_css + [ATOMISP_INPUT_STREAM_GENERAL] + [CSS_PIPE_ID_PREVIEW]); + dev_err(isp->dev, + "%s, metadata buffers in css capture pipe:%d\n", + __func__, + asd->metadata_bufs_in_css + [ATOMISP_INPUT_STREAM_GENERAL] + [CSS_PIPE_ID_CAPTURE]); + dev_err(isp->dev, + "%s, metadata buffers in css video pipe:%d\n", + __func__, + asd->metadata_bufs_in_css + [ATOMISP_INPUT_STREAM_GENERAL] + [CSS_PIPE_ID_VIDEO]); + if (asd->enable_raw_buffer_lock->val) { + unsigned int j; + + dev_err(isp->dev, "%s, raw_buffer_locked_count %d\n", + __func__, asd->raw_buffer_locked_count); + for (j = 0; j <= ATOMISP_MAX_EXP_ID/32; j++) + dev_err(isp->dev, "%s, raw_buffer_bitmap[%d]: 0x%x\n", + __func__, j, + asd->raw_buffer_bitmap[j]); + } + } + + /*sh_css_dump_sp_state();*/ + /*sh_css_dump_isp_state();*/ + } else { + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd = &isp->asd[i]; + if (asd->streaming == + ATOMISP_DEVICE_STREAMING_ENABLED) { + atomisp_clear_css_buffer_counters(asd); + atomisp_flush_bufs_and_wakeup(asd); + complete(&asd->init_done); + } +#ifdef ISP2401 + atomisp_wdt_stop(asd, false); +#endif + } + +#ifndef ISP2401 + atomic_set(&isp->wdt_count, 0); +#endif + isp->isp_fatal_error = true; + atomic_set(&isp->wdt_work_queued, 0); + + rt_mutex_unlock(&isp->mutex); + return; + } + + __atomisp_css_recover(isp, true); +#ifdef ISP2401 + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd = &isp->asd[i]; + if (asd->streaming == + ATOMISP_DEVICE_STREAMING_ENABLED) { + atomisp_wdt_refresh(asd, + isp->sw_contex.file_input ? + ATOMISP_ISP_FILE_TIMEOUT_DURATION : + ATOMISP_ISP_TIMEOUT_DURATION); + } + } +#endif + atomisp_set_stop_timeout(ATOMISP_CSS_STOP_TIMEOUT_US); + dev_err(isp->dev, "timeout recovery handling done\n"); + atomic_set(&isp->wdt_work_queued, 0); + + rt_mutex_unlock(&isp->mutex); +} + +void atomisp_css_flush(struct atomisp_device *isp) +{ + int i; + + if (!atomisp_streaming_count(isp)) + return; + + /* Disable wdt */ + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd = &isp->asd[i]; + atomisp_wdt_stop(asd, true); + } + + /* Start recover */ + __atomisp_css_recover(isp, false); + /* Restore wdt */ + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd = &isp->asd[i]; + + if (asd->streaming != + ATOMISP_DEVICE_STREAMING_ENABLED) + continue; + + atomisp_wdt_refresh(asd, + isp->sw_contex.file_input ? + ATOMISP_ISP_FILE_TIMEOUT_DURATION : + ATOMISP_ISP_TIMEOUT_DURATION); + } + dev_dbg(isp->dev, "atomisp css flush done\n"); +} + +#ifndef ISP2401 +void atomisp_wdt(unsigned long isp_addr) +#else +void atomisp_wdt(unsigned long pipe_addr) +#endif +{ +#ifndef ISP2401 + struct atomisp_device *isp = (struct atomisp_device *)isp_addr; +#else + struct atomisp_video_pipe *pipe = + (struct atomisp_video_pipe *)pipe_addr; + struct atomisp_sub_device *asd = pipe->asd; + struct atomisp_device *isp = asd->isp; +#endif + +#ifdef ISP2401 + atomic_inc(&pipe->wdt_count); + dev_warn(isp->dev, + "[WARNING]asd %d pipe %s ISP timeout %d!\n", + asd->index, pipe->vdev.name, + atomic_read(&pipe->wdt_count)); +#endif + if (atomic_read(&isp->wdt_work_queued)) { + dev_dbg(isp->dev, "ISP watchdog was put into workqueue\n"); + return; + } + atomic_set(&isp->wdt_work_queued, 1); + queue_work(isp->wdt_work_queue, &isp->wdt_work); +} + +#ifndef ISP2401 +void atomisp_wdt_refresh(struct atomisp_sub_device *asd, unsigned int delay) +#else +void atomisp_wdt_refresh_pipe(struct atomisp_video_pipe *pipe, + unsigned int delay) +#endif +{ + unsigned long next; + + if (delay != ATOMISP_WDT_KEEP_CURRENT_DELAY) +#ifndef ISP2401 + asd->wdt_duration = delay; +#else + pipe->wdt_duration = delay; +#endif + +#ifndef ISP2401 + next = jiffies + asd->wdt_duration; +#else + next = jiffies + pipe->wdt_duration; +#endif + + /* Override next if it has been pushed beyon the "next" time */ +#ifndef ISP2401 + if (atomisp_is_wdt_running(asd) && time_after(asd->wdt_expires, next)) + next = asd->wdt_expires; +#else + if (atomisp_is_wdt_running(pipe) && time_after(pipe->wdt_expires, next)) + next = pipe->wdt_expires; +#endif + +#ifndef ISP2401 + asd->wdt_expires = next; +#else + pipe->wdt_expires = next; +#endif + +#ifndef ISP2401 + if (atomisp_is_wdt_running(asd)) + dev_dbg(asd->isp->dev, "WDT will hit after %d ms\n", + ((int)(next - jiffies) * 1000 / HZ)); +#else + if (atomisp_is_wdt_running(pipe)) + dev_dbg(pipe->asd->isp->dev, "WDT will hit after %d ms (%s)\n", + ((int)(next - jiffies) * 1000 / HZ), pipe->vdev.name); +#endif + else +#ifndef ISP2401 + dev_dbg(asd->isp->dev, "WDT starts with %d ms period\n", + ((int)(next - jiffies) * 1000 / HZ)); +#else + dev_dbg(pipe->asd->isp->dev, "WDT starts with %d ms period (%s)\n", + ((int)(next - jiffies) * 1000 / HZ), pipe->vdev.name); +#endif + +#ifndef ISP2401 + mod_timer(&asd->wdt, next); + atomic_set(&asd->isp->wdt_count, 0); +#else + mod_timer(&pipe->wdt, next); +#endif +} + +#ifndef ISP2401 +void atomisp_wdt_stop(struct atomisp_sub_device *asd, bool sync) +#else +void atomisp_wdt_refresh(struct atomisp_sub_device *asd, unsigned int delay) +{ + dev_dbg(asd->isp->dev, "WDT refresh all:\n"); + if (atomisp_is_wdt_running(&asd->video_out_capture)) + atomisp_wdt_refresh_pipe(&asd->video_out_capture, delay); + if (atomisp_is_wdt_running(&asd->video_out_preview)) + atomisp_wdt_refresh_pipe(&asd->video_out_preview, delay); + if (atomisp_is_wdt_running(&asd->video_out_vf)) + atomisp_wdt_refresh_pipe(&asd->video_out_vf, delay); + if (atomisp_is_wdt_running(&asd->video_out_video_capture)) + atomisp_wdt_refresh_pipe(&asd->video_out_video_capture, delay); +} + + +void atomisp_wdt_stop_pipe(struct atomisp_video_pipe *pipe, bool sync) +#endif +{ +#ifndef ISP2401 + dev_dbg(asd->isp->dev, "WDT stop\n"); +#else + if (!atomisp_is_wdt_running(pipe)) + return; + + dev_dbg(pipe->asd->isp->dev, + "WDT stop asd %d (%s)\n", pipe->asd->index, pipe->vdev.name); + +#endif + if (sync) { +#ifndef ISP2401 + del_timer_sync(&asd->wdt); + cancel_work_sync(&asd->isp->wdt_work); +#else + del_timer_sync(&pipe->wdt); + cancel_work_sync(&pipe->asd->isp->wdt_work); +#endif + } else { +#ifndef ISP2401 + del_timer(&asd->wdt); +#else + del_timer(&pipe->wdt); +#endif + } +} + +#ifndef ISP2401 +void atomisp_wdt_start(struct atomisp_sub_device *asd) +#else +void atomisp_wdt_stop(struct atomisp_sub_device *asd, bool sync) +{ + dev_dbg(asd->isp->dev, "WDT stop all:\n"); + atomisp_wdt_stop_pipe(&asd->video_out_capture, sync); + atomisp_wdt_stop_pipe(&asd->video_out_preview, sync); + atomisp_wdt_stop_pipe(&asd->video_out_vf, sync); + atomisp_wdt_stop_pipe(&asd->video_out_video_capture, sync); +} + +void atomisp_wdt_start(struct atomisp_video_pipe *pipe) +#endif +{ +#ifndef ISP2401 + atomisp_wdt_refresh(asd, ATOMISP_ISP_TIMEOUT_DURATION); +#else + atomisp_wdt_refresh_pipe(pipe, ATOMISP_ISP_TIMEOUT_DURATION); +#endif +} + +void atomisp_setup_flash(struct atomisp_sub_device *asd) +{ + struct atomisp_device *isp = asd->isp; + struct v4l2_control ctrl; + + if (isp->flash == NULL) + return; + + if (asd->params.flash_state != ATOMISP_FLASH_REQUESTED && + asd->params.flash_state != ATOMISP_FLASH_DONE) + return; + + if (asd->params.num_flash_frames) { + /* make sure the timeout is set before setting flash mode */ + ctrl.id = V4L2_CID_FLASH_TIMEOUT; + ctrl.value = FLASH_TIMEOUT; + + if (v4l2_s_ctrl(NULL, isp->flash->ctrl_handler, &ctrl)) { + dev_err(isp->dev, "flash timeout configure failed\n"); + return; + } + + atomisp_css_request_flash(asd); + asd->params.flash_state = ATOMISP_FLASH_ONGOING; + } else { + asd->params.flash_state = ATOMISP_FLASH_IDLE; + } +} + +irqreturn_t atomisp_isr_thread(int irq, void *isp_ptr) +{ + struct atomisp_device *isp = isp_ptr; + unsigned long flags; + bool frame_done_found[MAX_STREAM_NUM] = {0}; + bool css_pipe_done[MAX_STREAM_NUM] = {0}; + unsigned int i; + struct atomisp_sub_device *asd = &isp->asd[0]; + + dev_dbg(isp->dev, ">%s\n", __func__); + + spin_lock_irqsave(&isp->lock, flags); + + if (!atomisp_streaming_count(isp) && !atomisp_is_acc_enabled(isp)) { + spin_unlock_irqrestore(&isp->lock, flags); + return IRQ_HANDLED; + } + + spin_unlock_irqrestore(&isp->lock, flags); + + /* + * The standard CSS2.0 API tells the following calling sequence of + * dequeue ready buffers: + * while (ia_css_dequeue_event(...)) { + * switch (event.type) { + * ... + * ia_css_pipe_dequeue_buffer() + * } + * } + * That is, dequeue event and buffer are one after another. + * + * But the following implementation is to first deuque all the event + * to a FIFO, then process the event in the FIFO. + * This will not have issue in single stream mode, but it do have some + * issue in multiple stream case. The issue is that + * ia_css_pipe_dequeue_buffer() will not return the corrent buffer in + * a specific pipe. + * + * This is due to ia_css_pipe_dequeue_buffer() does not take the + * ia_css_pipe parameter. + * + * So: + * For CSS2.0: we change the way to not dequeue all the event at one + * time, instead, dequue one and process one, then another + */ + rt_mutex_lock(&isp->mutex); + if (atomisp_css_isr_thread(isp, frame_done_found, css_pipe_done)) + goto out; + + for (i = 0; i < isp->num_of_streams; i++) { + asd = &isp->asd[i]; + if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED) + continue; + atomisp_setup_flash(asd); + + } +out: + rt_mutex_unlock(&isp->mutex); + for (i = 0; i < isp->num_of_streams; i++) { + asd = &isp->asd[i]; + if (asd->streaming == ATOMISP_DEVICE_STREAMING_ENABLED + && css_pipe_done[asd->index] + && isp->sw_contex.file_input) + v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + video, s_stream, 1); + /* FIXME! FIX ACC implementation */ + if (asd->acc.pipeline && css_pipe_done[asd->index]) + atomisp_css_acc_done(asd); + } + dev_dbg(isp->dev, "<%s\n", __func__); + + return IRQ_HANDLED; +} + +/* + * utils for buffer allocation/free + */ + +int atomisp_get_frame_pgnr(struct atomisp_device *isp, + const struct atomisp_css_frame *frame, u32 *p_pgnr) +{ + if (!frame) { + dev_err(isp->dev, "%s: NULL frame pointer ERROR.\n", __func__); + return -EINVAL; + } + + *p_pgnr = DIV_ROUND_UP(frame->data_bytes, PAGE_SIZE); + return 0; +} + +/* + * Get internal fmt according to V4L2 fmt + */ +static enum atomisp_css_frame_format +v4l2_fmt_to_sh_fmt(u32 fmt) +{ + switch (fmt) { + case V4L2_PIX_FMT_YUV420: + return CSS_FRAME_FORMAT_YUV420; + case V4L2_PIX_FMT_YVU420: + return CSS_FRAME_FORMAT_YV12; + case V4L2_PIX_FMT_YUV422P: + return CSS_FRAME_FORMAT_YUV422; + case V4L2_PIX_FMT_YUV444: + return CSS_FRAME_FORMAT_YUV444; + case V4L2_PIX_FMT_NV12: + return CSS_FRAME_FORMAT_NV12; + case V4L2_PIX_FMT_NV21: + return CSS_FRAME_FORMAT_NV21; + case V4L2_PIX_FMT_NV16: + return CSS_FRAME_FORMAT_NV16; + case V4L2_PIX_FMT_NV61: + return CSS_FRAME_FORMAT_NV61; + case V4L2_PIX_FMT_UYVY: + return CSS_FRAME_FORMAT_UYVY; + case V4L2_PIX_FMT_YUYV: + return CSS_FRAME_FORMAT_YUYV; + case V4L2_PIX_FMT_RGB24: + return CSS_FRAME_FORMAT_PLANAR_RGB888; + case V4L2_PIX_FMT_RGB32: + return CSS_FRAME_FORMAT_RGBA888; + case V4L2_PIX_FMT_RGB565: + return CSS_FRAME_FORMAT_RGB565; + case V4L2_PIX_FMT_JPEG: + case V4L2_PIX_FMT_CUSTOM_M10MO_RAW: + return CSS_FRAME_FORMAT_BINARY_8; + case V4L2_PIX_FMT_SBGGR16: + case V4L2_PIX_FMT_SBGGR10: + case V4L2_PIX_FMT_SGBRG10: + case V4L2_PIX_FMT_SGRBG10: + case V4L2_PIX_FMT_SRGGB10: + case V4L2_PIX_FMT_SBGGR12: + case V4L2_PIX_FMT_SGBRG12: + case V4L2_PIX_FMT_SGRBG12: + case V4L2_PIX_FMT_SRGGB12: + case V4L2_PIX_FMT_SBGGR8: + case V4L2_PIX_FMT_SGBRG8: + case V4L2_PIX_FMT_SGRBG8: + case V4L2_PIX_FMT_SRGGB8: + return CSS_FRAME_FORMAT_RAW; + default: + return -EINVAL; + } +} +/* + * raw format match between SH format and V4L2 format + */ +static int raw_output_format_match_input(u32 input, u32 output) +{ + if ((input == CSS_FORMAT_RAW_12) && + ((output == V4L2_PIX_FMT_SRGGB12) || + (output == V4L2_PIX_FMT_SGRBG12) || + (output == V4L2_PIX_FMT_SBGGR12) || + (output == V4L2_PIX_FMT_SGBRG12))) + return 0; + + if ((input == CSS_FORMAT_RAW_10) && + ((output == V4L2_PIX_FMT_SRGGB10) || + (output == V4L2_PIX_FMT_SGRBG10) || + (output == V4L2_PIX_FMT_SBGGR10) || + (output == V4L2_PIX_FMT_SGBRG10))) + return 0; + + if ((input == CSS_FORMAT_RAW_8) && + ((output == V4L2_PIX_FMT_SRGGB8) || + (output == V4L2_PIX_FMT_SGRBG8) || + (output == V4L2_PIX_FMT_SBGGR8) || + (output == V4L2_PIX_FMT_SGBRG8))) + return 0; + + if ((input == CSS_FORMAT_RAW_16) && (output == V4L2_PIX_FMT_SBGGR16)) + return 0; + + return -EINVAL; +} + +static u32 get_pixel_depth(u32 pixelformat) +{ + switch (pixelformat) { + case V4L2_PIX_FMT_YUV420: + case V4L2_PIX_FMT_NV12: + case V4L2_PIX_FMT_NV21: + case V4L2_PIX_FMT_YVU420: + return 12; + case V4L2_PIX_FMT_YUV422P: + case V4L2_PIX_FMT_YUYV: + case V4L2_PIX_FMT_UYVY: + case V4L2_PIX_FMT_NV16: + case V4L2_PIX_FMT_NV61: + case V4L2_PIX_FMT_RGB565: + case V4L2_PIX_FMT_SBGGR16: + case V4L2_PIX_FMT_SBGGR12: + case V4L2_PIX_FMT_SGBRG12: + case V4L2_PIX_FMT_SGRBG12: + case V4L2_PIX_FMT_SRGGB12: + case V4L2_PIX_FMT_SBGGR10: + case V4L2_PIX_FMT_SGBRG10: + case V4L2_PIX_FMT_SGRBG10: + case V4L2_PIX_FMT_SRGGB10: + return 16; + case V4L2_PIX_FMT_RGB24: + case V4L2_PIX_FMT_YUV444: + return 24; + case V4L2_PIX_FMT_RGB32: + return 32; + case V4L2_PIX_FMT_JPEG: + case V4L2_PIX_FMT_CUSTOM_M10MO_RAW: + case V4L2_PIX_FMT_SBGGR8: + case V4L2_PIX_FMT_SGBRG8: + case V4L2_PIX_FMT_SGRBG8: + case V4L2_PIX_FMT_SRGGB8: + return 8; + default: + return 8 * 2; /* raw type now */ + } +} + +bool atomisp_is_mbuscode_raw(uint32_t code) +{ + return code >= 0x3000 && code < 0x4000; +} + +/* + * ISP features control function + */ + +/* + * Set ISP capture mode based on current settings + */ +static void atomisp_update_capture_mode(struct atomisp_sub_device *asd) +{ + if (asd->params.gdc_cac_en) + atomisp_css_capture_set_mode(asd, CSS_CAPTURE_MODE_ADVANCED); + else if (asd->params.low_light) + atomisp_css_capture_set_mode(asd, CSS_CAPTURE_MODE_LOW_LIGHT); + else if (asd->video_out_capture.sh_fmt == CSS_FRAME_FORMAT_RAW) + atomisp_css_capture_set_mode(asd, CSS_CAPTURE_MODE_RAW); + else + atomisp_css_capture_set_mode(asd, CSS_CAPTURE_MODE_PRIMARY); +} + +#ifdef ISP2401 +int atomisp_set_sensor_runmode(struct atomisp_sub_device *asd, + struct atomisp_s_runmode *runmode) +{ + struct atomisp_device *isp = asd->isp; + struct v4l2_ctrl *c; + struct v4l2_streamparm p = {0}; + int ret; + int modes[] = { CI_MODE_NONE, + CI_MODE_VIDEO, + CI_MODE_STILL_CAPTURE, + CI_MODE_CONTINUOUS, + CI_MODE_PREVIEW }; + + if (!(runmode && (runmode->mode & RUNMODE_MASK))) + return -EINVAL; + + mutex_lock(asd->ctrl_handler.lock); + c = v4l2_ctrl_find(isp->inputs[asd->input_curr].camera->ctrl_handler, + V4L2_CID_RUN_MODE); + + if (c) { + ret = v4l2_ctrl_s_ctrl(c, runmode->mode); + } else { + p.parm.capture.capturemode = modes[runmode->mode]; + ret = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + video, s_parm, &p); + } + + mutex_unlock(asd->ctrl_handler.lock); + return ret; +} + +#endif +/* + * Function to enable/disable lens geometry distortion correction (GDC) and + * chromatic aberration correction (CAC) + */ +int atomisp_gdc_cac(struct atomisp_sub_device *asd, int flag, + __s32 *value) +{ + if (flag == 0) { + *value = asd->params.gdc_cac_en; + return 0; + } + + asd->params.gdc_cac_en = !!*value; + if (asd->params.gdc_cac_en) { + atomisp_css_set_morph_table(asd, + asd->params.css_param.morph_table); + } else { + atomisp_css_set_morph_table(asd, NULL); + } + asd->params.css_update_params_needed = true; + atomisp_update_capture_mode(asd); + return 0; +} + +/* + * Function to enable/disable low light mode including ANR + */ +int atomisp_low_light(struct atomisp_sub_device *asd, int flag, + __s32 *value) +{ + if (flag == 0) { + *value = asd->params.low_light; + return 0; + } + + asd->params.low_light = (*value != 0); + atomisp_update_capture_mode(asd); + return 0; +} + +/* + * Function to enable/disable extra noise reduction (XNR) in low light + * condition + */ +int atomisp_xnr(struct atomisp_sub_device *asd, int flag, + int *xnr_enable) +{ + if (flag == 0) { + *xnr_enable = asd->params.xnr_en; + return 0; + } + + atomisp_css_capture_enable_xnr(asd, !!*xnr_enable); + + return 0; +} + +/* + * Function to configure bayer noise reduction + */ +int atomisp_nr(struct atomisp_sub_device *asd, int flag, + struct atomisp_nr_config *arg) +{ + if (flag == 0) { + /* Get nr config from current setup */ + if (atomisp_css_get_nr_config(asd, arg)) + return -EINVAL; + } else { + /* Set nr config to isp parameters */ + memcpy(&asd->params.css_param.nr_config, arg, + sizeof(struct atomisp_css_nr_config)); + atomisp_css_set_nr_config(asd, &asd->params.css_param.nr_config); + asd->params.css_update_params_needed = true; + } + return 0; +} + +/* + * Function to configure temporal noise reduction (TNR) + */ +int atomisp_tnr(struct atomisp_sub_device *asd, int flag, + struct atomisp_tnr_config *config) +{ + /* Get tnr config from current setup */ + if (flag == 0) { + /* Get tnr config from current setup */ + if (atomisp_css_get_tnr_config(asd, config)) + return -EINVAL; + } else { + /* Set tnr config to isp parameters */ + memcpy(&asd->params.css_param.tnr_config, config, + sizeof(struct atomisp_css_tnr_config)); + atomisp_css_set_tnr_config(asd, &asd->params.css_param.tnr_config); + asd->params.css_update_params_needed = true; + } + + return 0; +} + +/* + * Function to configure black level compensation + */ +int atomisp_black_level(struct atomisp_sub_device *asd, int flag, + struct atomisp_ob_config *config) +{ + if (flag == 0) { + /* Get ob config from current setup */ + if (atomisp_css_get_ob_config(asd, config)) + return -EINVAL; + } else { + /* Set ob config to isp parameters */ + memcpy(&asd->params.css_param.ob_config, config, + sizeof(struct atomisp_css_ob_config)); + atomisp_css_set_ob_config(asd, &asd->params.css_param.ob_config); + asd->params.css_update_params_needed = true; + } + + return 0; +} + +/* + * Function to configure edge enhancement + */ +int atomisp_ee(struct atomisp_sub_device *asd, int flag, + struct atomisp_ee_config *config) +{ + if (flag == 0) { + /* Get ee config from current setup */ + if (atomisp_css_get_ee_config(asd, config)) + return -EINVAL; + } else { + /* Set ee config to isp parameters */ + memcpy(&asd->params.css_param.ee_config, config, + sizeof(asd->params.css_param.ee_config)); + atomisp_css_set_ee_config(asd, &asd->params.css_param.ee_config); + asd->params.css_update_params_needed = true; + } + + return 0; +} + +/* + * Function to update Gamma table for gamma, brightness and contrast config + */ +int atomisp_gamma(struct atomisp_sub_device *asd, int flag, + struct atomisp_gamma_table *config) +{ + if (flag == 0) { + /* Get gamma table from current setup */ + if (atomisp_css_get_gamma_table(asd, config)) + return -EINVAL; + } else { + /* Set gamma table to isp parameters */ + memcpy(&asd->params.css_param.gamma_table, config, + sizeof(asd->params.css_param.gamma_table)); + atomisp_css_set_gamma_table(asd, &asd->params.css_param.gamma_table); + } + + return 0; +} + +/* + * Function to update Ctc table for Chroma Enhancement + */ +int atomisp_ctc(struct atomisp_sub_device *asd, int flag, + struct atomisp_ctc_table *config) +{ + if (flag == 0) { + /* Get ctc table from current setup */ + if (atomisp_css_get_ctc_table(asd, config)) + return -EINVAL; + } else { + /* Set ctc table to isp parameters */ + memcpy(&asd->params.css_param.ctc_table, config, + sizeof(asd->params.css_param.ctc_table)); + atomisp_css_set_ctc_table(asd, &asd->params.css_param.ctc_table); + } + + return 0; +} + +/* + * Function to update gamma correction parameters + */ +int atomisp_gamma_correction(struct atomisp_sub_device *asd, int flag, + struct atomisp_gc_config *config) +{ + if (flag == 0) { + /* Get gamma correction params from current setup */ + if (atomisp_css_get_gc_config(asd, config)) + return -EINVAL; + } else { + /* Set gamma correction params to isp parameters */ + memcpy(&asd->params.css_param.gc_config, config, + sizeof(asd->params.css_param.gc_config)); + atomisp_css_set_gc_config(asd, &asd->params.css_param.gc_config); + asd->params.css_update_params_needed = true; + } + + return 0; +} + +/* + * Function to update narrow gamma flag + */ +int atomisp_formats(struct atomisp_sub_device *asd, int flag, + struct atomisp_formats_config *config) +{ + if (flag == 0) { + /* Get narrow gamma flag from current setup */ + if (atomisp_css_get_formats_config(asd, config)) + return -EINVAL; + } else { + /* Set narrow gamma flag to isp parameters */ + memcpy(&asd->params.css_param.formats_config, config, + sizeof(asd->params.css_param.formats_config)); + atomisp_css_set_formats_config(asd, &asd->params.css_param.formats_config); + } + + return 0; +} + +void atomisp_free_internal_buffers(struct atomisp_sub_device *asd) +{ + atomisp_free_css_parameters(&asd->params.css_param); + + if (asd->raw_output_frame) { + atomisp_css_frame_free(asd->raw_output_frame); + asd->raw_output_frame = NULL; + } +} + +static void atomisp_update_grid_info(struct atomisp_sub_device *asd, + enum atomisp_css_pipe_id pipe_id, int source_pad) +{ + struct atomisp_device *isp = asd->isp; + int err; + uint16_t stream_id = atomisp_source_pad_to_stream_id(asd, source_pad); + + if (atomisp_css_get_grid_info(asd, pipe_id, source_pad)) + return; + + /* We must free all buffers because they no longer match + the grid size. */ + atomisp_css_free_stat_buffers(asd); + + err = atomisp_alloc_css_stat_bufs(asd, stream_id); + if (err) { + dev_err(isp->dev, "stat_buf allocate error\n"); + goto err; + } + + if (atomisp_alloc_3a_output_buf(asd)) { + /* Failure for 3A buffers does not influence DIS buffers */ + if (asd->params.s3a_output_bytes != 0) { + /* For SOC sensor happens s3a_output_bytes == 0, + * using if condition to exclude false error log */ + dev_err(isp->dev, "Failed to allocate memory for 3A statistics\n"); + } + goto err; + } + + if (atomisp_alloc_dis_coef_buf(asd)) { + dev_err(isp->dev, + "Failed to allocate memory for DIS statistics\n"); + goto err; + } + + if (atomisp_alloc_metadata_output_buf(asd)) { + dev_err(isp->dev, "Failed to allocate memory for metadata\n"); + goto err; + } + + return; + +err: + atomisp_css_free_stat_buffers(asd); + return; +} + +static void atomisp_curr_user_grid_info(struct atomisp_sub_device *asd, + struct atomisp_grid_info *info) +{ + memcpy(info, &asd->params.curr_grid_info.s3a_grid, + sizeof(struct atomisp_css_3a_grid_info)); +} + +int atomisp_compare_grid(struct atomisp_sub_device *asd, + struct atomisp_grid_info *atomgrid) +{ + struct atomisp_grid_info tmp = {0}; + + atomisp_curr_user_grid_info(asd, &tmp); + return memcmp(atomgrid, &tmp, sizeof(tmp)); +} + +/* + * Function to update Gdc table for gdc + */ +int atomisp_gdc_cac_table(struct atomisp_sub_device *asd, int flag, + struct atomisp_morph_table *config) +{ + int ret; + int i; + struct atomisp_device *isp = asd->isp; + + if (flag == 0) { + /* Get gdc table from current setup */ + struct atomisp_css_morph_table tab = {0}; + atomisp_css_get_morph_table(asd, &tab); + + config->width = tab.width; + config->height = tab.height; + + for (i = 0; i < CSS_MORPH_TABLE_NUM_PLANES; i++) { + ret = copy_to_user(config->coordinates_x[i], + tab.coordinates_x[i], tab.height * + tab.width * sizeof(*tab.coordinates_x[i])); + if (ret) { + dev_err(isp->dev, + "Failed to copy to User for x\n"); + return -EFAULT; + } + ret = copy_to_user(config->coordinates_y[i], + tab.coordinates_y[i], tab.height * + tab.width * sizeof(*tab.coordinates_y[i])); + if (ret) { + dev_err(isp->dev, + "Failed to copy to User for y\n"); + return -EFAULT; + } + } + } else { + struct atomisp_css_morph_table *tab = + asd->params.css_param.morph_table; + + /* free first if we have one */ + if (tab) { + atomisp_css_morph_table_free(tab); + asd->params.css_param.morph_table = NULL; + } + + /* allocate new one */ + tab = atomisp_css_morph_table_allocate(config->width, + config->height); + + if (!tab) { + dev_err(isp->dev, "out of memory\n"); + return -EINVAL; + } + + for (i = 0; i < CSS_MORPH_TABLE_NUM_PLANES; i++) { + ret = copy_from_user(tab->coordinates_x[i], + config->coordinates_x[i], + config->height * config->width * + sizeof(*config->coordinates_x[i])); + if (ret) { + dev_err(isp->dev, + "Failed to copy from User for x, ret %d\n", + ret); + atomisp_css_morph_table_free(tab); + return -EFAULT; + } + ret = copy_from_user(tab->coordinates_y[i], + config->coordinates_y[i], + config->height * config->width * + sizeof(*config->coordinates_y[i])); + if (ret) { + dev_err(isp->dev, + "Failed to copy from User for y, ret is %d\n", + ret); + atomisp_css_morph_table_free(tab); + return -EFAULT; + } + } + asd->params.css_param.morph_table = tab; + if (asd->params.gdc_cac_en) + atomisp_css_set_morph_table(asd, tab); + } + + return 0; +} + +int atomisp_macc_table(struct atomisp_sub_device *asd, int flag, + struct atomisp_macc_config *config) +{ + struct atomisp_css_macc_table *macc_table; + + switch (config->color_effect) { + case V4L2_COLORFX_NONE: + macc_table = &asd->params.css_param.macc_table; + break; + case V4L2_COLORFX_SKY_BLUE: + macc_table = &blue_macc_table; + break; + case V4L2_COLORFX_GRASS_GREEN: + macc_table = &green_macc_table; + break; + case V4L2_COLORFX_SKIN_WHITEN_LOW: + macc_table = &skin_low_macc_table; + break; + case V4L2_COLORFX_SKIN_WHITEN: + macc_table = &skin_medium_macc_table; + break; + case V4L2_COLORFX_SKIN_WHITEN_HIGH: + macc_table = &skin_high_macc_table; + break; + default: + return -EINVAL; + } + + if (flag == 0) { + /* Get macc table from current setup */ + memcpy(&config->table, macc_table, + sizeof(struct atomisp_css_macc_table)); + } else { + memcpy(macc_table, &config->table, + sizeof(struct atomisp_css_macc_table)); + if (config->color_effect == asd->params.color_effect) + atomisp_css_set_macc_table(asd, macc_table); + } + + return 0; +} + +int atomisp_set_dis_vector(struct atomisp_sub_device *asd, + struct atomisp_dis_vector *vector) +{ + atomisp_css_video_set_dis_vector(asd, vector); + + asd->params.dis_proj_data_valid = false; + asd->params.css_update_params_needed = true; + return 0; +} + +/* + * Function to set/get image stablization statistics + */ +int atomisp_get_dis_stat(struct atomisp_sub_device *asd, + struct atomisp_dis_statistics *stats) +{ + return atomisp_css_get_dis_stat(asd, stats); +} + +/* + * Function set camrea_prefiles.xml current sensor pixel array size + */ +int atomisp_set_array_res(struct atomisp_sub_device *asd, + struct atomisp_resolution *config) +{ + dev_dbg(asd->isp->dev, ">%s start\n", __func__); + if (config == NULL || config->width < 0 + || config->height < 0) { + dev_err(asd->isp->dev, "Set sensor array size is not valid\n"); + return -EINVAL; + } + + asd->sensor_array_res.width = config->width; + asd->sensor_array_res.height = config->height; + return 0; +} + +/* + * Function to get DVS2 BQ resolution settings + */ +int atomisp_get_dvs2_bq_resolutions(struct atomisp_sub_device *asd, + struct atomisp_dvs2_bq_resolutions *bq_res) +{ + struct ia_css_pipe_config *pipe_cfg = NULL; + struct ia_css_stream_config *stream_cfg = NULL; + struct ia_css_stream_input_config *input_config = NULL; + + struct ia_css_stream *stream = + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream; + if (!stream) { + dev_warn(asd->isp->dev, "stream is not created"); + return -EAGAIN; + } + + pipe_cfg = &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .pipe_configs[CSS_PIPE_ID_VIDEO]; + stream_cfg = &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .stream_config; + input_config = &stream_cfg->input_config; + + if (!bq_res) + return -EINVAL; + + /* the GDC output resolution */ + bq_res->output_bq.width_bq = pipe_cfg->output_info[0].res.width / 2; + bq_res->output_bq.height_bq = pipe_cfg->output_info[0].res.height / 2; + + bq_res->envelope_bq.width_bq = 0; + bq_res->envelope_bq.height_bq = 0; + /* the GDC input resolution */ + if (!asd->continuous_mode->val) { + bq_res->source_bq.width_bq = bq_res->output_bq.width_bq + + pipe_cfg->dvs_envelope.width / 2; + bq_res->source_bq.height_bq = bq_res->output_bq.height_bq + + pipe_cfg->dvs_envelope.height / 2; + /* + * Bad pixels caused by spatial filter processing + * ISP filter resolution should be given by CSS/FW, but for now + * there is not such API to query, and it is fixed value, so + * hardcoded here. + */ + bq_res->ispfilter_bq.width_bq = 12 / 2; + bq_res->ispfilter_bq.height_bq = 12 / 2; + /* spatial filter shift, always 4 pixels */ + bq_res->gdc_shift_bq.width_bq = 4 / 2; + bq_res->gdc_shift_bq.height_bq = 4 / 2; + + if (asd->params.video_dis_en) { + bq_res->envelope_bq.width_bq = pipe_cfg->dvs_envelope.width + / 2 - bq_res->ispfilter_bq.width_bq; + bq_res->envelope_bq.height_bq = pipe_cfg->dvs_envelope.height + / 2 - bq_res->ispfilter_bq.height_bq; + } + } else { + unsigned int w_padding; + unsigned int gdc_effective_input = 0; + + /* For GDC: + * gdc_effective_input = effective_input + envelope + * + * From the comment and formula in BZ1786, + * we see the source_bq should be: + * effective_input / bayer_ds_ratio + */ + bq_res->source_bq.width_bq = + (input_config->effective_res.width * + pipe_cfg->bayer_ds_out_res.width / + input_config->effective_res.width + 1) / 2; + bq_res->source_bq.height_bq = + (input_config->effective_res.height * + pipe_cfg->bayer_ds_out_res.height / + input_config->effective_res.height + 1) / 2; + + + if (!asd->params.video_dis_en) { + /* + * We adjust the ispfilter_bq to: + * ispfilter_bq = 128/BDS + * we still need firmware team to provide an offical + * formula for SDV. + */ + bq_res->ispfilter_bq.width_bq = 128 * + pipe_cfg->bayer_ds_out_res.width / + input_config->effective_res.width / 2; + bq_res->ispfilter_bq.height_bq = 128 * + pipe_cfg->bayer_ds_out_res.width / + input_config->effective_res.width / 2; + + if (IS_HWREVISION(asd->isp, ATOMISP_HW_REVISION_ISP2401)) { + /* No additional left padding for ISYS2401 */ + bq_res->gdc_shift_bq.width_bq = 4 / 2; + bq_res->gdc_shift_bq.height_bq = 4 / 2; + } else { + /* + * For the w_padding and gdc_shift_bq cacluation + * Please see the BZ 1786 and 4358 for more info. + * Just test that this formula can work now, + * but we still have no offical formula. + * + * w_padding = ceiling(gdc_effective_input + * /128, 1) * 128 - effective_width + * gdc_shift_bq = w_padding/BDS/2 + ispfilter_bq/2 + */ + gdc_effective_input = + input_config->effective_res.width + + pipe_cfg->dvs_envelope.width; + w_padding = roundup(gdc_effective_input, 128) - + input_config->effective_res.width; + w_padding = w_padding * + pipe_cfg->bayer_ds_out_res.width / + input_config->effective_res.width + 1; + w_padding = roundup(w_padding/2, 1); + + bq_res->gdc_shift_bq.width_bq = bq_res->ispfilter_bq.width_bq / 2 + + w_padding; + bq_res->gdc_shift_bq.height_bq = 4 / 2; + } + } else { + unsigned int dvs_w, dvs_h, dvs_w_max, dvs_h_max; + + bq_res->ispfilter_bq.width_bq = 8 / 2; + bq_res->ispfilter_bq.height_bq = 8 / 2; + + if (IS_HWREVISION(asd->isp, ATOMISP_HW_REVISION_ISP2401)) { + /* No additional left padding for ISYS2401 */ + bq_res->gdc_shift_bq.width_bq = 4 / 2; + bq_res->gdc_shift_bq.height_bq = 4 / 2; + } else { + w_padding = + roundup(input_config->effective_res.width, 128) - + input_config->effective_res.width; + if (w_padding < 12) + w_padding = 12; + bq_res->gdc_shift_bq.width_bq = 4 / 2 + + ((w_padding - 12) * + pipe_cfg->bayer_ds_out_res.width / + input_config->effective_res.width + 1) / 2; + bq_res->gdc_shift_bq.height_bq = 4 / 2; + } + + dvs_w = pipe_cfg->bayer_ds_out_res.width - + pipe_cfg->output_info[0].res.width; + dvs_h = pipe_cfg->bayer_ds_out_res.height - + pipe_cfg->output_info[0].res.height; + dvs_w_max = rounddown( + pipe_cfg->output_info[0].res.width / 5, + ATOM_ISP_STEP_WIDTH); + dvs_h_max = rounddown( + pipe_cfg->output_info[0].res.height / 5, + ATOM_ISP_STEP_HEIGHT); + bq_res->envelope_bq.width_bq = + min((dvs_w / 2), (dvs_w_max / 2)) - + bq_res->ispfilter_bq.width_bq; + bq_res->envelope_bq.height_bq = + min((dvs_h / 2), (dvs_h_max / 2)) - + bq_res->ispfilter_bq.height_bq; + } + } + + dev_dbg(asd->isp->dev, "source_bq.width_bq %d, source_bq.height_bq %d,\nispfilter_bq.width_bq %d, ispfilter_bq.height_bq %d,\ngdc_shift_bq.width_bq %d, gdc_shift_bq.height_bq %d,\nenvelope_bq.width_bq %d, envelope_bq.height_bq %d,\noutput_bq.width_bq %d, output_bq.height_bq %d\n", + bq_res->source_bq.width_bq, bq_res->source_bq.height_bq, + bq_res->ispfilter_bq.width_bq, bq_res->ispfilter_bq.height_bq, + bq_res->gdc_shift_bq.width_bq, bq_res->gdc_shift_bq.height_bq, + bq_res->envelope_bq.width_bq, bq_res->envelope_bq.height_bq, + bq_res->output_bq.width_bq, bq_res->output_bq.height_bq); + + return 0; +} + +int atomisp_set_dis_coefs(struct atomisp_sub_device *asd, + struct atomisp_dis_coefficients *coefs) +{ + return atomisp_css_set_dis_coefs(asd, coefs); +} + +/* + * Function to set/get 3A stat from isp + */ +int atomisp_3a_stat(struct atomisp_sub_device *asd, int flag, + struct atomisp_3a_statistics *config) +{ + struct atomisp_device *isp = asd->isp; + struct atomisp_s3a_buf *s3a_buf; + unsigned long ret; + + if (flag != 0) + return -EINVAL; + + /* sanity check to avoid writing into unallocated memory. */ + if (asd->params.s3a_output_bytes == 0) + return -EINVAL; + + if (atomisp_compare_grid(asd, &config->grid_info) != 0) { + /* If the grid info in the argument differs from the current + grid info, we tell the caller to reset the grid size and + try again. */ + return -EAGAIN; + } + + if (list_empty(&asd->s3a_stats_ready)) { + dev_err(isp->dev, "3a statistics is not valid.\n"); + return -EAGAIN; + } + + s3a_buf = list_entry(asd->s3a_stats_ready.next, + struct atomisp_s3a_buf, list); + if (s3a_buf->s3a_map) + ia_css_translate_3a_statistics( + asd->params.s3a_user_stat, s3a_buf->s3a_map); + else + ia_css_get_3a_statistics(asd->params.s3a_user_stat, + s3a_buf->s3a_data); + + config->exp_id = s3a_buf->s3a_data->exp_id; + config->isp_config_id = s3a_buf->s3a_data->isp_config_id; + + ret = copy_to_user(config->data, asd->params.s3a_user_stat->data, + asd->params.s3a_output_bytes); + if (ret) { + dev_err(isp->dev, "copy to user failed: copied %lu bytes\n", + ret); + return -EFAULT; + } + + /* Move to free buffer list */ + list_del_init(&s3a_buf->list); + list_add_tail(&s3a_buf->list, &asd->s3a_stats); + dev_dbg(isp->dev, "%s: finish getting exp_id %d 3a stat, isp_config_id %d\n", __func__, + config->exp_id, config->isp_config_id); + return 0; +} + +int atomisp_get_metadata(struct atomisp_sub_device *asd, int flag, + struct atomisp_metadata *md) +{ + struct atomisp_device *isp = asd->isp; + struct ia_css_stream_config *stream_config; + struct ia_css_stream_info *stream_info; + struct camera_mipi_info *mipi_info; + struct atomisp_metadata_buf *md_buf; + enum atomisp_metadata_type md_type = ATOMISP_MAIN_METADATA; + int ret, i; + + if (flag != 0) + return -EINVAL; + + stream_config = &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]. + stream_config; + stream_info = &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]. + stream_info; + + /* We always return the resolution and stride even if there is + * no valid metadata. This allows the caller to get the information + * needed to allocate user-space buffers. */ + md->width = stream_info->metadata_info.resolution.width; + md->height = stream_info->metadata_info.resolution.height; + md->stride = stream_info->metadata_info.stride; + + /* sanity check to avoid writing into unallocated memory. + * This does not return an error because it is a valid way + * for applications to detect that metadata is not enabled. */ + if (md->width == 0 || md->height == 0 || !md->data) + return 0; + + /* This is done in the atomisp_buf_done() */ + if (list_empty(&asd->metadata_ready[md_type])) { + dev_warn(isp->dev, "Metadata queue is empty now!\n"); + return -EAGAIN; + } + + mipi_info = atomisp_to_sensor_mipi_info( + isp->inputs[asd->input_curr].camera); + if (mipi_info == NULL) + return -EINVAL; + + if (mipi_info->metadata_effective_width != NULL) { + for (i = 0; i < md->height; i++) + md->effective_width[i] = + mipi_info->metadata_effective_width[i]; + } + + md_buf = list_entry(asd->metadata_ready[md_type].next, + struct atomisp_metadata_buf, list); + md->exp_id = md_buf->metadata->exp_id; + if (md_buf->md_vptr) { + ret = copy_to_user(md->data, + md_buf->md_vptr, + stream_info->metadata_info.size); + } else { + hrt_isp_css_mm_load(md_buf->metadata->address, + asd->params.metadata_user[md_type], + stream_info->metadata_info.size); + + ret = copy_to_user(md->data, + asd->params.metadata_user[md_type], + stream_info->metadata_info.size); + } + if (ret) { + dev_err(isp->dev, "copy to user failed: copied %d bytes\n", + ret); + return -EFAULT; + } else { + list_del_init(&md_buf->list); + list_add_tail(&md_buf->list, &asd->metadata[md_type]); + } + + dev_dbg(isp->dev, "%s: HAL de-queued metadata type %d with exp_id %d\n", + __func__, md_type, md->exp_id); + return 0; +} + +int atomisp_get_metadata_by_type(struct atomisp_sub_device *asd, int flag, + struct atomisp_metadata_with_type *md) +{ + struct atomisp_device *isp = asd->isp; + struct ia_css_stream_config *stream_config; + struct ia_css_stream_info *stream_info; + struct camera_mipi_info *mipi_info; + struct atomisp_metadata_buf *md_buf; + enum atomisp_metadata_type md_type; + int ret, i; + + if (flag != 0) + return -EINVAL; + + stream_config = &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]. + stream_config; + stream_info = &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]. + stream_info; + + /* We always return the resolution and stride even if there is + * no valid metadata. This allows the caller to get the information + * needed to allocate user-space buffers. */ + md->width = stream_info->metadata_info.resolution.width; + md->height = stream_info->metadata_info.resolution.height; + md->stride = stream_info->metadata_info.stride; + + /* sanity check to avoid writing into unallocated memory. + * This does not return an error because it is a valid way + * for applications to detect that metadata is not enabled. */ + if (md->width == 0 || md->height == 0 || !md->data) + return 0; + + md_type = md->type; + if (md_type >= ATOMISP_METADATA_TYPE_NUM) + return -EINVAL; + + /* This is done in the atomisp_buf_done() */ + if (list_empty(&asd->metadata_ready[md_type])) { + dev_warn(isp->dev, "Metadata queue is empty now!\n"); + return -EAGAIN; + } + + mipi_info = atomisp_to_sensor_mipi_info( + isp->inputs[asd->input_curr].camera); + if (mipi_info == NULL) + return -EINVAL; + + if (mipi_info->metadata_effective_width != NULL) { + for (i = 0; i < md->height; i++) + md->effective_width[i] = + mipi_info->metadata_effective_width[i]; + } + + md_buf = list_entry(asd->metadata_ready[md_type].next, + struct atomisp_metadata_buf, list); + md->exp_id = md_buf->metadata->exp_id; + if (md_buf->md_vptr) { + ret = copy_to_user(md->data, + md_buf->md_vptr, + stream_info->metadata_info.size); + } else { + hrt_isp_css_mm_load(md_buf->metadata->address, + asd->params.metadata_user[md_type], + stream_info->metadata_info.size); + + ret = copy_to_user(md->data, + asd->params.metadata_user[md_type], + stream_info->metadata_info.size); + } + if (ret) { + dev_err(isp->dev, "copy to user failed: copied %d bytes\n", + ret); + return -EFAULT; + } else { + list_del_init(&md_buf->list); + list_add_tail(&md_buf->list, &asd->metadata[md_type]); + } + dev_dbg(isp->dev, "%s: HAL de-queued metadata type %d with exp_id %d\n", + __func__, md_type, md->exp_id); + return 0; +} + +/* + * Function to calculate real zoom region for every pipe + */ +int atomisp_calculate_real_zoom_region(struct atomisp_sub_device *asd, + struct ia_css_dz_config *dz_config, + enum atomisp_css_pipe_id css_pipe_id) + +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + struct atomisp_resolution eff_res, out_res; +#ifdef ISP2401 + int w_offset, h_offset; +#endif + + memset(&eff_res, 0, sizeof(eff_res)); + memset(&out_res, 0, sizeof(out_res)); + + if (dz_config->dx || dz_config->dy) + return 0; + + if (css_pipe_id != IA_CSS_PIPE_ID_PREVIEW + && css_pipe_id != IA_CSS_PIPE_ID_CAPTURE) { + dev_err(asd->isp->dev, "%s the set pipe no support crop region" + , __func__); + return -EINVAL; + } + + eff_res.width = + stream_env->stream_config.input_config.effective_res.width; + eff_res.height = + stream_env->stream_config.input_config.effective_res.height; + if (eff_res.width == 0 || eff_res.height == 0) { + dev_err(asd->isp->dev, "%s err effective resolution" + , __func__); + return -EINVAL; + } + + if (dz_config->zoom_region.resolution.width + == asd->sensor_array_res.width + || dz_config->zoom_region.resolution.height + == asd->sensor_array_res.height) { + /*no need crop region*/ + dz_config->zoom_region.origin.x = 0; + dz_config->zoom_region.origin.y = 0; + dz_config->zoom_region.resolution.width = eff_res.width; + dz_config->zoom_region.resolution.height = eff_res.height; + return 0; + } + + /* FIXME: + * This is not the correct implementation with Google's definition, due + * to firmware limitation. + * map real crop region base on above calculating base max crop region. + */ +#ifdef ISP2401 + out_res.width = + stream_env->pipe_configs[css_pipe_id].output_info[0].res.width; + out_res.height = + stream_env->pipe_configs[css_pipe_id].output_info[0].res.height; + if (out_res.width == 0 || out_res.height == 0) { + dev_err(asd->isp->dev, "%s err current pipe output resolution" + , __func__); + return -EINVAL; + } + + if (asd->sensor_array_res.width * out_res.height + < out_res.width * asd->sensor_array_res.height) { + h_offset = asd->sensor_array_res.height - + asd->sensor_array_res.width + * out_res.height / out_res.width; + h_offset = h_offset / 2; + if (dz_config->zoom_region.origin.y < h_offset) + dz_config->zoom_region.origin.y = 0; + else + dz_config->zoom_region.origin.y = + dz_config->zoom_region.origin.y - h_offset; + w_offset = 0; + } else { + w_offset = asd->sensor_array_res.width - + asd->sensor_array_res.height + * out_res.width / out_res.height; + w_offset = w_offset / 2; + if (dz_config->zoom_region.origin.x < w_offset) + dz_config->zoom_region.origin.x = 0; + else + dz_config->zoom_region.origin.x = + dz_config->zoom_region.origin.x - w_offset; + h_offset = 0; + } +#endif + dz_config->zoom_region.origin.x = + dz_config->zoom_region.origin.x + * eff_res.width +#ifndef ISP2401 + / asd->sensor_array_res.width; +#else + / (asd->sensor_array_res.width - + 2 * w_offset); +#endif + dz_config->zoom_region.origin.y = + dz_config->zoom_region.origin.y + * eff_res.height +#ifndef ISP2401 + / asd->sensor_array_res.height; +#else + / (asd->sensor_array_res.height - + 2 * h_offset); +#endif + dz_config->zoom_region.resolution.width = + dz_config->zoom_region.resolution.width + * eff_res.width +#ifndef ISP2401 + / asd->sensor_array_res.width; +#else + / (asd->sensor_array_res.width - + 2 * w_offset); +#endif + dz_config->zoom_region.resolution.height = + dz_config->zoom_region.resolution.height + * eff_res.height +#ifndef ISP2401 + / asd->sensor_array_res.height; +#else + / (asd->sensor_array_res.height - + 2 * h_offset); +#endif + + /* + * Set same ratio of crop region resolution and current pipe output + * resolution + */ +#ifndef ISP2401 + out_res.width = + stream_env->pipe_configs[css_pipe_id].output_info[0].res.width; + out_res.height = + stream_env->pipe_configs[css_pipe_id].output_info[0].res.height; + if (out_res.width == 0 || out_res.height == 0) { + dev_err(asd->isp->dev, "%s err current pipe output resolution" + , __func__); + return -EINVAL; + } + +#endif + if (out_res.width * dz_config->zoom_region.resolution.height + > dz_config->zoom_region.resolution.width * out_res.height) { + dz_config->zoom_region.resolution.height = + dz_config->zoom_region.resolution.width + * out_res.height / out_res.width; + } else { + dz_config->zoom_region.resolution.width = + dz_config->zoom_region.resolution.height + * out_res.width / out_res.height; + } + dev_dbg(asd->isp->dev, "%s crop region:(%d,%d),(%d,%d) eff_res(%d, %d) array_size(%d,%d) out_res(%d, %d)\n", + __func__, dz_config->zoom_region.origin.x, + dz_config->zoom_region.origin.y, + dz_config->zoom_region.resolution.width, + dz_config->zoom_region.resolution.height, + eff_res.width, eff_res.height, + asd->sensor_array_res.width, + asd->sensor_array_res.height, + out_res.width, out_res.height); + + + if ((dz_config->zoom_region.origin.x + + dz_config->zoom_region.resolution.width + > eff_res.width) || + (dz_config->zoom_region.origin.y + + dz_config->zoom_region.resolution.height + > eff_res.height)) + return -EINVAL; + + return 0; +} + + +/* + * Function to check the zoom region whether is effective + */ +static bool atomisp_check_zoom_region( + struct atomisp_sub_device *asd, + struct ia_css_dz_config *dz_config) +{ + struct atomisp_resolution config; + bool flag = false; + unsigned int w , h; + + memset(&config, 0, sizeof(struct atomisp_resolution)); + + if (dz_config->dx && dz_config->dy) + return true; + + config.width = asd->sensor_array_res.width; + config.height = asd->sensor_array_res.height; + w = dz_config->zoom_region.origin.x + + dz_config->zoom_region.resolution.width; + h = dz_config->zoom_region.origin.y + + dz_config->zoom_region.resolution.height; + + if ((w <= config.width) && (h <= config.height) && w > 0 && h > 0) + flag = true; + else + /* setting error zoom region */ + dev_err(asd->isp->dev, "%s zoom region ERROR:dz_config:(%d,%d),(%d,%d)array_res(%d, %d)\n", + __func__, dz_config->zoom_region.origin.x, + dz_config->zoom_region.origin.y, + dz_config->zoom_region.resolution.width, + dz_config->zoom_region.resolution.height, + config.width, config.height); + + return flag; +} + +void atomisp_apply_css_parameters( + struct atomisp_sub_device *asd, + struct atomisp_css_params *css_param) +{ + if (css_param->update_flag.wb_config) + atomisp_css_set_wb_config(asd, &css_param->wb_config); + + if (css_param->update_flag.ob_config) + atomisp_css_set_ob_config(asd, &css_param->ob_config); + + if (css_param->update_flag.dp_config) + atomisp_css_set_dp_config(asd, &css_param->dp_config); + + if (css_param->update_flag.nr_config) + atomisp_css_set_nr_config(asd, &css_param->nr_config); + + if (css_param->update_flag.ee_config) + atomisp_css_set_ee_config(asd, &css_param->ee_config); + + if (css_param->update_flag.tnr_config) + atomisp_css_set_tnr_config(asd, &css_param->tnr_config); + + if (css_param->update_flag.a3a_config) + atomisp_css_set_3a_config(asd, &css_param->s3a_config); + + if (css_param->update_flag.ctc_config) + atomisp_css_set_ctc_config(asd, &css_param->ctc_config); + + if (css_param->update_flag.cnr_config) + atomisp_css_set_cnr_config(asd, &css_param->cnr_config); + + if (css_param->update_flag.ecd_config) + atomisp_css_set_ecd_config(asd, &css_param->ecd_config); + + if (css_param->update_flag.ynr_config) + atomisp_css_set_ynr_config(asd, &css_param->ynr_config); + + if (css_param->update_flag.fc_config) + atomisp_css_set_fc_config(asd, &css_param->fc_config); + + if (css_param->update_flag.macc_config) + atomisp_css_set_macc_config(asd, &css_param->macc_config); + + if (css_param->update_flag.aa_config) + atomisp_css_set_aa_config(asd, &css_param->aa_config); + + if (css_param->update_flag.anr_config) + atomisp_css_set_anr_config(asd, &css_param->anr_config); + + if (css_param->update_flag.xnr_config) + atomisp_css_set_xnr_config(asd, &css_param->xnr_config); + + if (css_param->update_flag.yuv2rgb_cc_config) + atomisp_css_set_yuv2rgb_cc_config(asd, + &css_param->yuv2rgb_cc_config); + + if (css_param->update_flag.rgb2yuv_cc_config) + atomisp_css_set_rgb2yuv_cc_config(asd, + &css_param->rgb2yuv_cc_config); + + if (css_param->update_flag.macc_table) + atomisp_css_set_macc_table(asd, &css_param->macc_table); + + if (css_param->update_flag.xnr_table) + atomisp_css_set_xnr_table(asd, &css_param->xnr_table); + + if (css_param->update_flag.r_gamma_table) + atomisp_css_set_r_gamma_table(asd, &css_param->r_gamma_table); + + if (css_param->update_flag.g_gamma_table) + atomisp_css_set_g_gamma_table(asd, &css_param->g_gamma_table); + + if (css_param->update_flag.b_gamma_table) + atomisp_css_set_b_gamma_table(asd, &css_param->b_gamma_table); + + if (css_param->update_flag.anr_thres) + atomisp_css_set_anr_thres(asd, &css_param->anr_thres); + + if (css_param->update_flag.shading_table) + atomisp_css_set_shading_table(asd, css_param->shading_table); + + if (css_param->update_flag.morph_table && asd->params.gdc_cac_en) + atomisp_css_set_morph_table(asd, css_param->morph_table); + + if (css_param->update_flag.dvs2_coefs) { + struct atomisp_css_dvs_grid_info *dvs_grid_info = + atomisp_css_get_dvs_grid_info( + &asd->params.curr_grid_info); + + if (dvs_grid_info && dvs_grid_info->enable) + atomisp_css_set_dvs2_coefs(asd, css_param->dvs2_coeff); + } + + if (css_param->update_flag.dvs_6axis_config) + atomisp_css_set_dvs_6axis(asd, css_param->dvs_6axis); + + atomisp_css_set_isp_config_id(asd, css_param->isp_config_id); + /* + * These configurations are on used by ISP1.x, not for ISP2.x, + * so do not handle them. see comments of ia_css_isp_config. + * 1 cc_config + * 2 ce_config + * 3 de_config + * 4 gc_config + * 5 gamma_table + * 6 ctc_table + * 7 dvs_coefs + */ +} + +static unsigned int long copy_from_compatible(void *to, const void *from, + unsigned long n, bool from_user) +{ + if (from_user) + return copy_from_user(to, from, n); + else + memcpy(to, from, n); + return 0; +} + +int atomisp_cp_general_isp_parameters(struct atomisp_sub_device *asd, + struct atomisp_parameters *arg, + struct atomisp_css_params *css_param, + bool from_user) +{ + struct atomisp_parameters *cur_config = &css_param->update_flag; + + if (!arg || !asd || !css_param) + return -EINVAL; + + if (arg->wb_config && (from_user || !cur_config->wb_config)) { + if (copy_from_compatible(&css_param->wb_config, arg->wb_config, + sizeof(struct atomisp_css_wb_config), + from_user)) + return -EFAULT; + css_param->update_flag.wb_config = + (struct atomisp_wb_config *) &css_param->wb_config; + } + + if (arg->ob_config && (from_user || !cur_config->ob_config)) { + if (copy_from_compatible(&css_param->ob_config, arg->ob_config, + sizeof(struct atomisp_css_ob_config), + from_user)) + return -EFAULT; + css_param->update_flag.ob_config = + (struct atomisp_ob_config *) &css_param->ob_config; + } + + if (arg->dp_config && (from_user || !cur_config->dp_config)) { + if (copy_from_compatible(&css_param->dp_config, arg->dp_config, + sizeof(struct atomisp_css_dp_config), + from_user)) + return -EFAULT; + css_param->update_flag.dp_config = + (struct atomisp_dp_config *) &css_param->dp_config; + } + + if (asd->run_mode->val != ATOMISP_RUN_MODE_VIDEO) { + if (arg->dz_config && (from_user || !cur_config->dz_config)) { + if (copy_from_compatible(&css_param->dz_config, + arg->dz_config, + sizeof(struct atomisp_css_dz_config), + from_user)) + return -EFAULT; + if (!atomisp_check_zoom_region(asd, + &css_param->dz_config)) { + dev_err(asd->isp->dev, "crop region error!"); + return -EINVAL; + } + css_param->update_flag.dz_config = + (struct atomisp_dz_config *) + &css_param->dz_config; + } + } + + if (arg->nr_config && (from_user || !cur_config->nr_config)) { + if (copy_from_compatible(&css_param->nr_config, arg->nr_config, + sizeof(struct atomisp_css_nr_config), + from_user)) + return -EFAULT; + css_param->update_flag.nr_config = + (struct atomisp_nr_config *) &css_param->nr_config; + } + + if (arg->ee_config && (from_user || !cur_config->ee_config)) { + if (copy_from_compatible(&css_param->ee_config, arg->ee_config, + sizeof(struct atomisp_css_ee_config), + from_user)) + return -EFAULT; + css_param->update_flag.ee_config = + (struct atomisp_ee_config *) &css_param->ee_config; + } + + if (arg->tnr_config && (from_user || !cur_config->tnr_config)) { + if (copy_from_compatible(&css_param->tnr_config, + arg->tnr_config, + sizeof(struct atomisp_css_tnr_config), + from_user)) + return -EFAULT; + css_param->update_flag.tnr_config = + (struct atomisp_tnr_config *) + &css_param->tnr_config; + } + + if (arg->a3a_config && (from_user || !cur_config->a3a_config)) { + if (copy_from_compatible(&css_param->s3a_config, + arg->a3a_config, + sizeof(struct atomisp_css_3a_config), + from_user)) + return -EFAULT; + css_param->update_flag.a3a_config = + (struct atomisp_3a_config *) &css_param->s3a_config; + } + + if (arg->ctc_config && (from_user || !cur_config->ctc_config)) { + if (copy_from_compatible(&css_param->ctc_config, + arg->ctc_config, + sizeof(struct atomisp_css_ctc_config), + from_user)) + return -EFAULT; + css_param->update_flag.ctc_config = + (struct atomisp_ctc_config *) + &css_param->ctc_config; + } + + if (arg->cnr_config && (from_user || !cur_config->cnr_config)) { + if (copy_from_compatible(&css_param->cnr_config, + arg->cnr_config, + sizeof(struct atomisp_css_cnr_config), + from_user)) + return -EFAULT; + css_param->update_flag.cnr_config = + (struct atomisp_cnr_config *) + &css_param->cnr_config; + } + + if (arg->ecd_config && (from_user || !cur_config->ecd_config)) { + if (copy_from_compatible(&css_param->ecd_config, + arg->ecd_config, + sizeof(struct atomisp_css_ecd_config), + from_user)) + return -EFAULT; + css_param->update_flag.ecd_config = + (struct atomisp_ecd_config *) + &css_param->ecd_config; + } + + if (arg->ynr_config && (from_user || !cur_config->ynr_config)) { + if (copy_from_compatible(&css_param->ynr_config, + arg->ynr_config, + sizeof(struct atomisp_css_ynr_config), + from_user)) + return -EFAULT; + css_param->update_flag.ynr_config = + (struct atomisp_ynr_config *) + &css_param->ynr_config; + } + + if (arg->fc_config && (from_user || !cur_config->fc_config)) { + if (copy_from_compatible(&css_param->fc_config, + arg->fc_config, + sizeof(struct atomisp_css_fc_config), + from_user)) + return -EFAULT; + css_param->update_flag.fc_config = + (struct atomisp_fc_config *) &css_param->fc_config; + } + + if (arg->macc_config && (from_user || !cur_config->macc_config)) { + if (copy_from_compatible(&css_param->macc_config, + arg->macc_config, + sizeof(struct atomisp_css_macc_config), + from_user)) + return -EFAULT; + css_param->update_flag.macc_config = + (struct atomisp_macc_config *) + &css_param->macc_config; + } + + if (arg->aa_config && (from_user || !cur_config->aa_config)) { + if (copy_from_compatible(&css_param->aa_config, arg->aa_config, + sizeof(struct atomisp_css_aa_config), + from_user)) + return -EFAULT; + css_param->update_flag.aa_config = + (struct atomisp_aa_config *) &css_param->aa_config; + } + + if (arg->anr_config && (from_user || !cur_config->anr_config)) { + if (copy_from_compatible(&css_param->anr_config, + arg->anr_config, + sizeof(struct atomisp_css_anr_config), + from_user)) + return -EFAULT; + css_param->update_flag.anr_config = + (struct atomisp_anr_config *) + &css_param->anr_config; + } + + if (arg->xnr_config && (from_user || !cur_config->xnr_config)) { + if (copy_from_compatible(&css_param->xnr_config, + arg->xnr_config, + sizeof(struct atomisp_css_xnr_config), + from_user)) + return -EFAULT; + css_param->update_flag.xnr_config = + (struct atomisp_xnr_config *) + &css_param->xnr_config; + } + + if (arg->yuv2rgb_cc_config && + (from_user || !cur_config->yuv2rgb_cc_config)) { + if (copy_from_compatible(&css_param->yuv2rgb_cc_config, + arg->yuv2rgb_cc_config, + sizeof(struct atomisp_css_cc_config), + from_user)) + return -EFAULT; + css_param->update_flag.yuv2rgb_cc_config = + (struct atomisp_cc_config *) + &css_param->yuv2rgb_cc_config; + } + + if (arg->rgb2yuv_cc_config && + (from_user || !cur_config->rgb2yuv_cc_config)) { + if (copy_from_compatible(&css_param->rgb2yuv_cc_config, + arg->rgb2yuv_cc_config, + sizeof(struct atomisp_css_cc_config), + from_user)) + return -EFAULT; + css_param->update_flag.rgb2yuv_cc_config = + (struct atomisp_cc_config *) + &css_param->rgb2yuv_cc_config; + } + + if (arg->macc_table && (from_user || !cur_config->macc_table)) { + if (copy_from_compatible(&css_param->macc_table, + arg->macc_table, + sizeof(struct atomisp_css_macc_table), + from_user)) + return -EFAULT; + css_param->update_flag.macc_table = + (struct atomisp_macc_table *) + &css_param->macc_table; + } + + if (arg->xnr_table && (from_user || !cur_config->xnr_table)) { + if (copy_from_compatible(&css_param->xnr_table, + arg->xnr_table, + sizeof(struct atomisp_css_xnr_table), + from_user)) + return -EFAULT; + css_param->update_flag.xnr_table = + (struct atomisp_xnr_table *) &css_param->xnr_table; + } + + if (arg->r_gamma_table && (from_user || !cur_config->r_gamma_table)) { + if (copy_from_compatible(&css_param->r_gamma_table, + arg->r_gamma_table, + sizeof(struct atomisp_css_rgb_gamma_table), + from_user)) + return -EFAULT; + css_param->update_flag.r_gamma_table = + (struct atomisp_rgb_gamma_table *) + &css_param->r_gamma_table; + } + + if (arg->g_gamma_table && (from_user || !cur_config->g_gamma_table)) { + if (copy_from_compatible(&css_param->g_gamma_table, + arg->g_gamma_table, + sizeof(struct atomisp_css_rgb_gamma_table), + from_user)) + return -EFAULT; + css_param->update_flag.g_gamma_table = + (struct atomisp_rgb_gamma_table *) + &css_param->g_gamma_table; + } + + if (arg->b_gamma_table && (from_user || !cur_config->b_gamma_table)) { + if (copy_from_compatible(&css_param->b_gamma_table, + arg->b_gamma_table, + sizeof(struct atomisp_css_rgb_gamma_table), + from_user)) + return -EFAULT; + css_param->update_flag.b_gamma_table = + (struct atomisp_rgb_gamma_table *) + &css_param->b_gamma_table; + } + + if (arg->anr_thres && (from_user || !cur_config->anr_thres)) { + if (copy_from_compatible(&css_param->anr_thres, arg->anr_thres, + sizeof(struct atomisp_css_anr_thres), + from_user)) + return -EFAULT; + css_param->update_flag.anr_thres = + (struct atomisp_anr_thres *) &css_param->anr_thres; + } + + if (from_user) + css_param->isp_config_id = arg->isp_config_id; + /* + * These configurations are on used by ISP1.x, not for ISP2.x, + * so do not handle them. see comments of ia_css_isp_config. + * 1 cc_config + * 2 ce_config + * 3 de_config + * 4 gc_config + * 5 gamma_table + * 6 ctc_table + * 7 dvs_coefs + */ + return 0; +} + +int atomisp_cp_lsc_table(struct atomisp_sub_device *asd, + struct atomisp_shading_table *source_st, + struct atomisp_css_params *css_param, + bool from_user) +{ + unsigned int i; + unsigned int len_table; + struct atomisp_css_shading_table *shading_table; + struct atomisp_css_shading_table *old_table; +#ifdef ISP2401 + struct atomisp_shading_table st; +#endif + + if (!source_st) + return 0; + + if (!css_param) + return -EINVAL; + + if (!from_user && css_param->update_flag.shading_table) + return 0; + +#ifdef ISP2401 + if (copy_from_compatible(&st, source_st, + sizeof(struct atomisp_shading_table), + from_user)) { + dev_err(asd->isp->dev, "copy shading table failed!"); + return -EFAULT; + } + +#endif + old_table = css_param->shading_table; + +#ifdef ISP2401 + +#endif + /* user config is to disable the shading table. */ +#ifndef ISP2401 + if (!source_st->enable) { +#else + if (!st.enable) { +#endif + /* Generate a minimum table with enable = 0. */ + shading_table = atomisp_css_shading_table_alloc(1, 1); + if (!shading_table) + return -ENOMEM; + shading_table->enable = 0; + goto set_lsc; + } + + /* Setting a new table. Validate first - all tables must be set */ + for (i = 0; i < ATOMISP_NUM_SC_COLORS; i++) { +#ifndef ISP2401 + if (!source_st->data[i]) +#else + if (!st.data[i]) { + dev_err(asd->isp->dev, "shading table validate failed"); +#endif + return -EINVAL; +#ifdef ISP2401 + } +#endif + } + + /* Shading table size per color */ +#ifndef ISP2401 + if (source_st->width > SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR || + source_st->height > SH_CSS_MAX_SCTBL_HEIGHT_PER_COLOR) +#else + if (st.width > SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR || + st.height > SH_CSS_MAX_SCTBL_HEIGHT_PER_COLOR) { + dev_err(asd->isp->dev, "shading table w/h validate failed!"); +#endif + return -EINVAL; +#ifdef ISP2401 + } +#endif + +#ifndef ISP2401 + shading_table = atomisp_css_shading_table_alloc(source_st->width, + source_st->height); + if (!shading_table) + return -ENOMEM; +#else + shading_table = atomisp_css_shading_table_alloc(st.width, + st.height); + if (!shading_table) { + dev_err(asd->isp->dev, "shading table alloc failed!"); + return -ENOMEM; + } +#endif + +#ifndef ISP2401 + len_table = source_st->width * source_st->height * ATOMISP_SC_TYPE_SIZE; +#else + len_table = st.width * st.height * ATOMISP_SC_TYPE_SIZE; +#endif + for (i = 0; i < ATOMISP_NUM_SC_COLORS; i++) { + if (copy_from_compatible(shading_table->data[i], +#ifndef ISP2401 + source_st->data[i], len_table, from_user)) { +#else + st.data[i], len_table, from_user)) { +#endif + atomisp_css_shading_table_free(shading_table); + return -EFAULT; + } + + } +#ifndef ISP2401 + shading_table->sensor_width = source_st->sensor_width; + shading_table->sensor_height = source_st->sensor_height; + shading_table->fraction_bits = source_st->fraction_bits; + shading_table->enable = source_st->enable; +#else + shading_table->sensor_width = st.sensor_width; + shading_table->sensor_height = st.sensor_height; + shading_table->fraction_bits = st.fraction_bits; + shading_table->enable = st.enable; +#endif + + /* No need to update shading table if it is the same */ + if (old_table != NULL && + old_table->sensor_width == shading_table->sensor_width && + old_table->sensor_height == shading_table->sensor_height && + old_table->width == shading_table->width && + old_table->height == shading_table->height && + old_table->fraction_bits == shading_table->fraction_bits && + old_table->enable == shading_table->enable) { + bool data_is_same = true; + + for (i = 0; i < ATOMISP_NUM_SC_COLORS; i++) { + if (memcmp(shading_table->data[i], old_table->data[i], + len_table) != 0) { + data_is_same = false; + break; + } + } + + if (data_is_same) { + atomisp_css_shading_table_free(shading_table); + return 0; + } + } + +set_lsc: + /* set LSC to CSS */ + css_param->shading_table = shading_table; + css_param->update_flag.shading_table = + (struct atomisp_shading_table *) shading_table; + asd->params.sc_en = shading_table != NULL; + + if (old_table) + atomisp_css_shading_table_free(old_table); + + return 0; +} + +int atomisp_css_cp_dvs2_coefs(struct atomisp_sub_device *asd, + struct ia_css_dvs2_coefficients *coefs, + struct atomisp_css_params *css_param, + bool from_user) +{ + struct atomisp_css_dvs_grid_info *cur = + atomisp_css_get_dvs_grid_info(&asd->params.curr_grid_info); + int dvs_hor_coef_bytes, dvs_ver_coef_bytes; +#ifdef ISP2401 + struct ia_css_dvs2_coefficients dvs2_coefs; +#endif + + if (!coefs || !cur) + return 0; + + if (!from_user && css_param->update_flag.dvs2_coefs) + return 0; + +#ifndef ISP2401 + if (sizeof(*cur) != sizeof(coefs->grid) || + memcmp(&coefs->grid, cur, sizeof(coefs->grid))) { +#else + if (copy_from_compatible(&dvs2_coefs, coefs, + sizeof(struct ia_css_dvs2_coefficients), + from_user)) { + dev_err(asd->isp->dev, "copy dvs2 coef failed"); + return -EFAULT; + } + + if (sizeof(*cur) != sizeof(dvs2_coefs.grid) || + memcmp(&dvs2_coefs.grid, cur, sizeof(dvs2_coefs.grid))) { +#endif + dev_err(asd->isp->dev, "dvs grid mis-match!\n"); + /* If the grid info in the argument differs from the current + grid info, we tell the caller to reset the grid size and + try again. */ + return -EAGAIN; + } + +#ifndef ISP2401 + if (coefs->hor_coefs.odd_real == NULL || + coefs->hor_coefs.odd_imag == NULL || + coefs->hor_coefs.even_real == NULL || + coefs->hor_coefs.even_imag == NULL || + coefs->ver_coefs.odd_real == NULL || + coefs->ver_coefs.odd_imag == NULL || + coefs->ver_coefs.even_real == NULL || + coefs->ver_coefs.even_imag == NULL) +#else + if (dvs2_coefs.hor_coefs.odd_real == NULL || + dvs2_coefs.hor_coefs.odd_imag == NULL || + dvs2_coefs.hor_coefs.even_real == NULL || + dvs2_coefs.hor_coefs.even_imag == NULL || + dvs2_coefs.ver_coefs.odd_real == NULL || + dvs2_coefs.ver_coefs.odd_imag == NULL || + dvs2_coefs.ver_coefs.even_real == NULL || + dvs2_coefs.ver_coefs.even_imag == NULL) +#endif + return -EINVAL; + + if (!css_param->dvs2_coeff) { + /* DIS coefficients. */ + css_param->dvs2_coeff = ia_css_dvs2_coefficients_allocate(cur); + if (!css_param->dvs2_coeff) + return -ENOMEM; + } + + dvs_hor_coef_bytes = asd->params.dvs_hor_coef_bytes; + dvs_ver_coef_bytes = asd->params.dvs_ver_coef_bytes; + if (copy_from_compatible(css_param->dvs2_coeff->hor_coefs.odd_real, +#ifndef ISP2401 + coefs->hor_coefs.odd_real, dvs_hor_coef_bytes, from_user) || +#else + dvs2_coefs.hor_coefs.odd_real, dvs_hor_coef_bytes, from_user) || +#endif + copy_from_compatible(css_param->dvs2_coeff->hor_coefs.odd_imag, +#ifndef ISP2401 + coefs->hor_coefs.odd_imag, dvs_hor_coef_bytes, from_user) || +#else + dvs2_coefs.hor_coefs.odd_imag, dvs_hor_coef_bytes, from_user) || +#endif + copy_from_compatible(css_param->dvs2_coeff->hor_coefs.even_real, +#ifndef ISP2401 + coefs->hor_coefs.even_real, dvs_hor_coef_bytes, from_user) || +#else + dvs2_coefs.hor_coefs.even_real, dvs_hor_coef_bytes, from_user) || +#endif + copy_from_compatible(css_param->dvs2_coeff->hor_coefs.even_imag, +#ifndef ISP2401 + coefs->hor_coefs.even_imag, dvs_hor_coef_bytes, from_user) || +#else + dvs2_coefs.hor_coefs.even_imag, dvs_hor_coef_bytes, from_user) || +#endif + copy_from_compatible(css_param->dvs2_coeff->ver_coefs.odd_real, +#ifndef ISP2401 + coefs->ver_coefs.odd_real, dvs_ver_coef_bytes, from_user) || +#else + dvs2_coefs.ver_coefs.odd_real, dvs_ver_coef_bytes, from_user) || +#endif + copy_from_compatible(css_param->dvs2_coeff->ver_coefs.odd_imag, +#ifndef ISP2401 + coefs->ver_coefs.odd_imag, dvs_ver_coef_bytes, from_user) || +#else + dvs2_coefs.ver_coefs.odd_imag, dvs_ver_coef_bytes, from_user) || +#endif + copy_from_compatible(css_param->dvs2_coeff->ver_coefs.even_real, +#ifndef ISP2401 + coefs->ver_coefs.even_real, dvs_ver_coef_bytes, from_user) || +#else + dvs2_coefs.ver_coefs.even_real, dvs_ver_coef_bytes, from_user) || +#endif + copy_from_compatible(css_param->dvs2_coeff->ver_coefs.even_imag, +#ifndef ISP2401 + coefs->ver_coefs.even_imag, dvs_ver_coef_bytes, from_user)) { +#else + dvs2_coefs.ver_coefs.even_imag, dvs_ver_coef_bytes, from_user)) { +#endif + ia_css_dvs2_coefficients_free(css_param->dvs2_coeff); + css_param->dvs2_coeff = NULL; + return -EFAULT; + } + + css_param->update_flag.dvs2_coefs = + (struct atomisp_dvs2_coefficients *)css_param->dvs2_coeff; + return 0; +} + +int atomisp_cp_dvs_6axis_config(struct atomisp_sub_device *asd, + struct atomisp_dvs_6axis_config *source_6axis_config, + struct atomisp_css_params *css_param, + bool from_user) +{ + struct atomisp_css_dvs_6axis_config *dvs_6axis_config; + struct atomisp_css_dvs_6axis_config *old_6axis_config; +#ifdef ISP2401 + struct atomisp_css_dvs_6axis_config t_6axis_config; +#endif + struct ia_css_stream *stream = + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream; + struct atomisp_css_dvs_grid_info *dvs_grid_info = + atomisp_css_get_dvs_grid_info(&asd->params.curr_grid_info); + int ret = -EFAULT; + + if (stream == NULL) { + dev_err(asd->isp->dev, "%s: internal error!", __func__); + return -EINVAL; + } + + if (!source_6axis_config || !dvs_grid_info) + return 0; + + if (!dvs_grid_info->enable) + return 0; + + if (!from_user && css_param->update_flag.dvs_6axis_config) + return 0; + + /* check whether need to reallocate for 6 axis config */ + old_6axis_config = css_param->dvs_6axis; + dvs_6axis_config = old_6axis_config; +#ifdef ISP2401 + + if (copy_from_compatible(&t_6axis_config, source_6axis_config, + sizeof(struct atomisp_dvs_6axis_config), + from_user)) { + dev_err(asd->isp->dev, "copy morph table failed!"); + return -EFAULT; + } + +#endif + if (old_6axis_config && +#ifndef ISP2401 + (old_6axis_config->width_y != source_6axis_config->width_y || + old_6axis_config->height_y != source_6axis_config->height_y || + old_6axis_config->width_uv != source_6axis_config->width_uv || + old_6axis_config->height_uv != source_6axis_config->height_uv)) { +#else + (old_6axis_config->width_y != t_6axis_config.width_y || + old_6axis_config->height_y != t_6axis_config.height_y || + old_6axis_config->width_uv != t_6axis_config.width_uv || + old_6axis_config->height_uv != t_6axis_config.height_uv)) { +#endif + ia_css_dvs2_6axis_config_free(css_param->dvs_6axis); + css_param->dvs_6axis = NULL; + + dvs_6axis_config = ia_css_dvs2_6axis_config_allocate(stream); + if (!dvs_6axis_config) + return -ENOMEM; + } else if (!dvs_6axis_config) { + dvs_6axis_config = ia_css_dvs2_6axis_config_allocate(stream); + if (!dvs_6axis_config) + return -ENOMEM; + } + +#ifndef ISP2401 + dvs_6axis_config->exp_id = source_6axis_config->exp_id; +#else + dvs_6axis_config->exp_id = t_6axis_config.exp_id; +#endif + + if (copy_from_compatible(dvs_6axis_config->xcoords_y, +#ifndef ISP2401 + source_6axis_config->xcoords_y, + source_6axis_config->width_y * + source_6axis_config->height_y * + sizeof(*source_6axis_config->xcoords_y), +#else + t_6axis_config.xcoords_y, + t_6axis_config.width_y * + t_6axis_config.height_y * + sizeof(*dvs_6axis_config->xcoords_y), +#endif + from_user)) + goto error; + if (copy_from_compatible(dvs_6axis_config->ycoords_y, +#ifndef ISP2401 + source_6axis_config->ycoords_y, + source_6axis_config->width_y * + source_6axis_config->height_y * + sizeof(*source_6axis_config->ycoords_y), +#else + t_6axis_config.ycoords_y, + t_6axis_config.width_y * + t_6axis_config.height_y * + sizeof(*dvs_6axis_config->ycoords_y), +#endif + from_user)) + goto error; + if (copy_from_compatible(dvs_6axis_config->xcoords_uv, +#ifndef ISP2401 + source_6axis_config->xcoords_uv, + source_6axis_config->width_uv * + source_6axis_config->height_uv * + sizeof(*source_6axis_config->xcoords_uv), +#else + t_6axis_config.xcoords_uv, + t_6axis_config.width_uv * + t_6axis_config.height_uv * + sizeof(*dvs_6axis_config->xcoords_uv), +#endif + from_user)) + goto error; + if (copy_from_compatible(dvs_6axis_config->ycoords_uv, +#ifndef ISP2401 + source_6axis_config->ycoords_uv, + source_6axis_config->width_uv * + source_6axis_config->height_uv * + sizeof(*source_6axis_config->ycoords_uv), +#else + t_6axis_config.ycoords_uv, + t_6axis_config.width_uv * + t_6axis_config.height_uv * + sizeof(*dvs_6axis_config->ycoords_uv), +#endif + from_user)) + goto error; + + css_param->dvs_6axis = dvs_6axis_config; + css_param->update_flag.dvs_6axis_config = + (struct atomisp_dvs_6axis_config *) dvs_6axis_config; + return 0; + +error: + if (dvs_6axis_config) + ia_css_dvs2_6axis_config_free(dvs_6axis_config); + return ret; +} + +int atomisp_cp_morph_table(struct atomisp_sub_device *asd, + struct atomisp_morph_table *source_morph_table, + struct atomisp_css_params *css_param, + bool from_user) +{ + int ret = -EFAULT; + unsigned int i; + struct atomisp_css_morph_table *morph_table; +#ifdef ISP2401 + struct atomisp_css_morph_table mtbl; +#endif + struct atomisp_css_morph_table *old_morph_table; + + if (!source_morph_table) + return 0; + + if (!from_user && css_param->update_flag.morph_table) + return 0; + + old_morph_table = css_param->morph_table; + +#ifdef ISP2401 + if (copy_from_compatible(&mtbl, source_morph_table, + sizeof(struct atomisp_morph_table), + from_user)) { + dev_err(asd->isp->dev, "copy morph table failed!"); + return -EFAULT; + } + +#endif + morph_table = atomisp_css_morph_table_allocate( +#ifndef ISP2401 + source_morph_table->width, + source_morph_table->height); +#else + mtbl.width, + mtbl.height); +#endif + if (!morph_table) + return -ENOMEM; + + for (i = 0; i < CSS_MORPH_TABLE_NUM_PLANES; i++) { + if (copy_from_compatible(morph_table->coordinates_x[i], + source_morph_table->coordinates_x[i], +#ifndef ISP2401 + source_morph_table->height * source_morph_table->width * + sizeof(*source_morph_table->coordinates_x[i]), +#else + mtbl.height * mtbl.width * + sizeof(*morph_table->coordinates_x[i]), +#endif + from_user)) + goto error; + + if (copy_from_compatible(morph_table->coordinates_y[i], + source_morph_table->coordinates_y[i], +#ifndef ISP2401 + source_morph_table->height * source_morph_table->width * + sizeof(*source_morph_table->coordinates_y[i]), +#else + mtbl.height * mtbl.width * + sizeof(*morph_table->coordinates_y[i]), +#endif + from_user)) + goto error; + } + + css_param->morph_table = morph_table; + if (old_morph_table) + atomisp_css_morph_table_free(old_morph_table); + css_param->update_flag.morph_table = + (struct atomisp_morph_table *) morph_table; + return 0; + +error: + if (morph_table) + atomisp_css_morph_table_free(morph_table); + return ret; +} + +int atomisp_makeup_css_parameters(struct atomisp_sub_device *asd, + struct atomisp_parameters *arg, + struct atomisp_css_params *css_param) +{ + int ret; + + ret = atomisp_cp_general_isp_parameters(asd, arg, css_param, false); + if (ret) + return ret; + ret = atomisp_cp_lsc_table(asd, arg->shading_table, css_param, false); + if (ret) + return ret; + ret = atomisp_cp_morph_table(asd, arg->morph_table, css_param, false); + if (ret) + return ret; + ret = atomisp_css_cp_dvs2_coefs(asd, + (struct ia_css_dvs2_coefficients *) arg->dvs2_coefs, + css_param, false); + if (ret) + return ret; + ret = atomisp_cp_dvs_6axis_config(asd, arg->dvs_6axis_config, + css_param, false); + return ret; +} + +void atomisp_free_css_parameters(struct atomisp_css_params *css_param) +{ + if (css_param->dvs_6axis) { + ia_css_dvs2_6axis_config_free(css_param->dvs_6axis); + css_param->dvs_6axis = NULL; + } + if (css_param->dvs2_coeff) { + ia_css_dvs2_coefficients_free(css_param->dvs2_coeff); + css_param->dvs2_coeff = NULL; + } + if (css_param->shading_table) { + ia_css_shading_table_free(css_param->shading_table); + css_param->shading_table = NULL; + } + if (css_param->morph_table) { + ia_css_morph_table_free(css_param->morph_table); + css_param->morph_table = NULL; + } +} + +/* + * Check parameter queue list and buffer queue list to find out if matched items + * and then set parameter to CSS and enqueue buffer to CSS. + * Of course, if the buffer in buffer waiting list is not bound to a per-frame + * parameter, it will be enqueued into CSS as long as the per-frame setting + * buffers before it get enqueued. + */ +void atomisp_handle_parameter_and_buffer(struct atomisp_video_pipe *pipe) +{ + struct atomisp_sub_device *asd = pipe->asd; + struct videobuf_buffer *vb = NULL, *vb_tmp; + struct atomisp_css_params_with_list *param = NULL, *param_tmp; + struct videobuf_vmalloc_memory *vm_mem = NULL; + unsigned long irqflags; + bool need_to_enqueue_buffer = false; + + if (atomisp_is_vf_pipe(pipe)) + return; + + /* + * CSS/FW requires set parameter and enqueue buffer happen after ISP + * is streamon. + */ + if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED) + return; + + if (list_empty(&pipe->per_frame_params) || + list_empty(&pipe->buffers_waiting_for_param)) + return; + + list_for_each_entry_safe(vb, vb_tmp, + &pipe->buffers_waiting_for_param, queue) { + if (pipe->frame_request_config_id[vb->i]) { + list_for_each_entry_safe(param, param_tmp, + &pipe->per_frame_params, list) { + if (pipe->frame_request_config_id[vb->i] != + param->params.isp_config_id) + continue; + + list_del(¶m->list); + list_del(&vb->queue); + /* + * clear the request config id as the buffer + * will be handled and enqueued into CSS soon + */ + pipe->frame_request_config_id[vb->i] = 0; + pipe->frame_params[vb->i] = param; + vm_mem = vb->priv; + BUG_ON(!vm_mem); + break; + } + + if (vm_mem) { + spin_lock_irqsave(&pipe->irq_lock, irqflags); + list_add_tail(&vb->queue, &pipe->activeq); + spin_unlock_irqrestore(&pipe->irq_lock, irqflags); + vm_mem = NULL; + need_to_enqueue_buffer = true; + } else { + /* The is the end, stop further loop */ + break; + } + } else { + list_del(&vb->queue); + pipe->frame_params[vb->i] = NULL; + spin_lock_irqsave(&pipe->irq_lock, irqflags); + list_add_tail(&vb->queue, &pipe->activeq); + spin_unlock_irqrestore(&pipe->irq_lock, irqflags); + need_to_enqueue_buffer = true; + } + } + + if (need_to_enqueue_buffer) { + atomisp_qbuffers_to_css(asd); +#ifndef ISP2401 + if (!atomisp_is_wdt_running(asd) && atomisp_buffers_queued(asd)) + atomisp_wdt_start(asd); +#else + if (atomisp_buffers_queued_pipe(pipe)) { + if (!atomisp_is_wdt_running(pipe)) + atomisp_wdt_start(pipe); + else + atomisp_wdt_refresh_pipe(pipe, + ATOMISP_WDT_KEEP_CURRENT_DELAY); + } +#endif + } +} + +/* +* Function to configure ISP parameters +*/ +int atomisp_set_parameters(struct video_device *vdev, + struct atomisp_parameters *arg) +{ + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + struct atomisp_sub_device *asd = pipe->asd; + struct atomisp_css_params_with_list *param = NULL; + struct atomisp_css_params *css_param = &asd->params.css_param; + int ret; + + if (asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream == NULL) { + dev_err(asd->isp->dev, "%s: internal error!\n", __func__); + return -EINVAL; + } + + dev_dbg(asd->isp->dev, "%s: set parameter(per_frame_setting %d) for asd%d with isp_config_id %d of %s\n", + __func__, arg->per_frame_setting, asd->index, + arg->isp_config_id, vdev->name); +#ifdef ISP2401 + + if (atomisp_is_vf_pipe(pipe) && arg->per_frame_setting) { + dev_err(asd->isp->dev, "%s: vf pipe not support per_frame_setting", + __func__); + return -EINVAL; + } + +#endif + if (arg->per_frame_setting && !atomisp_is_vf_pipe(pipe)) { + /* + * Per-frame setting enabled, we allocate a new paramter + * buffer to cache the parameters and only when frame buffers + * are ready, the parameters will be set to CSS. + * per-frame setting only works for the main output frame. + */ + param = atomisp_kernel_zalloc(sizeof(*param), true); + if (!param) { + dev_err(asd->isp->dev, "%s: failed to alloc params buffer\n", + __func__); + return -ENOMEM; + } + css_param = ¶m->params; + } + + ret = atomisp_cp_general_isp_parameters(asd, arg, css_param, true); + if (ret) + goto apply_parameter_failed; + + ret = atomisp_cp_lsc_table(asd, arg->shading_table, css_param, true); + if (ret) + goto apply_parameter_failed; + + ret = atomisp_cp_morph_table(asd, arg->morph_table, css_param, true); + if (ret) + goto apply_parameter_failed; + + ret = atomisp_css_cp_dvs2_coefs(asd, + (struct ia_css_dvs2_coefficients *) arg->dvs2_coefs, + css_param, true); + if (ret) + goto apply_parameter_failed; + + ret = atomisp_cp_dvs_6axis_config(asd, arg->dvs_6axis_config, + css_param, true); + if (ret) + goto apply_parameter_failed; + + if (!(arg->per_frame_setting && !atomisp_is_vf_pipe(pipe))) { + /* indicate to CSS that we have parameters to be updated */ + asd->params.css_update_params_needed = true; + } else { + list_add_tail(¶m->list, &pipe->per_frame_params); + atomisp_handle_parameter_and_buffer(pipe); + } + + return 0; + +apply_parameter_failed: + if (css_param) + atomisp_free_css_parameters(css_param); + if (param) + atomisp_kernel_free(param); + + return ret; +} + +/* + * Function to set/get isp parameters to isp + */ +int atomisp_param(struct atomisp_sub_device *asd, int flag, + struct atomisp_parm *config) +{ + struct atomisp_device *isp = asd->isp; + struct ia_css_pipe_config *vp_cfg = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]. + pipe_configs[IA_CSS_PIPE_ID_VIDEO]; + + /* Read parameter for 3A binary info */ + if (flag == 0) { + struct atomisp_css_dvs_grid_info *dvs_grid_info = + atomisp_css_get_dvs_grid_info( + &asd->params.curr_grid_info); + + if (&config->info == NULL) { + dev_err(isp->dev, "ERROR: NULL pointer in grid_info\n"); + return -EINVAL; + } + atomisp_curr_user_grid_info(asd, &config->info); + + /* We always return the resolution and stride even if there is + * no valid metadata. This allows the caller to get the + * information needed to allocate user-space buffers. */ + config->metadata_config.metadata_height = asd-> + stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream_info. + metadata_info.resolution.height; + config->metadata_config.metadata_stride = asd-> + stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream_info. + metadata_info.stride; + + /* update dvs grid info */ + if (dvs_grid_info) + memcpy(&config->dvs_grid, + dvs_grid_info, + sizeof(struct atomisp_css_dvs_grid_info)); + + if (asd->run_mode->val != ATOMISP_RUN_MODE_VIDEO) { + config->dvs_envelop.width = 0; + config->dvs_envelop.height = 0; + return 0; + } + + /* update dvs envelop info */ + if (!asd->continuous_mode->val) { + config->dvs_envelop.width = vp_cfg->dvs_envelope.width; + config->dvs_envelop.height = + vp_cfg->dvs_envelope.height; + } else { + unsigned int dvs_w, dvs_h, dvs_w_max, dvs_h_max; + + dvs_w = vp_cfg->bayer_ds_out_res.width - + vp_cfg->output_info[0].res.width; + dvs_h = vp_cfg->bayer_ds_out_res.height - + vp_cfg->output_info[0].res.height; + dvs_w_max = rounddown( + vp_cfg->output_info[0].res.width / 5, + ATOM_ISP_STEP_WIDTH); + dvs_h_max = rounddown( + vp_cfg->output_info[0].res.height / 5, + ATOM_ISP_STEP_HEIGHT); + + config->dvs_envelop.width = min(dvs_w, dvs_w_max); + config->dvs_envelop.height = min(dvs_h, dvs_h_max); + } + + return 0; + } + + memcpy(&asd->params.css_param.wb_config, &config->wb_config, + sizeof(struct atomisp_css_wb_config)); + memcpy(&asd->params.css_param.ob_config, &config->ob_config, + sizeof(struct atomisp_css_ob_config)); + memcpy(&asd->params.css_param.dp_config, &config->dp_config, + sizeof(struct atomisp_css_dp_config)); + memcpy(&asd->params.css_param.de_config, &config->de_config, + sizeof(struct atomisp_css_de_config)); + memcpy(&asd->params.css_param.dz_config, &config->dz_config, + sizeof(struct atomisp_css_dz_config)); + memcpy(&asd->params.css_param.ce_config, &config->ce_config, + sizeof(struct atomisp_css_ce_config)); + memcpy(&asd->params.css_param.nr_config, &config->nr_config, + sizeof(struct atomisp_css_nr_config)); + memcpy(&asd->params.css_param.ee_config, &config->ee_config, + sizeof(struct atomisp_css_ee_config)); + memcpy(&asd->params.css_param.tnr_config, &config->tnr_config, + sizeof(struct atomisp_css_tnr_config)); + + if (asd->params.color_effect == V4L2_COLORFX_NEGATIVE) { + asd->params.css_param.cc_config.matrix[3] = -config->cc_config.matrix[3]; + asd->params.css_param.cc_config.matrix[4] = -config->cc_config.matrix[4]; + asd->params.css_param.cc_config.matrix[5] = -config->cc_config.matrix[5]; + asd->params.css_param.cc_config.matrix[6] = -config->cc_config.matrix[6]; + asd->params.css_param.cc_config.matrix[7] = -config->cc_config.matrix[7]; + asd->params.css_param.cc_config.matrix[8] = -config->cc_config.matrix[8]; + } + + if (asd->params.color_effect != V4L2_COLORFX_SEPIA && + asd->params.color_effect != V4L2_COLORFX_BW) { + memcpy(&asd->params.css_param.cc_config, &config->cc_config, + sizeof(struct atomisp_css_cc_config)); + atomisp_css_set_cc_config(asd, &asd->params.css_param.cc_config); + } + + atomisp_css_set_wb_config(asd, &asd->params.css_param.wb_config); + atomisp_css_set_ob_config(asd, &asd->params.css_param.ob_config); + atomisp_css_set_de_config(asd, &asd->params.css_param.de_config); + atomisp_css_set_dz_config(asd, &asd->params.css_param.dz_config); + atomisp_css_set_ce_config(asd, &asd->params.css_param.ce_config); + atomisp_css_set_dp_config(asd, &asd->params.css_param.dp_config); + atomisp_css_set_nr_config(asd, &asd->params.css_param.nr_config); + atomisp_css_set_ee_config(asd, &asd->params.css_param.ee_config); + atomisp_css_set_tnr_config(asd, &asd->params.css_param.tnr_config); + asd->params.css_update_params_needed = true; + + return 0; +} + +/* + * Function to configure color effect of the image + */ +int atomisp_color_effect(struct atomisp_sub_device *asd, int flag, + __s32 *effect) +{ + struct atomisp_css_cc_config *cc_config = NULL; + struct atomisp_css_macc_table *macc_table = NULL; + struct atomisp_css_ctc_table *ctc_table = NULL; + int ret = 0; + struct v4l2_control control; + struct atomisp_device *isp = asd->isp; + + if (flag == 0) { + *effect = asd->params.color_effect; + return 0; + } + + + control.id = V4L2_CID_COLORFX; + control.value = *effect; + ret = + v4l2_s_ctrl(NULL, isp->inputs[asd->input_curr].camera->ctrl_handler, + &control); + /* + * if set color effect to sensor successfully, return + * 0 directly. + */ + if (!ret) { + asd->params.color_effect = (u32)*effect; + return 0; + } + + if (*effect == asd->params.color_effect) + return 0; + + /* + * isp_subdev->params.macc_en should be set to false. + */ + asd->params.macc_en = false; + + switch (*effect) { + case V4L2_COLORFX_NONE: + macc_table = &asd->params.css_param.macc_table; + asd->params.macc_en = true; + break; + case V4L2_COLORFX_SEPIA: + cc_config = &sepia_cc_config; + break; + case V4L2_COLORFX_NEGATIVE: + cc_config = &nega_cc_config; + break; + case V4L2_COLORFX_BW: + cc_config = &mono_cc_config; + break; + case V4L2_COLORFX_SKY_BLUE: + macc_table = &blue_macc_table; + asd->params.macc_en = true; + break; + case V4L2_COLORFX_GRASS_GREEN: + macc_table = &green_macc_table; + asd->params.macc_en = true; + break; + case V4L2_COLORFX_SKIN_WHITEN_LOW: + macc_table = &skin_low_macc_table; + asd->params.macc_en = true; + break; + case V4L2_COLORFX_SKIN_WHITEN: + macc_table = &skin_medium_macc_table; + asd->params.macc_en = true; + break; + case V4L2_COLORFX_SKIN_WHITEN_HIGH: + macc_table = &skin_high_macc_table; + asd->params.macc_en = true; + break; + case V4L2_COLORFX_VIVID: + ctc_table = &vivid_ctc_table; + break; + default: + return -EINVAL; + } + atomisp_update_capture_mode(asd); + + if (cc_config) + atomisp_css_set_cc_config(asd, cc_config); + if (macc_table) + atomisp_css_set_macc_table(asd, macc_table); + if (ctc_table) + atomisp_css_set_ctc_table(asd, ctc_table); + asd->params.color_effect = (u32)*effect; + asd->params.css_update_params_needed = true; + return 0; +} + +/* + * Function to configure bad pixel correction + */ +int atomisp_bad_pixel(struct atomisp_sub_device *asd, int flag, + __s32 *value) +{ + + if (flag == 0) { + *value = asd->params.bad_pixel_en; + return 0; + } + asd->params.bad_pixel_en = !!*value; + + return 0; +} + +/* + * Function to configure bad pixel correction params + */ +int atomisp_bad_pixel_param(struct atomisp_sub_device *asd, int flag, + struct atomisp_dp_config *config) +{ + if (flag == 0) { + /* Get bad pixel from current setup */ + if (atomisp_css_get_dp_config(asd, config)) + return -EINVAL; + } else { + /* Set bad pixel to isp parameters */ + memcpy(&asd->params.css_param.dp_config, config, + sizeof(asd->params.css_param.dp_config)); + atomisp_css_set_dp_config(asd, &asd->params.css_param.dp_config); + asd->params.css_update_params_needed = true; + } + + return 0; +} + +/* + * Function to enable/disable video image stablization + */ +int atomisp_video_stable(struct atomisp_sub_device *asd, int flag, + __s32 *value) +{ + if (flag == 0) + *value = asd->params.video_dis_en; + else + asd->params.video_dis_en = !!*value; + + return 0; +} + +/* + * Function to configure fixed pattern noise + */ +int atomisp_fixed_pattern(struct atomisp_sub_device *asd, int flag, + __s32 *value) +{ + + if (flag == 0) { + *value = asd->params.fpn_en; + return 0; + } + + if (*value == 0) { + asd->params.fpn_en = 0; + return 0; + } + + /* Add function to get black from from sensor with shutter off */ + return 0; +} + +static unsigned int +atomisp_bytesperline_to_padded_width(unsigned int bytesperline, + enum atomisp_css_frame_format format) +{ + switch (format) { + case CSS_FRAME_FORMAT_UYVY: + case CSS_FRAME_FORMAT_YUYV: + case CSS_FRAME_FORMAT_RAW: + case CSS_FRAME_FORMAT_RGB565: + return bytesperline/2; + case CSS_FRAME_FORMAT_RGBA888: + return bytesperline/4; + /* The following cases could be removed, but we leave them + in to document the formats that are included. */ + case CSS_FRAME_FORMAT_NV11: + case CSS_FRAME_FORMAT_NV12: + case CSS_FRAME_FORMAT_NV16: + case CSS_FRAME_FORMAT_NV21: + case CSS_FRAME_FORMAT_NV61: + case CSS_FRAME_FORMAT_YV12: + case CSS_FRAME_FORMAT_YV16: + case CSS_FRAME_FORMAT_YUV420: + case CSS_FRAME_FORMAT_YUV420_16: + case CSS_FRAME_FORMAT_YUV422: + case CSS_FRAME_FORMAT_YUV422_16: + case CSS_FRAME_FORMAT_YUV444: + case CSS_FRAME_FORMAT_YUV_LINE: + case CSS_FRAME_FORMAT_PLANAR_RGB888: + case CSS_FRAME_FORMAT_QPLANE6: + case CSS_FRAME_FORMAT_BINARY_8: + default: + return bytesperline; + } +} + +static int +atomisp_v4l2_framebuffer_to_css_frame(const struct v4l2_framebuffer *arg, + struct atomisp_css_frame **result) +{ + struct atomisp_css_frame *res; + unsigned int padded_width; + enum atomisp_css_frame_format sh_format; + char *tmp_buf = NULL; + int ret = 0; + + sh_format = v4l2_fmt_to_sh_fmt(arg->fmt.pixelformat); + padded_width = atomisp_bytesperline_to_padded_width( + arg->fmt.bytesperline, sh_format); + + /* Note: the padded width on an atomisp_css_frame is in elements, not in + bytes. The RAW frame we use here should always be a 16bit RAW + frame. This is why we bytesperline/2 is equal to the padded with */ + if (atomisp_css_frame_allocate(&res, arg->fmt.width, arg->fmt.height, + sh_format, padded_width, 0)) { + ret = -ENOMEM; + goto err; + } + + tmp_buf = vmalloc(arg->fmt.sizeimage); + if (!tmp_buf) { + ret = -ENOMEM; + goto err; + } + if (copy_from_user(tmp_buf, (void __user __force *)arg->base, + arg->fmt.sizeimage)) { + ret = -EFAULT; + goto err; + } + + if (hmm_store(res->data, tmp_buf, arg->fmt.sizeimage)) { + ret = -EINVAL; + goto err; + } + +err: + if (ret && res) + atomisp_css_frame_free(res); + if (tmp_buf) + vfree(tmp_buf); + if (ret == 0) + *result = res; + return ret; +} + +/* + * Function to configure fixed pattern noise table + */ +int atomisp_fixed_pattern_table(struct atomisp_sub_device *asd, + struct v4l2_framebuffer *arg) +{ + struct atomisp_css_frame *raw_black_frame = NULL; + int ret; + + if (arg == NULL) + return -EINVAL; + + ret = atomisp_v4l2_framebuffer_to_css_frame(arg, &raw_black_frame); + if (ret) + return ret; + if (atomisp_css_set_black_frame(asd, raw_black_frame)) + ret = -ENOMEM; + + atomisp_css_frame_free(raw_black_frame); + return ret; +} + +/* + * Function to configure false color correction + */ +int atomisp_false_color(struct atomisp_sub_device *asd, int flag, + __s32 *value) +{ + /* Get nr config from current setup */ + if (flag == 0) { + *value = asd->params.false_color; + return 0; + } + + /* Set nr config to isp parameters */ + if (*value) { + atomisp_css_set_default_de_config(asd); + } else { + asd->params.css_param.de_config.pixelnoise = 0; + atomisp_css_set_de_config(asd, &asd->params.css_param.de_config); + } + asd->params.css_update_params_needed = true; + asd->params.false_color = *value; + return 0; +} + +/* + * Function to configure bad pixel correction params + */ +int atomisp_false_color_param(struct atomisp_sub_device *asd, int flag, + struct atomisp_de_config *config) +{ + if (flag == 0) { + /* Get false color from current setup */ + if (atomisp_css_get_de_config(asd, config)) + return -EINVAL; + } else { + /* Set false color to isp parameters */ + memcpy(&asd->params.css_param.de_config, config, + sizeof(asd->params.css_param.de_config)); + atomisp_css_set_de_config(asd, &asd->params.css_param.de_config); + asd->params.css_update_params_needed = true; + } + + return 0; +} + +/* + * Function to configure white balance params + */ +int atomisp_white_balance_param(struct atomisp_sub_device *asd, int flag, + struct atomisp_wb_config *config) +{ + if (flag == 0) { + /* Get white balance from current setup */ + if (atomisp_css_get_wb_config(asd, config)) + return -EINVAL; + } else { + /* Set white balance to isp parameters */ + memcpy(&asd->params.css_param.wb_config, config, + sizeof(asd->params.css_param.wb_config)); + atomisp_css_set_wb_config(asd, &asd->params.css_param.wb_config); + asd->params.css_update_params_needed = true; + } + + return 0; +} + +int atomisp_3a_config_param(struct atomisp_sub_device *asd, int flag, + struct atomisp_3a_config *config) +{ + struct atomisp_device *isp = asd->isp; + + dev_dbg(isp->dev, ">%s %d\n", __func__, flag); + + if (flag == 0) { + /* Get white balance from current setup */ + if (atomisp_css_get_3a_config(asd, config)) + return -EINVAL; + } else { + /* Set white balance to isp parameters */ + memcpy(&asd->params.css_param.s3a_config, config, + sizeof(asd->params.css_param.s3a_config)); + atomisp_css_set_3a_config(asd, &asd->params.css_param.s3a_config); + asd->params.css_update_params_needed = true; + } + + dev_dbg(isp->dev, "<%s %d\n", __func__, flag); + return 0; +} + +/* + * Function to setup digital zoom + */ +int atomisp_digital_zoom(struct atomisp_sub_device *asd, int flag, + __s32 *value) +{ + u32 zoom; + struct atomisp_device *isp = asd->isp; + + unsigned int max_zoom = MRFLD_MAX_ZOOM_FACTOR; + + if (flag == 0) { + atomisp_css_get_zoom_factor(asd, &zoom); + *value = max_zoom - zoom; + } else { + if (*value < 0) + return -EINVAL; + + zoom = max_zoom - min_t(u32, max_zoom - 1, *value); + atomisp_css_set_zoom_factor(asd, zoom); + + dev_dbg(isp->dev, "%s, zoom: %d\n", __func__, zoom); + asd->params.css_update_params_needed = true; + } + + return 0; +} + +/* + * Function to get sensor specific info for current resolution, + * which will be used for auto exposure conversion. + */ +int atomisp_get_sensor_mode_data(struct atomisp_sub_device *asd, + struct atomisp_sensor_mode_data *config) +{ + struct camera_mipi_info *mipi_info; + struct atomisp_device *isp = asd->isp; + + mipi_info = atomisp_to_sensor_mipi_info( + isp->inputs[asd->input_curr].camera); + if (mipi_info == NULL) + return -EINVAL; + + memcpy(config, &mipi_info->data, sizeof(*config)); + return 0; +} + +int atomisp_get_fmt(struct video_device *vdev, struct v4l2_format *f) +{ + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + + f->fmt.pix = pipe->pix; + + return 0; +} + +static void __atomisp_update_stream_env(struct atomisp_sub_device *asd, + uint16_t stream_index, struct atomisp_input_stream_info *stream_info) +{ + int i; + +#if defined(ISP2401_NEW_INPUT_SYSTEM) + /* assign virtual channel id return from sensor driver query */ + asd->stream_env[stream_index].ch_id = stream_info->ch_id; +#endif + asd->stream_env[stream_index].isys_configs = stream_info->isys_configs; + for (i = 0; i < stream_info->isys_configs; i++) { + asd->stream_env[stream_index].isys_info[i].input_format = + stream_info->isys_info[i].input_format; + asd->stream_env[stream_index].isys_info[i].width = + stream_info->isys_info[i].width; + asd->stream_env[stream_index].isys_info[i].height = + stream_info->isys_info[i].height; + } +} + +static void __atomisp_init_stream_info(uint16_t stream_index, + struct atomisp_input_stream_info *stream_info) +{ + int i; + + stream_info->enable = 1; + stream_info->stream = stream_index; + stream_info->ch_id = 0; + stream_info->isys_configs = 0; + for (i = 0; i < MAX_STREAMS_PER_CHANNEL; i++) { + stream_info->isys_info[i].input_format = 0; + stream_info->isys_info[i].width = 0; + stream_info->isys_info[i].height = 0; + } +} + +/* This function looks up the closest available resolution. */ +int atomisp_try_fmt(struct video_device *vdev, struct v4l2_format *f, + bool *res_overflow) +{ + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; +#ifndef ISP2401 + struct v4l2_subdev_pad_config pad_cfg; +#else + struct v4l2_subdev_pad_config pad_cfg; +#endif + struct v4l2_subdev_format format = { + .which = V4L2_SUBDEV_FORMAT_TRY, +#ifndef ISP2401 + }; +#else + }; +#endif + struct v4l2_mbus_framefmt *snr_mbus_fmt = &format.format; + const struct atomisp_format_bridge *fmt; + struct atomisp_input_stream_info *stream_info = +#ifndef ISP2401 + (struct atomisp_input_stream_info *)snr_mbus_fmt->reserved; +#else + (struct atomisp_input_stream_info *)snr_mbus_fmt->reserved; +#endif + uint16_t stream_index; + int source_pad = atomisp_subdev_source_pad(vdev); + int ret; + + if (isp->inputs[asd->input_curr].camera == NULL) + return -EINVAL; + + stream_index = atomisp_source_pad_to_stream_id(asd, source_pad); + fmt = atomisp_get_format_bridge(f->fmt.pix.pixelformat); + if (fmt == NULL) { + dev_err(isp->dev, "unsupported pixelformat!\n"); + fmt = atomisp_output_fmts; + } + +#ifdef ISP2401 + if (f->fmt.pix.width <= 0 || f->fmt.pix.height <= 0) + return -EINVAL; + +#endif + snr_mbus_fmt->code = fmt->mbus_code; + snr_mbus_fmt->width = f->fmt.pix.width; + snr_mbus_fmt->height = f->fmt.pix.height; + + __atomisp_init_stream_info(stream_index, stream_info); + + dev_dbg(isp->dev, "try_mbus_fmt: asking for %ux%u\n", + snr_mbus_fmt->width, snr_mbus_fmt->height); + + ret = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, +#ifndef ISP2401 + pad, set_fmt, &pad_cfg, &format); +#else + pad, set_fmt, &pad_cfg, &format); +#endif + if (ret) + return ret; + + dev_dbg(isp->dev, "try_mbus_fmt: got %ux%u\n", + snr_mbus_fmt->width, snr_mbus_fmt->height); + + fmt = atomisp_get_format_bridge_from_mbus(snr_mbus_fmt->code); + if (fmt == NULL) { + dev_err(isp->dev, "unknown sensor format 0x%8.8x\n", + snr_mbus_fmt->code); + return -EINVAL; + } + + f->fmt.pix.pixelformat = fmt->pixelformat; + + /* + * If the format is jpeg or custom RAW, then the width and height will + * not satisfy the normal atomisp requirements and no need to check + * the below conditions. So just assign to what is being returned from + * the sensor driver. + */ + if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_JPEG || + f->fmt.pix.pixelformat == V4L2_PIX_FMT_CUSTOM_M10MO_RAW) { + f->fmt.pix.width = snr_mbus_fmt->width; + f->fmt.pix.height = snr_mbus_fmt->height; + return 0; + } + + if (snr_mbus_fmt->width < f->fmt.pix.width + && snr_mbus_fmt->height < f->fmt.pix.height) { + f->fmt.pix.width = snr_mbus_fmt->width; + f->fmt.pix.height = snr_mbus_fmt->height; + /* Set the flag when resolution requested is + * beyond the max value supported by sensor + */ + if (res_overflow != NULL) + *res_overflow = true; + } + + /* app vs isp */ + f->fmt.pix.width = rounddown( + clamp_t(u32, f->fmt.pix.width, ATOM_ISP_MIN_WIDTH, + ATOM_ISP_MAX_WIDTH), ATOM_ISP_STEP_WIDTH); + f->fmt.pix.height = rounddown( + clamp_t(u32, f->fmt.pix.height, ATOM_ISP_MIN_HEIGHT, + ATOM_ISP_MAX_HEIGHT), ATOM_ISP_STEP_HEIGHT); + + return 0; +} + +static int +atomisp_try_fmt_file(struct atomisp_device *isp, struct v4l2_format *f) +{ + u32 width = f->fmt.pix.width; + u32 height = f->fmt.pix.height; + u32 pixelformat = f->fmt.pix.pixelformat; + enum v4l2_field field = f->fmt.pix.field; + u32 depth; + + if (!atomisp_get_format_bridge(pixelformat)) { + dev_err(isp->dev, "Wrong output pixelformat\n"); + return -EINVAL; + } + + depth = get_pixel_depth(pixelformat); + + if (!field || field == V4L2_FIELD_ANY) + field = V4L2_FIELD_NONE; + else if (field != V4L2_FIELD_NONE) { + dev_err(isp->dev, "Wrong output field\n"); + return -EINVAL; + } + + f->fmt.pix.field = field; + f->fmt.pix.width = clamp_t(u32, + rounddown(width, (u32)ATOM_ISP_STEP_WIDTH), + ATOM_ISP_MIN_WIDTH, ATOM_ISP_MAX_WIDTH); + f->fmt.pix.height = clamp_t(u32, rounddown(height, + (u32)ATOM_ISP_STEP_HEIGHT), + ATOM_ISP_MIN_HEIGHT, ATOM_ISP_MAX_HEIGHT); + f->fmt.pix.bytesperline = (width * depth) >> 3; + + return 0; +} + +mipi_port_ID_t __get_mipi_port(struct atomisp_device *isp, + enum atomisp_camera_port port) +{ + switch (port) { + case ATOMISP_CAMERA_PORT_PRIMARY: + return MIPI_PORT0_ID; + case ATOMISP_CAMERA_PORT_SECONDARY: + return MIPI_PORT1_ID; + case ATOMISP_CAMERA_PORT_TERTIARY: + if (MIPI_PORT1_ID + 1 != N_MIPI_PORT_ID) + return MIPI_PORT1_ID + 1; + /* go through down for else case */ + default: + dev_err(isp->dev, "unsupported port: %d\n", port); + return MIPI_PORT0_ID; + } +} + +static inline int atomisp_set_sensor_mipi_to_isp( + struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + struct camera_mipi_info *mipi_info) +{ + struct v4l2_control ctrl; + struct atomisp_device *isp = asd->isp; + const struct atomisp_in_fmt_conv *fc; + int mipi_freq = 0; + unsigned int input_format, bayer_order; + + ctrl.id = V4L2_CID_LINK_FREQ; + if (v4l2_g_ctrl + (isp->inputs[asd->input_curr].camera->ctrl_handler, &ctrl) == 0) + mipi_freq = ctrl.value; + + if (asd->stream_env[stream_id].isys_configs == 1) { + input_format = + asd->stream_env[stream_id].isys_info[0].input_format; + atomisp_css_isys_set_format(asd, stream_id, + input_format, IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX); + } else if (asd->stream_env[stream_id].isys_configs == 2) { + atomisp_css_isys_two_stream_cfg_update_stream1( + asd, stream_id, + asd->stream_env[stream_id].isys_info[0].input_format, + asd->stream_env[stream_id].isys_info[0].width, + asd->stream_env[stream_id].isys_info[0].height); + + atomisp_css_isys_two_stream_cfg_update_stream2( + asd, stream_id, + asd->stream_env[stream_id].isys_info[1].input_format, + asd->stream_env[stream_id].isys_info[1].width, + asd->stream_env[stream_id].isys_info[1].height); + } + + /* Compatibility for sensors which provide no media bus code + * in s_mbus_framefmt() nor support pad formats. */ + if (mipi_info->input_format != -1) { + bayer_order = mipi_info->raw_bayer_order; + + /* Input stream config is still needs configured */ + /* TODO: Check if this is necessary */ + fc = atomisp_find_in_fmt_conv_by_atomisp_in_fmt( + mipi_info->input_format); + if (!fc) + return -EINVAL; + input_format = fc->css_stream_fmt; + } else { + struct v4l2_mbus_framefmt *sink; + sink = atomisp_subdev_get_ffmt(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK); + fc = atomisp_find_in_fmt_conv(sink->code); + if (!fc) + return -EINVAL; + input_format = fc->css_stream_fmt; + bayer_order = fc->bayer_order; + } + + atomisp_css_input_set_format(asd, stream_id, input_format); + atomisp_css_input_set_bayer_order(asd, stream_id, bayer_order); + + fc = atomisp_find_in_fmt_conv_by_atomisp_in_fmt( + mipi_info->metadata_format); + if (!fc) + return -EINVAL; + input_format = fc->css_stream_fmt; + atomisp_css_input_configure_port(asd, + __get_mipi_port(asd->isp, mipi_info->port), + mipi_info->num_lanes, + 0xffff4, mipi_freq, + input_format, + mipi_info->metadata_width, + mipi_info->metadata_height); + return 0; +} + +static int __enable_continuous_mode(struct atomisp_sub_device *asd, + bool enable) +{ + struct atomisp_device *isp = asd->isp; + + dev_dbg(isp->dev, + "continuous mode %d, raw buffers %d, stop preview %d\n", + enable, asd->continuous_raw_buffer_size->val, + !asd->continuous_viewfinder->val); +#ifndef ISP2401 + atomisp_css_capture_set_mode(asd, CSS_CAPTURE_MODE_PRIMARY); +#else + atomisp_update_capture_mode(asd); +#endif + /* in case of ANR, force capture pipe to offline mode */ + atomisp_css_capture_enable_online(asd, ATOMISP_INPUT_STREAM_GENERAL, + asd->params.low_light ? false : !enable); + atomisp_css_preview_enable_online(asd, ATOMISP_INPUT_STREAM_GENERAL, + !enable); + atomisp_css_enable_continuous(asd, enable); + atomisp_css_enable_cvf(asd, asd->continuous_viewfinder->val); + + if (atomisp_css_continuous_set_num_raw_frames(asd, + asd->continuous_raw_buffer_size->val)) { + dev_err(isp->dev, "css_continuous_set_num_raw_frames failed\n"); + return -EINVAL; + } + + if (!enable) { + atomisp_css_enable_raw_binning(asd, false); + atomisp_css_input_set_two_pixels_per_clock(asd, false); + } + + if (isp->inputs[asd->input_curr].type != FILE_INPUT) + atomisp_css_input_set_mode(asd, CSS_INPUT_MODE_SENSOR); + + return atomisp_update_run_mode(asd); +} + +int configure_pp_input_nop(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height) +{ + return 0; +} + +int configure_output_nop(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum atomisp_css_frame_format sh_fmt) +{ + return 0; +} + +int get_frame_info_nop(struct atomisp_sub_device *asd, + struct atomisp_css_frame_info *finfo) +{ + return 0; +} + +/** + * Resets CSS parameters that depend on input resolution. + * + * Update params like CSS RAW binning, 2ppc mode and pp_input + * which depend on input size, but are not automatically + * handled in CSS when the input resolution is changed. + */ +static int css_input_resolution_changed(struct atomisp_sub_device *asd, + struct v4l2_mbus_framefmt *ffmt) +{ + struct atomisp_metadata_buf *md_buf = NULL, *_md_buf; + unsigned int i; + + dev_dbg(asd->isp->dev, "css_input_resolution_changed to %ux%u\n", + ffmt->width, ffmt->height); + +#if defined(ISP2401_NEW_INPUT_SYSTEM) + atomisp_css_input_set_two_pixels_per_clock(asd, false); +#else + atomisp_css_input_set_two_pixels_per_clock(asd, true); +#endif + if (asd->continuous_mode->val) { + /* Note for all checks: ffmt includes pad_w+pad_h */ + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO || + (ffmt->width >= 2048 || ffmt->height >= 1536)) { + /* + * For preview pipe, enable only if resolution + * is >= 3M for ISP2400. + */ + atomisp_css_enable_raw_binning(asd, true); + } + } + /* + * If sensor input changed, which means metadata resolution changed + * together. Release all metadata buffers here to let it re-allocated + * next time in reqbufs. + */ + for (i = 0; i < ATOMISP_METADATA_TYPE_NUM; i++) { + list_for_each_entry_safe(md_buf, _md_buf, &asd->metadata[i], + list) { + atomisp_css_free_metadata_buffer(md_buf); + list_del(&md_buf->list); + kfree(md_buf); + } + } + return 0; + + /* + * TODO: atomisp_css_preview_configure_pp_input() not + * reset due to CSS bug tracked as PSI BZ 115124 + */ +} + +static int atomisp_set_fmt_to_isp(struct video_device *vdev, + struct atomisp_css_frame_info *output_info, + struct atomisp_css_frame_info *raw_output_info, + struct v4l2_pix_format *pix, + unsigned int source_pad) +{ + struct camera_mipi_info *mipi_info; + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + const struct atomisp_format_bridge *format; + struct v4l2_rect *isp_sink_crop; + enum atomisp_css_pipe_id pipe_id; + struct v4l2_subdev_fh fh; + int (*configure_output)(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum atomisp_css_frame_format sh_fmt) = + configure_output_nop; + int (*get_frame_info)(struct atomisp_sub_device *asd, + struct atomisp_css_frame_info *finfo) = + get_frame_info_nop; + int (*configure_pp_input)(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height) = + configure_pp_input_nop; + uint16_t stream_index = atomisp_source_pad_to_stream_id(asd, source_pad); + const struct atomisp_in_fmt_conv *fc; + int ret; + + v4l2_fh_init(&fh.vfh, vdev); + + isp_sink_crop = atomisp_subdev_get_rect( + &asd->subdev, NULL, V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK, V4L2_SEL_TGT_CROP); + + format = atomisp_get_format_bridge(pix->pixelformat); + if (format == NULL) + return -EINVAL; + + if (isp->inputs[asd->input_curr].type != TEST_PATTERN && + isp->inputs[asd->input_curr].type != FILE_INPUT) { + mipi_info = atomisp_to_sensor_mipi_info( + isp->inputs[asd->input_curr].camera); + if (!mipi_info) { + dev_err(isp->dev, "mipi_info is NULL\n"); + return -EINVAL; + } + if (atomisp_set_sensor_mipi_to_isp(asd, stream_index, + mipi_info)) + return -EINVAL; + fc = atomisp_find_in_fmt_conv_by_atomisp_in_fmt( + mipi_info->input_format); + if (!fc) + fc = atomisp_find_in_fmt_conv( + atomisp_subdev_get_ffmt(&asd->subdev, + NULL, V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK)->code); + if (!fc) + return -EINVAL; + if (format->sh_fmt == CSS_FRAME_FORMAT_RAW && + raw_output_format_match_input(fc->css_stream_fmt, + pix->pixelformat)) + return -EINVAL; + } + + /* + * Configure viewfinder also when vfpp is disabled: the + * CSS still requires viewfinder configuration. + */ + if (asd->fmt_auto->val || + asd->vfpp->val != ATOMISP_VFPP_ENABLE) { + struct v4l2_rect vf_size = {0}; + struct v4l2_mbus_framefmt vf_ffmt = {0}; + + if (pix->width < 640 || pix->height < 480) { + vf_size.width = pix->width; + vf_size.height = pix->height; + } else { + vf_size.width = 640; + vf_size.height = 480; + } + + /* FIXME: proper format name for this one. See + atomisp_output_fmts[] in atomisp_v4l2.c */ + vf_ffmt.code = V4L2_MBUS_FMT_CUSTOM_YUV420; + + atomisp_subdev_set_selection(&asd->subdev, fh.pad, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SOURCE_VF, + V4L2_SEL_TGT_COMPOSE, 0, &vf_size); + atomisp_subdev_set_ffmt(&asd->subdev, fh.pad, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SOURCE_VF, &vf_ffmt); + asd->video_out_vf.sh_fmt = CSS_FRAME_FORMAT_NV12; + + if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_SCALER) { + atomisp_css_video_configure_viewfinder(asd, + vf_size.width, vf_size.height, 0, + asd->video_out_vf.sh_fmt); + } else if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) { + if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW || + source_pad == ATOMISP_SUBDEV_PAD_SOURCE_VIDEO) + atomisp_css_video_configure_viewfinder(asd, + vf_size.width, vf_size.height, 0, + asd->video_out_vf.sh_fmt); + else + atomisp_css_capture_configure_viewfinder(asd, + vf_size.width, vf_size.height, 0, + asd->video_out_vf.sh_fmt); + } else if (source_pad != ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW || + asd->vfpp->val == ATOMISP_VFPP_DISABLE_LOWLAT) { + atomisp_css_capture_configure_viewfinder(asd, + vf_size.width, vf_size.height, 0, + asd->video_out_vf.sh_fmt); + } + } + + if (asd->continuous_mode->val) { + ret = __enable_continuous_mode(asd, true); + if (ret) + return -EINVAL; + } + + atomisp_css_input_set_mode(asd, CSS_INPUT_MODE_SENSOR); + atomisp_css_disable_vf_pp(asd, + asd->vfpp->val != ATOMISP_VFPP_ENABLE); + + /* ISP2401 new input system need to use copy pipe */ + if (asd->copy_mode) { + pipe_id = CSS_PIPE_ID_COPY; + atomisp_css_capture_enable_online(asd, stream_index, false); + } else if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_SCALER) { + /* video same in continuouscapture and online modes */ + configure_output = atomisp_css_video_configure_output; + get_frame_info = atomisp_css_video_get_output_frame_info; + pipe_id = CSS_PIPE_ID_VIDEO; + } else if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) { + if (!asd->continuous_mode->val) { + configure_output = atomisp_css_video_configure_output; + get_frame_info = + atomisp_css_video_get_output_frame_info; + pipe_id = CSS_PIPE_ID_VIDEO; + } else { + if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW || + source_pad == ATOMISP_SUBDEV_PAD_SOURCE_VIDEO) { + configure_output = + atomisp_css_video_configure_output; + get_frame_info = + atomisp_css_video_get_output_frame_info; + configure_pp_input = + atomisp_css_video_configure_pp_input; + pipe_id = CSS_PIPE_ID_VIDEO; + } else { + configure_output = + atomisp_css_capture_configure_output; + get_frame_info = + atomisp_css_capture_get_output_frame_info; + configure_pp_input = + atomisp_css_capture_configure_pp_input; + pipe_id = CSS_PIPE_ID_CAPTURE; + + atomisp_update_capture_mode(asd); + atomisp_css_capture_enable_online(asd, stream_index, false); + } + } + } else if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW) { + configure_output = atomisp_css_preview_configure_output; + get_frame_info = atomisp_css_preview_get_output_frame_info; + configure_pp_input = atomisp_css_preview_configure_pp_input; + pipe_id = CSS_PIPE_ID_PREVIEW; + } else { + /* CSS doesn't support low light mode on SOC cameras, so disable + * it. FIXME: if this is done elsewhere, it gives corrupted + * colors into thumbnail image. + */ + if (isp->inputs[asd->input_curr].type == SOC_CAMERA) + asd->params.low_light = false; + + if (format->sh_fmt == CSS_FRAME_FORMAT_RAW) { + atomisp_css_capture_set_mode(asd, CSS_CAPTURE_MODE_RAW); + atomisp_css_enable_dz(asd, false); + } else { + atomisp_update_capture_mode(asd); + } + + if (!asd->continuous_mode->val) + /* in case of ANR, force capture pipe to offline mode */ + atomisp_css_capture_enable_online(asd, stream_index, + asd->params.low_light ? + false : asd->params.online_process); + + configure_output = atomisp_css_capture_configure_output; + get_frame_info = atomisp_css_capture_get_output_frame_info; + configure_pp_input = atomisp_css_capture_configure_pp_input; + pipe_id = CSS_PIPE_ID_CAPTURE; + + if (!asd->params.online_process && + !asd->continuous_mode->val) { + ret = atomisp_css_capture_get_output_raw_frame_info(asd, + raw_output_info); + if (ret) + return ret; + } + if (!asd->continuous_mode->val && asd->run_mode->val + != ATOMISP_RUN_MODE_STILL_CAPTURE) { + dev_err(isp->dev, + "Need to set the running mode first\n"); + asd->run_mode->val = ATOMISP_RUN_MODE_STILL_CAPTURE; + } + } + + /* + * to SOC camera, use yuvpp pipe. + */ + if (ATOMISP_USE_YUVPP(asd)) + pipe_id = CSS_PIPE_ID_YUVPP; + + if (asd->copy_mode) + ret = atomisp_css_copy_configure_output(asd, stream_index, + pix->width, pix->height, + format->planar ? pix->bytesperline : + pix->bytesperline * 8 / format->depth, + format->sh_fmt); + else + ret = configure_output(asd, pix->width, pix->height, + format->planar ? pix->bytesperline : + pix->bytesperline * 8 / format->depth, + format->sh_fmt); + if (ret) { + dev_err(isp->dev, "configure_output %ux%u, format %8.8x\n", + pix->width, pix->height, format->sh_fmt); + return -EINVAL; + } + + if (asd->continuous_mode->val && + (configure_pp_input == atomisp_css_preview_configure_pp_input || + configure_pp_input == atomisp_css_video_configure_pp_input)) { + /* for isp 2.2, configure pp input is available for continuous + * mode */ + ret = configure_pp_input(asd, isp_sink_crop->width, + isp_sink_crop->height); + if (ret) { + dev_err(isp->dev, "configure_pp_input %ux%u\n", + isp_sink_crop->width, + isp_sink_crop->height); + return -EINVAL; + } + } else { + ret = configure_pp_input(asd, isp_sink_crop->width, + isp_sink_crop->height); + if (ret) { + dev_err(isp->dev, "configure_pp_input %ux%u\n", + isp_sink_crop->width, isp_sink_crop->height); + return -EINVAL; + } + } + if (asd->copy_mode) + ret = atomisp_css_copy_get_output_frame_info(asd, stream_index, + output_info); + else + ret = get_frame_info(asd, output_info); + if (ret) { + dev_err(isp->dev, "get_frame_info %ux%u (padded to %u)\n", + pix->width, pix->height, pix->bytesperline); + return -EINVAL; + } + + atomisp_update_grid_info(asd, pipe_id, source_pad); + + /* Free the raw_dump buffer first */ + atomisp_css_frame_free(asd->raw_output_frame); + asd->raw_output_frame = NULL; + + if (!asd->continuous_mode->val && + !asd->params.online_process && !isp->sw_contex.file_input && + atomisp_css_frame_allocate_from_info(&asd->raw_output_frame, + raw_output_info)) + return -ENOMEM; + + return 0; +} + +static void atomisp_get_dis_envelop(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int *dvs_env_w, unsigned int *dvs_env_h) +{ + struct atomisp_device *isp = asd->isp; + + /* if subdev type is SOC camera,we do not need to set DVS */ + if (isp->inputs[asd->input_curr].type == SOC_CAMERA) + asd->params.video_dis_en = 0; + + if (asd->params.video_dis_en && + asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) { + /* envelope is 20% of the output resolution */ + /* + * dvs envelope cannot be round up. + * it would cause ISP timeout and color switch issue + */ + *dvs_env_w = rounddown(width / 5, ATOM_ISP_STEP_WIDTH); + *dvs_env_h = rounddown(height / 5, ATOM_ISP_STEP_HEIGHT); + } + + asd->params.dis_proj_data_valid = false; + asd->params.css_update_params_needed = true; +} + +static void atomisp_check_copy_mode(struct atomisp_sub_device *asd, + int source_pad, struct v4l2_format *f) +{ +#if defined(ISP2401_NEW_INPUT_SYSTEM) + struct v4l2_mbus_framefmt *sink, *src; + + sink = atomisp_subdev_get_ffmt(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, ATOMISP_SUBDEV_PAD_SINK); + src = atomisp_subdev_get_ffmt(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, source_pad); + + if ((sink->code == src->code && + sink->width == f->fmt.pix.width && + sink->height == f->fmt.pix.height) || + ((asd->isp->inputs[asd->input_curr].type == SOC_CAMERA) && + (asd->isp->inputs[asd->input_curr].camera_caps-> + sensor[asd->sensor_curr].stream_num > 1))) + asd->copy_mode = true; + else +#endif + /* Only used for the new input system */ + asd->copy_mode = false; + + dev_dbg(asd->isp->dev, "copy_mode: %d\n", asd->copy_mode); + +} + +static int atomisp_set_fmt_to_snr(struct video_device *vdev, + struct v4l2_format *f, unsigned int pixelformat, + unsigned int padding_w, unsigned int padding_h, + unsigned int dvs_env_w, unsigned int dvs_env_h) +{ + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + const struct atomisp_format_bridge *format; + struct v4l2_subdev_pad_config pad_cfg; + struct v4l2_subdev_format vformat = { + .which = V4L2_SUBDEV_FORMAT_TRY, + }; + struct v4l2_mbus_framefmt *ffmt = &vformat.format; + struct v4l2_mbus_framefmt *req_ffmt; + struct atomisp_device *isp = asd->isp; + struct atomisp_input_stream_info *stream_info = + (struct atomisp_input_stream_info *)ffmt->reserved; + uint16_t stream_index = ATOMISP_INPUT_STREAM_GENERAL; + int source_pad = atomisp_subdev_source_pad(vdev); + struct v4l2_subdev_fh fh; + int ret; + + v4l2_fh_init(&fh.vfh, vdev); + + stream_index = atomisp_source_pad_to_stream_id(asd, source_pad); + + format = atomisp_get_format_bridge(pixelformat); + if (format == NULL) + return -EINVAL; + + v4l2_fill_mbus_format(ffmt, &f->fmt.pix, format->mbus_code); + ffmt->height += padding_h + dvs_env_h; + ffmt->width += padding_w + dvs_env_w; + + dev_dbg(isp->dev, "s_mbus_fmt: ask %ux%u (padding %ux%u, dvs %ux%u)\n", + ffmt->width, ffmt->height, padding_w, padding_h, + dvs_env_w, dvs_env_h); + + __atomisp_init_stream_info(stream_index, stream_info); + + req_ffmt = ffmt; + + /* Disable dvs if resolution can't be supported by sensor */ + if (asd->params.video_dis_en && + source_pad == ATOMISP_SUBDEV_PAD_SOURCE_VIDEO) { + vformat.which = V4L2_SUBDEV_FORMAT_TRY; + ret = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + pad, set_fmt, &pad_cfg, &vformat); + if (ret) + return ret; + if (ffmt->width < req_ffmt->width || + ffmt->height < req_ffmt->height) { + req_ffmt->height -= dvs_env_h; + req_ffmt->width -= dvs_env_w; + ffmt = req_ffmt; + dev_warn(isp->dev, + "can not enable video dis due to sensor limitation."); + asd->params.video_dis_en = 0; + } + } + dev_dbg(isp->dev, "sensor width: %d, height: %d\n", + ffmt->width, ffmt->height); + vformat.which = V4L2_SUBDEV_FORMAT_ACTIVE; + ret = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, pad, + set_fmt, NULL, &vformat); + if (ret) + return ret; + + __atomisp_update_stream_env(asd, stream_index, stream_info); + + dev_dbg(isp->dev, "sensor width: %d, height: %d\n", + ffmt->width, ffmt->height); + + if (ffmt->width < ATOM_ISP_STEP_WIDTH || + ffmt->height < ATOM_ISP_STEP_HEIGHT) + return -EINVAL; + + if (asd->params.video_dis_en && + source_pad == ATOMISP_SUBDEV_PAD_SOURCE_VIDEO && + (ffmt->width < req_ffmt->width || ffmt->height < req_ffmt->height)) { + dev_warn(isp->dev, + "can not enable video dis due to sensor limitation."); + asd->params.video_dis_en = 0; + } + + atomisp_subdev_set_ffmt(&asd->subdev, fh.pad, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK, ffmt); + + return css_input_resolution_changed(asd, ffmt); +} + +int atomisp_set_fmt(struct video_device *vdev, struct v4l2_format *f) +{ + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + struct atomisp_sub_device *asd = pipe->asd; + const struct atomisp_format_bridge *format_bridge; + const struct atomisp_format_bridge *snr_format_bridge; + struct atomisp_css_frame_info output_info, raw_output_info; + struct v4l2_format snr_fmt = *f; + struct v4l2_format backup_fmt = *f, s_fmt = *f; + unsigned int dvs_env_w = 0, dvs_env_h = 0; + unsigned int padding_w = pad_w, padding_h = pad_h; + bool res_overflow = false, crop_needs_override = false; + struct v4l2_mbus_framefmt isp_sink_fmt; + struct v4l2_mbus_framefmt isp_source_fmt = {0}; + struct v4l2_rect isp_sink_crop; + uint16_t source_pad = atomisp_subdev_source_pad(vdev); + struct v4l2_subdev_fh fh; + int ret; + + dev_dbg(isp->dev, + "setting resolution %ux%u on pad %u for asd%d, bytesperline %u\n", + f->fmt.pix.width, f->fmt.pix.height, source_pad, + asd->index, f->fmt.pix.bytesperline); + + if (source_pad >= ATOMISP_SUBDEV_PADS_NUM) + return -EINVAL; + + if (asd->streaming == ATOMISP_DEVICE_STREAMING_ENABLED) { + dev_warn(isp->dev, "ISP does not support set format while at streaming!\n"); + return -EBUSY; + } + + v4l2_fh_init(&fh.vfh, vdev); + + format_bridge = atomisp_get_format_bridge(f->fmt.pix.pixelformat); + if (format_bridge == NULL) + return -EINVAL; + + pipe->sh_fmt = format_bridge->sh_fmt; + pipe->pix.pixelformat = f->fmt.pix.pixelformat; + + if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_VF || + (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW + && asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO)) { + if (asd->fmt_auto->val) { + struct v4l2_rect *capture_comp; + struct v4l2_rect r = {0}; + + r.width = f->fmt.pix.width; + r.height = f->fmt.pix.height; + + if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW) + capture_comp = atomisp_subdev_get_rect( + &asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SOURCE_VIDEO, + V4L2_SEL_TGT_COMPOSE); + else + capture_comp = atomisp_subdev_get_rect( + &asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE, + V4L2_SEL_TGT_COMPOSE); + + if (capture_comp->width < r.width + || capture_comp->height < r.height) { + r.width = capture_comp->width; + r.height = capture_comp->height; + } + + atomisp_subdev_set_selection( + &asd->subdev, fh.pad, + V4L2_SUBDEV_FORMAT_ACTIVE, source_pad, + V4L2_SEL_TGT_COMPOSE, 0, &r); + + f->fmt.pix.width = r.width; + f->fmt.pix.height = r.height; + } + + if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW && + (asd->isp->inputs[asd->input_curr].type == SOC_CAMERA) && + (asd->isp->inputs[asd->input_curr].camera_caps-> + sensor[asd->sensor_curr].stream_num > 1)) { + /* For M10MO outputing YUV preview images. */ + uint16_t video_index = + atomisp_source_pad_to_stream_id(asd, + ATOMISP_SUBDEV_PAD_SOURCE_VIDEO); + + ret = atomisp_css_copy_get_output_frame_info(asd, + video_index, &output_info); + if (ret) { + dev_err(isp->dev, + "copy_get_output_frame_info ret %i", ret); + return -EINVAL; + } + if (!asd->yuvpp_mode) { + /* + * If viewfinder was configured into copy_mode, + * we switch to using yuvpp pipe instead. + */ + asd->yuvpp_mode = true; + ret = atomisp_css_copy_configure_output( + asd, video_index, 0, 0, 0, 0); + if (ret) { + dev_err(isp->dev, + "failed to disable copy pipe"); + return -EINVAL; + } + ret = atomisp_css_yuvpp_configure_output( + asd, video_index, + output_info.res.width, + output_info.res.height, + output_info.padded_width, + output_info.format); + if (ret) { + dev_err(isp->dev, + "failed to set up yuvpp pipe\n"); + return -EINVAL; + } + atomisp_css_video_enable_online(asd, false); + atomisp_css_preview_enable_online(asd, + ATOMISP_INPUT_STREAM_GENERAL, false); + } + atomisp_css_yuvpp_configure_viewfinder(asd, video_index, + f->fmt.pix.width, f->fmt.pix.height, + format_bridge->planar ? f->fmt.pix.bytesperline + : f->fmt.pix.bytesperline * 8 + / format_bridge->depth, format_bridge->sh_fmt); + atomisp_css_yuvpp_get_viewfinder_frame_info( + asd, video_index, &output_info); + } else if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW) { + atomisp_css_video_configure_viewfinder(asd, + f->fmt.pix.width, f->fmt.pix.height, + format_bridge->planar ? f->fmt.pix.bytesperline + : f->fmt.pix.bytesperline * 8 + / format_bridge->depth, format_bridge->sh_fmt); + atomisp_css_video_get_viewfinder_frame_info(asd, + &output_info); + asd->copy_mode = false; + } else { + atomisp_css_capture_configure_viewfinder(asd, + f->fmt.pix.width, f->fmt.pix.height, + format_bridge->planar ? f->fmt.pix.bytesperline + : f->fmt.pix.bytesperline * 8 + / format_bridge->depth, format_bridge->sh_fmt); + atomisp_css_capture_get_viewfinder_frame_info(asd, + &output_info); + asd->copy_mode = false; + } + + goto done; + } + /* + * Check whether main resolution configured smaller + * than snapshot resolution. If so, force main resolution + * to be the same as snapshot resolution + */ + if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE) { + struct v4l2_rect *r; + + r = atomisp_subdev_get_rect( + &asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SOURCE_VF, V4L2_SEL_TGT_COMPOSE); + + if (r->width && r->height + && (r->width > f->fmt.pix.width + || r->height > f->fmt.pix.height)) + dev_warn(isp->dev, + "Main Resolution config smaller then Vf Resolution. Force to be equal with Vf Resolution."); + } + + /* Pipeline configuration done through subdevs. Bail out now. */ + if (!asd->fmt_auto->val) + goto set_fmt_to_isp; + + /* get sensor resolution and format */ + ret = atomisp_try_fmt(vdev, &snr_fmt, &res_overflow); + if (ret) + return ret; + f->fmt.pix.width = snr_fmt.fmt.pix.width; + f->fmt.pix.height = snr_fmt.fmt.pix.height; + + snr_format_bridge = + atomisp_get_format_bridge(snr_fmt.fmt.pix.pixelformat); + if (!snr_format_bridge) + return -EINVAL; + + atomisp_subdev_get_ffmt(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK)->code = + snr_format_bridge->mbus_code; + + isp_sink_fmt = *atomisp_subdev_get_ffmt(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK); + + isp_source_fmt.code = format_bridge->mbus_code; + atomisp_subdev_set_ffmt(&asd->subdev, fh.pad, + V4L2_SUBDEV_FORMAT_ACTIVE, + source_pad, &isp_source_fmt); + + if (!atomisp_subdev_format_conversion(asd, source_pad)) { + padding_w = 0; + padding_h = 0; + } else if (IS_BYT) { + padding_w = 12; + padding_h = 12; + } + + /* construct resolution supported by isp */ + if (res_overflow && !asd->continuous_mode->val) { + f->fmt.pix.width = rounddown( + clamp_t(u32, f->fmt.pix.width - padding_w, + ATOM_ISP_MIN_WIDTH, + ATOM_ISP_MAX_WIDTH), ATOM_ISP_STEP_WIDTH); + f->fmt.pix.height = rounddown( + clamp_t(u32, f->fmt.pix.height - padding_h, + ATOM_ISP_MIN_HEIGHT, + ATOM_ISP_MAX_HEIGHT), ATOM_ISP_STEP_HEIGHT); + } + + atomisp_get_dis_envelop(asd, f->fmt.pix.width, f->fmt.pix.height, + &dvs_env_w, &dvs_env_h); + + if (asd->continuous_mode->val) { + struct v4l2_rect *r; + + r = atomisp_subdev_get_rect( + &asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE, + V4L2_SEL_TGT_COMPOSE); + /* + * The ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE should get resolutions + * properly set otherwise, it should not be the capture_pad. + */ + if (r->width && r->height) + asd->capture_pad = ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE; + else + asd->capture_pad = source_pad; + } else { + asd->capture_pad = source_pad; + } + /* + * set format info to sensor + * In continuous mode, resolution is set only if it is higher than + * existing value. This because preview pipe will be configured after + * capture pipe and usually has lower resolution than capture pipe. + */ + if (!asd->continuous_mode->val || + isp_sink_fmt.width < (f->fmt.pix.width + padding_w + dvs_env_w) || + isp_sink_fmt.height < (f->fmt.pix.height + padding_h + + dvs_env_h)) { + /* + * For jpeg or custom raw format the sensor will return constant + * width and height. Because we already had quried try_mbus_fmt, + * f->fmt.pix.width and f->fmt.pix.height has been changed to + * this fixed width and height. So we cannot select the correct + * resolution with that information. So use the original width + * and height while set_mbus_fmt() so actual resolutions are + * being used in while set media bus format. + */ + s_fmt = *f; + if (f->fmt.pix.pixelformat == V4L2_PIX_FMT_JPEG || + f->fmt.pix.pixelformat == V4L2_PIX_FMT_CUSTOM_M10MO_RAW) { + s_fmt.fmt.pix.width = backup_fmt.fmt.pix.width; + s_fmt.fmt.pix.height = backup_fmt.fmt.pix.height; + } + ret = atomisp_set_fmt_to_snr(vdev, &s_fmt, + f->fmt.pix.pixelformat, padding_w, + padding_h, dvs_env_w, dvs_env_h); + if (ret) + return -EINVAL; + + atomisp_csi_lane_config(isp); + crop_needs_override = true; + } + + atomisp_check_copy_mode(asd, source_pad, &backup_fmt); + asd->yuvpp_mode = false; /* Reset variable */ + + isp_sink_crop = *atomisp_subdev_get_rect(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK, + V4L2_SEL_TGT_CROP); + + /* Try to enable YUV downscaling if ISP input is 10 % (either + * width or height) bigger than the desired result. */ + if (isp_sink_crop.width * 9 / 10 < f->fmt.pix.width || + isp_sink_crop.height * 9 / 10 < f->fmt.pix.height || + (atomisp_subdev_format_conversion(asd, source_pad) && + ((asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO && + !asd->continuous_mode->val) || + asd->vfpp->val == ATOMISP_VFPP_DISABLE_SCALER))) { + /* for continuous mode, preview size might be smaller than + * still capture size. if preview size still needs crop, + * pick the larger one between crop size of preview and + * still capture. + */ + if (asd->continuous_mode->val + && source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW + && !crop_needs_override) { + isp_sink_crop.width = + max_t(unsigned int, f->fmt.pix.width, + isp_sink_crop.width); + isp_sink_crop.height = + max_t(unsigned int, f->fmt.pix.height, + isp_sink_crop.height); + } else { + isp_sink_crop.width = f->fmt.pix.width; + isp_sink_crop.height = f->fmt.pix.height; + } + + atomisp_subdev_set_selection(&asd->subdev, fh.pad, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK, + V4L2_SEL_TGT_CROP, + V4L2_SEL_FLAG_KEEP_CONFIG, + &isp_sink_crop); + atomisp_subdev_set_selection(&asd->subdev, fh.pad, + V4L2_SUBDEV_FORMAT_ACTIVE, + source_pad, V4L2_SEL_TGT_COMPOSE, + 0, &isp_sink_crop); + } else if (IS_MOFD) { + struct v4l2_rect main_compose = {0}; + + main_compose.width = isp_sink_crop.width; + main_compose.height = + DIV_ROUND_UP(main_compose.width * f->fmt.pix.height, + f->fmt.pix.width); + if (main_compose.height > isp_sink_crop.height) { + main_compose.height = isp_sink_crop.height; + main_compose.width = + DIV_ROUND_UP(main_compose.height * + f->fmt.pix.width, + f->fmt.pix.height); + } + + atomisp_subdev_set_selection(&asd->subdev, fh.pad, + V4L2_SUBDEV_FORMAT_ACTIVE, + source_pad, + V4L2_SEL_TGT_COMPOSE, 0, + &main_compose); + } else { + struct v4l2_rect sink_crop = {0}; + struct v4l2_rect main_compose = {0}; + + main_compose.width = f->fmt.pix.width; + main_compose.height = f->fmt.pix.height; + +#ifndef ISP2401 + /* WORKAROUND: this override is universally enabled in + * GMIN to work around a CTS failures (GMINL-539) + * which appears to be related by a hardware + * performance limitation. It's unclear why this + * particular code triggers the issue. */ + if (1 || + crop_needs_override) { +#else + if (crop_needs_override) { +#endif + if (isp_sink_crop.width * main_compose.height > + isp_sink_crop.height * main_compose.width) { + sink_crop.height = isp_sink_crop.height; + sink_crop.width = DIV_NEAREST_STEP( + sink_crop.height * + f->fmt.pix.width, + f->fmt.pix.height, + ATOM_ISP_STEP_WIDTH); + } else { + sink_crop.width = isp_sink_crop.width; + sink_crop.height = DIV_NEAREST_STEP( + sink_crop.width * + f->fmt.pix.height, + f->fmt.pix.width, + ATOM_ISP_STEP_HEIGHT); + } + atomisp_subdev_set_selection(&asd->subdev, fh.pad, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK, + V4L2_SEL_TGT_CROP, + V4L2_SEL_FLAG_KEEP_CONFIG, + &sink_crop); + } + atomisp_subdev_set_selection(&asd->subdev, fh.pad, + V4L2_SUBDEV_FORMAT_ACTIVE, + source_pad, + V4L2_SEL_TGT_COMPOSE, 0, + &main_compose); + } + +set_fmt_to_isp: + ret = atomisp_set_fmt_to_isp(vdev, &output_info, &raw_output_info, + &f->fmt.pix, source_pad); + if (ret) + return -EINVAL; +done: + pipe->pix.width = f->fmt.pix.width; + pipe->pix.height = f->fmt.pix.height; + pipe->pix.pixelformat = f->fmt.pix.pixelformat; + if (format_bridge->planar) { + pipe->pix.bytesperline = output_info.padded_width; + pipe->pix.sizeimage = PAGE_ALIGN(f->fmt.pix.height * + DIV_ROUND_UP(format_bridge->depth * + output_info.padded_width, 8)); + } else { + pipe->pix.bytesperline = + DIV_ROUND_UP(format_bridge->depth * + output_info.padded_width, 8); + pipe->pix.sizeimage = + PAGE_ALIGN(f->fmt.pix.height * pipe->pix.bytesperline); + + } + if (f->fmt.pix.field == V4L2_FIELD_ANY) + f->fmt.pix.field = V4L2_FIELD_NONE; + pipe->pix.field = f->fmt.pix.field; + + f->fmt.pix = pipe->pix; + f->fmt.pix.priv = PAGE_ALIGN(pipe->pix.width * + pipe->pix.height * 2); + + pipe->capq.field = f->fmt.pix.field; + + /* + * If in video 480P case, no GFX throttle + */ + if (asd->run_mode->val == ATOMISP_SUBDEV_PAD_SOURCE_VIDEO && + f->fmt.pix.width == 720 && f->fmt.pix.height == 480) + isp->need_gfx_throttle = false; + else + isp->need_gfx_throttle = true; + + return 0; +} + +int atomisp_set_fmt_file(struct video_device *vdev, struct v4l2_format *f) +{ + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + struct atomisp_sub_device *asd = pipe->asd; + struct v4l2_mbus_framefmt ffmt = {0}; + const struct atomisp_format_bridge *format_bridge; + struct v4l2_subdev_fh fh; + int ret; + + v4l2_fh_init(&fh.vfh, vdev); + + dev_dbg(isp->dev, "setting fmt %ux%u 0x%x for file inject\n", + f->fmt.pix.width, f->fmt.pix.height, f->fmt.pix.pixelformat); + ret = atomisp_try_fmt_file(isp, f); + if (ret) { + dev_err(isp->dev, "atomisp_try_fmt_file err: %d\n", ret); + return ret; + } + + format_bridge = atomisp_get_format_bridge(f->fmt.pix.pixelformat); + if (format_bridge == NULL) { + dev_dbg(isp->dev, "atomisp_get_format_bridge err! fmt:0x%x\n", + f->fmt.pix.pixelformat); + return -EINVAL; + } + + pipe->pix = f->fmt.pix; + atomisp_css_input_set_mode(asd, CSS_INPUT_MODE_FIFO); + atomisp_css_input_configure_port(asd, + __get_mipi_port(isp, ATOMISP_CAMERA_PORT_PRIMARY), 2, 0xffff4, + 0, 0, 0, 0); + ffmt.width = f->fmt.pix.width; + ffmt.height = f->fmt.pix.height; + ffmt.code = format_bridge->mbus_code; + + atomisp_subdev_set_ffmt(&asd->subdev, fh.pad, V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK, &ffmt); + + return 0; +} + +int atomisp_set_shading_table(struct atomisp_sub_device *asd, + struct atomisp_shading_table *user_shading_table) +{ + struct atomisp_css_shading_table *shading_table; + struct atomisp_css_shading_table *free_table; + unsigned int len_table; + int i; + int ret = 0; + + if (!user_shading_table) + return -EINVAL; + + if (!user_shading_table->enable) { + atomisp_css_set_shading_table(asd, NULL); + asd->params.sc_en = 0; + return 0; + } + + /* If enabling, all tables must be set */ + for (i = 0; i < ATOMISP_NUM_SC_COLORS; i++) { + if (!user_shading_table->data[i]) + return -EINVAL; + } + + /* Shading table size per color */ + if (user_shading_table->width > SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR || + user_shading_table->height > SH_CSS_MAX_SCTBL_HEIGHT_PER_COLOR) + return -EINVAL; + + shading_table = atomisp_css_shading_table_alloc( + user_shading_table->width, user_shading_table->height); + if (!shading_table) + return -ENOMEM; + + len_table = user_shading_table->width * user_shading_table->height * + ATOMISP_SC_TYPE_SIZE; + for (i = 0; i < ATOMISP_NUM_SC_COLORS; i++) { + ret = copy_from_user(shading_table->data[i], + user_shading_table->data[i], len_table); + if (ret) { + free_table = shading_table; + ret = -EFAULT; + goto out; + } + } + shading_table->sensor_width = user_shading_table->sensor_width; + shading_table->sensor_height = user_shading_table->sensor_height; + shading_table->fraction_bits = user_shading_table->fraction_bits; + + free_table = asd->params.css_param.shading_table; + asd->params.css_param.shading_table = shading_table; + atomisp_css_set_shading_table(asd, shading_table); + asd->params.sc_en = 1; + +out: + if (free_table != NULL) + atomisp_css_shading_table_free(free_table); + + return ret; +} + +/*Turn off ISP dphy */ +int atomisp_ospm_dphy_down(struct atomisp_device *isp) +{ + unsigned long flags; + u32 reg; + + dev_dbg(isp->dev, "%s\n", __func__); + + /* if ISP timeout, we can force powerdown */ + if (isp->isp_timeout) + goto done; + + if (!atomisp_dev_users(isp)) + goto done; + + spin_lock_irqsave(&isp->lock, flags); + isp->sw_contex.power_state = ATOM_ISP_POWER_DOWN; + spin_unlock_irqrestore(&isp->lock, flags); +done: + /* + * MRFLD IUNIT DPHY is located in an always-power-on island + * MRFLD HW design need all CSI ports are disabled before + * powering down the IUNIT. + */ + pci_read_config_dword(isp->pdev, MRFLD_PCI_CSI_CONTROL, ®); + reg |= MRFLD_ALL_CSI_PORTS_OFF_MASK; + pci_write_config_dword(isp->pdev, MRFLD_PCI_CSI_CONTROL, reg); + return 0; +} + +/*Turn on ISP dphy */ +int atomisp_ospm_dphy_up(struct atomisp_device *isp) +{ + unsigned long flags; + dev_dbg(isp->dev, "%s\n", __func__); + + spin_lock_irqsave(&isp->lock, flags); + isp->sw_contex.power_state = ATOM_ISP_POWER_UP; + spin_unlock_irqrestore(&isp->lock, flags); + + return 0; +} + + +int atomisp_exif_makernote(struct atomisp_sub_device *asd, + struct atomisp_makernote_info *config) +{ + struct v4l2_control ctrl; + struct atomisp_device *isp = asd->isp; + + ctrl.id = V4L2_CID_FOCAL_ABSOLUTE; + if (v4l2_g_ctrl + (isp->inputs[asd->input_curr].camera->ctrl_handler, &ctrl)) { + dev_warn(isp->dev, "failed to g_ctrl for focal length\n"); + return -EINVAL; + } else { + config->focal_length = ctrl.value; + } + + ctrl.id = V4L2_CID_FNUMBER_ABSOLUTE; + if (v4l2_g_ctrl + (isp->inputs[asd->input_curr].camera->ctrl_handler, &ctrl)) { + dev_warn(isp->dev, "failed to g_ctrl for f-number\n"); + return -EINVAL; + } else { + config->f_number_curr = ctrl.value; + } + + ctrl.id = V4L2_CID_FNUMBER_RANGE; + if (v4l2_g_ctrl + (isp->inputs[asd->input_curr].camera->ctrl_handler, &ctrl)) { + dev_warn(isp->dev, "failed to g_ctrl for f number range\n"); + return -EINVAL; + } else { + config->f_number_range = ctrl.value; + } + + return 0; +} + +int atomisp_offline_capture_configure(struct atomisp_sub_device *asd, + struct atomisp_cont_capture_conf *cvf_config) +{ + struct v4l2_ctrl *c; + + /* + * In case of M10MO ZSL capture case, we need to issue a separate + * capture request to M10MO which will output captured jpeg image + */ + c = v4l2_ctrl_find( + asd->isp->inputs[asd->input_curr].camera->ctrl_handler, + V4L2_CID_START_ZSL_CAPTURE); + if (c) { + int ret; + dev_dbg(asd->isp->dev, "%s trigger ZSL capture request\n", + __func__); + /* TODO: use the cvf_config */ + ret = v4l2_ctrl_s_ctrl(c, 1); + if (ret) + return ret; + + return v4l2_ctrl_s_ctrl(c, 0); + } + + asd->params.offline_parm = *cvf_config; + + if (asd->params.offline_parm.num_captures) { + if (asd->streaming == ATOMISP_DEVICE_STREAMING_DISABLED) { + unsigned int init_raw_num; + + if (asd->enable_raw_buffer_lock->val) { + init_raw_num = + ATOMISP_CSS2_NUM_OFFLINE_INIT_CONTINUOUS_FRAMES_LOCK_EN; + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO && + asd->params.video_dis_en) + init_raw_num += + ATOMISP_CSS2_NUM_DVS_FRAME_DELAY; + } else { + init_raw_num = + ATOMISP_CSS2_NUM_OFFLINE_INIT_CONTINUOUS_FRAMES; + } + + /* TODO: this can be removed once user-space + * has been updated to use control API */ + asd->continuous_raw_buffer_size->val = + max_t(int, + asd->continuous_raw_buffer_size->val, + asd->params.offline_parm. + num_captures + init_raw_num); + asd->continuous_raw_buffer_size->val = + min_t(int, ATOMISP_CONT_RAW_FRAMES, + asd->continuous_raw_buffer_size->val); + } + asd->continuous_mode->val = true; + } else { + asd->continuous_mode->val = false; + __enable_continuous_mode(asd, false); + } + + return 0; +} + +/* + * set auto exposure metering window to camera sensor + */ +int atomisp_s_ae_window(struct atomisp_sub_device *asd, + struct atomisp_ae_window *arg) +{ + struct atomisp_device *isp = asd->isp; +#ifndef ISP2401 + /* Coverity CID 298071 - initialzize struct */ +#endif + struct v4l2_subdev_selection sel = { 0 }; + + sel.r.left = arg->x_left; + sel.r.top = arg->y_top; + sel.r.width = arg->x_right - arg->x_left + 1; + sel.r.height = arg->y_bottom - arg->y_top + 1; + + if (v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + pad, set_selection, NULL, &sel)) { + dev_err(isp->dev, "failed to call sensor set_selection.\n"); + return -EINVAL; + } + + return 0; +} + +int atomisp_flash_enable(struct atomisp_sub_device *asd, int num_frames) +{ + struct atomisp_device *isp = asd->isp; + + if (num_frames < 0) { + dev_dbg(isp->dev, "%s ERROR: num_frames: %d\n", __func__, + num_frames); + return -EINVAL; + } + /* a requested flash is still in progress. */ + if (num_frames && asd->params.flash_state != ATOMISP_FLASH_IDLE) { + dev_dbg(isp->dev, "%s flash busy: %d frames left: %d\n", + __func__, asd->params.flash_state, + asd->params.num_flash_frames); + return -EBUSY; + } + + asd->params.num_flash_frames = num_frames; + asd->params.flash_state = ATOMISP_FLASH_REQUESTED; + return 0; +} + +int atomisp_source_pad_to_stream_id(struct atomisp_sub_device *asd, + uint16_t source_pad) +{ + int stream_id; + struct atomisp_device *isp = asd->isp; + + if (isp->inputs[asd->input_curr].camera_caps-> + sensor[asd->sensor_curr].stream_num == 1) + return ATOMISP_INPUT_STREAM_GENERAL; + + switch (source_pad) { + case ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE: + stream_id = ATOMISP_INPUT_STREAM_CAPTURE; + break; + case ATOMISP_SUBDEV_PAD_SOURCE_VF: + stream_id = ATOMISP_INPUT_STREAM_POSTVIEW; + break; + case ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW: + stream_id = ATOMISP_INPUT_STREAM_PREVIEW; + break; + case ATOMISP_SUBDEV_PAD_SOURCE_VIDEO: + stream_id = ATOMISP_INPUT_STREAM_VIDEO; + break; + default: + stream_id = ATOMISP_INPUT_STREAM_GENERAL; + } + + return stream_id; +} + +bool atomisp_is_vf_pipe(struct atomisp_video_pipe *pipe) +{ + struct atomisp_sub_device *asd = pipe->asd; + + if (pipe == &asd->video_out_vf) + return true; + + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO && + pipe == &asd->video_out_preview) + return true; + + return false; +} + +static int __checking_exp_id(struct atomisp_sub_device *asd, int exp_id) +{ + struct atomisp_device *isp = asd->isp; + + if (!asd->enable_raw_buffer_lock->val) { + dev_warn(isp->dev, "%s Raw Buffer Lock is disable.\n", __func__); + return -EINVAL; + } + if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED) { + dev_err(isp->dev, "%s streaming %d invalid exp_id %d.\n", + __func__, exp_id, asd->streaming); + return -EINVAL; + } + if ((exp_id > ATOMISP_MAX_EXP_ID) || (exp_id <= 0)) { + dev_err(isp->dev, "%s exp_id %d invalid.\n", __func__, exp_id); + return -EINVAL; + } + return 0; +} + +void atomisp_init_raw_buffer_bitmap(struct atomisp_sub_device *asd) +{ + unsigned long flags; + spin_lock_irqsave(&asd->raw_buffer_bitmap_lock, flags); + memset(asd->raw_buffer_bitmap, 0, sizeof(asd->raw_buffer_bitmap)); + asd->raw_buffer_locked_count = 0; + spin_unlock_irqrestore(&asd->raw_buffer_bitmap_lock, flags); +} + +int atomisp_set_raw_buffer_bitmap(struct atomisp_sub_device *asd, int exp_id) +{ + int *bitmap, bit; + unsigned long flags; + + if (__checking_exp_id(asd, exp_id)) + return -EINVAL; + + bitmap = asd->raw_buffer_bitmap + exp_id / 32; + bit = exp_id % 32; + spin_lock_irqsave(&asd->raw_buffer_bitmap_lock, flags); + (*bitmap) |= (1 << bit); + asd->raw_buffer_locked_count++; + spin_unlock_irqrestore(&asd->raw_buffer_bitmap_lock, flags); + + dev_dbg(asd->isp->dev, "%s: exp_id %d, raw_buffer_locked_count %d\n", + __func__, exp_id, asd->raw_buffer_locked_count); + + /* Check if the raw buffer after next is still locked!!! */ + exp_id += 2; + if (exp_id > ATOMISP_MAX_EXP_ID) + exp_id -= ATOMISP_MAX_EXP_ID; + bitmap = asd->raw_buffer_bitmap + exp_id / 32; + bit = exp_id % 32; + if ((*bitmap) & (1 << bit)) { + int ret; + + /* WORKAROUND unlock the raw buffer compulsively */ + ret = atomisp_css_exp_id_unlock(asd, exp_id); + if (ret) { + dev_err(asd->isp->dev, "%s exp_id is wrapping back to %d but force unlock failed,, err %d.\n", + __func__, exp_id, ret); + return ret; + } + + spin_lock_irqsave(&asd->raw_buffer_bitmap_lock, flags); + (*bitmap) &= ~(1 << bit); + asd->raw_buffer_locked_count--; + spin_unlock_irqrestore(&asd->raw_buffer_bitmap_lock, flags); + dev_warn(asd->isp->dev, "%s exp_id is wrapping back to %d but it is still locked so force unlock it, raw_buffer_locked_count %d\n", + __func__, exp_id, asd->raw_buffer_locked_count); + } + return 0; +} + +static int __is_raw_buffer_locked(struct atomisp_sub_device *asd, int exp_id) +{ + int *bitmap, bit; + unsigned long flags; + int ret; + + if (__checking_exp_id(asd, exp_id)) + return -EINVAL; + + bitmap = asd->raw_buffer_bitmap + exp_id / 32; + bit = exp_id % 32; + spin_lock_irqsave(&asd->raw_buffer_bitmap_lock, flags); + ret = ((*bitmap) & (1 << bit)); + spin_unlock_irqrestore(&asd->raw_buffer_bitmap_lock, flags); + return !ret; +} + +static int __clear_raw_buffer_bitmap(struct atomisp_sub_device *asd, int exp_id) +{ + int *bitmap, bit; + unsigned long flags; + + if (__is_raw_buffer_locked(asd, exp_id)) + return -EINVAL; + + bitmap = asd->raw_buffer_bitmap + exp_id / 32; + bit = exp_id % 32; + spin_lock_irqsave(&asd->raw_buffer_bitmap_lock, flags); + (*bitmap) &= ~(1 << bit); + asd->raw_buffer_locked_count--; + spin_unlock_irqrestore(&asd->raw_buffer_bitmap_lock, flags); + + dev_dbg(asd->isp->dev, "%s: exp_id %d, raw_buffer_locked_count %d\n", + __func__, exp_id, asd->raw_buffer_locked_count); + return 0; +} + +int atomisp_exp_id_capture(struct atomisp_sub_device *asd, int *exp_id) +{ + struct atomisp_device *isp = asd->isp; + int value = *exp_id; + int ret; + + ret = __is_raw_buffer_locked(asd, value); + if (ret) { + dev_err(isp->dev, "%s exp_id %d invalid %d.\n", __func__, value, ret); + return -EINVAL; + } + + dev_dbg(isp->dev, "%s exp_id %d\n", __func__, value); + ret = atomisp_css_exp_id_capture(asd, value); + if (ret) { + dev_err(isp->dev, "%s exp_id %d failed.\n", __func__, value); + return -EIO; + } + return 0; +} + +int atomisp_exp_id_unlock(struct atomisp_sub_device *asd, int *exp_id) +{ + struct atomisp_device *isp = asd->isp; + int value = *exp_id; + int ret; + + ret = __clear_raw_buffer_bitmap(asd, value); + if (ret) { + dev_err(isp->dev, "%s exp_id %d invalid %d.\n", __func__, value, ret); + return -EINVAL; + } + + dev_dbg(isp->dev, "%s exp_id %d\n", __func__, value); + ret = atomisp_css_exp_id_unlock(asd, value); + if (ret) + dev_err(isp->dev, "%s exp_id %d failed, err %d.\n", + __func__, value, ret); + + return ret; +} + +int atomisp_enable_dz_capt_pipe(struct atomisp_sub_device *asd, + unsigned int *enable) +{ + bool value; + + if (enable == NULL) + return -EINVAL; + + value = *enable > 0 ? true : false; + + atomisp_en_dz_capt_pipe(asd, value); + + return 0; +} + +int atomisp_inject_a_fake_event(struct atomisp_sub_device *asd, int *event) +{ + if (!event || asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED) + return -EINVAL; + + dev_dbg(asd->isp->dev, "%s: trying to inject a fake event 0x%x\n", + __func__, *event); + + switch (*event) { + case V4L2_EVENT_FRAME_SYNC: + atomisp_sof_event(asd); + break; + case V4L2_EVENT_FRAME_END: + atomisp_eof_event(asd, 0); + break; + case V4L2_EVENT_ATOMISP_3A_STATS_READY: + atomisp_3a_stats_ready_event(asd, 0); + break; + case V4L2_EVENT_ATOMISP_METADATA_READY: + atomisp_metadata_ready_event(asd, 0); + break; + default: + return -EINVAL; + } + + return 0; +} + +int atomisp_get_pipe_id(struct atomisp_video_pipe *pipe) +{ + struct atomisp_sub_device *asd = pipe->asd; + + if (ATOMISP_USE_YUVPP(asd)) + return CSS_PIPE_ID_YUVPP; + else if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_SCALER) + return CSS_PIPE_ID_VIDEO; + else if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_LOWLAT) + return CSS_PIPE_ID_CAPTURE; + else if (pipe == &asd->video_out_video_capture) + return CSS_PIPE_ID_VIDEO; + else if (pipe == &asd->video_out_vf) + return CSS_PIPE_ID_CAPTURE; + else if (pipe == &asd->video_out_preview) { + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) + return CSS_PIPE_ID_VIDEO; + else + return CSS_PIPE_ID_PREVIEW; + } else if (pipe == &asd->video_out_capture) { + if (asd->copy_mode) + return IA_CSS_PIPE_ID_COPY; + else + return CSS_PIPE_ID_CAPTURE; + } + + /* fail through */ + dev_warn(asd->isp->dev, "%s failed to find proper pipe\n", + __func__); + return CSS_PIPE_ID_CAPTURE; +} + +int atomisp_get_invalid_frame_num(struct video_device *vdev, + int *invalid_frame_num) +{ + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + struct atomisp_sub_device *asd = pipe->asd; + enum atomisp_css_pipe_id pipe_id; + struct ia_css_pipe_info p_info; + int ret; + + if (asd->isp->inputs[asd->input_curr].camera_caps-> + sensor[asd->sensor_curr].stream_num > 1) { + /* External ISP */ + *invalid_frame_num = 0; + return 0; + } + + pipe_id = atomisp_get_pipe_id(pipe); + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].pipes[pipe_id]) { + dev_warn(asd->isp->dev, "%s pipe %d has not been created yet, do SET_FMT first!\n", + __func__, pipe_id); + return -EINVAL; + } + + ret = ia_css_pipe_get_info( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .pipes[pipe_id], &p_info); + if (ret == IA_CSS_SUCCESS) { + *invalid_frame_num = p_info.num_invalid_frames; + return 0; + } else { + dev_warn(asd->isp->dev, "%s get pipe infor failed %d\n", + __func__, ret); + return -EINVAL; + } +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_cmd.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_cmd.h new file mode 100644 index 0000000000000000000000000000000000000000..abca5cc58dac2db36df54e31ea67e4f3b09f32a8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_cmd.h @@ -0,0 +1,457 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __ATOMISP_CMD_H__ +#define __ATOMISP_CMD_H__ + +#include +#include +#include + +#include + +#include "atomisp_internal.h" + +#include "ia_css_types.h" +#include "ia_css.h" + +struct atomisp_device; +struct atomisp_css_frame; + +#define MSI_ENABLE_BIT 16 +#define INTR_DISABLE_BIT 10 +#define BUS_MASTER_ENABLE 2 +#define MEMORY_SPACE_ENABLE 1 +#define INTR_IER 24 +#define INTR_IIR 16 +#ifdef ISP2401 +#define RUNMODE_MASK (ATOMISP_RUN_MODE_VIDEO | ATOMISP_RUN_MODE_STILL_CAPTURE \ + | ATOMISP_RUN_MODE_PREVIEW) + +/* FIXME: check if can go */ +extern int atomisp_punit_hpll_freq; +#endif + +/* + * Helper function + */ +void dump_sp_dmem(struct atomisp_device *isp, unsigned int addr, + unsigned int size); +struct camera_mipi_info *atomisp_to_sensor_mipi_info(struct v4l2_subdev *sd); +struct atomisp_video_pipe *atomisp_to_video_pipe(struct video_device *dev); +struct atomisp_acc_pipe *atomisp_to_acc_pipe(struct video_device *dev); +int atomisp_reset(struct atomisp_device *isp); +void atomisp_flush_bufs_and_wakeup(struct atomisp_sub_device *asd); +void atomisp_clear_css_buffer_counters(struct atomisp_sub_device *asd); +#ifndef ISP2401 +bool atomisp_buffers_queued(struct atomisp_sub_device *asd); +#else +bool atomisp_buffers_queued_pipe(struct atomisp_video_pipe *pipe); +#endif + +/* TODO:should be here instead of atomisp_helper.h +extern void __iomem *atomisp_io_base; + +static inline void __iomem *atomisp_get_io_virt_addr(unsigned int address) +{ + void __iomem *ret = atomisp_io_base + (address & 0x003FFFFF); + return ret; +} +*/ +void *atomisp_kernel_malloc(size_t bytes); +void *atomisp_kernel_zalloc(size_t bytes, bool zero_mem); +void atomisp_kernel_free(void *ptr); + +/* + * Interrupt functions + */ +void atomisp_msi_irq_init(struct atomisp_device *isp, struct pci_dev *dev); +void atomisp_msi_irq_uninit(struct atomisp_device *isp, struct pci_dev *dev); +void atomisp_wdt_work(struct work_struct *work); +#ifndef ISP2401 +void atomisp_wdt(unsigned long isp_addr); +#else +void atomisp_wdt(unsigned long pipe_addr); +#endif +void atomisp_setup_flash(struct atomisp_sub_device *asd); +irqreturn_t atomisp_isr(int irq, void *dev); +irqreturn_t atomisp_isr_thread(int irq, void *isp_ptr); +const struct atomisp_format_bridge *get_atomisp_format_bridge_from_mbus( + u32 mbus_code); +bool atomisp_is_mbuscode_raw(uint32_t code); +int atomisp_get_frame_pgnr(struct atomisp_device *isp, + const struct atomisp_css_frame *frame, u32 *p_pgnr); +void atomisp_delayed_init_work(struct work_struct *work); + +/* + * Get internal fmt according to V4L2 fmt + */ + +bool atomisp_is_viewfinder_support(struct atomisp_device *isp); + +/* + * ISP features control function + */ + +/* +#ifdef ISP2401 + * Function to set sensor runmode by user when + * ATOMISP_IOC_S_SENSOR_RUNMODE ioctl was called + */ +int atomisp_set_sensor_runmode(struct atomisp_sub_device *asd, + struct atomisp_s_runmode *runmode); +/* +#endif + * Function to enable/disable lens geometry distortion correction (GDC) and + * chromatic aberration correction (CAC) + */ +int atomisp_gdc_cac(struct atomisp_sub_device *asd, int flag, + __s32 *value); + +/* + * Function to enable/disable low light mode (including ANR) + */ +int atomisp_low_light(struct atomisp_sub_device *asd, int flag, + __s32 *value); + +/* + * Function to enable/disable extra noise reduction (XNR) in low light + * condition + */ +int atomisp_xnr(struct atomisp_sub_device *asd, int flag, int *arg); + +int atomisp_formats(struct atomisp_sub_device *asd, int flag, + struct atomisp_formats_config *config); + +/* + * Function to configure noise reduction + */ +int atomisp_nr(struct atomisp_sub_device *asd, int flag, + struct atomisp_nr_config *config); + +/* + * Function to configure temporal noise reduction (TNR) + */ +int atomisp_tnr(struct atomisp_sub_device *asd, int flag, + struct atomisp_tnr_config *config); + +/* + * Function to configure black level compensation + */ +int atomisp_black_level(struct atomisp_sub_device *asd, int flag, + struct atomisp_ob_config *config); + +/* + * Function to configure edge enhancement + */ +int atomisp_ee(struct atomisp_sub_device *asd, int flag, + struct atomisp_ee_config *config); + +/* + * Function to update Gamma table for gamma, brightness and contrast config + */ +int atomisp_gamma(struct atomisp_sub_device *asd, int flag, + struct atomisp_gamma_table *config); +/* + * Function to update Ctc table for Chroma Enhancement + */ +int atomisp_ctc(struct atomisp_sub_device *asd, int flag, + struct atomisp_ctc_table *config); + +/* + * Function to update gamma correction parameters + */ +int atomisp_gamma_correction(struct atomisp_sub_device *asd, int flag, + struct atomisp_gc_config *config); + +/* + * Function to update Gdc table for gdc + */ +int atomisp_gdc_cac_table(struct atomisp_sub_device *asd, int flag, + struct atomisp_morph_table *config); + +/* + * Function to update table for macc + */ +int atomisp_macc_table(struct atomisp_sub_device *asd, int flag, + struct atomisp_macc_config *config); +/* + * Function to get DIS statistics. + */ +int atomisp_get_dis_stat(struct atomisp_sub_device *asd, + struct atomisp_dis_statistics *stats); + +/* + * Function to get DVS2 BQ resolution settings + */ +int atomisp_get_dvs2_bq_resolutions(struct atomisp_sub_device *asd, + struct atomisp_dvs2_bq_resolutions *bq_res); + +/* + * Function to set the DIS coefficients. + */ +int atomisp_set_dis_coefs(struct atomisp_sub_device *asd, + struct atomisp_dis_coefficients *coefs); + +/* + * Function to set the DIS motion vector. + */ +int atomisp_set_dis_vector(struct atomisp_sub_device *asd, + struct atomisp_dis_vector *vector); + +/* + * Function to set/get 3A stat from isp + */ +int atomisp_3a_stat(struct atomisp_sub_device *asd, int flag, + struct atomisp_3a_statistics *config); + +/* + * Function to get metadata from isp + */ +int atomisp_get_metadata(struct atomisp_sub_device *asd, int flag, + struct atomisp_metadata *config); + +int atomisp_get_metadata_by_type(struct atomisp_sub_device *asd, int flag, + struct atomisp_metadata_with_type *config); + +int atomisp_set_parameters(struct video_device *vdev, + struct atomisp_parameters *arg); +/* + * Function to set/get isp parameters to isp + */ +int atomisp_param(struct atomisp_sub_device *asd, int flag, + struct atomisp_parm *config); + +/* + * Function to configure color effect of the image + */ +int atomisp_color_effect(struct atomisp_sub_device *asd, int flag, + __s32 *effect); + +/* + * Function to configure bad pixel correction + */ +int atomisp_bad_pixel(struct atomisp_sub_device *asd, int flag, + __s32 *value); + +/* + * Function to configure bad pixel correction params + */ +int atomisp_bad_pixel_param(struct atomisp_sub_device *asd, int flag, + struct atomisp_dp_config *config); + +/* + * Function to enable/disable video image stablization + */ +int atomisp_video_stable(struct atomisp_sub_device *asd, int flag, + __s32 *value); + +/* + * Function to configure fixed pattern noise + */ +int atomisp_fixed_pattern(struct atomisp_sub_device *asd, int flag, + __s32 *value); + +/* + * Function to configure fixed pattern noise table + */ +int atomisp_fixed_pattern_table(struct atomisp_sub_device *asd, + struct v4l2_framebuffer *config); + +/* + * Function to configure false color correction + */ +int atomisp_false_color(struct atomisp_sub_device *asd, int flag, + __s32 *value); + +/* + * Function to configure false color correction params + */ +int atomisp_false_color_param(struct atomisp_sub_device *asd, int flag, + struct atomisp_de_config *config); + +/* + * Function to configure white balance params + */ +int atomisp_white_balance_param(struct atomisp_sub_device *asd, int flag, + struct atomisp_wb_config *config); + +int atomisp_3a_config_param(struct atomisp_sub_device *asd, int flag, + struct atomisp_3a_config *config); + +/* + * Function to setup digital zoom + */ +int atomisp_digital_zoom(struct atomisp_sub_device *asd, int flag, + __s32 *value); + +/* + * Function set camera_prefiles.xml current sensor pixel array size + */ +int atomisp_set_array_res(struct atomisp_sub_device *asd, + struct atomisp_resolution *config); + +/* + * Function to calculate real zoom region for every pipe + */ +int atomisp_calculate_real_zoom_region(struct atomisp_sub_device *asd, + struct atomisp_css_dz_config *dz_config, + enum atomisp_css_pipe_id css_pipe_id); + +int atomisp_cp_general_isp_parameters(struct atomisp_sub_device *asd, + struct atomisp_parameters *arg, + struct atomisp_css_params *css_param, + bool from_user); + +int atomisp_cp_lsc_table(struct atomisp_sub_device *asd, + struct atomisp_shading_table *source_st, + struct atomisp_css_params *css_param, + bool from_user); + +int atomisp_css_cp_dvs2_coefs(struct atomisp_sub_device *asd, + struct ia_css_dvs2_coefficients *coefs, + struct atomisp_css_params *css_param, + bool from_user); + +int atomisp_cp_morph_table(struct atomisp_sub_device *asd, + struct atomisp_morph_table *source_morph_table, + struct atomisp_css_params *css_param, + bool from_user); + +int atomisp_cp_dvs_6axis_config(struct atomisp_sub_device *asd, + struct atomisp_dvs_6axis_config *user_6axis_config, + struct atomisp_css_params *css_param, + bool from_user); + +int atomisp_makeup_css_parameters(struct atomisp_sub_device *asd, + struct atomisp_parameters *arg, + struct atomisp_css_params *css_param); + +int atomisp_compare_grid(struct atomisp_sub_device *asd, + struct atomisp_grid_info *atomgrid); + +int atomisp_get_sensor_mode_data(struct atomisp_sub_device *asd, + struct atomisp_sensor_mode_data *config); + +int atomisp_get_fmt(struct video_device *vdev, struct v4l2_format *f); + + +/* This function looks up the closest available resolution. */ +int atomisp_try_fmt(struct video_device *vdev, struct v4l2_format *f, + bool *res_overflow); + +int atomisp_set_fmt(struct video_device *vdev, struct v4l2_format *f); +int atomisp_set_fmt_file(struct video_device *vdev, struct v4l2_format *f); + +int atomisp_set_shading_table(struct atomisp_sub_device *asd, + struct atomisp_shading_table *shading_table); + +int atomisp_offline_capture_configure(struct atomisp_sub_device *asd, + struct atomisp_cont_capture_conf *cvf_config); + +int atomisp_ospm_dphy_down(struct atomisp_device *isp); +int atomisp_ospm_dphy_up(struct atomisp_device *isp); +int atomisp_exif_makernote(struct atomisp_sub_device *asd, + struct atomisp_makernote_info *config); + +void atomisp_free_internal_buffers(struct atomisp_sub_device *asd); + +int atomisp_s_ae_window(struct atomisp_sub_device *asd, + struct atomisp_ae_window *arg); + +int atomisp_flash_enable(struct atomisp_sub_device *asd, + int num_frames); + +int atomisp_freq_scaling(struct atomisp_device *vdev, + enum atomisp_dfs_mode mode, + bool force); + +void atomisp_buf_done(struct atomisp_sub_device *asd, int error, + enum atomisp_css_buffer_type buf_type, + enum atomisp_css_pipe_id css_pipe_id, + bool q_buffers, enum atomisp_input_stream_id stream_id); + +void atomisp_css_flush(struct atomisp_device *isp); +int atomisp_source_pad_to_stream_id(struct atomisp_sub_device *asd, + uint16_t source_pad); + +/* + * Events. Only one event has to be exported for now. + */ +void atomisp_eof_event(struct atomisp_sub_device *asd, uint8_t exp_id); + +mipi_port_ID_t __get_mipi_port(struct atomisp_device *isp, + enum atomisp_camera_port port); + +bool atomisp_is_vf_pipe(struct atomisp_video_pipe *pipe); + +void atomisp_apply_css_parameters( + struct atomisp_sub_device *asd, + struct atomisp_css_params *css_param); +void atomisp_free_css_parameters(struct atomisp_css_params *css_param); + +void atomisp_handle_parameter_and_buffer(struct atomisp_video_pipe *pipe); + +void atomisp_flush_params_queue(struct atomisp_video_pipe *asd); +/* + * Function to do Raw Buffer related operation, after enable Lock Unlock Raw Buffer + */ +int atomisp_exp_id_unlock(struct atomisp_sub_device *asd, int *exp_id); +int atomisp_exp_id_capture(struct atomisp_sub_device *asd, int *exp_id); + +/* + * Function to update Raw Buffer bitmap + */ +int atomisp_set_raw_buffer_bitmap(struct atomisp_sub_device *asd, int exp_id); +void atomisp_init_raw_buffer_bitmap(struct atomisp_sub_device *asd); + +/* + * Function to enable/disable zoom for capture pipe + */ +int atomisp_enable_dz_capt_pipe(struct atomisp_sub_device *asd, + unsigned int *enable); + +/* + * Function to get metadata type bu pipe id + */ +enum atomisp_metadata_type +atomisp_get_metadata_type(struct atomisp_sub_device *asd, + enum ia_css_pipe_id pipe_id); + +/* + * Function for HAL to inject a fake event to wake up poll thread + */ +int atomisp_inject_a_fake_event(struct atomisp_sub_device *asd, int *event); + +/* + * Function for HAL to query how many invalid frames at the beginning of ISP + * pipeline output + */ +int atomisp_get_invalid_frame_num(struct video_device *vdev, + int *invalid_frame_num); + +int atomisp_mrfld_power_up(struct atomisp_device *isp); +int atomisp_mrfld_power_down(struct atomisp_device *isp); +int atomisp_runtime_suspend(struct device *dev); +int atomisp_runtime_resume(struct device *dev); +#endif /* __ATOMISP_CMD_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_common.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_common.h new file mode 100644 index 0000000000000000000000000000000000000000..3044e0ef65877d53f82bd4acffd1e82d02a4f8e5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_common.h @@ -0,0 +1,79 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __ATOMISP_COMMON_H__ +#define __ATOMISP_COMMON_H__ + +#include + +#include + +#include + +#include "atomisp_compat.h" + +#include "ia_css.h" + +extern int dbg_level; +extern int dbg_func; +extern int mipicsi_flag; +extern int pad_w; +extern int pad_h; + +#define CSS_DTRACE_VERBOSITY_LEVEL 5 /* Controls trace verbosity */ +#define CSS_DTRACE_VERBOSITY_TIMEOUT 9 /* Verbosity on ISP timeout */ +#define MRFLD_MAX_ZOOM_FACTOR 1024 +#ifdef ISP2401 +#define ATOMISP_CSS_ISP_PIPE_VERSION_2_2 0 +#define ATOMISP_CSS_ISP_PIPE_VERSION_2_7 1 +#endif + +#define IS_ISP2401(isp) \ + (((isp)->media_dev.hw_revision & ATOMISP_HW_REVISION_MASK) \ + >= (ATOMISP_HW_REVISION_ISP2401_LEGACY << ATOMISP_HW_REVISION_SHIFT)) + +struct atomisp_format_bridge { + unsigned int pixelformat; + unsigned int depth; + u32 mbus_code; + enum atomisp_css_frame_format sh_fmt; + unsigned char description[32]; /* the same as struct v4l2_fmtdesc */ + bool planar; +}; + +struct atomisp_fmt { + u32 pixelformat; + u32 depth; + u32 bytesperline; + u32 framesize; + u32 imagesize; + u32 width; + u32 height; + u32 bayer_order; +}; + +struct atomisp_buffer { + struct videobuf_buffer vb; +}; + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat.h new file mode 100644 index 0000000000000000000000000000000000000000..5a404e4bee43d1a7245599c99c30306848705eb7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat.h @@ -0,0 +1,669 @@ +/* + * Support for Clovertrail PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2012 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __ATOMISP_COMPAT_H__ +#define __ATOMISP_COMPAT_H__ + +#include "atomisp_compat_css20.h" + +#include +#include + +#define CSS_RX_IRQ_INFO_BUFFER_OVERRUN \ + CSS_ID(CSS_RX_IRQ_INFO_BUFFER_OVERRUN) +#define CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE \ + CSS_ID(CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE) +#define CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE \ + CSS_ID(CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE) +#define CSS_RX_IRQ_INFO_ECC_CORRECTED \ + CSS_ID(CSS_RX_IRQ_INFO_ECC_CORRECTED) +#define CSS_RX_IRQ_INFO_ERR_SOT \ + CSS_ID(CSS_RX_IRQ_INFO_ERR_SOT) +#define CSS_RX_IRQ_INFO_ERR_SOT_SYNC \ + CSS_ID(CSS_RX_IRQ_INFO_ERR_SOT_SYNC) +#define CSS_RX_IRQ_INFO_ERR_CONTROL \ + CSS_ID(CSS_RX_IRQ_INFO_ERR_CONTROL) +#define CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE \ + CSS_ID(CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE) +#define CSS_RX_IRQ_INFO_ERR_CRC \ + CSS_ID(CSS_RX_IRQ_INFO_ERR_CRC) +#define CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID \ + CSS_ID(CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID) +#define CSS_RX_IRQ_INFO_ERR_FRAME_SYNC \ + CSS_ID(CSS_RX_IRQ_INFO_ERR_FRAME_SYNC) +#define CSS_RX_IRQ_INFO_ERR_FRAME_DATA \ + CSS_ID(CSS_RX_IRQ_INFO_ERR_FRAME_DATA) +#define CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT \ + CSS_ID(CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT) +#define CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC \ + CSS_ID(CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC) +#define CSS_RX_IRQ_INFO_ERR_LINE_SYNC \ + CSS_ID(CSS_RX_IRQ_INFO_ERR_LINE_SYNC) +#define CSS_RX_IRQ_INFO_INIT_TIMEOUT \ + CSS_ID(CSS_RX_IRQ_INFO_INIT_TIMEOUT) + +#define CSS_IRQ_INFO_CSS_RECEIVER_SOF CSS_ID(CSS_IRQ_INFO_CSS_RECEIVER_SOF) +#define CSS_IRQ_INFO_CSS_RECEIVER_EOF CSS_ID(CSS_IRQ_INFO_CSS_RECEIVER_EOF) +#define CSS_IRQ_INFO_CSS_RECEIVER_FIFO_OVERFLOW \ + CSS_ID(CSS_IRQ_INFO_CSS_RECEIVER_FIFO_OVERFLOW) +#define CSS_EVENT_OUTPUT_FRAME_DONE CSS_EVENT(OUTPUT_FRAME_DONE) +#define CSS_EVENT_SEC_OUTPUT_FRAME_DONE CSS_EVENT(SECOND_OUTPUT_FRAME_DONE) +#define CSS_EVENT_VF_OUTPUT_FRAME_DONE CSS_EVENT(VF_OUTPUT_FRAME_DONE) +#define CSS_EVENT_SEC_VF_OUTPUT_FRAME_DONE CSS_EVENT(SECOND_VF_OUTPUT_FRAME_DONE) +#define CSS_EVENT_3A_STATISTICS_DONE CSS_EVENT(3A_STATISTICS_DONE) +#define CSS_EVENT_DIS_STATISTICS_DONE CSS_EVENT(DIS_STATISTICS_DONE) +#define CSS_EVENT_PIPELINE_DONE CSS_EVENT(PIPELINE_DONE) +#define CSS_EVENT_METADATA_DONE CSS_EVENT(METADATA_DONE) +#define CSS_EVENT_ACC_STAGE_COMPLETE CSS_EVENT(ACC_STAGE_COMPLETE) +#define CSS_EVENT_TIMER CSS_EVENT(TIMER) + +#define CSS_BUFFER_TYPE_METADATA CSS_ID(CSS_BUFFER_TYPE_METADATA) +#define CSS_BUFFER_TYPE_3A_STATISTICS CSS_ID(CSS_BUFFER_TYPE_3A_STATISTICS) +#define CSS_BUFFER_TYPE_DIS_STATISTICS CSS_ID(CSS_BUFFER_TYPE_DIS_STATISTICS) +#define CSS_BUFFER_TYPE_INPUT_FRAME CSS_ID(CSS_BUFFER_TYPE_INPUT_FRAME) +#define CSS_BUFFER_TYPE_OUTPUT_FRAME CSS_ID(CSS_BUFFER_TYPE_OUTPUT_FRAME) +#define CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME CSS_ID(CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME) +#define CSS_BUFFER_TYPE_VF_OUTPUT_FRAME CSS_ID(CSS_BUFFER_TYPE_VF_OUTPUT_FRAME) +#define CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME CSS_ID(CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME) +#define CSS_BUFFER_TYPE_RAW_OUTPUT_FRAME \ + CSS_ID(CSS_BUFFER_TYPE_RAW_OUTPUT_FRAME) + +#define CSS_FORMAT_RAW_8 CSS_FORMAT(RAW_8) +#define CSS_FORMAT_RAW_10 CSS_FORMAT(RAW_10) +#define CSS_FORMAT_RAW_12 CSS_FORMAT(RAW_12) +#define CSS_FORMAT_RAW_16 CSS_FORMAT(RAW_16) + +#define CSS_CAPTURE_MODE_RAW CSS_ID(CSS_CAPTURE_MODE_RAW) +#define CSS_CAPTURE_MODE_BAYER CSS_ID(CSS_CAPTURE_MODE_BAYER) +#define CSS_CAPTURE_MODE_PRIMARY CSS_ID(CSS_CAPTURE_MODE_PRIMARY) +#define CSS_CAPTURE_MODE_ADVANCED CSS_ID(CSS_CAPTURE_MODE_ADVANCED) +#define CSS_CAPTURE_MODE_LOW_LIGHT CSS_ID(CSS_CAPTURE_MODE_LOW_LIGHT) + +#define CSS_MORPH_TABLE_NUM_PLANES CSS_ID(CSS_MORPH_TABLE_NUM_PLANES) + +#define CSS_FRAME_FORMAT_NV11 CSS_ID(CSS_FRAME_FORMAT_NV11) +#define CSS_FRAME_FORMAT_NV12 CSS_ID(CSS_FRAME_FORMAT_NV12) +#define CSS_FRAME_FORMAT_NV16 CSS_ID(CSS_FRAME_FORMAT_NV16) +#define CSS_FRAME_FORMAT_NV21 CSS_ID(CSS_FRAME_FORMAT_NV21) +#define CSS_FRAME_FORMAT_NV61 CSS_ID(CSS_FRAME_FORMAT_NV61) +#define CSS_FRAME_FORMAT_YV12 CSS_ID(CSS_FRAME_FORMAT_YV12) +#define CSS_FRAME_FORMAT_YV16 CSS_ID(CSS_FRAME_FORMAT_YV16) +#define CSS_FRAME_FORMAT_YUV420 CSS_ID(CSS_FRAME_FORMAT_YUV420) +#define CSS_FRAME_FORMAT_YUV420_16 CSS_ID(CSS_FRAME_FORMAT_YUV420_16) +#define CSS_FRAME_FORMAT_YUV422 CSS_ID(CSS_FRAME_FORMAT_YUV422) +#define CSS_FRAME_FORMAT_YUV422_16 CSS_ID(CSS_FRAME_FORMAT_YUV422_16) +#define CSS_FRAME_FORMAT_UYVY CSS_ID(CSS_FRAME_FORMAT_UYVY) +#define CSS_FRAME_FORMAT_YUYV CSS_ID(CSS_FRAME_FORMAT_YUYV) +#define CSS_FRAME_FORMAT_YUV444 CSS_ID(CSS_FRAME_FORMAT_YUV444) +#define CSS_FRAME_FORMAT_YUV_LINE CSS_ID(CSS_FRAME_FORMAT_YUV_LINE) +#define CSS_FRAME_FORMAT_RAW CSS_ID(CSS_FRAME_FORMAT_RAW) +#define CSS_FRAME_FORMAT_RGB565 CSS_ID(CSS_FRAME_FORMAT_RGB565) +#define CSS_FRAME_FORMAT_PLANAR_RGB888 CSS_ID(CSS_FRAME_FORMAT_PLANAR_RGB888) +#define CSS_FRAME_FORMAT_RGBA888 CSS_ID(CSS_FRAME_FORMAT_RGBA888) +#define CSS_FRAME_FORMAT_QPLANE6 CSS_ID(CSS_FRAME_FORMAT_QPLANE6) +#define CSS_FRAME_FORMAT_BINARY_8 CSS_ID(CSS_FRAME_FORMAT_BINARY_8) + +struct atomisp_device; +struct atomisp_sub_device; +struct video_device; +enum atomisp_input_stream_id; + +struct atomisp_metadata_buf { + struct ia_css_metadata *metadata; + void *md_vptr; + struct list_head list; +}; + +void atomisp_css_debug_dump_sp_sw_debug_info(void); +void atomisp_css_debug_dump_debug_info(const char *context); +void atomisp_css_debug_set_dtrace_level(const unsigned int trace_level); + +void atomisp_store_uint32(hrt_address addr, uint32_t data); +void atomisp_load_uint32(hrt_address addr, uint32_t *data); + +int atomisp_css_init(struct atomisp_device *isp); + +void atomisp_css_uninit(struct atomisp_device *isp); + +void atomisp_css_suspend(struct atomisp_device *isp); + +int atomisp_css_resume(struct atomisp_device *isp); + +void atomisp_css_init_struct(struct atomisp_sub_device *asd); + +int atomisp_css_irq_translate(struct atomisp_device *isp, + unsigned int *infos); + +void atomisp_css_rx_get_irq_info(enum ia_css_csi2_port port, + unsigned int *infos); + +void atomisp_css_rx_clear_irq_info(enum ia_css_csi2_port port, + unsigned int infos); + +int atomisp_css_irq_enable(struct atomisp_device *isp, + enum atomisp_css_irq_info info, bool enable); + +int atomisp_q_video_buffer_to_css(struct atomisp_sub_device *asd, + struct videobuf_vmalloc_memory *vm_mem, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_buffer_type css_buf_type, + enum atomisp_css_pipe_id css_pipe_id); + +int atomisp_q_s3a_buffer_to_css(struct atomisp_sub_device *asd, + struct atomisp_s3a_buf *s3a_buf, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_pipe_id css_pipe_id); + +int atomisp_q_metadata_buffer_to_css(struct atomisp_sub_device *asd, + struct atomisp_metadata_buf *metadata_buf, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_pipe_id css_pipe_id); + +int atomisp_q_dis_buffer_to_css(struct atomisp_sub_device *asd, + struct atomisp_dis_buf *dis_buf, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_pipe_id css_pipe_id); + +void atomisp_css_mmu_invalidate_cache(void); + +void atomisp_css_mmu_invalidate_tlb(void); + +void atomisp_css_mmu_set_page_table_base_index(unsigned long base_index); + +int atomisp_css_start(struct atomisp_sub_device *asd, + enum atomisp_css_pipe_id pipe_id, bool in_reset); + +void atomisp_css_update_isp_params(struct atomisp_sub_device *asd); +void atomisp_css_update_isp_params_on_pipe(struct atomisp_sub_device *asd, + struct ia_css_pipe *pipe); + +int atomisp_css_queue_buffer(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_pipe_id pipe_id, + enum atomisp_css_buffer_type buf_type, + struct atomisp_css_buffer *isp_css_buffer); + +int atomisp_css_dequeue_buffer(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_pipe_id pipe_id, + enum atomisp_css_buffer_type buf_type, + struct atomisp_css_buffer *isp_css_buffer); + +int atomisp_css_allocate_stat_buffers(struct atomisp_sub_device *asd, + uint16_t stream_id, + struct atomisp_s3a_buf *s3a_buf, + struct atomisp_dis_buf *dis_buf, + struct atomisp_metadata_buf *md_buf); + +void atomisp_css_free_stat_buffers(struct atomisp_sub_device *asd); + +void atomisp_css_free_3a_buffer(struct atomisp_s3a_buf *s3a_buf); + +void atomisp_css_free_dis_buffer(struct atomisp_dis_buf *dis_buf); + +void atomisp_css_free_metadata_buffer(struct atomisp_metadata_buf *metadata_buf); + +int atomisp_css_get_grid_info(struct atomisp_sub_device *asd, + enum atomisp_css_pipe_id pipe_id, + int source_pad); + +int atomisp_alloc_3a_output_buf(struct atomisp_sub_device *asd); + +int atomisp_alloc_dis_coef_buf(struct atomisp_sub_device *asd); + +int atomisp_alloc_metadata_output_buf(struct atomisp_sub_device *asd); + +void atomisp_free_metadata_output_buf(struct atomisp_sub_device *asd); + +void atomisp_css_get_dis_statistics(struct atomisp_sub_device *asd, + struct atomisp_css_buffer *isp_css_buffer, + struct ia_css_isp_dvs_statistics_map *dvs_map); + +int atomisp_css_dequeue_event(struct atomisp_css_event *current_event); + +void atomisp_css_temp_pipe_to_pipe_id(struct atomisp_sub_device *asd, + struct atomisp_css_event *current_event); + +int atomisp_css_isys_set_resolution(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + struct v4l2_mbus_framefmt *ffmt, + int isys_stream); + +void atomisp_css_isys_set_link(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + int link, + int isys_stream); + +void atomisp_css_isys_set_valid(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + bool valid, + int isys_stream); + +void atomisp_css_isys_set_format(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_stream_format format, + int isys_stream); + +int atomisp_css_set_default_isys_config(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + struct v4l2_mbus_framefmt *ffmt); + +int atomisp_css_isys_two_stream_cfg(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_stream_format input_format); + +void atomisp_css_isys_two_stream_cfg_update_stream1( + struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_stream_format input_format, + unsigned int width, unsigned int height); + +void atomisp_css_isys_two_stream_cfg_update_stream2( + struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_stream_format input_format, + unsigned int width, unsigned int height); + +int atomisp_css_input_set_resolution(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + struct v4l2_mbus_framefmt *ffmt); + +void atomisp_css_input_set_binning_factor(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + unsigned int bin_factor); + +void atomisp_css_input_set_bayer_order(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_bayer_order bayer_order); + +void atomisp_css_input_set_format(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_stream_format format); + +int atomisp_css_input_set_effective_resolution( + struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + unsigned int width, + unsigned int height); + +void atomisp_css_video_set_dis_envelope(struct atomisp_sub_device *asd, + unsigned int dvs_w, unsigned int dvs_h); + +void atomisp_css_input_set_two_pixels_per_clock( + struct atomisp_sub_device *asd, + bool two_ppc); + +void atomisp_css_enable_raw_binning(struct atomisp_sub_device *asd, + bool enable); + +void atomisp_css_enable_dz(struct atomisp_sub_device *asd, bool enable); + +void atomisp_css_capture_set_mode(struct atomisp_sub_device *asd, + enum atomisp_css_capture_mode mode); + +void atomisp_css_input_set_mode(struct atomisp_sub_device *asd, + enum atomisp_css_input_mode mode); + +void atomisp_css_capture_enable_online(struct atomisp_sub_device *asd, + unsigned short stream_index, bool enable); + +void atomisp_css_preview_enable_online(struct atomisp_sub_device *asd, + unsigned short stream_index, bool enable); + +void atomisp_css_video_enable_online(struct atomisp_sub_device *asd, + bool enable); + +void atomisp_css_enable_continuous(struct atomisp_sub_device *asd, + bool enable); + +void atomisp_css_enable_cvf(struct atomisp_sub_device *asd, + bool enable); + +int atomisp_css_input_configure_port(struct atomisp_sub_device *asd, + mipi_port_ID_t port, + unsigned int num_lanes, + unsigned int timeout, + unsigned int mipi_freq, + enum atomisp_css_stream_format metadata_format, + unsigned int metadata_width, + unsigned int metadata_height); + +int atomisp_css_frame_allocate(struct atomisp_css_frame **frame, + unsigned int width, unsigned int height, + enum atomisp_css_frame_format format, + unsigned int padded_width, + unsigned int raw_bit_depth); + +int atomisp_css_frame_allocate_from_info(struct atomisp_css_frame **frame, + const struct atomisp_css_frame_info *info); + +void atomisp_css_frame_free(struct atomisp_css_frame *frame); + +int atomisp_css_frame_map(struct atomisp_css_frame **frame, + const struct atomisp_css_frame_info *info, + const void *data, uint16_t attribute, + void *context); + +int atomisp_css_set_black_frame(struct atomisp_sub_device *asd, + const struct atomisp_css_frame *raw_black_frame); + +int atomisp_css_allocate_continuous_frames(bool init_time, + struct atomisp_sub_device *asd); + +void atomisp_css_update_continuous_frames(struct atomisp_sub_device *asd); + +void atomisp_create_pipes_stream(struct atomisp_sub_device *asd); +void atomisp_destroy_pipes_stream_force(struct atomisp_sub_device *asd); + +int atomisp_css_stop(struct atomisp_sub_device *asd, + enum atomisp_css_pipe_id pipe_id, bool in_reset); + +int atomisp_css_continuous_set_num_raw_frames( + struct atomisp_sub_device *asd, + int num_frames); + +void atomisp_css_disable_vf_pp(struct atomisp_sub_device *asd, + bool disable); + +int atomisp_css_copy_configure_output(struct atomisp_sub_device *asd, + unsigned int stream_index, + unsigned int width, unsigned int height, + unsigned int padded_width, + enum atomisp_css_frame_format format); + +int atomisp_css_yuvpp_configure_output(struct atomisp_sub_device *asd, + unsigned int stream_index, + unsigned int width, unsigned int height, + unsigned int padded_width, + enum atomisp_css_frame_format format); + +int atomisp_css_yuvpp_configure_viewfinder( + struct atomisp_sub_device *asd, + unsigned int stream_index, + unsigned int width, unsigned int height, + unsigned int min_width, + enum atomisp_css_frame_format format); + +int atomisp_css_yuvpp_get_output_frame_info( + struct atomisp_sub_device *asd, + unsigned int stream_index, + struct atomisp_css_frame_info *info); + +int atomisp_css_yuvpp_get_viewfinder_frame_info( + struct atomisp_sub_device *asd, + unsigned int stream_index, + struct atomisp_css_frame_info *info); + +int atomisp_css_preview_configure_output(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum atomisp_css_frame_format format); + +int atomisp_css_capture_configure_output(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum atomisp_css_frame_format format); + +int atomisp_css_video_configure_output(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum atomisp_css_frame_format format); + +int atomisp_get_css_frame_info(struct atomisp_sub_device *asd, + uint16_t source_pad, + struct atomisp_css_frame_info *frame_info); + +int atomisp_css_video_configure_viewfinder(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum atomisp_css_frame_format format); + +int atomisp_css_capture_configure_viewfinder( + struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum atomisp_css_frame_format format); + +int atomisp_css_video_get_viewfinder_frame_info( + struct atomisp_sub_device *asd, + struct atomisp_css_frame_info *info); + +int atomisp_css_capture_get_viewfinder_frame_info( + struct atomisp_sub_device *asd, + struct atomisp_css_frame_info *info); + +int atomisp_css_copy_get_output_frame_info( + struct atomisp_sub_device *asd, + unsigned int stream_index, + struct atomisp_css_frame_info *info); + +int atomisp_css_capture_get_output_raw_frame_info( + struct atomisp_sub_device *asd, + struct atomisp_css_frame_info *info); + +int atomisp_css_preview_get_output_frame_info( + struct atomisp_sub_device *asd, + struct atomisp_css_frame_info *info); + +int atomisp_css_capture_get_output_frame_info( + struct atomisp_sub_device *asd, + struct atomisp_css_frame_info *info); + +int atomisp_css_video_get_output_frame_info( + struct atomisp_sub_device *asd, + struct atomisp_css_frame_info *info); + +int atomisp_css_preview_configure_pp_input( + struct atomisp_sub_device *asd, + unsigned int width, unsigned int height); + +int atomisp_css_capture_configure_pp_input( + struct atomisp_sub_device *asd, + unsigned int width, unsigned int height); + +int atomisp_css_video_configure_pp_input( + struct atomisp_sub_device *asd, + unsigned int width, unsigned int height); + +int atomisp_css_offline_capture_configure(struct atomisp_sub_device *asd, + int num_captures, unsigned int skip, int offset); +int atomisp_css_exp_id_capture(struct atomisp_sub_device *asd, int exp_id); +int atomisp_css_exp_id_unlock(struct atomisp_sub_device *asd, int exp_id); + +int atomisp_css_capture_enable_xnr(struct atomisp_sub_device *asd, + bool enable); + +void atomisp_css_send_input_frame(struct atomisp_sub_device *asd, + unsigned short *data, unsigned int width, + unsigned int height); + +bool atomisp_css_isp_has_started(void); + +void atomisp_css_request_flash(struct atomisp_sub_device *asd); + +void atomisp_css_set_wb_config(struct atomisp_sub_device *asd, + struct atomisp_css_wb_config *wb_config); + +void atomisp_css_set_ob_config(struct atomisp_sub_device *asd, + struct atomisp_css_ob_config *ob_config); + +void atomisp_css_set_dp_config(struct atomisp_sub_device *asd, + struct atomisp_css_dp_config *dp_config); + +void atomisp_css_set_de_config(struct atomisp_sub_device *asd, + struct atomisp_css_de_config *de_config); + +void atomisp_css_set_dz_config(struct atomisp_sub_device *asd, + struct atomisp_css_dz_config *dz_config); + +void atomisp_css_set_default_de_config(struct atomisp_sub_device *asd); + +void atomisp_css_set_ce_config(struct atomisp_sub_device *asd, + struct atomisp_css_ce_config *ce_config); + +void atomisp_css_set_nr_config(struct atomisp_sub_device *asd, + struct atomisp_css_nr_config *nr_config); + +void atomisp_css_set_ee_config(struct atomisp_sub_device *asd, + struct atomisp_css_ee_config *ee_config); + +void atomisp_css_set_tnr_config(struct atomisp_sub_device *asd, + struct atomisp_css_tnr_config *tnr_config); + +void atomisp_css_set_cc_config(struct atomisp_sub_device *asd, + struct atomisp_css_cc_config *cc_config); + +void atomisp_css_set_macc_table(struct atomisp_sub_device *asd, + struct atomisp_css_macc_table *macc_table); + +void atomisp_css_set_gamma_table(struct atomisp_sub_device *asd, + struct atomisp_css_gamma_table *gamma_table); + +void atomisp_css_set_ctc_table(struct atomisp_sub_device *asd, + struct atomisp_css_ctc_table *ctc_table); + +void atomisp_css_set_gc_config(struct atomisp_sub_device *asd, + struct atomisp_css_gc_config *gc_config); + +void atomisp_css_set_3a_config(struct atomisp_sub_device *asd, + struct atomisp_css_3a_config *s3a_config); + +void atomisp_css_video_set_dis_vector(struct atomisp_sub_device *asd, + struct atomisp_dis_vector *vector); + +void atomisp_css_set_dvs2_coefs(struct atomisp_sub_device *asd, + struct ia_css_dvs2_coefficients *coefs); + +int atomisp_css_set_dis_coefs(struct atomisp_sub_device *asd, + struct atomisp_dis_coefficients *coefs); + +void atomisp_css_set_zoom_factor(struct atomisp_sub_device *asd, + unsigned int zoom); + +int atomisp_css_get_wb_config(struct atomisp_sub_device *asd, + struct atomisp_wb_config *config); + +int atomisp_css_get_ob_config(struct atomisp_sub_device *asd, + struct atomisp_ob_config *config); + +int atomisp_css_get_dp_config(struct atomisp_sub_device *asd, + struct atomisp_dp_config *config); + +int atomisp_css_get_de_config(struct atomisp_sub_device *asd, + struct atomisp_de_config *config); + +int atomisp_css_get_nr_config(struct atomisp_sub_device *asd, + struct atomisp_nr_config *config); + +int atomisp_css_get_ee_config(struct atomisp_sub_device *asd, + struct atomisp_ee_config *config); + +int atomisp_css_get_tnr_config(struct atomisp_sub_device *asd, + struct atomisp_tnr_config *config); + +int atomisp_css_get_ctc_table(struct atomisp_sub_device *asd, + struct atomisp_ctc_table *config); + +int atomisp_css_get_gamma_table(struct atomisp_sub_device *asd, + struct atomisp_gamma_table *config); + +int atomisp_css_get_gc_config(struct atomisp_sub_device *asd, + struct atomisp_gc_config *config); + +int atomisp_css_get_3a_config(struct atomisp_sub_device *asd, + struct atomisp_3a_config *config); + +int atomisp_css_get_formats_config(struct atomisp_sub_device *asd, + struct atomisp_formats_config *formats_config); + +void atomisp_css_set_formats_config(struct atomisp_sub_device *asd, + struct atomisp_css_formats_config *formats_config); + +int atomisp_css_get_zoom_factor(struct atomisp_sub_device *asd, + unsigned int *zoom); + +struct atomisp_css_shading_table *atomisp_css_shading_table_alloc( + unsigned int width, unsigned int height); + +void atomisp_css_set_shading_table(struct atomisp_sub_device *asd, + struct atomisp_css_shading_table *table); + +void atomisp_css_shading_table_free(struct atomisp_css_shading_table *table); + +struct atomisp_css_morph_table *atomisp_css_morph_table_allocate( + unsigned int width, unsigned int height); + +void atomisp_css_set_morph_table(struct atomisp_sub_device *asd, + struct atomisp_css_morph_table *table); + +void atomisp_css_get_morph_table(struct atomisp_sub_device *asd, + struct atomisp_css_morph_table *table); + +void atomisp_css_morph_table_free(struct atomisp_css_morph_table *table); + +void atomisp_css_set_cont_prev_start_time(struct atomisp_device *isp, + unsigned int overlap); + +int atomisp_css_get_dis_stat(struct atomisp_sub_device *asd, + struct atomisp_dis_statistics *stats); + +int atomisp_css_update_stream(struct atomisp_sub_device *asd); + +int atomisp_css_create_acc_pipe(struct atomisp_sub_device *asd); + +int atomisp_css_start_acc_pipe(struct atomisp_sub_device *asd); + +int atomisp_css_stop_acc_pipe(struct atomisp_sub_device *asd); + +void atomisp_css_destroy_acc_pipe(struct atomisp_sub_device *asd); + +int atomisp_css_load_acc_extension(struct atomisp_sub_device *asd, + struct atomisp_css_fw_info *fw, + enum atomisp_css_pipe_id pipe_id, + unsigned int type); + +void atomisp_css_unload_acc_extension(struct atomisp_sub_device *asd, + struct atomisp_css_fw_info *fw, + enum atomisp_css_pipe_id pipe_id); + +int atomisp_css_wait_acc_finish(struct atomisp_sub_device *asd); + +void atomisp_css_acc_done(struct atomisp_sub_device *asd); + +int atomisp_css_load_acc_binary(struct atomisp_sub_device *asd, + struct atomisp_css_fw_info *fw, + unsigned int index); + +void atomisp_css_unload_acc_binary(struct atomisp_sub_device *asd); + +struct atomisp_acc_fw; +int atomisp_css_set_acc_parameters(struct atomisp_acc_fw *acc_fw); + +int atomisp_css_isr_thread(struct atomisp_device *isp, + bool *frame_done_found, + bool *css_pipe_done); +void atomisp_set_stop_timeout(unsigned int timeout); + +bool atomisp_css_valid_sof(struct atomisp_device *isp); + +void atomisp_en_dz_capt_pipe(struct atomisp_sub_device *asd, bool enable); + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_css20.c b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_css20.c new file mode 100644 index 0000000000000000000000000000000000000000..6697d72710b07fc89da0bd8f3ba745093a5e9a84 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_css20.c @@ -0,0 +1,4800 @@ +/* + * Support for Clovertrail PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include +#include + +#include "mmu/isp_mmu.h" +#include "mmu/sh_mmu_mrfld.h" +#include "hmm/hmm_bo.h" +#include "hmm/hmm.h" + +#include "atomisp_compat.h" +#include "atomisp_internal.h" +#include "atomisp_cmd.h" +#include "atomisp-regs.h" +#include "atomisp_fops.h" +#include "atomisp_ioctl.h" +#include "atomisp_acc.h" + +#include "hrt/hive_isp_css_mm_hrt.h" + +#include + +#include "ia_css_debug.h" +#include "ia_css_isp_param.h" +#include "sh_css_hrt.h" +#include "ia_css_isys.h" + +#include + +/* Assume max number of ACC stages */ +#define MAX_ACC_STAGES 20 + +/* Ideally, this should come from CSS headers */ +#define NO_LINK -1 + +/* + * to serialize MMIO access , this is due to ISP2400 silicon issue Sighting + * #4684168, if concurrency access happened, system may hard hang. + */ +static DEFINE_SPINLOCK(mmio_lock); + +enum frame_info_type { + ATOMISP_CSS_VF_FRAME, + ATOMISP_CSS_SECOND_VF_FRAME, + ATOMISP_CSS_OUTPUT_FRAME, + ATOMISP_CSS_SECOND_OUTPUT_FRAME, + ATOMISP_CSS_RAW_FRAME, +}; + +struct bayer_ds_factor { + unsigned int numerator; + unsigned int denominator; +}; + +void atomisp_css_debug_dump_sp_sw_debug_info(void) +{ + ia_css_debug_dump_sp_sw_debug_info(); +} + +void atomisp_css_debug_dump_debug_info(const char *context) +{ + ia_css_debug_dump_debug_info(context); +} + +void atomisp_css_debug_set_dtrace_level(const unsigned int trace_level) +{ + ia_css_debug_set_dtrace_level(trace_level); +} + +unsigned int atomisp_css_debug_get_dtrace_level(void) +{ + return ia_css_debug_trace_level; +} + +static ia_css_ptr atomisp_css2_mm_alloc(size_t bytes, uint32_t attr) +{ + if (attr & IA_CSS_MEM_ATTR_ZEROED) { + if (attr & IA_CSS_MEM_ATTR_CACHED) { + if (attr & IA_CSS_MEM_ATTR_CONTIGUOUS) + return (ia_css_ptr) hrt_isp_css_mm_calloc_contiguous(bytes); + else + return (ia_css_ptr) hrt_isp_css_mm_calloc_cached(bytes); + } else { + if (attr & IA_CSS_MEM_ATTR_CONTIGUOUS) + return (ia_css_ptr) hrt_isp_css_mm_calloc_contiguous(bytes); + else + return (ia_css_ptr) hrt_isp_css_mm_calloc(bytes); + } + } else { + if (attr & IA_CSS_MEM_ATTR_CACHED) { + if (attr & IA_CSS_MEM_ATTR_CONTIGUOUS) + return (ia_css_ptr) hrt_isp_css_mm_alloc_contiguous(bytes); + else + return (ia_css_ptr) hrt_isp_css_mm_alloc_cached(bytes); + } else { + if (attr & IA_CSS_MEM_ATTR_CONTIGUOUS) + return (ia_css_ptr) hrt_isp_css_mm_alloc_contiguous(bytes); + else + return (ia_css_ptr) hrt_isp_css_mm_alloc(bytes); + } + } +} + +static void atomisp_css2_mm_free(ia_css_ptr ptr) +{ + hrt_isp_css_mm_free(ptr); +} + +static int atomisp_css2_mm_load(ia_css_ptr ptr, void *data, size_t bytes) +{ + return hrt_isp_css_mm_load(ptr, data, bytes); +} + +static int atomisp_css2_mm_store(ia_css_ptr ptr, const void *data, size_t bytes) +{ + return hrt_isp_css_mm_store(ptr, data, bytes); +} + +static int atomisp_css2_mm_set(ia_css_ptr ptr, int c, size_t bytes) +{ + return hrt_isp_css_mm_set(ptr, c, bytes); +} + +static ia_css_ptr atomisp_css2_mm_mmap(const void *ptr, const size_t size, + uint16_t attribute, void *context) +{ + struct hrt_userbuffer_attr *userbuffer_attr = context; + return hrt_isp_css_mm_alloc_user_ptr( + size, (void *)ptr, userbuffer_attr->pgnr, + userbuffer_attr->type, + attribute & HRT_BUF_FLAG_CACHED); +} + +void atomisp_css2_hw_store_8(hrt_address addr, uint8_t data) +{ + unsigned long flags; + + spin_lock_irqsave(&mmio_lock, flags); + _hrt_master_port_store_8(addr, data); + spin_unlock_irqrestore(&mmio_lock, flags); +} + +static void atomisp_css2_hw_store_16(hrt_address addr, uint16_t data) +{ + unsigned long flags; + + spin_lock_irqsave(&mmio_lock, flags); + _hrt_master_port_store_16(addr, data); + spin_unlock_irqrestore(&mmio_lock, flags); +} + +static void atomisp_css2_hw_store_32(hrt_address addr, uint32_t data) +{ + unsigned long flags; + + spin_lock_irqsave(&mmio_lock, flags); + _hrt_master_port_store_32(addr, data); + spin_unlock_irqrestore(&mmio_lock, flags); +} + +static uint8_t atomisp_css2_hw_load_8(hrt_address addr) +{ + unsigned long flags; + uint8_t ret; + + spin_lock_irqsave(&mmio_lock, flags); + ret = _hrt_master_port_load_8(addr); + spin_unlock_irqrestore(&mmio_lock, flags); + return ret; +} + +uint16_t atomisp_css2_hw_load_16(hrt_address addr) +{ + unsigned long flags; + uint16_t ret; + + spin_lock_irqsave(&mmio_lock, flags); + ret = _hrt_master_port_load_16(addr); + spin_unlock_irqrestore(&mmio_lock, flags); + return ret; +} +uint32_t atomisp_css2_hw_load_32(hrt_address addr) +{ + unsigned long flags; + uint32_t ret; + + spin_lock_irqsave(&mmio_lock, flags); + ret = _hrt_master_port_load_32(addr); + spin_unlock_irqrestore(&mmio_lock, flags); + return ret; +} + +static void atomisp_css2_hw_store(hrt_address addr, + const void *from, uint32_t n) +{ + unsigned long flags; + unsigned i; + unsigned int _to = (unsigned int)addr; + const char *_from = (const char *)from; + + spin_lock_irqsave(&mmio_lock, flags); + for (i = 0; i < n; i++, _to++, _from++) + _hrt_master_port_store_8(_to , *_from); + spin_unlock_irqrestore(&mmio_lock, flags); +} + +static void atomisp_css2_hw_load(hrt_address addr, void *to, uint32_t n) +{ + unsigned long flags; + unsigned i; + char *_to = (char *)to; + unsigned int _from = (unsigned int)addr; + + spin_lock_irqsave(&mmio_lock, flags); + for (i = 0; i < n; i++, _to++, _from++) + *_to = _hrt_master_port_load_8(_from); + spin_unlock_irqrestore(&mmio_lock, flags); +} + +static int atomisp_css2_dbg_print(const char *fmt, va_list args) +{ + vprintk(fmt, args); + return 0; +} + +static int atomisp_css2_dbg_ftrace_print(const char *fmt, va_list args) +{ + ftrace_vprintk(fmt, args); + return 0; +} + +static int atomisp_css2_err_print(const char *fmt, va_list args) +{ + vprintk(fmt, args); + return 0; +} + +void atomisp_store_uint32(hrt_address addr, uint32_t data) +{ + atomisp_css2_hw_store_32(addr, data); +} + +void atomisp_load_uint32(hrt_address addr, uint32_t *data) +{ + *data = atomisp_css2_hw_load_32(addr); +} +static int hmm_get_mmu_base_addr(unsigned int *mmu_base_addr) +{ + if (sh_mmu_mrfld.get_pd_base == NULL) { + dev_err(atomisp_dev, "get mmu base address failed.\n"); + return -EINVAL; + } + + *mmu_base_addr = sh_mmu_mrfld.get_pd_base(&bo_device.mmu, + bo_device.mmu.base_address); + return 0; +} + +static void atomisp_isp_parameters_clean_up( + struct atomisp_css_isp_config *config) +{ + /* + * Set NULL to configs pointer to avoid they are set into isp again when + * some configs are changed and need to be updated later. + */ + memset(config, 0, sizeof(*config)); +} + +static void __dump_pipe_config(struct atomisp_sub_device *asd, + struct atomisp_stream_env *stream_env, + unsigned int pipe_id) +{ + struct atomisp_device *isp = asd->isp; + if (stream_env->pipes[pipe_id]) { + struct ia_css_pipe_config *p_config; + struct ia_css_pipe_extra_config *pe_config; + p_config = &stream_env->pipe_configs[pipe_id]; + pe_config = &stream_env->pipe_extra_configs[pipe_id]; + dev_dbg(isp->dev, "dumping pipe[%d] config:\n", pipe_id); + dev_dbg(isp->dev, + "pipe_config.pipe_mode:%d.\n", p_config->mode); + dev_dbg(isp->dev, + "pipe_config.output_info[0] w=%d, h=%d.\n", + p_config->output_info[0].res.width, + p_config->output_info[0].res.height); + dev_dbg(isp->dev, + "pipe_config.vf_pp_in_res w=%d, h=%d.\n", + p_config->vf_pp_in_res.width, + p_config->vf_pp_in_res.height); + dev_dbg(isp->dev, + "pipe_config.capt_pp_in_res w=%d, h=%d.\n", + p_config->capt_pp_in_res.width, + p_config->capt_pp_in_res.height); + dev_dbg(isp->dev, + "pipe_config.output.padded w=%d.\n", + p_config->output_info[0].padded_width); + dev_dbg(isp->dev, + "pipe_config.vf_output_info[0] w=%d, h=%d.\n", + p_config->vf_output_info[0].res.width, + p_config->vf_output_info[0].res.height); + dev_dbg(isp->dev, + "pipe_config.bayer_ds_out_res w=%d, h=%d.\n", + p_config->bayer_ds_out_res.width, + p_config->bayer_ds_out_res.height); + dev_dbg(isp->dev, + "pipe_config.envelope w=%d, h=%d.\n", + p_config->dvs_envelope.width, + p_config->dvs_envelope.height); + dev_dbg(isp->dev, + "pipe_config.dvs_frame_delay=%d.\n", + p_config->dvs_frame_delay); + dev_dbg(isp->dev, + "pipe_config.isp_pipe_version:%d.\n", + p_config->isp_pipe_version); + dev_dbg(isp->dev, + "pipe_config.acc_extension=%p.\n", + p_config->acc_extension); + dev_dbg(isp->dev, + "pipe_config.acc_stages=%p.\n", + p_config->acc_stages); + dev_dbg(isp->dev, + "pipe_config.num_acc_stages=%d.\n", + p_config->num_acc_stages); + dev_dbg(isp->dev, + "pipe_config.acc_num_execs=%d.\n", + p_config->acc_num_execs); + dev_dbg(isp->dev, + "pipe_config.default_capture_config.capture_mode=%d.\n", + p_config->default_capture_config.mode); + dev_dbg(isp->dev, + "pipe_config.enable_dz=%d.\n", + p_config->enable_dz); + dev_dbg(isp->dev, + "pipe_config.default_capture_config.enable_xnr=%d.\n", + p_config->default_capture_config.enable_xnr); + dev_dbg(isp->dev, + "dumping pipe[%d] extra config:\n", pipe_id); + dev_dbg(isp->dev, + "pipe_extra_config.enable_raw_binning:%d.\n", + pe_config->enable_raw_binning); + dev_dbg(isp->dev, + "pipe_extra_config.enable_yuv_ds:%d.\n", + pe_config->enable_yuv_ds); + dev_dbg(isp->dev, + "pipe_extra_config.enable_high_speed:%d.\n", + pe_config->enable_high_speed); + dev_dbg(isp->dev, + "pipe_extra_config.enable_dvs_6axis:%d.\n", + pe_config->enable_dvs_6axis); + dev_dbg(isp->dev, + "pipe_extra_config.enable_reduced_pipe:%d.\n", + pe_config->enable_reduced_pipe); + dev_dbg(isp->dev, + "pipe_(extra_)config.enable_dz:%d.\n", + p_config->enable_dz); + dev_dbg(isp->dev, + "pipe_extra_config.disable_vf_pp:%d.\n", + pe_config->disable_vf_pp); + } +} + +static void __dump_stream_config(struct atomisp_sub_device *asd, + struct atomisp_stream_env *stream_env) +{ + struct atomisp_device *isp = asd->isp; + struct ia_css_stream_config *s_config; + int j; + bool valid_stream = false; + + for (j = 0; j < IA_CSS_PIPE_ID_NUM; j++) { + if (stream_env->pipes[j]) { + __dump_pipe_config(asd, stream_env, j); + valid_stream = true; + } + } + if (!valid_stream) + return; + s_config = &stream_env->stream_config; + dev_dbg(isp->dev, "stream_config.mode=%d.\n", s_config->mode); + + if (s_config->mode == IA_CSS_INPUT_MODE_SENSOR || + s_config->mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR) { + dev_dbg(isp->dev, "stream_config.source.port.port=%d.\n", + s_config->source.port.port); + dev_dbg(isp->dev, "stream_config.source.port.num_lanes=%d.\n", + s_config->source.port.num_lanes); + dev_dbg(isp->dev, "stream_config.source.port.timeout=%d.\n", + s_config->source.port.timeout); + dev_dbg(isp->dev, "stream_config.source.port.rxcount=0x%x.\n", + s_config->source.port.rxcount); + dev_dbg(isp->dev, "stream_config.source.port.compression.type=%d.\n", + s_config->source.port.compression.type); + dev_dbg(isp->dev, "stream_config.source.port.compression.compressed_bits_per_pixel=%d.\n", + s_config->source.port.compression. + compressed_bits_per_pixel); + dev_dbg(isp->dev, "stream_config.source.port.compression.uncompressed_bits_per_pixel=%d.\n", + s_config->source.port.compression. + uncompressed_bits_per_pixel); + } else if (s_config->mode == IA_CSS_INPUT_MODE_TPG) { + dev_dbg(isp->dev, "stream_config.source.tpg.id=%d.\n", + s_config->source.tpg.id); + dev_dbg(isp->dev, "stream_config.source.tpg.mode=%d.\n", + s_config->source.tpg.mode); + dev_dbg(isp->dev, "stream_config.source.tpg.x_mask=%d.\n", + s_config->source.tpg.x_mask); + dev_dbg(isp->dev, "stream_config.source.tpg.x_delta=%d.\n", + s_config->source.tpg.x_delta); + dev_dbg(isp->dev, "stream_config.source.tpg.y_mask=%d.\n", + s_config->source.tpg.y_mask); + dev_dbg(isp->dev, "stream_config.source.tpg.y_delta=%d.\n", + s_config->source.tpg.y_delta); + dev_dbg(isp->dev, "stream_config.source.tpg.xy_mask=%d.\n", + s_config->source.tpg.xy_mask); + } else if (s_config->mode == IA_CSS_INPUT_MODE_PRBS) { + dev_dbg(isp->dev, "stream_config.source.prbs.id=%d.\n", + s_config->source.prbs.id); + dev_dbg(isp->dev, "stream_config.source.prbs.h_blank=%d.\n", + s_config->source.prbs.h_blank); + dev_dbg(isp->dev, "stream_config.source.prbs.v_blank=%d.\n", + s_config->source.prbs.v_blank); + dev_dbg(isp->dev, "stream_config.source.prbs.seed=%d.\n", + s_config->source.prbs.seed); + dev_dbg(isp->dev, "stream_config.source.prbs.seed1=%d.\n", + s_config->source.prbs.seed1); + } + + for (j = 0; j < IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH; j++) { + dev_dbg(isp->dev, "stream_configisys_config[%d].input_res w=%d, h=%d.\n", + j, + s_config->isys_config[j].input_res.width, + s_config->isys_config[j].input_res.height); + + dev_dbg(isp->dev, "stream_configisys_config[%d].linked_isys_stream_id=%d\n", + j, + s_config->isys_config[j].linked_isys_stream_id); + + dev_dbg(isp->dev, "stream_configisys_config[%d].format=%d\n", + j, + s_config->isys_config[j].format); + + dev_dbg(isp->dev, "stream_configisys_config[%d].valid=%d.\n", + j, + s_config->isys_config[j].valid); + } + + dev_dbg(isp->dev, "stream_config.input_config.input_res w=%d, h=%d.\n", + s_config->input_config.input_res.width, + s_config->input_config.input_res.height); + + dev_dbg(isp->dev, "stream_config.input_config.effective_res w=%d, h=%d.\n", + s_config->input_config.effective_res.width, + s_config->input_config.effective_res.height); + + dev_dbg(isp->dev, "stream_config.input_config.format=%d\n", + s_config->input_config.format); + + dev_dbg(isp->dev, "stream_config.input_config.bayer_order=%d.\n", + s_config->input_config.bayer_order); + + dev_dbg(isp->dev, "stream_config.pixels_per_clock=%d.\n", + s_config->pixels_per_clock); + dev_dbg(isp->dev, "stream_config.online=%d.\n", s_config->online); + dev_dbg(isp->dev, "stream_config.continuous=%d.\n", + s_config->continuous); + dev_dbg(isp->dev, "stream_config.disable_cont_viewfinder=%d.\n", + s_config->disable_cont_viewfinder); + dev_dbg(isp->dev, "stream_config.channel_id=%d.\n", + s_config->channel_id); + dev_dbg(isp->dev, "stream_config.init_num_cont_raw_buf=%d.\n", + s_config->init_num_cont_raw_buf); + dev_dbg(isp->dev, "stream_config.target_num_cont_raw_buf=%d.\n", + s_config->target_num_cont_raw_buf); + dev_dbg(isp->dev, "stream_config.left_padding=%d.\n", + s_config->left_padding); + dev_dbg(isp->dev, "stream_config.sensor_binning_factor=%d.\n", + s_config->sensor_binning_factor); + dev_dbg(isp->dev, "stream_config.pixels_per_clock=%d.\n", + s_config->pixels_per_clock); + dev_dbg(isp->dev, "stream_config.pack_raw_pixels=%d.\n", + s_config->pack_raw_pixels); + dev_dbg(isp->dev, "stream_config.flash_gpio_pin=%d.\n", + s_config->flash_gpio_pin); + dev_dbg(isp->dev, "stream_config.mipi_buffer_config.size_mem_words=%d.\n", + s_config->mipi_buffer_config.size_mem_words); + dev_dbg(isp->dev, "stream_config.mipi_buffer_config.contiguous=%d.\n", + s_config->mipi_buffer_config.contiguous); + dev_dbg(isp->dev, "stream_config.metadata_config.data_type=%d.\n", + s_config->metadata_config.data_type); + dev_dbg(isp->dev, "stream_config.metadata_config.resolution w=%d, h=%d.\n", + s_config->metadata_config.resolution.width, + s_config->metadata_config.resolution.height); +} + +static int __destroy_stream(struct atomisp_sub_device *asd, + struct atomisp_stream_env *stream_env, bool force) +{ + struct atomisp_device *isp = asd->isp; + int i; + unsigned long timeout; + + if (!stream_env->stream) + return 0; + + if (!force) { + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) + if (stream_env->update_pipe[i]) + break; + + if (i == IA_CSS_PIPE_ID_NUM) + return 0; + } + + if (stream_env->stream_state == CSS_STREAM_STARTED + && ia_css_stream_stop(stream_env->stream) != IA_CSS_SUCCESS) { + dev_err(isp->dev, "stop stream failed.\n"); + return -EINVAL; + } + + if (stream_env->stream_state == CSS_STREAM_STARTED) { + timeout = jiffies + msecs_to_jiffies(40); + while (1) { + if (ia_css_stream_has_stopped(stream_env->stream)) + break; + + if (time_after(jiffies, timeout)) { + dev_warn(isp->dev, "stop stream timeout.\n"); + break; + } + + usleep_range(100, 200); + }; + } + + stream_env->stream_state = CSS_STREAM_STOPPED; + + if (ia_css_stream_destroy(stream_env->stream) != IA_CSS_SUCCESS) { + dev_err(isp->dev, "destroy stream failed.\n"); + return -EINVAL; + } + stream_env->stream_state = CSS_STREAM_UNINIT; + stream_env->stream = NULL; + + return 0; +} + +static int __destroy_streams(struct atomisp_sub_device *asd, bool force) +{ + int ret, i; + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) { + ret = __destroy_stream(asd, &asd->stream_env[i], force); + if (ret) + return ret; + } + asd->stream_prepared = false; + return 0; +} +static int __create_stream(struct atomisp_sub_device *asd, + struct atomisp_stream_env *stream_env) +{ + int pipe_index = 0, i; + struct ia_css_pipe *multi_pipes[IA_CSS_PIPE_ID_NUM]; + + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { + if (stream_env->pipes[i]) + multi_pipes[pipe_index++] = stream_env->pipes[i]; + } + if (pipe_index == 0) + return 0; + + stream_env->stream_config.target_num_cont_raw_buf = + asd->continuous_raw_buffer_size->val; + stream_env->stream_config.channel_id = stream_env->ch_id; + stream_env->stream_config.ia_css_enable_raw_buffer_locking = + asd->enable_raw_buffer_lock->val; + + __dump_stream_config(asd, stream_env); + if (ia_css_stream_create(&stream_env->stream_config, + pipe_index, multi_pipes, &stream_env->stream) != IA_CSS_SUCCESS) + return -EINVAL; + if (ia_css_stream_get_info(stream_env->stream, + &stream_env->stream_info) != IA_CSS_SUCCESS) { + ia_css_stream_destroy(stream_env->stream); + stream_env->stream = NULL; + return -EINVAL; + } + + stream_env->stream_state = CSS_STREAM_CREATED; + return 0; +} + +static int __create_streams(struct atomisp_sub_device *asd) +{ + int ret, i; + + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) { + ret = __create_stream(asd, &asd->stream_env[i]); + if (ret) + goto rollback; + } + asd->stream_prepared = true; + return 0; +rollback: + for (i--; i >= 0; i--) + __destroy_stream(asd, &asd->stream_env[i], true); + return ret; +} + +static int __destroy_stream_pipes(struct atomisp_sub_device *asd, + struct atomisp_stream_env *stream_env, + bool force) +{ + struct atomisp_device *isp = asd->isp; + int ret = 0; + int i; + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { + if (!stream_env->pipes[i] || + !(force || stream_env->update_pipe[i])) + continue; + if (ia_css_pipe_destroy(stream_env->pipes[i]) + != IA_CSS_SUCCESS) { + dev_err(isp->dev, + "destroy pipe[%d]failed.cannot recover.\n", i); + ret = -EINVAL; + } + stream_env->pipes[i] = NULL; + stream_env->update_pipe[i] = false; + } + return ret; +} + +static int __destroy_pipes(struct atomisp_sub_device *asd, bool force) +{ + struct atomisp_device *isp = asd->isp; + int i; + int ret = 0; + + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) { + if (asd->stream_env[i].stream) { + + dev_err(isp->dev, + "cannot destroy css pipes for stream[%d].\n", + i); + continue; + } + + ret = __destroy_stream_pipes(asd, &asd->stream_env[i], force); + if (ret) + return ret; + } + + return 0; +} + +void atomisp_destroy_pipes_stream_force(struct atomisp_sub_device *asd) +{ + __destroy_streams(asd, true); + __destroy_pipes(asd, true); +} + +static void __apply_additional_pipe_config( + struct atomisp_sub_device *asd, + struct atomisp_stream_env *stream_env, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + + if (pipe_id < 0 || pipe_id >= IA_CSS_PIPE_ID_NUM) { + dev_err(isp->dev, + "wrong pipe_id for additional pipe config.\n"); + return; + } + + /* apply default pipe config */ + stream_env->pipe_configs[pipe_id].isp_pipe_version = 2; + stream_env->pipe_configs[pipe_id].enable_dz = + asd->disable_dz->val ? false : true; + /* apply isp 2.2 specific config for baytrail*/ + switch (pipe_id) { + case IA_CSS_PIPE_ID_CAPTURE: + /* enable capture pp/dz manually or digital zoom would + * fail*/ + if (stream_env->pipe_configs[pipe_id]. + default_capture_config.mode == CSS_CAPTURE_MODE_RAW) + stream_env->pipe_configs[pipe_id].enable_dz = false; +#ifdef ISP2401 + + /* the isp default to use ISP2.2 and the camera hal will + * control whether use isp2.7 */ + if (asd->select_isp_version->val == + ATOMISP_CSS_ISP_PIPE_VERSION_2_7) + stream_env->pipe_configs[pipe_id].isp_pipe_version = + SH_CSS_ISP_PIPE_VERSION_2_7; + else + stream_env->pipe_configs[pipe_id].isp_pipe_version = + SH_CSS_ISP_PIPE_VERSION_2_2; +#endif + break; + case IA_CSS_PIPE_ID_VIDEO: + /* enable reduced pipe to have binary + * video_dz_2_min selected*/ + stream_env->pipe_extra_configs[pipe_id] + .enable_reduced_pipe = true; + stream_env->pipe_configs[pipe_id] + .enable_dz = false; + if (ATOMISP_SOC_CAMERA(asd)) + stream_env->pipe_configs[pipe_id].enable_dz = true; + + if (asd->params.video_dis_en) { + stream_env->pipe_extra_configs[pipe_id] + .enable_dvs_6axis = true; + stream_env->pipe_configs[pipe_id] + .dvs_frame_delay = + ATOMISP_CSS2_NUM_DVS_FRAME_DELAY; + } + break; + case IA_CSS_PIPE_ID_PREVIEW: + break; + case IA_CSS_PIPE_ID_YUVPP: + case IA_CSS_PIPE_ID_COPY: + if (ATOMISP_SOC_CAMERA(asd)) + stream_env->pipe_configs[pipe_id].enable_dz = true; + else + stream_env->pipe_configs[pipe_id].enable_dz = false; + break; + case IA_CSS_PIPE_ID_ACC: + stream_env->pipe_configs[pipe_id].mode = IA_CSS_PIPE_MODE_ACC; + stream_env->pipe_configs[pipe_id].enable_dz = false; + break; + default: + break; + } +} + +static bool is_pipe_valid_to_current_run_mode(struct atomisp_sub_device *asd, + enum ia_css_pipe_id pipe_id) +{ + if (!asd) + return false; + + if (pipe_id == CSS_PIPE_ID_ACC || pipe_id == CSS_PIPE_ID_YUVPP) + return true; + + if (asd->vfpp) { + if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_SCALER) { + if (pipe_id == IA_CSS_PIPE_ID_VIDEO) + return true; + else + return false; + } else if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_LOWLAT) { + if (pipe_id == IA_CSS_PIPE_ID_CAPTURE) + return true; + else + return false; + } + } + + if (!asd->run_mode) + return false; + + if (asd->copy_mode && pipe_id == IA_CSS_PIPE_ID_COPY) + return true; + + switch (asd->run_mode->val) { + case ATOMISP_RUN_MODE_STILL_CAPTURE: + if (pipe_id == IA_CSS_PIPE_ID_CAPTURE) + return true; + else + return false; + case ATOMISP_RUN_MODE_PREVIEW: + if (!asd->continuous_mode->val) { + if (pipe_id == IA_CSS_PIPE_ID_PREVIEW) + return true; + else + return false; + } + /* fall through to ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE */ + case ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE: + if (pipe_id == IA_CSS_PIPE_ID_CAPTURE || + pipe_id == IA_CSS_PIPE_ID_PREVIEW) + return true; + else + return false; + case ATOMISP_RUN_MODE_VIDEO: + if (!asd->continuous_mode->val) { + if (pipe_id == IA_CSS_PIPE_ID_VIDEO || + pipe_id == IA_CSS_PIPE_ID_YUVPP) + return true; + else + return false; + } + /* fall through to ATOMISP_RUN_MODE_SDV */ + case ATOMISP_RUN_MODE_SDV: + if (pipe_id == IA_CSS_PIPE_ID_CAPTURE || + pipe_id == IA_CSS_PIPE_ID_VIDEO) + return true; + else + return false; + } + + return false; +} + +static int __create_pipe(struct atomisp_sub_device *asd, + struct atomisp_stream_env *stream_env, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + struct ia_css_pipe_extra_config extra_config; + enum ia_css_err ret; + + if (pipe_id >= IA_CSS_PIPE_ID_NUM) + return -EINVAL; + + if (pipe_id != CSS_PIPE_ID_ACC && + !stream_env->pipe_configs[pipe_id].output_info[0].res.width) + return 0; + + if (pipe_id == CSS_PIPE_ID_ACC && + !stream_env->pipe_configs[pipe_id].acc_extension) + return 0; + + if (!is_pipe_valid_to_current_run_mode(asd, pipe_id)) + return 0; + + ia_css_pipe_extra_config_defaults(&extra_config); + + __apply_additional_pipe_config(asd, stream_env, pipe_id); + if (!memcmp(&extra_config, + &stream_env->pipe_extra_configs[pipe_id], + sizeof(extra_config))) + ret = ia_css_pipe_create( + &stream_env->pipe_configs[pipe_id], + &stream_env->pipes[pipe_id]); + else + ret = ia_css_pipe_create_extra( + &stream_env->pipe_configs[pipe_id], + &stream_env->pipe_extra_configs[pipe_id], + &stream_env->pipes[pipe_id]); + if (ret != IA_CSS_SUCCESS) + dev_err(isp->dev, "create pipe[%d] error.\n", pipe_id); + return ret; +} + +static int __create_pipes(struct atomisp_sub_device *asd) +{ + enum ia_css_err ret; + int i, j; + + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) { + for (j = 0; j < IA_CSS_PIPE_ID_NUM; j++) { + ret = __create_pipe(asd, &asd->stream_env[i], j); + if (ret != IA_CSS_SUCCESS) + break; + } + if (j < IA_CSS_PIPE_ID_NUM) + goto pipe_err; + } + return 0; +pipe_err: + for (; i >= 0; i--) { + for (j--; j >= 0; j--) { + if (asd->stream_env[i].pipes[j]) { + ia_css_pipe_destroy(asd->stream_env[i].pipes[j]); + asd->stream_env[i].pipes[j] = NULL; + } + } + j = IA_CSS_PIPE_ID_NUM; + } + return -EINVAL; +} + +void atomisp_create_pipes_stream(struct atomisp_sub_device *asd) +{ + __create_pipes(asd); + __create_streams(asd); +} + +int atomisp_css_update_stream(struct atomisp_sub_device *asd) +{ + int ret; + struct atomisp_device *isp = asd->isp; + + if (__destroy_streams(asd, true) != IA_CSS_SUCCESS) + dev_warn(isp->dev, "destroy stream failed.\n"); + + if (__destroy_pipes(asd, true) != IA_CSS_SUCCESS) + dev_warn(isp->dev, "destroy pipe failed.\n"); + + ret = __create_pipes(asd); + if (ret != IA_CSS_SUCCESS) { + dev_err(isp->dev, "create pipe failed %d.\n", ret); + return -EIO; + } + + ret = __create_streams(asd); + if (ret != IA_CSS_SUCCESS) { + dev_warn(isp->dev, "create stream failed %d.\n", ret); + __destroy_pipes(asd, true); + return -EIO; + } + + return 0; +} + +int atomisp_css_init(struct atomisp_device *isp) +{ + unsigned int mmu_base_addr; + int ret; + enum ia_css_err err; + + ret = hmm_get_mmu_base_addr(&mmu_base_addr); + if (ret) + return ret; + + /* Init ISP */ + err = ia_css_init(&isp->css_env.isp_css_env, NULL, + (uint32_t)mmu_base_addr, IA_CSS_IRQ_TYPE_PULSE); + if (err != IA_CSS_SUCCESS) { + dev_err(isp->dev, "css init failed --- bad firmware?\n"); + return -EINVAL; + } + ia_css_enable_isys_event_queue(true); + + isp->css_initialized = true; + dev_dbg(isp->dev, "sh_css_init success\n"); + + return 0; +} + +static inline int __set_css_print_env(struct atomisp_device *isp, int opt) +{ + int ret = 0; + + if (0 == opt) + isp->css_env.isp_css_env.print_env.debug_print = NULL; + else if (1 == opt) + isp->css_env.isp_css_env.print_env.debug_print = + atomisp_css2_dbg_ftrace_print; + else if (2 == opt) + isp->css_env.isp_css_env.print_env.debug_print = + atomisp_css2_dbg_print; + else + ret = -EINVAL; + + return ret; +} + +int atomisp_css_check_firmware_version(struct atomisp_device *isp) +{ + if (!sh_css_check_firmware_version((void *)isp->firmware->data)) { + dev_err(isp->dev, "Fw version check failed.\n"); + return -EINVAL; + } + return 0; +} + +int atomisp_css_load_firmware(struct atomisp_device *isp) +{ + enum ia_css_err err; + + /* set css env */ + isp->css_env.isp_css_fw.data = (void *)isp->firmware->data; + isp->css_env.isp_css_fw.bytes = isp->firmware->size; + + isp->css_env.isp_css_env.cpu_mem_env.alloc = atomisp_kernel_zalloc; + isp->css_env.isp_css_env.cpu_mem_env.free = atomisp_kernel_free; + + isp->css_env.isp_css_env.css_mem_env.alloc = atomisp_css2_mm_alloc; + isp->css_env.isp_css_env.css_mem_env.free = atomisp_css2_mm_free; + isp->css_env.isp_css_env.css_mem_env.load = atomisp_css2_mm_load; + isp->css_env.isp_css_env.css_mem_env.store = atomisp_css2_mm_store; + isp->css_env.isp_css_env.css_mem_env.set = atomisp_css2_mm_set; + isp->css_env.isp_css_env.css_mem_env.mmap = atomisp_css2_mm_mmap; + + isp->css_env.isp_css_env.hw_access_env.store_8 = + atomisp_css2_hw_store_8; + isp->css_env.isp_css_env.hw_access_env.store_16 = + atomisp_css2_hw_store_16; + isp->css_env.isp_css_env.hw_access_env.store_32 = + atomisp_css2_hw_store_32; + + isp->css_env.isp_css_env.hw_access_env.load_8 = atomisp_css2_hw_load_8; + isp->css_env.isp_css_env.hw_access_env.load_16 = + atomisp_css2_hw_load_16; + isp->css_env.isp_css_env.hw_access_env.load_32 = + atomisp_css2_hw_load_32; + + isp->css_env.isp_css_env.hw_access_env.load = atomisp_css2_hw_load; + isp->css_env.isp_css_env.hw_access_env.store = atomisp_css2_hw_store; + + __set_css_print_env(isp, dbg_func); + + isp->css_env.isp_css_env.print_env.error_print = atomisp_css2_err_print; + + /* load isp fw into ISP memory */ + err = ia_css_load_firmware(&isp->css_env.isp_css_env, + &isp->css_env.isp_css_fw); + if (err != IA_CSS_SUCCESS) { + dev_err(isp->dev, "css load fw failed.\n"); + return -EINVAL; + } + + return 0; +} + +void atomisp_css_unload_firmware(struct atomisp_device *isp) +{ + ia_css_unload_firmware(); +} + +void atomisp_css_uninit(struct atomisp_device *isp) +{ + struct atomisp_sub_device *asd; + unsigned int i; + + for (i = 0; i < isp->num_of_streams; i++) { + asd = &isp->asd[i]; + atomisp_isp_parameters_clean_up(&asd->params.config); + asd->params.css_update_params_needed = false; + } + + isp->css_initialized = false; + ia_css_uninit(); +} + +void atomisp_css_suspend(struct atomisp_device *isp) +{ + isp->css_initialized = false; + ia_css_uninit(); +} + +int atomisp_css_resume(struct atomisp_device *isp) +{ + unsigned int mmu_base_addr; + int ret; + + ret = hmm_get_mmu_base_addr(&mmu_base_addr); + if (ret) { + dev_err(isp->dev, "get base address error.\n"); + return -EINVAL; + } + + ret = ia_css_init(&isp->css_env.isp_css_env, NULL, + mmu_base_addr, IA_CSS_IRQ_TYPE_PULSE); + if (ret) { + dev_err(isp->dev, "re-init css failed.\n"); + return -EINVAL; + } + ia_css_enable_isys_event_queue(true); + + isp->css_initialized = true; + return 0; +} + +int atomisp_css_irq_translate(struct atomisp_device *isp, + unsigned int *infos) +{ + int err; + + err = ia_css_irq_translate(infos); + if (err != IA_CSS_SUCCESS) { + dev_warn(isp->dev, + "%s:failed to translate irq (err = %d,infos = %d)\n", + __func__, err, *infos); + return -EINVAL; + } + + return 0; +} + +void atomisp_css_rx_get_irq_info(enum ia_css_csi2_port port, + unsigned int *infos) +{ +#ifndef ISP2401_NEW_INPUT_SYSTEM + ia_css_isys_rx_get_irq_info(port, infos); +#else + *infos = 0; +#endif +} + +void atomisp_css_rx_clear_irq_info(enum ia_css_csi2_port port, + unsigned int infos) +{ +#ifndef ISP2401_NEW_INPUT_SYSTEM + ia_css_isys_rx_clear_irq_info(port, infos); +#endif +} + +int atomisp_css_irq_enable(struct atomisp_device *isp, + enum atomisp_css_irq_info info, bool enable) +{ + if (ia_css_irq_enable(info, enable) != IA_CSS_SUCCESS) { + dev_warn(isp->dev, "%s:Invalid irq info.\n", __func__); + return -EINVAL; + } + + return 0; +} + +void atomisp_css_init_struct(struct atomisp_sub_device *asd) +{ + int i, j; + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) { + asd->stream_env[i].stream = NULL; + for (j = 0; j < IA_CSS_PIPE_MODE_NUM; j++) { + asd->stream_env[i].pipes[j] = NULL; + asd->stream_env[i].update_pipe[j] = false; + ia_css_pipe_config_defaults( + &asd->stream_env[i].pipe_configs[j]); + ia_css_pipe_extra_config_defaults( + &asd->stream_env[i].pipe_extra_configs[j]); + } + ia_css_stream_config_defaults(&asd->stream_env[i].stream_config); + } +} + +int atomisp_q_video_buffer_to_css(struct atomisp_sub_device *asd, + struct videobuf_vmalloc_memory *vm_mem, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_buffer_type css_buf_type, + enum atomisp_css_pipe_id css_pipe_id) +{ + struct atomisp_stream_env *stream_env = &asd->stream_env[stream_id]; + struct ia_css_buffer css_buf = {0}; + enum ia_css_err err; + + css_buf.type = css_buf_type; + css_buf.data.frame = vm_mem->vaddr; + + err = ia_css_pipe_enqueue_buffer( + stream_env->pipes[css_pipe_id], &css_buf); + if (err != IA_CSS_SUCCESS) + return -EINVAL; + + return 0; +} + +int atomisp_q_metadata_buffer_to_css(struct atomisp_sub_device *asd, + struct atomisp_metadata_buf *metadata_buf, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_pipe_id css_pipe_id) +{ + struct atomisp_stream_env *stream_env = &asd->stream_env[stream_id]; + struct ia_css_buffer buffer = {0}; + struct atomisp_device *isp = asd->isp; + + buffer.type = IA_CSS_BUFFER_TYPE_METADATA; + buffer.data.metadata = metadata_buf->metadata; + if (ia_css_pipe_enqueue_buffer(stream_env->pipes[css_pipe_id], + &buffer)) { + dev_err(isp->dev, "failed to q meta data buffer\n"); + return -EINVAL; + } + + return 0; +} + +int atomisp_q_s3a_buffer_to_css(struct atomisp_sub_device *asd, + struct atomisp_s3a_buf *s3a_buf, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_pipe_id css_pipe_id) +{ + struct atomisp_stream_env *stream_env = &asd->stream_env[stream_id]; + struct ia_css_buffer buffer = {0}; + struct atomisp_device *isp = asd->isp; + + buffer.type = IA_CSS_BUFFER_TYPE_3A_STATISTICS; + buffer.data.stats_3a = s3a_buf->s3a_data; + if (ia_css_pipe_enqueue_buffer( + stream_env->pipes[css_pipe_id], + &buffer)) { + dev_dbg(isp->dev, "failed to q s3a stat buffer\n"); + return -EINVAL; + } + + return 0; +} + +int atomisp_q_dis_buffer_to_css(struct atomisp_sub_device *asd, + struct atomisp_dis_buf *dis_buf, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_pipe_id css_pipe_id) +{ + struct atomisp_stream_env *stream_env = &asd->stream_env[stream_id]; + struct ia_css_buffer buffer = {0}; + struct atomisp_device *isp = asd->isp; + + buffer.type = IA_CSS_BUFFER_TYPE_DIS_STATISTICS; + buffer.data.stats_dvs = dis_buf->dis_data; + if (ia_css_pipe_enqueue_buffer( + stream_env->pipes[css_pipe_id], + &buffer)) { + dev_dbg(isp->dev, "failed to q dvs stat buffer\n"); + return -EINVAL; + } + + return 0; +} + +void atomisp_css_mmu_invalidate_cache(void) +{ + ia_css_mmu_invalidate_cache(); +} + +void atomisp_css_mmu_invalidate_tlb(void) +{ + ia_css_mmu_invalidate_cache(); +} + +void atomisp_css_mmu_set_page_table_base_index(unsigned long base_index) +{ +} + +/* + * Check whether currently running MIPI buffer size fulfill + * the requirement of the stream to be run + */ +bool __need_realloc_mipi_buffer(struct atomisp_device *isp) +{ + unsigned int i; + + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd = &isp->asd[i]; + + if (asd->streaming != + ATOMISP_DEVICE_STREAMING_ENABLED) + continue; + if (asd->mipi_frame_size < isp->mipi_frame_size) + return true; + } + + return false; +} + +int atomisp_css_start(struct atomisp_sub_device *asd, + enum atomisp_css_pipe_id pipe_id, bool in_reset) +{ + struct atomisp_device *isp = asd->isp; + bool sp_is_started = false; + int ret = 0, i = 0; + if (in_reset) { + if (__destroy_streams(asd, true)) + dev_warn(isp->dev, "destroy stream failed.\n"); + + if (__destroy_pipes(asd, true)) + dev_warn(isp->dev, "destroy pipe failed.\n"); + + if (__create_pipes(asd)) { + dev_err(isp->dev, "create pipe error.\n"); + return -EINVAL; + } + if (__create_streams(asd)) { + dev_err(isp->dev, "create stream error.\n"); + ret = -EINVAL; + goto stream_err; + } + /* in_reset == true, extension firmwares are reloaded after the recovery */ + atomisp_acc_load_extensions(asd); + } + + /* + * For dual steam case, it is possible that: + * 1: for this stream, it is at the stage that: + * - after set_fmt is called + * - before stream on is called + * 2: for the other stream, the stream off is called which css reset + * has been done. + * + * Thus the stream created in set_fmt get destroyed and need to be + * recreated in the next stream on. + */ + if (asd->stream_prepared == false) { + if (__create_pipes(asd)) { + dev_err(isp->dev, "create pipe error.\n"); + return -EINVAL; + } + if (__create_streams(asd)) { + dev_err(isp->dev, "create stream error.\n"); + ret = -EINVAL; + goto stream_err; + } + } + /* + * SP can only be started one time + * if atomisp_subdev_streaming_count() tell there already has some + * subdev at streamming, then SP should already be started previously, + * so need to skip start sp procedure + */ + if (atomisp_streaming_count(isp)) { + dev_dbg(isp->dev, "skip start sp\n"); + } else { + if (!sh_css_hrt_system_is_idle()) + dev_err(isp->dev, "CSS HW not idle before starting SP\n"); + if (ia_css_start_sp() != IA_CSS_SUCCESS) { + dev_err(isp->dev, "start sp error.\n"); + ret = -EINVAL; + goto start_err; + } else { + sp_is_started = true; + } + } + + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) { + if (asd->stream_env[i].stream) { + if (ia_css_stream_start(asd->stream_env[i] + .stream) != IA_CSS_SUCCESS) { + dev_err(isp->dev, "stream[%d] start error.\n", i); + ret = -EINVAL; + goto start_err; + } else { + asd->stream_env[i].stream_state = CSS_STREAM_STARTED; + dev_dbg(isp->dev, "stream[%d] started.\n", i); + } + } + } + + return 0; + +start_err: + __destroy_streams(asd, true); +stream_err: + __destroy_pipes(asd, true); + + /* css 2.0 API limitation: ia_css_stop_sp() could be only called after + * destroy all pipes + */ + /* + * SP can not be stop if other streams are in use + */ + if ((atomisp_streaming_count(isp) == 0) && sp_is_started) + ia_css_stop_sp(); + + return ret; +} + +void atomisp_css_update_isp_params(struct atomisp_sub_device *asd) +{ + /* + * FIXME! + * for ISP2401 new input system, this api is under development. + * Calling it would cause kernel panic. + * + * VIED BZ: 1458 + * + * Check if it is Cherry Trail and also new input system + */ + if (asd->copy_mode) { + dev_warn(asd->isp->dev, + "%s: ia_css_stream_set_isp_config() not supported in copy mode!.\n", + __func__); + return; + } + + ia_css_stream_set_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &asd->params.config); + atomisp_isp_parameters_clean_up(&asd->params.config); +} + + +void atomisp_css_update_isp_params_on_pipe(struct atomisp_sub_device *asd, + struct ia_css_pipe *pipe) +{ + enum ia_css_err ret; + + if (!pipe) { + atomisp_css_update_isp_params(asd); + return; + } + + dev_dbg(asd->isp->dev, "%s: apply parameter for ia_css_frame %p with isp_config_id %d on pipe %p.\n", + __func__, asd->params.config.output_frame, + asd->params.config.isp_config_id, pipe); + + ret = ia_css_stream_set_isp_config_on_pipe( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &asd->params.config, pipe); + if (ret != IA_CSS_SUCCESS) + dev_warn(asd->isp->dev, "%s: ia_css_stream_set_isp_config_on_pipe failed %d\n", + __func__, ret); + atomisp_isp_parameters_clean_up(&asd->params.config); +} + +int atomisp_css_queue_buffer(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_pipe_id pipe_id, + enum atomisp_css_buffer_type buf_type, + struct atomisp_css_buffer *isp_css_buffer) +{ + if (ia_css_pipe_enqueue_buffer( + asd->stream_env[stream_id].pipes[pipe_id], + &isp_css_buffer->css_buffer) + != IA_CSS_SUCCESS) + return -EINVAL; + + return 0; +} + +int atomisp_css_dequeue_buffer(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_pipe_id pipe_id, + enum atomisp_css_buffer_type buf_type, + struct atomisp_css_buffer *isp_css_buffer) +{ + struct atomisp_device *isp = asd->isp; + enum ia_css_err err; + + err = ia_css_pipe_dequeue_buffer( + asd->stream_env[stream_id].pipes[pipe_id], + &isp_css_buffer->css_buffer); + if (err != IA_CSS_SUCCESS) { + dev_err(isp->dev, + "ia_css_pipe_dequeue_buffer failed: 0x%x\n", err); + return -EINVAL; + } + + return 0; +} + +int atomisp_css_allocate_stat_buffers(struct atomisp_sub_device *asd, + uint16_t stream_id, + struct atomisp_s3a_buf *s3a_buf, + struct atomisp_dis_buf *dis_buf, + struct atomisp_metadata_buf *md_buf) +{ + struct atomisp_device *isp = asd->isp; + struct atomisp_css_dvs_grid_info *dvs_grid_info = + atomisp_css_get_dvs_grid_info(&asd->params.curr_grid_info); + + if (s3a_buf && asd->params.curr_grid_info.s3a_grid.enable) { + void *s3a_ptr; + + s3a_buf->s3a_data = ia_css_isp_3a_statistics_allocate( + &asd->params.curr_grid_info.s3a_grid); + if (!s3a_buf->s3a_data) { + dev_err(isp->dev, "3a buf allocation failed.\n"); + return -EINVAL; + } + + s3a_ptr = hmm_vmap(s3a_buf->s3a_data->data_ptr, true); + s3a_buf->s3a_map = ia_css_isp_3a_statistics_map_allocate( + s3a_buf->s3a_data, s3a_ptr); + } + + if (dis_buf && dvs_grid_info && dvs_grid_info->enable) { + void *dvs_ptr; + + dis_buf->dis_data = ia_css_isp_dvs2_statistics_allocate( + dvs_grid_info); + if (!dis_buf->dis_data) { + dev_err(isp->dev, "dvs buf allocation failed.\n"); + if (s3a_buf) + ia_css_isp_3a_statistics_free(s3a_buf->s3a_data); + return -EINVAL; + } + + dvs_ptr = hmm_vmap(dis_buf->dis_data->data_ptr, true); + dis_buf->dvs_map = ia_css_isp_dvs_statistics_map_allocate( + dis_buf->dis_data, dvs_ptr); + } + + if (asd->stream_env[stream_id].stream_info. + metadata_info.size && md_buf) { + md_buf->metadata = ia_css_metadata_allocate( + &asd->stream_env[stream_id].stream_info.metadata_info); + if (!md_buf->metadata) { + if (s3a_buf) + ia_css_isp_3a_statistics_free(s3a_buf->s3a_data); + if (dis_buf) + ia_css_isp_dvs2_statistics_free(dis_buf->dis_data); + dev_err(isp->dev, "metadata buf allocation failed.\n"); + return -EINVAL; + } + md_buf->md_vptr = hmm_vmap(md_buf->metadata->address, false); + } + + return 0; +} + +void atomisp_css_free_3a_buffer(struct atomisp_s3a_buf *s3a_buf) +{ + if (s3a_buf->s3a_data) + hmm_vunmap(s3a_buf->s3a_data->data_ptr); + + ia_css_isp_3a_statistics_map_free(s3a_buf->s3a_map); + s3a_buf->s3a_map = NULL; + ia_css_isp_3a_statistics_free(s3a_buf->s3a_data); +} + +void atomisp_css_free_dis_buffer(struct atomisp_dis_buf *dis_buf) +{ + if (dis_buf->dis_data) + hmm_vunmap(dis_buf->dis_data->data_ptr); + + ia_css_isp_dvs_statistics_map_free(dis_buf->dvs_map); + dis_buf->dvs_map = NULL; + ia_css_isp_dvs2_statistics_free(dis_buf->dis_data); +} + +void atomisp_css_free_metadata_buffer(struct atomisp_metadata_buf *metadata_buf) +{ + if (metadata_buf->md_vptr) { + hmm_vunmap(metadata_buf->metadata->address); + metadata_buf->md_vptr = NULL; + } + ia_css_metadata_free(metadata_buf->metadata); +} + +void atomisp_css_free_stat_buffers(struct atomisp_sub_device *asd) +{ + struct atomisp_s3a_buf *s3a_buf, *_s3a_buf; + struct atomisp_dis_buf *dis_buf, *_dis_buf; + struct atomisp_metadata_buf *md_buf, *_md_buf; + struct atomisp_css_dvs_grid_info *dvs_grid_info = + atomisp_css_get_dvs_grid_info(&asd->params.curr_grid_info); + unsigned int i; + + /* 3A statistics use vmalloc, DIS use kmalloc */ + if (dvs_grid_info && dvs_grid_info->enable) { + ia_css_dvs2_coefficients_free(asd->params.css_param.dvs2_coeff); + ia_css_dvs2_statistics_free(asd->params.dvs_stat); + asd->params.css_param.dvs2_coeff = NULL; + asd->params.dvs_stat = NULL; + asd->params.dvs_hor_proj_bytes = 0; + asd->params.dvs_ver_proj_bytes = 0; + asd->params.dvs_hor_coef_bytes = 0; + asd->params.dvs_ver_coef_bytes = 0; + asd->params.dis_proj_data_valid = false; + list_for_each_entry_safe(dis_buf, _dis_buf, + &asd->dis_stats, list) { + atomisp_css_free_dis_buffer(dis_buf); + list_del(&dis_buf->list); + kfree(dis_buf); + } + list_for_each_entry_safe(dis_buf, _dis_buf, + &asd->dis_stats_in_css, list) { + atomisp_css_free_dis_buffer(dis_buf); + list_del(&dis_buf->list); + kfree(dis_buf); + } + } + if (asd->params.curr_grid_info.s3a_grid.enable) { + ia_css_3a_statistics_free(asd->params.s3a_user_stat); + asd->params.s3a_user_stat = NULL; + asd->params.s3a_output_bytes = 0; + list_for_each_entry_safe(s3a_buf, _s3a_buf, + &asd->s3a_stats, list) { + atomisp_css_free_3a_buffer(s3a_buf); + list_del(&s3a_buf->list); + kfree(s3a_buf); + } + list_for_each_entry_safe(s3a_buf, _s3a_buf, + &asd->s3a_stats_in_css, list) { + atomisp_css_free_3a_buffer(s3a_buf); + list_del(&s3a_buf->list); + kfree(s3a_buf); + } + list_for_each_entry_safe(s3a_buf, _s3a_buf, + &asd->s3a_stats_ready, list) { + atomisp_css_free_3a_buffer(s3a_buf); + list_del(&s3a_buf->list); + kfree(s3a_buf); + } + } + + if (asd->params.css_param.dvs_6axis) { + ia_css_dvs2_6axis_config_free(asd->params.css_param.dvs_6axis); + asd->params.css_param.dvs_6axis = NULL; + } + + for (i = 0; i < ATOMISP_METADATA_TYPE_NUM; i++) { + list_for_each_entry_safe(md_buf, _md_buf, + &asd->metadata[i], list) { + atomisp_css_free_metadata_buffer(md_buf); + list_del(&md_buf->list); + kfree(md_buf); + } + list_for_each_entry_safe(md_buf, _md_buf, + &asd->metadata_in_css[i], list) { + atomisp_css_free_metadata_buffer(md_buf); + list_del(&md_buf->list); + kfree(md_buf); + } + list_for_each_entry_safe(md_buf, _md_buf, + &asd->metadata_ready[i], list) { + atomisp_css_free_metadata_buffer(md_buf); + list_del(&md_buf->list); + kfree(md_buf); + } + } + asd->params.metadata_width_size = 0; + atomisp_free_metadata_output_buf(asd); +} + +int atomisp_css_get_grid_info(struct atomisp_sub_device *asd, + enum atomisp_css_pipe_id pipe_id, + int source_pad) +{ + struct ia_css_pipe_info p_info; + struct ia_css_grid_info old_info; + struct atomisp_device *isp = asd->isp; + int stream_index = atomisp_source_pad_to_stream_id(asd, source_pad); + int md_width = asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]. + stream_config.metadata_config.resolution.width; + + memset(&p_info, 0, sizeof(struct ia_css_pipe_info)); + memset(&old_info, 0, sizeof(struct ia_css_grid_info)); + + if (ia_css_pipe_get_info( + asd->stream_env[stream_index].pipes[pipe_id], + &p_info) != IA_CSS_SUCCESS) { + dev_err(isp->dev, "ia_css_pipe_get_info failed\n"); + return -EINVAL; + } + + memcpy(&old_info, &asd->params.curr_grid_info, + sizeof(struct ia_css_grid_info)); + memcpy(&asd->params.curr_grid_info, &p_info.grid_info, + sizeof(struct ia_css_grid_info)); + /* + * Record which css pipe enables s3a_grid. + * Currently would have one css pipe that need it + */ + if (asd->params.curr_grid_info.s3a_grid.enable) { + if (asd->params.s3a_enabled_pipe != CSS_PIPE_ID_NUM) + dev_dbg(isp->dev, "css pipe %d enabled s3a grid replaced by: %d.\n", + asd->params.s3a_enabled_pipe, pipe_id); + asd->params.s3a_enabled_pipe = pipe_id; + } + + /* If the grid info has not changed and the buffers for 3A and + * DIS statistics buffers are allocated or buffer size would be zero + * then no need to do anything. */ + if (((!memcmp(&old_info, &asd->params.curr_grid_info, sizeof(old_info)) + && asd->params.s3a_user_stat && asd->params.dvs_stat) + || asd->params.curr_grid_info.s3a_grid.width == 0 + || asd->params.curr_grid_info.s3a_grid.height == 0) + && asd->params.metadata_width_size == md_width) { + dev_dbg(isp->dev, + "grid info change escape. memcmp=%d, s3a_user_stat=%d," + "dvs_stat=%d, s3a.width=%d, s3a.height=%d, metadata width =%d\n", + !memcmp(&old_info, &asd->params.curr_grid_info, + sizeof(old_info)), + !!asd->params.s3a_user_stat, !!asd->params.dvs_stat, + asd->params.curr_grid_info.s3a_grid.width, + asd->params.curr_grid_info.s3a_grid.height, + asd->params.metadata_width_size); + return -EINVAL; + } + asd->params.metadata_width_size = md_width; + + return 0; +} + +int atomisp_alloc_3a_output_buf(struct atomisp_sub_device *asd) +{ + if (!asd->params.curr_grid_info.s3a_grid.width || + !asd->params.curr_grid_info.s3a_grid.height) + return 0; + + asd->params.s3a_user_stat = ia_css_3a_statistics_allocate( + &asd->params.curr_grid_info.s3a_grid); + if (!asd->params.s3a_user_stat) + return -ENOMEM; + /* 3A statistics. These can be big, so we use vmalloc. */ + asd->params.s3a_output_bytes = + asd->params.curr_grid_info.s3a_grid.width * + asd->params.curr_grid_info.s3a_grid.height * + sizeof(*asd->params.s3a_user_stat->data); + + return 0; +} + +int atomisp_alloc_dis_coef_buf(struct atomisp_sub_device *asd) +{ + struct atomisp_css_dvs_grid_info *dvs_grid = + atomisp_css_get_dvs_grid_info(&asd->params.curr_grid_info); + + if (!dvs_grid) + return 0; + + if (!dvs_grid->enable) { + dev_dbg(asd->isp->dev, "%s: dvs_grid not enabled.\n", __func__); + return 0; + } + + /* DIS coefficients. */ + asd->params.css_param.dvs2_coeff = ia_css_dvs2_coefficients_allocate( + dvs_grid); + if (!asd->params.css_param.dvs2_coeff) + return -ENOMEM; + + asd->params.dvs_hor_coef_bytes = dvs_grid->num_hor_coefs * + sizeof(*asd->params.css_param.dvs2_coeff->hor_coefs.odd_real); + + asd->params.dvs_ver_coef_bytes = dvs_grid->num_ver_coefs * + sizeof(*asd->params.css_param.dvs2_coeff->ver_coefs.odd_real); + + /* DIS projections. */ + asd->params.dis_proj_data_valid = false; + asd->params.dvs_stat = ia_css_dvs2_statistics_allocate(dvs_grid); + if (!asd->params.dvs_stat) + return -ENOMEM; + + asd->params.dvs_hor_proj_bytes = + dvs_grid->aligned_height * dvs_grid->aligned_width * + sizeof(*asd->params.dvs_stat->hor_prod.odd_real); + + asd->params.dvs_ver_proj_bytes = + dvs_grid->aligned_height * dvs_grid->aligned_width * + sizeof(*asd->params.dvs_stat->ver_prod.odd_real); + + return 0; +} + +int atomisp_alloc_metadata_output_buf(struct atomisp_sub_device *asd) +{ +#ifndef ISP2401 + int i; /* Coverity CID 298003 - index var must be signed */ +#else + int i; +#endif + + /* We allocate the cpu-side buffer used for communication with user + * space */ + for (i = 0; i < ATOMISP_METADATA_TYPE_NUM; i++) { + asd->params.metadata_user[i] = atomisp_kernel_malloc( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]. + stream_info.metadata_info.size); + if (!asd->params.metadata_user[i]) { + while (--i >= 0) { + atomisp_kernel_free(asd->params.metadata_user[i]); + asd->params.metadata_user[i] = NULL; + } + return -ENOMEM; + } + } + + return 0; +} + +void atomisp_free_metadata_output_buf(struct atomisp_sub_device *asd) +{ + unsigned int i; + + for (i = 0; i < ATOMISP_METADATA_TYPE_NUM; i++) { + if (asd->params.metadata_user[i]) { + atomisp_kernel_free(asd->params.metadata_user[i]); + asd->params.metadata_user[i] = NULL; + } + } +} + +void atomisp_css_get_dis_statistics(struct atomisp_sub_device *asd, + struct atomisp_css_buffer *isp_css_buffer, + struct ia_css_isp_dvs_statistics_map *dvs_map) +{ + if (asd->params.dvs_stat) { + if (dvs_map) + ia_css_translate_dvs2_statistics( + asd->params.dvs_stat, dvs_map); + else + ia_css_get_dvs2_statistics(asd->params.dvs_stat, + isp_css_buffer->css_buffer.data.stats_dvs); + + } +} + +int atomisp_css_dequeue_event(struct atomisp_css_event *current_event) +{ + if (ia_css_dequeue_event(¤t_event->event) != IA_CSS_SUCCESS) + return -EINVAL; + + return 0; +} + +void atomisp_css_temp_pipe_to_pipe_id(struct atomisp_sub_device *asd, + struct atomisp_css_event *current_event) +{ + /* + * FIXME! + * Pipe ID reported in CSS event is not correct for new system's + * copy pipe. + * VIED BZ: 1463 + */ + ia_css_temp_pipe_to_pipe_id(current_event->event.pipe, + ¤t_event->pipe); + if (asd && asd->copy_mode && + current_event->pipe == IA_CSS_PIPE_ID_CAPTURE) + current_event->pipe = IA_CSS_PIPE_ID_COPY; +} + +int atomisp_css_isys_set_resolution(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + struct v4l2_mbus_framefmt *ffmt, + int isys_stream) +{ + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + + if (isys_stream >= IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH) + return -EINVAL; + + s_config->isys_config[isys_stream].input_res.width = ffmt->width; + s_config->isys_config[isys_stream].input_res.height = ffmt->height; + return 0; +} + +int atomisp_css_input_set_resolution(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + struct v4l2_mbus_framefmt *ffmt) +{ + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + + s_config->input_config.input_res.width = ffmt->width; + s_config->input_config.input_res.height = ffmt->height; + return 0; +} + +void atomisp_css_input_set_binning_factor(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + unsigned int bin_factor) +{ + asd->stream_env[stream_id] + .stream_config.sensor_binning_factor = bin_factor; +} + +void atomisp_css_input_set_bayer_order(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_bayer_order bayer_order) +{ + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + s_config->input_config.bayer_order = bayer_order; +} + +void atomisp_css_isys_set_link(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + int link, + int isys_stream) +{ + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + + s_config->isys_config[isys_stream].linked_isys_stream_id = link; +} + +void atomisp_css_isys_set_valid(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + bool valid, + int isys_stream) +{ + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + + s_config->isys_config[isys_stream].valid = valid; +} + +void atomisp_css_isys_set_format(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_stream_format format, + int isys_stream) +{ + + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + + s_config->isys_config[isys_stream].format = format; +} + +void atomisp_css_input_set_format(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_stream_format format) +{ + + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + + s_config->input_config.format = format; +} + +int atomisp_css_set_default_isys_config(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + struct v4l2_mbus_framefmt *ffmt) +{ + int i; + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + /* + * Set all isys configs to not valid. + * Currently we support only one stream per channel + */ + for (i = IA_CSS_STREAM_ISYS_STREAM_0; + i < IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH; i++) + s_config->isys_config[i].valid = false; + + atomisp_css_isys_set_resolution(asd, stream_id, ffmt, + IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX); + atomisp_css_isys_set_format(asd, stream_id, + s_config->input_config.format, + IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX); + atomisp_css_isys_set_link(asd, stream_id, NO_LINK, + IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX); + atomisp_css_isys_set_valid(asd, stream_id, true, + IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX); + + return 0; +} + +int atomisp_css_isys_two_stream_cfg(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_stream_format input_format) +{ + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_1].input_res.width = + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_0].input_res.width; + + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_1].input_res.height = + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_0].input_res.height / 2; + + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_1].linked_isys_stream_id + = IA_CSS_STREAM_ISYS_STREAM_0; + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_0].format = + IA_CSS_STREAM_FORMAT_USER_DEF1; + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_1].format = + IA_CSS_STREAM_FORMAT_USER_DEF2; + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_1].valid = true; + return 0; +} + +void atomisp_css_isys_two_stream_cfg_update_stream1( + struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_stream_format input_format, + unsigned int width, unsigned int height) +{ + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_0].input_res.width = + width; + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_0].input_res.height = + height; + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_0].format = + input_format; + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_0].valid = true; +} + +void atomisp_css_isys_two_stream_cfg_update_stream2( + struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_stream_format input_format, + unsigned int width, unsigned int height) +{ + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_1].input_res.width = + width; + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_1].input_res.height = + height; + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_1].linked_isys_stream_id + = IA_CSS_STREAM_ISYS_STREAM_0; + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_1].format = + input_format; + s_config->isys_config[IA_CSS_STREAM_ISYS_STREAM_1].valid = true; +} + +int atomisp_css_input_set_effective_resolution( + struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + unsigned int width, unsigned int height) +{ + struct ia_css_stream_config *s_config = + &asd->stream_env[stream_id].stream_config; + s_config->input_config.effective_res.width = width; + s_config->input_config.effective_res.height = height; + return 0; +} + +void atomisp_css_video_set_dis_envelope(struct atomisp_sub_device *asd, + unsigned int dvs_w, unsigned int dvs_h) +{ + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .pipe_configs[IA_CSS_PIPE_ID_VIDEO].dvs_envelope.width = dvs_w; + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .pipe_configs[IA_CSS_PIPE_ID_VIDEO].dvs_envelope.height = dvs_h; +} + +void atomisp_css_input_set_two_pixels_per_clock( + struct atomisp_sub_device *asd, + bool two_ppc) +{ + int i; + + if (asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .stream_config.pixels_per_clock == (two_ppc ? 2 : 1)) + return; + + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .stream_config.pixels_per_clock = (two_ppc ? 2 : 1); + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .update_pipe[i] = true; +} + +void atomisp_css_enable_raw_binning(struct atomisp_sub_device *asd, + bool enable) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + unsigned int pipe; + + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) + pipe = IA_CSS_PIPE_ID_VIDEO; + else + pipe = IA_CSS_PIPE_ID_PREVIEW; + + stream_env->pipe_extra_configs[pipe].enable_raw_binning = enable; + stream_env->update_pipe[pipe] = true; + if (enable) + stream_env->pipe_configs[pipe].output_info[0].padded_width = + stream_env->stream_config.input_config.effective_res.width; +} + +void atomisp_css_enable_dz(struct atomisp_sub_device *asd, bool enable) +{ + int i; + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .pipe_configs[i].enable_dz = enable; +} + +void atomisp_css_capture_set_mode(struct atomisp_sub_device *asd, + enum atomisp_css_capture_mode mode) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + + if (stream_env->pipe_configs[IA_CSS_PIPE_ID_CAPTURE] + .default_capture_config.mode == mode) + return; + + stream_env->pipe_configs[IA_CSS_PIPE_ID_CAPTURE]. + default_capture_config.mode = mode; + stream_env->update_pipe[IA_CSS_PIPE_ID_CAPTURE] = true; +} + +void atomisp_css_input_set_mode(struct atomisp_sub_device *asd, + enum atomisp_css_input_mode mode) +{ + int i; + struct atomisp_device *isp = asd->isp; + unsigned int size_mem_words; + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) + asd->stream_env[i].stream_config.mode = mode; + + if (isp->inputs[asd->input_curr].type == TEST_PATTERN) { + struct ia_css_stream_config *s_config = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream_config; + s_config->mode = IA_CSS_INPUT_MODE_TPG; + s_config->source.tpg.mode = IA_CSS_TPG_MODE_CHECKERBOARD; + s_config->source.tpg.x_mask = (1 << 4) - 1; + s_config->source.tpg.x_delta = -2; + s_config->source.tpg.y_mask = (1 << 4) - 1; + s_config->source.tpg.y_delta = 3; + s_config->source.tpg.xy_mask = (1 << 8) - 1; + return; + } + + if (mode != IA_CSS_INPUT_MODE_BUFFERED_SENSOR) + return; + + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) { + /* + * TODO: sensor needs to export the embedded_data_size_words + * information to atomisp for each setting. + * Here using a large safe value. + */ + struct ia_css_stream_config *s_config = + &asd->stream_env[i].stream_config; + + if (s_config->input_config.input_res.width == 0) + continue; + + if (ia_css_mipi_frame_calculate_size( + s_config->input_config.input_res.width, + s_config->input_config.input_res.height, + s_config->input_config.format, + true, + 0x13000, + &size_mem_words) != IA_CSS_SUCCESS) { + if (intel_mid_identify_cpu() == + INTEL_MID_CPU_CHIP_TANGIER) + size_mem_words = CSS_MIPI_FRAME_BUFFER_SIZE_2; + else + size_mem_words = CSS_MIPI_FRAME_BUFFER_SIZE_1; + dev_warn(asd->isp->dev, + "ia_css_mipi_frame_calculate_size failed," + "applying pre-defined MIPI buffer size %u.\n", + size_mem_words); + } + s_config->mipi_buffer_config.size_mem_words = size_mem_words; + s_config->mipi_buffer_config.nof_mipi_buffers = 2; + } +} + +void atomisp_css_capture_enable_online(struct atomisp_sub_device *asd, + unsigned short stream_index, bool enable) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[stream_index]; + + if (stream_env->stream_config.online == !!enable) + return; + + stream_env->stream_config.online = !!enable; + stream_env->update_pipe[IA_CSS_PIPE_ID_CAPTURE] = true; +} + +void atomisp_css_preview_enable_online(struct atomisp_sub_device *asd, + unsigned short stream_index, bool enable) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[stream_index]; + int i; + + if (stream_env->stream_config.online != !!enable) { + stream_env->stream_config.online = !!enable; + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) + stream_env->update_pipe[i] = true; + } +} + +void atomisp_css_video_enable_online(struct atomisp_sub_device *asd, + bool enable) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_VIDEO]; + int i; + + if (stream_env->stream_config.online != enable) { + stream_env->stream_config.online = enable; + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) + stream_env->update_pipe[i] = true; + } +} + +void atomisp_css_enable_continuous(struct atomisp_sub_device *asd, + bool enable) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + int i; + + /* + * To SOC camera, there is only one YUVPP pipe in any case + * including ZSL/SDV/continuous viewfinder, so always set + * stream_config.continuous to 0. + */ + if (ATOMISP_USE_YUVPP(asd)) { + stream_env->stream_config.continuous = 0; + stream_env->stream_config.online = 1; + return; + } + + if (stream_env->stream_config.continuous != !!enable) { + stream_env->stream_config.continuous = !!enable; + stream_env->stream_config.pack_raw_pixels = true; + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) + stream_env->update_pipe[i] = true; + } +} + +void atomisp_css_enable_cvf(struct atomisp_sub_device *asd, + bool enable) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + int i; + + if (stream_env->stream_config.disable_cont_viewfinder != !enable) { + stream_env->stream_config.disable_cont_viewfinder = !enable; + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) + stream_env->update_pipe[i] = true; + } +} + +int atomisp_css_input_configure_port( + struct atomisp_sub_device *asd, + mipi_port_ID_t port, + unsigned int num_lanes, + unsigned int timeout, + unsigned int mipi_freq, + enum atomisp_css_stream_format metadata_format, + unsigned int metadata_width, + unsigned int metadata_height) +{ + int i; + struct atomisp_stream_env *stream_env; + /* + * Calculate rx_count as follows: + * Input: mipi_freq : CSI-2 bus frequency in Hz + * UI = 1 / (2 * mipi_freq) : period of one bit on the bus + * min = 85e-9 + 6 * UI : Limits for rx_count in seconds + * max = 145e-9 + 10 * UI + * rxcount0 = min / (4 / mipi_freq) : convert seconds to byte clocks + * rxcount = rxcount0 - 2 : adjust for better results + * The formula below is simplified version of the above with + * 10-bit fixed points for improved accuracy. + */ + const unsigned int rxcount = + min(((mipi_freq / 46000) - 1280) >> 10, 0xffU) * 0x01010101U; + + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) { + stream_env = &asd->stream_env[i]; + stream_env->stream_config.source.port.port = port; + stream_env->stream_config.source.port.num_lanes = num_lanes; + stream_env->stream_config.source.port.timeout = timeout; + if (mipi_freq) + stream_env->stream_config.source.port.rxcount = rxcount; + stream_env->stream_config. + metadata_config.data_type = metadata_format; + stream_env->stream_config. + metadata_config.resolution.width = metadata_width; + stream_env->stream_config. + metadata_config.resolution.height = metadata_height; + } + + return 0; +} + +int atomisp_css_frame_allocate(struct atomisp_css_frame **frame, + unsigned int width, unsigned int height, + enum atomisp_css_frame_format format, + unsigned int padded_width, + unsigned int raw_bit_depth) +{ + if (ia_css_frame_allocate(frame, width, height, format, + padded_width, raw_bit_depth) != IA_CSS_SUCCESS) + return -ENOMEM; + + return 0; +} + +int atomisp_css_frame_allocate_from_info(struct atomisp_css_frame **frame, + const struct atomisp_css_frame_info *info) +{ + if (ia_css_frame_allocate_from_info(frame, info) != IA_CSS_SUCCESS) + return -ENOMEM; + + return 0; +} + +void atomisp_css_frame_free(struct atomisp_css_frame *frame) +{ + ia_css_frame_free(frame); +} + +int atomisp_css_frame_map(struct atomisp_css_frame **frame, + const struct atomisp_css_frame_info *info, + const void *data, uint16_t attribute, + void *context) +{ + if (ia_css_frame_map(frame, info, data, attribute, context) + != IA_CSS_SUCCESS) + return -ENOMEM; + + return 0; +} + +int atomisp_css_set_black_frame(struct atomisp_sub_device *asd, + const struct atomisp_css_frame *raw_black_frame) +{ + if (sh_css_set_black_frame( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + raw_black_frame) != IA_CSS_SUCCESS) + return -ENOMEM; + + return 0; +} + +int atomisp_css_allocate_continuous_frames(bool init_time, + struct atomisp_sub_device *asd) +{ + if (ia_css_alloc_continuous_frame_remain( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) + != IA_CSS_SUCCESS) + return -EINVAL; + return 0; +} + +void atomisp_css_update_continuous_frames(struct atomisp_sub_device *asd) +{ + ia_css_update_continuous_frames( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream); +} + +int atomisp_css_stop(struct atomisp_sub_device *asd, + enum atomisp_css_pipe_id pipe_id, bool in_reset) +{ + struct atomisp_device *isp = asd->isp; + struct atomisp_s3a_buf *s3a_buf; + struct atomisp_dis_buf *dis_buf; + struct atomisp_metadata_buf *md_buf; + unsigned long irqflags; + unsigned int i; + + /* if is called in atomisp_reset(), force destroy stream */ + if (__destroy_streams(asd, true)) + dev_err(isp->dev, "destroy stream failed.\n"); + + /* if is called in atomisp_reset(), force destroy all pipes */ + if (__destroy_pipes(asd, true)) + dev_err(isp->dev, "destroy pipes failed.\n"); + + atomisp_init_raw_buffer_bitmap(asd); + + /* + * SP can not be stop if other streams are in use + */ + if (atomisp_streaming_count(isp) == 0) + ia_css_stop_sp(); + + if (!in_reset) { + struct atomisp_stream_env *stream_env; + int i, j; + for (i = 0; i < ATOMISP_INPUT_STREAM_NUM; i++) { + stream_env = &asd->stream_env[i]; + for (j = 0; j < IA_CSS_PIPE_ID_NUM; j++) { + ia_css_pipe_config_defaults( + &stream_env->pipe_configs[j]); + ia_css_pipe_extra_config_defaults( + &stream_env->pipe_extra_configs[j]); + } + ia_css_stream_config_defaults( + &stream_env->stream_config); + } + atomisp_isp_parameters_clean_up(&asd->params.config); + asd->params.css_update_params_needed = false; + } + + /* move stats buffers to free queue list */ + while (!list_empty(&asd->s3a_stats_in_css)) { + s3a_buf = list_entry(asd->s3a_stats_in_css.next, + struct atomisp_s3a_buf, list); + list_del(&s3a_buf->list); + list_add_tail(&s3a_buf->list, &asd->s3a_stats); + } + while (!list_empty(&asd->s3a_stats_ready)) { + s3a_buf = list_entry(asd->s3a_stats_ready.next, + struct atomisp_s3a_buf, list); + list_del(&s3a_buf->list); + list_add_tail(&s3a_buf->list, &asd->s3a_stats); + } + + spin_lock_irqsave(&asd->dis_stats_lock, irqflags); + while (!list_empty(&asd->dis_stats_in_css)) { + dis_buf = list_entry(asd->dis_stats_in_css.next, + struct atomisp_dis_buf, list); + list_del(&dis_buf->list); + list_add_tail(&dis_buf->list, &asd->dis_stats); + } + asd->params.dis_proj_data_valid = false; + spin_unlock_irqrestore(&asd->dis_stats_lock, irqflags); + + for (i = 0; i < ATOMISP_METADATA_TYPE_NUM; i++) { + while (!list_empty(&asd->metadata_in_css[i])) { + md_buf = list_entry(asd->metadata_in_css[i].next, + struct atomisp_metadata_buf, list); + list_del(&md_buf->list); + list_add_tail(&md_buf->list, &asd->metadata[i]); + } + while (!list_empty(&asd->metadata_ready[i])) { + md_buf = list_entry(asd->metadata_ready[i].next, + struct atomisp_metadata_buf, list); + list_del(&md_buf->list); + list_add_tail(&md_buf->list, &asd->metadata[i]); + } + } + + atomisp_flush_params_queue(&asd->video_out_capture); + atomisp_flush_params_queue(&asd->video_out_vf); + atomisp_flush_params_queue(&asd->video_out_preview); + atomisp_flush_params_queue(&asd->video_out_video_capture); + atomisp_free_css_parameters(&asd->params.css_param); + memset(&asd->params.css_param, 0, sizeof(asd->params.css_param)); + return 0; +} + +int atomisp_css_continuous_set_num_raw_frames( + struct atomisp_sub_device *asd, + int num_frames) +{ + if (asd->enable_raw_buffer_lock->val) { + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .stream_config.init_num_cont_raw_buf = + ATOMISP_CSS2_NUM_OFFLINE_INIT_CONTINUOUS_FRAMES_LOCK_EN; + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO && + asd->params.video_dis_en) + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .stream_config.init_num_cont_raw_buf += + ATOMISP_CSS2_NUM_DVS_FRAME_DELAY; + } else { + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .stream_config.init_num_cont_raw_buf = + ATOMISP_CSS2_NUM_OFFLINE_INIT_CONTINUOUS_FRAMES; + } + + if (asd->params.video_dis_en) + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .stream_config.init_num_cont_raw_buf += + ATOMISP_CSS2_NUM_DVS_FRAME_DELAY; + + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .stream_config.target_num_cont_raw_buf = num_frames; + return 0; +} + +void atomisp_css_disable_vf_pp(struct atomisp_sub_device *asd, + bool disable) +{ + int i; + + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .pipe_extra_configs[i].disable_vf_pp = !!disable; +} + +static enum ia_css_pipe_mode __pipe_id_to_pipe_mode( + struct atomisp_sub_device *asd, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + struct camera_mipi_info *mipi_info = atomisp_to_sensor_mipi_info( + isp->inputs[asd->input_curr].camera); + + switch (pipe_id) { + case IA_CSS_PIPE_ID_COPY: + /* Currently only YUVPP mode supports YUV420_Legacy format. + * Revert this when other pipe modes can support + * YUV420_Legacy format. + */ + if (mipi_info && mipi_info->input_format == + ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY) + return IA_CSS_PIPE_MODE_YUVPP; + return IA_CSS_PIPE_MODE_COPY; + case IA_CSS_PIPE_ID_PREVIEW: + return IA_CSS_PIPE_MODE_PREVIEW; + case IA_CSS_PIPE_ID_CAPTURE: + return IA_CSS_PIPE_MODE_CAPTURE; + case IA_CSS_PIPE_ID_VIDEO: + return IA_CSS_PIPE_MODE_VIDEO; + case IA_CSS_PIPE_ID_ACC: + return IA_CSS_PIPE_MODE_ACC; + case IA_CSS_PIPE_ID_YUVPP: + return IA_CSS_PIPE_MODE_YUVPP; + default: + WARN_ON(1); + return IA_CSS_PIPE_MODE_PREVIEW; + } + +} + +static void __configure_output(struct atomisp_sub_device *asd, + unsigned int stream_index, + unsigned int width, unsigned int height, + unsigned int min_width, + enum ia_css_frame_format format, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + struct atomisp_stream_env *stream_env = + &asd->stream_env[stream_index]; + struct ia_css_stream_config *s_config = &stream_env->stream_config; + + stream_env->pipe_configs[pipe_id].mode = + __pipe_id_to_pipe_mode(asd, pipe_id); + stream_env->update_pipe[pipe_id] = true; + + stream_env->pipe_configs[pipe_id].output_info[0].res.width = width; + stream_env->pipe_configs[pipe_id].output_info[0].res.height = height; + stream_env->pipe_configs[pipe_id].output_info[0].format = format; + stream_env->pipe_configs[pipe_id].output_info[0].padded_width = min_width; + + /* isp binary 2.2 specific setting*/ + if (width > s_config->input_config.effective_res.width || + height > s_config->input_config.effective_res.height) { + s_config->input_config.effective_res.width = width; + s_config->input_config.effective_res.height = height; + } + + dev_dbg(isp->dev, "configuring pipe[%d] output info w=%d.h=%d.f=%d.\n", + pipe_id, width, height, format); +} + +static void __configure_video_preview_output(struct atomisp_sub_device *asd, + unsigned int stream_index, + unsigned int width, unsigned int height, + unsigned int min_width, + enum ia_css_frame_format format, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + struct atomisp_stream_env *stream_env = + &asd->stream_env[stream_index]; + struct ia_css_frame_info *css_output_info; + struct ia_css_stream_config *stream_config = &stream_env->stream_config; + + stream_env->pipe_configs[pipe_id].mode = + __pipe_id_to_pipe_mode(asd, pipe_id); + stream_env->update_pipe[pipe_id] = true; + + /* + * second_output will be as video main output in SDV mode + * with SOC camera. output will be as video main output in + * normal video mode. + */ + if (asd->continuous_mode->val) + css_output_info = &stream_env->pipe_configs[pipe_id]. + output_info[ATOMISP_CSS_OUTPUT_SECOND_INDEX]; + else + css_output_info = &stream_env->pipe_configs[pipe_id]. + output_info[ATOMISP_CSS_OUTPUT_DEFAULT_INDEX]; + + css_output_info->res.width = width; + css_output_info->res.height = height; + css_output_info->format = format; + css_output_info->padded_width = min_width; + + /* isp binary 2.2 specific setting*/ + if (width > stream_config->input_config.effective_res.width || + height > stream_config->input_config.effective_res.height) { + stream_config->input_config.effective_res.width = width; + stream_config->input_config.effective_res.height = height; + } + + dev_dbg(isp->dev, "configuring pipe[%d] output info w=%d.h=%d.f=%d.\n", + pipe_id, width, height, format); +} + +/* + * For CSS2.1, capture pipe uses capture_pp_in_res to configure yuv + * downscaling input resolution. + */ +static void __configure_capture_pp_input(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + struct ia_css_stream_config *stream_config = &stream_env->stream_config; + struct ia_css_pipe_config *pipe_configs = + &stream_env->pipe_configs[pipe_id]; + struct ia_css_pipe_extra_config *pipe_extra_configs = + &stream_env->pipe_extra_configs[pipe_id]; + unsigned int hor_ds_factor = 0, ver_ds_factor = 0; +#define CEIL_DIV(a, b) ((b) ? ((a) + (b) - 1) / (b) : 0) + + if (width == 0 && height == 0) + return; + + if (width * 9 / 10 < pipe_configs->output_info[0].res.width || + height * 9 / 10 < pipe_configs->output_info[0].res.height) + return; + /* here just copy the calculation in css */ + hor_ds_factor = CEIL_DIV(width >> 1, + pipe_configs->output_info[0].res.width); + ver_ds_factor = CEIL_DIV(height >> 1, + pipe_configs->output_info[0].res.height); + + if ((asd->isp->media_dev.hw_revision < + (ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT) || + IS_CHT) && hor_ds_factor != ver_ds_factor) { + dev_warn(asd->isp->dev, + "Cropping for capture due to FW limitation"); + return; + } + + pipe_configs->mode = __pipe_id_to_pipe_mode(asd, pipe_id); + stream_env->update_pipe[pipe_id] = true; + + pipe_extra_configs->enable_yuv_ds = true; + + pipe_configs->capt_pp_in_res.width = + stream_config->input_config.effective_res.width; + pipe_configs->capt_pp_in_res.height = + stream_config->input_config.effective_res.height; + + dev_dbg(isp->dev, "configuring pipe[%d]capture pp input w=%d.h=%d.\n", + pipe_id, width, height); +} + +/* + * For CSS2.1, preview pipe could support bayer downscaling, yuv decimation and + * yuv downscaling, which needs addtional configurations. + */ +static void __configure_preview_pp_input(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + int out_width, out_height, yuv_ds_in_width, yuv_ds_in_height; + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + struct ia_css_stream_config *stream_config = &stream_env->stream_config; + struct ia_css_pipe_config *pipe_configs = + &stream_env->pipe_configs[pipe_id]; + struct ia_css_pipe_extra_config *pipe_extra_configs = + &stream_env->pipe_extra_configs[pipe_id]; + struct ia_css_resolution *bayer_ds_out_res = + &pipe_configs->bayer_ds_out_res; + struct ia_css_resolution *vf_pp_in_res = + &pipe_configs->vf_pp_in_res; + struct ia_css_resolution *effective_res = + &stream_config->input_config.effective_res; + + const struct bayer_ds_factor bds_fct[] = {{2, 1}, {3, 2}, {5, 4} }; + /* + * BZ201033: YUV decimation factor of 4 causes couple of rightmost + * columns to be shaded. Remove this factor to work around the CSS bug. + * const unsigned int yuv_dec_fct[] = {4, 2}; + */ + const unsigned int yuv_dec_fct[] = { 2 }; + unsigned int i; + + if (width == 0 && height == 0) + return; + + pipe_configs->mode = __pipe_id_to_pipe_mode(asd, pipe_id); + stream_env->update_pipe[pipe_id] = true; + + out_width = pipe_configs->output_info[0].res.width; + out_height = pipe_configs->output_info[0].res.height; + + /* + * The ISP could do bayer downscaling, yuv decimation and yuv + * downscaling: + * 1: Bayer Downscaling: between effective resolution and + * bayer_ds_res_out; + * 2: YUV Decimation: between bayer_ds_res_out and vf_pp_in_res; + * 3: YUV Downscaling: between vf_pp_in_res and final vf output + * + * Rule for Bayer Downscaling: support factor 2, 1.5 and 1.25 + * Rule for YUV Decimation: support factor 2, 4 + * Rule for YUV Downscaling: arbitary value below 2 + * + * General rule of factor distribution among these stages: + * 1: try to do Bayer downscaling first if not in online mode. + * 2: try to do maximum of 2 for YUV downscaling + * 3: the remainling for YUV decimation + * + * Note: + * Do not configure bayer_ds_out_res if: + * online == 1 or continuous == 0 or raw_binning = 0 + */ + if (stream_config->online || !stream_config->continuous || + !pipe_extra_configs->enable_raw_binning) { + bayer_ds_out_res->width = 0; + bayer_ds_out_res->height = 0; + } else { + bayer_ds_out_res->width = effective_res->width; + bayer_ds_out_res->height = effective_res->height; + + for (i = 0; i < ARRAY_SIZE(bds_fct); i++) { + if (effective_res->width >= out_width * + bds_fct[i].numerator / bds_fct[i].denominator && + effective_res->height >= out_height * + bds_fct[i].numerator / bds_fct[i].denominator) { + bayer_ds_out_res->width = + effective_res->width * + bds_fct[i].denominator / + bds_fct[i].numerator; + bayer_ds_out_res->height = + effective_res->height * + bds_fct[i].denominator / + bds_fct[i].numerator; + break; + } + } + } + /* + * calculate YUV Decimation, YUV downscaling facor: + * YUV Downscaling factor must not exceed 2. + * YUV Decimation factor could be 2, 4. + */ + /* first decide the yuv_ds input resolution */ + if (bayer_ds_out_res->width == 0) { + yuv_ds_in_width = effective_res->width; + yuv_ds_in_height = effective_res->height; + } else { + yuv_ds_in_width = bayer_ds_out_res->width; + yuv_ds_in_height = bayer_ds_out_res->height; + } + + vf_pp_in_res->width = yuv_ds_in_width; + vf_pp_in_res->height = yuv_ds_in_height; + + /* find out the yuv decimation factor */ + for (i = 0; i < ARRAY_SIZE(yuv_dec_fct); i++) { + if (yuv_ds_in_width >= out_width * yuv_dec_fct[i] && + yuv_ds_in_height >= out_height * yuv_dec_fct[i]) { + vf_pp_in_res->width = yuv_ds_in_width / yuv_dec_fct[i]; + vf_pp_in_res->height = yuv_ds_in_height / yuv_dec_fct[i]; + break; + } + } + + if (vf_pp_in_res->width == out_width && + vf_pp_in_res->height == out_height) { + pipe_extra_configs->enable_yuv_ds = false; + vf_pp_in_res->width = 0; + vf_pp_in_res->height = 0; + } else { + pipe_extra_configs->enable_yuv_ds = true; + } + + dev_dbg(isp->dev, "configuring pipe[%d]preview pp input w=%d.h=%d.\n", + pipe_id, width, height); +} + +/* + * For CSS2.1, offline video pipe could support bayer decimation, and + * yuv downscaling, which needs addtional configurations. + */ +static void __configure_video_pp_input(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + int out_width, out_height; + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + struct ia_css_stream_config *stream_config = &stream_env->stream_config; + struct ia_css_pipe_config *pipe_configs = + &stream_env->pipe_configs[pipe_id]; + struct ia_css_pipe_extra_config *pipe_extra_configs = + &stream_env->pipe_extra_configs[pipe_id]; + struct ia_css_resolution *bayer_ds_out_res = + &pipe_configs->bayer_ds_out_res; + struct ia_css_resolution *effective_res = + &stream_config->input_config.effective_res; + + const struct bayer_ds_factor bds_factors[] = { + {8, 1}, {6, 1}, {4, 1}, {3, 1}, {2, 1}, {3, 2} }; + unsigned int i; + + if (width == 0 && height == 0) + return; + + pipe_configs->mode = __pipe_id_to_pipe_mode(asd, pipe_id); + stream_env->update_pipe[pipe_id] = true; + + pipe_extra_configs->enable_yuv_ds = false; + + /* + * If DVS is enabled, video binary will take care the dvs envelope + * and usually the bayer_ds_out_res should be larger than 120% of + * destination resolution, the extra 20% will be cropped as DVS + * envelope. But, if the bayer_ds_out_res is less than 120% of the + * destination. The ISP can still work, but DVS quality is not good. + */ + /* taking at least 10% as envelope */ + if (asd->params.video_dis_en) { + out_width = pipe_configs->output_info[0].res.width * 110 / 100; + out_height = pipe_configs->output_info[0].res.height * 110 / 100; + } else { + out_width = pipe_configs->output_info[0].res.width; + out_height = pipe_configs->output_info[0].res.height; + } + + /* + * calculate bayer decimate factor: + * 1: only 1.5, 2, 4 and 8 get supported + * 2: Do not configure bayer_ds_out_res if: + * online == 1 or continuous == 0 or raw_binning = 0 + */ + if (stream_config->online || !stream_config->continuous) { + bayer_ds_out_res->width = 0; + bayer_ds_out_res->height = 0; + goto done; + } + + pipe_extra_configs->enable_raw_binning = true; + bayer_ds_out_res->width = effective_res->width; + bayer_ds_out_res->height = effective_res->height; + + for (i = 0; i < sizeof(bds_factors) / sizeof(struct bayer_ds_factor); + i++) { + if (effective_res->width >= out_width * + bds_factors[i].numerator / bds_factors[i].denominator && + effective_res->height >= out_height * + bds_factors[i].numerator / bds_factors[i].denominator) { + bayer_ds_out_res->width = effective_res->width * + bds_factors[i].denominator / + bds_factors[i].numerator; + bayer_ds_out_res->height = effective_res->height * + bds_factors[i].denominator / + bds_factors[i].numerator; + break; + } + } + + /* + * DVS is cropped from BDS output, so we do not really need to set the + * envelope to 20% of output resolution here. always set it to 12x12 + * per firmware requirement. + */ + pipe_configs->dvs_envelope.width = 12; + pipe_configs->dvs_envelope.height = 12; + +done: + if (pipe_id == IA_CSS_PIPE_ID_YUVPP) + stream_config->left_padding = -1; + else + stream_config->left_padding = 12; + dev_dbg(isp->dev, "configuring pipe[%d]video pp input w=%d.h=%d.\n", + pipe_id, width, height); +} + +static void __configure_vf_output(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum atomisp_css_frame_format format, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + stream_env->pipe_configs[pipe_id].mode = + __pipe_id_to_pipe_mode(asd, pipe_id); + stream_env->update_pipe[pipe_id] = true; + + stream_env->pipe_configs[pipe_id].vf_output_info[0].res.width = width; + stream_env->pipe_configs[pipe_id].vf_output_info[0].res.height = height; + stream_env->pipe_configs[pipe_id].vf_output_info[0].format = format; + stream_env->pipe_configs[pipe_id].vf_output_info[0].padded_width = + min_width; + dev_dbg(isp->dev, + "configuring pipe[%d] vf output info w=%d.h=%d.f=%d.\n", + pipe_id, width, height, format); +} + +static void __configure_video_vf_output(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum atomisp_css_frame_format format, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + struct ia_css_frame_info *css_output_info; + stream_env->pipe_configs[pipe_id].mode = + __pipe_id_to_pipe_mode(asd, pipe_id); + stream_env->update_pipe[pipe_id] = true; + + /* + * second_vf_output will be as video viewfinder in SDV mode + * with SOC camera. vf_output will be as video viewfinder in + * normal video mode. + */ + if (asd->continuous_mode->val) + css_output_info = &stream_env->pipe_configs[pipe_id]. + vf_output_info[ATOMISP_CSS_OUTPUT_SECOND_INDEX]; + else + css_output_info = &stream_env->pipe_configs[pipe_id]. + vf_output_info[ATOMISP_CSS_OUTPUT_DEFAULT_INDEX]; + + css_output_info->res.width = width; + css_output_info->res.height = height; + css_output_info->format = format; + css_output_info->padded_width = min_width; + dev_dbg(isp->dev, + "configuring pipe[%d] vf output info w=%d.h=%d.f=%d.\n", + pipe_id, width, height, format); +} + +static int __get_frame_info(struct atomisp_sub_device *asd, + unsigned int stream_index, + struct atomisp_css_frame_info *info, + enum frame_info_type type, + enum ia_css_pipe_id pipe_id) +{ + struct atomisp_device *isp = asd->isp; + enum ia_css_err ret; + struct ia_css_pipe_info p_info; + + /* FIXME! No need to destroy/recreate all streams */ + if (__destroy_streams(asd, true)) + dev_warn(isp->dev, "destroy stream failed.\n"); + + if (__destroy_pipes(asd, true)) + dev_warn(isp->dev, "destroy pipe failed.\n"); + + if (__create_pipes(asd)) + return -EINVAL; + + if (__create_streams(asd)) + goto stream_err; + + ret = ia_css_pipe_get_info( + asd->stream_env[stream_index] + .pipes[pipe_id], &p_info); + if (ret == IA_CSS_SUCCESS) { + switch (type) { + case ATOMISP_CSS_VF_FRAME: + *info = p_info.vf_output_info[0]; + dev_dbg(isp->dev, "getting vf frame info.\n"); + break; + case ATOMISP_CSS_SECOND_VF_FRAME: + *info = p_info.vf_output_info[1]; + dev_dbg(isp->dev, "getting second vf frame info.\n"); + break; + case ATOMISP_CSS_OUTPUT_FRAME: + *info = p_info.output_info[0]; + dev_dbg(isp->dev, "getting main frame info.\n"); + break; + case ATOMISP_CSS_SECOND_OUTPUT_FRAME: + *info = p_info.output_info[1]; + dev_dbg(isp->dev, "getting second main frame info.\n"); + break; + case ATOMISP_CSS_RAW_FRAME: + *info = p_info.raw_output_info; + dev_dbg(isp->dev, "getting raw frame info.\n"); + } + dev_dbg(isp->dev, "get frame info: w=%d, h=%d, num_invalid_frames %d.\n", + info->res.width, info->res.height, p_info.num_invalid_frames); + return 0; + } + +stream_err: + __destroy_pipes(asd, true); + return -EINVAL; +} + +unsigned int atomisp_get_pipe_index(struct atomisp_sub_device *asd, + uint16_t source_pad) +{ + struct atomisp_device *isp = asd->isp; + /* + * to SOC camera, use yuvpp pipe. + */ + if (ATOMISP_USE_YUVPP(asd)) + return IA_CSS_PIPE_ID_YUVPP; + + switch (source_pad) { + case ATOMISP_SUBDEV_PAD_SOURCE_VIDEO: + if (asd->yuvpp_mode) + return IA_CSS_PIPE_ID_YUVPP; + if (asd->copy_mode) + return IA_CSS_PIPE_ID_COPY; + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO + || asd->vfpp->val == ATOMISP_VFPP_DISABLE_SCALER) + return IA_CSS_PIPE_ID_VIDEO; + else + return IA_CSS_PIPE_ID_CAPTURE; + case ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE: + if (asd->copy_mode) + return IA_CSS_PIPE_ID_COPY; + return IA_CSS_PIPE_ID_CAPTURE; + case ATOMISP_SUBDEV_PAD_SOURCE_VF: + if (!atomisp_is_mbuscode_raw( + asd->fmt[asd->capture_pad].fmt.code)) + return IA_CSS_PIPE_ID_CAPTURE; + case ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW: + if (asd->yuvpp_mode) + return IA_CSS_PIPE_ID_YUVPP; + if (asd->copy_mode) + return IA_CSS_PIPE_ID_COPY; + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) + return IA_CSS_PIPE_ID_VIDEO; + else + return IA_CSS_PIPE_ID_PREVIEW; + } + dev_warn(isp->dev, + "invalid source pad:%d, return default preview pipe index.\n", + source_pad); + return IA_CSS_PIPE_ID_PREVIEW; +} + +int atomisp_get_css_frame_info(struct atomisp_sub_device *asd, + uint16_t source_pad, + struct atomisp_css_frame_info *frame_info) +{ + struct ia_css_pipe_info info; + int pipe_index = atomisp_get_pipe_index(asd, source_pad); + int stream_index; + struct atomisp_device *isp = asd->isp; + + if (ATOMISP_SOC_CAMERA(asd)) + stream_index = atomisp_source_pad_to_stream_id(asd, source_pad); + else { + stream_index = (pipe_index == IA_CSS_PIPE_ID_YUVPP) ? + ATOMISP_INPUT_STREAM_VIDEO : + atomisp_source_pad_to_stream_id(asd, source_pad); + } + + if (IA_CSS_SUCCESS != ia_css_pipe_get_info(asd->stream_env[stream_index] + .pipes[pipe_index], &info)) { + dev_err(isp->dev, "ia_css_pipe_get_info FAILED"); + return -EINVAL; + } + + switch (source_pad) { + case ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE: + *frame_info = info.output_info[0]; + break; + case ATOMISP_SUBDEV_PAD_SOURCE_VIDEO: + if (ATOMISP_USE_YUVPP(asd) && asd->continuous_mode->val) + *frame_info = info. + output_info[ATOMISP_CSS_OUTPUT_SECOND_INDEX]; + else + *frame_info = info. + output_info[ATOMISP_CSS_OUTPUT_DEFAULT_INDEX]; + break; + case ATOMISP_SUBDEV_PAD_SOURCE_VF: + if (stream_index == ATOMISP_INPUT_STREAM_POSTVIEW) + *frame_info = info.output_info[0]; + else + *frame_info = info.vf_output_info[0]; + break; + case ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW: + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO && + (pipe_index == IA_CSS_PIPE_ID_VIDEO || + pipe_index == IA_CSS_PIPE_ID_YUVPP)) + if (ATOMISP_USE_YUVPP(asd) && asd->continuous_mode->val) + *frame_info = info. + vf_output_info[ATOMISP_CSS_OUTPUT_SECOND_INDEX]; + else + *frame_info = info. + vf_output_info[ATOMISP_CSS_OUTPUT_DEFAULT_INDEX]; + else if (ATOMISP_USE_YUVPP(asd) && asd->continuous_mode->val) + *frame_info = + info.output_info[ATOMISP_CSS_OUTPUT_SECOND_INDEX]; + else + *frame_info = + info.output_info[ATOMISP_CSS_OUTPUT_DEFAULT_INDEX]; + + break; + default: + frame_info = NULL; + break; + } + return frame_info ? 0 : -EINVAL; +} + +int atomisp_css_copy_configure_output(struct atomisp_sub_device *asd, + unsigned int stream_index, + unsigned int width, unsigned int height, + unsigned int padded_width, + enum atomisp_css_frame_format format) +{ + asd->stream_env[stream_index].pipe_configs[IA_CSS_PIPE_ID_COPY]. + default_capture_config.mode = + CSS_CAPTURE_MODE_RAW; + + __configure_output(asd, stream_index, width, height, padded_width, + format, IA_CSS_PIPE_ID_COPY); + return 0; +} + +int atomisp_css_yuvpp_configure_output(struct atomisp_sub_device *asd, + unsigned int stream_index, + unsigned int width, unsigned int height, + unsigned int padded_width, + enum atomisp_css_frame_format format) +{ + asd->stream_env[stream_index].pipe_configs[IA_CSS_PIPE_ID_YUVPP]. + default_capture_config.mode = + CSS_CAPTURE_MODE_RAW; + + __configure_output(asd, stream_index, width, height, padded_width, + format, IA_CSS_PIPE_ID_YUVPP); + return 0; +} + +int atomisp_css_yuvpp_configure_viewfinder( + struct atomisp_sub_device *asd, + unsigned int stream_index, + unsigned int width, unsigned int height, + unsigned int min_width, + enum atomisp_css_frame_format format) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[stream_index]; + enum ia_css_pipe_id pipe_id = IA_CSS_PIPE_ID_YUVPP; + + stream_env->pipe_configs[pipe_id].mode = + __pipe_id_to_pipe_mode(asd, pipe_id); + stream_env->update_pipe[pipe_id] = true; + + stream_env->pipe_configs[pipe_id].vf_output_info[0].res.width = width; + stream_env->pipe_configs[pipe_id].vf_output_info[0].res.height = height; + stream_env->pipe_configs[pipe_id].vf_output_info[0].format = format; + stream_env->pipe_configs[pipe_id].vf_output_info[0].padded_width = + min_width; + return 0; +} + +int atomisp_css_yuvpp_get_output_frame_info( + struct atomisp_sub_device *asd, + unsigned int stream_index, + struct atomisp_css_frame_info *info) +{ + return __get_frame_info(asd, stream_index, info, + ATOMISP_CSS_OUTPUT_FRAME, IA_CSS_PIPE_ID_YUVPP); +} + +int atomisp_css_yuvpp_get_viewfinder_frame_info( + struct atomisp_sub_device *asd, + unsigned int stream_index, + struct atomisp_css_frame_info *info) +{ + return __get_frame_info(asd, stream_index, info, + ATOMISP_CSS_VF_FRAME, IA_CSS_PIPE_ID_YUVPP); +} + +int atomisp_css_preview_configure_output(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum atomisp_css_frame_format format) +{ + /* + * to SOC camera, use yuvpp pipe. + */ + if (ATOMISP_USE_YUVPP(asd)) + __configure_video_preview_output(asd, ATOMISP_INPUT_STREAM_GENERAL, width, height, + min_width, format, IA_CSS_PIPE_ID_YUVPP); + else + __configure_output(asd, ATOMISP_INPUT_STREAM_GENERAL, width, height, + min_width, format, IA_CSS_PIPE_ID_PREVIEW); + return 0; +} + +int atomisp_css_capture_configure_output(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum atomisp_css_frame_format format) +{ + enum ia_css_pipe_id pipe_id; + + /* + * to SOC camera, use yuvpp pipe. + */ + if (ATOMISP_USE_YUVPP(asd)) + pipe_id = IA_CSS_PIPE_ID_YUVPP; + else + pipe_id = IA_CSS_PIPE_ID_CAPTURE; + + __configure_output(asd, ATOMISP_INPUT_STREAM_GENERAL, width, height, + min_width, format, pipe_id); + return 0; +} + +int atomisp_css_video_configure_output(struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum atomisp_css_frame_format format) +{ + /* + * to SOC camera, use yuvpp pipe. + */ + if (ATOMISP_USE_YUVPP(asd)) + __configure_video_preview_output(asd, ATOMISP_INPUT_STREAM_GENERAL, width, height, + min_width, format, IA_CSS_PIPE_ID_YUVPP); + else + __configure_output(asd, ATOMISP_INPUT_STREAM_GENERAL, width, height, + min_width, format, IA_CSS_PIPE_ID_VIDEO); + return 0; +} + +int atomisp_css_video_configure_viewfinder( + struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum atomisp_css_frame_format format) +{ + /* + * to SOC camera, video will use yuvpp pipe. + */ + if (ATOMISP_USE_YUVPP(asd)) + __configure_video_vf_output(asd, width, height, min_width, format, + IA_CSS_PIPE_ID_YUVPP); + else + __configure_vf_output(asd, width, height, min_width, format, + IA_CSS_PIPE_ID_VIDEO); + return 0; +} + +int atomisp_css_capture_configure_viewfinder( + struct atomisp_sub_device *asd, + unsigned int width, unsigned int height, + unsigned int min_width, + enum atomisp_css_frame_format format) +{ + enum ia_css_pipe_id pipe_id; + + /* + * to SOC camera, video will use yuvpp pipe. + */ + if (ATOMISP_USE_YUVPP(asd)) + pipe_id = IA_CSS_PIPE_ID_YUVPP; + else + pipe_id = IA_CSS_PIPE_ID_CAPTURE; + + __configure_vf_output(asd, width, height, min_width, format, + pipe_id); + return 0; +} + +int atomisp_css_video_get_viewfinder_frame_info( + struct atomisp_sub_device *asd, + struct atomisp_css_frame_info *info) +{ + enum ia_css_pipe_id pipe_id; + enum frame_info_type frame_type = ATOMISP_CSS_VF_FRAME; + + if (ATOMISP_USE_YUVPP(asd)) { + pipe_id = IA_CSS_PIPE_ID_YUVPP; + if (asd->continuous_mode->val) + frame_type = ATOMISP_CSS_SECOND_VF_FRAME; + } else { + pipe_id = IA_CSS_PIPE_ID_VIDEO; + } + + return __get_frame_info(asd, ATOMISP_INPUT_STREAM_GENERAL, info, + frame_type, pipe_id); +} + +int atomisp_css_capture_get_viewfinder_frame_info( + struct atomisp_sub_device *asd, + struct atomisp_css_frame_info *info) +{ + enum ia_css_pipe_id pipe_id; + + if (ATOMISP_USE_YUVPP(asd)) + pipe_id = IA_CSS_PIPE_ID_YUVPP; + else + pipe_id = IA_CSS_PIPE_ID_CAPTURE; + + return __get_frame_info(asd, ATOMISP_INPUT_STREAM_GENERAL, info, + ATOMISP_CSS_VF_FRAME, pipe_id); +} + +int atomisp_css_capture_get_output_raw_frame_info( + struct atomisp_sub_device *asd, + struct atomisp_css_frame_info *info) +{ + if (ATOMISP_USE_YUVPP(asd)) + return 0; + + return __get_frame_info(asd, ATOMISP_INPUT_STREAM_GENERAL, info, + ATOMISP_CSS_RAW_FRAME, IA_CSS_PIPE_ID_CAPTURE); +} + +int atomisp_css_copy_get_output_frame_info( + struct atomisp_sub_device *asd, + unsigned int stream_index, + struct atomisp_css_frame_info *info) +{ + return __get_frame_info(asd, stream_index, info, + ATOMISP_CSS_OUTPUT_FRAME, IA_CSS_PIPE_ID_COPY); +} + +int atomisp_css_preview_get_output_frame_info( + struct atomisp_sub_device *asd, + struct atomisp_css_frame_info *info) +{ + enum ia_css_pipe_id pipe_id; + enum frame_info_type frame_type = ATOMISP_CSS_OUTPUT_FRAME; + + if (ATOMISP_USE_YUVPP(asd)) { + pipe_id = IA_CSS_PIPE_ID_YUVPP; + if (asd->continuous_mode->val) + frame_type = ATOMISP_CSS_SECOND_OUTPUT_FRAME; + } else { + pipe_id = IA_CSS_PIPE_ID_PREVIEW; + } + + return __get_frame_info(asd, ATOMISP_INPUT_STREAM_GENERAL, info, + frame_type, pipe_id); +} + +int atomisp_css_capture_get_output_frame_info( + struct atomisp_sub_device *asd, + struct atomisp_css_frame_info *info) +{ + enum ia_css_pipe_id pipe_id; + + if (ATOMISP_USE_YUVPP(asd)) + pipe_id = IA_CSS_PIPE_ID_YUVPP; + else + pipe_id = IA_CSS_PIPE_ID_CAPTURE; + + return __get_frame_info(asd, ATOMISP_INPUT_STREAM_GENERAL, info, + ATOMISP_CSS_OUTPUT_FRAME, pipe_id); +} + +int atomisp_css_video_get_output_frame_info( + struct atomisp_sub_device *asd, + struct atomisp_css_frame_info *info) +{ + enum ia_css_pipe_id pipe_id; + enum frame_info_type frame_type = ATOMISP_CSS_OUTPUT_FRAME; + + if (ATOMISP_USE_YUVPP(asd)) { + pipe_id = IA_CSS_PIPE_ID_YUVPP; + if (asd->continuous_mode->val) + frame_type = ATOMISP_CSS_SECOND_OUTPUT_FRAME; + } else { + pipe_id = IA_CSS_PIPE_ID_VIDEO; + } + + return __get_frame_info(asd, ATOMISP_INPUT_STREAM_GENERAL, info, + frame_type, pipe_id); +} + +int atomisp_css_preview_configure_pp_input( + struct atomisp_sub_device *asd, + unsigned int width, unsigned int height) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + __configure_preview_pp_input(asd, width, height, + ATOMISP_USE_YUVPP(asd) ? + IA_CSS_PIPE_ID_YUVPP : IA_CSS_PIPE_ID_PREVIEW); + + if (width > stream_env->pipe_configs[IA_CSS_PIPE_ID_CAPTURE]. + capt_pp_in_res.width) + __configure_capture_pp_input(asd, width, height, + ATOMISP_USE_YUVPP(asd) ? + IA_CSS_PIPE_ID_YUVPP : IA_CSS_PIPE_ID_CAPTURE); + return 0; +} + +int atomisp_css_capture_configure_pp_input( + struct atomisp_sub_device *asd, + unsigned int width, unsigned int height) +{ + __configure_capture_pp_input(asd, width, height, + ATOMISP_USE_YUVPP(asd) ? + IA_CSS_PIPE_ID_YUVPP : IA_CSS_PIPE_ID_CAPTURE); + return 0; +} + +int atomisp_css_video_configure_pp_input( + struct atomisp_sub_device *asd, + unsigned int width, unsigned int height) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + + __configure_video_pp_input(asd, width, height, + ATOMISP_USE_YUVPP(asd) ? + IA_CSS_PIPE_ID_YUVPP : IA_CSS_PIPE_ID_VIDEO); + + if (width > stream_env->pipe_configs[IA_CSS_PIPE_ID_CAPTURE]. + capt_pp_in_res.width) + __configure_capture_pp_input(asd, width, height, + ATOMISP_USE_YUVPP(asd) ? + IA_CSS_PIPE_ID_YUVPP : IA_CSS_PIPE_ID_CAPTURE); + return 0; +} + +int atomisp_css_offline_capture_configure(struct atomisp_sub_device *asd, + int num_captures, unsigned int skip, int offset) +{ + enum ia_css_err ret; + +#ifdef ISP2401 + dev_dbg(asd->isp->dev, "%s num_capture:%d skip:%d offset:%d\n", + __func__, num_captures, skip, offset); +#endif + ret = ia_css_stream_capture( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + num_captures, skip, offset); + if (ret != IA_CSS_SUCCESS) + return -EINVAL; + + return 0; +} + +int atomisp_css_exp_id_capture(struct atomisp_sub_device *asd, int exp_id) +{ + enum ia_css_err ret; + + ret = ia_css_stream_capture_frame( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + exp_id); + if (ret == IA_CSS_ERR_QUEUE_IS_FULL) { + /* capture cmd queue is full */ + return -EBUSY; + } else if (ret != IA_CSS_SUCCESS) { + return -EIO; + } + + return 0; +} + +int atomisp_css_exp_id_unlock(struct atomisp_sub_device *asd, int exp_id) +{ + enum ia_css_err ret; + + ret = ia_css_unlock_raw_frame( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + exp_id); + if (ret == IA_CSS_ERR_QUEUE_IS_FULL) + return -EAGAIN; + else if (ret != IA_CSS_SUCCESS) + return -EIO; + + return 0; +} + +int atomisp_css_capture_enable_xnr(struct atomisp_sub_device *asd, + bool enable) +{ + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .pipe_configs[IA_CSS_PIPE_ID_CAPTURE] + .default_capture_config.enable_xnr = enable; + asd->params.capture_config.enable_xnr = enable; + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .update_pipe[IA_CSS_PIPE_ID_CAPTURE] = true; + + return 0; +} + +void atomisp_css_send_input_frame(struct atomisp_sub_device *asd, + unsigned short *data, unsigned int width, + unsigned int height) +{ + ia_css_stream_send_input_frame( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + data, width, height); +} + +bool atomisp_css_isp_has_started(void) +{ + return ia_css_isp_has_started(); +} + +void atomisp_css_request_flash(struct atomisp_sub_device *asd) +{ + ia_css_stream_request_flash( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream); +} + +void atomisp_css_set_wb_config(struct atomisp_sub_device *asd, + struct atomisp_css_wb_config *wb_config) +{ + asd->params.config.wb_config = wb_config; +} + +void atomisp_css_set_ob_config(struct atomisp_sub_device *asd, + struct atomisp_css_ob_config *ob_config) +{ + asd->params.config.ob_config = ob_config; +} + +void atomisp_css_set_dp_config(struct atomisp_sub_device *asd, + struct atomisp_css_dp_config *dp_config) +{ + asd->params.config.dp_config = dp_config; +} + +void atomisp_css_set_de_config(struct atomisp_sub_device *asd, + struct atomisp_css_de_config *de_config) +{ + asd->params.config.de_config = de_config; +} + +void atomisp_css_set_dz_config(struct atomisp_sub_device *asd, + struct atomisp_css_dz_config *dz_config) +{ + asd->params.config.dz_config = dz_config; +} + +void atomisp_css_set_default_de_config(struct atomisp_sub_device *asd) +{ + asd->params.config.de_config = NULL; +} + +void atomisp_css_set_ce_config(struct atomisp_sub_device *asd, + struct atomisp_css_ce_config *ce_config) +{ + asd->params.config.ce_config = ce_config; +} + +void atomisp_css_set_nr_config(struct atomisp_sub_device *asd, + struct atomisp_css_nr_config *nr_config) +{ + asd->params.config.nr_config = nr_config; +} + +void atomisp_css_set_ee_config(struct atomisp_sub_device *asd, + struct atomisp_css_ee_config *ee_config) +{ + asd->params.config.ee_config = ee_config; +} + +void atomisp_css_set_tnr_config(struct atomisp_sub_device *asd, + struct atomisp_css_tnr_config *tnr_config) +{ + asd->params.config.tnr_config = tnr_config; +} + +void atomisp_css_set_cc_config(struct atomisp_sub_device *asd, + struct atomisp_css_cc_config *cc_config) +{ + asd->params.config.cc_config = cc_config; +} + +void atomisp_css_set_macc_table(struct atomisp_sub_device *asd, + struct atomisp_css_macc_table *macc_table) +{ + asd->params.config.macc_table = macc_table; +} + +void atomisp_css_set_macc_config(struct atomisp_sub_device *asd, + struct atomisp_css_macc_config *macc_config) +{ + asd->params.config.macc_config = macc_config; +} + +void atomisp_css_set_ecd_config(struct atomisp_sub_device *asd, + struct atomisp_css_ecd_config *ecd_config) +{ + asd->params.config.ecd_config = ecd_config; +} + +void atomisp_css_set_ynr_config(struct atomisp_sub_device *asd, + struct atomisp_css_ynr_config *ynr_config) +{ + asd->params.config.ynr_config = ynr_config; +} + +void atomisp_css_set_fc_config(struct atomisp_sub_device *asd, + struct atomisp_css_fc_config *fc_config) +{ + asd->params.config.fc_config = fc_config; +} + +void atomisp_css_set_ctc_config(struct atomisp_sub_device *asd, + struct atomisp_css_ctc_config *ctc_config) +{ + asd->params.config.ctc_config = ctc_config; +} + +void atomisp_css_set_cnr_config(struct atomisp_sub_device *asd, + struct atomisp_css_cnr_config *cnr_config) +{ + asd->params.config.cnr_config = cnr_config; +} + +void atomisp_css_set_aa_config(struct atomisp_sub_device *asd, + struct atomisp_css_aa_config *aa_config) +{ + asd->params.config.aa_config = aa_config; +} + +void atomisp_css_set_baa_config(struct atomisp_sub_device *asd, + struct atomisp_css_baa_config *baa_config) +{ + asd->params.config.baa_config = baa_config; +} + +void atomisp_css_set_anr_config(struct atomisp_sub_device *asd, + struct atomisp_css_anr_config *anr_config) +{ + asd->params.config.anr_config = anr_config; +} + +void atomisp_css_set_xnr_config(struct atomisp_sub_device *asd, + struct atomisp_css_xnr_config *xnr_config) +{ + asd->params.config.xnr_config = xnr_config; +} + +void atomisp_css_set_yuv2rgb_cc_config(struct atomisp_sub_device *asd, + struct atomisp_css_cc_config *yuv2rgb_cc_config) +{ + asd->params.config.yuv2rgb_cc_config = yuv2rgb_cc_config; +} + +void atomisp_css_set_rgb2yuv_cc_config(struct atomisp_sub_device *asd, + struct atomisp_css_cc_config *rgb2yuv_cc_config) +{ + asd->params.config.rgb2yuv_cc_config = rgb2yuv_cc_config; +} + +void atomisp_css_set_xnr_table(struct atomisp_sub_device *asd, + struct atomisp_css_xnr_table *xnr_table) +{ + asd->params.config.xnr_table = xnr_table; +} + +void atomisp_css_set_r_gamma_table(struct atomisp_sub_device *asd, + struct atomisp_css_rgb_gamma_table *r_gamma_table) +{ + asd->params.config.r_gamma_table = r_gamma_table; +} + +void atomisp_css_set_g_gamma_table(struct atomisp_sub_device *asd, + struct atomisp_css_rgb_gamma_table *g_gamma_table) +{ + asd->params.config.g_gamma_table = g_gamma_table; +} + +void atomisp_css_set_b_gamma_table(struct atomisp_sub_device *asd, + struct atomisp_css_rgb_gamma_table *b_gamma_table) +{ + asd->params.config.b_gamma_table = b_gamma_table; +} + +void atomisp_css_set_gamma_table(struct atomisp_sub_device *asd, + struct atomisp_css_gamma_table *gamma_table) +{ + asd->params.config.gamma_table = gamma_table; +} + +void atomisp_css_set_ctc_table(struct atomisp_sub_device *asd, + struct atomisp_css_ctc_table *ctc_table) +{ + int i; + uint16_t *vamem_ptr = ctc_table->data.vamem_1; + int data_size = IA_CSS_VAMEM_1_CTC_TABLE_SIZE; + bool valid = false; + + /* workaround: if ctc_table is all 0, do not apply it */ + if (ctc_table->vamem_type == IA_CSS_VAMEM_TYPE_2) { + vamem_ptr = ctc_table->data.vamem_2; + data_size = IA_CSS_VAMEM_2_CTC_TABLE_SIZE; + } + + for (i = 0; i < data_size; i++) { + if (*(vamem_ptr + i)) { + valid = true; + break; + } + } + + if (valid) + asd->params.config.ctc_table = ctc_table; + else + dev_warn(asd->isp->dev, "Bypass the invalid ctc_table.\n"); +} + +void atomisp_css_set_anr_thres(struct atomisp_sub_device *asd, + struct atomisp_css_anr_thres *anr_thres) +{ + asd->params.config.anr_thres = anr_thres; +} + +void atomisp_css_set_dvs_6axis(struct atomisp_sub_device *asd, + struct atomisp_css_dvs_6axis *dvs_6axis) +{ + asd->params.config.dvs_6axis_config = dvs_6axis; +} + +void atomisp_css_set_gc_config(struct atomisp_sub_device *asd, + struct atomisp_css_gc_config *gc_config) +{ + asd->params.config.gc_config = gc_config; +} + +void atomisp_css_set_3a_config(struct atomisp_sub_device *asd, + struct atomisp_css_3a_config *s3a_config) +{ + asd->params.config.s3a_config = s3a_config; +} + +void atomisp_css_video_set_dis_vector(struct atomisp_sub_device *asd, + struct atomisp_dis_vector *vector) +{ + if (!asd->params.config.motion_vector) + asd->params.config.motion_vector = &asd->params.css_param.motion_vector; + + memset(asd->params.config.motion_vector, + 0, sizeof(struct ia_css_vector)); + asd->params.css_param.motion_vector.x = vector->x; + asd->params.css_param.motion_vector.y = vector->y; +} + +static int atomisp_compare_dvs_grid(struct atomisp_sub_device *asd, + struct atomisp_dvs_grid_info *atomgrid) +{ + struct atomisp_css_dvs_grid_info *cur = + atomisp_css_get_dvs_grid_info(&asd->params.curr_grid_info); + + if (!cur) { + dev_err(asd->isp->dev, "dvs grid not available!\n"); + return -EINVAL; + } + + if (sizeof(*cur) != sizeof(*atomgrid)) { + dev_err(asd->isp->dev, "dvs grid mis-match!\n"); + return -EINVAL; + } + + if (!cur->enable) { + dev_err(asd->isp->dev, "dvs not enabled!\n"); + return -EINVAL; + } + + return memcmp(atomgrid, cur, sizeof(*cur)); +} + +void atomisp_css_set_dvs2_coefs(struct atomisp_sub_device *asd, + struct ia_css_dvs2_coefficients *coefs) +{ + asd->params.config.dvs2_coefs = coefs; +} + +int atomisp_css_set_dis_coefs(struct atomisp_sub_device *asd, + struct atomisp_dis_coefficients *coefs) +{ + if (atomisp_compare_dvs_grid(asd, &coefs->grid_info) != 0) + /* If the grid info in the argument differs from the current + grid info, we tell the caller to reset the grid size and + try again. */ + return -EAGAIN; + + if (coefs->hor_coefs.odd_real == NULL || + coefs->hor_coefs.odd_imag == NULL || + coefs->hor_coefs.even_real == NULL || + coefs->hor_coefs.even_imag == NULL || + coefs->ver_coefs.odd_real == NULL || + coefs->ver_coefs.odd_imag == NULL || + coefs->ver_coefs.even_real == NULL || + coefs->ver_coefs.even_imag == NULL || + asd->params.css_param.dvs2_coeff->hor_coefs.odd_real == NULL || + asd->params.css_param.dvs2_coeff->hor_coefs.odd_imag == NULL || + asd->params.css_param.dvs2_coeff->hor_coefs.even_real == NULL || + asd->params.css_param.dvs2_coeff->hor_coefs.even_imag == NULL || + asd->params.css_param.dvs2_coeff->ver_coefs.odd_real == NULL || + asd->params.css_param.dvs2_coeff->ver_coefs.odd_imag == NULL || + asd->params.css_param.dvs2_coeff->ver_coefs.even_real == NULL || + asd->params.css_param.dvs2_coeff->ver_coefs.even_imag == NULL) + return -EINVAL; + + if (copy_from_user(asd->params.css_param.dvs2_coeff->hor_coefs.odd_real, + coefs->hor_coefs.odd_real, asd->params.dvs_hor_coef_bytes)) + return -EFAULT; + if (copy_from_user(asd->params.css_param.dvs2_coeff->hor_coefs.odd_imag, + coefs->hor_coefs.odd_imag, asd->params.dvs_hor_coef_bytes)) + return -EFAULT; + if (copy_from_user(asd->params.css_param.dvs2_coeff->hor_coefs.even_real, + coefs->hor_coefs.even_real, asd->params.dvs_hor_coef_bytes)) + return -EFAULT; + if (copy_from_user(asd->params.css_param.dvs2_coeff->hor_coefs.even_imag, + coefs->hor_coefs.even_imag, asd->params.dvs_hor_coef_bytes)) + return -EFAULT; + + if (copy_from_user(asd->params.css_param.dvs2_coeff->ver_coefs.odd_real, + coefs->ver_coefs.odd_real, asd->params.dvs_ver_coef_bytes)) + return -EFAULT; + if (copy_from_user(asd->params.css_param.dvs2_coeff->ver_coefs.odd_imag, + coefs->ver_coefs.odd_imag, asd->params.dvs_ver_coef_bytes)) + return -EFAULT; + if (copy_from_user(asd->params.css_param.dvs2_coeff->ver_coefs.even_real, + coefs->ver_coefs.even_real, asd->params.dvs_ver_coef_bytes)) + return -EFAULT; + if (copy_from_user(asd->params.css_param.dvs2_coeff->ver_coefs.even_imag, + coefs->ver_coefs.even_imag, asd->params.dvs_ver_coef_bytes)) + return -EFAULT; + + asd->params.css_param.update_flag.dvs2_coefs = + (struct atomisp_dvs2_coefficients *) + asd->params.css_param.dvs2_coeff; + /* FIXME! */ +/* asd->params.dis_proj_data_valid = false; */ + asd->params.css_update_params_needed = true; + + return 0; +} + +void atomisp_css_set_zoom_factor(struct atomisp_sub_device *asd, + unsigned int zoom) +{ + struct atomisp_device *isp = asd->isp; + + if (zoom == asd->params.css_param.dz_config.dx && + zoom == asd->params.css_param.dz_config.dy) { + dev_dbg(isp->dev, "same zoom scale. skipped.\n"); + return; + } + + memset(&asd->params.css_param.dz_config, 0, + sizeof(struct ia_css_dz_config)); + asd->params.css_param.dz_config.dx = zoom; + asd->params.css_param.dz_config.dy = zoom; + + asd->params.css_param.update_flag.dz_config = + (struct atomisp_dz_config *) &asd->params.css_param.dz_config; + asd->params.css_update_params_needed = true; +} + +void atomisp_css_set_formats_config(struct atomisp_sub_device *asd, + struct atomisp_css_formats_config *formats_config) +{ + asd->params.config.formats_config = formats_config; +} + +int atomisp_css_get_wb_config(struct atomisp_sub_device *asd, + struct atomisp_wb_config *config) +{ + struct atomisp_css_wb_config wb_config; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&wb_config, 0, sizeof(struct atomisp_css_wb_config)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.wb_config = &wb_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + memcpy(config, &wb_config, sizeof(*config)); + + return 0; +} + +int atomisp_css_get_ob_config(struct atomisp_sub_device *asd, + struct atomisp_ob_config *config) +{ + struct atomisp_css_ob_config ob_config; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&ob_config, 0, sizeof(struct atomisp_css_ob_config)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.ob_config = &ob_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + memcpy(config, &ob_config, sizeof(*config)); + + return 0; +} + +int atomisp_css_get_dp_config(struct atomisp_sub_device *asd, + struct atomisp_dp_config *config) +{ + struct atomisp_css_dp_config dp_config; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&dp_config, 0, sizeof(struct atomisp_css_dp_config)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.dp_config = &dp_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + memcpy(config, &dp_config, sizeof(*config)); + + return 0; +} + +int atomisp_css_get_de_config(struct atomisp_sub_device *asd, + struct atomisp_de_config *config) +{ + struct atomisp_css_de_config de_config; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&de_config, 0, sizeof(struct atomisp_css_de_config)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.de_config = &de_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + memcpy(config, &de_config, sizeof(*config)); + + return 0; +} + +int atomisp_css_get_nr_config(struct atomisp_sub_device *asd, + struct atomisp_nr_config *config) +{ + struct atomisp_css_nr_config nr_config; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&nr_config, 0, sizeof(struct atomisp_css_nr_config)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + + isp_config.nr_config = &nr_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + memcpy(config, &nr_config, sizeof(*config)); + + return 0; +} + +int atomisp_css_get_ee_config(struct atomisp_sub_device *asd, + struct atomisp_ee_config *config) +{ + struct atomisp_css_ee_config ee_config; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&ee_config, 0, sizeof(struct atomisp_css_ee_config)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.ee_config = &ee_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + memcpy(config, &ee_config, sizeof(*config)); + + return 0; +} + +int atomisp_css_get_tnr_config(struct atomisp_sub_device *asd, + struct atomisp_tnr_config *config) +{ + struct atomisp_css_tnr_config tnr_config; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&tnr_config, 0, sizeof(struct atomisp_css_tnr_config)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.tnr_config = &tnr_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + memcpy(config, &tnr_config, sizeof(*config)); + + return 0; +} + +int atomisp_css_get_ctc_table(struct atomisp_sub_device *asd, + struct atomisp_ctc_table *config) +{ + struct atomisp_css_ctc_table *tab; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + + tab = vzalloc(sizeof(struct atomisp_css_ctc_table)); + if (!tab) + return -ENOMEM; + + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.ctc_table = tab; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + memcpy(config, tab, sizeof(*tab)); + vfree(tab); + + return 0; +} + +int atomisp_css_get_gamma_table(struct atomisp_sub_device *asd, + struct atomisp_gamma_table *config) +{ + struct atomisp_css_gamma_table *tab; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + + tab = vzalloc(sizeof(struct atomisp_css_gamma_table)); + if (!tab) + return -ENOMEM; + + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.gamma_table = tab; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + memcpy(config, tab, sizeof(*tab)); + vfree(tab); + + return 0; +} + +int atomisp_css_get_gc_config(struct atomisp_sub_device *asd, + struct atomisp_gc_config *config) +{ + struct atomisp_css_gc_config gc_config; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&gc_config, 0, sizeof(struct atomisp_css_gc_config)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.gc_config = &gc_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + /* Get gamma correction params from current setup */ + memcpy(config, &gc_config, sizeof(*config)); + + return 0; +} + +int atomisp_css_get_3a_config(struct atomisp_sub_device *asd, + struct atomisp_3a_config *config) +{ + struct atomisp_css_3a_config s3a_config; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&s3a_config, 0, sizeof(struct atomisp_css_3a_config)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.s3a_config = &s3a_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + /* Get white balance from current setup */ + memcpy(config, &s3a_config, sizeof(*config)); + + return 0; +} + +int atomisp_css_get_formats_config(struct atomisp_sub_device *asd, + struct atomisp_formats_config *config) +{ + struct atomisp_css_formats_config formats_config; + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&formats_config, 0, sizeof(formats_config)); + memset(&isp_config, 0, sizeof(isp_config)); + isp_config.formats_config = &formats_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + /* Get narrow gamma from current setup */ + memcpy(config, &formats_config, sizeof(*config)); + + return 0; +} + +int atomisp_css_get_zoom_factor(struct atomisp_sub_device *asd, + unsigned int *zoom) +{ + struct ia_css_dz_config dz_config; /**< Digital Zoom */ + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, "%s called after streamoff, skipping.\n", + __func__); + return -EINVAL; + } + memset(&dz_config, 0, sizeof(struct ia_css_dz_config)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.dz_config = &dz_config; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); + *zoom = dz_config.dx; + + return 0; +} + + +/* + * Function to set/get image stablization statistics + */ +int atomisp_css_get_dis_stat(struct atomisp_sub_device *asd, + struct atomisp_dis_statistics *stats) +{ + struct atomisp_device *isp = asd->isp; + struct atomisp_dis_buf *dis_buf; + unsigned long flags; + + if (asd->params.dvs_stat->hor_prod.odd_real == NULL || + asd->params.dvs_stat->hor_prod.odd_imag == NULL || + asd->params.dvs_stat->hor_prod.even_real == NULL || + asd->params.dvs_stat->hor_prod.even_imag == NULL || + asd->params.dvs_stat->ver_prod.odd_real == NULL || + asd->params.dvs_stat->ver_prod.odd_imag == NULL || + asd->params.dvs_stat->ver_prod.even_real == NULL || + asd->params.dvs_stat->ver_prod.even_imag == NULL) + return -EINVAL; + + /* isp needs to be streaming to get DIS statistics */ + spin_lock_irqsave(&isp->lock, flags); + if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED) { + spin_unlock_irqrestore(&isp->lock, flags); + return -EINVAL; + } + spin_unlock_irqrestore(&isp->lock, flags); + + if (atomisp_compare_dvs_grid(asd, &stats->dvs2_stat.grid_info) != 0) + /* If the grid info in the argument differs from the current + grid info, we tell the caller to reset the grid size and + try again. */ + return -EAGAIN; + + spin_lock_irqsave(&asd->dis_stats_lock, flags); + if (!asd->params.dis_proj_data_valid || list_empty(&asd->dis_stats)) { + spin_unlock_irqrestore(&asd->dis_stats_lock, flags); + dev_err(isp->dev, "dis statistics is not valid.\n"); + return -EAGAIN; + } + + dis_buf = list_entry(asd->dis_stats.next, + struct atomisp_dis_buf, list); + list_del_init(&dis_buf->list); + spin_unlock_irqrestore(&asd->dis_stats_lock, flags); + + if (dis_buf->dvs_map) + ia_css_translate_dvs2_statistics( + asd->params.dvs_stat, dis_buf->dvs_map); + else + ia_css_get_dvs2_statistics(asd->params.dvs_stat, + dis_buf->dis_data); + stats->exp_id = dis_buf->dis_data->exp_id; + + spin_lock_irqsave(&asd->dis_stats_lock, flags); + list_add_tail(&dis_buf->list, &asd->dis_stats); + spin_unlock_irqrestore(&asd->dis_stats_lock, flags); + + if (copy_to_user(stats->dvs2_stat.ver_prod.odd_real, + asd->params.dvs_stat->ver_prod.odd_real, + asd->params.dvs_ver_proj_bytes)) + return -EFAULT; + if (copy_to_user(stats->dvs2_stat.ver_prod.odd_imag, + asd->params.dvs_stat->ver_prod.odd_imag, + asd->params.dvs_ver_proj_bytes)) + return -EFAULT; + if (copy_to_user(stats->dvs2_stat.ver_prod.even_real, + asd->params.dvs_stat->ver_prod.even_real, + asd->params.dvs_ver_proj_bytes)) + return -EFAULT; + if (copy_to_user(stats->dvs2_stat.ver_prod.even_imag, + asd->params.dvs_stat->ver_prod.even_imag, + asd->params.dvs_ver_proj_bytes)) + return -EFAULT; + if (copy_to_user(stats->dvs2_stat.hor_prod.odd_real, + asd->params.dvs_stat->hor_prod.odd_real, + asd->params.dvs_hor_proj_bytes)) + return -EFAULT; + if (copy_to_user(stats->dvs2_stat.hor_prod.odd_imag, + asd->params.dvs_stat->hor_prod.odd_imag, + asd->params.dvs_hor_proj_bytes)) + return -EFAULT; + if (copy_to_user(stats->dvs2_stat.hor_prod.even_real, + asd->params.dvs_stat->hor_prod.even_real, + asd->params.dvs_hor_proj_bytes)) + return -EFAULT; + if (copy_to_user(stats->dvs2_stat.hor_prod.even_imag, + asd->params.dvs_stat->hor_prod.even_imag, + asd->params.dvs_hor_proj_bytes)) + return -EFAULT; + + return 0; +} + +struct atomisp_css_shading_table *atomisp_css_shading_table_alloc( + unsigned int width, unsigned int height) +{ + return ia_css_shading_table_alloc(width, height); +} + +void atomisp_css_set_shading_table(struct atomisp_sub_device *asd, + struct atomisp_css_shading_table *table) +{ + asd->params.config.shading_table = table; +} + +void atomisp_css_shading_table_free(struct atomisp_css_shading_table *table) +{ + ia_css_shading_table_free(table); +} + +struct atomisp_css_morph_table *atomisp_css_morph_table_allocate( + unsigned int width, unsigned int height) +{ + return ia_css_morph_table_allocate(width, height); +} + +void atomisp_css_set_morph_table(struct atomisp_sub_device *asd, + struct atomisp_css_morph_table *table) +{ + asd->params.config.morph_table = table; +} + +void atomisp_css_get_morph_table(struct atomisp_sub_device *asd, + struct atomisp_css_morph_table *table) +{ + struct ia_css_isp_config isp_config; + struct atomisp_device *isp = asd->isp; + + if (!asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream) { + dev_err(isp->dev, + "%s called after streamoff, skipping.\n", __func__); + return; + } + memset(table, 0, sizeof(struct atomisp_css_morph_table)); + memset(&isp_config, 0, sizeof(struct ia_css_isp_config)); + isp_config.morph_table = table; + ia_css_stream_get_isp_config( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + &isp_config); +} + +void atomisp_css_morph_table_free(struct atomisp_css_morph_table *table) +{ + ia_css_morph_table_free(table); +} + +void atomisp_css_set_cont_prev_start_time(struct atomisp_device *isp, + unsigned int overlap) +{ + /* CSS 2.0 doesn't support this API. */ + dev_dbg(isp->dev, "set cont prev start time is not supported.\n"); + return; +} + +void atomisp_css_acc_done(struct atomisp_sub_device *asd) +{ + complete(&asd->acc.acc_done); +} + +int atomisp_css_wait_acc_finish(struct atomisp_sub_device *asd) +{ + int ret = 0; + struct atomisp_device *isp = asd->isp; + + /* Unlock the isp mutex taken in IOCTL handler before sleeping! */ + rt_mutex_unlock(&isp->mutex); + if (wait_for_completion_interruptible_timeout(&asd->acc.acc_done, + ATOMISP_ISP_TIMEOUT_DURATION) == 0) { + dev_err(isp->dev, "<%s: completion timeout\n", __func__); + atomisp_css_debug_dump_sp_sw_debug_info(); + atomisp_css_debug_dump_debug_info(__func__); + ret = -EIO; + } + rt_mutex_lock(&isp->mutex); + + return ret; +} + +/* Set the ACC binary arguments */ +int atomisp_css_set_acc_parameters(struct atomisp_acc_fw *acc_fw) +{ + unsigned int mem; + + for (mem = 0; mem < ATOMISP_ACC_NR_MEMORY; mem++) { + if (acc_fw->args[mem].length == 0) + continue; + + ia_css_isp_param_set_css_mem_init(&acc_fw->fw->mem_initializers, + IA_CSS_PARAM_CLASS_PARAM, mem, + acc_fw->args[mem].css_ptr, + acc_fw->args[mem].length); + } + + return 0; +} + +/* Load acc binary extension */ +int atomisp_css_load_acc_extension(struct atomisp_sub_device *asd, + struct atomisp_css_fw_info *fw, + enum atomisp_css_pipe_id pipe_id, + unsigned int type) +{ + struct atomisp_css_fw_info **hd; + + fw->next = NULL; + hd = &(asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .pipe_configs[pipe_id].acc_extension); + while (*hd) + hd = &(*hd)->next; + *hd = fw; + + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .update_pipe[pipe_id] = true; + return 0; +} + +/* Unload acc binary extension */ +void atomisp_css_unload_acc_extension(struct atomisp_sub_device *asd, + struct atomisp_css_fw_info *fw, + enum atomisp_css_pipe_id pipe_id) +{ + struct atomisp_css_fw_info **hd; + + hd = &(asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .pipe_configs[pipe_id].acc_extension); + while (*hd && *hd != fw) + hd = &(*hd)->next; + if (!*hd) { + dev_err(asd->isp->dev, "did not find acc fw for removal\n"); + return; + } + *hd = fw->next; + fw->next = NULL; + + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .update_pipe[pipe_id] = true; +} + +int atomisp_css_create_acc_pipe(struct atomisp_sub_device *asd) +{ + struct atomisp_device *isp = asd->isp; + struct ia_css_pipe_config *pipe_config; + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + + if (stream_env->acc_stream) { + if (stream_env->acc_stream_state == CSS_STREAM_STARTED) { + if (ia_css_stream_stop(stream_env->acc_stream) + != IA_CSS_SUCCESS) { + dev_err(isp->dev, "stop acc_stream failed.\n"); + return -EBUSY; + } + } + + if (ia_css_stream_destroy(stream_env->acc_stream) + != IA_CSS_SUCCESS) { + dev_err(isp->dev, "destroy acc_stream failed.\n"); + return -EBUSY; + } + stream_env->acc_stream = NULL; + } + + pipe_config = &stream_env->pipe_configs[CSS_PIPE_ID_ACC]; + ia_css_pipe_config_defaults(pipe_config); + asd->acc.acc_stages = kzalloc(MAX_ACC_STAGES * + sizeof(void *), GFP_KERNEL); + if (!asd->acc.acc_stages) + return -ENOMEM; + pipe_config->acc_stages = asd->acc.acc_stages; + pipe_config->mode = IA_CSS_PIPE_MODE_ACC; + pipe_config->num_acc_stages = 0; + + /* + * We delay the ACC pipeline creation to atomisp_css_start_acc_pipe, + * because pipe configuration will soon be changed by + * atomisp_css_load_acc_binary() + */ + return 0; +} + +int atomisp_css_start_acc_pipe(struct atomisp_sub_device *asd) +{ + struct atomisp_device *isp = asd->isp; + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + struct ia_css_pipe_config *pipe_config = + &stream_env->pipe_configs[IA_CSS_PIPE_ID_ACC]; + + if (ia_css_pipe_create(pipe_config, + &stream_env->pipes[IA_CSS_PIPE_ID_ACC]) != IA_CSS_SUCCESS) { + dev_err(isp->dev, "%s: ia_css_pipe_create failed\n", + __func__); + return -EBADE; + } + + memset(&stream_env->acc_stream_config, 0, + sizeof(struct ia_css_stream_config)); + if (ia_css_stream_create(&stream_env->acc_stream_config, 1, + &stream_env->pipes[IA_CSS_PIPE_ID_ACC], + &stream_env->acc_stream) != IA_CSS_SUCCESS) { + dev_err(isp->dev, "%s: create acc_stream error.\n", __func__); + return -EINVAL; + } + stream_env->acc_stream_state = CSS_STREAM_CREATED; + + init_completion(&asd->acc.acc_done); + asd->acc.pipeline = stream_env->pipes[IA_CSS_PIPE_ID_ACC]; + + atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_MAX, false); + + if (ia_css_start_sp() != IA_CSS_SUCCESS) { + dev_err(isp->dev, "start sp error.\n"); + return -EIO; + } + + if (ia_css_stream_start(stream_env->acc_stream) + != IA_CSS_SUCCESS) { + dev_err(isp->dev, "acc_stream start error.\n"); + return -EIO; + } + + stream_env->acc_stream_state = CSS_STREAM_STARTED; + return 0; +} + +int atomisp_css_stop_acc_pipe(struct atomisp_sub_device *asd) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + if (stream_env->acc_stream_state == CSS_STREAM_STARTED) { + ia_css_stream_stop(stream_env->acc_stream); + stream_env->acc_stream_state = CSS_STREAM_STOPPED; + } + return 0; +} + +void atomisp_css_destroy_acc_pipe(struct atomisp_sub_device *asd) +{ + struct atomisp_stream_env *stream_env = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL]; + if (stream_env->acc_stream) { + if (ia_css_stream_destroy(stream_env->acc_stream) + != IA_CSS_SUCCESS) + dev_warn(asd->isp->dev, + "destroy acc_stream failed.\n"); + stream_env->acc_stream = NULL; + } + + if (stream_env->pipes[IA_CSS_PIPE_ID_ACC]) { + if (ia_css_pipe_destroy(stream_env->pipes[IA_CSS_PIPE_ID_ACC]) + != IA_CSS_SUCCESS) + dev_warn(asd->isp->dev, + "destroy ACC pipe failed.\n"); + stream_env->pipes[IA_CSS_PIPE_ID_ACC] = NULL; + stream_env->update_pipe[IA_CSS_PIPE_ID_ACC] = false; + ia_css_pipe_config_defaults( + &stream_env->pipe_configs[IA_CSS_PIPE_ID_ACC]); + ia_css_pipe_extra_config_defaults( + &stream_env->pipe_extra_configs[IA_CSS_PIPE_ID_ACC]); + } + asd->acc.pipeline = NULL; + + /* css 2.0 API limitation: ia_css_stop_sp() could be only called after + * destroy all pipes + */ + ia_css_stop_sp(); + + kfree(asd->acc.acc_stages); + asd->acc.acc_stages = NULL; + + atomisp_freq_scaling(asd->isp, ATOMISP_DFS_MODE_LOW, false); +} + +int atomisp_css_load_acc_binary(struct atomisp_sub_device *asd, + struct atomisp_css_fw_info *fw, + unsigned int index) +{ + struct ia_css_pipe_config *pipe_config = + &asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL] + .pipe_configs[IA_CSS_PIPE_ID_ACC]; + + if (index >= MAX_ACC_STAGES) { + dev_dbg(asd->isp->dev, "%s: index(%d) out of range\n", + __func__, index); + return -ENOMEM; + } + + pipe_config->acc_stages[index] = fw; + pipe_config->num_acc_stages = index + 1; + pipe_config->acc_num_execs = 1; + + return 0; +} + +static struct atomisp_sub_device *__get_atomisp_subdev( + struct ia_css_pipe *css_pipe, + struct atomisp_device *isp, + enum atomisp_input_stream_id *stream_id) { + int i, j, k; + struct atomisp_sub_device *asd; + struct atomisp_stream_env *stream_env; + + for (i = 0; i < isp->num_of_streams; i++) { + asd = &isp->asd[i]; + if (asd->streaming == ATOMISP_DEVICE_STREAMING_DISABLED && + !asd->acc.pipeline) + continue; + for (j = 0; j < ATOMISP_INPUT_STREAM_NUM; j++) { + stream_env = &asd->stream_env[j]; + for (k = 0; k < IA_CSS_PIPE_ID_NUM; k++) { + if (stream_env->pipes[k] && + stream_env->pipes[k] == css_pipe) { + *stream_id = j; + return asd; + } + } + } + } + + return NULL; +} + +int atomisp_css_isr_thread(struct atomisp_device *isp, + bool *frame_done_found, + bool *css_pipe_done) +{ + enum atomisp_input_stream_id stream_id = 0; + struct atomisp_css_event current_event; + struct atomisp_sub_device *asd = &isp->asd[0]; +#ifndef ISP2401 + bool reset_wdt_timer[MAX_STREAM_NUM] = {false}; +#endif + int i; + + while (!atomisp_css_dequeue_event(¤t_event)) { + if (current_event.event.type == + IA_CSS_EVENT_TYPE_FW_ASSERT) { + /* + * Received FW assertion signal, + * trigger WDT to recover + */ + dev_err(isp->dev, "%s: ISP reports FW_ASSERT event! fw_assert_module_id %d fw_assert_line_no %d\n", + __func__, + current_event.event.fw_assert_module_id, + current_event.event.fw_assert_line_no); + for (i = 0; i < isp->num_of_streams; i++) + atomisp_wdt_stop(&isp->asd[i], 0); +#ifndef ISP2401 + atomisp_wdt((unsigned long)isp); +#else + queue_work(isp->wdt_work_queue, &isp->wdt_work); +#endif + return -EINVAL; + } else if (current_event.event.type == IA_CSS_EVENT_TYPE_FW_WARNING) { + dev_warn(isp->dev, "%s: ISP reports warning, code is %d, exp_id %d\n", + __func__, current_event.event.fw_warning, + current_event.event.exp_id); + continue; + } + + asd = __get_atomisp_subdev(current_event.event.pipe, + isp, &stream_id); + if (!asd) { + if (current_event.event.type == CSS_EVENT_TIMER) + dev_dbg(isp->dev, + "event: Timer event."); + else + dev_warn(isp->dev, "%s:no subdev.event:%d", + __func__, + current_event.event.type); + continue; + } + + atomisp_css_temp_pipe_to_pipe_id(asd, ¤t_event); + switch (current_event.event.type) { + case CSS_EVENT_OUTPUT_FRAME_DONE: + frame_done_found[asd->index] = true; + atomisp_buf_done(asd, 0, CSS_BUFFER_TYPE_OUTPUT_FRAME, + current_event.pipe, true, stream_id); +#ifndef ISP2401 + reset_wdt_timer[asd->index] = true; /* ISP running */ +#endif + break; + case CSS_EVENT_SEC_OUTPUT_FRAME_DONE: + frame_done_found[asd->index] = true; + atomisp_buf_done(asd, 0, CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME, + current_event.pipe, true, stream_id); +#ifndef ISP2401 + reset_wdt_timer[asd->index] = true; /* ISP running */ +#endif + break; + case CSS_EVENT_3A_STATISTICS_DONE: + atomisp_buf_done(asd, 0, + CSS_BUFFER_TYPE_3A_STATISTICS, + current_event.pipe, + false, stream_id); + break; + case CSS_EVENT_METADATA_DONE: + atomisp_buf_done(asd, 0, + CSS_BUFFER_TYPE_METADATA, + current_event.pipe, + false, stream_id); + break; + case CSS_EVENT_VF_OUTPUT_FRAME_DONE: + atomisp_buf_done(asd, 0, + CSS_BUFFER_TYPE_VF_OUTPUT_FRAME, + current_event.pipe, true, stream_id); +#ifndef ISP2401 + reset_wdt_timer[asd->index] = true; /* ISP running */ +#endif + break; + case CSS_EVENT_SEC_VF_OUTPUT_FRAME_DONE: + atomisp_buf_done(asd, 0, + CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME, + current_event.pipe, true, stream_id); +#ifndef ISP2401 + reset_wdt_timer[asd->index] = true; /* ISP running */ +#endif + break; + case CSS_EVENT_DIS_STATISTICS_DONE: + atomisp_buf_done(asd, 0, + CSS_BUFFER_TYPE_DIS_STATISTICS, + current_event.pipe, + false, stream_id); + break; + case CSS_EVENT_PIPELINE_DONE: + css_pipe_done[asd->index] = true; + break; + case CSS_EVENT_ACC_STAGE_COMPLETE: + atomisp_acc_done(asd, current_event.event.fw_handle); + break; + default: + dev_dbg(isp->dev, "unhandled css stored event: 0x%x\n", + current_event.event.type); + break; + } + } +#ifndef ISP2401 + /* If there are no buffers queued then + * delete wdt timer. */ + for (i = 0; i < isp->num_of_streams; i++) { + asd = &isp->asd[i]; + if (!asd) + continue; + if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED) + continue; + if (!atomisp_buffers_queued(asd)) + atomisp_wdt_stop(asd, false); + else if (reset_wdt_timer[i]) + /* SOF irq should not reset wdt timer. */ + atomisp_wdt_refresh(asd, + ATOMISP_WDT_KEEP_CURRENT_DELAY); + } +#endif + + return 0; +} + +void atomisp_set_stop_timeout(unsigned int timeout) +{ + return; +} + +bool atomisp_css_valid_sof(struct atomisp_device *isp) +{ + unsigned int i, j; + + /* Loop for each css stream */ + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd = &isp->asd[i]; + /* Loop for each css vc stream */ + for (j = 0; j < ATOMISP_INPUT_STREAM_NUM; j++) { + if (asd->stream_env[j].stream && + asd->stream_env[j].stream_config.mode == + IA_CSS_INPUT_MODE_BUFFERED_SENSOR) + return false; + } + } + + return true; +} + +int atomisp_css_debug_dump_isp_binary(void) +{ + ia_css_debug_dump_isp_binary(); + return 0; +} + +int atomisp_css_dump_sp_raw_copy_linecount(bool reduced) +{ + sh_css_dump_sp_raw_copy_linecount(reduced); + return 0; +} + +int atomisp_css_dump_blob_infor(void) +{ + struct ia_css_blob_descr *bd = sh_css_blob_info; + unsigned i, nm = sh_css_num_binaries; + + if (nm == 0) + return -EPERM; + if (bd == NULL) + return -EPERM; + + for (i = 1; i < sh_css_num_binaries; i++) + dev_dbg(atomisp_dev, "Num%d binary id is %d, name is %s\n", i, + bd[i-1].header.info.isp.sp.id, bd[i-1].name); + + return 0; +} + +void atomisp_css_set_isp_config_id(struct atomisp_sub_device *asd, + uint32_t isp_config_id) +{ + asd->params.config.isp_config_id = isp_config_id; +} + +void atomisp_css_set_isp_config_applied_frame(struct atomisp_sub_device *asd, + struct atomisp_css_frame *output_frame) +{ + asd->params.config.output_frame = output_frame; +} + +int atomisp_get_css_dbgfunc(void) +{ + return dbg_func; +} + +int atomisp_set_css_dbgfunc(struct atomisp_device *isp, int opt) +{ + int ret; + + ret = __set_css_print_env(isp, opt); + if (0 == ret) + dbg_func = opt; + + return ret; +} +void atomisp_en_dz_capt_pipe(struct atomisp_sub_device *asd, bool enable) +{ + ia_css_en_dz_capt_pipe( + asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream, + enable); +} + +struct atomisp_css_dvs_grid_info *atomisp_css_get_dvs_grid_info( + struct atomisp_css_grid_info *grid_info) +{ + if (!grid_info) + return NULL; + +#ifdef IA_CSS_DVS_STAT_GRID_INFO_SUPPORTED + return &grid_info->dvs_grid.dvs_grid_info; +#else + return &grid_info->dvs_grid; +#endif +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_css20.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_css20.h new file mode 100644 index 0000000000000000000000000000000000000000..b62ad9082018b204ee74574f842044c12c2f4e5f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_css20.h @@ -0,0 +1,282 @@ +/* + * Support for Clovertrail PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __ATOMISP_COMPAT_CSS20_H__ +#define __ATOMISP_COMPAT_CSS20_H__ + +#include + +#include "ia_css.h" +#include "ia_css_types.h" +#include "ia_css_acc_types.h" +#include "sh_css_legacy.h" + +#define ATOMISP_CSS2_PIPE_MAX 2 +#define ATOMISP_CSS2_NUM_OFFLINE_INIT_CONTINUOUS_FRAMES 3 +#define ATOMISP_CSS2_NUM_OFFLINE_INIT_CONTINUOUS_FRAMES_LOCK_EN 4 +#define ATOMISP_CSS2_NUM_DVS_FRAME_DELAY 2 + +#define atomisp_css_pipe_id ia_css_pipe_id +#define atomisp_css_pipeline ia_css_pipe +#define atomisp_css_buffer_type ia_css_buffer_type +#define atomisp_css_dis_data ia_css_isp_dvs_statistics +#define atomisp_css_irq_info ia_css_irq_info +#define atomisp_css_isp_config ia_css_isp_config +#define atomisp_css_bayer_order ia_css_bayer_order +#define atomisp_css_stream_format ia_css_stream_format +#define atomisp_css_capture_mode ia_css_capture_mode +#define atomisp_css_input_mode ia_css_input_mode +#define atomisp_css_frame ia_css_frame +#define atomisp_css_frame_format ia_css_frame_format +#define atomisp_css_frame_info ia_css_frame_info +#define atomisp_css_dp_config ia_css_dp_config +#define atomisp_css_wb_config ia_css_wb_config +#define atomisp_css_cc_config ia_css_cc_config +#define atomisp_css_nr_config ia_css_nr_config +#define atomisp_css_ee_config ia_css_ee_config +#define atomisp_css_ob_config ia_css_ob_config +#define atomisp_css_de_config ia_css_de_config +#define atomisp_css_dz_config ia_css_dz_config +#define atomisp_css_ce_config ia_css_ce_config +#define atomisp_css_gc_config ia_css_gc_config +#define atomisp_css_tnr_config ia_css_tnr_config +#define atomisp_css_cnr_config ia_css_cnr_config +#define atomisp_css_ctc_config ia_css_ctc_config +#define atomisp_css_3a_config ia_css_3a_config +#define atomisp_css_ecd_config ia_css_ecd_config +#define atomisp_css_ynr_config ia_css_ynr_config +#define atomisp_css_fc_config ia_css_fc_config +#define atomisp_css_aa_config ia_css_aa_config +#define atomisp_css_baa_config ia_css_aa_config +#define atomisp_css_anr_config ia_css_anr_config +#define atomisp_css_xnr_config ia_css_xnr_config +#define atomisp_css_macc_config ia_css_macc_config +#define atomisp_css_gamma_table ia_css_gamma_table +#define atomisp_css_ctc_table ia_css_ctc_table +#define atomisp_css_macc_table ia_css_macc_table +#define atomisp_css_xnr_table ia_css_xnr_table +#define atomisp_css_rgb_gamma_table ia_css_rgb_gamma_table +#define atomisp_css_anr_thres ia_css_anr_thres +#define atomisp_css_dvs_6axis ia_css_dvs_6axis_config +#define atomisp_css_grid_info ia_css_grid_info +#define atomisp_css_3a_grid_info ia_css_3a_grid_info +#define atomisp_css_dvs_grid_info ia_css_dvs_grid_info +#define atomisp_css_shading_table ia_css_shading_table +#define atomisp_css_morph_table ia_css_morph_table +#define atomisp_css_dvs_6axis_config ia_css_dvs_6axis_config +#define atomisp_css_fw_info ia_css_fw_info +#define atomisp_css_formats_config ia_css_formats_config + +#define CSS_PIPE_ID_PREVIEW IA_CSS_PIPE_ID_PREVIEW +#define CSS_PIPE_ID_COPY IA_CSS_PIPE_ID_COPY +#define CSS_PIPE_ID_VIDEO IA_CSS_PIPE_ID_VIDEO +#define CSS_PIPE_ID_CAPTURE IA_CSS_PIPE_ID_CAPTURE +#define CSS_PIPE_ID_ACC IA_CSS_PIPE_ID_ACC +#define CSS_PIPE_ID_YUVPP IA_CSS_PIPE_ID_YUVPP +#define CSS_PIPE_ID_NUM IA_CSS_PIPE_ID_NUM + +#define CSS_INPUT_MODE_SENSOR IA_CSS_INPUT_MODE_BUFFERED_SENSOR +#define CSS_INPUT_MODE_FIFO IA_CSS_INPUT_MODE_FIFO +#define CSS_INPUT_MODE_TPG IA_CSS_INPUT_MODE_TPG +#define CSS_INPUT_MODE_PRBS IA_CSS_INPUT_MODE_PRBS +#define CSS_INPUT_MODE_MEMORY IA_CSS_INPUT_MODE_MEMORY + +#define CSS_IRQ_INFO_CSS_RECEIVER_ERROR IA_CSS_IRQ_INFO_CSS_RECEIVER_ERROR +#define CSS_IRQ_INFO_EVENTS_READY IA_CSS_IRQ_INFO_EVENTS_READY +#define CSS_IRQ_INFO_INPUT_SYSTEM_ERROR \ + IA_CSS_IRQ_INFO_INPUT_SYSTEM_ERROR +#define CSS_IRQ_INFO_IF_ERROR IA_CSS_IRQ_INFO_IF_ERROR + +#define CSS_BUFFER_TYPE_NUM IA_CSS_BUFFER_TYPE_NUM + +#define CSS_FRAME_FLASH_STATE_NONE IA_CSS_FRAME_FLASH_STATE_NONE +#define CSS_FRAME_FLASH_STATE_PARTIAL IA_CSS_FRAME_FLASH_STATE_PARTIAL +#define CSS_FRAME_FLASH_STATE_FULL IA_CSS_FRAME_FLASH_STATE_FULL + +#define CSS_BAYER_ORDER_GRBG IA_CSS_BAYER_ORDER_GRBG +#define CSS_BAYER_ORDER_RGGB IA_CSS_BAYER_ORDER_RGGB +#define CSS_BAYER_ORDER_BGGR IA_CSS_BAYER_ORDER_BGGR +#define CSS_BAYER_ORDER_GBRG IA_CSS_BAYER_ORDER_GBRG + +/* + * Hide IA_ naming difference in otherwise common CSS macros. + */ +#define CSS_ID(val) (IA_ ## val) +#define CSS_EVENT(val) (IA_CSS_EVENT_TYPE_ ## val) +#define CSS_FORMAT(val) (IA_CSS_STREAM_FORMAT_ ## val) + +#define CSS_EVENT_PORT_EOF CSS_EVENT(PORT_EOF) +#define CSS_EVENT_FRAME_TAGGED CSS_EVENT(FRAME_TAGGED) + +#define CSS_MIPI_FRAME_BUFFER_SIZE_1 0x60000 +#define CSS_MIPI_FRAME_BUFFER_SIZE_2 0x80000 + +struct atomisp_device; +struct atomisp_sub_device; + +#define MAX_STREAMS_PER_CHANNEL 2 + +/* + * These are used to indicate the css stream state, corresponding + * stream handling can be done via judging the different state. + */ +enum atomisp_css_stream_state { + CSS_STREAM_UNINIT, + CSS_STREAM_CREATED, + CSS_STREAM_STARTED, + CSS_STREAM_STOPPED, +}; + +/* + * Sensor of external ISP can send multiple steams with different mipi data + * type in the same virtual channel. This information needs to come from the + * sensor or external ISP + */ +struct atomisp_css_isys_config_info { + unsigned int input_format; + unsigned int width; + unsigned int height; +}; + +struct atomisp_stream_env { + struct ia_css_stream *stream; + struct ia_css_stream_config stream_config; + struct ia_css_stream_info stream_info; + struct ia_css_pipe *pipes[IA_CSS_PIPE_ID_NUM]; + struct ia_css_pipe *multi_pipes[IA_CSS_PIPE_ID_NUM]; + struct ia_css_pipe_config pipe_configs[IA_CSS_PIPE_ID_NUM]; + struct ia_css_pipe_extra_config pipe_extra_configs[IA_CSS_PIPE_ID_NUM]; + bool update_pipe[IA_CSS_PIPE_ID_NUM]; + enum atomisp_css_stream_state stream_state; + struct ia_css_stream *acc_stream; + enum atomisp_css_stream_state acc_stream_state; + struct ia_css_stream_config acc_stream_config; + unsigned int ch_id; /* virtual channel ID */ + unsigned int isys_configs; + struct atomisp_css_isys_config_info isys_info[MAX_STREAMS_PER_CHANNEL]; +}; + +struct atomisp_css_env { + struct ia_css_env isp_css_env; + struct ia_css_fw isp_css_fw; +}; + +struct atomisp_s3a_buf { + struct ia_css_isp_3a_statistics *s3a_data; + struct ia_css_isp_3a_statistics_map *s3a_map; + struct list_head list; +}; + +struct atomisp_dis_buf { + struct atomisp_css_dis_data *dis_data; + struct ia_css_isp_dvs_statistics_map *dvs_map; + struct list_head list; +}; + +struct atomisp_css_buffer { + struct ia_css_buffer css_buffer; +}; + +struct atomisp_css_event { + enum atomisp_css_pipe_id pipe; + struct ia_css_event event; +}; + +void atomisp_css_set_macc_config(struct atomisp_sub_device *asd, + struct atomisp_css_macc_config *macc_config); + +void atomisp_css_set_ecd_config(struct atomisp_sub_device *asd, + struct atomisp_css_ecd_config *ecd_config); + +void atomisp_css_set_ynr_config(struct atomisp_sub_device *asd, + struct atomisp_css_ynr_config *ynr_config); + +void atomisp_css_set_fc_config(struct atomisp_sub_device *asd, + struct atomisp_css_fc_config *fc_config); + +void atomisp_css_set_aa_config(struct atomisp_sub_device *asd, + struct atomisp_css_aa_config *aa_config); + +void atomisp_css_set_baa_config(struct atomisp_sub_device *asd, + struct atomisp_css_baa_config *baa_config); + +void atomisp_css_set_anr_config(struct atomisp_sub_device *asd, + struct atomisp_css_anr_config *anr_config); + +void atomisp_css_set_xnr_config(struct atomisp_sub_device *asd, + struct atomisp_css_xnr_config *xnr_config); + +void atomisp_css_set_cnr_config(struct atomisp_sub_device *asd, + struct atomisp_css_cnr_config *cnr_config); + +void atomisp_css_set_ctc_config(struct atomisp_sub_device *asd, + struct atomisp_css_ctc_config *ctc_config); + +void atomisp_css_set_yuv2rgb_cc_config(struct atomisp_sub_device *asd, + struct atomisp_css_cc_config *yuv2rgb_cc_config); + +void atomisp_css_set_rgb2yuv_cc_config(struct atomisp_sub_device *asd, + struct atomisp_css_cc_config *rgb2yuv_cc_config); + +void atomisp_css_set_xnr_table(struct atomisp_sub_device *asd, + struct atomisp_css_xnr_table *xnr_table); + +void atomisp_css_set_r_gamma_table(struct atomisp_sub_device *asd, + struct atomisp_css_rgb_gamma_table *r_gamma_table); + +void atomisp_css_set_g_gamma_table(struct atomisp_sub_device *asd, + struct atomisp_css_rgb_gamma_table *g_gamma_table); + +void atomisp_css_set_b_gamma_table(struct atomisp_sub_device *asd, + struct atomisp_css_rgb_gamma_table *b_gamma_table); + +void atomisp_css_set_anr_thres(struct atomisp_sub_device *asd, + struct atomisp_css_anr_thres *anr_thres); + +int atomisp_css_check_firmware_version(struct atomisp_device *isp); + +int atomisp_css_load_firmware(struct atomisp_device *isp); + +void atomisp_css_unload_firmware(struct atomisp_device *isp); + +void atomisp_css_set_dvs_6axis(struct atomisp_sub_device *asd, + struct atomisp_css_dvs_6axis *dvs_6axis); + +unsigned int atomisp_css_debug_get_dtrace_level(void); + +int atomisp_css_debug_dump_isp_binary(void); + +int atomisp_css_dump_sp_raw_copy_linecount(bool reduced); + +int atomisp_css_dump_blob_infor(void); + +void atomisp_css_set_isp_config_id(struct atomisp_sub_device *asd, + uint32_t isp_config_id); + +void atomisp_css_set_isp_config_applied_frame(struct atomisp_sub_device *asd, + struct atomisp_css_frame *output_frame); + +int atomisp_get_css_dbgfunc(void); + +int atomisp_set_css_dbgfunc(struct atomisp_device *isp, int opt); +struct atomisp_css_dvs_grid_info *atomisp_css_get_dvs_grid_info( + struct atomisp_css_grid_info *grid_info); +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_ioctl32.c b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_ioctl32.c new file mode 100644 index 0000000000000000000000000000000000000000..0592ac1f2832eedd947dcc3c1d39dad917454751 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_ioctl32.c @@ -0,0 +1,1263 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#ifdef CONFIG_COMPAT +#include + +#include + +#include "atomisp_internal.h" +#include "atomisp_compat.h" +#include "atomisp_compat_ioctl32.h" + +static int get_atomisp_histogram32(struct atomisp_histogram *kp, + struct atomisp_histogram32 __user *up) +{ + compat_uptr_t tmp; + + if (!access_ok(VERIFY_READ, up, sizeof(struct atomisp_histogram32)) || + get_user(kp->num_elements, &up->num_elements) || + get_user(tmp, &up->data)) + return -EFAULT; + + kp->data = compat_ptr(tmp); + return 0; +} + +static int put_atomisp_histogram32(struct atomisp_histogram *kp, + struct atomisp_histogram32 __user *up) +{ + compat_uptr_t tmp = (compat_uptr_t)((uintptr_t)kp->data); + + if (!access_ok(VERIFY_WRITE, up, sizeof(struct atomisp_histogram32)) || + put_user(kp->num_elements, &up->num_elements) || + put_user(tmp, &up->data)) + return -EFAULT; + + return 0; +} + +static inline int get_v4l2_pix_format(struct v4l2_pix_format *kp, + struct v4l2_pix_format __user *up) +{ + if (copy_from_user(kp, up, sizeof(struct v4l2_pix_format))) + return -EFAULT; + return 0; +} + +static inline int put_v4l2_pix_format(struct v4l2_pix_format *kp, + struct v4l2_pix_format __user *up) +{ + if (copy_to_user(up, kp, sizeof(struct v4l2_pix_format))) + return -EFAULT; + return 0; +} + +static int get_v4l2_framebuffer32(struct v4l2_framebuffer *kp, + struct v4l2_framebuffer32 __user *up) +{ + compat_uptr_t tmp; + + if (!access_ok(VERIFY_READ, up, sizeof(struct v4l2_framebuffer32)) || + get_user(tmp, &up->base) || + get_user(kp->capability, &up->capability) || + get_user(kp->flags, &up->flags)) + return -EFAULT; + + kp->base = compat_ptr(tmp); + get_v4l2_pix_format((struct v4l2_pix_format *)&kp->fmt, &up->fmt); + return 0; +} + +static int get_atomisp_dis_statistics32(struct atomisp_dis_statistics *kp, + struct atomisp_dis_statistics32 __user *up) +{ + compat_uptr_t hor_prod_odd_real; + compat_uptr_t hor_prod_odd_imag; + compat_uptr_t hor_prod_even_real; + compat_uptr_t hor_prod_even_imag; + compat_uptr_t ver_prod_odd_real; + compat_uptr_t ver_prod_odd_imag; + compat_uptr_t ver_prod_even_real; + compat_uptr_t ver_prod_even_imag; + + if (!access_ok(VERIFY_READ, up, + sizeof(struct atomisp_dis_statistics32)) || + copy_from_user(kp, up, sizeof(struct atomisp_dvs_grid_info)) || + get_user(hor_prod_odd_real, + &up->dvs2_stat.hor_prod.odd_real) || + get_user(hor_prod_odd_imag, + &up->dvs2_stat.hor_prod.odd_imag) || + get_user(hor_prod_even_real, + &up->dvs2_stat.hor_prod.even_real) || + get_user(hor_prod_even_imag, + &up->dvs2_stat.hor_prod.even_imag) || + get_user(ver_prod_odd_real, + &up->dvs2_stat.ver_prod.odd_real) || + get_user(ver_prod_odd_imag, + &up->dvs2_stat.ver_prod.odd_imag) || + get_user(ver_prod_even_real, + &up->dvs2_stat.ver_prod.even_real) || + get_user(ver_prod_even_imag, + &up->dvs2_stat.ver_prod.even_imag) || + get_user(kp->exp_id, &up->exp_id)) + return -EFAULT; + + kp->dvs2_stat.hor_prod.odd_real = compat_ptr(hor_prod_odd_real); + kp->dvs2_stat.hor_prod.odd_imag = compat_ptr(hor_prod_odd_imag); + kp->dvs2_stat.hor_prod.even_real = compat_ptr(hor_prod_even_real); + kp->dvs2_stat.hor_prod.even_imag = compat_ptr(hor_prod_even_imag); + kp->dvs2_stat.ver_prod.odd_real = compat_ptr(ver_prod_odd_real); + kp->dvs2_stat.ver_prod.odd_imag = compat_ptr(ver_prod_odd_imag); + kp->dvs2_stat.ver_prod.even_real = compat_ptr(ver_prod_even_real); + kp->dvs2_stat.ver_prod.even_imag = compat_ptr(ver_prod_even_imag); + return 0; +} + +static int put_atomisp_dis_statistics32(struct atomisp_dis_statistics *kp, + struct atomisp_dis_statistics32 __user *up) +{ + compat_uptr_t hor_prod_odd_real = + (compat_uptr_t)((uintptr_t)kp->dvs2_stat.hor_prod.odd_real); + compat_uptr_t hor_prod_odd_imag = + (compat_uptr_t)((uintptr_t)kp->dvs2_stat.hor_prod.odd_imag); + compat_uptr_t hor_prod_even_real = + (compat_uptr_t)((uintptr_t)kp->dvs2_stat.hor_prod.even_real); + compat_uptr_t hor_prod_even_imag = + (compat_uptr_t)((uintptr_t)kp->dvs2_stat.hor_prod.even_imag); + compat_uptr_t ver_prod_odd_real = + (compat_uptr_t)((uintptr_t)kp->dvs2_stat.ver_prod.odd_real); + compat_uptr_t ver_prod_odd_imag = + (compat_uptr_t)((uintptr_t)kp->dvs2_stat.ver_prod.odd_imag); + compat_uptr_t ver_prod_even_real = + (compat_uptr_t)((uintptr_t)kp->dvs2_stat.ver_prod.even_real); + compat_uptr_t ver_prod_even_imag = + (compat_uptr_t)((uintptr_t)kp->dvs2_stat.ver_prod.even_imag); + + if (!access_ok(VERIFY_WRITE, up, + sizeof(struct atomisp_dis_statistics32)) || + copy_to_user(up, kp, sizeof(struct atomisp_dvs_grid_info)) || + put_user(hor_prod_odd_real, + &up->dvs2_stat.hor_prod.odd_real) || + put_user(hor_prod_odd_imag, + &up->dvs2_stat.hor_prod.odd_imag) || + put_user(hor_prod_even_real, + &up->dvs2_stat.hor_prod.even_real) || + put_user(hor_prod_even_imag, + &up->dvs2_stat.hor_prod.even_imag) || + put_user(ver_prod_odd_real, + &up->dvs2_stat.ver_prod.odd_real) || + put_user(ver_prod_odd_imag, + &up->dvs2_stat.ver_prod.odd_imag) || + put_user(ver_prod_even_real, + &up->dvs2_stat.ver_prod.even_real) || + put_user(ver_prod_even_imag, + &up->dvs2_stat.ver_prod.even_imag) || + put_user(kp->exp_id, &up->exp_id)) + return -EFAULT; + + return 0; +} + +static int get_atomisp_dis_coefficients32(struct atomisp_dis_coefficients *kp, + struct atomisp_dis_coefficients32 __user *up) +{ + compat_uptr_t hor_coefs_odd_real; + compat_uptr_t hor_coefs_odd_imag; + compat_uptr_t hor_coefs_even_real; + compat_uptr_t hor_coefs_even_imag; + compat_uptr_t ver_coefs_odd_real; + compat_uptr_t ver_coefs_odd_imag; + compat_uptr_t ver_coefs_even_real; + compat_uptr_t ver_coefs_even_imag; + + if (!access_ok(VERIFY_READ, up, + sizeof(struct atomisp_dis_coefficients32)) || + copy_from_user(kp, up, sizeof(struct atomisp_dvs_grid_info)) || + get_user(hor_coefs_odd_real, &up->hor_coefs.odd_real) || + get_user(hor_coefs_odd_imag, &up->hor_coefs.odd_imag) || + get_user(hor_coefs_even_real, &up->hor_coefs.even_real) || + get_user(hor_coefs_even_imag, &up->hor_coefs.even_imag) || + get_user(ver_coefs_odd_real, &up->ver_coefs.odd_real) || + get_user(ver_coefs_odd_imag, &up->ver_coefs.odd_imag) || + get_user(ver_coefs_even_real, &up->ver_coefs.even_real) || + get_user(ver_coefs_even_imag, &up->ver_coefs.even_imag)) + return -EFAULT; + + kp->hor_coefs.odd_real = compat_ptr(hor_coefs_odd_real); + kp->hor_coefs.odd_imag = compat_ptr(hor_coefs_odd_imag); + kp->hor_coefs.even_real = compat_ptr(hor_coefs_even_real); + kp->hor_coefs.even_imag = compat_ptr(hor_coefs_even_imag); + kp->ver_coefs.odd_real = compat_ptr(ver_coefs_odd_real); + kp->ver_coefs.odd_imag = compat_ptr(ver_coefs_odd_imag); + kp->ver_coefs.even_real = compat_ptr(ver_coefs_even_real); + kp->ver_coefs.even_imag = compat_ptr(ver_coefs_even_imag); + return 0; +} + +static int get_atomisp_dvs_6axis_config32(struct atomisp_dvs_6axis_config *kp, + struct atomisp_dvs_6axis_config32 __user *up) +{ compat_uptr_t xcoords_y; + compat_uptr_t ycoords_y; + compat_uptr_t xcoords_uv; + compat_uptr_t ycoords_uv; + + if (!access_ok(VERIFY_READ, up, + sizeof(struct atomisp_dvs_6axis_config32)) || + get_user(kp->exp_id, &up->exp_id) || + get_user(kp->width_y, &up->width_y) || + get_user(kp->height_y, &up->height_y) || + get_user(kp->width_uv, &up->width_uv) || + get_user(kp->height_uv, &up->height_uv) || + get_user(xcoords_y, &up->xcoords_y) || + get_user(ycoords_y, &up->ycoords_y) || + get_user(xcoords_uv, &up->xcoords_uv) || + get_user(ycoords_uv, &up->ycoords_uv)) + return -EFAULT; + + kp->xcoords_y = compat_ptr(xcoords_y); + kp->ycoords_y = compat_ptr(ycoords_y); + kp->xcoords_uv = compat_ptr(xcoords_uv); + kp->ycoords_uv = compat_ptr(ycoords_uv); + return 0; +} + +static int get_atomisp_3a_statistics32(struct atomisp_3a_statistics *kp, + struct atomisp_3a_statistics32 __user *up) +{ + compat_uptr_t data; + compat_uptr_t rgby_data; + + if (!access_ok(VERIFY_READ, up, + sizeof(struct atomisp_3a_statistics32)) || + copy_from_user(kp, up, sizeof(struct atomisp_grid_info)) || + get_user(rgby_data, &up->rgby_data) || + get_user(data, &up->data) || + get_user(kp->exp_id, &up->exp_id) || + get_user(kp->isp_config_id, &up->isp_config_id)) + return -EFAULT; + + kp->data = compat_ptr(data); + kp->rgby_data = compat_ptr(rgby_data); + + return 0; +} + +static int put_atomisp_3a_statistics32(struct atomisp_3a_statistics *kp, + struct atomisp_3a_statistics32 __user *up) +{ + compat_uptr_t data = (compat_uptr_t)((uintptr_t)kp->data); + compat_uptr_t rgby_data = (compat_uptr_t)((uintptr_t)kp->rgby_data); + + if (!access_ok(VERIFY_WRITE, up, + sizeof(struct atomisp_3a_statistics32)) || + copy_to_user(up, kp, sizeof(struct atomisp_grid_info)) || + put_user(rgby_data, &up->rgby_data) || + put_user(data, &up->data) || + put_user(kp->exp_id, &up->exp_id) || + put_user(kp->isp_config_id, &up->isp_config_id)) + return -EFAULT; + + return 0; +} + + +static int get_atomisp_metadata_stat32(struct atomisp_metadata *kp, + struct atomisp_metadata32 __user *up) +{ + compat_uptr_t data; + compat_uptr_t effective_width; + + if (!access_ok(VERIFY_READ, up, + sizeof(struct atomisp_metadata32)) || + get_user(data, &up->data) || + get_user(kp->width, &up->width) || + get_user(kp->height, &up->height) || + get_user(kp->stride, &up->stride) || + get_user(kp->exp_id, &up->exp_id) || + get_user(effective_width, &up->effective_width)) + return -EFAULT; + + kp->data = compat_ptr(data); + kp->effective_width = compat_ptr(effective_width); + return 0; +} + + +static int put_atomisp_metadata_stat32(struct atomisp_metadata *kp, + struct atomisp_metadata32 __user *up) +{ + compat_uptr_t data = (compat_uptr_t)((uintptr_t)kp->data); + compat_uptr_t effective_width = + (compat_uptr_t)((uintptr_t)kp->effective_width); + if (!access_ok(VERIFY_WRITE, up, + sizeof(struct atomisp_metadata32)) || + put_user(data, &up->data) || + put_user(kp->width, &up->width) || + put_user(kp->height, &up->height) || + put_user(kp->stride, &up->stride) || + put_user(kp->exp_id, &up->exp_id) || + put_user(effective_width, &up->effective_width)) + return -EFAULT; + + return 0; +} + +static int put_atomisp_metadata_by_type_stat32( + struct atomisp_metadata_with_type *kp, + struct atomisp_metadata_with_type32 __user *up) +{ + compat_uptr_t data = (compat_uptr_t)((uintptr_t)kp->data); + compat_uptr_t effective_width = + (compat_uptr_t)((uintptr_t)kp->effective_width); + if (!access_ok(VERIFY_WRITE, up, + sizeof(struct atomisp_metadata_with_type32)) || + put_user(data, &up->data) || + put_user(kp->width, &up->width) || + put_user(kp->height, &up->height) || + put_user(kp->stride, &up->stride) || + put_user(kp->exp_id, &up->exp_id) || + put_user(effective_width, &up->effective_width) || + put_user(kp->type, &up->type)) + return -EFAULT; + + return 0; +} + +static int get_atomisp_metadata_by_type_stat32( + struct atomisp_metadata_with_type *kp, + struct atomisp_metadata_with_type32 __user *up) +{ + compat_uptr_t data; + compat_uptr_t effective_width; + + if (!access_ok(VERIFY_READ, up, + sizeof(struct atomisp_metadata_with_type32)) || + get_user(data, &up->data) || + get_user(kp->width, &up->width) || + get_user(kp->height, &up->height) || + get_user(kp->stride, &up->stride) || + get_user(kp->exp_id, &up->exp_id) || + get_user(effective_width, &up->effective_width) || + get_user(kp->type, &up->type)) + return -EFAULT; + + kp->data = compat_ptr(data); + kp->effective_width = compat_ptr(effective_width); + return 0; +} + +static int get_atomisp_morph_table32(struct atomisp_morph_table *kp, + struct atomisp_morph_table32 __user *up) +{ + unsigned int n = ATOMISP_MORPH_TABLE_NUM_PLANES; + + if (!access_ok(VERIFY_READ, up, + sizeof(struct atomisp_morph_table32)) || + get_user(kp->enabled, &up->enabled) || + get_user(kp->width, &up->width) || + get_user(kp->height, &up->height)) + return -EFAULT; + + while (n-- > 0) { + uintptr_t *coord_kp = (uintptr_t *)&kp->coordinates_x[n]; + + if (get_user((*coord_kp), &up->coordinates_x[n])) + return -EFAULT; + + coord_kp = (uintptr_t *)&kp->coordinates_y[n]; + if (get_user((*coord_kp), &up->coordinates_y[n])) + return -EFAULT; + } + return 0; +} + +static int put_atomisp_morph_table32(struct atomisp_morph_table *kp, + struct atomisp_morph_table32 __user *up) +{ + unsigned int n = ATOMISP_MORPH_TABLE_NUM_PLANES; + + if (!access_ok(VERIFY_WRITE, up, + sizeof(struct atomisp_morph_table32)) || + put_user(kp->enabled, &up->enabled) || + put_user(kp->width, &up->width) || + put_user(kp->height, &up->height)) + return -EFAULT; + + while (n-- > 0) { + uintptr_t *coord_kp = (uintptr_t *)&kp->coordinates_x[n]; + + if (put_user((*coord_kp), &up->coordinates_x[n])) + return -EFAULT; + + coord_kp = (uintptr_t *)&kp->coordinates_y[n]; + if (put_user((*coord_kp), &up->coordinates_y[n])) + return -EFAULT; + } + return 0; +} + +static int get_atomisp_overlay32(struct atomisp_overlay *kp, + struct atomisp_overlay32 __user *up) +{ + compat_uptr_t frame; + if (!access_ok(VERIFY_READ, up, sizeof(struct atomisp_overlay32)) || + get_user(frame, &up->frame) || + get_user(kp->bg_y, &up->bg_y) || + get_user(kp->bg_u, &up->bg_u) || + get_user(kp->bg_v, &up->bg_v) || + get_user(kp->blend_input_perc_y, &up->blend_input_perc_y) || + get_user(kp->blend_input_perc_u, &up->blend_input_perc_u) || + get_user(kp->blend_input_perc_v, &up->blend_input_perc_v) || + get_user(kp->blend_overlay_perc_y, + &up->blend_overlay_perc_y) || + get_user(kp->blend_overlay_perc_u, + &up->blend_overlay_perc_u) || + get_user(kp->blend_overlay_perc_v, + &up->blend_overlay_perc_v) || + get_user(kp->blend_overlay_perc_u, + &up->blend_overlay_perc_u) || + get_user(kp->overlay_start_x, &up->overlay_start_y)) + return -EFAULT; + + kp->frame = compat_ptr(frame); + return 0; +} + +static int put_atomisp_overlay32(struct atomisp_overlay *kp, + struct atomisp_overlay32 __user *up) +{ + compat_uptr_t frame = (compat_uptr_t)((uintptr_t)kp->frame); + + if (!access_ok(VERIFY_WRITE, up, sizeof(struct atomisp_overlay32)) || + put_user(frame, &up->frame) || + put_user(kp->bg_y, &up->bg_y) || + put_user(kp->bg_u, &up->bg_u) || + put_user(kp->bg_v, &up->bg_v) || + put_user(kp->blend_input_perc_y, &up->blend_input_perc_y) || + put_user(kp->blend_input_perc_u, &up->blend_input_perc_u) || + put_user(kp->blend_input_perc_v, &up->blend_input_perc_v) || + put_user(kp->blend_overlay_perc_y, + &up->blend_overlay_perc_y) || + put_user(kp->blend_overlay_perc_u, + &up->blend_overlay_perc_u) || + put_user(kp->blend_overlay_perc_v, + &up->blend_overlay_perc_v) || + put_user(kp->blend_overlay_perc_u, + &up->blend_overlay_perc_u) || + put_user(kp->overlay_start_x, &up->overlay_start_y)) + return -EFAULT; + + return 0; +} + +static int get_atomisp_calibration_group32( + struct atomisp_calibration_group *kp, + struct atomisp_calibration_group32 __user *up) +{ + compat_uptr_t calb_grp_values; + + if (!access_ok(VERIFY_READ, up, + sizeof(struct atomisp_calibration_group32)) || + get_user(kp->size, &up->size) || + get_user(kp->type, &up->type) || + get_user(calb_grp_values, &up->calb_grp_values)) + return -EFAULT; + + kp->calb_grp_values = compat_ptr(calb_grp_values); + return 0; +} + +static int put_atomisp_calibration_group32( + struct atomisp_calibration_group *kp, + struct atomisp_calibration_group32 __user *up) +{ + compat_uptr_t calb_grp_values = + (compat_uptr_t)((uintptr_t)kp->calb_grp_values); + + if (!access_ok(VERIFY_WRITE, up, + sizeof(struct atomisp_calibration_group32)) || + put_user(kp->size, &up->size) || + put_user(kp->type, &up->type) || + put_user(calb_grp_values, &up->calb_grp_values)) + return -EFAULT; + + return 0; +} + +static int get_atomisp_acc_fw_load32(struct atomisp_acc_fw_load *kp, + struct atomisp_acc_fw_load32 __user *up) +{ + compat_uptr_t data; + + if (!access_ok(VERIFY_READ, up, + sizeof(struct atomisp_acc_fw_load32)) || + get_user(kp->size, &up->size) || + get_user(kp->fw_handle, &up->fw_handle) || + get_user(data, &up->data)) + return -EFAULT; + + kp->data = compat_ptr(data); + return 0; +} + +static int put_atomisp_acc_fw_load32(struct atomisp_acc_fw_load *kp, + struct atomisp_acc_fw_load32 __user *up) +{ + compat_uptr_t data = (compat_uptr_t)((uintptr_t)kp->data); + + if (!access_ok(VERIFY_WRITE, up, + sizeof(struct atomisp_acc_fw_load32)) || + put_user(kp->size, &up->size) || + put_user(kp->fw_handle, &up->fw_handle) || + put_user(data, &up->data)) + return -EFAULT; + + return 0; +} + +static int get_atomisp_acc_fw_arg32(struct atomisp_acc_fw_arg *kp, + struct atomisp_acc_fw_arg32 __user *up) +{ + compat_uptr_t value; + + if (!access_ok(VERIFY_READ, up, sizeof(struct atomisp_acc_fw_arg32)) || + get_user(kp->fw_handle, &up->fw_handle) || + get_user(kp->index, &up->index) || + get_user(value, &up->value) || + get_user(kp->size, &up->size)) + return -EFAULT; + + kp->value = compat_ptr(value); + return 0; +} + +static int put_atomisp_acc_fw_arg32(struct atomisp_acc_fw_arg *kp, + struct atomisp_acc_fw_arg32 __user *up) +{ + compat_uptr_t value = (compat_uptr_t)((uintptr_t)kp->value); + + if (!access_ok(VERIFY_WRITE, up, sizeof(struct atomisp_acc_fw_arg32)) || + put_user(kp->fw_handle, &up->fw_handle) || + put_user(kp->index, &up->index) || + put_user(value, &up->value) || + put_user(kp->size, &up->size)) + return -EFAULT; + + return 0; +} + +static int get_v4l2_private_int_data32(struct v4l2_private_int_data *kp, + struct v4l2_private_int_data32 __user *up) +{ + compat_uptr_t data; + + if (!access_ok(VERIFY_READ, up, + sizeof(struct v4l2_private_int_data32)) || + get_user(kp->size, &up->size) || + get_user(data, &up->data) || + get_user(kp->reserved[0], &up->reserved[0]) || + get_user(kp->reserved[1], &up->reserved[1])) + return -EFAULT; + + kp->data = compat_ptr(data); + return 0; +} + +static int put_v4l2_private_int_data32(struct v4l2_private_int_data *kp, + struct v4l2_private_int_data32 __user *up) +{ + compat_uptr_t data = (compat_uptr_t)((uintptr_t)kp->data); + + if (!access_ok(VERIFY_WRITE, up, + sizeof(struct v4l2_private_int_data32)) || + put_user(kp->size, &up->size) || + put_user(data, &up->data) || + put_user(kp->reserved[0], &up->reserved[0]) || + put_user(kp->reserved[1], &up->reserved[1])) + return -EFAULT; + + return 0; +} + +static int get_atomisp_shading_table32(struct atomisp_shading_table *kp, + struct atomisp_shading_table32 __user *up) +{ + unsigned int n = ATOMISP_NUM_SC_COLORS; + + if (!access_ok(VERIFY_READ, up, + sizeof(struct atomisp_shading_table32)) || + get_user(kp->enable, &up->enable) || + get_user(kp->sensor_width, &up->sensor_width) || + get_user(kp->sensor_height, &up->sensor_height) || + get_user(kp->width, &up->width) || + get_user(kp->height, &up->height) || + get_user(kp->fraction_bits, &up->fraction_bits)) + return -EFAULT; + + while (n-- > 0) { + uintptr_t *data_p = (uintptr_t *)&kp->data[n]; + + if (get_user((*data_p), &up->data[n])) + return -EFAULT; + } + return 0; +} + +static int get_atomisp_acc_map32(struct atomisp_acc_map *kp, + struct atomisp_acc_map32 __user *up) +{ + compat_uptr_t user_ptr; + + if (!access_ok(VERIFY_READ, up, sizeof(struct atomisp_acc_map32)) || + get_user(kp->flags, &up->flags) || + get_user(kp->length, &up->length) || + get_user(user_ptr, &up->user_ptr) || + get_user(kp->css_ptr, &up->css_ptr) || + get_user(kp->reserved[0], &up->reserved[0]) || + get_user(kp->reserved[1], &up->reserved[1]) || + get_user(kp->reserved[2], &up->reserved[2]) || + get_user(kp->reserved[3], &up->reserved[3])) + return -EFAULT; + + kp->user_ptr = compat_ptr(user_ptr); + return 0; +} + +static int put_atomisp_acc_map32(struct atomisp_acc_map *kp, + struct atomisp_acc_map32 __user *up) +{ + compat_uptr_t user_ptr = (compat_uptr_t)((uintptr_t)kp->user_ptr); + + if (!access_ok(VERIFY_WRITE, up, sizeof(struct atomisp_acc_map32)) || + put_user(kp->flags, &up->flags) || + put_user(kp->length, &up->length) || + put_user(user_ptr, &up->user_ptr) || + put_user(kp->css_ptr, &up->css_ptr) || + put_user(kp->reserved[0], &up->reserved[0]) || + put_user(kp->reserved[1], &up->reserved[1]) || + put_user(kp->reserved[2], &up->reserved[2]) || + put_user(kp->reserved[3], &up->reserved[3])) + return -EFAULT; + + return 0; +} + +static int get_atomisp_acc_s_mapped_arg32(struct atomisp_acc_s_mapped_arg *kp, + struct atomisp_acc_s_mapped_arg32 __user *up) +{ + if (!access_ok(VERIFY_READ, up, + sizeof(struct atomisp_acc_s_mapped_arg32)) || + get_user(kp->fw_handle, &up->fw_handle) || + get_user(kp->memory, &up->memory) || + get_user(kp->length, &up->length) || + get_user(kp->css_ptr, &up->css_ptr)) + return -EFAULT; + + return 0; +} + +static int put_atomisp_acc_s_mapped_arg32(struct atomisp_acc_s_mapped_arg *kp, + struct atomisp_acc_s_mapped_arg32 __user *up) +{ + if (!access_ok(VERIFY_WRITE, up, + sizeof(struct atomisp_acc_s_mapped_arg32)) || + put_user(kp->fw_handle, &up->fw_handle) || + put_user(kp->memory, &up->memory) || + put_user(kp->length, &up->length) || + put_user(kp->css_ptr, &up->css_ptr)) + return -EFAULT; + + return 0; +} + +static int get_atomisp_parameters32(struct atomisp_parameters *kp, + struct atomisp_parameters32 __user *up) +{ + int n = offsetof(struct atomisp_parameters32, output_frame) / + sizeof(compat_uptr_t); + unsigned int size, offset = 0; + void __user *user_ptr; +#ifdef ISP2401 + unsigned int stp, mtp, dcp, dscp = 0; + +#endif + if (!access_ok(VERIFY_READ, up, sizeof(struct atomisp_parameters32))) + return -EFAULT; + + while (n >= 0) { + compat_uptr_t *src = (compat_uptr_t *)up + n; + uintptr_t *dst = (uintptr_t *)kp + n; + + if (get_user((*dst), src)) + return -EFAULT; + n--; + } + if (get_user(kp->isp_config_id, &up->isp_config_id) || +#ifndef ISP2401 + get_user(kp->per_frame_setting, &up->per_frame_setting)) +#else + get_user(kp->per_frame_setting, &up->per_frame_setting) || + get_user(stp, &up->shading_table) || + get_user(mtp, &up->morph_table) || + get_user(dcp, &up->dvs2_coefs) || + get_user(dscp, &up->dvs_6axis_config)) +#endif + return -EFAULT; + + { + union { + struct atomisp_shading_table shading_table; + struct atomisp_morph_table morph_table; + struct atomisp_dis_coefficients dvs2_coefs; + struct atomisp_dvs_6axis_config dvs_6axis_config; + } karg; + + size = sizeof(struct atomisp_shading_table) + + sizeof(struct atomisp_morph_table) + + sizeof(struct atomisp_dis_coefficients) + + sizeof(struct atomisp_dvs_6axis_config); + user_ptr = compat_alloc_user_space(size); + + /* handle shading table */ +#ifndef ISP2401 + if (up->shading_table != 0) { +#else + if (stp != 0) { +#endif + if (get_atomisp_shading_table32(&karg.shading_table, + (struct atomisp_shading_table32 __user *) +#ifndef ISP2401 + (uintptr_t)up->shading_table)) +#else + (uintptr_t)stp)) +#endif + return -EFAULT; + + kp->shading_table = user_ptr + offset; + offset = sizeof(struct atomisp_shading_table); + if (!kp->shading_table) + return -EFAULT; + + if (copy_to_user(kp->shading_table, + &karg.shading_table, + sizeof(struct atomisp_shading_table))) + return -EFAULT; + } + + /* handle morph table */ +#ifndef ISP2401 + if (up->morph_table != 0) { +#else + if (mtp != 0) { +#endif + if (get_atomisp_morph_table32(&karg.morph_table, + (struct atomisp_morph_table32 __user *) +#ifndef ISP2401 + (uintptr_t)up->morph_table)) +#else + (uintptr_t)mtp)) +#endif + return -EFAULT; + + kp->morph_table = user_ptr + offset; + offset += sizeof(struct atomisp_morph_table); + if (!kp->morph_table) + return -EFAULT; + + if (copy_to_user(kp->morph_table, &karg.morph_table, + sizeof(struct atomisp_morph_table))) + return -EFAULT; + } + + /* handle dvs2 coefficients */ +#ifndef ISP2401 + if (up->dvs2_coefs != 0) { +#else + if (dcp != 0) { +#endif + if (get_atomisp_dis_coefficients32(&karg.dvs2_coefs, + (struct atomisp_dis_coefficients32 __user *) +#ifndef ISP2401 + (uintptr_t)up->dvs2_coefs)) +#else + (uintptr_t)dcp)) +#endif + return -EFAULT; + + kp->dvs2_coefs = user_ptr + offset; + offset += sizeof(struct atomisp_dis_coefficients); + if (!kp->dvs2_coefs) + return -EFAULT; + + if (copy_to_user(kp->dvs2_coefs, &karg.dvs2_coefs, + sizeof(struct atomisp_dis_coefficients))) + return -EFAULT; + } + /* handle dvs 6axis configuration */ +#ifndef ISP2401 + if (up->dvs_6axis_config != 0) { +#else + if (dscp != 0) { +#endif + if (get_atomisp_dvs_6axis_config32(&karg.dvs_6axis_config, + (struct atomisp_dvs_6axis_config32 __user *) +#ifndef ISP2401 + (uintptr_t)up->dvs_6axis_config)) +#else + (uintptr_t)dscp)) +#endif + return -EFAULT; + + kp->dvs_6axis_config = user_ptr + offset; + offset += sizeof(struct atomisp_dvs_6axis_config); + if (!kp->dvs_6axis_config) + return -EFAULT; + + if (copy_to_user(kp->dvs_6axis_config, &karg.dvs_6axis_config, + sizeof(struct atomisp_dvs_6axis_config))) + return -EFAULT; + } + } + return 0; +} + +static int get_atomisp_acc_fw_load_to_pipe32( + struct atomisp_acc_fw_load_to_pipe *kp, + struct atomisp_acc_fw_load_to_pipe32 __user *up) +{ + compat_uptr_t data; + if (!access_ok(VERIFY_READ, up, + sizeof(struct atomisp_acc_fw_load_to_pipe32)) || + get_user(kp->flags, &up->flags) || + get_user(kp->fw_handle, &up->fw_handle) || + get_user(kp->size, &up->size) || + get_user(kp->type, &up->type) || + get_user(kp->reserved[0], &up->reserved[0]) || + get_user(kp->reserved[1], &up->reserved[1]) || + get_user(kp->reserved[2], &up->reserved[2]) || + get_user(data, &up->data)) + return -EFAULT; + + kp->data = compat_ptr(data); + return 0; +} + +static int put_atomisp_acc_fw_load_to_pipe32( + struct atomisp_acc_fw_load_to_pipe *kp, + struct atomisp_acc_fw_load_to_pipe32 __user *up) +{ + compat_uptr_t data = (compat_uptr_t)((uintptr_t)kp->data); + if (!access_ok(VERIFY_WRITE, up, + sizeof(struct atomisp_acc_fw_load_to_pipe32)) || + put_user(kp->flags, &up->flags) || + put_user(kp->fw_handle, &up->fw_handle) || + put_user(kp->size, &up->size) || + put_user(kp->type, &up->type) || + put_user(kp->reserved[0], &up->reserved[0]) || + put_user(kp->reserved[1], &up->reserved[1]) || + put_user(kp->reserved[2], &up->reserved[2]) || + put_user(data, &up->data)) + return -EFAULT; + + return 0; +} + +static int get_atomisp_sensor_ae_bracketing_lut( + struct atomisp_sensor_ae_bracketing_lut *kp, + struct atomisp_sensor_ae_bracketing_lut32 __user *up) +{ + compat_uptr_t lut; + if (!access_ok(VERIFY_READ, up, + sizeof(struct atomisp_sensor_ae_bracketing_lut32)) || + get_user(kp->lut_size, &up->lut_size) || + get_user(lut, &up->lut)) + return -EFAULT; + + kp->lut = compat_ptr(lut); + return 0; +} + +static long native_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + long ret = -ENOIOCTLCMD; + + if (file->f_op->unlocked_ioctl) + ret = file->f_op->unlocked_ioctl(file, cmd, arg); + + return ret; +} + +long atomisp_do_compat_ioctl(struct file *file, + unsigned int cmd, unsigned long arg) +{ + union { + struct atomisp_histogram his; + struct atomisp_dis_statistics dis_s; + struct atomisp_dis_coefficients dis_c; + struct atomisp_dvs_6axis_config dvs_c; + struct atomisp_3a_statistics s3a_s; + struct atomisp_morph_table mor_t; + struct v4l2_framebuffer v4l2_buf; + struct atomisp_overlay overlay; + struct atomisp_calibration_group cal_grp; + struct atomisp_acc_fw_load acc_fw_load; + struct atomisp_acc_fw_arg acc_fw_arg; + struct v4l2_private_int_data v4l2_pri_data; + struct atomisp_shading_table shd_tbl; + struct atomisp_acc_map acc_map; + struct atomisp_acc_s_mapped_arg acc_map_arg; + struct atomisp_parameters param; + struct atomisp_acc_fw_load_to_pipe acc_fw_to_pipe; + struct atomisp_metadata md; + struct atomisp_metadata_with_type md_with_type; + struct atomisp_sensor_ae_bracketing_lut lut; + } karg; + mm_segment_t old_fs; + void __user *up = compat_ptr(arg); + long err = -ENOIOCTLCMD; + + /* First, convert the command. */ + switch (cmd) { + case ATOMISP_IOC_G_HISTOGRAM32: + cmd = ATOMISP_IOC_G_HISTOGRAM; + break; + case ATOMISP_IOC_S_HISTOGRAM32: + cmd = ATOMISP_IOC_S_HISTOGRAM; + break; + case ATOMISP_IOC_G_DIS_STAT32: + cmd = ATOMISP_IOC_G_DIS_STAT; + break; + case ATOMISP_IOC_S_DIS_COEFS32: + cmd = ATOMISP_IOC_S_DIS_COEFS; + break; + case ATOMISP_IOC_S_DIS_VECTOR32: + cmd = ATOMISP_IOC_S_DIS_VECTOR; + break; + case ATOMISP_IOC_G_3A_STAT32: + cmd = ATOMISP_IOC_G_3A_STAT; + break; + case ATOMISP_IOC_G_ISP_GDC_TAB32: + cmd = ATOMISP_IOC_G_ISP_GDC_TAB; + break; + case ATOMISP_IOC_S_ISP_GDC_TAB32: + cmd = ATOMISP_IOC_S_ISP_GDC_TAB; + break; + case ATOMISP_IOC_S_ISP_FPN_TABLE32: + cmd = ATOMISP_IOC_S_ISP_FPN_TABLE; + break; + case ATOMISP_IOC_G_ISP_OVERLAY32: + cmd = ATOMISP_IOC_G_ISP_OVERLAY; + break; + case ATOMISP_IOC_S_ISP_OVERLAY32: + cmd = ATOMISP_IOC_S_ISP_OVERLAY; + break; + case ATOMISP_IOC_G_SENSOR_CALIBRATION_GROUP32: + cmd = ATOMISP_IOC_G_SENSOR_CALIBRATION_GROUP; + break; + case ATOMISP_IOC_ACC_LOAD32: + cmd = ATOMISP_IOC_ACC_LOAD; + break; + case ATOMISP_IOC_ACC_S_ARG32: + cmd = ATOMISP_IOC_ACC_S_ARG; + break; + case ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA32: + cmd = ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA; + break; + case ATOMISP_IOC_S_ISP_SHD_TAB32: + cmd = ATOMISP_IOC_S_ISP_SHD_TAB; + break; + case ATOMISP_IOC_ACC_DESTAB32: + cmd = ATOMISP_IOC_ACC_DESTAB; + break; + case ATOMISP_IOC_G_MOTOR_PRIV_INT_DATA32: + cmd = ATOMISP_IOC_G_MOTOR_PRIV_INT_DATA; + break; + case ATOMISP_IOC_ACC_MAP32: + cmd = ATOMISP_IOC_ACC_MAP; + break; + case ATOMISP_IOC_ACC_UNMAP32: + cmd = ATOMISP_IOC_ACC_UNMAP; + break; + case ATOMISP_IOC_ACC_S_MAPPED_ARG32: + cmd = ATOMISP_IOC_ACC_S_MAPPED_ARG; + break; + case ATOMISP_IOC_S_PARAMETERS32: + cmd = ATOMISP_IOC_S_PARAMETERS; + break; + case ATOMISP_IOC_ACC_LOAD_TO_PIPE32: + cmd = ATOMISP_IOC_ACC_LOAD_TO_PIPE; + break; + case ATOMISP_IOC_G_METADATA32: + cmd = ATOMISP_IOC_G_METADATA; + break; + case ATOMISP_IOC_G_METADATA_BY_TYPE32: + cmd = ATOMISP_IOC_G_METADATA_BY_TYPE; + break; + case ATOMISP_IOC_S_SENSOR_AE_BRACKETING_LUT32: + cmd = ATOMISP_IOC_S_SENSOR_AE_BRACKETING_LUT; + break; + } + + switch (cmd) { + case ATOMISP_IOC_G_HISTOGRAM: + case ATOMISP_IOC_S_HISTOGRAM: + err = get_atomisp_histogram32(&karg.his, up); + break; + case ATOMISP_IOC_G_DIS_STAT: + err = get_atomisp_dis_statistics32(&karg.dis_s, up); + break; + case ATOMISP_IOC_S_DIS_COEFS: + err = get_atomisp_dis_coefficients32(&karg.dis_c, up); + break; + case ATOMISP_IOC_S_DIS_VECTOR: + err = get_atomisp_dvs_6axis_config32(&karg.dvs_c, up); + break; + case ATOMISP_IOC_G_3A_STAT: + err = get_atomisp_3a_statistics32(&karg.s3a_s, up); + break; + case ATOMISP_IOC_G_ISP_GDC_TAB: + case ATOMISP_IOC_S_ISP_GDC_TAB: + err = get_atomisp_morph_table32(&karg.mor_t, up); + break; + case ATOMISP_IOC_S_ISP_FPN_TABLE: + err = get_v4l2_framebuffer32(&karg.v4l2_buf, up); + break; + case ATOMISP_IOC_G_ISP_OVERLAY: + case ATOMISP_IOC_S_ISP_OVERLAY: + err = get_atomisp_overlay32(&karg.overlay, up); + break; + case ATOMISP_IOC_G_SENSOR_CALIBRATION_GROUP: + err = get_atomisp_calibration_group32(&karg.cal_grp, up); + break; + case ATOMISP_IOC_ACC_LOAD: + err = get_atomisp_acc_fw_load32(&karg.acc_fw_load, up); + break; + case ATOMISP_IOC_ACC_S_ARG: + case ATOMISP_IOC_ACC_DESTAB: + err = get_atomisp_acc_fw_arg32(&karg.acc_fw_arg, up); + break; + case ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA: + case ATOMISP_IOC_G_MOTOR_PRIV_INT_DATA: + err = get_v4l2_private_int_data32(&karg.v4l2_pri_data, up); + break; + case ATOMISP_IOC_S_ISP_SHD_TAB: + err = get_atomisp_shading_table32(&karg.shd_tbl, up); + break; + case ATOMISP_IOC_ACC_MAP: + case ATOMISP_IOC_ACC_UNMAP: + err = get_atomisp_acc_map32(&karg.acc_map, up); + break; + case ATOMISP_IOC_ACC_S_MAPPED_ARG: + err = get_atomisp_acc_s_mapped_arg32(&karg.acc_map_arg, up); + break; + case ATOMISP_IOC_S_PARAMETERS: + err = get_atomisp_parameters32(&karg.param, up); + break; + case ATOMISP_IOC_ACC_LOAD_TO_PIPE: + err = get_atomisp_acc_fw_load_to_pipe32(&karg.acc_fw_to_pipe, + up); + break; + case ATOMISP_IOC_G_METADATA: + err = get_atomisp_metadata_stat32(&karg.md, up); + break; + case ATOMISP_IOC_G_METADATA_BY_TYPE: + err = get_atomisp_metadata_by_type_stat32(&karg.md_with_type, + up); + break; + case ATOMISP_IOC_S_SENSOR_AE_BRACKETING_LUT: + err = get_atomisp_sensor_ae_bracketing_lut(&karg.lut, up); + break; + } + if (err) + return err; + + old_fs = get_fs(); + set_fs(KERNEL_DS); + err = native_ioctl(file, cmd, (unsigned long)&karg); + set_fs(old_fs); + if (err) + return err; + + switch (cmd) { + case ATOMISP_IOC_G_HISTOGRAM: + err = put_atomisp_histogram32(&karg.his, up); + break; + case ATOMISP_IOC_G_DIS_STAT: + err = put_atomisp_dis_statistics32(&karg.dis_s, up); + break; + case ATOMISP_IOC_G_3A_STAT: + err = put_atomisp_3a_statistics32(&karg.s3a_s, up); + break; + case ATOMISP_IOC_G_ISP_GDC_TAB: + err = put_atomisp_morph_table32(&karg.mor_t, up); + break; + case ATOMISP_IOC_G_ISP_OVERLAY: + err = put_atomisp_overlay32(&karg.overlay, up); + break; + case ATOMISP_IOC_G_SENSOR_CALIBRATION_GROUP: + err = put_atomisp_calibration_group32(&karg.cal_grp, up); + break; + case ATOMISP_IOC_ACC_LOAD: + err = put_atomisp_acc_fw_load32(&karg.acc_fw_load, up); + break; + case ATOMISP_IOC_ACC_S_ARG: + case ATOMISP_IOC_ACC_DESTAB: + err = put_atomisp_acc_fw_arg32(&karg.acc_fw_arg, up); + break; + case ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA: + case ATOMISP_IOC_G_MOTOR_PRIV_INT_DATA: + err = put_v4l2_private_int_data32(&karg.v4l2_pri_data, up); + break; + case ATOMISP_IOC_ACC_MAP: + case ATOMISP_IOC_ACC_UNMAP: + err = put_atomisp_acc_map32(&karg.acc_map, up); + break; + case ATOMISP_IOC_ACC_S_MAPPED_ARG: + err = put_atomisp_acc_s_mapped_arg32(&karg.acc_map_arg, up); + break; + case ATOMISP_IOC_ACC_LOAD_TO_PIPE: + err = put_atomisp_acc_fw_load_to_pipe32(&karg.acc_fw_to_pipe, + up); + break; + case ATOMISP_IOC_G_METADATA: + err = put_atomisp_metadata_stat32(&karg.md, up); + break; + case ATOMISP_IOC_G_METADATA_BY_TYPE: + err = put_atomisp_metadata_by_type_stat32(&karg.md_with_type, + up); + break; + } + + return err; +} + +long atomisp_compat_ioctl32(struct file *file, + unsigned int cmd, unsigned long arg) +{ + + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + long ret = -ENOIOCTLCMD; + + if (!file->f_op->unlocked_ioctl) + return ret; + + switch (cmd) { + case ATOMISP_IOC_G_XNR: + case ATOMISP_IOC_S_XNR: + case ATOMISP_IOC_G_NR: + case ATOMISP_IOC_S_NR: + case ATOMISP_IOC_G_TNR: + case ATOMISP_IOC_S_TNR: + case ATOMISP_IOC_G_BLACK_LEVEL_COMP: + case ATOMISP_IOC_S_BLACK_LEVEL_COMP: + case ATOMISP_IOC_G_EE: + case ATOMISP_IOC_S_EE: + case ATOMISP_IOC_S_DIS_VECTOR: + case ATOMISP_IOC_G_ISP_PARM: + case ATOMISP_IOC_S_ISP_PARM: + case ATOMISP_IOC_G_ISP_GAMMA: + case ATOMISP_IOC_S_ISP_GAMMA: + case ATOMISP_IOC_ISP_MAKERNOTE: + case ATOMISP_IOC_G_ISP_MACC: + case ATOMISP_IOC_S_ISP_MACC: + case ATOMISP_IOC_G_ISP_BAD_PIXEL_DETECTION: + case ATOMISP_IOC_S_ISP_BAD_PIXEL_DETECTION: + case ATOMISP_IOC_G_ISP_FALSE_COLOR_CORRECTION: + case ATOMISP_IOC_S_ISP_FALSE_COLOR_CORRECTION: + case ATOMISP_IOC_G_ISP_CTC: + case ATOMISP_IOC_S_ISP_CTC: + case ATOMISP_IOC_G_ISP_WHITE_BALANCE: + case ATOMISP_IOC_S_ISP_WHITE_BALANCE: + case ATOMISP_IOC_CAMERA_BRIDGE: + case ATOMISP_IOC_G_SENSOR_MODE_DATA: + case ATOMISP_IOC_S_EXPOSURE: + case ATOMISP_IOC_G_3A_CONFIG: + case ATOMISP_IOC_S_3A_CONFIG: + case ATOMISP_IOC_ACC_UNLOAD: + case ATOMISP_IOC_ACC_START: + case ATOMISP_IOC_ACC_WAIT: + case ATOMISP_IOC_ACC_ABORT: + case ATOMISP_IOC_G_ISP_GAMMA_CORRECTION: + case ATOMISP_IOC_S_ISP_GAMMA_CORRECTION: + case ATOMISP_IOC_S_CONT_CAPTURE_CONFIG: + case ATOMISP_IOC_G_DVS2_BQ_RESOLUTIONS: + case ATOMISP_IOC_EXT_ISP_CTRL: + case ATOMISP_IOC_EXP_ID_UNLOCK: + case ATOMISP_IOC_EXP_ID_CAPTURE: + case ATOMISP_IOC_S_ENABLE_DZ_CAPT_PIPE: + case ATOMISP_IOC_G_FORMATS_CONFIG: + case ATOMISP_IOC_S_FORMATS_CONFIG: + case ATOMISP_IOC_S_EXPOSURE_WINDOW: + case ATOMISP_IOC_S_ACC_STATE: + case ATOMISP_IOC_G_ACC_STATE: + case ATOMISP_IOC_INJECT_A_FAKE_EVENT: + case ATOMISP_IOC_G_SENSOR_AE_BRACKETING_INFO: + case ATOMISP_IOC_S_SENSOR_AE_BRACKETING_MODE: + case ATOMISP_IOC_G_SENSOR_AE_BRACKETING_MODE: + case ATOMISP_IOC_G_INVALID_FRAME_NUM: + case ATOMISP_IOC_S_ARRAY_RESOLUTION: +#ifdef ISP2401 + case ATOMISP_IOC_S_SENSOR_RUNMODE: + case ATOMISP_IOC_G_UPDATE_EXPOSURE: +#endif + ret = native_ioctl(file, cmd, arg); + break; + + case ATOMISP_IOC_G_HISTOGRAM32: + case ATOMISP_IOC_S_HISTOGRAM32: + case ATOMISP_IOC_G_DIS_STAT32: + case ATOMISP_IOC_S_DIS_COEFS32: + case ATOMISP_IOC_S_DIS_VECTOR32: + case ATOMISP_IOC_G_3A_STAT32: + case ATOMISP_IOC_G_ISP_GDC_TAB32: + case ATOMISP_IOC_S_ISP_GDC_TAB32: + case ATOMISP_IOC_S_ISP_FPN_TABLE32: + case ATOMISP_IOC_G_ISP_OVERLAY32: + case ATOMISP_IOC_S_ISP_OVERLAY32: + case ATOMISP_IOC_G_SENSOR_CALIBRATION_GROUP32: + case ATOMISP_IOC_ACC_LOAD32: + case ATOMISP_IOC_ACC_S_ARG32: + case ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA32: + case ATOMISP_IOC_S_ISP_SHD_TAB32: + case ATOMISP_IOC_ACC_DESTAB32: + case ATOMISP_IOC_G_MOTOR_PRIV_INT_DATA32: + case ATOMISP_IOC_ACC_MAP32: + case ATOMISP_IOC_ACC_UNMAP32: + case ATOMISP_IOC_ACC_S_MAPPED_ARG32: + case ATOMISP_IOC_S_PARAMETERS32: + case ATOMISP_IOC_ACC_LOAD_TO_PIPE32: + case ATOMISP_IOC_G_METADATA32: + case ATOMISP_IOC_G_METADATA_BY_TYPE32: + case ATOMISP_IOC_S_SENSOR_AE_BRACKETING_LUT32: + ret = atomisp_do_compat_ioctl(file, cmd, arg); + break; + + default: + dev_warn(isp->dev, + "%s: unknown ioctl '%c', dir=%d, #%d (0x%08x)\n", + __func__, _IOC_TYPE(cmd), _IOC_DIR(cmd), _IOC_NR(cmd), + cmd); + break; + } + return ret; +} +#endif /* CONFIG_COMPAT */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_ioctl32.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_ioctl32.h new file mode 100644 index 0000000000000000000000000000000000000000..750478f614d6a9c940f2c2ba13312abffd868aae --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_compat_ioctl32.h @@ -0,0 +1,369 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#ifndef __ATOMISP_COMPAT_IOCTL32_H__ +#define __ATOMISP_COMPAT_IOCTL32_H__ + +#include +#include + +#include "atomisp_compat.h" + +struct atomisp_histogram32 { + unsigned int num_elements; + compat_uptr_t data; +}; + +struct atomisp_dvs2_stat_types32 { + compat_uptr_t odd_real; /**< real part of the odd statistics*/ + compat_uptr_t odd_imag; /**< imaginary part of the odd statistics*/ + compat_uptr_t even_real;/**< real part of the even statistics*/ + compat_uptr_t even_imag;/**< imaginary part of the even statistics*/ +}; + +struct atomisp_dvs2_coef_types32 { + compat_uptr_t odd_real; /**< real part of the odd coefficients*/ + compat_uptr_t odd_imag; /**< imaginary part of the odd coefficients*/ + compat_uptr_t even_real;/**< real part of the even coefficients*/ + compat_uptr_t even_imag;/**< imaginary part of the even coefficients*/ +}; + +struct atomisp_dvs2_statistics32 { + struct atomisp_dvs_grid_info grid_info; + struct atomisp_dvs2_stat_types32 hor_prod; + struct atomisp_dvs2_stat_types32 ver_prod; +}; + +struct atomisp_dis_statistics32 { + struct atomisp_dvs2_statistics32 dvs2_stat; + uint32_t exp_id; +}; + +struct atomisp_dis_coefficients32 { + struct atomisp_dvs_grid_info grid_info; + struct atomisp_dvs2_coef_types32 hor_coefs; + struct atomisp_dvs2_coef_types32 ver_coefs; +}; + +struct atomisp_3a_statistics32 { + struct atomisp_grid_info grid_info; + compat_uptr_t data; + compat_uptr_t rgby_data; + uint32_t exp_id; + uint32_t isp_config_id; +}; + +struct atomisp_metadata_with_type32 { + /* to specify which type of metadata to get */ + enum atomisp_metadata_type type; + compat_uptr_t data; + uint32_t width; + uint32_t height; + uint32_t stride; /* in bytes */ + uint32_t exp_id; /* exposure ID */ + compat_uptr_t effective_width; +}; + +struct atomisp_metadata32 { + compat_uptr_t data; + uint32_t width; + uint32_t height; + uint32_t stride; + uint32_t exp_id; + compat_uptr_t effective_width; +}; + +struct atomisp_morph_table32 { + unsigned int enabled; + unsigned int height; + unsigned int width; /* number of valid elements per line */ + compat_uptr_t coordinates_x[ATOMISP_MORPH_TABLE_NUM_PLANES]; + compat_uptr_t coordinates_y[ATOMISP_MORPH_TABLE_NUM_PLANES]; +}; + +struct v4l2_framebuffer32 { + __u32 capability; + __u32 flags; + compat_uptr_t base; + struct v4l2_pix_format fmt; +}; + +struct atomisp_overlay32 { + /* the frame containing the overlay data The overlay frame width should + * be the multiples of 2*ISP_VEC_NELEMS. The overlay frame height + * should be the multiples of 2. + */ + compat_uptr_t frame; + /* Y value of overlay background */ + unsigned char bg_y; + /* U value of overlay background */ + char bg_u; + /* V value of overlay background */ + char bg_v; + /* the blending percent of input data for Y subpixels */ + unsigned char blend_input_perc_y; + /* the blending percent of input data for U subpixels */ + unsigned char blend_input_perc_u; + /* the blending percent of input data for V subpixels */ + unsigned char blend_input_perc_v; + /* the blending percent of overlay data for Y subpixels */ + unsigned char blend_overlay_perc_y; + /* the blending percent of overlay data for U subpixels */ + unsigned char blend_overlay_perc_u; + /* the blending percent of overlay data for V subpixels */ + unsigned char blend_overlay_perc_v; + /* the overlay start x pixel position on output frame It should be the + multiples of 2*ISP_VEC_NELEMS. */ + unsigned int overlay_start_x; + /* the overlay start y pixel position on output frame It should be the + multiples of 2. */ + unsigned int overlay_start_y; +}; + +struct atomisp_calibration_group32 { + unsigned int size; + unsigned int type; + compat_uptr_t calb_grp_values; +}; + +struct atomisp_acc_fw_load32 { + unsigned int size; + unsigned int fw_handle; + compat_uptr_t data; +}; + +struct atomisp_acc_fw_arg32 { + unsigned int fw_handle; + unsigned int index; + compat_uptr_t value; + compat_size_t size; +}; + +struct v4l2_private_int_data32 { + __u32 size; + compat_uptr_t data; + __u32 reserved[2]; +}; + +struct atomisp_shading_table32 { + __u32 enable; + __u32 sensor_width; + __u32 sensor_height; + __u32 width; + __u32 height; + __u32 fraction_bits; + + compat_uptr_t data[ATOMISP_NUM_SC_COLORS]; +}; + +struct atomisp_acc_map32 { + __u32 flags; /* Flags, see list below */ + __u32 length; /* Length of data in bytes */ + compat_uptr_t user_ptr; /* Pointer into user space */ + compat_ulong_t css_ptr; /* Pointer into CSS address space */ + __u32 reserved[4]; /* Set to zero */ +}; + +struct atomisp_acc_s_mapped_arg32 { + unsigned int fw_handle; + __u32 memory; /* one of enum atomisp_acc_memory */ + compat_size_t length; + compat_ulong_t css_ptr; +}; + +struct atomisp_parameters32 { + compat_uptr_t wb_config; /* White Balance config */ + compat_uptr_t cc_config; /* Color Correction config */ + compat_uptr_t tnr_config; /* Temporal Noise Reduction */ + compat_uptr_t ecd_config; /* Eigen Color Demosaicing */ + compat_uptr_t ynr_config; /* Y(Luma) Noise Reduction */ + compat_uptr_t fc_config; /* Fringe Control */ + compat_uptr_t formats_config; /* Formats Control */ + compat_uptr_t cnr_config; /* Chroma Noise Reduction */ + compat_uptr_t macc_config; /* MACC */ + compat_uptr_t ctc_config; /* Chroma Tone Control */ + compat_uptr_t aa_config; /* Anti-Aliasing */ + compat_uptr_t baa_config; /* Anti-Aliasing */ + compat_uptr_t ce_config; + compat_uptr_t dvs_6axis_config; + compat_uptr_t ob_config; /* Objective Black config */ + compat_uptr_t dp_config; /* Dead Pixel config */ + compat_uptr_t nr_config; /* Noise Reduction config */ + compat_uptr_t ee_config; /* Edge Enhancement config */ + compat_uptr_t de_config; /* Demosaic config */ + compat_uptr_t gc_config; /* Gamma Correction config */ + compat_uptr_t anr_config; /* Advanced Noise Reduction */ + compat_uptr_t a3a_config; /* 3A Statistics config */ + compat_uptr_t xnr_config; /* eXtra Noise Reduction */ + compat_uptr_t dz_config; /* Digital Zoom */ + compat_uptr_t yuv2rgb_cc_config; /* Color + Correction config */ + compat_uptr_t rgb2yuv_cc_config; /* Color + Correction config */ + compat_uptr_t macc_table; + compat_uptr_t gamma_table; + compat_uptr_t ctc_table; + compat_uptr_t xnr_table; + compat_uptr_t r_gamma_table; + compat_uptr_t g_gamma_table; + compat_uptr_t b_gamma_table; + compat_uptr_t motion_vector; /* For 2-axis DVS */ + compat_uptr_t shading_table; + compat_uptr_t morph_table; + compat_uptr_t dvs_coefs; /* DVS 1.0 coefficients */ + compat_uptr_t dvs2_coefs; /* DVS 2.0 coefficients */ + compat_uptr_t capture_config; + compat_uptr_t anr_thres; + + compat_uptr_t lin_2500_config; /* Skylake: Linearization config */ + compat_uptr_t obgrid_2500_config; /* Skylake: OBGRID config */ + compat_uptr_t bnr_2500_config; /* Skylake: bayer denoise config */ + compat_uptr_t shd_2500_config; /* Skylake: shading config */ + compat_uptr_t dm_2500_config; /* Skylake: demosaic config */ + compat_uptr_t rgbpp_2500_config; /* Skylake: RGBPP config */ + compat_uptr_t dvs_stat_2500_config; /* Skylake: DVS STAT config */ + compat_uptr_t lace_stat_2500_config; /* Skylake: LACE STAT config */ + compat_uptr_t yuvp1_2500_config; /* Skylake: yuvp1 config */ + compat_uptr_t yuvp2_2500_config; /* Skylake: yuvp2 config */ + compat_uptr_t tnr_2500_config; /* Skylake: TNR config */ + compat_uptr_t dpc_2500_config; /* Skylake: DPC config */ + compat_uptr_t awb_2500_config; /* Skylake: auto white balance config */ + compat_uptr_t awb_fr_2500_config; /* Skylake: auto white balance filter response config */ + compat_uptr_t anr_2500_config; /* Skylake: ANR config */ + compat_uptr_t af_2500_config; /* Skylake: auto focus config */ + compat_uptr_t ae_2500_config; /* Skylake: auto exposure config */ + compat_uptr_t bds_2500_config; /* Skylake: bayer downscaler config */ + compat_uptr_t dvs_2500_config; /* Skylake: digital video stabilization config */ + compat_uptr_t res_mgr_2500_config; + + /* + * Output frame pointer the config is to be applied to (optional), + * set to NULL to make this config is applied as global. + */ + compat_uptr_t output_frame; + /* + * Unique ID to track which config was actually applied to a particular + * frame, driver will send this id back with output frame together. + */ + uint32_t isp_config_id; + uint32_t per_frame_setting; +}; + +struct atomisp_acc_fw_load_to_pipe32 { + __u32 flags; /* Flags, see below for valid values */ + unsigned int fw_handle; /* Handle, filled by kernel. */ + __u32 size; /* Firmware binary size */ + compat_uptr_t data; /* Pointer to firmware */ + __u32 type; /* Binary type */ + __u32 reserved[3]; /* Set to zero */ +}; + +struct atomisp_dvs_6axis_config32 { + uint32_t exp_id; + uint32_t width_y; + uint32_t height_y; + uint32_t width_uv; + uint32_t height_uv; + compat_uptr_t xcoords_y; + compat_uptr_t ycoords_y; + compat_uptr_t xcoords_uv; + compat_uptr_t ycoords_uv; +}; + +struct atomisp_sensor_ae_bracketing_lut32 { + compat_uptr_t lut; + unsigned int lut_size; +}; + +#define ATOMISP_IOC_G_HISTOGRAM32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 3, struct atomisp_histogram32) +#define ATOMISP_IOC_S_HISTOGRAM32 \ + _IOW('v', BASE_VIDIOC_PRIVATE + 3, struct atomisp_histogram32) + +#define ATOMISP_IOC_G_DIS_STAT32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 6, struct atomisp_dis_statistics32) +#define ATOMISP_IOC_S_DIS_COEFS32 \ + _IOW('v', BASE_VIDIOC_PRIVATE + 6, struct atomisp_dis_coefficients32) + +#define ATOMISP_IOC_S_DIS_VECTOR32 \ + _IOW('v', BASE_VIDIOC_PRIVATE + 6, struct atomisp_dvs_6axis_config32) + +#define ATOMISP_IOC_G_3A_STAT32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 7, struct atomisp_3a_statistics32) + +#define ATOMISP_IOC_G_ISP_GDC_TAB32 \ + _IOR('v', BASE_VIDIOC_PRIVATE + 10, struct atomisp_morph_table32) +#define ATOMISP_IOC_S_ISP_GDC_TAB32 \ + _IOW('v', BASE_VIDIOC_PRIVATE + 10, struct atomisp_morph_table32) + +#define ATOMISP_IOC_S_ISP_FPN_TABLE32 \ + _IOW('v', BASE_VIDIOC_PRIVATE + 17, struct v4l2_framebuffer32) + +#define ATOMISP_IOC_G_ISP_OVERLAY32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 18, struct atomisp_overlay32) +#define ATOMISP_IOC_S_ISP_OVERLAY32 \ + _IOW('v', BASE_VIDIOC_PRIVATE + 18, struct atomisp_overlay32) + +#define ATOMISP_IOC_G_SENSOR_CALIBRATION_GROUP32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 22, struct atomisp_calibration_group32) + +#define ATOMISP_IOC_ACC_LOAD32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 24, struct atomisp_acc_fw_load32) + +#define ATOMISP_IOC_ACC_S_ARG32 \ + _IOW('v', BASE_VIDIOC_PRIVATE + 24, struct atomisp_acc_fw_arg32) + +#define ATOMISP_IOC_ACC_DESTAB32 \ + _IOW('v', BASE_VIDIOC_PRIVATE + 25, struct atomisp_acc_fw_arg32) + +#define ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 26, struct v4l2_private_int_data32) + +#define ATOMISP_IOC_S_ISP_SHD_TAB32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 27, struct atomisp_shading_table32) + +#define ATOMISP_IOC_G_MOTOR_PRIV_INT_DATA32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 29, struct v4l2_private_int_data32) + +#define ATOMISP_IOC_ACC_MAP32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 30, struct atomisp_acc_map32) + +#define ATOMISP_IOC_ACC_UNMAP32 \ + _IOW('v', BASE_VIDIOC_PRIVATE + 30, struct atomisp_acc_map32) + +#define ATOMISP_IOC_ACC_S_MAPPED_ARG32 \ + _IOW('v', BASE_VIDIOC_PRIVATE + 30, struct atomisp_acc_s_mapped_arg32) + +#define ATOMISP_IOC_ACC_LOAD_TO_PIPE32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 31, struct atomisp_acc_fw_load_to_pipe32) + +#define ATOMISP_IOC_S_PARAMETERS32 \ + _IOW('v', BASE_VIDIOC_PRIVATE + 32, struct atomisp_parameters32) + +#define ATOMISP_IOC_G_METADATA32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 34, struct atomisp_metadata32) + +#define ATOMISP_IOC_G_METADATA_BY_TYPE32 \ + _IOWR('v', BASE_VIDIOC_PRIVATE + 34, struct atomisp_metadata_with_type32) + +#define ATOMISP_IOC_S_SENSOR_AE_BRACKETING_LUT32 \ + _IOW('v', BASE_VIDIOC_PRIVATE + 43, struct atomisp_sensor_ae_bracketing_lut32) + +#endif /* __ATOMISP_COMPAT_IOCTL32_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_csi2.c b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_csi2.c new file mode 100644 index 0000000000000000000000000000000000000000..2c50366854475a3746fb1d4da6261f3e9a30b90e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_csi2.c @@ -0,0 +1,446 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include +#include "atomisp_cmd.h" +#include "atomisp_internal.h" +#include "atomisp-regs.h" + +static struct v4l2_mbus_framefmt *__csi2_get_format(struct + atomisp_mipi_csi2_device + *csi2, + struct + v4l2_subdev_pad_config *cfg, + enum + v4l2_subdev_format_whence + which, unsigned int pad) +{ + if (which == V4L2_SUBDEV_FORMAT_TRY) + return v4l2_subdev_get_try_format(&csi2->subdev, cfg, pad); + else + return &csi2->formats[pad]; +} + +/* + * csi2_enum_mbus_code - Handle pixel format enumeration + * @sd : pointer to v4l2 subdev structure + * @fh : V4L2 subdev file handle + * @code : pointer to v4l2_subdev_pad_mbus_code_enum structure + * return -EINVAL or zero on success +*/ +static int csi2_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + const struct atomisp_in_fmt_conv *ic = atomisp_in_fmt_conv; + unsigned int i = 0; + + while (ic->code) { + if (i == code->index) { + code->code = ic->code; + return 0; + } + i++, ic++; + } + + return -EINVAL; +} + +/* + * csi2_get_format - Handle get format by pads subdev method + * @sd : pointer to v4l2 subdev structure + * @fh : V4L2 subdev file handle + * @pad: pad num + * @fmt: pointer to v4l2 format structure + * return -EINVAL or zero on sucess +*/ +static int csi2_get_format(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + struct atomisp_mipi_csi2_device *csi2 = v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt *format; + + format = __csi2_get_format(csi2, cfg, fmt->which, fmt->pad); + + fmt->format = *format; + + return 0; +} + +int atomisp_csi2_set_ffmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + unsigned int which, uint16_t pad, + struct v4l2_mbus_framefmt *ffmt) +{ + struct atomisp_mipi_csi2_device *csi2 = v4l2_get_subdevdata(sd); + struct v4l2_mbus_framefmt *actual_ffmt = +#ifndef ISP2401 + __csi2_get_format(csi2, cfg, which, pad); +#else + __csi2_get_format(csi2, cfg, which, pad); +#endif + + if (pad == CSI2_PAD_SINK) { + const struct atomisp_in_fmt_conv *ic; + struct v4l2_mbus_framefmt tmp_ffmt; + + ic = atomisp_find_in_fmt_conv(ffmt->code); + if (ic) + actual_ffmt->code = ic->code; + else + actual_ffmt->code = atomisp_in_fmt_conv[0].code; + + actual_ffmt->width = clamp_t( + u32, ffmt->width, ATOM_ISP_MIN_WIDTH, + ATOM_ISP_MAX_WIDTH); + actual_ffmt->height = clamp_t( + u32, ffmt->height, ATOM_ISP_MIN_HEIGHT, + ATOM_ISP_MAX_HEIGHT); + + tmp_ffmt = *ffmt = *actual_ffmt; + + return atomisp_csi2_set_ffmt(sd, cfg, which, CSI2_PAD_SOURCE, + &tmp_ffmt); + } + + /* FIXME: DPCM decompression */ + *actual_ffmt = *ffmt = +#ifndef ISP2401 + *__csi2_get_format(csi2, cfg, which, CSI2_PAD_SINK); +#else + *__csi2_get_format(csi2, cfg, which, CSI2_PAD_SINK); +#endif + + return 0; +} + +/* + * csi2_set_format - Handle set format by pads subdev method + * @sd : pointer to v4l2 subdev structure + * @fh : V4L2 subdev file handle + * @pad: pad num + * @fmt: pointer to v4l2 format structure + * return -EINVAL or zero on success +*/ +static int csi2_set_format(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +{ + return atomisp_csi2_set_ffmt(sd, cfg, fmt->which, fmt->pad, + &fmt->format); +} + +/* + * csi2_set_stream - Enable/Disable streaming on the CSI2 module + * @sd: ISP CSI2 V4L2 subdevice + * @enable: Enable/disable stream (1/0) + * + * Return 0 on success or a negative error code otherwise. +*/ +static int csi2_set_stream(struct v4l2_subdev *sd, int enable) +{ + return 0; +} + +/* subdev core operations */ +static const struct v4l2_subdev_core_ops csi2_core_ops = { +}; + +/* subdev video operations */ +static const struct v4l2_subdev_video_ops csi2_video_ops = { + .s_stream = csi2_set_stream, +}; + +/* subdev pad operations */ +static const struct v4l2_subdev_pad_ops csi2_pad_ops = { + .enum_mbus_code = csi2_enum_mbus_code, + .get_fmt = csi2_get_format, + .set_fmt = csi2_set_format, + .link_validate = v4l2_subdev_link_validate_default, +}; + +/* subdev operations */ +static const struct v4l2_subdev_ops csi2_ops = { + .core = &csi2_core_ops, + .video = &csi2_video_ops, + .pad = &csi2_pad_ops, +}; + +#ifndef ISP2401 + +#endif +/* + * csi2_link_setup - Setup CSI2 connections. + * @entity : Pointer to media entity structure + * @local : Pointer to local pad array + * @remote : Pointer to remote pad array + * @flags : Link flags + * return -EINVAL or zero on success +*/ +static int csi2_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); + struct atomisp_mipi_csi2_device *csi2 = v4l2_get_subdevdata(sd); + u32 result = local->index | is_media_entity_v4l2_subdev(remote->entity); + + switch (result) { + case CSI2_PAD_SOURCE | MEDIA_ENT_F_OLD_BASE: + /* not supported yet */ + return -EINVAL; + + case CSI2_PAD_SOURCE | MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN: + if (flags & MEDIA_LNK_FL_ENABLED) { + if (csi2->output & ~CSI2_OUTPUT_ISP_SUBDEV) + return -EBUSY; + csi2->output |= CSI2_OUTPUT_ISP_SUBDEV; + } else { + csi2->output &= ~CSI2_OUTPUT_ISP_SUBDEV; + } + break; + + default: + /* Link from camera to CSI2 is fixed... */ + return -EINVAL; + } + return 0; +} + +/* media operations */ +static const struct media_entity_operations csi2_media_ops = { + .link_setup = csi2_link_setup, + .link_validate = v4l2_subdev_link_validate, +}; + +/* +* ispcsi2_init_entities - Initialize subdev and media entity. +* @csi2: Pointer to ispcsi2 structure. +* return -ENOMEM or zero on success +*/ +static int mipi_csi2_init_entities(struct atomisp_mipi_csi2_device *csi2, + int port) +{ + struct v4l2_subdev *sd = &csi2->subdev; + struct media_pad *pads = csi2->pads; + struct media_entity *me = &sd->entity; + int ret; + + v4l2_subdev_init(sd, &csi2_ops); + snprintf(sd->name, sizeof(sd->name), "ATOM ISP CSI2-port%d", port); + + v4l2_set_subdevdata(sd, csi2); + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + + pads[CSI2_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE; + pads[CSI2_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + + me->ops = &csi2_media_ops; + me->function = MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN; + ret = media_entity_pads_init(me, CSI2_PADS_NUM, pads); + if (ret < 0) + return ret; + + csi2->formats[CSI2_PAD_SINK].code = + csi2->formats[CSI2_PAD_SOURCE].code = + atomisp_in_fmt_conv[0].code; + + return 0; +} + +void +atomisp_mipi_csi2_unregister_entities(struct atomisp_mipi_csi2_device *csi2) +{ + media_entity_cleanup(&csi2->subdev.entity); + v4l2_device_unregister_subdev(&csi2->subdev); +} + +int atomisp_mipi_csi2_register_entities(struct atomisp_mipi_csi2_device *csi2, + struct v4l2_device *vdev) +{ + int ret; + + /* Register the subdev and video nodes. */ + ret = v4l2_device_register_subdev(vdev, &csi2->subdev); + if (ret < 0) + goto error; + + return 0; + +error: + atomisp_mipi_csi2_unregister_entities(csi2); + return ret; +} + +static const int LIMIT_SHIFT = 6; /* Limit numeric range into 31 bits */ + +static int +atomisp_csi2_configure_calc(const short int coeffs[2], int mipi_freq, int def) +{ + /* Delay counter accuracy, 1/0.0625 for ANN/CHT, 1/0.125 for BXT */ + static const int accinv = 16; /* 1 / COUNT_ACC */ + int r; + + if (mipi_freq >> LIMIT_SHIFT <= 0) + return def; + + r = accinv * coeffs[1] * (500000000 >> LIMIT_SHIFT); + r /= mipi_freq >> LIMIT_SHIFT; + r += accinv * coeffs[0]; + + return r; +} + +static void atomisp_csi2_configure_isp2401(struct atomisp_sub_device *asd) +{ + /* + * The ISP2401 new input system CSI2+ receiver has several + * parameters affecting the receiver timings. These depend + * on the MIPI bus frequency F in Hz (sensor transmitter rate) + * as follows: + * register value = (A/1e9 + B * UI) / COUNT_ACC + * where + * UI = 1 / (2 * F) in seconds + * COUNT_ACC = counter accuracy in seconds + * For ANN and CHV, COUNT_ACC = 0.0625 ns + * For BXT, COUNT_ACC = 0.125 ns + * A and B are coefficients from the table below, + * depending whether the register minimum or maximum value is + * calculated. + * Minimum Maximum + * Clock lane A B A B + * reg_rx_csi_dly_cnt_termen_clane 0 0 38 0 + * reg_rx_csi_dly_cnt_settle_clane 95 -8 300 -16 + * Data lanes + * reg_rx_csi_dly_cnt_termen_dlane0 0 0 35 4 + * reg_rx_csi_dly_cnt_settle_dlane0 85 -2 145 -6 + * reg_rx_csi_dly_cnt_termen_dlane1 0 0 35 4 + * reg_rx_csi_dly_cnt_settle_dlane1 85 -2 145 -6 + * reg_rx_csi_dly_cnt_termen_dlane2 0 0 35 4 + * reg_rx_csi_dly_cnt_settle_dlane2 85 -2 145 -6 + * reg_rx_csi_dly_cnt_termen_dlane3 0 0 35 4 + * reg_rx_csi_dly_cnt_settle_dlane3 85 -2 145 -6 + * + * We use the minimum values in the calculations below. + */ + static const short int coeff_clk_termen[] = { 0, 0 }; + static const short int coeff_clk_settle[] = { 95, -8 }; + static const short int coeff_dat_termen[] = { 0, 0 }; + static const short int coeff_dat_settle[] = { 85, -2 }; + static const int TERMEN_DEFAULT = 0 * 0; + static const int SETTLE_DEFAULT = 0x480; + static const hrt_address csi2_port_base[] = { + [ATOMISP_CAMERA_PORT_PRIMARY] = CSI2_PORT_A_BASE, + [ATOMISP_CAMERA_PORT_SECONDARY] = CSI2_PORT_B_BASE, + [ATOMISP_CAMERA_PORT_TERTIARY] = CSI2_PORT_C_BASE, + }; + /* Number of lanes on each port, excluding clock lane */ + static const unsigned char csi2_port_lanes[] = { + [ATOMISP_CAMERA_PORT_PRIMARY] = 4, + [ATOMISP_CAMERA_PORT_SECONDARY] = 2, + [ATOMISP_CAMERA_PORT_TERTIARY] = 2, + }; + static const hrt_address csi2_lane_base[] = { + CSI2_LANE_CL_BASE, + CSI2_LANE_D0_BASE, + CSI2_LANE_D1_BASE, + CSI2_LANE_D2_BASE, + CSI2_LANE_D3_BASE, + }; + + int clk_termen; + int clk_settle; + int dat_termen; + int dat_settle; + + struct v4l2_control ctrl; + struct atomisp_device *isp = asd->isp; + struct camera_mipi_info *mipi_info; + int mipi_freq = 0; + enum atomisp_camera_port port; + + int n; + + mipi_info = atomisp_to_sensor_mipi_info( + isp->inputs[asd->input_curr].camera); + port = mipi_info->port; + + ctrl.id = V4L2_CID_LINK_FREQ; + if (v4l2_g_ctrl + (isp->inputs[asd->input_curr].camera->ctrl_handler, &ctrl) == 0) + mipi_freq = ctrl.value; + + clk_termen = atomisp_csi2_configure_calc(coeff_clk_termen, + mipi_freq, TERMEN_DEFAULT); + clk_settle = atomisp_csi2_configure_calc(coeff_clk_settle, + mipi_freq, SETTLE_DEFAULT); + dat_termen = atomisp_csi2_configure_calc(coeff_dat_termen, + mipi_freq, TERMEN_DEFAULT); + dat_settle = atomisp_csi2_configure_calc(coeff_dat_settle, + mipi_freq, SETTLE_DEFAULT); + for (n = 0; n < csi2_port_lanes[port] + 1; n++) { + hrt_address base = csi2_port_base[port] + csi2_lane_base[n]; + atomisp_store_uint32(base + CSI2_REG_RX_CSI_DLY_CNT_TERMEN, + n == 0 ? clk_termen : dat_termen); + atomisp_store_uint32(base + CSI2_REG_RX_CSI_DLY_CNT_SETTLE, + n == 0 ? clk_settle : dat_settle); + } +} + +void atomisp_csi2_configure(struct atomisp_sub_device *asd) +{ + if (IS_HWREVISION(asd->isp, ATOMISP_HW_REVISION_ISP2401)) + atomisp_csi2_configure_isp2401(asd); +} + +/* + * atomisp_mipi_csi2_cleanup - Routine for module driver cleanup +*/ +void atomisp_mipi_csi2_cleanup(struct atomisp_device *isp) +{ +} + +#ifndef ISP2401 + +#endif +int atomisp_mipi_csi2_init(struct atomisp_device *isp) +{ + struct atomisp_mipi_csi2_device *csi2_port; + unsigned int i; + int ret; + + for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) { + csi2_port = &isp->csi2_port[i]; + csi2_port->isp = isp; + ret = mipi_csi2_init_entities(csi2_port, i); + if (ret < 0) + goto fail; + } + + return 0; + +fail: + atomisp_mipi_csi2_cleanup(isp); + return ret; +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_csi2.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_csi2.h new file mode 100644 index 0000000000000000000000000000000000000000..faa9cf7e05c04aae71244e6c052999dd24e83f39 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_csi2.h @@ -0,0 +1,61 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#ifndef __ATOMISP_CSI2_H__ +#define __ATOMISP_CSI2_H__ + +#include +#include + +#define CSI2_PAD_SINK 0 +#define CSI2_PAD_SOURCE 1 +#define CSI2_PADS_NUM 2 + +#define CSI2_OUTPUT_ISP_SUBDEV (1 << 0) +#define CSI2_OUTPUT_MEMORY (1 << 1) + +struct atomisp_device; +struct v4l2_device; +struct atomisp_sub_device; + +struct atomisp_mipi_csi2_device { + struct v4l2_subdev subdev; + struct media_pad pads[CSI2_PADS_NUM]; + struct v4l2_mbus_framefmt formats[CSI2_PADS_NUM]; + + struct v4l2_ctrl_handler ctrls; + struct atomisp_device *isp; + + u32 output; /* output direction */ +}; + +int atomisp_csi2_set_ffmt(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, + unsigned int which, uint16_t pad, + struct v4l2_mbus_framefmt *ffmt); +int atomisp_mipi_csi2_init(struct atomisp_device *isp); +void atomisp_mipi_csi2_cleanup(struct atomisp_device *isp); +void atomisp_mipi_csi2_unregister_entities( + struct atomisp_mipi_csi2_device *csi2); +int atomisp_mipi_csi2_register_entities(struct atomisp_mipi_csi2_device *csi2, + struct v4l2_device *vdev); + +void atomisp_csi2_configure(struct atomisp_sub_device *asd); + +#endif /* __ATOMISP_CSI2_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_dfs_tables.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_dfs_tables.h new file mode 100644 index 0000000000000000000000000000000000000000..dfb94e67459c1a2cf80ac974648f564d863b4c7d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_dfs_tables.h @@ -0,0 +1,416 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#ifndef __ATOMISP_DFS_TABLES_H__ +#define __ATOMISP_DFS_TABLES_H__ + +#include + +struct atomisp_freq_scaling_rule { + unsigned int width; + unsigned int height; + unsigned short fps; + unsigned int isp_freq; + unsigned int run_mode; +}; + + +struct atomisp_dfs_config { + unsigned int lowest_freq; + unsigned int max_freq_at_vmin; + unsigned int highest_freq; + const struct atomisp_freq_scaling_rule *dfs_table; + unsigned int dfs_table_size; +}; + +static const struct atomisp_freq_scaling_rule dfs_rules_merr[] = { + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_PREVIEW, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_457MHZ, + .run_mode = ATOMISP_RUN_MODE_SDV, + }, +}; + +/* Merrifield and Moorefield DFS rules */ +static const struct atomisp_dfs_config dfs_config_merr = { + .lowest_freq = ISP_FREQ_200MHZ, + .max_freq_at_vmin = ISP_FREQ_400MHZ, + .highest_freq = ISP_FREQ_457MHZ, + .dfs_table = dfs_rules_merr, + .dfs_table_size = ARRAY_SIZE(dfs_rules_merr), +}; + +static const struct atomisp_freq_scaling_rule dfs_rules_merr_1179[] = { + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_PREVIEW, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_SDV, + }, +}; + +static const struct atomisp_dfs_config dfs_config_merr_1179 = { + .lowest_freq = ISP_FREQ_200MHZ, + .max_freq_at_vmin = ISP_FREQ_400MHZ, + .highest_freq = ISP_FREQ_400MHZ, + .dfs_table = dfs_rules_merr_1179, + .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_1179), +}; + +static const struct atomisp_freq_scaling_rule dfs_rules_merr_117a[] = { + { + .width = 1920, + .height = 1080, + .fps = 30, + .isp_freq = ISP_FREQ_266MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = 1080, + .height = 1920, + .fps = 30, +#ifndef ISP2401 + .isp_freq = ISP_FREQ_266MHZ, +#else + .isp_freq = ISP_FREQ_400MHZ, +#endif + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = 1920, + .height = 1080, + .fps = 45, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = 1080, + .height = 1920, + .fps = 45, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = 60, + .isp_freq = ISP_FREQ_356MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_200MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_200MHZ, + .run_mode = ATOMISP_RUN_MODE_PREVIEW, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_SDV, + }, +}; + +static const struct atomisp_dfs_config dfs_config_merr_117a = { + .lowest_freq = ISP_FREQ_200MHZ, + .max_freq_at_vmin = ISP_FREQ_200MHZ, + .highest_freq = ISP_FREQ_400MHZ, + .dfs_table = dfs_rules_merr_117a, + .dfs_table_size = ARRAY_SIZE(dfs_rules_merr_117a), +}; + +static const struct atomisp_freq_scaling_rule dfs_rules_byt[] = { + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_PREVIEW, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_400MHZ, + .run_mode = ATOMISP_RUN_MODE_SDV, + }, +}; + +static const struct atomisp_dfs_config dfs_config_byt = { + .lowest_freq = ISP_FREQ_200MHZ, + .max_freq_at_vmin = ISP_FREQ_400MHZ, + .highest_freq = ISP_FREQ_400MHZ, + .dfs_table = dfs_rules_byt, + .dfs_table_size = ARRAY_SIZE(dfs_rules_byt), +}; + +static const struct atomisp_freq_scaling_rule dfs_rules_byt_cr[] = { + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_PREVIEW, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_SDV, + }, +}; + +static const struct atomisp_dfs_config dfs_config_byt_cr = { + .lowest_freq = ISP_FREQ_200MHZ, + .max_freq_at_vmin = ISP_FREQ_320MHZ, + .highest_freq = ISP_FREQ_320MHZ, + .dfs_table = dfs_rules_byt_cr, + .dfs_table_size = ARRAY_SIZE(dfs_rules_byt_cr), +}; + +static const struct atomisp_freq_scaling_rule dfs_rules_cht[] = { + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_356MHZ, + .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_PREVIEW, + }, + { +#ifdef ISP2401 + .width = 1280, + .height = 720, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_SDV, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_356MHZ, + .run_mode = ATOMISP_RUN_MODE_SDV, + }, +}; + +static const struct atomisp_freq_scaling_rule dfs_rules_cht_soc[] = { + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_356MHZ, + .run_mode = ATOMISP_RUN_MODE_VIDEO, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_356MHZ, + .run_mode = ATOMISP_RUN_MODE_STILL_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE, + }, + { + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_320MHZ, + .run_mode = ATOMISP_RUN_MODE_PREVIEW, + }, + { +#endif + .width = ISP_FREQ_RULE_ANY, + .height = ISP_FREQ_RULE_ANY, + .fps = ISP_FREQ_RULE_ANY, + .isp_freq = ISP_FREQ_356MHZ, + .run_mode = ATOMISP_RUN_MODE_SDV, + }, +}; + +static const struct atomisp_dfs_config dfs_config_cht = { + .lowest_freq = ISP_FREQ_100MHZ, + .max_freq_at_vmin = ISP_FREQ_356MHZ, + .highest_freq = ISP_FREQ_356MHZ, + .dfs_table = dfs_rules_cht, + .dfs_table_size = ARRAY_SIZE(dfs_rules_cht), +}; + +#ifdef ISP2401 +static const struct atomisp_dfs_config dfs_config_cht_soc = { + .lowest_freq = ISP_FREQ_100MHZ, + .max_freq_at_vmin = ISP_FREQ_356MHZ, + .highest_freq = ISP_FREQ_356MHZ, + .dfs_table = dfs_rules_cht_soc, + .dfs_table_size = ARRAY_SIZE(dfs_rules_cht_soc), +}; + +#endif +#endif /* __ATOMISP_DFS_TABLES_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_drvfs.c b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_drvfs.c new file mode 100644 index 0000000000000000000000000000000000000000..327a5c535fab391f00ac20b91250bd6f6c61dea5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_drvfs.c @@ -0,0 +1,218 @@ +/* + * Support for atomisp driver sysfs interface + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include +#include + +#include "atomisp_compat.h" +#include "atomisp_internal.h" +#include "atomisp_ioctl.h" +#include "hmm/hmm.h" + +/* + * _iunit_debug: + * dbglvl: iunit css driver trace level + * dbgopt: iunit debug option: + * bit 0: binary list + * bit 1: running binary + * bit 2: memory statistic +*/ +struct _iunit_debug { + struct pci_driver *drv; + struct atomisp_device *isp; + unsigned int dbglvl; + unsigned int dbgfun; + unsigned int dbgopt; +}; + +#define OPTION_BIN_LIST (1<<0) +#define OPTION_BIN_RUN (1<<1) +#define OPTION_MEM_STAT (1<<2) +#define OPTION_VALID (OPTION_BIN_LIST \ + | OPTION_BIN_RUN \ + | OPTION_MEM_STAT) + +static struct _iunit_debug iunit_debug = { + .dbglvl = 0, + .dbgopt = OPTION_BIN_LIST, +}; + +static inline int iunit_dump_dbgopt(struct atomisp_device *isp, + unsigned int opt) +{ + int ret = 0; + + if (opt & OPTION_VALID) { + if (opt & OPTION_BIN_LIST) { + ret = atomisp_css_dump_blob_infor(); + if (ret) { + dev_err(atomisp_dev, "%s dump blob infor err[ret:%d]\n", + __func__, ret); + goto opt_err; + } + } + + if (opt & OPTION_BIN_RUN) { + if (atomisp_streaming_count(isp)) { + atomisp_css_dump_sp_raw_copy_linecount(true); + atomisp_css_debug_dump_isp_binary(); + } else { + ret = -EPERM; + dev_err(atomisp_dev, "%s dump running bin err[ret:%d]\n", + __func__, ret); + goto opt_err; + } + } + + if (opt & OPTION_MEM_STAT) + hmm_show_mem_stat(__func__, __LINE__); + } else { + ret = -EINVAL; + dev_err(atomisp_dev, "%s dump nothing[ret=%d]\n", __func__, + ret); + } + +opt_err: + return ret; +} + +static ssize_t iunit_dbglvl_show(struct device_driver *drv, char *buf) +{ + iunit_debug.dbglvl = atomisp_css_debug_get_dtrace_level(); + return sprintf(buf, "dtrace level:%u\n", iunit_debug.dbglvl); +} + +static ssize_t iunit_dbglvl_store(struct device_driver *drv, const char *buf, + size_t size) +{ + if (kstrtouint(buf, 10, &iunit_debug.dbglvl) + || iunit_debug.dbglvl < 1 + || iunit_debug.dbglvl > 9) { + dev_err(atomisp_dev, "%s setting %d value invalid, should be [1,9]\n", + __func__, iunit_debug.dbglvl); + return -EINVAL; + } + atomisp_css_debug_set_dtrace_level(iunit_debug.dbglvl); + + return size; +} + +static ssize_t iunit_dbgfun_show(struct device_driver *drv, char *buf) +{ + iunit_debug.dbgfun = atomisp_get_css_dbgfunc(); + return sprintf(buf, "dbgfun opt:%u\n", iunit_debug.dbgfun); +} + +static ssize_t iunit_dbgfun_store(struct device_driver *drv, const char *buf, + size_t size) +{ + unsigned int opt; + int ret; + + if (kstrtouint(buf, 10, &opt)) { + dev_err(atomisp_dev, "%s setting %d value invalid\n", + __func__, opt); + return -EINVAL; + } + + ret = atomisp_set_css_dbgfunc(iunit_debug.isp, opt); + if (ret) + return ret; + + iunit_debug.dbgfun = opt; + + return size; +} + +static ssize_t iunit_dbgopt_show(struct device_driver *drv, char *buf) +{ + return sprintf(buf, "option:0x%x\n", iunit_debug.dbgopt); +} + +static ssize_t iunit_dbgopt_store(struct device_driver *drv, const char *buf, + size_t size) +{ + unsigned int opt; + int ret; + + if (kstrtouint(buf, 10, &opt)) { + dev_err(atomisp_dev, "%s setting %d value invalid\n", + __func__, opt); + return -EINVAL; + } + + iunit_debug.dbgopt = opt; + ret = iunit_dump_dbgopt(iunit_debug.isp, iunit_debug.dbgopt); + if (ret) + return ret; + + return size; +} + +static struct driver_attribute iunit_drvfs_attrs[] = { + __ATTR(dbglvl, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH, iunit_dbglvl_show, + iunit_dbglvl_store), + __ATTR(dbgfun, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH, iunit_dbgfun_show, + iunit_dbgfun_store), + __ATTR(dbgopt, S_IRUSR|S_IWUSR|S_IRGRP|S_IROTH, iunit_dbgopt_show, + iunit_dbgopt_store), +}; + +static int iunit_drvfs_create_files(struct pci_driver *drv) +{ + int i, ret = 0; + + for (i = 0; i < ARRAY_SIZE(iunit_drvfs_attrs); i++) + ret |= driver_create_file(&(drv->driver), + &iunit_drvfs_attrs[i]); + + return ret; +} + +static void iunit_drvfs_remove_files(struct pci_driver *drv) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(iunit_drvfs_attrs); i++) + driver_remove_file(&(drv->driver), &iunit_drvfs_attrs[i]); +} + +int atomisp_drvfs_init(struct pci_driver *drv, struct atomisp_device *isp) +{ + int ret; + + iunit_debug.isp = isp; + iunit_debug.drv = drv; + + ret = iunit_drvfs_create_files(iunit_debug.drv); + if (ret) { + dev_err(atomisp_dev, "drvfs_create_files error: %d\n", ret); + iunit_drvfs_remove_files(drv); + } + + return ret; +} + +void atomisp_drvfs_exit(void) +{ + iunit_drvfs_remove_files(iunit_debug.drv); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_drvfs.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_drvfs.h new file mode 100644 index 0000000000000000000000000000000000000000..5cb717b0c1c2fcb2b8d8a6282ccbfc079ae0f6aa --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_drvfs.h @@ -0,0 +1,29 @@ +/* + * Support for atomisp driver sysfs interface. + * + * Copyright (c) 2014 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __ATOMISP_DRVFS_H__ +#define __ATOMISP_DRVFS_H__ + +extern int atomisp_drvfs_init(struct pci_driver *drv, struct atomisp_device + *isp); +extern void atomisp_drvfs_exit(void); + +#endif /* __ATOMISP_DRVFS_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_file.c b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_file.c new file mode 100644 index 0000000000000000000000000000000000000000..c766119bf7981336550819e7328f017a007f0495 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_file.c @@ -0,0 +1,245 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include + +#include +#include + +#include "ia_css.h" + +#include "atomisp_cmd.h" +#include "atomisp_common.h" +#include "atomisp_file.h" +#include "atomisp_internal.h" +#include "atomisp_ioctl.h" + +static void file_work(struct work_struct *work) +{ + struct atomisp_file_device *file_dev = + container_of(work, struct atomisp_file_device, work); + struct atomisp_device *isp = file_dev->isp; + /* only support file injection on subdev0 */ + struct atomisp_sub_device *asd = &isp->asd[0]; + struct atomisp_video_pipe *out_pipe = &asd->video_in; + unsigned short *buf = videobuf_to_vmalloc(out_pipe->outq.bufs[0]); + struct v4l2_mbus_framefmt isp_sink_fmt; + + if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED) + return; + + dev_dbg(isp->dev, ">%s: ready to start streaming\n", __func__); + isp_sink_fmt = *atomisp_subdev_get_ffmt(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK); + + while (!atomisp_css_isp_has_started()) + usleep_range(1000, 1500); + + atomisp_css_send_input_frame(asd, buf, isp_sink_fmt.width, + isp_sink_fmt.height); + dev_dbg(isp->dev, "<%s: streaming done\n", __func__); +} + +static int file_input_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct atomisp_file_device *file_dev = v4l2_get_subdevdata(sd); + struct atomisp_device *isp = file_dev->isp; + /* only support file injection on subdev0 */ + struct atomisp_sub_device *asd = &isp->asd[0]; + + dev_dbg(isp->dev, "%s: enable %d\n", __func__, enable); + if (enable) { + if (asd->streaming != ATOMISP_DEVICE_STREAMING_ENABLED) + return 0; + + queue_work(file_dev->work_queue, &file_dev->work); + return 0; + } + cancel_work_sync(&file_dev->work); + return 0; +} + +static int file_input_g_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + /*to fake*/ + return 0; +} + +static int file_input_s_parm(struct v4l2_subdev *sd, + struct v4l2_streamparm *param) +{ + /*to fake*/ + return 0; +} + +static int file_input_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + struct atomisp_file_device *file_dev = v4l2_get_subdevdata(sd); + struct atomisp_device *isp = file_dev->isp; + /* only support file injection on subdev0 */ + struct atomisp_sub_device *asd = &isp->asd[0]; + struct v4l2_mbus_framefmt *isp_sink_fmt; + if (format->pad) + return -EINVAL; + isp_sink_fmt = atomisp_subdev_get_ffmt(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK); + + fmt->width = isp_sink_fmt->width; + fmt->height = isp_sink_fmt->height; + fmt->code = isp_sink_fmt->code; + + return 0; +} + +static int file_input_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + if (format->pad) + return -EINVAL; + file_input_get_fmt(sd, cfg, format); + if (format->which == V4L2_SUBDEV_FORMAT_TRY) + cfg->try_fmt = *fmt; + return 0; +} + +static int file_input_log_status(struct v4l2_subdev *sd) +{ + /*to fake*/ + return 0; +} + +static int file_input_s_power(struct v4l2_subdev *sd, int on) +{ + /* to fake */ + return 0; +} + +static int file_input_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + /*to fake*/ + return 0; +} + +static int file_input_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + /*to fake*/ + return 0; +} + +static int file_input_enum_frame_ival(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum + *fie) +{ + /*to fake*/ + return 0; +} + +static const struct v4l2_subdev_video_ops file_input_video_ops = { + .s_stream = file_input_s_stream, + .g_parm = file_input_g_parm, + .s_parm = file_input_s_parm, +}; + +static const struct v4l2_subdev_core_ops file_input_core_ops = { + .log_status = file_input_log_status, + .s_power = file_input_s_power, +}; + +static const struct v4l2_subdev_pad_ops file_input_pad_ops = { + .enum_mbus_code = file_input_enum_mbus_code, + .enum_frame_size = file_input_enum_frame_size, + .enum_frame_interval = file_input_enum_frame_ival, + .get_fmt = file_input_get_fmt, + .set_fmt = file_input_set_fmt, +}; + +static const struct v4l2_subdev_ops file_input_ops = { + .core = &file_input_core_ops, + .video = &file_input_video_ops, + .pad = &file_input_pad_ops, +}; + +void +atomisp_file_input_unregister_entities(struct atomisp_file_device *file_dev) +{ + media_entity_cleanup(&file_dev->sd.entity); + v4l2_device_unregister_subdev(&file_dev->sd); +} + +int atomisp_file_input_register_entities(struct atomisp_file_device *file_dev, + struct v4l2_device *vdev) +{ + /* Register the subdev and video nodes. */ + return v4l2_device_register_subdev(vdev, &file_dev->sd); +} + +void atomisp_file_input_cleanup(struct atomisp_device *isp) +{ + struct atomisp_file_device *file_dev = &isp->file_dev; + + if (file_dev->work_queue) { + destroy_workqueue(file_dev->work_queue); + file_dev->work_queue = NULL; + } +} + +int atomisp_file_input_init(struct atomisp_device *isp) +{ + struct atomisp_file_device *file_dev = &isp->file_dev; + struct v4l2_subdev *sd = &file_dev->sd; + struct media_pad *pads = file_dev->pads; + struct media_entity *me = &sd->entity; + + file_dev->isp = isp; + file_dev->work_queue = alloc_workqueue(isp->v4l2_dev.name, 0, 1); + if (file_dev->work_queue == NULL) { + dev_err(isp->dev, "Failed to initialize file inject workq\n"); + return -ENOMEM; + } + + INIT_WORK(&file_dev->work, file_work); + + v4l2_subdev_init(sd, &file_input_ops); + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + strcpy(sd->name, "file_input_subdev"); + v4l2_set_subdevdata(sd, file_dev); + + pads[0].flags = MEDIA_PAD_FL_SINK; + me->function = MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN; + + return media_entity_pads_init(me, 1, pads); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_file.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_file.h new file mode 100644 index 0000000000000000000000000000000000000000..1b86abd35c383c57808d802d721dc3363f144276 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_file.h @@ -0,0 +1,47 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __ATOMISP_FILE_H__ +#define __ATOMISP_FILE_H__ + +#include +#include + +struct atomisp_device; + +struct atomisp_file_device { + struct v4l2_subdev sd; + struct atomisp_device *isp; + struct media_pad pads[1]; + + struct workqueue_struct *work_queue; + struct work_struct work; +}; + +void atomisp_file_input_cleanup(struct atomisp_device *isp); +int atomisp_file_input_init(struct atomisp_device *isp); +void atomisp_file_input_unregister_entities( + struct atomisp_file_device *file_dev); +int atomisp_file_input_register_entities(struct atomisp_file_device *file_dev, + struct v4l2_device *vdev); +#endif /* __ATOMISP_FILE_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_fops.c b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_fops.c new file mode 100644 index 0000000000000000000000000000000000000000..20e581e5a94b6d53253ada13d4920d782241f440 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_fops.c @@ -0,0 +1,1304 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include + +#include +#include + +#include "atomisp_cmd.h" +#include "atomisp_common.h" +#include "atomisp_fops.h" +#include "atomisp_internal.h" +#include "atomisp_ioctl.h" +#include "atomisp_compat.h" +#include "atomisp_subdev.h" +#include "atomisp_v4l2.h" +#include "atomisp-regs.h" +#include "hmm/hmm.h" + +#include "hrt/hive_isp_css_mm_hrt.h" + +#include "type_support.h" +#include "device_access/device_access.h" +#include "memory_access/memory_access.h" + +#include "atomisp_acc.h" + +#define ISP_LEFT_PAD 128 /* equal to 2*NWAY */ + +/* + * input image data, and current frame resolution for test + */ +#define ISP_PARAM_MMAP_OFFSET 0xfffff000 + +#define MAGIC_CHECK(is, should) \ + do { \ + if (unlikely((is) != (should))) { \ + pr_err("magic mismatch: %x (expected %x)\n", \ + is, should); \ + BUG(); \ + } \ + } while (0) + +/* + * Videobuf ops + */ +static int atomisp_buf_setup(struct videobuf_queue *vq, unsigned int *count, + unsigned int *size) +{ + struct atomisp_video_pipe *pipe = vq->priv_data; + + *size = pipe->pix.sizeimage; + + return 0; +} + +static int atomisp_buf_prepare(struct videobuf_queue *vq, + struct videobuf_buffer *vb, + enum v4l2_field field) +{ + struct atomisp_video_pipe *pipe = vq->priv_data; + + vb->size = pipe->pix.sizeimage; + vb->width = pipe->pix.width; + vb->height = pipe->pix.height; + vb->field = field; + vb->state = VIDEOBUF_PREPARED; + + return 0; +} + +static int atomisp_q_one_metadata_buffer(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_pipe_id css_pipe_id) +{ + struct atomisp_metadata_buf *metadata_buf; + enum atomisp_metadata_type md_type = + atomisp_get_metadata_type(asd, css_pipe_id); + struct list_head *metadata_list; + + if (asd->metadata_bufs_in_css[stream_id][css_pipe_id] >= + ATOMISP_CSS_Q_DEPTH) + return 0; /* we have reached CSS queue depth */ + + if (!list_empty(&asd->metadata[md_type])) { + metadata_list = &asd->metadata[md_type]; + } else if (!list_empty(&asd->metadata_ready[md_type])) { + metadata_list = &asd->metadata_ready[md_type]; + } else { + dev_warn(asd->isp->dev, "%s: No metadata buffers available for type %d!\n", + __func__, md_type); + return -EINVAL; + } + + metadata_buf = list_entry(metadata_list->next, + struct atomisp_metadata_buf, list); + list_del_init(&metadata_buf->list); + + if (atomisp_q_metadata_buffer_to_css(asd, metadata_buf, + stream_id, css_pipe_id)) { + list_add(&metadata_buf->list, metadata_list); + return -EINVAL; + } else { + list_add_tail(&metadata_buf->list, + &asd->metadata_in_css[md_type]); + } + asd->metadata_bufs_in_css[stream_id][css_pipe_id]++; + + return 0; +} + +int atomisp_q_one_s3a_buffer(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_pipe_id css_pipe_id) +{ + struct atomisp_s3a_buf *s3a_buf; + struct list_head *s3a_list; + unsigned int exp_id; + + if (asd->s3a_bufs_in_css[css_pipe_id] >= ATOMISP_CSS_Q_DEPTH) + return 0; /* we have reached CSS queue depth */ + + if (!list_empty(&asd->s3a_stats)) { + s3a_list = &asd->s3a_stats; + } else if (!list_empty(&asd->s3a_stats_ready)) { + s3a_list = &asd->s3a_stats_ready; + } else { + dev_warn(asd->isp->dev, "%s: No s3a buffers available!\n", + __func__); + return -EINVAL; + } + + s3a_buf = list_entry(s3a_list->next, struct atomisp_s3a_buf, list); + list_del_init(&s3a_buf->list); + exp_id = s3a_buf->s3a_data->exp_id; + + hmm_flush_vmap(s3a_buf->s3a_data->data_ptr); + if (atomisp_q_s3a_buffer_to_css(asd, s3a_buf, + stream_id, css_pipe_id)) { + /* got from head, so return back to the head */ + list_add(&s3a_buf->list, s3a_list); + return -EINVAL; + } else { + list_add_tail(&s3a_buf->list, &asd->s3a_stats_in_css); + if (s3a_list == &asd->s3a_stats_ready) + dev_warn(asd->isp->dev, "%s: drop one s3a stat which has exp_id %d!\n", + __func__, exp_id); + } + + asd->s3a_bufs_in_css[css_pipe_id]++; + return 0; +} + +int atomisp_q_one_dis_buffer(struct atomisp_sub_device *asd, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_pipe_id css_pipe_id) +{ + struct atomisp_dis_buf *dis_buf; + unsigned long irqflags; + + if (asd->dis_bufs_in_css >= ATOMISP_CSS_Q_DEPTH) + return 0; /* we have reached CSS queue depth */ + + spin_lock_irqsave(&asd->dis_stats_lock, irqflags); + if (list_empty(&asd->dis_stats)) { + spin_unlock_irqrestore(&asd->dis_stats_lock, irqflags); + dev_warn(asd->isp->dev, "%s: No dis buffers available!\n", + __func__); + return -EINVAL; + } + + dis_buf = list_entry(asd->dis_stats.prev, + struct atomisp_dis_buf, list); + list_del_init(&dis_buf->list); + spin_unlock_irqrestore(&asd->dis_stats_lock, irqflags); + + hmm_flush_vmap(dis_buf->dis_data->data_ptr); + if (atomisp_q_dis_buffer_to_css(asd, dis_buf, + stream_id, css_pipe_id)) { + spin_lock_irqsave(&asd->dis_stats_lock, irqflags); + /* got from tail, so return back to the tail */ + list_add_tail(&dis_buf->list, &asd->dis_stats); + spin_unlock_irqrestore(&asd->dis_stats_lock, irqflags); + return -EINVAL; + } else { + spin_lock_irqsave(&asd->dis_stats_lock, irqflags); + list_add_tail(&dis_buf->list, &asd->dis_stats_in_css); + spin_unlock_irqrestore(&asd->dis_stats_lock, irqflags); + } + + asd->dis_bufs_in_css++; + + return 0; +} + +int atomisp_q_video_buffers_to_css(struct atomisp_sub_device *asd, + struct atomisp_video_pipe *pipe, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_buffer_type css_buf_type, + enum atomisp_css_pipe_id css_pipe_id) +{ + struct videobuf_vmalloc_memory *vm_mem; + struct atomisp_css_params_with_list *param; + struct atomisp_css_dvs_grid_info *dvs_grid = + atomisp_css_get_dvs_grid_info(&asd->params.curr_grid_info); + unsigned long irqflags; + int err = 0; + + while (pipe->buffers_in_css < ATOMISP_CSS_Q_DEPTH) { + struct videobuf_buffer *vb; + + spin_lock_irqsave(&pipe->irq_lock, irqflags); + if (list_empty(&pipe->activeq)) { + spin_unlock_irqrestore(&pipe->irq_lock, irqflags); + return -EINVAL; + } + vb = list_entry(pipe->activeq.next, + struct videobuf_buffer, queue); + list_del_init(&vb->queue); + vb->state = VIDEOBUF_ACTIVE; + spin_unlock_irqrestore(&pipe->irq_lock, irqflags); + + /* + * If there is a per_frame setting to apply on the buffer, + * do it before buffer en-queueing. + */ + vm_mem = vb->priv; + + param = pipe->frame_params[vb->i]; + if (param) { + atomisp_makeup_css_parameters(asd, + &asd->params.css_param.update_flag, + ¶m->params); + atomisp_apply_css_parameters(asd, ¶m->params); + + if (param->params.update_flag.dz_config && + asd->run_mode->val != ATOMISP_RUN_MODE_VIDEO) { + err = atomisp_calculate_real_zoom_region(asd, + ¶m->params.dz_config, css_pipe_id); + if (!err) + atomisp_css_set_dz_config(asd, + ¶m->params.dz_config); + } + atomisp_css_set_isp_config_applied_frame(asd, + vm_mem->vaddr); + atomisp_css_update_isp_params_on_pipe(asd, + asd->stream_env[stream_id].pipes[css_pipe_id]); + asd->params.dvs_6axis = (struct atomisp_css_dvs_6axis *) + param->params.dvs_6axis; + + /* + * WORKAROUND: + * Because the camera halv3 can't ensure to set zoom + * region to per_frame setting and global setting at + * same time and only set zoom region to pre_frame + * setting now.so when the pre_frame setting inculde + * zoom region,I will set it to global setting. + */ + if (param->params.update_flag.dz_config && + asd->run_mode->val != ATOMISP_RUN_MODE_VIDEO + && !err) { + memcpy(&asd->params.css_param.dz_config, + ¶m->params.dz_config, + sizeof(struct ia_css_dz_config)); + asd->params.css_param.update_flag.dz_config = + (struct atomisp_dz_config *) + &asd->params.css_param.dz_config; + asd->params.css_update_params_needed = true; + } + } + /* Enqueue buffer */ + err = atomisp_q_video_buffer_to_css(asd, vm_mem, stream_id, + css_buf_type, css_pipe_id); + if (err) { + spin_lock_irqsave(&pipe->irq_lock, irqflags); + list_add_tail(&vb->queue, &pipe->activeq); + vb->state = VIDEOBUF_QUEUED; + spin_unlock_irqrestore(&pipe->irq_lock, irqflags); + dev_err(asd->isp->dev, "%s, css q fails: %d\n", + __func__, err); + return -EINVAL; + } + pipe->buffers_in_css++; + + /* enqueue 3A/DIS/metadata buffers */ + if (asd->params.curr_grid_info.s3a_grid.enable && + css_pipe_id == asd->params.s3a_enabled_pipe && + css_buf_type == CSS_BUFFER_TYPE_OUTPUT_FRAME) + atomisp_q_one_s3a_buffer(asd, stream_id, + css_pipe_id); + + if (asd->stream_env[ATOMISP_INPUT_STREAM_GENERAL].stream_info. + metadata_info.size && + css_buf_type == CSS_BUFFER_TYPE_OUTPUT_FRAME) + atomisp_q_one_metadata_buffer(asd, stream_id, + css_pipe_id); + + if (dvs_grid && dvs_grid->enable && + css_pipe_id == CSS_PIPE_ID_VIDEO && + css_buf_type == CSS_BUFFER_TYPE_OUTPUT_FRAME) + atomisp_q_one_dis_buffer(asd, stream_id, + css_pipe_id); + } + + return 0; +} + +static int atomisp_get_css_buf_type(struct atomisp_sub_device *asd, + enum atomisp_css_pipe_id pipe_id, + uint16_t source_pad) +{ + if (ATOMISP_USE_YUVPP(asd)) { + /* when run ZSL case */ + if (asd->continuous_mode->val && + asd->run_mode->val == ATOMISP_RUN_MODE_PREVIEW) { + if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE) + return CSS_BUFFER_TYPE_OUTPUT_FRAME; + else if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW) + return CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME; + else + return CSS_BUFFER_TYPE_VF_OUTPUT_FRAME; + } + + /*when run SDV case*/ + if (asd->continuous_mode->val && + asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) { + if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE) + return CSS_BUFFER_TYPE_OUTPUT_FRAME; + else if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW) + return CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME; + else if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_VIDEO) + return CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME; + else + return CSS_BUFFER_TYPE_VF_OUTPUT_FRAME; + } + + /*other case: default setting*/ + if (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE || + source_pad == ATOMISP_SUBDEV_PAD_SOURCE_VIDEO || + (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW && + asd->run_mode->val != ATOMISP_RUN_MODE_VIDEO)) + return CSS_BUFFER_TYPE_OUTPUT_FRAME; + else + return CSS_BUFFER_TYPE_VF_OUTPUT_FRAME; + } + + if (pipe_id == CSS_PIPE_ID_COPY || + source_pad == ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE || + source_pad == ATOMISP_SUBDEV_PAD_SOURCE_VIDEO || + (source_pad == ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW && + asd->run_mode->val != ATOMISP_RUN_MODE_VIDEO)) + return CSS_BUFFER_TYPE_OUTPUT_FRAME; + else + return CSS_BUFFER_TYPE_VF_OUTPUT_FRAME; +} + +static int atomisp_qbuffers_to_css_for_all_pipes(struct atomisp_sub_device *asd) +{ + enum atomisp_css_buffer_type buf_type; + enum atomisp_css_pipe_id css_capture_pipe_id = CSS_PIPE_ID_COPY; + enum atomisp_css_pipe_id css_preview_pipe_id = CSS_PIPE_ID_COPY; + enum atomisp_css_pipe_id css_video_pipe_id = CSS_PIPE_ID_COPY; + enum atomisp_input_stream_id input_stream_id; + struct atomisp_video_pipe *capture_pipe; + struct atomisp_video_pipe *preview_pipe; + struct atomisp_video_pipe *video_pipe; + + capture_pipe = &asd->video_out_capture; + preview_pipe = &asd->video_out_preview; + video_pipe = &asd->video_out_video_capture; + + buf_type = atomisp_get_css_buf_type( + asd, css_preview_pipe_id, + atomisp_subdev_source_pad(&preview_pipe->vdev)); + input_stream_id = ATOMISP_INPUT_STREAM_PREVIEW; + atomisp_q_video_buffers_to_css(asd, preview_pipe, + input_stream_id, + buf_type, css_preview_pipe_id); + + buf_type = atomisp_get_css_buf_type(asd, css_capture_pipe_id, + atomisp_subdev_source_pad(&capture_pipe->vdev)); + input_stream_id = ATOMISP_INPUT_STREAM_GENERAL; + atomisp_q_video_buffers_to_css(asd, capture_pipe, + input_stream_id, + buf_type, css_capture_pipe_id); + + buf_type = atomisp_get_css_buf_type(asd, css_video_pipe_id, + atomisp_subdev_source_pad(&video_pipe->vdev)); + input_stream_id = ATOMISP_INPUT_STREAM_VIDEO; + atomisp_q_video_buffers_to_css(asd, video_pipe, + input_stream_id, + buf_type, css_video_pipe_id); + return 0; +} + + +/* queue all available buffers to css */ +int atomisp_qbuffers_to_css(struct atomisp_sub_device *asd) +{ + enum atomisp_css_buffer_type buf_type; + enum atomisp_css_pipe_id css_capture_pipe_id = CSS_PIPE_ID_NUM; + enum atomisp_css_pipe_id css_preview_pipe_id = CSS_PIPE_ID_NUM; + enum atomisp_css_pipe_id css_video_pipe_id = CSS_PIPE_ID_NUM; + enum atomisp_input_stream_id input_stream_id; + struct atomisp_video_pipe *capture_pipe = NULL; + struct atomisp_video_pipe *vf_pipe = NULL; + struct atomisp_video_pipe *preview_pipe = NULL; + struct atomisp_video_pipe *video_pipe = NULL; + bool raw_mode = atomisp_is_mbuscode_raw( + asd->fmt[asd->capture_pad].fmt.code); + + if (asd->isp->inputs[asd->input_curr].camera_caps-> + sensor[asd->sensor_curr].stream_num == 2 && + !asd->yuvpp_mode) + return atomisp_qbuffers_to_css_for_all_pipes(asd); + + if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_SCALER) { + video_pipe = &asd->video_out_video_capture; + css_video_pipe_id = CSS_PIPE_ID_VIDEO; + } else if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_LOWLAT) { + preview_pipe = &asd->video_out_capture; + css_preview_pipe_id = CSS_PIPE_ID_CAPTURE; + } else if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) { + if (asd->continuous_mode->val) { + capture_pipe = &asd->video_out_capture; + vf_pipe = &asd->video_out_vf; + css_capture_pipe_id = CSS_PIPE_ID_CAPTURE; + } + video_pipe = &asd->video_out_video_capture; + preview_pipe = &asd->video_out_preview; + css_video_pipe_id = CSS_PIPE_ID_VIDEO; + css_preview_pipe_id = CSS_PIPE_ID_VIDEO; + } else if (asd->continuous_mode->val) { + capture_pipe = &asd->video_out_capture; + vf_pipe = &asd->video_out_vf; + preview_pipe = &asd->video_out_preview; + + css_preview_pipe_id = CSS_PIPE_ID_PREVIEW; + css_capture_pipe_id = CSS_PIPE_ID_CAPTURE; + } else if (asd->run_mode->val == ATOMISP_RUN_MODE_PREVIEW) { + preview_pipe = &asd->video_out_preview; + css_preview_pipe_id = CSS_PIPE_ID_PREVIEW; + } else { + /* ATOMISP_RUN_MODE_STILL_CAPTURE */ + capture_pipe = &asd->video_out_capture; + if (!raw_mode) + vf_pipe = &asd->video_out_vf; + css_capture_pipe_id = CSS_PIPE_ID_CAPTURE; + } + +#ifdef ISP2401_NEW_INPUT_SYSTEM + if (asd->copy_mode) { + css_capture_pipe_id = CSS_PIPE_ID_COPY; + css_preview_pipe_id = CSS_PIPE_ID_COPY; + css_video_pipe_id = CSS_PIPE_ID_COPY; + } +#endif + + if (asd->yuvpp_mode) { + capture_pipe = &asd->video_out_capture; + video_pipe = &asd->video_out_video_capture; + preview_pipe = &asd->video_out_preview; + css_capture_pipe_id = CSS_PIPE_ID_COPY; + css_video_pipe_id = CSS_PIPE_ID_YUVPP; + css_preview_pipe_id = CSS_PIPE_ID_YUVPP; + } + + if (capture_pipe) { + buf_type = atomisp_get_css_buf_type( + asd, css_capture_pipe_id, + atomisp_subdev_source_pad(&capture_pipe->vdev)); + input_stream_id = ATOMISP_INPUT_STREAM_GENERAL; + + /* + * use yuvpp pipe for SOC camera. + */ + if (ATOMISP_USE_YUVPP(asd)) + css_capture_pipe_id = CSS_PIPE_ID_YUVPP; + + atomisp_q_video_buffers_to_css(asd, capture_pipe, + input_stream_id, + buf_type, css_capture_pipe_id); + } + + if (vf_pipe) { + buf_type = atomisp_get_css_buf_type( + asd, css_capture_pipe_id, + atomisp_subdev_source_pad(&vf_pipe->vdev)); + if (asd->stream_env[ATOMISP_INPUT_STREAM_POSTVIEW].stream) + input_stream_id = ATOMISP_INPUT_STREAM_POSTVIEW; + else + input_stream_id = ATOMISP_INPUT_STREAM_GENERAL; + + /* + * use yuvpp pipe for SOC camera. + */ + if (ATOMISP_USE_YUVPP(asd)) + css_capture_pipe_id = CSS_PIPE_ID_YUVPP; + atomisp_q_video_buffers_to_css(asd, vf_pipe, + input_stream_id, + buf_type, css_capture_pipe_id); + } + + if (preview_pipe) { + buf_type = atomisp_get_css_buf_type( + asd, css_preview_pipe_id, + atomisp_subdev_source_pad(&preview_pipe->vdev)); + if (ATOMISP_SOC_CAMERA(asd) && css_preview_pipe_id == CSS_PIPE_ID_YUVPP) + input_stream_id = ATOMISP_INPUT_STREAM_GENERAL; + /* else for ext isp use case */ + else if (css_preview_pipe_id == CSS_PIPE_ID_YUVPP) + input_stream_id = ATOMISP_INPUT_STREAM_VIDEO; + else if (asd->stream_env[ATOMISP_INPUT_STREAM_PREVIEW].stream) + input_stream_id = ATOMISP_INPUT_STREAM_PREVIEW; + else + input_stream_id = ATOMISP_INPUT_STREAM_GENERAL; + + /* + * use yuvpp pipe for SOC camera. + */ + if (ATOMISP_USE_YUVPP(asd)) + css_preview_pipe_id = CSS_PIPE_ID_YUVPP; + + atomisp_q_video_buffers_to_css(asd, preview_pipe, + input_stream_id, + buf_type, css_preview_pipe_id); + } + + if (video_pipe) { + buf_type = atomisp_get_css_buf_type( + asd, css_video_pipe_id, + atomisp_subdev_source_pad(&video_pipe->vdev)); + if (asd->stream_env[ATOMISP_INPUT_STREAM_VIDEO].stream) + input_stream_id = ATOMISP_INPUT_STREAM_VIDEO; + else + input_stream_id = ATOMISP_INPUT_STREAM_GENERAL; + + /* + * use yuvpp pipe for SOC camera. + */ + if (ATOMISP_USE_YUVPP(asd)) + css_video_pipe_id = CSS_PIPE_ID_YUVPP; + + atomisp_q_video_buffers_to_css(asd, video_pipe, + input_stream_id, + buf_type, css_video_pipe_id); + } + + return 0; +} + +static void atomisp_buf_queue(struct videobuf_queue *vq, + struct videobuf_buffer *vb) +{ + struct atomisp_video_pipe *pipe = vq->priv_data; + + /* + * when a frame buffer meets following conditions, it should be put into + * the waiting list: + * 1. It is not a main output frame, and it has a per-frame parameter + * to go with it. + * 2. It is not a main output frame, and the waiting buffer list is not + * empty, to keep the FIFO sequence of frame buffer processing, it + * is put to waiting list until previous per-frame parameter buffers + * get enqueued. + */ + if (!atomisp_is_vf_pipe(pipe) && + (pipe->frame_request_config_id[vb->i] || + !list_empty(&pipe->buffers_waiting_for_param))) + list_add_tail(&vb->queue, &pipe->buffers_waiting_for_param); + else + list_add_tail(&vb->queue, &pipe->activeq); + + vb->state = VIDEOBUF_QUEUED; +} + +static void atomisp_buf_release(struct videobuf_queue *vq, + struct videobuf_buffer *vb) +{ + vb->state = VIDEOBUF_NEEDS_INIT; + atomisp_videobuf_free_buf(vb); +} + +static int atomisp_buf_setup_output(struct videobuf_queue *vq, + unsigned int *count, unsigned int *size) +{ + struct atomisp_video_pipe *pipe = vq->priv_data; + + *size = pipe->pix.sizeimage; + + return 0; +} + +static int atomisp_buf_prepare_output(struct videobuf_queue *vq, + struct videobuf_buffer *vb, + enum v4l2_field field) +{ + struct atomisp_video_pipe *pipe = vq->priv_data; + + vb->size = pipe->pix.sizeimage; + vb->width = pipe->pix.width; + vb->height = pipe->pix.height; + vb->field = field; + vb->state = VIDEOBUF_PREPARED; + + return 0; +} + +static void atomisp_buf_queue_output(struct videobuf_queue *vq, + struct videobuf_buffer *vb) +{ + struct atomisp_video_pipe *pipe = vq->priv_data; + + list_add_tail(&vb->queue, &pipe->activeq_out); + vb->state = VIDEOBUF_QUEUED; +} + +static void atomisp_buf_release_output(struct videobuf_queue *vq, + struct videobuf_buffer *vb) +{ + videobuf_vmalloc_free(vb); + vb->state = VIDEOBUF_NEEDS_INIT; +} + +static struct videobuf_queue_ops videobuf_qops = { + .buf_setup = atomisp_buf_setup, + .buf_prepare = atomisp_buf_prepare, + .buf_queue = atomisp_buf_queue, + .buf_release = atomisp_buf_release, +}; + +static struct videobuf_queue_ops videobuf_qops_output = { + .buf_setup = atomisp_buf_setup_output, + .buf_prepare = atomisp_buf_prepare_output, + .buf_queue = atomisp_buf_queue_output, + .buf_release = atomisp_buf_release_output, +}; + +static int atomisp_init_pipe(struct atomisp_video_pipe *pipe) +{ + /* init locks */ + spin_lock_init(&pipe->irq_lock); + + videobuf_queue_vmalloc_init(&pipe->capq, &videobuf_qops, NULL, + &pipe->irq_lock, + V4L2_BUF_TYPE_VIDEO_CAPTURE, + V4L2_FIELD_NONE, + sizeof(struct atomisp_buffer), pipe, + NULL); /* ext_lock: NULL */ + + videobuf_queue_vmalloc_init(&pipe->outq, &videobuf_qops_output, NULL, + &pipe->irq_lock, + V4L2_BUF_TYPE_VIDEO_OUTPUT, + V4L2_FIELD_NONE, + sizeof(struct atomisp_buffer), pipe, + NULL); /* ext_lock: NULL */ + + INIT_LIST_HEAD(&pipe->activeq); + INIT_LIST_HEAD(&pipe->activeq_out); + INIT_LIST_HEAD(&pipe->buffers_waiting_for_param); + INIT_LIST_HEAD(&pipe->per_frame_params); + memset(pipe->frame_request_config_id, 0, + VIDEO_MAX_FRAME * sizeof(unsigned int)); + memset(pipe->frame_params, 0, + VIDEO_MAX_FRAME * + sizeof(struct atomisp_css_params_with_list *)); + + return 0; +} + +static void atomisp_dev_init_struct(struct atomisp_device *isp) +{ + unsigned int i; + + isp->sw_contex.file_input = 0; + isp->need_gfx_throttle = true; + isp->isp_fatal_error = false; + isp->mipi_frame_size = 0; + + for (i = 0; i < isp->input_cnt; i++) + isp->inputs[i].asd = NULL; + /* + * For Merrifield, frequency is scalable. + * After boot-up, the default frequency is 200MHz. + */ + isp->sw_contex.running_freq = ISP_FREQ_200MHZ; +} + +static void atomisp_subdev_init_struct(struct atomisp_sub_device *asd) +{ + v4l2_ctrl_s_ctrl(asd->run_mode, ATOMISP_RUN_MODE_STILL_CAPTURE); + memset(&asd->params.css_param, 0, sizeof(asd->params.css_param)); + asd->params.color_effect = V4L2_COLORFX_NONE; + asd->params.bad_pixel_en = 1; + asd->params.gdc_cac_en = 0; + asd->params.video_dis_en = 0; + asd->params.sc_en = 0; + asd->params.fpn_en = 0; + asd->params.xnr_en = 0; + asd->params.false_color = 0; + asd->params.online_process = 1; + asd->params.yuv_ds_en = 0; + /* s3a grid not enabled for any pipe */ + asd->params.s3a_enabled_pipe = CSS_PIPE_ID_NUM; + + asd->params.offline_parm.num_captures = 1; + asd->params.offline_parm.skip_frames = 0; + asd->params.offline_parm.offset = 0; + asd->delayed_init = ATOMISP_DELAYED_INIT_NOT_QUEUED; + /* Add for channel */ + asd->input_curr = 0; + + asd->mipi_frame_size = 0; + asd->copy_mode = false; + asd->yuvpp_mode = false; + + asd->stream_prepared = false; + asd->high_speed_mode = false; + asd->sensor_array_res.height = 0; + asd->sensor_array_res.width = 0; + atomisp_css_init_struct(asd); +} +/* + * file operation functions + */ +unsigned int atomisp_subdev_users(struct atomisp_sub_device *asd) +{ + return asd->video_out_preview.users + + asd->video_out_vf.users + + asd->video_out_capture.users + + asd->video_out_video_capture.users + + asd->video_acc.users + + asd->video_in.users; +} + +unsigned int atomisp_dev_users(struct atomisp_device *isp) +{ + unsigned int i, sum; + for (i = 0, sum = 0; i < isp->num_of_streams; i++) + sum += atomisp_subdev_users(&isp->asd[i]); + + return sum; +} + +static int atomisp_open(struct file *file) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_video_pipe *pipe = NULL; + struct atomisp_acc_pipe *acc_pipe = NULL; + struct atomisp_sub_device *asd; + bool acc_node = false; + int ret; + + dev_dbg(isp->dev, "open device %s\n", vdev->name); + + rt_mutex_lock(&isp->mutex); + + acc_node = !strncmp(vdev->name, "ATOMISP ISP ACC", + sizeof(vdev->name)); + if (acc_node) { + acc_pipe = atomisp_to_acc_pipe(vdev); + asd = acc_pipe->asd; + } else { + pipe = atomisp_to_video_pipe(vdev); + asd = pipe->asd; + } + asd->subdev.devnode = vdev; + /* Deferred firmware loading case. */ + if (isp->css_env.isp_css_fw.bytes == 0) { + isp->firmware = atomisp_load_firmware(isp); + if (!isp->firmware) { + dev_err(isp->dev, "Failed to load ISP firmware.\n"); + ret = -ENOENT; + goto error; + } + ret = atomisp_css_load_firmware(isp); + if (ret) { + dev_err(isp->dev, "Failed to init css.\n"); + goto error; + } + /* No need to keep FW in memory anymore. */ + release_firmware(isp->firmware); + isp->firmware = NULL; + isp->css_env.isp_css_fw.data = NULL; + } + + if (acc_node && acc_pipe->users) { + dev_dbg(isp->dev, "acc node already opened\n"); + rt_mutex_unlock(&isp->mutex); + return -EBUSY; + } else if (acc_node) { + goto dev_init; + } + + if (!isp->input_cnt) { + dev_err(isp->dev, "no camera attached\n"); + ret = -EINVAL; + goto error; + } + + /* + * atomisp does not allow multiple open + */ + if (pipe->users) { + dev_dbg(isp->dev, "video node already opened\n"); + rt_mutex_unlock(&isp->mutex); + return -EBUSY; + } + + ret = atomisp_init_pipe(pipe); + if (ret) + goto error; + +dev_init: + if (atomisp_dev_users(isp)) { + dev_dbg(isp->dev, "skip init isp in open\n"); + goto init_subdev; + } + + /* runtime power management, turn on ISP */ + ret = pm_runtime_get_sync(vdev->v4l2_dev->dev); + if (ret < 0) { + dev_err(isp->dev, "Failed to power on device\n"); + goto error; + } + + if (dypool_enable) { + ret = hmm_pool_register(dypool_pgnr, HMM_POOL_TYPE_DYNAMIC); + if (ret) + dev_err(isp->dev, "Failed to register dynamic memory pool.\n"); + } + + /* Init ISP */ + if (atomisp_css_init(isp)) { + ret = -EINVAL; + /* Need to clean up CSS init if it fails. */ + goto css_error; + } + + atomisp_dev_init_struct(isp); + + ret = v4l2_subdev_call(isp->flash, core, s_power, 1); + if (ret < 0 && ret != -ENODEV && ret != -ENOIOCTLCMD) { + dev_err(isp->dev, "Failed to power-on flash\n"); + goto css_error; + } + +init_subdev: + if (atomisp_subdev_users(asd)) + goto done; + + atomisp_subdev_init_struct(asd); + +done: + + if (acc_node) + acc_pipe->users++; + else + pipe->users++; + rt_mutex_unlock(&isp->mutex); + return 0; + +css_error: + atomisp_css_uninit(isp); +error: + hmm_pool_unregister(HMM_POOL_TYPE_DYNAMIC); + pm_runtime_put(vdev->v4l2_dev->dev); + rt_mutex_unlock(&isp->mutex); + return ret; +} + +static int atomisp_release(struct file *file) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_video_pipe *pipe; + struct atomisp_acc_pipe *acc_pipe; + struct atomisp_sub_device *asd; + bool acc_node; + struct v4l2_requestbuffers req; + struct v4l2_subdev_fh fh; + struct v4l2_rect clear_compose = {0}; + int ret = 0; + + v4l2_fh_init(&fh.vfh, vdev); + + req.count = 0; + if (isp == NULL) + return -EBADF; + + mutex_lock(&isp->streamoff_mutex); + rt_mutex_lock(&isp->mutex); + + dev_dbg(isp->dev, "release device %s\n", vdev->name); + acc_node = !strncmp(vdev->name, "ATOMISP ISP ACC", + sizeof(vdev->name)); + if (acc_node) { + acc_pipe = atomisp_to_acc_pipe(vdev); + asd = acc_pipe->asd; + } else { + pipe = atomisp_to_video_pipe(vdev); + asd = pipe->asd; + } + asd->subdev.devnode = vdev; + if (acc_node) { + acc_pipe->users--; + goto subdev_uninit; + } + pipe->users--; + + if (pipe->capq.streaming) + dev_warn(isp->dev, + "%s: ISP still streaming while closing!", + __func__); + + if (pipe->capq.streaming && + __atomisp_streamoff(file, NULL, V4L2_BUF_TYPE_VIDEO_CAPTURE)) { + dev_err(isp->dev, + "atomisp_streamoff failed on release, driver bug"); + goto done; + } + + if (pipe->users) + goto done; + + if (__atomisp_reqbufs(file, NULL, &req)) { + dev_err(isp->dev, + "atomisp_reqbufs failed on release, driver bug"); + goto done; + } + + if (pipe->outq.bufs[0]) { + mutex_lock(&pipe->outq.vb_lock); + videobuf_queue_cancel(&pipe->outq); + mutex_unlock(&pipe->outq.vb_lock); + } + + /* + * A little trick here: + * file injection input resolution is recorded in the sink pad, + * therefore can not be cleared when releaseing one device node. + * The sink pad setting can only be cleared when all device nodes + * get released. + */ + if (!isp->sw_contex.file_input && asd->fmt_auto->val) { + struct v4l2_mbus_framefmt isp_sink_fmt = { 0 }; + atomisp_subdev_set_ffmt(&asd->subdev, fh.pad, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK, &isp_sink_fmt); + } +subdev_uninit: + if (atomisp_subdev_users(asd)) + goto done; + + /* clear the sink pad for file input */ + if (isp->sw_contex.file_input && asd->fmt_auto->val) { + struct v4l2_mbus_framefmt isp_sink_fmt = { 0 }; + atomisp_subdev_set_ffmt(&asd->subdev, fh.pad, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK, &isp_sink_fmt); + } + + atomisp_css_free_stat_buffers(asd); + atomisp_free_internal_buffers(asd); + ret = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + core, s_power, 0); + if (ret) + dev_warn(isp->dev, "Failed to power-off sensor\n"); + + /* clear the asd field to show this camera is not used */ + isp->inputs[asd->input_curr].asd = NULL; + asd->streaming = ATOMISP_DEVICE_STREAMING_DISABLED; + + if (atomisp_dev_users(isp)) + goto done; + + atomisp_acc_release(asd); + + atomisp_destroy_pipes_stream_force(asd); + atomisp_css_uninit(isp); + + if (defer_fw_load) { + atomisp_css_unload_firmware(isp); + isp->css_env.isp_css_fw.data = NULL; + isp->css_env.isp_css_fw.bytes = 0; + } + + hmm_pool_unregister(HMM_POOL_TYPE_DYNAMIC); + + ret = v4l2_subdev_call(isp->flash, core, s_power, 0); + if (ret < 0 && ret != -ENODEV && ret != -ENOIOCTLCMD) + dev_warn(isp->dev, "Failed to power-off flash\n"); + + if (pm_runtime_put_sync(vdev->v4l2_dev->dev) < 0) + dev_err(isp->dev, "Failed to power off device\n"); + +done: + if (!acc_node) { + atomisp_subdev_set_selection(&asd->subdev, fh.pad, + V4L2_SUBDEV_FORMAT_ACTIVE, + atomisp_subdev_source_pad(vdev), + V4L2_SEL_TGT_COMPOSE, 0, + &clear_compose); + } + rt_mutex_unlock(&isp->mutex); + mutex_unlock(&isp->streamoff_mutex); + + return 0; +} + +/* + * Memory help functions for image frame and private parameters + */ +static int do_isp_mm_remap(struct atomisp_device *isp, + struct vm_area_struct *vma, + ia_css_ptr isp_virt, u32 host_virt, u32 pgnr) +{ + u32 pfn; + + while (pgnr) { + pfn = hmm_virt_to_phys(isp_virt) >> PAGE_SHIFT; + if (remap_pfn_range(vma, host_virt, pfn, + PAGE_SIZE, PAGE_SHARED)) { + dev_err(isp->dev, "remap_pfn_range err.\n"); + return -EAGAIN; + } + + isp_virt += PAGE_SIZE; + host_virt += PAGE_SIZE; + pgnr--; + } + + return 0; +} + +static int frame_mmap(struct atomisp_device *isp, + const struct atomisp_css_frame *frame, struct vm_area_struct *vma) +{ + ia_css_ptr isp_virt; + u32 host_virt; + u32 pgnr; + + if (!frame) { + dev_err(isp->dev, "%s: NULL frame pointer.\n", __func__); + return -EINVAL; + } + + host_virt = vma->vm_start; + isp_virt = frame->data; + atomisp_get_frame_pgnr(isp, frame, &pgnr); + + if (do_isp_mm_remap(isp, vma, isp_virt, host_virt, pgnr)) + return -EAGAIN; + + return 0; +} + +int atomisp_videobuf_mmap_mapper(struct videobuf_queue *q, + struct vm_area_struct *vma) +{ + u32 offset = vma->vm_pgoff << PAGE_SHIFT; + int ret = -EINVAL, i; + struct atomisp_device *isp = + ((struct atomisp_video_pipe *)(q->priv_data))->isp; + struct videobuf_vmalloc_memory *vm_mem; + struct videobuf_mapping *map; + + MAGIC_CHECK(q->int_ops->magic, MAGIC_QTYPE_OPS); + if (!(vma->vm_flags & VM_WRITE) || !(vma->vm_flags & VM_SHARED)) { + dev_err(isp->dev, "map appl bug: PROT_WRITE and MAP_SHARED are required\n"); + return -EINVAL; + } + + mutex_lock(&q->vb_lock); + for (i = 0; i < VIDEO_MAX_FRAME; i++) { + struct videobuf_buffer *buf = q->bufs[i]; + if (buf == NULL) + continue; + + map = kzalloc(sizeof(struct videobuf_mapping), GFP_KERNEL); + if (map == NULL) { + mutex_unlock(&q->vb_lock); + return -ENOMEM; + } + + buf->map = map; + map->q = q; + + buf->baddr = vma->vm_start; + + if (buf && buf->memory == V4L2_MEMORY_MMAP && + buf->boff == offset) { + vm_mem = buf->priv; + ret = frame_mmap(isp, vm_mem->vaddr, vma); + vma->vm_flags |= VM_IO|VM_DONTEXPAND|VM_DONTDUMP; + break; + } + } + mutex_unlock(&q->vb_lock); + + return ret; +} + +/* The input frame contains left and right padding that need to be removed. + * There is always ISP_LEFT_PAD padding on the left side. + * There is also padding on the right (padded_width - width). + */ +static int remove_pad_from_frame(struct atomisp_device *isp, + struct atomisp_css_frame *in_frame, __u32 width, __u32 height) +{ + unsigned int i; + unsigned short *buffer; + int ret = 0; + ia_css_ptr load = in_frame->data; + ia_css_ptr store = load; + + buffer = kmalloc(width*sizeof(load), GFP_KERNEL); + if (!buffer) { + dev_err(isp->dev, "out of memory.\n"); + return -ENOMEM; + } + + load += ISP_LEFT_PAD; + for (i = 0; i < height; i++) { + ret = hrt_isp_css_mm_load(load, buffer, width*sizeof(load)); + if (ret < 0) + goto remove_pad_error; + + ret = hrt_isp_css_mm_store(store, buffer, width*sizeof(store)); + if (ret < 0) + goto remove_pad_error; + + load += in_frame->info.padded_width; + store += width; + } + +remove_pad_error: + kfree(buffer); + return ret; +} + +static int atomisp_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + struct atomisp_sub_device *asd = pipe->asd; + struct atomisp_css_frame *raw_virt_addr; + u32 start = vma->vm_start; + u32 end = vma->vm_end; + u32 size = end - start; + u32 origin_size, new_size; + int ret; + + if (!(vma->vm_flags & (VM_WRITE | VM_READ))) + return -EACCES; + + rt_mutex_lock(&isp->mutex); + + if (!(vma->vm_flags & VM_SHARED)) { + /* Map private buffer. + * Set VM_SHARED to the flags since we need + * to map the buffer page by page. + * Without VM_SHARED, remap_pfn_range() treats + * this kind of mapping as invalid. + */ + vma->vm_flags |= VM_SHARED; + ret = hmm_mmap(vma, vma->vm_pgoff << PAGE_SHIFT); + rt_mutex_unlock(&isp->mutex); + return ret; + } + + /* mmap for ISP offline raw data */ + if (atomisp_subdev_source_pad(vdev) + == ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE && + vma->vm_pgoff == (ISP_PARAM_MMAP_OFFSET >> PAGE_SHIFT)) { + new_size = pipe->pix.width * pipe->pix.height * 2; + if (asd->params.online_process != 0) { + ret = -EINVAL; + goto error; + } + raw_virt_addr = asd->raw_output_frame; + if (raw_virt_addr == NULL) { + dev_err(isp->dev, "Failed to request RAW frame\n"); + ret = -EINVAL; + goto error; + } + + ret = remove_pad_from_frame(isp, raw_virt_addr, + pipe->pix.width, pipe->pix.height); + if (ret < 0) { + dev_err(isp->dev, "remove pad failed.\n"); + goto error; + } + origin_size = raw_virt_addr->data_bytes; + raw_virt_addr->data_bytes = new_size; + + if (size != PAGE_ALIGN(new_size)) { + dev_err(isp->dev, "incorrect size for mmap ISP Raw Frame\n"); + ret = -EINVAL; + goto error; + } + + if (frame_mmap(isp, raw_virt_addr, vma)) { + dev_err(isp->dev, "frame_mmap failed.\n"); + raw_virt_addr->data_bytes = origin_size; + ret = -EAGAIN; + goto error; + } + raw_virt_addr->data_bytes = origin_size; + vma->vm_flags |= VM_IO|VM_DONTEXPAND|VM_DONTDUMP; + rt_mutex_unlock(&isp->mutex); + return 0; + } + + /* + * mmap for normal frames + */ + if (size != pipe->pix.sizeimage) { + dev_err(isp->dev, "incorrect size for mmap ISP frames\n"); + ret = -EINVAL; + goto error; + } + rt_mutex_unlock(&isp->mutex); + + return atomisp_videobuf_mmap_mapper(&pipe->capq, vma); + +error: + rt_mutex_unlock(&isp->mutex); + + return ret; +} + +static int atomisp_file_mmap(struct file *file, struct vm_area_struct *vma) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + + return videobuf_mmap_mapper(&pipe->outq, vma); +} + +static unsigned int atomisp_poll(struct file *file, + struct poll_table_struct *pt) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + + rt_mutex_lock(&isp->mutex); + if (pipe->capq.streaming != 1) { + rt_mutex_unlock(&isp->mutex); + return POLLERR; + } + rt_mutex_unlock(&isp->mutex); + + return videobuf_poll_stream(file, &pipe->capq, pt); +} + +const struct v4l2_file_operations atomisp_fops = { + .owner = THIS_MODULE, + .open = atomisp_open, + .release = atomisp_release, + .mmap = atomisp_mmap, + .unlocked_ioctl = video_ioctl2, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = atomisp_compat_ioctl32, +#endif + .poll = atomisp_poll, +}; + +const struct v4l2_file_operations atomisp_file_fops = { + .owner = THIS_MODULE, + .open = atomisp_open, + .release = atomisp_release, + .mmap = atomisp_file_mmap, + .unlocked_ioctl = video_ioctl2, +#ifdef CONFIG_COMPAT + .compat_ioctl32 = atomisp_compat_ioctl32, +#endif + .poll = atomisp_poll, +}; + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_fops.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_fops.h new file mode 100644 index 0000000000000000000000000000000000000000..8471e391501a10f573f6b46779f72fdbb8aa501b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_fops.h @@ -0,0 +1,54 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __ATOMISP_FOPS_H__ +#define __ATOMISP_FOPS_H__ +#include "atomisp_subdev.h" + +int atomisp_q_video_buffers_to_css(struct atomisp_sub_device *asd, + struct atomisp_video_pipe *pipe, + enum atomisp_input_stream_id stream_id, + enum atomisp_css_buffer_type css_buf_type, + enum atomisp_css_pipe_id css_pipe_id); + +unsigned int atomisp_dev_users(struct atomisp_device *isp); +unsigned int atomisp_sub_dev_users(struct atomisp_sub_device *asd); + +/* + * Memory help functions for image frame and private parameters + */ + +int atomisp_videobuf_mmap_mapper(struct videobuf_queue *q, + struct vm_area_struct *vma); + +int atomisp_qbuf_to_css(struct atomisp_device *isp, + struct atomisp_video_pipe *pipe, + struct videobuf_buffer *vb); + +int atomisp_qbuffers_to_css(struct atomisp_sub_device *asd); + +extern const struct v4l2_file_operations atomisp_fops; + +extern bool defer_fw_load; + +#endif /* __ATOMISP_FOPS_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_helper.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_helper.h new file mode 100644 index 0000000000000000000000000000000000000000..e9650cb75ba5f17dcbbda5ea9e32dc2c40d3f2d6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_helper.h @@ -0,0 +1,33 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#ifndef _atomisp_helper_h_ +#define _atomisp_helper_h_ +extern void __iomem *atomisp_io_base; + +static inline void __iomem *atomisp_get_io_virt_addr(unsigned int address) +{ + void __iomem *ret = atomisp_io_base + (address & 0x003FFFFF); + return ret; +} +#endif + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_internal.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_internal.h new file mode 100644 index 0000000000000000000000000000000000000000..a21f793860263b7c8df3f020397b6a01839439ed --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_internal.h @@ -0,0 +1,331 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#ifndef __ATOMISP_INTERNAL_H__ +#define __ATOMISP_INTERNAL_H__ + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +#ifndef ISP2401 +#include "ia_css_types.h" +#include "sh_css_legacy.h" +#else +/*#include "ia_css_types.h"*/ +/*#include "sh_css_legacy.h"*/ +#endif + +#include "atomisp_csi2.h" +#include "atomisp_file.h" +#include "atomisp_subdev.h" +#include "atomisp_tpg.h" +#include "atomisp_compat.h" + +#include "gp_device.h" +#include "irq.h" +#include + +#define V4L2_EVENT_FRAME_END 5 + +#define IS_HWREVISION(isp, rev) \ + (((isp)->media_dev.hw_revision & ATOMISP_HW_REVISION_MASK) == \ + ((rev) << ATOMISP_HW_REVISION_SHIFT)) + +#define MAX_STREAM_NUM 2 + +#define ATOMISP_PCI_DEVICE_SOC_MASK 0xfff8 +/* MRFLD with 0x1178: ISP freq can burst to 457MHz */ +#define ATOMISP_PCI_DEVICE_SOC_MRFLD 0x1178 +/* MRFLD with 0x1179: max ISP freq limited to 400MHz */ +#define ATOMISP_PCI_DEVICE_SOC_MRFLD_1179 0x1179 +/* MRFLD with 0x117a: max ISP freq is 400MHz and max freq at Vmin is 200MHz */ +#define ATOMISP_PCI_DEVICE_SOC_MRFLD_117A 0x117a +#define ATOMISP_PCI_DEVICE_SOC_BYT 0x0f38 +#define ATOMISP_PCI_DEVICE_SOC_ANN 0x1478 +#define ATOMISP_PCI_DEVICE_SOC_CHT 0x22b8 + +#define ATOMISP_PCI_REV_MRFLD_A0_MAX 0 +#define ATOMISP_PCI_REV_BYT_A0_MAX 4 + +#define ATOMISP_MAJOR 0 +#define ATOMISP_MINOR 5 +#define ATOMISP_PATCHLEVEL 1 + +#define DRIVER_VERSION_STR __stringify(ATOMISP_MAJOR) \ + "." __stringify(ATOMISP_MINOR) "." __stringify(ATOMISP_PATCHLEVEL) +#define DRIVER_VERSION KERNEL_VERSION(ATOMISP_MAJOR, \ + ATOMISP_MINOR, ATOMISP_PATCHLEVEL) + +#define ATOM_ISP_STEP_WIDTH 2 +#define ATOM_ISP_STEP_HEIGHT 2 + +#define ATOM_ISP_MIN_WIDTH 4 +#define ATOM_ISP_MIN_HEIGHT 4 +#define ATOM_ISP_MAX_WIDTH UINT_MAX +#define ATOM_ISP_MAX_HEIGHT UINT_MAX + +/* sub-QCIF resolution */ +#define ATOM_RESOLUTION_SUBQCIF_WIDTH 128 +#define ATOM_RESOLUTION_SUBQCIF_HEIGHT 96 + +#define ATOM_ISP_MAX_WIDTH_TMP 1280 +#define ATOM_ISP_MAX_HEIGHT_TMP 720 + +#define ATOM_ISP_I2C_BUS_1 4 +#define ATOM_ISP_I2C_BUS_2 5 + +#define ATOM_ISP_POWER_DOWN 0 +#define ATOM_ISP_POWER_UP 1 + +#define ATOM_ISP_MAX_INPUTS 4 + +#define ATOMISP_SC_TYPE_SIZE 2 + +#define ATOMISP_ISP_TIMEOUT_DURATION (2 * HZ) +#define ATOMISP_EXT_ISP_TIMEOUT_DURATION (6 * HZ) +#define ATOMISP_ISP_FILE_TIMEOUT_DURATION (60 * HZ) +#define ATOMISP_WDT_KEEP_CURRENT_DELAY 0 +#define ATOMISP_ISP_MAX_TIMEOUT_COUNT 2 +#define ATOMISP_CSS_STOP_TIMEOUT_US 200000 + +#define ATOMISP_CSS_Q_DEPTH 3 +#define ATOMISP_CSS_EVENTS_MAX 16 +#define ATOMISP_CONT_RAW_FRAMES 15 +#define ATOMISP_METADATA_QUEUE_DEPTH_FOR_HAL 8 +#define ATOMISP_S3A_BUF_QUEUE_DEPTH_FOR_HAL 8 + +#define ATOMISP_DELAYED_INIT_NOT_QUEUED 0 +#define ATOMISP_DELAYED_INIT_QUEUED 1 +#define ATOMISP_DELAYED_INIT_DONE 2 + +#define ATOMISP_CALC_CSS_PREV_OVERLAP(lines) \ + ((lines) * 38 / 100 & 0xfffffe) + +/* + * Define how fast CPU should be able to serve ISP interrupts. + * The bigger the value, the higher risk that the ISP is not + * triggered sufficiently fast for it to process image during + * vertical blanking time, increasing risk of dropped frames. + * 1000 us is a reasonable value considering that the processing + * time is typically ~2000 us. + */ +#define ATOMISP_MAX_ISR_LATENCY 1000 + +/* Add new YUVPP pipe for SOC sensor. */ +#define ATOMISP_CSS_SUPPORT_YUVPP 1 + +#define ATOMISP_CSS_OUTPUT_SECOND_INDEX 1 +#define ATOMISP_CSS_OUTPUT_DEFAULT_INDEX 0 + +/* + * ATOMISP_SOC_CAMERA + * This is to differentiate between ext-isp and soc camera in + * Moorefield/Baytrail platform. + */ +#define ATOMISP_SOC_CAMERA(asd) \ + (asd->isp->inputs[asd->input_curr].type == SOC_CAMERA \ + && asd->isp->inputs[asd->input_curr].camera_caps-> \ + sensor[asd->sensor_curr].stream_num == 1) + +#define ATOMISP_USE_YUVPP(asd) \ + (ATOMISP_SOC_CAMERA(asd) && ATOMISP_CSS_SUPPORT_YUVPP && \ + !asd->copy_mode) + +#define ATOMISP_DEPTH_SENSOR_STREAMON_COUNT 2 + +#define ATOMISP_DEPTH_DEFAULT_MASTER_SENSOR 0 +#define ATOMISP_DEPTH_DEFAULT_SLAVE_SENSOR 1 + +#ifdef ISP2401 +#define ATOMISP_ION_DEVICE_FD_OFFSET 16 +#define ATOMISP_ION_SHARED_FD_MASK (0xFFFF) +#define ATOMISP_ION_DEVICE_FD_MASK (~ATOMISP_ION_SHARED_FD_MASK) +#define ION_FD_UNSET (-1) + +#endif +#define DIV_NEAREST_STEP(n, d, step) \ + round_down((2 * (n) + (d) * (step))/(2 * (d)), (step)) + +struct atomisp_input_subdev { + unsigned int type; + enum atomisp_camera_port port; + struct v4l2_subdev *camera; + struct v4l2_subdev *motor; + struct v4l2_frmsizeenum frame_size; + + /* + * To show this resource is used by + * which stream, in ISP multiple stream mode + */ + struct atomisp_sub_device *asd; + + const struct atomisp_camera_caps *camera_caps; + int sensor_index; +}; + +enum atomisp_dfs_mode { + ATOMISP_DFS_MODE_AUTO = 0, + ATOMISP_DFS_MODE_LOW, + ATOMISP_DFS_MODE_MAX, +}; + +struct atomisp_regs { + /* PCI config space info */ + u16 pcicmdsts; + u32 ispmmadr; + u32 msicap; + u32 msi_addr; + u16 msi_data; + u8 intr; + u32 interrupt_control; + u32 pmcs; + u32 cg_dis; + u32 i_control; + + /* I-Unit PHY related info */ + u32 csi_rcomp_config; + u32 csi_afe_dly; + u32 csi_control; + + /* New for MRFLD */ + u32 csi_afe_rcomp_config; + u32 csi_afe_hs_control; + u32 csi_deadline_control; + u32 csi_access_viol; +}; + +struct atomisp_sw_contex { + bool file_input; + int power_state; + int running_freq; +}; + + +#define ATOMISP_DEVICE_STREAMING_DISABLED 0 +#define ATOMISP_DEVICE_STREAMING_ENABLED 1 +#define ATOMISP_DEVICE_STREAMING_STOPPING 2 + +/* + * ci device struct + */ +struct atomisp_device { + struct pci_dev *pdev; + struct device *dev; + struct v4l2_device v4l2_dev; + struct media_device media_dev; + struct atomisp_platform_data *pdata; + void *mmu_l1_base; + struct pci_dev *pci_root; + const struct firmware *firmware; + + struct pm_qos_request pm_qos; + s32 max_isr_latency; + + /* + * ISP modules + * Multiple streams are represents by multiple + * atomisp_sub_device instances + */ + struct atomisp_sub_device *asd; + /* + * this will be assiged dyanamically. + * For Merr/BTY(ISP2400), 2 streams are supported. + */ + unsigned int num_of_streams; + + struct atomisp_mipi_csi2_device csi2_port[ATOMISP_CAMERA_NR_PORTS]; + struct atomisp_tpg_device tpg; + struct atomisp_file_device file_dev; + + /* Purpose of mutex is to protect and serialize use of isp data + * structures and css API calls. */ + struct rt_mutex mutex; + /* + * Serialise streamoff: mutex is dropped during streamoff to + * cancel the watchdog queue. MUST be acquired BEFORE + * "mutex". + */ + struct mutex streamoff_mutex; + + int input_cnt; + struct atomisp_input_subdev inputs[ATOM_ISP_MAX_INPUTS]; + struct v4l2_subdev *flash; + struct v4l2_subdev *motor; + + struct atomisp_regs saved_regs; + struct atomisp_sw_contex sw_contex; + struct atomisp_css_env css_env; + + /* isp timeout status flag */ + bool isp_timeout; + bool isp_fatal_error; + struct workqueue_struct *wdt_work_queue; + struct work_struct wdt_work; +#ifndef ISP2401 + atomic_t wdt_count; +#endif + atomic_t wdt_work_queued; + + spinlock_t lock; /* Just for streaming below */ + + bool need_gfx_throttle; + + unsigned int mipi_frame_size; + const struct atomisp_dfs_config *dfs; + unsigned int hpll_freq; + + bool css_initialized; +}; + +#define v4l2_dev_to_atomisp_device(dev) \ + container_of(dev, struct atomisp_device, v4l2_dev) + +extern struct device *atomisp_dev; + +extern void *atomisp_kernel_malloc(size_t bytes); + +extern void atomisp_kernel_free(void *ptr); + +#define atomisp_is_wdt_running(a) timer_pending(&(a)->wdt) +#ifdef ISP2401 +extern void atomisp_wdt_refresh_pipe(struct atomisp_video_pipe *pipe, + unsigned int delay); +#endif +extern void atomisp_wdt_refresh(struct atomisp_sub_device *asd, unsigned int delay); +#ifndef ISP2401 +extern void atomisp_wdt_start(struct atomisp_sub_device *asd); +#else +extern void atomisp_wdt_start(struct atomisp_video_pipe *pipe); +extern void atomisp_wdt_stop_pipe(struct atomisp_video_pipe *pipe, bool sync); +#endif +extern void atomisp_wdt_stop(struct atomisp_sub_device *asd, bool sync); + +#endif /* __ATOMISP_INTERNAL_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_ioctl.c b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_ioctl.c new file mode 100644 index 0000000000000000000000000000000000000000..0a0652a16a585e694df867f4a040589526292a3a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_ioctl.c @@ -0,0 +1,3151 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include + +#include + +#include +#include +#include + +#include "atomisp_acc.h" +#include "atomisp_cmd.h" +#include "atomisp_common.h" +#include "atomisp_fops.h" +#include "atomisp_internal.h" +#include "atomisp_ioctl.h" +#include "atomisp-regs.h" +#include "atomisp_compat.h" + +#include "sh_css_hrt.h" + +#include "gp_device.h" +#include "device_access.h" +#include "irq.h" + +#include "hrt/hive_isp_css_mm_hrt.h" + +/* for v4l2_capability */ +static const char *DRIVER = "atomisp"; /* max size 15 */ +static const char *CARD = "ATOM ISP"; /* max size 31 */ +static const char *BUS_INFO = "PCI-3"; /* max size 31 */ +static const u32 VERSION = DRIVER_VERSION; + +/* + * FIXME: ISP should not know beforehand all CIDs supported by sensor. + * Instead, it needs to propagate to sensor unkonwn CIDs. + */ +static struct v4l2_queryctrl ci_v4l2_controls[] = { + { + .id = V4L2_CID_AUTO_WHITE_BALANCE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Automatic White Balance", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_RED_BALANCE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Red Balance", + .minimum = 0x00, + .maximum = 0xff, + .step = 1, + .default_value = 0x00, + }, + { + .id = V4L2_CID_BLUE_BALANCE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Blue Balance", + .minimum = 0x00, + .maximum = 0xff, + .step = 1, + .default_value = 0x00, + }, + { + .id = V4L2_CID_GAMMA, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Gamma", + .minimum = 0x00, + .maximum = 0xff, + .step = 1, + .default_value = 0x00, + }, + { + .id = V4L2_CID_POWER_LINE_FREQUENCY, + .type = V4L2_CTRL_TYPE_MENU, + .name = "Light frequency filter", + .minimum = 1, + .maximum = 2, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_COLORFX, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Image Color Effect", + .minimum = 0, + .maximum = 9, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_COLORFX_CBCR, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Image Color Effect CbCr", + .minimum = 0, + .maximum = 0xffff, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_ATOMISP_BAD_PIXEL_DETECTION, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Bad Pixel Correction", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_ATOMISP_POSTPROCESS_GDC_CAC, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "GDC/CAC", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_ATOMISP_VIDEO_STABLIZATION, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Video Stablization", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_ATOMISP_FIXED_PATTERN_NR, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Fixed Pattern Noise Reduction", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_ATOMISP_FALSE_COLOR_CORRECTION, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "False Color Correction", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_REQUEST_FLASH, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Request flash frames", + .minimum = 0, + .maximum = 10, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_ATOMISP_LOW_LIGHT, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Low light mode", + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_BIN_FACTOR_HORZ, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Horizontal binning factor", + .minimum = 0, + .maximum = 10, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_BIN_FACTOR_VERT, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Vertical binning factor", + .minimum = 0, + .maximum = 10, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_2A_STATUS, + .type = V4L2_CTRL_TYPE_BITMASK, + .name = "AE and AWB status", + .minimum = 0, + .maximum = V4L2_2A_STATUS_AE_READY | V4L2_2A_STATUS_AWB_READY, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_EXPOSURE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "exposure", + .minimum = -4, + .maximum = 4, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_EXPOSURE_ZONE_NUM, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "one-time exposure zone number", + .minimum = 0x0, + .maximum = 0xffff, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_EXPOSURE_AUTO_PRIORITY, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Exposure auto priority", + .minimum = V4L2_EXPOSURE_AUTO, + .maximum = V4L2_EXPOSURE_APERTURE_PRIORITY, + .step = 1, + .default_value = V4L2_EXPOSURE_AUTO, + }, + { + .id = V4L2_CID_SCENE_MODE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "scene mode", + .minimum = 0, + .maximum = 13, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_ISO_SENSITIVITY, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "iso", + .minimum = -4, + .maximum = 4, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_ISO_SENSITIVITY_AUTO, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "iso mode", + .minimum = V4L2_ISO_SENSITIVITY_MANUAL, + .maximum = V4L2_ISO_SENSITIVITY_AUTO, + .step = 1, + .default_value = V4L2_ISO_SENSITIVITY_AUTO, + }, + { + .id = V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "white balance", + .minimum = 0, + .maximum = 9, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_EXPOSURE_METERING, + .type = V4L2_CTRL_TYPE_MENU, + .name = "metering", + .minimum = 0, + .maximum = 3, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_3A_LOCK, + .type = V4L2_CTRL_TYPE_BITMASK, + .name = "3a lock", + .minimum = 0, + .maximum = V4L2_LOCK_EXPOSURE | V4L2_LOCK_WHITE_BALANCE + | V4L2_LOCK_FOCUS, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_TEST_PATTERN, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test Pattern", + .minimum = 0, + .maximum = 0xffff, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_TEST_PATTERN_COLOR_R, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test Pattern Solid Color R", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_TEST_PATTERN_COLOR_GR, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test Pattern Solid Color GR", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_TEST_PATTERN_COLOR_GB, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test Pattern Solid Color GB", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_TEST_PATTERN_COLOR_B, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Test Pattern Solid Color B", + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, +}; +static const u32 ctrls_num = ARRAY_SIZE(ci_v4l2_controls); + +/* + * supported V4L2 fmts and resolutions + */ +const struct atomisp_format_bridge atomisp_output_fmts[] = { + { + .pixelformat = V4L2_PIX_FMT_YUV420, + .depth = 12, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_YUV420, + .sh_fmt = CSS_FRAME_FORMAT_YUV420, + .description = "YUV420, planar", + .planar = true + }, { + .pixelformat = V4L2_PIX_FMT_YVU420, + .depth = 12, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_YVU420, + .sh_fmt = CSS_FRAME_FORMAT_YV12, + .description = "YVU420, planar", + .planar = true + }, { + .pixelformat = V4L2_PIX_FMT_YUV422P, + .depth = 16, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_YUV422P, + .sh_fmt = CSS_FRAME_FORMAT_YUV422, + .description = "YUV422, planar", + .planar = true + }, { + .pixelformat = V4L2_PIX_FMT_YUV444, + .depth = 24, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_YUV444, + .sh_fmt = CSS_FRAME_FORMAT_YUV444, + .description = "YUV444" + }, { + .pixelformat = V4L2_PIX_FMT_NV12, + .depth = 12, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_NV12, + .sh_fmt = CSS_FRAME_FORMAT_NV12, + .description = "NV12, Y-plane, CbCr interleaved", + .planar = true + }, { + .pixelformat = V4L2_PIX_FMT_NV21, + .depth = 12, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_NV21, + .sh_fmt = CSS_FRAME_FORMAT_NV21, + .description = "NV21, Y-plane, CbCr interleaved", + .planar = true + }, { + .pixelformat = V4L2_PIX_FMT_NV16, + .depth = 16, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_NV16, + .sh_fmt = CSS_FRAME_FORMAT_NV16, + .description = "NV16, Y-plane, CbCr interleaved", + .planar = true + }, { + .pixelformat = V4L2_PIX_FMT_YUYV, + .depth = 16, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_YUYV, + .sh_fmt = CSS_FRAME_FORMAT_YUYV, + .description = "YUYV, interleaved" + }, { + .pixelformat = V4L2_PIX_FMT_UYVY, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_UYVY8_1X16, + .sh_fmt = CSS_FRAME_FORMAT_UYVY, + .description = "UYVY, interleaved" + }, { /* This one is for parallel sensors! DO NOT USE! */ + .pixelformat = V4L2_PIX_FMT_UYVY, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8, + .sh_fmt = CSS_FRAME_FORMAT_UYVY, + .description = "UYVY, interleaved" + }, { + .pixelformat = V4L2_PIX_FMT_SBGGR16, + .depth = 16, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_SBGGR16, + .sh_fmt = CSS_FRAME_FORMAT_RAW, + .description = "Bayer 16" + }, { + .pixelformat = V4L2_PIX_FMT_SBGGR8, + .depth = 8, + .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8, + .sh_fmt = CSS_FRAME_FORMAT_RAW, + .description = "Bayer 8" + }, { + .pixelformat = V4L2_PIX_FMT_SGBRG8, + .depth = 8, + .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8, + .sh_fmt = CSS_FRAME_FORMAT_RAW, + .description = "Bayer 8" + }, { + .pixelformat = V4L2_PIX_FMT_SGRBG8, + .depth = 8, + .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8, + .sh_fmt = CSS_FRAME_FORMAT_RAW, + .description = "Bayer 8" + }, { + .pixelformat = V4L2_PIX_FMT_SRGGB8, + .depth = 8, + .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8, + .sh_fmt = CSS_FRAME_FORMAT_RAW, + .description = "Bayer 8" + }, { + .pixelformat = V4L2_PIX_FMT_SBGGR10, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10, + .sh_fmt = CSS_FRAME_FORMAT_RAW, + .description = "Bayer 10" + }, { + .pixelformat = V4L2_PIX_FMT_SGBRG10, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10, + .sh_fmt = CSS_FRAME_FORMAT_RAW, + .description = "Bayer 10" + }, { + .pixelformat = V4L2_PIX_FMT_SGRBG10, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10, + .sh_fmt = CSS_FRAME_FORMAT_RAW, + .description = "Bayer 10" + }, { + .pixelformat = V4L2_PIX_FMT_SRGGB10, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10, + .sh_fmt = CSS_FRAME_FORMAT_RAW, + .description = "Bayer 10" + }, { + .pixelformat = V4L2_PIX_FMT_SBGGR12, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12, + .sh_fmt = CSS_FRAME_FORMAT_RAW, + .description = "Bayer 12" + }, { + .pixelformat = V4L2_PIX_FMT_SGBRG12, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12, + .sh_fmt = CSS_FRAME_FORMAT_RAW, + .description = "Bayer 12" + }, { + .pixelformat = V4L2_PIX_FMT_SGRBG12, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12, + .sh_fmt = CSS_FRAME_FORMAT_RAW, + .description = "Bayer 12" + }, { + .pixelformat = V4L2_PIX_FMT_SRGGB12, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12, + .sh_fmt = CSS_FRAME_FORMAT_RAW, + .description = "Bayer 12" + }, { + .pixelformat = V4L2_PIX_FMT_RGB32, + .depth = 32, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_RGB32, + .sh_fmt = CSS_FRAME_FORMAT_RGBA888, + .description = "32 RGB 8-8-8-8" + }, { + .pixelformat = V4L2_PIX_FMT_RGB565, + .depth = 16, + .mbus_code = MEDIA_BUS_FMT_BGR565_2X8_LE, + .sh_fmt = CSS_FRAME_FORMAT_RGB565, + .description = "16 RGB 5-6-5" + }, { + .pixelformat = V4L2_PIX_FMT_JPEG, + .depth = 8, + .mbus_code = MEDIA_BUS_FMT_JPEG_1X8, + .sh_fmt = CSS_FRAME_FORMAT_BINARY_8, + .description = "JPEG" + }, { + /* This is a custom format being used by M10MO to send the RAW data */ + .pixelformat = V4L2_PIX_FMT_CUSTOM_M10MO_RAW, + .depth = 8, + .mbus_code = V4L2_MBUS_FMT_CUSTOM_M10MO_RAW, + .sh_fmt = CSS_FRAME_FORMAT_BINARY_8, + .description = "Custom RAW for M10MO" + }, +}; + +const struct atomisp_format_bridge *atomisp_get_format_bridge( + unsigned int pixelformat) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(atomisp_output_fmts); i++) { + if (atomisp_output_fmts[i].pixelformat == pixelformat) + return &atomisp_output_fmts[i]; + } + + return NULL; +} + +#ifndef ISP2401 +const struct atomisp_format_bridge *atomisp_get_format_bridge_from_mbus( + u32 mbus_code) +#else +const struct atomisp_format_bridge *atomisp_get_format_bridge_from_mbus(u32 + mbus_code) +#endif +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(atomisp_output_fmts); i++) { + if (mbus_code == atomisp_output_fmts[i].mbus_code) + return &atomisp_output_fmts[i]; + } + + return NULL; +} + +/* + * v4l2 ioctls + * return ISP capabilities + * + * FIXME: capabilities should be different for video0/video2/video3 + */ +static int atomisp_querycap(struct file *file, void *fh, + struct v4l2_capability *cap) +{ + int ret = 0; + + memset(cap, 0, sizeof(struct v4l2_capability)); + + WARN_ON(sizeof(DRIVER) > sizeof(cap->driver) || + sizeof(CARD) > sizeof(cap->card) || + sizeof(BUS_INFO) > sizeof(cap->bus_info)); + + strncpy(cap->driver, DRIVER, sizeof(cap->driver) - 1); + strncpy(cap->card, CARD, sizeof(cap->card) - 1); + strncpy(cap->bus_info, BUS_INFO, sizeof(cap->card) - 1); + + cap->version = VERSION; + + cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | + V4L2_CAP_STREAMING | V4L2_CAP_VIDEO_OUTPUT; + cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS; + return ret; +} + +/* + * enum input are used to check primary/secondary camera + */ +static int atomisp_enum_input(struct file *file, void *fh, + struct v4l2_input *input) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + int index = input->index; + + if (index >= isp->input_cnt) + return -EINVAL; + + if (!isp->inputs[index].camera) + return -EINVAL; + + memset(input, 0, sizeof(struct v4l2_input)); + strncpy(input->name, isp->inputs[index].camera->name, + sizeof(input->name) - 1); + + /* + * HACK: append actuator's name to sensor's + * As currently userspace can't talk directly to subdev nodes, this + * ioctl is the only way to enum inputs + possible external actuators + * for 3A tuning purpose. + */ +#ifndef ISP2401 + if (isp->inputs[index].motor && + strlen(isp->inputs[index].motor->name) > 0) { +#else + if (isp->motor && + strlen(isp->motor->name) > 0) { +#endif + const int cur_len = strlen(input->name); + const int max_size = sizeof(input->name) - cur_len - 1; + + if (max_size > 1) { + input->name[cur_len] = '+'; + strncpy(&input->name[cur_len + 1], +#ifndef ISP2401 + isp->inputs[index].motor->name, max_size - 1); +#else + isp->motor->name, max_size - 1); +#endif + } + } + + input->type = V4L2_INPUT_TYPE_CAMERA; + input->index = index; + input->reserved[0] = isp->inputs[index].type; + input->reserved[1] = isp->inputs[index].port; + + return 0; +} + +static unsigned int atomisp_subdev_streaming_count( + struct atomisp_sub_device *asd) +{ + return asd->video_out_preview.capq.streaming + + asd->video_out_capture.capq.streaming + + asd->video_out_video_capture.capq.streaming + + asd->video_out_vf.capq.streaming + + asd->video_in.capq.streaming; +} + +unsigned int atomisp_streaming_count(struct atomisp_device *isp) +{ + unsigned int i, sum; + + for (i = 0, sum = 0; i < isp->num_of_streams; i++) + sum += isp->asd[i].streaming == + ATOMISP_DEVICE_STREAMING_ENABLED; + + return sum; +} + +unsigned int atomisp_is_acc_enabled(struct atomisp_device *isp) +{ + unsigned int i; + + for (i = 0; i < isp->num_of_streams; i++) + if (isp->asd[i].acc.pipeline) + return 1; + + return 0; +} +/* + * get input are used to get current primary/secondary camera + */ +static int atomisp_g_input(struct file *file, void *fh, unsigned int *input) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + + rt_mutex_lock(&isp->mutex); + *input = asd->input_curr; + rt_mutex_unlock(&isp->mutex); + + return 0; +} +/* + * set input are used to set current primary/secondary camera + */ +static int atomisp_s_input(struct file *file, void *fh, unsigned int input) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + struct v4l2_subdev *camera = NULL; + int ret; + + rt_mutex_lock(&isp->mutex); + if (input >= ATOM_ISP_MAX_INPUTS || input > isp->input_cnt) { + dev_dbg(isp->dev, "input_cnt: %d\n", isp->input_cnt); + ret = -EINVAL; + goto error; + } + + /* + * check whether the request camera: + * 1: already in use + * 2: if in use, whether it is used by other streams + */ + if (isp->inputs[input].asd != NULL && isp->inputs[input].asd != asd) { + dev_err(isp->dev, + "%s, camera is already used by stream: %d\n", __func__, + isp->inputs[input].asd->index); + ret = -EBUSY; + goto error; + } + + camera = isp->inputs[input].camera; + if (!camera) { + dev_err(isp->dev, "%s, no camera\n", __func__); + ret = -EINVAL; + goto error; + } + + if (atomisp_subdev_streaming_count(asd)) { + dev_err(isp->dev, + "ISP is still streaming, stop first\n"); + ret = -EINVAL; + goto error; + } + + /* power off the current owned sensor, as it is not used this time */ + if (isp->inputs[asd->input_curr].asd == asd && + asd->input_curr != input) { + ret = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + core, s_power, 0); + if (ret) + dev_warn(isp->dev, + "Failed to power-off sensor\n"); + /* clear the asd field to show this camera is not used */ + isp->inputs[asd->input_curr].asd = NULL; + } + + /* powe on the new sensor */ + ret = v4l2_subdev_call(isp->inputs[input].camera, core, s_power, 1); + if (ret) { + dev_err(isp->dev, "Failed to power-on sensor\n"); + goto error; + } + /* + * Some sensor driver resets the run mode during power-on, thus force + * update the run mode to sensor after power-on. + */ + atomisp_update_run_mode(asd); + + /* select operating sensor */ + ret = v4l2_subdev_call(isp->inputs[input].camera, video, s_routing, + 0, isp->inputs[input].sensor_index, 0); + if (ret && (ret != -ENOIOCTLCMD)) { + dev_err(isp->dev, "Failed to select sensor\n"); + goto error; + } + +#ifndef ISP2401 + if (!isp->sw_contex.file_input && isp->inputs[input].motor) + ret = v4l2_subdev_call(isp->inputs[input].motor, core, + init, 1); +#else + if (isp->motor) + ret = v4l2_subdev_call(isp->motor, core, s_power, 1); + + if (!isp->sw_contex.file_input && isp->motor) + ret = v4l2_subdev_call(isp->motor, core, init, 1); +#endif + + asd->input_curr = input; + /* mark this camera is used by the current stream */ + isp->inputs[input].asd = asd; + rt_mutex_unlock(&isp->mutex); + + return 0; + +error: + rt_mutex_unlock(&isp->mutex); + + return ret; +} + +static int atomisp_enum_fmt_cap(struct file *file, void *fh, + struct v4l2_fmtdesc *f) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + struct v4l2_subdev_mbus_code_enum code = { 0 }; + unsigned int i, fi = 0; + int rval; + + rt_mutex_lock(&isp->mutex); + rval = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, pad, + enum_mbus_code, NULL, &code); + if (rval == -ENOIOCTLCMD) { + dev_warn(isp->dev, "enum_mbus_code pad op not supported. Please fix your sensor driver!\n"); + // rval = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + // video, enum_mbus_fmt, 0, &code.code); + } + rt_mutex_unlock(&isp->mutex); + + if (rval) + return rval; + + for (i = 0; i < ARRAY_SIZE(atomisp_output_fmts); i++) { + const struct atomisp_format_bridge *format = + &atomisp_output_fmts[i]; + + /* + * Is the atomisp-supported format is valid for the + * sensor (configuration)? If not, skip it. + */ + if (format->sh_fmt == CSS_FRAME_FORMAT_RAW + && format->mbus_code != code.code) + continue; + + /* Found a match. Now let's pick f->index'th one. */ + if (fi < f->index) { + fi++; + continue; + } + + strlcpy(f->description, format->description, + sizeof(f->description)); + f->pixelformat = format->pixelformat; + return 0; + } + + return -EINVAL; +} + +static int atomisp_g_fmt_cap(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + + int ret; + + rt_mutex_lock(&isp->mutex); + ret = atomisp_get_fmt(vdev, f); + rt_mutex_unlock(&isp->mutex); + return ret; +} + +static int atomisp_g_fmt_file(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + + rt_mutex_lock(&isp->mutex); + f->fmt.pix = pipe->pix; + rt_mutex_unlock(&isp->mutex); + + return 0; +} + +/* This function looks up the closest available resolution. */ +static int atomisp_try_fmt_cap(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + int ret; + + rt_mutex_lock(&isp->mutex); + ret = atomisp_try_fmt(vdev, f, NULL); + rt_mutex_unlock(&isp->mutex); + return ret; +} + +static int atomisp_s_fmt_cap(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + int ret; + + rt_mutex_lock(&isp->mutex); + if (isp->isp_fatal_error) { + ret = -EIO; + rt_mutex_unlock(&isp->mutex); + return ret; + } + ret = atomisp_set_fmt(vdev, f); + rt_mutex_unlock(&isp->mutex); + return ret; +} + +static int atomisp_s_fmt_file(struct file *file, void *fh, + struct v4l2_format *f) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + int ret; + + rt_mutex_lock(&isp->mutex); + ret = atomisp_set_fmt_file(vdev, f); + rt_mutex_unlock(&isp->mutex); + return ret; +} + +/* + * Free videobuffer buffer priv data + */ +void atomisp_videobuf_free_buf(struct videobuf_buffer *vb) +{ + struct videobuf_vmalloc_memory *vm_mem; + + if (vb == NULL) + return; + + vm_mem = vb->priv; + if (vm_mem && vm_mem->vaddr) { + atomisp_css_frame_free(vm_mem->vaddr); + vm_mem->vaddr = NULL; + } +} + +/* + * this function is used to free video buffer queue + */ +static void atomisp_videobuf_free_queue(struct videobuf_queue *q) +{ + int i; + + for (i = 0; i < VIDEO_MAX_FRAME; i++) { + atomisp_videobuf_free_buf(q->bufs[i]); + kfree(q->bufs[i]); + q->bufs[i] = NULL; + } +} + +int atomisp_alloc_css_stat_bufs(struct atomisp_sub_device *asd, + uint16_t stream_id) +{ + struct atomisp_device *isp = asd->isp; + struct atomisp_s3a_buf *s3a_buf = NULL, *_s3a_buf; + struct atomisp_dis_buf *dis_buf = NULL, *_dis_buf; + struct atomisp_metadata_buf *md_buf = NULL, *_md_buf; + int count; + struct atomisp_css_dvs_grid_info *dvs_grid_info = + atomisp_css_get_dvs_grid_info(&asd->params.curr_grid_info); + unsigned int i; + + if (list_empty(&asd->s3a_stats) && + asd->params.curr_grid_info.s3a_grid.enable) { + count = ATOMISP_CSS_Q_DEPTH + + ATOMISP_S3A_BUF_QUEUE_DEPTH_FOR_HAL; + dev_dbg(isp->dev, "allocating %d 3a buffers\n", count); + while (count--) { + s3a_buf = kzalloc(sizeof(struct atomisp_s3a_buf), GFP_KERNEL); + if (!s3a_buf) { + dev_err(isp->dev, "s3a stat buf alloc failed\n"); + goto error; + } + + if (atomisp_css_allocate_stat_buffers( + asd, stream_id, s3a_buf, NULL, NULL)) { + kfree(s3a_buf); + goto error; + } + + list_add_tail(&s3a_buf->list, &asd->s3a_stats); + } + } + + if (list_empty(&asd->dis_stats) && dvs_grid_info && + dvs_grid_info->enable) { + count = ATOMISP_CSS_Q_DEPTH + 1; + dev_dbg(isp->dev, "allocating %d dis buffers\n", count); + while (count--) { + dis_buf = kzalloc(sizeof(struct atomisp_dis_buf), GFP_KERNEL); + if (!dis_buf) { + dev_err(isp->dev, "dis stat buf alloc failed\n"); + kfree(s3a_buf); + goto error; + } + if (atomisp_css_allocate_stat_buffers( + asd, stream_id, NULL, dis_buf, NULL)) { + kfree(dis_buf); + goto error; + } + + list_add_tail(&dis_buf->list, &asd->dis_stats); + } + } + + for (i = 0; i < ATOMISP_METADATA_TYPE_NUM; i++) { + if (list_empty(&asd->metadata[i]) && + list_empty(&asd->metadata_ready[i]) && + list_empty(&asd->metadata_in_css[i])) { + count = ATOMISP_CSS_Q_DEPTH + + ATOMISP_METADATA_QUEUE_DEPTH_FOR_HAL; + dev_dbg(isp->dev, "allocating %d metadata buffers for type %d\n", + count, i); + while (count--) { + md_buf = kzalloc(sizeof(struct atomisp_metadata_buf), + GFP_KERNEL); + if (!md_buf) { + dev_err(isp->dev, "metadata buf alloc failed\n"); + goto error; + } + + if (atomisp_css_allocate_stat_buffers( + asd, stream_id, NULL, NULL, md_buf)) { + kfree(md_buf); + goto error; + } + list_add_tail(&md_buf->list, &asd->metadata[i]); + } + } + } + return 0; + +error: + dev_err(isp->dev, "failed to allocate statistics buffers\n"); + + list_for_each_entry_safe(dis_buf, _dis_buf, &asd->dis_stats, list) { + atomisp_css_free_dis_buffer(dis_buf); + list_del(&dis_buf->list); + kfree(dis_buf); + } + + list_for_each_entry_safe(s3a_buf, _s3a_buf, &asd->s3a_stats, list) { + atomisp_css_free_3a_buffer(s3a_buf); + list_del(&s3a_buf->list); + kfree(s3a_buf); + } + + for (i = 0; i < ATOMISP_METADATA_TYPE_NUM; i++) { + list_for_each_entry_safe(md_buf, _md_buf, &asd->metadata[i], + list) { + atomisp_css_free_metadata_buffer(md_buf); + list_del(&md_buf->list); + kfree(md_buf); + } + } + return -ENOMEM; +} + +/* + * Initiate Memory Mapping or User Pointer I/O + */ +int __atomisp_reqbufs(struct file *file, void *fh, + struct v4l2_requestbuffers *req) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + struct atomisp_sub_device *asd = pipe->asd; + struct atomisp_css_frame_info frame_info; + struct atomisp_css_frame *frame; + struct videobuf_vmalloc_memory *vm_mem; + uint16_t source_pad = atomisp_subdev_source_pad(vdev); + uint16_t stream_id = atomisp_source_pad_to_stream_id(asd, source_pad); + int ret = 0, i = 0; + + if (req->count == 0) { + mutex_lock(&pipe->capq.vb_lock); + if (!list_empty(&pipe->capq.stream)) + videobuf_queue_cancel(&pipe->capq); + + atomisp_videobuf_free_queue(&pipe->capq); + mutex_unlock(&pipe->capq.vb_lock); + /* clear request config id */ + memset(pipe->frame_request_config_id, 0, + VIDEO_MAX_FRAME * sizeof(unsigned int)); + memset(pipe->frame_params, 0, + VIDEO_MAX_FRAME * + sizeof(struct atomisp_css_params_with_list *)); + return 0; + } + + ret = videobuf_reqbufs(&pipe->capq, req); + if (ret) + return ret; + + atomisp_alloc_css_stat_bufs(asd, stream_id); + + /* + * for user pointer type, buffers are not really allcated here, + * buffers are setup in QBUF operation through v4l2_buffer structure + */ + if (req->memory == V4L2_MEMORY_USERPTR) + return 0; + + ret = atomisp_get_css_frame_info(asd, source_pad, &frame_info); + if (ret) + return ret; + + /* + * Allocate the real frame here for selected node using our + * memory management function + */ + for (i = 0; i < req->count; i++) { + if (atomisp_css_frame_allocate_from_info(&frame, &frame_info)) + goto error; + vm_mem = pipe->capq.bufs[i]->priv; + vm_mem->vaddr = frame; + } + + return ret; + +error: + while (i--) { + vm_mem = pipe->capq.bufs[i]->priv; + atomisp_css_frame_free(vm_mem->vaddr); + } + + if (asd->vf_frame) + atomisp_css_frame_free(asd->vf_frame); + + return -ENOMEM; +} + +int atomisp_reqbufs(struct file *file, void *fh, + struct v4l2_requestbuffers *req) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + int ret; + + rt_mutex_lock(&isp->mutex); + ret = __atomisp_reqbufs(file, fh, req); + rt_mutex_unlock(&isp->mutex); + + return ret; +} + +static int atomisp_reqbufs_file(struct file *file, void *fh, + struct v4l2_requestbuffers *req) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + + if (req->count == 0) { + mutex_lock(&pipe->outq.vb_lock); + atomisp_videobuf_free_queue(&pipe->outq); + mutex_unlock(&pipe->outq.vb_lock); + return 0; + } + + return videobuf_reqbufs(&pipe->outq, req); +} + +/* application query the status of a buffer */ +static int atomisp_querybuf(struct file *file, void *fh, + struct v4l2_buffer *buf) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + + return videobuf_querybuf(&pipe->capq, buf); +} + +static int atomisp_querybuf_file(struct file *file, void *fh, + struct v4l2_buffer *buf) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + + return videobuf_querybuf(&pipe->outq, buf); +} + +/* + * Applications call the VIDIOC_QBUF ioctl to enqueue an empty (capturing) or + * filled (output) buffer in the drivers incoming queue. + */ +static int atomisp_qbuf(struct file *file, void *fh, struct v4l2_buffer *buf) +{ + static const int NOFLUSH_FLAGS = V4L2_BUF_FLAG_NO_CACHE_INVALIDATE | + V4L2_BUF_FLAG_NO_CACHE_CLEAN; + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + struct atomisp_sub_device *asd = pipe->asd; + struct videobuf_buffer *vb; + struct videobuf_vmalloc_memory *vm_mem; + struct atomisp_css_frame_info frame_info; + struct atomisp_css_frame *handle = NULL; + u32 length; + u32 pgnr; + int ret = 0; + + rt_mutex_lock(&isp->mutex); + if (isp->isp_fatal_error) { + ret = -EIO; + goto error; + } + + if (asd->streaming == ATOMISP_DEVICE_STREAMING_STOPPING) { + dev_err(isp->dev, "%s: reject, as ISP at stopping.\n", + __func__); + ret = -EIO; + goto error; + } + + if (!buf || buf->index >= VIDEO_MAX_FRAME || + !pipe->capq.bufs[buf->index]) { + dev_err(isp->dev, "Invalid index for qbuf.\n"); + ret = -EINVAL; + goto error; + } + + /* + * For userptr type frame, we convert user space address to physic + * address and reprograme out page table properly + */ + if (buf->memory == V4L2_MEMORY_USERPTR) { + struct hrt_userbuffer_attr attributes; + vb = pipe->capq.bufs[buf->index]; + vm_mem = vb->priv; + if (!vm_mem) { + ret = -EINVAL; + goto error; + } + + length = vb->bsize; + pgnr = (length + (PAGE_SIZE - 1)) >> PAGE_SHIFT; + + if (vb->baddr == buf->m.userptr && vm_mem->vaddr) + goto done; + + if (atomisp_get_css_frame_info(asd, + atomisp_subdev_source_pad(vdev), &frame_info)) { + ret = -EIO; + goto error; + } + + attributes.pgnr = pgnr; +#ifdef CONFIG_ION +#ifndef ISP2401 + attributes.type = buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_ION + ? HRT_USR_ION : HRT_USR_PTR; +#else + if (buf->reserved & ATOMISP_BUFFER_TYPE_IS_ION) { + attributes.type = HRT_USR_ION; + if (asd->ion_dev_fd->val != ION_FD_UNSET) { + dev_dbg(isp->dev, "ION buffer queued, share_fd=%lddev_fd=%d.\n", + buf->m.userptr, asd->ion_dev_fd->val); + /* + * Make sure the shared fd we just got + * from user space isn't larger than + * the space we have for it. + */ + if ((buf->m.userptr & + (ATOMISP_ION_DEVICE_FD_MASK)) != 0) { + dev_err(isp->dev, + "Error: v4l2 buffer fd:0X%0lX > 0XFFFF.\n", + buf->m.userptr); + ret = -EINVAL; + goto error; + } + buf->m.userptr |= asd->ion_dev_fd->val << + ATOMISP_ION_DEVICE_FD_OFFSET; + } else { + dev_err(isp->dev, "v4l2 buffer type is ION, \ + but no dev fd set from userspace.\n"); + ret = -EINVAL; + goto error; + } + } else { + attributes.type = HRT_USR_PTR; + } +#endif +#else + attributes.type = HRT_USR_PTR; +#endif + ret = atomisp_css_frame_map(&handle, &frame_info, + (void *)buf->m.userptr, + 0, &attributes); + if (ret) { + dev_err(isp->dev, "Failed to map user buffer\n"); + goto error; + } + + if (vm_mem->vaddr) { + mutex_lock(&pipe->capq.vb_lock); + atomisp_css_frame_free(vm_mem->vaddr); + vm_mem->vaddr = NULL; + vb->state = VIDEOBUF_NEEDS_INIT; + mutex_unlock(&pipe->capq.vb_lock); + } + + vm_mem->vaddr = handle; + + buf->flags &= ~V4L2_BUF_FLAG_MAPPED; + buf->flags |= V4L2_BUF_FLAG_QUEUED; + buf->flags &= ~V4L2_BUF_FLAG_DONE; + } else if (buf->memory == V4L2_MEMORY_MMAP) { + buf->flags |= V4L2_BUF_FLAG_MAPPED; + buf->flags |= V4L2_BUF_FLAG_QUEUED; + buf->flags &= ~V4L2_BUF_FLAG_DONE; + } + +done: + if (!((buf->flags & NOFLUSH_FLAGS) == NOFLUSH_FLAGS)) + wbinvd(); + + if (!atomisp_is_vf_pipe(pipe) && + (buf->reserved2 & ATOMISP_BUFFER_HAS_PER_FRAME_SETTING)) { + /* this buffer will have a per-frame parameter */ + pipe->frame_request_config_id[buf->index] = buf->reserved2 & + ~ATOMISP_BUFFER_HAS_PER_FRAME_SETTING; +#ifndef ISP2401 + dev_dbg(isp->dev, "This buffer requires per_frame setting which has isp_config_id %d\n", + pipe->frame_request_config_id[buf->index]); +#else + dev_dbg(isp->dev, "This buffer requires per_frame setting \ + which has isp_config_id %d\n", + pipe->frame_request_config_id[buf->index]); +#endif + } else { + pipe->frame_request_config_id[buf->index] = 0; + } + + pipe->frame_params[buf->index] = NULL; + + rt_mutex_unlock(&isp->mutex); + + ret = videobuf_qbuf(&pipe->capq, buf); + rt_mutex_lock(&isp->mutex); + if (ret) + goto error; + + /* TODO: do this better, not best way to queue to css */ + if (asd->streaming == ATOMISP_DEVICE_STREAMING_ENABLED) { + if (!list_empty(&pipe->buffers_waiting_for_param)) { + atomisp_handle_parameter_and_buffer(pipe); + } else { + atomisp_qbuffers_to_css(asd); + +#ifndef ISP2401 + if (!atomisp_is_wdt_running(asd) && atomisp_buffers_queued(asd)) + atomisp_wdt_start(asd); +#else + if (!atomisp_is_wdt_running(pipe) && + atomisp_buffers_queued_pipe(pipe)) + atomisp_wdt_start(pipe); +#endif + } + } + + /* Workaround: Due to the design of HALv3, + * sometimes in ZSL or SDV mode HAL needs to + * capture multiple images within one streaming cycle. + * But the capture number cannot be determined by HAL. + * So HAL only sets the capture number to be 1 and queue multiple + * buffers. Atomisp driver needs to check this case and re-trigger + * CSS to do capture when new buffer is queued. */ + if (asd->continuous_mode->val && + atomisp_subdev_source_pad(vdev) + == ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE && + pipe->capq.streaming && + !asd->enable_raw_buffer_lock->val && + asd->params.offline_parm.num_captures == 1) { +#ifndef ISP2401 + asd->pending_capture_request++; + dev_dbg(isp->dev, "Add one pending capture request.\n"); +#else + if (asd->re_trigger_capture) { + ret = atomisp_css_offline_capture_configure(asd, + asd->params.offline_parm.num_captures, + asd->params.offline_parm.skip_frames, + asd->params.offline_parm.offset); + asd->re_trigger_capture = false; + dev_dbg(isp->dev, "%s Trigger capture again ret=%d\n", + __func__, ret); + + } else { + asd->pending_capture_request++; + asd->re_trigger_capture = false; + dev_dbg(isp->dev, "Add one pending capture request.\n"); + } +#endif + } + rt_mutex_unlock(&isp->mutex); + + dev_dbg(isp->dev, "qbuf buffer %d (%s) for asd%d\n", buf->index, + vdev->name, asd->index); + + return ret; + +error: + rt_mutex_unlock(&isp->mutex); + return ret; +} + +static int atomisp_qbuf_file(struct file *file, void *fh, + struct v4l2_buffer *buf) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + int ret; + + rt_mutex_lock(&isp->mutex); + if (isp->isp_fatal_error) { + ret = -EIO; + goto error; + } + + if (!buf || buf->index >= VIDEO_MAX_FRAME || + !pipe->outq.bufs[buf->index]) { + dev_err(isp->dev, "Invalid index for qbuf.\n"); + ret = -EINVAL; + goto error; + } + + if (buf->memory != V4L2_MEMORY_MMAP) { + dev_err(isp->dev, "Unsupported memory method\n"); + ret = -EINVAL; + goto error; + } + + if (buf->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + dev_err(isp->dev, "Unsupported buffer type\n"); + ret = -EINVAL; + goto error; + } + rt_mutex_unlock(&isp->mutex); + + return videobuf_qbuf(&pipe->outq, buf); + +error: + rt_mutex_unlock(&isp->mutex); + + return ret; +} + +static int __get_frame_exp_id(struct atomisp_video_pipe *pipe, + struct v4l2_buffer *buf) +{ + struct videobuf_vmalloc_memory *vm_mem; + struct atomisp_css_frame *handle; + int i; + + for (i = 0; pipe->capq.bufs[i]; i++) { + vm_mem = pipe->capq.bufs[i]->priv; + handle = vm_mem->vaddr; + if (buf->index == pipe->capq.bufs[i]->i && handle) + return handle->exp_id; + } + return -EINVAL; +} + +/* + * Applications call the VIDIOC_DQBUF ioctl to dequeue a filled (capturing) or + * displayed (output buffer)from the driver's outgoing queue + */ +static int atomisp_dqbuf(struct file *file, void *fh, struct v4l2_buffer *buf) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + struct atomisp_sub_device *asd = pipe->asd; + struct atomisp_device *isp = video_get_drvdata(vdev); + int ret = 0; + + rt_mutex_lock(&isp->mutex); + + if (isp->isp_fatal_error) { + rt_mutex_unlock(&isp->mutex); + return -EIO; + } + + if (asd->streaming == ATOMISP_DEVICE_STREAMING_STOPPING) { + rt_mutex_unlock(&isp->mutex); + dev_err(isp->dev, "%s: reject, as ISP at stopping.\n", + __func__); + return -EIO; + } + + rt_mutex_unlock(&isp->mutex); + + ret = videobuf_dqbuf(&pipe->capq, buf, file->f_flags & O_NONBLOCK); + if (ret) { + dev_dbg(isp->dev, "<%s: %d\n", __func__, ret); + return ret; + } + rt_mutex_lock(&isp->mutex); + buf->bytesused = pipe->pix.sizeimage; + buf->reserved = asd->frame_status[buf->index]; + + /* + * Hack: + * Currently frame_status in the enum type which takes no more lower + * 8 bit. + * use bit[31:16] for exp_id as it is only in the range of 1~255 + */ + buf->reserved &= 0x0000ffff; + if (!(buf->flags & V4L2_BUF_FLAG_ERROR)) + buf->reserved |= __get_frame_exp_id(pipe, buf) << 16; + buf->reserved2 = pipe->frame_config_id[buf->index]; + rt_mutex_unlock(&isp->mutex); + +#ifndef ISP2401 + dev_dbg(isp->dev, "dqbuf buffer %d (%s) for asd%d with exp_id %d, isp_config_id %d\n", +#else + dev_dbg(isp->dev, "dqbuf buffer %d (%s) for asd%d with exp_id %d, \ + isp_config_id %d\n", +#endif + buf->index, vdev->name, asd->index, buf->reserved >> 16, + buf->reserved2); + return 0; +} + +enum atomisp_css_pipe_id atomisp_get_css_pipe_id(struct atomisp_sub_device *asd) +{ + if (ATOMISP_USE_YUVPP(asd)) + return CSS_PIPE_ID_YUVPP; + + if (asd->continuous_mode->val) { + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) + return CSS_PIPE_ID_VIDEO; + else + return CSS_PIPE_ID_PREVIEW; + } + + /* + * Disable vf_pp and run CSS in video mode. This allows using ISP + * scaling but it has one frame delay due to CSS internal buffering. + */ + if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_SCALER) + return CSS_PIPE_ID_VIDEO; + + /* + * Disable vf_pp and run CSS in still capture mode. In this mode + * CSS does not cause extra latency with buffering, but scaling + * is not available. + */ + if (asd->vfpp->val == ATOMISP_VFPP_DISABLE_LOWLAT) + return CSS_PIPE_ID_CAPTURE; + + switch (asd->run_mode->val) { + case ATOMISP_RUN_MODE_PREVIEW: + return CSS_PIPE_ID_PREVIEW; + case ATOMISP_RUN_MODE_VIDEO: + return CSS_PIPE_ID_VIDEO; + case ATOMISP_RUN_MODE_STILL_CAPTURE: + /* fall through */ + default: + return CSS_PIPE_ID_CAPTURE; + } +} + +static unsigned int atomisp_sensor_start_stream(struct atomisp_sub_device *asd) +{ + struct atomisp_device *isp = asd->isp; + + if (isp->inputs[asd->input_curr].camera_caps-> + sensor[asd->sensor_curr].stream_num > 1) { + if (asd->high_speed_mode) + return 1; + else + return 2; + } + + if (asd->vfpp->val != ATOMISP_VFPP_ENABLE || + asd->copy_mode) + return 1; + + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO || + (asd->run_mode->val == ATOMISP_RUN_MODE_STILL_CAPTURE && + !atomisp_is_mbuscode_raw( + asd->fmt[ + asd->capture_pad].fmt.code) && + !asd->continuous_mode->val)) + return 2; + else + return 1; +} +#ifndef ISP2401 +int atomisp_stream_on_master_slave_sensor(struct atomisp_device *isp, bool isp_timeout) +#else +int atomisp_stream_on_master_slave_sensor(struct atomisp_device *isp, + bool isp_timeout) +#endif +{ + unsigned int master = -1, slave = -1, delay_slave = 0; + int i, ret; + + /* + * ISP only support 2 streams now so ignore multiple master/slave + * case to reduce the delay between 2 stream_on calls. + */ + for (i = 0; i < isp->num_of_streams; i++) { + int sensor_index = isp->asd[i].input_curr; + if (isp->inputs[sensor_index].camera_caps-> + sensor[isp->asd[i].sensor_curr].is_slave) + slave = sensor_index; + else + master = sensor_index; + } + + if (master == -1 || slave == -1) { + master = ATOMISP_DEPTH_DEFAULT_MASTER_SENSOR; + slave = ATOMISP_DEPTH_DEFAULT_SLAVE_SENSOR; + dev_warn(isp->dev, + "depth mode use default master=%s.slave=%s.\n", + isp->inputs[master].camera->name, + isp->inputs[slave].camera->name); + } + + ret = v4l2_subdev_call(isp->inputs[master].camera, core, + ioctl, ATOMISP_IOC_G_DEPTH_SYNC_COMP, + &delay_slave); + if (ret) + dev_warn(isp->dev, + "get depth sensor %s compensation delay failed.\n", + isp->inputs[master].camera->name); + + ret = v4l2_subdev_call(isp->inputs[master].camera, + video, s_stream, 1); + if (ret) { + dev_err(isp->dev, "depth mode master sensor %s stream-on failed.\n", + isp->inputs[master].camera->name); + return -EINVAL; + } + + if (delay_slave != 0) + udelay(delay_slave); + + ret = v4l2_subdev_call(isp->inputs[slave].camera, + video, s_stream, 1); + if (ret) { + dev_err(isp->dev, "depth mode slave sensor %s stream-on failed.\n", + isp->inputs[slave].camera->name); + v4l2_subdev_call(isp->inputs[master].camera, video, s_stream, 0); + + return -EINVAL; + } + + return 0; +} + +/* FIXME! */ +#ifndef ISP2401 +void __wdt_on_master_slave_sensor(struct atomisp_device *isp, unsigned int wdt_duration) +#else +void __wdt_on_master_slave_sensor(struct atomisp_video_pipe *pipe, + unsigned int wdt_duration, bool enable) +#endif +{ +#ifndef ISP2401 + if (atomisp_buffers_queued(&isp->asd[0])) + atomisp_wdt_refresh(&isp->asd[0], wdt_duration); + if (atomisp_buffers_queued(&isp->asd[1])) + atomisp_wdt_refresh(&isp->asd[1], wdt_duration); +#else + static struct atomisp_video_pipe *pipe0; + + if (enable) { + if (atomisp_buffers_queued_pipe(pipe0)) + atomisp_wdt_refresh_pipe(pipe0, wdt_duration); + if (atomisp_buffers_queued_pipe(pipe)) + atomisp_wdt_refresh_pipe(pipe, wdt_duration); + } else { + pipe0 = pipe; + } +#endif +} + +static void atomisp_pause_buffer_event(struct atomisp_device *isp) +{ + struct v4l2_event event = {0}; + int i; + + event.type = V4L2_EVENT_ATOMISP_PAUSE_BUFFER; + + for (i = 0; i < isp->num_of_streams; i++) { + int sensor_index = isp->asd[i].input_curr; + if (isp->inputs[sensor_index].camera_caps-> + sensor[isp->asd[i].sensor_curr].is_slave) { + v4l2_event_queue(isp->asd[i].subdev.devnode, &event); + break; + } + } +} + +/* Input system HW workaround */ +/* Input system address translation corrupts burst during */ +/* invalidate. SW workaround for this is to set burst length */ +/* manually to 128 in case of 13MPx snapshot and to 1 otherwise. */ +static void atomisp_dma_burst_len_cfg(struct atomisp_sub_device *asd) +{ + + struct v4l2_mbus_framefmt *sink; + sink = atomisp_subdev_get_ffmt(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK); + + if (sink->width * sink->height >= 4096*3072) + atomisp_store_uint32(DMA_BURST_SIZE_REG, 0x7F); + else + atomisp_store_uint32(DMA_BURST_SIZE_REG, 0x00); +} + +/* + * This ioctl start the capture during streaming I/O. + */ +static int atomisp_streamon(struct file *file, void *fh, + enum v4l2_buf_type type) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + struct atomisp_sub_device *asd = pipe->asd; + struct atomisp_device *isp = video_get_drvdata(vdev); + enum atomisp_css_pipe_id css_pipe_id; + unsigned int sensor_start_stream; + unsigned int wdt_duration = ATOMISP_ISP_TIMEOUT_DURATION; + int ret = 0; + unsigned long irqflags; + + dev_dbg(isp->dev, "Start stream on pad %d for asd%d\n", + atomisp_subdev_source_pad(vdev), asd->index); + + if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + dev_dbg(isp->dev, "unsupported v4l2 buf type\n"); + return -EINVAL; + } + + rt_mutex_lock(&isp->mutex); + if (isp->isp_fatal_error) { + ret = -EIO; + goto out; + } + + if (asd->streaming == ATOMISP_DEVICE_STREAMING_STOPPING) { + ret = -EBUSY; + goto out; + } + + if (pipe->capq.streaming) + goto out; + + /* Input system HW workaround */ + atomisp_dma_burst_len_cfg(asd); + + /* + * The number of streaming video nodes is based on which + * binary is going to be run. + */ + sensor_start_stream = atomisp_sensor_start_stream(asd); + + spin_lock_irqsave(&pipe->irq_lock, irqflags); + if (list_empty(&(pipe->capq.stream))) { + spin_unlock_irqrestore(&pipe->irq_lock, irqflags); + dev_dbg(isp->dev, "no buffer in the queue\n"); + ret = -EINVAL; + goto out; + } + spin_unlock_irqrestore(&pipe->irq_lock, irqflags); + + ret = videobuf_streamon(&pipe->capq); + if (ret) + goto out; + + /* Reset pending capture request count. */ + asd->pending_capture_request = 0; +#ifdef ISP2401 + asd->re_trigger_capture = false; +#endif + + if ((atomisp_subdev_streaming_count(asd) > sensor_start_stream) && + (!isp->inputs[asd->input_curr].camera_caps->multi_stream_ctrl)) { + /* trigger still capture */ + if (asd->continuous_mode->val && + atomisp_subdev_source_pad(vdev) + == ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE) { + if (asd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) + dev_dbg(isp->dev, "SDV last video raw buffer id: %u\n", + asd->latest_preview_exp_id); + else + dev_dbg(isp->dev, "ZSL last preview raw buffer id: %u\n", + asd->latest_preview_exp_id); + + if (asd->delayed_init == ATOMISP_DELAYED_INIT_QUEUED) { + flush_work(&asd->delayed_init_work); + rt_mutex_unlock(&isp->mutex); + if (wait_for_completion_interruptible( + &asd->init_done) != 0) + return -ERESTARTSYS; + rt_mutex_lock(&isp->mutex); + } + + /* handle per_frame_setting parameter and buffers */ + atomisp_handle_parameter_and_buffer(pipe); + + /* + * only ZSL/SDV capture request will be here, raise + * the ISP freq to the highest possible to minimize + * the S2S latency. + */ + atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_MAX, false); + /* + * When asd->enable_raw_buffer_lock->val is true, + * An extra IOCTL is needed to call + * atomisp_css_exp_id_capture and trigger real capture + */ + if (!asd->enable_raw_buffer_lock->val) { + ret = atomisp_css_offline_capture_configure(asd, + asd->params.offline_parm.num_captures, + asd->params.offline_parm.skip_frames, + asd->params.offline_parm.offset); + if (ret) { + ret = -EINVAL; + goto out; + } + if (asd->depth_mode->val) + atomisp_pause_buffer_event(isp); + } + } + atomisp_qbuffers_to_css(asd); + goto out; + } + + if (asd->streaming == ATOMISP_DEVICE_STREAMING_ENABLED) { + atomisp_qbuffers_to_css(asd); + goto start_sensor; + } + + css_pipe_id = atomisp_get_css_pipe_id(asd); + + ret = atomisp_acc_load_extensions(asd); + if (ret < 0) { + dev_err(isp->dev, "acc extension failed to load\n"); + goto out; + } + + if (asd->params.css_update_params_needed) { + atomisp_apply_css_parameters(asd, &asd->params.css_param); + if (asd->params.css_param.update_flag.dz_config) + atomisp_css_set_dz_config(asd, + &asd->params.css_param.dz_config); + atomisp_css_update_isp_params(asd); + asd->params.css_update_params_needed = false; + memset(&asd->params.css_param.update_flag, 0, + sizeof(struct atomisp_parameters)); + } + asd->params.dvs_6axis = NULL; + + ret = atomisp_css_start(asd, css_pipe_id, false); + if (ret) + goto out; + + asd->streaming = ATOMISP_DEVICE_STREAMING_ENABLED; + atomic_set(&asd->sof_count, -1); + atomic_set(&asd->sequence, -1); + atomic_set(&asd->sequence_temp, -1); + if (isp->sw_contex.file_input) + wdt_duration = ATOMISP_ISP_FILE_TIMEOUT_DURATION; + + asd->params.dis_proj_data_valid = false; + asd->latest_preview_exp_id = 0; + asd->postview_exp_id = 1; + asd->preview_exp_id = 1; + + /* handle per_frame_setting parameter and buffers */ + atomisp_handle_parameter_and_buffer(pipe); + + atomisp_qbuffers_to_css(asd); + + /* Only start sensor when the last streaming instance started */ + if (atomisp_subdev_streaming_count(asd) < sensor_start_stream) + goto out; + +start_sensor: + if (isp->flash) { + asd->params.num_flash_frames = 0; + asd->params.flash_state = ATOMISP_FLASH_IDLE; + atomisp_setup_flash(asd); + } + + if (!isp->sw_contex.file_input) { + atomisp_css_irq_enable(isp, CSS_IRQ_INFO_CSS_RECEIVER_SOF, + atomisp_css_valid_sof(isp)); + atomisp_csi2_configure(asd); + /* + * set freq to max when streaming count > 1 which indicate + * dual camera would run + */ + if (atomisp_streaming_count(isp) > 1) { + if (atomisp_freq_scaling(isp, + ATOMISP_DFS_MODE_MAX, false) < 0) + dev_dbg(isp->dev, "dfs failed!\n"); + } else { + if (atomisp_freq_scaling(isp, + ATOMISP_DFS_MODE_AUTO, false) < 0) + dev_dbg(isp->dev, "dfs failed!\n"); + } + } else { + if (atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_MAX, false) < 0) + dev_dbg(isp->dev, "dfs failed!\n"); + } + + if (asd->depth_mode->val && atomisp_streaming_count(isp) == + ATOMISP_DEPTH_SENSOR_STREAMON_COUNT) { + ret = atomisp_stream_on_master_slave_sensor(isp, false); + if (ret) { + dev_err(isp->dev, "master slave sensor stream on failed!\n"); + goto out; + } +#ifndef ISP2401 + __wdt_on_master_slave_sensor(isp, wdt_duration); +#else + __wdt_on_master_slave_sensor(pipe, wdt_duration, true); +#endif + goto start_delay_wq; + } else if (asd->depth_mode->val && (atomisp_streaming_count(isp) < + ATOMISP_DEPTH_SENSOR_STREAMON_COUNT)) { +#ifdef ISP2401 + __wdt_on_master_slave_sensor(pipe, wdt_duration, false); +#endif + goto start_delay_wq; + } + + /* Enable the CSI interface on ANN B0/K0 */ + if (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 << + ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0)) { + pci_write_config_word(isp->pdev, MRFLD_PCI_CSI_CONTROL, + isp->saved_regs.csi_control | + MRFLD_PCI_CSI_CONTROL_CSI_READY); + } + + /* stream on the sensor */ + ret = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + video, s_stream, 1); + if (ret) { + asd->streaming = ATOMISP_DEVICE_STREAMING_DISABLED; + ret = -EINVAL; + goto out; + } + +#ifndef ISP2401 + if (atomisp_buffers_queued(asd)) + atomisp_wdt_refresh(asd, wdt_duration); +#else + if (atomisp_buffers_queued_pipe(pipe)) + atomisp_wdt_refresh_pipe(pipe, wdt_duration); +#endif + +start_delay_wq: + if (asd->continuous_mode->val) { + struct v4l2_mbus_framefmt *sink; + + sink = atomisp_subdev_get_ffmt(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK); + + reinit_completion(&asd->init_done); + asd->delayed_init = ATOMISP_DELAYED_INIT_QUEUED; + queue_work(asd->delayed_init_workq, &asd->delayed_init_work); + atomisp_css_set_cont_prev_start_time(isp, + ATOMISP_CALC_CSS_PREV_OVERLAP(sink->height)); + } else { + asd->delayed_init = ATOMISP_DELAYED_INIT_NOT_QUEUED; + } +out: + rt_mutex_unlock(&isp->mutex); + return ret; +} + +int __atomisp_streamoff(struct file *file, void *fh, enum v4l2_buf_type type) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_video_pipe *pipe = atomisp_to_video_pipe(vdev); + struct atomisp_sub_device *asd = pipe->asd; + struct atomisp_video_pipe *capture_pipe = NULL; + struct atomisp_video_pipe *vf_pipe = NULL; + struct atomisp_video_pipe *preview_pipe = NULL; + struct atomisp_video_pipe *video_pipe = NULL; + struct videobuf_buffer *vb, *_vb; + enum atomisp_css_pipe_id css_pipe_id; + int ret; + unsigned long flags; + bool first_streamoff = false; + + dev_dbg(isp->dev, "Stop stream on pad %d for asd%d\n", + atomisp_subdev_source_pad(vdev), asd->index); + + BUG_ON(!rt_mutex_is_locked(&isp->mutex)); + BUG_ON(!mutex_is_locked(&isp->streamoff_mutex)); + + if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + dev_dbg(isp->dev, "unsupported v4l2 buf type\n"); + return -EINVAL; + } + + /* + * do only videobuf_streamoff for capture & vf pipes in + * case of continuous capture + */ + if ((asd->continuous_mode->val || + isp->inputs[asd->input_curr].camera_caps->multi_stream_ctrl) && + atomisp_subdev_source_pad(vdev) != + ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW && + atomisp_subdev_source_pad(vdev) != + ATOMISP_SUBDEV_PAD_SOURCE_VIDEO) { + + if (isp->inputs[asd->input_curr].camera_caps->multi_stream_ctrl) { + v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + video, s_stream, 0); + } else if (atomisp_subdev_source_pad(vdev) + == ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE) { + /* stop continuous still capture if needed */ + if (asd->params.offline_parm.num_captures == -1) + atomisp_css_offline_capture_configure(asd, + 0, 0, 0); + atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_AUTO, false); + } + /* + * Currently there is no way to flush buffers queued to css. + * When doing videobuf_streamoff, active buffers will be + * marked as VIDEOBUF_NEEDS_INIT. HAL will be able to use + * these buffers again, and these buffers might be queued to + * css more than once! Warn here, if HAL has not dequeued all + * buffers back before calling streamoff. + */ + if (pipe->buffers_in_css != 0) { + WARN(1, "%s: buffers of vdev %s still in CSS!\n", + __func__, pipe->vdev.name); + + /* + * Buffers remained in css maybe dequeued out in the + * next stream on, while this will causes serious + * issues as buffers already get invalid after + * previous stream off. + * + * No way to flush buffers but to reset the whole css + */ + dev_warn(isp->dev, "Reset CSS to clean up css buffers.\n"); + atomisp_css_flush(isp); + } + + return videobuf_streamoff(&pipe->capq); + } + + if (!pipe->capq.streaming) + return 0; + + spin_lock_irqsave(&isp->lock, flags); + if (asd->streaming == ATOMISP_DEVICE_STREAMING_ENABLED) { + asd->streaming = ATOMISP_DEVICE_STREAMING_STOPPING; + first_streamoff = true; + } + spin_unlock_irqrestore(&isp->lock, flags); + + if (first_streamoff) { + /* if other streams are running, should not disable watch dog */ + rt_mutex_unlock(&isp->mutex); + atomisp_wdt_stop(asd, true); + + /* + * must stop sending pixels into GP_FIFO before stop + * the pipeline. + */ + if (isp->sw_contex.file_input) + v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + video, s_stream, 0); + + rt_mutex_lock(&isp->mutex); + atomisp_acc_unload_extensions(asd); + } + + spin_lock_irqsave(&isp->lock, flags); + if (atomisp_subdev_streaming_count(asd) == 1) + asd->streaming = ATOMISP_DEVICE_STREAMING_DISABLED; + spin_unlock_irqrestore(&isp->lock, flags); + + if (!first_streamoff) { + ret = videobuf_streamoff(&pipe->capq); + if (ret) + return ret; + goto stopsensor; + } + + atomisp_clear_css_buffer_counters(asd); + + if (!isp->sw_contex.file_input) + atomisp_css_irq_enable(isp, CSS_IRQ_INFO_CSS_RECEIVER_SOF, + false); + + if (asd->delayed_init == ATOMISP_DELAYED_INIT_QUEUED) { + cancel_work_sync(&asd->delayed_init_work); + asd->delayed_init = ATOMISP_DELAYED_INIT_NOT_QUEUED; + } + if (first_streamoff) { + css_pipe_id = atomisp_get_css_pipe_id(asd); + ret = atomisp_css_stop(asd, css_pipe_id, false); + } + /* cancel work queue*/ + if (asd->video_out_capture.users) { + capture_pipe = &asd->video_out_capture; + wake_up_interruptible(&capture_pipe->capq.wait); + } + if (asd->video_out_vf.users) { + vf_pipe = &asd->video_out_vf; + wake_up_interruptible(&vf_pipe->capq.wait); + } + if (asd->video_out_preview.users) { + preview_pipe = &asd->video_out_preview; + wake_up_interruptible(&preview_pipe->capq.wait); + } + if (asd->video_out_video_capture.users) { + video_pipe = &asd->video_out_video_capture; + wake_up_interruptible(&video_pipe->capq.wait); + } + ret = videobuf_streamoff(&pipe->capq); + if (ret) + return ret; + + /* cleanup css here */ + /* no need for this, as ISP will be reset anyway */ + /*atomisp_flush_bufs_in_css(isp);*/ + + spin_lock_irqsave(&pipe->irq_lock, flags); + list_for_each_entry_safe(vb, _vb, &pipe->activeq, queue) { + vb->state = VIDEOBUF_PREPARED; + list_del(&vb->queue); + } + list_for_each_entry_safe(vb, _vb, &pipe->buffers_waiting_for_param, queue) { + vb->state = VIDEOBUF_PREPARED; + list_del(&vb->queue); + pipe->frame_request_config_id[vb->i] = 0; + } + spin_unlock_irqrestore(&pipe->irq_lock, flags); + + atomisp_subdev_cleanup_pending_events(asd); +stopsensor: + if (atomisp_subdev_streaming_count(asd) + 1 + != atomisp_sensor_start_stream(asd)) + return 0; + + if (!isp->sw_contex.file_input) + ret = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + video, s_stream, 0); + + if (isp->flash) { + asd->params.num_flash_frames = 0; + asd->params.flash_state = ATOMISP_FLASH_IDLE; + } + + /* if other streams are running, isp should not be powered off */ + if (atomisp_streaming_count(isp)) { + atomisp_css_flush(isp); + return 0; + } + + /* Disable the CSI interface on ANN B0/K0 */ + if (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 << + ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0)) { + pci_write_config_word(isp->pdev, MRFLD_PCI_CSI_CONTROL, + isp->saved_regs.csi_control & + ~MRFLD_PCI_CSI_CONTROL_CSI_READY); + } + + if (atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, false)) + dev_warn(isp->dev, "DFS failed.\n"); + /* + * ISP work around, need to reset isp + * Is it correct time to reset ISP when first node does streamoff? + */ + if (isp->sw_contex.power_state == ATOM_ISP_POWER_UP) { + unsigned int i; + bool recreate_streams[MAX_STREAM_NUM] = {0}; + if (isp->isp_timeout) + dev_err(isp->dev, "%s: Resetting with WA activated", + __func__); + /* + * It is possible that the other asd stream is in the stage + * that v4l2_setfmt is just get called on it, which will + * create css stream on that stream. But at this point, there + * is no way to destroy the css stream created on that stream. + * + * So force stream destroy here. + */ + for (i = 0; i < isp->num_of_streams; i++) { + if (isp->asd[i].stream_prepared) { + atomisp_destroy_pipes_stream_force(&isp-> + asd[i]); + recreate_streams[i] = true; + } + } + + /* disable PUNIT/ISP acknowlede/handshake - SRSE=3 */ + pci_write_config_dword(isp->pdev, PCI_I_CONTROL, isp->saved_regs.i_control | + MRFLD_PCI_I_CONTROL_SRSE_RESET_MASK); + dev_err(isp->dev, "atomisp_reset"); + atomisp_reset(isp); + for (i = 0; i < isp->num_of_streams; i++) { + if (recreate_streams[i]) + atomisp_create_pipes_stream(&isp->asd[i]); + } + isp->isp_timeout = false; + } + return ret; +} + +static int atomisp_streamoff(struct file *file, void *fh, + enum v4l2_buf_type type) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + int rval; + + mutex_lock(&isp->streamoff_mutex); + rt_mutex_lock(&isp->mutex); + rval = __atomisp_streamoff(file, fh, type); + rt_mutex_unlock(&isp->mutex); + mutex_unlock(&isp->streamoff_mutex); + + return rval; +} + +/* + * To get the current value of a control. + * applications initialize the id field of a struct v4l2_control and + * call this ioctl with a pointer to this structure + */ +static int atomisp_g_ctrl(struct file *file, void *fh, + struct v4l2_control *control) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + struct atomisp_device *isp = video_get_drvdata(vdev); + int i, ret = -EINVAL; + + for (i = 0; i < ctrls_num; i++) { + if (ci_v4l2_controls[i].id == control->id) { + ret = 0; + break; + } + } + + if (ret) + return ret; + + rt_mutex_lock(&isp->mutex); + + switch (control->id) { + case V4L2_CID_IRIS_ABSOLUTE: + case V4L2_CID_EXPOSURE_ABSOLUTE: + case V4L2_CID_FNUMBER_ABSOLUTE: + case V4L2_CID_2A_STATUS: + case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE: + case V4L2_CID_EXPOSURE: + case V4L2_CID_EXPOSURE_AUTO: + case V4L2_CID_SCENE_MODE: + case V4L2_CID_ISO_SENSITIVITY: + case V4L2_CID_ISO_SENSITIVITY_AUTO: + case V4L2_CID_CONTRAST: + case V4L2_CID_SATURATION: + case V4L2_CID_SHARPNESS: + case V4L2_CID_3A_LOCK: + case V4L2_CID_EXPOSURE_ZONE_NUM: + case V4L2_CID_TEST_PATTERN: + case V4L2_CID_TEST_PATTERN_COLOR_R: + case V4L2_CID_TEST_PATTERN_COLOR_GR: + case V4L2_CID_TEST_PATTERN_COLOR_GB: + case V4L2_CID_TEST_PATTERN_COLOR_B: + rt_mutex_unlock(&isp->mutex); + return v4l2_g_ctrl(isp->inputs[asd->input_curr].camera-> + ctrl_handler, control); + case V4L2_CID_COLORFX: + ret = atomisp_color_effect(asd, 0, &control->value); + break; + case V4L2_CID_ATOMISP_BAD_PIXEL_DETECTION: + ret = atomisp_bad_pixel(asd, 0, &control->value); + break; + case V4L2_CID_ATOMISP_POSTPROCESS_GDC_CAC: + ret = atomisp_gdc_cac(asd, 0, &control->value); + break; + case V4L2_CID_ATOMISP_VIDEO_STABLIZATION: + ret = atomisp_video_stable(asd, 0, &control->value); + break; + case V4L2_CID_ATOMISP_FIXED_PATTERN_NR: + ret = atomisp_fixed_pattern(asd, 0, &control->value); + break; + case V4L2_CID_ATOMISP_FALSE_COLOR_CORRECTION: + ret = atomisp_false_color(asd, 0, &control->value); + break; + case V4L2_CID_ATOMISP_LOW_LIGHT: + ret = atomisp_low_light(asd, 0, &control->value); + break; + default: + ret = -EINVAL; + break; + } + + rt_mutex_unlock(&isp->mutex); + return ret; +} + +/* + * To change the value of a control. + * applications initialize the id and value fields of a struct v4l2_control + * and call this ioctl. + */ +static int atomisp_s_ctrl(struct file *file, void *fh, + struct v4l2_control *control) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + struct atomisp_device *isp = video_get_drvdata(vdev); + int i, ret = -EINVAL; + + for (i = 0; i < ctrls_num; i++) { + if (ci_v4l2_controls[i].id == control->id) { + ret = 0; + break; + } + } + + if (ret) + return ret; + + rt_mutex_lock(&isp->mutex); + switch (control->id) { + case V4L2_CID_AUTO_N_PRESET_WHITE_BALANCE: + case V4L2_CID_EXPOSURE: + case V4L2_CID_EXPOSURE_AUTO: + case V4L2_CID_EXPOSURE_AUTO_PRIORITY: + case V4L2_CID_SCENE_MODE: + case V4L2_CID_ISO_SENSITIVITY: + case V4L2_CID_ISO_SENSITIVITY_AUTO: + case V4L2_CID_POWER_LINE_FREQUENCY: + case V4L2_CID_EXPOSURE_METERING: + case V4L2_CID_CONTRAST: + case V4L2_CID_SATURATION: + case V4L2_CID_SHARPNESS: + case V4L2_CID_3A_LOCK: + case V4L2_CID_COLORFX_CBCR: + case V4L2_CID_TEST_PATTERN: + case V4L2_CID_TEST_PATTERN_COLOR_R: + case V4L2_CID_TEST_PATTERN_COLOR_GR: + case V4L2_CID_TEST_PATTERN_COLOR_GB: + case V4L2_CID_TEST_PATTERN_COLOR_B: + rt_mutex_unlock(&isp->mutex); + return v4l2_s_ctrl(NULL, + isp->inputs[asd->input_curr].camera-> + ctrl_handler, control); + case V4L2_CID_COLORFX: + ret = atomisp_color_effect(asd, 1, &control->value); + break; + case V4L2_CID_ATOMISP_BAD_PIXEL_DETECTION: + ret = atomisp_bad_pixel(asd, 1, &control->value); + break; + case V4L2_CID_ATOMISP_POSTPROCESS_GDC_CAC: + ret = atomisp_gdc_cac(asd, 1, &control->value); + break; + case V4L2_CID_ATOMISP_VIDEO_STABLIZATION: + ret = atomisp_video_stable(asd, 1, &control->value); + break; + case V4L2_CID_ATOMISP_FIXED_PATTERN_NR: + ret = atomisp_fixed_pattern(asd, 1, &control->value); + break; + case V4L2_CID_ATOMISP_FALSE_COLOR_CORRECTION: + ret = atomisp_false_color(asd, 1, &control->value); + break; + case V4L2_CID_REQUEST_FLASH: + ret = atomisp_flash_enable(asd, control->value); + break; + case V4L2_CID_ATOMISP_LOW_LIGHT: + ret = atomisp_low_light(asd, 1, &control->value); + break; + default: + ret = -EINVAL; + break; + } + rt_mutex_unlock(&isp->mutex); + return ret; +} +/* + * To query the attributes of a control. + * applications set the id field of a struct v4l2_queryctrl and call the + * this ioctl with a pointer to this structure. The driver fills + * the rest of the structure. + */ +static int atomisp_queryctl(struct file *file, void *fh, + struct v4l2_queryctrl *qc) +{ + int i, ret = -EINVAL; + struct video_device *vdev = video_devdata(file); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + struct atomisp_device *isp = video_get_drvdata(vdev); + + switch (qc->id) { + case V4L2_CID_FOCUS_ABSOLUTE: + case V4L2_CID_FOCUS_RELATIVE: + case V4L2_CID_FOCUS_STATUS: +#ifndef ISP2401 + return v4l2_queryctrl(isp->inputs[asd->input_curr].camera-> + ctrl_handler, qc); +#else + if (isp->motor) + return v4l2_queryctrl(isp->motor->ctrl_handler, qc); + else + return v4l2_queryctrl(isp->inputs[asd->input_curr]. + camera->ctrl_handler, qc); +#endif + } + + if (qc->id & V4L2_CTRL_FLAG_NEXT_CTRL) + return ret; + + for (i = 0; i < ctrls_num; i++) { + if (ci_v4l2_controls[i].id == qc->id) { + memcpy(qc, &ci_v4l2_controls[i], + sizeof(struct v4l2_queryctrl)); + qc->reserved[0] = 0; + ret = 0; + break; + } + } + if (ret != 0) + qc->flags = V4L2_CTRL_FLAG_DISABLED; + + return ret; +} + +static int atomisp_camera_g_ext_ctrls(struct file *file, void *fh, + struct v4l2_ext_controls *c) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + struct atomisp_device *isp = video_get_drvdata(vdev); + struct v4l2_control ctrl; + int i; + int ret = 0; + + for (i = 0; i < c->count; i++) { + ctrl.id = c->controls[i].id; + ctrl.value = c->controls[i].value; + switch (ctrl.id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + case V4L2_CID_EXPOSURE_AUTO: + case V4L2_CID_IRIS_ABSOLUTE: + case V4L2_CID_FNUMBER_ABSOLUTE: + case V4L2_CID_BIN_FACTOR_HORZ: + case V4L2_CID_BIN_FACTOR_VERT: + case V4L2_CID_3A_LOCK: + case V4L2_CID_TEST_PATTERN: + case V4L2_CID_TEST_PATTERN_COLOR_R: + case V4L2_CID_TEST_PATTERN_COLOR_GR: + case V4L2_CID_TEST_PATTERN_COLOR_GB: + case V4L2_CID_TEST_PATTERN_COLOR_B: + /* + * Exposure related control will be handled by sensor + * driver + */ + ret = + v4l2_g_ctrl(isp->inputs[asd->input_curr].camera-> + ctrl_handler, &ctrl); + break; + case V4L2_CID_FOCUS_ABSOLUTE: + case V4L2_CID_FOCUS_RELATIVE: + case V4L2_CID_FOCUS_STATUS: + case V4L2_CID_FOCUS_AUTO: +#ifndef ISP2401 + if (isp->inputs[asd->input_curr].motor) +#else + if (isp->motor) +#endif + ret = +#ifndef ISP2401 + v4l2_g_ctrl(isp->inputs[asd->input_curr]. + motor->ctrl_handler, &ctrl); +#else + v4l2_g_ctrl(isp->motor->ctrl_handler, + &ctrl); +#endif + else + ret = + v4l2_g_ctrl(isp->inputs[asd->input_curr]. + camera->ctrl_handler, &ctrl); + break; + case V4L2_CID_FLASH_STATUS: + case V4L2_CID_FLASH_INTENSITY: + case V4L2_CID_FLASH_TORCH_INTENSITY: + case V4L2_CID_FLASH_INDICATOR_INTENSITY: + case V4L2_CID_FLASH_TIMEOUT: + case V4L2_CID_FLASH_STROBE: + case V4L2_CID_FLASH_MODE: + case V4L2_CID_FLASH_STATUS_REGISTER: + if (isp->flash) + ret = + v4l2_g_ctrl(isp->flash->ctrl_handler, + &ctrl); + break; + case V4L2_CID_ZOOM_ABSOLUTE: + rt_mutex_lock(&isp->mutex); + ret = atomisp_digital_zoom(asd, 0, &ctrl.value); + rt_mutex_unlock(&isp->mutex); + break; + case V4L2_CID_G_SKIP_FRAMES: + ret = v4l2_subdev_call( + isp->inputs[asd->input_curr].camera, + sensor, g_skip_frames, (u32 *)&ctrl.value); + break; + default: + ret = -EINVAL; + } + + if (ret) { + c->error_idx = i; + break; + } + c->controls[i].value = ctrl.value; + } + return ret; +} + +/* This ioctl allows the application to get multiple controls by class */ +static int atomisp_g_ext_ctrls(struct file *file, void *fh, + struct v4l2_ext_controls *c) +{ + struct v4l2_control ctrl; + int i, ret = 0; + + /* input_lock is not need for the Camera releated IOCTLs + * The input_lock downgrade the FPS of 3A*/ + ret = atomisp_camera_g_ext_ctrls(file, fh, c); + if (ret != -EINVAL) + return ret; + + for (i = 0; i < c->count; i++) { + ctrl.id = c->controls[i].id; + ctrl.value = c->controls[i].value; + ret = atomisp_g_ctrl(file, fh, &ctrl); + c->controls[i].value = ctrl.value; + if (ret) { + c->error_idx = i; + break; + } + } + return ret; +} + +static int atomisp_camera_s_ext_ctrls(struct file *file, void *fh, + struct v4l2_ext_controls *c) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + struct atomisp_device *isp = video_get_drvdata(vdev); + struct v4l2_control ctrl; + int i; + int ret = 0; + + for (i = 0; i < c->count; i++) { + struct v4l2_ctrl *ctr; + + ctrl.id = c->controls[i].id; + ctrl.value = c->controls[i].value; + switch (ctrl.id) { + case V4L2_CID_EXPOSURE_ABSOLUTE: + case V4L2_CID_EXPOSURE_AUTO: + case V4L2_CID_EXPOSURE_METERING: + case V4L2_CID_IRIS_ABSOLUTE: + case V4L2_CID_FNUMBER_ABSOLUTE: + case V4L2_CID_VCM_TIMEING: + case V4L2_CID_VCM_SLEW: + case V4L2_CID_3A_LOCK: + case V4L2_CID_TEST_PATTERN: + case V4L2_CID_TEST_PATTERN_COLOR_R: + case V4L2_CID_TEST_PATTERN_COLOR_GR: + case V4L2_CID_TEST_PATTERN_COLOR_GB: + case V4L2_CID_TEST_PATTERN_COLOR_B: + ret = v4l2_s_ctrl(NULL, + isp->inputs[asd->input_curr].camera-> + ctrl_handler, &ctrl); + break; + case V4L2_CID_FOCUS_ABSOLUTE: + case V4L2_CID_FOCUS_RELATIVE: + case V4L2_CID_FOCUS_STATUS: + case V4L2_CID_FOCUS_AUTO: +#ifndef ISP2401 + if (isp->inputs[asd->input_curr].motor) +#else + if (isp->motor) +#endif + ret = v4l2_s_ctrl(NULL, +#ifndef ISP2401 + isp->inputs[asd->input_curr]. + motor->ctrl_handler, &ctrl); +#else + isp->motor->ctrl_handler, + &ctrl); +#endif + else + ret = v4l2_s_ctrl(NULL, + isp->inputs[asd->input_curr]. + camera->ctrl_handler, &ctrl); + break; + case V4L2_CID_FLASH_STATUS: + case V4L2_CID_FLASH_INTENSITY: + case V4L2_CID_FLASH_TORCH_INTENSITY: + case V4L2_CID_FLASH_INDICATOR_INTENSITY: + case V4L2_CID_FLASH_TIMEOUT: + case V4L2_CID_FLASH_STROBE: + case V4L2_CID_FLASH_MODE: + case V4L2_CID_FLASH_STATUS_REGISTER: + rt_mutex_lock(&isp->mutex); + if (isp->flash) { + ret = + v4l2_s_ctrl(NULL, isp->flash->ctrl_handler, + &ctrl); + /* When flash mode is changed we need to reset + * flash state */ + if (ctrl.id == V4L2_CID_FLASH_MODE) { + asd->params.flash_state = + ATOMISP_FLASH_IDLE; + asd->params.num_flash_frames = 0; + } + } + rt_mutex_unlock(&isp->mutex); + break; + case V4L2_CID_ZOOM_ABSOLUTE: + rt_mutex_lock(&isp->mutex); + ret = atomisp_digital_zoom(asd, 1, &ctrl.value); + rt_mutex_unlock(&isp->mutex); + break; + default: + ctr = v4l2_ctrl_find(&asd->ctrl_handler, ctrl.id); + if (ctr) + ret = v4l2_ctrl_s_ctrl(ctr, ctrl.value); + else + ret = -EINVAL; + } + + if (ret) { + c->error_idx = i; + break; + } + c->controls[i].value = ctrl.value; + } + return ret; +} + +/* This ioctl allows the application to set multiple controls by class */ +static int atomisp_s_ext_ctrls(struct file *file, void *fh, + struct v4l2_ext_controls *c) +{ + struct v4l2_control ctrl; + int i, ret = 0; + + /* input_lock is not need for the Camera releated IOCTLs + * The input_lock downgrade the FPS of 3A*/ + ret = atomisp_camera_s_ext_ctrls(file, fh, c); + if (ret != -EINVAL) + return ret; + + for (i = 0; i < c->count; i++) { + ctrl.id = c->controls[i].id; + ctrl.value = c->controls[i].value; + ret = atomisp_s_ctrl(file, fh, &ctrl); + c->controls[i].value = ctrl.value; + if (ret) { + c->error_idx = i; + break; + } + } + return ret; +} + +/* + * vidioc_g/s_param are used to switch isp running mode + */ +static int atomisp_g_parm(struct file *file, void *fh, + struct v4l2_streamparm *parm) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + struct atomisp_device *isp = video_get_drvdata(vdev); + + if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + dev_err(isp->dev, "unsupport v4l2 buf type\n"); + return -EINVAL; + } + + rt_mutex_lock(&isp->mutex); + parm->parm.capture.capturemode = asd->run_mode->val; + rt_mutex_unlock(&isp->mutex); + + return 0; +} + +static int atomisp_s_parm(struct file *file, void *fh, + struct v4l2_streamparm *parm) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_sub_device *asd = atomisp_to_video_pipe(vdev)->asd; + int mode; + int rval; + int fps; + + if (parm->type != V4L2_BUF_TYPE_VIDEO_CAPTURE) { + dev_err(isp->dev, "unsupport v4l2 buf type\n"); + return -EINVAL; + } + + rt_mutex_lock(&isp->mutex); + + asd->high_speed_mode = false; + switch (parm->parm.capture.capturemode) { + case CI_MODE_NONE: { + struct v4l2_subdev_frame_interval fi = {0}; + + fi.interval = parm->parm.capture.timeperframe; + + rval = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + video, s_frame_interval, &fi); + if (!rval) + parm->parm.capture.timeperframe = fi.interval; + + if (fi.interval.numerator != 0) { + fps = fi.interval.denominator / fi.interval.numerator; + if (fps > 30) + asd->high_speed_mode = true; + } + + goto out; + } + case CI_MODE_VIDEO: + mode = ATOMISP_RUN_MODE_VIDEO; + break; + case CI_MODE_STILL_CAPTURE: + mode = ATOMISP_RUN_MODE_STILL_CAPTURE; + break; + case CI_MODE_CONTINUOUS: + mode = ATOMISP_RUN_MODE_CONTINUOUS_CAPTURE; + break; + case CI_MODE_PREVIEW: + mode = ATOMISP_RUN_MODE_PREVIEW; + break; + default: + rval = -EINVAL; + goto out; + } + + rval = v4l2_ctrl_s_ctrl(asd->run_mode, mode); + +out: + rt_mutex_unlock(&isp->mutex); + + return rval == -ENOIOCTLCMD ? 0 : rval; +} + +static int atomisp_s_parm_file(struct file *file, void *fh, + struct v4l2_streamparm *parm) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + + if (parm->type != V4L2_BUF_TYPE_VIDEO_OUTPUT) { + dev_err(isp->dev, "unsupport v4l2 buf type for output\n"); + return -EINVAL; + } + + rt_mutex_lock(&isp->mutex); + isp->sw_contex.file_input = 1; + rt_mutex_unlock(&isp->mutex); + + return 0; +} + +static long atomisp_vidioc_default(struct file *file, void *fh, + bool valid_prio, unsigned int cmd, void *arg) +{ + struct video_device *vdev = video_devdata(file); + struct atomisp_device *isp = video_get_drvdata(vdev); + struct atomisp_sub_device *asd; + bool acc_node; + int err; + + acc_node = !strncmp(vdev->name, "ATOMISP ISP ACC", + sizeof(vdev->name)); + if (acc_node) + asd = atomisp_to_acc_pipe(vdev)->asd; + else + asd = atomisp_to_video_pipe(vdev)->asd; + + switch (cmd) { + case ATOMISP_IOC_G_MOTOR_PRIV_INT_DATA: + case ATOMISP_IOC_S_EXPOSURE: + case ATOMISP_IOC_G_SENSOR_CALIBRATION_GROUP: + case ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA: + case ATOMISP_IOC_EXT_ISP_CTRL: + case ATOMISP_IOC_G_SENSOR_AE_BRACKETING_INFO: + case ATOMISP_IOC_S_SENSOR_AE_BRACKETING_MODE: + case ATOMISP_IOC_G_SENSOR_AE_BRACKETING_MODE: + case ATOMISP_IOC_S_SENSOR_AE_BRACKETING_LUT: + case ATOMISP_IOC_S_SENSOR_EE_CONFIG: +#ifdef ISP2401 + case ATOMISP_IOC_G_UPDATE_EXPOSURE: +#endif + /* we do not need take isp->mutex for these IOCTLs */ + break; + default: + rt_mutex_lock(&isp->mutex); + break; + } + switch (cmd) { +#ifdef ISP2401 + case ATOMISP_IOC_S_SENSOR_RUNMODE: + err = atomisp_set_sensor_runmode(asd, arg); + break; + +#endif + case ATOMISP_IOC_G_XNR: + err = atomisp_xnr(asd, 0, arg); + break; + + case ATOMISP_IOC_S_XNR: + err = atomisp_xnr(asd, 1, arg); + break; + + case ATOMISP_IOC_G_NR: + err = atomisp_nr(asd, 0, arg); + break; + + case ATOMISP_IOC_S_NR: + err = atomisp_nr(asd, 1, arg); + break; + + case ATOMISP_IOC_G_TNR: + err = atomisp_tnr(asd, 0, arg); + break; + + case ATOMISP_IOC_S_TNR: + err = atomisp_tnr(asd, 1, arg); + break; + + case ATOMISP_IOC_G_BLACK_LEVEL_COMP: + err = atomisp_black_level(asd, 0, arg); + break; + + case ATOMISP_IOC_S_BLACK_LEVEL_COMP: + err = atomisp_black_level(asd, 1, arg); + break; + + case ATOMISP_IOC_G_EE: + err = atomisp_ee(asd, 0, arg); + break; + + case ATOMISP_IOC_S_EE: + err = atomisp_ee(asd, 1, arg); + break; + + case ATOMISP_IOC_G_DIS_STAT: + err = atomisp_get_dis_stat(asd, arg); + break; + + case ATOMISP_IOC_G_DVS2_BQ_RESOLUTIONS: + err = atomisp_get_dvs2_bq_resolutions(asd, arg); + break; + + case ATOMISP_IOC_S_DIS_COEFS: + err = atomisp_css_cp_dvs2_coefs(asd, arg, + &asd->params.css_param, true); + if (!err && arg) + asd->params.css_update_params_needed = true; + break; + + case ATOMISP_IOC_S_DIS_VECTOR: + err = atomisp_cp_dvs_6axis_config(asd, arg, + &asd->params.css_param, true); + if (!err && arg) + asd->params.css_update_params_needed = true; + break; + + case ATOMISP_IOC_G_ISP_PARM: + err = atomisp_param(asd, 0, arg); + break; + + case ATOMISP_IOC_S_ISP_PARM: + err = atomisp_param(asd, 1, arg); + break; + + case ATOMISP_IOC_G_3A_STAT: + err = atomisp_3a_stat(asd, 0, arg); + break; + + case ATOMISP_IOC_G_ISP_GAMMA: + err = atomisp_gamma(asd, 0, arg); + break; + + case ATOMISP_IOC_S_ISP_GAMMA: + err = atomisp_gamma(asd, 1, arg); + break; + + case ATOMISP_IOC_G_ISP_GDC_TAB: + err = atomisp_gdc_cac_table(asd, 0, arg); + break; + + case ATOMISP_IOC_S_ISP_GDC_TAB: + err = atomisp_gdc_cac_table(asd, 1, arg); + break; + + case ATOMISP_IOC_G_ISP_MACC: + err = atomisp_macc_table(asd, 0, arg); + break; + + case ATOMISP_IOC_S_ISP_MACC: + err = atomisp_macc_table(asd, 1, arg); + break; + + case ATOMISP_IOC_G_ISP_BAD_PIXEL_DETECTION: + err = atomisp_bad_pixel_param(asd, 0, arg); + break; + + case ATOMISP_IOC_S_ISP_BAD_PIXEL_DETECTION: + err = atomisp_bad_pixel_param(asd, 1, arg); + break; + + case ATOMISP_IOC_G_ISP_FALSE_COLOR_CORRECTION: + err = atomisp_false_color_param(asd, 0, arg); + break; + + case ATOMISP_IOC_S_ISP_FALSE_COLOR_CORRECTION: + err = atomisp_false_color_param(asd, 1, arg); + break; + + case ATOMISP_IOC_G_ISP_CTC: + err = atomisp_ctc(asd, 0, arg); + break; + + case ATOMISP_IOC_S_ISP_CTC: + err = atomisp_ctc(asd, 1, arg); + break; + + case ATOMISP_IOC_G_ISP_WHITE_BALANCE: + err = atomisp_white_balance_param(asd, 0, arg); + break; + + case ATOMISP_IOC_S_ISP_WHITE_BALANCE: + err = atomisp_white_balance_param(asd, 1, arg); + break; + + case ATOMISP_IOC_G_3A_CONFIG: + err = atomisp_3a_config_param(asd, 0, arg); + break; + + case ATOMISP_IOC_S_3A_CONFIG: + err = atomisp_3a_config_param(asd, 1, arg); + break; + + case ATOMISP_IOC_S_ISP_FPN_TABLE: + err = atomisp_fixed_pattern_table(asd, arg); + break; + + case ATOMISP_IOC_ISP_MAKERNOTE: + err = atomisp_exif_makernote(asd, arg); + break; + + case ATOMISP_IOC_G_SENSOR_MODE_DATA: + err = atomisp_get_sensor_mode_data(asd, arg); + break; + + case ATOMISP_IOC_G_MOTOR_PRIV_INT_DATA: +#ifndef ISP2401 + if (isp->inputs[asd->input_curr].motor) +#else + if (isp->motor) +#endif + err = v4l2_subdev_call( +#ifndef ISP2401 + isp->inputs[asd->input_curr].motor, +#else + isp->motor, +#endif + core, ioctl, cmd, arg); + else + err = v4l2_subdev_call( + isp->inputs[asd->input_curr].camera, + core, ioctl, cmd, arg); + break; + + case ATOMISP_IOC_S_EXPOSURE: + case ATOMISP_IOC_G_SENSOR_CALIBRATION_GROUP: + case ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA: + case ATOMISP_IOC_G_SENSOR_AE_BRACKETING_INFO: + case ATOMISP_IOC_S_SENSOR_AE_BRACKETING_MODE: + case ATOMISP_IOC_G_SENSOR_AE_BRACKETING_MODE: + case ATOMISP_IOC_S_SENSOR_AE_BRACKETING_LUT: +#ifdef ISP2401 + case ATOMISP_IOC_G_UPDATE_EXPOSURE: +#endif + err = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + core, ioctl, cmd, arg); + break; + + case ATOMISP_IOC_ACC_LOAD: + err = atomisp_acc_load(asd, arg); + break; + + case ATOMISP_IOC_ACC_LOAD_TO_PIPE: + err = atomisp_acc_load_to_pipe(asd, arg); + break; + + case ATOMISP_IOC_ACC_UNLOAD: + err = atomisp_acc_unload(asd, arg); + break; + + case ATOMISP_IOC_ACC_START: + err = atomisp_acc_start(asd, arg); + break; + + case ATOMISP_IOC_ACC_WAIT: + err = atomisp_acc_wait(asd, arg); + break; + + case ATOMISP_IOC_ACC_MAP: + err = atomisp_acc_map(asd, arg); + break; + + case ATOMISP_IOC_ACC_UNMAP: + err = atomisp_acc_unmap(asd, arg); + break; + + case ATOMISP_IOC_ACC_S_MAPPED_ARG: + err = atomisp_acc_s_mapped_arg(asd, arg); + break; + + case ATOMISP_IOC_S_ISP_SHD_TAB: + err = atomisp_set_shading_table(asd, arg); + break; + + case ATOMISP_IOC_G_ISP_GAMMA_CORRECTION: + err = atomisp_gamma_correction(asd, 0, arg); + break; + + case ATOMISP_IOC_S_ISP_GAMMA_CORRECTION: + err = atomisp_gamma_correction(asd, 1, arg); + break; + + case ATOMISP_IOC_S_PARAMETERS: + err = atomisp_set_parameters(vdev, arg); + break; + + case ATOMISP_IOC_S_CONT_CAPTURE_CONFIG: + err = atomisp_offline_capture_configure(asd, arg); + break; + case ATOMISP_IOC_G_METADATA: + err = atomisp_get_metadata(asd, 0, arg); + break; + case ATOMISP_IOC_G_METADATA_BY_TYPE: + err = atomisp_get_metadata_by_type(asd, 0, arg); + break; + case ATOMISP_IOC_EXT_ISP_CTRL: + err = v4l2_subdev_call(isp->inputs[asd->input_curr].camera, + core, ioctl, cmd, arg); + break; + case ATOMISP_IOC_EXP_ID_UNLOCK: + err = atomisp_exp_id_unlock(asd, arg); + break; + case ATOMISP_IOC_EXP_ID_CAPTURE: + err = atomisp_exp_id_capture(asd, arg); + break; + case ATOMISP_IOC_S_ENABLE_DZ_CAPT_PIPE: + err = atomisp_enable_dz_capt_pipe(asd, arg); + break; + case ATOMISP_IOC_G_FORMATS_CONFIG: + err = atomisp_formats(asd, 0, arg); + break; + + case ATOMISP_IOC_S_FORMATS_CONFIG: + err = atomisp_formats(asd, 1, arg); + break; + case ATOMISP_IOC_S_EXPOSURE_WINDOW: + err = atomisp_s_ae_window(asd, arg); + break; + case ATOMISP_IOC_S_ACC_STATE: + err = atomisp_acc_set_state(asd, arg); + break; + case ATOMISP_IOC_G_ACC_STATE: + err = atomisp_acc_get_state(asd, arg); + break; + case ATOMISP_IOC_INJECT_A_FAKE_EVENT: + err = atomisp_inject_a_fake_event(asd, arg); + break; + case ATOMISP_IOC_G_INVALID_FRAME_NUM: + err = atomisp_get_invalid_frame_num(vdev, arg); + break; + case ATOMISP_IOC_S_ARRAY_RESOLUTION: + err = atomisp_set_array_res(asd, arg); + break; + default: + err = -EINVAL; + break; + } + + switch (cmd) { + case ATOMISP_IOC_G_MOTOR_PRIV_INT_DATA: + case ATOMISP_IOC_S_EXPOSURE: + case ATOMISP_IOC_G_SENSOR_CALIBRATION_GROUP: + case ATOMISP_IOC_G_SENSOR_PRIV_INT_DATA: + case ATOMISP_IOC_EXT_ISP_CTRL: + case ATOMISP_IOC_G_SENSOR_AE_BRACKETING_INFO: + case ATOMISP_IOC_S_SENSOR_AE_BRACKETING_MODE: + case ATOMISP_IOC_G_SENSOR_AE_BRACKETING_MODE: + case ATOMISP_IOC_S_SENSOR_AE_BRACKETING_LUT: +#ifdef ISP2401 + case ATOMISP_IOC_G_UPDATE_EXPOSURE: +#endif + break; + default: + rt_mutex_unlock(&isp->mutex); + break; + } + return err; +} + +const struct v4l2_ioctl_ops atomisp_ioctl_ops = { + .vidioc_querycap = atomisp_querycap, + .vidioc_enum_input = atomisp_enum_input, + .vidioc_g_input = atomisp_g_input, + .vidioc_s_input = atomisp_s_input, + .vidioc_queryctrl = atomisp_queryctl, + .vidioc_s_ctrl = atomisp_s_ctrl, + .vidioc_g_ctrl = atomisp_g_ctrl, + .vidioc_s_ext_ctrls = atomisp_s_ext_ctrls, + .vidioc_g_ext_ctrls = atomisp_g_ext_ctrls, + .vidioc_enum_fmt_vid_cap = atomisp_enum_fmt_cap, + .vidioc_try_fmt_vid_cap = atomisp_try_fmt_cap, + .vidioc_g_fmt_vid_cap = atomisp_g_fmt_cap, + .vidioc_s_fmt_vid_cap = atomisp_s_fmt_cap, + .vidioc_reqbufs = atomisp_reqbufs, + .vidioc_querybuf = atomisp_querybuf, + .vidioc_qbuf = atomisp_qbuf, + .vidioc_dqbuf = atomisp_dqbuf, + .vidioc_streamon = atomisp_streamon, + .vidioc_streamoff = atomisp_streamoff, + .vidioc_default = atomisp_vidioc_default, + .vidioc_s_parm = atomisp_s_parm, + .vidioc_g_parm = atomisp_g_parm, +}; + +const struct v4l2_ioctl_ops atomisp_file_ioctl_ops = { + .vidioc_querycap = atomisp_querycap, + .vidioc_g_fmt_vid_out = atomisp_g_fmt_file, + .vidioc_s_fmt_vid_out = atomisp_s_fmt_file, + .vidioc_s_parm = atomisp_s_parm_file, + .vidioc_reqbufs = atomisp_reqbufs_file, + .vidioc_querybuf = atomisp_querybuf_file, + .vidioc_qbuf = atomisp_qbuf_file, +}; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_ioctl.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_ioctl.h new file mode 100644 index 0000000000000000000000000000000000000000..fb5fadb5332ba59de3cd4fd83680d66af9951501 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_ioctl.h @@ -0,0 +1,73 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __ATOMISP_IOCTL_H__ +#define __ATOMISP_IOCTL_H__ + +#include "ia_css.h" + +struct atomisp_device; +struct atomisp_video_pipe; + +extern const struct atomisp_format_bridge atomisp_output_fmts[]; + +const struct atomisp_format_bridge *atomisp_get_format_bridge( + unsigned int pixelformat); +#ifndef ISP2401 +const struct atomisp_format_bridge *atomisp_get_format_bridge_from_mbus( + u32 mbus_code); +#else +const struct atomisp_format_bridge *atomisp_get_format_bridge_from_mbus(u32 + mbus_code); +#endif + +int atomisp_alloc_css_stat_bufs(struct atomisp_sub_device *asd, + uint16_t stream_id); + +int __atomisp_streamoff(struct file *file, void *fh, enum v4l2_buf_type type); +int __atomisp_reqbufs(struct file *file, void *fh, + struct v4l2_requestbuffers *req); + +int atomisp_reqbufs(struct file *file, void *fh, + struct v4l2_requestbuffers *req); + +enum atomisp_css_pipe_id atomisp_get_css_pipe_id(struct atomisp_sub_device + *asd); + +void atomisp_videobuf_free_buf(struct videobuf_buffer *vb); + +extern const struct v4l2_file_operations atomisp_file_fops; + +extern const struct v4l2_ioctl_ops atomisp_ioctl_ops; + +extern const struct v4l2_ioctl_ops atomisp_file_ioctl_ops; + +unsigned int atomisp_streaming_count(struct atomisp_device *isp); + +unsigned int atomisp_is_acc_enabled(struct atomisp_device *isp); +/* compat_ioctl for 32bit userland app and 64bit kernel */ +long atomisp_compat_ioctl32(struct file *file, + unsigned int cmd, unsigned long arg); + +int atomisp_stream_on_master_slave_sensor(struct atomisp_device *isp, bool isp_timeout); +#endif /* __ATOMISP_IOCTL_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_subdev.c b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_subdev.c new file mode 100644 index 0000000000000000000000000000000000000000..a62320bf0a15c0b650a5c1e2879045ec352849f4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_subdev.c @@ -0,0 +1,1516 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include "atomisp_cmd.h" +#include "atomisp_common.h" +#include "atomisp_compat.h" +#include "atomisp_internal.h" + +const struct atomisp_in_fmt_conv atomisp_in_fmt_conv[] = { + { MEDIA_BUS_FMT_SBGGR8_1X8, 8, 8, ATOMISP_INPUT_FORMAT_RAW_8, CSS_BAYER_ORDER_BGGR, CSS_FORMAT_RAW_8 }, + { MEDIA_BUS_FMT_SGBRG8_1X8, 8, 8, ATOMISP_INPUT_FORMAT_RAW_8, CSS_BAYER_ORDER_GBRG, CSS_FORMAT_RAW_8 }, + { MEDIA_BUS_FMT_SGRBG8_1X8, 8, 8, ATOMISP_INPUT_FORMAT_RAW_8, CSS_BAYER_ORDER_GRBG, CSS_FORMAT_RAW_8 }, + { MEDIA_BUS_FMT_SRGGB8_1X8, 8, 8, ATOMISP_INPUT_FORMAT_RAW_8, CSS_BAYER_ORDER_RGGB, CSS_FORMAT_RAW_8 }, + { MEDIA_BUS_FMT_SBGGR10_1X10, 10, 10, ATOMISP_INPUT_FORMAT_RAW_10, CSS_BAYER_ORDER_BGGR, CSS_FORMAT_RAW_10 }, + { MEDIA_BUS_FMT_SGBRG10_1X10, 10, 10, ATOMISP_INPUT_FORMAT_RAW_10, CSS_BAYER_ORDER_GBRG, CSS_FORMAT_RAW_10 }, + { MEDIA_BUS_FMT_SGRBG10_1X10, 10, 10, ATOMISP_INPUT_FORMAT_RAW_10, CSS_BAYER_ORDER_GRBG, CSS_FORMAT_RAW_10 }, + { MEDIA_BUS_FMT_SRGGB10_1X10, 10, 10, ATOMISP_INPUT_FORMAT_RAW_10, CSS_BAYER_ORDER_RGGB, CSS_FORMAT_RAW_10 }, + { MEDIA_BUS_FMT_SBGGR12_1X12, 12, 12, ATOMISP_INPUT_FORMAT_RAW_12, CSS_BAYER_ORDER_BGGR, CSS_FORMAT_RAW_12 }, + { MEDIA_BUS_FMT_SGBRG12_1X12, 12, 12, ATOMISP_INPUT_FORMAT_RAW_12, CSS_BAYER_ORDER_GBRG, CSS_FORMAT_RAW_12 }, + { MEDIA_BUS_FMT_SGRBG12_1X12, 12, 12, ATOMISP_INPUT_FORMAT_RAW_12, CSS_BAYER_ORDER_GRBG, CSS_FORMAT_RAW_12 }, + { MEDIA_BUS_FMT_SRGGB12_1X12, 12, 12, ATOMISP_INPUT_FORMAT_RAW_12, CSS_BAYER_ORDER_RGGB, CSS_FORMAT_RAW_12 }, + { MEDIA_BUS_FMT_UYVY8_1X16, 8, 8, ATOMISP_INPUT_FORMAT_YUV422_8, 0, IA_CSS_STREAM_FORMAT_YUV422_8 }, + { MEDIA_BUS_FMT_YUYV8_1X16, 8, 8, ATOMISP_INPUT_FORMAT_YUV422_8, 0, IA_CSS_STREAM_FORMAT_YUV422_8 }, + { MEDIA_BUS_FMT_JPEG_1X8, 8, 8, CSS_FRAME_FORMAT_BINARY_8, 0, IA_CSS_STREAM_FORMAT_BINARY_8 }, + { V4L2_MBUS_FMT_CUSTOM_NV12, 12, 12, CSS_FRAME_FORMAT_NV12, 0, CSS_FRAME_FORMAT_NV12 }, + { V4L2_MBUS_FMT_CUSTOM_NV21, 12, 12, CSS_FRAME_FORMAT_NV21, 0, CSS_FRAME_FORMAT_NV21 }, + { V4L2_MBUS_FMT_CUSTOM_YUV420, 12, 12, ATOMISP_INPUT_FORMAT_YUV420_8_LEGACY, 0, IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY }, + { V4L2_MBUS_FMT_CUSTOM_M10MO_RAW, 8, 8, CSS_FRAME_FORMAT_BINARY_8, 0, IA_CSS_STREAM_FORMAT_BINARY_8 }, + /* no valid V4L2 MBUS code for metadata format, so leave it 0. */ + { 0, 0, 0, ATOMISP_INPUT_FORMAT_EMBEDDED, 0, IA_CSS_STREAM_FORMAT_EMBEDDED }, + {} +}; + +static const struct { + u32 code; + u32 compressed; +} compressed_codes[] = { + { MEDIA_BUS_FMT_SBGGR10_1X10, MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8 }, + { MEDIA_BUS_FMT_SGBRG10_1X10, MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8 }, + { MEDIA_BUS_FMT_SGRBG10_1X10, MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8 }, + { MEDIA_BUS_FMT_SRGGB10_1X10, MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8 }, +}; + +u32 atomisp_subdev_uncompressed_code(u32 code) +{ + unsigned int i; + + for (i = 0; i < ARRAY_SIZE(compressed_codes); i++) + if (code == compressed_codes[i].compressed) + return compressed_codes[i].code; + + return code; +} + +bool atomisp_subdev_is_compressed(u32 code) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(atomisp_in_fmt_conv) - 1; i++) + if (code == atomisp_in_fmt_conv[i].code) + return atomisp_in_fmt_conv[i].bpp != + atomisp_in_fmt_conv[i].depth; + + return false; +} + +const struct atomisp_in_fmt_conv *atomisp_find_in_fmt_conv(u32 code) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(atomisp_in_fmt_conv) - 1; i++) + if (code == atomisp_in_fmt_conv[i].code) + return atomisp_in_fmt_conv + i; + + return NULL; +} + +const struct atomisp_in_fmt_conv *atomisp_find_in_fmt_conv_by_atomisp_in_fmt( + enum atomisp_css_stream_format atomisp_in_fmt) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(atomisp_in_fmt_conv) - 1; i++) + if (atomisp_in_fmt_conv[i].atomisp_in_fmt == atomisp_in_fmt) + return atomisp_in_fmt_conv + i; + + return NULL; +} + +bool atomisp_subdev_format_conversion(struct atomisp_sub_device *asd, + unsigned int source_pad) +{ + struct v4l2_mbus_framefmt *sink, *src; + + sink = atomisp_subdev_get_ffmt(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, + ATOMISP_SUBDEV_PAD_SINK); + src = atomisp_subdev_get_ffmt(&asd->subdev, NULL, + V4L2_SUBDEV_FORMAT_ACTIVE, source_pad); + + return atomisp_is_mbuscode_raw(sink->code) + && !atomisp_is_mbuscode_raw(src->code); +} + +uint16_t atomisp_subdev_source_pad(struct video_device * vdev) +{ + struct media_link *link; + uint16_t ret = 0; + list_for_each_entry(link, &vdev->entity.links, list) { + if (link->source) { + ret = link->source->index; + break; + } + } + return ret; +} + +/* + * V4L2 subdev operations + */ + +/* + * isp_subdev_ioctl - CCDC module private ioctl's + * @sd: ISP V4L2 subdevice + * @cmd: ioctl command + * @arg: ioctl argument + * + * Return 0 on success or a negative error code otherwise. + */ +static long isp_subdev_ioctl(struct v4l2_subdev *sd, + unsigned int cmd, void *arg) +{ + int ret = 0; + + return ret; +} + +/* + * isp_subdev_set_power - Power on/off the CCDC module + * @sd: ISP V4L2 subdevice + * @on: power on/off + * + * Return 0 on success or a negative error code otherwise. + */ +static int isp_subdev_set_power(struct v4l2_subdev *sd, int on) +{ + return 0; +} + +static int isp_subdev_subscribe_event(struct v4l2_subdev *sd, + struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + struct atomisp_sub_device *isp_sd = v4l2_get_subdevdata(sd); + struct atomisp_device *isp = isp_sd->isp; + + if (sub->type != V4L2_EVENT_FRAME_SYNC && + sub->type != V4L2_EVENT_FRAME_END && + sub->type != V4L2_EVENT_ATOMISP_3A_STATS_READY && + sub->type != V4L2_EVENT_ATOMISP_METADATA_READY && + sub->type != V4L2_EVENT_ATOMISP_PAUSE_BUFFER && + sub->type != V4L2_EVENT_ATOMISP_CSS_RESET && + sub->type != V4L2_EVENT_ATOMISP_RAW_BUFFERS_ALLOC_DONE && + sub->type != V4L2_EVENT_ATOMISP_ACC_COMPLETE) + return -EINVAL; + + if (sub->type == V4L2_EVENT_FRAME_SYNC && + !atomisp_css_valid_sof(isp)) + return -EINVAL; + + return v4l2_event_subscribe(fh, sub, 16, NULL); +} + +static int isp_subdev_unsubscribe_event(struct v4l2_subdev *sd, + struct v4l2_fh *fh, + struct v4l2_event_subscription *sub) +{ + return v4l2_event_unsubscribe(fh, sub); +} + +/* + * isp_subdev_enum_mbus_code - Handle pixel format enumeration + * @sd: pointer to v4l2 subdev structure + * @fh : V4L2 subdev file handle + * @code: pointer to v4l2_subdev_pad_mbus_code_enum structure + * return -EINVAL or zero on success + */ +static int isp_subdev_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + if (code->index >= ARRAY_SIZE(atomisp_in_fmt_conv) - 1) + return -EINVAL; + + code->code = atomisp_in_fmt_conv[code->index].code; + + return 0; +} + +static int isp_subdev_validate_rect(struct v4l2_subdev *sd, uint32_t pad, + uint32_t target) +{ + switch (pad) { + case ATOMISP_SUBDEV_PAD_SINK: + switch (target) { + case V4L2_SEL_TGT_CROP: + return 0; + } + break; + default: + switch (target) { + case V4L2_SEL_TGT_COMPOSE: + return 0; + } + break; + } + + return -EINVAL; +} + +struct v4l2_rect *atomisp_subdev_get_rect(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + uint32_t which, uint32_t pad, + uint32_t target) +{ + struct atomisp_sub_device *isp_sd = v4l2_get_subdevdata(sd); + + if (which == V4L2_SUBDEV_FORMAT_TRY) { + switch (target) { + case V4L2_SEL_TGT_CROP: + return v4l2_subdev_get_try_crop(sd, cfg, pad); + case V4L2_SEL_TGT_COMPOSE: + return v4l2_subdev_get_try_compose(sd, cfg, pad); + } + } + + switch (target) { + case V4L2_SEL_TGT_CROP: + return &isp_sd->fmt[pad].crop; + case V4L2_SEL_TGT_COMPOSE: + return &isp_sd->fmt[pad].compose; + } + + return NULL; +} + +struct v4l2_mbus_framefmt +*atomisp_subdev_get_ffmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, uint32_t which, + uint32_t pad) +{ + struct atomisp_sub_device *isp_sd = v4l2_get_subdevdata(sd); + + if (which == V4L2_SUBDEV_FORMAT_TRY) + return v4l2_subdev_get_try_format(sd, cfg, pad); + + return &isp_sd->fmt[pad].fmt; +} + +static void isp_get_fmt_rect(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, uint32_t which, + struct v4l2_mbus_framefmt **ffmt, + struct v4l2_rect *crop[ATOMISP_SUBDEV_PADS_NUM], + struct v4l2_rect *comp[ATOMISP_SUBDEV_PADS_NUM]) +{ + unsigned int i; + + for (i = 0; i < ATOMISP_SUBDEV_PADS_NUM; i++) { + ffmt[i] = atomisp_subdev_get_ffmt(sd, cfg, which, i); + crop[i] = atomisp_subdev_get_rect(sd, cfg, which, i, + V4L2_SEL_TGT_CROP); + comp[i] = atomisp_subdev_get_rect(sd, cfg, which, i, + V4L2_SEL_TGT_COMPOSE); + } +} + +static void isp_subdev_propagate(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + uint32_t which, uint32_t pad, uint32_t target, + uint32_t flags) +{ + struct v4l2_mbus_framefmt *ffmt[ATOMISP_SUBDEV_PADS_NUM]; + struct v4l2_rect *crop[ATOMISP_SUBDEV_PADS_NUM], + *comp[ATOMISP_SUBDEV_PADS_NUM]; + + if (flags & V4L2_SEL_FLAG_KEEP_CONFIG) + return; + + isp_get_fmt_rect(sd, cfg, which, ffmt, crop, comp); + + switch (pad) { + case ATOMISP_SUBDEV_PAD_SINK: { + struct v4l2_rect r = {0}; + + /* Only crop target supported on sink pad. */ + r.width = ffmt[pad]->width; + r.height = ffmt[pad]->height; + +#ifndef ISP2401 + atomisp_subdev_set_selection(sd, cfg, which, pad, target, flags, + &r); + break; + } +#else + atomisp_subdev_set_selection(sd, cfg, which, pad, + target, flags, &r); + break; + } +#endif + } +} + +static int isp_subdev_get_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_selection *sel) +{ + struct v4l2_rect *rec; + int rval = isp_subdev_validate_rect(sd, sel->pad, sel->target); + + if (rval) + return rval; + + rec = atomisp_subdev_get_rect(sd, cfg, sel->which, sel->pad, + sel->target); + if (!rec) + return -EINVAL; + + sel->r = *rec; + return 0; +} + +static char *atomisp_pad_str[] = { "ATOMISP_SUBDEV_PAD_SINK", + "ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE", + "ATOMISP_SUBDEV_PAD_SOURCE_VF", + "ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW", + "ATOMISP_SUBDEV_PAD_SOURCE_VIDEO"}; + +int atomisp_subdev_set_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + uint32_t which, uint32_t pad, uint32_t target, + uint32_t flags, struct v4l2_rect *r) +{ + struct atomisp_sub_device *isp_sd = v4l2_get_subdevdata(sd); + struct atomisp_device *isp = isp_sd->isp; + struct v4l2_mbus_framefmt *ffmt[ATOMISP_SUBDEV_PADS_NUM]; + uint16_t vdev_pad = atomisp_subdev_source_pad(sd->devnode); + struct v4l2_rect *crop[ATOMISP_SUBDEV_PADS_NUM], + *comp[ATOMISP_SUBDEV_PADS_NUM]; + enum atomisp_input_stream_id stream_id; + unsigned int i; + unsigned int padding_w = pad_w; + unsigned int padding_h = pad_h; + + stream_id = atomisp_source_pad_to_stream_id(isp_sd, vdev_pad); + + isp_get_fmt_rect(sd, cfg, which, ffmt, crop, comp); + + dev_dbg(isp->dev, + "sel: pad %s tgt %s l %d t %d w %d h %d which %s f 0x%8.8x\n", + atomisp_pad_str[pad], target == V4L2_SEL_TGT_CROP + ? "V4L2_SEL_TGT_CROP" : "V4L2_SEL_TGT_COMPOSE", + r->left, r->top, r->width, r->height, + which == V4L2_SUBDEV_FORMAT_TRY ? "V4L2_SUBDEV_FORMAT_TRY" + : "V4L2_SUBDEV_FORMAT_ACTIVE", flags); + + r->width = rounddown(r->width, ATOM_ISP_STEP_WIDTH); + r->height = rounddown(r->height, ATOM_ISP_STEP_HEIGHT); + + switch (pad) { + case ATOMISP_SUBDEV_PAD_SINK: { + /* Only crop target supported on sink pad. */ + unsigned int dvs_w, dvs_h; + + crop[pad]->width = ffmt[pad]->width; + crop[pad]->height = ffmt[pad]->height; + + /* Workaround for BYT 1080p perfectshot since the maxinum resolution of + * front camera ov2722 is 1932x1092 and cannot use pad_w > 12*/ + if (!strncmp(isp->inputs[isp_sd->input_curr].camera->name, + "ov2722", 6) && crop[pad]->height == 1092) { + padding_w = 12; + padding_h = 12; + } + + if (isp->inputs[isp_sd->input_curr].type == SOC_CAMERA) { + padding_w = 0; + padding_h = 0; + } + + if (atomisp_subdev_format_conversion(isp_sd, + isp_sd->capture_pad) + && crop[pad]->width && crop[pad]->height) + crop[pad]->width -= padding_w, crop[pad]->height -= padding_h; + + /* if subdev type is SOC camera,we do not need to set DVS */ + if (isp->inputs[isp_sd->input_curr].type == SOC_CAMERA) + isp_sd->params.video_dis_en = 0; + + if (isp_sd->params.video_dis_en && + isp_sd->run_mode->val == ATOMISP_RUN_MODE_VIDEO && + !isp_sd->continuous_mode->val) { + /* This resolution contains 20 % of DVS slack + * (of the desired captured image before + * scaling, or 1 / 6 of what we get from the + * sensor) in both width and height. Remove + * it. */ + crop[pad]->width = roundup(crop[pad]->width * 5 / 6, + ATOM_ISP_STEP_WIDTH); + crop[pad]->height = roundup(crop[pad]->height * 5 / 6, + ATOM_ISP_STEP_HEIGHT); + } + + crop[pad]->width = min(crop[pad]->width, r->width); + crop[pad]->height = min(crop[pad]->height, r->height); + + if (!(flags & V4L2_SEL_FLAG_KEEP_CONFIG)) { + for (i = ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE; + i < ATOMISP_SUBDEV_PADS_NUM; i++) { + struct v4l2_rect tmp = *crop[pad]; + +#ifndef ISP2401 + atomisp_subdev_set_selection( + sd, cfg, which, i, V4L2_SEL_TGT_COMPOSE, + flags, &tmp); + } +#else + atomisp_subdev_set_selection(sd, cfg, + which, i, + V4L2_SEL_TGT_COMPOSE, + flags, + &tmp); + } +#endif + } + + if (which == V4L2_SUBDEV_FORMAT_TRY) + break; + + if (isp_sd->params.video_dis_en && + isp_sd->run_mode->val == ATOMISP_RUN_MODE_VIDEO && + !isp_sd->continuous_mode->val) { + dvs_w = rounddown(crop[pad]->width / 5, + ATOM_ISP_STEP_WIDTH); + dvs_h = rounddown(crop[pad]->height / 5, + ATOM_ISP_STEP_HEIGHT); + } else if (!isp_sd->params.video_dis_en && + isp_sd->run_mode->val == ATOMISP_RUN_MODE_VIDEO) { + /* + * For CSS2.0, digital zoom needs to set dvs envelope to 12 + * when dvs is disabled. + */ + dvs_w = dvs_h = 12; + } else + dvs_w = dvs_h = 0; + + atomisp_css_video_set_dis_envelope(isp_sd, dvs_w, dvs_h); + atomisp_css_input_set_effective_resolution(isp_sd, stream_id, + crop[pad]->width, crop[pad]->height); + + break; + } + case ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE: + case ATOMISP_SUBDEV_PAD_SOURCE_VIDEO: { + /* Only compose target is supported on source pads. */ + + if (isp_sd->vfpp->val == ATOMISP_VFPP_DISABLE_LOWLAT) { + /* Scaling is disabled in this mode */ + r->width = crop[ATOMISP_SUBDEV_PAD_SINK]->width; + r->height = crop[ATOMISP_SUBDEV_PAD_SINK]->height; + } + + if (crop[ATOMISP_SUBDEV_PAD_SINK]->width == r->width + && crop[ATOMISP_SUBDEV_PAD_SINK]->height == r->height) + isp_sd->params.yuv_ds_en = false; + else + isp_sd->params.yuv_ds_en = true; + + comp[pad]->width = r->width; + comp[pad]->height = r->height; + + if (r->width == 0 || r->height == 0 || + crop[ATOMISP_SUBDEV_PAD_SINK]->width == 0 || + crop[ATOMISP_SUBDEV_PAD_SINK]->height == 0) + break; + /* + * do cropping on sensor input if ratio of required resolution + * is different with sensor output resolution ratio: + * + * ratio = width / height + * + * if ratio_output < ratio_sensor: + * effect_width = sensor_height * out_width / out_height; + * effect_height = sensor_height; + * else + * effect_width = sensor_width; + * effect_height = sensor_width * out_height / out_width; + * + */ + if (r->width * crop[ATOMISP_SUBDEV_PAD_SINK]->height < + crop[ATOMISP_SUBDEV_PAD_SINK]->width * r->height) + atomisp_css_input_set_effective_resolution(isp_sd, + stream_id, + rounddown(crop[ATOMISP_SUBDEV_PAD_SINK]-> + height * r->width / r->height, + ATOM_ISP_STEP_WIDTH), + crop[ATOMISP_SUBDEV_PAD_SINK]->height); + else + atomisp_css_input_set_effective_resolution(isp_sd, + stream_id, + crop[ATOMISP_SUBDEV_PAD_SINK]->width, + rounddown(crop[ATOMISP_SUBDEV_PAD_SINK]-> + width * r->height / r->width, + ATOM_ISP_STEP_WIDTH)); + + break; + } + case ATOMISP_SUBDEV_PAD_SOURCE_VF: + case ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW: + comp[pad]->width = r->width; + comp[pad]->height = r->height; + break; + default: + return -EINVAL; + } + + /* Set format dimensions on non-sink pads as well. */ + if (pad != ATOMISP_SUBDEV_PAD_SINK) { + ffmt[pad]->width = comp[pad]->width; + ffmt[pad]->height = comp[pad]->height; + } + + if (!atomisp_subdev_get_rect(sd, cfg, which, pad, target)) + return -EINVAL; + *r = *atomisp_subdev_get_rect(sd, cfg, which, pad, target); + + dev_dbg(isp->dev, "sel actual: l %d t %d w %d h %d\n", + r->left, r->top, r->width, r->height); + + return 0; +} + +static int isp_subdev_set_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_selection *sel) +{ + int rval = isp_subdev_validate_rect(sd, sel->pad, sel->target); + if (rval) + return rval; + + return atomisp_subdev_set_selection(sd, cfg, sel->which, sel->pad, + sel->target, sel->flags, &sel->r); +} + +static int atomisp_get_sensor_bin_factor(struct atomisp_sub_device *asd) +{ + struct v4l2_control ctrl = {0}; + struct atomisp_device *isp = asd->isp; + int hbin, vbin; + int ret; + + if (isp->inputs[asd->input_curr].type == FILE_INPUT || + isp->inputs[asd->input_curr].type == TEST_PATTERN) + return 0; + + ctrl.id = V4L2_CID_BIN_FACTOR_HORZ; + ret = + v4l2_g_ctrl(isp->inputs[asd->input_curr].camera->ctrl_handler, + &ctrl); + hbin = ctrl.value; + ctrl.id = V4L2_CID_BIN_FACTOR_VERT; + ret |= + v4l2_g_ctrl(isp->inputs[asd->input_curr].camera->ctrl_handler, + &ctrl); + vbin = ctrl.value; + + /* + * ISP needs to know binning factor from sensor. + * In case horizontal and vertical sensor's binning factors + * are different or sensor does not support binning factor CID, + * ISP will apply default 0 value. + */ + if (ret || hbin != vbin) + hbin = 0; + + return hbin; +} + +#ifndef ISP2401 +void atomisp_subdev_set_ffmt(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config *cfg, + uint32_t which, uint32_t pad, + struct v4l2_mbus_framefmt *ffmt) +#else +void atomisp_subdev_set_ffmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, uint32_t which, + uint32_t pad, struct v4l2_mbus_framefmt *ffmt) +#endif +{ + struct atomisp_sub_device *isp_sd = v4l2_get_subdevdata(sd); + struct atomisp_device *isp = isp_sd->isp; + struct v4l2_mbus_framefmt *__ffmt = +#ifndef ISP2401 + atomisp_subdev_get_ffmt(sd, cfg, which, pad); +#else + atomisp_subdev_get_ffmt(sd, cfg, which, pad); +#endif + uint16_t vdev_pad = atomisp_subdev_source_pad(sd->devnode); + enum atomisp_input_stream_id stream_id; + + dev_dbg(isp->dev, "ffmt: pad %s w %d h %d code 0x%8.8x which %s\n", + atomisp_pad_str[pad], ffmt->width, ffmt->height, ffmt->code, + which == V4L2_SUBDEV_FORMAT_TRY ? "V4L2_SUBDEV_FORMAT_TRY" + : "V4L2_SUBDEV_FORMAT_ACTIVE"); + + stream_id = atomisp_source_pad_to_stream_id(isp_sd, vdev_pad); + + switch (pad) { + case ATOMISP_SUBDEV_PAD_SINK: { + const struct atomisp_in_fmt_conv *fc = + atomisp_find_in_fmt_conv(ffmt->code); + + if (!fc) { + fc = atomisp_in_fmt_conv; + ffmt->code = fc->code; + dev_dbg(isp->dev, "using 0x%8.8x instead\n", + ffmt->code); + } + + *__ffmt = *ffmt; + + isp_subdev_propagate(sd, cfg, which, pad, + V4L2_SEL_TGT_CROP, 0); + + if (which == V4L2_SUBDEV_FORMAT_ACTIVE) { + atomisp_css_input_set_resolution(isp_sd, + stream_id, ffmt); + atomisp_css_input_set_binning_factor(isp_sd, + stream_id, + atomisp_get_sensor_bin_factor(isp_sd)); + atomisp_css_input_set_bayer_order(isp_sd, stream_id, + fc->bayer_order); + atomisp_css_input_set_format(isp_sd, stream_id, + fc->css_stream_fmt); + atomisp_css_set_default_isys_config(isp_sd, stream_id, + ffmt); + } + + break; + } + case ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE: + case ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW: + case ATOMISP_SUBDEV_PAD_SOURCE_VF: + case ATOMISP_SUBDEV_PAD_SOURCE_VIDEO: + __ffmt->code = ffmt->code; + break; + } +} + +/* + * isp_subdev_get_format - Retrieve the video format on a pad + * @sd : ISP V4L2 subdevice + * @fh : V4L2 subdev file handle + * @pad: Pad number + * @fmt: Format + * + * Return 0 on success or -EINVAL if the pad is invalid or doesn't correspond + * to the format type. + */ +static int isp_subdev_get_format(struct v4l2_subdev *sd, +#ifndef ISP2401 + struct v4l2_subdev_pad_config *cfg, struct v4l2_subdev_format *fmt) +#else + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +#endif +{ + fmt->format = *atomisp_subdev_get_ffmt(sd, cfg, fmt->which, fmt->pad); + + return 0; +} + +/* + * isp_subdev_set_format - Set the video format on a pad + * @sd : ISP subdev V4L2 subdevice + * @fh : V4L2 subdev file handle + * @pad: Pad number + * @fmt: Format + * + * Return 0 on success or -EINVAL if the pad is invalid or doesn't correspond + * to the format type. + */ +static int isp_subdev_set_format(struct v4l2_subdev *sd, +#ifndef ISP2401 + struct v4l2_subdev_pad_config *cfg, struct v4l2_subdev_format *fmt) +#else + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *fmt) +#endif +{ + atomisp_subdev_set_ffmt(sd, cfg, fmt->which, fmt->pad, &fmt->format); + + return 0; +} + +/* V4L2 subdev core operations */ +static const struct v4l2_subdev_core_ops isp_subdev_v4l2_core_ops = { + .ioctl = isp_subdev_ioctl, .s_power = isp_subdev_set_power, + .subscribe_event = isp_subdev_subscribe_event, + .unsubscribe_event = isp_subdev_unsubscribe_event, +}; + +/* V4L2 subdev pad operations */ +static const struct v4l2_subdev_pad_ops isp_subdev_v4l2_pad_ops = { +#ifndef ISP2401 + .enum_mbus_code = isp_subdev_enum_mbus_code, + .get_fmt = isp_subdev_get_format, .set_fmt = isp_subdev_set_format, + .get_selection = isp_subdev_get_selection, + .set_selection = isp_subdev_set_selection, + .link_validate = v4l2_subdev_link_validate_default, +#else + .enum_mbus_code = isp_subdev_enum_mbus_code, + .get_fmt = isp_subdev_get_format, + .set_fmt = isp_subdev_set_format, + .get_selection = isp_subdev_get_selection, + .set_selection = isp_subdev_set_selection, + .link_validate = v4l2_subdev_link_validate_default, +#endif +}; + +/* V4L2 subdev operations */ +static const struct v4l2_subdev_ops isp_subdev_v4l2_ops = { +#ifndef ISP2401 + .core = &isp_subdev_v4l2_core_ops, .pad = &isp_subdev_v4l2_pad_ops, +#else + .core = &isp_subdev_v4l2_core_ops, + .pad = &isp_subdev_v4l2_pad_ops, +#endif +}; + +static void isp_subdev_init_params(struct atomisp_sub_device *asd) +{ + unsigned int i; + + /* parameters initialization */ + INIT_LIST_HEAD(&asd->s3a_stats); + INIT_LIST_HEAD(&asd->s3a_stats_in_css); + INIT_LIST_HEAD(&asd->s3a_stats_ready); + INIT_LIST_HEAD(&asd->dis_stats); + INIT_LIST_HEAD(&asd->dis_stats_in_css); + spin_lock_init(&asd->dis_stats_lock); + for (i = 0; i < ATOMISP_METADATA_TYPE_NUM; i++) { + INIT_LIST_HEAD(&asd->metadata[i]); + INIT_LIST_HEAD(&asd->metadata_in_css[i]); + INIT_LIST_HEAD(&asd->metadata_ready[i]); + } +} + +/* +* isp_subdev_link_setup - Setup isp subdev connections +* @entity: ispsubdev media entity +* @local: Pad at the local end of the link +* @remote: Pad at the remote end of the link +* @flags: Link flags +* +* return -EINVAL or zero on success +*/ +static int isp_subdev_link_setup(struct media_entity *entity, + const struct media_pad *local, + const struct media_pad *remote, u32 flags) +{ + struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity); + struct atomisp_sub_device *isp_sd = v4l2_get_subdevdata(sd); + struct atomisp_device *isp = isp_sd->isp; + unsigned int i; + + switch (local->index | is_media_entity_v4l2_subdev(remote->entity)) { + case ATOMISP_SUBDEV_PAD_SINK | MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN: + /* Read from the sensor CSI2-ports. */ + if (!(flags & MEDIA_LNK_FL_ENABLED)) { + isp_sd->input = ATOMISP_SUBDEV_INPUT_NONE; + break; + } + + if (isp_sd->input != ATOMISP_SUBDEV_INPUT_NONE) + return -EBUSY; + + for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) { + if (remote->entity != &isp->csi2_port[i].subdev.entity) + continue; + + isp_sd->input = ATOMISP_SUBDEV_INPUT_CSI2_PORT1 + i; + return 0; + } + + return -EINVAL; + + case ATOMISP_SUBDEV_PAD_SINK | MEDIA_ENT_F_OLD_BASE: + /* read from memory */ + if (flags & MEDIA_LNK_FL_ENABLED) { + if (isp_sd->input >= ATOMISP_SUBDEV_INPUT_CSI2_PORT1 && + isp_sd->input < (ATOMISP_SUBDEV_INPUT_CSI2_PORT1 + + ATOMISP_CAMERA_NR_PORTS)) + return -EBUSY; + isp_sd->input = ATOMISP_SUBDEV_INPUT_MEMORY; + } else { + if (isp_sd->input == ATOMISP_SUBDEV_INPUT_MEMORY) + isp_sd->input = ATOMISP_SUBDEV_INPUT_NONE; + } + break; + + case ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW | MEDIA_ENT_F_OLD_BASE: + /* always write to memory */ + break; + + case ATOMISP_SUBDEV_PAD_SOURCE_VF | MEDIA_ENT_F_OLD_BASE: + /* always write to memory */ + break; + + case ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE | MEDIA_ENT_F_OLD_BASE: + /* always write to memory */ + break; + + case ATOMISP_SUBDEV_PAD_SOURCE_VIDEO | MEDIA_ENT_F_OLD_BASE: + /* always write to memory */ + break; + + default: + return -EINVAL; + } + + return 0; +} + +/* media operations */ +static const struct media_entity_operations isp_subdev_media_ops = { + .link_setup = isp_subdev_link_setup, + .link_validate = v4l2_subdev_link_validate, +/* .set_power = v4l2_subdev_set_power, */ +}; + +static int __atomisp_update_run_mode(struct atomisp_sub_device *asd) +{ + struct atomisp_device *isp = asd->isp; + struct v4l2_ctrl *ctrl = asd->run_mode; + struct v4l2_ctrl *c; + struct v4l2_streamparm p = {0}; + int modes[] = { CI_MODE_NONE, + CI_MODE_VIDEO, + CI_MODE_STILL_CAPTURE, + CI_MODE_CONTINUOUS, + CI_MODE_PREVIEW }; + s32 mode; + + if (ctrl->val != ATOMISP_RUN_MODE_VIDEO && + asd->continuous_mode->val) + mode = ATOMISP_RUN_MODE_PREVIEW; + else + mode = ctrl->val; + + c = v4l2_ctrl_find( + isp->inputs[asd->input_curr].camera->ctrl_handler, + V4L2_CID_RUN_MODE); + + if (c) + return v4l2_ctrl_s_ctrl(c, mode); + + /* Fall back to obsolete s_parm */ + p.parm.capture.capturemode = modes[mode]; + + return v4l2_subdev_call( + isp->inputs[asd->input_curr].camera, video, s_parm, &p); +} + +int atomisp_update_run_mode(struct atomisp_sub_device *asd) +{ + int rval; + + mutex_lock(asd->ctrl_handler.lock); + rval = __atomisp_update_run_mode(asd); + mutex_unlock(asd->ctrl_handler.lock); + + return rval; +} + +static int s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct atomisp_sub_device *asd = container_of( + ctrl->handler, struct atomisp_sub_device, ctrl_handler); + + switch (ctrl->id) { + case V4L2_CID_RUN_MODE: + return __atomisp_update_run_mode(asd); + case V4L2_CID_DEPTH_MODE: + if (asd->streaming != ATOMISP_DEVICE_STREAMING_DISABLED) { + dev_err(asd->isp->dev, "ISP is streaming, it is not supported to change the depth mode\n"); + return -EINVAL; + } + break; + } + + return 0; +} + +static const struct v4l2_ctrl_ops ctrl_ops = { + .s_ctrl = &s_ctrl, +}; + +static const struct v4l2_ctrl_config ctrl_fmt_auto = { + .ops = &ctrl_ops, + .id = V4L2_CID_FMT_AUTO, + .name = "Automatic format guessing", + .type = V4L2_CTRL_TYPE_BOOLEAN, + .min = 0, + .max = 1, + .step = 1, + .def = 1, +}; + +static const char * const ctrl_run_mode_menu[] = { + NULL, + "Video", + "Still capture", + "Continuous capture", + "Preview", +}; + +static const struct v4l2_ctrl_config ctrl_run_mode = { + .ops = &ctrl_ops, + .id = V4L2_CID_RUN_MODE, + .name = "Atomisp run mode", + .type = V4L2_CTRL_TYPE_MENU, + .min = 1, + .def = 1, + .max = 4, + .qmenu = ctrl_run_mode_menu, +}; + +static const char * const ctrl_vfpp_mode_menu[] = { + "Enable", /* vfpp always enabled */ + "Disable to scaler mode", /* CSS into video mode and disable */ + "Disable to low latency mode", /* CSS into still mode and disable */ +}; + +static const struct v4l2_ctrl_config ctrl_vfpp = { + .id = V4L2_CID_VFPP, + .name = "Atomisp vf postprocess", + .type = V4L2_CTRL_TYPE_MENU, + .min = 0, + .def = 0, + .max = 2, + .qmenu = ctrl_vfpp_mode_menu, +}; + +/* + * Control for ISP continuous mode + * + * When enabled, capture processing is possible without + * stopping the preview pipeline. When disabled, ISP needs + * to be restarted between preview and capture. + */ +static const struct v4l2_ctrl_config ctrl_continuous_mode = { + .ops = &ctrl_ops, + .id = V4L2_CID_ATOMISP_CONTINUOUS_MODE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Continuous mode", + .min = 0, + .max = 1, + .step = 1, + .def = 0, +}; + +/* + * Control for continuous mode raw buffer size + * + * The size of the RAW ringbuffer sets limit on how much + * back in time application can go when requesting capture + * frames to be rendered, and how many frames can be rendered + * in a burst at full sensor rate. + * + * Note: this setting has a big impact on memory consumption of + * the CSS subsystem. + */ +static const struct v4l2_ctrl_config ctrl_continuous_raw_buffer_size = { + .ops = &ctrl_ops, + .id = V4L2_CID_ATOMISP_CONTINUOUS_RAW_BUFFER_SIZE, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Continuous raw ringbuffer size", + .min = 1, + .max = 100, /* depends on CSS version, runtime checked */ + .step = 1, + .def = 3, +}; + +/* + * Control for enabling continuous viewfinder + * + * When enabled, and ISP is in continuous mode (see ctrl_continuous_mode ), + * preview pipeline continues concurrently with capture + * processing. When disabled, and continuous mode is used, + * preview is paused while captures are processed, but + * full pipeline restart is not needed. + * + * By setting this to disabled, capture processing is + * essentially given priority over preview, and the effective + * capture output rate may be higher than with continuous + * viewfinder enabled. + */ +static const struct v4l2_ctrl_config ctrl_continuous_viewfinder = { + .id = V4L2_CID_ATOMISP_CONTINUOUS_VIEWFINDER, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Continuous viewfinder", + .min = 0, + .max = 1, + .step = 1, + .def = 0, +}; + +/* + * Control for enabling Lock&Unlock Raw Buffer mechanism + * + * When enabled, Raw Buffer can be locked and unlocked. + * Application can hold the exp_id of Raw Buffer + * and unlock it when no longer needed. + * Note: Make sure set this configuration before creating stream. + */ +static const struct v4l2_ctrl_config ctrl_enable_raw_buffer_lock = { + .id = V4L2_CID_ENABLE_RAW_BUFFER_LOCK, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Lock Unlock Raw Buffer", + .min = 0, + .max = 1, + .step = 1, + .def = 0, +}; + +/* + * Control to disable digital zoom of the whole stream + * + * When it is true, pipe configuation enable_dz will be set to false. + * This can help get a better performance by disabling pp binary. + * + * Note: Make sure set this configuration before creating stream. + */ +static const struct v4l2_ctrl_config ctrl_disable_dz = { + .id = V4L2_CID_DISABLE_DZ, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Disable digital zoom", + .min = 0, + .max = 1, + .step = 1, + .def = 0, +}; + +/* + * Control for ISP depth mode + * + * When enabled, that means ISP will deal with dual streams and sensors will be + * in slave/master mode. + * slave sensor will have no output until master sensor is streamed on. + */ +static const struct v4l2_ctrl_config ctrl_depth_mode = { + .ops = &ctrl_ops, + .id = V4L2_CID_DEPTH_MODE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Depth mode", + .min = 0, + .max = 1, + .step = 1, + .def = 0, +}; + +#ifdef ISP2401 +/* + * Control for selectting ISP version + * + * When enabled, that means ISP version will be used ISP2.7. when disable, the + * isp will default to use ISP2.2. + * Note: Make sure set this configuration before creating stream. + */ +static const struct v4l2_ctrl_config ctrl_select_isp_version = { + .ops = &ctrl_ops, + .id = V4L2_CID_ATOMISP_SELECT_ISP_VERSION, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .name = "Select Isp version", + .min = 0, + .max = 1, + .step = 1, + .def = 0, +}; + +#ifdef CONFIG_ION +/* + * Control for ISP ion device fd + * + * userspace will open ion device and pass the fd to kernel. + * this fd will be used to map shared fd to buffer. + */ +static const struct v4l2_ctrl_config ctrl_ion_dev_fd = { + .ops = &ctrl_ops, + .id = V4L2_CID_ATOMISP_ION_DEVICE_FD, + .type = V4L2_CTRL_TYPE_INTEGER, + .name = "Ion Device Fd", + .min = -1, + .max = 1024, + .step = 1, + .def = ION_FD_UNSET +}; +#endif + +#endif +static void atomisp_init_subdev_pipe(struct atomisp_sub_device *asd, + struct atomisp_video_pipe *pipe, enum v4l2_buf_type buf_type) +{ + pipe->type = buf_type; + pipe->asd = asd; + pipe->isp = asd->isp; + spin_lock_init(&pipe->irq_lock); + INIT_LIST_HEAD(&pipe->activeq); + INIT_LIST_HEAD(&pipe->activeq_out); + INIT_LIST_HEAD(&pipe->buffers_waiting_for_param); + INIT_LIST_HEAD(&pipe->per_frame_params); + memset(pipe->frame_request_config_id, + 0, VIDEO_MAX_FRAME * sizeof(unsigned int)); + memset(pipe->frame_params, + 0, VIDEO_MAX_FRAME * + sizeof(struct atomisp_css_params_with_list *)); +} + +static void atomisp_init_acc_pipe(struct atomisp_sub_device *asd, + struct atomisp_acc_pipe *pipe) +{ + pipe->asd = asd; + pipe->isp = asd->isp; + INIT_LIST_HEAD(&asd->acc.fw); + INIT_LIST_HEAD(&asd->acc.memory_maps); + ida_init(&asd->acc.ida); +} + +/* + * isp_subdev_init_entities - Initialize V4L2 subdev and media entity + * @asd: ISP CCDC module + * + * Return 0 on success and a negative error code on failure. + */ +static int isp_subdev_init_entities(struct atomisp_sub_device *asd) +{ + struct v4l2_subdev *sd = &asd->subdev; + struct media_pad *pads = asd->pads; + struct media_entity *me = &sd->entity; + int ret; + + asd->input = ATOMISP_SUBDEV_INPUT_NONE; + + v4l2_subdev_init(sd, &isp_subdev_v4l2_ops); + sprintf(sd->name, "ATOMISP_SUBDEV_%d", asd->index); + v4l2_set_subdevdata(sd, asd); + sd->flags |= V4L2_SUBDEV_FL_HAS_EVENTS | V4L2_SUBDEV_FL_HAS_DEVNODE; + + pads[ATOMISP_SUBDEV_PAD_SINK].flags = MEDIA_PAD_FL_SINK; + pads[ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW].flags = MEDIA_PAD_FL_SOURCE; + pads[ATOMISP_SUBDEV_PAD_SOURCE_VF].flags = MEDIA_PAD_FL_SOURCE; + pads[ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE].flags = MEDIA_PAD_FL_SOURCE; + pads[ATOMISP_SUBDEV_PAD_SOURCE_VIDEO].flags = MEDIA_PAD_FL_SOURCE; + +#ifndef ISP2401 + asd->fmt[ATOMISP_SUBDEV_PAD_SINK].fmt.code = + MEDIA_BUS_FMT_SBGGR10_1X10; +#else + asd->fmt[ATOMISP_SUBDEV_PAD_SINK].fmt.code = MEDIA_BUS_FMT_SBGGR10_1X10; +#endif + asd->fmt[ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW].fmt.code = + MEDIA_BUS_FMT_SBGGR10_1X10; + asd->fmt[ATOMISP_SUBDEV_PAD_SOURCE_VF].fmt.code = + MEDIA_BUS_FMT_SBGGR10_1X10; + asd->fmt[ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE].fmt.code = + MEDIA_BUS_FMT_SBGGR10_1X10; + asd->fmt[ATOMISP_SUBDEV_PAD_SOURCE_VIDEO].fmt.code = + MEDIA_BUS_FMT_SBGGR10_1X10; + + me->ops = &isp_subdev_media_ops; + me->function = MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN; + ret = media_entity_pads_init(me, ATOMISP_SUBDEV_PADS_NUM, pads); + if (ret < 0) + return ret; + + atomisp_init_subdev_pipe(asd, &asd->video_in, +#ifndef ISP2401 + V4L2_BUF_TYPE_VIDEO_OUTPUT); +#else + V4L2_BUF_TYPE_VIDEO_OUTPUT); +#endif + + atomisp_init_subdev_pipe(asd, &asd->video_out_preview, +#ifndef ISP2401 + V4L2_BUF_TYPE_VIDEO_CAPTURE); +#else + V4L2_BUF_TYPE_VIDEO_CAPTURE); +#endif + + atomisp_init_subdev_pipe(asd, &asd->video_out_vf, +#ifndef ISP2401 + V4L2_BUF_TYPE_VIDEO_CAPTURE); +#else + V4L2_BUF_TYPE_VIDEO_CAPTURE); +#endif + + atomisp_init_subdev_pipe(asd, &asd->video_out_capture, +#ifndef ISP2401 + V4L2_BUF_TYPE_VIDEO_CAPTURE); +#else + V4L2_BUF_TYPE_VIDEO_CAPTURE); +#endif + + atomisp_init_subdev_pipe(asd, &asd->video_out_video_capture, +#ifndef ISP2401 + V4L2_BUF_TYPE_VIDEO_CAPTURE); +#else + V4L2_BUF_TYPE_VIDEO_CAPTURE); +#endif + + atomisp_init_acc_pipe(asd, &asd->video_acc); + + ret = atomisp_video_init(&asd->video_in, "MEMORY"); + if (ret < 0) + return ret; + + ret = atomisp_video_init(&asd->video_out_capture, "CAPTURE"); + if (ret < 0) + return ret; + + ret = atomisp_video_init(&asd->video_out_vf, "VIEWFINDER"); + if (ret < 0) + return ret; + + ret = atomisp_video_init(&asd->video_out_preview, "PREVIEW"); + if (ret < 0) + return ret; + + ret = atomisp_video_init(&asd->video_out_video_capture, "VIDEO"); + if (ret < 0) + return ret; + + atomisp_acc_init(&asd->video_acc, "ACC"); + + ret = v4l2_ctrl_handler_init(&asd->ctrl_handler, 1); + if (ret) + return ret; + + asd->fmt_auto = v4l2_ctrl_new_custom(&asd->ctrl_handler, + &ctrl_fmt_auto, NULL); + asd->run_mode = v4l2_ctrl_new_custom(&asd->ctrl_handler, + &ctrl_run_mode, NULL); + asd->vfpp = v4l2_ctrl_new_custom(&asd->ctrl_handler, + &ctrl_vfpp, NULL); + asd->continuous_mode = v4l2_ctrl_new_custom(&asd->ctrl_handler, + &ctrl_continuous_mode, NULL); + asd->continuous_viewfinder = v4l2_ctrl_new_custom(&asd->ctrl_handler, + &ctrl_continuous_viewfinder, + NULL); + asd->continuous_raw_buffer_size = + v4l2_ctrl_new_custom(&asd->ctrl_handler, + &ctrl_continuous_raw_buffer_size, + NULL); + + asd->enable_raw_buffer_lock = + v4l2_ctrl_new_custom(&asd->ctrl_handler, + &ctrl_enable_raw_buffer_lock, + NULL); + asd->depth_mode = + v4l2_ctrl_new_custom(&asd->ctrl_handler, + &ctrl_depth_mode, + NULL); + asd->disable_dz = + v4l2_ctrl_new_custom(&asd->ctrl_handler, + &ctrl_disable_dz, + NULL); +#ifdef ISP2401 + asd->select_isp_version = + v4l2_ctrl_new_custom(&asd->ctrl_handler, + &ctrl_select_isp_version, + NULL); + +#ifdef CONFIG_ION + asd->ion_dev_fd = + v4l2_ctrl_new_custom(&asd->ctrl_handler, + &ctrl_ion_dev_fd, + NULL); +#endif +#endif + + /* Make controls visible on subdev as well. */ + asd->subdev.ctrl_handler = &asd->ctrl_handler; + spin_lock_init(&asd->raw_buffer_bitmap_lock); + return asd->ctrl_handler.error; +} + +int atomisp_create_pads_links(struct atomisp_device *isp) +{ + struct atomisp_sub_device *asd; + int i, j, ret = 0; + isp->num_of_streams = isp->media_dev.driver_version >= + ATOMISP_CSS_VERSION_20 ? 2 : 1; + for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) { + for (j = 0; j < isp->num_of_streams; j++) { + ret = + media_create_pad_link(&isp->csi2_port[i].subdev. + entity, CSI2_PAD_SOURCE, + &isp->asd[j].subdev.entity, + ATOMISP_SUBDEV_PAD_SINK, 0); + if (ret < 0) + return ret; + } + } + for (i = 0; i < isp->input_cnt - 2; i++) { + ret = media_create_pad_link(&isp->inputs[i].camera->entity, 0, + &isp->csi2_port[isp->inputs[i]. + port].subdev.entity, + CSI2_PAD_SINK, + MEDIA_LNK_FL_ENABLED | + MEDIA_LNK_FL_IMMUTABLE); + if (ret < 0) + return ret; + } + for (i = 0; i < isp->num_of_streams; i++) { + asd = &isp->asd[i]; + ret = media_create_pad_link(&asd->subdev.entity, + ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW, + &asd->video_out_preview.vdev.entity, + 0, 0); + if (ret < 0) + return ret; + ret = media_create_pad_link(&asd->subdev.entity, + ATOMISP_SUBDEV_PAD_SOURCE_VF, + &asd->video_out_vf.vdev.entity, 0, + 0); + if (ret < 0) + return ret; + ret = media_create_pad_link(&asd->subdev.entity, + ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE, + &asd->video_out_capture.vdev.entity, + 0, 0); + if (ret < 0) + return ret; + ret = media_create_pad_link(&asd->subdev.entity, + ATOMISP_SUBDEV_PAD_SOURCE_VIDEO, + &asd->video_out_video_capture.vdev. + entity, 0, 0); + if (ret < 0) + return ret; + /* + * file input only supported on subdev0 + * so do not create pad link for subdevs other then subdev0 + */ + if (asd->index) + return 0; + ret = media_create_pad_link(&asd->video_in.vdev.entity, + 0, &asd->subdev.entity, + ATOMISP_SUBDEV_PAD_SINK, 0); + if (ret < 0) + return ret; + } + return 0; +} + +static void atomisp_subdev_cleanup_entities(struct atomisp_sub_device *asd) +{ + v4l2_ctrl_handler_free(&asd->ctrl_handler); + + media_entity_cleanup(&asd->subdev.entity); +} + +void atomisp_subdev_cleanup_pending_events(struct atomisp_sub_device *asd) +{ + struct v4l2_fh *fh, *fh_tmp; + struct v4l2_event event; + unsigned int i, pending_event; + + list_for_each_entry_safe(fh, fh_tmp, +#ifndef ISP2401 + &asd->subdev.devnode->fh_list, list) { +#else + &asd->subdev.devnode->fh_list, list) { +#endif + pending_event = v4l2_event_pending(fh); + for (i = 0; i < pending_event; i++) + v4l2_event_dequeue(fh, &event, 1); + } +} + +void atomisp_subdev_unregister_entities(struct atomisp_sub_device *asd) +{ + atomisp_subdev_cleanup_entities(asd); + v4l2_device_unregister_subdev(&asd->subdev); + atomisp_video_unregister(&asd->video_in); + atomisp_video_unregister(&asd->video_out_preview); + atomisp_video_unregister(&asd->video_out_vf); + atomisp_video_unregister(&asd->video_out_capture); + atomisp_video_unregister(&asd->video_out_video_capture); + atomisp_acc_unregister(&asd->video_acc); +} + +int atomisp_subdev_register_entities(struct atomisp_sub_device *asd, + struct v4l2_device *vdev) +{ + int ret; + + /* Register the subdev and video node. */ + ret = v4l2_device_register_subdev(vdev, &asd->subdev); + if (ret < 0) + goto error; + + ret = atomisp_video_register(&asd->video_out_capture, vdev); + if (ret < 0) + goto error; + + ret = atomisp_video_register(&asd->video_out_vf, vdev); + if (ret < 0) + goto error; + + ret = atomisp_video_register(&asd->video_out_preview, vdev); + if (ret < 0) + goto error; + + ret = atomisp_video_register(&asd->video_out_video_capture, vdev); + if (ret < 0) + goto error; + + ret = atomisp_acc_register(&asd->video_acc, vdev); + if (ret < 0) + goto error; + + /* + * file input only supported on subdev0 + * so do not create video node for subdevs other then subdev0 + */ + if (asd->index) + return 0; + ret = atomisp_video_register(&asd->video_in, vdev); + if (ret < 0) + goto error; + + return 0; + +error: + atomisp_subdev_unregister_entities(asd); + return ret; +} + +#ifndef ISP2401 + +#endif +/* + * atomisp_subdev_init - ISP Subdevice initialization. + * @dev: Device pointer specific to the ATOM ISP. + * + * TODO: Get the initialisation values from platform data. + * + * Return 0 on success or a negative error code otherwise. + */ +int atomisp_subdev_init(struct atomisp_device *isp) +{ + struct atomisp_sub_device *asd; + int i, ret = 0; + + /* + * CSS2.0 running ISP2400 support + * multiple streams + */ + isp->num_of_streams = isp->media_dev.driver_version >= + ATOMISP_CSS_VERSION_20 ? 2 : 1; + isp->asd = devm_kzalloc(isp->dev, sizeof(struct atomisp_sub_device) * + isp->num_of_streams, GFP_KERNEL); + if (!isp->asd) + return -ENOMEM; + for (i = 0; i < isp->num_of_streams; i++) { + asd = &isp->asd[i]; + spin_lock_init(&asd->lock); + asd->isp = isp; + isp_subdev_init_params(asd); + asd->index = i; + ret = isp_subdev_init_entities(asd); + if (ret < 0) { + atomisp_subdev_cleanup_entities(asd); + break; + } + } + + return ret; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_subdev.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_subdev.h new file mode 100644 index 0000000000000000000000000000000000000000..ba5c2ab14253419e31f36019d0b777b1d290def3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_subdev.h @@ -0,0 +1,471 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#ifndef __ATOMISP_SUBDEV_H__ +#define __ATOMISP_SUBDEV_H__ + +#include +#include +#include +#include + +#include "atomisp_common.h" +#include "atomisp_compat.h" +#include "atomisp_v4l2.h" + +#include "ia_css.h" + +/* EXP_ID's ranger is 1 ~ 250 */ +#define ATOMISP_MAX_EXP_ID (250) +enum atomisp_subdev_input_entity { + ATOMISP_SUBDEV_INPUT_NONE, + ATOMISP_SUBDEV_INPUT_MEMORY, + ATOMISP_SUBDEV_INPUT_CSI2, + /* + * The following enum for CSI2 port must go together in one row. + * Otherwise it breaks the code logic. + */ + ATOMISP_SUBDEV_INPUT_CSI2_PORT1, + ATOMISP_SUBDEV_INPUT_CSI2_PORT2, + ATOMISP_SUBDEV_INPUT_CSI2_PORT3, +}; + +#define ATOMISP_SUBDEV_PAD_SINK 0 +/* capture output for still frames */ +#define ATOMISP_SUBDEV_PAD_SOURCE_CAPTURE 1 +/* viewfinder output for downscaled capture output */ +#define ATOMISP_SUBDEV_PAD_SOURCE_VF 2 +/* preview output for display */ +#define ATOMISP_SUBDEV_PAD_SOURCE_PREVIEW 3 +/* main output for video pipeline */ +#define ATOMISP_SUBDEV_PAD_SOURCE_VIDEO 4 +#define ATOMISP_SUBDEV_PADS_NUM 5 + +struct atomisp_in_fmt_conv { + u32 code; + uint8_t bpp; /* bits per pixel */ + uint8_t depth; /* uncompressed */ + enum atomisp_css_stream_format atomisp_in_fmt; + enum atomisp_css_bayer_order bayer_order; + enum ia_css_stream_format css_stream_fmt; +}; + +struct atomisp_sub_device; + +struct atomisp_video_pipe { + struct video_device vdev; + enum v4l2_buf_type type; + struct media_pad pad; + struct videobuf_queue capq; + struct videobuf_queue outq; + struct list_head activeq; + struct list_head activeq_out; + /* + * the buffers waiting for per-frame parameters, this is only valid + * in per-frame setting mode. + */ + struct list_head buffers_waiting_for_param; + /* the link list to store per_frame parameters */ + struct list_head per_frame_params; + + unsigned int buffers_in_css; + + /* irq_lock is used to protect video buffer state change operations and + * also to make activeq, activeq_out, capq and outq list + * operations atomic. */ + spinlock_t irq_lock; + unsigned int users; + + struct atomisp_device *isp; + struct v4l2_pix_format pix; + uint32_t sh_fmt; + + struct atomisp_sub_device *asd; + + /* + * This frame_config_id is got from CSS when dequueues buffers from CSS, + * it is used to indicate which parameter it has applied. + */ + unsigned int frame_config_id[VIDEO_MAX_FRAME]; + /* + * This config id is set when camera HAL enqueues buffer, it has a + * non-zero value to indicate which parameter it needs to applu + */ + unsigned int frame_request_config_id[VIDEO_MAX_FRAME]; + struct atomisp_css_params_with_list *frame_params[VIDEO_MAX_FRAME]; +#ifdef ISP2401 + + /* + * move wdt from asd struct to create wdt for each pipe + */ + struct timer_list wdt; + unsigned int wdt_duration; /* in jiffies */ + unsigned long wdt_expires; + atomic_t wdt_count; +#endif +}; + +struct atomisp_acc_pipe { + struct video_device vdev; + unsigned int users; + bool running; + struct atomisp_sub_device *asd; + struct atomisp_device *isp; +}; + +struct atomisp_pad_format { + struct v4l2_mbus_framefmt fmt; + struct v4l2_rect crop; + struct v4l2_rect compose; +}; + +/* Internal states for flash process */ +enum atomisp_flash_state { + ATOMISP_FLASH_IDLE, + ATOMISP_FLASH_REQUESTED, + ATOMISP_FLASH_ONGOING, + ATOMISP_FLASH_DONE +}; + +/* + * This structure is used to cache the CSS parameters, it aligns to + * struct ia_css_isp_config but without un-supported and deprecated parts. + */ +struct atomisp_css_params { + struct ia_css_wb_config wb_config; + struct ia_css_cc_config cc_config; + struct ia_css_tnr_config tnr_config; + struct ia_css_ecd_config ecd_config; + struct ia_css_ynr_config ynr_config; + struct ia_css_fc_config fc_config; + struct ia_css_formats_config formats_config; + struct ia_css_cnr_config cnr_config; + struct ia_css_macc_config macc_config; + struct ia_css_ctc_config ctc_config; + struct ia_css_aa_config aa_config; + struct ia_css_aa_config baa_config; + struct ia_css_ce_config ce_config; + struct ia_css_ob_config ob_config; + struct ia_css_dp_config dp_config; + struct ia_css_de_config de_config; + struct ia_css_gc_config gc_config; + struct ia_css_nr_config nr_config; + struct ia_css_ee_config ee_config; + struct ia_css_anr_config anr_config; + struct ia_css_3a_config s3a_config; + struct ia_css_xnr_config xnr_config; + struct ia_css_dz_config dz_config; + struct ia_css_cc_config yuv2rgb_cc_config; + struct ia_css_cc_config rgb2yuv_cc_config; + struct ia_css_macc_table macc_table; + struct ia_css_gamma_table gamma_table; + struct ia_css_ctc_table ctc_table; + + struct ia_css_xnr_table xnr_table; + struct ia_css_rgb_gamma_table r_gamma_table; + struct ia_css_rgb_gamma_table g_gamma_table; + struct ia_css_rgb_gamma_table b_gamma_table; + + struct ia_css_vector motion_vector; + struct ia_css_anr_thres anr_thres; + + struct ia_css_dvs_6axis_config *dvs_6axis; + struct ia_css_dvs2_coefficients *dvs2_coeff; + struct ia_css_shading_table *shading_table; + struct ia_css_morph_table *morph_table; + + /* + * Used to store the user pointer address of the frame. driver needs to + * translate to ia_css_frame * and then set to CSS. + */ + void *output_frame; + uint32_t isp_config_id; + + /* Indicates which parameters need to be updated. */ + struct atomisp_parameters update_flag; +}; + +struct atomisp_subdev_params { + /* FIXME: Determines whether raw capture buffer are being passed to + * user space. Unimplemented for now. */ + int online_process; + int yuv_ds_en; + unsigned int color_effect; + bool gdc_cac_en; + bool macc_en; + bool bad_pixel_en; + bool video_dis_en; + bool sc_en; + bool fpn_en; + bool xnr_en; + bool low_light; + int false_color; + unsigned int histogram_elenum; + + /* Current grid info */ + struct atomisp_css_grid_info curr_grid_info; + enum atomisp_css_pipe_id s3a_enabled_pipe; + + int s3a_output_bytes; + + bool dis_proj_data_valid; + + struct ia_css_dz_config dz_config; /**< Digital Zoom */ + struct ia_css_capture_config capture_config; + + struct atomisp_css_isp_config config; + + /* current configurations */ + struct atomisp_css_params css_param; + + /* + * Intermediate buffers used to communicate data between + * CSS and user space. + */ + struct ia_css_3a_statistics *s3a_user_stat; + + void *metadata_user[ATOMISP_METADATA_TYPE_NUM]; + uint32_t metadata_width_size; + + struct ia_css_dvs2_statistics *dvs_stat; + struct atomisp_css_dvs_6axis *dvs_6axis; + uint32_t exp_id; + int dvs_hor_coef_bytes; + int dvs_ver_coef_bytes; + int dvs_ver_proj_bytes; + int dvs_hor_proj_bytes; + + /* Flash */ + int num_flash_frames; + enum atomisp_flash_state flash_state; + enum atomisp_frame_status last_frame_status; + + /* continuous capture */ + struct atomisp_cont_capture_conf offline_parm; + /* Flag to check if driver needs to update params to css */ + bool css_update_params_needed; +}; + +struct atomisp_css_params_with_list { + /* parameters for CSS */ + struct atomisp_css_params params; + struct list_head list; +}; + +struct atomisp_acc_fw { + struct atomisp_css_fw_info *fw; + unsigned int handle; + unsigned int flags; + unsigned int type; + struct { + size_t length; + unsigned long css_ptr; + } args[ATOMISP_ACC_NR_MEMORY]; + struct list_head list; +}; + +struct atomisp_map { + ia_css_ptr ptr; + size_t length; + struct list_head list; + /* FIXME: should keep book which maps are currently used + * by binaries and not allow releasing those + * which are in use. Implement by reference counting. + */ +}; + +struct atomisp_sub_device { + struct v4l2_subdev subdev; + struct media_pad pads[ATOMISP_SUBDEV_PADS_NUM]; + struct atomisp_pad_format fmt[ATOMISP_SUBDEV_PADS_NUM]; + uint16_t capture_pad; /* main capture pad; defines much of isp config */ + + enum atomisp_subdev_input_entity input; + unsigned int output; + struct atomisp_video_pipe video_in; + struct atomisp_video_pipe video_out_capture; /* capture output */ + struct atomisp_video_pipe video_out_vf; /* viewfinder output */ + struct atomisp_video_pipe video_out_preview; /* preview output */ + struct atomisp_acc_pipe video_acc; + /* video pipe main output */ + struct atomisp_video_pipe video_out_video_capture; + /* struct isp_subdev_params params; */ + spinlock_t lock; + struct atomisp_device *isp; + struct v4l2_ctrl_handler ctrl_handler; + struct v4l2_ctrl *fmt_auto; + struct v4l2_ctrl *run_mode; + struct v4l2_ctrl *depth_mode; + struct v4l2_ctrl *vfpp; + struct v4l2_ctrl *continuous_mode; + struct v4l2_ctrl *continuous_raw_buffer_size; + struct v4l2_ctrl *continuous_viewfinder; + struct v4l2_ctrl *enable_raw_buffer_lock; +#ifdef ISP2401 + struct v4l2_ctrl *ion_dev_fd; +#endif + struct v4l2_ctrl *disable_dz; +#ifdef ISP2401 + struct v4l2_ctrl *select_isp_version; +#endif + + struct { + struct list_head fw; + struct list_head memory_maps; + struct atomisp_css_pipeline *pipeline; + bool extension_mode; + struct ida ida; + struct completion acc_done; + void *acc_stages; + } acc; + + struct atomisp_subdev_params params; + + struct atomisp_stream_env stream_env[ATOMISP_INPUT_STREAM_NUM]; + + struct v4l2_pix_format dvs_envelop; + unsigned int s3a_bufs_in_css[CSS_PIPE_ID_NUM]; + unsigned int dis_bufs_in_css; + + unsigned int metadata_bufs_in_css + [ATOMISP_INPUT_STREAM_NUM][CSS_PIPE_ID_NUM]; + /* The list of free and available metadata buffers for CSS */ + struct list_head metadata[ATOMISP_METADATA_TYPE_NUM]; + /* The list of metadata buffers which have been en-queued to CSS */ + struct list_head metadata_in_css[ATOMISP_METADATA_TYPE_NUM]; + /* The list of metadata buffers which are ready for userspace to get */ + struct list_head metadata_ready[ATOMISP_METADATA_TYPE_NUM]; + + /* The list of free and available s3a stat buffers for CSS */ + struct list_head s3a_stats; + /* The list of s3a stat buffers which have been en-queued to CSS */ + struct list_head s3a_stats_in_css; + /* The list of s3a stat buffers which are ready for userspace to get */ + struct list_head s3a_stats_ready; + + struct list_head dis_stats; + struct list_head dis_stats_in_css; + spinlock_t dis_stats_lock; + + struct atomisp_css_frame *vf_frame; /* TODO: needed? */ + struct atomisp_css_frame *raw_output_frame; + enum atomisp_frame_status frame_status[VIDEO_MAX_FRAME]; + + /* This field specifies which camera (v4l2 input) is selected. */ + int input_curr; + /* This field specifies which sensor is being selected when there + are multiple sensors connected to the same MIPI port. */ + int sensor_curr; + + atomic_t sof_count; + atomic_t sequence; /* Sequence value that is assigned to buffer. */ + atomic_t sequence_temp; + + unsigned int streaming; /* Hold both mutex and lock to change this */ + bool stream_prepared; /* whether css stream is created */ + + /* subdev index: will be used to show which subdev is holding the + * resource, like which camera is used by which subdev + */ + unsigned int index; + + /* delayed memory allocation for css */ + struct completion init_done; + struct workqueue_struct *delayed_init_workq; + unsigned int delayed_init; + struct work_struct delayed_init_work; + + unsigned int latest_preview_exp_id; /* CSS ZSL/SDV raw buffer id */ + + unsigned int mipi_frame_size; + + bool copy_mode; /* CSI2+ use copy mode */ + bool yuvpp_mode; /* CSI2+ yuvpp pipe */ + + int raw_buffer_bitmap[ATOMISP_MAX_EXP_ID/32 + 1]; /* Record each Raw Buffer lock status */ + int raw_buffer_locked_count; + spinlock_t raw_buffer_bitmap_lock; + +#ifndef ISP2401 + struct timer_list wdt; + unsigned int wdt_duration; /* in jiffies */ + unsigned long wdt_expires; + +#endif + struct atomisp_resolution sensor_array_res; + bool high_speed_mode; /* Indicate whether now is a high speed mode */ + int pending_capture_request; /* Indicates the number of pending capture requests. */ +#ifndef ISP2401 + +#else + bool re_trigger_capture; +#endif + unsigned int preview_exp_id; + unsigned int postview_exp_id; +}; + +extern const struct atomisp_in_fmt_conv atomisp_in_fmt_conv[]; + +u32 atomisp_subdev_uncompressed_code(u32 code); +bool atomisp_subdev_is_compressed(u32 code); +const struct atomisp_in_fmt_conv *atomisp_find_in_fmt_conv(u32 code); +#ifndef ISP2401 +const struct atomisp_in_fmt_conv *atomisp_find_in_fmt_conv_by_atomisp_in_fmt( + enum atomisp_css_stream_format atomisp_in_fmt); +#else +const struct atomisp_in_fmt_conv + *atomisp_find_in_fmt_conv_by_atomisp_in_fmt(enum atomisp_css_stream_format + atomisp_in_fmt); +#endif +const struct atomisp_in_fmt_conv *atomisp_find_in_fmt_conv_compressed(u32 code); +bool atomisp_subdev_format_conversion(struct atomisp_sub_device *asd, + unsigned int source_pad); +uint16_t atomisp_subdev_source_pad(struct video_device *vdev); + +/* Get pointer to appropriate format */ +struct v4l2_mbus_framefmt +*atomisp_subdev_get_ffmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, uint32_t which, + uint32_t pad); +struct v4l2_rect *atomisp_subdev_get_rect(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + uint32_t which, uint32_t pad, + uint32_t target); +int atomisp_subdev_set_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + uint32_t which, uint32_t pad, uint32_t target, + uint32_t flags, struct v4l2_rect *r); +/* Actually set the format */ +void atomisp_subdev_set_ffmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, uint32_t which, + uint32_t pad, struct v4l2_mbus_framefmt *ffmt); + +int atomisp_update_run_mode(struct atomisp_sub_device *asd); + +void atomisp_subdev_cleanup_pending_events(struct atomisp_sub_device *asd); + +void atomisp_subdev_unregister_entities(struct atomisp_sub_device *asd); +int atomisp_subdev_register_entities(struct atomisp_sub_device *asd, + struct v4l2_device *vdev); +int atomisp_subdev_init(struct atomisp_device *isp); +void atomisp_subdev_cleanup(struct atomisp_device *isp); +int atomisp_create_pads_links(struct atomisp_device *isp); + +#endif /* __ATOMISP_SUBDEV_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_tables.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_tables.h new file mode 100644 index 0000000000000000000000000000000000000000..af09218d8b713035f68d44032feaf38e09211dbf --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_tables.h @@ -0,0 +1,191 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#ifndef __ATOMISP_TABLES_H__ +#define __ATOMISP_TABLES_H__ + +#include "sh_css_params.h" + +/*Sepia image effect table*/ +static struct atomisp_css_cc_config sepia_cc_config = { + .fraction_bits = 8, + .matrix = {141, 18, 68, -40, -5, -19, 35, 4, 16}, +}; + +/*Negative image effect table*/ +static struct atomisp_css_cc_config nega_cc_config = { + .fraction_bits = 8, + .matrix = {255, 29, 120, 0, 374, 342, 0, 672, -301}, +}; + +/*Mono image effect table*/ +static struct atomisp_css_cc_config mono_cc_config = { + .fraction_bits = 8, + .matrix = {255, 29, 120, 0, 0, 0, 0, 0, 0}, +}; + +/*Skin whiten image effect table*/ +static struct atomisp_css_macc_table skin_low_macc_table = { + .data = { + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 7168, 0, 2048, 8192, + 5120, -1024, 2048, 8192, + 8192, 2048, -1024, 5120, + 8192, 2048, 0, 7168, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192 + } +}; + +static struct atomisp_css_macc_table skin_medium_macc_table = { + .data = { + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 5120, 0, 6144, 8192, + 3072, -1024, 2048, 6144, + 6144, 2048, -1024, 3072, + 8192, 6144, 0, 5120, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192 + } +}; + +static struct atomisp_css_macc_table skin_high_macc_table = { + .data = { + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 4096, 0, 8192, 8192, + 0, -2048, 4096, 6144, + 6144, 4096, -2048, 0, + 8192, 8192, 0, 4096, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192 + } +}; + +/*Blue enhencement image effect table*/ +static struct atomisp_css_macc_table blue_macc_table = { + .data = { + 9728, -3072, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 9728, 0, -3072, 8192, + 12800, 1536, -3072, 8192, + 11264, 0, 0, 11264, + 9728, -3072, 0, 11264 + } +}; + +/*Green enhencement image effect table*/ +static struct atomisp_css_macc_table green_macc_table = { + .data = { + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 10240, 4096, 0, 8192, + 10240, 4096, 0, 12288, + 12288, 0, 0, 12288, + 14336, -2048, 4096, 8192, + 10240, 0, 4096, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192, + 8192, 0, 0, 8192 + } +}; + +static struct atomisp_css_ctc_table vivid_ctc_table = { + .data.vamem_2 = { + 0, 384, 837, 957, 1011, 1062, 1083, 1080, + 1078, 1077, 1053, 1039, 1012, 992, 969, 951, + 929, 906, 886, 866, 845, 823, 809, 790, + 772, 758, 741, 726, 711, 701, 688, 675, + 666, 656, 648, 639, 633, 626, 618, 612, + 603, 594, 582, 572, 557, 545, 529, 516, + 504, 491, 480, 467, 459, 447, 438, 429, + 419, 412, 404, 397, 389, 382, 376, 368, + 363, 357, 351, 345, 340, 336, 330, 326, + 321, 318, 312, 308, 304, 300, 297, 294, + 291, 286, 284, 281, 278, 275, 271, 268, + 261, 257, 251, 245, 240, 235, 232, 225, + 223, 218, 213, 209, 206, 204, 199, 197, + 193, 189, 186, 185, 183, 179, 177, 175, + 172, 170, 169, 167, 164, 164, 162, 160, + 158, 157, 156, 154, 154, 152, 151, 150, + 149, 148, 146, 147, 146, 144, 143, 143, + 142, 141, 140, 141, 139, 138, 138, 138, + 137, 136, 136, 135, 134, 134, 134, 133, + 132, 132, 131, 130, 131, 130, 129, 128, + 129, 127, 127, 127, 127, 125, 125, 125, + 123, 123, 122, 120, 118, 115, 114, 111, + 110, 108, 106, 105, 103, 102, 100, 99, + 97, 97, 96, 95, 94, 93, 93, 91, + 91, 91, 90, 90, 89, 89, 88, 88, + 89, 88, 88, 87, 87, 87, 87, 86, + 87, 87, 86, 87, 86, 86, 84, 84, + 82, 80, 78, 76, 74, 72, 70, 68, + 67, 65, 62, 60, 58, 56, 55, 54, + 53, 51, 49, 49, 47, 45, 45, 45, + 41, 40, 39, 39, 34, 33, 34, 32, + 25, 23, 24, 20, 13, 9, 12, 0, + 0 + } +}; +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_tpg.c b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_tpg.c new file mode 100644 index 0000000000000000000000000000000000000000..996d1bdebad4dfe9546738ed5962355ca5eae81c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_tpg.c @@ -0,0 +1,181 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include +#include +#include "atomisp_internal.h" +#include "atomisp_tpg.h" + +static int tpg_s_stream(struct v4l2_subdev *sd, int enable) +{ + return 0; +} + +static int tpg_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *param) +{ + /*to fake*/ + return 0; +} + +static int tpg_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *param) +{ + /*to fake*/ + return 0; +} + +static int tpg_get_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + /*to fake*/ + return 0; +} + +static int tpg_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_format *format) +{ + struct v4l2_mbus_framefmt *fmt = &format->format; + if (format->pad) + return -EINVAL; + /* only raw8 grbg is supported by TPG */ + fmt->code = MEDIA_BUS_FMT_SGRBG8_1X8; + if (format->which == V4L2_SUBDEV_FORMAT_TRY) { + cfg->try_fmt = *fmt; + return 0; + } + return 0; +} + +static int tpg_log_status(struct v4l2_subdev *sd) +{ + /*to fake*/ + return 0; +} + +static int tpg_s_power(struct v4l2_subdev *sd, int on) +{ + return 0; +} + +static int tpg_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_mbus_code_enum *code) +{ + /*to fake*/ + return 0; +} + +static int tpg_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_size_enum *fse) +{ + /*to fake*/ + return 0; +} + +static int tpg_enum_frame_ival(struct v4l2_subdev *sd, + struct v4l2_subdev_pad_config *cfg, + struct v4l2_subdev_frame_interval_enum *fie) +{ + /*to fake*/ + return 0; +} + +static const struct v4l2_subdev_video_ops tpg_video_ops = { + .s_stream = tpg_s_stream, + .g_parm = tpg_g_parm, + .s_parm = tpg_s_parm, +}; + +static const struct v4l2_subdev_core_ops tpg_core_ops = { + .log_status = tpg_log_status, + .s_power = tpg_s_power, +}; + +static const struct v4l2_subdev_pad_ops tpg_pad_ops = { + .enum_mbus_code = tpg_enum_mbus_code, + .enum_frame_size = tpg_enum_frame_size, + .enum_frame_interval = tpg_enum_frame_ival, + .get_fmt = tpg_get_fmt, + .set_fmt = tpg_set_fmt, +}; + +static const struct v4l2_subdev_ops tpg_ops = { + .core = &tpg_core_ops, + .video = &tpg_video_ops, + .pad = &tpg_pad_ops, +}; + +void atomisp_tpg_unregister_entities(struct atomisp_tpg_device *tpg) +{ + media_entity_cleanup(&tpg->sd.entity); + v4l2_device_unregister_subdev(&tpg->sd); +} + +int atomisp_tpg_register_entities(struct atomisp_tpg_device *tpg, + struct v4l2_device *vdev) +{ + int ret; + /* Register the subdev and video nodes. */ + ret = v4l2_device_register_subdev(vdev, &tpg->sd); + if (ret < 0) + goto error; + + return 0; + +error: + atomisp_tpg_unregister_entities(tpg); + return ret; +} + +void atomisp_tpg_cleanup(struct atomisp_device *isp) +{ + +} + +int atomisp_tpg_init(struct atomisp_device *isp) +{ + struct atomisp_tpg_device *tpg = &isp->tpg; + struct v4l2_subdev *sd = &tpg->sd; + struct media_pad *pads = tpg->pads; + struct media_entity *me = &sd->entity; + int ret; + + tpg->isp = isp; + v4l2_subdev_init(sd, &tpg_ops); + sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; + strcpy(sd->name, "tpg_subdev"); + v4l2_set_subdevdata(sd, tpg); + + pads[0].flags = MEDIA_PAD_FL_SINK; + me->function = MEDIA_ENT_F_V4L2_SUBDEV_UNKNOWN; + + ret = media_entity_pads_init(me, 1, pads); + if (ret < 0) + goto fail; + return 0; +fail: + atomisp_tpg_cleanup(isp); + return ret; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_tpg.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_tpg.h new file mode 100644 index 0000000000000000000000000000000000000000..64ab60f02e858827808a90970d7d27c6aff1cbe7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_tpg.h @@ -0,0 +1,42 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __ATOMISP_TPG_H__ +#define __ATOMISP_TPG_H__ + +#include +#include + +struct atomisp_tpg_device { + struct v4l2_subdev sd; + struct atomisp_device *isp; + struct media_pad pads[1]; +}; + +void atomisp_tpg_cleanup(struct atomisp_device *isp); +int atomisp_tpg_init(struct atomisp_device *isp); +void atomisp_tpg_unregister_entities(struct atomisp_tpg_device *tpg); +int atomisp_tpg_register_entities(struct atomisp_tpg_device *tpg, + struct v4l2_device *vdev); + +#endif /* __ATOMISP_TPG_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_trace_event.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_trace_event.h new file mode 100644 index 0000000000000000000000000000000000000000..5ce282d6c9395159da37877fcc0de5d6b95e6585 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_trace_event.h @@ -0,0 +1,133 @@ +/* + * Support Camera Imaging tracer core. + * + * Copyright (c) 2013 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#undef TRACE_SYSTEM +#define TRACE_SYSTEM atomisp + +#if !defined(ATOMISP_TRACE_EVENT_H) || defined(TRACE_HEADER_MULTI_READ) +#define ATOMISP_TRACE_EVENT_H + +#include +#include +TRACE_EVENT(camera_meminfo, + + TP_PROTO(const char *name, int uptr_size, int counter, int sys_size, + int sys_res_size, int cam_sys_use, int cam_dyc_use, + int cam_res_use), + + TP_ARGS(name, uptr_size, counter, sys_size, sys_res_size, cam_sys_use, + cam_dyc_use, cam_res_use), + + TP_STRUCT__entry( + __array(char, name, 24) + __field(int, uptr_size) + __field(int, counter) + __field(int, sys_size) + __field(int, sys_res_size) + __field(int, cam_res_use) + __field(int, cam_dyc_use) + __field(int, cam_sys_use) + ), + + TP_fast_assign( + strlcpy(__entry->name, name, 24); + __entry->uptr_size = uptr_size; + __entry->counter = counter; + __entry->sys_size = sys_size; + __entry->sys_res_size = sys_res_size; + __entry->cam_res_use = cam_res_use; + __entry->cam_dyc_use = cam_dyc_use; + __entry->cam_sys_use = cam_sys_use; + ), + + TP_printk( + "<%s> User ptr memory:%d pages,\tISP private memory used:%d" + " pages:\tsysFP system size:%d,\treserved size:%d" + "\tcamFP sysUse:%d,\tdycUse:%d,\tresUse:%d.\n", + __entry->name, __entry->uptr_size, __entry->counter, + __entry->sys_size, __entry->sys_res_size, __entry->cam_sys_use, + __entry->cam_dyc_use, __entry->cam_res_use) +); + +TRACE_EVENT(camera_debug, + + TP_PROTO(const char *name, char *info, const int line), + + TP_ARGS(name, info, line), + + TP_STRUCT__entry( + __array(char, name, 24) + __array(char, info, 24) + __field(int, line) + ), + + TP_fast_assign( + strlcpy(__entry->name, name, 24); + strlcpy(__entry->info, info, 24); + __entry->line = line; + ), + + TP_printk("<%s>-<%d> %s\n", __entry->name, __entry->line, + __entry->info) +); + +TRACE_EVENT(ipu_cstate, + + TP_PROTO(int cstate), + + TP_ARGS(cstate), + + TP_STRUCT__entry( + __field(int, cstate) + ), + + TP_fast_assign( + __entry->cstate = cstate; + ), + + TP_printk("cstate=%d", __entry->cstate) +); + +TRACE_EVENT(ipu_pstate, + + TP_PROTO(int freq, int util), + + TP_ARGS(freq, util), + + TP_STRUCT__entry( + __field(int, freq) + __field(int, util) + ), + + TP_fast_assign( + __entry->freq = freq; + __entry->util = util; + ), + + TP_printk("freq=%d util=%d", __entry->freq, __entry->util) +); +#endif + +#undef TRACE_INCLUDE_PATH +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_PATH . +#define TRACE_INCLUDE_FILE atomisp_trace_event +/* This part must be outside protection */ +#include diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_v4l2.c b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_v4l2.c new file mode 100644 index 0000000000000000000000000000000000000000..478d41f3485a39f08188d38896f540a32a7e8e41 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_v4l2.c @@ -0,0 +1,1649 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "atomisp_cmd.h" +#include "atomisp_common.h" +#include "atomisp_fops.h" +#include "atomisp_file.h" +#include "atomisp_ioctl.h" +#include "atomisp_internal.h" +#include "atomisp_acc.h" +#include "atomisp-regs.h" +#include "atomisp_dfs_tables.h" +#include "atomisp_drvfs.h" +#include "hmm/hmm.h" +#include "atomisp_trace_event.h" + +#include "hrt/hive_isp_css_mm_hrt.h" + +#include "device_access.h" +#include +#include + +/* G-Min addition: pull this in from intel_mid_pm.h */ +#define CSTATE_EXIT_LATENCY_C1 1 + +/* Moorefield lacks PCI PM, BYT advertises it but it's broken, use PUNIT */ +#define ATOMISP_INTERNAL_PM (IS_MOFD || IS_BYT || IS_CHT) + +#ifdef ISP2401 +static uint skip_fwload = 0; +module_param(skip_fwload, uint, 0644); +MODULE_PARM_DESC(skip_fwload, "Skip atomisp firmware load for COS"); + +#endif +/* set reserved memory pool size in page */ +unsigned int repool_pgnr; +module_param(repool_pgnr, uint, 0644); +MODULE_PARM_DESC(repool_pgnr, + "Set the reserved memory pool size in page (default:0)"); + +/* set dynamic memory pool size in page */ +unsigned int dypool_pgnr = UINT_MAX; +module_param(dypool_pgnr, uint, 0644); +MODULE_PARM_DESC(dypool_pgnr, + "Set the dynamic memory pool size in page (default:0)"); + +bool dypool_enable; +module_param(dypool_enable, bool, 0644); +MODULE_PARM_DESC(dypool_enable, + "dynamic memory pool enable/disable (default:disable)"); + +/* memory optimization: deferred firmware loading */ +bool defer_fw_load; +module_param(defer_fw_load, bool, 0644); +MODULE_PARM_DESC(defer_fw_load, + "Defer FW loading until device is opened (default:disable)"); + +/* cross componnet debug message flag */ +int dbg_level; +module_param(dbg_level, int, 0644); +MODULE_PARM_DESC(dbg_level, "debug message on/off (default:off)"); + +/* log function switch */ +int dbg_func = 2; +module_param(dbg_func, int, 0644); +MODULE_PARM_DESC(dbg_func, + "log function switch non/trace_printk/printk (default:printk)"); + +int mipicsi_flag; +module_param(mipicsi_flag, int, 0644); +MODULE_PARM_DESC(mipicsi_flag, "mipi csi compression predictor algorithm"); + +/*set to 16x16 since this is the amount of lines and pixels the sensor +exports extra. If these are kept at the 10x8 that they were on, in yuv +downscaling modes incorrect resolutions where requested to the sensor +driver with strange outcomes as a result. The proper way tot do this +would be to have a list of tables the specify the sensor res, mipi rec, +output res, and isp output res. however since we do not have this yet, +the chosen solution is the next best thing. */ +int pad_w = 16; +module_param(pad_w, int, 0644); +MODULE_PARM_DESC(pad_w, "extra data for ISP processing"); + +int pad_h = 16; +module_param(pad_h, int, 0644); +MODULE_PARM_DESC(pad_h, "extra data for ISP processing"); + +struct device *atomisp_dev; + +void __iomem *atomisp_io_base; + +int atomisp_video_init(struct atomisp_video_pipe *video, const char *name) +{ + int ret; + const char *direction; + + switch (video->type) { + case V4L2_BUF_TYPE_VIDEO_CAPTURE: + direction = "output"; + video->pad.flags = MEDIA_PAD_FL_SINK; + video->vdev.fops = &atomisp_fops; + video->vdev.ioctl_ops = &atomisp_ioctl_ops; + break; + case V4L2_BUF_TYPE_VIDEO_OUTPUT: + direction = "input"; + video->pad.flags = MEDIA_PAD_FL_SOURCE; + video->vdev.fops = &atomisp_file_fops; + video->vdev.ioctl_ops = &atomisp_file_ioctl_ops; + break; + default: + return -EINVAL; + } + + ret = media_entity_pads_init(&video->vdev.entity, 1, &video->pad); + if (ret < 0) + return ret; + + /* Initialize the video device. */ + snprintf(video->vdev.name, sizeof(video->vdev.name), + "ATOMISP ISP %s %s", name, direction); + video->vdev.release = video_device_release_empty; + video_set_drvdata(&video->vdev, video->isp); + + return 0; +} + +void atomisp_acc_init(struct atomisp_acc_pipe *video, const char *name) +{ + video->vdev.fops = &atomisp_fops; + video->vdev.ioctl_ops = &atomisp_ioctl_ops; + + /* Initialize the video device. */ + snprintf(video->vdev.name, sizeof(video->vdev.name), + "ATOMISP ISP %s", name); + video->vdev.release = video_device_release_empty; + video_set_drvdata(&video->vdev, video->isp); +} + +int atomisp_video_register(struct atomisp_video_pipe *video, + struct v4l2_device *vdev) +{ + int ret; + + video->vdev.v4l2_dev = vdev; + + ret = video_register_device(&video->vdev, VFL_TYPE_GRABBER, -1); + if (ret < 0) + dev_err(vdev->dev, "%s: could not register video device (%d)\n", + __func__, ret); + + return ret; +} + +int atomisp_acc_register(struct atomisp_acc_pipe *video, + struct v4l2_device *vdev) +{ + int ret; + + video->vdev.v4l2_dev = vdev; + + ret = video_register_device(&video->vdev, VFL_TYPE_GRABBER, -1); + if (ret < 0) + dev_err(vdev->dev, "%s: could not register video device (%d)\n", + __func__, ret); + + return ret; +} + +void atomisp_video_unregister(struct atomisp_video_pipe *video) +{ + if (video_is_registered(&video->vdev)) { + media_entity_cleanup(&video->vdev.entity); + video_unregister_device(&video->vdev); + } +} + +void atomisp_acc_unregister(struct atomisp_acc_pipe *video) +{ + if (video_is_registered(&video->vdev)) + video_unregister_device(&video->vdev); +} + +static int atomisp_save_iunit_reg(struct atomisp_device *isp) +{ + struct pci_dev *dev = isp->pdev; + + dev_dbg(isp->dev, "%s\n", __func__); + + pci_read_config_word(dev, PCI_COMMAND, &isp->saved_regs.pcicmdsts); + /* isp->saved_regs.ispmmadr is set from the atomisp_pci_probe() */ + pci_read_config_dword(dev, PCI_MSI_CAPID, &isp->saved_regs.msicap); + pci_read_config_dword(dev, PCI_MSI_ADDR, &isp->saved_regs.msi_addr); + pci_read_config_word(dev, PCI_MSI_DATA, &isp->saved_regs.msi_data); + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &isp->saved_regs.intr); + pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, + &isp->saved_regs.interrupt_control); + + pci_read_config_dword(dev, MRFLD_PCI_PMCS, + &isp->saved_regs.pmcs); + /* Ensure read/write combining is enabled. */ + pci_read_config_dword(dev, PCI_I_CONTROL, + &isp->saved_regs.i_control); + isp->saved_regs.i_control |= + MRFLD_PCI_I_CONTROL_ENABLE_READ_COMBINING | + MRFLD_PCI_I_CONTROL_ENABLE_WRITE_COMBINING; + pci_read_config_dword(dev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL, + &isp->saved_regs.csi_access_viol); + pci_read_config_dword(dev, MRFLD_PCI_CSI_RCOMP_CONTROL, + &isp->saved_regs.csi_rcomp_config); + /* + * Hardware bugs require setting CSI_HS_OVR_CLK_GATE_ON_UPDATE. + * ANN/CHV: RCOMP updates do not happen when using CSI2+ path + * and sensor sending "continuous clock". + * TNG/ANN/CHV: MIPI packets are lost if the HS entry sequence + * is missed, and IUNIT can hang. + * For both issues, setting this bit is a workaround. + */ + isp->saved_regs.csi_rcomp_config |= + MRFLD_PCI_CSI_HS_OVR_CLK_GATE_ON_UPDATE; + pci_read_config_dword(dev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, + &isp->saved_regs.csi_afe_dly); + pci_read_config_dword(dev, MRFLD_PCI_CSI_CONTROL, + &isp->saved_regs.csi_control); + if (isp->media_dev.hw_revision >= + (ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT)) + isp->saved_regs.csi_control |= + MRFLD_PCI_CSI_CONTROL_PARPATHEN; + /* + * On CHT CSI_READY bit should be enabled before stream on + */ + if (IS_CHT && (isp->media_dev.hw_revision >= ((ATOMISP_HW_REVISION_ISP2401 << + ATOMISP_HW_REVISION_SHIFT) | ATOMISP_HW_STEPPING_B0))) + isp->saved_regs.csi_control |= + MRFLD_PCI_CSI_CONTROL_CSI_READY; + pci_read_config_dword(dev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL, + &isp->saved_regs.csi_afe_rcomp_config); + pci_read_config_dword(dev, MRFLD_PCI_CSI_AFE_HS_CONTROL, + &isp->saved_regs.csi_afe_hs_control); + pci_read_config_dword(dev, MRFLD_PCI_CSI_DEADLINE_CONTROL, + &isp->saved_regs.csi_deadline_control); + return 0; +} + +static int atomisp_restore_iunit_reg(struct atomisp_device *isp) +{ + struct pci_dev *dev = isp->pdev; + + dev_dbg(isp->dev, "%s\n", __func__); + + pci_write_config_word(dev, PCI_COMMAND, isp->saved_regs.pcicmdsts); + pci_write_config_dword(dev, PCI_BASE_ADDRESS_0, + isp->saved_regs.ispmmadr); + pci_write_config_dword(dev, PCI_MSI_CAPID, isp->saved_regs.msicap); + pci_write_config_dword(dev, PCI_MSI_ADDR, isp->saved_regs.msi_addr); + pci_write_config_word(dev, PCI_MSI_DATA, isp->saved_regs.msi_data); + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, isp->saved_regs.intr); + pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, + isp->saved_regs.interrupt_control); + pci_write_config_dword(dev, PCI_I_CONTROL, + isp->saved_regs.i_control); + + pci_write_config_dword(dev, MRFLD_PCI_PMCS, + isp->saved_regs.pmcs); + pci_write_config_dword(dev, MRFLD_PCI_CSI_ACCESS_CTRL_VIOL, + isp->saved_regs.csi_access_viol); + pci_write_config_dword(dev, MRFLD_PCI_CSI_RCOMP_CONTROL, + isp->saved_regs.csi_rcomp_config); + pci_write_config_dword(dev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, + isp->saved_regs.csi_afe_dly); + pci_write_config_dword(dev, MRFLD_PCI_CSI_CONTROL, + isp->saved_regs.csi_control); + pci_write_config_dword(dev, MRFLD_PCI_CSI_AFE_RCOMP_CONTROL, + isp->saved_regs.csi_afe_rcomp_config); + pci_write_config_dword(dev, MRFLD_PCI_CSI_AFE_HS_CONTROL, + isp->saved_regs.csi_afe_hs_control); + pci_write_config_dword(dev, MRFLD_PCI_CSI_DEADLINE_CONTROL, + isp->saved_regs.csi_deadline_control); + + /* + * for MRFLD, Software/firmware needs to write a 1 to bit0 + * of the register at CSI_RECEIVER_SELECTION_REG to enable + * SH CSI backend write 0 will enable Arasan CSI backend, + * which has bugs(like sighting:4567697 and 4567699) and + * will be removed in B0 + */ + atomisp_store_uint32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1); + return 0; +} + +#ifdef CONFIG_PM +static int atomisp_mrfld_pre_power_down(struct atomisp_device *isp) +{ + struct pci_dev *dev = isp->pdev; + u32 irq; + unsigned long flags; + + spin_lock_irqsave(&isp->lock, flags); + if (isp->sw_contex.power_state == ATOM_ISP_POWER_DOWN) { + spin_unlock_irqrestore(&isp->lock, flags); + dev_dbg(isp->dev, "<%s %d.\n", __func__, __LINE__); + return 0; + } + /* + * MRFLD HAS requirement: cannot power off i-unit if + * ISP has IRQ not serviced. + * So, here we need to check if there is any pending + * IRQ, if so, waiting for it to be served + */ + pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq); + irq = irq & 1 << INTR_IIR; + pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, irq); + + pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq); + if (!(irq & (1 << INTR_IIR))) + goto done; + + atomisp_store_uint32(MRFLD_INTR_CLEAR_REG, 0xFFFFFFFF); + atomisp_load_uint32(MRFLD_INTR_STATUS_REG, &irq); + if (irq != 0) { + dev_err(isp->dev, + "%s: fail to clear isp interrupt status reg=0x%x\n", + __func__, irq); + spin_unlock_irqrestore(&isp->lock, flags); + return -EAGAIN; + } else { + pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq); + irq = irq & 1 << INTR_IIR; + pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, irq); + + pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq); + if (!(irq & (1 << INTR_IIR))) { + atomisp_store_uint32(MRFLD_INTR_ENABLE_REG, 0x0); + goto done; + } + dev_err(isp->dev, + "%s: error in iunit interrupt. status reg=0x%x\n", + __func__, irq); + spin_unlock_irqrestore(&isp->lock, flags); + return -EAGAIN; + } +done: + /* + * MRFLD WORKAROUND: + * before powering off IUNIT, clear the pending interrupts + * and disable the interrupt. driver should avoid writing 0 + * to IIR. It could block subsequent interrupt messages. + * HW sighting:4568410. + */ + pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq); + irq &= ~(1 << INTR_IER); + pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, irq); + + atomisp_msi_irq_uninit(isp, dev); + atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true); + spin_unlock_irqrestore(&isp->lock, flags); + + return 0; +} + + + /* + * WA for DDR DVFS enable/disable + * By default, ISP will force DDR DVFS 1600MHz before disable DVFS + */ +void punit_ddr_dvfs_enable(bool enable) +{ + int reg = intel_mid_msgbus_read32(PUNIT_PORT, MRFLD_ISPSSDVFS); + int door_bell = 1 << 8; + int max_wait = 30; + + if (enable) { + reg &= ~(MRFLD_BIT0 | MRFLD_BIT1); + } else { + reg |= (MRFLD_BIT1 | door_bell); + reg &= ~(MRFLD_BIT0); + } + + intel_mid_msgbus_write32(PUNIT_PORT, MRFLD_ISPSSDVFS, reg); + + /*Check Req_ACK to see freq status, wait until door_bell is cleared*/ + if (reg & door_bell) { + while (max_wait--) { + if (0 == (intel_mid_msgbus_read32(PUNIT_PORT, + MRFLD_ISPSSDVFS) & door_bell)) + break; + + usleep_range(100, 500); + } + } + + if (max_wait == 0) + pr_info("DDR DVFS, door bell is not cleared within 3ms\n"); +} + +/* Workaround for pmu_nc_set_power_state not ready in MRFLD */ +int atomisp_mrfld_power_down(struct atomisp_device *isp) +{ + unsigned long timeout; + u32 reg_value; + + /* writing 0x3 to ISPSSPM0 bit[1:0] to power off the IUNIT */ + reg_value = intel_mid_msgbus_read32(PUNIT_PORT, MRFLD_ISPSSPM0); + reg_value &= ~MRFLD_ISPSSPM0_ISPSSC_MASK; + reg_value |= MRFLD_ISPSSPM0_IUNIT_POWER_OFF; + intel_mid_msgbus_write32(PUNIT_PORT, MRFLD_ISPSSPM0, reg_value); + + /*WA:Enable DVFS*/ + if (IS_CHT) + punit_ddr_dvfs_enable(true); + + /* + * There should be no iunit access while power-down is + * in progress HW sighting: 4567865 + * FIXME: msecs_to_jiffies(50)- experienced value + */ + timeout = jiffies + msecs_to_jiffies(50); + while (1) { + reg_value = intel_mid_msgbus_read32(PUNIT_PORT, + MRFLD_ISPSSPM0); + dev_dbg(isp->dev, "power-off in progress, ISPSSPM0: 0x%x\n", + reg_value); + /* wait until ISPSSPM0 bit[25:24] shows 0x3 */ + if ((reg_value >> MRFLD_ISPSSPM0_ISPSSS_OFFSET) == + MRFLD_ISPSSPM0_IUNIT_POWER_OFF) { + trace_ipu_cstate(0); + return 0; + } + + if (time_after(jiffies, timeout)) { + dev_err(isp->dev, "power-off iunit timeout.\n"); + return -EBUSY; + } + /* FIXME: experienced value for delay */ + usleep_range(100, 150); + }; +} + + +/* Workaround for pmu_nc_set_power_state not ready in MRFLD */ +int atomisp_mrfld_power_up(struct atomisp_device *isp) +{ + unsigned long timeout; + u32 reg_value; + + /*WA for PUNIT, if DVFS enabled, ISP timeout observed*/ + if (IS_CHT) + punit_ddr_dvfs_enable(false); + + /* + * FIXME:WA for ECS28A, with this sleep, CTS + * android.hardware.camera2.cts.CameraDeviceTest#testCameraDeviceAbort + * PASS, no impact on other platforms + */ + if (IS_BYT) + msleep(10); + + /* writing 0x0 to ISPSSPM0 bit[1:0] to power off the IUNIT */ + reg_value = intel_mid_msgbus_read32(PUNIT_PORT, MRFLD_ISPSSPM0); + reg_value &= ~MRFLD_ISPSSPM0_ISPSSC_MASK; + intel_mid_msgbus_write32(PUNIT_PORT, MRFLD_ISPSSPM0, reg_value); + + /* FIXME: experienced value for delay */ + timeout = jiffies + msecs_to_jiffies(50); + while (1) { + reg_value = intel_mid_msgbus_read32(PUNIT_PORT, MRFLD_ISPSSPM0); + dev_dbg(isp->dev, "power-on in progress, ISPSSPM0: 0x%x\n", + reg_value); + /* wait until ISPSSPM0 bit[25:24] shows 0x0 */ + if ((reg_value >> MRFLD_ISPSSPM0_ISPSSS_OFFSET) == + MRFLD_ISPSSPM0_IUNIT_POWER_ON) { + trace_ipu_cstate(1); + return 0; + } + + if (time_after(jiffies, timeout)) { + dev_err(isp->dev, "power-on iunit timeout.\n"); + return -EBUSY; + } + /* FIXME: experienced value for delay */ + usleep_range(100, 150); + }; +} + +int atomisp_runtime_suspend(struct device *dev) +{ + struct atomisp_device *isp = (struct atomisp_device *) + dev_get_drvdata(dev); + int ret; + + ret = atomisp_mrfld_pre_power_down(isp); + if (ret) + return ret; + + /*Turn off the ISP d-phy*/ + ret = atomisp_ospm_dphy_down(isp); + if (ret) + return ret; + pm_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE); + if (ATOMISP_INTERNAL_PM) + ret = atomisp_mrfld_power_down(isp); + + return ret; +} + +int atomisp_runtime_resume(struct device *dev) +{ + struct atomisp_device *isp = (struct atomisp_device *) + dev_get_drvdata(dev); + int ret; + + if (ATOMISP_INTERNAL_PM) { + ret = atomisp_mrfld_power_up(isp); + if (ret) + return ret; + } + + pm_qos_update_request(&isp->pm_qos, isp->max_isr_latency); + if (isp->sw_contex.power_state == ATOM_ISP_POWER_DOWN) { + /*Turn on ISP d-phy */ + ret = atomisp_ospm_dphy_up(isp); + if (ret) { + dev_err(isp->dev, "Failed to power up ISP!.\n"); + return -EINVAL; + } + } + + /*restore register values for iUnit and iUnitPHY registers*/ + if (isp->saved_regs.pcicmdsts) + atomisp_restore_iunit_reg(isp); + + atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true); + return 0; +} + +static int atomisp_suspend(struct device *dev) +{ + struct atomisp_device *isp = (struct atomisp_device *) + dev_get_drvdata(dev); + /* FIXME: only has one isp_subdev at present */ + struct atomisp_sub_device *asd = &isp->asd[0]; + unsigned long flags; + int ret; + + /* + * FIXME: Suspend is not supported by sensors. Abort if any video + * node was opened. + */ + if (atomisp_dev_users(isp)) + return -EBUSY; + + spin_lock_irqsave(&isp->lock, flags); + if (asd->streaming != ATOMISP_DEVICE_STREAMING_DISABLED) { + spin_unlock_irqrestore(&isp->lock, flags); + dev_err(isp->dev, "atomisp cannot suspend at this time.\n"); + return -EINVAL; + } + spin_unlock_irqrestore(&isp->lock, flags); + + ret = atomisp_mrfld_pre_power_down(isp); + if (ret) + return ret; + + /*Turn off the ISP d-phy */ + ret = atomisp_ospm_dphy_down(isp); + if (ret) { + dev_err(isp->dev, "fail to power off ISP\n"); + return ret; + } + pm_qos_update_request(&isp->pm_qos, PM_QOS_DEFAULT_VALUE); + if (ATOMISP_INTERNAL_PM) + ret = atomisp_mrfld_power_down(isp); + + return ret; +} + +static int atomisp_resume(struct device *dev) +{ + struct atomisp_device *isp = (struct atomisp_device *) + dev_get_drvdata(dev); + int ret; + + if (ATOMISP_INTERNAL_PM) { + ret = atomisp_mrfld_power_up(isp); + if (ret) + return ret; + } + + pm_qos_update_request(&isp->pm_qos, isp->max_isr_latency); + + /*Turn on ISP d-phy */ + ret = atomisp_ospm_dphy_up(isp); + if (ret) { + dev_err(isp->dev, "Failed to power up ISP!.\n"); + return -EINVAL; + } + + /*restore register values for iUnit and iUnitPHY registers*/ + if (isp->saved_regs.pcicmdsts) + atomisp_restore_iunit_reg(isp); + + atomisp_freq_scaling(isp, ATOMISP_DFS_MODE_LOW, true); + return 0; +} +#endif + +int atomisp_csi_lane_config(struct atomisp_device *isp) +{ + static const struct { + u8 code; + u8 lanes[MRFLD_PORT_NUM]; + } portconfigs[] = { + /* Tangier/Merrifield available lane configurations */ + { 0x00, { 4, 1, 0 } }, /* 00000 */ + { 0x01, { 3, 1, 0 } }, /* 00001 */ + { 0x02, { 2, 1, 0 } }, /* 00010 */ + { 0x03, { 1, 1, 0 } }, /* 00011 */ + { 0x04, { 2, 1, 2 } }, /* 00100 */ + { 0x08, { 3, 1, 1 } }, /* 01000 */ + { 0x09, { 2, 1, 1 } }, /* 01001 */ + { 0x0a, { 1, 1, 1 } }, /* 01010 */ + + /* Anniedale/Moorefield only configurations */ + { 0x10, { 4, 2, 0 } }, /* 10000 */ + { 0x11, { 3, 2, 0 } }, /* 10001 */ + { 0x12, { 2, 2, 0 } }, /* 10010 */ + { 0x13, { 1, 2, 0 } }, /* 10011 */ + { 0x14, { 2, 2, 2 } }, /* 10100 */ + { 0x18, { 3, 2, 1 } }, /* 11000 */ + { 0x19, { 2, 2, 1 } }, /* 11001 */ + { 0x1a, { 1, 2, 1 } }, /* 11010 */ + }; + + unsigned int i, j; + u8 sensor_lanes[MRFLD_PORT_NUM] = { 0 }; + u32 csi_control; + int nportconfigs; + u32 port_config_mask; + int port3_lanes_shift; + + if (isp->media_dev.hw_revision < + ATOMISP_HW_REVISION_ISP2401_LEGACY << + ATOMISP_HW_REVISION_SHIFT) { + /* Merrifield */ + port_config_mask = MRFLD_PORT_CONFIG_MASK; + port3_lanes_shift = MRFLD_PORT3_LANES_SHIFT; + } else { + /* Moorefield / Cherryview */ + port_config_mask = CHV_PORT_CONFIG_MASK; + port3_lanes_shift = CHV_PORT3_LANES_SHIFT; + } + + if (isp->media_dev.hw_revision < + ATOMISP_HW_REVISION_ISP2401 << + ATOMISP_HW_REVISION_SHIFT) { + /* Merrifield / Moorefield legacy input system */ + nportconfigs = MRFLD_PORT_CONFIG_NUM; + } else { + /* Moorefield / Cherryview new input system */ + nportconfigs = ARRAY_SIZE(portconfigs); + } + + for (i = 0; i < isp->input_cnt; i++) { + struct camera_mipi_info *mipi_info; + + if (isp->inputs[i].type != RAW_CAMERA && + isp->inputs[i].type != SOC_CAMERA) + continue; + + mipi_info = atomisp_to_sensor_mipi_info(isp->inputs[i].camera); + if (!mipi_info) + continue; + + switch (mipi_info->port) { + case ATOMISP_CAMERA_PORT_PRIMARY: + sensor_lanes[0] = mipi_info->num_lanes; + break; + case ATOMISP_CAMERA_PORT_SECONDARY: + sensor_lanes[1] = mipi_info->num_lanes; + break; + case ATOMISP_CAMERA_PORT_TERTIARY: + sensor_lanes[2] = mipi_info->num_lanes; + break; + default: + dev_err(isp->dev, + "%s: invalid port: %d for the %dth sensor\n", + __func__, mipi_info->port, i); + return -EINVAL; + } + } + + for (i = 0; i < nportconfigs; i++) { + for (j = 0; j < MRFLD_PORT_NUM; j++) + if (sensor_lanes[j] && + sensor_lanes[j] != portconfigs[i].lanes[j]) + break; + + if (j == MRFLD_PORT_NUM) + break; /* Found matching setting */ + } + + if (i >= nportconfigs) { + dev_err(isp->dev, + "%s: could not find the CSI port setting for %d-%d-%d\n", + __func__, + sensor_lanes[0], sensor_lanes[1], sensor_lanes[2]); + return -EINVAL; + } + + pci_read_config_dword(isp->pdev, MRFLD_PCI_CSI_CONTROL, &csi_control); + csi_control &= ~port_config_mask; + csi_control |= (portconfigs[i].code << MRFLD_PORT_CONFIGCODE_SHIFT) + | (portconfigs[i].lanes[0] ? 0 : (1 << MRFLD_PORT1_ENABLE_SHIFT)) + | (portconfigs[i].lanes[1] ? 0 : (1 << MRFLD_PORT2_ENABLE_SHIFT)) + | (portconfigs[i].lanes[2] ? 0 : (1 << MRFLD_PORT3_ENABLE_SHIFT)) + | (((1 << portconfigs[i].lanes[0]) - 1) << MRFLD_PORT1_LANES_SHIFT) + | (((1 << portconfigs[i].lanes[1]) - 1) << MRFLD_PORT2_LANES_SHIFT) + | (((1 << portconfigs[i].lanes[2]) - 1) << port3_lanes_shift); + + pci_write_config_dword(isp->pdev, MRFLD_PCI_CSI_CONTROL, csi_control); + + dev_dbg(isp->dev, + "%s: the portconfig is %d-%d-%d, CSI_CONTROL is 0x%08X\n", + __func__, portconfigs[i].lanes[0], portconfigs[i].lanes[1], + portconfigs[i].lanes[2], csi_control); + + return 0; +} + +static int atomisp_subdev_probe(struct atomisp_device *isp) +{ + const struct atomisp_platform_data *pdata; + struct intel_v4l2_subdev_table *subdevs; + int ret, raw_index = -1; + + pdata = atomisp_get_platform_data(); + if (pdata == NULL) { + dev_err(isp->dev, "no platform data available\n"); + return 0; + } + + for (subdevs = pdata->subdevs; subdevs->type; ++subdevs) { + struct v4l2_subdev *subdev; + struct i2c_board_info *board_info = + &subdevs->v4l2_subdev.board_info; + struct i2c_adapter *adapter = + i2c_get_adapter(subdevs->v4l2_subdev.i2c_adapter_id); + struct camera_sensor_platform_data *sensor_pdata; + int sensor_num, i; + + if (adapter == NULL) { + dev_err(isp->dev, + "Failed to find i2c adapter for subdev %s\n", + board_info->type); + break; + } + + /* In G-Min, the sensor devices will already be probed + * (via ACPI) and registered, do not create new + * ones */ + subdev = atomisp_gmin_find_subdev(adapter, board_info); + ret = v4l2_device_register_subdev(&isp->v4l2_dev, subdev); + if (ret) { + dev_warn(isp->dev, "Subdev %s detection fail\n", + board_info->type); + continue; + } + + if (subdev == NULL) { + dev_warn(isp->dev, "Subdev %s detection fail\n", + board_info->type); + continue; + } + + dev_info(isp->dev, "Subdev %s successfully register\n", + board_info->type); + + switch (subdevs->type) { + case RAW_CAMERA: + raw_index = isp->input_cnt; + dev_dbg(isp->dev, "raw_index: %d\n", raw_index); + case SOC_CAMERA: + dev_dbg(isp->dev, "SOC_INDEX: %d\n", isp->input_cnt); + if (isp->input_cnt >= ATOM_ISP_MAX_INPUTS) { + dev_warn(isp->dev, + "too many atomisp inputs, ignored\n"); + break; + } + + isp->inputs[isp->input_cnt].type = subdevs->type; + isp->inputs[isp->input_cnt].port = subdevs->port; + isp->inputs[isp->input_cnt].camera = subdev; + isp->inputs[isp->input_cnt].sensor_index = 0; + /* + * initialize the subdev frame size, then next we can + * judge whether frame_size store effective value via + * pixel_format. + */ + isp->inputs[isp->input_cnt].frame_size.pixel_format = 0; + sensor_pdata = (struct camera_sensor_platform_data *) + board_info->platform_data; + if (sensor_pdata->get_camera_caps) + isp->inputs[isp->input_cnt].camera_caps = + sensor_pdata->get_camera_caps(); + else + isp->inputs[isp->input_cnt].camera_caps = + atomisp_get_default_camera_caps(); + sensor_num = isp->inputs[isp->input_cnt] + .camera_caps->sensor_num; + isp->input_cnt++; + for (i = 1; i < sensor_num; i++) { + if (isp->input_cnt >= ATOM_ISP_MAX_INPUTS) { + dev_warn(isp->dev, + "atomisp inputs out of range\n"); + break; + } + isp->inputs[isp->input_cnt] = + isp->inputs[isp->input_cnt - 1]; + isp->inputs[isp->input_cnt].sensor_index = i; + isp->input_cnt++; + } + break; + case CAMERA_MOTOR: + isp->motor = subdev; + break; + case LED_FLASH: + case XENON_FLASH: + isp->flash = subdev; + break; + default: + dev_dbg(isp->dev, "unknown subdev probed\n"); + break; + } + + } + + /* + * HACK: Currently VCM belongs to primary sensor only, but correct + * approach must be to acquire from platform code which sensor + * owns it. + */ + if (isp->motor && raw_index >= 0) + isp->inputs[raw_index].motor = isp->motor; + + /* Proceed even if no modules detected. For COS mode and no modules. */ + if (!isp->inputs[0].camera) + dev_warn(isp->dev, "no camera attached or fail to detect\n"); + + return atomisp_csi_lane_config(isp); +} + +static void atomisp_unregister_entities(struct atomisp_device *isp) +{ + unsigned int i; + struct v4l2_subdev *sd, *next; + + for (i = 0; i < isp->num_of_streams; i++) + atomisp_subdev_unregister_entities(&isp->asd[i]); + atomisp_tpg_unregister_entities(&isp->tpg); + atomisp_file_input_unregister_entities(&isp->file_dev); + for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) + atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]); + + list_for_each_entry_safe(sd, next, &isp->v4l2_dev.subdevs, list) + v4l2_device_unregister_subdev(sd); + + v4l2_device_unregister(&isp->v4l2_dev); + media_device_unregister(&isp->media_dev); +} + +static int atomisp_register_entities(struct atomisp_device *isp) +{ + int ret = 0; + unsigned int i; + + isp->media_dev.dev = isp->dev; + + strlcpy(isp->media_dev.model, "Intel Atom ISP", + sizeof(isp->media_dev.model)); +#ifndef ISP2401 + +#endif + media_device_init(&isp->media_dev); + isp->v4l2_dev.mdev = &isp->media_dev; + ret = v4l2_device_register(isp->dev, &isp->v4l2_dev); + if (ret < 0) { + dev_err(isp->dev, "%s: V4L2 device registration failed (%d)\n", + __func__, ret); + goto v4l2_device_failed; + } + + ret = atomisp_subdev_probe(isp); + if (ret < 0) + goto csi_and_subdev_probe_failed; + + /* Register internal entities */ + for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) { + ret = atomisp_mipi_csi2_register_entities(&isp->csi2_port[i], + &isp->v4l2_dev); + if (ret == 0) + continue; + + /* error case */ + dev_err(isp->dev, "failed to register the CSI port: %d\n", i); + /* deregister all registered CSI ports */ + while (i--) + atomisp_mipi_csi2_unregister_entities( + &isp->csi2_port[i]); + + goto csi_and_subdev_probe_failed; + } + + ret = + atomisp_file_input_register_entities(&isp->file_dev, &isp->v4l2_dev); + if (ret < 0) { + dev_err(isp->dev, "atomisp_file_input_register_entities\n"); + goto file_input_register_failed; + } + + ret = atomisp_tpg_register_entities(&isp->tpg, &isp->v4l2_dev); + if (ret < 0) { + dev_err(isp->dev, "atomisp_tpg_register_entities\n"); + goto tpg_register_failed; + } + + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd = &isp->asd[i]; + + ret = atomisp_subdev_register_entities(asd, &isp->v4l2_dev); + if (ret < 0) { + dev_err(isp->dev, + "atomisp_subdev_register_entities fail\n"); + for (; i > 0; i--) + atomisp_subdev_unregister_entities( + &isp->asd[i - 1]); + goto subdev_register_failed; + } + } + + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd = &isp->asd[i]; + + init_completion(&asd->init_done); + + asd->delayed_init_workq = + alloc_workqueue(isp->v4l2_dev.name, WQ_CPU_INTENSIVE, + 1); + if (asd->delayed_init_workq == NULL) { + dev_err(isp->dev, + "Failed to initialize delayed init workq\n"); + ret = -ENOMEM; + + for (; i > 0; i--) + destroy_workqueue(isp->asd[i - 1]. + delayed_init_workq); + goto wq_alloc_failed; + } + INIT_WORK(&asd->delayed_init_work, atomisp_delayed_init_work); + } + + for (i = 0; i < isp->input_cnt; i++) { + if (isp->inputs[i].port >= ATOMISP_CAMERA_NR_PORTS) { + dev_err(isp->dev, "isp->inputs port %d not supported\n", + isp->inputs[i].port); + ret = -EINVAL; + goto link_failed; + } + } + + dev_dbg(isp->dev, + "FILE_INPUT enable, camera_cnt: %d\n", isp->input_cnt); + isp->inputs[isp->input_cnt].type = FILE_INPUT; + isp->inputs[isp->input_cnt].port = -1; + isp->inputs[isp->input_cnt].camera_caps = + atomisp_get_default_camera_caps(); + isp->inputs[isp->input_cnt++].camera = &isp->file_dev.sd; + + if (isp->input_cnt < ATOM_ISP_MAX_INPUTS) { + dev_dbg(isp->dev, + "TPG detected, camera_cnt: %d\n", isp->input_cnt); + isp->inputs[isp->input_cnt].type = TEST_PATTERN; + isp->inputs[isp->input_cnt].port = -1; + isp->inputs[isp->input_cnt].camera_caps = + atomisp_get_default_camera_caps(); + isp->inputs[isp->input_cnt++].camera = &isp->tpg.sd; + } else { + dev_warn(isp->dev, "too many atomisp inputs, TPG ignored.\n"); + } + + ret = v4l2_device_register_subdev_nodes(&isp->v4l2_dev); + if (ret < 0) + goto link_failed; + + return media_device_register(&isp->media_dev); + +link_failed: + for (i = 0; i < isp->num_of_streams; i++) + destroy_workqueue(isp->asd[i]. + delayed_init_workq); +wq_alloc_failed: + for (i = 0; i < isp->num_of_streams; i++) + atomisp_subdev_unregister_entities( + &isp->asd[i]); +subdev_register_failed: + atomisp_tpg_unregister_entities(&isp->tpg); +tpg_register_failed: + atomisp_file_input_unregister_entities(&isp->file_dev); +file_input_register_failed: + for (i = 0; i < ATOMISP_CAMERA_NR_PORTS; i++) + atomisp_mipi_csi2_unregister_entities(&isp->csi2_port[i]); +csi_and_subdev_probe_failed: + v4l2_device_unregister(&isp->v4l2_dev); +v4l2_device_failed: + media_device_unregister(&isp->media_dev); + media_device_cleanup(&isp->media_dev); + return ret; +} + +static int atomisp_initialize_modules(struct atomisp_device *isp) +{ + int ret; + + ret = atomisp_mipi_csi2_init(isp); + if (ret < 0) { + dev_err(isp->dev, "mipi csi2 initialization failed\n"); + goto error_mipi_csi2; + } + + ret = atomisp_file_input_init(isp); + if (ret < 0) { + dev_err(isp->dev, + "file input device initialization failed\n"); + goto error_file_input; + } + + ret = atomisp_tpg_init(isp); + if (ret < 0) { + dev_err(isp->dev, "tpg initialization failed\n"); + goto error_tpg; + } + + ret = atomisp_subdev_init(isp); + if (ret < 0) { + dev_err(isp->dev, "ISP subdev initialization failed\n"); + goto error_isp_subdev; + } + + + return 0; + +error_isp_subdev: +error_tpg: + atomisp_tpg_cleanup(isp); +error_file_input: + atomisp_file_input_cleanup(isp); +error_mipi_csi2: + atomisp_mipi_csi2_cleanup(isp); + return ret; +} + +static void atomisp_uninitialize_modules(struct atomisp_device *isp) +{ + atomisp_tpg_cleanup(isp); + atomisp_file_input_cleanup(isp); + atomisp_mipi_csi2_cleanup(isp); +} + +const struct firmware * +atomisp_load_firmware(struct atomisp_device *isp) +{ + const struct firmware *fw; + int rc; + char *fw_path = NULL; + +#ifdef ISP2401 + if (skip_fwload) + return NULL; + +#endif +#if defined(ATOMISP_FWNAME) + fw_path = ATOMISP_FWNAME; +#else + if (isp->media_dev.driver_version == ATOMISP_CSS_VERSION_21) { + if (isp->media_dev.hw_revision == + ((ATOMISP_HW_REVISION_ISP2401 << ATOMISP_HW_REVISION_SHIFT) + | ATOMISP_HW_STEPPING_A0)) + fw_path = "shisp_2401a0_v21.bin"; + + if (isp->media_dev.hw_revision == + ((ATOMISP_HW_REVISION_ISP2401_LEGACY << ATOMISP_HW_REVISION_SHIFT) + | ATOMISP_HW_STEPPING_A0)) + fw_path = "shisp_2401a0_legacy_v21.bin"; + + if (isp->media_dev.hw_revision == + ((ATOMISP_HW_REVISION_ISP2400 << ATOMISP_HW_REVISION_SHIFT) + | ATOMISP_HW_STEPPING_B0)) + fw_path = "shisp_2400b0_v21.bin"; + } +#endif + + if (!fw_path) { + dev_err(isp->dev, + "Unsupported driver_version 0x%x, hw_revision 0x%x\n", + isp->media_dev.driver_version, + isp->media_dev.hw_revision); + return NULL; + } + + rc = request_firmware(&fw, fw_path, isp->dev); + if (rc) { + dev_err(isp->dev, + "atomisp: Error %d while requesting firmware %s\n", + rc, fw_path); + return NULL; + } + + return fw; +} + +/* + * Check for flags the driver was compiled with against the PCI + * device. Always returns true on other than ISP 2400. + */ +static bool is_valid_device(struct pci_dev *dev, + const struct pci_device_id *id) +{ + unsigned int a0_max_id; + + switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) { + case ATOMISP_PCI_DEVICE_SOC_MRFLD: + a0_max_id = ATOMISP_PCI_REV_MRFLD_A0_MAX; + break; + case ATOMISP_PCI_DEVICE_SOC_BYT: + a0_max_id = ATOMISP_PCI_REV_BYT_A0_MAX; + break; + default: + return true; + } + + return dev->revision > a0_max_id; +} + +static int init_atomisp_wdts(struct atomisp_device *isp) +{ + int i, err; + + atomic_set(&isp->wdt_work_queued, 0); + isp->wdt_work_queue = alloc_workqueue(isp->v4l2_dev.name, 0, 1); + if (isp->wdt_work_queue == NULL) { + dev_err(isp->dev, "Failed to initialize wdt work queue\n"); + err = -ENOMEM; + goto alloc_fail; + } + INIT_WORK(&isp->wdt_work, atomisp_wdt_work); + + for (i = 0; i < isp->num_of_streams; i++) { + struct atomisp_sub_device *asd = &isp->asd[i]; + asd = &isp->asd[i]; +#ifndef ISP2401 + setup_timer(&asd->wdt, atomisp_wdt, (unsigned long)isp); +#else + setup_timer(&asd->video_out_capture.wdt, + atomisp_wdt, (unsigned long)&asd->video_out_capture); + setup_timer(&asd->video_out_preview.wdt, + atomisp_wdt, (unsigned long)&asd->video_out_preview); + setup_timer(&asd->video_out_vf.wdt, + atomisp_wdt, (unsigned long)&asd->video_out_vf); + setup_timer(&asd->video_out_video_capture.wdt, + atomisp_wdt, + (unsigned long)&asd->video_out_video_capture); +#endif + } + return 0; +alloc_fail: + return err; +} + +static struct pci_driver atomisp_pci_driver; + +#define ATOM_ISP_PCI_BAR 0 + +static int atomisp_pci_probe(struct pci_dev *dev, + const struct pci_device_id *id) +{ + const struct atomisp_platform_data *pdata; + struct atomisp_device *isp; + unsigned int start; + void __iomem *base; + int err, val; + u32 irq; + + if (!dev) { + dev_err(&dev->dev, "atomisp: error device ptr\n"); + return -EINVAL; + } + + if (!is_valid_device(dev, id)) + return -ENODEV; + /* Pointer to struct device. */ + atomisp_dev = &dev->dev; + + pdata = atomisp_get_platform_data(); + if (pdata == NULL) + dev_warn(&dev->dev, "no platform data available\n"); + + err = pcim_enable_device(dev); + if (err) { + dev_err(&dev->dev, "Failed to enable CI ISP device (%d)\n", + err); + return err; + } + + start = pci_resource_start(dev, ATOM_ISP_PCI_BAR); + dev_dbg(&dev->dev, "start: 0x%x\n", start); + + err = pcim_iomap_regions(dev, 1 << ATOM_ISP_PCI_BAR, pci_name(dev)); + if (err) { + dev_err(&dev->dev, "Failed to I/O memory remapping (%d)\n", + err); + return err; + } + + base = pcim_iomap_table(dev)[ATOM_ISP_PCI_BAR]; + dev_dbg(&dev->dev, "base: %p\n", base); + + atomisp_io_base = base; + + dev_dbg(&dev->dev, "atomisp_io_base: %p\n", atomisp_io_base); + + isp = devm_kzalloc(&dev->dev, sizeof(struct atomisp_device), GFP_KERNEL); + if (!isp) { + dev_err(&dev->dev, "Failed to alloc CI ISP structure\n"); + return -ENOMEM; + } + isp->pdev = dev; + isp->dev = &dev->dev; + isp->sw_contex.power_state = ATOM_ISP_POWER_UP; + isp->pci_root = pci_get_bus_and_slot(0, 0); + if (!isp->pci_root) { + dev_err(&dev->dev, "Unable to find PCI host\n"); + return -ENODEV; + } + isp->saved_regs.ispmmadr = start; + + rt_mutex_init(&isp->mutex); + mutex_init(&isp->streamoff_mutex); + spin_lock_init(&isp->lock); + + /* This is not a true PCI device on SoC, so the delay is not needed. */ + isp->pdev->d3_delay = 0; + + isp->media_dev.driver_version = ATOMISP_CSS_VERSION_21; + switch (id->device & ATOMISP_PCI_DEVICE_SOC_MASK) { + case ATOMISP_PCI_DEVICE_SOC_MRFLD: + isp->media_dev.hw_revision = + (ATOMISP_HW_REVISION_ISP2400 + << ATOMISP_HW_REVISION_SHIFT) | + ATOMISP_HW_STEPPING_B0; + + switch (id->device) { + case ATOMISP_PCI_DEVICE_SOC_MRFLD_1179: + isp->dfs = &dfs_config_merr_1179; + break; + case ATOMISP_PCI_DEVICE_SOC_MRFLD_117A: + isp->dfs = &dfs_config_merr_117a; + break; + default: + isp->dfs = &dfs_config_merr; + break; + } + isp->hpll_freq = HPLL_FREQ_1600MHZ; + break; + case ATOMISP_PCI_DEVICE_SOC_BYT: + isp->media_dev.hw_revision = + (ATOMISP_HW_REVISION_ISP2400 + << ATOMISP_HW_REVISION_SHIFT) | + ATOMISP_HW_STEPPING_B0; +#ifdef FIXME + if (INTEL_MID_BOARD(3, TABLET, BYT, BLK, PRO, CRV2) || + INTEL_MID_BOARD(3, TABLET, BYT, BLK, ENG, CRV2)) { + isp->dfs = &dfs_config_byt_cr; + isp->hpll_freq = HPLL_FREQ_2000MHZ; + } else +#endif + { + isp->dfs = &dfs_config_byt; + isp->hpll_freq = HPLL_FREQ_1600MHZ; + } + /* HPLL frequency is known to be device-specific, but we don't + * have specs yet for exactly how it varies. Default to + * BYT-CR but let provisioning set it via EFI variable */ + isp->hpll_freq = gmin_get_var_int(&dev->dev, "HpllFreq", + HPLL_FREQ_2000MHZ); + + /* + * for BYT/CHT we are put isp into D3cold to avoid pci registers access + * in power off. Set d3cold_delay to 0 since default 100ms is not + * necessary. + */ + isp->pdev->d3cold_delay = 0; + break; + case ATOMISP_PCI_DEVICE_SOC_ANN: + isp->media_dev.hw_revision = ( +#ifdef ISP2401_NEW_INPUT_SYSTEM + ATOMISP_HW_REVISION_ISP2401 +#else + ATOMISP_HW_REVISION_ISP2401_LEGACY +#endif + << ATOMISP_HW_REVISION_SHIFT); + isp->media_dev.hw_revision |= isp->pdev->revision < 2 ? + ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0; + isp->dfs = &dfs_config_merr; + isp->hpll_freq = HPLL_FREQ_1600MHZ; + break; + case ATOMISP_PCI_DEVICE_SOC_CHT: + isp->media_dev.hw_revision = ( +#ifdef ISP2401_NEW_INPUT_SYSTEM + ATOMISP_HW_REVISION_ISP2401 +#else + ATOMISP_HW_REVISION_ISP2401_LEGACY +#endif + << ATOMISP_HW_REVISION_SHIFT); + isp->media_dev.hw_revision |= isp->pdev->revision < 2 ? + ATOMISP_HW_STEPPING_A0 : ATOMISP_HW_STEPPING_B0; + + isp->dfs = &dfs_config_cht; + isp->pdev->d3cold_delay = 0; + + val = intel_mid_msgbus_read32(CCK_PORT, CCK_FUSE_REG_0); + switch (val & CCK_FUSE_HPLL_FREQ_MASK) { + case 0x00: + isp->hpll_freq = HPLL_FREQ_800MHZ; + break; + case 0x01: + isp->hpll_freq = HPLL_FREQ_1600MHZ; + break; + case 0x02: + isp->hpll_freq = HPLL_FREQ_2000MHZ; + break; + default: + isp->hpll_freq = HPLL_FREQ_1600MHZ; + dev_warn(isp->dev, + "read HPLL from cck failed.default 1600MHz.\n"); + } + break; + default: + dev_err(&dev->dev, "un-supported IUNIT device\n"); + return -ENODEV; + } + + dev_info(&dev->dev, "ISP HPLL frequency base = %d MHz\n", + isp->hpll_freq); + + isp->max_isr_latency = ATOMISP_MAX_ISR_LATENCY; + + /* Load isp firmware from user space */ + if (!defer_fw_load) { + isp->firmware = atomisp_load_firmware(isp); + if (!isp->firmware) { + err = -ENOENT; + goto load_fw_fail; + } + + err = atomisp_css_check_firmware_version(isp); + if (err) { + dev_dbg(&dev->dev, "Firmware version check failed\n"); + goto fw_validation_fail; + } + } + + pci_set_master(dev); + pci_set_drvdata(dev, isp); + + err = pci_enable_msi(dev); + if (err) { + dev_err(&dev->dev, "Failed to enable msi (%d)\n", err); + goto enable_msi_fail; + } + + atomisp_msi_irq_init(isp, dev); + + pm_qos_add_request(&isp->pm_qos, PM_QOS_CPU_DMA_LATENCY, + PM_QOS_DEFAULT_VALUE); + + /* + * for MRFLD, Software/firmware needs to write a 1 to bit 0 of + * the register at CSI_RECEIVER_SELECTION_REG to enable SH CSI + * backend write 0 will enable Arasan CSI backend, which has + * bugs(like sighting:4567697 and 4567699) and will be removed + * in B0 + */ + atomisp_store_uint32(MRFLD_CSI_RECEIVER_SELECTION_REG, 1); + + if ((id->device & ATOMISP_PCI_DEVICE_SOC_MASK) == + ATOMISP_PCI_DEVICE_SOC_MRFLD) { + u32 csi_afe_trim; + + /* + * Workaround for imbalance data eye issue which is observed + * on TNG B0. + */ + pci_read_config_dword(dev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, + &csi_afe_trim); + csi_afe_trim &= ~((MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << + MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) | + (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << + MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) | + (MRFLD_PCI_CSI_HSRXCLKTRIM_MASK << + MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT)); + csi_afe_trim |= (MRFLD_PCI_CSI1_HSRXCLKTRIM << + MRFLD_PCI_CSI1_HSRXCLKTRIM_SHIFT) | + (MRFLD_PCI_CSI2_HSRXCLKTRIM << + MRFLD_PCI_CSI2_HSRXCLKTRIM_SHIFT) | + (MRFLD_PCI_CSI3_HSRXCLKTRIM << + MRFLD_PCI_CSI3_HSRXCLKTRIM_SHIFT); + pci_write_config_dword(dev, MRFLD_PCI_CSI_AFE_TRIM_CONTROL, + csi_afe_trim); + } + + err = atomisp_initialize_modules(isp); + if (err < 0) { + dev_err(&dev->dev, "atomisp_initialize_modules (%d)\n", err); + goto initialize_modules_fail; + } + + err = atomisp_register_entities(isp); + if (err < 0) { + dev_err(&dev->dev, "atomisp_register_entities failed (%d)\n", + err); + goto register_entities_fail; + } + err = atomisp_create_pads_links(isp); + if (err < 0) + goto register_entities_fail; + /* init atomisp wdts */ + if (init_atomisp_wdts(isp) != 0) + goto wdt_work_queue_fail; + + /* save the iunit context only once after all the values are init'ed. */ + atomisp_save_iunit_reg(isp); + + pm_runtime_put_noidle(&dev->dev); + pm_runtime_allow(&dev->dev); + + hmm_init_mem_stat(repool_pgnr, dypool_enable, dypool_pgnr); + err = hmm_pool_register(repool_pgnr, HMM_POOL_TYPE_RESERVED); + if (err) { + dev_err(&dev->dev, "Failed to register reserved memory pool.\n"); + goto hmm_pool_fail; + } + + /* Init ISP memory management */ + hrt_isp_css_mm_init(); + + err = devm_request_threaded_irq(&dev->dev, dev->irq, + atomisp_isr, atomisp_isr_thread, + IRQF_SHARED, "isp_irq", isp); + if (err) { + dev_err(&dev->dev, "Failed to request irq (%d)\n", err); + goto request_irq_fail; + } + + /* Load firmware into ISP memory */ + if (!defer_fw_load) { + err = atomisp_css_load_firmware(isp); + if (err) { + dev_err(&dev->dev, "Failed to init css.\n"); + goto css_init_fail; + } + } else { + dev_dbg(&dev->dev, "Skip css init.\n"); + } + /* Clear FW image from memory */ + release_firmware(isp->firmware); + isp->firmware = NULL; + isp->css_env.isp_css_fw.data = NULL; + + atomisp_drvfs_init(&atomisp_pci_driver, isp); + + return 0; + +css_init_fail: + devm_free_irq(&dev->dev, dev->irq, isp); +request_irq_fail: + hrt_isp_css_mm_clear(); + hmm_pool_unregister(HMM_POOL_TYPE_RESERVED); +hmm_pool_fail: + destroy_workqueue(isp->wdt_work_queue); +wdt_work_queue_fail: + atomisp_acc_cleanup(isp); + atomisp_unregister_entities(isp); +register_entities_fail: + atomisp_uninitialize_modules(isp); +initialize_modules_fail: + pm_qos_remove_request(&isp->pm_qos); + atomisp_msi_irq_uninit(isp, dev); +enable_msi_fail: +fw_validation_fail: + release_firmware(isp->firmware); +load_fw_fail: + /* + * Switch off ISP, as keeping it powered on would prevent + * reaching S0ix states. + * + * The following lines have been copied from atomisp suspend path + */ + + pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq); + irq = irq & 1 << INTR_IIR; + pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, irq); + + pci_read_config_dword(dev, PCI_INTERRUPT_CTRL, &irq); + irq &= ~(1 << INTR_IER); + pci_write_config_dword(dev, PCI_INTERRUPT_CTRL, irq); + + atomisp_msi_irq_uninit(isp, dev); + + atomisp_ospm_dphy_down(isp); +#ifndef ISP2401 + /* Address later when we worry about the ...field chips */ +#endif + if (ATOMISP_INTERNAL_PM) { + if (atomisp_mrfld_power_down(isp)) + dev_err(&dev->dev, "Failed to switch off ISP\n"); + } +#ifdef ISP2401 + +#endif + pci_dev_put(isp->pci_root); + return err; +} + +static void atomisp_pci_remove(struct pci_dev *dev) +{ + struct atomisp_device *isp = (struct atomisp_device *) + pci_get_drvdata(dev); + + atomisp_drvfs_exit(); + + atomisp_acc_cleanup(isp); + + atomisp_css_unload_firmware(isp); + hrt_isp_css_mm_clear(); + + pm_runtime_forbid(&dev->dev); + pm_runtime_get_noresume(&dev->dev); + pm_qos_remove_request(&isp->pm_qos); + + atomisp_msi_irq_uninit(isp, dev); + pci_dev_put(isp->pci_root); + + atomisp_unregister_entities(isp); + + destroy_workqueue(isp->wdt_work_queue); + atomisp_file_input_cleanup(isp); + + release_firmware(isp->firmware); + + hmm_pool_unregister(HMM_POOL_TYPE_RESERVED); +} + +static const struct pci_device_id atomisp_pci_tbl[] = { +#if defined(ISP2400) || defined(ISP2400B0) + /* Merrifield */ + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1178)}, + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1179)}, + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x117a)}, + /* Baytrail */ + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x0f38)}, +#elif defined(ISP2401) + /* Anniedale (Merrifield+ / Moorefield) */ + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x1478)}, + /* Cherrytrail */ + {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x22b8)}, +#endif + {0,} +}; + +MODULE_DEVICE_TABLE(pci, atomisp_pci_tbl); + +#ifdef CONFIG_PM +static const struct dev_pm_ops atomisp_pm_ops = { + .runtime_suspend = atomisp_runtime_suspend, + .runtime_resume = atomisp_runtime_resume, + .suspend = atomisp_suspend, + .resume = atomisp_resume, +}; + +#define DEV_PM_OPS (&atomisp_pm_ops) +#else +#define DEV_PM_OPS NULL +#endif + +static struct pci_driver atomisp_pci_driver = { + .driver = { + .pm = DEV_PM_OPS, + }, + .name = "atomisp-isp2", + .id_table = atomisp_pci_tbl, + .probe = atomisp_pci_probe, + .remove = atomisp_pci_remove, +}; + +static int __init atomisp_init(void) +{ + return pci_register_driver(&atomisp_pci_driver); +} + +static void __exit atomisp_exit(void) +{ + pci_unregister_driver(&atomisp_pci_driver); +} + +module_init(atomisp_init); +module_exit(atomisp_exit); + +MODULE_AUTHOR("Wen Wang "); +MODULE_AUTHOR("Xiaolin Zhang "); +MODULE_LICENSE("GPL"); +MODULE_DESCRIPTION("Intel ATOM Platform ISP Driver"); diff --git a/drivers/staging/media/atomisp/pci/atomisp2/atomisp_v4l2.h b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_v4l2.h new file mode 100644 index 0000000000000000000000000000000000000000..191b2e57a810af9763c283b010510e5e97aec521 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/atomisp_v4l2.h @@ -0,0 +1,44 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __ATOMISP_V4L2_H__ +#define __ATOMISP_V4L2_H__ + +struct atomisp_video_pipe; +struct atomisp_acc_pipe; +struct v4l2_device; +struct atomisp_device; +struct firmware; + +int atomisp_video_init(struct atomisp_video_pipe *video, const char *name); +void atomisp_acc_init(struct atomisp_acc_pipe *video, const char *name); +void atomisp_video_unregister(struct atomisp_video_pipe *video); +int atomisp_video_register(struct atomisp_video_pipe *video, + struct v4l2_device *vdev); +void atomisp_acc_unregister(struct atomisp_acc_pipe *video); +int atomisp_acc_register(struct atomisp_acc_pipe *video, + struct v4l2_device *vdev); +const struct firmware *atomisp_load_firmware(struct atomisp_device *isp); +int atomisp_csi_lane_config(struct atomisp_device *isp); + +#endif /* __ATOMISP_V4L2_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/Makefile b/drivers/staging/media/atomisp/pci/atomisp2/css2400/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..04defaafa02c90e79c1c17ce7e89dd775e16007f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/Makefile @@ -0,0 +1,4 @@ +ccflags-y += -DISP2400B0 +ISP2400B0 := y + +include $(srctree)/$(src)/../Makefile.common diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/interface/ia_css_circbuf.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/interface/ia_css_circbuf.h new file mode 100644 index 0000000000000000000000000000000000000000..2a38e2b7b8d36730ee242015a56ec6796f07be6b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/interface/ia_css_circbuf.h @@ -0,0 +1,386 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_CIRCBUF_H +#define _IA_CSS_CIRCBUF_H + +#include +#include +#include +#include +#include +#include +#include "ia_css_circbuf_comm.h" +#include "ia_css_circbuf_desc.h" +#ifdef __SP +#include "event_handler.sp.h" +/* We should not #define SP_FILE_ID here, because we are in a header file. */ +#include "ia_css_sp_assert_level.sp.h" +#endif + +/**************************************************************** + * + * Data structures. + * + ****************************************************************/ +/** + * @brief Data structure for the circular buffer. + */ +typedef struct ia_css_circbuf_s ia_css_circbuf_t; +struct ia_css_circbuf_s { + ia_css_circbuf_desc_t *desc; /* Pointer to the descriptor of the circbuf */ + ia_css_circbuf_elem_t *elems; /* an array of elements */ +}; + +/** + * @brief Create the circular buffer. + * + * @param cb The pointer to the circular buffer. + * @param elems An array of elements. + * @param desc The descriptor set to the size using ia_css_circbuf_desc_init(). + */ +STORAGE_CLASS_EXTERN void ia_css_circbuf_create( + ia_css_circbuf_t *cb, + ia_css_circbuf_elem_t *elems, + ia_css_circbuf_desc_t *desc); + +/** + * @brief Destroy the circular buffer. + * + * @param cb The pointer to the circular buffer. + */ +STORAGE_CLASS_EXTERN void ia_css_circbuf_destroy( + ia_css_circbuf_t *cb); + +/** + * @brief Pop a value out of the circular buffer. + * Get a value at the head of the circular buffer. + * The user should call "ia_css_circbuf_is_empty()" + * to avoid accessing to an empty buffer. + * + * @param cb The pointer to the circular buffer. + * + * @return the pop-out value. + */ +STORAGE_CLASS_EXTERN uint32_t ia_css_circbuf_pop( + ia_css_circbuf_t *cb); + +/** + * @brief Extract a value out of the circular buffer. + * Get a value at an arbitrary poistion in the circular + * buffer. The user should call "ia_css_circbuf_is_empty()" + * to avoid accessing to an empty buffer. + * + * @param cb The pointer to the circular buffer. + * @param offset The offset from "start" to the target position. + * + * @return the extracted value. + */ +STORAGE_CLASS_EXTERN uint32_t ia_css_circbuf_extract( + ia_css_circbuf_t *cb, + int offset); + +/**************************************************************** + * + * Inline functions. + * + ****************************************************************/ +/** + * @brief Set the "val" field in the element. + * + * @param elem The pointer to the element. + * @param val The value to be set. + */ +STORAGE_CLASS_INLINE void ia_css_circbuf_elem_set_val( + ia_css_circbuf_elem_t *elem, + uint32_t val) +{ + OP___assert(elem != NULL); + + elem->val = val; +} + +/** + * @brief Initialize the element. + * + * @param elem The pointer to the element. + */ +STORAGE_CLASS_INLINE void ia_css_circbuf_elem_init( + ia_css_circbuf_elem_t *elem) +{ + OP___assert(elem != NULL); + ia_css_circbuf_elem_set_val(elem, 0); +} + +/** + * @brief Copy an element. + * + * @param src The element as the copy source. + * @param dest The element as the copy destination. + */ +STORAGE_CLASS_INLINE void ia_css_circbuf_elem_cpy( + ia_css_circbuf_elem_t *src, + ia_css_circbuf_elem_t *dest) +{ + OP___assert(src != NULL); + OP___assert(dest != NULL); + + ia_css_circbuf_elem_set_val(dest, src->val); +} + +/** + * @brief Get position in the circular buffer. + * + * @param cb The pointer to the circular buffer. + * @param base The base position. + * @param offset The offset. + * + * @return the position at offset. + */ +STORAGE_CLASS_INLINE uint8_t ia_css_circbuf_get_pos_at_offset( + ia_css_circbuf_t *cb, + uint32_t base, + int offset) +{ + uint8_t dest; + + OP___assert(cb != NULL); + OP___assert(cb->desc != NULL); + OP___assert(cb->desc->size > 0); + + /* step 1: adjudst the offset */ + while (offset < 0) { + offset += cb->desc->size; + } + + /* step 2: shift and round by the upper limit */ + dest = OP_std_modadd(base, offset, cb->desc->size); + + return dest; +} + +/** + * @brief Get the offset between two positions in the circular buffer. + * Get the offset from the source position to the terminal position, + * along the direction in which the new elements come in. + * + * @param cb The pointer to the circular buffer. + * @param src_pos The source position. + * @param dest_pos The terminal position. + * + * @return the offset. + */ +STORAGE_CLASS_INLINE int ia_css_circbuf_get_offset( + ia_css_circbuf_t *cb, + uint32_t src_pos, + uint32_t dest_pos) +{ + int offset; + + OP___assert(cb != NULL); + OP___assert(cb->desc != NULL); + + offset = (int)(dest_pos - src_pos); + offset += (offset < 0) ? cb->desc->size : 0; + + return offset; +} + +/** + * @brief Get the maximum number of elements. + * + * @param cb The pointer to the circular buffer. + * + * @return the maximum number of elements. + * + * TODO: Test this API. + */ +STORAGE_CLASS_INLINE uint32_t ia_css_circbuf_get_size( + ia_css_circbuf_t *cb) +{ + OP___assert(cb != NULL); + OP___assert(cb->desc != NULL); + + return cb->desc->size; +} + +/** + * @brief Get the number of available elements. + * + * @param cb The pointer to the circular buffer. + * + * @return the number of available elements. + */ +STORAGE_CLASS_INLINE uint32_t ia_css_circbuf_get_num_elems( + ia_css_circbuf_t *cb) +{ + int num; + + OP___assert(cb != NULL); + OP___assert(cb->desc != NULL); + + num = ia_css_circbuf_get_offset(cb, cb->desc->start, cb->desc->end); + + return (uint32_t)num; +} + +/** + * @brief Test if the circular buffer is empty. + * + * @param cb The pointer to the circular buffer. + * + * @return + * - true when it is empty. + * - false when it is not empty. + */ +STORAGE_CLASS_INLINE bool ia_css_circbuf_is_empty( + ia_css_circbuf_t *cb) +{ + OP___assert(cb != NULL); + OP___assert(cb->desc != NULL); + + return ia_css_circbuf_desc_is_empty(cb->desc); +} + +/** + * @brief Test if the circular buffer is full. + * + * @param cb The pointer to the circular buffer. + * + * @return + * - true when it is full. + * - false when it is not full. + */ +STORAGE_CLASS_INLINE bool ia_css_circbuf_is_full(ia_css_circbuf_t *cb) +{ + OP___assert(cb != NULL); + OP___assert(cb->desc != NULL); + + return ia_css_circbuf_desc_is_full(cb->desc); +} + +/** + * @brief Write a new element into the circular buffer. + * Write a new element WITHOUT checking whether the + * circular buffer is full or not. So it also overwrites + * the oldest element when the buffer is full. + * + * @param cb The pointer to the circular buffer. + * @param elem The new element. + */ +STORAGE_CLASS_INLINE void ia_css_circbuf_write( + ia_css_circbuf_t *cb, + ia_css_circbuf_elem_t elem) +{ + OP___assert(cb != NULL); + OP___assert(cb->desc != NULL); + + /* Cannot continue as the queue is full*/ +#ifdef __SP + SP_ASSERT_FATAL(!ia_css_circbuf_is_full(cb)); +#else + assert(!ia_css_circbuf_is_full(cb)); +#endif + + ia_css_circbuf_elem_cpy(&elem, &cb->elems[cb->desc->end]); + + cb->desc->end = ia_css_circbuf_get_pos_at_offset(cb, cb->desc->end, 1); +} + +/** + * @brief Push a value in the circular buffer. + * Put a new value at the tail of the circular buffer. + * The user should call "ia_css_circbuf_is_full()" + * to avoid accessing to a full buffer. + * + * @param cb The pointer to the circular buffer. + * @param val The value to be pushed in. + */ +STORAGE_CLASS_INLINE void ia_css_circbuf_push( + ia_css_circbuf_t *cb, + uint32_t val) +{ + ia_css_circbuf_elem_t elem; + + OP___assert(cb != NULL); + + /* set up an element */ + ia_css_circbuf_elem_init(&elem); + ia_css_circbuf_elem_set_val(&elem, val); + + /* write the element into the buffer */ + ia_css_circbuf_write(cb, elem); +} + +/** + * @brief Get the number of free elements. + * + * @param cb The pointer to the circular buffer. + * + * @return: The number of free elements. + */ +STORAGE_CLASS_INLINE uint32_t ia_css_circbuf_get_free_elems( + ia_css_circbuf_t *cb) +{ + OP___assert(cb != NULL); + OP___assert(cb->desc != NULL); + + return ia_css_circbuf_desc_get_free_elems(cb->desc); +} + +/** + * @brief Peek an element in Circular Buffer. + * + * @param cb The pointer to the circular buffer. + * @param offset Offset to the element. + * + * @return the elements value. + */ +STORAGE_CLASS_EXTERN uint32_t ia_css_circbuf_peek( + ia_css_circbuf_t *cb, + int offset); + +/** + * @brief Get an element in Circular Buffer. + * + * @param cb The pointer to the circular buffer. + * @param offset Offset to the element. + * + * @return the elements value. + */ +STORAGE_CLASS_EXTERN uint32_t ia_css_circbuf_peek_from_start( + ia_css_circbuf_t *cb, + int offset); + +/** + * @brief Increase Size of a Circular Buffer. + * Use 'CAUTION' before using this function, This was added to + * support / fix issue with increasing size for tagger only + * + * @param cb The pointer to the circular buffer. + * @param sz_delta delta increase for new size + * @param elems (optional) pointers to new additional elements + * cb element array size will not be increased dynamically, + * but new elements should be added at the end to existing + * cb element array which if of max_size >= new size + * + * @return true on succesfully increasing the size + * false on failure + */ +STORAGE_CLASS_EXTERN bool ia_css_circbuf_increase_size( + ia_css_circbuf_t *cb, + unsigned int sz_delta, + ia_css_circbuf_elem_t *elems); + +#endif /*_IA_CSS_CIRCBUF_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/interface/ia_css_circbuf_comm.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/interface/ia_css_circbuf_comm.h new file mode 100644 index 0000000000000000000000000000000000000000..3fc0330b9526d12fc3ad9c1995f96d729bbe91ea --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/interface/ia_css_circbuf_comm.h @@ -0,0 +1,56 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_CIRCBUF_COMM_H +#define _IA_CSS_CIRCBUF_COMM_H + +#include /* uint8_t, uint32_t */ + +#define IA_CSS_CIRCBUF_PADDING 1 /* The circular buffer is implemented in lock-less manner, wherein + * the head and tail can advance independently without any locks. + * But to achieve this, an extra buffer element is required to detect + * queue full & empty conditions, wherein the tail trails the head for + * full and is equal to head for empty condition. This causes 1 buffer + * not being available for use. + */ + +/**************************************************************** + * + * Portable Data structures + * + ****************************************************************/ +/** + * @brief Data structure for the circular descriptor. + */ +typedef struct ia_css_circbuf_desc_s ia_css_circbuf_desc_t; +struct ia_css_circbuf_desc_s { + uint8_t size; /* the maximum number of elements*/ + uint8_t step; /* number of bytes per element */ + uint8_t start; /* index of the oldest element */ + uint8_t end; /* index at which to write the new element */ +}; +#define SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT \ + (4 * sizeof(uint8_t)) + +/** + * @brief Data structure for the circular buffer element. + */ +typedef struct ia_css_circbuf_elem_s ia_css_circbuf_elem_t; +struct ia_css_circbuf_elem_s { + uint32_t val; /* the value stored in the element */ +}; +#define SIZE_OF_IA_CSS_CIRCBUF_ELEM_S_STRUCT \ + (sizeof(uint32_t)) + +#endif /*_IA_CSS_CIRCBUF_COMM_H*/ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/interface/ia_css_circbuf_desc.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/interface/ia_css_circbuf_desc.h new file mode 100644 index 0000000000000000000000000000000000000000..a8447d409c312cff8f71055f16b723764ee6ffb2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/interface/ia_css_circbuf_desc.h @@ -0,0 +1,170 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_CIRCBUF_DESC_H_ +#define _IA_CSS_CIRCBUF_DESC_H_ + +#include +#include +#include +#include +#include +#include "ia_css_circbuf_comm.h" +/**************************************************************** + * + * Inline functions. + * + ****************************************************************/ +/** + * @brief Test if the circular buffer is empty. + * + * @param cb_desc The pointer to the circular buffer descriptor. + * + * @return + * - true when it is empty. + * - false when it is not empty. + */ +STORAGE_CLASS_INLINE bool ia_css_circbuf_desc_is_empty( + ia_css_circbuf_desc_t *cb_desc) +{ + OP___assert(cb_desc != NULL); + return (cb_desc->end == cb_desc->start); +} + +/** + * @brief Test if the circular buffer descriptor is full. + * + * @param cb_desc The pointer to the circular buffer + * descriptor. + * + * @return + * - true when it is full. + * - false when it is not full. + */ +STORAGE_CLASS_INLINE bool ia_css_circbuf_desc_is_full( + ia_css_circbuf_desc_t *cb_desc) +{ + OP___assert(cb_desc != NULL); + return (OP_std_modadd(cb_desc->end, 1, cb_desc->size) == cb_desc->start); +} + +/** + * @brief Initialize the circular buffer descriptor + * + * @param cb_desc The pointer circular buffer descriptor + * @param size The size of the circular buffer + */ +STORAGE_CLASS_INLINE void ia_css_circbuf_desc_init( + ia_css_circbuf_desc_t *cb_desc, + int8_t size) +{ + OP___assert(cb_desc != NULL); + cb_desc->size = size; +} + +/** + * @brief Get a position in the circular buffer descriptor. + * + * @param cb The pointer to the circular buffer descriptor. + * @param base The base position. + * @param offset The offset. + * + * @return the position in the circular buffer descriptor. + */ +STORAGE_CLASS_INLINE uint8_t ia_css_circbuf_desc_get_pos_at_offset( + ia_css_circbuf_desc_t *cb_desc, + uint32_t base, + int offset) +{ + uint8_t dest; + OP___assert(cb_desc != NULL); + OP___assert(cb_desc->size > 0); + + /* step 1: adjust the offset */ + while (offset < 0) { + offset += cb_desc->size; + } + + /* step 2: shift and round by the upper limit */ + dest = OP_std_modadd(base, offset, cb_desc->size); + + return dest; +} + +/** + * @brief Get the offset between two positions in the circular buffer + * descriptor. + * Get the offset from the source position to the terminal position, + * along the direction in which the new elements come in. + * + * @param cb_desc The pointer to the circular buffer descriptor. + * @param src_pos The source position. + * @param dest_pos The terminal position. + * + * @return the offset. + */ +STORAGE_CLASS_INLINE int ia_css_circbuf_desc_get_offset( + ia_css_circbuf_desc_t *cb_desc, + uint32_t src_pos, + uint32_t dest_pos) +{ + int offset; + OP___assert(cb_desc != NULL); + + offset = (int)(dest_pos - src_pos); + offset += (offset < 0) ? cb_desc->size : 0; + + return offset; +} + +/** + * @brief Get the number of available elements. + * + * @param cb_desc The pointer to the circular buffer. + * + * @return The number of available elements. + */ +STORAGE_CLASS_INLINE uint32_t ia_css_circbuf_desc_get_num_elems( + ia_css_circbuf_desc_t *cb_desc) +{ + int num; + OP___assert(cb_desc != NULL); + + num = ia_css_circbuf_desc_get_offset(cb_desc, + cb_desc->start, + cb_desc->end); + + return (uint32_t)num; +} + +/** + * @brief Get the number of free elements. + * + * @param cb_desc The pointer to the circular buffer descriptor. + * + * @return: The number of free elements. + */ +STORAGE_CLASS_INLINE uint32_t ia_css_circbuf_desc_get_free_elems( + ia_css_circbuf_desc_t *cb_desc) +{ + uint32_t num; + OP___assert(cb_desc != NULL); + + num = ia_css_circbuf_desc_get_offset(cb_desc, + cb_desc->start, + cb_desc->end); + + return (cb_desc->size - num); +} +#endif /*_IA_CSS_CIRCBUF_DESC_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/src/circbuf.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/src/circbuf.c new file mode 100644 index 0000000000000000000000000000000000000000..2493dd249fcb20c9011082149d0d1f2cc744c79e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/circbuf/src/circbuf.c @@ -0,0 +1,334 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_circbuf.h" + +#include + +#ifdef __SP +#include +#include +#ifndef SP_FILE_ID +#define SP_FILE_ID SP_FILE_ID_CIRCBUF /* overrule default in ia_css_sp_assert_level.sp.h */ +#endif +#include +#endif + +/********************************************************************** + * + * Forward declarations. + * + **********************************************************************/ +/** + * @brief Read the oldest element from the circular buffer. + * Read the oldest element WITHOUT checking whehter the + * circular buffer is empty or not. The oldest element is + * also removed out from the circular buffer. + * + * @param cb The pointer to the circular buffer. + * + * @return the oldest element. + */ +static inline ia_css_circbuf_elem_t +ia_css_circbuf_read(ia_css_circbuf_t *cb); + +/** + * @brief Shift a chunk of elements in the circular buffer. + * A chunk of elements (i.e. the ones from the "start" position + * to the "chunk_src" position) are shifted in the circular buffer, + * along the direction of new elements coming. + * + * @param cb The pointer to the circular buffer. + * @param chunk_src The position at which the first element in the chunk is. + * @param chunk_dest The position to which the first element in the chunk would be shift. + */ +static inline void ia_css_circbuf_shift_chunk(ia_css_circbuf_t *cb, + uint32_t chunk_src, + uint32_t chunk_dest); + +/** + * @brief Get the "val" field in the element. + * + * @param elem The pointer to the element. + * + * @return the "val" field. + */ +static inline uint32_t +ia_css_circbuf_elem_get_val(ia_css_circbuf_elem_t *elem); + +/********************************************************************** + * + * Non-inline functions. + * + **********************************************************************/ +/** + * @brief Create the circular buffer. + * Refer to "ia_css_circbuf.h" for details. + */ +void +ia_css_circbuf_create(ia_css_circbuf_t *cb, + ia_css_circbuf_elem_t *elems, + ia_css_circbuf_desc_t *desc) +{ + uint32_t i; + + OP___assert(desc); + + cb->desc = desc; + /* Initialize to defaults */ + cb->desc->start = 0; + cb->desc->end = 0; + cb->desc->step = 0; + + for (i = 0; i < cb->desc->size; i++) + ia_css_circbuf_elem_init(&elems[i]); + + cb->elems = elems; +} + +/** + * @brief Destroy the circular buffer. + * Refer to "ia_css_circbuf.h" for details. + */ +void ia_css_circbuf_destroy(ia_css_circbuf_t *cb) +{ + cb->desc = NULL; + + cb->elems = NULL; +} + +/** + * @brief Pop a value out of the circular buffer. + * Refer to "ia_css_circbuf.h" for details. + */ +uint32_t ia_css_circbuf_pop(ia_css_circbuf_t *cb) +{ + uint32_t ret; + ia_css_circbuf_elem_t elem; + +#ifdef __SP + SP_ASSERT_FATAL(!ia_css_circbuf_is_empty(cb)); +#else + assert(!ia_css_circbuf_is_empty(cb)); +#endif + + /* read an element from the buffer */ + elem = ia_css_circbuf_read(cb); + ret = ia_css_circbuf_elem_get_val(&elem); + return ret; +} + +/** + * @brief Extract a value out of the circular buffer. + * Refer to "ia_css_circbuf.h" for details. + */ +uint32_t ia_css_circbuf_extract(ia_css_circbuf_t *cb, int offset) +{ + int max_offset; + uint32_t val; + uint32_t pos; + uint32_t src_pos; + uint32_t dest_pos; + + /* get the maximum offest */ + max_offset = ia_css_circbuf_get_offset(cb, cb->desc->start, cb->desc->end); + max_offset--; + + /* + * Step 1: When the target element is at the "start" position. + */ + if (offset == 0) { + val = ia_css_circbuf_pop(cb); + return val; + } + + /* + * Step 2: When the target element is out of the range. + */ + if (offset > max_offset) { + val = 0; + return val; + } + + /* + * Step 3: When the target element is between the "start" and + * "end" position. + */ + /* get the position of the target element */ + pos = ia_css_circbuf_get_pos_at_offset(cb, cb->desc->start, offset); + + /* get the value from the target element */ + val = ia_css_circbuf_elem_get_val(&cb->elems[pos]); + + /* shift the elements */ + src_pos = ia_css_circbuf_get_pos_at_offset(cb, pos, -1); + dest_pos = pos; + ia_css_circbuf_shift_chunk(cb, src_pos, dest_pos); + + return val; +} + +/** + * @brief Peek an element from the circular buffer. + * Refer to "ia_css_circbuf.h" for details. + */ +uint32_t ia_css_circbuf_peek(ia_css_circbuf_t *cb, int offset) +{ + int pos; + + pos = ia_css_circbuf_get_pos_at_offset(cb, cb->desc->end, offset); + + /* get the value at the position */ + return cb->elems[pos].val; +} + +/** + * @brief Get the value of an element from the circular buffer. + * Refer to "ia_css_circbuf.h" for details. + */ +uint32_t ia_css_circbuf_peek_from_start(ia_css_circbuf_t *cb, int offset) +{ + int pos; + + pos = ia_css_circbuf_get_pos_at_offset(cb, cb->desc->start, offset); + + /* get the value at the position */ + return cb->elems[pos].val; +} + +/** @brief increase size of a circular buffer. + * Use 'CAUTION' before using this function. This was added to + * support / fix issue with increasing size for tagger only + * Please refer to "ia_css_circbuf.h" for details. + */ +bool ia_css_circbuf_increase_size( + ia_css_circbuf_t *cb, + unsigned int sz_delta, + ia_css_circbuf_elem_t *elems) +{ + uint8_t curr_size; + uint8_t curr_end; + unsigned int i = 0; + + if (!cb || sz_delta == 0) + return false; + + curr_size = cb->desc->size; + curr_end = cb->desc->end; + /* We assume cb was pre defined as global to allow + * increase in size */ + /* FM: are we sure this cannot cause size to become too big? */ + if (((uint8_t)(cb->desc->size + (uint8_t)sz_delta) > cb->desc->size) && ((uint8_t)sz_delta == sz_delta)) + cb->desc->size += (uint8_t)sz_delta; + else + return false; /* overflow in size */ + + /* If elems are passed update them else we assume its been taken + * care before calling this function */ + if (elems) { + /* cb element array size will not be increased dynamically, + * but pointers to new elements can be added at the end + * of existing pre defined cb element array of + * size >= new size if not already added */ + for (i = curr_size; i < cb->desc->size; i++) + cb->elems[i] = elems[i - curr_size]; + } + /* Fix Start / End */ + if (curr_end < cb->desc->start) { + if (curr_end == 0) { + /* Easily fix End */ + cb->desc->end = curr_size; + } else { + /* Move elements and fix Start*/ + ia_css_circbuf_shift_chunk(cb, + curr_size - 1, + curr_size + sz_delta - 1); + } + } + + return true; +} + +/**************************************************************** + * + * Inline functions. + * + ****************************************************************/ +/** + * @brief Get the "val" field in the element. + * Refer to "Forward declarations" for details. + */ +static inline uint32_t +ia_css_circbuf_elem_get_val(ia_css_circbuf_elem_t *elem) +{ + return elem->val; +} + +/** + * @brief Read the oldest element from the circular buffer. + * Refer to "Forward declarations" for details. + */ +static inline ia_css_circbuf_elem_t +ia_css_circbuf_read(ia_css_circbuf_t *cb) +{ + ia_css_circbuf_elem_t elem; + + /* get the element from the target position */ + elem = cb->elems[cb->desc->start]; + + /* clear the target position */ + ia_css_circbuf_elem_init(&cb->elems[cb->desc->start]); + + /* adjust the "start" position */ + cb->desc->start = ia_css_circbuf_get_pos_at_offset(cb, cb->desc->start, 1); + return elem; +} + +/** + * @brief Shift a chunk of elements in the circular buffer. + * Refer to "Forward declarations" for details. + */ +static inline void +ia_css_circbuf_shift_chunk(ia_css_circbuf_t *cb, + uint32_t chunk_src, uint32_t chunk_dest) +{ + int chunk_offset; + int chunk_sz; + int i; + + /* get the chunk offset and size */ + chunk_offset = ia_css_circbuf_get_offset(cb, + chunk_src, chunk_dest); + chunk_sz = ia_css_circbuf_get_offset(cb, cb->desc->start, chunk_src) + 1; + + /* shift each element to its terminal position */ + for (i = 0; i < chunk_sz; i++) { + + /* copy the element from the source to the destination */ + ia_css_circbuf_elem_cpy(&cb->elems[chunk_src], + &cb->elems[chunk_dest]); + + /* clear the source position */ + ia_css_circbuf_elem_init(&cb->elems[chunk_src]); + + /* adjust the source/terminal positions */ + chunk_src = ia_css_circbuf_get_pos_at_offset(cb, chunk_src, -1); + chunk_dest = ia_css_circbuf_get_pos_at_offset(cb, chunk_dest, -1); + + } + + /* adjust the index "start" */ + cb->desc->start = ia_css_circbuf_get_pos_at_offset(cb, cb->desc->start, chunk_offset); +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/refcount/interface/ia_css_refcount.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/refcount/interface/ia_css_refcount.h new file mode 100644 index 0000000000000000000000000000000000000000..20db4de6beeb66f0008ff6a52dcc628ebe618603 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/refcount/interface/ia_css_refcount.h @@ -0,0 +1,83 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_REFCOUNT_H_ +#define _IA_CSS_REFCOUNT_H_ + +#include +#include +#include + +typedef void (*clear_func)(hrt_vaddress ptr); + +/*! \brief Function for initializing refcount list + * + * \param[in] size Size of the refcount list. + * \return ia_css_err + */ +extern enum ia_css_err ia_css_refcount_init(uint32_t size); + +/*! \brief Function for de-initializing refcount list + * + * \return None + */ +extern void ia_css_refcount_uninit(void); + +/*! \brief Function for increasing reference by 1. + * + * \param[in] id ID of the object. + * \param[in] ptr Data of the object (ptr). + * \return hrt_vaddress (saved address) + */ +extern hrt_vaddress ia_css_refcount_increment(int32_t id, hrt_vaddress ptr); + +/*! \brief Function for decrease reference by 1. + * + * \param[in] id ID of the object. + * \param[in] ptr Data of the object (ptr). + * + * - true, if it is successful. + * - false, otherwise. + */ +extern bool ia_css_refcount_decrement(int32_t id, hrt_vaddress ptr); + +/*! \brief Function to check if reference count is 1. + * + * \param[in] ptr Data of the object (ptr). + * + * - true, if it is successful. + * - false, otherwise. + */ +extern bool ia_css_refcount_is_single(hrt_vaddress ptr); + +/*! \brief Function to clear reference list objects. + * + * \param[in] id ID of the object. + * \param[in] clear_func function to be run to free reference objects. + * + * return None + */ +extern void ia_css_refcount_clear(int32_t id, + clear_func clear_func_ptr); + +/*! \brief Function to verify if object is valid + * + * \param[in] ptr Data of the object (ptr) + * + * - true, if valid + * - false, if invalid + */ +extern bool ia_css_refcount_is_valid(hrt_vaddress ptr); + +#endif /* _IA_CSS_REFCOUNT_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/refcount/src/refcount.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/refcount/src/refcount.c new file mode 100644 index 0000000000000000000000000000000000000000..05e4bc39253d8cf7a9672e8692f545f5d738e895 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/base/refcount/src/refcount.c @@ -0,0 +1,281 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_refcount.h" +#include "memory_access/memory_access.h" +#include "sh_css_defs.h" + +#include "platform_support.h" + +#include "assert_support.h" + +#include "ia_css_debug.h" + +/* TODO: enable for other memory aswell + now only for hrt_vaddress */ +struct ia_css_refcount_entry { + uint32_t count; + hrt_vaddress data; + int32_t id; +}; + +struct ia_css_refcount_list { + uint32_t size; + struct ia_css_refcount_entry *items; +}; + +static struct ia_css_refcount_list myrefcount; + +static struct ia_css_refcount_entry *refcount_find_entry(hrt_vaddress ptr, + bool firstfree) +{ + uint32_t i; + + if (ptr == 0) + return NULL; + if (myrefcount.items == NULL) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "refcount_find_entry(): Ref count not initiliazed!\n"); + return NULL; + } + + for (i = 0; i < myrefcount.size; i++) { + + if ((&myrefcount.items[i])->data == 0) { + if (firstfree) { + /* for new entry */ + return &myrefcount.items[i]; + } + } + if ((&myrefcount.items[i])->data == ptr) { + /* found entry */ + return &myrefcount.items[i]; + } + } + return NULL; +} + +enum ia_css_err ia_css_refcount_init(uint32_t size) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + if (size == 0) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_refcount_init(): Size of 0 for Ref count init!\n"); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + if (myrefcount.items != NULL) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_refcount_init(): Ref count is already initialized\n"); + return IA_CSS_ERR_INTERNAL_ERROR; + } + myrefcount.items = + sh_css_malloc(sizeof(struct ia_css_refcount_entry) * size); + if (!myrefcount.items) + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + if (err == IA_CSS_SUCCESS) { + memset(myrefcount.items, 0, + sizeof(struct ia_css_refcount_entry) * size); + myrefcount.size = size; + } + return err; +} + +void ia_css_refcount_uninit(void) +{ + struct ia_css_refcount_entry *entry; + uint32_t i; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_refcount_uninit() entry\n"); + for (i = 0; i < myrefcount.size; i++) { + /* driver verifier tool has issues with &arr[i] + and prefers arr + i; as these are actually equivalent + the line below uses + i + */ + entry = myrefcount.items + i; + if (entry->data != mmgr_NULL) { + /* ia_css_debug_dtrace(IA_CSS_DBG_TRACE, + "ia_css_refcount_uninit: freeing (%x)\n", + entry->data);*/ + mmgr_free(entry->data); + entry->data = mmgr_NULL; + entry->count = 0; + entry->id = 0; + } + } + sh_css_free(myrefcount.items); + myrefcount.items = NULL; + myrefcount.size = 0; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_refcount_uninit() leave\n"); +} + +hrt_vaddress ia_css_refcount_increment(int32_t id, hrt_vaddress ptr) +{ + struct ia_css_refcount_entry *entry; + + if (ptr == mmgr_NULL) + return ptr; + + entry = refcount_find_entry(ptr, false); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_refcount_increment(%x) 0x%x\n", id, ptr); + + if (!entry) { + entry = refcount_find_entry(ptr, true); + assert(entry != NULL); + if (entry == NULL) + return mmgr_NULL; + entry->id = id; + } + + if (entry->id != id) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "ia_css_refcount_increment(): Ref count IDS do not match!\n"); + return mmgr_NULL; + } + + if (entry->data == ptr) + entry->count += 1; + else if (entry->data == mmgr_NULL) { + entry->data = ptr; + entry->count = 1; + } else + return mmgr_NULL; + + return ptr; +} + +bool ia_css_refcount_decrement(int32_t id, hrt_vaddress ptr) +{ + struct ia_css_refcount_entry *entry; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_refcount_decrement(%x) 0x%x\n", id, ptr); + + if (ptr == mmgr_NULL) + return false; + + entry = refcount_find_entry(ptr, false); + + if (entry) { + if (entry->id != id) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "ia_css_refcount_decrement(): Ref count IDS do not match!\n"); + return false; + } + if (entry->count > 0) { + entry->count -= 1; + if (entry->count == 0) { + /* ia_css_debug_dtrace(IA_CSS_DBEUG_TRACE, + "ia_css_refcount_decrement: freeing\n");*/ + mmgr_free(ptr); + entry->data = mmgr_NULL; + entry->id = 0; + } + return true; + } + } + + /* SHOULD NOT HAPPEN: ptr not managed by refcount, or not + valid anymore */ + if (entry) + IA_CSS_ERROR("id %x, ptr 0x%x entry %p entry->id %x entry->count %d\n", + id, ptr, entry, entry->id, entry->count); + else + IA_CSS_ERROR("entry NULL\n"); +#ifdef ISP2401 + assert(false); +#endif + + return false; +} + +bool ia_css_refcount_is_single(hrt_vaddress ptr) +{ + struct ia_css_refcount_entry *entry; + + if (ptr == mmgr_NULL) + return false; + + entry = refcount_find_entry(ptr, false); + + if (entry) + return (entry->count == 1); + + return true; +} + +void ia_css_refcount_clear(int32_t id, clear_func clear_func_ptr) +{ + struct ia_css_refcount_entry *entry; + uint32_t i; + uint32_t count = 0; + + assert(clear_func_ptr != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_refcount_clear(%x)\n", + id); + + for (i = 0; i < myrefcount.size; i++) { + /* driver verifier tool has issues with &arr[i] + and prefers arr + i; as these are actually equivalent + the line below uses + i + */ + entry = myrefcount.items + i; + if ((entry->data != mmgr_NULL) && (entry->id == id)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_refcount_clear:" + " %x: 0x%x\n", id, entry->data); + if (clear_func_ptr) { + /* clear using provided function */ + clear_func_ptr(entry->data); + } else { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_refcount_clear: " + "using mmgr_free: " + "no clear_func\n"); + mmgr_free(entry->data); + } +#ifndef ISP2401 + +#else + assert(entry->count == 0); +#endif + if (entry->count != 0) { + IA_CSS_WARNING("Ref count for entry %x is not zero!", entry->id); + } + entry->data = mmgr_NULL; + entry->count = 0; + entry->id = 0; + count++; + } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_refcount_clear(%x): cleared %d\n", id, + count); +} + +bool ia_css_refcount_is_valid(hrt_vaddress ptr) +{ + struct ia_css_refcount_entry *entry; + + if (ptr == mmgr_NULL) + return false; + + entry = refcount_find_entry(ptr, false); + + return entry != NULL; +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_binarydesc.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_binarydesc.h new file mode 100644 index 0000000000000000000000000000000000000000..616789d9b3f644086b1bf142f4ae2bc68d4416dc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_binarydesc.h @@ -0,0 +1,297 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PIPE_BINARYDESC_H__ +#define __IA_CSS_PIPE_BINARYDESC_H__ + +#include /* ia_css_pipe */ +#include /* ia_css_frame_info */ +#include /* ia_css_binary_descr */ + +/** @brief Get a binary descriptor for copy. + * + * @param[in] pipe + * @param[out] copy_desc + * @param[in/out] in_info + * @param[in/out] out_info + * @param[in/out] vf_info + * @return None + * + */ +extern void ia_css_pipe_get_copy_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *copy_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info); + +/** @brief Get a binary descriptor for vfpp. + * + * @param[in] pipe + * @param[out] vfpp_descr + * @param[in/out] in_info + * @param[in/out] out_info + * @return None + * + */ +extern void ia_css_pipe_get_vfpp_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *vf_pp_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info); + +/** @brief Get numerator and denominator of bayer downscaling factor. + * + * @param[in] bds_factor: The bayer downscaling factor. + * (= The bds_factor member in the sh_css_bds_factor structure.) + * @param[out] bds_factor_numerator: The numerator of the bayer downscaling factor. + * (= The numerator member in the sh_css_bds_factor structure.) + * @param[out] bds_factor_denominator: The denominator of the bayer downscaling factor. + * (= The denominator member in the sh_css_bds_factor structure.) + * @return IA_CSS_SUCCESS or error code upon error. + * + */ +extern enum ia_css_err sh_css_bds_factor_get_numerator_denominator( + unsigned int bds_factor, + unsigned int *bds_factor_numerator, + unsigned int *bds_factor_denominator); + +/** @brief Get a binary descriptor for preview stage. + * + * @param[in] pipe + * @param[out] preview_descr + * @param[in/out] in_info + * @param[in/out] bds_out_info + * @param[in/out] out_info + * @param[in/out] vf_info + * @return IA_CSS_SUCCESS or error code upon error. + * + */ +extern enum ia_css_err ia_css_pipe_get_preview_binarydesc( + struct ia_css_pipe * const pipe, + struct ia_css_binary_descr *preview_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *bds_out_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info); + +/** @brief Get a binary descriptor for video stage. + * + * @param[in/out] pipe + * @param[out] video_descr + * @param[in/out] in_info + * @param[in/out] bds_out_info + * @param[in/out] vf_info + * @return IA_CSS_SUCCESS or error code upon error. + * + */ +extern enum ia_css_err ia_css_pipe_get_video_binarydesc( + struct ia_css_pipe * const pipe, + struct ia_css_binary_descr *video_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *bds_out_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info, + int stream_config_left_padding); + +/** @brief Get a binary descriptor for yuv scaler stage. + * + * @param[in/out] pipe + * @param[out] yuv_scaler_descr + * @param[in/out] in_info + * @param[in/out] out_info + * @param[in/out] internal_out_info + * @param[in/out] vf_info + * @return None + * + */ +void ia_css_pipe_get_yuvscaler_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *yuv_scaler_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *internal_out_info, + struct ia_css_frame_info *vf_info); + +/** @brief Get a binary descriptor for capture pp stage. + * + * @param[in/out] pipe + * @param[out] capture_pp_descr + * @param[in/out] in_info + * @param[in/out] vf_info + * @return None + * + */ +extern void ia_css_pipe_get_capturepp_binarydesc( + struct ia_css_pipe * const pipe, + struct ia_css_binary_descr *capture_pp_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info); + +/** @brief Get a binary descriptor for primary capture. + * + * @param[in] pipe + * @param[out] prim_descr + * @param[in/out] in_info + * @param[in/out] out_info + * @param[in/out] vf_info + * @return None + * + */ +extern void ia_css_pipe_get_primary_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *prim_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info, + unsigned int stage_idx); + +/** @brief Get a binary descriptor for pre gdc stage. + * + * @param[in] pipe + * @param[out] pre_gdc_descr + * @param[in/out] in_info + * @param[in/out] out_info + * @return None + * + */ +extern void ia_css_pipe_get_pre_gdc_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *gdc_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info); + +/** @brief Get a binary descriptor for gdc stage. + * + * @param[in] pipe + * @param[out] gdc_descr + * @param[in/out] in_info + * @param[in/out] out_info + * @return None + * + */ +extern void ia_css_pipe_get_gdc_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *gdc_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info); + +/** @brief Get a binary descriptor for post gdc. + * + * @param[in] pipe + * @param[out] post_gdc_descr + * @param[in/out] in_info + * @param[in/out] out_info + * @param[in/out] vf_info + * @return None + * + */ +extern void ia_css_pipe_get_post_gdc_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *post_gdc_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info); + +/** @brief Get a binary descriptor for de. + * + * @param[in] pipe + * @param[out] pre_de_descr + * @param[in/out] in_info + * @param[in/out] out_info + * @return None + * + */ +extern void ia_css_pipe_get_pre_de_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *pre_de_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info); + +/** @brief Get a binary descriptor for pre anr stage. + * + * @param[in] pipe + * @param[out] pre_anr_descr + * @param[in/out] in_info + * @param[in/out] out_info + * @return None + * + */ +extern void ia_css_pipe_get_pre_anr_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *pre_anr_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info); + +/** @brief Get a binary descriptor for ANR stage. + * + * @param[in] pipe + * @param[out] anr_descr + * @param[in/out] in_info + * @param[in/out] out_info + * @return None + * + */ +extern void ia_css_pipe_get_anr_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *anr_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info); + +/** @brief Get a binary descriptor for post anr stage. + * + * @param[in] pipe + * @param[out] post_anr_descr + * @param[in/out] in_info + * @param[in/out] out_info + * @param[in/out] vf_info + * @return None + * + */ +extern void ia_css_pipe_get_post_anr_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *post_anr_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info); + +/** @brief Get a binary descriptor for ldc stage. + * + * @param[in/out] pipe + * @param[out] capture_pp_descr + * @param[in/out] in_info + * @param[in/out] vf_info + * @return None + * + */ +extern void ia_css_pipe_get_ldc_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *ldc_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info); + +/** @brief Calculates the required BDS factor + * + * @param[in] input_res + * @param[in] output_res + * @param[in/out] bds_factor + * @return IA_CSS_SUCCESS or error code upon error. + */ +enum ia_css_err binarydesc_calculate_bds_factor( + struct ia_css_resolution input_res, + struct ia_css_resolution output_res, + unsigned int *bds_factor); + +#endif /* __IA_CSS_PIPE_BINARYDESC_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_stagedesc.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_stagedesc.h new file mode 100644 index 0000000000000000000000000000000000000000..38690ea093c2879bbfaa97a6df67b839ad6d4f51 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_stagedesc.h @@ -0,0 +1,52 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PIPE_STAGEDESC_H__ +#define __IA_CSS_PIPE_STAGEDESC_H__ + +#include /* ia_css_fw_info */ +#include +#include +#include "ia_css_pipeline.h" +#include "ia_css_pipeline_common.h" + +extern void ia_css_pipe_get_generic_stage_desc( + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_binary *binary, + struct ia_css_frame *out_frame[], + struct ia_css_frame *in_frame, + struct ia_css_frame *vf_frame); + +extern void ia_css_pipe_get_firmwares_stage_desc( + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_binary *binary, + struct ia_css_frame *out_frame[], + struct ia_css_frame *in_frame, + struct ia_css_frame *vf_frame, + const struct ia_css_fw_info *fw, + unsigned int mode); + +extern void ia_css_pipe_get_acc_stage_desc( + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_binary *binary, + struct ia_css_fw_info *fw); + +extern void ia_css_pipe_get_sp_func_stage_desc( + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_frame *out_frame, + enum ia_css_pipeline_stage_sp_func sp_func, + unsigned max_input_width); + +#endif /*__IA_CSS_PIPE_STAGEDESC__H__ */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_util.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_util.h new file mode 100644 index 0000000000000000000000000000000000000000..ba8858759b300d03e281da379253ff2edb2815a6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/interface/ia_css_pipe_util.h @@ -0,0 +1,39 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PIPE_UTIL_H__ +#define __IA_CSS_PIPE_UTIL_H__ + +#include +#include + +/** @brief Get Input format bits per pixel based on stream configuration of this + * pipe. + * + * @param[in] pipe + * @return bits per pixel for the underlying stream + * + */ +extern unsigned int ia_css_pipe_util_pipe_input_format_bpp( + const struct ia_css_pipe * const pipe); + +extern void ia_css_pipe_util_create_output_frames( + struct ia_css_frame *frames[]); + +extern void ia_css_pipe_util_set_output_frames( + struct ia_css_frame *frames[], + unsigned int idx, + struct ia_css_frame *frame); + +#endif /* __IA_CSS_PIPE_UTIL_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/src/pipe_binarydesc.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/src/pipe_binarydesc.c new file mode 100644 index 0000000000000000000000000000000000000000..17d3b7de93ba289a185564cc08fa0d1ff139dc5c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/src/pipe_binarydesc.c @@ -0,0 +1,883 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_pipe_binarydesc.h" +#include "ia_css_frame_format.h" +#include "ia_css_pipe.h" +#include "ia_css_pipe_util.h" +#include "ia_css_util.h" +#include "ia_css_debug.h" +#include "sh_css_params.h" +#include +/* HRT_GDC_N */ +#include "gdc_device.h" + +/* This module provides a binary descriptions to used to find a binary. Since, + * every stage is associated with a binary, it implicity helps stage + * description. Apart from providing a binary description, this module also + * populates the frame info's when required.*/ + +/* Generic descriptor for offline binaries. Internal function. */ +static void pipe_binarydesc_get_offline( + struct ia_css_pipe const * const pipe, + const int mode, + struct ia_css_binary_descr *descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info[], + struct ia_css_frame_info *vf_info) +{ + unsigned int i; + /* in_info, out_info, vf_info can be NULL */ + assert(pipe != NULL); + assert(descr != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "pipe_binarydesc_get_offline() enter:\n"); + + descr->mode = mode; + descr->online = false; + descr->continuous = pipe->stream->config.continuous; + descr->striped = false; + descr->two_ppc = false; + descr->enable_yuv_ds = false; + descr->enable_high_speed = false; + descr->enable_dvs_6axis = false; + descr->enable_reduced_pipe = false; + descr->enable_dz = true; + descr->enable_xnr = false; + descr->enable_dpc = false; +#ifdef ISP2401 + descr->enable_luma_only = false; + descr->enable_tnr = false; +#endif + descr->enable_capture_pp_bli = false; + descr->enable_fractional_ds = false; + descr->dvs_env.width = 0; + descr->dvs_env.height = 0; + descr->stream_format = pipe->stream->config.input_config.format; + descr->in_info = in_info; + descr->bds_out_info = NULL; + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + descr->out_info[i] = out_info[i]; + descr->vf_info = vf_info; + descr->isp_pipe_version = pipe->config.isp_pipe_version; + descr->required_bds_factor = SH_CSS_BDS_FACTOR_1_00; + descr->stream_config_left_padding = -1; +} + +void ia_css_pipe_get_copy_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *copy_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info) +{ + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + unsigned int i; + /* out_info can be NULL */ + assert(pipe != NULL); + assert(in_info != NULL); + IA_CSS_ENTER_PRIVATE(""); + + *in_info = *out_info; + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_COPY, + copy_descr, in_info, out_infos, vf_info); + copy_descr->online = true; + copy_descr->continuous = false; + copy_descr->two_ppc = (pipe->stream->config.pixels_per_clock == 2); + copy_descr->enable_dz = false; + copy_descr->isp_pipe_version = IA_CSS_PIPE_VERSION_1; + IA_CSS_LEAVE_PRIVATE(""); +} +void ia_css_pipe_get_vfpp_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *vf_pp_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info) +{ + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + unsigned int i; + /* out_info can be NULL ??? */ + assert(pipe != NULL); + assert(in_info != NULL); + IA_CSS_ENTER_PRIVATE(""); + + in_info->raw_bit_depth = 0; + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_VF_PP, + vf_pp_descr, in_info, out_infos, NULL); + vf_pp_descr->enable_fractional_ds = true; + IA_CSS_LEAVE_PRIVATE(""); +} + +static struct sh_css_bds_factor bds_factors_list[] = { + {1, 1, SH_CSS_BDS_FACTOR_1_00}, + {5, 4, SH_CSS_BDS_FACTOR_1_25}, + {3, 2, SH_CSS_BDS_FACTOR_1_50}, + {2, 1, SH_CSS_BDS_FACTOR_2_00}, + {9, 4, SH_CSS_BDS_FACTOR_2_25}, + {5, 2, SH_CSS_BDS_FACTOR_2_50}, + {3, 1, SH_CSS_BDS_FACTOR_3_00}, + {4, 1, SH_CSS_BDS_FACTOR_4_00}, + {9, 2, SH_CSS_BDS_FACTOR_4_50}, + {5, 1, SH_CSS_BDS_FACTOR_5_00}, + {6, 1, SH_CSS_BDS_FACTOR_6_00}, + {8, 1, SH_CSS_BDS_FACTOR_8_00} +}; + +enum ia_css_err sh_css_bds_factor_get_numerator_denominator( + unsigned int bds_factor, + unsigned int *bds_factor_numerator, + unsigned int *bds_factor_denominator) +{ + unsigned int i; + unsigned int bds_list_size = sizeof(bds_factors_list) / + sizeof(struct sh_css_bds_factor); + + /* Loop over all bds factors until a match is found */ + for (i = 0; i < bds_list_size; i++) { + if (bds_factors_list[i].bds_factor == bds_factor) { + *bds_factor_numerator = bds_factors_list[i].numerator; + *bds_factor_denominator = bds_factors_list[i].denominator; + return IA_CSS_SUCCESS; + } + } + + /* Throw an error since bds_factor cannot be found + in bds_factors_list */ + return IA_CSS_ERR_INVALID_ARGUMENTS; +} + +enum ia_css_err binarydesc_calculate_bds_factor( + struct ia_css_resolution input_res, + struct ia_css_resolution output_res, + unsigned int *bds_factor) +{ + unsigned int i; + unsigned int bds_list_size = sizeof(bds_factors_list) / + sizeof(struct sh_css_bds_factor); + unsigned int in_w = input_res.width, + in_h = input_res.height, + out_w = output_res.width, out_h = output_res.height; + + unsigned int max_bds_factor = 8; + unsigned int max_rounding_margin = 2; + /* delta in pixels to account for rounding margin in the calculation */ + unsigned int delta = max_bds_factor * max_rounding_margin; + + /* Assert if the resolutions are not set */ + assert(in_w != 0 && in_h != 0); + assert(out_w != 0 && out_h != 0); + + /* Loop over all bds factors until a match is found */ + for (i = 0; i < bds_list_size; i++) { + unsigned num = bds_factors_list[i].numerator; + unsigned den = bds_factors_list[i].denominator; + + /* See width-wise and height-wise if this bds_factor + * satisfies the condition */ + bool cond = (out_w * num / den + delta > in_w) && + (out_w * num / den <= in_w) && + (out_h * num / den + delta > in_h) && + (out_h * num / den <= in_h); + + if (cond) { + *bds_factor = bds_factors_list[i].bds_factor; + return IA_CSS_SUCCESS; + } + } + + /* Throw an error since a suitable bds_factor cannot be found */ + return IA_CSS_ERR_INVALID_ARGUMENTS; +} + +enum ia_css_err ia_css_pipe_get_preview_binarydesc( + struct ia_css_pipe * const pipe, + struct ia_css_binary_descr *preview_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *bds_out_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info) +{ + enum ia_css_err err; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + int mode = IA_CSS_BINARY_MODE_PREVIEW; + unsigned int i; + + assert(pipe != NULL); + assert(in_info != NULL); + assert(out_info != NULL); + assert(vf_info != NULL); + IA_CSS_ENTER_PRIVATE(""); + + /* + * Set up the info of the input frame with + * the ISP required resolution + */ + in_info->res = pipe->config.input_effective_res; + in_info->padded_width = in_info->res.width; + in_info->raw_bit_depth = ia_css_pipe_util_pipe_input_format_bpp(pipe); + + if (ia_css_util_is_input_format_yuv(pipe->stream->config.input_config.format)) + mode = IA_CSS_BINARY_MODE_COPY; + else + in_info->format = IA_CSS_FRAME_FORMAT_RAW; + + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, mode, + preview_descr, in_info, out_infos, vf_info); + if (pipe->stream->config.online) { + preview_descr->online = pipe->stream->config.online; + preview_descr->two_ppc = + (pipe->stream->config.pixels_per_clock == 2); + } + preview_descr->stream_format = pipe->stream->config.input_config.format; + + /* TODO: Remove this when bds_out_info is available! */ + *bds_out_info = *in_info; + + if (pipe->extra_config.enable_raw_binning) { + if (pipe->config.bayer_ds_out_res.width != 0 && + pipe->config.bayer_ds_out_res.height != 0) { + bds_out_info->res.width = + pipe->config.bayer_ds_out_res.width; + bds_out_info->res.height = + pipe->config.bayer_ds_out_res.height; + bds_out_info->padded_width = + pipe->config.bayer_ds_out_res.width; + err = + binarydesc_calculate_bds_factor(in_info->res, + bds_out_info->res, + &preview_descr->required_bds_factor); + if (err != IA_CSS_SUCCESS) + return err; + } else { + bds_out_info->res.width = in_info->res.width / 2; + bds_out_info->res.height = in_info->res.height / 2; + bds_out_info->padded_width = in_info->padded_width / 2; + preview_descr->required_bds_factor = + SH_CSS_BDS_FACTOR_2_00; + } + } else { + /* TODO: Remove this when bds_out_info->is available! */ + bds_out_info->res.width = in_info->res.width; + bds_out_info->res.height = in_info->res.height; + bds_out_info->padded_width = in_info->padded_width; + preview_descr->required_bds_factor = SH_CSS_BDS_FACTOR_1_00; + } + pipe->required_bds_factor = preview_descr->required_bds_factor; + + /* bayer ds and fractional ds cannot be enabled at the same time, + so we disable bds_out_info when fractional ds is used */ + if (!pipe->extra_config.enable_fractional_ds) + preview_descr->bds_out_info = bds_out_info; + else + preview_descr->bds_out_info = NULL; + /* + ----Preview binary----- + --in-->|--out->|vf_veceven|--|--->vf + ----------------------- + * Preview binary normally doesn't have a vf_port but + * instead it has an output port. However, the output is + * generated by vf_veceven module in which we might have + * a downscaling (by 1x, 2x, or 4x). Because the resolution + * might change, we need two different info, namely out_info + * & vf_info. In fill_binary_info we use out&vf info to + * calculate vf decimation factor. + */ + *out_info = *vf_info; + + /* In case of preview_ds binary, we can do any fractional amount + * of downscale, so there is no DS needed in vf_veceven. Therefore, + * out and vf infos will be the same. Otherwise, we set out resolution + * equal to in resolution. */ + if (!pipe->extra_config.enable_fractional_ds) { + /* TODO: Change this when bds_out_info is available! */ + out_info->res.width = bds_out_info->res.width; + out_info->res.height = bds_out_info->res.height; + out_info->padded_width = bds_out_info->padded_width; + } + preview_descr->enable_fractional_ds = + pipe->extra_config.enable_fractional_ds; + + preview_descr->enable_dpc = pipe->config.enable_dpc; + + preview_descr->isp_pipe_version = pipe->config.isp_pipe_version; + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + return IA_CSS_SUCCESS; +} + +enum ia_css_err ia_css_pipe_get_video_binarydesc( + struct ia_css_pipe * const pipe, + struct ia_css_binary_descr *video_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *bds_out_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info, + int stream_config_left_padding) +{ + int mode = IA_CSS_BINARY_MODE_VIDEO; + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + enum ia_css_err err = IA_CSS_SUCCESS; + bool stream_dz_config = false; + + /* vf_info can be NULL */ + assert(pipe != NULL); + assert(in_info != NULL); + /* assert(vf_info != NULL); */ + IA_CSS_ENTER_PRIVATE(""); + + /* The solution below is not optimal; we should move to using ia_css_pipe_get_copy_binarydesc() + * But for now this fixes things; this code used to be there but was removed + * with gerrit 8908 as this was wrong for Skycam; however 240x still needs this + */ + if (ia_css_util_is_input_format_yuv(pipe->stream->config.input_config.format)) + mode = IA_CSS_BINARY_MODE_COPY; + + in_info->res = pipe->config.input_effective_res; + in_info->padded_width = in_info->res.width; + in_info->format = IA_CSS_FRAME_FORMAT_RAW; + in_info->raw_bit_depth = ia_css_pipe_util_pipe_input_format_bpp(pipe); + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, mode, + video_descr, in_info, out_infos, vf_info); + + if (pipe->stream->config.online) { + video_descr->online = pipe->stream->config.online; + video_descr->two_ppc = + (pipe->stream->config.pixels_per_clock == 2); + } + + if (mode == IA_CSS_BINARY_MODE_VIDEO) { + stream_dz_config = + ((pipe->stream->isp_params_configs->dz_config.dx != + HRT_GDC_N) + || (pipe->stream->isp_params_configs->dz_config.dy != + HRT_GDC_N)); + + video_descr->enable_dz = pipe->config.enable_dz + || stream_dz_config; + video_descr->dvs_env = pipe->config.dvs_envelope; + video_descr->enable_yuv_ds = pipe->extra_config.enable_yuv_ds; + video_descr->enable_high_speed = + pipe->extra_config.enable_high_speed; + video_descr->enable_dvs_6axis = + pipe->extra_config.enable_dvs_6axis; + video_descr->enable_reduced_pipe = + pipe->extra_config.enable_reduced_pipe; + video_descr->isp_pipe_version = pipe->config.isp_pipe_version; + video_descr->enable_fractional_ds = + pipe->extra_config.enable_fractional_ds; + video_descr->enable_dpc = + pipe->config.enable_dpc; +#ifdef ISP2401 + video_descr->enable_luma_only = + pipe->config.enable_luma_only; + video_descr->enable_tnr = + pipe->config.enable_tnr; +#endif + + if (pipe->extra_config.enable_raw_binning) { + if (pipe->config.bayer_ds_out_res.width != 0 && + pipe->config.bayer_ds_out_res.height != 0) { + bds_out_info->res.width = + pipe->config.bayer_ds_out_res.width; + bds_out_info->res.height = + pipe->config.bayer_ds_out_res.height; + bds_out_info->padded_width = + pipe->config.bayer_ds_out_res.width; + err = + binarydesc_calculate_bds_factor( + in_info->res, bds_out_info->res, + &video_descr->required_bds_factor); + if (err != IA_CSS_SUCCESS) + return err; + } else { + bds_out_info->res.width = + in_info->res.width / 2; + bds_out_info->res.height = + in_info->res.height / 2; + bds_out_info->padded_width = + in_info->padded_width / 2; + video_descr->required_bds_factor = + SH_CSS_BDS_FACTOR_2_00; + } + } else { + bds_out_info->res.width = in_info->res.width; + bds_out_info->res.height = in_info->res.height; + bds_out_info->padded_width = in_info->padded_width; + video_descr->required_bds_factor = + SH_CSS_BDS_FACTOR_1_00; + } + + pipe->required_bds_factor = video_descr->required_bds_factor; + + /* bayer ds and fractional ds cannot be enabled + at the same time, so we disable bds_out_info when + fractional ds is used */ + if (!pipe->extra_config.enable_fractional_ds) + video_descr->bds_out_info = bds_out_info; + else + video_descr->bds_out_info = NULL; + + video_descr->enable_fractional_ds = + pipe->extra_config.enable_fractional_ds; + video_descr->stream_config_left_padding = stream_config_left_padding; + } + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +void ia_css_pipe_get_yuvscaler_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *yuv_scaler_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *internal_out_info, + struct ia_css_frame_info *vf_info) +{ + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_frame_info *this_vf_info = NULL; + + assert(pipe != NULL); + assert(in_info != NULL); + /* Note: if the following assert fails, the number of ports has been + * changed; in that case an additional initializer must be added + * a few lines below after which this assert can be updated. + */ + assert(IA_CSS_BINARY_MAX_OUTPUT_PORTS == 2); + IA_CSS_ENTER_PRIVATE(""); + + in_info->padded_width = in_info->res.width; + in_info->raw_bit_depth = 0; + ia_css_frame_info_set_width(in_info, in_info->res.width, 0); + out_infos[0] = out_info; + out_infos[1] = internal_out_info; + /* add initializers here if + * assert(IA_CSS_BINARY_MAX_OUTPUT_PORTS == ...); + * fails + */ + + if (vf_info) { + this_vf_info = (vf_info->res.width == 0 && + vf_info->res.height == 0) ? NULL : vf_info; + } + + pipe_binarydesc_get_offline(pipe, + IA_CSS_BINARY_MODE_CAPTURE_PP, + yuv_scaler_descr, + in_info, out_infos, this_vf_info); + + yuv_scaler_descr->enable_fractional_ds = true; + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_pipe_get_capturepp_binarydesc( + struct ia_css_pipe * const pipe, + struct ia_css_binary_descr *capture_pp_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info) +{ + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + + assert(pipe != NULL); + assert(in_info != NULL); + assert(vf_info != NULL); + IA_CSS_ENTER_PRIVATE(""); + + + /* the in_info is only used for resolution to enable + bayer down scaling. */ + if (pipe->out_yuv_ds_input_info.res.width) + *in_info = pipe->out_yuv_ds_input_info; + else + *in_info = *out_info; + in_info->format = IA_CSS_FRAME_FORMAT_YUV420; + in_info->raw_bit_depth = 0; + ia_css_frame_info_set_width(in_info, in_info->res.width, 0); + + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, + IA_CSS_BINARY_MODE_CAPTURE_PP, + capture_pp_descr, + in_info, out_infos, vf_info); + + capture_pp_descr->enable_capture_pp_bli = + pipe->config.default_capture_config.enable_capture_pp_bli; + capture_pp_descr->enable_fractional_ds = true; + capture_pp_descr->enable_xnr = + pipe->config.default_capture_config.enable_xnr != 0; + IA_CSS_LEAVE_PRIVATE(""); +} + +/* lookup table for high quality primary binaries */ +static unsigned int primary_hq_binary_modes[NUM_PRIMARY_HQ_STAGES] = +{ + IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE0, + IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE1, + IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE2, + IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE3, + IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE4, + IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE5 +}; + +void ia_css_pipe_get_primary_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *prim_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info, + unsigned int stage_idx) +{ + enum ia_css_pipe_version pipe_version = pipe->config.isp_pipe_version; + int mode; + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + + assert(pipe != NULL); + assert(in_info != NULL); + assert(out_info != NULL); + assert(stage_idx < NUM_PRIMARY_HQ_STAGES); + /* vf_info can be NULL - example video_binarydescr */ + /*assert(vf_info != NULL);*/ + IA_CSS_ENTER_PRIVATE(""); + + if (pipe_version == IA_CSS_PIPE_VERSION_2_6_1) + mode = primary_hq_binary_modes[stage_idx]; + else + mode = IA_CSS_BINARY_MODE_PRIMARY; + + if (ia_css_util_is_input_format_yuv(pipe->stream->config.input_config.format)) + mode = IA_CSS_BINARY_MODE_COPY; + + in_info->res = pipe->config.input_effective_res; + in_info->padded_width = in_info->res.width; + +#if !defined(HAS_NO_PACKED_RAW_PIXELS) + if (pipe->stream->config.pack_raw_pixels) + in_info->format = IA_CSS_FRAME_FORMAT_RAW_PACKED; + else +#endif + in_info->format = IA_CSS_FRAME_FORMAT_RAW; + + in_info->raw_bit_depth = ia_css_pipe_util_pipe_input_format_bpp(pipe); + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, mode, + prim_descr, in_info, out_infos, vf_info); + + if (pipe->stream->config.online && + pipe->stream->config.mode != IA_CSS_INPUT_MODE_MEMORY) { + prim_descr->online = true; + prim_descr->two_ppc = + (pipe->stream->config.pixels_per_clock == 2); + prim_descr->stream_format = pipe->stream->config.input_config.format; + } + if (mode == IA_CSS_BINARY_MODE_PRIMARY) { + prim_descr->isp_pipe_version = pipe->config.isp_pipe_version; + prim_descr->enable_fractional_ds = + pipe->extra_config.enable_fractional_ds; +#ifdef ISP2401 + prim_descr->enable_luma_only = + pipe->config.enable_luma_only; +#endif + /* We have both striped and non-striped primary binaries, + * if continuous viewfinder is required, then we must select + * a striped one. Otherwise we prefer to use a non-striped + * since it has better performance. */ + if (pipe_version == IA_CSS_PIPE_VERSION_2_6_1) + prim_descr->striped = false; + else +#ifndef ISP2401 + prim_descr->striped = prim_descr->continuous && (!pipe->stream->stop_copy_preview || !pipe->stream->disable_cont_vf); +#else + prim_descr->striped = prim_descr->continuous && !pipe->stream->disable_cont_vf; + + if ((pipe->config.default_capture_config.enable_xnr != 0) && + (pipe->extra_config.enable_dvs_6axis == true)) + prim_descr->enable_xnr = true; +#endif + } + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_pipe_get_pre_gdc_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *pre_gdc_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info) +{ + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + + assert(pipe != NULL); + assert(in_info != NULL); + assert(out_info != NULL); + IA_CSS_ENTER_PRIVATE(""); + + *in_info = *out_info; + in_info->format = IA_CSS_FRAME_FORMAT_RAW; + in_info->raw_bit_depth = ia_css_pipe_util_pipe_input_format_bpp(pipe); + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_PRE_ISP, + pre_gdc_descr, in_info, out_infos, NULL); + pre_gdc_descr->isp_pipe_version = pipe->config.isp_pipe_version; + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_pipe_get_gdc_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *gdc_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info) +{ + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + + assert(pipe != NULL); + assert(in_info != NULL); + assert(out_info != NULL); + IA_CSS_ENTER_PRIVATE(""); + + *in_info = *out_info; + in_info->format = IA_CSS_FRAME_FORMAT_QPLANE6; + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_GDC, + gdc_descr, in_info, out_infos, NULL); + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_pipe_get_post_gdc_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *post_gdc_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info) +{ + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + + assert(pipe != NULL); + assert(in_info != NULL); + assert(out_info != NULL); + assert(vf_info != NULL); + IA_CSS_ENTER_PRIVATE(""); + + *in_info = *out_info; + in_info->format = IA_CSS_FRAME_FORMAT_YUV420_16; + in_info->raw_bit_depth = 16; + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_POST_ISP, + post_gdc_descr, in_info, out_infos, vf_info); + + post_gdc_descr->isp_pipe_version = pipe->config.isp_pipe_version; + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_pipe_get_pre_de_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *pre_de_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info) +{ + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + + assert(pipe != NULL); + assert(in_info != NULL); + assert(out_info != NULL); + IA_CSS_ENTER_PRIVATE(""); + + *in_info = *out_info; + in_info->format = IA_CSS_FRAME_FORMAT_RAW; + in_info->raw_bit_depth = ia_css_pipe_util_pipe_input_format_bpp(pipe); + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + if (pipe->config.isp_pipe_version == IA_CSS_PIPE_VERSION_1) + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_PRE_ISP, + pre_de_descr, in_info, out_infos, NULL); + else if (pipe->config.isp_pipe_version == IA_CSS_PIPE_VERSION_2_2) { + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_PRE_DE, + pre_de_descr, in_info, out_infos, NULL); + } + + if (pipe->stream->config.online) { + pre_de_descr->online = true; + pre_de_descr->two_ppc = + (pipe->stream->config.pixels_per_clock == 2); + pre_de_descr->stream_format = pipe->stream->config.input_config.format; + } + pre_de_descr->isp_pipe_version = pipe->config.isp_pipe_version; + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_pipe_get_pre_anr_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *pre_anr_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info) +{ + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + + assert(pipe != NULL); + assert(in_info != NULL); + assert(out_info != NULL); + IA_CSS_ENTER_PRIVATE(""); + + *in_info = *out_info; + in_info->format = IA_CSS_FRAME_FORMAT_RAW; + in_info->raw_bit_depth = ia_css_pipe_util_pipe_input_format_bpp(pipe); + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_PRE_ISP, + pre_anr_descr, in_info, out_infos, NULL); + + if (pipe->stream->config.online) { + pre_anr_descr->online = true; + pre_anr_descr->two_ppc = + (pipe->stream->config.pixels_per_clock == 2); + pre_anr_descr->stream_format = pipe->stream->config.input_config.format; + } + pre_anr_descr->isp_pipe_version = pipe->config.isp_pipe_version; + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_pipe_get_anr_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *anr_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info) +{ + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + + assert(pipe != NULL); + assert(in_info != NULL); + assert(out_info != NULL); + IA_CSS_ENTER_PRIVATE(""); + + *in_info = *out_info; + in_info->format = IA_CSS_FRAME_FORMAT_RAW; + in_info->raw_bit_depth = ANR_ELEMENT_BITS; + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_ANR, + anr_descr, in_info, out_infos, NULL); + + anr_descr->isp_pipe_version = pipe->config.isp_pipe_version; + IA_CSS_LEAVE_PRIVATE(""); +} + + +void ia_css_pipe_get_post_anr_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *post_anr_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info) +{ + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + + assert(pipe != NULL); + assert(in_info != NULL); + assert(out_info != NULL); + assert(vf_info != NULL); + IA_CSS_ENTER_PRIVATE(""); + + *in_info = *out_info; + in_info->format = IA_CSS_FRAME_FORMAT_RAW; + in_info->raw_bit_depth = ANR_ELEMENT_BITS; + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_POST_ISP, + post_anr_descr, in_info, out_infos, vf_info); + + post_anr_descr->isp_pipe_version = pipe->config.isp_pipe_version; + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_pipe_get_ldc_binarydesc( + struct ia_css_pipe const * const pipe, + struct ia_css_binary_descr *ldc_descr, + struct ia_css_frame_info *in_info, + struct ia_css_frame_info *out_info) +{ + unsigned int i; + struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + + assert(pipe != NULL); + assert(in_info != NULL); + assert(out_info != NULL); + IA_CSS_ENTER_PRIVATE(""); + +#ifndef ISP2401 + *in_info = *out_info; +#else + if (pipe->out_yuv_ds_input_info.res.width) + *in_info = pipe->out_yuv_ds_input_info; + else + *in_info = *out_info; +#endif + in_info->format = IA_CSS_FRAME_FORMAT_YUV420; + in_info->raw_bit_depth = 0; + ia_css_frame_info_set_width(in_info, in_info->res.width, 0); + + out_infos[0] = out_info; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + out_infos[i] = NULL; + + pipe_binarydesc_get_offline(pipe, IA_CSS_BINARY_MODE_CAPTURE_PP, + ldc_descr, in_info, out_infos, NULL); + ldc_descr->enable_dvs_6axis = + pipe->extra_config.enable_dvs_6axis; + IA_CSS_LEAVE_PRIVATE(""); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/src/pipe_stagedesc.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/src/pipe_stagedesc.c new file mode 100644 index 0000000000000000000000000000000000000000..40af8daf5ad96bae7d873bf84b4c2edcc087b259 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/src/pipe_stagedesc.c @@ -0,0 +1,115 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_pipe_stagedesc.h" +#include "assert_support.h" +#include "ia_css_debug.h" + +void ia_css_pipe_get_generic_stage_desc( + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_binary *binary, + struct ia_css_frame *out_frame[], + struct ia_css_frame *in_frame, + struct ia_css_frame *vf_frame) +{ + unsigned int i; + IA_CSS_ENTER_PRIVATE("stage_desc = %p, binary = %p, out_frame = %p, in_frame = %p, vf_frame = %p", + stage_desc, binary, out_frame, in_frame, vf_frame); + + assert(stage_desc != NULL && binary != NULL && binary->info != NULL); + if (stage_desc == NULL || binary == NULL || binary->info == NULL) { + IA_CSS_ERROR("invalid arguments"); + goto ERR; + } + + stage_desc->binary = binary; + stage_desc->firmware = NULL; + stage_desc->sp_func = IA_CSS_PIPELINE_NO_FUNC; + stage_desc->max_input_width = 0; + stage_desc->mode = binary->info->sp.pipeline.mode; + stage_desc->in_frame = in_frame; + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + stage_desc->out_frame[i] = out_frame[i]; + } + stage_desc->vf_frame = vf_frame; +ERR: + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_pipe_get_firmwares_stage_desc( + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_binary *binary, + struct ia_css_frame *out_frame[], + struct ia_css_frame *in_frame, + struct ia_css_frame *vf_frame, + const struct ia_css_fw_info *fw, + unsigned int mode) +{ + unsigned int i; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_pipe_get_firmwares_stage_desc() enter:\n"); + stage_desc->binary = binary; + stage_desc->firmware = fw; + stage_desc->sp_func = IA_CSS_PIPELINE_NO_FUNC; + stage_desc->max_input_width = 0; + stage_desc->mode = mode; + stage_desc->in_frame = in_frame; + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + stage_desc->out_frame[i] = out_frame[i]; + } + stage_desc->vf_frame = vf_frame; +} + +void ia_css_pipe_get_acc_stage_desc( + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_binary *binary, + struct ia_css_fw_info *fw) +{ + unsigned int i; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_pipe_get_acc_stage_desc() enter:\n"); + stage_desc->binary = binary; + stage_desc->firmware = fw; + stage_desc->sp_func = IA_CSS_PIPELINE_NO_FUNC; + stage_desc->max_input_width = 0; + stage_desc->mode = IA_CSS_BINARY_MODE_VF_PP; + stage_desc->in_frame = NULL; + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + stage_desc->out_frame[i] = NULL; + } + stage_desc->vf_frame = NULL; +} + +void ia_css_pipe_get_sp_func_stage_desc( + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_frame *out_frame, + enum ia_css_pipeline_stage_sp_func sp_func, + unsigned max_input_width) +{ + unsigned int i; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_pipe_get_sp_func_stage_desc() enter:\n"); + stage_desc->binary = NULL; + stage_desc->firmware = NULL; + stage_desc->sp_func = sp_func; + stage_desc->max_input_width = max_input_width; + stage_desc->mode = (unsigned int)-1; + stage_desc->in_frame = NULL; + stage_desc->out_frame[0] = out_frame; + for (i = 1; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + stage_desc->out_frame[i] = NULL; + } + stage_desc->vf_frame = NULL; +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/src/pipe_util.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/src/pipe_util.c new file mode 100644 index 0000000000000000000000000000000000000000..5fc1718cb2bd0cb03ff0803350723650fec03274 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/pipe/src/pipe_util.c @@ -0,0 +1,51 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_pipe_util.h" +#include "ia_css_frame_public.h" +#include "ia_css_pipe.h" +#include "ia_css_util.h" +#include "assert_support.h" + +unsigned int ia_css_pipe_util_pipe_input_format_bpp( + const struct ia_css_pipe * const pipe) +{ + assert(pipe != NULL); + assert(pipe->stream != NULL); + + return ia_css_util_input_format_bpp(pipe->stream->config.input_config.format, + pipe->stream->config.pixels_per_clock == 2); +} + +void ia_css_pipe_util_create_output_frames( + struct ia_css_frame *frames[]) +{ + unsigned int i; + + assert(frames != NULL); + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + frames[i] = NULL; + } +} + +void ia_css_pipe_util_set_output_frames( + struct ia_css_frame *frames[], + unsigned int idx, + struct ia_css_frame *frame) +{ + assert(idx < IA_CSS_BINARY_MAX_OUTPUT_PORTS); + + frames[idx] = frame; +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/util/interface/ia_css_util.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/util/interface/ia_css_util.h new file mode 100644 index 0000000000000000000000000000000000000000..f8b2e458f87669646cd5d75c91454fded7fbc9f7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/util/interface/ia_css_util.h @@ -0,0 +1,141 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_UTIL_H__ +#define __IA_CSS_UTIL_H__ + +#include +#include +#include +#include +#include +#include + +/** @brief convert "errno" error code to "ia_css_err" error code + * + * @param[in] "errno" error code + * @return "ia_css_err" error code + * + */ +enum ia_css_err ia_css_convert_errno( + int in_err); + +/** @brief check vf frame info. + * + * @param[in] info + * @return IA_CSS_SUCCESS or error code upon error. + * + */ +extern enum ia_css_err ia_css_util_check_vf_info( + const struct ia_css_frame_info * const info); + +/** @brief check input configuration. + * + * @param[in] stream_config + * @param[in] must_be_raw + * @return IA_CSS_SUCCESS or error code upon error. + * + */ +extern enum ia_css_err ia_css_util_check_input( + const struct ia_css_stream_config * const stream_config, + bool must_be_raw, + bool must_be_yuv); + +/** @brief check vf and out frame info. + * + * @param[in] out_info + * @param[in] vf_info + * @return IA_CSS_SUCCESS or error code upon error. + * + */ +extern enum ia_css_err ia_css_util_check_vf_out_info( + const struct ia_css_frame_info * const out_info, + const struct ia_css_frame_info * const vf_info); + +/** @brief check width and height + * + * @param[in] width + * @param[in] height + * @return IA_CSS_SUCCESS or error code upon error. + * + */ +extern enum ia_css_err ia_css_util_check_res( + unsigned int width, + unsigned int height); + +#ifdef ISP2401 +/** @brief compare resolutions (less or equal) + * + * @param[in] a resolution + * @param[in] b resolution + * @return true if both dimensions of a are less or + * equal than those of b, false otherwise + * + */ +extern bool ia_css_util_res_leq( + struct ia_css_resolution a, + struct ia_css_resolution b); + +/** + * @brief Check if resolution is zero + * + * @param[in] resolution The resolution to check + * + * @returns true if resolution is zero + */ +extern bool ia_css_util_resolution_is_zero( + const struct ia_css_resolution resolution); + +/** + * @brief Check if resolution is even + * + * @param[in] resolution The resolution to check + * + * @returns true if resolution is even + */ +extern bool ia_css_util_resolution_is_even( + const struct ia_css_resolution resolution); + +#endif +/** @brief check width and height + * + * @param[in] stream_format + * @param[in] two_ppc + * @return bits per pixel based on given parameters. + * + */ +extern unsigned int ia_css_util_input_format_bpp( + enum ia_css_stream_format stream_format, + bool two_ppc); + +/** @brief check if input format it raw + * + * @param[in] stream_format + * @return true if the input format is raw or false otherwise + * + */ +extern bool ia_css_util_is_input_format_raw( + enum ia_css_stream_format stream_format); + +/** @brief check if input format it yuv + * + * @param[in] stream_format + * @return true if the input format is yuv or false otherwise + * + */ +extern bool ia_css_util_is_input_format_yuv( + enum ia_css_stream_format stream_format); + +#endif /* __IA_CSS_UTIL_H__ */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/util/src/util.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/util/src/util.c new file mode 100644 index 0000000000000000000000000000000000000000..08f486e20a65efcb3f8abfd3bf8efbb62d8e31e7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/camera/util/src/util.c @@ -0,0 +1,227 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_util.h" +#include +#include +#include + +/* for ia_css_binary_max_vf_width() */ +#include "ia_css_binary.h" + + +enum ia_css_err ia_css_convert_errno( + int in_err) +{ + enum ia_css_err out_err; + + switch (in_err) { + case 0: + out_err = IA_CSS_SUCCESS; + break; + case EINVAL: + out_err = IA_CSS_ERR_INVALID_ARGUMENTS; + break; + case ENODATA: + out_err = IA_CSS_ERR_QUEUE_IS_EMPTY; + break; + case ENOSYS: + case ENOTSUP: + out_err = IA_CSS_ERR_INTERNAL_ERROR; + break; + case ENOBUFS: + out_err = IA_CSS_ERR_QUEUE_IS_FULL; + break; + default: + out_err = IA_CSS_ERR_INTERNAL_ERROR; + break; + } + return out_err; +} + +/* MW: Table look-up ??? */ +unsigned int ia_css_util_input_format_bpp( + enum ia_css_stream_format format, + bool two_ppc) +{ + unsigned int rval = 0; + switch (format) { + case IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY: + case IA_CSS_STREAM_FORMAT_YUV420_8: + case IA_CSS_STREAM_FORMAT_YUV422_8: + case IA_CSS_STREAM_FORMAT_RGB_888: + case IA_CSS_STREAM_FORMAT_RAW_8: + case IA_CSS_STREAM_FORMAT_BINARY_8: + case IA_CSS_STREAM_FORMAT_EMBEDDED: + rval = 8; + break; + case IA_CSS_STREAM_FORMAT_YUV420_10: + case IA_CSS_STREAM_FORMAT_YUV422_10: + case IA_CSS_STREAM_FORMAT_RAW_10: + rval = 10; + break; + case IA_CSS_STREAM_FORMAT_YUV420_16: + case IA_CSS_STREAM_FORMAT_YUV422_16: + rval = 16; + break; + case IA_CSS_STREAM_FORMAT_RGB_444: + rval = 4; + break; + case IA_CSS_STREAM_FORMAT_RGB_555: + rval = 5; + break; + case IA_CSS_STREAM_FORMAT_RGB_565: + rval = 65; + break; + case IA_CSS_STREAM_FORMAT_RGB_666: + case IA_CSS_STREAM_FORMAT_RAW_6: + rval = 6; + break; + case IA_CSS_STREAM_FORMAT_RAW_7: + rval = 7; + break; + case IA_CSS_STREAM_FORMAT_RAW_12: + rval = 12; + break; + case IA_CSS_STREAM_FORMAT_RAW_14: + if (two_ppc) + rval = 14; + else + rval = 12; + break; + case IA_CSS_STREAM_FORMAT_RAW_16: + if (two_ppc) + rval = 16; + else + rval = 12; + break; + default: + rval = 0; + break; + + } +return rval; +} + +enum ia_css_err ia_css_util_check_vf_info( + const struct ia_css_frame_info * const info) +{ + enum ia_css_err err; + unsigned int max_vf_width; + assert(info != NULL); + err = ia_css_frame_check_info(info); + if (err != IA_CSS_SUCCESS) + return err; + max_vf_width = ia_css_binary_max_vf_width(); + if (max_vf_width != 0 && info->res.width > max_vf_width*2) + return IA_CSS_ERR_INVALID_ARGUMENTS; + return IA_CSS_SUCCESS; +} + +enum ia_css_err ia_css_util_check_vf_out_info( + const struct ia_css_frame_info * const out_info, + const struct ia_css_frame_info * const vf_info) +{ + enum ia_css_err err; + + assert(out_info != NULL); + assert(vf_info != NULL); + + err = ia_css_frame_check_info(out_info); + if (err != IA_CSS_SUCCESS) + return err; + err = ia_css_util_check_vf_info(vf_info); + if (err != IA_CSS_SUCCESS) + return err; + return IA_CSS_SUCCESS; +} + +enum ia_css_err ia_css_util_check_res(unsigned int width, unsigned int height) +{ + /* height can be odd number for jpeg/embedded data from ISYS2401 */ + if (((width == 0) || + (height == 0) || + IS_ODD(width))) { + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + return IA_CSS_SUCCESS; +} + +#ifdef ISP2401 +bool ia_css_util_res_leq(struct ia_css_resolution a, struct ia_css_resolution b) +{ + return a.width <= b.width && a.height <= b.height; +} + +bool ia_css_util_resolution_is_zero(const struct ia_css_resolution resolution) +{ + return (resolution.width == 0) || (resolution.height == 0); +} + +bool ia_css_util_resolution_is_even(const struct ia_css_resolution resolution) +{ + return IS_EVEN(resolution.height) && IS_EVEN(resolution.width); +} + +#endif +bool ia_css_util_is_input_format_raw(enum ia_css_stream_format format) +{ + return ((format == IA_CSS_STREAM_FORMAT_RAW_6) || + (format == IA_CSS_STREAM_FORMAT_RAW_7) || + (format == IA_CSS_STREAM_FORMAT_RAW_8) || + (format == IA_CSS_STREAM_FORMAT_RAW_10) || + (format == IA_CSS_STREAM_FORMAT_RAW_12)); + /* raw_14 and raw_16 are not supported as input formats to the ISP. + * They can only be copied to a frame in memory using the + * copy binary. + */ +} + +bool ia_css_util_is_input_format_yuv(enum ia_css_stream_format format) +{ + return format == IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY || + format == IA_CSS_STREAM_FORMAT_YUV420_8 || + format == IA_CSS_STREAM_FORMAT_YUV420_10 || + format == IA_CSS_STREAM_FORMAT_YUV420_16 || + format == IA_CSS_STREAM_FORMAT_YUV422_8 || + format == IA_CSS_STREAM_FORMAT_YUV422_10 || + format == IA_CSS_STREAM_FORMAT_YUV422_16; +} + +enum ia_css_err ia_css_util_check_input( + const struct ia_css_stream_config * const stream_config, + bool must_be_raw, + bool must_be_yuv) +{ + assert(stream_config != NULL); + + if (stream_config == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + +#ifdef IS_ISP_2400_SYSTEM + if (stream_config->input_config.effective_res.width == 0 || + stream_config->input_config.effective_res.height == 0) + return IA_CSS_ERR_INVALID_ARGUMENTS; +#endif + if (must_be_raw && + !ia_css_util_is_input_format_raw(stream_config->input_config.format)) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + if (must_be_yuv && + !ia_css_util_is_input_format_yuv(stream_config->input_config.format)) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + return IA_CSS_SUCCESS; +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_configs.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_configs.c new file mode 100644 index 0000000000000000000000000000000000000000..325b821f276cf504f5f2cf1b87ad48a9d7c9fc77 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_configs.c @@ -0,0 +1,360 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* Generated code: do not edit or commmit. */ + +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_pipeline.h" +#include "ia_css_isp_configs.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_iterator( + const struct ia_css_binary *binary, + const struct ia_css_iterator_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_iterator() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.iterator.size; + offset = binary->info->mem_offsets.offsets.config->dmem.iterator.offset; + } + if (size) { + ia_css_iterator_config((struct sh_css_isp_iterator_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_iterator() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_copy_output( + const struct ia_css_binary *binary, + const struct ia_css_copy_output_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_copy_output() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.copy_output.size; + offset = binary->info->mem_offsets.offsets.config->dmem.copy_output.offset; + } + if (size) { + ia_css_copy_output_config((struct sh_css_isp_copy_output_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_copy_output() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_crop( + const struct ia_css_binary *binary, + const struct ia_css_crop_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_crop() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.crop.size; + offset = binary->info->mem_offsets.offsets.config->dmem.crop.offset; + } + if (size) { + ia_css_crop_config((struct sh_css_isp_crop_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_crop() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_fpn( + const struct ia_css_binary *binary, + const struct ia_css_fpn_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_fpn() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.fpn.size; + offset = binary->info->mem_offsets.offsets.config->dmem.fpn.offset; + } + if (size) { + ia_css_fpn_config((struct sh_css_isp_fpn_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_fpn() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_dvs( + const struct ia_css_binary *binary, + const struct ia_css_dvs_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_dvs() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.dvs.size; + offset = binary->info->mem_offsets.offsets.config->dmem.dvs.offset; + } + if (size) { + ia_css_dvs_config((struct sh_css_isp_dvs_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_dvs() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_qplane( + const struct ia_css_binary *binary, + const struct ia_css_qplane_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_qplane() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.qplane.size; + offset = binary->info->mem_offsets.offsets.config->dmem.qplane.offset; + } + if (size) { + ia_css_qplane_config((struct sh_css_isp_qplane_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_qplane() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output0( + const struct ia_css_binary *binary, + const struct ia_css_output0_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output0() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.output0.size; + offset = binary->info->mem_offsets.offsets.config->dmem.output0.offset; + } + if (size) { + ia_css_output0_config((struct sh_css_isp_output_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output0() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output1( + const struct ia_css_binary *binary, + const struct ia_css_output1_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output1() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.output1.size; + offset = binary->info->mem_offsets.offsets.config->dmem.output1.offset; + } + if (size) { + ia_css_output1_config((struct sh_css_isp_output_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output1() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output( + const struct ia_css_binary *binary, + const struct ia_css_output_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.output.size; + offset = binary->info->mem_offsets.offsets.config->dmem.output.offset; + } + if (size) { + ia_css_output_config((struct sh_css_isp_output_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ +#ifdef ISP2401 + +void +ia_css_configure_sc( + const struct ia_css_binary *binary, + const struct ia_css_sc_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_sc() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.sc.size; + offset = binary->info->mem_offsets.offsets.config->dmem.sc.offset; + } + if (size) { + ia_css_sc_config((struct sh_css_isp_sc_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_sc() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ +#endif + +void +ia_css_configure_raw( + const struct ia_css_binary *binary, + const struct ia_css_raw_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_raw() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.raw.size; + offset = binary->info->mem_offsets.offsets.config->dmem.raw.offset; + } + if (size) { + ia_css_raw_config((struct sh_css_isp_raw_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_raw() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_tnr( + const struct ia_css_binary *binary, + const struct ia_css_tnr_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_tnr() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.tnr.size; + offset = binary->info->mem_offsets.offsets.config->dmem.tnr.offset; + } + if (size) { + ia_css_tnr_config((struct sh_css_isp_tnr_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_tnr() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_ref( + const struct ia_css_binary *binary, + const struct ia_css_ref_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_ref() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.ref.size; + offset = binary->info->mem_offsets.offsets.config->dmem.ref.offset; + } + if (size) { + ia_css_ref_config((struct sh_css_isp_ref_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_ref() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_vf( + const struct ia_css_binary *binary, + const struct ia_css_vf_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_vf() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.vf.size; + offset = binary->info->mem_offsets.offsets.config->dmem.vf.offset; + } + if (size) { + ia_css_vf_config((struct sh_css_isp_vf_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_vf() leave:\n"); +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_configs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_configs.h new file mode 100644 index 0000000000000000000000000000000000000000..8aacd3dbc05a5263063f91a016f10329c24e61d9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_configs.h @@ -0,0 +1,189 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifdef IA_CSS_INCLUDE_CONFIGURATIONS +#include "isp/kernels/crop/crop_1.0/ia_css_crop.host.h" +#include "isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.h" +#include "isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h" +#include "isp/kernels/ob/ob_1.0/ia_css_ob.host.h" +#include "isp/kernels/output/output_1.0/ia_css_output.host.h" +#include "isp/kernels/qplane/qplane_2/ia_css_qplane.host.h" +#include "isp/kernels/raw/raw_1.0/ia_css_raw.host.h" +#include "isp/kernels/ref/ref_1.0/ia_css_ref.host.h" +#include "isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h" +#ifdef ISP2401 +#include "isp/kernels/sc/sc_1.0/ia_css_sc.host.h" +#endif +#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h" +#include "isp/kernels/vf/vf_1.0/ia_css_vf.host.h" +#include "isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.h" +#include "isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.h" +#endif /* IA_CSS_INCLUDE_CONFIGURATIONS */ +/* Generated code: do not edit or commmit. */ + +#ifndef _IA_CSS_ISP_CONFIG_H +#define _IA_CSS_ISP_CONFIG_H + +/* Code generated by genparam/gencode.c:gen_param_enum() */ + +enum ia_css_configuration_ids { + IA_CSS_ITERATOR_CONFIG_ID, + IA_CSS_COPY_OUTPUT_CONFIG_ID, + IA_CSS_CROP_CONFIG_ID, + IA_CSS_FPN_CONFIG_ID, + IA_CSS_DVS_CONFIG_ID, + IA_CSS_QPLANE_CONFIG_ID, + IA_CSS_OUTPUT0_CONFIG_ID, + IA_CSS_OUTPUT1_CONFIG_ID, + IA_CSS_OUTPUT_CONFIG_ID, +#ifdef ISP2401 + IA_CSS_SC_CONFIG_ID, +#endif + IA_CSS_RAW_CONFIG_ID, + IA_CSS_TNR_CONFIG_ID, + IA_CSS_REF_CONFIG_ID, + IA_CSS_VF_CONFIG_ID, + IA_CSS_NUM_CONFIGURATION_IDS +}; + +/* Code generated by genparam/gencode.c:gen_param_offsets() */ + +struct ia_css_config_memory_offsets { + struct { + struct ia_css_isp_parameter iterator; + struct ia_css_isp_parameter copy_output; + struct ia_css_isp_parameter crop; + struct ia_css_isp_parameter fpn; + struct ia_css_isp_parameter dvs; + struct ia_css_isp_parameter qplane; + struct ia_css_isp_parameter output0; + struct ia_css_isp_parameter output1; + struct ia_css_isp_parameter output; +#ifdef ISP2401 + struct ia_css_isp_parameter sc; +#endif + struct ia_css_isp_parameter raw; + struct ia_css_isp_parameter tnr; + struct ia_css_isp_parameter ref; + struct ia_css_isp_parameter vf; + } dmem; +}; + +#if defined(IA_CSS_INCLUDE_CONFIGURATIONS) + +#include "ia_css_stream.h" /* struct ia_css_stream */ +#include "ia_css_binary.h" /* struct ia_css_binary */ +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_iterator( + const struct ia_css_binary *binary, + const struct ia_css_iterator_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_copy_output( + const struct ia_css_binary *binary, + const struct ia_css_copy_output_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_crop( + const struct ia_css_binary *binary, + const struct ia_css_crop_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_fpn( + const struct ia_css_binary *binary, + const struct ia_css_fpn_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_dvs( + const struct ia_css_binary *binary, + const struct ia_css_dvs_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_qplane( + const struct ia_css_binary *binary, + const struct ia_css_qplane_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output0( + const struct ia_css_binary *binary, + const struct ia_css_output0_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output1( + const struct ia_css_binary *binary, + const struct ia_css_output1_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output( + const struct ia_css_binary *binary, + const struct ia_css_output_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +#ifdef ISP2401 +void +ia_css_configure_sc( + const struct ia_css_binary *binary, + const struct ia_css_sc_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +#endif +void +ia_css_configure_raw( + const struct ia_css_binary *binary, + const struct ia_css_raw_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_tnr( + const struct ia_css_binary *binary, + const struct ia_css_tnr_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_ref( + const struct ia_css_binary *binary, + const struct ia_css_ref_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_vf( + const struct ia_css_binary *binary, + const struct ia_css_vf_configuration *config_dmem); + +#endif /* IA_CSS_INCLUDE_CONFIGURATION */ + +#endif /* _IA_CSS_ISP_CONFIG_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_params.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_params.c new file mode 100644 index 0000000000000000000000000000000000000000..744e56ec9c12b1b25caeaf299ade78ab6e51cda9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_params.c @@ -0,0 +1,3238 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#define IA_CSS_INCLUDE_PARAMETERS +#include "sh_css_params.h" +#include "isp/kernels/aa/aa_2/ia_css_aa2.host.h" +#include "isp/kernels/anr/anr_1.0/ia_css_anr.host.h" +#include "isp/kernels/anr/anr_2/ia_css_anr2.host.h" +#include "isp/kernels/bh/bh_2/ia_css_bh.host.h" +#include "isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.h" +#include "isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.h" +#include "isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h" +#include "isp/kernels/crop/crop_1.0/ia_css_crop.host.h" +#include "isp/kernels/csc/csc_1.0/ia_css_csc.host.h" +#include "isp/kernels/ctc/ctc_1.0/ia_css_ctc.host.h" +#include "isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.h" +#include "isp/kernels/ctc/ctc2/ia_css_ctc2.host.h" +#include "isp/kernels/de/de_1.0/ia_css_de.host.h" +#include "isp/kernels/de/de_2/ia_css_de2.host.h" +#include "isp/kernels/dp/dp_1.0/ia_css_dp.host.h" +#include "isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds.host.h" +#include "isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h" +#include "isp/kernels/gc/gc_1.0/ia_css_gc.host.h" +#include "isp/kernels/gc/gc_2/ia_css_gc2.host.h" +#include "isp/kernels/macc/macc_1.0/ia_css_macc.host.h" +#include "isp/kernels/macc/macc1_5/ia_css_macc1_5.host.h" +#include "isp/kernels/ob/ob_1.0/ia_css_ob.host.h" +#include "isp/kernels/ob/ob2/ia_css_ob2.host.h" +#include "isp/kernels/output/output_1.0/ia_css_output.host.h" +#include "isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.h" +#include "isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h" +#include "isp/kernels/sc/sc_1.0/ia_css_sc.host.h" +#include "isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.h" +#include "isp/kernels/sdis/sdis_2/ia_css_sdis2.host.h" +#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h" +#include "isp/kernels/uds/uds_1.0/ia_css_uds.host.h" +#include "isp/kernels/wb/wb_1.0/ia_css_wb.host.h" +#include "isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.h" +#include "isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.h" +#include "isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h" +#include "isp/kernels/ynr/ynr_2/ia_css_ynr2.host.h" +#include "isp/kernels/fc/fc_1.0/ia_css_formats.host.h" +#include "isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.h" +#include "isp/kernels/iefd2_6/ia_css_iefd2_6.host.h" +#include "isp/kernels/dpc2/ia_css_dpc2.host.h" +#include "isp/kernels/eed1_8/ia_css_eed1_8.host.h" +#include "isp/kernels/bnlm/ia_css_bnlm.host.h" +#include "isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.h" +/* Generated code: do not edit or commmit. */ + +#include "ia_css_pipeline.h" +#include "ia_css_isp_params.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_aa( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.aa.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.aa.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_aa() enter:\n"); + + ia_css_aa_encode((struct sh_css_isp_aa_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->aa_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_aa() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_anr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.anr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.anr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr() enter:\n"); + + ia_css_anr_encode((struct sh_css_isp_anr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->anr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_anr2( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.anr2.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.anr2.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr2() enter:\n"); + + ia_css_anr2_vmem_encode((struct ia_css_isp_anr2_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->anr_thres, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr2() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_bh( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bh.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bh.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() enter:\n"); + + ia_css_bh_encode((struct sh_css_isp_bh_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->s3a_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() leave:\n"); + } + + } + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->hmem0.bh.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->hmem0.bh.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() enter:\n"); + + ia_css_bh_hmem_encode((struct sh_css_isp_bh_hmem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_HMEM0].address[offset], + ¶ms->s3a_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_HMEM0] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_cnr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.cnr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.cnr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_cnr() enter:\n"); + + ia_css_cnr_encode((struct sh_css_isp_cnr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->cnr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_cnr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_crop( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.crop.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.crop.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_crop() enter:\n"); + + ia_css_crop_encode((struct sh_css_isp_crop_isp_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->crop_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_crop() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_csc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.csc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.csc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_csc() enter:\n"); + + ia_css_csc_encode((struct sh_css_isp_csc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->cc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_csc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_dp( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.dp.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.dp.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_dp() enter:\n"); + + ia_css_dp_encode((struct sh_css_isp_dp_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dp_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_dp() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_bnr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bnr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bnr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bnr() enter:\n"); + + ia_css_bnr_encode((struct sh_css_isp_bnr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->nr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bnr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_de( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.de.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.de.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_de() enter:\n"); + + ia_css_de_encode((struct sh_css_isp_de_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->de_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_de() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ecd( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ecd.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ecd.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ecd() enter:\n"); + + ia_css_ecd_encode((struct sh_css_isp_ecd_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ecd_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ecd() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_formats( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.formats.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.formats.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_formats() enter:\n"); + + ia_css_formats_encode((struct sh_css_isp_formats_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->formats_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_formats() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_fpn( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.fpn.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.fpn.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fpn() enter:\n"); + + ia_css_fpn_encode((struct sh_css_isp_fpn_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->fpn_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fpn() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_gc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.gc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.gc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() enter:\n"); + + ia_css_gc_encode((struct sh_css_isp_gc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->gc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() leave:\n"); + } + + } + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.gc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.gc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() enter:\n"); + + ia_css_gc_vamem_encode((struct sh_css_isp_gc_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM1].address[offset], + ¶ms->gc_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM1] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ce( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ce.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ce.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ce() enter:\n"); + + ia_css_ce_encode((struct sh_css_isp_ce_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ce_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ce() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_yuv2rgb( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yuv2rgb() enter:\n"); + + ia_css_yuv2rgb_encode((struct sh_css_isp_csc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->yuv2rgb_cc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yuv2rgb() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_rgb2yuv( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_rgb2yuv() enter:\n"); + + ia_css_rgb2yuv_encode((struct sh_css_isp_csc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->rgb2yuv_cc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_rgb2yuv() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_r_gamma( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_r_gamma() enter:\n"); + + ia_css_r_gamma_vamem_encode((struct sh_css_isp_rgb_gamma_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM0].address[offset], + ¶ms->r_gamma_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM0] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_r_gamma() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_g_gamma( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_g_gamma() enter:\n"); + + ia_css_g_gamma_vamem_encode((struct sh_css_isp_rgb_gamma_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM1].address[offset], + ¶ms->g_gamma_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM1] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_g_gamma() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_b_gamma( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_b_gamma() enter:\n"); + + ia_css_b_gamma_vamem_encode((struct sh_css_isp_rgb_gamma_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM2].address[offset], + ¶ms->b_gamma_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM2] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_b_gamma() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_uds( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.uds.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.uds.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_uds() enter:\n"); + + ia_css_uds_encode((struct sh_css_sp_uds_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->uds_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_uds() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_raa( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.raa.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.raa.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_raa() enter:\n"); + + ia_css_raa_encode((struct sh_css_isp_aa_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->raa_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_raa() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_s3a( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.s3a.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.s3a.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_s3a() enter:\n"); + + ia_css_s3a_encode((struct sh_css_isp_s3a_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->s3a_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_s3a() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ob( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ob.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ob.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() enter:\n"); + + ia_css_ob_encode((struct sh_css_isp_ob_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ob_config, +¶ms->stream_configs.ob, size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() leave:\n"); + } + + } + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.ob.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.ob.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() enter:\n"); + + ia_css_ob_vmem_encode((struct sh_css_isp_ob_vmem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->ob_config, +¶ms->stream_configs.ob, size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_output( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.output.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.output.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_output() enter:\n"); + + ia_css_output_encode((struct sh_css_isp_output_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->output_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_output() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sc() enter:\n"); + + ia_css_sc_encode((struct sh_css_isp_sc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->sc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_bds( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bds.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bds.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bds() enter:\n"); + + ia_css_bds_encode((struct sh_css_isp_bds_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->bds_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bds() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_tnr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.tnr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.tnr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_tnr() enter:\n"); + + ia_css_tnr_encode((struct sh_css_isp_tnr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->tnr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_tnr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_macc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.macc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.macc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_macc() enter:\n"); + + ia_css_macc_encode((struct sh_css_isp_macc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->macc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_macc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis_horicoef( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horicoef() enter:\n"); + + ia_css_sdis_horicoef_vmem_encode((struct sh_css_isp_sdis_hori_coef_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->dvs_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horicoef() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis_vertcoef( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertcoef() enter:\n"); + + ia_css_sdis_vertcoef_vmem_encode((struct sh_css_isp_sdis_vert_coef_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->dvs_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertcoef() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis_horiproj( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horiproj() enter:\n"); + + ia_css_sdis_horiproj_encode((struct sh_css_isp_sdis_hori_proj_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dvs_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horiproj() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis_vertproj( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertproj() enter:\n"); + + ia_css_sdis_vertproj_encode((struct sh_css_isp_sdis_vert_proj_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dvs_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertproj() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis2_horicoef( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horicoef() enter:\n"); + + ia_css_sdis2_horicoef_vmem_encode((struct sh_css_isp_sdis_hori_coef_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->dvs2_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horicoef() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis2_vertcoef( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertcoef() enter:\n"); + + ia_css_sdis2_vertcoef_vmem_encode((struct sh_css_isp_sdis_vert_coef_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->dvs2_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertcoef() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis2_horiproj( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horiproj() enter:\n"); + + ia_css_sdis2_horiproj_encode((struct sh_css_isp_sdis_hori_proj_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dvs2_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horiproj() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis2_vertproj( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertproj() enter:\n"); + + ia_css_sdis2_vertproj_encode((struct sh_css_isp_sdis_vert_proj_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dvs2_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertproj() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_wb( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.wb.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.wb.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_wb() enter:\n"); + + ia_css_wb_encode((struct sh_css_isp_wb_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->wb_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_wb() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_nr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.nr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.nr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_nr() enter:\n"); + + ia_css_nr_encode((struct sh_css_isp_ynr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->nr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_nr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_yee( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.yee.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.yee.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yee() enter:\n"); + + ia_css_yee_encode((struct sh_css_isp_yee_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->yee_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yee() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ynr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ynr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ynr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ynr() enter:\n"); + + ia_css_ynr_encode((struct sh_css_isp_yee2_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ynr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ynr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_fc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.fc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.fc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fc() enter:\n"); + + ia_css_fc_encode((struct sh_css_isp_fc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->fc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ctc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ctc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ctc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() enter:\n"); + + ia_css_ctc_encode((struct sh_css_isp_ctc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ctc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() leave:\n"); + } + + } + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() enter:\n"); + + ia_css_ctc_vamem_encode((struct sh_css_isp_ctc_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM0].address[offset], + ¶ms->ctc_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM0] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_xnr_table( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr_table() enter:\n"); + + ia_css_xnr_table_vamem_encode((struct sh_css_isp_xnr_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM1].address[offset], + ¶ms->xnr_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM1] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr_table() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_xnr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.xnr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.xnr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr() enter:\n"); + + ia_css_xnr_encode((struct sh_css_isp_xnr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->xnr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_xnr3( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() enter:\n"); + + ia_css_xnr3_encode((struct sh_css_isp_xnr3_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->xnr3_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() leave:\n"); + } + + } +#ifdef ISP2401 + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.xnr3.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.xnr3.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() enter:\n"); + + ia_css_xnr3_vmem_encode((struct sh_css_isp_xnr3_vmem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->xnr3_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() leave:\n"); + } + + } +#endif +} + +/* Code generated by genparam/gencode.c:gen_param_process_table() */ + +void (* ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) = { + ia_css_process_aa, + ia_css_process_anr, + ia_css_process_anr2, + ia_css_process_bh, + ia_css_process_cnr, + ia_css_process_crop, + ia_css_process_csc, + ia_css_process_dp, + ia_css_process_bnr, + ia_css_process_de, + ia_css_process_ecd, + ia_css_process_formats, + ia_css_process_fpn, + ia_css_process_gc, + ia_css_process_ce, + ia_css_process_yuv2rgb, + ia_css_process_rgb2yuv, + ia_css_process_r_gamma, + ia_css_process_g_gamma, + ia_css_process_b_gamma, + ia_css_process_uds, + ia_css_process_raa, + ia_css_process_s3a, + ia_css_process_ob, + ia_css_process_output, + ia_css_process_sc, + ia_css_process_bds, + ia_css_process_tnr, + ia_css_process_macc, + ia_css_process_sdis_horicoef, + ia_css_process_sdis_vertcoef, + ia_css_process_sdis_horiproj, + ia_css_process_sdis_vertproj, + ia_css_process_sdis2_horicoef, + ia_css_process_sdis2_vertcoef, + ia_css_process_sdis2_horiproj, + ia_css_process_sdis2_vertproj, + ia_css_process_wb, + ia_css_process_nr, + ia_css_process_yee, + ia_css_process_ynr, + ia_css_process_fc, + ia_css_process_ctc, + ia_css_process_xnr_table, + ia_css_process_xnr, + ia_css_process_xnr3, +}; + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_dp_config(const struct ia_css_isp_parameters *params, + struct ia_css_dp_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_dp_config() enter: " + "config=%p\n",config); + + *config = params->dp_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_dp_config() leave\n"); + ia_css_dp_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_dp_config(struct ia_css_isp_parameters *params, + const struct ia_css_dp_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_dp_config() enter:\n"); + ia_css_dp_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dp_config = *config; + params->config_changed[IA_CSS_DP_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_DP_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_dp_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_wb_config(const struct ia_css_isp_parameters *params, + struct ia_css_wb_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_wb_config() enter: " + "config=%p\n",config); + + *config = params->wb_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_wb_config() leave\n"); + ia_css_wb_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_wb_config(struct ia_css_isp_parameters *params, + const struct ia_css_wb_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_wb_config() enter:\n"); + ia_css_wb_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->wb_config = *config; + params->config_changed[IA_CSS_WB_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_WB_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_wb_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_tnr_config(const struct ia_css_isp_parameters *params, + struct ia_css_tnr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_tnr_config() enter: " + "config=%p\n",config); + + *config = params->tnr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_tnr_config() leave\n"); + ia_css_tnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_tnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_tnr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_tnr_config() enter:\n"); + ia_css_tnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->tnr_config = *config; + params->config_changed[IA_CSS_TNR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_TNR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_tnr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ob_config(const struct ia_css_isp_parameters *params, + struct ia_css_ob_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ob_config() enter: " + "config=%p\n",config); + + *config = params->ob_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ob_config() leave\n"); + ia_css_ob_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ob_config(struct ia_css_isp_parameters *params, + const struct ia_css_ob_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ob_config() enter:\n"); + ia_css_ob_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ob_config = *config; + params->config_changed[IA_CSS_OB_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_OB_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ob_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_de_config(const struct ia_css_isp_parameters *params, + struct ia_css_de_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_de_config() enter: " + "config=%p\n",config); + + *config = params->de_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_de_config() leave\n"); + ia_css_de_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_de_config(struct ia_css_isp_parameters *params, + const struct ia_css_de_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_de_config() enter:\n"); + ia_css_de_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->de_config = *config; + params->config_changed[IA_CSS_DE_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_DE_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_de_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_anr_config(const struct ia_css_isp_parameters *params, + struct ia_css_anr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr_config() enter: " + "config=%p\n",config); + + *config = params->anr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr_config() leave\n"); + ia_css_anr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_anr_config(struct ia_css_isp_parameters *params, + const struct ia_css_anr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_anr_config() enter:\n"); + ia_css_anr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->anr_config = *config; + params->config_changed[IA_CSS_ANR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_ANR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_anr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_anr2_config(const struct ia_css_isp_parameters *params, + struct ia_css_anr_thres *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr2_config() enter: " + "config=%p\n",config); + + *config = params->anr_thres; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr2_config() leave\n"); + ia_css_anr2_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_anr2_config(struct ia_css_isp_parameters *params, + const struct ia_css_anr_thres *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_anr2_config() enter:\n"); + ia_css_anr2_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->anr_thres = *config; + params->config_changed[IA_CSS_ANR2_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_ANR2_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_anr2_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ce_config(const struct ia_css_isp_parameters *params, + struct ia_css_ce_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ce_config() enter: " + "config=%p\n",config); + + *config = params->ce_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ce_config() leave\n"); + ia_css_ce_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ce_config(struct ia_css_isp_parameters *params, + const struct ia_css_ce_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ce_config() enter:\n"); + ia_css_ce_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ce_config = *config; + params->config_changed[IA_CSS_CE_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_CE_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ce_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ecd_config(const struct ia_css_isp_parameters *params, + struct ia_css_ecd_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ecd_config() enter: " + "config=%p\n",config); + + *config = params->ecd_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ecd_config() leave\n"); + ia_css_ecd_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ecd_config(struct ia_css_isp_parameters *params, + const struct ia_css_ecd_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ecd_config() enter:\n"); + ia_css_ecd_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ecd_config = *config; + params->config_changed[IA_CSS_ECD_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_ECD_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ecd_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ynr_config(const struct ia_css_isp_parameters *params, + struct ia_css_ynr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ynr_config() enter: " + "config=%p\n",config); + + *config = params->ynr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ynr_config() leave\n"); + ia_css_ynr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ynr_config(struct ia_css_isp_parameters *params, + const struct ia_css_ynr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ynr_config() enter:\n"); + ia_css_ynr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ynr_config = *config; + params->config_changed[IA_CSS_YNR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_YNR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ynr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_fc_config(const struct ia_css_isp_parameters *params, + struct ia_css_fc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_fc_config() enter: " + "config=%p\n",config); + + *config = params->fc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_fc_config() leave\n"); + ia_css_fc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_fc_config(struct ia_css_isp_parameters *params, + const struct ia_css_fc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_fc_config() enter:\n"); + ia_css_fc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->fc_config = *config; + params->config_changed[IA_CSS_FC_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_FC_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_fc_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_cnr_config(const struct ia_css_isp_parameters *params, + struct ia_css_cnr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_cnr_config() enter: " + "config=%p\n",config); + + *config = params->cnr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_cnr_config() leave\n"); + ia_css_cnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_cnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_cnr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_cnr_config() enter:\n"); + ia_css_cnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->cnr_config = *config; + params->config_changed[IA_CSS_CNR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_CNR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_cnr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_macc_config(const struct ia_css_isp_parameters *params, + struct ia_css_macc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_macc_config() enter: " + "config=%p\n",config); + + *config = params->macc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_macc_config() leave\n"); + ia_css_macc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_macc_config(struct ia_css_isp_parameters *params, + const struct ia_css_macc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_macc_config() enter:\n"); + ia_css_macc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->macc_config = *config; + params->config_changed[IA_CSS_MACC_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_MACC_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_macc_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ctc_config(const struct ia_css_isp_parameters *params, + struct ia_css_ctc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ctc_config() enter: " + "config=%p\n",config); + + *config = params->ctc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ctc_config() leave\n"); + ia_css_ctc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ctc_config(struct ia_css_isp_parameters *params, + const struct ia_css_ctc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ctc_config() enter:\n"); + ia_css_ctc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ctc_config = *config; + params->config_changed[IA_CSS_CTC_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_CTC_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ctc_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_aa_config(const struct ia_css_isp_parameters *params, + struct ia_css_aa_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_aa_config() enter: " + "config=%p\n",config); + + *config = params->aa_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_aa_config() leave\n"); + ia_css_aa_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_aa_config(struct ia_css_isp_parameters *params, + const struct ia_css_aa_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_aa_config() enter:\n"); + ia_css_aa_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->aa_config = *config; + params->config_changed[IA_CSS_AA_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_AA_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_aa_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_yuv2rgb_config(const struct ia_css_isp_parameters *params, + struct ia_css_cc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_yuv2rgb_config() enter: " + "config=%p\n",config); + + *config = params->yuv2rgb_cc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_yuv2rgb_config() leave\n"); + ia_css_yuv2rgb_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_yuv2rgb_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_yuv2rgb_config() enter:\n"); + ia_css_yuv2rgb_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->yuv2rgb_cc_config = *config; + params->config_changed[IA_CSS_YUV2RGB_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_YUV2RGB_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_yuv2rgb_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_rgb2yuv_config(const struct ia_css_isp_parameters *params, + struct ia_css_cc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_rgb2yuv_config() enter: " + "config=%p\n",config); + + *config = params->rgb2yuv_cc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_rgb2yuv_config() leave\n"); + ia_css_rgb2yuv_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_rgb2yuv_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_rgb2yuv_config() enter:\n"); + ia_css_rgb2yuv_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->rgb2yuv_cc_config = *config; + params->config_changed[IA_CSS_RGB2YUV_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_RGB2YUV_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_rgb2yuv_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_csc_config(const struct ia_css_isp_parameters *params, + struct ia_css_cc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_csc_config() enter: " + "config=%p\n",config); + + *config = params->cc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_csc_config() leave\n"); + ia_css_csc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_csc_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_csc_config() enter:\n"); + ia_css_csc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->cc_config = *config; + params->config_changed[IA_CSS_CSC_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_CSC_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_csc_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_nr_config(const struct ia_css_isp_parameters *params, + struct ia_css_nr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_nr_config() enter: " + "config=%p\n",config); + + *config = params->nr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_nr_config() leave\n"); + ia_css_nr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_nr_config(struct ia_css_isp_parameters *params, + const struct ia_css_nr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_nr_config() enter:\n"); + ia_css_nr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->nr_config = *config; + params->config_changed[IA_CSS_BNR_ID] = true; + params->config_changed[IA_CSS_NR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_NR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_nr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_gc_config(const struct ia_css_isp_parameters *params, + struct ia_css_gc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_gc_config() enter: " + "config=%p\n",config); + + *config = params->gc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_gc_config() leave\n"); + ia_css_gc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_gc_config(struct ia_css_isp_parameters *params, + const struct ia_css_gc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_gc_config() enter:\n"); + ia_css_gc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->gc_config = *config; + params->config_changed[IA_CSS_GC_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_GC_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_gc_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis_horicoef_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horicoef_config() enter: " + "config=%p\n",config); + + *config = params->dvs_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horicoef_config() leave\n"); + ia_css_sdis_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_horicoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_horicoef_config() enter:\n"); + ia_css_sdis_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs_coefs = *config; + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_horicoef_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis_vertcoef_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertcoef_config() enter: " + "config=%p\n",config); + + *config = params->dvs_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertcoef_config() leave\n"); + ia_css_sdis_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_vertcoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_vertcoef_config() enter:\n"); + ia_css_sdis_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs_coefs = *config; + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_vertcoef_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis_horiproj_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horiproj_config() enter: " + "config=%p\n",config); + + *config = params->dvs_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horiproj_config() leave\n"); + ia_css_sdis_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_horiproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_horiproj_config() enter:\n"); + ia_css_sdis_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs_coefs = *config; + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_horiproj_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis_vertproj_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertproj_config() enter: " + "config=%p\n",config); + + *config = params->dvs_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertproj_config() leave\n"); + ia_css_sdis_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_vertproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_vertproj_config() enter:\n"); + ia_css_sdis_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs_coefs = *config; + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_vertproj_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis2_horicoef_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs2_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horicoef_config() enter: " + "config=%p\n",config); + + *config = params->dvs2_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horicoef_config() leave\n"); + ia_css_sdis2_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_horicoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_horicoef_config() enter:\n"); + ia_css_sdis2_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs2_coefs = *config; + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_horicoef_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis2_vertcoef_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs2_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertcoef_config() enter: " + "config=%p\n",config); + + *config = params->dvs2_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertcoef_config() leave\n"); + ia_css_sdis2_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_vertcoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_vertcoef_config() enter:\n"); + ia_css_sdis2_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs2_coefs = *config; + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_vertcoef_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis2_horiproj_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs2_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horiproj_config() enter: " + "config=%p\n",config); + + *config = params->dvs2_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horiproj_config() leave\n"); + ia_css_sdis2_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_horiproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_horiproj_config() enter:\n"); + ia_css_sdis2_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs2_coefs = *config; + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_horiproj_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis2_vertproj_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs2_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertproj_config() enter: " + "config=%p\n",config); + + *config = params->dvs2_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertproj_config() leave\n"); + ia_css_sdis2_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_vertproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_vertproj_config() enter:\n"); + ia_css_sdis2_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs2_coefs = *config; + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_vertproj_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_r_gamma_config(const struct ia_css_isp_parameters *params, + struct ia_css_rgb_gamma_table *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_r_gamma_config() enter: " + "config=%p\n",config); + + *config = params->r_gamma_table; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_r_gamma_config() leave\n"); + ia_css_r_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_r_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_r_gamma_config() enter:\n"); + ia_css_r_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->r_gamma_table = *config; + params->config_changed[IA_CSS_R_GAMMA_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_R_GAMMA_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_r_gamma_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_g_gamma_config(const struct ia_css_isp_parameters *params, + struct ia_css_rgb_gamma_table *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_g_gamma_config() enter: " + "config=%p\n",config); + + *config = params->g_gamma_table; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_g_gamma_config() leave\n"); + ia_css_g_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_g_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_g_gamma_config() enter:\n"); + ia_css_g_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->g_gamma_table = *config; + params->config_changed[IA_CSS_G_GAMMA_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_G_GAMMA_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_g_gamma_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_b_gamma_config(const struct ia_css_isp_parameters *params, + struct ia_css_rgb_gamma_table *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_b_gamma_config() enter: " + "config=%p\n",config); + + *config = params->b_gamma_table; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_b_gamma_config() leave\n"); + ia_css_b_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_b_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_b_gamma_config() enter:\n"); + ia_css_b_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->b_gamma_table = *config; + params->config_changed[IA_CSS_B_GAMMA_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_B_GAMMA_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_b_gamma_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_xnr_table_config(const struct ia_css_isp_parameters *params, + struct ia_css_xnr_table *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_table_config() enter: " + "config=%p\n",config); + + *config = params->xnr_table; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_table_config() leave\n"); + ia_css_xnr_table_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr_table_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr_table *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr_table_config() enter:\n"); + ia_css_xnr_table_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->xnr_table = *config; + params->config_changed[IA_CSS_XNR_TABLE_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_XNR_TABLE_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr_table_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_formats_config(const struct ia_css_isp_parameters *params, + struct ia_css_formats_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_formats_config() enter: " + "config=%p\n",config); + + *config = params->formats_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_formats_config() leave\n"); + ia_css_formats_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_formats_config(struct ia_css_isp_parameters *params, + const struct ia_css_formats_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_formats_config() enter:\n"); + ia_css_formats_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->formats_config = *config; + params->config_changed[IA_CSS_FORMATS_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_FORMATS_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_formats_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_xnr_config(const struct ia_css_isp_parameters *params, + struct ia_css_xnr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_config() enter: " + "config=%p\n",config); + + *config = params->xnr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_config() leave\n"); + ia_css_xnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr_config() enter:\n"); + ia_css_xnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->xnr_config = *config; + params->config_changed[IA_CSS_XNR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_XNR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_xnr3_config(const struct ia_css_isp_parameters *params, + struct ia_css_xnr3_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr3_config() enter: " + "config=%p\n",config); + + *config = params->xnr3_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr3_config() leave\n"); + ia_css_xnr3_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr3_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr3_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr3_config() enter:\n"); + ia_css_xnr3_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->xnr3_config = *config; + params->config_changed[IA_CSS_XNR3_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_XNR3_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr3_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_s3a_config(const struct ia_css_isp_parameters *params, + struct ia_css_3a_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_s3a_config() enter: " + "config=%p\n",config); + + *config = params->s3a_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_s3a_config() leave\n"); + ia_css_s3a_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_s3a_config(struct ia_css_isp_parameters *params, + const struct ia_css_3a_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_s3a_config() enter:\n"); + ia_css_s3a_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->s3a_config = *config; + params->config_changed[IA_CSS_BH_ID] = true; + params->config_changed[IA_CSS_S3A_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_S3A_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_s3a_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_output_config(const struct ia_css_isp_parameters *params, + struct ia_css_output_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_output_config() enter: " + "config=%p\n",config); + + *config = params->output_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_output_config() leave\n"); + ia_css_output_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_output_config(struct ia_css_isp_parameters *params, + const struct ia_css_output_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_output_config() enter:\n"); + ia_css_output_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->output_config = *config; + params->config_changed[IA_CSS_OUTPUT_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_OUTPUT_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_output_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_global_access_function() */ + +void +ia_css_get_configs(struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config) +{ + ia_css_get_dp_config(params, config->dp_config); + ia_css_get_wb_config(params, config->wb_config); + ia_css_get_tnr_config(params, config->tnr_config); + ia_css_get_ob_config(params, config->ob_config); + ia_css_get_de_config(params, config->de_config); + ia_css_get_anr_config(params, config->anr_config); + ia_css_get_anr2_config(params, config->anr_thres); + ia_css_get_ce_config(params, config->ce_config); + ia_css_get_ecd_config(params, config->ecd_config); + ia_css_get_ynr_config(params, config->ynr_config); + ia_css_get_fc_config(params, config->fc_config); + ia_css_get_cnr_config(params, config->cnr_config); + ia_css_get_macc_config(params, config->macc_config); + ia_css_get_ctc_config(params, config->ctc_config); + ia_css_get_aa_config(params, config->aa_config); + ia_css_get_yuv2rgb_config(params, config->yuv2rgb_cc_config); + ia_css_get_rgb2yuv_config(params, config->rgb2yuv_cc_config); + ia_css_get_csc_config(params, config->cc_config); + ia_css_get_nr_config(params, config->nr_config); + ia_css_get_gc_config(params, config->gc_config); + ia_css_get_sdis_horicoef_config(params, config->dvs_coefs); + ia_css_get_sdis_vertcoef_config(params, config->dvs_coefs); + ia_css_get_sdis_horiproj_config(params, config->dvs_coefs); + ia_css_get_sdis_vertproj_config(params, config->dvs_coefs); + ia_css_get_sdis2_horicoef_config(params, config->dvs2_coefs); + ia_css_get_sdis2_vertcoef_config(params, config->dvs2_coefs); + ia_css_get_sdis2_horiproj_config(params, config->dvs2_coefs); + ia_css_get_sdis2_vertproj_config(params, config->dvs2_coefs); + ia_css_get_r_gamma_config(params, config->r_gamma_table); + ia_css_get_g_gamma_config(params, config->g_gamma_table); + ia_css_get_b_gamma_config(params, config->b_gamma_table); + ia_css_get_xnr_table_config(params, config->xnr_table); + ia_css_get_formats_config(params, config->formats_config); + ia_css_get_xnr_config(params, config->xnr_config); + ia_css_get_xnr3_config(params, config->xnr3_config); + ia_css_get_s3a_config(params, config->s3a_config); + ia_css_get_output_config(params, config->output_config); +} + +/* Code generated by genparam/gencode.c:gen_global_access_function() */ + +void +ia_css_set_configs(struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config) +{ + ia_css_set_dp_config(params, config->dp_config); + ia_css_set_wb_config(params, config->wb_config); + ia_css_set_tnr_config(params, config->tnr_config); + ia_css_set_ob_config(params, config->ob_config); + ia_css_set_de_config(params, config->de_config); + ia_css_set_anr_config(params, config->anr_config); + ia_css_set_anr2_config(params, config->anr_thres); + ia_css_set_ce_config(params, config->ce_config); + ia_css_set_ecd_config(params, config->ecd_config); + ia_css_set_ynr_config(params, config->ynr_config); + ia_css_set_fc_config(params, config->fc_config); + ia_css_set_cnr_config(params, config->cnr_config); + ia_css_set_macc_config(params, config->macc_config); + ia_css_set_ctc_config(params, config->ctc_config); + ia_css_set_aa_config(params, config->aa_config); + ia_css_set_yuv2rgb_config(params, config->yuv2rgb_cc_config); + ia_css_set_rgb2yuv_config(params, config->rgb2yuv_cc_config); + ia_css_set_csc_config(params, config->cc_config); + ia_css_set_nr_config(params, config->nr_config); + ia_css_set_gc_config(params, config->gc_config); + ia_css_set_sdis_horicoef_config(params, config->dvs_coefs); + ia_css_set_sdis_vertcoef_config(params, config->dvs_coefs); + ia_css_set_sdis_horiproj_config(params, config->dvs_coefs); + ia_css_set_sdis_vertproj_config(params, config->dvs_coefs); + ia_css_set_sdis2_horicoef_config(params, config->dvs2_coefs); + ia_css_set_sdis2_vertcoef_config(params, config->dvs2_coefs); + ia_css_set_sdis2_horiproj_config(params, config->dvs2_coefs); + ia_css_set_sdis2_vertproj_config(params, config->dvs2_coefs); + ia_css_set_r_gamma_config(params, config->r_gamma_table); + ia_css_set_g_gamma_config(params, config->g_gamma_table); + ia_css_set_b_gamma_config(params, config->b_gamma_table); + ia_css_set_xnr_table_config(params, config->xnr_table); + ia_css_set_formats_config(params, config->formats_config); + ia_css_set_xnr_config(params, config->xnr_config); + ia_css_set_xnr3_config(params, config->xnr3_config); + ia_css_set_s3a_config(params, config->s3a_config); + ia_css_set_output_config(params, config->output_config); +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_params.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_params.h new file mode 100644 index 0000000000000000000000000000000000000000..5b3deb7f74aecf1de25749111f2cc7c81d6cd3e2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_params.h @@ -0,0 +1,399 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* Generated code: do not edit or commmit. */ + +#ifndef _IA_CSS_ISP_PARAM_H +#define _IA_CSS_ISP_PARAM_H + +/* Code generated by genparam/gencode.c:gen_param_enum() */ + +enum ia_css_parameter_ids { + IA_CSS_AA_ID, + IA_CSS_ANR_ID, + IA_CSS_ANR2_ID, + IA_CSS_BH_ID, + IA_CSS_CNR_ID, + IA_CSS_CROP_ID, + IA_CSS_CSC_ID, + IA_CSS_DP_ID, + IA_CSS_BNR_ID, + IA_CSS_DE_ID, + IA_CSS_ECD_ID, + IA_CSS_FORMATS_ID, + IA_CSS_FPN_ID, + IA_CSS_GC_ID, + IA_CSS_CE_ID, + IA_CSS_YUV2RGB_ID, + IA_CSS_RGB2YUV_ID, + IA_CSS_R_GAMMA_ID, + IA_CSS_G_GAMMA_ID, + IA_CSS_B_GAMMA_ID, + IA_CSS_UDS_ID, + IA_CSS_RAA_ID, + IA_CSS_S3A_ID, + IA_CSS_OB_ID, + IA_CSS_OUTPUT_ID, + IA_CSS_SC_ID, + IA_CSS_BDS_ID, + IA_CSS_TNR_ID, + IA_CSS_MACC_ID, + IA_CSS_SDIS_HORICOEF_ID, + IA_CSS_SDIS_VERTCOEF_ID, + IA_CSS_SDIS_HORIPROJ_ID, + IA_CSS_SDIS_VERTPROJ_ID, + IA_CSS_SDIS2_HORICOEF_ID, + IA_CSS_SDIS2_VERTCOEF_ID, + IA_CSS_SDIS2_HORIPROJ_ID, + IA_CSS_SDIS2_VERTPROJ_ID, + IA_CSS_WB_ID, + IA_CSS_NR_ID, + IA_CSS_YEE_ID, + IA_CSS_YNR_ID, + IA_CSS_FC_ID, + IA_CSS_CTC_ID, + IA_CSS_XNR_TABLE_ID, + IA_CSS_XNR_ID, + IA_CSS_XNR3_ID, + IA_CSS_NUM_PARAMETER_IDS +}; + +/* Code generated by genparam/gencode.c:gen_param_offsets() */ + +struct ia_css_memory_offsets { + struct { + struct ia_css_isp_parameter aa; + struct ia_css_isp_parameter anr; + struct ia_css_isp_parameter bh; + struct ia_css_isp_parameter cnr; + struct ia_css_isp_parameter crop; + struct ia_css_isp_parameter csc; + struct ia_css_isp_parameter dp; + struct ia_css_isp_parameter bnr; + struct ia_css_isp_parameter de; + struct ia_css_isp_parameter ecd; + struct ia_css_isp_parameter formats; + struct ia_css_isp_parameter fpn; + struct ia_css_isp_parameter gc; + struct ia_css_isp_parameter ce; + struct ia_css_isp_parameter yuv2rgb; + struct ia_css_isp_parameter rgb2yuv; + struct ia_css_isp_parameter uds; + struct ia_css_isp_parameter raa; + struct ia_css_isp_parameter s3a; + struct ia_css_isp_parameter ob; + struct ia_css_isp_parameter output; + struct ia_css_isp_parameter sc; + struct ia_css_isp_parameter bds; + struct ia_css_isp_parameter tnr; + struct ia_css_isp_parameter macc; + struct ia_css_isp_parameter sdis_horiproj; + struct ia_css_isp_parameter sdis_vertproj; + struct ia_css_isp_parameter sdis2_horiproj; + struct ia_css_isp_parameter sdis2_vertproj; + struct ia_css_isp_parameter wb; + struct ia_css_isp_parameter nr; + struct ia_css_isp_parameter yee; + struct ia_css_isp_parameter ynr; + struct ia_css_isp_parameter fc; + struct ia_css_isp_parameter ctc; + struct ia_css_isp_parameter xnr; + struct ia_css_isp_parameter xnr3; + struct ia_css_isp_parameter get; + struct ia_css_isp_parameter put; + } dmem; + struct { + struct ia_css_isp_parameter anr2; + struct ia_css_isp_parameter ob; + struct ia_css_isp_parameter sdis_horicoef; + struct ia_css_isp_parameter sdis_vertcoef; + struct ia_css_isp_parameter sdis2_horicoef; + struct ia_css_isp_parameter sdis2_vertcoef; +#ifdef ISP2401 + struct ia_css_isp_parameter xnr3; +#endif + } vmem; + struct { + struct ia_css_isp_parameter bh; + } hmem0; + struct { + struct ia_css_isp_parameter gc; + struct ia_css_isp_parameter g_gamma; + struct ia_css_isp_parameter xnr_table; + } vamem1; + struct { + struct ia_css_isp_parameter r_gamma; + struct ia_css_isp_parameter ctc; + } vamem0; + struct { + struct ia_css_isp_parameter b_gamma; + } vamem2; +}; + +#if defined(IA_CSS_INCLUDE_PARAMETERS) + +#include "ia_css_stream.h" /* struct ia_css_stream */ +#include "ia_css_binary.h" /* struct ia_css_binary */ +/* Code generated by genparam/gencode.c:gen_param_process_table() */ + +struct ia_css_pipeline_stage; /* forward declaration */ + +extern void (* ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_dp_config(struct ia_css_isp_parameters *params, + const struct ia_css_dp_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_wb_config(struct ia_css_isp_parameters *params, + const struct ia_css_wb_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_tnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_tnr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ob_config(struct ia_css_isp_parameters *params, + const struct ia_css_ob_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_de_config(struct ia_css_isp_parameters *params, + const struct ia_css_de_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_anr_config(struct ia_css_isp_parameters *params, + const struct ia_css_anr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_anr2_config(struct ia_css_isp_parameters *params, + const struct ia_css_anr_thres *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ce_config(struct ia_css_isp_parameters *params, + const struct ia_css_ce_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ecd_config(struct ia_css_isp_parameters *params, + const struct ia_css_ecd_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ynr_config(struct ia_css_isp_parameters *params, + const struct ia_css_ynr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_fc_config(struct ia_css_isp_parameters *params, + const struct ia_css_fc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_cnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_cnr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_macc_config(struct ia_css_isp_parameters *params, + const struct ia_css_macc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ctc_config(struct ia_css_isp_parameters *params, + const struct ia_css_ctc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_aa_config(struct ia_css_isp_parameters *params, + const struct ia_css_aa_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_yuv2rgb_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_rgb2yuv_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_csc_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_nr_config(struct ia_css_isp_parameters *params, + const struct ia_css_nr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_gc_config(struct ia_css_isp_parameters *params, + const struct ia_css_gc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_horicoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_vertcoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_horiproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_vertproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_horicoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_vertcoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_horiproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_vertproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_r_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_g_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_b_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr_table_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr_table *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_formats_config(struct ia_css_isp_parameters *params, + const struct ia_css_formats_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr3_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr3_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_s3a_config(struct ia_css_isp_parameters *params, + const struct ia_css_3a_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_output_config(struct ia_css_isp_parameters *params, + const struct ia_css_output_config *config); + +/* Code generated by genparam/gencode.c:gen_global_access_function() */ + +void +ia_css_get_configs(struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config) +; +#ifdef ISP2401 + +#endif +/* Code generated by genparam/gencode.c:gen_global_access_function() */ + +void +ia_css_set_configs(struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config) +; +#ifdef ISP2401 + +#endif +#endif /* IA_CSS_INCLUDE_PARAMETER */ + +#endif /* _IA_CSS_ISP_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_states.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_states.c new file mode 100644 index 0000000000000000000000000000000000000000..471ceba7f313ed985d29ed938ad95117e2a0b878 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_states.c @@ -0,0 +1,217 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +/* Generated code: do not edit or commmit. */ + +#include "ia_css_pipeline.h" +#include "ia_css_isp_states.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_aa_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_aa_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.aa.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.aa.offset; + + if (size) { + ia_css_init_aa_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_aa_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_cnr_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.cnr.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.cnr.offset; + + if (size) { + ia_css_init_cnr_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_cnr2_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr2_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.cnr2.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.cnr2.offset; + + if (size) { + ia_css_init_cnr2_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr2_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_dp_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_dp_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.dp.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.dp.offset; + + if (size) { + ia_css_init_dp_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_dp_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_de_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_de_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.de.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.de.offset; + + if (size) { + ia_css_init_de_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_de_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_tnr_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_tnr_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->dmem.tnr.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->dmem.tnr.offset; + + if (size) { + ia_css_init_tnr_state((struct sh_css_isp_tnr_dmem_state *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_tnr_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_ref_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ref_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->dmem.ref.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->dmem.ref.offset; + + if (size) { + ia_css_init_ref_state((struct sh_css_isp_ref_dmem_state *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ref_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_ynr_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ynr_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.ynr.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.ynr.offset; + + if (size) { + ia_css_init_ynr_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ynr_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_state_init_table() */ + +void (* ia_css_kernel_init_state[IA_CSS_NUM_STATE_IDS])(const struct ia_css_binary *binary) = { + ia_css_initialize_aa_state, + ia_css_initialize_cnr_state, + ia_css_initialize_cnr2_state, + ia_css_initialize_dp_state, + ia_css_initialize_de_state, + ia_css_initialize_tnr_state, + ia_css_initialize_ref_state, + ia_css_initialize_ynr_state, +}; + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_states.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_states.h new file mode 100644 index 0000000000000000000000000000000000000000..d658a005d694ce52062748bccc677b36aa0e50ad --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_states.h @@ -0,0 +1,74 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#define IA_CSS_INCLUDE_STATES +#include "ia_css_memory_access.h" +#include "isp/kernels/aa/aa_2/ia_css_aa2.host.h" +#include "isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.h" +#include "isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h" +#include "isp/kernels/de/de_1.0/ia_css_de.host.h" +#include "isp/kernels/dp/dp_1.0/ia_css_dp.host.h" +#include "isp/kernels/ref/ref_1.0/ia_css_ref.host.h" +#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h" +#include "isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h" +#include "isp/kernels/iefd2_6/ia_css_iefd2_6.host.h" +#include "isp/kernels/dpc2/ia_css_dpc2.host.h" +#include "isp/kernels/eed1_8/ia_css_eed1_8.host.h" +/* Generated code: do not edit or commmit. */ + +#ifndef _IA_CSS_ISP_STATE_H +#define _IA_CSS_ISP_STATE_H + +/* Code generated by genparam/gencode.c:gen_param_enum() */ + +enum ia_css_state_ids { + IA_CSS_AA_STATE_ID, + IA_CSS_CNR_STATE_ID, + IA_CSS_CNR2_STATE_ID, + IA_CSS_DP_STATE_ID, + IA_CSS_DE_STATE_ID, + IA_CSS_TNR_STATE_ID, + IA_CSS_REF_STATE_ID, + IA_CSS_YNR_STATE_ID, + IA_CSS_NUM_STATE_IDS +}; + +/* Code generated by genparam/gencode.c:gen_param_offsets() */ + +struct ia_css_state_memory_offsets { + struct { + struct ia_css_isp_parameter aa; + struct ia_css_isp_parameter cnr; + struct ia_css_isp_parameter cnr2; + struct ia_css_isp_parameter dp; + struct ia_css_isp_parameter de; + struct ia_css_isp_parameter ynr; + } vmem; + struct { + struct ia_css_isp_parameter tnr; + struct ia_css_isp_parameter ref; + } dmem; +}; + +#if defined(IA_CSS_INCLUDE_STATES) + +#include "ia_css_stream.h" /* struct ia_css_stream */ +#include "ia_css_binary.h" /* struct ia_css_binary */ +/* Code generated by genparam/genstate.c:gen_state_init_table() */ + +extern void (* ia_css_kernel_init_state[IA_CSS_NUM_STATE_IDS])(const struct ia_css_binary *binary); + +#endif /* IA_CSS_INCLUDE_STATE */ + +#endif /* _IA_CSS_ISP_STATE_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/bits.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/bits.h new file mode 100644 index 0000000000000000000000000000000000000000..e71e33d9d1434c91cd8317ea40d5719c02b86172 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/bits.h @@ -0,0 +1,104 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HRT_BITS_H +#define _HRT_BITS_H + +#include "defs.h" + +#define _hrt_ones(n) HRTCAT(_hrt_ones_, n) +#define _hrt_ones_0x0 0x00000000U +#define _hrt_ones_0x1 0x00000001U +#define _hrt_ones_0x2 0x00000003U +#define _hrt_ones_0x3 0x00000007U +#define _hrt_ones_0x4 0x0000000FU +#define _hrt_ones_0x5 0x0000001FU +#define _hrt_ones_0x6 0x0000003FU +#define _hrt_ones_0x7 0x0000007FU +#define _hrt_ones_0x8 0x000000FFU +#define _hrt_ones_0x9 0x000001FFU +#define _hrt_ones_0xA 0x000003FFU +#define _hrt_ones_0xB 0x000007FFU +#define _hrt_ones_0xC 0x00000FFFU +#define _hrt_ones_0xD 0x00001FFFU +#define _hrt_ones_0xE 0x00003FFFU +#define _hrt_ones_0xF 0x00007FFFU +#define _hrt_ones_0x10 0x0000FFFFU +#define _hrt_ones_0x11 0x0001FFFFU +#define _hrt_ones_0x12 0x0003FFFFU +#define _hrt_ones_0x13 0x0007FFFFU +#define _hrt_ones_0x14 0x000FFFFFU +#define _hrt_ones_0x15 0x001FFFFFU +#define _hrt_ones_0x16 0x003FFFFFU +#define _hrt_ones_0x17 0x007FFFFFU +#define _hrt_ones_0x18 0x00FFFFFFU +#define _hrt_ones_0x19 0x01FFFFFFU +#define _hrt_ones_0x1A 0x03FFFFFFU +#define _hrt_ones_0x1B 0x07FFFFFFU +#define _hrt_ones_0x1C 0x0FFFFFFFU +#define _hrt_ones_0x1D 0x1FFFFFFFU +#define _hrt_ones_0x1E 0x3FFFFFFFU +#define _hrt_ones_0x1F 0x7FFFFFFFU +#define _hrt_ones_0x20 0xFFFFFFFFU + +#define _hrt_ones_0 _hrt_ones_0x0 +#define _hrt_ones_1 _hrt_ones_0x1 +#define _hrt_ones_2 _hrt_ones_0x2 +#define _hrt_ones_3 _hrt_ones_0x3 +#define _hrt_ones_4 _hrt_ones_0x4 +#define _hrt_ones_5 _hrt_ones_0x5 +#define _hrt_ones_6 _hrt_ones_0x6 +#define _hrt_ones_7 _hrt_ones_0x7 +#define _hrt_ones_8 _hrt_ones_0x8 +#define _hrt_ones_9 _hrt_ones_0x9 +#define _hrt_ones_10 _hrt_ones_0xA +#define _hrt_ones_11 _hrt_ones_0xB +#define _hrt_ones_12 _hrt_ones_0xC +#define _hrt_ones_13 _hrt_ones_0xD +#define _hrt_ones_14 _hrt_ones_0xE +#define _hrt_ones_15 _hrt_ones_0xF +#define _hrt_ones_16 _hrt_ones_0x10 +#define _hrt_ones_17 _hrt_ones_0x11 +#define _hrt_ones_18 _hrt_ones_0x12 +#define _hrt_ones_19 _hrt_ones_0x13 +#define _hrt_ones_20 _hrt_ones_0x14 +#define _hrt_ones_21 _hrt_ones_0x15 +#define _hrt_ones_22 _hrt_ones_0x16 +#define _hrt_ones_23 _hrt_ones_0x17 +#define _hrt_ones_24 _hrt_ones_0x18 +#define _hrt_ones_25 _hrt_ones_0x19 +#define _hrt_ones_26 _hrt_ones_0x1A +#define _hrt_ones_27 _hrt_ones_0x1B +#define _hrt_ones_28 _hrt_ones_0x1C +#define _hrt_ones_29 _hrt_ones_0x1D +#define _hrt_ones_30 _hrt_ones_0x1E +#define _hrt_ones_31 _hrt_ones_0x1F +#define _hrt_ones_32 _hrt_ones_0x20 + +#define _hrt_mask(b, n) \ + (_hrt_ones(n) << (b)) +#define _hrt_get_bits(w, b, n) \ + (((w) >> (b)) & _hrt_ones(n)) +#define _hrt_set_bits(w, b, n, v) \ + (((w) & ~_hrt_mask(b, n)) | (((v) & _hrt_ones(n)) << (b))) +#define _hrt_get_bit(w, b) \ + (((w) >> (b)) & 1) +#define _hrt_set_bit(w, b, v) \ + (((w) & (~(1 << (b)))) | (((v)&1) << (b))) +#define _hrt_set_lower_half(w, v) \ + _hrt_set_bits(w, 0, 16, v) +#define _hrt_set_upper_half(w, v) \ + _hrt_set_bits(w, 16, 16, v) + +#endif /* _HRT_BITS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/cell_params.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/cell_params.h new file mode 100644 index 0000000000000000000000000000000000000000..b5756bfe8eb6b1e10c7f70659bc20e6537e8df1c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/cell_params.h @@ -0,0 +1,42 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _cell_params_h +#define _cell_params_h + +#define SP_PMEM_LOG_WIDTH_BITS 6 /*Width of PC, 64 bits, 8 bytes*/ +#define SP_ICACHE_TAG_BITS 4 /*size of tag*/ +#define SP_ICACHE_SET_BITS 8 /* 256 sets*/ +#define SP_ICACHE_BLOCKS_PER_SET_BITS 1 /* 2 way associative*/ +#define SP_ICACHE_BLOCK_ADDRESS_BITS 11 /* 2048 lines capacity*/ + +#define SP_ICACHE_ADDRESS_BITS \ + (SP_ICACHE_TAG_BITS+SP_ICACHE_BLOCK_ADDRESS_BITS) + +#define SP_PMEM_DEPTH (1< input_selector*/ +/* !! Changes here should be copied to systems/isp/isp_css/bin/conv_transmitter_cmd.tcl !! */ +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB888 0 // 36 'h24 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB555 1 // 33 'h +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB444 2 // 32 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB565 3 // 34 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB666 4 // 35 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW10 6 // 43 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW6 7 // 40 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW7 8 // 41 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW12 9 // 43 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW14 10 // 45 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8 11 // 30 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10 12 // 25 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_8 13 // 30 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_10 14 // 31 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_1 15 // 48 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8L 16 // 26 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_Emb 17 // 18 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_2 18 // 49 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_3 19 // 50 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_4 20 // 51 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_5 21 // 52 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_6 22 // 53 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_7 23 // 54 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_8 24 // 55 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8_CSPS 25 // 28 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10_CSPS 26 // 29 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW16 27 // ? +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18 28 // ? +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_2 29 // ? Option 2 for depacketiser +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_3 30 // ? Option 3 for depacketiser +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding + +/* definition for state machine of data FIFO for decode different type of data */ +#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV420_10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_YUV420_8L_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV422_8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV422_10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB555_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB565_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9 +#define _HRT_CSS_RECEIVER_2400_RGB888_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW6_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW7_REPEAT_PTN 7 +#define _HRT_CSS_RECEIVER_2400_RAW8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_RAW10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW14_REPEAT_PTN 7 + +#define _HRT_CSS_RECEIVER_2400_MAX_REPEAT_PTN _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN + +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_WIDTH 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_IDX 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_WIDTH 1 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_USD_BITS 4 /* bits per USD type */ + +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_EN_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_OPTION_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_EN_IDX 8 + +#define _HRT_CSS_RECEIVER_2400_BE_COMP_NO_COMP 0 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_6_10 1 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_7_10 2 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_8_10 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_6_12 4 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_7_12 5 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_8_12 6 + + +/* packet bit definition */ +#define _HRT_CSS_RECEIVER_2400_PKT_SOP_IDX 32 +#define _HRT_CSS_RECEIVER_2400_PKT_SOP_BITS 1 +#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_IDX 22 +#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_BITS 2 +#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_IDX 16 +#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_BITS 6 +#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_IDX 0 +#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_BITS 16 +#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_IDX 0 +#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_BITS 32 + + +/*************************************************************************************************/ +/* Custom Decoding */ +/* These Custom Defs are defined based on design-time config in "csi_be_pixel_formatter.chdl" !! */ +/*************************************************************************************************/ +#define BE_CUST_EN_IDX 0 /* 2bits */ +#define BE_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */ +#define BE_CUST_EN_WIDTH 8 +#define BE_CUST_MODE_ALL 1 /* Enable Custom Decoding for all DATA IDs */ +#define BE_CUST_MODE_ONE 3 /* Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID */ + +/* Data State config = {get_bits(6bits), valid(1bit)} */ +#define BE_CUST_DATA_STATE_S0_IDX 0 /* 7bits */ +#define BE_CUST_DATA_STATE_S1_IDX 7 /* 7bits */ +#define BE_CUST_DATA_STATE_S2_IDX 14 /* 7bits */ +#define BE_CUST_DATA_STATE_WIDTH 21 +#define BE_CUST_DATA_STATE_VALID_IDX 0 /* 1bits */ +#define BE_CUST_DATA_STATE_GETBITS_IDX 1 /* 6bits */ + +/* Pixel Extractor config */ +#define BE_CUST_PIX_EXT_DATA_ALIGN_IDX 0 /* 5bits */ +#define BE_CUST_PIX_EXT_PIX_ALIGN_IDX 5 /* 5bits */ +#define BE_CUST_PIX_EXT_PIX_MASK_IDX 10 /* 18bits */ +#define BE_CUST_PIX_EXT_PIX_EN_IDX 28 /* 1bits */ +#define BE_CUST_PIX_EXT_WIDTH 29 + +/* Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} */ +#define BE_CUST_PIX_VALID_EOP_P0_IDX 0 /* 4bits */ +#define BE_CUST_PIX_VALID_EOP_P1_IDX 4 /* 4bits */ +#define BE_CUST_PIX_VALID_EOP_P2_IDX 8 /* 4bits */ +#define BE_CUST_PIX_VALID_EOP_P3_IDX 12 /* 4bits */ +#define BE_CUST_PIX_VALID_EOP_WIDTH 16 +#define BE_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 /* Normal (NO less get_bits case) Valid - 1bits */ +#define BE_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 /* Normal (NO less get_bits case) EoP - 1bits */ +#define BE_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 /* Especial (less get_bits case) Valid - 1bits */ +#define BE_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 /* Especial (less get_bits case) EoP - 1bits */ + +#endif /* _mipi_backend_common_defs_h_ */ +#endif /* _css_receiver_2400_common_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/css_receiver_2400_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/css_receiver_2400_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..6f5b7d3d3715e905f55265a2774be86cc5eb9f08 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/css_receiver_2400_defs.h @@ -0,0 +1,258 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _css_receiver_2400_defs_h_ +#define _css_receiver_2400_defs_h_ + +#include "css_receiver_2400_common_defs.h" + +#define CSS_RECEIVER_DATA_WIDTH 8 +#define CSS_RECEIVER_RX_TRIG 4 +#define CSS_RECEIVER_RF_WORD 32 +#define CSS_RECEIVER_IMG_PROC_RF_ADDR 10 +#define CSS_RECEIVER_CSI_RF_ADDR 4 +#define CSS_RECEIVER_DATA_OUT 12 +#define CSS_RECEIVER_CHN_NO 2 +#define CSS_RECEIVER_DWORD_CNT 11 +#define CSS_RECEIVER_FORMAT_TYP 5 +#define CSS_RECEIVER_HRESPONSE 2 +#define CSS_RECEIVER_STATE_WIDTH 3 +#define CSS_RECEIVER_FIFO_DAT 32 +#define CSS_RECEIVER_CNT_VAL 2 +#define CSS_RECEIVER_PRED10_VAL 10 +#define CSS_RECEIVER_PRED12_VAL 12 +#define CSS_RECEIVER_CNT_WIDTH 8 +#define CSS_RECEIVER_WORD_CNT 16 +#define CSS_RECEIVER_PIXEL_LEN 6 +#define CSS_RECEIVER_PIXEL_CNT 5 +#define CSS_RECEIVER_COMP_8_BIT 8 +#define CSS_RECEIVER_COMP_7_BIT 7 +#define CSS_RECEIVER_COMP_6_BIT 6 + +#define CSI_CONFIG_WIDTH 4 + +/* division of gen_short data, ch_id and fmt_type over streaming data interface */ +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB 0 +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB - 1) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB - 1) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH - 1) + +#define _HRT_CSS_RECEIVER_2400_REG_ALIGN 4 +#define _HRT_CSS_RECEIVER_2400_BYTES_PER_PKT 4 + +#define hrt_css_receiver_2400_4_lane_port_offset 0x100 +#define hrt_css_receiver_2400_1_lane_port_offset 0x200 +#define hrt_css_receiver_2400_2_lane_port_offset 0x300 +#define hrt_css_receiver_2400_backend_port_offset 0x100 + +#define _HRT_CSS_RECEIVER_2400_DEVICE_READY_REG_IDX 0 +#define _HRT_CSS_RECEIVER_2400_IRQ_STATUS_REG_IDX 1 +#define _HRT_CSS_RECEIVER_2400_IRQ_ENABLE_REG_IDX 2 +#define _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX 3 +#define _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX 4 +#define _HRT_CSS_RECEIVER_2400_FS_TO_LS_DELAY_REG_IDX 7 +#define _HRT_CSS_RECEIVER_2400_LS_TO_DATA_DELAY_REG_IDX 8 +#define _HRT_CSS_RECEIVER_2400_DATA_TO_LE_DELAY_REG_IDX 9 +#define _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX 10 +#define _HRT_CSS_RECEIVER_2400_FE_TO_FS_DELAY_REG_IDX 11 +#define _HRT_CSS_RECEIVER_2400_LE_TO_LS_DELAY_REG_IDX 12 +#define _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX 13 +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_REG_IDX 14 +#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX 15 +#define _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX 16 +#define _HRT_CSS_RECEIVER_2400_BACKEND_RST_REG_IDX 17 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX 18 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX 19 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX 20 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX 21 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX 22 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX 23 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX 24 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX 25 +#define _HRT_CSS_RECEIVER_2400_RAW18_REG_IDX 26 +#define _HRT_CSS_RECEIVER_2400_FORCE_RAW8_REG_IDX 27 +#define _HRT_CSS_RECEIVER_2400_RAW16_REG_IDX 28 + +/* Interrupt bits for IRQ_STATUS and IRQ_ENABLE registers */ +#define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_BIT 0 +#define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_BIT 1 +#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_BIT 2 +#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_BIT 3 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_BIT 4 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_BIT 5 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_BIT 6 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_BIT 7 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_BIT 8 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_BIT 9 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT 10 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_BIT 11 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_BIT 12 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_BIT 13 +#define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_BIT 14 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_BIT 15 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_BIT 16 + +#define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_CAUSE_ "Fifo Overrun" +#define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_CAUSE_ "Reserved" +#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_CAUSE_ "Sleep mode entry" +#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_CAUSE_ "Sleep mode exit" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_CAUSE_ "Error high speed SOT" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_CAUSE_ "Error high speed sync SOT" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_CAUSE_ "Error control" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_CAUSE_ "Error correction double bit" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_CAUSE_ "Error correction single bit" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_CAUSE_ "No error" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_CAUSE_ "Error cyclic redundancy check" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_CAUSE_ "Error id" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_CAUSE_ "Error frame sync" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_CAUSE_ "Error frame data" +#define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_CAUSE_ "Data time-out" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_CAUSE_ "Error escape" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_CAUSE_ "Error line sync" + +/* Bits for CSI2_DEVICE_READY register */ +#define _HRT_CSS_RECEIVER_2400_CSI2_DEVICE_READY_IDX 0 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_INIT_TIME_OUT_ERR_IDX 2 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_OVER_RUN_ERR_IDX 3 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_SOT_SYNC_ERR_IDX 4 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_RECEIVE_DATA_TIME_OUT_ERR_IDX 5 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_ECC_TWO_BIT_ERR_IDX 6 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_DATA_ID_ERR_IDX 7 + + +/* Bits for CSI2_FUNC_PROG register */ +#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS 19 + +/* Bits for INIT_COUNT register */ +#define _HRT_CSS_RECEIVER_2400_INIT_TIMER_IDX 0 +#define _HRT_CSS_RECEIVER_2400_INIT_TIMER_BITS 16 + +/* Bits for COUNT registers */ +#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_BITS 8 +#define _HRT_CSS_RECEIVER_2400_RX_COUNT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_RX_COUNT_BITS 8 + +/* Bits for RAW116_18_DATAID register */ +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_BITS 6 +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_IDX 8 +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_BITS 6 + +/* Bits for COMP_FORMAT register, this selects the compression data format */ +#define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS 8 +#define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_IDX (_HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX + _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS) +#define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_BITS 8 + +/* Bits for COMP_PREDICT register, this selects the predictor algorithm */ +#define _HRT_CSS_RECEIVER_2400_PREDICT_NO_COMP 0 +#define _HRT_CSS_RECEIVER_2400_PREDICT_1 1 +#define _HRT_CSS_RECEIVER_2400_PREDICT_2 2 + +/* Number of bits used for the delay registers */ +#define _HRT_CSS_RECEIVER_2400_DELAY_BITS 8 + +/* Bits for COMP_SCHEME register, this selects the compression scheme for a VC */ +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD1_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD2_BITS_IDX 5 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD3_BITS_IDX 10 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD4_BITS_IDX 15 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD5_BITS_IDX 20 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD6_BITS_IDX 25 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD7_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD8_BITS_IDX 5 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_BITS_BITS 5 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_BITS 3 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_IDX 3 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_BITS 2 + + +/* BITS for backend RAW16 and RAW 18 registers */ + +#define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_BITS 6 +#define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_IDX 6 +#define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_BITS 2 +#define _HRT_CSS_RECEIVER_2400_RAW18_EN_IDX 8 +#define _HRT_CSS_RECEIVER_2400_RAW18_EN_BITS 1 + +#define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_BITS 6 +#define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_IDX 6 +#define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_BITS 2 +#define _HRT_CSS_RECEIVER_2400_RAW16_EN_IDX 8 +#define _HRT_CSS_RECEIVER_2400_RAW16_EN_BITS 1 + +/* These hsync and vsync values are for HSS simulation only */ +#define _HRT_CSS_RECEIVER_2400_HSYNC_VAL (1<<16) +#define _HRT_CSS_RECEIVER_2400_VSYNC_VAL (1<<17) + +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_WIDTH 28 +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB 0 +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB + CSS_RECEIVER_DATA_OUT - 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB + 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT + 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB + CSS_RECEIVER_DATA_OUT - 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB + 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT + 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_EOP_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT + 1) + +// SH Backend Register IDs +#define _HRT_CSS_RECEIVER_2400_BE_GSP_ACC_OVL_REG_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_REG_IDX 1 +#define _HRT_CSS_RECEIVER_2400_BE_TWO_PPC_REG_IDX 2 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG0_IDX 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG1_IDX 4 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG2_IDX 5 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG3_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_SEL_REG_IDX 7 +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_CONFIG_REG_IDX 8 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_CONFIG_REG_IDX 9 +#define _HRT_CSS_RECEIVER_2400_BE_FORCE_RAW8_REG_IDX 10 +#define _HRT_CSS_RECEIVER_2400_BE_IRQ_STATUS_REG_IDX 11 +#define _HRT_CSS_RECEIVER_2400_BE_IRQ_CLEAR_REG_IDX 12 +#define _HRT_CSS_RECEIVER_2400_BE_CUST_EN_REG_IDX 13 +#define _HRT_CSS_RECEIVER_2400_BE_CUST_DATA_STATE_REG_IDX 14 /* Data State 0,1,2 config */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P0_REG_IDX 15 /* Pixel Extractor config for Data State 0 & Pix 0 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P1_REG_IDX 16 /* Pixel Extractor config for Data State 0 & Pix 1 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P2_REG_IDX 17 /* Pixel Extractor config for Data State 0 & Pix 2 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P3_REG_IDX 18 /* Pixel Extractor config for Data State 0 & Pix 3 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P0_REG_IDX 19 /* Pixel Extractor config for Data State 1 & Pix 0 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P1_REG_IDX 20 /* Pixel Extractor config for Data State 1 & Pix 1 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P2_REG_IDX 21 /* Pixel Extractor config for Data State 1 & Pix 2 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P3_REG_IDX 22 /* Pixel Extractor config for Data State 1 & Pix 3 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P0_REG_IDX 23 /* Pixel Extractor config for Data State 2 & Pix 0 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P1_REG_IDX 24 /* Pixel Extractor config for Data State 2 & Pix 1 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P2_REG_IDX 25 /* Pixel Extractor config for Data State 2 & Pix 2 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P3_REG_IDX 26 /* Pixel Extractor config for Data State 2 & Pix 3 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_VALID_EOP_REG_IDX 27 /* Pixel Valid & EoP config for Pix 0,1,2,3 */ + +#define _HRT_CSS_RECEIVER_2400_BE_NOF_REGISTERS 28 + +#define _HRT_CSS_RECEIVER_2400_BE_SRST_HE 0 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_RCF 1 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_PF 2 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_SM 3 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_PD 4 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_SD 5 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_OT 6 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_BC 7 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_WIDTH 8 + +#endif /* _css_receiver_2400_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/defs.h new file mode 100644 index 0000000000000000000000000000000000000000..47505f41790c17ef0aa42727d9553666bb3961ae --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/defs.h @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HRT_DEFS_H_ +#define _HRT_DEFS_H_ + +#ifndef HRTCAT +#define _HRTCAT(m, n) m##n +#define HRTCAT(m, n) _HRTCAT(m, n) +#endif + +#ifndef HRTSTR +#define _HRTSTR(x) #x +#define HRTSTR(x) _HRTSTR(x) +#endif + +#ifndef HRTMIN +#define HRTMIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef HRTMAX +#define HRTMAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +#endif /* _HRT_DEFS_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/dma_v2_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/dma_v2_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..d184a8b313c91c6978c70b10c42f32231cc65cb9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/dma_v2_defs.h @@ -0,0 +1,199 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _dma_v2_defs_h +#define _dma_v2_defs_h + +#define _DMA_V2_NUM_CHANNELS_ID MaxNumChannels +#define _DMA_V2_CONNECTIONS_ID Connections +#define _DMA_V2_DEV_ELEM_WIDTHS_ID DevElemWidths +#define _DMA_V2_DEV_FIFO_DEPTH_ID DevFifoDepth +#define _DMA_V2_DEV_FIFO_RD_LAT_ID DevFifoRdLat +#define _DMA_V2_DEV_FIFO_LAT_BYPASS_ID DevFifoRdLatBypass +#define _DMA_V2_DEV_NO_BURST_ID DevNoBurst +#define _DMA_V2_DEV_RD_ACCEPT_ID DevRdAccept +#define _DMA_V2_DEV_SRMD_ID DevSRMD +#define _DMA_V2_DEV_HAS_CRUN_ID CRunMasters +#define _DMA_V2_CTRL_ACK_FIFO_DEPTH_ID CtrlAckFifoDepth +#define _DMA_V2_CMD_FIFO_DEPTH_ID CommandFifoDepth +#define _DMA_V2_CMD_FIFO_RD_LAT_ID CommandFifoRdLat +#define _DMA_V2_CMD_FIFO_LAT_BYPASS_ID CommandFifoRdLatBypass +#define _DMA_V2_NO_PACK_ID has_no_pack + +#define _DMA_V2_REG_ALIGN 4 +#define _DMA_V2_REG_ADDR_BITS 2 + +/* Command word */ +#define _DMA_V2_CMD_IDX 0 +#define _DMA_V2_CMD_BITS 6 +#define _DMA_V2_CHANNEL_IDX (_DMA_V2_CMD_IDX + _DMA_V2_CMD_BITS) +#define _DMA_V2_CHANNEL_BITS 5 + +/* The command to set a parameter contains the PARAM field next */ +#define _DMA_V2_PARAM_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS) +#define _DMA_V2_PARAM_BITS 4 + +/* Commands to read, write or init specific blocks contain these + three values */ +#define _DMA_V2_SPEC_DEV_A_XB_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS) +#define _DMA_V2_SPEC_DEV_A_XB_BITS 8 +#define _DMA_V2_SPEC_DEV_B_XB_IDX (_DMA_V2_SPEC_DEV_A_XB_IDX + _DMA_V2_SPEC_DEV_A_XB_BITS) +#define _DMA_V2_SPEC_DEV_B_XB_BITS 8 +#define _DMA_V2_SPEC_YB_IDX (_DMA_V2_SPEC_DEV_B_XB_IDX + _DMA_V2_SPEC_DEV_B_XB_BITS) +#define _DMA_V2_SPEC_YB_BITS (32-_DMA_V2_SPEC_DEV_B_XB_BITS-_DMA_V2_SPEC_DEV_A_XB_BITS-_DMA_V2_CMD_BITS-_DMA_V2_CHANNEL_BITS) + +/* */ +#define _DMA_V2_CMD_CTRL_IDX 4 +#define _DMA_V2_CMD_CTRL_BITS 4 + +/* Packing setup word */ +#define _DMA_V2_CONNECTION_IDX 0 +#define _DMA_V2_CONNECTION_BITS 4 +#define _DMA_V2_EXTENSION_IDX (_DMA_V2_CONNECTION_IDX + _DMA_V2_CONNECTION_BITS) +#define _DMA_V2_EXTENSION_BITS 1 + +/* Elements packing word */ +#define _DMA_V2_ELEMENTS_IDX 0 +#define _DMA_V2_ELEMENTS_BITS 8 +#define _DMA_V2_LEFT_CROPPING_IDX (_DMA_V2_ELEMENTS_IDX + _DMA_V2_ELEMENTS_BITS) +#define _DMA_V2_LEFT_CROPPING_BITS 8 + +#define _DMA_V2_WIDTH_IDX 0 +#define _DMA_V2_WIDTH_BITS 16 + +#define _DMA_V2_HEIGHT_IDX 0 +#define _DMA_V2_HEIGHT_BITS 16 + +#define _DMA_V2_STRIDE_IDX 0 +#define _DMA_V2_STRIDE_BITS 32 + +/* Command IDs */ +#define _DMA_V2_MOVE_B2A_COMMAND 0 +#define _DMA_V2_MOVE_B2A_BLOCK_COMMAND 1 +#define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND 2 +#define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND 3 +#define _DMA_V2_MOVE_A2B_COMMAND 4 +#define _DMA_V2_MOVE_A2B_BLOCK_COMMAND 5 +#define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND 6 +#define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND 7 +#define _DMA_V2_INIT_A_COMMAND 8 +#define _DMA_V2_INIT_A_BLOCK_COMMAND 9 +#define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND 10 +#define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND 11 +#define _DMA_V2_INIT_B_COMMAND 12 +#define _DMA_V2_INIT_B_BLOCK_COMMAND 13 +#define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND 14 +#define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND 15 +#define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_CONFIG_CHANNEL_COMMAND 32 +#define _DMA_V2_SET_CHANNEL_PARAM_COMMAND 33 +#define _DMA_V2_SET_CRUN_COMMAND 62 + +/* Channel Parameter IDs */ +#define _DMA_V2_PACKING_SETUP_PARAM 0 +#define _DMA_V2_STRIDE_A_PARAM 1 +#define _DMA_V2_ELEM_CROPPING_A_PARAM 2 +#define _DMA_V2_WIDTH_A_PARAM 3 +#define _DMA_V2_STRIDE_B_PARAM 4 +#define _DMA_V2_ELEM_CROPPING_B_PARAM 5 +#define _DMA_V2_WIDTH_B_PARAM 6 +#define _DMA_V2_HEIGHT_PARAM 7 +#define _DMA_V2_QUEUED_CMDS 8 + +/* Parameter Constants */ +#define _DMA_V2_ZERO_EXTEND 0 +#define _DMA_V2_SIGN_EXTEND 1 + + /* SLAVE address map */ +#define _DMA_V2_SEL_FSM_CMD 0 +#define _DMA_V2_SEL_CH_REG 1 +#define _DMA_V2_SEL_CONN_GROUP 2 +#define _DMA_V2_SEL_DEV_INTERF 3 + +#define _DMA_V2_ADDR_SEL_COMP_IDX 12 +#define _DMA_V2_ADDR_SEL_COMP_BITS 4 +#define _DMA_V2_ADDR_SEL_CH_REG_IDX 2 +#define _DMA_V2_ADDR_SEL_CH_REG_BITS 6 +#define _DMA_V2_ADDR_SEL_PARAM_IDX (_DMA_V2_ADDR_SEL_CH_REG_BITS+_DMA_V2_ADDR_SEL_CH_REG_IDX) +#define _DMA_V2_ADDR_SEL_PARAM_BITS 4 + +#define _DMA_V2_ADDR_SEL_GROUP_COMP_IDX 2 +#define _DMA_V2_ADDR_SEL_GROUP_COMP_BITS 6 +#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_IDX (_DMA_V2_ADDR_SEL_GROUP_COMP_BITS + _DMA_V2_ADDR_SEL_GROUP_COMP_IDX) +#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_BITS 4 + +#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX 2 +#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS 6 +#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX+_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS) +#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS 4 + +#define _DMA_V2_FSM_GROUP_CMD_IDX 0 +#define _DMA_V2_FSM_GROUP_ADDR_SRC_IDX 1 +#define _DMA_V2_FSM_GROUP_ADDR_DEST_IDX 2 +#define _DMA_V2_FSM_GROUP_CMD_CTRL_IDX 3 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_IDX 4 +#define _DMA_V2_FSM_GROUP_FSM_PACK_IDX 5 +#define _DMA_V2_FSM_GROUP_FSM_REQ_IDX 6 +#define _DMA_V2_FSM_GROUP_FSM_WR_IDX 7 + +#define _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX 0 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX 1 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX 2 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX 3 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_XB_IDX 4 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_YB_IDX 5 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX 6 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX 7 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX 8 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX 9 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX 10 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX 11 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX 12 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX 13 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX 14 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX 15 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_CMD_CTRL_IDX 15 + +#define _DMA_V2_FSM_GROUP_FSM_PACK_STATE_IDX 0 +#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_YB_IDX 1 +#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX 2 +#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX 3 + +#define _DMA_V2_FSM_GROUP_FSM_REQ_STATE_IDX 0 +#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_YB_IDX 1 +#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_XB_IDX 2 +#define _DMA_V2_FSM_GROUP_FSM_REQ_XB_REMAINING_IDX 3 +#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_BURST_IDX 4 + +#define _DMA_V2_FSM_GROUP_FSM_WR_STATE_IDX 0 +#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_YB_IDX 1 +#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_XB_IDX 2 +#define _DMA_V2_FSM_GROUP_FSM_WR_XB_REMAINING_IDX 3 +#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_BURST_IDX 4 + +#define _DMA_V2_DEV_INTERF_REQ_SIDE_STATUS_IDX 0 +#define _DMA_V2_DEV_INTERF_SEND_SIDE_STATUS_IDX 1 +#define _DMA_V2_DEV_INTERF_FIFO_STATUS_IDX 2 +#define _DMA_V2_DEV_INTERF_REQ_ONLY_COMPLETE_BURST_IDX 3 +#define _DMA_V2_DEV_INTERF_MAX_BURST_IDX 4 +#define _DMA_V2_DEV_INTERF_CHK_ADDR_ALIGN 5 + +#endif /* _dma_v2_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/gdc_v2_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/gdc_v2_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..77722d20570108c94c8258640f679564ef0e40dc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/gdc_v2_defs.h @@ -0,0 +1,170 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef HRT_GDC_v2_defs_h_ +#define HRT_GDC_v2_defs_h_ + +#define HRT_GDC_IS_V2 + +#define HRT_GDC_N 1024 /* Top-level design constant, equal to the number of entries in the LUT */ +#define HRT_GDC_FRAC_BITS 10 /* Number of fractional bits in the GDC block, driven by the size of the LUT */ + +#define HRT_GDC_BLI_FRAC_BITS 4 /* Number of fractional bits for the bi-linear interpolation type */ +#define HRT_GDC_BLI_COEF_ONE (1 << HRT_GDC_BLI_FRAC_BITS) + +#define HRT_GDC_BCI_COEF_BITS 14 /* 14 bits per coefficient */ +#define HRT_GDC_BCI_COEF_ONE (1 << (HRT_GDC_BCI_COEF_BITS-2)) /* We represent signed 10 bit coefficients. */ + /* The supported range is [-256, .., +256] */ + /* in 14-bit signed notation, */ + /* We need all ten bits (MSB must be zero). */ + /* -s is inserted to solve this issue, and */ + /* therefore "1" is equal to +256. */ +#define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1) + +#define HRT_GDC_LUT_BYTES (HRT_GDC_N*4*2) /* 1024 addresses, 4 coefficients per address, */ + /* 2 bytes per coefficient */ + +#define _HRT_GDC_REG_ALIGN 4 + + // 31 30 29 25 24 0 + // |-----|---|--------|------------------------| + // | CMD | C | Reg_ID | Value | + + + // There are just two commands possible for the GDC block: + // 1 - Configure reg + // 0 - Data token + + // C - Reserved bit + // Used in protocol to indicate whether it is C-run or other type of runs + // In case of C-run, this bit has a value of 1, for all the other runs, it is 0. + + // Reg_ID - Address of the register to be configured + + // Value - Value to store to the addressed register, maximum of 24 bits + + // Configure reg command is not followed by any other token. + // The address of the register and the data to be filled in is contained in the same token + + // When the first data token is received, it must be: + // 1. FRX and FRY (device configured in one of the scaling modes) ***DEFAULT MODE***, or, + // 2. P0'X (device configured in one of the tetragon modes) + // After the first data token is received, pre-defined number of tokens with the following meaning follow: + // 1. two tokens: SRC address ; DST address + // 2. nine tokens: P0'Y, .., P3'Y ; SRC address ; DST address + +#define HRT_GDC_CONFIG_CMD 1 +#define HRT_GDC_DATA_CMD 0 + + +#define HRT_GDC_CMD_POS 31 +#define HRT_GDC_CMD_BITS 1 +#define HRT_GDC_CRUN_POS 30 +#define HRT_GDC_REG_ID_POS 25 +#define HRT_GDC_REG_ID_BITS 5 +#define HRT_GDC_DATA_POS 0 +#define HRT_GDC_DATA_BITS 25 + +#define HRT_GDC_FRYIPXFRX_BITS 26 +#define HRT_GDC_P0X_BITS 23 + + +#define HRT_GDC_MAX_OXDIM (8192-64) +#define HRT_GDC_MAX_OYDIM 4095 +#define HRT_GDC_MAX_IXDIM (8192-64) +#define HRT_GDC_MAX_IYDIM 4095 +#define HRT_GDC_MAX_DS_FAC 16 +#define HRT_GDC_MAX_DX (HRT_GDC_MAX_DS_FAC*HRT_GDC_N - 1) +#define HRT_GDC_MAX_DY HRT_GDC_MAX_DX + + +/* GDC lookup tables entries are 10 bits values, but they're + stored 2 by 2 as 32 bit values, yielding 16 bits per entry. + A GDC lookup table contains 64 * 4 elements */ + +#define HRT_GDC_PERF_1_1_pix 0 +#define HRT_GDC_PERF_2_1_pix 1 +#define HRT_GDC_PERF_1_2_pix 2 +#define HRT_GDC_PERF_2_2_pix 3 + +#define HRT_GDC_NND_MODE 0 +#define HRT_GDC_BLI_MODE 1 +#define HRT_GDC_BCI_MODE 2 +#define HRT_GDC_LUT_MODE 3 + +#define HRT_GDC_SCAN_STB 0 +#define HRT_GDC_SCAN_STR 1 + +#define HRT_GDC_MODE_SCALING 0 +#define HRT_GDC_MODE_TETRAGON 1 + +#define HRT_GDC_LUT_COEFF_OFFSET 16 +#define HRT_GDC_FRY_BIT_OFFSET 16 +// FRYIPXFRX is the only register where we store two values in one field, +// to save one token in the scaling protocol. +// Like this, we have three tokens in the scaling protocol, +// Otherwise, we would have had four. +// The register bit-map is: +// 31 26 25 16 15 10 9 0 +// |------|----------|------|----------| +// | XXXX | FRY | IPX | FRX | + + +#define HRT_GDC_CE_FSM0_POS 0 +#define HRT_GDC_CE_FSM0_LEN 2 +#define HRT_GDC_CE_OPY_POS 2 +#define HRT_GDC_CE_OPY_LEN 14 +#define HRT_GDC_CE_OPX_POS 16 +#define HRT_GDC_CE_OPX_LEN 16 +// CHK_ENGINE register bit-map: +// 31 16 15 2 1 0 +// |----------------|-----------|----| +// | OPX | OPY |FSM0| +// However, for the time being at least, +// this implementation is meaningless in hss model, +// So, we just return 0 + + +#define HRT_GDC_CHK_ENGINE_IDX 0 +#define HRT_GDC_WOIX_IDX 1 +#define HRT_GDC_WOIY_IDX 2 +#define HRT_GDC_BPP_IDX 3 +#define HRT_GDC_FRYIPXFRX_IDX 4 +#define HRT_GDC_OXDIM_IDX 5 +#define HRT_GDC_OYDIM_IDX 6 +#define HRT_GDC_SRC_ADDR_IDX 7 +#define HRT_GDC_SRC_END_ADDR_IDX 8 +#define HRT_GDC_SRC_WRAP_ADDR_IDX 9 +#define HRT_GDC_SRC_STRIDE_IDX 10 +#define HRT_GDC_DST_ADDR_IDX 11 +#define HRT_GDC_DST_STRIDE_IDX 12 +#define HRT_GDC_DX_IDX 13 +#define HRT_GDC_DY_IDX 14 +#define HRT_GDC_P0X_IDX 15 +#define HRT_GDC_P0Y_IDX 16 +#define HRT_GDC_P1X_IDX 17 +#define HRT_GDC_P1Y_IDX 18 +#define HRT_GDC_P2X_IDX 19 +#define HRT_GDC_P2Y_IDX 20 +#define HRT_GDC_P3X_IDX 21 +#define HRT_GDC_P3Y_IDX 22 +#define HRT_GDC_PERF_POINT_IDX 23 // 1x1 ; 1x2 ; 2x1 ; 2x2 pixels per cc +#define HRT_GDC_INTERP_TYPE_IDX 24 // NND ; BLI ; BCI ; LUT +#define HRT_GDC_SCAN_IDX 25 // 0 = STB (Slide To Bottom) ; 1 = STR (Slide To Right) +#define HRT_GDC_PROC_MODE_IDX 26 // 0 = Scaling ; 1 = Tetragon + +#define HRT_GDC_LUT_IDX 32 + + +#endif /* HRT_GDC_v2_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/gp_regs_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/gp_regs_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..34e734f6648eb0ef6297cab46f912c933466310f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/gp_regs_defs.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _gp_regs_defs_h +#define _gp_regs_defs_h + +#define _HRT_GP_REGS_IS_FWD_REG_IDX 0 + +#define _HRT_GP_REGS_REG_ALIGN 4 + +#endif /* _gp_regs_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/gp_timer_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/gp_timer_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..3082e2f5e014117ccd1548cceae21fd5eb2bd430 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/gp_timer_defs.h @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _gp_timer_defs_h +#define _gp_timer_defs_h + +#define _HRT_GP_TIMER_REG_ALIGN 4 + +#define HIVE_GP_TIMER_RESET_REG_IDX 0 +#define HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX 1 +#define HIVE_GP_TIMER_ENABLE_REG_IDX(timer) (HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX + 1 + timer) +#define HIVE_GP_TIMER_VALUE_REG_IDX(timer,timers) (HIVE_GP_TIMER_ENABLE_REG_IDX(timers) + timer) +#define HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer,timers) (HIVE_GP_TIMER_VALUE_REG_IDX(timers, timers) + timer) +#define HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer,timers) (HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timers, timers) + timer) +#define HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq,timers) (HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timers, timers) + irq) +#define HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq,timers,irqs) (HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irqs, timers) + irq) +#define HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq,timers,irqs) (HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irqs, timers, irqs) + irq) + +#define HIVE_GP_TIMER_COUNT_TYPE_HIGH 0 +#define HIVE_GP_TIMER_COUNT_TYPE_LOW 1 +#define HIVE_GP_TIMER_COUNT_TYPE_POSEDGE 2 +#define HIVE_GP_TIMER_COUNT_TYPE_NEGEDGE 3 +#define HIVE_GP_TIMER_COUNT_TYPES 4 + +#endif /* _gp_timer_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/gpio_block_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/gpio_block_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..a807d4c990414af50c61c4e20075d385db25862f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/gpio_block_defs.h @@ -0,0 +1,42 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _gpio_block_defs_h_ +#define _gpio_block_defs_h_ + +#define _HRT_GPIO_BLOCK_REG_ALIGN 4 + +/* R/W registers */ +#define _gpio_block_reg_do_e 0 +#define _gpio_block_reg_do_select 1 +#define _gpio_block_reg_do_0 2 +#define _gpio_block_reg_do_1 3 +#define _gpio_block_reg_do_pwm_cnt_0 4 +#define _gpio_block_reg_do_pwm_cnt_1 5 +#define _gpio_block_reg_do_pwm_cnt_2 6 +#define _gpio_block_reg_do_pwm_cnt_3 7 +#define _gpio_block_reg_do_pwm_main_cnt 8 +#define _gpio_block_reg_do_pwm_enable 9 +#define _gpio_block_reg_di_debounce_sel 10 +#define _gpio_block_reg_di_debounce_cnt_0 11 +#define _gpio_block_reg_di_debounce_cnt_1 12 +#define _gpio_block_reg_di_debounce_cnt_2 13 +#define _gpio_block_reg_di_debounce_cnt_3 14 +#define _gpio_block_reg_di_active_level 15 + + +/* read-only registers */ +#define _gpio_block_reg_di 16 + +#endif /* _gpio_block_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/hive_isp_css_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/hive_isp_css_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..39584996092e5d76e5c3da100d87189f7b8c941b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/hive_isp_css_defs.h @@ -0,0 +1,416 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _hive_isp_css_defs_h__ +#define _hive_isp_css_defs_h__ + +#define HIVE_ISP_CSS_IS_2400B0_SYSTEM + +#define HIVE_ISP_CTRL_DATA_WIDTH 32 +#define HIVE_ISP_CTRL_ADDRESS_WIDTH 32 +#define HIVE_ISP_CTRL_MAX_BURST_SIZE 1 +#define HIVE_ISP_DDR_ADDRESS_WIDTH 36 + +#define HIVE_ISP_HOST_MAX_BURST_SIZE 8 /* host supports bursts in order to prevent repeating DDRAM accesses */ +#define HIVE_ISP_NUM_GPIO_PINS 12 + +/* This list of vector num_elems/elem_bits pairs is valid both in C as initializer + and in the DMA parameter list */ +#define HIVE_ISP_DDR_DMA_SPECS {{32, 8}, {16, 16}, {18, 14}, {25, 10}, {21, 12}} +#define HIVE_ISP_DDR_WORD_BITS 256 +#define HIVE_ISP_DDR_WORD_BYTES (HIVE_ISP_DDR_WORD_BITS/8) +#define HIVE_ISP_DDR_BYTES (512 * 1024 * 1024) /* hss only */ +#define HIVE_ISP_DDR_BYTES_RTL (127 * 1024 * 1024) /* RTL only */ +#define HIVE_ISP_DDR_SMALL_BYTES (128 * 256 / 8) +#define HIVE_ISP_PAGE_SHIFT 12 +#define HIVE_ISP_PAGE_SIZE (1<_defs.h + */ +typedef enum hrt_isp_css_irq { + hrt_isp_css_irq_gpio_pin_0 = HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID , + hrt_isp_css_irq_gpio_pin_1 = HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID , + hrt_isp_css_irq_gpio_pin_2 = HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID , + hrt_isp_css_irq_gpio_pin_3 = HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID , + hrt_isp_css_irq_gpio_pin_4 = HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID , + hrt_isp_css_irq_gpio_pin_5 = HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID , + hrt_isp_css_irq_gpio_pin_6 = HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID , + hrt_isp_css_irq_gpio_pin_7 = HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID , + hrt_isp_css_irq_gpio_pin_8 = HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID , + hrt_isp_css_irq_gpio_pin_9 = HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID , + hrt_isp_css_irq_gpio_pin_10 = HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID , + hrt_isp_css_irq_gpio_pin_11 = HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID , + hrt_isp_css_irq_sp = HIVE_GP_DEV_IRQ_SP_BIT_ID , + hrt_isp_css_irq_isp = HIVE_GP_DEV_IRQ_ISP_BIT_ID , + hrt_isp_css_irq_isys = HIVE_GP_DEV_IRQ_ISYS_BIT_ID , + hrt_isp_css_irq_isel = HIVE_GP_DEV_IRQ_ISEL_BIT_ID , + hrt_isp_css_irq_ifmt = HIVE_GP_DEV_IRQ_IFMT_BIT_ID , + hrt_isp_css_irq_sp_stream_mon = HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID , + hrt_isp_css_irq_isp_stream_mon = HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID , + hrt_isp_css_irq_mod_stream_mon = HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID , +#ifdef _HIVE_ISP_CSS_2401_SYSTEM + hrt_isp_css_irq_is2401 = HIVE_GP_DEV_IRQ_IS2401_BIT_ID , +#else + hrt_isp_css_irq_isp_pmem_error = HIVE_GP_DEV_IRQ_ISP_PMEM_ERROR_BIT_ID , +#endif + hrt_isp_css_irq_isp_bamem_error = HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID , + hrt_isp_css_irq_isp_dmem_error = HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID , + hrt_isp_css_irq_sp_icache_mem_error = HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID , + hrt_isp_css_irq_sp_dmem_error = HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID , + hrt_isp_css_irq_mmu_cache_mem_error = HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID , + hrt_isp_css_irq_gp_timer_0 = HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID , + hrt_isp_css_irq_gp_timer_1 = HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID , + hrt_isp_css_irq_sw_pin_0 = HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID , + hrt_isp_css_irq_sw_pin_1 = HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID , + hrt_isp_css_irq_dma = HIVE_GP_DEV_IRQ_DMA_BIT_ID , + hrt_isp_css_irq_sp_stream_mon_b = HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID , + /* this must (obviously) be the last on in the enum */ + hrt_isp_css_irq_num_irqs +} hrt_isp_css_irq_t; + +typedef enum hrt_isp_css_irq_status { + hrt_isp_css_irq_status_error, + hrt_isp_css_irq_status_more_irqs, + hrt_isp_css_irq_status_success +} hrt_isp_css_irq_status_t; + +#endif /* _HIVE_ISP_CSS_IRQ_TYPES_HRT_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/hive_isp_css_streaming_to_mipi_types_hrt.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/hive_isp_css_streaming_to_mipi_types_hrt.h new file mode 100644 index 0000000000000000000000000000000000000000..b4211a0c631a2b150ee025de86841f3aa1bac062 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/hive_isp_css_streaming_to_mipi_types_hrt.h @@ -0,0 +1,26 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _hive_isp_css_streaming_to_mipi_types_hrt_h_ +#define _hive_isp_css_streaming_to_mipi_types_hrt_h_ + +#include + +#define _HIVE_ISP_CH_ID_MASK ((1U << HIVE_ISP_CH_ID_BITS)-1) +#define _HIVE_ISP_FMT_TYPE_MASK ((1U << HIVE_ISP_FMT_TYPE_BITS)-1) + +#define _HIVE_STR_TO_MIPI_FMT_TYPE_LSB (HIVE_STR_TO_MIPI_CH_ID_LSB + HIVE_ISP_CH_ID_BITS) +#define _HIVE_STR_TO_MIPI_DATA_B_LSB (HIVE_STR_TO_MIPI_DATA_A_LSB + HIVE_IF_PIXEL_WIDTH) + +#endif /* _hive_isp_css_streaming_to_mipi_types_hrt_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/hive_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/hive_types.h new file mode 100644 index 0000000000000000000000000000000000000000..58b0e6effbd068fe9f2d175072bb1e66c921428a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/hive_types.h @@ -0,0 +1,128 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HRT_HIVE_TYPES_H +#define _HRT_HIVE_TYPES_H + +#include "version.h" +#include "defs.h" + +#ifndef HRTCAT3 +#define _HRTCAT3(m,n,o) m##n##o +#define HRTCAT3(m,n,o) _HRTCAT3(m,n,o) +#endif + +#ifndef HRTCAT4 +#define _HRTCAT4(m,n,o,p) m##n##o##p +#define HRTCAT4(m,n,o,p) _HRTCAT4(m,n,o,p) +#endif + +#ifndef HRTMIN +#define HRTMIN(a,b) (((a)<(b))?(a):(b)) +#endif + +#ifndef HRTMAX +#define HRTMAX(a,b) (((a)>(b))?(a):(b)) +#endif + +/* boolean data type */ +typedef unsigned int hive_bool; +#define hive_false 0 +#define hive_true 1 + +typedef char hive_int8; +typedef short hive_int16; +typedef int hive_int32; +typedef long long hive_int64; + +typedef unsigned char hive_uint8; +typedef unsigned short hive_uint16; +typedef unsigned int hive_uint32; +typedef unsigned long long hive_uint64; + +/* by default assume 32 bit master port (both data and address) */ +#ifndef HRT_DATA_WIDTH +#define HRT_DATA_WIDTH 32 +#endif +#ifndef HRT_ADDRESS_WIDTH +#define HRT_ADDRESS_WIDTH 32 +#endif + +#define HRT_DATA_BYTES (HRT_DATA_WIDTH/8) +#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH/8) + +#if HRT_DATA_WIDTH == 64 +typedef hive_uint64 hrt_data; +#elif HRT_DATA_WIDTH == 32 +typedef hive_uint32 hrt_data; +#else +#error data width not supported +#endif + +#if HRT_ADDRESS_WIDTH == 64 +typedef hive_uint64 hrt_address; +#elif HRT_ADDRESS_WIDTH == 32 +typedef hive_uint32 hrt_address; +#else +#error adddres width not supported +#endif + +/* The SP side representation of an HMM virtual address */ +typedef hive_uint32 hrt_vaddress; + +/* use 64 bit addresses in simulation, where possible */ +typedef hive_uint64 hive_sim_address; + +/* below is for csim, not for hrt, rename and move this elsewhere */ + +typedef unsigned int hive_uint; +typedef hive_uint32 hive_address; +typedef hive_address hive_slave_address; +typedef hive_address hive_mem_address; + +/* MMIO devices */ +typedef hive_uint hive_mmio_id; +typedef hive_mmio_id hive_slave_id; +typedef hive_mmio_id hive_port_id; +typedef hive_mmio_id hive_master_id; +typedef hive_mmio_id hive_mem_id; +typedef hive_mmio_id hive_dev_id; +typedef hive_mmio_id hive_fifo_id; + +typedef hive_uint hive_hier_id; +typedef hive_hier_id hive_device_id; +typedef hive_device_id hive_proc_id; +typedef hive_device_id hive_cell_id; +typedef hive_device_id hive_host_id; +typedef hive_device_id hive_bus_id; +typedef hive_device_id hive_bridge_id; +typedef hive_device_id hive_fifo_adapter_id; +typedef hive_device_id hive_custom_device_id; + +typedef hive_uint hive_slot_id; +typedef hive_uint hive_fu_id; +typedef hive_uint hive_reg_file_id; +typedef hive_uint hive_reg_id; + +/* Streaming devices */ +typedef hive_uint hive_outport_id; +typedef hive_uint hive_inport_id; + +typedef hive_uint hive_msink_id; + +/* HRT specific */ +typedef char* hive_program; +typedef char* hive_function; + +#endif /* _HRT_HIVE_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/if_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/if_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..7d39e45796ae17965aee2ef1fb61f0d76a03b88f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/if_defs.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IF_DEFS_H +#define _IF_DEFS_H + +#define HIVE_IF_FRAME_REQUEST 0xA000 +#define HIVE_IF_LINES_REQUEST 0xB000 +#define HIVE_IF_VECTORS_REQUEST 0xC000 + +#endif /* _IF_DEFS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/input_formatter_subsystem_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/input_formatter_subsystem_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..16bfe1d80bc96a1f0c25f7d818db5d1dfff5003b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/input_formatter_subsystem_defs.h @@ -0,0 +1,53 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _if_subsystem_defs_h +#define _if_subsystem_defs_h__ + +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0 0 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_1 1 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_2 2 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_3 3 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_4 4 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_5 5 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_6 6 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_7 7 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_FSYNC_LUT_REG 8 +#define HIVE_IFMT_GP_REGS_SRST_IDX 9 +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IDX 10 + +#define HIVE_IFMT_GP_REGS_CH_ID_FMT_TYPE_IDX 11 + +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_BASE HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0 + +/* order of the input bits for the ifmt irq controller */ +#define HIVE_IFMT_IRQ_IFT_PRIM_BIT_ID 0 +#define HIVE_IFMT_IRQ_IFT_PRIM_B_BIT_ID 1 +#define HIVE_IFMT_IRQ_IFT_SEC_BIT_ID 2 +#define HIVE_IFMT_IRQ_MEM_CPY_BIT_ID 3 +#define HIVE_IFMT_IRQ_SIDEBAND_CHANGED_BIT_ID 4 + +/* order of the input bits for the ifmt Soft reset register */ +#define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_BIT_IDX 0 +#define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_B_BIT_IDX 1 +#define HIVE_IFMT_GP_REGS_SRST_IFT_SEC_BIT_IDX 2 +#define HIVE_IFMT_GP_REGS_SRST_MEM_CPY_BIT_IDX 3 + +/* order of the input bits for the ifmt Soft reset register */ +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_BIT_IDX 0 +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_B_BIT_IDX 1 +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_SEC_BIT_IDX 2 +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_MEM_CPY_BIT_IDX 3 + +#endif /* _if_subsystem_defs_h__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/input_selector_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/input_selector_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..87fbf82edb5bc44d6c5ca761c06aa57a8606fc97 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/input_selector_defs.h @@ -0,0 +1,89 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _input_selector_defs_h +#define _input_selector_defs_h + +#ifndef HIVE_ISP_ISEL_SEL_BITS +#define HIVE_ISP_ISEL_SEL_BITS 2 +#endif + +#ifndef HIVE_ISP_CH_ID_BITS +#define HIVE_ISP_CH_ID_BITS 2 +#endif + +#ifndef HIVE_ISP_FMT_TYPE_BITS +#define HIVE_ISP_FMT_TYPE_BITS 5 +#endif + +/* gp_register register id's -- Outputs */ +#define HIVE_ISEL_GP_REGS_SYNCGEN_ENABLE_IDX 0 +#define HIVE_ISEL_GP_REGS_SYNCGEN_FREE_RUNNING_IDX 1 +#define HIVE_ISEL_GP_REGS_SYNCGEN_PAUSE_IDX 2 +#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_FRAMES_IDX 3 +#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_PIX_IDX 4 +#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_LINES_IDX 5 +#define HIVE_ISEL_GP_REGS_SYNCGEN_HBLANK_CYCLES_IDX 6 +#define HIVE_ISEL_GP_REGS_SYNCGEN_VBLANK_CYCLES_IDX 7 + +#define HIVE_ISEL_GP_REGS_SOF_IDX 8 +#define HIVE_ISEL_GP_REGS_EOF_IDX 9 +#define HIVE_ISEL_GP_REGS_SOL_IDX 10 +#define HIVE_ISEL_GP_REGS_EOL_IDX 11 + +#define HIVE_ISEL_GP_REGS_PRBS_ENABLE 12 +#define HIVE_ISEL_GP_REGS_PRBS_ENABLE_PORT_B 13 +#define HIVE_ISEL_GP_REGS_PRBS_LFSR_RESET_VALUE 14 + +#define HIVE_ISEL_GP_REGS_TPG_ENABLE 15 +#define HIVE_ISEL_GP_REGS_TPG_ENABLE_PORT_B 16 +#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_MASK_IDX 17 +#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_MASK_IDX 18 +#define HIVE_ISEL_GP_REGS_TPG_XY_CNT_MASK_IDX 19 +#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_DELTA_IDX 20 +#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_DELTA_IDX 21 +#define HIVE_ISEL_GP_REGS_TPG_MODE_IDX 22 +#define HIVE_ISEL_GP_REGS_TPG_R1_IDX 23 +#define HIVE_ISEL_GP_REGS_TPG_G1_IDX 24 +#define HIVE_ISEL_GP_REGS_TPG_B1_IDX 25 +#define HIVE_ISEL_GP_REGS_TPG_R2_IDX 26 +#define HIVE_ISEL_GP_REGS_TPG_G2_IDX 27 +#define HIVE_ISEL_GP_REGS_TPG_B2_IDX 28 + + +#define HIVE_ISEL_GP_REGS_CH_ID_IDX 29 +#define HIVE_ISEL_GP_REGS_FMT_TYPE_IDX 30 +#define HIVE_ISEL_GP_REGS_DATA_SEL_IDX 31 +#define HIVE_ISEL_GP_REGS_SBAND_SEL_IDX 32 +#define HIVE_ISEL_GP_REGS_SYNC_SEL_IDX 33 +#define HIVE_ISEL_GP_REGS_SRST_IDX 37 + +#define HIVE_ISEL_GP_REGS_SRST_SYNCGEN_BIT 0 +#define HIVE_ISEL_GP_REGS_SRST_PRBS_BIT 1 +#define HIVE_ISEL_GP_REGS_SRST_TPG_BIT 2 +#define HIVE_ISEL_GP_REGS_SRST_FIFO_BIT 3 + +/* gp_register register id's -- Inputs */ +#define HIVE_ISEL_GP_REGS_SYNCGEN_HOR_CNT_IDX 34 +#define HIVE_ISEL_GP_REGS_SYNCGEN_VER_CNT_IDX 35 +#define HIVE_ISEL_GP_REGS_SYNCGEN_FRAMES_CNT_IDX 36 + +/* irq sources isel irq controller */ +#define HIVE_ISEL_IRQ_SYNC_GEN_SOF_BIT_ID 0 +#define HIVE_ISEL_IRQ_SYNC_GEN_EOF_BIT_ID 1 +#define HIVE_ISEL_IRQ_SYNC_GEN_SOL_BIT_ID 2 +#define HIVE_ISEL_IRQ_SYNC_GEN_EOL_BIT_ID 3 +#define HIVE_ISEL_IRQ_NUM_IRQS 4 + +#endif /* _input_selector_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/input_switch_2400_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/input_switch_2400_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..20a13c4cdb562fc8773992317d0b9b4a06a149cb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/input_switch_2400_defs.h @@ -0,0 +1,30 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _input_switch_2400_defs_h +#define _input_switch_2400_defs_h + +#define _HIVE_INPUT_SWITCH_GET_LUT_REG_ID(ch_id, fmt_type) (((ch_id)*2) + ((fmt_type)>=16)) +#define _HIVE_INPUT_SWITCH_GET_LUT_REG_LSB(fmt_type) (((fmt_type)%16) * 2) + +#define HIVE_INPUT_SWITCH_SELECT_NO_OUTPUT 0 +#define HIVE_INPUT_SWITCH_SELECT_IF_PRIM 1 +#define HIVE_INPUT_SWITCH_SELECT_IF_SEC 2 +#define HIVE_INPUT_SWITCH_SELECT_STR_TO_MEM 3 +#define HIVE_INPUT_SWITCH_VSELECT_NO_OUTPUT 0 +#define HIVE_INPUT_SWITCH_VSELECT_IF_PRIM 1 +#define HIVE_INPUT_SWITCH_VSELECT_IF_SEC 2 +#define HIVE_INPUT_SWITCH_VSELECT_STR_TO_MEM 4 + +#endif /* _input_switch_2400_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/input_system_ctrl_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/input_system_ctrl_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..a7f0ca80bc9be0afed16a0726fdd068946aef12a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/input_system_ctrl_defs.h @@ -0,0 +1,254 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _input_system_ctrl_defs_h +#define _input_system_ctrl_defs_h + +#define _INPUT_SYSTEM_CTRL_REG_ALIGN 4 /* assuming 32 bit control bus width */ + +/* --------------------------------------------------*/ + +/* --------------------------------------------------*/ +/* REGISTER INFO */ +/* --------------------------------------------------*/ + +// Number of registers +#define ISYS_CTRL_NOF_REGS 23 + +// Register id's of MMIO slave accesible registers +#define ISYS_CTRL_CAPT_START_ADDR_A_REG_ID 0 +#define ISYS_CTRL_CAPT_START_ADDR_B_REG_ID 1 +#define ISYS_CTRL_CAPT_START_ADDR_C_REG_ID 2 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID 3 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID 4 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID 5 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID 6 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID 7 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID 8 +#define ISYS_CTRL_ACQ_START_ADDR_REG_ID 9 +#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID 10 +#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID 11 +#define ISYS_CTRL_INIT_REG_ID 12 +#define ISYS_CTRL_LAST_COMMAND_REG_ID 13 +#define ISYS_CTRL_NEXT_COMMAND_REG_ID 14 +#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_ID 15 +#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_ID 16 +#define ISYS_CTRL_FSM_STATE_INFO_REG_ID 17 +#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_ID 18 +#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_ID 19 +#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID 20 +#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID 21 +#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID 22 + + +/* register reset value */ +#define ISYS_CTRL_CAPT_START_ADDR_A_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_START_ADDR_B_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_START_ADDR_C_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_RSTVAL 128 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_RSTVAL 128 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_RSTVAL 128 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL 3 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL 3 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL 3 +#define ISYS_CTRL_ACQ_START_ADDR_REG_RSTVAL 0 +#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL 128 +#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3 +#define ISYS_CTRL_INIT_REG_RSTVAL 0 +#define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) +#define ISYS_CTRL_NEXT_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) +#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) +#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) +#define ISYS_CTRL_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_RSTVAL 0 + +/* register width value */ +#define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH 9 +#define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH 9 +#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH 9 +#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH 9 +#define ISYS_CTRL_INIT_REG_WIDTH 3 +#define ISYS_CTRL_LAST_COMMAND_REG_WIDTH 32 /* slave data width */ +#define ISYS_CTRL_NEXT_COMMAND_REG_WIDTH 32 +#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_WIDTH 32 +#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_WIDTH 32 +#define ISYS_CTRL_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_WIDTH 1 + +/* bit definitions */ + +/* --------------------------------------------------*/ +/* TOKEN INFO */ +/* --------------------------------------------------*/ + +/* +InpSysCaptFramesAcq 1/0 [3:0] - 'b0000 +[7:4] - CaptPortId, + CaptA-'b0000 + CaptB-'b0001 + CaptC-'b0010 +[31:16] - NOF_frames +InpSysCaptFrameExt 2/0 [3:0] - 'b0001' +[7:4] - CaptPortId, + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + + 2/1 [31:0] - external capture address +InpSysAcqFrame 2/0 [3:0] - 'b0010, +[31:4] - NOF_ext_mem_words + 2/1 [31:0] - external memory read start address +InpSysOverruleON 1/0 [3:0] - 'b0011, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + +InpSysOverruleOFF 1/0 [3:0] - 'b0100, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + +InpSysOverruleCmd 2/0 [3:0] - 'b0101, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + + 2/1 [31:0] - command token value for port opid + + +acknowledge tokens: + +InpSysAckCFA 1/0 [3:0] - 'b0000 + [7:4] - CaptPortId, + CaptA-'b0000 + CaptB- 'b0001 + CaptC-'b0010 + [31:16] - NOF_frames +InpSysAckCFE 1/0 [3:0] - 'b0001' +[7:4] - CaptPortId, + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + +InpSysAckAF 1/0 [3:0] - 'b0010 +InpSysAckOverruleON 1/0 [3:0] - 'b0011, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + +InpSysAckOverruleOFF 1/0 [3:0] - 'b0100, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + +InpSysAckOverrule 2/0 [3:0] - 'b0101, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + + 2/1 [31:0] - acknowledge token value from port opid + + + +*/ + + +/* Command and acknowledge tokens IDs */ +#define ISYS_CTRL_CAPT_FRAMES_ACQ_TOKEN_ID 0 /* 0000b */ +#define ISYS_CTRL_CAPT_FRAME_EXT_TOKEN_ID 1 /* 0001b */ +#define ISYS_CTRL_ACQ_FRAME_TOKEN_ID 2 /* 0010b */ +#define ISYS_CTRL_OVERRULE_ON_TOKEN_ID 3 /* 0011b */ +#define ISYS_CTRL_OVERRULE_OFF_TOKEN_ID 4 /* 0100b */ +#define ISYS_CTRL_OVERRULE_TOKEN_ID 5 /* 0101b */ + +#define ISYS_CTRL_ACK_CFA_TOKEN_ID 0 +#define ISYS_CTRL_ACK_CFE_TOKEN_ID 1 +#define ISYS_CTRL_ACK_AF_TOKEN_ID 2 +#define ISYS_CTRL_ACK_OVERRULE_ON_TOKEN_ID 3 +#define ISYS_CTRL_ACK_OVERRULE_OFF_TOKEN_ID 4 +#define ISYS_CTRL_ACK_OVERRULE_TOKEN_ID 5 +#define ISYS_CTRL_ACK_DEVICE_ERROR_TOKEN_ID 6 + +#define ISYS_CTRL_TOKEN_ID_MSB 3 +#define ISYS_CTRL_TOKEN_ID_LSB 0 +#define ISYS_CTRL_PORT_ID_TOKEN_MSB 7 +#define ISYS_CTRL_PORT_ID_TOKEN_LSB 4 +#define ISYS_CTRL_NOF_CAPT_TOKEN_MSB 31 +#define ISYS_CTRL_NOF_CAPT_TOKEN_LSB 16 +#define ISYS_CTRL_NOF_EXT_TOKEN_MSB 31 +#define ISYS_CTRL_NOF_EXT_TOKEN_LSB 8 + +#define ISYS_CTRL_TOKEN_ID_IDX 0 +#define ISYS_CTRL_TOKEN_ID_BITS (ISYS_CTRL_TOKEN_ID_MSB - ISYS_CTRL_TOKEN_ID_LSB + 1) +#define ISYS_CTRL_PORT_ID_IDX (ISYS_CTRL_TOKEN_ID_IDX + ISYS_CTRL_TOKEN_ID_BITS) +#define ISYS_CTRL_PORT_ID_BITS (ISYS_CTRL_PORT_ID_TOKEN_MSB - ISYS_CTRL_PORT_ID_TOKEN_LSB +1) +#define ISYS_CTRL_NOF_CAPT_IDX ISYS_CTRL_NOF_CAPT_TOKEN_LSB +#define ISYS_CTRL_NOF_CAPT_BITS (ISYS_CTRL_NOF_CAPT_TOKEN_MSB - ISYS_CTRL_NOF_CAPT_TOKEN_LSB + 1) +#define ISYS_CTRL_NOF_EXT_IDX ISYS_CTRL_NOF_EXT_TOKEN_LSB +#define ISYS_CTRL_NOF_EXT_BITS (ISYS_CTRL_NOF_EXT_TOKEN_MSB - ISYS_CTRL_NOF_EXT_TOKEN_LSB + 1) + +#define ISYS_CTRL_PORT_ID_CAPT_A 0 /* device ID for capture unit A */ +#define ISYS_CTRL_PORT_ID_CAPT_B 1 /* device ID for capture unit B */ +#define ISYS_CTRL_PORT_ID_CAPT_C 2 /* device ID for capture unit C */ +#define ISYS_CTRL_PORT_ID_ACQUISITION 3 /* device ID for acquistion unit */ +#define ISYS_CTRL_PORT_ID_DMA_CAPT_A 4 /* device ID for dma unit */ +#define ISYS_CTRL_PORT_ID_DMA_CAPT_B 5 /* device ID for dma unit */ +#define ISYS_CTRL_PORT_ID_DMA_CAPT_C 6 /* device ID for dma unit */ +#define ISYS_CTRL_PORT_ID_DMA_ACQ 7 /* device ID for dma unit */ + +#define ISYS_CTRL_NO_ACQ_ACK 16 /* no ack from acquisition unit */ +#define ISYS_CTRL_NO_DMA_ACK 0 +#define ISYS_CTRL_NO_CAPT_ACK 16 + +#endif /* _input_system_ctrl_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/input_system_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/input_system_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..ae62163034a66d6bae8fb55feadcb2de8cbfbddd --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/input_system_defs.h @@ -0,0 +1,126 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _input_system_defs_h +#define _input_system_defs_h + +/* csi controller modes */ +#define HIVE_CSI_CONFIG_MAIN 0 +#define HIVE_CSI_CONFIG_STEREO1 4 +#define HIVE_CSI_CONFIG_STEREO2 8 + +/* general purpose register IDs */ + +/* Stream Multicast select modes */ +#define HIVE_ISYS_GPREG_MULTICAST_A_IDX 0 +#define HIVE_ISYS_GPREG_MULTICAST_B_IDX 1 +#define HIVE_ISYS_GPREG_MULTICAST_C_IDX 2 + +/* Stream Mux select modes */ +#define HIVE_ISYS_GPREG_MUX_IDX 3 + +/* streaming monitor status and control */ +#define HIVE_ISYS_GPREG_STRMON_STAT_IDX 4 +#define HIVE_ISYS_GPREG_STRMON_COND_IDX 5 +#define HIVE_ISYS_GPREG_STRMON_IRQ_EN_IDX 6 +#define HIVE_ISYS_GPREG_SRST_IDX 7 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_IDX 8 +#define HIVE_ISYS_GPREG_REG_PORT_A_IDX 9 +#define HIVE_ISYS_GPREG_REG_PORT_B_IDX 10 + +/* Bit numbers of the soft reset register */ +#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_A_BIT 0 +#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_B_BIT 1 +#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_C_BIT 2 +#define HIVE_ISYS_GPREG_SRST_MULTICAST_A_BIT 3 +#define HIVE_ISYS_GPREG_SRST_MULTICAST_B_BIT 4 +#define HIVE_ISYS_GPREG_SRST_MULTICAST_C_BIT 5 +#define HIVE_ISYS_GPREG_SRST_CAPT_A_BIT 6 +#define HIVE_ISYS_GPREG_SRST_CAPT_B_BIT 7 +#define HIVE_ISYS_GPREG_SRST_CAPT_C_BIT 8 +#define HIVE_ISYS_GPREG_SRST_ACQ_BIT 9 +/* For ISYS_CTRL 5bits are defined to allow soft-reset per sub-controller and top-ctrl */ +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_BIT 10 /*LSB for 5bit vector */ +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_A_BIT 10 +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_B_BIT 11 +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_C_BIT 12 +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_ACQ_BIT 13 +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_TOP_BIT 14 +/* -- */ +#define HIVE_ISYS_GPREG_SRST_STR_MUX_BIT 15 +#define HIVE_ISYS_GPREG_SRST_CIO2AHB_BIT 16 +#define HIVE_ISYS_GPREG_SRST_GEN_SHORT_FIFO_BIT 17 +#define HIVE_ISYS_GPREG_SRST_WIDE_BUS_BIT 18 // includes CIO conv +#define HIVE_ISYS_GPREG_SRST_DMA_BIT 19 +#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_A_BIT 20 +#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_B_BIT 21 +#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_C_BIT 22 +#define HIVE_ISYS_GPREG_SRST_SF_CTRL_ACQ_BIT 23 +#define HIVE_ISYS_GPREG_SRST_CSI_BE_OUT_BIT 24 + +#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_A_BIT 0 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_B_BIT 1 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_C_BIT 2 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_ACQ_BIT 3 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_DMA_BIT 4 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_ISYS_CTRL_BIT 5 + +/* streaming monitor port id's */ +#define HIVE_ISYS_STR_MON_PORT_CAPA 0 +#define HIVE_ISYS_STR_MON_PORT_CAPB 1 +#define HIVE_ISYS_STR_MON_PORT_CAPC 2 +#define HIVE_ISYS_STR_MON_PORT_ACQ 3 +#define HIVE_ISYS_STR_MON_PORT_CSS_GENSH 4 +#define HIVE_ISYS_STR_MON_PORT_SF_GENSH 5 +#define HIVE_ISYS_STR_MON_PORT_SP2ISYS 6 +#define HIVE_ISYS_STR_MON_PORT_ISYS2SP 7 +#define HIVE_ISYS_STR_MON_PORT_PIXA 8 +#define HIVE_ISYS_STR_MON_PORT_PIXB 9 + +/* interrupt bit ID's */ +#define HIVE_ISYS_IRQ_CSI_SOF_BIT_ID 0 +#define HIVE_ISYS_IRQ_CSI_EOF_BIT_ID 1 +#define HIVE_ISYS_IRQ_CSI_SOL_BIT_ID 2 +#define HIVE_ISYS_IRQ_CSI_EOL_BIT_ID 3 +#define HIVE_ISYS_IRQ_CSI_RECEIVER_BIT_ID 4 +#define HIVE_ISYS_IRQ_CSI_RECEIVER_BE_BIT_ID 5 +#define HIVE_ISYS_IRQ_CAP_UNIT_A_NO_SOP 6 +#define HIVE_ISYS_IRQ_CAP_UNIT_A_LATE_SOP 7 +/*#define HIVE_ISYS_IRQ_CAP_UNIT_A_UNDEF_PH 7*/ +#define HIVE_ISYS_IRQ_CAP_UNIT_B_NO_SOP 8 +#define HIVE_ISYS_IRQ_CAP_UNIT_B_LATE_SOP 9 +/*#define HIVE_ISYS_IRQ_CAP_UNIT_B_UNDEF_PH 10*/ +#define HIVE_ISYS_IRQ_CAP_UNIT_C_NO_SOP 10 +#define HIVE_ISYS_IRQ_CAP_UNIT_C_LATE_SOP 11 +/*#define HIVE_ISYS_IRQ_CAP_UNIT_C_UNDEF_PH 13*/ +#define HIVE_ISYS_IRQ_ACQ_UNIT_SOP_MISMATCH 12 +/*#define HIVE_ISYS_IRQ_ACQ_UNIT_UNDEF_PH 15*/ +#define HIVE_ISYS_IRQ_INP_CTRL_CAPA 13 +#define HIVE_ISYS_IRQ_INP_CTRL_CAPB 14 +#define HIVE_ISYS_IRQ_INP_CTRL_CAPC 15 +#define HIVE_ISYS_IRQ_CIO2AHB 16 +#define HIVE_ISYS_IRQ_DMA_BIT_ID 17 +#define HIVE_ISYS_IRQ_STREAM_MON_BIT_ID 18 +#define HIVE_ISYS_IRQ_NUM_BITS 19 + +/* DMA */ +#define HIVE_ISYS_DMA_CHANNEL 0 +#define HIVE_ISYS_DMA_IBUF_DDR_CONN 0 +#define HIVE_ISYS_DMA_HEIGHT 1 +#define HIVE_ISYS_DMA_ELEMS 1 /* both master buses of same width */ +#define HIVE_ISYS_DMA_STRIDE 0 /* no stride required as height is fixed to 1 */ +#define HIVE_ISYS_DMA_CROP 0 /* no cropping */ +#define HIVE_ISYS_DMA_EXTENSION 0 /* no extension as elem width is same on both side */ + +#endif /* _input_system_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/irq_controller_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/irq_controller_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..ec6dd4487158e4fabf4e587684e4290ffdd23ed2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/irq_controller_defs.h @@ -0,0 +1,28 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _irq_controller_defs_h +#define _irq_controller_defs_h + +#define _HRT_IRQ_CONTROLLER_EDGE_REG_IDX 0 +#define _HRT_IRQ_CONTROLLER_MASK_REG_IDX 1 +#define _HRT_IRQ_CONTROLLER_STATUS_REG_IDX 2 +#define _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX 3 +#define _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX 4 +#define _HRT_IRQ_CONTROLLER_EDGE_NOT_PULSE_REG_IDX 5 +#define _HRT_IRQ_CONTROLLER_STR_OUT_ENABLE_REG_IDX 6 + +#define _HRT_IRQ_CONTROLLER_REG_ALIGN 4 + +#endif /* _irq_controller_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/isp2400_mamoiada_params.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/isp2400_mamoiada_params.h new file mode 100644 index 0000000000000000000000000000000000000000..c33d24114bbf3a09c08c77a9800909e0e0ce2477 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/isp2400_mamoiada_params.h @@ -0,0 +1,258 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* Version */ +#define RTL_VERSION + +/* Cell name */ +#define ISP_CELL_TYPE isp2400_mamoiada +#define ISP_VMEM simd_vmem +#define _HRT_ISP_VMEM isp2400_mamoiada_simd_vmem + +/* instruction pipeline depth */ +#define ISP_BRANCHDELAY 5 + +/* bus */ +#define ISP_BUS_WIDTH 32 +#define ISP_BUS_ADDR_WIDTH 32 +#define ISP_BUS_BURST_SIZE 1 + +/* data-path */ +#define ISP_SCALAR_WIDTH 32 +#define ISP_SLICE_NELEMS 4 +#define ISP_VEC_NELEMS 64 +#define ISP_VEC_ELEMBITS 14 +#define ISP_VEC_ELEM8BITS 16 +#define ISP_CLONE_DATAPATH_IS_16 1 + +/* memories */ +#define ISP_DMEM_DEPTH 4096 +#define ISP_DMEM_BSEL_DOWNSAMPLE 8 +#define ISP_VMEM_DEPTH 3072 +#define ISP_VMEM_BSEL_DOWNSAMPLE 8 +#define ISP_VMEM_ELEMBITS 14 +#define ISP_VMEM_ELEM_PRECISION 14 +#define ISP_VMEM_IS_BAMEM 1 +#if ISP_VMEM_IS_BAMEM + #define ISP_VMEM_BAMEM_MAX_BOI_HEIGHT 8 + #define ISP_VMEM_BAMEM_LATENCY 5 + #define ISP_VMEM_BAMEM_BANK_NARROWING_FACTOR 2 + #define ISP_VMEM_BAMEM_NR_DATA_PLANES 8 + #define ISP_VMEM_BAMEM_NR_CFG_REGISTERS 16 + #define ISP_VMEM_BAMEM_LININT 0 + #define ISP_VMEM_BAMEM_DAP_BITS 3 + #define ISP_VMEM_BAMEM_LININT_FRAC_BITS 0 + #define ISP_VMEM_BAMEM_PID_BITS 3 + #define ISP_VMEM_BAMEM_OFFSET_BITS 19 + #define ISP_VMEM_BAMEM_ADDRESS_BITS 25 + #define ISP_VMEM_BAMEM_RID_BITS 4 + #define ISP_VMEM_BAMEM_TRANSPOSITION 1 + #define ISP_VMEM_BAMEM_VEC_PLUS_SLICE 1 + #define ISP_VMEM_BAMEM_ARB_SERVICE_CYCLE_BITS 1 + #define ISP_VMEM_BAMEM_LUT_ELEMS 16 + #define ISP_VMEM_BAMEM_LUT_ADDR_WIDTH 14 + #define ISP_VMEM_BAMEM_HALF_BLOCK_WRITE 1 + #define ISP_VMEM_BAMEM_SMART_FETCH 1 + #define ISP_VMEM_BAMEM_BIG_ENDIANNESS 0 +#endif /* ISP_VMEM_IS_BAMEM */ +#define ISP_PMEM_DEPTH 2048 +#define ISP_PMEM_WIDTH 640 +#define ISP_VAMEM_ADDRESS_BITS 12 +#define ISP_VAMEM_ELEMBITS 12 +#define ISP_VAMEM_DEPTH 2048 +#define ISP_VAMEM_ALIGNMENT 2 +#define ISP_VA_ADDRESS_WIDTH 896 +#define ISP_VEC_VALSU_LATENCY ISP_VEC_NELEMS +#define ISP_HIST_ADDRESS_BITS 12 +#define ISP_HIST_ALIGNMENT 4 +#define ISP_HIST_COMP_IN_PREC 12 +#define ISP_HIST_DEPTH 1024 +#define ISP_HIST_WIDTH 24 +#define ISP_HIST_COMPONENTS 4 + +/* program counter */ +#define ISP_PC_WIDTH 13 + +/* Template switches */ +#define ISP_SHIELD_INPUT_DMEM 0 +#define ISP_SHIELD_OUTPUT_DMEM 1 +#define ISP_SHIELD_INPUT_VMEM 0 +#define ISP_SHIELD_OUTPUT_VMEM 0 +#define ISP_SHIELD_INPUT_PMEM 1 +#define ISP_SHIELD_OUTPUT_PMEM 1 +#define ISP_SHIELD_INPUT_HIST 1 +#define ISP_SHIELD_OUTPUT_HIST 1 +/* When LUT is select the shielding is always on */ +#define ISP_SHIELD_INPUT_VAMEM 1 +#define ISP_SHIELD_OUTPUT_VAMEM 1 + +#define ISP_HAS_IRQ 1 +#define ISP_HAS_SOFT_RESET 1 +#define ISP_HAS_VEC_DIV 0 +#define ISP_HAS_VFU_W_2O 1 +#define ISP_HAS_DEINT3 1 +#define ISP_HAS_LUT 1 +#define ISP_HAS_HIST 1 +#define ISP_HAS_VALSU 1 +#define ISP_HAS_3rdVALSU 1 +#define ISP_VRF1_HAS_2P 1 + +#define ISP_SRU_GUARDING 1 +#define ISP_VLSU_GUARDING 1 + +#define ISP_VRF_RAM 1 +#define ISP_SRF_RAM 1 + +#define ISP_SPLIT_VMUL_VADD_IS 0 +#define ISP_RFSPLIT_FPGA 0 + +/* RSN or Bus pipelining */ +#define ISP_RSN_PIPE 1 +#define ISP_VSF_BUS_PIPE 0 + +/* extra slave port to vmem */ +#define ISP_IF_VMEM 0 +#define ISP_GDC_VMEM 0 + +/* Streaming ports */ +#define ISP_IF 1 +#define ISP_IF_B 1 +#define ISP_GDC 1 +#define ISP_SCL 1 +#define ISP_GPFIFO 1 +#define ISP_SP 1 + +/* Removing Issue Slot(s) */ +#define ISP_HAS_NOT_SIMD_IS2 0 +#define ISP_HAS_NOT_SIMD_IS3 0 +#define ISP_HAS_NOT_SIMD_IS4 0 +#define ISP_HAS_NOT_SIMD_IS4_VADD 0 +#define ISP_HAS_NOT_SIMD_IS5 0 +#define ISP_HAS_NOT_SIMD_IS6 0 +#define ISP_HAS_NOT_SIMD_IS7 0 +#define ISP_HAS_NOT_SIMD_IS8 0 + +/* ICache */ +#define ISP_ICACHE 1 +#define ISP_ICACHE_ONLY 0 +#define ISP_ICACHE_PREFETCH 1 +#define ISP_ICACHE_INDEX_BITS 8 +#define ISP_ICACHE_SET_BITS 5 +#define ISP_ICACHE_BLOCKS_PER_SET_BITS 1 + +/* Experimental Flags */ +#define ISP_EXP_1 0 +#define ISP_EXP_2 0 +#define ISP_EXP_3 0 +#define ISP_EXP_4 0 +#define ISP_EXP_5 0 +#define ISP_EXP_6 0 + +/* Derived values */ +#define ISP_LOG2_PMEM_WIDTH 10 +#define ISP_VEC_WIDTH 896 +#define ISP_SLICE_WIDTH 56 +#define ISP_VMEM_WIDTH 896 +#define ISP_VMEM_ALIGN 128 +#if ISP_VMEM_IS_BAMEM + #define ISP_VMEM_ALIGN_ELEM 2 +#endif /* ISP_VMEM_IS_BAMEM */ +#define ISP_SIMDLSU 1 +#define ISP_LSU_IMM_BITS 12 + +/* convenient shortcuts for software*/ +#define ISP_NWAY ISP_VEC_NELEMS +#define NBITS ISP_VEC_ELEMBITS + +#define _isp_ceil_div(a,b) (((a)+(b)-1)/(b)) + +#ifdef C_RUN +#define ISP_VEC_ALIGN (_isp_ceil_div(ISP_VEC_WIDTH, 64)*8) +#else +#define ISP_VEC_ALIGN ISP_VMEM_ALIGN +#endif + +/* HRT specific vector support */ +#define isp2400_mamoiada_vector_alignment ISP_VEC_ALIGN +#define isp2400_mamoiada_vector_elem_bits ISP_VMEM_ELEMBITS +#define isp2400_mamoiada_vector_elem_precision ISP_VMEM_ELEM_PRECISION +#define isp2400_mamoiada_vector_num_elems ISP_VEC_NELEMS + +/* register file sizes */ +#define ISP_RF0_SIZE 64 +#define ISP_RF1_SIZE 16 +#define ISP_RF2_SIZE 64 +#define ISP_RF3_SIZE 4 +#define ISP_RF4_SIZE 64 +#define ISP_RF5_SIZE 16 +#define ISP_RF6_SIZE 16 +#define ISP_RF7_SIZE 16 +#define ISP_RF8_SIZE 16 +#define ISP_RF9_SIZE 16 +#define ISP_RF10_SIZE 16 +#define ISP_RF11_SIZE 16 +#define ISP_VRF1_SIZE 24 +#define ISP_VRF2_SIZE 24 +#define ISP_VRF3_SIZE 24 +#define ISP_VRF4_SIZE 24 +#define ISP_VRF5_SIZE 24 +#define ISP_VRF6_SIZE 24 +#define ISP_VRF7_SIZE 24 +#define ISP_VRF8_SIZE 24 +#define ISP_SRF1_SIZE 4 +#define ISP_SRF2_SIZE 64 +#define ISP_SRF3_SIZE 64 +#define ISP_SRF4_SIZE 32 +#define ISP_SRF5_SIZE 64 +#define ISP_FRF0_SIZE 16 +#define ISP_FRF1_SIZE 4 +#define ISP_FRF2_SIZE 16 +#define ISP_FRF3_SIZE 4 +#define ISP_FRF4_SIZE 4 +#define ISP_FRF5_SIZE 8 +#define ISP_FRF6_SIZE 4 +/* register file read latency */ +#define ISP_VRF1_READ_LAT 1 +#define ISP_VRF2_READ_LAT 1 +#define ISP_VRF3_READ_LAT 1 +#define ISP_VRF4_READ_LAT 1 +#define ISP_VRF5_READ_LAT 1 +#define ISP_VRF6_READ_LAT 1 +#define ISP_VRF7_READ_LAT 1 +#define ISP_VRF8_READ_LAT 1 +#define ISP_SRF1_READ_LAT 1 +#define ISP_SRF2_READ_LAT 1 +#define ISP_SRF3_READ_LAT 1 +#define ISP_SRF4_READ_LAT 1 +#define ISP_SRF5_READ_LAT 1 +#define ISP_SRF5_READ_LAT 1 +/* immediate sizes */ +#define ISP_IS1_IMM_BITS 14 +#define ISP_IS2_IMM_BITS 13 +#define ISP_IS3_IMM_BITS 14 +#define ISP_IS4_IMM_BITS 14 +#define ISP_IS5_IMM_BITS 9 +#define ISP_IS6_IMM_BITS 16 +#define ISP_IS7_IMM_BITS 9 +#define ISP_IS8_IMM_BITS 16 +#define ISP_IS9_IMM_BITS 11 +/* fifo depths */ +#define ISP_IF_FIFO_DEPTH 0 +#define ISP_IF_B_FIFO_DEPTH 0 +#define ISP_DMA_FIFO_DEPTH 0 +#define ISP_OF_FIFO_DEPTH 0 +#define ISP_GDC_FIFO_DEPTH 0 +#define ISP_SCL_FIFO_DEPTH 0 +#define ISP_GPFIFO_FIFO_DEPTH 0 +#define ISP_SP_FIFO_DEPTH 0 diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/isp2400_support.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/isp2400_support.h new file mode 100644 index 0000000000000000000000000000000000000000..e00bc841d0f0d2c00e942467981630e5051d040a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/isp2400_support.h @@ -0,0 +1,38 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _isp2400_support_h +#define _isp2400_support_h + +#ifndef ISP2400_VECTOR_TYPES +/* This typedef is to be able to include hive header files + in the host code which is useful in crun */ +typedef char *tmemvectors, *tmemvectoru, *tvector; +#endif + +#define hrt_isp_vamem1_store_16(cell, addr, val) hrt_mem_store_16(cell, HRT_PROC_TYPE_PROP(cell, _simd_vamem1), addr, val) +#define hrt_isp_vamem2_store_16(cell, addr, val) hrt_mem_store_16(cell, HRT_PROC_TYPE_PROP(cell, _simd_vamem2), addr, val) + +#define hrt_isp_dmem(cell) HRT_PROC_TYPE_PROP(cell, _base_dmem) +#define hrt_isp_vmem(cell) HRT_PROC_TYPE_PROP(cell, _simd_vmem) + +#define hrt_isp_dmem_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_dmem(cell)) +#define hrt_isp_vmem_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_vmem(cell)) + +#if ISP_HAS_HIST + #define hrt_isp_hist(cell) HRT_PROC_TYPE_PROP(cell, _simd_histogram) + #define hrt_isp_hist_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_hist(cell)) +#endif + +#endif /* _isp2400_support_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/isp_acquisition_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/isp_acquisition_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..59362072162710fbc0d5a5a47c11c48dd38b6861 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/isp_acquisition_defs.h @@ -0,0 +1,234 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _isp_acquisition_defs_h +#define _isp_acquisition_defs_h + +#define _ISP_ACQUISITION_REG_ALIGN 4 /* assuming 32 bit control bus width */ +#define _ISP_ACQUISITION_BYTES_PER_ELEM 4 + +/* --------------------------------------------------*/ + +#define NOF_ACQ_IRQS 1 + +/* --------------------------------------------------*/ +/* FSM */ +/* --------------------------------------------------*/ +#define MEM2STREAM_FSM_STATE_BITS 2 +#define ACQ_SYNCHRONIZER_FSM_STATE_BITS 2 + +/* --------------------------------------------------*/ +/* REGISTER INFO */ +/* --------------------------------------------------*/ + +#define NOF_ACQ_REGS 12 + +// Register id's of MMIO slave accesible registers +#define ACQ_START_ADDR_REG_ID 0 +#define ACQ_MEM_REGION_SIZE_REG_ID 1 +#define ACQ_NUM_MEM_REGIONS_REG_ID 2 +#define ACQ_INIT_REG_ID 3 +#define ACQ_RECEIVED_SHORT_PACKETS_REG_ID 4 +#define ACQ_RECEIVED_LONG_PACKETS_REG_ID 5 +#define ACQ_LAST_COMMAND_REG_ID 6 +#define ACQ_NEXT_COMMAND_REG_ID 7 +#define ACQ_LAST_ACKNOWLEDGE_REG_ID 8 +#define ACQ_NEXT_ACKNOWLEDGE_REG_ID 9 +#define ACQ_FSM_STATE_INFO_REG_ID 10 +#define ACQ_INT_CNTR_INFO_REG_ID 11 + +// Register width +#define ACQ_START_ADDR_REG_WIDTH 9 +#define ACQ_MEM_REGION_SIZE_REG_WIDTH 9 +#define ACQ_NUM_MEM_REGIONS_REG_WIDTH 9 +#define ACQ_INIT_REG_WIDTH 3 +#define ACQ_RECEIVED_SHORT_PACKETS_REG_WIDTH 32 +#define ACQ_RECEIVED_LONG_PACKETS_REG_WIDTH 32 +#define ACQ_LAST_COMMAND_REG_WIDTH 32 +#define ACQ_NEXT_COMMAND_REG_WIDTH 32 +#define ACQ_LAST_ACKNOWLEDGE_REG_WIDTH 32 +#define ACQ_NEXT_ACKNOWLEDGE_REG_WIDTH 32 +#define ACQ_FSM_STATE_INFO_REG_WIDTH ((MEM2STREAM_FSM_STATE_BITS * 3) + (ACQ_SYNCHRONIZER_FSM_STATE_BITS *3)) +#define ACQ_INT_CNTR_INFO_REG_WIDTH 32 + +/* register reset value */ +#define ACQ_START_ADDR_REG_RSTVAL 0 +#define ACQ_MEM_REGION_SIZE_REG_RSTVAL 128 +#define ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3 +#define ACQ_INIT_REG_RSTVAL 0 +#define ACQ_RECEIVED_SHORT_PACKETS_REG_RSTVAL 0 +#define ACQ_RECEIVED_LONG_PACKETS_REG_RSTVAL 0 +#define ACQ_LAST_COMMAND_REG_RSTVAL 0 +#define ACQ_NEXT_COMMAND_REG_RSTVAL 0 +#define ACQ_LAST_ACKNOWLEDGE_REG_RSTVAL 0 +#define ACQ_NEXT_ACKNOWLEDGE_REG_RSTVAL 0 +#define ACQ_FSM_STATE_INFO_REG_RSTVAL 0 +#define ACQ_INT_CNTR_INFO_REG_RSTVAL 0 + +/* bit definitions */ +#define ACQ_INIT_RST_REG_BIT 0 +#define ACQ_INIT_RESYNC_BIT 2 +#define ACQ_INIT_RST_IDX ACQ_INIT_RST_REG_BIT +#define ACQ_INIT_RST_BITS 1 +#define ACQ_INIT_RESYNC_IDX ACQ_INIT_RESYNC_BIT +#define ACQ_INIT_RESYNC_BITS 1 + +/* --------------------------------------------------*/ +/* TOKEN INFO */ +/* --------------------------------------------------*/ +#define ACQ_TOKEN_ID_LSB 0 +#define ACQ_TOKEN_ID_MSB 3 +#define ACQ_TOKEN_WIDTH (ACQ_TOKEN_ID_MSB - ACQ_TOKEN_ID_LSB + 1) // 4 +#define ACQ_TOKEN_ID_IDX 0 +#define ACQ_TOKEN_ID_BITS ACQ_TOKEN_WIDTH +#define ACQ_INIT_CMD_INIT_IDX 4 +#define ACQ_INIT_CMD_INIT_BITS 3 +#define ACQ_CMD_START_ADDR_IDX 4 +#define ACQ_CMD_START_ADDR_BITS 9 +#define ACQ_CMD_NOFWORDS_IDX 13 +#define ACQ_CMD_NOFWORDS_BITS 9 +#define ACQ_MEM_REGION_ID_IDX 22 +#define ACQ_MEM_REGION_ID_BITS 9 +#define ACQ_PACKET_LENGTH_TOKEN_MSB 21 +#define ACQ_PACKET_LENGTH_TOKEN_LSB 13 +#define ACQ_PACKET_DATA_FORMAT_ID_TOKEN_MSB 9 +#define ACQ_PACKET_DATA_FORMAT_ID_TOKEN_LSB 4 +#define ACQ_PACKET_CH_ID_TOKEN_MSB 11 +#define ACQ_PACKET_CH_ID_TOKEN_LSB 10 +#define ACQ_PACKET_MEM_REGION_ID_TOKEN_MSB 12 /* only for capt_end_of_packet_written */ +#define ACQ_PACKET_MEM_REGION_ID_TOKEN_LSB 4 /* only for capt_end_of_packet_written */ + + +/* Command tokens IDs */ +#define ACQ_READ_REGION_AUTO_INCR_TOKEN_ID 0 //0000b +#define ACQ_READ_REGION_TOKEN_ID 1 //0001b +#define ACQ_READ_REGION_SOP_TOKEN_ID 2 //0010b +#define ACQ_INIT_TOKEN_ID 8 //1000b + +/* Acknowledge token IDs */ +#define ACQ_READ_REGION_ACK_TOKEN_ID 0 //0000b +#define ACQ_END_OF_PACKET_TOKEN_ID 4 //0100b +#define ACQ_END_OF_REGION_TOKEN_ID 5 //0101b +#define ACQ_SOP_MISMATCH_TOKEN_ID 6 //0110b +#define ACQ_UNDEF_PH_TOKEN_ID 7 //0111b + +#define ACQ_TOKEN_MEMREGIONID_MSB 30 +#define ACQ_TOKEN_MEMREGIONID_LSB 22 +#define ACQ_TOKEN_NOFWORDS_MSB 21 +#define ACQ_TOKEN_NOFWORDS_LSB 13 +#define ACQ_TOKEN_STARTADDR_MSB 12 +#define ACQ_TOKEN_STARTADDR_LSB 4 + + +/* --------------------------------------------------*/ +/* MIPI */ +/* --------------------------------------------------*/ + +#define WORD_COUNT_WIDTH 16 +#define PKT_CODE_WIDTH 6 +#define CHN_NO_WIDTH 2 +#define ERROR_INFO_WIDTH 8 + +#define LONG_PKTCODE_MAX 63 +#define LONG_PKTCODE_MIN 16 +#define SHORT_PKTCODE_MAX 15 + +#define EOF_CODE 1 + +/* --------------------------------------------------*/ +/* Packet Info */ +/* --------------------------------------------------*/ +#define ACQ_START_OF_FRAME 0 +#define ACQ_END_OF_FRAME 1 +#define ACQ_START_OF_LINE 2 +#define ACQ_END_OF_LINE 3 +#define ACQ_LINE_PAYLOAD 4 +#define ACQ_GEN_SH_PKT 5 + + +/* bit definition */ +#define ACQ_PKT_TYPE_IDX 16 +#define ACQ_PKT_TYPE_BITS 6 +#define ACQ_PKT_SOP_IDX 32 +#define ACQ_WORD_CNT_IDX 0 +#define ACQ_WORD_CNT_BITS 16 +#define ACQ_PKT_INFO_IDX 16 +#define ACQ_PKT_INFO_BITS 8 +#define ACQ_HEADER_DATA_IDX 0 +#define ACQ_HEADER_DATA_BITS 16 +#define ACQ_ACK_TOKEN_ID_IDX ACQ_TOKEN_ID_IDX +#define ACQ_ACK_TOKEN_ID_BITS ACQ_TOKEN_ID_BITS +#define ACQ_ACK_NOFWORDS_IDX 13 +#define ACQ_ACK_NOFWORDS_BITS 9 +#define ACQ_ACK_PKT_LEN_IDX 4 +#define ACQ_ACK_PKT_LEN_BITS 16 + + +/* --------------------------------------------------*/ +/* Packet Data Type */ +/* --------------------------------------------------*/ + + +#define ACQ_YUV420_8_DATA 24 /* 01 1000 YUV420 8-bit */ +#define ACQ_YUV420_10_DATA 25 /* 01 1001 YUV420 10-bit */ +#define ACQ_YUV420_8L_DATA 26 /* 01 1010 YUV420 8-bit legacy */ +#define ACQ_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */ +#define ACQ_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */ +#define ACQ_RGB444_DATA 32 /* 10 0000 RGB444 */ +#define ACQ_RGB555_DATA 33 /* 10 0001 RGB555 */ +#define ACQ_RGB565_DATA 34 /* 10 0010 RGB565 */ +#define ACQ_RGB666_DATA 35 /* 10 0011 RGB666 */ +#define ACQ_RGB888_DATA 36 /* 10 0100 RGB888 */ +#define ACQ_RAW6_DATA 40 /* 10 1000 RAW6 */ +#define ACQ_RAW7_DATA 41 /* 10 1001 RAW7 */ +#define ACQ_RAW8_DATA 42 /* 10 1010 RAW8 */ +#define ACQ_RAW10_DATA 43 /* 10 1011 RAW10 */ +#define ACQ_RAW12_DATA 44 /* 10 1100 RAW12 */ +#define ACQ_RAW14_DATA 45 /* 10 1101 RAW14 */ +#define ACQ_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */ +#define ACQ_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */ +#define ACQ_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */ +#define ACQ_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */ +#define ACQ_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */ +#define ACQ_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */ +#define ACQ_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */ +#define ACQ_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */ +#define ACQ_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */ +#define ACQ_SOF_DATA 0 /* 00 0000 frame start */ +#define ACQ_EOF_DATA 1 /* 00 0001 frame end */ +#define ACQ_SOL_DATA 2 /* 00 0010 line start */ +#define ACQ_EOL_DATA 3 /* 00 0011 line end */ +#define ACQ_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */ +#define ACQ_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */ +#define ACQ_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */ +#define ACQ_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */ +#define ACQ_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */ +#define ACQ_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */ +#define ACQ_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */ +#define ACQ_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */ +#define ACQ_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */ +#define ACQ_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */ +#define ACQ_RESERVED_DATA_TYPE_MIN 56 +#define ACQ_RESERVED_DATA_TYPE_MAX 63 +#define ACQ_GEN_LONG_RESERVED_DATA_TYPE_MIN 19 +#define ACQ_GEN_LONG_RESERVED_DATA_TYPE_MAX 23 +#define ACQ_YUV_RESERVED_DATA_TYPE 27 +#define ACQ_RGB_RESERVED_DATA_TYPE_MIN 37 +#define ACQ_RGB_RESERVED_DATA_TYPE_MAX 39 +#define ACQ_RAW_RESERVED_DATA_TYPE_MIN 46 +#define ACQ_RAW_RESERVED_DATA_TYPE_MAX 47 + +/* --------------------------------------------------*/ + +#endif /* _isp_acquisition_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/isp_capture_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/isp_capture_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..0a249ce3e5897d00d64254de6e1957c38b516a38 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/isp_capture_defs.h @@ -0,0 +1,310 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _isp_capture_defs_h +#define _isp_capture_defs_h + +#define _ISP_CAPTURE_REG_ALIGN 4 /* assuming 32 bit control bus width */ +#define _ISP_CAPTURE_BITS_PER_ELEM 32 /* only for data, not SOP */ +#define _ISP_CAPTURE_BYTES_PER_ELEM (_ISP_CAPTURE_BITS_PER_ELEM/8 ) +#define _ISP_CAPTURE_BYTES_PER_WORD 32 /* 256/8 */ +#define _ISP_CAPTURE_ELEM_PER_WORD _ISP_CAPTURE_BYTES_PER_WORD / _ISP_CAPTURE_BYTES_PER_ELEM + +//#define CAPT_RCV_ACK 1 +//#define CAPT_WRT_ACK 2 +//#define CAPT_IRQ_ACK 3 + +/* --------------------------------------------------*/ + +#define NOF_IRQS 2 + +/* --------------------------------------------------*/ +/* REGISTER INFO */ +/* --------------------------------------------------*/ + +// Number of registers +#define CAPT_NOF_REGS 16 + +// Register id's of MMIO slave accesible registers +#define CAPT_START_MODE_REG_ID 0 +#define CAPT_START_ADDR_REG_ID 1 +#define CAPT_MEM_REGION_SIZE_REG_ID 2 +#define CAPT_NUM_MEM_REGIONS_REG_ID 3 +#define CAPT_INIT_REG_ID 4 +#define CAPT_START_REG_ID 5 +#define CAPT_STOP_REG_ID 6 + +#define CAPT_PACKET_LENGTH_REG_ID 7 +#define CAPT_RECEIVED_LENGTH_REG_ID 8 +#define CAPT_RECEIVED_SHORT_PACKETS_REG_ID 9 +#define CAPT_RECEIVED_LONG_PACKETS_REG_ID 10 +#define CAPT_LAST_COMMAND_REG_ID 11 +#define CAPT_NEXT_COMMAND_REG_ID 12 +#define CAPT_LAST_ACKNOWLEDGE_REG_ID 13 +#define CAPT_NEXT_ACKNOWLEDGE_REG_ID 14 +#define CAPT_FSM_STATE_INFO_REG_ID 15 + +// Register width +#define CAPT_START_MODE_REG_WIDTH 1 +#define CAPT_START_ADDR_REG_WIDTH 9 +#define CAPT_MEM_REGION_SIZE_REG_WIDTH 9 +#define CAPT_NUM_MEM_REGIONS_REG_WIDTH 9 +#define CAPT_INIT_REG_WIDTH (18 + 4) + +#define CAPT_START_REG_WIDTH 1 +#define CAPT_STOP_REG_WIDTH 1 + +/* --------------------------------------------------*/ +/* FSM */ +/* --------------------------------------------------*/ +#define CAPT_WRITE2MEM_FSM_STATE_BITS 2 +#define CAPT_SYNCHRONIZER_FSM_STATE_BITS 3 + + +#define CAPT_PACKET_LENGTH_REG_WIDTH 17 +#define CAPT_RECEIVED_LENGTH_REG_WIDTH 17 +#define CAPT_RECEIVED_SHORT_PACKETS_REG_WIDTH 32 +#define CAPT_RECEIVED_LONG_PACKETS_REG_WIDTH 32 +#define CAPT_LAST_COMMAND_REG_WIDTH 32 +/* #define CAPT_NEXT_COMMAND_REG_WIDTH 32 */ +#define CAPT_LAST_ACKNOWLEDGE_REG_WIDTH 32 +#define CAPT_NEXT_ACKNOWLEDGE_REG_WIDTH 32 +#define CAPT_FSM_STATE_INFO_REG_WIDTH ((CAPT_WRITE2MEM_FSM_STATE_BITS * 3) + (CAPT_SYNCHRONIZER_FSM_STATE_BITS * 3)) + +#define CAPT_INIT_RESTART_MEM_ADDR_WIDTH 9 +#define CAPT_INIT_RESTART_MEM_REGION_WIDTH 9 + +/* register reset value */ +#define CAPT_START_MODE_REG_RSTVAL 0 +#define CAPT_START_ADDR_REG_RSTVAL 0 +#define CAPT_MEM_REGION_SIZE_REG_RSTVAL 128 +#define CAPT_NUM_MEM_REGIONS_REG_RSTVAL 3 +#define CAPT_INIT_REG_RSTVAL 0 + +#define CAPT_START_REG_RSTVAL 0 +#define CAPT_STOP_REG_RSTVAL 0 + +#define CAPT_PACKET_LENGTH_REG_RSTVAL 0 +#define CAPT_RECEIVED_LENGTH_REG_RSTVAL 0 +#define CAPT_RECEIVED_SHORT_PACKETS_REG_RSTVAL 0 +#define CAPT_RECEIVED_LONG_PACKETS_REG_RSTVAL 0 +#define CAPT_LAST_COMMAND_REG_RSTVAL 0 +#define CAPT_NEXT_COMMAND_REG_RSTVAL 0 +#define CAPT_LAST_ACKNOWLEDGE_REG_RSTVAL 0 +#define CAPT_NEXT_ACKNOWLEDGE_REG_RSTVAL 0 +#define CAPT_FSM_STATE_INFO_REG_RSTVAL 0 + +/* bit definitions */ +#define CAPT_INIT_RST_REG_BIT 0 +#define CAPT_INIT_FLUSH_BIT 1 +#define CAPT_INIT_RESYNC_BIT 2 +#define CAPT_INIT_RESTART_BIT 3 +#define CAPT_INIT_RESTART_MEM_ADDR_LSB 4 +#define CAPT_INIT_RESTART_MEM_ADDR_MSB 12 +#define CAPT_INIT_RESTART_MEM_REGION_LSB 13 +#define CAPT_INIT_RESTART_MEM_REGION_MSB 21 + + +#define CAPT_INIT_RST_REG_IDX CAPT_INIT_RST_REG_BIT +#define CAPT_INIT_RST_REG_BITS 1 +#define CAPT_INIT_FLUSH_IDX CAPT_INIT_FLUSH_BIT +#define CAPT_INIT_FLUSH_BITS 1 +#define CAPT_INIT_RESYNC_IDX CAPT_INIT_RESYNC_BIT +#define CAPT_INIT_RESYNC_BITS 1 +#define CAPT_INIT_RESTART_IDX CAPT_INIT_RESTART_BIT +#define CAPT_INIT_RESTART_BITS 1 +#define CAPT_INIT_RESTART_MEM_ADDR_IDX CAPT_INIT_RESTART_MEM_ADDR_LSB +#define CAPT_INIT_RESTART_MEM_ADDR_BITS (CAPT_INIT_RESTART_MEM_ADDR_MSB - CAPT_INIT_RESTART_MEM_ADDR_LSB + 1) +#define CAPT_INIT_RESTART_MEM_REGION_IDX CAPT_INIT_RESTART_MEM_REGION_LSB +#define CAPT_INIT_RESTART_MEM_REGION_BITS (CAPT_INIT_RESTART_MEM_REGION_MSB - CAPT_INIT_RESTART_MEM_REGION_LSB + 1) + + + +/* --------------------------------------------------*/ +/* TOKEN INFO */ +/* --------------------------------------------------*/ +#define CAPT_TOKEN_ID_LSB 0 +#define CAPT_TOKEN_ID_MSB 3 +#define CAPT_TOKEN_WIDTH (CAPT_TOKEN_ID_MSB - CAPT_TOKEN_ID_LSB + 1) /* 4 */ + +/* Command tokens IDs */ +#define CAPT_START_TOKEN_ID 0 /* 0000b */ +#define CAPT_STOP_TOKEN_ID 1 /* 0001b */ +#define CAPT_FREEZE_TOKEN_ID 2 /* 0010b */ +#define CAPT_RESUME_TOKEN_ID 3 /* 0011b */ +#define CAPT_INIT_TOKEN_ID 8 /* 1000b */ + +#define CAPT_START_TOKEN_BIT 0 +#define CAPT_STOP_TOKEN_BIT 0 +#define CAPT_FREEZE_TOKEN_BIT 0 +#define CAPT_RESUME_TOKEN_BIT 0 +#define CAPT_INIT_TOKEN_BIT 0 + +/* Acknowledge token IDs */ +#define CAPT_END_OF_PACKET_RECEIVED_TOKEN_ID 0 /* 0000b */ +#define CAPT_END_OF_PACKET_WRITTEN_TOKEN_ID 1 /* 0001b */ +#define CAPT_END_OF_REGION_WRITTEN_TOKEN_ID 2 /* 0010b */ +#define CAPT_FLUSH_DONE_TOKEN_ID 3 /* 0011b */ +#define CAPT_PREMATURE_SOP_TOKEN_ID 4 /* 0100b */ +#define CAPT_MISSING_SOP_TOKEN_ID 5 /* 0101b */ +#define CAPT_UNDEF_PH_TOKEN_ID 6 /* 0110b */ +#define CAPT_STOP_ACK_TOKEN_ID 7 /* 0111b */ + +#define CAPT_PACKET_LENGTH_TOKEN_MSB 19 +#define CAPT_PACKET_LENGTH_TOKEN_LSB 4 +#define CAPT_SUPER_PACKET_LENGTH_TOKEN_MSB 20 +#define CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB 4 +#define CAPT_PACKET_DATA_FORMAT_ID_TOKEN_MSB 25 +#define CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB 20 +#define CAPT_PACKET_CH_ID_TOKEN_MSB 27 +#define CAPT_PACKET_CH_ID_TOKEN_LSB 26 +#define CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB 29 +#define CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB 21 + +/* bit definition */ +#define CAPT_CMD_IDX CAPT_TOKEN_ID_LSB +#define CAPT_CMD_BITS (CAPT_TOKEN_ID_MSB - CAPT_TOKEN_ID_LSB + 1) +#define CAPT_SOP_IDX 32 +#define CAPT_SOP_BITS 1 +#define CAPT_PKT_INFO_IDX 16 +#define CAPT_PKT_INFO_BITS 8 +#define CAPT_PKT_TYPE_IDX 0 +#define CAPT_PKT_TYPE_BITS 6 +#define CAPT_HEADER_DATA_IDX 0 +#define CAPT_HEADER_DATA_BITS 16 +#define CAPT_PKT_DATA_IDX 0 +#define CAPT_PKT_DATA_BITS 32 +#define CAPT_WORD_CNT_IDX 0 +#define CAPT_WORD_CNT_BITS 16 +#define CAPT_ACK_TOKEN_ID_IDX 0 +#define CAPT_ACK_TOKEN_ID_BITS 4 +//#define CAPT_ACK_PKT_LEN_IDX CAPT_PACKET_LENGTH_TOKEN_LSB +//#define CAPT_ACK_PKT_LEN_BITS (CAPT_PACKET_LENGTH_TOKEN_MSB - CAPT_PACKET_LENGTH_TOKEN_LSB + 1) +//#define CAPT_ACK_PKT_INFO_IDX 20 +//#define CAPT_ACK_PKT_INFO_BITS 8 +//#define CAPT_ACK_MEM_REG_ID1_IDX 20 /* for capt_end_of_packet_written */ +//#define CAPT_ACK_MEM_REG_ID2_IDX 4 /* for capt_end_of_region_written */ +#define CAPT_ACK_PKT_LEN_IDX CAPT_PACKET_LENGTH_TOKEN_LSB +#define CAPT_ACK_PKT_LEN_BITS (CAPT_PACKET_LENGTH_TOKEN_MSB - CAPT_PACKET_LENGTH_TOKEN_LSB + 1) +#define CAPT_ACK_SUPER_PKT_LEN_IDX CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB +#define CAPT_ACK_SUPER_PKT_LEN_BITS (CAPT_SUPER_PACKET_LENGTH_TOKEN_MSB - CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB + 1) +#define CAPT_ACK_PKT_INFO_IDX CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB +#define CAPT_ACK_PKT_INFO_BITS (CAPT_PACKET_CH_ID_TOKEN_MSB - CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB + 1) +#define CAPT_ACK_MEM_REGION_ID_IDX CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB +#define CAPT_ACK_MEM_REGION_ID_BITS (CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB - CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB + 1) +#define CAPT_ACK_PKT_TYPE_IDX CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB +#define CAPT_ACK_PKT_TYPE_BITS (CAPT_PACKET_DATA_FORMAT_ID_TOKEN_MSB - CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB + 1) +#define CAPT_INIT_TOKEN_INIT_IDX 4 +#define CAPT_INIT_TOKEN_INIT_BITS 22 + + +/* --------------------------------------------------*/ +/* MIPI */ +/* --------------------------------------------------*/ + +#define CAPT_WORD_COUNT_WIDTH 16 +#define CAPT_PKT_CODE_WIDTH 6 +#define CAPT_CHN_NO_WIDTH 2 +#define CAPT_ERROR_INFO_WIDTH 8 + +#define LONG_PKTCODE_MAX 63 +#define LONG_PKTCODE_MIN 16 +#define SHORT_PKTCODE_MAX 15 + + +/* --------------------------------------------------*/ +/* Packet Info */ +/* --------------------------------------------------*/ +#define CAPT_START_OF_FRAME 0 +#define CAPT_END_OF_FRAME 1 +#define CAPT_START_OF_LINE 2 +#define CAPT_END_OF_LINE 3 +#define CAPT_LINE_PAYLOAD 4 +#define CAPT_GEN_SH_PKT 5 + + +/* --------------------------------------------------*/ +/* Packet Data Type */ +/* --------------------------------------------------*/ + +#define CAPT_YUV420_8_DATA 24 /* 01 1000 YUV420 8-bit */ +#define CAPT_YUV420_10_DATA 25 /* 01 1001 YUV420 10-bit */ +#define CAPT_YUV420_8L_DATA 26 /* 01 1010 YUV420 8-bit legacy */ +#define CAPT_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */ +#define CAPT_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */ +#define CAPT_RGB444_DATA 32 /* 10 0000 RGB444 */ +#define CAPT_RGB555_DATA 33 /* 10 0001 RGB555 */ +#define CAPT_RGB565_DATA 34 /* 10 0010 RGB565 */ +#define CAPT_RGB666_DATA 35 /* 10 0011 RGB666 */ +#define CAPT_RGB888_DATA 36 /* 10 0100 RGB888 */ +#define CAPT_RAW6_DATA 40 /* 10 1000 RAW6 */ +#define CAPT_RAW7_DATA 41 /* 10 1001 RAW7 */ +#define CAPT_RAW8_DATA 42 /* 10 1010 RAW8 */ +#define CAPT_RAW10_DATA 43 /* 10 1011 RAW10 */ +#define CAPT_RAW12_DATA 44 /* 10 1100 RAW12 */ +#define CAPT_RAW14_DATA 45 /* 10 1101 RAW14 */ +#define CAPT_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */ +#define CAPT_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */ +#define CAPT_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */ +#define CAPT_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */ +#define CAPT_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */ +#define CAPT_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */ +#define CAPT_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */ +#define CAPT_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */ +#define CAPT_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */ +#define CAPT_SOF_DATA 0 /* 00 0000 frame start */ +#define CAPT_EOF_DATA 1 /* 00 0001 frame end */ +#define CAPT_SOL_DATA 2 /* 00 0010 line start */ +#define CAPT_EOL_DATA 3 /* 00 0011 line end */ +#define CAPT_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */ +#define CAPT_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */ +#define CAPT_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */ +#define CAPT_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */ +#define CAPT_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */ +#define CAPT_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */ +#define CAPT_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */ +#define CAPT_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */ +#define CAPT_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */ +#define CAPT_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */ +#define CAPT_RESERVED_DATA_TYPE_MIN 56 +#define CAPT_RESERVED_DATA_TYPE_MAX 63 +#define CAPT_GEN_LONG_RESERVED_DATA_TYPE_MIN 19 +#define CAPT_GEN_LONG_RESERVED_DATA_TYPE_MAX 23 +#define CAPT_YUV_RESERVED_DATA_TYPE 27 +#define CAPT_RGB_RESERVED_DATA_TYPE_MIN 37 +#define CAPT_RGB_RESERVED_DATA_TYPE_MAX 39 +#define CAPT_RAW_RESERVED_DATA_TYPE_MIN 46 +#define CAPT_RAW_RESERVED_DATA_TYPE_MAX 47 + + +/* --------------------------------------------------*/ +/* Capture Unit State */ +/* --------------------------------------------------*/ +#define CAPT_FREE_RUN 0 +#define CAPT_NO_SYNC 1 +#define CAPT_SYNC_SWP 2 +#define CAPT_SYNC_MWP 3 +#define CAPT_SYNC_WAIT 4 +#define CAPT_FREEZE 5 +#define CAPT_RUN 6 + + +/* --------------------------------------------------*/ + +#endif /* _isp_capture_defs_h */ + + + + + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/mmu_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/mmu_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..c038f39ffd25e3f3d1b9afdbba93495642da5e6b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/mmu_defs.h @@ -0,0 +1,23 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _mmu_defs_h +#define _mmu_defs_h + +#define _HRT_MMU_INVALIDATE_TLB_REG_IDX 0 +#define _HRT_MMU_PAGE_TABLE_BASE_ADDRESS_REG_IDX 1 + +#define _HRT_MMU_REG_ALIGN 4 + +#endif /* _mmu_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/scalar_processor_2400_params.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/scalar_processor_2400_params.h new file mode 100644 index 0000000000000000000000000000000000000000..9b6c2893d950708458b4c82d4f5951923b57512e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/scalar_processor_2400_params.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _scalar_processor_2400_params_h +#define _scalar_processor_2400_params_h + +#include "cell_params.h" + +#endif /* _scalar_processor_2400_params_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/sp_hrt.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/sp_hrt.h new file mode 100644 index 0000000000000000000000000000000000000000..7ee4deba519ac9988da4ab01774a0899be97e7d5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/sp_hrt.h @@ -0,0 +1,24 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _sp_hrt_h_ +#define _sp_hrt_h_ + +#define hrt_sp_dmem(cell) HRT_PROC_TYPE_PROP(cell, _dmem) + +#define hrt_sp_dmem_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_sp_dmem(cell)) + +#endif /* _sp_hrt_h_ */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/str2mem_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/str2mem_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..1cb62444cf68bc590aceb0f6d3958feec81d95e2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/str2mem_defs.h @@ -0,0 +1,39 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _ST2MEM_DEFS_H +#define _ST2MEM_DEFS_H + +#define _STR2MEM_CRUN_BIT 0x100000 +#define _STR2MEM_CMD_BITS 0x0F0000 +#define _STR2MEM_COUNT_BITS 0x00FFFF + +#define _STR2MEM_BLOCKS_CMD 0xA0000 +#define _STR2MEM_PACKETS_CMD 0xB0000 +#define _STR2MEM_BYTES_CMD 0xC0000 +#define _STR2MEM_BYTES_FROM_PACKET_CMD 0xD0000 + +#define _STR2MEM_SOFT_RESET_REG_ID 0 +#define _STR2MEM_INPUT_ENDIANNESS_REG_ID 1 +#define _STR2MEM_OUTPUT_ENDIANNESS_REG_ID 2 +#define _STR2MEM_BIT_SWAPPING_REG_ID 3 +#define _STR2MEM_BLOCK_SYNC_LEVEL_REG_ID 4 +#define _STR2MEM_PACKET_SYNC_LEVEL_REG_ID 5 +#define _STR2MEM_READ_POST_WRITE_SYNC_ENABLE_REG_ID 6 +#define _STR2MEM_DUAL_BYTE_INPUTS_ENABLED_REG_ID 7 +#define _STR2MEM_EN_STAT_UPDATE_ID 8 + +#define _STR2MEM_REG_ALIGN 4 + +#endif /* _ST2MEM_DEFS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/streaming_to_mipi_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/streaming_to_mipi_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..60143b8743a2d5a4079f557387033e83acf99870 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/streaming_to_mipi_defs.h @@ -0,0 +1,28 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _streaming_to_mipi_defs_h +#define _streaming_to_mipi_defs_h + +#define HIVE_STR_TO_MIPI_VALID_A_BIT 0 +#define HIVE_STR_TO_MIPI_VALID_B_BIT 1 +#define HIVE_STR_TO_MIPI_SOL_BIT 2 +#define HIVE_STR_TO_MIPI_EOL_BIT 3 +#define HIVE_STR_TO_MIPI_SOF_BIT 4 +#define HIVE_STR_TO_MIPI_EOF_BIT 5 +#define HIVE_STR_TO_MIPI_CH_ID_LSB 6 + +#define HIVE_STR_TO_MIPI_DATA_A_LSB (HIVE_STR_TO_MIPI_VALID_B_BIT + 1) + +#endif /* _streaming_to_mipi_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/timed_controller_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/timed_controller_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..d2b8972b0d9ec64ae887e8c6f96d586262737b0f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/timed_controller_defs.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _timed_controller_defs_h +#define _timed_controller_defs_h + +#define _HRT_TIMED_CONTROLLER_CMD_REG_IDX 0 + +#define _HRT_TIMED_CONTROLLER_REG_ALIGN 4 + +#endif /* _timed_controller_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/var.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/var.h new file mode 100644 index 0000000000000000000000000000000000000000..19b19ef484f953867e311a95df2e48c418ffa156 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/var.h @@ -0,0 +1,99 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HRT_VAR_H +#define _HRT_VAR_H + +#include "version.h" +#include "system_api.h" +#include "hive_types.h" + +#define hrt_int_type_of_char char +#define hrt_int_type_of_uchar unsigned char +#define hrt_int_type_of_short short +#define hrt_int_type_of_ushort unsigned short +#define hrt_int_type_of_int int +#define hrt_int_type_of_uint unsigned int +#define hrt_int_type_of_long long +#define hrt_int_type_of_ulong unsigned long +#define hrt_int_type_of_ptr unsigned int + +#define hrt_host_type_of_char char +#define hrt_host_type_of_uchar unsigned char +#define hrt_host_type_of_short short +#define hrt_host_type_of_ushort unsigned short +#define hrt_host_type_of_int int +#define hrt_host_type_of_uint unsigned int +#define hrt_host_type_of_long long +#define hrt_host_type_of_ulong unsigned long +#define hrt_host_type_of_ptr void* + +#define HRT_TYPE_BYTES(cell, type) (HRT_TYPE_BITS(cell, type)/8) +#define HRT_HOST_TYPE(cell_type) HRTCAT(hrt_host_type_of_, cell_type) +#define HRT_INT_TYPE(type) HRTCAT(hrt_int_type_of_, type) + +#ifdef C_RUN + +#ifdef C_RUN_DYNAMIC_LINK_PROGRAMS +extern void *csim_processor_get_crun_symbol(hive_proc_id p, const char *sym); +#define _hrt_cell_get_crun_symbol(cell,sym) csim_processor_get_crun_symbol(cell,HRTSTR(sym)) +#define _hrt_cell_get_crun_indexed_symbol(cell,sym) csim_processor_get_crun_symbol(cell,HRTSTR(sym)) +#else +#define _hrt_cell_get_crun_symbol(cell,sym) (&sym) +#define _hrt_cell_get_crun_indexed_symbol(cell,sym) (sym) +#endif // C_RUN_DYNAMIC_LINK_PROGRAMS + +#define hrt_scalar_store(cell, type, var, data) \ + ((*(HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_symbol(cell,var)) = (data)) +#define hrt_scalar_load(cell, type, var) \ + ((*(HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_symbol(cell,var))) + +#define hrt_indexed_store(cell, type, array, index, data) \ + ((((HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_indexed_symbol(cell,array))[index]) = (data)) +#define hrt_indexed_load(cell, type, array, index) \ + (((HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_indexed_symbol(cell,array))[index]) + +#else /* C_RUN */ + +#define hrt_scalar_store(cell, type, var, data) \ + HRTCAT(hrt_mem_store_,HRT_TYPE_BITS(cell, type))(\ + cell, \ + HRTCAT(HIVE_MEM_,var), \ + HRTCAT(HIVE_ADDR_,var), \ + (HRT_INT_TYPE(type))(data)) + +#define hrt_scalar_load(cell, type, var) \ + (HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_,HRT_PROC_TYPE(cell),_,type) ( \ + cell, \ + HRTCAT(HIVE_MEM_,var), \ + HRTCAT(HIVE_ADDR_,var))) + +#define hrt_indexed_store(cell, type, array, index, data) \ + HRTCAT(hrt_mem_store_,HRT_TYPE_BITS(cell, type))(\ + cell, \ + HRTCAT(HIVE_MEM_,array), \ + (HRTCAT(HIVE_ADDR_,array))+((index)*HRT_TYPE_BYTES(cell, type)), \ + (HRT_INT_TYPE(type))(data)) + +#define hrt_indexed_load(cell, type, array, index) \ + (HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_,HRT_PROC_TYPE(cell),_,type) ( \ + cell, \ + HRTCAT(HIVE_MEM_,array), \ + (HRTCAT(HIVE_ADDR_,array))+((index)*HRT_TYPE_BYTES(cell, type)))) + +#endif /* C_RUN */ + +#endif /* _HRT_VAR_H */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/version.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/version.h new file mode 100644 index 0000000000000000000000000000000000000000..bbc4948baea9b913b590d8992a2d50358503c5f4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/hrt/version.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef HRT_VERSION_H +#define HRT_VERSION_H +#define HRT_VERSION_MAJOR 1 +#define HRT_VERSION_MINOR 4 +#define HRT_VERSION 1_4 +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/spmem_dump.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/spmem_dump.c new file mode 100644 index 0000000000000000000000000000000000000000..ddc7a8f051536d6b57953681a297b0d3f07f2693 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2400_system/spmem_dump.c @@ -0,0 +1,3634 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _sp_map_h_ +#define _sp_map_h_ + + +#ifndef _hrt_dummy_use_blob_sp +#define _hrt_dummy_use_blob_sp() +#endif + +#define _hrt_cell_load_program_sp(proc) _hrt_cell_load_program_embedded(proc, sp) + +#ifndef ISP2401 +/* function input_system_acquisition_stop: ADE */ +#else +/* function input_system_acquisition_stop: AD8 */ +#endif + +#ifndef ISP2401 +/* function longjmp: 684E */ +#else +/* function longjmp: 69C1 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_HIVE_IF_SRST_MASK +#define HIVE_MEM_HIVE_IF_SRST_MASK scalar_processor_2400_dmem +#define HIVE_ADDR_HIVE_IF_SRST_MASK 0x1C8 +#define HIVE_SIZE_HIVE_IF_SRST_MASK 16 +#else +#endif +#endif +#define HIVE_MEM_sp_HIVE_IF_SRST_MASK scalar_processor_2400_dmem +#define HIVE_ADDR_sp_HIVE_IF_SRST_MASK 0x1C8 +#define HIVE_SIZE_sp_HIVE_IF_SRST_MASK 16 + +#ifndef ISP2401 +/* function tmpmem_init_dmem: 6580 */ +#else +/* function tmpmem_init_dmem: 66BB */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_token_map_receive_ack: 5EC4 */ +#else +/* function ia_css_isys_sp_token_map_receive_ack: 5FFF */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_set_addr_B: 332C */ +#else +/* function ia_css_dmaproxy_sp_set_addr_B: 3520 */ + +/* function ia_css_pipe_data_init_tagger_resources: A4F */ +#endif + +/* function debug_buffer_set_ddr_addr: DD */ + +#ifndef ISP2401 +/* function receiver_port_reg_load: AC2 */ +#else +/* function receiver_port_reg_load: ABC */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_vbuf_mipi +#define HIVE_MEM_vbuf_mipi scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_vbuf_mipi 0x631C +#else +#define HIVE_ADDR_vbuf_mipi 0x6378 +#endif +#define HIVE_SIZE_vbuf_mipi 12 +#else +#endif +#endif +#define HIVE_MEM_sp_vbuf_mipi scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_vbuf_mipi 0x631C +#else +#define HIVE_ADDR_sp_vbuf_mipi 0x6378 +#endif +#define HIVE_SIZE_sp_vbuf_mipi 12 + +#ifndef ISP2401 +/* function ia_css_event_sp_decode: 351D */ +#else +/* function ia_css_event_sp_decode: 3711 */ +#endif + +#ifndef ISP2401 +/* function ia_css_queue_get_size: 48A5 */ +#else +/* function ia_css_queue_get_size: 4B2D */ +#endif + +#ifndef ISP2401 +/* function ia_css_queue_load: 4EE6 */ +#else +/* function ia_css_queue_load: 5144 */ +#endif + +#ifndef ISP2401 +/* function setjmp: 6857 */ +#else +/* function setjmp: 69CA */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_sp2host_isys_event_queue +#define HIVE_MEM_sem_for_sp2host_isys_event_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_sp2host_isys_event_queue 0x4684 +#else +#define HIVE_ADDR_sem_for_sp2host_isys_event_queue 0x46CC +#endif +#define HIVE_SIZE_sem_for_sp2host_isys_event_queue 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_sp2host_isys_event_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_sp2host_isys_event_queue 0x4684 +#else +#define HIVE_ADDR_sp_sem_for_sp2host_isys_event_queue 0x46CC +#endif +#define HIVE_SIZE_sp_sem_for_sp2host_isys_event_queue 20 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_wait_for_ack: 6E07 */ +#else +/* function ia_css_dmaproxy_sp_wait_for_ack: 6F4B */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_rawcopy_func: 510B */ +#else +/* function ia_css_sp_rawcopy_func: 5369 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_pop_marked: 29F7 */ +#else +/* function ia_css_tagger_buf_sp_pop_marked: 2B99 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isp_stage +#define HIVE_MEM_isp_stage scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isp_stage 0x5C00 +#else +#define HIVE_ADDR_isp_stage 0x5C60 +#endif +#define HIVE_SIZE_isp_stage 832 +#else +#endif +#endif +#define HIVE_MEM_sp_isp_stage scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_stage 0x5C00 +#else +#define HIVE_ADDR_sp_isp_stage 0x5C60 +#endif +#define HIVE_SIZE_sp_isp_stage 832 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_vbuf_raw +#define HIVE_MEM_vbuf_raw scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_vbuf_raw 0x2F4 +#else +#define HIVE_ADDR_vbuf_raw 0x30C +#endif +#define HIVE_SIZE_vbuf_raw 4 +#else +#endif +#endif +#define HIVE_MEM_sp_vbuf_raw scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_vbuf_raw 0x2F4 +#else +#define HIVE_ADDR_sp_vbuf_raw 0x30C +#endif +#define HIVE_SIZE_sp_vbuf_raw 4 + +#ifndef ISP2401 +/* function ia_css_sp_bin_copy_func: 5032 */ +#else +/* function ia_css_sp_bin_copy_func: 5290 */ +#endif + +#ifndef ISP2401 +/* function ia_css_queue_item_store: 4C34 */ +#else +/* function ia_css_queue_item_store: 4E92 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_metadata_bufs +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_metadata_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_metadata_bufs 0x4AA0 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_metadata_bufs 0x4AFC +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_metadata_bufs 20 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_metadata_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_metadata_bufs 0x4AA0 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_metadata_bufs 0x4AFC +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_metadata_bufs 20 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_buffer_bufs +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_buffer_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_buffer_bufs 0x4AB4 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_buffer_bufs 0x4B10 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_buffer_bufs 160 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_buffer_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_buffer_bufs 0x4AB4 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_buffer_bufs 0x4B10 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_buffer_bufs 160 + +/* function sp_start_isp: 45D */ + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_binary_group +#define HIVE_MEM_sp_binary_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_binary_group 0x5FF0 +#else +#define HIVE_ADDR_sp_binary_group 0x6050 +#endif +#define HIVE_SIZE_sp_binary_group 32 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_binary_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_binary_group 0x5FF0 +#else +#define HIVE_ADDR_sp_sp_binary_group 0x6050 +#endif +#define HIVE_SIZE_sp_sp_binary_group 32 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_sw_state +#define HIVE_MEM_sp_sw_state scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sw_state 0x62AC +#else +#define HIVE_ADDR_sp_sw_state 0x6308 +#endif +#define HIVE_SIZE_sp_sw_state 4 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_sw_state scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_sw_state 0x62AC +#else +#define HIVE_ADDR_sp_sp_sw_state 0x6308 +#endif +#define HIVE_SIZE_sp_sp_sw_state 4 + +#ifndef ISP2401 +/* function ia_css_thread_sp_main: D5B */ +#else +/* function ia_css_thread_sp_main: D50 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_init_internal_buffers: 3723 */ +#else +/* function ia_css_ispctrl_sp_init_internal_buffers: 3952 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp2host_psys_event_queue_handle +#define HIVE_MEM_sp2host_psys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp2host_psys_event_queue_handle 0x4B54 +#else +#define HIVE_ADDR_sp2host_psys_event_queue_handle 0x4BB0 +#endif +#define HIVE_SIZE_sp2host_psys_event_queue_handle 12 +#else +#endif +#endif +#define HIVE_MEM_sp_sp2host_psys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp2host_psys_event_queue_handle 0x4B54 +#else +#define HIVE_ADDR_sp_sp2host_psys_event_queue_handle 0x4BB0 +#endif +#define HIVE_SIZE_sp_sp2host_psys_event_queue_handle 12 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_sp2host_psys_event_queue +#define HIVE_MEM_sem_for_sp2host_psys_event_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_sp2host_psys_event_queue 0x4698 +#else +#define HIVE_ADDR_sem_for_sp2host_psys_event_queue 0x46E0 +#endif +#define HIVE_SIZE_sem_for_sp2host_psys_event_queue 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_sp2host_psys_event_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_sp2host_psys_event_queue 0x4698 +#else +#define HIVE_ADDR_sp_sem_for_sp2host_psys_event_queue 0x46E0 +#endif +#define HIVE_SIZE_sp_sem_for_sp2host_psys_event_queue 20 + +#ifndef ISP2401 +/* function ia_css_tagger_sp_propagate_frame: 2410 */ + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_stop_copy_preview +#define HIVE_MEM_sp_stop_copy_preview scalar_processor_2400_dmem +#define HIVE_ADDR_sp_stop_copy_preview 0x6290 +#define HIVE_SIZE_sp_stop_copy_preview 4 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_stop_copy_preview scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_stop_copy_preview 0x6290 +#define HIVE_SIZE_sp_sp_stop_copy_preview 4 +#else +/* function ia_css_tagger_sp_propagate_frame: 2460 */ +#endif + +#ifndef ISP2401 +/* function input_system_reg_load: B17 */ +#else +/* function input_system_reg_load: B11 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_vbuf_handles +#define HIVE_MEM_vbuf_handles scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_vbuf_handles 0x6328 +#else +#define HIVE_ADDR_vbuf_handles 0x6384 +#endif +#define HIVE_SIZE_vbuf_handles 960 +#else +#endif +#endif +#define HIVE_MEM_sp_vbuf_handles scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_vbuf_handles 0x6328 +#else +#define HIVE_ADDR_sp_vbuf_handles 0x6384 +#endif +#define HIVE_SIZE_sp_vbuf_handles 960 + +#ifndef ISP2401 +/* function ia_css_queue_store: 4D9A */ + +/* function ia_css_sp_flash_register: 2C2C */ +#else +/* function ia_css_queue_store: 4FF8 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_rawcopy_dummy_function: 5652 */ +#else +/* function ia_css_sp_flash_register: 2DCE */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_backend_create: 5B37 */ +#else +/* function ia_css_isys_sp_backend_create: 5C72 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_init: 1833 */ +#else +/* function ia_css_pipeline_sp_init: 186D */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_configure: 2300 */ +#else +/* function ia_css_tagger_sp_configure: 2350 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_end_binary: 3566 */ +#else +/* function ia_css_ispctrl_sp_end_binary: 375A */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs +#define HIVE_MEM_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x4B60 +#else +#define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x4BBC +#endif +#define HIVE_SIZE_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 20 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x4B60 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x4BBC +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 20 + +#ifndef ISP2401 +/* function receiver_port_reg_store: AC9 */ +#else +/* function receiver_port_reg_store: AC3 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_event_is_pending_mask +#define HIVE_MEM_event_is_pending_mask scalar_processor_2400_dmem +#define HIVE_ADDR_event_is_pending_mask 0x5C +#define HIVE_SIZE_event_is_pending_mask 44 +#else +#endif +#endif +#define HIVE_MEM_sp_event_is_pending_mask scalar_processor_2400_dmem +#define HIVE_ADDR_sp_event_is_pending_mask 0x5C +#define HIVE_SIZE_sp_event_is_pending_mask 44 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cb_elems_frame +#define HIVE_MEM_sp_all_cb_elems_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cb_elems_frame 0x46AC +#else +#define HIVE_ADDR_sp_all_cb_elems_frame 0x46F4 +#endif +#define HIVE_SIZE_sp_all_cb_elems_frame 16 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cb_elems_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cb_elems_frame 0x46AC +#else +#define HIVE_ADDR_sp_sp_all_cb_elems_frame 0x46F4 +#endif +#define HIVE_SIZE_sp_sp_all_cb_elems_frame 16 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp2host_isys_event_queue_handle +#define HIVE_MEM_sp2host_isys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp2host_isys_event_queue_handle 0x4B74 +#else +#define HIVE_ADDR_sp2host_isys_event_queue_handle 0x4BD0 +#endif +#define HIVE_SIZE_sp2host_isys_event_queue_handle 12 +#else +#endif +#endif +#define HIVE_MEM_sp_sp2host_isys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp2host_isys_event_queue_handle 0x4B74 +#else +#define HIVE_ADDR_sp_sp2host_isys_event_queue_handle 0x4BD0 +#endif +#define HIVE_SIZE_sp_sp2host_isys_event_queue_handle 12 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host_sp_com +#define HIVE_MEM_host_sp_com scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host_sp_com 0x4114 +#else +#define HIVE_ADDR_host_sp_com 0x4134 +#endif +#define HIVE_SIZE_host_sp_com 220 +#else +#endif +#endif +#define HIVE_MEM_sp_host_sp_com scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host_sp_com 0x4114 +#else +#define HIVE_ADDR_sp_host_sp_com 0x4134 +#endif +#define HIVE_SIZE_sp_host_sp_com 220 + +#ifndef ISP2401 +/* function ia_css_queue_get_free_space: 49F9 */ +#else +/* function ia_css_queue_get_free_space: 4C57 */ +#endif + +#ifndef ISP2401 +/* function exec_image_pipe: 6C4 */ +#else +/* function exec_image_pipe: 658 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_init_dmem_data +#define HIVE_MEM_sp_init_dmem_data scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_init_dmem_data 0x62B0 +#else +#define HIVE_ADDR_sp_init_dmem_data 0x630C +#endif +#define HIVE_SIZE_sp_init_dmem_data 24 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_init_dmem_data scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_init_dmem_data 0x62B0 +#else +#define HIVE_ADDR_sp_sp_init_dmem_data 0x630C +#endif +#define HIVE_SIZE_sp_sp_init_dmem_data 24 + +#ifndef ISP2401 +/* function ia_css_sp_metadata_start: 5914 */ +#else +/* function ia_css_sp_metadata_start: 5A4F */ +#endif + +#ifndef ISP2401 +/* function ia_css_bufq_sp_init_buffer_queues: 2C9B */ +#else +/* function ia_css_bufq_sp_init_buffer_queues: 2E3D */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_stop: 1816 */ +#else +/* function ia_css_pipeline_sp_stop: 1850 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_connect_pipes: 27EA */ +#else +/* function ia_css_tagger_sp_connect_pipes: 283A */ +#endif + +#ifndef ISP2401 +/* function sp_isys_copy_wait: 70D */ +#else +/* function sp_isys_copy_wait: 6A1 */ +#endif + +/* function is_isp_debug_buffer_full: 337 */ + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_configure_channel_from_info: 32AF */ +#else +/* function ia_css_dmaproxy_sp_configure_channel_from_info: 3490 */ +#endif + +#ifndef ISP2401 +/* function encode_and_post_timer_event: A30 */ +#else +/* function encode_and_post_timer_event: 9C4 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_per_frame_data +#define HIVE_MEM_sp_per_frame_data scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_per_frame_data 0x41F0 +#else +#define HIVE_ADDR_sp_per_frame_data 0x4210 +#endif +#define HIVE_SIZE_sp_per_frame_data 4 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_per_frame_data scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_per_frame_data 0x41F0 +#else +#define HIVE_ADDR_sp_sp_per_frame_data 0x4210 +#endif +#define HIVE_SIZE_sp_sp_per_frame_data 4 + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_vbuf_dequeue: 62D4 */ +#else +/* function ia_css_rmgr_sp_vbuf_dequeue: 640F */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host2sp_psys_event_queue_handle +#define HIVE_MEM_host2sp_psys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host2sp_psys_event_queue_handle 0x4B80 +#else +#define HIVE_ADDR_host2sp_psys_event_queue_handle 0x4BDC +#endif +#define HIVE_SIZE_host2sp_psys_event_queue_handle 12 +#else +#endif +#endif +#define HIVE_MEM_sp_host2sp_psys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host2sp_psys_event_queue_handle 0x4B80 +#else +#define HIVE_ADDR_sp_host2sp_psys_event_queue_handle 0x4BDC +#endif +#define HIVE_SIZE_sp_host2sp_psys_event_queue_handle 12 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_xmem_bin_addr +#define HIVE_MEM_xmem_bin_addr scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_xmem_bin_addr 0x41F4 +#else +#define HIVE_ADDR_xmem_bin_addr 0x4214 +#endif +#define HIVE_SIZE_xmem_bin_addr 4 +#else +#endif +#endif +#define HIVE_MEM_sp_xmem_bin_addr scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_xmem_bin_addr 0x41F4 +#else +#define HIVE_ADDR_sp_xmem_bin_addr 0x4214 +#endif +#define HIVE_SIZE_sp_xmem_bin_addr 4 + +#ifndef ISP2401 +/* function tmr_clock_init: 65A0 */ +#else +/* function tmr_clock_init: 66DB */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_run: 1403 */ +#else +/* function ia_css_pipeline_sp_run: 1424 */ +#endif + +#ifndef ISP2401 +/* function memcpy: 68F7 */ +#else +/* function memcpy: 6A6A */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_GP_DEVICE_BASE +#define HIVE_MEM_GP_DEVICE_BASE scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_GP_DEVICE_BASE 0x2FC +#else +#define HIVE_ADDR_GP_DEVICE_BASE 0x314 +#endif +#define HIVE_SIZE_GP_DEVICE_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_GP_DEVICE_BASE scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_GP_DEVICE_BASE 0x2FC +#else +#define HIVE_ADDR_sp_GP_DEVICE_BASE 0x314 +#endif +#define HIVE_SIZE_sp_GP_DEVICE_BASE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_thread_sp_ready_queue +#define HIVE_MEM_ia_css_thread_sp_ready_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_thread_sp_ready_queue 0x1E0 +#else +#define HIVE_ADDR_ia_css_thread_sp_ready_queue 0x1E4 +#endif +#define HIVE_SIZE_ia_css_thread_sp_ready_queue 12 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_thread_sp_ready_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_thread_sp_ready_queue 0x1E0 +#else +#define HIVE_ADDR_sp_ia_css_thread_sp_ready_queue 0x1E4 +#endif +#define HIVE_SIZE_sp_ia_css_thread_sp_ready_queue 12 + +#ifndef ISP2401 +/* function input_system_reg_store: B1E */ +#else +/* function input_system_reg_store: B18 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_frontend_start: 5D4D */ +#else +/* function ia_css_isys_sp_frontend_start: 5E88 */ +#endif + +#ifndef ISP2401 +/* function ia_css_uds_sp_scale_params: 6600 */ +#else +/* function ia_css_uds_sp_scale_params: 6773 */ +#endif + +#ifndef ISP2401 +/* function ia_css_circbuf_increase_size: E40 */ +#else +/* function ia_css_circbuf_increase_size: E35 */ +#endif + +#ifndef ISP2401 +/* function __divu: 6875 */ +#else +/* function __divu: 69E8 */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_get_state: C83 */ +#else +/* function ia_css_thread_sp_get_state: C78 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_cont_capt_stop +#define HIVE_MEM_sem_for_cont_capt_stop scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_cont_capt_stop 0x46BC +#else +#define HIVE_ADDR_sem_for_cont_capt_stop 0x4704 +#endif +#define HIVE_SIZE_sem_for_cont_capt_stop 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_cont_capt_stop scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_cont_capt_stop 0x46BC +#else +#define HIVE_ADDR_sp_sem_for_cont_capt_stop 0x4704 +#endif +#define HIVE_SIZE_sp_sem_for_cont_capt_stop 20 + +#ifndef ISP2401 +/* function thread_fiber_sp_main: E39 */ +#else +/* function thread_fiber_sp_main: E2E */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_isp_pipe_thread +#define HIVE_MEM_sp_isp_pipe_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_pipe_thread 0x4800 +#define HIVE_SIZE_sp_isp_pipe_thread 340 +#else +#define HIVE_ADDR_sp_isp_pipe_thread 0x4848 +#define HIVE_SIZE_sp_isp_pipe_thread 360 +#endif +#else +#endif +#endif +#define HIVE_MEM_sp_sp_isp_pipe_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_isp_pipe_thread 0x4800 +#define HIVE_SIZE_sp_sp_isp_pipe_thread 340 +#else +#define HIVE_ADDR_sp_sp_isp_pipe_thread 0x4848 +#define HIVE_SIZE_sp_sp_isp_pipe_thread 360 +#endif + +#ifndef ISP2401 +/* function ia_css_parambuf_sp_handle_parameter_sets: 128A */ +#else +/* function ia_css_parambuf_sp_handle_parameter_sets: 127F */ +#endif + +#ifndef ISP2401 +/* function ia_css_spctrl_sp_set_state: 5943 */ +#else +/* function ia_css_spctrl_sp_set_state: 5A7E */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sem_sp_signal: 6AF7 */ +#else +/* function ia_css_thread_sem_sp_signal: 6C6C */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_IRQ_BASE +#define HIVE_MEM_IRQ_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_IRQ_BASE 0x2C +#define HIVE_SIZE_IRQ_BASE 16 +#else +#endif +#endif +#define HIVE_MEM_sp_IRQ_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_IRQ_BASE 0x2C +#define HIVE_SIZE_sp_IRQ_BASE 16 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_TIMED_CTRL_BASE +#define HIVE_MEM_TIMED_CTRL_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_TIMED_CTRL_BASE 0x40 +#define HIVE_SIZE_TIMED_CTRL_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_TIMED_CTRL_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_TIMED_CTRL_BASE 0x40 +#define HIVE_SIZE_sp_TIMED_CTRL_BASE 4 + +#ifndef ISP2401 +/* function ia_css_isys_sp_isr: 6FDC */ + +/* function ia_css_isys_sp_generate_exp_id: 60E5 */ +#else +/* function ia_css_isys_sp_isr: 7139 */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_init: 61CF */ +#else +/* function ia_css_isys_sp_generate_exp_id: 6220 */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sem_sp_init: 6BC8 */ +#else +/* function ia_css_rmgr_sp_init: 630A */ +#endif + +#ifndef ISP2401 +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_is_isp_requested +#define HIVE_MEM_is_isp_requested scalar_processor_2400_dmem +#define HIVE_ADDR_is_isp_requested 0x308 +#define HIVE_SIZE_is_isp_requested 4 +#else +#endif +#endif +#define HIVE_MEM_sp_is_isp_requested scalar_processor_2400_dmem +#define HIVE_ADDR_sp_is_isp_requested 0x308 +#define HIVE_SIZE_sp_is_isp_requested 4 +#else +/* function ia_css_thread_sem_sp_init: 6D3B */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_reading_cb_frame +#define HIVE_MEM_sem_for_reading_cb_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_reading_cb_frame 0x46D0 +#else +#define HIVE_ADDR_sem_for_reading_cb_frame 0x4718 +#endif +#define HIVE_SIZE_sem_for_reading_cb_frame 40 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_reading_cb_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_reading_cb_frame 0x46D0 +#else +#define HIVE_ADDR_sp_sem_for_reading_cb_frame 0x4718 +#endif +#define HIVE_SIZE_sp_sem_for_reading_cb_frame 40 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_execute: 3217 */ +#else +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_is_isp_requested +#define HIVE_MEM_is_isp_requested scalar_processor_2400_dmem +#define HIVE_ADDR_is_isp_requested 0x320 +#define HIVE_SIZE_is_isp_requested 4 +#else +#endif +#endif +#define HIVE_MEM_sp_is_isp_requested scalar_processor_2400_dmem +#define HIVE_ADDR_sp_is_isp_requested 0x320 +#define HIVE_SIZE_sp_is_isp_requested 4 + +/* function ia_css_dmaproxy_sp_execute: 33F6 */ +#endif + +#ifndef ISP2401 +/* function ia_css_queue_is_empty: 48E0 */ +#else +/* function ia_css_queue_is_empty: 7098 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_has_stopped: 180C */ +#else +/* function ia_css_pipeline_sp_has_stopped: 1846 */ +#endif + +#ifndef ISP2401 +/* function ia_css_circbuf_extract: F44 */ +#else +/* function ia_css_circbuf_extract: F39 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_is_locked_from_start: 2B0D */ +#else +/* function ia_css_tagger_buf_sp_is_locked_from_start: 2CAF */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_current_sp_thread +#define HIVE_MEM_current_sp_thread scalar_processor_2400_dmem +#define HIVE_ADDR_current_sp_thread 0x1DC +#define HIVE_SIZE_current_sp_thread 4 +#else +#endif +#endif +#define HIVE_MEM_sp_current_sp_thread scalar_processor_2400_dmem +#define HIVE_ADDR_sp_current_sp_thread 0x1DC +#define HIVE_SIZE_sp_current_sp_thread 4 + +#ifndef ISP2401 +/* function ia_css_spctrl_sp_get_spid: 594A */ +#else +/* function ia_css_spctrl_sp_get_spid: 5A85 */ +#endif + +#ifndef ISP2401 +/* function ia_css_bufq_sp_reset_buffers: 2D22 */ +#else +/* function ia_css_bufq_sp_reset_buffers: 2EC4 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_read_byte_addr: 6E35 */ +#else +/* function ia_css_dmaproxy_sp_read_byte_addr: 6F79 */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_uninit: 61C8 */ +#else +/* function ia_css_rmgr_sp_uninit: 6303 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_threads_stack +#define HIVE_MEM_sp_threads_stack scalar_processor_2400_dmem +#define HIVE_ADDR_sp_threads_stack 0x164 +#define HIVE_SIZE_sp_threads_stack 28 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_threads_stack scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_threads_stack 0x164 +#define HIVE_SIZE_sp_sp_threads_stack 28 + +#ifndef ISP2401 +/* function ia_css_circbuf_peek: F26 */ +#else +/* function ia_css_circbuf_peek: F1B */ +#endif + +#ifndef ISP2401 +/* function ia_css_parambuf_sp_wait_for_in_param: 1053 */ +#else +/* function ia_css_parambuf_sp_wait_for_in_param: 1048 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_token_map_get_exp_id: 5FAD */ +#else +/* function ia_css_isys_sp_token_map_get_exp_id: 60E8 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cb_elems_param +#define HIVE_MEM_sp_all_cb_elems_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cb_elems_param 0x46F8 +#else +#define HIVE_ADDR_sp_all_cb_elems_param 0x4740 +#endif +#define HIVE_SIZE_sp_all_cb_elems_param 16 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cb_elems_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cb_elems_param 0x46F8 +#else +#define HIVE_ADDR_sp_sp_all_cb_elems_param 0x4740 +#endif +#define HIVE_SIZE_sp_sp_all_cb_elems_param 16 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_pipeline_sp_curr_binary_id +#define HIVE_MEM_pipeline_sp_curr_binary_id scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_pipeline_sp_curr_binary_id 0x1EC +#else +#define HIVE_ADDR_pipeline_sp_curr_binary_id 0x1F0 +#endif +#define HIVE_SIZE_pipeline_sp_curr_binary_id 4 +#else +#endif +#endif +#define HIVE_MEM_sp_pipeline_sp_curr_binary_id scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_pipeline_sp_curr_binary_id 0x1EC +#else +#define HIVE_ADDR_sp_pipeline_sp_curr_binary_id 0x1F0 +#endif +#define HIVE_SIZE_sp_pipeline_sp_curr_binary_id 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cbs_frame_desc +#define HIVE_MEM_sp_all_cbs_frame_desc scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cbs_frame_desc 0x4708 +#else +#define HIVE_ADDR_sp_all_cbs_frame_desc 0x4750 +#endif +#define HIVE_SIZE_sp_all_cbs_frame_desc 8 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cbs_frame_desc scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cbs_frame_desc 0x4708 +#else +#define HIVE_ADDR_sp_sp_all_cbs_frame_desc 0x4750 +#endif +#define HIVE_SIZE_sp_sp_all_cbs_frame_desc 8 + +#ifndef ISP2401 +/* function sp_isys_copy_func_v2: 706 */ +#else +/* function sp_isys_copy_func_v2: 69A */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_reading_cb_param +#define HIVE_MEM_sem_for_reading_cb_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_reading_cb_param 0x4710 +#else +#define HIVE_ADDR_sem_for_reading_cb_param 0x4758 +#endif +#define HIVE_SIZE_sem_for_reading_cb_param 40 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_reading_cb_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_reading_cb_param 0x4710 +#else +#define HIVE_ADDR_sp_sem_for_reading_cb_param 0x4758 +#endif +#define HIVE_SIZE_sp_sem_for_reading_cb_param 40 + +#ifndef ISP2401 +/* function ia_css_queue_get_used_space: 49AD */ +#else +/* function ia_css_queue_get_used_space: 4C0B */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_cont_capt_start +#define HIVE_MEM_sem_for_cont_capt_start scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_cont_capt_start 0x4738 +#else +#define HIVE_ADDR_sem_for_cont_capt_start 0x4780 +#endif +#define HIVE_SIZE_sem_for_cont_capt_start 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_cont_capt_start scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_cont_capt_start 0x4738 +#else +#define HIVE_ADDR_sp_sem_for_cont_capt_start 0x4780 +#endif +#define HIVE_SIZE_sp_sem_for_cont_capt_start 20 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_tmp_heap +#define HIVE_MEM_tmp_heap scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_tmp_heap 0x6010 +#else +#define HIVE_ADDR_tmp_heap 0x6070 +#endif +#define HIVE_SIZE_tmp_heap 640 +#else +#endif +#endif +#define HIVE_MEM_sp_tmp_heap scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_tmp_heap 0x6010 +#else +#define HIVE_ADDR_sp_tmp_heap 0x6070 +#endif +#define HIVE_SIZE_sp_tmp_heap 640 + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_get_num_vbuf: 64D8 */ +#else +/* function ia_css_rmgr_sp_get_num_vbuf: 6613 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_output_compute_dma_info: 3F49 */ +#else +/* function ia_css_ispctrl_sp_output_compute_dma_info: 418C */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_lock_exp_id: 20CD */ +#else +/* function ia_css_tagger_sp_lock_exp_id: 211D */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_s3a_bufs +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_s3a_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_s3a_bufs 0x4B8C +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_s3a_bufs 0x4BE8 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_s3a_bufs 60 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_s3a_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_s3a_bufs 0x4B8C +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_s3a_bufs 0x4BE8 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_s3a_bufs 60 + +#ifndef ISP2401 +/* function ia_css_queue_is_full: 4A44 */ +#else +/* function ia_css_queue_is_full: 4CA2 */ +#endif + +/* function debug_buffer_init_isp: E4 */ + +#ifndef ISP2401 +/* function ia_css_isys_sp_frontend_uninit: 5D07 */ +#else +/* function ia_css_isys_sp_frontend_uninit: 5E42 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_exp_id_is_locked: 2003 */ +#else +/* function ia_css_tagger_sp_exp_id_is_locked: 2053 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_rmgr_sp_mipi_frame_sem +#define HIVE_MEM_ia_css_rmgr_sp_mipi_frame_sem scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_rmgr_sp_mipi_frame_sem 0x66E8 +#else +#define HIVE_ADDR_ia_css_rmgr_sp_mipi_frame_sem 0x6744 +#endif +#define HIVE_SIZE_ia_css_rmgr_sp_mipi_frame_sem 60 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_rmgr_sp_mipi_frame_sem scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_rmgr_sp_mipi_frame_sem 0x66E8 +#else +#define HIVE_ADDR_sp_ia_css_rmgr_sp_mipi_frame_sem 0x6744 +#endif +#define HIVE_SIZE_sp_ia_css_rmgr_sp_mipi_frame_sem 60 + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_refcount_dump: 62AF */ +#else +/* function ia_css_rmgr_sp_refcount_dump: 63EA */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_isp_parameters_id +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_isp_parameters_id scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x4BC8 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x4C24 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_isp_parameters_id 20 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x4BC8 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x4C24 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id 20 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_pipe_threads +#define HIVE_MEM_sp_pipe_threads scalar_processor_2400_dmem +#define HIVE_ADDR_sp_pipe_threads 0x150 +#define HIVE_SIZE_sp_pipe_threads 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_pipe_threads scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_pipe_threads 0x150 +#define HIVE_SIZE_sp_sp_pipe_threads 20 + +#ifndef ISP2401 +/* function sp_event_proxy_func: 71B */ +#else +/* function sp_event_proxy_func: 6AF */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host2sp_isys_event_queue_handle +#define HIVE_MEM_host2sp_isys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host2sp_isys_event_queue_handle 0x4BDC +#else +#define HIVE_ADDR_host2sp_isys_event_queue_handle 0x4C38 +#endif +#define HIVE_SIZE_host2sp_isys_event_queue_handle 12 +#else +#endif +#endif +#define HIVE_MEM_sp_host2sp_isys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host2sp_isys_event_queue_handle 0x4BDC +#else +#define HIVE_ADDR_sp_host2sp_isys_event_queue_handle 0x4C38 +#endif +#define HIVE_SIZE_sp_host2sp_isys_event_queue_handle 12 + +#ifndef ISP2401 +/* function ia_css_thread_sp_yield: 6A70 */ +#else +/* function ia_css_thread_sp_yield: 6BEA */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cbs_param_desc +#define HIVE_MEM_sp_all_cbs_param_desc scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cbs_param_desc 0x474C +#else +#define HIVE_ADDR_sp_all_cbs_param_desc 0x4794 +#endif +#define HIVE_SIZE_sp_all_cbs_param_desc 8 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cbs_param_desc scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cbs_param_desc 0x474C +#else +#define HIVE_ADDR_sp_sp_all_cbs_param_desc 0x4794 +#endif +#define HIVE_SIZE_sp_sp_all_cbs_param_desc 8 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_dmaproxy_sp_invalidate_tlb +#define HIVE_MEM_ia_css_dmaproxy_sp_invalidate_tlb scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb 0x5BF4 +#else +#define HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb 0x5C50 +#endif +#define HIVE_SIZE_ia_css_dmaproxy_sp_invalidate_tlb 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_dmaproxy_sp_invalidate_tlb scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_dmaproxy_sp_invalidate_tlb 0x5BF4 +#else +#define HIVE_ADDR_sp_ia_css_dmaproxy_sp_invalidate_tlb 0x5C50 +#endif +#define HIVE_SIZE_sp_ia_css_dmaproxy_sp_invalidate_tlb 4 + +#ifndef ISP2401 +/* function ia_css_thread_sp_fork: D10 */ +#else +/* function ia_css_thread_sp_fork: D05 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_destroy: 27F4 */ +#else +/* function ia_css_tagger_sp_destroy: 2844 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_vmem_read: 31B7 */ +#else +/* function ia_css_dmaproxy_sp_vmem_read: 3396 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ifmtr_sp_init: 6136 */ +#else +/* function ia_css_ifmtr_sp_init: 6271 */ +#endif + +#ifndef ISP2401 +/* function initialize_sp_group: 6D4 */ +#else +/* function initialize_sp_group: 668 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_peek: 2919 */ +#else +/* function ia_css_tagger_buf_sp_peek: 2ABB */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_init: D3C */ +#else +/* function ia_css_thread_sp_init: D31 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_reset_exp_id: 60DD */ +#else +/* function ia_css_isys_sp_reset_exp_id: 6218 */ +#endif + +#ifndef ISP2401 +/* function qos_scheduler_update_fps: 65F0 */ +#else +/* function qos_scheduler_update_fps: 6763 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_set_stream_base_addr: 461E */ +#else +/* function ia_css_ispctrl_sp_set_stream_base_addr: 4879 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_DMEM_BASE +#define HIVE_MEM_ISP_DMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_ISP_DMEM_BASE 0x10 +#define HIVE_SIZE_ISP_DMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_DMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ISP_DMEM_BASE 0x10 +#define HIVE_SIZE_sp_ISP_DMEM_BASE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_SP_DMEM_BASE +#define HIVE_MEM_SP_DMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_SP_DMEM_BASE 0x4 +#define HIVE_SIZE_SP_DMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_SP_DMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_SP_DMEM_BASE 0x4 +#define HIVE_SIZE_sp_SP_DMEM_BASE 4 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_read: 322D */ +#else +/* function __ia_css_queue_is_empty_text: 4B68 */ + +/* function ia_css_dmaproxy_sp_read: 340C */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_raw_copy_line_count +#define HIVE_MEM_raw_copy_line_count scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_raw_copy_line_count 0x2C8 +#else +#define HIVE_ADDR_raw_copy_line_count 0x2E0 +#endif +#define HIVE_SIZE_raw_copy_line_count 4 +#else +#endif +#endif +#define HIVE_MEM_sp_raw_copy_line_count scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_raw_copy_line_count 0x2C8 +#else +#define HIVE_ADDR_sp_raw_copy_line_count 0x2E0 +#endif +#define HIVE_SIZE_sp_raw_copy_line_count 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host2sp_tag_cmd_queue_handle +#define HIVE_MEM_host2sp_tag_cmd_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host2sp_tag_cmd_queue_handle 0x4BE8 +#else +#define HIVE_ADDR_host2sp_tag_cmd_queue_handle 0x4C44 +#endif +#define HIVE_SIZE_host2sp_tag_cmd_queue_handle 12 +#else +#endif +#endif +#define HIVE_MEM_sp_host2sp_tag_cmd_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host2sp_tag_cmd_queue_handle 0x4BE8 +#else +#define HIVE_ADDR_sp_host2sp_tag_cmd_queue_handle 0x4C44 +#endif +#define HIVE_SIZE_sp_host2sp_tag_cmd_queue_handle 12 + +#ifndef ISP2401 +/* function ia_css_queue_peek: 4923 */ +#else +/* function ia_css_queue_peek: 4B81 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_flash_sp_frame_cnt +#define HIVE_MEM_ia_css_flash_sp_frame_cnt scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_flash_sp_frame_cnt 0x4A94 +#else +#define HIVE_ADDR_ia_css_flash_sp_frame_cnt 0x4AF0 +#endif +#define HIVE_SIZE_ia_css_flash_sp_frame_cnt 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_flash_sp_frame_cnt scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_flash_sp_frame_cnt 0x4A94 +#else +#define HIVE_ADDR_sp_ia_css_flash_sp_frame_cnt 0x4AF0 +#endif +#define HIVE_SIZE_sp_ia_css_flash_sp_frame_cnt 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_event_can_send_token_mask +#define HIVE_MEM_event_can_send_token_mask scalar_processor_2400_dmem +#define HIVE_ADDR_event_can_send_token_mask 0x88 +#define HIVE_SIZE_event_can_send_token_mask 44 +#else +#endif +#endif +#define HIVE_MEM_sp_event_can_send_token_mask scalar_processor_2400_dmem +#define HIVE_ADDR_sp_event_can_send_token_mask 0x88 +#define HIVE_SIZE_sp_event_can_send_token_mask 44 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isp_thread +#define HIVE_MEM_isp_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isp_thread 0x5F40 +#else +#define HIVE_ADDR_isp_thread 0x5FA0 +#endif +#define HIVE_SIZE_isp_thread 4 +#else +#endif +#endif +#define HIVE_MEM_sp_isp_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_thread 0x5F40 +#else +#define HIVE_ADDR_sp_isp_thread 0x5FA0 +#endif +#define HIVE_SIZE_sp_isp_thread 4 + +#ifndef ISP2401 +/* function encode_and_post_sp_event_non_blocking: A78 */ +#else +/* function encode_and_post_sp_event_non_blocking: A0C */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_frontend_destroy: 5DDF */ +#else +/* function ia_css_isys_sp_frontend_destroy: 5F1A */ +#endif + +/* function is_ddr_debug_buffer_full: 2CC */ + +#ifndef ISP2401 +/* function ia_css_isys_sp_frontend_stop: 5D1F */ +#else +/* function ia_css_isys_sp_frontend_stop: 5E5A */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_token_map_init: 607B */ +#else +/* function ia_css_isys_sp_token_map_init: 61B6 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_get_oldest_marked_offset: 2969 */ +#else +/* function ia_css_tagger_buf_sp_get_oldest_marked_offset: 2B0B */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_threads_fiber +#define HIVE_MEM_sp_threads_fiber scalar_processor_2400_dmem +#define HIVE_ADDR_sp_threads_fiber 0x19C +#define HIVE_SIZE_sp_threads_fiber 28 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_threads_fiber scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_threads_fiber 0x19C +#define HIVE_SIZE_sp_sp_threads_fiber 28 + +#ifndef ISP2401 +/* function encode_and_post_sp_event: A01 */ +#else +/* function encode_and_post_sp_event: 995 */ +#endif + +/* function debug_enqueue_ddr: EE */ + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_refcount_init_vbuf: 626A */ +#else +/* function ia_css_rmgr_sp_refcount_init_vbuf: 63A5 */ +#endif + +#ifndef ISP2401 +/* function dmaproxy_sp_read_write: 6EE4 */ +#else +/* function dmaproxy_sp_read_write: 7017 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_dmaproxy_isp_dma_cmd_buffer +#define HIVE_MEM_ia_css_dmaproxy_isp_dma_cmd_buffer scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_dmaproxy_isp_dma_cmd_buffer 0x5BF8 +#else +#define HIVE_ADDR_ia_css_dmaproxy_isp_dma_cmd_buffer 0x5C54 +#endif +#define HIVE_SIZE_ia_css_dmaproxy_isp_dma_cmd_buffer 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_dmaproxy_isp_dma_cmd_buffer scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_dmaproxy_isp_dma_cmd_buffer 0x5BF8 +#else +#define HIVE_ADDR_sp_ia_css_dmaproxy_isp_dma_cmd_buffer 0x5C54 +#endif +#define HIVE_SIZE_sp_ia_css_dmaproxy_isp_dma_cmd_buffer 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host2sp_buffer_queue_handle +#define HIVE_MEM_host2sp_buffer_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host2sp_buffer_queue_handle 0x4BF4 +#else +#define HIVE_ADDR_host2sp_buffer_queue_handle 0x4C50 +#endif +#define HIVE_SIZE_host2sp_buffer_queue_handle 480 +#else +#endif +#endif +#define HIVE_MEM_sp_host2sp_buffer_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host2sp_buffer_queue_handle 0x4BF4 +#else +#define HIVE_ADDR_sp_host2sp_buffer_queue_handle 0x4C50 +#endif +#define HIVE_SIZE_sp_host2sp_buffer_queue_handle 480 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_flash_sp_in_service +#define HIVE_MEM_ia_css_flash_sp_in_service scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_flash_sp_in_service 0x3178 +#else +#define HIVE_ADDR_ia_css_flash_sp_in_service 0x3198 +#endif +#define HIVE_SIZE_ia_css_flash_sp_in_service 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_flash_sp_in_service scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_flash_sp_in_service 0x3178 +#else +#define HIVE_ADDR_sp_ia_css_flash_sp_in_service 0x3198 +#endif +#define HIVE_SIZE_sp_ia_css_flash_sp_in_service 4 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_process: 6BF0 */ +#else +/* function ia_css_dmaproxy_sp_process: 6D63 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_mark_from_end: 2BF1 */ +#else +/* function ia_css_tagger_buf_sp_mark_from_end: 2D93 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_backend_rcv_acquire_ack: 59EC */ +#else +/* function ia_css_isys_sp_backend_rcv_acquire_ack: 5B27 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_backend_pre_acquire_request: 5A02 */ +#else +/* function ia_css_isys_sp_backend_pre_acquire_request: 5B3D */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_init_cs: 3653 */ +#else +/* function ia_css_ispctrl_sp_init_cs: 3855 */ +#endif + +#ifndef ISP2401 +/* function ia_css_spctrl_sp_init: 5958 */ +#else +/* function ia_css_spctrl_sp_init: 5A93 */ +#endif + +#ifndef ISP2401 +/* function sp_event_proxy_init: 730 */ +#else +/* function sp_event_proxy_init: 6C4 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_previous_clock_tick +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_previous_clock_tick scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x4DD4 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x4E30 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_previous_clock_tick 40 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x4DD4 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x4E30 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick 40 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_output +#define HIVE_MEM_sp_output scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_output 0x41F8 +#else +#define HIVE_ADDR_sp_output 0x4218 +#endif +#define HIVE_SIZE_sp_output 16 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_output scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_output 0x41F8 +#else +#define HIVE_ADDR_sp_sp_output 0x4218 +#endif +#define HIVE_SIZE_sp_sp_output 16 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_sems_for_host2sp_buf_queues +#define HIVE_MEM_ia_css_bufq_sp_sems_for_host2sp_buf_queues scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x4DFC +#else +#define HIVE_ADDR_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x4E58 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_sems_for_host2sp_buf_queues 800 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x4DFC +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x4E58 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues 800 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_CTRL_BASE +#define HIVE_MEM_ISP_CTRL_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_ISP_CTRL_BASE 0x8 +#define HIVE_SIZE_ISP_CTRL_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_CTRL_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ISP_CTRL_BASE 0x8 +#define HIVE_SIZE_sp_ISP_CTRL_BASE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_INPUT_FORMATTER_BASE +#define HIVE_MEM_INPUT_FORMATTER_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_INPUT_FORMATTER_BASE 0x4C +#define HIVE_SIZE_INPUT_FORMATTER_BASE 16 +#else +#endif +#endif +#define HIVE_MEM_sp_INPUT_FORMATTER_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_INPUT_FORMATTER_BASE 0x4C +#define HIVE_SIZE_sp_INPUT_FORMATTER_BASE 16 + +#ifndef ISP2401 +/* function sp_dma_proxy_reset_channels: 3487 */ +#else +/* function sp_dma_proxy_reset_channels: 367B */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_backend_acquire: 5B0D */ +#else +/* function ia_css_isys_sp_backend_acquire: 5C48 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_update_size: 28E8 */ +#else +/* function ia_css_tagger_sp_update_size: 2A8A */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_host_sp_queue +#define HIVE_MEM_ia_css_bufq_host_sp_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_host_sp_queue 0x511C +#else +#define HIVE_ADDR_ia_css_bufq_host_sp_queue 0x5178 +#endif +#define HIVE_SIZE_ia_css_bufq_host_sp_queue 2008 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_host_sp_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_host_sp_queue 0x511C +#else +#define HIVE_ADDR_sp_ia_css_bufq_host_sp_queue 0x5178 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_host_sp_queue 2008 + +#ifndef ISP2401 +/* function thread_fiber_sp_create: DA8 */ +#else +/* function thread_fiber_sp_create: D9D */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_set_increments: 3319 */ +#else +/* function ia_css_dmaproxy_sp_set_increments: 350D */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_writing_cb_frame +#define HIVE_MEM_sem_for_writing_cb_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_writing_cb_frame 0x4754 +#else +#define HIVE_ADDR_sem_for_writing_cb_frame 0x479C +#endif +#define HIVE_SIZE_sem_for_writing_cb_frame 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_writing_cb_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_writing_cb_frame 0x4754 +#else +#define HIVE_ADDR_sp_sem_for_writing_cb_frame 0x479C +#endif +#define HIVE_SIZE_sp_sem_for_writing_cb_frame 20 + +#ifndef ISP2401 +/* function receiver_reg_store: AD7 */ +#else +/* function receiver_reg_store: AD1 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_writing_cb_param +#define HIVE_MEM_sem_for_writing_cb_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_writing_cb_param 0x4768 +#else +#define HIVE_ADDR_sem_for_writing_cb_param 0x47B0 +#endif +#define HIVE_SIZE_sem_for_writing_cb_param 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_writing_cb_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_writing_cb_param 0x4768 +#else +#define HIVE_ADDR_sp_sem_for_writing_cb_param 0x47B0 +#endif +#define HIVE_SIZE_sp_sem_for_writing_cb_param 20 + +/* function sp_start_isp_entry: 453 */ +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifdef HIVE_ADDR_sp_start_isp_entry +#endif +#define HIVE_ADDR_sp_start_isp_entry 0x453 +#endif +#define HIVE_ADDR_sp_sp_start_isp_entry 0x453 + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_unmark_all: 2B75 */ +#else +/* function ia_css_tagger_buf_sp_unmark_all: 2D17 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_unmark_from_start: 2BB6 */ +#else +/* function ia_css_tagger_buf_sp_unmark_from_start: 2D58 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_channel_acquire: 34B3 */ +#else +/* function ia_css_dmaproxy_sp_channel_acquire: 36A7 */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_add_num_vbuf: 64B4 */ +#else +/* function ia_css_rmgr_sp_add_num_vbuf: 65EF */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_token_map_create: 60C4 */ +#else +/* function ia_css_isys_sp_token_map_create: 61FF */ +#endif + +#ifndef ISP2401 +/* function __ia_css_dmaproxy_sp_wait_for_ack_text: 3183 */ +#else +/* function __ia_css_dmaproxy_sp_wait_for_ack_text: 3362 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_acquire_buf_elem: 1FDB */ +#else +/* function ia_css_tagger_sp_acquire_buf_elem: 202B */ +#endif + +#ifndef ISP2401 +/* function ia_css_bufq_sp_is_dynamic_buffer: 306C */ +#else +/* function ia_css_bufq_sp_is_dynamic_buffer: 320E */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_group +#define HIVE_MEM_sp_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_group 0x4208 +#define HIVE_SIZE_sp_group 1144 +#else +#define HIVE_ADDR_sp_group 0x4228 +#define HIVE_SIZE_sp_group 1184 +#endif +#else +#endif +#endif +#define HIVE_MEM_sp_sp_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_group 0x4208 +#define HIVE_SIZE_sp_sp_group 1144 +#else +#define HIVE_ADDR_sp_sp_group 0x4228 +#define HIVE_SIZE_sp_sp_group 1184 +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_event_proxy_thread +#define HIVE_MEM_sp_event_proxy_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_event_proxy_thread 0x4954 +#define HIVE_SIZE_sp_event_proxy_thread 68 +#else +#define HIVE_ADDR_sp_event_proxy_thread 0x49B0 +#define HIVE_SIZE_sp_event_proxy_thread 72 +#endif +#else +#endif +#endif +#define HIVE_MEM_sp_sp_event_proxy_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_event_proxy_thread 0x4954 +#define HIVE_SIZE_sp_sp_event_proxy_thread 68 +#else +#define HIVE_ADDR_sp_sp_event_proxy_thread 0x49B0 +#define HIVE_SIZE_sp_sp_event_proxy_thread 72 +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_kill: CD6 */ +#else +/* function ia_css_thread_sp_kill: CCB */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_create: 28A2 */ +#else +/* function ia_css_tagger_sp_create: 2A38 */ +#endif + +#ifndef ISP2401 +/* function tmpmem_acquire_dmem: 6561 */ +#else +/* function tmpmem_acquire_dmem: 669C */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_MMU_BASE +#define HIVE_MEM_MMU_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_MMU_BASE 0x24 +#define HIVE_SIZE_MMU_BASE 8 +#else +#endif +#endif +#define HIVE_MEM_sp_MMU_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_MMU_BASE 0x24 +#define HIVE_SIZE_sp_MMU_BASE 8 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_channel_release: 349F */ +#else +/* function ia_css_dmaproxy_sp_channel_release: 3693 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_is_idle: 347F */ +#else +/* function ia_css_dmaproxy_sp_is_idle: 3673 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_qos_start +#define HIVE_MEM_sem_for_qos_start scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_qos_start 0x477C +#else +#define HIVE_ADDR_sem_for_qos_start 0x47C4 +#endif +#define HIVE_SIZE_sem_for_qos_start 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_qos_start scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_qos_start 0x477C +#else +#define HIVE_ADDR_sp_sem_for_qos_start 0x47C4 +#endif +#define HIVE_SIZE_sp_sem_for_qos_start 20 + +#ifndef ISP2401 +/* function isp_hmem_load: B55 */ +#else +/* function isp_hmem_load: B4F */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_release_buf_elem: 1FB7 */ +#else +/* function ia_css_tagger_sp_release_buf_elem: 2007 */ +#endif + +#ifndef ISP2401 +/* function ia_css_eventq_sp_send: 34F5 */ +#else +/* function ia_css_eventq_sp_send: 36E9 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_isys_sp_error_cnt +#define HIVE_MEM_ia_css_isys_sp_error_cnt scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_isys_sp_error_cnt 0x62D4 +#else +#define HIVE_ADDR_ia_css_isys_sp_error_cnt 0x6330 +#endif +#define HIVE_SIZE_ia_css_isys_sp_error_cnt 16 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_isys_sp_error_cnt scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_isys_sp_error_cnt 0x62D4 +#else +#define HIVE_ADDR_sp_ia_css_isys_sp_error_cnt 0x6330 +#endif +#define HIVE_SIZE_sp_ia_css_isys_sp_error_cnt 16 + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_unlock_from_start: 2AA5 */ +#else +/* function ia_css_tagger_buf_sp_unlock_from_start: 2C47 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_debug_buffer_ddr_address +#define HIVE_MEM_debug_buffer_ddr_address scalar_processor_2400_dmem +#define HIVE_ADDR_debug_buffer_ddr_address 0xBC +#define HIVE_SIZE_debug_buffer_ddr_address 4 +#else +#endif +#endif +#define HIVE_MEM_sp_debug_buffer_ddr_address scalar_processor_2400_dmem +#define HIVE_ADDR_sp_debug_buffer_ddr_address 0xBC +#define HIVE_SIZE_sp_debug_buffer_ddr_address 4 + +#ifndef ISP2401 +/* function sp_isys_copy_request: 714 */ +#else +/* function sp_isys_copy_request: 6A8 */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_refcount_retain_vbuf: 6344 */ +#else +/* function ia_css_rmgr_sp_refcount_retain_vbuf: 647F */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_set_priority: CCE */ +#else +/* function ia_css_thread_sp_set_priority: CC3 */ +#endif + +#ifndef ISP2401 +/* function sizeof_hmem: BFC */ +#else +/* function sizeof_hmem: BF6 */ +#endif + +#ifndef ISP2401 +/* function tmpmem_release_dmem: 6550 */ +#else +/* function tmpmem_release_dmem: 668B */ +#endif + +/* function cnd_input_system_cfg: 392 */ + +#ifndef ISP2401 +/* function __ia_css_sp_rawcopy_func_critical: 6F65 */ +#else +/* function __ia_css_sp_rawcopy_func_critical: 70C2 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_set_width_exception: 3304 */ +#else +/* function __ia_css_dmaproxy_sp_process_text: 3306 */ +#endif + +#ifndef ISP2401 +/* function sp_event_assert: 8B1 */ +#else +/* function ia_css_dmaproxy_sp_set_width_exception: 34F8 */ +#endif + +#ifndef ISP2401 +/* function ia_css_flash_sp_init_internal_params: 2C90 */ +#else +/* function sp_event_assert: 845 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_pop_unmarked_and_unlocked: 29AB */ +#else +/* function ia_css_flash_sp_init_internal_params: 2E32 */ +#endif + +#ifndef ISP2401 +/* function __modu: 68BB */ +#else +/* function ia_css_tagger_buf_sp_pop_unmarked_and_unlocked: 2B4D */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_init_isp_vector: 3189 */ +#else +/* function __modu: 6A2E */ + +/* function ia_css_dmaproxy_sp_init_isp_vector: 3368 */ +#endif + +/* function isp_vamem_store: 0 */ + +#ifdef ISP2401 +/* function ia_css_tagger_sp_set_copy_pipe: 2A2F */ + +#endif +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_GDC_BASE +#define HIVE_MEM_GDC_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_GDC_BASE 0x44 +#define HIVE_SIZE_GDC_BASE 8 +#else +#endif +#endif +#define HIVE_MEM_sp_GDC_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_GDC_BASE 0x44 +#define HIVE_SIZE_sp_GDC_BASE 8 + +#ifndef ISP2401 +/* function ia_css_queue_local_init: 4C0E */ +#else +/* function ia_css_queue_local_init: 4E6C */ +#endif + +#ifndef ISP2401 +/* function sp_event_proxy_callout_func: 6988 */ +#else +/* function sp_event_proxy_callout_func: 6AFB */ +#endif + +#ifndef ISP2401 +/* function qos_scheduler_schedule_stage: 65C1 */ +#else +/* function qos_scheduler_schedule_stage: 670F */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_thread_sp_num_ready_threads +#define HIVE_MEM_ia_css_thread_sp_num_ready_threads scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_thread_sp_num_ready_threads 0x49E0 +#else +#define HIVE_ADDR_ia_css_thread_sp_num_ready_threads 0x4A40 +#endif +#define HIVE_SIZE_ia_css_thread_sp_num_ready_threads 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_thread_sp_num_ready_threads scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_thread_sp_num_ready_threads 0x49E0 +#else +#define HIVE_ADDR_sp_ia_css_thread_sp_num_ready_threads 0x4A40 +#endif +#define HIVE_SIZE_sp_ia_css_thread_sp_num_ready_threads 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_threads_stack_size +#define HIVE_MEM_sp_threads_stack_size scalar_processor_2400_dmem +#define HIVE_ADDR_sp_threads_stack_size 0x180 +#define HIVE_SIZE_sp_threads_stack_size 28 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_threads_stack_size scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_threads_stack_size 0x180 +#define HIVE_SIZE_sp_sp_threads_stack_size 28 + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_isp_done_row_striping: 3F2F */ +#else +/* function ia_css_ispctrl_sp_isp_done_row_striping: 4172 */ +#endif + +#ifndef ISP2401 +/* function __ia_css_isys_sp_isr_text: 5E09 */ +#else +/* function __ia_css_isys_sp_isr_text: 5F44 */ +#endif + +#ifndef ISP2401 +/* function ia_css_queue_dequeue: 4A8C */ +#else +/* function ia_css_queue_dequeue: 4CEA */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_configure_channel: 6E4C */ +#else +/* function is_qos_standalone_mode: 66EA */ + +/* function ia_css_dmaproxy_sp_configure_channel: 6F90 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_current_thread_fiber_sp +#define HIVE_MEM_current_thread_fiber_sp scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_current_thread_fiber_sp 0x49E8 +#else +#define HIVE_ADDR_current_thread_fiber_sp 0x4A44 +#endif +#define HIVE_SIZE_current_thread_fiber_sp 4 +#else +#endif +#endif +#define HIVE_MEM_sp_current_thread_fiber_sp scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_current_thread_fiber_sp 0x49E8 +#else +#define HIVE_ADDR_sp_current_thread_fiber_sp 0x4A44 +#endif +#define HIVE_SIZE_sp_current_thread_fiber_sp 4 + +#ifndef ISP2401 +/* function ia_css_circbuf_pop: FD8 */ +#else +/* function ia_css_circbuf_pop: FCD */ +#endif + +#ifndef ISP2401 +/* function memset: 693A */ +#else +/* function memset: 6AAD */ +#endif + +/* function irq_raise_set_token: B6 */ + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_GPIO_BASE +#define HIVE_MEM_GPIO_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_GPIO_BASE 0x3C +#define HIVE_SIZE_GPIO_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_GPIO_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_GPIO_BASE 0x3C +#define HIVE_SIZE_sp_GPIO_BASE 4 + +#ifndef ISP2401 +/* function ia_css_pipeline_acc_stage_enable: 17D7 */ +#else +/* function ia_css_pipeline_acc_stage_enable: 17FF */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_unlock_exp_id: 2028 */ +#else +/* function ia_css_tagger_sp_unlock_exp_id: 2078 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isp_ph +#define HIVE_MEM_isp_ph scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isp_ph 0x62E4 +#else +#define HIVE_ADDR_isp_ph 0x6340 +#endif +#define HIVE_SIZE_isp_ph 28 +#else +#endif +#endif +#define HIVE_MEM_sp_isp_ph scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_ph 0x62E4 +#else +#define HIVE_ADDR_sp_isp_ph 0x6340 +#endif +#define HIVE_SIZE_sp_isp_ph 28 + +#ifndef ISP2401 +/* function ia_css_isys_sp_token_map_flush: 6009 */ +#else +/* function ia_css_isys_sp_token_map_flush: 6144 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_init_ds: 37B2 */ +#else +/* function ia_css_ispctrl_sp_init_ds: 39E1 */ +#endif + +#ifndef ISP2401 +/* function get_xmem_base_addr_raw: 3B5F */ +#else +/* function get_xmem_base_addr_raw: 3D9A */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cbs_param +#define HIVE_MEM_sp_all_cbs_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cbs_param 0x4790 +#else +#define HIVE_ADDR_sp_all_cbs_param 0x47D8 +#endif +#define HIVE_SIZE_sp_all_cbs_param 16 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cbs_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cbs_param 0x4790 +#else +#define HIVE_ADDR_sp_sp_all_cbs_param 0x47D8 +#endif +#define HIVE_SIZE_sp_sp_all_cbs_param 16 + +#ifndef ISP2401 +/* function ia_css_circbuf_create: 1026 */ +#else +/* function ia_css_circbuf_create: 101B */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_sp_group +#define HIVE_MEM_sem_for_sp_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_sp_group 0x47A0 +#else +#define HIVE_ADDR_sem_for_sp_group 0x47E8 +#endif +#define HIVE_SIZE_sem_for_sp_group 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_sp_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_sp_group 0x47A0 +#else +#define HIVE_ADDR_sp_sem_for_sp_group 0x47E8 +#endif +#define HIVE_SIZE_sp_sem_for_sp_group 20 + +#ifndef ISP2401 +/* function ia_css_framebuf_sp_wait_for_in_frame: 64DF */ +#else +/* function __ia_css_dmaproxy_sp_configure_channel_text: 34D7 */ + +/* function ia_css_framebuf_sp_wait_for_in_frame: 661A */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_rawcopy_tag_frame: 556F */ +#else +/* function ia_css_sp_rawcopy_tag_frame: 57B0 */ +#endif + +#ifndef ISP2401 +/* function isp_hmem_clear: B25 */ +#else +/* function isp_hmem_clear: B1F */ +#endif + +#ifndef ISP2401 +/* function ia_css_framebuf_sp_release_in_frame: 6522 */ +#else +/* function ia_css_framebuf_sp_release_in_frame: 665D */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_backend_snd_acquire_request: 5A5F */ +#else +/* function ia_css_isys_sp_backend_snd_acquire_request: 5B9A */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_token_map_is_full: 5E90 */ +#else +/* function ia_css_isys_sp_token_map_is_full: 5FCB */ +#endif + +#ifndef ISP2401 +/* function input_system_acquisition_run: AF9 */ +#else +/* function input_system_acquisition_run: AF3 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_start_binary: 3631 */ +#else +/* function ia_css_ispctrl_sp_start_binary: 3833 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_h_pipe_private_ddr_ptrs +#define HIVE_MEM_ia_css_bufq_sp_h_pipe_private_ddr_ptrs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x58F4 +#else +#define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x5950 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 20 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x58F4 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x5950 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 20 + +#ifndef ISP2401 +/* function ia_css_eventq_sp_recv: 34C7 */ +#else +/* function ia_css_eventq_sp_recv: 36BB */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isp_pool +#define HIVE_MEM_isp_pool scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isp_pool 0x2E8 +#else +#define HIVE_ADDR_isp_pool 0x300 +#endif +#define HIVE_SIZE_isp_pool 4 +#else +#endif +#endif +#define HIVE_MEM_sp_isp_pool scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_pool 0x2E8 +#else +#define HIVE_ADDR_sp_isp_pool 0x300 +#endif +#define HIVE_SIZE_sp_isp_pool 4 + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_rel_gen: 6211 */ +#else +/* function ia_css_rmgr_sp_rel_gen: 634C */ + +/* function ia_css_tagger_sp_unblock_clients: 2900 */ +#endif + +#ifndef ISP2401 +/* function css_get_frame_processing_time_end: 1FA7 */ +#else +/* function css_get_frame_processing_time_end: 1FF7 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_event_any_pending_mask +#define HIVE_MEM_event_any_pending_mask scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_event_any_pending_mask 0x300 +#else +#define HIVE_ADDR_event_any_pending_mask 0x318 +#endif +#define HIVE_SIZE_event_any_pending_mask 8 +#else +#endif +#endif +#define HIVE_MEM_sp_event_any_pending_mask scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_event_any_pending_mask 0x300 +#else +#define HIVE_ADDR_sp_event_any_pending_mask 0x318 +#endif +#define HIVE_SIZE_sp_event_any_pending_mask 8 + +#ifndef ISP2401 +/* function ia_css_isys_sp_backend_push: 5A16 */ +#else +/* function ia_css_isys_sp_backend_push: 5B51 */ +#endif + +/* function sh_css_decode_tag_descr: 352 */ + +/* function debug_enqueue_isp: 27B */ + +#ifndef ISP2401 +/* function qos_scheduler_update_stage_budget: 65AF */ +#else +/* function qos_scheduler_update_stage_budget: 66F2 */ +#endif + +#ifndef ISP2401 +/* function ia_css_spctrl_sp_uninit: 5951 */ +#else +/* function ia_css_spctrl_sp_uninit: 5A8C */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_HIVE_IF_SWITCH_CODE +#define HIVE_MEM_HIVE_IF_SWITCH_CODE scalar_processor_2400_dmem +#define HIVE_ADDR_HIVE_IF_SWITCH_CODE 0x1D8 +#define HIVE_SIZE_HIVE_IF_SWITCH_CODE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_HIVE_IF_SWITCH_CODE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_HIVE_IF_SWITCH_CODE 0x1D8 +#define HIVE_SIZE_sp_HIVE_IF_SWITCH_CODE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_dis_bufs +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_dis_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_dis_bufs 0x5908 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_dis_bufs 0x5964 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_dis_bufs 140 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_dis_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_dis_bufs 0x5908 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_dis_bufs 0x5964 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_dis_bufs 140 + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_lock_from_start: 2AD9 */ +#else +/* function ia_css_tagger_buf_sp_lock_from_start: 2C7B */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_isp_idle +#define HIVE_MEM_sem_for_isp_idle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_isp_idle 0x47B4 +#else +#define HIVE_ADDR_sem_for_isp_idle 0x47FC +#endif +#define HIVE_SIZE_sem_for_isp_idle 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_isp_idle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_isp_idle 0x47B4 +#else +#define HIVE_ADDR_sp_sem_for_isp_idle 0x47FC +#endif +#define HIVE_SIZE_sp_sem_for_isp_idle 20 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_write_byte_addr: 31E6 */ +#else +/* function ia_css_dmaproxy_sp_write_byte_addr: 33C5 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_init: 315D */ +#else +/* function ia_css_dmaproxy_sp_init: 333C */ +#endif + +#ifndef ISP2401 +/* function ia_css_bufq_sp_release_dynamic_buf_clock_tick: 2D62 */ +#else +/* function ia_css_bufq_sp_release_dynamic_buf_clock_tick: 2F04 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_VAMEM_BASE +#define HIVE_MEM_ISP_VAMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_ISP_VAMEM_BASE 0x14 +#define HIVE_SIZE_ISP_VAMEM_BASE 12 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_VAMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ISP_VAMEM_BASE 0x14 +#define HIVE_SIZE_sp_ISP_VAMEM_BASE 12 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_rawcopy_sp_tagger +#define HIVE_MEM_ia_css_rawcopy_sp_tagger scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_rawcopy_sp_tagger 0x6294 +#else +#define HIVE_ADDR_ia_css_rawcopy_sp_tagger 0x62F0 +#endif +#define HIVE_SIZE_ia_css_rawcopy_sp_tagger 24 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_rawcopy_sp_tagger scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_rawcopy_sp_tagger 0x6294 +#else +#define HIVE_ADDR_sp_ia_css_rawcopy_sp_tagger 0x62F0 +#endif +#define HIVE_SIZE_sp_ia_css_rawcopy_sp_tagger 24 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_exp_ids +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_exp_ids scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_exp_ids 0x5994 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_exp_ids 0x59F0 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_exp_ids 70 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_exp_ids scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_exp_ids 0x5994 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_exp_ids 0x59F0 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_exp_ids 70 + +#ifndef ISP2401 +/* function ia_css_queue_item_load: 4D00 */ +#else +/* function ia_css_queue_item_load: 4F5E */ +#endif + +#ifndef ISP2401 +/* function ia_css_spctrl_sp_get_state: 593C */ +#else +/* function ia_css_spctrl_sp_get_state: 5A77 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_token_map_uninit: 6026 */ +#else +/* function ia_css_isys_sp_token_map_uninit: 6161 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_callout_sp_thread +#define HIVE_MEM_callout_sp_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_callout_sp_thread 0x49DC +#else +#define HIVE_ADDR_callout_sp_thread 0x1E0 +#endif +#define HIVE_SIZE_callout_sp_thread 4 +#else +#endif +#endif +#define HIVE_MEM_sp_callout_sp_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_callout_sp_thread 0x49DC +#else +#define HIVE_ADDR_sp_callout_sp_thread 0x1E0 +#endif +#define HIVE_SIZE_sp_callout_sp_thread 4 + +#ifndef ISP2401 +/* function thread_fiber_sp_init: E2F */ +#else +/* function thread_fiber_sp_init: E24 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_SP_PMEM_BASE +#define HIVE_MEM_SP_PMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_SP_PMEM_BASE 0x0 +#define HIVE_SIZE_SP_PMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_SP_PMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_SP_PMEM_BASE 0x0 +#define HIVE_SIZE_sp_SP_PMEM_BASE 4 + +#ifndef ISP2401 +/* function ia_css_isys_sp_token_map_snd_acquire_req: 5F96 */ +#else +/* function ia_css_isys_sp_token_map_snd_acquire_req: 60D1 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_isp_input_stream_format +#define HIVE_MEM_sp_isp_input_stream_format scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_input_stream_format 0x40F8 +#else +#define HIVE_ADDR_sp_isp_input_stream_format 0x4118 +#endif +#define HIVE_SIZE_sp_isp_input_stream_format 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_isp_input_stream_format scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_isp_input_stream_format 0x40F8 +#else +#define HIVE_ADDR_sp_sp_isp_input_stream_format 0x4118 +#endif +#define HIVE_SIZE_sp_sp_isp_input_stream_format 20 + +#ifndef ISP2401 +/* function __mod: 68A7 */ +#else +/* function __mod: 6A1A */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_init_dmem_channel: 3247 */ +#else +/* function ia_css_dmaproxy_sp_init_dmem_channel: 3426 */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_join: CFF */ +#else +/* function ia_css_thread_sp_join: CF4 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_add_command: 6F4F */ +#else +/* function ia_css_dmaproxy_sp_add_command: 7082 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_metadata_thread_func: 57F0 */ +#else +/* function ia_css_sp_metadata_thread_func: 594F */ +#endif + +#ifndef ISP2401 +/* function __sp_event_proxy_func_critical: 6975 */ +#else +/* function __sp_event_proxy_func_critical: 6AE8 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_metadata_wait: 5903 */ +#else +/* function ia_css_sp_metadata_wait: 5A3E */ +#endif + +#ifndef ISP2401 +/* function ia_css_circbuf_peek_from_start: F08 */ +#else +/* function ia_css_circbuf_peek_from_start: EFD */ +#endif + +#ifndef ISP2401 +/* function ia_css_event_sp_encode: 3552 */ +#else +/* function ia_css_event_sp_encode: 3746 */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_run: D72 */ +#else +/* function ia_css_thread_sp_run: D67 */ +#endif + +#ifndef ISP2401 +/* function sp_isys_copy_func: 6F6 */ +#else +/* function sp_isys_copy_func: 68A */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_backend_flush: 5A7F */ +#else +/* function ia_css_isys_sp_backend_flush: 5BBA */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_backend_frame_exists: 599B */ +#else +/* function ia_css_isys_sp_backend_frame_exists: 5AD6 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_isp_param_init_isp_memories: 4789 */ +#else +/* function ia_css_sp_isp_param_init_isp_memories: 4A11 */ +#endif + +#ifndef ISP2401 +/* function register_isr: 8A9 */ +#else +/* function register_isr: 83D */ +#endif + +/* function irq_raise: C8 */ + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_mmu_invalidate: 3124 */ +#else +/* function ia_css_dmaproxy_sp_mmu_invalidate: 32CC */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_HIVE_IF_SRST_ADDRESS +#define HIVE_MEM_HIVE_IF_SRST_ADDRESS scalar_processor_2400_dmem +#define HIVE_ADDR_HIVE_IF_SRST_ADDRESS 0x1B8 +#define HIVE_SIZE_HIVE_IF_SRST_ADDRESS 16 +#else +#endif +#endif +#define HIVE_MEM_sp_HIVE_IF_SRST_ADDRESS scalar_processor_2400_dmem +#define HIVE_ADDR_sp_HIVE_IF_SRST_ADDRESS 0x1B8 +#define HIVE_SIZE_sp_HIVE_IF_SRST_ADDRESS 16 + +#ifndef ISP2401 +/* function pipeline_sp_initialize_stage: 190B */ +#else +/* function pipeline_sp_initialize_stage: 1945 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_isys_sp_frontend_states +#define HIVE_MEM_ia_css_isys_sp_frontend_states scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_isys_sp_frontend_states 0x62C8 +#else +#define HIVE_ADDR_ia_css_isys_sp_frontend_states 0x6324 +#endif +#define HIVE_SIZE_ia_css_isys_sp_frontend_states 12 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_isys_sp_frontend_states scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_isys_sp_frontend_states 0x62C8 +#else +#define HIVE_ADDR_sp_ia_css_isys_sp_frontend_states 0x6324 +#endif +#define HIVE_SIZE_sp_ia_css_isys_sp_frontend_states 12 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_read_byte_addr_mmio: 6E1E */ +#else +/* function ia_css_dmaproxy_sp_read_byte_addr_mmio: 6F62 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_done_ds: 3799 */ +#else +/* function ia_css_ispctrl_sp_done_ds: 39C8 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_isp_param_get_mem_inits: 4764 */ +#else +/* function ia_css_sp_isp_param_get_mem_inits: 49EC */ +#endif + +#ifndef ISP2401 +/* function ia_css_parambuf_sp_init_buffer_queues: 13D0 */ +#else +/* function ia_css_parambuf_sp_init_buffer_queues: 13F1 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_vbuf_pfp_spref +#define HIVE_MEM_vbuf_pfp_spref scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_vbuf_pfp_spref 0x2F0 +#else +#define HIVE_ADDR_vbuf_pfp_spref 0x308 +#endif +#define HIVE_SIZE_vbuf_pfp_spref 4 +#else +#endif +#endif +#define HIVE_MEM_sp_vbuf_pfp_spref scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_vbuf_pfp_spref 0x2F0 +#else +#define HIVE_ADDR_sp_vbuf_pfp_spref 0x308 +#endif +#define HIVE_SIZE_sp_vbuf_pfp_spref 4 + +#ifndef ISP2401 +/* function input_system_cfg: ABB */ +#else +/* function input_system_cfg: AB5 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_HMEM_BASE +#define HIVE_MEM_ISP_HMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_ISP_HMEM_BASE 0x20 +#define HIVE_SIZE_ISP_HMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_HMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ISP_HMEM_BASE 0x20 +#define HIVE_SIZE_sp_ISP_HMEM_BASE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_frames +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_frames scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_frames 0x59DC +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_frames 0x5A38 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_frames 280 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_frames scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_frames 0x59DC +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_frames 0x5A38 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_frames 280 + +#ifndef ISP2401 +/* function qos_scheduler_init_stage_budget: 65E8 */ +#else +/* function qos_scheduler_init_stage_budget: 6750 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_backend_release: 5AF4 */ +#else +/* function ia_css_isys_sp_backend_release: 5C2F */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_backend_destroy: 5B1E */ +#else +/* function ia_css_isys_sp_backend_destroy: 5C59 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp2host_buffer_queue_handle +#define HIVE_MEM_sp2host_buffer_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp2host_buffer_queue_handle 0x5AF4 +#else +#define HIVE_ADDR_sp2host_buffer_queue_handle 0x5B50 +#endif +#define HIVE_SIZE_sp2host_buffer_queue_handle 96 +#else +#endif +#endif +#define HIVE_MEM_sp_sp2host_buffer_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp2host_buffer_queue_handle 0x5AF4 +#else +#define HIVE_ADDR_sp_sp2host_buffer_queue_handle 0x5B50 +#endif +#define HIVE_SIZE_sp_sp2host_buffer_queue_handle 96 + +#ifndef ISP2401 +/* function ia_css_isys_sp_token_map_check_mipi_frame_size: 5F5A */ +#else +/* function ia_css_isys_sp_token_map_check_mipi_frame_size: 6095 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_init_isp_vars: 4483 */ +#else +/* function ia_css_ispctrl_sp_init_isp_vars: 46DE */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_frontend_has_empty_mipi_buffer_cb: 5B70 */ +#else +/* function ia_css_isys_sp_frontend_has_empty_mipi_buffer_cb: 5CAB */ +#endif + +#ifndef ISP2401 +/* function sp_warning: 8DC */ +#else +/* function sp_warning: 870 */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_vbuf_enqueue: 6304 */ +#else +/* function ia_css_rmgr_sp_vbuf_enqueue: 643F */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_tag_exp_id: 2142 */ +#else +/* function ia_css_tagger_sp_tag_exp_id: 2192 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_write: 31FD */ +#else +/* function ia_css_dmaproxy_sp_write: 33DC */ +#endif + +#ifndef ISP2401 +/* function ia_css_parambuf_sp_release_in_param: 1250 */ +#else +/* function ia_css_parambuf_sp_release_in_param: 1245 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_irq_sw_interrupt_token +#define HIVE_MEM_irq_sw_interrupt_token scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_irq_sw_interrupt_token 0x40F4 +#else +#define HIVE_ADDR_irq_sw_interrupt_token 0x4114 +#endif +#define HIVE_SIZE_irq_sw_interrupt_token 4 +#else +#endif +#endif +#define HIVE_MEM_sp_irq_sw_interrupt_token scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_irq_sw_interrupt_token 0x40F4 +#else +#define HIVE_ADDR_sp_irq_sw_interrupt_token 0x4114 +#endif +#define HIVE_SIZE_sp_irq_sw_interrupt_token 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_isp_addresses +#define HIVE_MEM_sp_isp_addresses scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_addresses 0x5F44 +#else +#define HIVE_ADDR_sp_isp_addresses 0x5FA4 +#endif +#define HIVE_SIZE_sp_isp_addresses 172 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_isp_addresses scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_isp_addresses 0x5F44 +#else +#define HIVE_ADDR_sp_sp_isp_addresses 0x5FA4 +#endif +#define HIVE_SIZE_sp_sp_isp_addresses 172 + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_acq_gen: 6229 */ +#else +/* function ia_css_rmgr_sp_acq_gen: 6364 */ +#endif + +#ifndef ISP2401 +/* function receiver_reg_load: AD0 */ +#else +/* function receiver_reg_load: ACA */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isps +#define HIVE_MEM_isps scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isps 0x6300 +#else +#define HIVE_ADDR_isps 0x635C +#endif +#define HIVE_SIZE_isps 28 +#else +#endif +#endif +#define HIVE_MEM_sp_isps scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isps 0x6300 +#else +#define HIVE_ADDR_sp_isps 0x635C +#endif +#define HIVE_SIZE_sp_isps 28 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host_sp_queues_initialized +#define HIVE_MEM_host_sp_queues_initialized scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host_sp_queues_initialized 0x410C +#else +#define HIVE_ADDR_host_sp_queues_initialized 0x412C +#endif +#define HIVE_SIZE_host_sp_queues_initialized 4 +#else +#endif +#endif +#define HIVE_MEM_sp_host_sp_queues_initialized scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host_sp_queues_initialized 0x410C +#else +#define HIVE_ADDR_sp_host_sp_queues_initialized 0x412C +#endif +#define HIVE_SIZE_sp_host_sp_queues_initialized 4 + +#ifndef ISP2401 +/* function ia_css_queue_uninit: 4BCC */ +#else +/* function ia_css_queue_uninit: 4E2A */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_ispctrl_sp_isp_started +#define HIVE_MEM_ia_css_ispctrl_sp_isp_started scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_ispctrl_sp_isp_started 0x5BFC +#else +#define HIVE_ADDR_ia_css_ispctrl_sp_isp_started 0x5C58 +#endif +#define HIVE_SIZE_ia_css_ispctrl_sp_isp_started 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_ispctrl_sp_isp_started scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_ispctrl_sp_isp_started 0x5BFC +#else +#define HIVE_ADDR_sp_ia_css_ispctrl_sp_isp_started 0x5C58 +#endif +#define HIVE_SIZE_sp_ia_css_ispctrl_sp_isp_started 4 + +#ifndef ISP2401 +/* function ia_css_bufq_sp_release_dynamic_buf: 2DCE */ +#else +/* function ia_css_bufq_sp_release_dynamic_buf: 2F70 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_set_height_exception: 32F5 */ +#else +/* function ia_css_dmaproxy_sp_set_height_exception: 34E9 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_init_vmem_channel: 327A */ +#else +/* function ia_css_dmaproxy_sp_init_vmem_channel: 345A */ +#endif + +#ifndef ISP2401 +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_num_ready_threads +#define HIVE_MEM_num_ready_threads scalar_processor_2400_dmem +#define HIVE_ADDR_num_ready_threads 0x49E4 +#define HIVE_SIZE_num_ready_threads 4 +#else +#endif +#endif +#define HIVE_MEM_sp_num_ready_threads scalar_processor_2400_dmem +#define HIVE_ADDR_sp_num_ready_threads 0x49E4 +#define HIVE_SIZE_sp_num_ready_threads 4 + +/* function ia_css_dmaproxy_sp_write_byte_addr_mmio: 31CF */ +#else +/* function ia_css_dmaproxy_sp_write_byte_addr_mmio: 33AE */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_vbuf_spref +#define HIVE_MEM_vbuf_spref scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_vbuf_spref 0x2EC +#else +#define HIVE_ADDR_vbuf_spref 0x304 +#endif +#define HIVE_SIZE_vbuf_spref 4 +#else +#endif +#endif +#define HIVE_MEM_sp_vbuf_spref scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_vbuf_spref 0x2EC +#else +#define HIVE_ADDR_sp_vbuf_spref 0x304 +#endif +#define HIVE_SIZE_sp_vbuf_spref 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_metadata_thread +#define HIVE_MEM_sp_metadata_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_metadata_thread 0x4998 +#define HIVE_SIZE_sp_metadata_thread 68 +#else +#define HIVE_ADDR_sp_metadata_thread 0x49F8 +#define HIVE_SIZE_sp_metadata_thread 72 +#endif +#else +#endif +#endif +#define HIVE_MEM_sp_sp_metadata_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_metadata_thread 0x4998 +#define HIVE_SIZE_sp_sp_metadata_thread 68 +#else +#define HIVE_ADDR_sp_sp_metadata_thread 0x49F8 +#define HIVE_SIZE_sp_sp_metadata_thread 72 +#endif + +#ifndef ISP2401 +/* function ia_css_queue_enqueue: 4B16 */ +#else +/* function ia_css_queue_enqueue: 4D74 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_flash_sp_request +#define HIVE_MEM_ia_css_flash_sp_request scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_flash_sp_request 0x4A98 +#else +#define HIVE_ADDR_ia_css_flash_sp_request 0x4AF4 +#endif +#define HIVE_SIZE_ia_css_flash_sp_request 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_flash_sp_request scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_flash_sp_request 0x4A98 +#else +#define HIVE_ADDR_sp_ia_css_flash_sp_request 0x4AF4 +#endif +#define HIVE_SIZE_sp_ia_css_flash_sp_request 4 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_vmem_write: 31A0 */ +#else +/* function ia_css_dmaproxy_sp_vmem_write: 337F */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_tagger_frames +#define HIVE_MEM_tagger_frames scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_tagger_frames 0x49EC +#else +#define HIVE_ADDR_tagger_frames 0x4A48 +#endif +#define HIVE_SIZE_tagger_frames 168 +#else +#endif +#endif +#define HIVE_MEM_sp_tagger_frames scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_tagger_frames 0x49EC +#else +#define HIVE_ADDR_sp_tagger_frames 0x4A48 +#endif +#define HIVE_SIZE_sp_tagger_frames 168 + +#ifndef ISP2401 +/* function ia_css_isys_sp_token_map_snd_capture_req: 5FB8 */ +#else +/* function ia_css_isys_sp_token_map_snd_capture_req: 60F3 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_reading_if +#define HIVE_MEM_sem_for_reading_if scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_reading_if 0x47C8 +#else +#define HIVE_ADDR_sem_for_reading_if 0x4810 +#endif +#define HIVE_SIZE_sem_for_reading_if 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_reading_if scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_reading_if 0x47C8 +#else +#define HIVE_ADDR_sp_sem_for_reading_if 0x4810 +#endif +#define HIVE_SIZE_sp_sem_for_reading_if 20 + +#ifndef ISP2401 +/* function sp_generate_interrupts: 95B */ +#else +/* function sp_generate_interrupts: 8EF */ + +/* function ia_css_pipeline_sp_start: 1858 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_start: 181E */ +#else +/* function ia_css_thread_default_callout: 6BE3 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_rawcopy_init: 50F3 */ +#else +/* function ia_css_sp_rawcopy_init: 5351 */ +#endif + +#ifndef ISP2401 +/* function tmr_clock_read: 6596 */ +#else +/* function tmr_clock_read: 66D1 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_BAMEM_BASE +#define HIVE_MEM_ISP_BAMEM_BASE scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ISP_BAMEM_BASE 0x2F8 +#else +#define HIVE_ADDR_ISP_BAMEM_BASE 0x310 +#endif +#define HIVE_SIZE_ISP_BAMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_BAMEM_BASE scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ISP_BAMEM_BASE 0x2F8 +#else +#define HIVE_ADDR_sp_ISP_BAMEM_BASE 0x310 +#endif +#define HIVE_SIZE_sp_ISP_BAMEM_BASE 4 + +#ifndef ISP2401 +/* function ia_css_isys_sp_frontend_rcv_capture_ack: 5C1F */ +#else +/* function ia_css_isys_sp_frontend_rcv_capture_ack: 5D5A */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_sems_for_sp2host_buf_queues +#define HIVE_MEM_ia_css_bufq_sp_sems_for_sp2host_buf_queues scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x5B54 +#else +#define HIVE_ADDR_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x5BB0 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_sems_for_sp2host_buf_queues 160 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x5B54 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x5BB0 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues 160 + +#ifndef ISP2401 +/* function css_get_frame_processing_time_start: 1FAF */ +#else +/* function css_get_frame_processing_time_start: 1FFF */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cbs_frame +#define HIVE_MEM_sp_all_cbs_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cbs_frame 0x47DC +#else +#define HIVE_ADDR_sp_all_cbs_frame 0x4824 +#endif +#define HIVE_SIZE_sp_all_cbs_frame 16 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cbs_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cbs_frame 0x47DC +#else +#define HIVE_ADDR_sp_sp_all_cbs_frame 0x4824 +#endif +#define HIVE_SIZE_sp_sp_all_cbs_frame 16 + +#ifndef ISP2401 +/* function thread_sp_queue_print: D8F */ +#else +/* function thread_sp_queue_print: D84 */ +#endif + +#ifndef ISP2401 +/* function sp_notify_eof: 907 */ +#else +/* function sp_notify_eof: 89B */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_str2mem +#define HIVE_MEM_sem_for_str2mem scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_str2mem 0x47EC +#else +#define HIVE_ADDR_sem_for_str2mem 0x4834 +#endif +#define HIVE_SIZE_sem_for_str2mem 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_str2mem scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_str2mem 0x47EC +#else +#define HIVE_ADDR_sp_sem_for_str2mem 0x4834 +#endif +#define HIVE_SIZE_sp_sem_for_str2mem 20 + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_is_marked_from_start: 2B41 */ +#else +/* function ia_css_tagger_buf_sp_is_marked_from_start: 2CE3 */ +#endif + +#ifndef ISP2401 +/* function ia_css_bufq_sp_acquire_dynamic_buf: 2F86 */ +#else +/* function ia_css_bufq_sp_acquire_dynamic_buf: 3128 */ +#endif + +#ifndef ISP2401 +/* function ia_css_circbuf_destroy: 101D */ +#else +/* function ia_css_circbuf_destroy: 1012 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_PMEM_BASE +#define HIVE_MEM_ISP_PMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_ISP_PMEM_BASE 0xC +#define HIVE_SIZE_ISP_PMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_PMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ISP_PMEM_BASE 0xC +#define HIVE_SIZE_sp_ISP_PMEM_BASE 4 + +#ifndef ISP2401 +/* function ia_css_sp_isp_param_mem_load: 46F7 */ +#else +/* function ia_css_sp_isp_param_mem_load: 497F */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_pop_from_start: 292D */ +#else +/* function ia_css_tagger_buf_sp_pop_from_start: 2ACF */ +#endif + +#ifndef ISP2401 +/* function __div: 685F */ +#else +/* function __div: 69D2 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_frontend_create: 5DF0 */ +#else +/* function ia_css_isys_sp_frontend_create: 5F2B */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_refcount_release_vbuf: 6323 */ +#else +/* function ia_css_rmgr_sp_refcount_release_vbuf: 645E */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_flash_sp_in_use +#define HIVE_MEM_ia_css_flash_sp_in_use scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_flash_sp_in_use 0x4A9C +#else +#define HIVE_ADDR_ia_css_flash_sp_in_use 0x4AF8 +#endif +#define HIVE_SIZE_ia_css_flash_sp_in_use 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_flash_sp_in_use scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_flash_sp_in_use 0x4A9C +#else +#define HIVE_ADDR_sp_ia_css_flash_sp_in_use 0x4AF8 +#endif +#define HIVE_SIZE_sp_ia_css_flash_sp_in_use 4 + +#ifndef ISP2401 +/* function ia_css_thread_sem_sp_wait: 6B42 */ +#else +/* function ia_css_thread_sem_sp_wait: 6CB7 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_sleep_mode +#define HIVE_MEM_sp_sleep_mode scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sleep_mode 0x4110 +#else +#define HIVE_ADDR_sp_sleep_mode 0x4130 +#endif +#define HIVE_SIZE_sp_sleep_mode 4 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_sleep_mode scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_sleep_mode 0x4110 +#else +#define HIVE_ADDR_sp_sp_sleep_mode 0x4130 +#endif +#define HIVE_SIZE_sp_sp_sleep_mode 4 + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_push: 2A3C */ +#else +/* function ia_css_tagger_buf_sp_push: 2BDE */ +#endif + +/* function mmu_invalidate_cache: D3 */ + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_max_cb_elems +#define HIVE_MEM_sp_max_cb_elems scalar_processor_2400_dmem +#define HIVE_ADDR_sp_max_cb_elems 0x148 +#define HIVE_SIZE_sp_max_cb_elems 8 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_max_cb_elems scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_max_cb_elems 0x148 +#define HIVE_SIZE_sp_sp_max_cb_elems 8 + +#ifndef ISP2401 +/* function ia_css_queue_remote_init: 4BEE */ +#else +/* function ia_css_queue_remote_init: 4E4C */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isp_stop_req +#define HIVE_MEM_isp_stop_req scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isp_stop_req 0x4680 +#else +#define HIVE_ADDR_isp_stop_req 0x46C8 +#endif +#define HIVE_SIZE_isp_stop_req 4 +#else +#endif +#endif +#define HIVE_MEM_sp_isp_stop_req scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_stop_req 0x4680 +#else +#define HIVE_ADDR_sp_isp_stop_req 0x46C8 +#endif +#define HIVE_SIZE_sp_isp_stop_req 4 + +#ifndef ISP2401 +#define HIVE_ICACHE_sp_critical_SEGMENT_START 0 +#define HIVE_ICACHE_sp_critical_NUM_SEGMENTS 1 +#endif + +#endif /* _sp_map_h_ */ +#ifndef ISP2401 +extern void sh_css_dump_sp_dmem(void); +void sh_css_dump_sp_dmem(void) +{ +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/csi_rx_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/csi_rx_global.h new file mode 100644 index 0000000000000000000000000000000000000000..146a578b7c74c699d1b05a394283f3225648045f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/csi_rx_global.h @@ -0,0 +1,63 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __CSI_RX_GLOBAL_H_INCLUDED__ +#define __CSI_RX_GLOBAL_H_INCLUDED__ + +#include + +typedef enum { + CSI_MIPI_PACKET_TYPE_UNDEFINED = 0, + CSI_MIPI_PACKET_TYPE_LONG, + CSI_MIPI_PACKET_TYPE_SHORT, + CSI_MIPI_PACKET_TYPE_RESERVED, + N_CSI_MIPI_PACKET_TYPE +} csi_mipi_packet_type_t; + +typedef struct csi_rx_backend_lut_entry_s csi_rx_backend_lut_entry_t; +struct csi_rx_backend_lut_entry_s { + uint32_t long_packet_entry; + uint32_t short_packet_entry; +}; + +typedef struct csi_rx_backend_cfg_s csi_rx_backend_cfg_t; +struct csi_rx_backend_cfg_s { + /* LUT entry for the packet */ + csi_rx_backend_lut_entry_t lut_entry; + + /* can be derived from the Data Type */ + csi_mipi_packet_type_t csi_mipi_packet_type; + + struct { + bool comp_enable; + uint32_t virtual_channel; + uint32_t data_type; + uint32_t comp_scheme; + uint32_t comp_predictor; + uint32_t comp_bit_idx; + } csi_mipi_cfg; +}; + +typedef struct csi_rx_frontend_cfg_s csi_rx_frontend_cfg_t; +struct csi_rx_frontend_cfg_s { + uint32_t active_lanes; +}; + +extern const uint32_t N_SHORT_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID]; +extern const uint32_t N_LONG_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID]; +extern const uint32_t N_CSI_RX_FE_CTRL_DLANES[N_CSI_RX_FRONTEND_ID]; +/* sid_width for CSI_RX_BACKEND_ID */ +extern const uint32_t N_CSI_RX_BE_SID_WIDTH[N_CSI_RX_BACKEND_ID]; + +#endif /* __CSI_RX_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_configs.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_configs.c new file mode 100644 index 0000000000000000000000000000000000000000..325b821f276cf504f5f2cf1b87ad48a9d7c9fc77 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_configs.c @@ -0,0 +1,360 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* Generated code: do not edit or commmit. */ + +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_pipeline.h" +#include "ia_css_isp_configs.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_iterator( + const struct ia_css_binary *binary, + const struct ia_css_iterator_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_iterator() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.iterator.size; + offset = binary->info->mem_offsets.offsets.config->dmem.iterator.offset; + } + if (size) { + ia_css_iterator_config((struct sh_css_isp_iterator_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_iterator() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_copy_output( + const struct ia_css_binary *binary, + const struct ia_css_copy_output_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_copy_output() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.copy_output.size; + offset = binary->info->mem_offsets.offsets.config->dmem.copy_output.offset; + } + if (size) { + ia_css_copy_output_config((struct sh_css_isp_copy_output_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_copy_output() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_crop( + const struct ia_css_binary *binary, + const struct ia_css_crop_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_crop() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.crop.size; + offset = binary->info->mem_offsets.offsets.config->dmem.crop.offset; + } + if (size) { + ia_css_crop_config((struct sh_css_isp_crop_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_crop() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_fpn( + const struct ia_css_binary *binary, + const struct ia_css_fpn_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_fpn() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.fpn.size; + offset = binary->info->mem_offsets.offsets.config->dmem.fpn.offset; + } + if (size) { + ia_css_fpn_config((struct sh_css_isp_fpn_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_fpn() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_dvs( + const struct ia_css_binary *binary, + const struct ia_css_dvs_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_dvs() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.dvs.size; + offset = binary->info->mem_offsets.offsets.config->dmem.dvs.offset; + } + if (size) { + ia_css_dvs_config((struct sh_css_isp_dvs_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_dvs() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_qplane( + const struct ia_css_binary *binary, + const struct ia_css_qplane_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_qplane() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.qplane.size; + offset = binary->info->mem_offsets.offsets.config->dmem.qplane.offset; + } + if (size) { + ia_css_qplane_config((struct sh_css_isp_qplane_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_qplane() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output0( + const struct ia_css_binary *binary, + const struct ia_css_output0_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output0() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.output0.size; + offset = binary->info->mem_offsets.offsets.config->dmem.output0.offset; + } + if (size) { + ia_css_output0_config((struct sh_css_isp_output_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output0() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output1( + const struct ia_css_binary *binary, + const struct ia_css_output1_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output1() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.output1.size; + offset = binary->info->mem_offsets.offsets.config->dmem.output1.offset; + } + if (size) { + ia_css_output1_config((struct sh_css_isp_output_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output1() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output( + const struct ia_css_binary *binary, + const struct ia_css_output_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.output.size; + offset = binary->info->mem_offsets.offsets.config->dmem.output.offset; + } + if (size) { + ia_css_output_config((struct sh_css_isp_output_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ +#ifdef ISP2401 + +void +ia_css_configure_sc( + const struct ia_css_binary *binary, + const struct ia_css_sc_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_sc() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.sc.size; + offset = binary->info->mem_offsets.offsets.config->dmem.sc.offset; + } + if (size) { + ia_css_sc_config((struct sh_css_isp_sc_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_sc() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ +#endif + +void +ia_css_configure_raw( + const struct ia_css_binary *binary, + const struct ia_css_raw_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_raw() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.raw.size; + offset = binary->info->mem_offsets.offsets.config->dmem.raw.offset; + } + if (size) { + ia_css_raw_config((struct sh_css_isp_raw_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_raw() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_tnr( + const struct ia_css_binary *binary, + const struct ia_css_tnr_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_tnr() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.tnr.size; + offset = binary->info->mem_offsets.offsets.config->dmem.tnr.offset; + } + if (size) { + ia_css_tnr_config((struct sh_css_isp_tnr_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_tnr() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_ref( + const struct ia_css_binary *binary, + const struct ia_css_ref_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_ref() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.ref.size; + offset = binary->info->mem_offsets.offsets.config->dmem.ref.offset; + } + if (size) { + ia_css_ref_config((struct sh_css_isp_ref_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_ref() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_vf( + const struct ia_css_binary *binary, + const struct ia_css_vf_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_vf() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.vf.size; + offset = binary->info->mem_offsets.offsets.config->dmem.vf.offset; + } + if (size) { + ia_css_vf_config((struct sh_css_isp_vf_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_vf() leave:\n"); +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_configs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_configs.h new file mode 100644 index 0000000000000000000000000000000000000000..8aacd3dbc05a5263063f91a016f10329c24e61d9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_configs.h @@ -0,0 +1,189 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifdef IA_CSS_INCLUDE_CONFIGURATIONS +#include "isp/kernels/crop/crop_1.0/ia_css_crop.host.h" +#include "isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.h" +#include "isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h" +#include "isp/kernels/ob/ob_1.0/ia_css_ob.host.h" +#include "isp/kernels/output/output_1.0/ia_css_output.host.h" +#include "isp/kernels/qplane/qplane_2/ia_css_qplane.host.h" +#include "isp/kernels/raw/raw_1.0/ia_css_raw.host.h" +#include "isp/kernels/ref/ref_1.0/ia_css_ref.host.h" +#include "isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h" +#ifdef ISP2401 +#include "isp/kernels/sc/sc_1.0/ia_css_sc.host.h" +#endif +#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h" +#include "isp/kernels/vf/vf_1.0/ia_css_vf.host.h" +#include "isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.h" +#include "isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.h" +#endif /* IA_CSS_INCLUDE_CONFIGURATIONS */ +/* Generated code: do not edit or commmit. */ + +#ifndef _IA_CSS_ISP_CONFIG_H +#define _IA_CSS_ISP_CONFIG_H + +/* Code generated by genparam/gencode.c:gen_param_enum() */ + +enum ia_css_configuration_ids { + IA_CSS_ITERATOR_CONFIG_ID, + IA_CSS_COPY_OUTPUT_CONFIG_ID, + IA_CSS_CROP_CONFIG_ID, + IA_CSS_FPN_CONFIG_ID, + IA_CSS_DVS_CONFIG_ID, + IA_CSS_QPLANE_CONFIG_ID, + IA_CSS_OUTPUT0_CONFIG_ID, + IA_CSS_OUTPUT1_CONFIG_ID, + IA_CSS_OUTPUT_CONFIG_ID, +#ifdef ISP2401 + IA_CSS_SC_CONFIG_ID, +#endif + IA_CSS_RAW_CONFIG_ID, + IA_CSS_TNR_CONFIG_ID, + IA_CSS_REF_CONFIG_ID, + IA_CSS_VF_CONFIG_ID, + IA_CSS_NUM_CONFIGURATION_IDS +}; + +/* Code generated by genparam/gencode.c:gen_param_offsets() */ + +struct ia_css_config_memory_offsets { + struct { + struct ia_css_isp_parameter iterator; + struct ia_css_isp_parameter copy_output; + struct ia_css_isp_parameter crop; + struct ia_css_isp_parameter fpn; + struct ia_css_isp_parameter dvs; + struct ia_css_isp_parameter qplane; + struct ia_css_isp_parameter output0; + struct ia_css_isp_parameter output1; + struct ia_css_isp_parameter output; +#ifdef ISP2401 + struct ia_css_isp_parameter sc; +#endif + struct ia_css_isp_parameter raw; + struct ia_css_isp_parameter tnr; + struct ia_css_isp_parameter ref; + struct ia_css_isp_parameter vf; + } dmem; +}; + +#if defined(IA_CSS_INCLUDE_CONFIGURATIONS) + +#include "ia_css_stream.h" /* struct ia_css_stream */ +#include "ia_css_binary.h" /* struct ia_css_binary */ +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_iterator( + const struct ia_css_binary *binary, + const struct ia_css_iterator_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_copy_output( + const struct ia_css_binary *binary, + const struct ia_css_copy_output_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_crop( + const struct ia_css_binary *binary, + const struct ia_css_crop_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_fpn( + const struct ia_css_binary *binary, + const struct ia_css_fpn_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_dvs( + const struct ia_css_binary *binary, + const struct ia_css_dvs_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_qplane( + const struct ia_css_binary *binary, + const struct ia_css_qplane_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output0( + const struct ia_css_binary *binary, + const struct ia_css_output0_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output1( + const struct ia_css_binary *binary, + const struct ia_css_output1_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output( + const struct ia_css_binary *binary, + const struct ia_css_output_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +#ifdef ISP2401 +void +ia_css_configure_sc( + const struct ia_css_binary *binary, + const struct ia_css_sc_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +#endif +void +ia_css_configure_raw( + const struct ia_css_binary *binary, + const struct ia_css_raw_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_tnr( + const struct ia_css_binary *binary, + const struct ia_css_tnr_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_ref( + const struct ia_css_binary *binary, + const struct ia_css_ref_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_vf( + const struct ia_css_binary *binary, + const struct ia_css_vf_configuration *config_dmem); + +#endif /* IA_CSS_INCLUDE_CONFIGURATION */ + +#endif /* _IA_CSS_ISP_CONFIG_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_params.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_params.c new file mode 100644 index 0000000000000000000000000000000000000000..fcc37d12d2279f6f1cf058ee03787475beee01c1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_params.c @@ -0,0 +1,3239 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#define IA_CSS_INCLUDE_PARAMETERS +#include "sh_css_params.h" +#include "isp/kernels/aa/aa_2/ia_css_aa2.host.h" +#include "isp/kernels/anr/anr_1.0/ia_css_anr.host.h" +#include "isp/kernels/anr/anr_2/ia_css_anr2.host.h" +#include "isp/kernels/bh/bh_2/ia_css_bh.host.h" +#include "isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.h" +#include "isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.h" +#include "isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h" +#include "isp/kernels/crop/crop_1.0/ia_css_crop.host.h" +#include "isp/kernels/csc/csc_1.0/ia_css_csc.host.h" +#include "isp/kernels/ctc/ctc_1.0/ia_css_ctc.host.h" +#include "isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.h" +#include "isp/kernels/ctc/ctc2/ia_css_ctc2.host.h" +#include "isp/kernels/de/de_1.0/ia_css_de.host.h" +#include "isp/kernels/de/de_2/ia_css_de2.host.h" +#include "isp/kernels/dp/dp_1.0/ia_css_dp.host.h" +#include "isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds.host.h" +#include "isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h" +#include "isp/kernels/gc/gc_1.0/ia_css_gc.host.h" +#include "isp/kernels/gc/gc_2/ia_css_gc2.host.h" +#include "isp/kernels/macc/macc_1.0/ia_css_macc.host.h" +#include "isp/kernels/macc/macc1_5/ia_css_macc1_5.host.h" +#include "isp/kernels/ob/ob_1.0/ia_css_ob.host.h" +#include "isp/kernels/ob/ob2/ia_css_ob2.host.h" +#include "isp/kernels/output/output_1.0/ia_css_output.host.h" +#include "isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.h" +#include "isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h" +#include "isp/kernels/sc/sc_1.0/ia_css_sc.host.h" +#include "isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.h" +#include "isp/kernels/sdis/sdis_2/ia_css_sdis2.host.h" +#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h" +#include "isp/kernels/uds/uds_1.0/ia_css_uds.host.h" +#include "isp/kernels/wb/wb_1.0/ia_css_wb.host.h" +#include "isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.h" +#include "isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.h" +#include "isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h" +#include "isp/kernels/ynr/ynr_2/ia_css_ynr2.host.h" +#include "isp/kernels/fc/fc_1.0/ia_css_formats.host.h" +#include "isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.h" +#include "isp/kernels/iefd2_6/ia_css_iefd2_6.host.h" +#include "isp/kernels/dpc2/ia_css_dpc2.host.h" +#include "isp/kernels/eed1_8/ia_css_eed1_8.host.h" +#include "isp/kernels/bnlm/ia_css_bnlm.host.h" +#include "isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.h" +/* Generated code: do not edit or commmit. */ + +#include "ia_css_pipeline.h" +#include "ia_css_isp_params.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_aa( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.aa.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.aa.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_aa() enter:\n"); + + ia_css_aa_encode((struct sh_css_isp_aa_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->aa_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_aa() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_anr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.anr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.anr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr() enter:\n"); + + ia_css_anr_encode((struct sh_css_isp_anr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->anr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_anr2( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.anr2.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.anr2.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr2() enter:\n"); + + ia_css_anr2_vmem_encode((struct ia_css_isp_anr2_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->anr_thres, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr2() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_bh( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bh.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bh.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() enter:\n"); + + ia_css_bh_encode((struct sh_css_isp_bh_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->s3a_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() leave:\n"); + } + + } + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->hmem0.bh.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->hmem0.bh.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() enter:\n"); + + ia_css_bh_hmem_encode((struct sh_css_isp_bh_hmem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_HMEM0].address[offset], + ¶ms->s3a_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_HMEM0] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_cnr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.cnr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.cnr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_cnr() enter:\n"); + + ia_css_cnr_encode((struct sh_css_isp_cnr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->cnr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_cnr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_crop( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.crop.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.crop.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_crop() enter:\n"); + + ia_css_crop_encode((struct sh_css_isp_crop_isp_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->crop_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_crop() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_csc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.csc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.csc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_csc() enter:\n"); + + ia_css_csc_encode((struct sh_css_isp_csc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->cc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_csc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_dp( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.dp.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.dp.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_dp() enter:\n"); + + ia_css_dp_encode((struct sh_css_isp_dp_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dp_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_dp() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_bnr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bnr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bnr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bnr() enter:\n"); + + ia_css_bnr_encode((struct sh_css_isp_bnr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->nr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bnr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_de( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.de.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.de.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_de() enter:\n"); + + ia_css_de_encode((struct sh_css_isp_de_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->de_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_de() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ecd( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ecd.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ecd.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ecd() enter:\n"); + + ia_css_ecd_encode((struct sh_css_isp_ecd_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ecd_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ecd() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_formats( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.formats.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.formats.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_formats() enter:\n"); + + ia_css_formats_encode((struct sh_css_isp_formats_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->formats_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_formats() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_fpn( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.fpn.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.fpn.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fpn() enter:\n"); + + ia_css_fpn_encode((struct sh_css_isp_fpn_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->fpn_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fpn() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_gc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.gc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.gc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() enter:\n"); + + ia_css_gc_encode((struct sh_css_isp_gc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->gc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() leave:\n"); + } + + } + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.gc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.gc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() enter:\n"); + + ia_css_gc_vamem_encode((struct sh_css_isp_gc_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM1].address[offset], + ¶ms->gc_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM1] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ce( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ce.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ce.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ce() enter:\n"); + + ia_css_ce_encode((struct sh_css_isp_ce_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ce_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ce() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_yuv2rgb( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yuv2rgb() enter:\n"); + + ia_css_yuv2rgb_encode((struct sh_css_isp_csc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->yuv2rgb_cc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yuv2rgb() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_rgb2yuv( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_rgb2yuv() enter:\n"); + + ia_css_rgb2yuv_encode((struct sh_css_isp_csc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->rgb2yuv_cc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_rgb2yuv() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_r_gamma( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_r_gamma() enter:\n"); + + ia_css_r_gamma_vamem_encode((struct sh_css_isp_rgb_gamma_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM0].address[offset], + ¶ms->r_gamma_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM0] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_r_gamma() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_g_gamma( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_g_gamma() enter:\n"); + + ia_css_g_gamma_vamem_encode((struct sh_css_isp_rgb_gamma_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM1].address[offset], + ¶ms->g_gamma_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM1] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_g_gamma() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_b_gamma( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_b_gamma() enter:\n"); + + ia_css_b_gamma_vamem_encode((struct sh_css_isp_rgb_gamma_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM2].address[offset], + ¶ms->b_gamma_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM2] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_b_gamma() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_uds( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.uds.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.uds.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_uds() enter:\n"); + + ia_css_uds_encode((struct sh_css_sp_uds_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->uds_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_uds() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_raa( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.raa.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.raa.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_raa() enter:\n"); + + ia_css_raa_encode((struct sh_css_isp_aa_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->raa_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_raa() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_s3a( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.s3a.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.s3a.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_s3a() enter:\n"); + + ia_css_s3a_encode((struct sh_css_isp_s3a_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->s3a_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_s3a() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ob( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ob.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ob.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() enter:\n"); + + ia_css_ob_encode((struct sh_css_isp_ob_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ob_config, +¶ms->stream_configs.ob, size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() leave:\n"); + } + + } + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.ob.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.ob.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() enter:\n"); + + ia_css_ob_vmem_encode((struct sh_css_isp_ob_vmem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->ob_config, +¶ms->stream_configs.ob, size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_output( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.output.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.output.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_output() enter:\n"); + + ia_css_output_encode((struct sh_css_isp_output_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->output_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_output() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sc() enter:\n"); + + ia_css_sc_encode((struct sh_css_isp_sc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->sc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_bds( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bds.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bds.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bds() enter:\n"); + + ia_css_bds_encode((struct sh_css_isp_bds_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->bds_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bds() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_tnr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.tnr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.tnr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_tnr() enter:\n"); + + ia_css_tnr_encode((struct sh_css_isp_tnr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->tnr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_tnr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_macc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.macc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.macc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_macc() enter:\n"); + + ia_css_macc_encode((struct sh_css_isp_macc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->macc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_macc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis_horicoef( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horicoef() enter:\n"); + + ia_css_sdis_horicoef_vmem_encode((struct sh_css_isp_sdis_hori_coef_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->dvs_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horicoef() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis_vertcoef( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertcoef() enter:\n"); + + ia_css_sdis_vertcoef_vmem_encode((struct sh_css_isp_sdis_vert_coef_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->dvs_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertcoef() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis_horiproj( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horiproj() enter:\n"); + + ia_css_sdis_horiproj_encode((struct sh_css_isp_sdis_hori_proj_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dvs_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horiproj() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis_vertproj( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertproj() enter:\n"); + + ia_css_sdis_vertproj_encode((struct sh_css_isp_sdis_vert_proj_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dvs_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertproj() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis2_horicoef( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horicoef() enter:\n"); + + ia_css_sdis2_horicoef_vmem_encode((struct sh_css_isp_sdis_hori_coef_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->dvs2_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horicoef() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis2_vertcoef( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertcoef() enter:\n"); + + ia_css_sdis2_vertcoef_vmem_encode((struct sh_css_isp_sdis_vert_coef_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->dvs2_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertcoef() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis2_horiproj( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horiproj() enter:\n"); + + ia_css_sdis2_horiproj_encode((struct sh_css_isp_sdis_hori_proj_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dvs2_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horiproj() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis2_vertproj( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertproj() enter:\n"); + + ia_css_sdis2_vertproj_encode((struct sh_css_isp_sdis_vert_proj_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dvs2_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertproj() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_wb( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.wb.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.wb.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_wb() enter:\n"); + + ia_css_wb_encode((struct sh_css_isp_wb_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->wb_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_wb() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_nr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.nr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.nr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_nr() enter:\n"); + + ia_css_nr_encode((struct sh_css_isp_ynr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->nr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_nr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_yee( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.yee.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.yee.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yee() enter:\n"); + + ia_css_yee_encode((struct sh_css_isp_yee_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->yee_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yee() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ynr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ynr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ynr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ynr() enter:\n"); + + ia_css_ynr_encode((struct sh_css_isp_yee2_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ynr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ynr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_fc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.fc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.fc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fc() enter:\n"); + + ia_css_fc_encode((struct sh_css_isp_fc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->fc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ctc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ctc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ctc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() enter:\n"); + + ia_css_ctc_encode((struct sh_css_isp_ctc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ctc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() leave:\n"); + } + + } + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() enter:\n"); + + ia_css_ctc_vamem_encode((struct sh_css_isp_ctc_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM0].address[offset], + ¶ms->ctc_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM0] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_xnr_table( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr_table() enter:\n"); + + ia_css_xnr_table_vamem_encode((struct sh_css_isp_xnr_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM1].address[offset], + ¶ms->xnr_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM1] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr_table() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_xnr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.xnr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.xnr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr() enter:\n"); + + ia_css_xnr_encode((struct sh_css_isp_xnr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->xnr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_xnr3( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() enter:\n"); + + ia_css_xnr3_encode((struct sh_css_isp_xnr3_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->xnr3_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() leave:\n"); + } + + } +#ifdef ISP2401 + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.xnr3.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.xnr3.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() enter:\n"); + + ia_css_xnr3_vmem_encode((struct sh_css_isp_xnr3_vmem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->xnr3_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() leave:\n"); + } + + } +#endif +} + +/* Code generated by genparam/gencode.c:gen_param_process_table() */ + +void (* ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) = { + ia_css_process_aa, + ia_css_process_anr, + ia_css_process_anr2, + ia_css_process_bh, + ia_css_process_cnr, + ia_css_process_crop, + ia_css_process_csc, + ia_css_process_dp, + ia_css_process_bnr, + ia_css_process_de, + ia_css_process_ecd, + ia_css_process_formats, + ia_css_process_fpn, + ia_css_process_gc, + ia_css_process_ce, + ia_css_process_yuv2rgb, + ia_css_process_rgb2yuv, + ia_css_process_r_gamma, + ia_css_process_g_gamma, + ia_css_process_b_gamma, + ia_css_process_uds, + ia_css_process_raa, + ia_css_process_s3a, + ia_css_process_ob, + ia_css_process_output, + ia_css_process_sc, + ia_css_process_bds, + ia_css_process_tnr, + ia_css_process_macc, + ia_css_process_sdis_horicoef, + ia_css_process_sdis_vertcoef, + ia_css_process_sdis_horiproj, + ia_css_process_sdis_vertproj, + ia_css_process_sdis2_horicoef, + ia_css_process_sdis2_vertcoef, + ia_css_process_sdis2_horiproj, + ia_css_process_sdis2_vertproj, + ia_css_process_wb, + ia_css_process_nr, + ia_css_process_yee, + ia_css_process_ynr, + ia_css_process_fc, + ia_css_process_ctc, + ia_css_process_xnr_table, + ia_css_process_xnr, + ia_css_process_xnr3, +}; + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_dp_config(const struct ia_css_isp_parameters *params, + struct ia_css_dp_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_dp_config() enter: " + "config=%p\n",config); + + *config = params->dp_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_dp_config() leave\n"); + ia_css_dp_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_dp_config(struct ia_css_isp_parameters *params, + const struct ia_css_dp_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_dp_config() enter:\n"); + ia_css_dp_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dp_config = *config; + params->config_changed[IA_CSS_DP_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_DP_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_dp_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_wb_config(const struct ia_css_isp_parameters *params, + struct ia_css_wb_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_wb_config() enter: " + "config=%p\n",config); + + *config = params->wb_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_wb_config() leave\n"); + ia_css_wb_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_wb_config(struct ia_css_isp_parameters *params, + const struct ia_css_wb_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_wb_config() enter:\n"); + ia_css_wb_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->wb_config = *config; + params->config_changed[IA_CSS_WB_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_WB_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_wb_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_tnr_config(const struct ia_css_isp_parameters *params, + struct ia_css_tnr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_tnr_config() enter: " + "config=%p\n",config); + + *config = params->tnr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_tnr_config() leave\n"); + ia_css_tnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_tnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_tnr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_tnr_config() enter:\n"); + ia_css_tnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->tnr_config = *config; + params->config_changed[IA_CSS_TNR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_TNR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_tnr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ob_config(const struct ia_css_isp_parameters *params, + struct ia_css_ob_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ob_config() enter: " + "config=%p\n",config); + + *config = params->ob_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ob_config() leave\n"); + ia_css_ob_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ob_config(struct ia_css_isp_parameters *params, + const struct ia_css_ob_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ob_config() enter:\n"); + ia_css_ob_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ob_config = *config; + params->config_changed[IA_CSS_OB_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_OB_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ob_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_de_config(const struct ia_css_isp_parameters *params, + struct ia_css_de_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_de_config() enter: " + "config=%p\n",config); + + *config = params->de_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_de_config() leave\n"); + ia_css_de_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_de_config(struct ia_css_isp_parameters *params, + const struct ia_css_de_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_de_config() enter:\n"); + ia_css_de_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->de_config = *config; + params->config_changed[IA_CSS_DE_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_DE_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_de_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_anr_config(const struct ia_css_isp_parameters *params, + struct ia_css_anr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr_config() enter: " + "config=%p\n",config); + + *config = params->anr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr_config() leave\n"); + ia_css_anr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_anr_config(struct ia_css_isp_parameters *params, + const struct ia_css_anr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_anr_config() enter:\n"); + ia_css_anr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->anr_config = *config; + params->config_changed[IA_CSS_ANR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_ANR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_anr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_anr2_config(const struct ia_css_isp_parameters *params, + struct ia_css_anr_thres *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr2_config() enter: " + "config=%p\n",config); + + *config = params->anr_thres; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr2_config() leave\n"); + ia_css_anr2_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_anr2_config(struct ia_css_isp_parameters *params, + const struct ia_css_anr_thres *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_anr2_config() enter:\n"); + ia_css_anr2_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->anr_thres = *config; + params->config_changed[IA_CSS_ANR2_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_ANR2_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_anr2_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ce_config(const struct ia_css_isp_parameters *params, + struct ia_css_ce_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ce_config() enter: " + "config=%p\n",config); + + *config = params->ce_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ce_config() leave\n"); + ia_css_ce_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ce_config(struct ia_css_isp_parameters *params, + const struct ia_css_ce_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ce_config() enter:\n"); + ia_css_ce_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ce_config = *config; + params->config_changed[IA_CSS_CE_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_CE_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ce_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ecd_config(const struct ia_css_isp_parameters *params, + struct ia_css_ecd_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ecd_config() enter: " + "config=%p\n",config); + + *config = params->ecd_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ecd_config() leave\n"); + ia_css_ecd_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ecd_config(struct ia_css_isp_parameters *params, + const struct ia_css_ecd_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ecd_config() enter:\n"); + ia_css_ecd_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ecd_config = *config; + params->config_changed[IA_CSS_ECD_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_ECD_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ecd_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ynr_config(const struct ia_css_isp_parameters *params, + struct ia_css_ynr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ynr_config() enter: " + "config=%p\n",config); + + *config = params->ynr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ynr_config() leave\n"); + ia_css_ynr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ynr_config(struct ia_css_isp_parameters *params, + const struct ia_css_ynr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ynr_config() enter:\n"); + ia_css_ynr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ynr_config = *config; + params->config_changed[IA_CSS_YNR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_YNR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ynr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_fc_config(const struct ia_css_isp_parameters *params, + struct ia_css_fc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_fc_config() enter: " + "config=%p\n",config); + + *config = params->fc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_fc_config() leave\n"); + ia_css_fc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_fc_config(struct ia_css_isp_parameters *params, + const struct ia_css_fc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_fc_config() enter:\n"); + ia_css_fc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->fc_config = *config; + params->config_changed[IA_CSS_FC_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_FC_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_fc_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_cnr_config(const struct ia_css_isp_parameters *params, + struct ia_css_cnr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_cnr_config() enter: " + "config=%p\n",config); + + *config = params->cnr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_cnr_config() leave\n"); + ia_css_cnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_cnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_cnr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_cnr_config() enter:\n"); + ia_css_cnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->cnr_config = *config; + params->config_changed[IA_CSS_CNR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_CNR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_cnr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_macc_config(const struct ia_css_isp_parameters *params, + struct ia_css_macc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_macc_config() enter: " + "config=%p\n",config); + + *config = params->macc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_macc_config() leave\n"); + ia_css_macc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_macc_config(struct ia_css_isp_parameters *params, + const struct ia_css_macc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_macc_config() enter:\n"); + ia_css_macc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->macc_config = *config; + params->config_changed[IA_CSS_MACC_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_MACC_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_macc_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ctc_config(const struct ia_css_isp_parameters *params, + struct ia_css_ctc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ctc_config() enter: " + "config=%p\n",config); + + *config = params->ctc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ctc_config() leave\n"); + ia_css_ctc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ctc_config(struct ia_css_isp_parameters *params, + const struct ia_css_ctc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ctc_config() enter:\n"); + ia_css_ctc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ctc_config = *config; + params->config_changed[IA_CSS_CTC_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_CTC_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ctc_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_aa_config(const struct ia_css_isp_parameters *params, + struct ia_css_aa_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_aa_config() enter: " + "config=%p\n",config); + + *config = params->aa_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_aa_config() leave\n"); + ia_css_aa_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_aa_config(struct ia_css_isp_parameters *params, + const struct ia_css_aa_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_aa_config() enter:\n"); + ia_css_aa_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->aa_config = *config; + params->config_changed[IA_CSS_AA_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_AA_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_aa_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_yuv2rgb_config(const struct ia_css_isp_parameters *params, + struct ia_css_cc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_yuv2rgb_config() enter: " + "config=%p\n",config); + + *config = params->yuv2rgb_cc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_yuv2rgb_config() leave\n"); + ia_css_yuv2rgb_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_yuv2rgb_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_yuv2rgb_config() enter:\n"); + ia_css_yuv2rgb_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->yuv2rgb_cc_config = *config; + params->config_changed[IA_CSS_YUV2RGB_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_YUV2RGB_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_yuv2rgb_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_rgb2yuv_config(const struct ia_css_isp_parameters *params, + struct ia_css_cc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_rgb2yuv_config() enter: " + "config=%p\n",config); + + *config = params->rgb2yuv_cc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_rgb2yuv_config() leave\n"); + ia_css_rgb2yuv_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_rgb2yuv_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_rgb2yuv_config() enter:\n"); + ia_css_rgb2yuv_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->rgb2yuv_cc_config = *config; + params->config_changed[IA_CSS_RGB2YUV_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_RGB2YUV_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_rgb2yuv_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_csc_config(const struct ia_css_isp_parameters *params, + struct ia_css_cc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_csc_config() enter: " + "config=%p\n",config); + + *config = params->cc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_csc_config() leave\n"); + ia_css_csc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_csc_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_csc_config() enter:\n"); + ia_css_csc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->cc_config = *config; + params->config_changed[IA_CSS_CSC_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_CSC_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_csc_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_nr_config(const struct ia_css_isp_parameters *params, + struct ia_css_nr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_nr_config() enter: " + "config=%p\n",config); + + *config = params->nr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_nr_config() leave\n"); + ia_css_nr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_nr_config(struct ia_css_isp_parameters *params, + const struct ia_css_nr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_nr_config() enter:\n"); + ia_css_nr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->nr_config = *config; + params->config_changed[IA_CSS_BNR_ID] = true; + params->config_changed[IA_CSS_NR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_NR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_nr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_gc_config(const struct ia_css_isp_parameters *params, + struct ia_css_gc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_gc_config() enter: " + "config=%p\n",config); + + *config = params->gc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_gc_config() leave\n"); + ia_css_gc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_gc_config(struct ia_css_isp_parameters *params, + const struct ia_css_gc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_gc_config() enter:\n"); + ia_css_gc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->gc_config = *config; + params->config_changed[IA_CSS_GC_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_GC_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_gc_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis_horicoef_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horicoef_config() enter: " + "config=%p\n",config); + + *config = params->dvs_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horicoef_config() leave\n"); + ia_css_sdis_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_horicoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_horicoef_config() enter:\n"); + ia_css_sdis_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs_coefs = *config; + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_horicoef_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis_vertcoef_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertcoef_config() enter: " + "config=%p\n",config); + + *config = params->dvs_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertcoef_config() leave\n"); + ia_css_sdis_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_vertcoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_vertcoef_config() enter:\n"); + ia_css_sdis_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs_coefs = *config; + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_vertcoef_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis_horiproj_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horiproj_config() enter: " + "config=%p\n",config); + + *config = params->dvs_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horiproj_config() leave\n"); + ia_css_sdis_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_horiproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_horiproj_config() enter:\n"); + ia_css_sdis_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs_coefs = *config; + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_horiproj_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis_vertproj_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertproj_config() enter: " + "config=%p\n",config); + + *config = params->dvs_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertproj_config() leave\n"); + ia_css_sdis_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_vertproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_vertproj_config() enter:\n"); + ia_css_sdis_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs_coefs = *config; + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_vertproj_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis2_horicoef_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs2_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horicoef_config() enter: " + "config=%p\n",config); + + *config = params->dvs2_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horicoef_config() leave\n"); + ia_css_sdis2_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_horicoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_horicoef_config() enter:\n"); + ia_css_sdis2_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs2_coefs = *config; + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_horicoef_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis2_vertcoef_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs2_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertcoef_config() enter: " + "config=%p\n",config); + + *config = params->dvs2_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertcoef_config() leave\n"); + ia_css_sdis2_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_vertcoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_vertcoef_config() enter:\n"); + ia_css_sdis2_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs2_coefs = *config; + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_vertcoef_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis2_horiproj_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs2_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horiproj_config() enter: " + "config=%p\n",config); + + *config = params->dvs2_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horiproj_config() leave\n"); + ia_css_sdis2_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_horiproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_horiproj_config() enter:\n"); + ia_css_sdis2_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs2_coefs = *config; + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_horiproj_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis2_vertproj_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs2_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertproj_config() enter: " + "config=%p\n",config); + + *config = params->dvs2_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertproj_config() leave\n"); + ia_css_sdis2_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_vertproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_vertproj_config() enter:\n"); + ia_css_sdis2_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs2_coefs = *config; + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_vertproj_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_r_gamma_config(const struct ia_css_isp_parameters *params, + struct ia_css_rgb_gamma_table *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_r_gamma_config() enter: " + "config=%p\n",config); + + *config = params->r_gamma_table; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_r_gamma_config() leave\n"); + ia_css_r_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_r_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_r_gamma_config() enter:\n"); + ia_css_r_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->r_gamma_table = *config; + params->config_changed[IA_CSS_R_GAMMA_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_R_GAMMA_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_r_gamma_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_g_gamma_config(const struct ia_css_isp_parameters *params, + struct ia_css_rgb_gamma_table *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_g_gamma_config() enter: " + "config=%p\n",config); + + *config = params->g_gamma_table; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_g_gamma_config() leave\n"); + ia_css_g_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_g_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_g_gamma_config() enter:\n"); + ia_css_g_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->g_gamma_table = *config; + params->config_changed[IA_CSS_G_GAMMA_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_G_GAMMA_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_g_gamma_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_b_gamma_config(const struct ia_css_isp_parameters *params, + struct ia_css_rgb_gamma_table *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_b_gamma_config() enter: " + "config=%p\n",config); + + *config = params->b_gamma_table; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_b_gamma_config() leave\n"); + ia_css_b_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_b_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_b_gamma_config() enter:\n"); + ia_css_b_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->b_gamma_table = *config; + params->config_changed[IA_CSS_B_GAMMA_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_B_GAMMA_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_b_gamma_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_xnr_table_config(const struct ia_css_isp_parameters *params, + struct ia_css_xnr_table *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_table_config() enter: " + "config=%p\n",config); + + *config = params->xnr_table; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_table_config() leave\n"); + ia_css_xnr_table_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr_table_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr_table *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr_table_config() enter:\n"); + ia_css_xnr_table_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->xnr_table = *config; + params->config_changed[IA_CSS_XNR_TABLE_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_XNR_TABLE_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr_table_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_formats_config(const struct ia_css_isp_parameters *params, + struct ia_css_formats_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_formats_config() enter: " + "config=%p\n",config); + + *config = params->formats_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_formats_config() leave\n"); + ia_css_formats_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_formats_config(struct ia_css_isp_parameters *params, + const struct ia_css_formats_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_formats_config() enter:\n"); + ia_css_formats_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->formats_config = *config; + params->config_changed[IA_CSS_FORMATS_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_FORMATS_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_formats_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_xnr_config(const struct ia_css_isp_parameters *params, + struct ia_css_xnr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_config() enter: " + "config=%p\n",config); + + *config = params->xnr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_config() leave\n"); + ia_css_xnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr_config() enter:\n"); + ia_css_xnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->xnr_config = *config; + params->config_changed[IA_CSS_XNR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_XNR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_xnr3_config(const struct ia_css_isp_parameters *params, + struct ia_css_xnr3_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr3_config() enter: " + "config=%p\n",config); + + *config = params->xnr3_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr3_config() leave\n"); + ia_css_xnr3_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr3_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr3_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr3_config() enter:\n"); + ia_css_xnr3_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->xnr3_config = *config; + params->config_changed[IA_CSS_XNR3_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_XNR3_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr3_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_s3a_config(const struct ia_css_isp_parameters *params, + struct ia_css_3a_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_s3a_config() enter: " + "config=%p\n",config); + + *config = params->s3a_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_s3a_config() leave\n"); + ia_css_s3a_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_s3a_config(struct ia_css_isp_parameters *params, + const struct ia_css_3a_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_s3a_config() enter:\n"); + ia_css_s3a_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->s3a_config = *config; + params->config_changed[IA_CSS_BH_ID] = true; + params->config_changed[IA_CSS_S3A_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_S3A_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_s3a_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_output_config(const struct ia_css_isp_parameters *params, + struct ia_css_output_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_output_config() enter: " + "config=%p\n",config); + + *config = params->output_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_output_config() leave\n"); + ia_css_output_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_output_config(struct ia_css_isp_parameters *params, + const struct ia_css_output_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_output_config() enter:\n"); + ia_css_output_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->output_config = *config; + params->config_changed[IA_CSS_OUTPUT_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_OUTPUT_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_output_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_global_access_function() */ + +void +ia_css_get_configs(struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config) +{ + ia_css_get_dp_config(params, config->dp_config); + ia_css_get_wb_config(params, config->wb_config); + ia_css_get_tnr_config(params, config->tnr_config); + ia_css_get_ob_config(params, config->ob_config); + ia_css_get_de_config(params, config->de_config); + ia_css_get_anr_config(params, config->anr_config); + ia_css_get_anr2_config(params, config->anr_thres); + ia_css_get_ce_config(params, config->ce_config); + ia_css_get_ecd_config(params, config->ecd_config); + ia_css_get_ynr_config(params, config->ynr_config); + ia_css_get_fc_config(params, config->fc_config); + ia_css_get_cnr_config(params, config->cnr_config); + ia_css_get_macc_config(params, config->macc_config); + ia_css_get_ctc_config(params, config->ctc_config); + ia_css_get_aa_config(params, config->aa_config); + ia_css_get_yuv2rgb_config(params, config->yuv2rgb_cc_config); + ia_css_get_rgb2yuv_config(params, config->rgb2yuv_cc_config); + ia_css_get_csc_config(params, config->cc_config); + ia_css_get_nr_config(params, config->nr_config); + ia_css_get_gc_config(params, config->gc_config); + ia_css_get_sdis_horicoef_config(params, config->dvs_coefs); + ia_css_get_sdis_vertcoef_config(params, config->dvs_coefs); + ia_css_get_sdis_horiproj_config(params, config->dvs_coefs); + ia_css_get_sdis_vertproj_config(params, config->dvs_coefs); + ia_css_get_sdis2_horicoef_config(params, config->dvs2_coefs); + ia_css_get_sdis2_vertcoef_config(params, config->dvs2_coefs); + ia_css_get_sdis2_horiproj_config(params, config->dvs2_coefs); + ia_css_get_sdis2_vertproj_config(params, config->dvs2_coefs); + ia_css_get_r_gamma_config(params, config->r_gamma_table); + ia_css_get_g_gamma_config(params, config->g_gamma_table); + ia_css_get_b_gamma_config(params, config->b_gamma_table); + ia_css_get_xnr_table_config(params, config->xnr_table); + ia_css_get_formats_config(params, config->formats_config); + ia_css_get_xnr_config(params, config->xnr_config); + ia_css_get_xnr3_config(params, config->xnr3_config); + ia_css_get_s3a_config(params, config->s3a_config); + ia_css_get_output_config(params, config->output_config); +} + +/* Code generated by genparam/gencode.c:gen_global_access_function() */ + +void +ia_css_set_configs(struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config) +{ + ia_css_set_dp_config(params, config->dp_config); + ia_css_set_wb_config(params, config->wb_config); + ia_css_set_tnr_config(params, config->tnr_config); + ia_css_set_ob_config(params, config->ob_config); + ia_css_set_de_config(params, config->de_config); + ia_css_set_anr_config(params, config->anr_config); + ia_css_set_anr2_config(params, config->anr_thres); + ia_css_set_ce_config(params, config->ce_config); + ia_css_set_ecd_config(params, config->ecd_config); + ia_css_set_ynr_config(params, config->ynr_config); + ia_css_set_fc_config(params, config->fc_config); + ia_css_set_cnr_config(params, config->cnr_config); + ia_css_set_macc_config(params, config->macc_config); + ia_css_set_ctc_config(params, config->ctc_config); + ia_css_set_aa_config(params, config->aa_config); + ia_css_set_yuv2rgb_config(params, config->yuv2rgb_cc_config); + ia_css_set_rgb2yuv_config(params, config->rgb2yuv_cc_config); + ia_css_set_csc_config(params, config->cc_config); + ia_css_set_nr_config(params, config->nr_config); + ia_css_set_gc_config(params, config->gc_config); + ia_css_set_sdis_horicoef_config(params, config->dvs_coefs); + ia_css_set_sdis_vertcoef_config(params, config->dvs_coefs); + ia_css_set_sdis_horiproj_config(params, config->dvs_coefs); + ia_css_set_sdis_vertproj_config(params, config->dvs_coefs); + ia_css_set_sdis2_horicoef_config(params, config->dvs2_coefs); + ia_css_set_sdis2_vertcoef_config(params, config->dvs2_coefs); + ia_css_set_sdis2_horiproj_config(params, config->dvs2_coefs); + ia_css_set_sdis2_vertproj_config(params, config->dvs2_coefs); + ia_css_set_r_gamma_config(params, config->r_gamma_table); + ia_css_set_g_gamma_config(params, config->g_gamma_table); + ia_css_set_b_gamma_config(params, config->b_gamma_table); + ia_css_set_xnr_table_config(params, config->xnr_table); + ia_css_set_formats_config(params, config->formats_config); + ia_css_set_xnr_config(params, config->xnr_config); + ia_css_set_xnr3_config(params, config->xnr3_config); + ia_css_set_s3a_config(params, config->s3a_config); + ia_css_set_output_config(params, config->output_config); +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_params.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_params.h new file mode 100644 index 0000000000000000000000000000000000000000..5b3deb7f74aecf1de25749111f2cc7c81d6cd3e2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_params.h @@ -0,0 +1,399 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* Generated code: do not edit or commmit. */ + +#ifndef _IA_CSS_ISP_PARAM_H +#define _IA_CSS_ISP_PARAM_H + +/* Code generated by genparam/gencode.c:gen_param_enum() */ + +enum ia_css_parameter_ids { + IA_CSS_AA_ID, + IA_CSS_ANR_ID, + IA_CSS_ANR2_ID, + IA_CSS_BH_ID, + IA_CSS_CNR_ID, + IA_CSS_CROP_ID, + IA_CSS_CSC_ID, + IA_CSS_DP_ID, + IA_CSS_BNR_ID, + IA_CSS_DE_ID, + IA_CSS_ECD_ID, + IA_CSS_FORMATS_ID, + IA_CSS_FPN_ID, + IA_CSS_GC_ID, + IA_CSS_CE_ID, + IA_CSS_YUV2RGB_ID, + IA_CSS_RGB2YUV_ID, + IA_CSS_R_GAMMA_ID, + IA_CSS_G_GAMMA_ID, + IA_CSS_B_GAMMA_ID, + IA_CSS_UDS_ID, + IA_CSS_RAA_ID, + IA_CSS_S3A_ID, + IA_CSS_OB_ID, + IA_CSS_OUTPUT_ID, + IA_CSS_SC_ID, + IA_CSS_BDS_ID, + IA_CSS_TNR_ID, + IA_CSS_MACC_ID, + IA_CSS_SDIS_HORICOEF_ID, + IA_CSS_SDIS_VERTCOEF_ID, + IA_CSS_SDIS_HORIPROJ_ID, + IA_CSS_SDIS_VERTPROJ_ID, + IA_CSS_SDIS2_HORICOEF_ID, + IA_CSS_SDIS2_VERTCOEF_ID, + IA_CSS_SDIS2_HORIPROJ_ID, + IA_CSS_SDIS2_VERTPROJ_ID, + IA_CSS_WB_ID, + IA_CSS_NR_ID, + IA_CSS_YEE_ID, + IA_CSS_YNR_ID, + IA_CSS_FC_ID, + IA_CSS_CTC_ID, + IA_CSS_XNR_TABLE_ID, + IA_CSS_XNR_ID, + IA_CSS_XNR3_ID, + IA_CSS_NUM_PARAMETER_IDS +}; + +/* Code generated by genparam/gencode.c:gen_param_offsets() */ + +struct ia_css_memory_offsets { + struct { + struct ia_css_isp_parameter aa; + struct ia_css_isp_parameter anr; + struct ia_css_isp_parameter bh; + struct ia_css_isp_parameter cnr; + struct ia_css_isp_parameter crop; + struct ia_css_isp_parameter csc; + struct ia_css_isp_parameter dp; + struct ia_css_isp_parameter bnr; + struct ia_css_isp_parameter de; + struct ia_css_isp_parameter ecd; + struct ia_css_isp_parameter formats; + struct ia_css_isp_parameter fpn; + struct ia_css_isp_parameter gc; + struct ia_css_isp_parameter ce; + struct ia_css_isp_parameter yuv2rgb; + struct ia_css_isp_parameter rgb2yuv; + struct ia_css_isp_parameter uds; + struct ia_css_isp_parameter raa; + struct ia_css_isp_parameter s3a; + struct ia_css_isp_parameter ob; + struct ia_css_isp_parameter output; + struct ia_css_isp_parameter sc; + struct ia_css_isp_parameter bds; + struct ia_css_isp_parameter tnr; + struct ia_css_isp_parameter macc; + struct ia_css_isp_parameter sdis_horiproj; + struct ia_css_isp_parameter sdis_vertproj; + struct ia_css_isp_parameter sdis2_horiproj; + struct ia_css_isp_parameter sdis2_vertproj; + struct ia_css_isp_parameter wb; + struct ia_css_isp_parameter nr; + struct ia_css_isp_parameter yee; + struct ia_css_isp_parameter ynr; + struct ia_css_isp_parameter fc; + struct ia_css_isp_parameter ctc; + struct ia_css_isp_parameter xnr; + struct ia_css_isp_parameter xnr3; + struct ia_css_isp_parameter get; + struct ia_css_isp_parameter put; + } dmem; + struct { + struct ia_css_isp_parameter anr2; + struct ia_css_isp_parameter ob; + struct ia_css_isp_parameter sdis_horicoef; + struct ia_css_isp_parameter sdis_vertcoef; + struct ia_css_isp_parameter sdis2_horicoef; + struct ia_css_isp_parameter sdis2_vertcoef; +#ifdef ISP2401 + struct ia_css_isp_parameter xnr3; +#endif + } vmem; + struct { + struct ia_css_isp_parameter bh; + } hmem0; + struct { + struct ia_css_isp_parameter gc; + struct ia_css_isp_parameter g_gamma; + struct ia_css_isp_parameter xnr_table; + } vamem1; + struct { + struct ia_css_isp_parameter r_gamma; + struct ia_css_isp_parameter ctc; + } vamem0; + struct { + struct ia_css_isp_parameter b_gamma; + } vamem2; +}; + +#if defined(IA_CSS_INCLUDE_PARAMETERS) + +#include "ia_css_stream.h" /* struct ia_css_stream */ +#include "ia_css_binary.h" /* struct ia_css_binary */ +/* Code generated by genparam/gencode.c:gen_param_process_table() */ + +struct ia_css_pipeline_stage; /* forward declaration */ + +extern void (* ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_dp_config(struct ia_css_isp_parameters *params, + const struct ia_css_dp_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_wb_config(struct ia_css_isp_parameters *params, + const struct ia_css_wb_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_tnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_tnr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ob_config(struct ia_css_isp_parameters *params, + const struct ia_css_ob_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_de_config(struct ia_css_isp_parameters *params, + const struct ia_css_de_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_anr_config(struct ia_css_isp_parameters *params, + const struct ia_css_anr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_anr2_config(struct ia_css_isp_parameters *params, + const struct ia_css_anr_thres *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ce_config(struct ia_css_isp_parameters *params, + const struct ia_css_ce_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ecd_config(struct ia_css_isp_parameters *params, + const struct ia_css_ecd_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ynr_config(struct ia_css_isp_parameters *params, + const struct ia_css_ynr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_fc_config(struct ia_css_isp_parameters *params, + const struct ia_css_fc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_cnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_cnr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_macc_config(struct ia_css_isp_parameters *params, + const struct ia_css_macc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ctc_config(struct ia_css_isp_parameters *params, + const struct ia_css_ctc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_aa_config(struct ia_css_isp_parameters *params, + const struct ia_css_aa_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_yuv2rgb_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_rgb2yuv_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_csc_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_nr_config(struct ia_css_isp_parameters *params, + const struct ia_css_nr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_gc_config(struct ia_css_isp_parameters *params, + const struct ia_css_gc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_horicoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_vertcoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_horiproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_vertproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_horicoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_vertcoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_horiproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_vertproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_r_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_g_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_b_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr_table_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr_table *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_formats_config(struct ia_css_isp_parameters *params, + const struct ia_css_formats_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr3_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr3_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_s3a_config(struct ia_css_isp_parameters *params, + const struct ia_css_3a_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_output_config(struct ia_css_isp_parameters *params, + const struct ia_css_output_config *config); + +/* Code generated by genparam/gencode.c:gen_global_access_function() */ + +void +ia_css_get_configs(struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config) +; +#ifdef ISP2401 + +#endif +/* Code generated by genparam/gencode.c:gen_global_access_function() */ + +void +ia_css_set_configs(struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config) +; +#ifdef ISP2401 + +#endif +#endif /* IA_CSS_INCLUDE_PARAMETER */ + +#endif /* _IA_CSS_ISP_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_states.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_states.c new file mode 100644 index 0000000000000000000000000000000000000000..a445d4f1fa2b44da67712bc6d3a47ee26550bb5e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_states.c @@ -0,0 +1,218 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* Generated code: do not edit or commmit. */ + +#include "ia_css_pipeline.h" +#include "ia_css_isp_states.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_aa_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_aa_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.aa.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.aa.offset; + + if (size) { + ia_css_init_aa_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_aa_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_cnr_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.cnr.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.cnr.offset; + + if (size) { + ia_css_init_cnr_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_cnr2_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr2_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.cnr2.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.cnr2.offset; + + if (size) { + ia_css_init_cnr2_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr2_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_dp_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_dp_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.dp.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.dp.offset; + + if (size) { + ia_css_init_dp_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_dp_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_de_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_de_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.de.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.de.offset; + + if (size) { + ia_css_init_de_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_de_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_tnr_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_tnr_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->dmem.tnr.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->dmem.tnr.offset; + + if (size) { + ia_css_init_tnr_state((struct sh_css_isp_tnr_dmem_state *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_tnr_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_ref_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ref_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->dmem.ref.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->dmem.ref.offset; + + if (size) { + ia_css_init_ref_state((struct sh_css_isp_ref_dmem_state *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ref_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_ynr_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ynr_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.ynr.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.ynr.offset; + + if (size) { + ia_css_init_ynr_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ynr_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_state_init_table() */ + +void (* ia_css_kernel_init_state[IA_CSS_NUM_STATE_IDS])(const struct ia_css_binary *binary) = { + ia_css_initialize_aa_state, + ia_css_initialize_cnr_state, + ia_css_initialize_cnr2_state, + ia_css_initialize_dp_state, + ia_css_initialize_de_state, + ia_css_initialize_tnr_state, + ia_css_initialize_ref_state, + ia_css_initialize_ynr_state, +}; + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_states.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_states.h new file mode 100644 index 0000000000000000000000000000000000000000..d658a005d694ce52062748bccc677b36aa0e50ad --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_states.h @@ -0,0 +1,74 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#define IA_CSS_INCLUDE_STATES +#include "ia_css_memory_access.h" +#include "isp/kernels/aa/aa_2/ia_css_aa2.host.h" +#include "isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.h" +#include "isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h" +#include "isp/kernels/de/de_1.0/ia_css_de.host.h" +#include "isp/kernels/dp/dp_1.0/ia_css_dp.host.h" +#include "isp/kernels/ref/ref_1.0/ia_css_ref.host.h" +#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h" +#include "isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h" +#include "isp/kernels/iefd2_6/ia_css_iefd2_6.host.h" +#include "isp/kernels/dpc2/ia_css_dpc2.host.h" +#include "isp/kernels/eed1_8/ia_css_eed1_8.host.h" +/* Generated code: do not edit or commmit. */ + +#ifndef _IA_CSS_ISP_STATE_H +#define _IA_CSS_ISP_STATE_H + +/* Code generated by genparam/gencode.c:gen_param_enum() */ + +enum ia_css_state_ids { + IA_CSS_AA_STATE_ID, + IA_CSS_CNR_STATE_ID, + IA_CSS_CNR2_STATE_ID, + IA_CSS_DP_STATE_ID, + IA_CSS_DE_STATE_ID, + IA_CSS_TNR_STATE_ID, + IA_CSS_REF_STATE_ID, + IA_CSS_YNR_STATE_ID, + IA_CSS_NUM_STATE_IDS +}; + +/* Code generated by genparam/gencode.c:gen_param_offsets() */ + +struct ia_css_state_memory_offsets { + struct { + struct ia_css_isp_parameter aa; + struct ia_css_isp_parameter cnr; + struct ia_css_isp_parameter cnr2; + struct ia_css_isp_parameter dp; + struct ia_css_isp_parameter de; + struct ia_css_isp_parameter ynr; + } vmem; + struct { + struct ia_css_isp_parameter tnr; + struct ia_css_isp_parameter ref; + } dmem; +}; + +#if defined(IA_CSS_INCLUDE_STATES) + +#include "ia_css_stream.h" /* struct ia_css_stream */ +#include "ia_css_binary.h" /* struct ia_css_binary */ +/* Code generated by genparam/genstate.c:gen_state_init_table() */ + +extern void (* ia_css_kernel_init_state[IA_CSS_NUM_STATE_IDS])(const struct ia_css_binary *binary); + +#endif /* IA_CSS_INCLUDE_STATE */ + +#endif /* _IA_CSS_ISP_STATE_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx.c new file mode 100644 index 0000000000000000000000000000000000000000..505e2b600beb9539a23fa4cfd879b935169851ce --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx.c @@ -0,0 +1,41 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + + +#include "system_global.h" + +const uint32_t N_SHORT_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID] = { + 4, /* 4 entries at CSI_RX_BACKEND0_ID*/ + 4, /* 4 entries at CSI_RX_BACKEND1_ID*/ + 4 /* 4 entries at CSI_RX_BACKEND2_ID*/ +}; + +const uint32_t N_LONG_PACKET_LUT_ENTRIES[N_CSI_RX_BACKEND_ID] = { + 8, /* 8 entries at CSI_RX_BACKEND0_ID*/ + 4, /* 4 entries at CSI_RX_BACKEND1_ID*/ + 4 /* 4 entries at CSI_RX_BACKEND2_ID*/ +}; + +const uint32_t N_CSI_RX_FE_CTRL_DLANES[N_CSI_RX_FRONTEND_ID] = { + N_CSI_RX_DLANE_ID, /* 4 dlanes for CSI_RX_FR0NTEND0_ID */ + N_CSI_RX_DLANE_ID, /* 4 dlanes for CSI_RX_FR0NTEND1_ID */ + N_CSI_RX_DLANE_ID /* 4 dlanes for CSI_RX_FR0NTEND2_ID */ +}; + +/* sid_width for CSI_RX_BACKEND_ID */ +const uint32_t N_CSI_RX_BE_SID_WIDTH[N_CSI_RX_BACKEND_ID] = { + 3, + 2, + 2 +}; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx_local.h new file mode 100644 index 0000000000000000000000000000000000000000..a2e9d54a4a37638e736fd0137fc75e0116c7f134 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx_local.h @@ -0,0 +1,61 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __CSI_RX_LOCAL_H_INCLUDED__ +#define __CSI_RX_LOCAL_H_INCLUDED__ + +#include "csi_rx_global.h" +#define N_CSI_RX_BE_MIPI_COMP_FMT_REG 4 +#define N_CSI_RX_BE_MIPI_CUSTOM_PEC 12 +#define N_CSI_RX_BE_SHORT_PKT_LUT 4 +#define N_CSI_RX_BE_LONG_PKT_LUT 8 +typedef struct csi_rx_fe_ctrl_state_s csi_rx_fe_ctrl_state_t; +typedef struct csi_rx_fe_ctrl_lane_s csi_rx_fe_ctrl_lane_t; +typedef struct csi_rx_be_ctrl_state_s csi_rx_be_ctrl_state_t; +/*mipi_backend_custom_mode_pixel_extraction_config*/ +typedef struct csi_rx_be_ctrl_pec_s csi_rx_be_ctrl_pec_t; + + +struct csi_rx_fe_ctrl_lane_s { + hrt_data termen; + hrt_data settle; +}; +struct csi_rx_fe_ctrl_state_s { + hrt_data enable; + hrt_data nof_enable_lanes; + hrt_data error_handling; + hrt_data status; + hrt_data status_dlane_hs; + hrt_data status_dlane_lp; + csi_rx_fe_ctrl_lane_t clane; + csi_rx_fe_ctrl_lane_t dlane[N_CSI_RX_DLANE_ID]; +}; +struct csi_rx_be_ctrl_state_s { + hrt_data enable; + hrt_data status; + hrt_data comp_format_reg[N_CSI_RX_BE_MIPI_COMP_FMT_REG]; + hrt_data raw16; + hrt_data raw18; + hrt_data force_raw8; + hrt_data irq_status; + hrt_data custom_mode_enable; + hrt_data custom_mode_data_state; + hrt_data pec[N_CSI_RX_BE_MIPI_CUSTOM_PEC]; + hrt_data custom_mode_valid_eop_config; + hrt_data global_lut_disregard_reg; + hrt_data packet_status_stall; + hrt_data short_packet_lut_entry[N_CSI_RX_BE_SHORT_PKT_LUT]; + hrt_data long_packet_lut_entry[N_CSI_RX_BE_LONG_PKT_LUT]; +}; +#endif /* __CSI_RX_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx_private.h new file mode 100644 index 0000000000000000000000000000000000000000..5819bcff5e55a01a1b5281dd9c1df1cdb0212082 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/csi_rx_private.h @@ -0,0 +1,282 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __CSI_RX_PRIVATE_H_INCLUDED__ +#define __CSI_RX_PRIVATE_H_INCLUDED__ + +#include "rx_csi_defs.h" +#include "mipi_backend_defs.h" +#include "csi_rx_public.h" + +#include "device_access.h" /* ia_css_device_load_uint32 */ + +#include "assert_support.h" /* assert */ +#include "print_support.h" /* print */ + + +/***************************************************** + * + * Native command interface (NCI). + * + *****************************************************/ +/** + * @brief Get the csi rx fe state. + * Refer to "csi_rx_public.h" for details. + */ +STORAGE_CLASS_CSI_RX_C void csi_rx_fe_ctrl_get_state( + const csi_rx_frontend_ID_t ID, + csi_rx_fe_ctrl_state_t *state) +{ + uint32_t i; + + state->enable = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_ENABLE_REG_IDX); + state->nof_enable_lanes = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_NOF_ENABLED_LANES_REG_IDX); + state->error_handling = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_ERROR_HANDLING_REG_IDX); + state->status = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_REG_IDX); + state->status_dlane_hs = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX); + state->status_dlane_lp = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX); + state->clane.termen = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_TERMEN_CLANE_REG_IDX); + state->clane.settle = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_SETTLE_CLANE_REG_IDX); + + /* + * Get the values of the register-set per + * dlane. + */ + for (i = 0; i < N_CSI_RX_FE_CTRL_DLANES[ID]; i++) { + csi_rx_fe_ctrl_get_dlane_state( + ID, + i, + &(state->dlane[i])); + } +} + +/** + * @brief Get the state of the csi rx fe dlane process. + * Refer to "csi_rx_public.h" for details. + */ +STORAGE_CLASS_CSI_RX_C void csi_rx_fe_ctrl_get_dlane_state( + const csi_rx_frontend_ID_t ID, + const uint32_t lane, + csi_rx_fe_ctrl_lane_t *dlane_state) +{ + + dlane_state->termen = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_TERMEN_DLANE_REG_IDX(lane)); + dlane_state->settle = + csi_rx_fe_ctrl_reg_load(ID, _HRT_CSI_RX_DLY_CNT_SETTLE_DLANE_REG_IDX(lane)); + +} +/** + * @brief dump the csi rx fe state. + * Refer to "csi_rx_public.h" for details. + */ +STORAGE_CLASS_CSI_RX_C void csi_rx_fe_ctrl_dump_state( + const csi_rx_frontend_ID_t ID, + csi_rx_fe_ctrl_state_t *state) +{ + uint32_t i; + + ia_css_print("CSI RX FE STATE Controller %d Enable state 0x%x \n", ID, state->enable); + ia_css_print("CSI RX FE STATE Controller %d No Of enable lanes 0x%x \n", ID, state->nof_enable_lanes); + ia_css_print("CSI RX FE STATE Controller %d Error handling 0x%x \n", ID, state->error_handling); + ia_css_print("CSI RX FE STATE Controller %d Status 0x%x \n", ID, state->status); + ia_css_print("CSI RX FE STATE Controller %d Status Dlane HS 0x%x \n", ID, state->status_dlane_hs); + ia_css_print("CSI RX FE STATE Controller %d Status Dlane LP 0x%x \n", ID, state->status_dlane_lp); + ia_css_print("CSI RX FE STATE Controller %d Status term enable LP 0x%x \n", ID, state->clane.termen); + ia_css_print("CSI RX FE STATE Controller %d Status term settle LP 0x%x \n", ID, state->clane.settle); + + /* + * Get the values of the register-set per + * dlane. + */ + for (i = 0; i < N_CSI_RX_FE_CTRL_DLANES[ID]; i++) { + ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d termen 0x%x \n", ID, i, state->dlane[i].termen); + ia_css_print("CSI RX FE STATE Controller %d DLANE ID %d settle 0x%x \n", ID, i, state->dlane[i].settle); + } +} + +/** + * @brief Get the csi rx be state. + * Refer to "csi_rx_public.h" for details. + */ +STORAGE_CLASS_CSI_RX_C void csi_rx_be_ctrl_get_state( + const csi_rx_backend_ID_t ID, + csi_rx_be_ctrl_state_t *state) +{ + uint32_t i; + + state->enable = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_ENABLE_REG_IDX); + + state->status = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_STATUS_REG_IDX); + + for(i = 0; i comp_format_reg[i] = + csi_rx_be_ctrl_reg_load(ID, + _HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX+i); + } + + state->raw16 = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_IDX); + + state->raw18 = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_IDX); + state->force_raw8 = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_FORCE_RAW8_REG_IDX); + state->irq_status = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_IRQ_STATUS_REG_IDX); +#if 0 /* device access error for these registers */ + /* ToDo: rootcause this failure */ + state->custom_mode_enable = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_EN_REG_IDX); + + state->custom_mode_data_state = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX); + for(i = 0; i pec[i] = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX + i); + } + state->custom_mode_valid_eop_config = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_REG_IDX); +#endif + state->global_lut_disregard_reg = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_IDX); + state->packet_status_stall = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_IDX); + /* + * Get the values of the register-set per + * lut. + */ + for (i = 0; i < N_SHORT_PACKET_LUT_ENTRIES[ID]; i++) { + state->short_packet_lut_entry[i] = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_IDX + i); + } + for (i = 0; i < N_LONG_PACKET_LUT_ENTRIES[ID]; i++) { + state->long_packet_lut_entry[i] = + csi_rx_be_ctrl_reg_load(ID, _HRT_MIPI_BACKEND_LP_LUT_ENTRY_0_REG_IDX + i); + } +} + +/** + * @brief Dump the csi rx be state. + * Refer to "csi_rx_public.h" for details. + */ +STORAGE_CLASS_CSI_RX_C void csi_rx_be_ctrl_dump_state( + const csi_rx_backend_ID_t ID, + csi_rx_be_ctrl_state_t *state) +{ + uint32_t i; + + ia_css_print("CSI RX BE STATE Controller %d Enable 0x%x \n", ID, state->enable); + ia_css_print("CSI RX BE STATE Controller %d Status 0x%x \n", ID, state->status); + + for(i = 0; i status); + } + ia_css_print("CSI RX BE STATE Controller %d RAW16 0x%x \n", ID, state->raw16); + ia_css_print("CSI RX BE STATE Controller %d RAW18 0x%x \n", ID, state->raw18); + ia_css_print("CSI RX BE STATE Controller %d Force RAW8 0x%x \n", ID, state->force_raw8); + ia_css_print("CSI RX BE STATE Controller %d IRQ state 0x%x \n", ID, state->irq_status); +#if 0 /* ToDo:Getting device access error for this register */ + for(i = 0; i pec[i]); + } +#endif + ia_css_print("CSI RX BE STATE Controller %d Global LUT diregard reg 0x%x \n", ID, state->global_lut_disregard_reg); + ia_css_print("CSI RX BE STATE Controller %d packet stall reg 0x%x \n", ID, state->packet_status_stall); + /* + * Get the values of the register-set per + * lut. + */ + for (i = 0; i < N_SHORT_PACKET_LUT_ENTRIES[ID]; i++) { + ia_css_print("CSI RX BE STATE Controller ID %d Short packat entry %d shart packet lut id 0x%x \n", ID, i, state->short_packet_lut_entry[i]); + } + for (i = 0; i < N_LONG_PACKET_LUT_ENTRIES[ID]; i++) { + ia_css_print("CSI RX BE STATE Controller ID %d Long packat entry %d Long packet lut id 0x%x \n", ID, i, state->long_packet_lut_entry[i]); + } +} +/* end of NCI */ +/***************************************************** + * + * Device level interface (DLI). + * + *****************************************************/ +/** + * @brief Load the register value. + * Refer to "csi_rx_public.h" for details. + */ +STORAGE_CLASS_CSI_RX_C hrt_data csi_rx_fe_ctrl_reg_load( + const csi_rx_frontend_ID_t ID, + const hrt_address reg) +{ + assert(ID < N_CSI_RX_FRONTEND_ID); + assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1); + return ia_css_device_load_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg*sizeof(hrt_data)); +} + + +/** + * @brief Store a value to the register. + * Refer to "ibuf_ctrl_public.h" for details. + */ +STORAGE_CLASS_CSI_RX_C void csi_rx_fe_ctrl_reg_store( + const csi_rx_frontend_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ + assert(ID < N_CSI_RX_FRONTEND_ID); + assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1); + + ia_css_device_store_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg*sizeof(hrt_data), value); +} +/** + * @brief Load the register value. + * Refer to "csi_rx_public.h" for details. + */ +STORAGE_CLASS_CSI_RX_C hrt_data csi_rx_be_ctrl_reg_load( + const csi_rx_backend_ID_t ID, + const hrt_address reg) +{ + assert(ID < N_CSI_RX_BACKEND_ID); + assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1); + return ia_css_device_load_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg*sizeof(hrt_data)); +} + + +/** + * @brief Store a value to the register. + * Refer to "ibuf_ctrl_public.h" for details. + */ +STORAGE_CLASS_CSI_RX_C void csi_rx_be_ctrl_reg_store( + const csi_rx_backend_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ + assert(ID < N_CSI_RX_BACKEND_ID); + assert(CSI_RX_BE_CTRL_BASE[ID] != (hrt_address)-1); + + ia_css_device_store_uint32(CSI_RX_BE_CTRL_BASE[ID] + reg*sizeof(hrt_data), value); +} +/** end of DLI */ + +#endif /* __CSI_RX_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl.c new file mode 100644 index 0000000000000000000000000000000000000000..14973d1c27560a70539b28ad52fd0d3c4e825652 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl.c @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include "system_global.h" + +const uint32_t N_IBUF_CTRL_PROCS[N_IBUF_CTRL_ID] = { + 8, /* IBUF_CTRL0_ID supports at most 8 processes */ + 4, /* IBUF_CTRL1_ID supports at most 4 processes */ + 4 /* IBUF_CTRL2_ID supports at most 4 processes */ +}; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl_local.h new file mode 100644 index 0000000000000000000000000000000000000000..ea40284623d1c4fd8610f17cafb516a419cce702 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl_local.h @@ -0,0 +1,58 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IBUF_CTRL_LOCAL_H_INCLUDED__ +#define __IBUF_CTRL_LOCAL_H_INCLUDED__ + +#include "ibuf_ctrl_global.h" + +typedef struct ibuf_ctrl_proc_state_s ibuf_ctrl_proc_state_t; +typedef struct ibuf_ctrl_state_s ibuf_ctrl_state_t; + +struct ibuf_ctrl_proc_state_s { + hrt_data num_items; + hrt_data num_stores; + hrt_data dma_channel; + hrt_data dma_command; + hrt_data ibuf_st_addr; + hrt_data ibuf_stride; + hrt_data ibuf_end_addr; + hrt_data dest_st_addr; + hrt_data dest_stride; + hrt_data dest_end_addr; + hrt_data sync_frame; + hrt_data sync_command; + hrt_data store_command; + hrt_data shift_returned_items; + hrt_data elems_ibuf; + hrt_data elems_dest; + hrt_data cur_stores; + hrt_data cur_acks; + hrt_data cur_s2m_ibuf_addr; + hrt_data cur_dma_ibuf_addr; + hrt_data cur_dma_dest_addr; + hrt_data cur_isp_dest_addr; + hrt_data dma_cmds_send; + hrt_data main_cntrl_state; + hrt_data dma_sync_state; + hrt_data isp_sync_state; +}; + +struct ibuf_ctrl_state_s { + hrt_data recalc_words; + hrt_data arbiters; + ibuf_ctrl_proc_state_t proc_state[N_STREAM2MMIO_SID_ID]; +}; + +#endif /* __IBUF_CTRL_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl_private.h new file mode 100644 index 0000000000000000000000000000000000000000..470c92d287fe550150c4027486ee00f5f1dc7e2d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/ibuf_ctrl_private.h @@ -0,0 +1,233 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IBUF_CTRL_PRIVATE_H_INCLUDED__ +#define __IBUF_CTRL_PRIVATE_H_INCLUDED__ + +#include "ibuf_ctrl_public.h" + +#include "device_access.h" /* ia_css_device_load_uint32 */ + +#include "assert_support.h" /* assert */ +#include "print_support.h" /* print */ + + +/***************************************************** + * + * Native command interface (NCI). + * + *****************************************************/ +/** + * @brief Get the ibuf-controller state. + * Refer to "ibuf_ctrl_public.h" for details. + */ +STORAGE_CLASS_IBUF_CTRL_C void ibuf_ctrl_get_state( + const ibuf_ctrl_ID_t ID, + ibuf_ctrl_state_t *state) +{ + uint32_t i; + + state->recalc_words = + ibuf_ctrl_reg_load(ID, _IBUF_CNTRL_RECALC_WORDS_STATUS); + state->arbiters = + ibuf_ctrl_reg_load(ID, _IBUF_CNTRL_ARBITERS_STATUS); + + /* + * Get the values of the register-set per + * ibuf-controller process. + */ + for (i = 0; i < N_IBUF_CTRL_PROCS[ID]; i++) { + ibuf_ctrl_get_proc_state( + ID, + i, + &(state->proc_state[i])); + } +} + +/** + * @brief Get the state of the ibuf-controller process. + * Refer to "ibuf_ctrl_public.h" for details. + */ +STORAGE_CLASS_IBUF_CTRL_C void ibuf_ctrl_get_proc_state( + const ibuf_ctrl_ID_t ID, + const uint32_t proc_id, + ibuf_ctrl_proc_state_t *state) +{ + hrt_address reg_bank_offset; + + reg_bank_offset = + _IBUF_CNTRL_PROC_REG_ALIGN * (1 + proc_id); + + state->num_items = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_NUM_ITEMS_PER_STORE); + + state->num_stores = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_NUM_STORES_PER_FRAME); + + state->dma_channel = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_CHANNEL); + + state->dma_command = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_CMD); + + state->ibuf_st_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_START_ADDRESS); + + state->ibuf_stride = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_STRIDE); + + state->ibuf_end_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_BUFFER_END_ADDRESS); + + state->dest_st_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_START_ADDRESS); + + state->dest_stride = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_STRIDE); + + state->dest_end_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DEST_END_ADDRESS); + + state->sync_frame = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_SYNC_FRAME); + + state->sync_command = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_STR2MMIO_SYNC_CMD); + + state->store_command = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_STR2MMIO_STORE_CMD); + + state->shift_returned_items = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_SHIFT_ITEMS); + + state->elems_ibuf = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ELEMS_P_WORD_IBUF); + + state->elems_dest = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ELEMS_P_WORD_DEST); + + state->cur_stores = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_STORES); + + state->cur_acks = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_ACKS); + + state->cur_s2m_ibuf_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_S2M_IBUF_ADDR); + + state->cur_dma_ibuf_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_DMA_IBUF_ADDR); + + state->cur_dma_dest_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_DMA_DEST_ADDR); + + state->cur_isp_dest_addr = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_ISP_DEST_ADDR); + + state->dma_cmds_send = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_CUR_NR_DMA_CMDS_SEND); + + state->main_cntrl_state = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_MAIN_CNTRL_STATE); + + state->dma_sync_state = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_DMA_SYNC_STATE); + + state->isp_sync_state = + ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_ISP_SYNC_STATE); +} +/** + * @brief Dump the ibuf-controller state. + * Refer to "ibuf_ctrl_public.h" for details. + */ +STORAGE_CLASS_IBUF_CTRL_C void ibuf_ctrl_dump_state( + const ibuf_ctrl_ID_t ID, + ibuf_ctrl_state_t *state) +{ + uint32_t i; + ia_css_print("IBUF controller ID %d recalculate words 0x%x\n", ID, state->recalc_words); + ia_css_print("IBUF controller ID %d arbiters 0x%x\n", ID, state->arbiters); + + /* + * Dump the values of the register-set per + * ibuf-controller process. + */ + for (i = 0; i < N_IBUF_CTRL_PROCS[ID]; i++) { + ia_css_print("IBUF controller ID %d Process ID %d num_items 0x%x\n", ID, i, state->proc_state[i].num_items); + ia_css_print("IBUF controller ID %d Process ID %d num_stores 0x%x\n", ID, i, state->proc_state[i].num_stores); + ia_css_print("IBUF controller ID %d Process ID %d dma_channel 0x%x\n", ID, i, state->proc_state[i].dma_channel); + ia_css_print("IBUF controller ID %d Process ID %d dma_command 0x%x\n", ID, i, state->proc_state[i].dma_command); + ia_css_print("IBUF controller ID %d Process ID %d ibuf_st_addr 0x%x\n", ID, i, state->proc_state[i].ibuf_st_addr); + ia_css_print("IBUF controller ID %d Process ID %d ibuf_stride 0x%x\n", ID, i, state->proc_state[i].ibuf_stride); + ia_css_print("IBUF controller ID %d Process ID %d ibuf_end_addr 0x%x\n", ID, i, state->proc_state[i].ibuf_end_addr); + ia_css_print("IBUF controller ID %d Process ID %d dest_st_addr 0x%x\n", ID, i, state->proc_state[i].dest_st_addr); + ia_css_print("IBUF controller ID %d Process ID %d dest_stride 0x%x\n", ID, i, state->proc_state[i].dest_stride); + ia_css_print("IBUF controller ID %d Process ID %d dest_end_addr 0x%x\n", ID, i, state->proc_state[i].dest_end_addr); + ia_css_print("IBUF controller ID %d Process ID %d sync_frame 0x%x\n", ID, i, state->proc_state[i].sync_frame); + ia_css_print("IBUF controller ID %d Process ID %d sync_command 0x%x\n", ID, i, state->proc_state[i].sync_command); + ia_css_print("IBUF controller ID %d Process ID %d store_command 0x%x\n", ID, i, state->proc_state[i].store_command); + ia_css_print("IBUF controller ID %d Process ID %d shift_returned_items 0x%x\n", ID, i, state->proc_state[i].shift_returned_items); + ia_css_print("IBUF controller ID %d Process ID %d elems_ibuf 0x%x\n", ID, i, state->proc_state[i].elems_ibuf); + ia_css_print("IBUF controller ID %d Process ID %d elems_dest 0x%x\n", ID, i, state->proc_state[i].elems_dest); + ia_css_print("IBUF controller ID %d Process ID %d cur_stores 0x%x\n", ID, i, state->proc_state[i].cur_stores); + ia_css_print("IBUF controller ID %d Process ID %d cur_acks 0x%x\n", ID, i, state->proc_state[i].cur_acks); + ia_css_print("IBUF controller ID %d Process ID %d cur_s2m_ibuf_addr 0x%x\n", ID, i, state->proc_state[i].cur_s2m_ibuf_addr); + ia_css_print("IBUF controller ID %d Process ID %d cur_dma_ibuf_addr 0x%x\n", ID, i, state->proc_state[i].cur_dma_ibuf_addr); + ia_css_print("IBUF controller ID %d Process ID %d cur_dma_dest_addr 0x%x\n", ID, i, state->proc_state[i].cur_dma_dest_addr); + ia_css_print("IBUF controller ID %d Process ID %d cur_isp_dest_addr 0x%x\n", ID, i, state->proc_state[i].cur_isp_dest_addr); + ia_css_print("IBUF controller ID %d Process ID %d dma_cmds_send 0x%x\n", ID, i, state->proc_state[i].dma_cmds_send); + ia_css_print("IBUF controller ID %d Process ID %d main_cntrl_state 0x%x\n", ID, i, state->proc_state[i].main_cntrl_state); + ia_css_print("IBUF controller ID %d Process ID %d dma_sync_state 0x%x\n", ID, i, state->proc_state[i].dma_sync_state); + ia_css_print("IBUF controller ID %d Process ID %d isp_sync_state 0x%x\n", ID, i, state->proc_state[i].isp_sync_state); + } +} +/** end of NCI */ + +/***************************************************** + * + * Device level interface (DLI). + * + *****************************************************/ +/** + * @brief Load the register value. + * Refer to "ibuf_ctrl_public.h" for details. + */ +STORAGE_CLASS_IBUF_CTRL_C hrt_data ibuf_ctrl_reg_load( + const ibuf_ctrl_ID_t ID, + const hrt_address reg) +{ + assert(ID < N_IBUF_CTRL_ID); + assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1); + return ia_css_device_load_uint32(IBUF_CTRL_BASE[ID] + reg*sizeof(hrt_data)); +} + + +/** + * @brief Store a value to the register. + * Refer to "ibuf_ctrl_public.h" for details. + */ +STORAGE_CLASS_IBUF_CTRL_C void ibuf_ctrl_reg_store( + const ibuf_ctrl_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ + assert(ID < N_IBUF_CTRL_ID); + assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1); + + ia_css_device_store_uint32(IBUF_CTRL_BASE[ID] + reg*sizeof(hrt_data), value); +} +/** end of DLI */ + + +#endif /* __IBUF_CTRL_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/input_system_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/input_system_local.h new file mode 100644 index 0000000000000000000000000000000000000000..f199423e28dae9b99b1c406f78ce03bfcc1da7ee --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/input_system_local.h @@ -0,0 +1,106 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_SYSTEM_LOCAL_H_INCLUDED__ +#define __INPUT_SYSTEM_LOCAL_H_INCLUDED__ + +#include "type_support.h" +#include "input_system_global.h" + +#include "ibuf_ctrl.h" +#include "csi_rx.h" +#include "pixelgen.h" +#include "isys_stream2mmio.h" +#include "isys_irq.h" + +typedef input_system_err_t input_system_error_t; + +typedef enum { + MIPI_FORMAT_SHORT1 = 0x08, + MIPI_FORMAT_SHORT2, + MIPI_FORMAT_SHORT3, + MIPI_FORMAT_SHORT4, + MIPI_FORMAT_SHORT5, + MIPI_FORMAT_SHORT6, + MIPI_FORMAT_SHORT7, + MIPI_FORMAT_SHORT8, + MIPI_FORMAT_EMBEDDED = 0x12, + MIPI_FORMAT_YUV420_8 = 0x18, + MIPI_FORMAT_YUV420_10, + MIPI_FORMAT_YUV420_8_LEGACY, + MIPI_FORMAT_YUV420_8_SHIFT = 0x1C, + MIPI_FORMAT_YUV420_10_SHIFT, + MIPI_FORMAT_YUV422_8 = 0x1E, + MIPI_FORMAT_YUV422_10, + MIPI_FORMAT_RGB444 = 0x20, + MIPI_FORMAT_RGB555, + MIPI_FORMAT_RGB565, + MIPI_FORMAT_RGB666, + MIPI_FORMAT_RGB888, + MIPI_FORMAT_RAW6 = 0x28, + MIPI_FORMAT_RAW7, + MIPI_FORMAT_RAW8, + MIPI_FORMAT_RAW10, + MIPI_FORMAT_RAW12, + MIPI_FORMAT_RAW14, + MIPI_FORMAT_CUSTOM0 = 0x30, + MIPI_FORMAT_CUSTOM1, + MIPI_FORMAT_CUSTOM2, + MIPI_FORMAT_CUSTOM3, + MIPI_FORMAT_CUSTOM4, + MIPI_FORMAT_CUSTOM5, + MIPI_FORMAT_CUSTOM6, + MIPI_FORMAT_CUSTOM7, + //MIPI_FORMAT_RAW16, /*not supported by 2401*/ + //MIPI_FORMAT_RAW18, + N_MIPI_FORMAT +} mipi_format_t; + +#define N_MIPI_FORMAT_CUSTOM 8 + +/* The number of stores for compressed format types */ +#define N_MIPI_COMPRESSOR_CONTEXT (N_RX_CHANNEL_ID * N_MIPI_FORMAT_CUSTOM) +#define UNCOMPRESSED_BITS_PER_PIXEL_10 10 +#define UNCOMPRESSED_BITS_PER_PIXEL_12 12 +#define COMPRESSED_BITS_PER_PIXEL_6 6 +#define COMPRESSED_BITS_PER_PIXEL_7 7 +#define COMPRESSED_BITS_PER_PIXEL_8 8 +enum mipi_compressor { + MIPI_COMPRESSOR_NONE = 0, + MIPI_COMPRESSOR_10_6_10, + MIPI_COMPRESSOR_10_7_10, + MIPI_COMPRESSOR_10_8_10, + MIPI_COMPRESSOR_12_6_12, + MIPI_COMPRESSOR_12_7_12, + MIPI_COMPRESSOR_12_8_12, + N_MIPI_COMPRESSOR_METHODS +}; + +typedef enum { + MIPI_PREDICTOR_NONE = 0, + MIPI_PREDICTOR_TYPE1, + MIPI_PREDICTOR_TYPE2, + N_MIPI_PREDICTOR_TYPES +} mipi_predictor_t; + +typedef struct input_system_state_s input_system_state_t; +struct input_system_state_s { + ibuf_ctrl_state_t ibuf_ctrl_state[N_IBUF_CTRL_ID]; + csi_rx_fe_ctrl_state_t csi_rx_fe_ctrl_state[N_CSI_RX_FRONTEND_ID]; + csi_rx_be_ctrl_state_t csi_rx_be_ctrl_state[N_CSI_RX_BACKEND_ID]; + pixelgen_ctrl_state_t pixelgen_ctrl_state[N_PIXELGEN_ID]; + stream2mmio_state_t stream2mmio_state[N_STREAM2MMIO_ID]; + isys_irqc_state_t isys_irqc_state[N_ISYS_IRQ_ID]; +}; +#endif /* __INPUT_SYSTEM_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/input_system_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/input_system_private.h new file mode 100644 index 0000000000000000000000000000000000000000..97505e436047fb57f3f3a78bb2ed887b3e058285 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/input_system_private.h @@ -0,0 +1,128 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_SYSTEM_PRIVATE_H_INCLUDED__ +#define __INPUT_SYSTEM_PRIVATE_H_INCLUDED__ + +#include "input_system_public.h" + +STORAGE_CLASS_INPUT_SYSTEM_C input_system_err_t input_system_get_state( + const input_system_ID_t ID, + input_system_state_t *state) +{ + uint32_t i; + + (void)(ID); + + /* get the states of all CSI RX frontend devices */ + for (i = 0; i < N_CSI_RX_FRONTEND_ID; i++) { + csi_rx_fe_ctrl_get_state( + (csi_rx_frontend_ID_t)i, + &(state->csi_rx_fe_ctrl_state[i])); + } + + /* get the states of all CIS RX backend devices */ + for (i = 0; i < N_CSI_RX_BACKEND_ID; i++) { + csi_rx_be_ctrl_get_state( + (csi_rx_backend_ID_t)i, + &(state->csi_rx_be_ctrl_state[i])); + } + + /* get the states of all pixelgen devices */ + for (i = 0; i < N_PIXELGEN_ID; i++) { + pixelgen_ctrl_get_state( + (pixelgen_ID_t)i, + &(state->pixelgen_ctrl_state[i])); + } + + /* get the states of all stream2mmio devices */ + for (i = 0; i < N_STREAM2MMIO_ID; i++) { + stream2mmio_get_state( + (stream2mmio_ID_t)i, + &(state->stream2mmio_state[i])); + } + + /* get the states of all ibuf-controller devices */ + for (i = 0; i < N_IBUF_CTRL_ID; i++) { + ibuf_ctrl_get_state( + (ibuf_ctrl_ID_t)i, + &(state->ibuf_ctrl_state[i])); + } + + /* get the states of all isys irq controllers */ + for (i = 0; i < N_ISYS_IRQ_ID; i++) { + isys_irqc_state_get((isys_irq_ID_t)i, &(state->isys_irqc_state[i])); + } + + /* TODO: get the states of all ISYS2401 DMA devices */ + for (i = 0; i < N_ISYS2401_DMA_ID; i++) { + } + + return INPUT_SYSTEM_ERR_NO_ERROR; +} +STORAGE_CLASS_INPUT_SYSTEM_C void input_system_dump_state( + const input_system_ID_t ID, + input_system_state_t *state) +{ + uint32_t i; + + (void)(ID); + + /* dump the states of all CSI RX frontend devices */ + for (i = 0; i < N_CSI_RX_FRONTEND_ID; i++) { + csi_rx_fe_ctrl_dump_state( + (csi_rx_frontend_ID_t)i, + &(state->csi_rx_fe_ctrl_state[i])); + } + + /* dump the states of all CIS RX backend devices */ + for (i = 0; i < N_CSI_RX_BACKEND_ID; i++) { + csi_rx_be_ctrl_dump_state( + (csi_rx_backend_ID_t)i, + &(state->csi_rx_be_ctrl_state[i])); + } + + /* dump the states of all pixelgen devices */ + for (i = 0; i < N_PIXELGEN_ID; i++) { + pixelgen_ctrl_dump_state( + (pixelgen_ID_t)i, + &(state->pixelgen_ctrl_state[i])); + } + + /* dump the states of all st2mmio devices */ + for (i = 0; i < N_STREAM2MMIO_ID; i++) { + stream2mmio_dump_state( + (stream2mmio_ID_t)i, + &(state->stream2mmio_state[i])); + } + + /* dump the states of all ibuf-controller devices */ + for (i = 0; i < N_IBUF_CTRL_ID; i++) { + ibuf_ctrl_dump_state( + (ibuf_ctrl_ID_t)i, + &(state->ibuf_ctrl_state[i])); + } + + /* dump the states of all isys irq controllers */ + for (i = 0; i < N_ISYS_IRQ_ID; i++) { + isys_irqc_state_dump((isys_irq_ID_t)i, &(state->isys_irqc_state[i])); + } + + /* TODO: dump the states of all ISYS2401 DMA devices */ + for (i = 0; i < N_ISYS2401_DMA_ID; i++) { + } + + return; +} +#endif /* __INPUT_SYSTEM_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_dma.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..77767228985ef92934916524df1ae12d5f2c7a30 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_dma.c @@ -0,0 +1,40 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "isys_dma.h" +#include "assert_support.h" + +#ifndef __INLINE_ISYS2401_DMA__ +/* + * Include definitions for isys dma register access functions. isys_dma.h + * includes declarations of these functions by including isys_dma_public.h. + */ +#include "isys_dma_private.h" +#endif + +const isys2401_dma_channel N_ISYS2401_DMA_CHANNEL_PROCS[N_ISYS2401_DMA_ID] = { + N_ISYS2401_DMA_CHANNEL +}; + +void isys2401_dma_set_max_burst_size( + const isys2401_dma_ID_t dma_id, + uint32_t max_burst_size) +{ + assert(dma_id < N_ISYS2401_DMA_ID); + assert((max_burst_size > 0x00) && (max_burst_size <= 0xFF)); + + isys2401_dma_reg_store(dma_id, + DMA_DEV_INFO_REG_IDX(_DMA_V2_DEV_INTERF_MAX_BURST_IDX, HIVE_DMA_BUS_DDR_CONN), + (max_burst_size - 1)); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_dma_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_dma_local.h new file mode 100644 index 0000000000000000000000000000000000000000..5c694a26386e940eb8f6cdbfeeb05fedc87f44ed --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_dma_local.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_DMA_LOCAL_H_INCLUDED__ +#define __ISYS_DMA_LOCAL_H_INCLUDED__ + +#include "isys_dma_global.h" + +#endif /* __ISYS_DMA_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_dma_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_dma_private.h new file mode 100644 index 0000000000000000000000000000000000000000..2cd1aeecf617b17b47415d366b1fb54fa99dce78 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_dma_private.h @@ -0,0 +1,60 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_DMA_PRIVATE_H_INCLUDED__ +#define __ISYS_DMA_PRIVATE_H_INCLUDED__ + +#include "isys_dma_public.h" +#include "device_access.h" +#include "assert_support.h" +#include "dma.h" +#include "dma_v2_defs.h" +#include "print_support.h" + + +STORAGE_CLASS_ISYS2401_DMA_C void isys2401_dma_reg_store( + const isys2401_dma_ID_t dma_id, + const unsigned int reg, + const hrt_data value) +{ + unsigned int reg_loc; + + assert(dma_id < N_ISYS2401_DMA_ID); + assert(ISYS2401_DMA_BASE[dma_id] != (hrt_address)-1); + + reg_loc = ISYS2401_DMA_BASE[dma_id] + (reg * sizeof(hrt_data)); + + ia_css_print("isys dma store at addr(0x%x) val(%u)\n", reg_loc, (unsigned int)value); + ia_css_device_store_uint32(reg_loc, value); +} + +STORAGE_CLASS_ISYS2401_DMA_C hrt_data isys2401_dma_reg_load( + const isys2401_dma_ID_t dma_id, + const unsigned int reg) +{ + unsigned int reg_loc; + hrt_data value; + + assert(dma_id < N_ISYS2401_DMA_ID); + assert(ISYS2401_DMA_BASE[dma_id] != (hrt_address)-1); + + reg_loc = ISYS2401_DMA_BASE[dma_id] + (reg * sizeof(hrt_data)); + + value = ia_css_device_load_uint32(reg_loc); + ia_css_print("isys dma load from addr(0x%x) val(%u)\n", reg_loc, (unsigned int)value); + + return value; +} + +#endif /* __ISYS_DMA_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq.c new file mode 100644 index 0000000000000000000000000000000000000000..14d1d3b627a9dc6d8b10dfe109d43d6d31ec4c54 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq.c @@ -0,0 +1,39 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include "device_access.h" +#include "assert_support.h" +#include "ia_css_debug.h" +#include "isys_irq.h" + +#ifndef __INLINE_ISYS2401_IRQ__ +/* + * Include definitions for isys irq private functions. isys_irq.h includes + * declarations of these functions by including isys_irq_public.h. + */ +#include "isys_irq_private.h" +#endif + +/** Public interface */ +STORAGE_CLASS_ISYS2401_IRQ_C void isys_irqc_status_enable( + const isys_irq_ID_t isys_irqc_id) +{ + assert(isys_irqc_id < N_ISYS_IRQ_ID); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "Setting irq mask for port %u\n", isys_irqc_id); + isys_irqc_reg_store(isys_irqc_id, ISYS_IRQ_MASK_REG_IDX, ISYS_IRQ_MASK_REG_VALUE); + isys_irqc_reg_store(isys_irqc_id, ISYS_IRQ_CLEAR_REG_IDX, ISYS_IRQ_CLEAR_REG_VALUE); + isys_irqc_reg_store(isys_irqc_id, ISYS_IRQ_ENABLE_REG_IDX, ISYS_IRQ_ENABLE_REG_VALUE); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq_local.h new file mode 100644 index 0000000000000000000000000000000000000000..0bffb5680e255cfab532b2a24034ea840de8ea70 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq_local.h @@ -0,0 +1,35 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_IRQ_LOCAL_H__ +#define __ISYS_IRQ_LOCAL_H__ + +#include + +#if defined(USE_INPUT_SYSTEM_VERSION_2401) + +typedef struct isys_irqc_state_s isys_irqc_state_t; + +struct isys_irqc_state_s { + hrt_data edge; + hrt_data mask; + hrt_data status; + hrt_data enable; + hrt_data level_no; +/*hrt_data clear; */ /* write-only register */ +}; + +#endif /* defined(USE_INPUT_SYSTEM_VERSION_2401) */ + +#endif /* __ISYS_IRQ_LOCAL_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq_private.h new file mode 100644 index 0000000000000000000000000000000000000000..c17ce131c9e1c530fa405ba9e3ff6c128d7509f7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_irq_private.h @@ -0,0 +1,108 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_IRQ_PRIVATE_H__ +#define __ISYS_IRQ_PRIVATE_H__ + +#include "isys_irq_global.h" +#include "isys_irq_local.h" + +#if defined(USE_INPUT_SYSTEM_VERSION_2401) + +/* -------------------------------------------------------+ + | Native command interface (NCI) | + + -------------------------------------------------------*/ + +/** +* @brief Get the isys irq status. +* Refer to "isys_irq.h" for details. +*/ +STORAGE_CLASS_ISYS2401_IRQ_C void isys_irqc_state_get( + const isys_irq_ID_t isys_irqc_id, + isys_irqc_state_t *state) +{ + state->edge = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_EDGE_REG_IDX); + state->mask = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_MASK_REG_IDX); + state->status = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_STATUS_REG_IDX); + state->enable = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_ENABLE_REG_IDX); + state->level_no = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_LEVEL_NO_REG_IDX); + /* + ** Invalid to read/load from write-only register 'clear' + ** state->clear = isys_irqc_reg_load(isys_irqc_id, ISYS_IRQ_CLEAR_REG_IDX); + */ +} + +/** +* @brief Dump the isys irq status. +* Refer to "isys_irq.h" for details. +*/ +STORAGE_CLASS_ISYS2401_IRQ_C void isys_irqc_state_dump( + const isys_irq_ID_t isys_irqc_id, + const isys_irqc_state_t *state) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "isys irq controller id %d" + "\n\tstatus:0x%x\n\tedge:0x%x\n\tmask:0x%x" + "\n\tenable:0x%x\n\tlevel_not_pulse:0x%x\n", + isys_irqc_id, + state->status, state->edge, state->mask, state->enable, state->level_no); +} + +/** end of NCI */ + +/* -------------------------------------------------------+ + | Device level interface (DLI) | + + -------------------------------------------------------*/ + +/* Support functions */ +STORAGE_CLASS_ISYS2401_IRQ_C void isys_irqc_reg_store( + const isys_irq_ID_t isys_irqc_id, + const unsigned int reg_idx, + const hrt_data value) +{ + unsigned int reg_addr; + + assert(isys_irqc_id < N_ISYS_IRQ_ID); + assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX); + + reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data)); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "isys irq store at addr(0x%x) val(%u)\n", reg_addr, (unsigned int)value); + + ia_css_device_store_uint32(reg_addr, value); +} + +STORAGE_CLASS_ISYS2401_IRQ_C hrt_data isys_irqc_reg_load( + const isys_irq_ID_t isys_irqc_id, + const unsigned int reg_idx) +{ + unsigned int reg_addr; + hrt_data value; + + assert(isys_irqc_id < N_ISYS_IRQ_ID); + assert(reg_idx <= ISYS_IRQ_LEVEL_NO_REG_IDX); + + reg_addr = ISYS_IRQ_BASE[isys_irqc_id] + (reg_idx * sizeof(hrt_data)); + value = ia_css_device_load_uint32(reg_addr); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "isys irq load from addr(0x%x) val(%u)\n", reg_addr, (unsigned int)value); + + return value; +} + +/** end of DLI */ + +#endif /* defined(USE_INPUT_SYSTEM_VERSION_2401) */ + +#endif /* __ISYS_IRQ_PRIVATE_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio.c new file mode 100644 index 0000000000000000000000000000000000000000..67570138ba24ce7b9287e96f9696987e739fa1d0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio.c @@ -0,0 +1,21 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "isys_stream2mmio.h" + +const stream2mmio_sid_ID_t N_STREAM2MMIO_SID_PROCS[N_STREAM2MMIO_ID] = { + N_STREAM2MMIO_SID_ID, + STREAM2MMIO_SID4_ID, + STREAM2MMIO_SID4_ID +}; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio_local.h new file mode 100644 index 0000000000000000000000000000000000000000..801523977e1d4b10eb0643f7bdc0256c32c43c7d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio_local.h @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_STREAM2MMIO_LOCAL_H_INCLUDED__ +#define __ISYS_STREAM2MMIO_LOCAL_H_INCLUDED__ + +#include "isys_stream2mmio_global.h" + +typedef struct stream2mmio_state_s stream2mmio_state_t; +typedef struct stream2mmio_sid_state_s stream2mmio_sid_state_t; + +struct stream2mmio_sid_state_s { + hrt_data rcv_ack; + hrt_data pix_width_id; + hrt_data start_addr; + hrt_data end_addr; + hrt_data strides; + hrt_data num_items; + hrt_data block_when_no_cmd; +}; + +struct stream2mmio_state_s { + stream2mmio_sid_state_t sid_state[N_STREAM2MMIO_SID_ID]; +}; +#endif /* __ISYS_STREAM2MMIO_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio_private.h new file mode 100644 index 0000000000000000000000000000000000000000..1603a09b621ad7c9e6d4532971e82d3e1f36182f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/isys_stream2mmio_private.h @@ -0,0 +1,168 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__ +#define __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__ + +#include "isys_stream2mmio_public.h" +#include "device_access.h" /* ia_css_device_load_uint32 */ +#include "assert_support.h" /* assert */ +#include "print_support.h" /* print */ + +#define STREAM2MMIO_COMMAND_REG_ID 0 +#define STREAM2MMIO_ACKNOWLEDGE_REG_ID 1 +#define STREAM2MMIO_PIX_WIDTH_ID_REG_ID 2 +#define STREAM2MMIO_START_ADDR_REG_ID 3 /* master port address,NOT Byte */ +#define STREAM2MMIO_END_ADDR_REG_ID 4 /* master port address,NOT Byte */ +#define STREAM2MMIO_STRIDE_REG_ID 5 /* stride in master port words, increment is per packet for long sids, stride is not used for short sid's*/ +#define STREAM2MMIO_NUM_ITEMS_REG_ID 6 /* number of packets for store packets cmd, number of words for store_words cmd */ +#define STREAM2MMIO_BLOCK_WHEN_NO_CMD_REG_ID 7 /* if this register is 1, input will be stalled if there is no pending command for this sid */ +#define STREAM2MMIO_REGS_PER_SID 8 + +/***************************************************** + * + * Native command interface (NCI). + * + *****************************************************/ +/** + * @brief Get the stream2mmio-controller state. + * Refer to "stream2mmio_public.h" for details. + */ +STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_get_state( + const stream2mmio_ID_t ID, + stream2mmio_state_t *state) +{ + stream2mmio_sid_ID_t i; + + /* + * Get the values of the register-set per + * stream2mmio-controller sids. + */ + for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++) { + stream2mmio_get_sid_state(ID, i, &(state->sid_state[i])); + } +} + +/** + * @brief Get the state of the stream2mmio-controller sidess. + * Refer to "stream2mmio_public.h" for details. + */ +STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_get_sid_state( + const stream2mmio_ID_t ID, + const stream2mmio_sid_ID_t sid_id, + stream2mmio_sid_state_t *state) +{ + + state->rcv_ack = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_ACKNOWLEDGE_REG_ID); + + state->pix_width_id = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_PIX_WIDTH_ID_REG_ID); + + state->start_addr = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_START_ADDR_REG_ID); + + state->end_addr = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_END_ADDR_REG_ID); + + state->strides = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_STRIDE_REG_ID); + + state->num_items = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_NUM_ITEMS_REG_ID); + + state->block_when_no_cmd = + stream2mmio_reg_load(ID, sid_id, STREAM2MMIO_BLOCK_WHEN_NO_CMD_REG_ID); + +} + +/** + * @brief Dump the state of the stream2mmio-controller sidess. + * Refer to "stream2mmio_public.h" for details. + */ +STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_print_sid_state( + stream2mmio_sid_state_t *state) +{ + ia_css_print("\t \t Receive acks 0x%x\n", state->rcv_ack); + ia_css_print("\t \t Pixel width 0x%x\n", state->pix_width_id); + ia_css_print("\t \t Startaddr 0x%x\n", state->start_addr); + ia_css_print("\t \t Endaddr 0x%x\n", state->end_addr); + ia_css_print("\t \t Strides 0x%x\n", state->strides); + ia_css_print("\t \t Num Items 0x%x\n", state->num_items); + ia_css_print("\t \t block when no cmd 0x%x\n", state->block_when_no_cmd); + +} +/** + * @brief Dump the ibuf-controller state. + * Refer to "stream2mmio_public.h" for details. + */ +STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_dump_state( + const stream2mmio_ID_t ID, + stream2mmio_state_t *state) +{ + stream2mmio_sid_ID_t i; + + /* + * Get the values of the register-set per + * stream2mmio-controller sids. + */ + for (i = STREAM2MMIO_SID0_ID; i < N_STREAM2MMIO_SID_PROCS[ID]; i++) { + ia_css_print("StREAM2MMIO ID %d SID %d\n", ID, i); + stream2mmio_print_sid_state(&(state->sid_state[i])); + } +} +/** end of NCI */ + +/***************************************************** + * + * Device level interface (DLI). + * + *****************************************************/ +/** + * @brief Load the register value. + * Refer to "stream2mmio_public.h" for details. + */ +STORAGE_CLASS_STREAM2MMIO_C hrt_data stream2mmio_reg_load( + const stream2mmio_ID_t ID, + const stream2mmio_sid_ID_t sid_id, + const uint32_t reg_idx) +{ + uint32_t reg_bank_offset; + + assert(ID < N_STREAM2MMIO_ID); + + reg_bank_offset = STREAM2MMIO_REGS_PER_SID * sid_id; + return ia_css_device_load_uint32(STREAM2MMIO_CTRL_BASE[ID] + + (reg_bank_offset + reg_idx) * sizeof(hrt_data)); +} + + +/** + * @brief Store a value to the register. + * Refer to "stream2mmio_public.h" for details. + */ +STORAGE_CLASS_STREAM2MMIO_C void stream2mmio_reg_store( + const stream2mmio_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ + assert(ID < N_STREAM2MMIO_ID); + assert(STREAM2MMIO_CTRL_BASE[ID] != (hrt_address)-1); + + ia_css_device_store_uint32(STREAM2MMIO_CTRL_BASE[ID] + + reg * sizeof(hrt_data), value); +} +/** end of DLI */ + +#endif /* __ISYS_STREAM2MMIO_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/pixelgen_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/pixelgen_local.h new file mode 100644 index 0000000000000000000000000000000000000000..24f4da9aef4011cc1fd51671b221328d03638d4e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/pixelgen_local.h @@ -0,0 +1,50 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __PIXELGEN_LOCAL_H_INCLUDED__ +#define __PIXELGEN_LOCAL_H_INCLUDED__ + +#include "pixelgen_global.h" + +typedef struct pixelgen_ctrl_state_s pixelgen_ctrl_state_t; +struct pixelgen_ctrl_state_s { + hrt_data com_enable; + hrt_data prbs_rstval0; + hrt_data prbs_rstval1; + hrt_data syng_sid; + hrt_data syng_free_run; + hrt_data syng_pause; + hrt_data syng_nof_frames; + hrt_data syng_nof_pixels; + hrt_data syng_nof_line; + hrt_data syng_hblank_cyc; + hrt_data syng_vblank_cyc; + hrt_data syng_stat_hcnt; + hrt_data syng_stat_vcnt; + hrt_data syng_stat_fcnt; + hrt_data syng_stat_done; + hrt_data tpg_mode; + hrt_data tpg_hcnt_mask; + hrt_data tpg_vcnt_mask; + hrt_data tpg_xycnt_mask; + hrt_data tpg_hcnt_delta; + hrt_data tpg_vcnt_delta; + hrt_data tpg_r1; + hrt_data tpg_g1; + hrt_data tpg_b1; + hrt_data tpg_r2; + hrt_data tpg_g2; + hrt_data tpg_b2; +}; +#endif /* __PIXELGEN_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/pixelgen_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/pixelgen_private.h new file mode 100644 index 0000000000000000000000000000000000000000..3f34b508f0bfe9178f401a6fd29622f83a4522fe --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/pixelgen_private.h @@ -0,0 +1,164 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __PIXELGEN_PRIVATE_H_INCLUDED__ +#define __PIXELGEN_PRIVATE_H_INCLUDED__ +#include "pixelgen_public.h" +#include "hive_isp_css_host_ids_hrt.h" +#include "PixelGen_SysBlock_defs.h" +#include "device_access.h" /* ia_css_device_load_uint32 */ +#include "assert_support.h" /* assert */ + + +/***************************************************** + * + * Native command interface (NCI). + * + *****************************************************/ +/** + * @brief Get the pixelgen state. + * Refer to "pixelgen_public.h" for details. + */ +STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_get_state( + const pixelgen_ID_t ID, + pixelgen_ctrl_state_t *state) +{ + + state->com_enable = + pixelgen_ctrl_reg_load(ID, _PXG_COM_ENABLE_REG_IDX); + state->prbs_rstval0 = + pixelgen_ctrl_reg_load(ID, _PXG_PRBS_RSTVAL_REG0_IDX); + state->prbs_rstval1 = + pixelgen_ctrl_reg_load(ID, _PXG_PRBS_RSTVAL_REG1_IDX); + state->syng_sid = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_SID_REG_IDX); + state->syng_free_run = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_FREE_RUN_REG_IDX); + state->syng_pause = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_PAUSE_REG_IDX); + state->syng_nof_frames = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_FRAME_REG_IDX); + state->syng_nof_pixels = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_PIXEL_REG_IDX); + state->syng_nof_line = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_NOF_LINE_REG_IDX); + state->syng_hblank_cyc = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_HBLANK_CYC_REG_IDX); + state->syng_vblank_cyc = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_VBLANK_CYC_REG_IDX); + state->syng_stat_hcnt = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_HCNT_REG_IDX); + state->syng_stat_vcnt = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_VCNT_REG_IDX); + state->syng_stat_fcnt = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_FCNT_REG_IDX); + state->syng_stat_done = + pixelgen_ctrl_reg_load(ID, _PXG_SYNG_STAT_DONE_REG_IDX); + state->tpg_mode = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_MODE_REG_IDX); + state->tpg_hcnt_mask = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_HCNT_MASK_REG_IDX); + state->tpg_vcnt_mask = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_VCNT_MASK_REG_IDX); + state->tpg_xycnt_mask = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_XYCNT_MASK_REG_IDX); + state->tpg_hcnt_delta = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_HCNT_DELTA_REG_IDX); + state->tpg_vcnt_delta = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_VCNT_DELTA_REG_IDX); + state->tpg_r1 = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_R1_REG_IDX); + state->tpg_g1 = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_G1_REG_IDX); + state->tpg_b1 = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_B1_REG_IDX); + state->tpg_r2 = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_R2_REG_IDX); + state->tpg_g2 = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_G2_REG_IDX); + state->tpg_b2 = + pixelgen_ctrl_reg_load(ID, _PXG_TPG_B2_REG_IDX); +} +/** + * @brief Dump the pixelgen state. + * Refer to "pixelgen_public.h" for details. + */ +STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_dump_state( + const pixelgen_ID_t ID, + pixelgen_ctrl_state_t *state) +{ + ia_css_print("Pixel Generator ID %d Enable 0x%x \n", ID, state->com_enable); + ia_css_print("Pixel Generator ID %d PRBS reset vlue 0 0x%x \n", ID, state->prbs_rstval0); + ia_css_print("Pixel Generator ID %d PRBS reset vlue 1 0x%x \n", ID, state->prbs_rstval1); + ia_css_print("Pixel Generator ID %d SYNC SID 0x%x \n", ID, state->syng_sid); + ia_css_print("Pixel Generator ID %d syng free run 0x%x \n", ID, state->syng_free_run); + ia_css_print("Pixel Generator ID %d syng pause 0x%x \n", ID, state->syng_pause); + ia_css_print("Pixel Generator ID %d syng no of frames 0x%x \n", ID, state->syng_nof_frames); + ia_css_print("Pixel Generator ID %d syng no of pixels 0x%x \n", ID, state->syng_nof_pixels); + ia_css_print("Pixel Generator ID %d syng no of line 0x%x \n", ID, state->syng_nof_line); + ia_css_print("Pixel Generator ID %d syng hblank cyc 0x%x \n", ID, state->syng_hblank_cyc); + ia_css_print("Pixel Generator ID %d syng vblank cyc 0x%x \n", ID, state->syng_vblank_cyc); + ia_css_print("Pixel Generator ID %d syng stat hcnt 0x%x \n", ID, state->syng_stat_hcnt); + ia_css_print("Pixel Generator ID %d syng stat vcnt 0x%x \n", ID, state->syng_stat_vcnt); + ia_css_print("Pixel Generator ID %d syng stat fcnt 0x%x \n", ID, state->syng_stat_fcnt); + ia_css_print("Pixel Generator ID %d syng stat done 0x%x \n", ID, state->syng_stat_done); + ia_css_print("Pixel Generator ID %d tpg modee 0x%x \n", ID, state->tpg_mode); + ia_css_print("Pixel Generator ID %d tpg hcnt mask 0x%x \n", ID, state->tpg_hcnt_mask); + ia_css_print("Pixel Generator ID %d tpg hcnt mask 0x%x \n", ID, state->tpg_hcnt_mask); + ia_css_print("Pixel Generator ID %d tpg xycnt mask 0x%x \n", ID, state->tpg_xycnt_mask); + ia_css_print("Pixel Generator ID %d tpg hcnt delta 0x%x \n", ID, state->tpg_hcnt_delta); + ia_css_print("Pixel Generator ID %d tpg vcnt delta 0x%x \n", ID, state->tpg_vcnt_delta); + ia_css_print("Pixel Generator ID %d tpg r1 0x%x \n", ID, state->tpg_r1); + ia_css_print("Pixel Generator ID %d tpg g1 0x%x \n", ID, state->tpg_g1); + ia_css_print("Pixel Generator ID %d tpg b1 0x%x \n", ID, state->tpg_b1); + ia_css_print("Pixel Generator ID %d tpg r2 0x%x \n", ID, state->tpg_r2); + ia_css_print("Pixel Generator ID %d tpg g2 0x%x \n", ID, state->tpg_g2); + ia_css_print("Pixel Generator ID %d tpg b2 0x%x \n", ID, state->tpg_b2); +} +/* end of NCI */ +/***************************************************** + * + * Device level interface (DLI). + * + *****************************************************/ +/** + * @brief Load the register value. + * Refer to "pixelgen_public.h" for details. + */ +STORAGE_CLASS_PIXELGEN_C hrt_data pixelgen_ctrl_reg_load( + const pixelgen_ID_t ID, + const hrt_address reg) +{ + assert(ID < N_PIXELGEN_ID); + assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address)-1); + return ia_css_device_load_uint32(PIXELGEN_CTRL_BASE[ID] + reg*sizeof(hrt_data)); +} + + +/** + * @brief Store a value to the register. + * Refer to "pixelgen_ctrl_public.h" for details. + */ +STORAGE_CLASS_PIXELGEN_C void pixelgen_ctrl_reg_store( + const pixelgen_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ + assert(ID < N_PIXELGEN_ID); + assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address)-1); + + ia_css_device_store_uint32(PIXELGEN_CTRL_BASE[ID] + reg*sizeof(hrt_data), value); +} +/** end of DLI */ +#endif /* __PIXELGEN_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/system_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/system_local.h new file mode 100644 index 0000000000000000000000000000000000000000..c1667098970213ce0c333f5765297932f63325d9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/host/system_local.h @@ -0,0 +1,381 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SYSTEM_LOCAL_H_INCLUDED__ +#define __SYSTEM_LOCAL_H_INCLUDED__ + +#ifdef HRT_ISP_CSS_CUSTOM_HOST +#ifndef HRT_USE_VIR_ADDRS +#define HRT_USE_VIR_ADDRS +#endif +/* This interface is deprecated */ +/*#include "hive_isp_css_custom_host_hrt.h"*/ +#endif + +#include "system_global.h" + +#ifdef __FIST__ +#define HRT_ADDRESS_WIDTH 32 /* Surprise, this is a local property and even differs per platform */ +#else +#define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property */ +#endif + +#if !defined(__KERNEL__) || (1 == 1) +/* This interface is deprecated */ +#include "hrt/hive_types.h" +#else /* __KERNEL__ */ +#include + +#if HRT_ADDRESS_WIDTH == 64 +typedef uint64_t hrt_address; +#elif HRT_ADDRESS_WIDTH == 32 +typedef uint32_t hrt_address; +#else +#error "system_local.h: HRT_ADDRESS_WIDTH must be one of {32,64}" +#endif + +typedef uint32_t hrt_vaddress; +typedef uint32_t hrt_data; +#endif /* __KERNEL__ */ + +/* + * Cell specific address maps + */ +#if HRT_ADDRESS_WIDTH == 64 + +#define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */ + +/* DDR */ +static const hrt_address DDR_BASE[N_DDR_ID] = { + 0x0000000120000000ULL}; + +/* ISP */ +static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = { + 0x0000000000020000ULL}; + +static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = { + 0x0000000000200000ULL}; + +static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = { + 0x0000000000100000ULL}; + +static const hrt_address ISP_VAMEM_BASE[N_VAMEM_ID] = { + 0x00000000001C0000ULL, + 0x00000000001D0000ULL, + 0x00000000001E0000ULL}; + +static const hrt_address ISP_HMEM_BASE[N_HMEM_ID] = { + 0x00000000001F0000ULL}; + +/* SP */ +static const hrt_address SP_CTRL_BASE[N_SP_ID] = { + 0x0000000000010000ULL}; + +static const hrt_address SP_DMEM_BASE[N_SP_ID] = { + 0x0000000000300000ULL}; + +/* MMU */ +#if defined(IS_ISP_2400_MAMOIADA_SYSTEM) || defined(IS_ISP_2401_MAMOIADA_SYSTEM) +/* + * MMU0_ID: The data MMU + * MMU1_ID: The icache MMU + */ +static const hrt_address MMU_BASE[N_MMU_ID] = { + 0x0000000000070000ULL, + 0x00000000000A0000ULL}; +#else +#error "system_local.h: SYSTEM must be one of {2400, 2401 }" +#endif + +/* DMA */ +static const hrt_address DMA_BASE[N_DMA_ID] = { + 0x0000000000040000ULL}; + +static const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID] = { + 0x00000000000CA000ULL}; + +/* IRQ */ +static const hrt_address IRQ_BASE[N_IRQ_ID] = { + 0x0000000000000500ULL, + 0x0000000000030A00ULL, + 0x000000000008C000ULL, + 0x0000000000090200ULL}; +/* + 0x0000000000000500ULL}; + */ + +/* GDC */ +static const hrt_address GDC_BASE[N_GDC_ID] = { + 0x0000000000050000ULL, + 0x0000000000060000ULL}; + +/* FIFO_MONITOR (not a subset of GP_DEVICE) */ +static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = { + 0x0000000000000000ULL}; + +/* +static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = { + 0x0000000000000000ULL}; + +static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = { + 0x0000000000090000ULL}; +*/ + +/* GP_DEVICE (single base for all separate GP_REG instances) */ +static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = { + 0x0000000000000000ULL}; + +/*GP TIMER , all timer registers are inter-twined, + * so, having multiple base addresses for + * different timers does not help*/ +static const hrt_address GP_TIMER_BASE = + (hrt_address)0x0000000000000600ULL; + +/* GPIO */ +static const hrt_address GPIO_BASE[N_GPIO_ID] = { + 0x0000000000000400ULL}; + +/* TIMED_CTRL */ +static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = { + 0x0000000000000100ULL}; + + +/* INPUT_FORMATTER */ +static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = { + 0x0000000000030000ULL, + 0x0000000000030200ULL, + 0x0000000000030400ULL, + 0x0000000000030600ULL}; /* memcpy() */ + +/* INPUT_SYSTEM */ +static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = { + 0x0000000000080000ULL}; +/* 0x0000000000081000ULL, */ /* capture A */ +/* 0x0000000000082000ULL, */ /* capture B */ +/* 0x0000000000083000ULL, */ /* capture C */ +/* 0x0000000000084000ULL, */ /* Acquisition */ +/* 0x0000000000085000ULL, */ /* DMA */ +/* 0x0000000000089000ULL, */ /* ctrl */ +/* 0x000000000008A000ULL, */ /* GP regs */ +/* 0x000000000008B000ULL, */ /* FIFO */ +/* 0x000000000008C000ULL, */ /* IRQ */ + +/* RX, the MIPI lane control regs start at offset 0 */ +static const hrt_address RX_BASE[N_RX_ID] = { + 0x0000000000080100ULL}; + +/* IBUF_CTRL, part of the Input System 2401 */ +static const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID] = { + 0x00000000000C1800ULL, /* ibuf controller A */ + 0x00000000000C3800ULL, /* ibuf controller B */ + 0x00000000000C5800ULL /* ibuf controller C */ +}; + +/* ISYS IRQ Controllers, part of the Input System 2401 */ +static const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID] = { + 0x00000000000C1400ULL, /* port a */ + 0x00000000000C3400ULL, /* port b */ + 0x00000000000C5400ULL /* port c */ +}; + +/* CSI FE, part of the Input System 2401 */ +static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID] = { + 0x00000000000C0400ULL, /* csi fe controller A */ + 0x00000000000C2400ULL, /* csi fe controller B */ + 0x00000000000C4400ULL /* csi fe controller C */ +}; +/* CSI BE, part of the Input System 2401 */ +static const hrt_address CSI_RX_BE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = { + 0x00000000000C0800ULL, /* csi be controller A */ + 0x00000000000C2800ULL, /* csi be controller B */ + 0x00000000000C4800ULL /* csi be controller C */ +}; +/* PIXEL Generator, part of the Input System 2401 */ +static const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = { + 0x00000000000C1000ULL, /* pixel gen controller A */ + 0x00000000000C3000ULL, /* pixel gen controller B */ + 0x00000000000C5000ULL /* pixel gen controller C */ +}; +/* Stream2MMIO, part of the Input System 2401 */ +static const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = { + 0x00000000000C0C00ULL, /* stream2mmio controller A */ + 0x00000000000C2C00ULL, /* stream2mmio controller B */ + 0x00000000000C4C00ULL /* stream2mmio controller C */ +}; +#elif HRT_ADDRESS_WIDTH == 32 + +#define GP_FIFO_BASE ((hrt_address)0x00090104) /* This is NOT a base address */ + +/* DDR : Attention, this value not defined in 32-bit */ +static const hrt_address DDR_BASE[N_DDR_ID] = { + 0x00000000UL}; + +/* ISP */ +static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = { + 0x00020000UL}; + +static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = { + 0xffffffffUL}; + +static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = { + 0xffffffffUL}; + +static const hrt_address ISP_VAMEM_BASE[N_VAMEM_ID] = { + 0xffffffffUL, + 0xffffffffUL, + 0xffffffffUL}; + +static const hrt_address ISP_HMEM_BASE[N_HMEM_ID] = { + 0xffffffffUL}; + +/* SP */ +static const hrt_address SP_CTRL_BASE[N_SP_ID] = { + 0x00010000UL}; + +static const hrt_address SP_DMEM_BASE[N_SP_ID] = { + 0x00300000UL}; + +/* MMU */ +#if defined(IS_ISP_2400_MAMOIADA_SYSTEM) || defined(IS_ISP_2401_MAMOIADA_SYSTEM) +/* + * MMU0_ID: The data MMU + * MMU1_ID: The icache MMU + */ +static const hrt_address MMU_BASE[N_MMU_ID] = { + 0x00070000UL, + 0x000A0000UL}; +#else +#error "system_local.h: SYSTEM must be one of {2400, 2401 }" +#endif + +/* DMA */ +static const hrt_address DMA_BASE[N_DMA_ID] = { + 0x00040000UL}; + +static const hrt_address ISYS2401_DMA_BASE[N_ISYS2401_DMA_ID] = { + 0x000CA000UL}; + +/* IRQ */ +static const hrt_address IRQ_BASE[N_IRQ_ID] = { + 0x00000500UL, + 0x00030A00UL, + 0x0008C000UL, + 0x00090200UL}; +/* + 0x00000500UL}; + */ + +/* GDC */ +static const hrt_address GDC_BASE[N_GDC_ID] = { + 0x00050000UL, + 0x00060000UL}; + +/* FIFO_MONITOR (not a subset of GP_DEVICE) */ +static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = { + 0x00000000UL}; + +/* +static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = { + 0x00000000UL}; + +static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = { + 0x00090000UL}; +*/ + +/* GP_DEVICE (single base for all separate GP_REG instances) */ +static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = { + 0x00000000UL}; + +/*GP TIMER , all timer registers are inter-twined, + * so, having multiple base addresses for + * different timers does not help*/ +static const hrt_address GP_TIMER_BASE = + (hrt_address)0x00000600UL; +/* GPIO */ +static const hrt_address GPIO_BASE[N_GPIO_ID] = { + 0x00000400UL}; + +/* TIMED_CTRL */ +static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = { + 0x00000100UL}; + + +/* INPUT_FORMATTER */ +static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = { + 0x00030000UL, + 0x00030200UL, + 0x00030400UL}; +/* 0x00030600UL, */ /* memcpy() */ + +/* INPUT_SYSTEM */ +static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = { + 0x00080000UL}; +/* 0x00081000UL, */ /* capture A */ +/* 0x00082000UL, */ /* capture B */ +/* 0x00083000UL, */ /* capture C */ +/* 0x00084000UL, */ /* Acquisition */ +/* 0x00085000UL, */ /* DMA */ +/* 0x00089000UL, */ /* ctrl */ +/* 0x0008A000UL, */ /* GP regs */ +/* 0x0008B000UL, */ /* FIFO */ +/* 0x0008C000UL, */ /* IRQ */ + +/* RX, the MIPI lane control regs start at offset 0 */ +static const hrt_address RX_BASE[N_RX_ID] = { + 0x00080100UL}; + +/* IBUF_CTRL, part of the Input System 2401 */ +static const hrt_address IBUF_CTRL_BASE[N_IBUF_CTRL_ID] = { + 0x000C1800UL, /* ibuf controller A */ + 0x000C3800UL, /* ibuf controller B */ + 0x000C5800UL /* ibuf controller C */ +}; + +/* ISYS IRQ Controllers, part of the Input System 2401 */ +static const hrt_address ISYS_IRQ_BASE[N_ISYS_IRQ_ID] = { + 0x000C1400ULL, /* port a */ + 0x000C3400ULL, /* port b */ + 0x000C5400ULL /* port c */ +}; + +/* CSI FE, part of the Input System 2401 */ +static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_FRONTEND_ID] = { + 0x000C0400UL, /* csi fe controller A */ + 0x000C2400UL, /* csi fe controller B */ + 0x000C4400UL /* csi fe controller C */ +}; +/* CSI BE, part of the Input System 2401 */ +static const hrt_address CSI_RX_FE_CTRL_BASE[N_CSI_RX_BACKEND_ID] = { + 0x000C0800UL, /* csi be controller A */ + 0x000C2800UL, /* csi be controller B */ + 0x000C4800UL /* csi be controller C */ +}; +/* PIXEL Generator, part of the Input System 2401 */ +static const hrt_address PIXELGEN_CTRL_BASE[N_PIXELGEN_ID] = { + 0x000C1000UL, /* pixel gen controller A */ + 0x000C3000UL, /* pixel gen controller B */ + 0x000C5000UL /* pixel gen controller C */ +}; +/* Stream2MMIO, part of the Input System 2401 */ +static const hrt_address STREAM2MMIO_CTRL_BASE[N_STREAM2MMIO_ID] = { + 0x000C0C00UL, /* stream2mmio controller A */ + 0x000C2C00UL, /* stream2mmio controller B */ + 0x000C4C00UL /* stream2mmio controller C */ +}; + +#else +#error "system_local.h: HRT_ADDRESS_WIDTH must be one of {32,64}" +#endif + +#endif /* __SYSTEM_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/PixelGen_SysBlock_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/PixelGen_SysBlock_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..1b3391c242a3d1be04c931206651791ba49fd2bc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/PixelGen_SysBlock_defs.h @@ -0,0 +1,126 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _PixelGen_SysBlock_defs_h +#define _PixelGen_SysBlock_defs_h + +#ifdef ISYS2401_PXG_A +#else +#ifdef ISYS2401_PXG_B +#else +#ifdef ISYS2401_PXG_C +#else +#include +#endif +#endif +#endif + +/* Parematers and User_Parameters for HSS */ +#define _PXG_PPC Ppc +#define _PXG_PIXEL_BITS PixelWidth +#define _PXG_MAX_NOF_SID MaxNofSids +#define _PXG_DATA_BITS DataWidth +#define _PXG_CNT_BITS CntWidth +#define _PXG_FIFODEPTH FifoDepth +#define _PXG_DBG Dbg_device_not_included + +/* ID's and Address */ +#define _PXG_ADRRESS_ALIGN_REG 4 + +#define _PXG_COM_ENABLE_REG_IDX 0 +#define _PXG_PRBS_RSTVAL_REG0_IDX 1 +#define _PXG_PRBS_RSTVAL_REG1_IDX 2 +#define _PXG_SYNG_SID_REG_IDX 3 +#define _PXG_SYNG_FREE_RUN_REG_IDX 4 +#define _PXG_SYNG_PAUSE_REG_IDX 5 +#define _PXG_SYNG_NOF_FRAME_REG_IDX 6 +#define _PXG_SYNG_NOF_PIXEL_REG_IDX 7 +#define _PXG_SYNG_NOF_LINE_REG_IDX 8 +#define _PXG_SYNG_HBLANK_CYC_REG_IDX 9 +#define _PXG_SYNG_VBLANK_CYC_REG_IDX 10 +#define _PXG_SYNG_STAT_HCNT_REG_IDX 11 +#define _PXG_SYNG_STAT_VCNT_REG_IDX 12 +#define _PXG_SYNG_STAT_FCNT_REG_IDX 13 +#define _PXG_SYNG_STAT_DONE_REG_IDX 14 +#define _PXG_TPG_MODE_REG_IDX 15 +#define _PXG_TPG_HCNT_MASK_REG_IDX 16 +#define _PXG_TPG_VCNT_MASK_REG_IDX 17 +#define _PXG_TPG_XYCNT_MASK_REG_IDX 18 +#define _PXG_TPG_HCNT_DELTA_REG_IDX 19 +#define _PXG_TPG_VCNT_DELTA_REG_IDX 20 +#define _PXG_TPG_R1_REG_IDX 21 +#define _PXG_TPG_G1_REG_IDX 22 +#define _PXG_TPG_B1_REG_IDX 23 +#define _PXG_TPG_R2_REG_IDX 24 +#define _PXG_TPG_G2_REG_IDX 25 +#define _PXG_TPG_B2_REG_IDX 26 +/* */ +#define _PXG_SYNG_PAUSE_CYCLES 0 +/* Subblock ID's */ +#define _PXG_DISBALE_IDX 0 +#define _PXG_PRBS_IDX 0 +#define _PXG_TPG_IDX 1 +#define _PXG_SYNG_IDX 2 +#define _PXG_SMUX_IDX 3 +/* Register Widths */ +#define _PXG_COM_ENABLE_REG_WIDTH 2 +#define _PXG_COM_SRST_REG_WIDTH 4 +#define _PXG_PRBS_RSTVAL_REG0_WIDTH 31 +#define _PXG_PRBS_RSTVAL_REG1_WIDTH 31 + +#define _PXG_SYNG_SID_REG_WIDTH 3 + +#define _PXG_SYNG_FREE_RUN_REG_WIDTH 1 +#define _PXG_SYNG_PAUSE_REG_WIDTH 1 +/* +#define _PXG_SYNG_NOF_FRAME_REG_WIDTH +#define _PXG_SYNG_NOF_PIXEL_REG_WIDTH +#define _PXG_SYNG_NOF_LINE_REG_WIDTH +#define _PXG_SYNG_HBLANK_CYC_REG_WIDTH +#define _PXG_SYNG_VBLANK_CYC_REG_WIDTH +#define _PXG_SYNG_STAT_HCNT_REG_WIDTH +#define _PXG_SYNG_STAT_VCNT_REG_WIDTH +#define _PXG_SYNG_STAT_FCNT_REG_WIDTH +*/ +#define _PXG_SYNG_STAT_DONE_REG_WIDTH 1 +#define _PXG_TPG_MODE_REG_WIDTH 2 +/* +#define _PXG_TPG_HCNT_MASK_REG_WIDTH +#define _PXG_TPG_VCNT_MASK_REG_WIDTH +#define _PXG_TPG_XYCNT_MASK_REG_WIDTH +*/ +#define _PXG_TPG_HCNT_DELTA_REG_WIDTH 4 +#define _PXG_TPG_VCNT_DELTA_REG_WIDTH 4 +/* +#define _PXG_TPG_R1_REG_WIDTH +#define _PXG_TPG_G1_REG_WIDTH +#define _PXG_TPG_B1_REG_WIDTH +#define _PXG_TPG_R2_REG_WIDTH +#define _PXG_TPG_G2_REG_WIDTH +#define _PXG_TPG_B2_REG_WIDTH +*/ +#define _PXG_FIFO_DEPTH 2 +/* MISC */ +#define _PXG_ENABLE_REG_VAL 1 +#define _PXG_PRBS_ENABLE_REG_VAL 1 +#define _PXG_TPG_ENABLE_REG_VAL 2 +#define _PXG_SYNG_ENABLE_REG_VAL 4 +#define _PXG_FIFO_ENABLE_REG_VAL 8 +#define _PXG_PXL_BITS 14 +#define _PXG_INVALID_FLAG 0xDEADBEEF +#define _PXG_CAFE_FLAG 0xCAFEBABE + + +#endif /* _PixelGen_SysBlock_defs_h */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/bits.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/bits.h new file mode 100644 index 0000000000000000000000000000000000000000..e71e33d9d1434c91cd8317ea40d5719c02b86172 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/bits.h @@ -0,0 +1,104 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HRT_BITS_H +#define _HRT_BITS_H + +#include "defs.h" + +#define _hrt_ones(n) HRTCAT(_hrt_ones_, n) +#define _hrt_ones_0x0 0x00000000U +#define _hrt_ones_0x1 0x00000001U +#define _hrt_ones_0x2 0x00000003U +#define _hrt_ones_0x3 0x00000007U +#define _hrt_ones_0x4 0x0000000FU +#define _hrt_ones_0x5 0x0000001FU +#define _hrt_ones_0x6 0x0000003FU +#define _hrt_ones_0x7 0x0000007FU +#define _hrt_ones_0x8 0x000000FFU +#define _hrt_ones_0x9 0x000001FFU +#define _hrt_ones_0xA 0x000003FFU +#define _hrt_ones_0xB 0x000007FFU +#define _hrt_ones_0xC 0x00000FFFU +#define _hrt_ones_0xD 0x00001FFFU +#define _hrt_ones_0xE 0x00003FFFU +#define _hrt_ones_0xF 0x00007FFFU +#define _hrt_ones_0x10 0x0000FFFFU +#define _hrt_ones_0x11 0x0001FFFFU +#define _hrt_ones_0x12 0x0003FFFFU +#define _hrt_ones_0x13 0x0007FFFFU +#define _hrt_ones_0x14 0x000FFFFFU +#define _hrt_ones_0x15 0x001FFFFFU +#define _hrt_ones_0x16 0x003FFFFFU +#define _hrt_ones_0x17 0x007FFFFFU +#define _hrt_ones_0x18 0x00FFFFFFU +#define _hrt_ones_0x19 0x01FFFFFFU +#define _hrt_ones_0x1A 0x03FFFFFFU +#define _hrt_ones_0x1B 0x07FFFFFFU +#define _hrt_ones_0x1C 0x0FFFFFFFU +#define _hrt_ones_0x1D 0x1FFFFFFFU +#define _hrt_ones_0x1E 0x3FFFFFFFU +#define _hrt_ones_0x1F 0x7FFFFFFFU +#define _hrt_ones_0x20 0xFFFFFFFFU + +#define _hrt_ones_0 _hrt_ones_0x0 +#define _hrt_ones_1 _hrt_ones_0x1 +#define _hrt_ones_2 _hrt_ones_0x2 +#define _hrt_ones_3 _hrt_ones_0x3 +#define _hrt_ones_4 _hrt_ones_0x4 +#define _hrt_ones_5 _hrt_ones_0x5 +#define _hrt_ones_6 _hrt_ones_0x6 +#define _hrt_ones_7 _hrt_ones_0x7 +#define _hrt_ones_8 _hrt_ones_0x8 +#define _hrt_ones_9 _hrt_ones_0x9 +#define _hrt_ones_10 _hrt_ones_0xA +#define _hrt_ones_11 _hrt_ones_0xB +#define _hrt_ones_12 _hrt_ones_0xC +#define _hrt_ones_13 _hrt_ones_0xD +#define _hrt_ones_14 _hrt_ones_0xE +#define _hrt_ones_15 _hrt_ones_0xF +#define _hrt_ones_16 _hrt_ones_0x10 +#define _hrt_ones_17 _hrt_ones_0x11 +#define _hrt_ones_18 _hrt_ones_0x12 +#define _hrt_ones_19 _hrt_ones_0x13 +#define _hrt_ones_20 _hrt_ones_0x14 +#define _hrt_ones_21 _hrt_ones_0x15 +#define _hrt_ones_22 _hrt_ones_0x16 +#define _hrt_ones_23 _hrt_ones_0x17 +#define _hrt_ones_24 _hrt_ones_0x18 +#define _hrt_ones_25 _hrt_ones_0x19 +#define _hrt_ones_26 _hrt_ones_0x1A +#define _hrt_ones_27 _hrt_ones_0x1B +#define _hrt_ones_28 _hrt_ones_0x1C +#define _hrt_ones_29 _hrt_ones_0x1D +#define _hrt_ones_30 _hrt_ones_0x1E +#define _hrt_ones_31 _hrt_ones_0x1F +#define _hrt_ones_32 _hrt_ones_0x20 + +#define _hrt_mask(b, n) \ + (_hrt_ones(n) << (b)) +#define _hrt_get_bits(w, b, n) \ + (((w) >> (b)) & _hrt_ones(n)) +#define _hrt_set_bits(w, b, n, v) \ + (((w) & ~_hrt_mask(b, n)) | (((v) & _hrt_ones(n)) << (b))) +#define _hrt_get_bit(w, b) \ + (((w) >> (b)) & 1) +#define _hrt_set_bit(w, b, v) \ + (((w) & (~(1 << (b)))) | (((v)&1) << (b))) +#define _hrt_set_lower_half(w, v) \ + _hrt_set_bits(w, 0, 16, v) +#define _hrt_set_upper_half(w, v) \ + _hrt_set_bits(w, 16, 16, v) + +#endif /* _HRT_BITS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/cell_params.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/cell_params.h new file mode 100644 index 0000000000000000000000000000000000000000..b5756bfe8eb6b1e10c7f70659bc20e6537e8df1c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/cell_params.h @@ -0,0 +1,42 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _cell_params_h +#define _cell_params_h + +#define SP_PMEM_LOG_WIDTH_BITS 6 /*Width of PC, 64 bits, 8 bytes*/ +#define SP_ICACHE_TAG_BITS 4 /*size of tag*/ +#define SP_ICACHE_SET_BITS 8 /* 256 sets*/ +#define SP_ICACHE_BLOCKS_PER_SET_BITS 1 /* 2 way associative*/ +#define SP_ICACHE_BLOCK_ADDRESS_BITS 11 /* 2048 lines capacity*/ + +#define SP_ICACHE_ADDRESS_BITS \ + (SP_ICACHE_TAG_BITS+SP_ICACHE_BLOCK_ADDRESS_BITS) + +#define SP_PMEM_DEPTH (1< input_selector*/ +/* !! Changes here should be copied to systems/isp/isp_css/bin/conv_transmitter_cmd.tcl !! */ +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB888 0 // 36 'h24 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB555 1 // 33 'h +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB444 2 // 32 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB565 3 // 34 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB666 4 // 35 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW10 6 // 43 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW6 7 // 40 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW7 8 // 41 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW12 9 // 43 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW14 10 // 45 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8 11 // 30 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10 12 // 25 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_8 13 // 30 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_10 14 // 31 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_1 15 // 48 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8L 16 // 26 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_Emb 17 // 18 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_2 18 // 49 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_3 19 // 50 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_4 20 // 51 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_5 21 // 52 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_6 22 // 53 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_7 23 // 54 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_8 24 // 55 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8_CSPS 25 // 28 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10_CSPS 26 // 29 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW16 27 // ? +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18 28 // ? +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_2 29 // ? Option 2 for depacketiser +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_3 30 // ? Option 3 for depacketiser +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding + +/* definition for state machine of data FIFO for decode different type of data */ +#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV420_10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_YUV420_8L_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV422_8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV422_10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB555_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB565_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9 +#define _HRT_CSS_RECEIVER_2400_RGB888_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW6_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW7_REPEAT_PTN 7 +#define _HRT_CSS_RECEIVER_2400_RAW8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_RAW10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW14_REPEAT_PTN 7 + +#define _HRT_CSS_RECEIVER_2400_MAX_REPEAT_PTN _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN + +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_WIDTH 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_IDX 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_WIDTH 1 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_USD_BITS 4 /* bits per USD type */ + +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_EN_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_OPTION_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_EN_IDX 8 + +#define _HRT_CSS_RECEIVER_2400_BE_COMP_NO_COMP 0 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_6_10 1 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_7_10 2 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_8_10 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_6_12 4 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_7_12 5 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_8_12 6 + + +/* packet bit definition */ +#define _HRT_CSS_RECEIVER_2400_PKT_SOP_IDX 32 +#define _HRT_CSS_RECEIVER_2400_PKT_SOP_BITS 1 +#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_IDX 22 +#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_BITS 2 +#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_IDX 16 +#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_BITS 6 +#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_IDX 0 +#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_BITS 16 +#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_IDX 0 +#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_BITS 32 + + +/*************************************************************************************************/ +/* Custom Decoding */ +/* These Custom Defs are defined based on design-time config in "csi_be_pixel_formatter.chdl" !! */ +/*************************************************************************************************/ +#define BE_CUST_EN_IDX 0 /* 2bits */ +#define BE_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */ +#define BE_CUST_EN_WIDTH 8 +#define BE_CUST_MODE_ALL 1 /* Enable Custom Decoding for all DATA IDs */ +#define BE_CUST_MODE_ONE 3 /* Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID */ + +/* Data State config = {get_bits(6bits), valid(1bit)} */ +#define BE_CUST_DATA_STATE_S0_IDX 0 /* 7bits */ +#define BE_CUST_DATA_STATE_S1_IDX 7 /* 7bits */ +#define BE_CUST_DATA_STATE_S2_IDX 14 /* 7bits */ +#define BE_CUST_DATA_STATE_WIDTH 21 +#define BE_CUST_DATA_STATE_VALID_IDX 0 /* 1bits */ +#define BE_CUST_DATA_STATE_GETBITS_IDX 1 /* 6bits */ + +/* Pixel Extractor config */ +#define BE_CUST_PIX_EXT_DATA_ALIGN_IDX 0 /* 5bits */ +#define BE_CUST_PIX_EXT_PIX_ALIGN_IDX 5 /* 5bits */ +#define BE_CUST_PIX_EXT_PIX_MASK_IDX 10 /* 18bits */ +#define BE_CUST_PIX_EXT_PIX_EN_IDX 28 /* 1bits */ +#define BE_CUST_PIX_EXT_WIDTH 29 + +/* Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} */ +#define BE_CUST_PIX_VALID_EOP_P0_IDX 0 /* 4bits */ +#define BE_CUST_PIX_VALID_EOP_P1_IDX 4 /* 4bits */ +#define BE_CUST_PIX_VALID_EOP_P2_IDX 8 /* 4bits */ +#define BE_CUST_PIX_VALID_EOP_P3_IDX 12 /* 4bits */ +#define BE_CUST_PIX_VALID_EOP_WIDTH 16 +#define BE_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 /* Normal (NO less get_bits case) Valid - 1bits */ +#define BE_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 /* Normal (NO less get_bits case) EoP - 1bits */ +#define BE_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 /* Especial (less get_bits case) Valid - 1bits */ +#define BE_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 /* Especial (less get_bits case) EoP - 1bits */ + +#endif /* _mipi_backend_common_defs_h_ */ +#endif /* _css_receiver_2400_common_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/css_receiver_2400_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/css_receiver_2400_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..6f5b7d3d3715e905f55265a2774be86cc5eb9f08 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/css_receiver_2400_defs.h @@ -0,0 +1,258 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _css_receiver_2400_defs_h_ +#define _css_receiver_2400_defs_h_ + +#include "css_receiver_2400_common_defs.h" + +#define CSS_RECEIVER_DATA_WIDTH 8 +#define CSS_RECEIVER_RX_TRIG 4 +#define CSS_RECEIVER_RF_WORD 32 +#define CSS_RECEIVER_IMG_PROC_RF_ADDR 10 +#define CSS_RECEIVER_CSI_RF_ADDR 4 +#define CSS_RECEIVER_DATA_OUT 12 +#define CSS_RECEIVER_CHN_NO 2 +#define CSS_RECEIVER_DWORD_CNT 11 +#define CSS_RECEIVER_FORMAT_TYP 5 +#define CSS_RECEIVER_HRESPONSE 2 +#define CSS_RECEIVER_STATE_WIDTH 3 +#define CSS_RECEIVER_FIFO_DAT 32 +#define CSS_RECEIVER_CNT_VAL 2 +#define CSS_RECEIVER_PRED10_VAL 10 +#define CSS_RECEIVER_PRED12_VAL 12 +#define CSS_RECEIVER_CNT_WIDTH 8 +#define CSS_RECEIVER_WORD_CNT 16 +#define CSS_RECEIVER_PIXEL_LEN 6 +#define CSS_RECEIVER_PIXEL_CNT 5 +#define CSS_RECEIVER_COMP_8_BIT 8 +#define CSS_RECEIVER_COMP_7_BIT 7 +#define CSS_RECEIVER_COMP_6_BIT 6 + +#define CSI_CONFIG_WIDTH 4 + +/* division of gen_short data, ch_id and fmt_type over streaming data interface */ +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB 0 +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB - 1) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB - 1) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH - 1) + +#define _HRT_CSS_RECEIVER_2400_REG_ALIGN 4 +#define _HRT_CSS_RECEIVER_2400_BYTES_PER_PKT 4 + +#define hrt_css_receiver_2400_4_lane_port_offset 0x100 +#define hrt_css_receiver_2400_1_lane_port_offset 0x200 +#define hrt_css_receiver_2400_2_lane_port_offset 0x300 +#define hrt_css_receiver_2400_backend_port_offset 0x100 + +#define _HRT_CSS_RECEIVER_2400_DEVICE_READY_REG_IDX 0 +#define _HRT_CSS_RECEIVER_2400_IRQ_STATUS_REG_IDX 1 +#define _HRT_CSS_RECEIVER_2400_IRQ_ENABLE_REG_IDX 2 +#define _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX 3 +#define _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX 4 +#define _HRT_CSS_RECEIVER_2400_FS_TO_LS_DELAY_REG_IDX 7 +#define _HRT_CSS_RECEIVER_2400_LS_TO_DATA_DELAY_REG_IDX 8 +#define _HRT_CSS_RECEIVER_2400_DATA_TO_LE_DELAY_REG_IDX 9 +#define _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX 10 +#define _HRT_CSS_RECEIVER_2400_FE_TO_FS_DELAY_REG_IDX 11 +#define _HRT_CSS_RECEIVER_2400_LE_TO_LS_DELAY_REG_IDX 12 +#define _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX 13 +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_REG_IDX 14 +#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX 15 +#define _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX 16 +#define _HRT_CSS_RECEIVER_2400_BACKEND_RST_REG_IDX 17 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX 18 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX 19 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX 20 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX 21 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX 22 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX 23 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX 24 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX 25 +#define _HRT_CSS_RECEIVER_2400_RAW18_REG_IDX 26 +#define _HRT_CSS_RECEIVER_2400_FORCE_RAW8_REG_IDX 27 +#define _HRT_CSS_RECEIVER_2400_RAW16_REG_IDX 28 + +/* Interrupt bits for IRQ_STATUS and IRQ_ENABLE registers */ +#define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_BIT 0 +#define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_BIT 1 +#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_BIT 2 +#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_BIT 3 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_BIT 4 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_BIT 5 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_BIT 6 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_BIT 7 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_BIT 8 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_BIT 9 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT 10 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_BIT 11 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_BIT 12 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_BIT 13 +#define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_BIT 14 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_BIT 15 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_BIT 16 + +#define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_CAUSE_ "Fifo Overrun" +#define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_CAUSE_ "Reserved" +#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_CAUSE_ "Sleep mode entry" +#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_CAUSE_ "Sleep mode exit" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_CAUSE_ "Error high speed SOT" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_CAUSE_ "Error high speed sync SOT" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_CAUSE_ "Error control" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_CAUSE_ "Error correction double bit" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_CAUSE_ "Error correction single bit" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_CAUSE_ "No error" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_CAUSE_ "Error cyclic redundancy check" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_CAUSE_ "Error id" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_CAUSE_ "Error frame sync" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_CAUSE_ "Error frame data" +#define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_CAUSE_ "Data time-out" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_CAUSE_ "Error escape" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_CAUSE_ "Error line sync" + +/* Bits for CSI2_DEVICE_READY register */ +#define _HRT_CSS_RECEIVER_2400_CSI2_DEVICE_READY_IDX 0 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_INIT_TIME_OUT_ERR_IDX 2 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_OVER_RUN_ERR_IDX 3 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_SOT_SYNC_ERR_IDX 4 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_RECEIVE_DATA_TIME_OUT_ERR_IDX 5 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_ECC_TWO_BIT_ERR_IDX 6 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_DATA_ID_ERR_IDX 7 + + +/* Bits for CSI2_FUNC_PROG register */ +#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS 19 + +/* Bits for INIT_COUNT register */ +#define _HRT_CSS_RECEIVER_2400_INIT_TIMER_IDX 0 +#define _HRT_CSS_RECEIVER_2400_INIT_TIMER_BITS 16 + +/* Bits for COUNT registers */ +#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_BITS 8 +#define _HRT_CSS_RECEIVER_2400_RX_COUNT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_RX_COUNT_BITS 8 + +/* Bits for RAW116_18_DATAID register */ +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_BITS 6 +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_IDX 8 +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_BITS 6 + +/* Bits for COMP_FORMAT register, this selects the compression data format */ +#define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS 8 +#define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_IDX (_HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX + _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS) +#define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_BITS 8 + +/* Bits for COMP_PREDICT register, this selects the predictor algorithm */ +#define _HRT_CSS_RECEIVER_2400_PREDICT_NO_COMP 0 +#define _HRT_CSS_RECEIVER_2400_PREDICT_1 1 +#define _HRT_CSS_RECEIVER_2400_PREDICT_2 2 + +/* Number of bits used for the delay registers */ +#define _HRT_CSS_RECEIVER_2400_DELAY_BITS 8 + +/* Bits for COMP_SCHEME register, this selects the compression scheme for a VC */ +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD1_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD2_BITS_IDX 5 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD3_BITS_IDX 10 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD4_BITS_IDX 15 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD5_BITS_IDX 20 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD6_BITS_IDX 25 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD7_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD8_BITS_IDX 5 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_BITS_BITS 5 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_BITS 3 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_IDX 3 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_BITS 2 + + +/* BITS for backend RAW16 and RAW 18 registers */ + +#define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_BITS 6 +#define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_IDX 6 +#define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_BITS 2 +#define _HRT_CSS_RECEIVER_2400_RAW18_EN_IDX 8 +#define _HRT_CSS_RECEIVER_2400_RAW18_EN_BITS 1 + +#define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_BITS 6 +#define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_IDX 6 +#define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_BITS 2 +#define _HRT_CSS_RECEIVER_2400_RAW16_EN_IDX 8 +#define _HRT_CSS_RECEIVER_2400_RAW16_EN_BITS 1 + +/* These hsync and vsync values are for HSS simulation only */ +#define _HRT_CSS_RECEIVER_2400_HSYNC_VAL (1<<16) +#define _HRT_CSS_RECEIVER_2400_VSYNC_VAL (1<<17) + +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_WIDTH 28 +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB 0 +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB + CSS_RECEIVER_DATA_OUT - 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB + 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT + 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB + CSS_RECEIVER_DATA_OUT - 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB + 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT + 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_EOP_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT + 1) + +// SH Backend Register IDs +#define _HRT_CSS_RECEIVER_2400_BE_GSP_ACC_OVL_REG_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_REG_IDX 1 +#define _HRT_CSS_RECEIVER_2400_BE_TWO_PPC_REG_IDX 2 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG0_IDX 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG1_IDX 4 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG2_IDX 5 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG3_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_SEL_REG_IDX 7 +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_CONFIG_REG_IDX 8 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_CONFIG_REG_IDX 9 +#define _HRT_CSS_RECEIVER_2400_BE_FORCE_RAW8_REG_IDX 10 +#define _HRT_CSS_RECEIVER_2400_BE_IRQ_STATUS_REG_IDX 11 +#define _HRT_CSS_RECEIVER_2400_BE_IRQ_CLEAR_REG_IDX 12 +#define _HRT_CSS_RECEIVER_2400_BE_CUST_EN_REG_IDX 13 +#define _HRT_CSS_RECEIVER_2400_BE_CUST_DATA_STATE_REG_IDX 14 /* Data State 0,1,2 config */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P0_REG_IDX 15 /* Pixel Extractor config for Data State 0 & Pix 0 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P1_REG_IDX 16 /* Pixel Extractor config for Data State 0 & Pix 1 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P2_REG_IDX 17 /* Pixel Extractor config for Data State 0 & Pix 2 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P3_REG_IDX 18 /* Pixel Extractor config for Data State 0 & Pix 3 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P0_REG_IDX 19 /* Pixel Extractor config for Data State 1 & Pix 0 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P1_REG_IDX 20 /* Pixel Extractor config for Data State 1 & Pix 1 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P2_REG_IDX 21 /* Pixel Extractor config for Data State 1 & Pix 2 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P3_REG_IDX 22 /* Pixel Extractor config for Data State 1 & Pix 3 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P0_REG_IDX 23 /* Pixel Extractor config for Data State 2 & Pix 0 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P1_REG_IDX 24 /* Pixel Extractor config for Data State 2 & Pix 1 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P2_REG_IDX 25 /* Pixel Extractor config for Data State 2 & Pix 2 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P3_REG_IDX 26 /* Pixel Extractor config for Data State 2 & Pix 3 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_VALID_EOP_REG_IDX 27 /* Pixel Valid & EoP config for Pix 0,1,2,3 */ + +#define _HRT_CSS_RECEIVER_2400_BE_NOF_REGISTERS 28 + +#define _HRT_CSS_RECEIVER_2400_BE_SRST_HE 0 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_RCF 1 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_PF 2 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_SM 3 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_PD 4 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_SD 5 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_OT 6 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_BC 7 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_WIDTH 8 + +#endif /* _css_receiver_2400_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/defs.h new file mode 100644 index 0000000000000000000000000000000000000000..47505f41790c17ef0aa42727d9553666bb3961ae --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/defs.h @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HRT_DEFS_H_ +#define _HRT_DEFS_H_ + +#ifndef HRTCAT +#define _HRTCAT(m, n) m##n +#define HRTCAT(m, n) _HRTCAT(m, n) +#endif + +#ifndef HRTSTR +#define _HRTSTR(x) #x +#define HRTSTR(x) _HRTSTR(x) +#endif + +#ifndef HRTMIN +#define HRTMIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef HRTMAX +#define HRTMAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +#endif /* _HRT_DEFS_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/dma_v2_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/dma_v2_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..d184a8b313c91c6978c70b10c42f32231cc65cb9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/dma_v2_defs.h @@ -0,0 +1,199 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _dma_v2_defs_h +#define _dma_v2_defs_h + +#define _DMA_V2_NUM_CHANNELS_ID MaxNumChannels +#define _DMA_V2_CONNECTIONS_ID Connections +#define _DMA_V2_DEV_ELEM_WIDTHS_ID DevElemWidths +#define _DMA_V2_DEV_FIFO_DEPTH_ID DevFifoDepth +#define _DMA_V2_DEV_FIFO_RD_LAT_ID DevFifoRdLat +#define _DMA_V2_DEV_FIFO_LAT_BYPASS_ID DevFifoRdLatBypass +#define _DMA_V2_DEV_NO_BURST_ID DevNoBurst +#define _DMA_V2_DEV_RD_ACCEPT_ID DevRdAccept +#define _DMA_V2_DEV_SRMD_ID DevSRMD +#define _DMA_V2_DEV_HAS_CRUN_ID CRunMasters +#define _DMA_V2_CTRL_ACK_FIFO_DEPTH_ID CtrlAckFifoDepth +#define _DMA_V2_CMD_FIFO_DEPTH_ID CommandFifoDepth +#define _DMA_V2_CMD_FIFO_RD_LAT_ID CommandFifoRdLat +#define _DMA_V2_CMD_FIFO_LAT_BYPASS_ID CommandFifoRdLatBypass +#define _DMA_V2_NO_PACK_ID has_no_pack + +#define _DMA_V2_REG_ALIGN 4 +#define _DMA_V2_REG_ADDR_BITS 2 + +/* Command word */ +#define _DMA_V2_CMD_IDX 0 +#define _DMA_V2_CMD_BITS 6 +#define _DMA_V2_CHANNEL_IDX (_DMA_V2_CMD_IDX + _DMA_V2_CMD_BITS) +#define _DMA_V2_CHANNEL_BITS 5 + +/* The command to set a parameter contains the PARAM field next */ +#define _DMA_V2_PARAM_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS) +#define _DMA_V2_PARAM_BITS 4 + +/* Commands to read, write or init specific blocks contain these + three values */ +#define _DMA_V2_SPEC_DEV_A_XB_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS) +#define _DMA_V2_SPEC_DEV_A_XB_BITS 8 +#define _DMA_V2_SPEC_DEV_B_XB_IDX (_DMA_V2_SPEC_DEV_A_XB_IDX + _DMA_V2_SPEC_DEV_A_XB_BITS) +#define _DMA_V2_SPEC_DEV_B_XB_BITS 8 +#define _DMA_V2_SPEC_YB_IDX (_DMA_V2_SPEC_DEV_B_XB_IDX + _DMA_V2_SPEC_DEV_B_XB_BITS) +#define _DMA_V2_SPEC_YB_BITS (32-_DMA_V2_SPEC_DEV_B_XB_BITS-_DMA_V2_SPEC_DEV_A_XB_BITS-_DMA_V2_CMD_BITS-_DMA_V2_CHANNEL_BITS) + +/* */ +#define _DMA_V2_CMD_CTRL_IDX 4 +#define _DMA_V2_CMD_CTRL_BITS 4 + +/* Packing setup word */ +#define _DMA_V2_CONNECTION_IDX 0 +#define _DMA_V2_CONNECTION_BITS 4 +#define _DMA_V2_EXTENSION_IDX (_DMA_V2_CONNECTION_IDX + _DMA_V2_CONNECTION_BITS) +#define _DMA_V2_EXTENSION_BITS 1 + +/* Elements packing word */ +#define _DMA_V2_ELEMENTS_IDX 0 +#define _DMA_V2_ELEMENTS_BITS 8 +#define _DMA_V2_LEFT_CROPPING_IDX (_DMA_V2_ELEMENTS_IDX + _DMA_V2_ELEMENTS_BITS) +#define _DMA_V2_LEFT_CROPPING_BITS 8 + +#define _DMA_V2_WIDTH_IDX 0 +#define _DMA_V2_WIDTH_BITS 16 + +#define _DMA_V2_HEIGHT_IDX 0 +#define _DMA_V2_HEIGHT_BITS 16 + +#define _DMA_V2_STRIDE_IDX 0 +#define _DMA_V2_STRIDE_BITS 32 + +/* Command IDs */ +#define _DMA_V2_MOVE_B2A_COMMAND 0 +#define _DMA_V2_MOVE_B2A_BLOCK_COMMAND 1 +#define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND 2 +#define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND 3 +#define _DMA_V2_MOVE_A2B_COMMAND 4 +#define _DMA_V2_MOVE_A2B_BLOCK_COMMAND 5 +#define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND 6 +#define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND 7 +#define _DMA_V2_INIT_A_COMMAND 8 +#define _DMA_V2_INIT_A_BLOCK_COMMAND 9 +#define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND 10 +#define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND 11 +#define _DMA_V2_INIT_B_COMMAND 12 +#define _DMA_V2_INIT_B_BLOCK_COMMAND 13 +#define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND 14 +#define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND 15 +#define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_CONFIG_CHANNEL_COMMAND 32 +#define _DMA_V2_SET_CHANNEL_PARAM_COMMAND 33 +#define _DMA_V2_SET_CRUN_COMMAND 62 + +/* Channel Parameter IDs */ +#define _DMA_V2_PACKING_SETUP_PARAM 0 +#define _DMA_V2_STRIDE_A_PARAM 1 +#define _DMA_V2_ELEM_CROPPING_A_PARAM 2 +#define _DMA_V2_WIDTH_A_PARAM 3 +#define _DMA_V2_STRIDE_B_PARAM 4 +#define _DMA_V2_ELEM_CROPPING_B_PARAM 5 +#define _DMA_V2_WIDTH_B_PARAM 6 +#define _DMA_V2_HEIGHT_PARAM 7 +#define _DMA_V2_QUEUED_CMDS 8 + +/* Parameter Constants */ +#define _DMA_V2_ZERO_EXTEND 0 +#define _DMA_V2_SIGN_EXTEND 1 + + /* SLAVE address map */ +#define _DMA_V2_SEL_FSM_CMD 0 +#define _DMA_V2_SEL_CH_REG 1 +#define _DMA_V2_SEL_CONN_GROUP 2 +#define _DMA_V2_SEL_DEV_INTERF 3 + +#define _DMA_V2_ADDR_SEL_COMP_IDX 12 +#define _DMA_V2_ADDR_SEL_COMP_BITS 4 +#define _DMA_V2_ADDR_SEL_CH_REG_IDX 2 +#define _DMA_V2_ADDR_SEL_CH_REG_BITS 6 +#define _DMA_V2_ADDR_SEL_PARAM_IDX (_DMA_V2_ADDR_SEL_CH_REG_BITS+_DMA_V2_ADDR_SEL_CH_REG_IDX) +#define _DMA_V2_ADDR_SEL_PARAM_BITS 4 + +#define _DMA_V2_ADDR_SEL_GROUP_COMP_IDX 2 +#define _DMA_V2_ADDR_SEL_GROUP_COMP_BITS 6 +#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_IDX (_DMA_V2_ADDR_SEL_GROUP_COMP_BITS + _DMA_V2_ADDR_SEL_GROUP_COMP_IDX) +#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_BITS 4 + +#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX 2 +#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS 6 +#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX+_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS) +#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS 4 + +#define _DMA_V2_FSM_GROUP_CMD_IDX 0 +#define _DMA_V2_FSM_GROUP_ADDR_SRC_IDX 1 +#define _DMA_V2_FSM_GROUP_ADDR_DEST_IDX 2 +#define _DMA_V2_FSM_GROUP_CMD_CTRL_IDX 3 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_IDX 4 +#define _DMA_V2_FSM_GROUP_FSM_PACK_IDX 5 +#define _DMA_V2_FSM_GROUP_FSM_REQ_IDX 6 +#define _DMA_V2_FSM_GROUP_FSM_WR_IDX 7 + +#define _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX 0 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX 1 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX 2 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX 3 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_XB_IDX 4 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_YB_IDX 5 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX 6 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX 7 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX 8 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX 9 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX 10 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX 11 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX 12 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX 13 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX 14 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX 15 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_CMD_CTRL_IDX 15 + +#define _DMA_V2_FSM_GROUP_FSM_PACK_STATE_IDX 0 +#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_YB_IDX 1 +#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX 2 +#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX 3 + +#define _DMA_V2_FSM_GROUP_FSM_REQ_STATE_IDX 0 +#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_YB_IDX 1 +#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_XB_IDX 2 +#define _DMA_V2_FSM_GROUP_FSM_REQ_XB_REMAINING_IDX 3 +#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_BURST_IDX 4 + +#define _DMA_V2_FSM_GROUP_FSM_WR_STATE_IDX 0 +#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_YB_IDX 1 +#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_XB_IDX 2 +#define _DMA_V2_FSM_GROUP_FSM_WR_XB_REMAINING_IDX 3 +#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_BURST_IDX 4 + +#define _DMA_V2_DEV_INTERF_REQ_SIDE_STATUS_IDX 0 +#define _DMA_V2_DEV_INTERF_SEND_SIDE_STATUS_IDX 1 +#define _DMA_V2_DEV_INTERF_FIFO_STATUS_IDX 2 +#define _DMA_V2_DEV_INTERF_REQ_ONLY_COMPLETE_BURST_IDX 3 +#define _DMA_V2_DEV_INTERF_MAX_BURST_IDX 4 +#define _DMA_V2_DEV_INTERF_CHK_ADDR_ALIGN 5 + +#endif /* _dma_v2_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gdc_v2_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gdc_v2_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..77722d20570108c94c8258640f679564ef0e40dc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gdc_v2_defs.h @@ -0,0 +1,170 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef HRT_GDC_v2_defs_h_ +#define HRT_GDC_v2_defs_h_ + +#define HRT_GDC_IS_V2 + +#define HRT_GDC_N 1024 /* Top-level design constant, equal to the number of entries in the LUT */ +#define HRT_GDC_FRAC_BITS 10 /* Number of fractional bits in the GDC block, driven by the size of the LUT */ + +#define HRT_GDC_BLI_FRAC_BITS 4 /* Number of fractional bits for the bi-linear interpolation type */ +#define HRT_GDC_BLI_COEF_ONE (1 << HRT_GDC_BLI_FRAC_BITS) + +#define HRT_GDC_BCI_COEF_BITS 14 /* 14 bits per coefficient */ +#define HRT_GDC_BCI_COEF_ONE (1 << (HRT_GDC_BCI_COEF_BITS-2)) /* We represent signed 10 bit coefficients. */ + /* The supported range is [-256, .., +256] */ + /* in 14-bit signed notation, */ + /* We need all ten bits (MSB must be zero). */ + /* -s is inserted to solve this issue, and */ + /* therefore "1" is equal to +256. */ +#define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1) + +#define HRT_GDC_LUT_BYTES (HRT_GDC_N*4*2) /* 1024 addresses, 4 coefficients per address, */ + /* 2 bytes per coefficient */ + +#define _HRT_GDC_REG_ALIGN 4 + + // 31 30 29 25 24 0 + // |-----|---|--------|------------------------| + // | CMD | C | Reg_ID | Value | + + + // There are just two commands possible for the GDC block: + // 1 - Configure reg + // 0 - Data token + + // C - Reserved bit + // Used in protocol to indicate whether it is C-run or other type of runs + // In case of C-run, this bit has a value of 1, for all the other runs, it is 0. + + // Reg_ID - Address of the register to be configured + + // Value - Value to store to the addressed register, maximum of 24 bits + + // Configure reg command is not followed by any other token. + // The address of the register and the data to be filled in is contained in the same token + + // When the first data token is received, it must be: + // 1. FRX and FRY (device configured in one of the scaling modes) ***DEFAULT MODE***, or, + // 2. P0'X (device configured in one of the tetragon modes) + // After the first data token is received, pre-defined number of tokens with the following meaning follow: + // 1. two tokens: SRC address ; DST address + // 2. nine tokens: P0'Y, .., P3'Y ; SRC address ; DST address + +#define HRT_GDC_CONFIG_CMD 1 +#define HRT_GDC_DATA_CMD 0 + + +#define HRT_GDC_CMD_POS 31 +#define HRT_GDC_CMD_BITS 1 +#define HRT_GDC_CRUN_POS 30 +#define HRT_GDC_REG_ID_POS 25 +#define HRT_GDC_REG_ID_BITS 5 +#define HRT_GDC_DATA_POS 0 +#define HRT_GDC_DATA_BITS 25 + +#define HRT_GDC_FRYIPXFRX_BITS 26 +#define HRT_GDC_P0X_BITS 23 + + +#define HRT_GDC_MAX_OXDIM (8192-64) +#define HRT_GDC_MAX_OYDIM 4095 +#define HRT_GDC_MAX_IXDIM (8192-64) +#define HRT_GDC_MAX_IYDIM 4095 +#define HRT_GDC_MAX_DS_FAC 16 +#define HRT_GDC_MAX_DX (HRT_GDC_MAX_DS_FAC*HRT_GDC_N - 1) +#define HRT_GDC_MAX_DY HRT_GDC_MAX_DX + + +/* GDC lookup tables entries are 10 bits values, but they're + stored 2 by 2 as 32 bit values, yielding 16 bits per entry. + A GDC lookup table contains 64 * 4 elements */ + +#define HRT_GDC_PERF_1_1_pix 0 +#define HRT_GDC_PERF_2_1_pix 1 +#define HRT_GDC_PERF_1_2_pix 2 +#define HRT_GDC_PERF_2_2_pix 3 + +#define HRT_GDC_NND_MODE 0 +#define HRT_GDC_BLI_MODE 1 +#define HRT_GDC_BCI_MODE 2 +#define HRT_GDC_LUT_MODE 3 + +#define HRT_GDC_SCAN_STB 0 +#define HRT_GDC_SCAN_STR 1 + +#define HRT_GDC_MODE_SCALING 0 +#define HRT_GDC_MODE_TETRAGON 1 + +#define HRT_GDC_LUT_COEFF_OFFSET 16 +#define HRT_GDC_FRY_BIT_OFFSET 16 +// FRYIPXFRX is the only register where we store two values in one field, +// to save one token in the scaling protocol. +// Like this, we have three tokens in the scaling protocol, +// Otherwise, we would have had four. +// The register bit-map is: +// 31 26 25 16 15 10 9 0 +// |------|----------|------|----------| +// | XXXX | FRY | IPX | FRX | + + +#define HRT_GDC_CE_FSM0_POS 0 +#define HRT_GDC_CE_FSM0_LEN 2 +#define HRT_GDC_CE_OPY_POS 2 +#define HRT_GDC_CE_OPY_LEN 14 +#define HRT_GDC_CE_OPX_POS 16 +#define HRT_GDC_CE_OPX_LEN 16 +// CHK_ENGINE register bit-map: +// 31 16 15 2 1 0 +// |----------------|-----------|----| +// | OPX | OPY |FSM0| +// However, for the time being at least, +// this implementation is meaningless in hss model, +// So, we just return 0 + + +#define HRT_GDC_CHK_ENGINE_IDX 0 +#define HRT_GDC_WOIX_IDX 1 +#define HRT_GDC_WOIY_IDX 2 +#define HRT_GDC_BPP_IDX 3 +#define HRT_GDC_FRYIPXFRX_IDX 4 +#define HRT_GDC_OXDIM_IDX 5 +#define HRT_GDC_OYDIM_IDX 6 +#define HRT_GDC_SRC_ADDR_IDX 7 +#define HRT_GDC_SRC_END_ADDR_IDX 8 +#define HRT_GDC_SRC_WRAP_ADDR_IDX 9 +#define HRT_GDC_SRC_STRIDE_IDX 10 +#define HRT_GDC_DST_ADDR_IDX 11 +#define HRT_GDC_DST_STRIDE_IDX 12 +#define HRT_GDC_DX_IDX 13 +#define HRT_GDC_DY_IDX 14 +#define HRT_GDC_P0X_IDX 15 +#define HRT_GDC_P0Y_IDX 16 +#define HRT_GDC_P1X_IDX 17 +#define HRT_GDC_P1Y_IDX 18 +#define HRT_GDC_P2X_IDX 19 +#define HRT_GDC_P2Y_IDX 20 +#define HRT_GDC_P3X_IDX 21 +#define HRT_GDC_P3Y_IDX 22 +#define HRT_GDC_PERF_POINT_IDX 23 // 1x1 ; 1x2 ; 2x1 ; 2x2 pixels per cc +#define HRT_GDC_INTERP_TYPE_IDX 24 // NND ; BLI ; BCI ; LUT +#define HRT_GDC_SCAN_IDX 25 // 0 = STB (Slide To Bottom) ; 1 = STR (Slide To Right) +#define HRT_GDC_PROC_MODE_IDX 26 // 0 = Scaling ; 1 = Tetragon + +#define HRT_GDC_LUT_IDX 32 + + +#endif /* HRT_GDC_v2_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gp_regs_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gp_regs_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..34e734f6648eb0ef6297cab46f912c933466310f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gp_regs_defs.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _gp_regs_defs_h +#define _gp_regs_defs_h + +#define _HRT_GP_REGS_IS_FWD_REG_IDX 0 + +#define _HRT_GP_REGS_REG_ALIGN 4 + +#endif /* _gp_regs_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gp_timer_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gp_timer_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..3082e2f5e014117ccd1548cceae21fd5eb2bd430 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gp_timer_defs.h @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _gp_timer_defs_h +#define _gp_timer_defs_h + +#define _HRT_GP_TIMER_REG_ALIGN 4 + +#define HIVE_GP_TIMER_RESET_REG_IDX 0 +#define HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX 1 +#define HIVE_GP_TIMER_ENABLE_REG_IDX(timer) (HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX + 1 + timer) +#define HIVE_GP_TIMER_VALUE_REG_IDX(timer,timers) (HIVE_GP_TIMER_ENABLE_REG_IDX(timers) + timer) +#define HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer,timers) (HIVE_GP_TIMER_VALUE_REG_IDX(timers, timers) + timer) +#define HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer,timers) (HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timers, timers) + timer) +#define HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq,timers) (HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timers, timers) + irq) +#define HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq,timers,irqs) (HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irqs, timers) + irq) +#define HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq,timers,irqs) (HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irqs, timers, irqs) + irq) + +#define HIVE_GP_TIMER_COUNT_TYPE_HIGH 0 +#define HIVE_GP_TIMER_COUNT_TYPE_LOW 1 +#define HIVE_GP_TIMER_COUNT_TYPE_POSEDGE 2 +#define HIVE_GP_TIMER_COUNT_TYPE_NEGEDGE 3 +#define HIVE_GP_TIMER_COUNT_TYPES 4 + +#endif /* _gp_timer_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gpio_block_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gpio_block_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..a807d4c990414af50c61c4e20075d385db25862f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/gpio_block_defs.h @@ -0,0 +1,42 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _gpio_block_defs_h_ +#define _gpio_block_defs_h_ + +#define _HRT_GPIO_BLOCK_REG_ALIGN 4 + +/* R/W registers */ +#define _gpio_block_reg_do_e 0 +#define _gpio_block_reg_do_select 1 +#define _gpio_block_reg_do_0 2 +#define _gpio_block_reg_do_1 3 +#define _gpio_block_reg_do_pwm_cnt_0 4 +#define _gpio_block_reg_do_pwm_cnt_1 5 +#define _gpio_block_reg_do_pwm_cnt_2 6 +#define _gpio_block_reg_do_pwm_cnt_3 7 +#define _gpio_block_reg_do_pwm_main_cnt 8 +#define _gpio_block_reg_do_pwm_enable 9 +#define _gpio_block_reg_di_debounce_sel 10 +#define _gpio_block_reg_di_debounce_cnt_0 11 +#define _gpio_block_reg_di_debounce_cnt_1 12 +#define _gpio_block_reg_di_debounce_cnt_2 13 +#define _gpio_block_reg_di_debounce_cnt_3 14 +#define _gpio_block_reg_di_active_level 15 + + +/* read-only registers */ +#define _gpio_block_reg_di 16 + +#endif /* _gpio_block_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_isp_css_2401_irq_types_hrt.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_isp_css_2401_irq_types_hrt.h new file mode 100644 index 0000000000000000000000000000000000000000..2f7cb2dff0e9be416ed5b578a780f928ae668e2d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_isp_css_2401_irq_types_hrt.h @@ -0,0 +1,68 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HIVE_ISP_CSS_2401_IRQ_TYPES_HRT_H_ +#define _HIVE_ISP_CSS_2401_IRQ_TYPES_HRT_H_ + +/* + * These are the indices of each interrupt in the interrupt + * controller's registers. these can be used as the irq_id + * argument to the hrt functions irq_controller.h. + * + * The definitions are taken from _defs.h + */ +typedef enum hrt_isp_css_irq { + hrt_isp_css_irq_gpio_pin_0 = HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID , + hrt_isp_css_irq_gpio_pin_1 = HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID , + hrt_isp_css_irq_gpio_pin_2 = HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID , + hrt_isp_css_irq_gpio_pin_3 = HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID , + hrt_isp_css_irq_gpio_pin_4 = HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID , + hrt_isp_css_irq_gpio_pin_5 = HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID , + hrt_isp_css_irq_gpio_pin_6 = HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID , + hrt_isp_css_irq_gpio_pin_7 = HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID , + hrt_isp_css_irq_gpio_pin_8 = HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID , + hrt_isp_css_irq_gpio_pin_9 = HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID , + hrt_isp_css_irq_gpio_pin_10 = HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID , + hrt_isp_css_irq_gpio_pin_11 = HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID , + hrt_isp_css_irq_sp = HIVE_GP_DEV_IRQ_SP_BIT_ID , + hrt_isp_css_irq_isp = HIVE_GP_DEV_IRQ_ISP_BIT_ID , + hrt_isp_css_irq_isys = HIVE_GP_DEV_IRQ_ISYS_BIT_ID , + hrt_isp_css_irq_isel = HIVE_GP_DEV_IRQ_ISEL_BIT_ID , + hrt_isp_css_irq_ifmt = HIVE_GP_DEV_IRQ_IFMT_BIT_ID , + hrt_isp_css_irq_sp_stream_mon = HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID , + hrt_isp_css_irq_isp_stream_mon = HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID , + hrt_isp_css_irq_mod_stream_mon = HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID , + hrt_isp_css_irq_is2401 = HIVE_GP_DEV_IRQ_IS2401_BIT_ID , + hrt_isp_css_irq_isp_bamem_error = HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID , + hrt_isp_css_irq_isp_dmem_error = HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID , + hrt_isp_css_irq_sp_icache_mem_error = HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID , + hrt_isp_css_irq_sp_dmem_error = HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID , + hrt_isp_css_irq_mmu_cache_mem_error = HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID , + hrt_isp_css_irq_gp_timer_0 = HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID , + hrt_isp_css_irq_gp_timer_1 = HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID , + hrt_isp_css_irq_sw_pin_0 = HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID , + hrt_isp_css_irq_sw_pin_1 = HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID , + hrt_isp_css_irq_dma = HIVE_GP_DEV_IRQ_DMA_BIT_ID , + hrt_isp_css_irq_sp_stream_mon_b = HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID , + /* this must (obviously) be the last on in the enum */ + hrt_isp_css_irq_num_irqs +} hrt_isp_css_irq_t; + +typedef enum hrt_isp_css_irq_status { + hrt_isp_css_irq_status_error, + hrt_isp_css_irq_status_more_irqs, + hrt_isp_css_irq_status_success +} hrt_isp_css_irq_status_t; + +#endif /* _HIVE_ISP_CSS_2401_IRQ_TYPES_HRT_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_isp_css_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_isp_css_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..5a2ce9108ae4968221b5690d3d641d579732e631 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_isp_css_defs.h @@ -0,0 +1,435 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _hive_isp_css_defs_h__ +#define _hive_isp_css_defs_h__ + +#define _HIVE_ISP_CSS_2401_SYSTEM 1 +#define HIVE_ISP_CTRL_DATA_WIDTH 32 +#define HIVE_ISP_CTRL_ADDRESS_WIDTH 32 +#define HIVE_ISP_CTRL_MAX_BURST_SIZE 1 +#define HIVE_ISP_DDR_ADDRESS_WIDTH 36 + +#define HIVE_ISP_HOST_MAX_BURST_SIZE 8 /* host supports bursts in order to prevent repeating DDRAM accesses */ +#define HIVE_ISP_NUM_GPIO_PINS 12 + +/* This list of vector num_elems/elem_bits pairs is valid both in C as initializer + and in the DMA parameter list */ +#define HIVE_ISP_DDR_DMA_SPECS {{32, 8}, {16, 16}, {18, 14}, {25, 10}, {21, 12}} +#define HIVE_ISP_DDR_WORD_BITS 256 +#define HIVE_ISP_DDR_WORD_BYTES (HIVE_ISP_DDR_WORD_BITS/8) +#define HIVE_ISP_DDR_BYTES (512 * 1024 * 1024) +#define HIVE_ISP_DDR_BYTES_RTL (127 * 1024 * 1024) +#define HIVE_ISP_DDR_SMALL_BYTES (128 * 256 / 8) +#define HIVE_ISP_PAGE_SHIFT 12 +#define HIVE_ISP_PAGE_SIZE (1< + +#define _HIVE_ISP_CH_ID_MASK ((1U << HIVE_ISP_CH_ID_BITS)-1) +#define _HIVE_ISP_FMT_TYPE_MASK ((1U << HIVE_ISP_FMT_TYPE_BITS)-1) + +#define _HIVE_STR_TO_MIPI_FMT_TYPE_LSB (HIVE_STR_TO_MIPI_CH_ID_LSB + HIVE_ISP_CH_ID_BITS) +#define _HIVE_STR_TO_MIPI_DATA_B_LSB (HIVE_STR_TO_MIPI_DATA_A_LSB + HIVE_IF_PIXEL_WIDTH) + +#endif /* _hive_isp_css_streaming_to_mipi_types_hrt_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_types.h new file mode 100644 index 0000000000000000000000000000000000000000..58b0e6effbd068fe9f2d175072bb1e66c921428a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/hive_types.h @@ -0,0 +1,128 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HRT_HIVE_TYPES_H +#define _HRT_HIVE_TYPES_H + +#include "version.h" +#include "defs.h" + +#ifndef HRTCAT3 +#define _HRTCAT3(m,n,o) m##n##o +#define HRTCAT3(m,n,o) _HRTCAT3(m,n,o) +#endif + +#ifndef HRTCAT4 +#define _HRTCAT4(m,n,o,p) m##n##o##p +#define HRTCAT4(m,n,o,p) _HRTCAT4(m,n,o,p) +#endif + +#ifndef HRTMIN +#define HRTMIN(a,b) (((a)<(b))?(a):(b)) +#endif + +#ifndef HRTMAX +#define HRTMAX(a,b) (((a)>(b))?(a):(b)) +#endif + +/* boolean data type */ +typedef unsigned int hive_bool; +#define hive_false 0 +#define hive_true 1 + +typedef char hive_int8; +typedef short hive_int16; +typedef int hive_int32; +typedef long long hive_int64; + +typedef unsigned char hive_uint8; +typedef unsigned short hive_uint16; +typedef unsigned int hive_uint32; +typedef unsigned long long hive_uint64; + +/* by default assume 32 bit master port (both data and address) */ +#ifndef HRT_DATA_WIDTH +#define HRT_DATA_WIDTH 32 +#endif +#ifndef HRT_ADDRESS_WIDTH +#define HRT_ADDRESS_WIDTH 32 +#endif + +#define HRT_DATA_BYTES (HRT_DATA_WIDTH/8) +#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH/8) + +#if HRT_DATA_WIDTH == 64 +typedef hive_uint64 hrt_data; +#elif HRT_DATA_WIDTH == 32 +typedef hive_uint32 hrt_data; +#else +#error data width not supported +#endif + +#if HRT_ADDRESS_WIDTH == 64 +typedef hive_uint64 hrt_address; +#elif HRT_ADDRESS_WIDTH == 32 +typedef hive_uint32 hrt_address; +#else +#error adddres width not supported +#endif + +/* The SP side representation of an HMM virtual address */ +typedef hive_uint32 hrt_vaddress; + +/* use 64 bit addresses in simulation, where possible */ +typedef hive_uint64 hive_sim_address; + +/* below is for csim, not for hrt, rename and move this elsewhere */ + +typedef unsigned int hive_uint; +typedef hive_uint32 hive_address; +typedef hive_address hive_slave_address; +typedef hive_address hive_mem_address; + +/* MMIO devices */ +typedef hive_uint hive_mmio_id; +typedef hive_mmio_id hive_slave_id; +typedef hive_mmio_id hive_port_id; +typedef hive_mmio_id hive_master_id; +typedef hive_mmio_id hive_mem_id; +typedef hive_mmio_id hive_dev_id; +typedef hive_mmio_id hive_fifo_id; + +typedef hive_uint hive_hier_id; +typedef hive_hier_id hive_device_id; +typedef hive_device_id hive_proc_id; +typedef hive_device_id hive_cell_id; +typedef hive_device_id hive_host_id; +typedef hive_device_id hive_bus_id; +typedef hive_device_id hive_bridge_id; +typedef hive_device_id hive_fifo_adapter_id; +typedef hive_device_id hive_custom_device_id; + +typedef hive_uint hive_slot_id; +typedef hive_uint hive_fu_id; +typedef hive_uint hive_reg_file_id; +typedef hive_uint hive_reg_id; + +/* Streaming devices */ +typedef hive_uint hive_outport_id; +typedef hive_uint hive_inport_id; + +typedef hive_uint hive_msink_id; + +/* HRT specific */ +typedef char* hive_program; +typedef char* hive_function; + +#endif /* _HRT_HIVE_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/ibuf_cntrl_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/ibuf_cntrl_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..f82bb79785cfc6bac7c96fee897b1fd526df09a1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/ibuf_cntrl_defs.h @@ -0,0 +1,138 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _ibuf_cntrl_defs_h_ +#define _ibuf_cntrl_defs_h_ + +#include +#include + +#define _IBUF_CNTRL_REG_ALIGN 4 + /* alignment of register banks, first bank are shared configuration and status registers: */ +#define _IBUF_CNTRL_PROC_REG_ALIGN 32 + + /* the actual amount of configuration registers per proc: */ +#define _IBUF_CNTRL_CONFIG_REGS_PER_PROC 18 + /* the actual amount of shared configuration registers: */ +#define _IBUF_CNTRL_CONFIG_REGS_NO_PROC 0 + + /* the actual amount of status registers per proc */ +#define _IBUF_CNTRL_STATUS_REGS_PER_PROC (_IBUF_CNTRL_CONFIG_REGS_PER_PROC + 10) + /* the actual amount shared status registers */ +#define _IBUF_CNTRL_STATUS_REGS_NO_PROC (_IBUF_CNTRL_CONFIG_REGS_NO_PROC + 2) + + /* time out bits, maximum time out value is 2^_IBUF_CNTRL_TIME_OUT_BITS - 1 */ +#define _IBUF_CNTRL_TIME_OUT_BITS 5 + +/* command token definition */ +#define _IBUF_CNTRL_CMD_TOKEN_LSB 0 +#define _IBUF_CNTRL_CMD_TOKEN_MSB 1 + +/* Str2MMIO defines */ +#define _IBUF_CNTRL_STREAM2MMIO_CMD_TOKEN_MSB _STREAM2MMIO_CMD_TOKEN_CMD_MSB +#define _IBUF_CNTRL_STREAM2MMIO_CMD_TOKEN_LSB _STREAM2MMIO_CMD_TOKEN_CMD_LSB +#define _IBUF_CNTRL_STREAM2MMIO_NUM_ITEMS_BITS _STREAM2MMIO_PACK_NUM_ITEMS_BITS +#define _IBUF_CNTRL_STREAM2MMIO_ACK_EOF_BIT _STREAM2MMIO_PACK_ACK_EOF_BIT +#define _IBUF_CNTRL_STREAM2MMIO_ACK_TOKEN_VALID_BIT _STREAM2MMIO_ACK_TOKEN_VALID_BIT + +/* acknowledge token definition */ +#define _IBUF_CNTRL_ACK_TOKEN_STORES_IDX 0 +#define _IBUF_CNTRL_ACK_TOKEN_STORES_BITS 15 +#define _IBUF_CNTRL_ACK_TOKEN_ITEMS_IDX (_IBUF_CNTRL_ACK_TOKEN_STORES_BITS + _IBUF_CNTRL_ACK_TOKEN_STORES_IDX) +#define _IBUF_CNTRL_ACK_TOKEN_ITEMS_BITS _STREAM2MMIO_PACK_NUM_ITEMS_BITS +#define _IBUF_CNTRL_ACK_TOKEN_LSB _IBUF_CNTRL_ACK_TOKEN_STORES_IDX +#define _IBUF_CNTRL_ACK_TOKEN_MSB (_IBUF_CNTRL_ACK_TOKEN_ITEMS_BITS + _IBUF_CNTRL_ACK_TOKEN_ITEMS_IDX - 1) + /* bit 31 indicates a valid ack: */ +#define _IBUF_CNTRL_ACK_TOKEN_VALID_BIT (_IBUF_CNTRL_ACK_TOKEN_ITEMS_BITS + _IBUF_CNTRL_ACK_TOKEN_ITEMS_IDX) + + +/*shared registers:*/ +#define _IBUF_CNTRL_RECALC_WORDS_STATUS 0 +#define _IBUF_CNTRL_ARBITERS_STATUS 1 + +#define _IBUF_CNTRL_SET_CRUN 2 /* NO PHYSICAL REGISTER!! Only used in HSS model */ + + +/*register addresses for each proc: */ +#define _IBUF_CNTRL_CMD 0 +#define _IBUF_CNTRL_ACK 1 + + /* number of items (packets or words) per frame: */ +#define _IBUF_CNTRL_NUM_ITEMS_PER_STORE 2 + + /* number of stores (packets or words) per store/buffer: */ +#define _IBUF_CNTRL_NUM_STORES_PER_FRAME 3 + + /* the channel and command in the DMA */ +#define _IBUF_CNTRL_DMA_CHANNEL 4 +#define _IBUF_CNTRL_DMA_CMD 5 + + /* the start address and stride of the buffers */ +#define _IBUF_CNTRL_BUFFER_START_ADDRESS 6 +#define _IBUF_CNTRL_BUFFER_STRIDE 7 +#define _IBUF_CNTRL_BUFFER_END_ADDRESS 8 + + /* destination start address, stride and end address; should be the same as in the DMA */ +#define _IBUF_CNTRL_DEST_START_ADDRESS 9 +#define _IBUF_CNTRL_DEST_STRIDE 10 +#define _IBUF_CNTRL_DEST_END_ADDRESS 11 + + /* send a frame sync or not, default 1 */ +#define _IBUF_CNTRL_SYNC_FRAME 12 + + /* str2mmio cmds */ +#define _IBUF_CNTRL_STR2MMIO_SYNC_CMD 13 +#define _IBUF_CNTRL_STR2MMIO_STORE_CMD 14 + + /* num elems p word*/ +#define _IBUF_CNTRL_SHIFT_ITEMS 15 +#define _IBUF_CNTRL_ELEMS_P_WORD_IBUF 16 +#define _IBUF_CNTRL_ELEMS_P_WORD_DEST 17 + + + /* STATUS */ + /* current frame and stores in buffer */ +#define _IBUF_CNTRL_CUR_STORES 18 +#define _IBUF_CNTRL_CUR_ACKS 19 + + /* current buffer and destination address for DMA cmd's */ +#define _IBUF_CNTRL_CUR_S2M_IBUF_ADDR 20 +#define _IBUF_CNTRL_CUR_DMA_IBUF_ADDR 21 +#define _IBUF_CNTRL_CUR_DMA_DEST_ADDR 22 +#define _IBUF_CNTRL_CUR_ISP_DEST_ADDR 23 + +#define _IBUF_CNTRL_CUR_NR_DMA_CMDS_SEND 24 + +#define _IBUF_CNTRL_MAIN_CNTRL_STATE 25 +#define _IBUF_CNTRL_DMA_SYNC_STATE 26 +#define _IBUF_CNTRL_ISP_SYNC_STATE 27 + + +/*Commands: */ +#define _IBUF_CNTRL_CMD_STORE_FRAME_IDX 0 +#define _IBUF_CNTRL_CMD_ONLINE_IDX 1 + + /* initialize, copy st_addr to cur_addr etc */ +#define _IBUF_CNTRL_CMD_INITIALIZE 0 + + /* store an online frame (sync with ISP, use end cfg start, stride and end address: */ +#define _IBUF_CNTRL_CMD_STORE_ONLINE_FRAME ((1<<_IBUF_CNTRL_CMD_STORE_FRAME_IDX) | (1<<_IBUF_CNTRL_CMD_ONLINE_IDX)) + + /* store an offline frame (don't sync with ISP, requires start address as 2nd token, no end address: */ +#define _IBUF_CNTRL_CMD_STORE_OFFLINE_FRAME (1<<_IBUF_CNTRL_CMD_STORE_FRAME_IDX) + + /* false command token, should be different then commands. Use online bit, not store frame: */ +#define _IBUF_CNTRL_FALSE_ACK 2 + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/if_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/if_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..7d39e45796ae17965aee2ef1fb61f0d76a03b88f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/if_defs.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IF_DEFS_H +#define _IF_DEFS_H + +#define HIVE_IF_FRAME_REQUEST 0xA000 +#define HIVE_IF_LINES_REQUEST 0xB000 +#define HIVE_IF_VECTORS_REQUEST 0xC000 + +#endif /* _IF_DEFS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_formatter_subsystem_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_formatter_subsystem_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..16bfe1d80bc96a1f0c25f7d818db5d1dfff5003b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_formatter_subsystem_defs.h @@ -0,0 +1,53 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _if_subsystem_defs_h +#define _if_subsystem_defs_h__ + +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0 0 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_1 1 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_2 2 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_3 3 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_4 4 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_5 5 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_6 6 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_7 7 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_FSYNC_LUT_REG 8 +#define HIVE_IFMT_GP_REGS_SRST_IDX 9 +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IDX 10 + +#define HIVE_IFMT_GP_REGS_CH_ID_FMT_TYPE_IDX 11 + +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_BASE HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0 + +/* order of the input bits for the ifmt irq controller */ +#define HIVE_IFMT_IRQ_IFT_PRIM_BIT_ID 0 +#define HIVE_IFMT_IRQ_IFT_PRIM_B_BIT_ID 1 +#define HIVE_IFMT_IRQ_IFT_SEC_BIT_ID 2 +#define HIVE_IFMT_IRQ_MEM_CPY_BIT_ID 3 +#define HIVE_IFMT_IRQ_SIDEBAND_CHANGED_BIT_ID 4 + +/* order of the input bits for the ifmt Soft reset register */ +#define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_BIT_IDX 0 +#define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_B_BIT_IDX 1 +#define HIVE_IFMT_GP_REGS_SRST_IFT_SEC_BIT_IDX 2 +#define HIVE_IFMT_GP_REGS_SRST_MEM_CPY_BIT_IDX 3 + +/* order of the input bits for the ifmt Soft reset register */ +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_BIT_IDX 0 +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_B_BIT_IDX 1 +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_SEC_BIT_IDX 2 +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_MEM_CPY_BIT_IDX 3 + +#endif /* _if_subsystem_defs_h__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_selector_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_selector_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..87fbf82edb5bc44d6c5ca761c06aa57a8606fc97 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_selector_defs.h @@ -0,0 +1,89 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _input_selector_defs_h +#define _input_selector_defs_h + +#ifndef HIVE_ISP_ISEL_SEL_BITS +#define HIVE_ISP_ISEL_SEL_BITS 2 +#endif + +#ifndef HIVE_ISP_CH_ID_BITS +#define HIVE_ISP_CH_ID_BITS 2 +#endif + +#ifndef HIVE_ISP_FMT_TYPE_BITS +#define HIVE_ISP_FMT_TYPE_BITS 5 +#endif + +/* gp_register register id's -- Outputs */ +#define HIVE_ISEL_GP_REGS_SYNCGEN_ENABLE_IDX 0 +#define HIVE_ISEL_GP_REGS_SYNCGEN_FREE_RUNNING_IDX 1 +#define HIVE_ISEL_GP_REGS_SYNCGEN_PAUSE_IDX 2 +#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_FRAMES_IDX 3 +#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_PIX_IDX 4 +#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_LINES_IDX 5 +#define HIVE_ISEL_GP_REGS_SYNCGEN_HBLANK_CYCLES_IDX 6 +#define HIVE_ISEL_GP_REGS_SYNCGEN_VBLANK_CYCLES_IDX 7 + +#define HIVE_ISEL_GP_REGS_SOF_IDX 8 +#define HIVE_ISEL_GP_REGS_EOF_IDX 9 +#define HIVE_ISEL_GP_REGS_SOL_IDX 10 +#define HIVE_ISEL_GP_REGS_EOL_IDX 11 + +#define HIVE_ISEL_GP_REGS_PRBS_ENABLE 12 +#define HIVE_ISEL_GP_REGS_PRBS_ENABLE_PORT_B 13 +#define HIVE_ISEL_GP_REGS_PRBS_LFSR_RESET_VALUE 14 + +#define HIVE_ISEL_GP_REGS_TPG_ENABLE 15 +#define HIVE_ISEL_GP_REGS_TPG_ENABLE_PORT_B 16 +#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_MASK_IDX 17 +#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_MASK_IDX 18 +#define HIVE_ISEL_GP_REGS_TPG_XY_CNT_MASK_IDX 19 +#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_DELTA_IDX 20 +#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_DELTA_IDX 21 +#define HIVE_ISEL_GP_REGS_TPG_MODE_IDX 22 +#define HIVE_ISEL_GP_REGS_TPG_R1_IDX 23 +#define HIVE_ISEL_GP_REGS_TPG_G1_IDX 24 +#define HIVE_ISEL_GP_REGS_TPG_B1_IDX 25 +#define HIVE_ISEL_GP_REGS_TPG_R2_IDX 26 +#define HIVE_ISEL_GP_REGS_TPG_G2_IDX 27 +#define HIVE_ISEL_GP_REGS_TPG_B2_IDX 28 + + +#define HIVE_ISEL_GP_REGS_CH_ID_IDX 29 +#define HIVE_ISEL_GP_REGS_FMT_TYPE_IDX 30 +#define HIVE_ISEL_GP_REGS_DATA_SEL_IDX 31 +#define HIVE_ISEL_GP_REGS_SBAND_SEL_IDX 32 +#define HIVE_ISEL_GP_REGS_SYNC_SEL_IDX 33 +#define HIVE_ISEL_GP_REGS_SRST_IDX 37 + +#define HIVE_ISEL_GP_REGS_SRST_SYNCGEN_BIT 0 +#define HIVE_ISEL_GP_REGS_SRST_PRBS_BIT 1 +#define HIVE_ISEL_GP_REGS_SRST_TPG_BIT 2 +#define HIVE_ISEL_GP_REGS_SRST_FIFO_BIT 3 + +/* gp_register register id's -- Inputs */ +#define HIVE_ISEL_GP_REGS_SYNCGEN_HOR_CNT_IDX 34 +#define HIVE_ISEL_GP_REGS_SYNCGEN_VER_CNT_IDX 35 +#define HIVE_ISEL_GP_REGS_SYNCGEN_FRAMES_CNT_IDX 36 + +/* irq sources isel irq controller */ +#define HIVE_ISEL_IRQ_SYNC_GEN_SOF_BIT_ID 0 +#define HIVE_ISEL_IRQ_SYNC_GEN_EOF_BIT_ID 1 +#define HIVE_ISEL_IRQ_SYNC_GEN_SOL_BIT_ID 2 +#define HIVE_ISEL_IRQ_SYNC_GEN_EOL_BIT_ID 3 +#define HIVE_ISEL_IRQ_NUM_IRQS 4 + +#endif /* _input_selector_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_switch_2400_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_switch_2400_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..20a13c4cdb562fc8773992317d0b9b4a06a149cb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_switch_2400_defs.h @@ -0,0 +1,30 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _input_switch_2400_defs_h +#define _input_switch_2400_defs_h + +#define _HIVE_INPUT_SWITCH_GET_LUT_REG_ID(ch_id, fmt_type) (((ch_id)*2) + ((fmt_type)>=16)) +#define _HIVE_INPUT_SWITCH_GET_LUT_REG_LSB(fmt_type) (((fmt_type)%16) * 2) + +#define HIVE_INPUT_SWITCH_SELECT_NO_OUTPUT 0 +#define HIVE_INPUT_SWITCH_SELECT_IF_PRIM 1 +#define HIVE_INPUT_SWITCH_SELECT_IF_SEC 2 +#define HIVE_INPUT_SWITCH_SELECT_STR_TO_MEM 3 +#define HIVE_INPUT_SWITCH_VSELECT_NO_OUTPUT 0 +#define HIVE_INPUT_SWITCH_VSELECT_IF_PRIM 1 +#define HIVE_INPUT_SWITCH_VSELECT_IF_SEC 2 +#define HIVE_INPUT_SWITCH_VSELECT_STR_TO_MEM 4 + +#endif /* _input_switch_2400_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_system_ctrl_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_system_ctrl_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..a7f0ca80bc9be0afed16a0726fdd068946aef12a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_system_ctrl_defs.h @@ -0,0 +1,254 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _input_system_ctrl_defs_h +#define _input_system_ctrl_defs_h + +#define _INPUT_SYSTEM_CTRL_REG_ALIGN 4 /* assuming 32 bit control bus width */ + +/* --------------------------------------------------*/ + +/* --------------------------------------------------*/ +/* REGISTER INFO */ +/* --------------------------------------------------*/ + +// Number of registers +#define ISYS_CTRL_NOF_REGS 23 + +// Register id's of MMIO slave accesible registers +#define ISYS_CTRL_CAPT_START_ADDR_A_REG_ID 0 +#define ISYS_CTRL_CAPT_START_ADDR_B_REG_ID 1 +#define ISYS_CTRL_CAPT_START_ADDR_C_REG_ID 2 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID 3 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID 4 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID 5 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID 6 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID 7 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID 8 +#define ISYS_CTRL_ACQ_START_ADDR_REG_ID 9 +#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID 10 +#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID 11 +#define ISYS_CTRL_INIT_REG_ID 12 +#define ISYS_CTRL_LAST_COMMAND_REG_ID 13 +#define ISYS_CTRL_NEXT_COMMAND_REG_ID 14 +#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_ID 15 +#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_ID 16 +#define ISYS_CTRL_FSM_STATE_INFO_REG_ID 17 +#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_ID 18 +#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_ID 19 +#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID 20 +#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID 21 +#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID 22 + + +/* register reset value */ +#define ISYS_CTRL_CAPT_START_ADDR_A_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_START_ADDR_B_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_START_ADDR_C_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_RSTVAL 128 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_RSTVAL 128 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_RSTVAL 128 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL 3 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL 3 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL 3 +#define ISYS_CTRL_ACQ_START_ADDR_REG_RSTVAL 0 +#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL 128 +#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3 +#define ISYS_CTRL_INIT_REG_RSTVAL 0 +#define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) +#define ISYS_CTRL_NEXT_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) +#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) +#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) +#define ISYS_CTRL_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_RSTVAL 0 + +/* register width value */ +#define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH 9 +#define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH 9 +#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH 9 +#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH 9 +#define ISYS_CTRL_INIT_REG_WIDTH 3 +#define ISYS_CTRL_LAST_COMMAND_REG_WIDTH 32 /* slave data width */ +#define ISYS_CTRL_NEXT_COMMAND_REG_WIDTH 32 +#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_WIDTH 32 +#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_WIDTH 32 +#define ISYS_CTRL_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_WIDTH 1 + +/* bit definitions */ + +/* --------------------------------------------------*/ +/* TOKEN INFO */ +/* --------------------------------------------------*/ + +/* +InpSysCaptFramesAcq 1/0 [3:0] - 'b0000 +[7:4] - CaptPortId, + CaptA-'b0000 + CaptB-'b0001 + CaptC-'b0010 +[31:16] - NOF_frames +InpSysCaptFrameExt 2/0 [3:0] - 'b0001' +[7:4] - CaptPortId, + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + + 2/1 [31:0] - external capture address +InpSysAcqFrame 2/0 [3:0] - 'b0010, +[31:4] - NOF_ext_mem_words + 2/1 [31:0] - external memory read start address +InpSysOverruleON 1/0 [3:0] - 'b0011, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + +InpSysOverruleOFF 1/0 [3:0] - 'b0100, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + +InpSysOverruleCmd 2/0 [3:0] - 'b0101, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + + 2/1 [31:0] - command token value for port opid + + +acknowledge tokens: + +InpSysAckCFA 1/0 [3:0] - 'b0000 + [7:4] - CaptPortId, + CaptA-'b0000 + CaptB- 'b0001 + CaptC-'b0010 + [31:16] - NOF_frames +InpSysAckCFE 1/0 [3:0] - 'b0001' +[7:4] - CaptPortId, + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + +InpSysAckAF 1/0 [3:0] - 'b0010 +InpSysAckOverruleON 1/0 [3:0] - 'b0011, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + +InpSysAckOverruleOFF 1/0 [3:0] - 'b0100, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + +InpSysAckOverrule 2/0 [3:0] - 'b0101, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + + 2/1 [31:0] - acknowledge token value from port opid + + + +*/ + + +/* Command and acknowledge tokens IDs */ +#define ISYS_CTRL_CAPT_FRAMES_ACQ_TOKEN_ID 0 /* 0000b */ +#define ISYS_CTRL_CAPT_FRAME_EXT_TOKEN_ID 1 /* 0001b */ +#define ISYS_CTRL_ACQ_FRAME_TOKEN_ID 2 /* 0010b */ +#define ISYS_CTRL_OVERRULE_ON_TOKEN_ID 3 /* 0011b */ +#define ISYS_CTRL_OVERRULE_OFF_TOKEN_ID 4 /* 0100b */ +#define ISYS_CTRL_OVERRULE_TOKEN_ID 5 /* 0101b */ + +#define ISYS_CTRL_ACK_CFA_TOKEN_ID 0 +#define ISYS_CTRL_ACK_CFE_TOKEN_ID 1 +#define ISYS_CTRL_ACK_AF_TOKEN_ID 2 +#define ISYS_CTRL_ACK_OVERRULE_ON_TOKEN_ID 3 +#define ISYS_CTRL_ACK_OVERRULE_OFF_TOKEN_ID 4 +#define ISYS_CTRL_ACK_OVERRULE_TOKEN_ID 5 +#define ISYS_CTRL_ACK_DEVICE_ERROR_TOKEN_ID 6 + +#define ISYS_CTRL_TOKEN_ID_MSB 3 +#define ISYS_CTRL_TOKEN_ID_LSB 0 +#define ISYS_CTRL_PORT_ID_TOKEN_MSB 7 +#define ISYS_CTRL_PORT_ID_TOKEN_LSB 4 +#define ISYS_CTRL_NOF_CAPT_TOKEN_MSB 31 +#define ISYS_CTRL_NOF_CAPT_TOKEN_LSB 16 +#define ISYS_CTRL_NOF_EXT_TOKEN_MSB 31 +#define ISYS_CTRL_NOF_EXT_TOKEN_LSB 8 + +#define ISYS_CTRL_TOKEN_ID_IDX 0 +#define ISYS_CTRL_TOKEN_ID_BITS (ISYS_CTRL_TOKEN_ID_MSB - ISYS_CTRL_TOKEN_ID_LSB + 1) +#define ISYS_CTRL_PORT_ID_IDX (ISYS_CTRL_TOKEN_ID_IDX + ISYS_CTRL_TOKEN_ID_BITS) +#define ISYS_CTRL_PORT_ID_BITS (ISYS_CTRL_PORT_ID_TOKEN_MSB - ISYS_CTRL_PORT_ID_TOKEN_LSB +1) +#define ISYS_CTRL_NOF_CAPT_IDX ISYS_CTRL_NOF_CAPT_TOKEN_LSB +#define ISYS_CTRL_NOF_CAPT_BITS (ISYS_CTRL_NOF_CAPT_TOKEN_MSB - ISYS_CTRL_NOF_CAPT_TOKEN_LSB + 1) +#define ISYS_CTRL_NOF_EXT_IDX ISYS_CTRL_NOF_EXT_TOKEN_LSB +#define ISYS_CTRL_NOF_EXT_BITS (ISYS_CTRL_NOF_EXT_TOKEN_MSB - ISYS_CTRL_NOF_EXT_TOKEN_LSB + 1) + +#define ISYS_CTRL_PORT_ID_CAPT_A 0 /* device ID for capture unit A */ +#define ISYS_CTRL_PORT_ID_CAPT_B 1 /* device ID for capture unit B */ +#define ISYS_CTRL_PORT_ID_CAPT_C 2 /* device ID for capture unit C */ +#define ISYS_CTRL_PORT_ID_ACQUISITION 3 /* device ID for acquistion unit */ +#define ISYS_CTRL_PORT_ID_DMA_CAPT_A 4 /* device ID for dma unit */ +#define ISYS_CTRL_PORT_ID_DMA_CAPT_B 5 /* device ID for dma unit */ +#define ISYS_CTRL_PORT_ID_DMA_CAPT_C 6 /* device ID for dma unit */ +#define ISYS_CTRL_PORT_ID_DMA_ACQ 7 /* device ID for dma unit */ + +#define ISYS_CTRL_NO_ACQ_ACK 16 /* no ack from acquisition unit */ +#define ISYS_CTRL_NO_DMA_ACK 0 +#define ISYS_CTRL_NO_CAPT_ACK 16 + +#endif /* _input_system_ctrl_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_system_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_system_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..ae62163034a66d6bae8fb55feadcb2de8cbfbddd --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/input_system_defs.h @@ -0,0 +1,126 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _input_system_defs_h +#define _input_system_defs_h + +/* csi controller modes */ +#define HIVE_CSI_CONFIG_MAIN 0 +#define HIVE_CSI_CONFIG_STEREO1 4 +#define HIVE_CSI_CONFIG_STEREO2 8 + +/* general purpose register IDs */ + +/* Stream Multicast select modes */ +#define HIVE_ISYS_GPREG_MULTICAST_A_IDX 0 +#define HIVE_ISYS_GPREG_MULTICAST_B_IDX 1 +#define HIVE_ISYS_GPREG_MULTICAST_C_IDX 2 + +/* Stream Mux select modes */ +#define HIVE_ISYS_GPREG_MUX_IDX 3 + +/* streaming monitor status and control */ +#define HIVE_ISYS_GPREG_STRMON_STAT_IDX 4 +#define HIVE_ISYS_GPREG_STRMON_COND_IDX 5 +#define HIVE_ISYS_GPREG_STRMON_IRQ_EN_IDX 6 +#define HIVE_ISYS_GPREG_SRST_IDX 7 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_IDX 8 +#define HIVE_ISYS_GPREG_REG_PORT_A_IDX 9 +#define HIVE_ISYS_GPREG_REG_PORT_B_IDX 10 + +/* Bit numbers of the soft reset register */ +#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_A_BIT 0 +#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_B_BIT 1 +#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_C_BIT 2 +#define HIVE_ISYS_GPREG_SRST_MULTICAST_A_BIT 3 +#define HIVE_ISYS_GPREG_SRST_MULTICAST_B_BIT 4 +#define HIVE_ISYS_GPREG_SRST_MULTICAST_C_BIT 5 +#define HIVE_ISYS_GPREG_SRST_CAPT_A_BIT 6 +#define HIVE_ISYS_GPREG_SRST_CAPT_B_BIT 7 +#define HIVE_ISYS_GPREG_SRST_CAPT_C_BIT 8 +#define HIVE_ISYS_GPREG_SRST_ACQ_BIT 9 +/* For ISYS_CTRL 5bits are defined to allow soft-reset per sub-controller and top-ctrl */ +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_BIT 10 /*LSB for 5bit vector */ +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_A_BIT 10 +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_B_BIT 11 +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_C_BIT 12 +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_ACQ_BIT 13 +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_TOP_BIT 14 +/* -- */ +#define HIVE_ISYS_GPREG_SRST_STR_MUX_BIT 15 +#define HIVE_ISYS_GPREG_SRST_CIO2AHB_BIT 16 +#define HIVE_ISYS_GPREG_SRST_GEN_SHORT_FIFO_BIT 17 +#define HIVE_ISYS_GPREG_SRST_WIDE_BUS_BIT 18 // includes CIO conv +#define HIVE_ISYS_GPREG_SRST_DMA_BIT 19 +#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_A_BIT 20 +#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_B_BIT 21 +#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_C_BIT 22 +#define HIVE_ISYS_GPREG_SRST_SF_CTRL_ACQ_BIT 23 +#define HIVE_ISYS_GPREG_SRST_CSI_BE_OUT_BIT 24 + +#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_A_BIT 0 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_B_BIT 1 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_C_BIT 2 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_ACQ_BIT 3 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_DMA_BIT 4 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_ISYS_CTRL_BIT 5 + +/* streaming monitor port id's */ +#define HIVE_ISYS_STR_MON_PORT_CAPA 0 +#define HIVE_ISYS_STR_MON_PORT_CAPB 1 +#define HIVE_ISYS_STR_MON_PORT_CAPC 2 +#define HIVE_ISYS_STR_MON_PORT_ACQ 3 +#define HIVE_ISYS_STR_MON_PORT_CSS_GENSH 4 +#define HIVE_ISYS_STR_MON_PORT_SF_GENSH 5 +#define HIVE_ISYS_STR_MON_PORT_SP2ISYS 6 +#define HIVE_ISYS_STR_MON_PORT_ISYS2SP 7 +#define HIVE_ISYS_STR_MON_PORT_PIXA 8 +#define HIVE_ISYS_STR_MON_PORT_PIXB 9 + +/* interrupt bit ID's */ +#define HIVE_ISYS_IRQ_CSI_SOF_BIT_ID 0 +#define HIVE_ISYS_IRQ_CSI_EOF_BIT_ID 1 +#define HIVE_ISYS_IRQ_CSI_SOL_BIT_ID 2 +#define HIVE_ISYS_IRQ_CSI_EOL_BIT_ID 3 +#define HIVE_ISYS_IRQ_CSI_RECEIVER_BIT_ID 4 +#define HIVE_ISYS_IRQ_CSI_RECEIVER_BE_BIT_ID 5 +#define HIVE_ISYS_IRQ_CAP_UNIT_A_NO_SOP 6 +#define HIVE_ISYS_IRQ_CAP_UNIT_A_LATE_SOP 7 +/*#define HIVE_ISYS_IRQ_CAP_UNIT_A_UNDEF_PH 7*/ +#define HIVE_ISYS_IRQ_CAP_UNIT_B_NO_SOP 8 +#define HIVE_ISYS_IRQ_CAP_UNIT_B_LATE_SOP 9 +/*#define HIVE_ISYS_IRQ_CAP_UNIT_B_UNDEF_PH 10*/ +#define HIVE_ISYS_IRQ_CAP_UNIT_C_NO_SOP 10 +#define HIVE_ISYS_IRQ_CAP_UNIT_C_LATE_SOP 11 +/*#define HIVE_ISYS_IRQ_CAP_UNIT_C_UNDEF_PH 13*/ +#define HIVE_ISYS_IRQ_ACQ_UNIT_SOP_MISMATCH 12 +/*#define HIVE_ISYS_IRQ_ACQ_UNIT_UNDEF_PH 15*/ +#define HIVE_ISYS_IRQ_INP_CTRL_CAPA 13 +#define HIVE_ISYS_IRQ_INP_CTRL_CAPB 14 +#define HIVE_ISYS_IRQ_INP_CTRL_CAPC 15 +#define HIVE_ISYS_IRQ_CIO2AHB 16 +#define HIVE_ISYS_IRQ_DMA_BIT_ID 17 +#define HIVE_ISYS_IRQ_STREAM_MON_BIT_ID 18 +#define HIVE_ISYS_IRQ_NUM_BITS 19 + +/* DMA */ +#define HIVE_ISYS_DMA_CHANNEL 0 +#define HIVE_ISYS_DMA_IBUF_DDR_CONN 0 +#define HIVE_ISYS_DMA_HEIGHT 1 +#define HIVE_ISYS_DMA_ELEMS 1 /* both master buses of same width */ +#define HIVE_ISYS_DMA_STRIDE 0 /* no stride required as height is fixed to 1 */ +#define HIVE_ISYS_DMA_CROP 0 /* no cropping */ +#define HIVE_ISYS_DMA_EXTENSION 0 /* no extension as elem width is same on both side */ + +#endif /* _input_system_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/irq_controller_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/irq_controller_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..ec6dd4487158e4fabf4e587684e4290ffdd23ed2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/irq_controller_defs.h @@ -0,0 +1,28 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _irq_controller_defs_h +#define _irq_controller_defs_h + +#define _HRT_IRQ_CONTROLLER_EDGE_REG_IDX 0 +#define _HRT_IRQ_CONTROLLER_MASK_REG_IDX 1 +#define _HRT_IRQ_CONTROLLER_STATUS_REG_IDX 2 +#define _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX 3 +#define _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX 4 +#define _HRT_IRQ_CONTROLLER_EDGE_NOT_PULSE_REG_IDX 5 +#define _HRT_IRQ_CONTROLLER_STR_OUT_ENABLE_REG_IDX 6 + +#define _HRT_IRQ_CONTROLLER_REG_ALIGN 4 + +#endif /* _irq_controller_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp2400_support.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp2400_support.h new file mode 100644 index 0000000000000000000000000000000000000000..e00bc841d0f0d2c00e942467981630e5051d040a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp2400_support.h @@ -0,0 +1,38 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _isp2400_support_h +#define _isp2400_support_h + +#ifndef ISP2400_VECTOR_TYPES +/* This typedef is to be able to include hive header files + in the host code which is useful in crun */ +typedef char *tmemvectors, *tmemvectoru, *tvector; +#endif + +#define hrt_isp_vamem1_store_16(cell, addr, val) hrt_mem_store_16(cell, HRT_PROC_TYPE_PROP(cell, _simd_vamem1), addr, val) +#define hrt_isp_vamem2_store_16(cell, addr, val) hrt_mem_store_16(cell, HRT_PROC_TYPE_PROP(cell, _simd_vamem2), addr, val) + +#define hrt_isp_dmem(cell) HRT_PROC_TYPE_PROP(cell, _base_dmem) +#define hrt_isp_vmem(cell) HRT_PROC_TYPE_PROP(cell, _simd_vmem) + +#define hrt_isp_dmem_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_dmem(cell)) +#define hrt_isp_vmem_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_vmem(cell)) + +#if ISP_HAS_HIST + #define hrt_isp_hist(cell) HRT_PROC_TYPE_PROP(cell, _simd_histogram) + #define hrt_isp_hist_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_hist(cell)) +#endif + +#endif /* _isp2400_support_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp2401_mamoiada_params.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp2401_mamoiada_params.h new file mode 100644 index 0000000000000000000000000000000000000000..033e23bcf672ae5ddfabeec7b2978d7b9f1f05b8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp2401_mamoiada_params.h @@ -0,0 +1,258 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* Version */ +#define RTL_VERSION + +/* Cell name */ +#define ISP_CELL_TYPE isp2401_mamoiada +#define ISP_VMEM simd_vmem +#define _HRT_ISP_VMEM isp2401_mamoiada_simd_vmem + +/* instruction pipeline depth */ +#define ISP_BRANCHDELAY 5 + +/* bus */ +#define ISP_BUS_WIDTH 32 +#define ISP_BUS_ADDR_WIDTH 32 +#define ISP_BUS_BURST_SIZE 1 + +/* data-path */ +#define ISP_SCALAR_WIDTH 32 +#define ISP_SLICE_NELEMS 4 +#define ISP_VEC_NELEMS 64 +#define ISP_VEC_ELEMBITS 14 +#define ISP_VEC_ELEM8BITS 16 +#define ISP_CLONE_DATAPATH_IS_16 1 + +/* memories */ +#define ISP_DMEM_DEPTH 4096 +#define ISP_DMEM_BSEL_DOWNSAMPLE 8 +#define ISP_VMEM_DEPTH 3072 +#define ISP_VMEM_BSEL_DOWNSAMPLE 8 +#define ISP_VMEM_ELEMBITS 14 +#define ISP_VMEM_ELEM_PRECISION 14 +#define ISP_VMEM_IS_BAMEM 1 +#if ISP_VMEM_IS_BAMEM + #define ISP_VMEM_BAMEM_MAX_BOI_HEIGHT 8 + #define ISP_VMEM_BAMEM_LATENCY 5 + #define ISP_VMEM_BAMEM_BANK_NARROWING_FACTOR 2 + #define ISP_VMEM_BAMEM_NR_DATA_PLANES 8 + #define ISP_VMEM_BAMEM_NR_CFG_REGISTERS 16 + #define ISP_VMEM_BAMEM_LININT 0 + #define ISP_VMEM_BAMEM_DAP_BITS 3 + #define ISP_VMEM_BAMEM_LININT_FRAC_BITS 0 + #define ISP_VMEM_BAMEM_PID_BITS 3 + #define ISP_VMEM_BAMEM_OFFSET_BITS 19 + #define ISP_VMEM_BAMEM_ADDRESS_BITS 25 + #define ISP_VMEM_BAMEM_RID_BITS 4 + #define ISP_VMEM_BAMEM_TRANSPOSITION 1 + #define ISP_VMEM_BAMEM_VEC_PLUS_SLICE 1 + #define ISP_VMEM_BAMEM_ARB_SERVICE_CYCLE_BITS 1 + #define ISP_VMEM_BAMEM_LUT_ELEMS 16 + #define ISP_VMEM_BAMEM_LUT_ADDR_WIDTH 14 + #define ISP_VMEM_BAMEM_HALF_BLOCK_WRITE 1 + #define ISP_VMEM_BAMEM_SMART_FETCH 1 + #define ISP_VMEM_BAMEM_BIG_ENDIANNESS 0 +#endif /* ISP_VMEM_IS_BAMEM */ +#define ISP_PMEM_DEPTH 2048 +#define ISP_PMEM_WIDTH 640 +#define ISP_VAMEM_ADDRESS_BITS 12 +#define ISP_VAMEM_ELEMBITS 12 +#define ISP_VAMEM_DEPTH 2048 +#define ISP_VAMEM_ALIGNMENT 2 +#define ISP_VA_ADDRESS_WIDTH 896 +#define ISP_VEC_VALSU_LATENCY ISP_VEC_NELEMS +#define ISP_HIST_ADDRESS_BITS 12 +#define ISP_HIST_ALIGNMENT 4 +#define ISP_HIST_COMP_IN_PREC 12 +#define ISP_HIST_DEPTH 1024 +#define ISP_HIST_WIDTH 24 +#define ISP_HIST_COMPONENTS 4 + +/* program counter */ +#define ISP_PC_WIDTH 13 + +/* Template switches */ +#define ISP_SHIELD_INPUT_DMEM 0 +#define ISP_SHIELD_OUTPUT_DMEM 1 +#define ISP_SHIELD_INPUT_VMEM 0 +#define ISP_SHIELD_OUTPUT_VMEM 0 +#define ISP_SHIELD_INPUT_PMEM 1 +#define ISP_SHIELD_OUTPUT_PMEM 1 +#define ISP_SHIELD_INPUT_HIST 1 +#define ISP_SHIELD_OUTPUT_HIST 1 +/* When LUT is select the shielding is always on */ +#define ISP_SHIELD_INPUT_VAMEM 1 +#define ISP_SHIELD_OUTPUT_VAMEM 1 + +#define ISP_HAS_IRQ 1 +#define ISP_HAS_SOFT_RESET 1 +#define ISP_HAS_VEC_DIV 0 +#define ISP_HAS_VFU_W_2O 1 +#define ISP_HAS_DEINT3 1 +#define ISP_HAS_LUT 1 +#define ISP_HAS_HIST 1 +#define ISP_HAS_VALSU 1 +#define ISP_HAS_3rdVALSU 1 +#define ISP_VRF1_HAS_2P 1 + +#define ISP_SRU_GUARDING 1 +#define ISP_VLSU_GUARDING 1 + +#define ISP_VRF_RAM 1 +#define ISP_SRF_RAM 1 + +#define ISP_SPLIT_VMUL_VADD_IS 0 +#define ISP_RFSPLIT_FPGA 0 + +/* RSN or Bus pipelining */ +#define ISP_RSN_PIPE 1 +#define ISP_VSF_BUS_PIPE 0 + +/* extra slave port to vmem */ +#define ISP_IF_VMEM 0 +#define ISP_GDC_VMEM 0 + +/* Streaming ports */ +#define ISP_IF 1 +#define ISP_IF_B 1 +#define ISP_GDC 1 +#define ISP_SCL 1 +#define ISP_GPFIFO 1 +#define ISP_SP 1 + +/* Removing Issue Slot(s) */ +#define ISP_HAS_NOT_SIMD_IS2 0 +#define ISP_HAS_NOT_SIMD_IS3 0 +#define ISP_HAS_NOT_SIMD_IS4 0 +#define ISP_HAS_NOT_SIMD_IS4_VADD 0 +#define ISP_HAS_NOT_SIMD_IS5 0 +#define ISP_HAS_NOT_SIMD_IS6 0 +#define ISP_HAS_NOT_SIMD_IS7 0 +#define ISP_HAS_NOT_SIMD_IS8 0 + +/* ICache */ +#define ISP_ICACHE 1 +#define ISP_ICACHE_ONLY 0 +#define ISP_ICACHE_PREFETCH 1 +#define ISP_ICACHE_INDEX_BITS 8 +#define ISP_ICACHE_SET_BITS 5 +#define ISP_ICACHE_BLOCKS_PER_SET_BITS 1 + +/* Experimental Flags */ +#define ISP_EXP_1 0 +#define ISP_EXP_2 0 +#define ISP_EXP_3 0 +#define ISP_EXP_4 0 +#define ISP_EXP_5 0 +#define ISP_EXP_6 0 + +/* Derived values */ +#define ISP_LOG2_PMEM_WIDTH 10 +#define ISP_VEC_WIDTH 896 +#define ISP_SLICE_WIDTH 56 +#define ISP_VMEM_WIDTH 896 +#define ISP_VMEM_ALIGN 128 +#if ISP_VMEM_IS_BAMEM + #define ISP_VMEM_ALIGN_ELEM 2 +#endif /* ISP_VMEM_IS_BAMEM */ +#define ISP_SIMDLSU 1 +#define ISP_LSU_IMM_BITS 12 + +/* convenient shortcuts for software*/ +#define ISP_NWAY ISP_VEC_NELEMS +#define NBITS ISP_VEC_ELEMBITS + +#define _isp_ceil_div(a,b) (((a)+(b)-1)/(b)) + +#ifdef C_RUN +#define ISP_VEC_ALIGN (_isp_ceil_div(ISP_VEC_WIDTH, 64)*8) +#else +#define ISP_VEC_ALIGN ISP_VMEM_ALIGN +#endif + +/* HRT specific vector support */ +#define isp2401_mamoiada_vector_alignment ISP_VEC_ALIGN +#define isp2401_mamoiada_vector_elem_bits ISP_VMEM_ELEMBITS +#define isp2401_mamoiada_vector_elem_precision ISP_VMEM_ELEM_PRECISION +#define isp2401_mamoiada_vector_num_elems ISP_VEC_NELEMS + +/* register file sizes */ +#define ISP_RF0_SIZE 64 +#define ISP_RF1_SIZE 16 +#define ISP_RF2_SIZE 64 +#define ISP_RF3_SIZE 4 +#define ISP_RF4_SIZE 64 +#define ISP_RF5_SIZE 16 +#define ISP_RF6_SIZE 16 +#define ISP_RF7_SIZE 16 +#define ISP_RF8_SIZE 16 +#define ISP_RF9_SIZE 16 +#define ISP_RF10_SIZE 16 +#define ISP_RF11_SIZE 16 +#define ISP_VRF1_SIZE 32 +#define ISP_VRF2_SIZE 32 +#define ISP_VRF3_SIZE 32 +#define ISP_VRF4_SIZE 32 +#define ISP_VRF5_SIZE 32 +#define ISP_VRF6_SIZE 32 +#define ISP_VRF7_SIZE 32 +#define ISP_VRF8_SIZE 32 +#define ISP_SRF1_SIZE 4 +#define ISP_SRF2_SIZE 64 +#define ISP_SRF3_SIZE 64 +#define ISP_SRF4_SIZE 32 +#define ISP_SRF5_SIZE 64 +#define ISP_FRF0_SIZE 16 +#define ISP_FRF1_SIZE 4 +#define ISP_FRF2_SIZE 16 +#define ISP_FRF3_SIZE 4 +#define ISP_FRF4_SIZE 4 +#define ISP_FRF5_SIZE 8 +#define ISP_FRF6_SIZE 4 +/* register file read latency */ +#define ISP_VRF1_READ_LAT 1 +#define ISP_VRF2_READ_LAT 1 +#define ISP_VRF3_READ_LAT 1 +#define ISP_VRF4_READ_LAT 1 +#define ISP_VRF5_READ_LAT 1 +#define ISP_VRF6_READ_LAT 1 +#define ISP_VRF7_READ_LAT 1 +#define ISP_VRF8_READ_LAT 1 +#define ISP_SRF1_READ_LAT 1 +#define ISP_SRF2_READ_LAT 1 +#define ISP_SRF3_READ_LAT 1 +#define ISP_SRF4_READ_LAT 1 +#define ISP_SRF5_READ_LAT 1 +#define ISP_SRF5_READ_LAT 1 +/* immediate sizes */ +#define ISP_IS1_IMM_BITS 14 +#define ISP_IS2_IMM_BITS 13 +#define ISP_IS3_IMM_BITS 14 +#define ISP_IS4_IMM_BITS 14 +#define ISP_IS5_IMM_BITS 9 +#define ISP_IS6_IMM_BITS 16 +#define ISP_IS7_IMM_BITS 9 +#define ISP_IS8_IMM_BITS 16 +#define ISP_IS9_IMM_BITS 11 +/* fifo depths */ +#define ISP_IF_FIFO_DEPTH 0 +#define ISP_IF_B_FIFO_DEPTH 0 +#define ISP_DMA_FIFO_DEPTH 0 +#define ISP_OF_FIFO_DEPTH 0 +#define ISP_GDC_FIFO_DEPTH 0 +#define ISP_SCL_FIFO_DEPTH 0 +#define ISP_GPFIFO_FIFO_DEPTH 0 +#define ISP_SP_FIFO_DEPTH 0 diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp_acquisition_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp_acquisition_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..59362072162710fbc0d5a5a47c11c48dd38b6861 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp_acquisition_defs.h @@ -0,0 +1,234 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _isp_acquisition_defs_h +#define _isp_acquisition_defs_h + +#define _ISP_ACQUISITION_REG_ALIGN 4 /* assuming 32 bit control bus width */ +#define _ISP_ACQUISITION_BYTES_PER_ELEM 4 + +/* --------------------------------------------------*/ + +#define NOF_ACQ_IRQS 1 + +/* --------------------------------------------------*/ +/* FSM */ +/* --------------------------------------------------*/ +#define MEM2STREAM_FSM_STATE_BITS 2 +#define ACQ_SYNCHRONIZER_FSM_STATE_BITS 2 + +/* --------------------------------------------------*/ +/* REGISTER INFO */ +/* --------------------------------------------------*/ + +#define NOF_ACQ_REGS 12 + +// Register id's of MMIO slave accesible registers +#define ACQ_START_ADDR_REG_ID 0 +#define ACQ_MEM_REGION_SIZE_REG_ID 1 +#define ACQ_NUM_MEM_REGIONS_REG_ID 2 +#define ACQ_INIT_REG_ID 3 +#define ACQ_RECEIVED_SHORT_PACKETS_REG_ID 4 +#define ACQ_RECEIVED_LONG_PACKETS_REG_ID 5 +#define ACQ_LAST_COMMAND_REG_ID 6 +#define ACQ_NEXT_COMMAND_REG_ID 7 +#define ACQ_LAST_ACKNOWLEDGE_REG_ID 8 +#define ACQ_NEXT_ACKNOWLEDGE_REG_ID 9 +#define ACQ_FSM_STATE_INFO_REG_ID 10 +#define ACQ_INT_CNTR_INFO_REG_ID 11 + +// Register width +#define ACQ_START_ADDR_REG_WIDTH 9 +#define ACQ_MEM_REGION_SIZE_REG_WIDTH 9 +#define ACQ_NUM_MEM_REGIONS_REG_WIDTH 9 +#define ACQ_INIT_REG_WIDTH 3 +#define ACQ_RECEIVED_SHORT_PACKETS_REG_WIDTH 32 +#define ACQ_RECEIVED_LONG_PACKETS_REG_WIDTH 32 +#define ACQ_LAST_COMMAND_REG_WIDTH 32 +#define ACQ_NEXT_COMMAND_REG_WIDTH 32 +#define ACQ_LAST_ACKNOWLEDGE_REG_WIDTH 32 +#define ACQ_NEXT_ACKNOWLEDGE_REG_WIDTH 32 +#define ACQ_FSM_STATE_INFO_REG_WIDTH ((MEM2STREAM_FSM_STATE_BITS * 3) + (ACQ_SYNCHRONIZER_FSM_STATE_BITS *3)) +#define ACQ_INT_CNTR_INFO_REG_WIDTH 32 + +/* register reset value */ +#define ACQ_START_ADDR_REG_RSTVAL 0 +#define ACQ_MEM_REGION_SIZE_REG_RSTVAL 128 +#define ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3 +#define ACQ_INIT_REG_RSTVAL 0 +#define ACQ_RECEIVED_SHORT_PACKETS_REG_RSTVAL 0 +#define ACQ_RECEIVED_LONG_PACKETS_REG_RSTVAL 0 +#define ACQ_LAST_COMMAND_REG_RSTVAL 0 +#define ACQ_NEXT_COMMAND_REG_RSTVAL 0 +#define ACQ_LAST_ACKNOWLEDGE_REG_RSTVAL 0 +#define ACQ_NEXT_ACKNOWLEDGE_REG_RSTVAL 0 +#define ACQ_FSM_STATE_INFO_REG_RSTVAL 0 +#define ACQ_INT_CNTR_INFO_REG_RSTVAL 0 + +/* bit definitions */ +#define ACQ_INIT_RST_REG_BIT 0 +#define ACQ_INIT_RESYNC_BIT 2 +#define ACQ_INIT_RST_IDX ACQ_INIT_RST_REG_BIT +#define ACQ_INIT_RST_BITS 1 +#define ACQ_INIT_RESYNC_IDX ACQ_INIT_RESYNC_BIT +#define ACQ_INIT_RESYNC_BITS 1 + +/* --------------------------------------------------*/ +/* TOKEN INFO */ +/* --------------------------------------------------*/ +#define ACQ_TOKEN_ID_LSB 0 +#define ACQ_TOKEN_ID_MSB 3 +#define ACQ_TOKEN_WIDTH (ACQ_TOKEN_ID_MSB - ACQ_TOKEN_ID_LSB + 1) // 4 +#define ACQ_TOKEN_ID_IDX 0 +#define ACQ_TOKEN_ID_BITS ACQ_TOKEN_WIDTH +#define ACQ_INIT_CMD_INIT_IDX 4 +#define ACQ_INIT_CMD_INIT_BITS 3 +#define ACQ_CMD_START_ADDR_IDX 4 +#define ACQ_CMD_START_ADDR_BITS 9 +#define ACQ_CMD_NOFWORDS_IDX 13 +#define ACQ_CMD_NOFWORDS_BITS 9 +#define ACQ_MEM_REGION_ID_IDX 22 +#define ACQ_MEM_REGION_ID_BITS 9 +#define ACQ_PACKET_LENGTH_TOKEN_MSB 21 +#define ACQ_PACKET_LENGTH_TOKEN_LSB 13 +#define ACQ_PACKET_DATA_FORMAT_ID_TOKEN_MSB 9 +#define ACQ_PACKET_DATA_FORMAT_ID_TOKEN_LSB 4 +#define ACQ_PACKET_CH_ID_TOKEN_MSB 11 +#define ACQ_PACKET_CH_ID_TOKEN_LSB 10 +#define ACQ_PACKET_MEM_REGION_ID_TOKEN_MSB 12 /* only for capt_end_of_packet_written */ +#define ACQ_PACKET_MEM_REGION_ID_TOKEN_LSB 4 /* only for capt_end_of_packet_written */ + + +/* Command tokens IDs */ +#define ACQ_READ_REGION_AUTO_INCR_TOKEN_ID 0 //0000b +#define ACQ_READ_REGION_TOKEN_ID 1 //0001b +#define ACQ_READ_REGION_SOP_TOKEN_ID 2 //0010b +#define ACQ_INIT_TOKEN_ID 8 //1000b + +/* Acknowledge token IDs */ +#define ACQ_READ_REGION_ACK_TOKEN_ID 0 //0000b +#define ACQ_END_OF_PACKET_TOKEN_ID 4 //0100b +#define ACQ_END_OF_REGION_TOKEN_ID 5 //0101b +#define ACQ_SOP_MISMATCH_TOKEN_ID 6 //0110b +#define ACQ_UNDEF_PH_TOKEN_ID 7 //0111b + +#define ACQ_TOKEN_MEMREGIONID_MSB 30 +#define ACQ_TOKEN_MEMREGIONID_LSB 22 +#define ACQ_TOKEN_NOFWORDS_MSB 21 +#define ACQ_TOKEN_NOFWORDS_LSB 13 +#define ACQ_TOKEN_STARTADDR_MSB 12 +#define ACQ_TOKEN_STARTADDR_LSB 4 + + +/* --------------------------------------------------*/ +/* MIPI */ +/* --------------------------------------------------*/ + +#define WORD_COUNT_WIDTH 16 +#define PKT_CODE_WIDTH 6 +#define CHN_NO_WIDTH 2 +#define ERROR_INFO_WIDTH 8 + +#define LONG_PKTCODE_MAX 63 +#define LONG_PKTCODE_MIN 16 +#define SHORT_PKTCODE_MAX 15 + +#define EOF_CODE 1 + +/* --------------------------------------------------*/ +/* Packet Info */ +/* --------------------------------------------------*/ +#define ACQ_START_OF_FRAME 0 +#define ACQ_END_OF_FRAME 1 +#define ACQ_START_OF_LINE 2 +#define ACQ_END_OF_LINE 3 +#define ACQ_LINE_PAYLOAD 4 +#define ACQ_GEN_SH_PKT 5 + + +/* bit definition */ +#define ACQ_PKT_TYPE_IDX 16 +#define ACQ_PKT_TYPE_BITS 6 +#define ACQ_PKT_SOP_IDX 32 +#define ACQ_WORD_CNT_IDX 0 +#define ACQ_WORD_CNT_BITS 16 +#define ACQ_PKT_INFO_IDX 16 +#define ACQ_PKT_INFO_BITS 8 +#define ACQ_HEADER_DATA_IDX 0 +#define ACQ_HEADER_DATA_BITS 16 +#define ACQ_ACK_TOKEN_ID_IDX ACQ_TOKEN_ID_IDX +#define ACQ_ACK_TOKEN_ID_BITS ACQ_TOKEN_ID_BITS +#define ACQ_ACK_NOFWORDS_IDX 13 +#define ACQ_ACK_NOFWORDS_BITS 9 +#define ACQ_ACK_PKT_LEN_IDX 4 +#define ACQ_ACK_PKT_LEN_BITS 16 + + +/* --------------------------------------------------*/ +/* Packet Data Type */ +/* --------------------------------------------------*/ + + +#define ACQ_YUV420_8_DATA 24 /* 01 1000 YUV420 8-bit */ +#define ACQ_YUV420_10_DATA 25 /* 01 1001 YUV420 10-bit */ +#define ACQ_YUV420_8L_DATA 26 /* 01 1010 YUV420 8-bit legacy */ +#define ACQ_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */ +#define ACQ_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */ +#define ACQ_RGB444_DATA 32 /* 10 0000 RGB444 */ +#define ACQ_RGB555_DATA 33 /* 10 0001 RGB555 */ +#define ACQ_RGB565_DATA 34 /* 10 0010 RGB565 */ +#define ACQ_RGB666_DATA 35 /* 10 0011 RGB666 */ +#define ACQ_RGB888_DATA 36 /* 10 0100 RGB888 */ +#define ACQ_RAW6_DATA 40 /* 10 1000 RAW6 */ +#define ACQ_RAW7_DATA 41 /* 10 1001 RAW7 */ +#define ACQ_RAW8_DATA 42 /* 10 1010 RAW8 */ +#define ACQ_RAW10_DATA 43 /* 10 1011 RAW10 */ +#define ACQ_RAW12_DATA 44 /* 10 1100 RAW12 */ +#define ACQ_RAW14_DATA 45 /* 10 1101 RAW14 */ +#define ACQ_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */ +#define ACQ_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */ +#define ACQ_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */ +#define ACQ_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */ +#define ACQ_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */ +#define ACQ_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */ +#define ACQ_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */ +#define ACQ_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */ +#define ACQ_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */ +#define ACQ_SOF_DATA 0 /* 00 0000 frame start */ +#define ACQ_EOF_DATA 1 /* 00 0001 frame end */ +#define ACQ_SOL_DATA 2 /* 00 0010 line start */ +#define ACQ_EOL_DATA 3 /* 00 0011 line end */ +#define ACQ_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */ +#define ACQ_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */ +#define ACQ_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */ +#define ACQ_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */ +#define ACQ_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */ +#define ACQ_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */ +#define ACQ_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */ +#define ACQ_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */ +#define ACQ_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */ +#define ACQ_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */ +#define ACQ_RESERVED_DATA_TYPE_MIN 56 +#define ACQ_RESERVED_DATA_TYPE_MAX 63 +#define ACQ_GEN_LONG_RESERVED_DATA_TYPE_MIN 19 +#define ACQ_GEN_LONG_RESERVED_DATA_TYPE_MAX 23 +#define ACQ_YUV_RESERVED_DATA_TYPE 27 +#define ACQ_RGB_RESERVED_DATA_TYPE_MIN 37 +#define ACQ_RGB_RESERVED_DATA_TYPE_MAX 39 +#define ACQ_RAW_RESERVED_DATA_TYPE_MIN 46 +#define ACQ_RAW_RESERVED_DATA_TYPE_MAX 47 + +/* --------------------------------------------------*/ + +#endif /* _isp_acquisition_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp_capture_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp_capture_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..aa413df022f2ed197fbec302d14b465b7deea48b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/isp_capture_defs.h @@ -0,0 +1,310 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _isp_capture_defs_h +#define _isp_capture_defs_h + +#define _ISP_CAPTURE_REG_ALIGN 4 /* assuming 32 bit control bus width */ +#define _ISP_CAPTURE_BITS_PER_ELEM 32 /* only for data, not SOP */ +#define _ISP_CAPTURE_BYTES_PER_ELEM (_ISP_CAPTURE_BITS_PER_ELEM/8 ) +#define _ISP_CAPTURE_BYTES_PER_WORD 32 /* 256/8 */ +#define _ISP_CAPTURE_ELEM_PER_WORD _ISP_CAPTURE_BYTES_PER_WORD / _ISP_CAPTURE_BYTES_PER_ELEM + +//#define CAPT_RCV_ACK 1 +//#define CAPT_WRT_ACK 2 +//#define CAPT_IRQ_ACK 3 + +/* --------------------------------------------------*/ + +#define NOF_IRQS 2 + +/* --------------------------------------------------*/ +/* REGISTER INFO */ +/* --------------------------------------------------*/ + +// Number of registers +#define CAPT_NOF_REGS 16 + +// Register id's of MMIO slave accesible registers +#define CAPT_START_MODE_REG_ID 0 +#define CAPT_START_ADDR_REG_ID 1 +#define CAPT_MEM_REGION_SIZE_REG_ID 2 +#define CAPT_NUM_MEM_REGIONS_REG_ID 3 +#define CAPT_INIT_REG_ID 4 +#define CAPT_START_REG_ID 5 +#define CAPT_STOP_REG_ID 6 + +#define CAPT_PACKET_LENGTH_REG_ID 7 +#define CAPT_RECEIVED_LENGTH_REG_ID 8 +#define CAPT_RECEIVED_SHORT_PACKETS_REG_ID 9 +#define CAPT_RECEIVED_LONG_PACKETS_REG_ID 10 +#define CAPT_LAST_COMMAND_REG_ID 11 +#define CAPT_NEXT_COMMAND_REG_ID 12 +#define CAPT_LAST_ACKNOWLEDGE_REG_ID 13 +#define CAPT_NEXT_ACKNOWLEDGE_REG_ID 14 +#define CAPT_FSM_STATE_INFO_REG_ID 15 + +// Register width +#define CAPT_START_MODE_REG_WIDTH 1 +//#define CAPT_START_ADDR_REG_WIDTH 9 +//#define CAPT_MEM_REGION_SIZE_REG_WIDTH 9 +//#define CAPT_NUM_MEM_REGIONS_REG_WIDTH 9 +#define CAPT_INIT_REG_WIDTH (22 + 4) + +#define CAPT_START_REG_WIDTH 1 +#define CAPT_STOP_REG_WIDTH 1 + +/* --------------------------------------------------*/ +/* FSM */ +/* --------------------------------------------------*/ +#define CAPT_WRITE2MEM_FSM_STATE_BITS 2 +#define CAPT_SYNCHRONIZER_FSM_STATE_BITS 3 + + +#define CAPT_PACKET_LENGTH_REG_WIDTH 17 +#define CAPT_RECEIVED_LENGTH_REG_WIDTH 17 +#define CAPT_RECEIVED_SHORT_PACKETS_REG_WIDTH 32 +#define CAPT_RECEIVED_LONG_PACKETS_REG_WIDTH 32 +#define CAPT_LAST_COMMAND_REG_WIDTH 32 +/* #define CAPT_NEXT_COMMAND_REG_WIDTH 32 */ +#define CAPT_LAST_ACKNOWLEDGE_REG_WIDTH 32 +#define CAPT_NEXT_ACKNOWLEDGE_REG_WIDTH 32 +#define CAPT_FSM_STATE_INFO_REG_WIDTH ((CAPT_WRITE2MEM_FSM_STATE_BITS * 3) + (CAPT_SYNCHRONIZER_FSM_STATE_BITS * 3)) + +//#define CAPT_INIT_RESTART_MEM_ADDR_WIDTH 9 +//#define CAPT_INIT_RESTART_MEM_REGION_WIDTH 9 + +/* register reset value */ +#define CAPT_START_MODE_REG_RSTVAL 0 +#define CAPT_START_ADDR_REG_RSTVAL 0 +#define CAPT_MEM_REGION_SIZE_REG_RSTVAL 128 +#define CAPT_NUM_MEM_REGIONS_REG_RSTVAL 3 +#define CAPT_INIT_REG_RSTVAL 0 + +#define CAPT_START_REG_RSTVAL 0 +#define CAPT_STOP_REG_RSTVAL 0 + +#define CAPT_PACKET_LENGTH_REG_RSTVAL 0 +#define CAPT_RECEIVED_LENGTH_REG_RSTVAL 0 +#define CAPT_RECEIVED_SHORT_PACKETS_REG_RSTVAL 0 +#define CAPT_RECEIVED_LONG_PACKETS_REG_RSTVAL 0 +#define CAPT_LAST_COMMAND_REG_RSTVAL 0 +#define CAPT_NEXT_COMMAND_REG_RSTVAL 0 +#define CAPT_LAST_ACKNOWLEDGE_REG_RSTVAL 0 +#define CAPT_NEXT_ACKNOWLEDGE_REG_RSTVAL 0 +#define CAPT_FSM_STATE_INFO_REG_RSTVAL 0 + +/* bit definitions */ +#define CAPT_INIT_RST_REG_BIT 0 +#define CAPT_INIT_FLUSH_BIT 1 +#define CAPT_INIT_RESYNC_BIT 2 +#define CAPT_INIT_RESTART_BIT 3 +#define CAPT_INIT_RESTART_MEM_ADDR_LSB 4 +#define CAPT_INIT_RESTART_MEM_ADDR_MSB 14 +#define CAPT_INIT_RESTART_MEM_REGION_LSB 15 +#define CAPT_INIT_RESTART_MEM_REGION_MSB 25 + + +#define CAPT_INIT_RST_REG_IDX CAPT_INIT_RST_REG_BIT +#define CAPT_INIT_RST_REG_BITS 1 +#define CAPT_INIT_FLUSH_IDX CAPT_INIT_FLUSH_BIT +#define CAPT_INIT_FLUSH_BITS 1 +#define CAPT_INIT_RESYNC_IDX CAPT_INIT_RESYNC_BIT +#define CAPT_INIT_RESYNC_BITS 1 +#define CAPT_INIT_RESTART_IDX CAPT_INIT_RESTART_BIT +#define CAPT_INIT_RESTART_BITS 1 +#define CAPT_INIT_RESTART_MEM_ADDR_IDX CAPT_INIT_RESTART_MEM_ADDR_LSB +#define CAPT_INIT_RESTART_MEM_ADDR_BITS (CAPT_INIT_RESTART_MEM_ADDR_MSB - CAPT_INIT_RESTART_MEM_ADDR_LSB + 1) +#define CAPT_INIT_RESTART_MEM_REGION_IDX CAPT_INIT_RESTART_MEM_REGION_LSB +#define CAPT_INIT_RESTART_MEM_REGION_BITS (CAPT_INIT_RESTART_MEM_REGION_MSB - CAPT_INIT_RESTART_MEM_REGION_LSB + 1) + + + +/* --------------------------------------------------*/ +/* TOKEN INFO */ +/* --------------------------------------------------*/ +#define CAPT_TOKEN_ID_LSB 0 +#define CAPT_TOKEN_ID_MSB 3 +#define CAPT_TOKEN_WIDTH (CAPT_TOKEN_ID_MSB - CAPT_TOKEN_ID_LSB + 1) /* 4 */ + +/* Command tokens IDs */ +#define CAPT_START_TOKEN_ID 0 /* 0000b */ +#define CAPT_STOP_TOKEN_ID 1 /* 0001b */ +#define CAPT_FREEZE_TOKEN_ID 2 /* 0010b */ +#define CAPT_RESUME_TOKEN_ID 3 /* 0011b */ +#define CAPT_INIT_TOKEN_ID 8 /* 1000b */ + +#define CAPT_START_TOKEN_BIT 0 +#define CAPT_STOP_TOKEN_BIT 0 +#define CAPT_FREEZE_TOKEN_BIT 0 +#define CAPT_RESUME_TOKEN_BIT 0 +#define CAPT_INIT_TOKEN_BIT 0 + +/* Acknowledge token IDs */ +#define CAPT_END_OF_PACKET_RECEIVED_TOKEN_ID 0 /* 0000b */ +#define CAPT_END_OF_PACKET_WRITTEN_TOKEN_ID 1 /* 0001b */ +#define CAPT_END_OF_REGION_WRITTEN_TOKEN_ID 2 /* 0010b */ +#define CAPT_FLUSH_DONE_TOKEN_ID 3 /* 0011b */ +#define CAPT_PREMATURE_SOP_TOKEN_ID 4 /* 0100b */ +#define CAPT_MISSING_SOP_TOKEN_ID 5 /* 0101b */ +#define CAPT_UNDEF_PH_TOKEN_ID 6 /* 0110b */ +#define CAPT_STOP_ACK_TOKEN_ID 7 /* 0111b */ + +#define CAPT_PACKET_LENGTH_TOKEN_MSB 19 +#define CAPT_PACKET_LENGTH_TOKEN_LSB 4 +#define CAPT_SUPER_PACKET_LENGTH_TOKEN_MSB 20 +#define CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB 4 +#define CAPT_PACKET_DATA_FORMAT_ID_TOKEN_MSB 25 +#define CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB 20 +#define CAPT_PACKET_CH_ID_TOKEN_MSB 27 +#define CAPT_PACKET_CH_ID_TOKEN_LSB 26 +#define CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB 29 +#define CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB 21 + +/* bit definition */ +#define CAPT_CMD_IDX CAPT_TOKEN_ID_LSB +#define CAPT_CMD_BITS (CAPT_TOKEN_ID_MSB - CAPT_TOKEN_ID_LSB + 1) +#define CAPT_SOP_IDX 32 +#define CAPT_SOP_BITS 1 +#define CAPT_PKT_INFO_IDX 16 +#define CAPT_PKT_INFO_BITS 8 +#define CAPT_PKT_TYPE_IDX 0 +#define CAPT_PKT_TYPE_BITS 6 +#define CAPT_HEADER_DATA_IDX 0 +#define CAPT_HEADER_DATA_BITS 16 +#define CAPT_PKT_DATA_IDX 0 +#define CAPT_PKT_DATA_BITS 32 +#define CAPT_WORD_CNT_IDX 0 +#define CAPT_WORD_CNT_BITS 16 +#define CAPT_ACK_TOKEN_ID_IDX 0 +#define CAPT_ACK_TOKEN_ID_BITS 4 +//#define CAPT_ACK_PKT_LEN_IDX CAPT_PACKET_LENGTH_TOKEN_LSB +//#define CAPT_ACK_PKT_LEN_BITS (CAPT_PACKET_LENGTH_TOKEN_MSB - CAPT_PACKET_LENGTH_TOKEN_LSB + 1) +//#define CAPT_ACK_PKT_INFO_IDX 20 +//#define CAPT_ACK_PKT_INFO_BITS 8 +//#define CAPT_ACK_MEM_REG_ID1_IDX 20 /* for capt_end_of_packet_written */ +//#define CAPT_ACK_MEM_REG_ID2_IDX 4 /* for capt_end_of_region_written */ +#define CAPT_ACK_PKT_LEN_IDX CAPT_PACKET_LENGTH_TOKEN_LSB +#define CAPT_ACK_PKT_LEN_BITS (CAPT_PACKET_LENGTH_TOKEN_MSB - CAPT_PACKET_LENGTH_TOKEN_LSB + 1) +#define CAPT_ACK_SUPER_PKT_LEN_IDX CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB +#define CAPT_ACK_SUPER_PKT_LEN_BITS (CAPT_SUPER_PACKET_LENGTH_TOKEN_MSB - CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB + 1) +#define CAPT_ACK_PKT_INFO_IDX CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB +#define CAPT_ACK_PKT_INFO_BITS (CAPT_PACKET_CH_ID_TOKEN_MSB - CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB + 1) +#define CAPT_ACK_MEM_REGION_ID_IDX CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB +#define CAPT_ACK_MEM_REGION_ID_BITS (CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB - CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB + 1) +#define CAPT_ACK_PKT_TYPE_IDX CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB +#define CAPT_ACK_PKT_TYPE_BITS (CAPT_PACKET_DATA_FORMAT_ID_TOKEN_MSB - CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB + 1) +#define CAPT_INIT_TOKEN_INIT_IDX 4 +#define CAPT_INIT_TOKEN_INIT_BITS 22 + + +/* --------------------------------------------------*/ +/* MIPI */ +/* --------------------------------------------------*/ + +#define CAPT_WORD_COUNT_WIDTH 16 +#define CAPT_PKT_CODE_WIDTH 6 +#define CAPT_CHN_NO_WIDTH 2 +#define CAPT_ERROR_INFO_WIDTH 8 + +#define LONG_PKTCODE_MAX 63 +#define LONG_PKTCODE_MIN 16 +#define SHORT_PKTCODE_MAX 15 + + +/* --------------------------------------------------*/ +/* Packet Info */ +/* --------------------------------------------------*/ +#define CAPT_START_OF_FRAME 0 +#define CAPT_END_OF_FRAME 1 +#define CAPT_START_OF_LINE 2 +#define CAPT_END_OF_LINE 3 +#define CAPT_LINE_PAYLOAD 4 +#define CAPT_GEN_SH_PKT 5 + + +/* --------------------------------------------------*/ +/* Packet Data Type */ +/* --------------------------------------------------*/ + +#define CAPT_YUV420_8_DATA 24 /* 01 1000 YUV420 8-bit */ +#define CAPT_YUV420_10_DATA 25 /* 01 1001 YUV420 10-bit */ +#define CAPT_YUV420_8L_DATA 26 /* 01 1010 YUV420 8-bit legacy */ +#define CAPT_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */ +#define CAPT_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */ +#define CAPT_RGB444_DATA 32 /* 10 0000 RGB444 */ +#define CAPT_RGB555_DATA 33 /* 10 0001 RGB555 */ +#define CAPT_RGB565_DATA 34 /* 10 0010 RGB565 */ +#define CAPT_RGB666_DATA 35 /* 10 0011 RGB666 */ +#define CAPT_RGB888_DATA 36 /* 10 0100 RGB888 */ +#define CAPT_RAW6_DATA 40 /* 10 1000 RAW6 */ +#define CAPT_RAW7_DATA 41 /* 10 1001 RAW7 */ +#define CAPT_RAW8_DATA 42 /* 10 1010 RAW8 */ +#define CAPT_RAW10_DATA 43 /* 10 1011 RAW10 */ +#define CAPT_RAW12_DATA 44 /* 10 1100 RAW12 */ +#define CAPT_RAW14_DATA 45 /* 10 1101 RAW14 */ +#define CAPT_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */ +#define CAPT_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */ +#define CAPT_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */ +#define CAPT_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */ +#define CAPT_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */ +#define CAPT_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */ +#define CAPT_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */ +#define CAPT_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */ +#define CAPT_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */ +#define CAPT_SOF_DATA 0 /* 00 0000 frame start */ +#define CAPT_EOF_DATA 1 /* 00 0001 frame end */ +#define CAPT_SOL_DATA 2 /* 00 0010 line start */ +#define CAPT_EOL_DATA 3 /* 00 0011 line end */ +#define CAPT_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */ +#define CAPT_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */ +#define CAPT_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */ +#define CAPT_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */ +#define CAPT_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */ +#define CAPT_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */ +#define CAPT_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */ +#define CAPT_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */ +#define CAPT_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */ +#define CAPT_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */ +#define CAPT_RESERVED_DATA_TYPE_MIN 56 +#define CAPT_RESERVED_DATA_TYPE_MAX 63 +#define CAPT_GEN_LONG_RESERVED_DATA_TYPE_MIN 19 +#define CAPT_GEN_LONG_RESERVED_DATA_TYPE_MAX 23 +#define CAPT_YUV_RESERVED_DATA_TYPE 27 +#define CAPT_RGB_RESERVED_DATA_TYPE_MIN 37 +#define CAPT_RGB_RESERVED_DATA_TYPE_MAX 39 +#define CAPT_RAW_RESERVED_DATA_TYPE_MIN 46 +#define CAPT_RAW_RESERVED_DATA_TYPE_MAX 47 + + +/* --------------------------------------------------*/ +/* Capture Unit State */ +/* --------------------------------------------------*/ +#define CAPT_FREE_RUN 0 +#define CAPT_NO_SYNC 1 +#define CAPT_SYNC_SWP 2 +#define CAPT_SYNC_MWP 3 +#define CAPT_SYNC_WAIT 4 +#define CAPT_FREEZE 5 +#define CAPT_RUN 6 + + +/* --------------------------------------------------*/ + +#endif /* _isp_capture_defs_h */ + + + + + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/mipi_backend_common_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/mipi_backend_common_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..76705d7a2b44a77da916bde823b68232c630cc93 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/mipi_backend_common_defs.h @@ -0,0 +1,210 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _css_receiver_2400_common_defs_h_ +#define _css_receiver_2400_common_defs_h_ +#ifndef _mipi_backend_common_defs_h_ +#define _mipi_backend_common_defs_h_ + +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH 16 +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH 2 +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH 3 +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH (_HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_CH_ID_WIDTH + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_WIDTH 32 /* use 32 to be compatibel with streaming monitor !, MSB's of interface are tied to '0' */ + +/* Definition of data format ID at the interface CSS_receiver capture/acquisition units */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8 24 /* 01 1000 YUV420 8-bit */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10 25 /* 01 1001 YUV420 10-bit */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8L 26 /* 01 1010 YUV420 8-bit legacy */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_8 30 /* 01 1110 YUV422 8-bit */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV422_10 31 /* 01 1111 YUV422 10-bit */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB444 32 /* 10 0000 RGB444 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB555 33 /* 10 0001 RGB555 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB565 34 /* 10 0010 RGB565 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB666 35 /* 10 0011 RGB666 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RGB888 36 /* 10 0100 RGB888 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW6 40 /* 10 1000 RAW6 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW7 41 /* 10 1001 RAW7 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW8 42 /* 10 1010 RAW8 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW10 43 /* 10 1011 RAW10 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW12 44 /* 10 1100 RAW12 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW14 45 /* 10 1101 RAW14 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_1 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_2 49 /* 11 0001 User Defined 8-bit Data Type 2 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_3 50 /* 11 0010 User Defined 8-bit Data Type 3 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_4 51 /* 11 0011 User Defined 8-bit Data Type 4 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_5 52 /* 11 0100 User Defined 8-bit Data Type 5 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_6 53 /* 11 0101 User Defined 8-bit Data Type 6 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_7 54 /* 11 0110 User Defined 8-bit Data Type 7 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_USR_DEF_8 55 /* 11 0111 User Defined 8-bit Data Type 8 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_Emb 18 /* 01 0010 embedded eight bit non image data */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_SOF 0 /* 00 0000 frame start */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_EOF 1 /* 00 0001 frame end */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_SOL 2 /* 00 0010 line start */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_EOL 3 /* 00 0011 line end */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH1 8 /* 00 1000 Generic Short Packet Code 1 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH2 9 /* 00 1001 Generic Short Packet Code 2 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH3 10 /* 00 1010 Generic Short Packet Code 3 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH4 11 /* 00 1011 Generic Short Packet Code 4 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH5 12 /* 00 1100 Generic Short Packet Code 5 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH6 13 /* 00 1101 Generic Short Packet Code 6 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH7 14 /* 00 1110 Generic Short Packet Code 7 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_GEN_SH8 15 /* 00 1111 Generic Short Packet Code 8 */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_8_CSPS 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_YUV420_10_CSPS 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */ +/* used reseved mipi positions for these */ +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW16 46 +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18 47 +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_2 37 +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_RAW18_3 38 + +//_HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 63 +#define _HRT_MIPI_BACKEND_FMT_TYPE_CUSTOM 63 + +#define _HRT_CSS_RECEIVER_2400_DATA_FORMAT_ID_WIDTH 6 + +/* Definition of format_types at the interface CSS --> input_selector*/ +/* !! Changes here should be copied to systems/isp/isp_css/bin/conv_transmitter_cmd.tcl !! */ +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB888 0 // 36 'h24 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB555 1 // 33 'h +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB444 2 // 32 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB565 3 // 34 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB666 4 // 35 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW10 6 // 43 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW6 7 // 40 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW7 8 // 41 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW12 9 // 43 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW14 10 // 45 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8 11 // 30 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10 12 // 25 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_8 13 // 30 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_10 14 // 31 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_1 15 // 48 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8L 16 // 26 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_Emb 17 // 18 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_2 18 // 49 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_3 19 // 50 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_4 20 // 51 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_5 21 // 52 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_6 22 // 53 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_7 23 // 54 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_8 24 // 55 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8_CSPS 25 // 28 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10_CSPS 26 // 29 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW16 27 // ? +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18 28 // ? +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_2 29 // ? Option 2 for depacketiser +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_3 30 // ? Option 3 for depacketiser +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding + +/* definition for state machine of data FIFO for decode different type of data */ +#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV420_10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_YUV420_8L_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV422_8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV422_10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB555_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB565_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9 +#define _HRT_CSS_RECEIVER_2400_RGB888_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW6_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW7_REPEAT_PTN 7 +#define _HRT_CSS_RECEIVER_2400_RAW8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_RAW10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW14_REPEAT_PTN 7 + +#define _HRT_CSS_RECEIVER_2400_MAX_REPEAT_PTN _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN + +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_WIDTH 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_IDX 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_WIDTH 1 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_USD_BITS 4 /* bits per USD type */ + +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_EN_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_OPTION_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_EN_IDX 8 + +#define _HRT_CSS_RECEIVER_2400_BE_COMP_NO_COMP 0 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_6_10 1 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_7_10 2 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_8_10 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_6_12 4 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_7_12 5 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_8_12 6 + + +/* packet bit definition */ +#define _HRT_CSS_RECEIVER_2400_PKT_SOP_IDX 32 +#define _HRT_CSS_RECEIVER_2400_PKT_SOP_BITS 1 +#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_IDX 22 +#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_BITS 2 +#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_IDX 16 +#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_BITS 6 +#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_IDX 0 +#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_BITS 16 +#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_IDX 0 +#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_BITS 32 + + +/*************************************************************************************************/ +/* Custom Decoding */ +/* These Custom Defs are defined based on design-time config in "mipi_backend_pixel_formatter.chdl" !! */ +/*************************************************************************************************/ +/* +#define BE_CUST_EN_IDX 0 // 2bits +#define BE_CUST_EN_DATAID_IDX 2 // 6bits MIPI DATA ID +#define BE_CUST_EN_WIDTH 8 +#define BE_CUST_MODE_ALL 1 // Enable Custom Decoding for all DATA IDs +#define BE_CUST_MODE_ONE 3 // Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID + +// Data State config = {get_bits(6bits), valid(1bit)} // +#define BE_CUST_DATA_STATE_S0_IDX 0 // 7bits +#define BE_CUST_DATA_STATE_S1_IDX 8 //7 // 7bits +#define BE_CUST_DATA_STATE_S2_IDX 16//14 // 7bits / +#define BE_CUST_DATA_STATE_WIDTH 24//21 +#define BE_CUST_DATA_STATE_VALID_IDX 0 // 1bits +#define BE_CUST_DATA_STATE_GETBITS_IDX 1 // 6bits + + + + +// Pixel Extractor config +#define BE_CUST_PIX_EXT_DATA_ALIGN_IDX 0 // 6bits +#define BE_CUST_PIX_EXT_PIX_ALIGN_IDX 6//5 // 5bits +#define BE_CUST_PIX_EXT_PIX_MASK_IDX 11//10 // 18bits +#define BE_CUST_PIX_EXT_PIX_EN_IDX 29 //28 // 1bits + +#define BE_CUST_PIX_EXT_WIDTH 30//29 + +// Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} +#define BE_CUST_PIX_VALID_EOP_P0_IDX 0 // 4bits +#define BE_CUST_PIX_VALID_EOP_P1_IDX 4 // 4bits +#define BE_CUST_PIX_VALID_EOP_P2_IDX 8 // 4bits +#define BE_CUST_PIX_VALID_EOP_P3_IDX 12 // 4bits +#define BE_CUST_PIX_VALID_EOP_WIDTH 16 +#define BE_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 // Normal (NO less get_bits case) Valid - 1bits +#define BE_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 // Normal (NO less get_bits case) EoP - 1bits +#define BE_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 // Especial (less get_bits case) Valid - 1bits +#define BE_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 // Especial (less get_bits case) EoP - 1bits + +*/ + +#endif /* _mipi_backend_common_defs_h_ */ +#endif /* _css_receiver_2400_common_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/mipi_backend_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/mipi_backend_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..db5a1d2caba0b754e81e14b2daa182ae7b16f1e9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/mipi_backend_defs.h @@ -0,0 +1,215 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _mipi_backend_defs_h +#define _mipi_backend_defs_h + +#include "mipi_backend_common_defs.h" + +#define MIPI_BACKEND_REG_ALIGN 4 // assuming 32 bit control bus width + +#define _HRT_MIPI_BACKEND_NOF_IRQS 3 // sid_lut + +// SH Backend Register IDs +#define _HRT_MIPI_BACKEND_ENABLE_REG_IDX 0 +#define _HRT_MIPI_BACKEND_STATUS_REG_IDX 1 +//#define _HRT_MIPI_BACKEND_HIGH_PREC_REG_IDX 2 +#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG0_IDX 2 +#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG1_IDX 3 +#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG2_IDX 4 +#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG3_IDX 5 +#define _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_IDX 6 +#define _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_IDX 7 +#define _HRT_MIPI_BACKEND_FORCE_RAW8_REG_IDX 8 +#define _HRT_MIPI_BACKEND_IRQ_STATUS_REG_IDX 9 +#define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_IDX 10 +//// +#define _HRT_MIPI_BACKEND_CUST_EN_REG_IDX 11 +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_REG_IDX 12 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P0_REG_IDX 13 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P1_REG_IDX 14 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P2_REG_IDX 15 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S0P3_REG_IDX 16 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P0_REG_IDX 17 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P1_REG_IDX 18 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P2_REG_IDX 19 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S1P3_REG_IDX 20 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P0_REG_IDX 21 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P1_REG_IDX 22 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P2_REG_IDX 23 +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_S2P3_REG_IDX 24 +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_REG_IDX 25 +//// +#define _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_IDX 26 +#define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_IDX 27 +//#define _HRT_MIPI_BACKEND_SP_LUT_ENABLE_REG_IDX 28 +#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_IDX 28 +#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_IDX 29 +#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_IDX 30 +#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_IDX 31 + +#define _HRT_MIPI_BACKEND_NOF_REGISTERS 32 // excluding the LP LUT entries + +#define _HRT_MIPI_BACKEND_LP_LUT_ENTRY_0_REG_IDX 32 + + +///////////////////////////////////////////////////////////////////////////////////////////////////// +#define _HRT_MIPI_BACKEND_ENABLE_REG_WIDTH 1 +#define _HRT_MIPI_BACKEND_STATUS_REG_WIDTH 1 +//#define _HRT_MIPI_BACKEND_HIGH_PREC_REG_WIDTH 1 +#define _HRT_MIPI_BACKEND_COMP_FORMAT_REG_WIDTH 32 +#define _HRT_MIPI_BACKEND_RAW16_CONFIG_REG_WIDTH 7 +#define _HRT_MIPI_BACKEND_RAW18_CONFIG_REG_WIDTH 9 +#define _HRT_MIPI_BACKEND_FORCE_RAW8_REG_WIDTH 8 +#define _HRT_MIPI_BACKEND_IRQ_STATUS_REG_WIDTH _HRT_MIPI_BACKEND_NOF_IRQS +#define _HRT_MIPI_BACKEND_IRQ_CLEAR_REG_WIDTH 0 +#define _HRT_MIPI_BACKEND_GLOBAL_LUT_DISREGARD_REG_WIDTH 1 +#define _HRT_MIPI_BACKEND_PKT_STALL_STATUS_REG_WIDTH 1+2+6 +//#define _HRT_MIPI_BACKEND_SP_LUT_ENABLE_REG_WIDTH 1 +//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_0_REG_WIDTH 7 +//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_1_REG_WIDTH 7 +//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_2_REG_WIDTH 7 +//#define _HRT_MIPI_BACKEND_SP_LUT_ENTRY_3_REG_WIDTH 7 + +///////////////////////////////////////////////////////////////////////////////////////////////////// + +#define _HRT_MIPI_BACKEND_NOF_SP_LUT_ENTRIES 4 + +//#define _HRT_MIPI_BACKEND_MAX_NOF_LP_LUT_ENTRIES 16 // to satisfy hss model static array declaration + + +#define _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH 2 +#define _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH 6 +#define _HRT_MIPI_BACKEND_PACKET_ID_WIDTH _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH + _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH + +#define _HRT_MIPI_BACKEND_STREAMING_PIX_A_LSB 0 +#define _HRT_MIPI_BACKEND_STREAMING_PIX_A_MSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_LSB + (pix_width) - 1) +#define _HRT_MIPI_BACKEND_STREAMING_PIX_A_VAL_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_MSB(pix_width) + 1) +#define _HRT_MIPI_BACKEND_STREAMING_PIX_B_LSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_A_VAL_BIT(pix_width) + 1) +#define _HRT_MIPI_BACKEND_STREAMING_PIX_B_MSB(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_LSB(pix_width) + (pix_width) - 1) +#define _HRT_MIPI_BACKEND_STREAMING_PIX_B_VAL_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_MSB(pix_width) + 1) +#define _HRT_MIPI_BACKEND_STREAMING_SOP_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_PIX_B_VAL_BIT(pix_width) + 1) +#define _HRT_MIPI_BACKEND_STREAMING_EOP_BIT(pix_width) (_HRT_MIPI_BACKEND_STREAMING_SOP_BIT(pix_width) + 1) +#define _HRT_MIPI_BACKEND_STREAMING_WIDTH(pix_width) (_HRT_MIPI_BACKEND_STREAMING_EOP_BIT(pix_width) + 1) + +/*************************************************************************************************/ +/* Custom Decoding */ +/* These Custom Defs are defined based on design-time config in "mipi_backend_pixel_formatter.chdl" !! */ +/*************************************************************************************************/ +#define _HRT_MIPI_BACKEND_CUST_EN_IDX 0 /* 2bits */ +#define _HRT_MIPI_BACKEND_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */ +#define _HRT_MIPI_BACKEND_CUST_EN_HIGH_PREC_IDX 8 // 1 bit +#define _HRT_MIPI_BACKEND_CUST_EN_WIDTH 9 +#define _HRT_MIPI_BACKEND_CUST_MODE_ALL 1 /* Enable Custom Decoding for all DATA IDs */ +#define _HRT_MIPI_BACKEND_CUST_MODE_ONE 3 /* Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID */ + +#define _HRT_MIPI_BACKEND_CUST_EN_OPTION_IDX 1 + +/* Data State config = {get_bits(6bits), valid(1bit)} */ +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S0_IDX 0 /* 7bits */ +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S1_IDX 8 /* 7bits */ +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_S2_IDX 16 /* was 14 7bits */ +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_WIDTH 24 /* was 21*/ +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_VALID_IDX 0 /* 1bits */ +#define _HRT_MIPI_BACKEND_CUST_DATA_STATE_GETBITS_IDX 1 /* 6bits */ + +/* Pixel Extractor config */ +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_DATA_ALIGN_IDX 0 /* 6bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_ALIGN_IDX 6 /* 5bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_MASK_IDX 11 /* was 10 18bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_PIX_EN_IDX 29 /* was 28 1bits */ + +#define _HRT_MIPI_BACKEND_CUST_PIX_EXT_WIDTH 30 /* was 29 */ + +/* Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P0_IDX 0 /* 4bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P1_IDX 4 /* 4bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P2_IDX 8 /* 4bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_P3_IDX 12 /* 4bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_WIDTH 16 +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 /* Normal (NO less get_bits case) Valid - 1bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 /* Normal (NO less get_bits case) EoP - 1bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 /* Especial (less get_bits case) Valid - 1bits */ +#define _HRT_MIPI_BACKEND_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 /* Especial (less get_bits case) EoP - 1bits */ + +/*************************************************************************************************/ +/* MIPI backend output streaming interface definition */ +/* These parameters define the fields within the streaming bus. These should also be used by the */ +/* subsequent block, ie stream2mmio. */ +/*************************************************************************************************/ +/* The pipe backend - stream2mmio should be design time configurable in */ +/* PixWidth - Number of bits per pixel */ +/* PPC - Pixel per Clocks */ +/* NumSids - Max number of source Ids (ifc's) and derived from that: */ +/* SidWidth - Number of bits required for the sid parameter */ +/* In order to keep this configurability, below Macro's have these as a parameter */ +/*************************************************************************************************/ + +#define HRT_MIPI_BACKEND_STREAM_EOP_BIT 0 +#define HRT_MIPI_BACKEND_STREAM_SOP_BIT 1 +#define HRT_MIPI_BACKEND_STREAM_EOF_BIT 2 +#define HRT_MIPI_BACKEND_STREAM_SOF_BIT 3 +#define HRT_MIPI_BACKEND_STREAM_CHID_LS_BIT 4 +#define HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT(sid_width) (HRT_MIPI_BACKEND_STREAM_CHID_LS_BIT+(sid_width)-1) +#define HRT_MIPI_BACKEND_STREAM_PIX_VAL_BIT(sid_width,p) (HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT(sid_width)+1+p) + +#define HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width,ppc,pix_width,p) (HRT_MIPI_BACKEND_STREAM_PIX_VAL_BIT(sid_width,ppc)+ ((pix_width)*p)) +#define HRT_MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_width,ppc,pix_width,p) (HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width,ppc,pix_width,p) + (pix_width) - 1) + +#if 0 +//#define HRT_MIPI_BACKEND_STREAM_PIX_BITS 14 +//#define HRT_MIPI_BACKEND_STREAM_CHID_BITS 4 +//#define HRT_MIPI_BACKEND_STREAM_PPC 4 +#endif + +#define HRT_MIPI_BACKEND_STREAM_BITS(sid_width,ppc,pix_width) (HRT_MIPI_BACKEND_STREAM_PIX_MS_BIT(sid_width,ppc,pix_width,(ppc-1))+1) + + +/* SP and LP LUT BIT POSITIONS */ +#define HRT_MIPI_BACKEND_LUT_PKT_DISREGARD_BIT 0 // 0 +#define HRT_MIPI_BACKEND_LUT_SID_LS_BIT HRT_MIPI_BACKEND_LUT_PKT_DISREGARD_BIT + 1 // 1 +#define HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) (HRT_MIPI_BACKEND_LUT_SID_LS_BIT+(sid_width)-1) // 1 + (4) - 1 = 4 +#define HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_LS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) + 1 // 5 +#define HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_LS_BIT(sid_width) + _HRT_MIPI_BACKEND_CHANNEL_ID_WIDTH - 1 // 6 +#define HRT_MIPI_BACKEND_LUT_MIPI_FMT_LS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) + 1 // 7 +#define HRT_MIPI_BACKEND_LUT_MIPI_FMT_MS_BIT(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_FMT_LS_BIT(sid_width) + _HRT_MIPI_BACKEND_FORMAT_TYPE_WIDTH - 1 // 12 + +/* #define HRT_MIPI_BACKEND_SP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_CH_ID_MS_BIT(sid_width) + 1 // 7 */ + +#define HRT_MIPI_BACKEND_SP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_SID_MS_BIT(sid_width) + 1 +#define HRT_MIPI_BACKEND_LP_LUT_BITS(sid_width) HRT_MIPI_BACKEND_LUT_MIPI_FMT_MS_BIT(sid_width) + 1 // 13 + + +// temp solution +//#define HRT_MIPI_BACKEND_STREAM_PIXA_VAL_BIT HRT_MIPI_BACKEND_STREAM_CHID_MS_BIT + 1 // 8 +//#define HRT_MIPI_BACKEND_STREAM_PIXB_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXA_VAL_BIT + 1 // 9 +//#define HRT_MIPI_BACKEND_STREAM_PIXC_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXB_VAL_BIT + 1 // 10 +//#define HRT_MIPI_BACKEND_STREAM_PIXD_VAL_BIT HRT_MIPI_BACKEND_STREAM_PIXC_VAL_BIT + 1 // 11 +//#define HRT_MIPI_BACKEND_STREAM_PIXA_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXD_VAL_BIT + 1 // 12 +//#define HRT_MIPI_BACKEND_STREAM_PIXA_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXA_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 25 +//#define HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXA_MS_BIT + 1 // 26 +//#define HRT_MIPI_BACKEND_STREAM_PIXB_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 39 +//#define HRT_MIPI_BACKEND_STREAM_PIXC_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXB_MS_BIT + 1 // 40 +//#define HRT_MIPI_BACKEND_STREAM_PIXC_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXC_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 53 +//#define HRT_MIPI_BACKEND_STREAM_PIXD_LS_BIT HRT_MIPI_BACKEND_STREAM_PIXC_MS_BIT + 1 // 54 +//#define HRT_MIPI_BACKEND_STREAM_PIXD_MS_BIT HRT_MIPI_BACKEND_STREAM_PIXD_LS_BIT + HRT_MIPI_BACKEND_STREAM_PIX_BITS - 1 // 67 + +// vc hidden in pixb data (passed as raw12 the pipe) +#define HRT_MIPI_BACKEND_STREAM_VC_LS_BIT(sid_width,ppc,pix_width) HRT_MIPI_BACKEND_STREAM_PIX_LS_BIT(sid_width,ppc,pix_width,1) + 10 //HRT_MIPI_BACKEND_STREAM_PIXB_LS_BIT + 10 // 36 +#define HRT_MIPI_BACKEND_STREAM_VC_MS_BIT(sid_width,ppc,pix_width) HRT_MIPI_BACKEND_STREAM_VC_LS_BIT(sid_width,ppc,pix_width) + 1 // 37 + + + + +#endif /* _mipi_backend_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/mmu_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/mmu_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..c038f39ffd25e3f3d1b9afdbba93495642da5e6b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/mmu_defs.h @@ -0,0 +1,23 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _mmu_defs_h +#define _mmu_defs_h + +#define _HRT_MMU_INVALIDATE_TLB_REG_IDX 0 +#define _HRT_MMU_PAGE_TABLE_BASE_ADDRESS_REG_IDX 1 + +#define _HRT_MMU_REG_ALIGN 4 + +#endif /* _mmu_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/rx_csi_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/rx_csi_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..0aad86e2e9145b5ee7ce7d37ec8673245b4d0337 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/rx_csi_defs.h @@ -0,0 +1,175 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _csi_rx_defs_h +#define _csi_rx_defs_h + +//#include "rx_csi_common_defs.h" + + + +#define MIPI_PKT_DATA_WIDTH 32 +//#define CLK_CROSSING_FIFO_DEPTH 16 +#define _CSI_RX_REG_ALIGN 4 + +//define number of IRQ (see below for definition of each IRQ bits) +#define CSI_RX_NOF_IRQS_BYTE_DOMAIN 11 +#define CSI_RX_NOF_IRQS_ISP_DOMAIN 15 // CSI_RX_NOF_IRQS_BYTE_DOMAIN + remaining from Dphy_rx already on ISP clock domain + +// REGISTER DESCRIPTION +//#define _HRT_CSI_RX_SOFTRESET_REG_IDX 0 +#define _HRT_CSI_RX_ENABLE_REG_IDX 0 +#define _HRT_CSI_RX_NOF_ENABLED_LANES_REG_IDX 1 +#define _HRT_CSI_RX_ERROR_HANDLING_REG_IDX 2 +#define _HRT_CSI_RX_STATUS_REG_IDX 3 +#define _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX 4 +#define _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX 5 +//#define _HRT_CSI_RX_IRQ_CONFIG_REG_IDX 6 +#define _HRT_CSI_RX_DLY_CNT_TERMEN_CLANE_REG_IDX 6 +#define _HRT_CSI_RX_DLY_CNT_SETTLE_CLANE_REG_IDX 7 +#define _HRT_CSI_RX_DLY_CNT_TERMEN_DLANE_REG_IDX(lane_idx) (8+(2*lane_idx)) +#define _HRT_CSI_RX_DLY_CNT_SETTLE_DLANE_REG_IDX(lane_idx) (8+(2*lane_idx)+1) + +#define _HRT_CSI_RX_NOF_REGISTERS(nof_dlanes) (8+2*(nof_dlanes)) + + +//#define _HRT_CSI_RX_SOFTRESET_REG_WIDTH 1 +#define _HRT_CSI_RX_ENABLE_REG_WIDTH 1 +#define _HRT_CSI_RX_NOF_ENABLED_LANES_REG_WIDTH 3 +#define _HRT_CSI_RX_ERROR_HANDLING_REG_WIDTH 4 +#define _HRT_CSI_RX_STATUS_REG_WIDTH 1 +#define _HRT_CSI_RX_STATUS_DLANE_HS_REG_WIDTH 8 +#define _HRT_CSI_RX_STATUS_DLANE_LP_REG_WIDTH 24 +#define _HRT_CSI_RX_IRQ_CONFIG_REG_WIDTH (CSI_RX_NOF_IRQS_ISP_DOMAIN) +#define _HRT_CSI_RX_DLY_CNT_REG_WIDTH 24 +//#define _HRT_CSI_RX_IRQ_STATUS_REG_WIDTH NOF_IRQS +//#define _HRT_CSI_RX_IRQ_CLEAR_REG_WIDTH 0 + + +#define ONE_LANE_ENABLED 0 +#define TWO_LANES_ENABLED 1 +#define THREE_LANES_ENABLED 2 +#define FOUR_LANES_ENABLED 3 + +// Error handling reg bit positions +#define ERR_DECISION_BIT 0 +#define DISC_RESERVED_SP_BIT 1 +#define DISC_RESERVED_LP_BIT 2 +#define DIS_INCOMP_PKT_CHK_BIT 3 + +#define _HRT_CSI_RX_IRQ_CONFIG_REG_VAL_POSEDGE 0 +#define _HRT_CSI_RX_IRQ_CONFIG_REG_VAL_ORIGINAL 1 + +// Interrupt bits +#define _HRT_RX_CSI_IRQ_SINGLE_PH_ERROR_CORRECTED 0 +#define _HRT_RX_CSI_IRQ_MULTIPLE_PH_ERROR_DETECTED 1 +#define _HRT_RX_CSI_IRQ_PAYLOAD_CHECKSUM_ERROR 2 +#define _HRT_RX_CSI_IRQ_FIFO_FULL_ERROR 3 +#define _HRT_RX_CSI_IRQ_RESERVED_SP_DETECTED 4 +#define _HRT_RX_CSI_IRQ_RESERVED_LP_DETECTED 5 +//#define _HRT_RX_CSI_IRQ_PREMATURE_SOP 6 +#define _HRT_RX_CSI_IRQ_INCOMPLETE_PACKET 6 +#define _HRT_RX_CSI_IRQ_FRAME_SYNC_ERROR 7 +#define _HRT_RX_CSI_IRQ_LINE_SYNC_ERROR 8 +#define _HRT_RX_CSI_IRQ_DLANE_HS_SOT_ERROR 9 +#define _HRT_RX_CSI_IRQ_DLANE_HS_SOT_SYNC_ERROR 10 + +#define _HRT_RX_CSI_IRQ_DLANE_ESC_ERROR 11 +#define _HRT_RX_CSI_IRQ_DLANE_TRIGGERESC 12 +#define _HRT_RX_CSI_IRQ_DLANE_ULPSESC 13 +#define _HRT_RX_CSI_IRQ_CLANE_ULPSCLKNOT 14 + +/* OLD ARASAN FRONTEND IRQs +#define _HRT_RX_CSI_IRQ_OVERRUN_BIT 0 +#define _HRT_RX_CSI_IRQ_RESERVED_BIT 1 +#define _HRT_RX_CSI_IRQ_SLEEP_MODE_ENTRY_BIT 2 +#define _HRT_RX_CSI_IRQ_SLEEP_MODE_EXIT_BIT 3 +#define _HRT_RX_CSI_IRQ_ERR_SOT_HS_BIT 4 +#define _HRT_RX_CSI_IRQ_ERR_SOT_SYNC_HS_BIT 5 +#define _HRT_RX_CSI_IRQ_ERR_CONTROL_BIT 6 +#define _HRT_RX_CSI_IRQ_ERR_ECC_DOUBLE_BIT 7 +#define _HRT_RX_CSI_IRQ_ERR_ECC_CORRECTED_BIT 8 +#define _HRT_RX_CSI_IRQ_ERR_ECC_NO_CORRECTION_BIT 9 +#define _HRT_RX_CSI_IRQ_ERR_CRC_BIT 10 +#define _HRT_RX_CSI_IRQ_ERR_ID_BIT 11 +#define _HRT_RX_CSI_IRQ_ERR_FRAME_SYNC_BIT 12 +#define _HRT_RX_CSI_IRQ_ERR_FRAME_DATA_BIT 13 +#define _HRT_RX_CSI_IRQ_DATA_TIMEOUT_BIT 14 +#define _HRT_RX_CSI_IRQ_ERR_ESCAPE_BIT 15 +#define _HRT_RX_CSI_IRQ_ERR_LINE_SYNC_BIT 16 +*/ + + +////Bit Description for reg _HRT_CSI_RX_STATUS_DLANE_HS_REG_IDX +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE0 0 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE1 1 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE2 2 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_ERR_LANE3 3 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE0 4 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE1 5 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE2 6 +#define _HRT_CSI_RX_STATUS_DLANE_HS_SOT_SYNC_ERR_LANE3 7 + +////Bit Description for reg _HRT_CSI_RX_STATUS_DLANE_LP_REG_IDX +#define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE0 0 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE1 1 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE2 2 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ESC_ERR_LANE3 3 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE0 4 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE0 5 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE0 6 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE0 7 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE1 8 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE1 9 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE1 10 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE1 11 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE2 12 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE2 13 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE2 14 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE2 15 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC0_LANE3 16 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC1_LANE3 17 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC2_LANE3 18 +#define _HRT_CSI_RX_STATUS_DLANE_LP_TRIGGERESC3_LANE3 19 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE0 20 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE1 21 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE2 22 +#define _HRT_CSI_RX_STATUS_DLANE_LP_ULPSESC_LANE3 23 + +/*********************************************************/ +/*** Relevant declarations from rx_csi_common_defs.h *****/ +/*********************************************************/ +/* packet bit definition */ +#define _HRT_RX_CSI_PKT_SOP_BITPOS 32 +#define _HRT_RX_CSI_PKT_EOP_BITPOS 33 +#define _HRT_RX_CSI_PKT_PAYLOAD_BITPOS 0 +#define _HRT_RX_CSI_PH_CH_ID_BITPOS 22 +#define _HRT_RX_CSI_PH_FMT_ID_BITPOS 16 +#define _HRT_RX_CSI_PH_DATA_FIELD_BITPOS 0 + +#define _HRT_RX_CSI_PKT_SOP_BITS 1 +#define _HRT_RX_CSI_PKT_EOP_BITS 1 +#define _HRT_RX_CSI_PKT_PAYLOAD_BITS 32 +#define _HRT_RX_CSI_PH_CH_ID_BITS 2 +#define _HRT_RX_CSI_PH_FMT_ID_BITS 6 +#define _HRT_RX_CSI_PH_DATA_FIELD_BITS 16 + +/* Definition of data format ID at the interface CSS_receiver units */ +#define _HRT_RX_CSI_DATA_FORMAT_ID_SOF 0 /* 00 0000 frame start */ +#define _HRT_RX_CSI_DATA_FORMAT_ID_EOF 1 /* 00 0001 frame end */ +#define _HRT_RX_CSI_DATA_FORMAT_ID_SOL 2 /* 00 0010 line start */ +#define _HRT_RX_CSI_DATA_FORMAT_ID_EOL 3 /* 00 0011 line end */ + + +#endif /* _csi_rx_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/scalar_processor_2400_params.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/scalar_processor_2400_params.h new file mode 100644 index 0000000000000000000000000000000000000000..9b6c2893d950708458b4c82d4f5951923b57512e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/scalar_processor_2400_params.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _scalar_processor_2400_params_h +#define _scalar_processor_2400_params_h + +#include "cell_params.h" + +#endif /* _scalar_processor_2400_params_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/sp_hrt.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/sp_hrt.h new file mode 100644 index 0000000000000000000000000000000000000000..7ee4deba519ac9988da4ab01774a0899be97e7d5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/sp_hrt.h @@ -0,0 +1,24 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _sp_hrt_h_ +#define _sp_hrt_h_ + +#define hrt_sp_dmem(cell) HRT_PROC_TYPE_PROP(cell, _dmem) + +#define hrt_sp_dmem_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_sp_dmem(cell)) + +#endif /* _sp_hrt_h_ */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/str2mem_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/str2mem_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..1cb62444cf68bc590aceb0f6d3958feec81d95e2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/str2mem_defs.h @@ -0,0 +1,39 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _ST2MEM_DEFS_H +#define _ST2MEM_DEFS_H + +#define _STR2MEM_CRUN_BIT 0x100000 +#define _STR2MEM_CMD_BITS 0x0F0000 +#define _STR2MEM_COUNT_BITS 0x00FFFF + +#define _STR2MEM_BLOCKS_CMD 0xA0000 +#define _STR2MEM_PACKETS_CMD 0xB0000 +#define _STR2MEM_BYTES_CMD 0xC0000 +#define _STR2MEM_BYTES_FROM_PACKET_CMD 0xD0000 + +#define _STR2MEM_SOFT_RESET_REG_ID 0 +#define _STR2MEM_INPUT_ENDIANNESS_REG_ID 1 +#define _STR2MEM_OUTPUT_ENDIANNESS_REG_ID 2 +#define _STR2MEM_BIT_SWAPPING_REG_ID 3 +#define _STR2MEM_BLOCK_SYNC_LEVEL_REG_ID 4 +#define _STR2MEM_PACKET_SYNC_LEVEL_REG_ID 5 +#define _STR2MEM_READ_POST_WRITE_SYNC_ENABLE_REG_ID 6 +#define _STR2MEM_DUAL_BYTE_INPUTS_ENABLED_REG_ID 7 +#define _STR2MEM_EN_STAT_UPDATE_ID 8 + +#define _STR2MEM_REG_ALIGN 4 + +#endif /* _ST2MEM_DEFS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/stream2mmio_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/stream2mmio_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..46b52fe5ae995900f6d75019a28681ba43efca4a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/stream2mmio_defs.h @@ -0,0 +1,71 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _STREAM2MMMIO_DEFS_H +#define _STREAM2MMMIO_DEFS_H + +#include + +#define _STREAM2MMIO_REG_ALIGN 4 + +#define _STREAM2MMIO_COMMAND_REG_ID 0 +#define _STREAM2MMIO_ACKNOWLEDGE_REG_ID 1 +#define _STREAM2MMIO_PIX_WIDTH_ID_REG_ID 2 +#define _STREAM2MMIO_START_ADDR_REG_ID 3 /* master port address,NOT Byte */ +#define _STREAM2MMIO_END_ADDR_REG_ID 4 /* master port address,NOT Byte */ +#define _STREAM2MMIO_STRIDE_REG_ID 5 /* stride in master port words, increment is per packet for long sids, stride is not used for short sid's*/ +#define _STREAM2MMIO_NUM_ITEMS_REG_ID 6 /* number of packets for store packets cmd, number of words for store_words cmd */ +#define _STREAM2MMIO_BLOCK_WHEN_NO_CMD_REG_ID 7 /* if this register is 1, input will be stalled if there is no pending command for this sid */ +#define _STREAM2MMIO_REGS_PER_SID 8 + +#define _STREAM2MMIO_SID_REG_OFFSET 8 +#define _STREAM2MMIO_MAX_NOF_SIDS 64 /* value used in hss model */ + +/* command token definition */ +#define _STREAM2MMIO_CMD_TOKEN_CMD_LSB 0 /* bits 1-0 is for the command field */ +#define _STREAM2MMIO_CMD_TOKEN_CMD_MSB 1 + +#define _STREAM2MMIO_CMD_TOKEN_WIDTH (_STREAM2MMIO_CMD_TOKEN_CMD_MSB+1-_STREAM2MMIO_CMD_TOKEN_CMD_LSB) + +#define _STREAM2MMIO_CMD_TOKEN_STORE_WORDS 0 /* command for storing a number of output words indicated by reg _STREAM2MMIO_NUM_ITEMS */ +#define _STREAM2MMIO_CMD_TOKEN_STORE_PACKETS 1 /* command for storing a number of packets indicated by reg _STREAM2MMIO_NUM_ITEMS */ +#define _STREAM2MMIO_CMD_TOKEN_SYNC_FRAME 2 /* command for waiting for a frame start */ + +/* acknowledges from packer module */ +/* fields: eof - indicates whether last (short) packet received was an eof packet */ +/* eop - indicates whether command has ended due to packet end or due to no of words requested has been received */ +/* count - indicates number of words stored */ +#define _STREAM2MMIO_PACK_NUM_ITEMS_BITS 16 +#define _STREAM2MMIO_PACK_ACK_EOP_BIT _STREAM2MMIO_PACK_NUM_ITEMS_BITS +#define _STREAM2MMIO_PACK_ACK_EOF_BIT (_STREAM2MMIO_PACK_ACK_EOP_BIT+1) + +/* acknowledge token definition */ +#define _STREAM2MMIO_ACK_TOKEN_NUM_ITEMS_LSB 0 /* bits 3-0 is for the command field */ +#define _STREAM2MMIO_ACK_TOKEN_NUM_ITEMS_MSB (_STREAM2MMIO_PACK_NUM_ITEMS_BITS-1) +#define _STREAM2MMIO_ACK_TOKEN_EOP_BIT _STREAM2MMIO_PACK_ACK_EOP_BIT +#define _STREAM2MMIO_ACK_TOKEN_EOF_BIT _STREAM2MMIO_PACK_ACK_EOF_BIT +#define _STREAM2MMIO_ACK_TOKEN_VALID_BIT (_STREAM2MMIO_ACK_TOKEN_EOF_BIT+1) /* this bit indicates a valid ack */ + /* if there is no valid ack, a read */ + /* on the ack register returns 0 */ +#define _STREAM2MMIO_ACK_TOKEN_WIDTH (_STREAM2MMIO_ACK_TOKEN_VALID_BIT+1) + +/* commands for packer module */ +#define _STREAM2MMIO_PACK_CMD_STORE_WORDS 0 +#define _STREAM2MMIO_PACK_CMD_STORE_LONG_PACKET 1 +#define _STREAM2MMIO_PACK_CMD_STORE_SHORT_PACKET 2 + + + + +#endif /* _STREAM2MMIO_DEFS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/streaming_to_mipi_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/streaming_to_mipi_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..60143b8743a2d5a4079f557387033e83acf99870 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/streaming_to_mipi_defs.h @@ -0,0 +1,28 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _streaming_to_mipi_defs_h +#define _streaming_to_mipi_defs_h + +#define HIVE_STR_TO_MIPI_VALID_A_BIT 0 +#define HIVE_STR_TO_MIPI_VALID_B_BIT 1 +#define HIVE_STR_TO_MIPI_SOL_BIT 2 +#define HIVE_STR_TO_MIPI_EOL_BIT 3 +#define HIVE_STR_TO_MIPI_SOF_BIT 4 +#define HIVE_STR_TO_MIPI_EOF_BIT 5 +#define HIVE_STR_TO_MIPI_CH_ID_LSB 6 + +#define HIVE_STR_TO_MIPI_DATA_A_LSB (HIVE_STR_TO_MIPI_VALID_B_BIT + 1) + +#endif /* _streaming_to_mipi_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/timed_controller_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/timed_controller_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..d2b8972b0d9ec64ae887e8c6f96d586262737b0f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/timed_controller_defs.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _timed_controller_defs_h +#define _timed_controller_defs_h + +#define _HRT_TIMED_CONTROLLER_CMD_REG_IDX 0 + +#define _HRT_TIMED_CONTROLLER_REG_ALIGN 4 + +#endif /* _timed_controller_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/var.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/var.h new file mode 100644 index 0000000000000000000000000000000000000000..19b19ef484f953867e311a95df2e48c418ffa156 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/var.h @@ -0,0 +1,99 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HRT_VAR_H +#define _HRT_VAR_H + +#include "version.h" +#include "system_api.h" +#include "hive_types.h" + +#define hrt_int_type_of_char char +#define hrt_int_type_of_uchar unsigned char +#define hrt_int_type_of_short short +#define hrt_int_type_of_ushort unsigned short +#define hrt_int_type_of_int int +#define hrt_int_type_of_uint unsigned int +#define hrt_int_type_of_long long +#define hrt_int_type_of_ulong unsigned long +#define hrt_int_type_of_ptr unsigned int + +#define hrt_host_type_of_char char +#define hrt_host_type_of_uchar unsigned char +#define hrt_host_type_of_short short +#define hrt_host_type_of_ushort unsigned short +#define hrt_host_type_of_int int +#define hrt_host_type_of_uint unsigned int +#define hrt_host_type_of_long long +#define hrt_host_type_of_ulong unsigned long +#define hrt_host_type_of_ptr void* + +#define HRT_TYPE_BYTES(cell, type) (HRT_TYPE_BITS(cell, type)/8) +#define HRT_HOST_TYPE(cell_type) HRTCAT(hrt_host_type_of_, cell_type) +#define HRT_INT_TYPE(type) HRTCAT(hrt_int_type_of_, type) + +#ifdef C_RUN + +#ifdef C_RUN_DYNAMIC_LINK_PROGRAMS +extern void *csim_processor_get_crun_symbol(hive_proc_id p, const char *sym); +#define _hrt_cell_get_crun_symbol(cell,sym) csim_processor_get_crun_symbol(cell,HRTSTR(sym)) +#define _hrt_cell_get_crun_indexed_symbol(cell,sym) csim_processor_get_crun_symbol(cell,HRTSTR(sym)) +#else +#define _hrt_cell_get_crun_symbol(cell,sym) (&sym) +#define _hrt_cell_get_crun_indexed_symbol(cell,sym) (sym) +#endif // C_RUN_DYNAMIC_LINK_PROGRAMS + +#define hrt_scalar_store(cell, type, var, data) \ + ((*(HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_symbol(cell,var)) = (data)) +#define hrt_scalar_load(cell, type, var) \ + ((*(HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_symbol(cell,var))) + +#define hrt_indexed_store(cell, type, array, index, data) \ + ((((HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_indexed_symbol(cell,array))[index]) = (data)) +#define hrt_indexed_load(cell, type, array, index) \ + (((HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_indexed_symbol(cell,array))[index]) + +#else /* C_RUN */ + +#define hrt_scalar_store(cell, type, var, data) \ + HRTCAT(hrt_mem_store_,HRT_TYPE_BITS(cell, type))(\ + cell, \ + HRTCAT(HIVE_MEM_,var), \ + HRTCAT(HIVE_ADDR_,var), \ + (HRT_INT_TYPE(type))(data)) + +#define hrt_scalar_load(cell, type, var) \ + (HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_,HRT_PROC_TYPE(cell),_,type) ( \ + cell, \ + HRTCAT(HIVE_MEM_,var), \ + HRTCAT(HIVE_ADDR_,var))) + +#define hrt_indexed_store(cell, type, array, index, data) \ + HRTCAT(hrt_mem_store_,HRT_TYPE_BITS(cell, type))(\ + cell, \ + HRTCAT(HIVE_MEM_,array), \ + (HRTCAT(HIVE_ADDR_,array))+((index)*HRT_TYPE_BYTES(cell, type)), \ + (HRT_INT_TYPE(type))(data)) + +#define hrt_indexed_load(cell, type, array, index) \ + (HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_,HRT_PROC_TYPE(cell),_,type) ( \ + cell, \ + HRTCAT(HIVE_MEM_,array), \ + (HRTCAT(HIVE_ADDR_,array))+((index)*HRT_TYPE_BYTES(cell, type)))) + +#endif /* C_RUN */ + +#endif /* _HRT_VAR_H */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/version.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/version.h new file mode 100644 index 0000000000000000000000000000000000000000..bbc4948baea9b913b590d8992a2d50358503c5f4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/hrt/version.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef HRT_VERSION_H +#define HRT_VERSION_H +#define HRT_VERSION_MAJOR 1 +#define HRT_VERSION_MINOR 4 +#define HRT_VERSION 1_4 +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/ibuf_ctrl_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/ibuf_ctrl_global.h new file mode 100644 index 0000000000000000000000000000000000000000..edb23252c48ea61eb53a5d9319365fe6bc0ac067 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/ibuf_ctrl_global.h @@ -0,0 +1,80 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IBUF_CTRL_GLOBAL_H_INCLUDED__ +#define __IBUF_CTRL_GLOBAL_H_INCLUDED__ + +#include + +#include /* _IBUF_CNTRL_RECALC_WORDS_STATUS, + * _IBUF_CNTRL_ARBITERS_STATUS, + * _IBUF_CNTRL_PROC_REG_ALIGN, + * etc. + */ + +/* Definition of contents of main controller state register is lacking + * in ibuf_cntrl_defs.h, so define these here: + */ +#define _IBUF_CNTRL_MAIN_CNTRL_FSM_MASK 0xf +#define _IBUF_CNTRL_MAIN_CNTRL_FSM_NEXT_COMMAND_CHECK 0x9 +#define _IBUF_CNTRL_MAIN_CNTRL_MEM_INP_BUF_ALLOC (1 << 8) +#define _IBUF_CNTRL_DMA_SYNC_WAIT_FOR_SYNC 1 +#define _IBUF_CNTRL_DMA_SYNC_FSM_WAIT_FOR_ACK (0x3 << 1) + +typedef struct ib_buffer_s ib_buffer_t; +struct ib_buffer_s { + uint32_t start_addr; /* start address of the buffer in the + * "input-buffer hardware block" + */ + + uint32_t stride; /* stride per buffer line (in bytes) */ + uint32_t lines; /* lines in the buffer */ +}; + +typedef struct ibuf_ctrl_cfg_s ibuf_ctrl_cfg_t; +struct ibuf_ctrl_cfg_s { + + bool online; + + struct { + /* DMA configuration */ + uint32_t channel; + uint32_t cmd; /* must be _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND */ + + /* DMA reconfiguration */ + uint32_t shift_returned_items; + uint32_t elems_per_word_in_ibuf; + uint32_t elems_per_word_in_dest; + } dma_cfg; + + ib_buffer_t ib_buffer; + + struct { + uint32_t stride; + uint32_t start_addr; + uint32_t lines; + } dest_buf_cfg; + + uint32_t items_per_store; + uint32_t stores_per_frame; + + struct { + uint32_t sync_cmd; /* must be _STREAM2MMIO_CMD_TOKEN_SYNC_FRAME */ + uint32_t store_cmd; /* must be _STREAM2MMIO_CMD_TOKEN_STORE_PACKETS */ + } stream2mmio_cfg; +}; + +extern const uint32_t N_IBUF_CTRL_PROCS[N_IBUF_CTRL_ID]; + +#endif /* __IBUF_CTRL_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/input_system_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/input_system_global.h new file mode 100644 index 0000000000000000000000000000000000000000..25e3f04f374baabcb91cc7c23777fa1de3277fac --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/input_system_global.h @@ -0,0 +1,206 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_SYSTEM_GLOBAL_H_INCLUDED__ +#define __INPUT_SYSTEM_GLOBAL_H_INCLUDED__ + +#define IS_INPUT_SYSTEM_VERSION_VERSION_2401 + +/* CSI reveiver has 3 ports. */ +#define N_CSI_PORTS (3) + +#include "isys_dma.h" /* isys2401_dma_channel, + * isys2401_dma_cfg_t + */ + +#include "ibuf_ctrl.h" /* ibuf_cfg_t, + * ibuf_ctrl_cfg_t + */ + +#include "isys_stream2mmio.h" /* stream2mmio_cfg_t */ + +#include "csi_rx.h" /* csi_rx_frontend_cfg_t, + * csi_rx_backend_cfg_t, + * csi_rx_backend_lut_entry_t + */ +#include "pixelgen.h" + + +#define INPUT_SYSTEM_N_STREAM_ID 6 /* maximum number of simultaneous + virtual channels supported*/ + +typedef enum { + INPUT_SYSTEM_ERR_NO_ERROR = 0, + INPUT_SYSTEM_ERR_CREATE_CHANNEL_FAIL, + INPUT_SYSTEM_ERR_CONFIGURE_CHANNEL_FAIL, + INPUT_SYSTEM_ERR_OPEN_CHANNEL_FAIL, + INPUT_SYSTEM_ERR_TRANSFER_FAIL, + INPUT_SYSTEM_ERR_CREATE_INPUT_PORT_FAIL, + INPUT_SYSTEM_ERR_CONFIGURE_INPUT_PORT_FAIL, + INPUT_SYSTEM_ERR_OPEN_INPUT_PORT_FAIL, + N_INPUT_SYSTEM_ERR +} input_system_err_t; + +typedef enum { + INPUT_SYSTEM_SOURCE_TYPE_UNDEFINED = 0, + INPUT_SYSTEM_SOURCE_TYPE_SENSOR, + INPUT_SYSTEM_SOURCE_TYPE_TPG, + INPUT_SYSTEM_SOURCE_TYPE_PRBS, + N_INPUT_SYSTEM_SOURCE_TYPE +} input_system_source_type_t; + +typedef enum { + INPUT_SYSTEM_POLL_ON_WAIT_FOR_FRAME, + INPUT_SYSTEM_POLL_ON_CAPTURE_REQUEST, +} input_system_polling_mode_t; + +typedef struct input_system_channel_s input_system_channel_t; +struct input_system_channel_s { + stream2mmio_ID_t stream2mmio_id; + stream2mmio_sid_ID_t stream2mmio_sid_id; + + ibuf_ctrl_ID_t ibuf_ctrl_id; + ib_buffer_t ib_buffer; + + isys2401_dma_ID_t dma_id; + isys2401_dma_channel dma_channel; +}; + +typedef struct input_system_channel_cfg_s input_system_channel_cfg_t; +struct input_system_channel_cfg_s { + stream2mmio_cfg_t stream2mmio_cfg; + ibuf_ctrl_cfg_t ibuf_ctrl_cfg; + isys2401_dma_cfg_t dma_cfg; + isys2401_dma_port_cfg_t dma_src_port_cfg; + isys2401_dma_port_cfg_t dma_dest_port_cfg; +}; + +typedef struct input_system_input_port_s input_system_input_port_t; +struct input_system_input_port_s { + input_system_source_type_t source_type; + + struct { + csi_rx_frontend_ID_t frontend_id; + csi_rx_backend_ID_t backend_id; + csi_mipi_packet_type_t packet_type; + csi_rx_backend_lut_entry_t backend_lut_entry; + } csi_rx; + + struct { + csi_mipi_packet_type_t packet_type; + csi_rx_backend_lut_entry_t backend_lut_entry; + } metadata; + + struct { + pixelgen_ID_t pixelgen_id; + } pixelgen; +}; + +typedef struct input_system_input_port_cfg_s input_system_input_port_cfg_t; +struct input_system_input_port_cfg_s { + struct { + csi_rx_frontend_cfg_t frontend_cfg; + csi_rx_backend_cfg_t backend_cfg; + csi_rx_backend_cfg_t md_backend_cfg; + } csi_rx_cfg; + + struct { + pixelgen_tpg_cfg_t tpg_cfg; + pixelgen_prbs_cfg_t prbs_cfg; + } pixelgen_cfg; +}; + +typedef struct input_system_cfg_s input_system_cfg_t; +struct input_system_cfg_s { + input_system_input_port_ID_t input_port_id; + + input_system_source_type_t mode; +#ifdef ISP2401 + input_system_polling_mode_t polling_mode; +#endif + + bool online; + bool raw_packed; + int8_t linked_isys_stream_id; + + struct { + bool comp_enable; + int32_t active_lanes; + int32_t fmt_type; + int32_t ch_id; + int32_t comp_predictor; + int32_t comp_scheme; + } csi_port_attr; + + pixelgen_tpg_cfg_t tpg_port_attr; + + pixelgen_prbs_cfg_t prbs_port_attr; + + struct { + int32_t align_req_in_bytes; + int32_t bits_per_pixel; + int32_t pixels_per_line; + int32_t lines_per_frame; + } input_port_resolution; + + struct { + int32_t left_padding; + int32_t max_isp_input_width; + } output_port_attr; + + struct { + bool enable; + int32_t fmt_type; + int32_t align_req_in_bytes; + int32_t bits_per_pixel; + int32_t pixels_per_line; + int32_t lines_per_frame; + } metadata; +}; + +typedef struct virtual_input_system_stream_s virtual_input_system_stream_t; +struct virtual_input_system_stream_s { + uint32_t id; /*Used when multiple MIPI data types and/or virtual channels are used. + Must be unique within one CSI RX + and lower than SH_CSS_MAX_ISYS_CHANNEL_NODES */ + uint8_t enable_metadata; + input_system_input_port_t input_port; + input_system_channel_t channel; + input_system_channel_t md_channel; /* metadata channel */ + uint8_t online; + int8_t linked_isys_stream_id; + uint8_t valid; +#ifdef ISP2401 + input_system_polling_mode_t polling_mode; + int32_t subscr_index; +#endif +}; + +typedef struct virtual_input_system_stream_cfg_s virtual_input_system_stream_cfg_t; +struct virtual_input_system_stream_cfg_s { + uint8_t enable_metadata; + input_system_input_port_cfg_t input_port_cfg; + input_system_channel_cfg_t channel_cfg; + input_system_channel_cfg_t md_channel_cfg; + uint8_t valid; +}; + +#define ISP_INPUT_BUF_START_ADDR 0 +#define NUM_OF_INPUT_BUF 2 +#define NUM_OF_LINES_PER_BUF 2 +#define LINES_OF_ISP_INPUT_BUF (NUM_OF_INPUT_BUF * NUM_OF_LINES_PER_BUF) +#define ISP_INPUT_BUF_STRIDE SH_CSS_MAX_SENSOR_WIDTH + + +#endif /* __INPUT_SYSTEM_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_dma_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_dma_global.h new file mode 100644 index 0000000000000000000000000000000000000000..e7a734a9fc43cc42d13f35d135c100693a19e532 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_dma_global.h @@ -0,0 +1,87 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_DMA_GLOBAL_H_INCLUDED__ +#define __ISYS_DMA_GLOBAL_H_INCLUDED__ + +#include + +#define HIVE_ISYS2401_DMA_IBUF_DDR_CONN 0 +#define HIVE_ISYS2401_DMA_IBUF_VMEM_CONN 1 +#define _DMA_V2_ZERO_EXTEND 0 +#define _DMA_V2_SIGN_EXTEND 1 + +#define _DMA_ZERO_EXTEND _DMA_V2_ZERO_EXTEND +#define _DMA_SIGN_EXTEND _DMA_V2_SIGN_EXTEND + +/******************************************************** + * + * DMA Port. + * + * The DMA port definition for the input system + * 2401 DMA is the duplication of the DMA port + * definition for the CSS system DMA. It is duplicated + * here just as the temporal step before the device libary + * is available. The device libary is suppose to provide + * the capability of reusing the control interface of the + * same device prototypes. The refactor team will work on + * this, right? + * + ********************************************************/ +typedef struct isys2401_dma_port_cfg_s isys2401_dma_port_cfg_t; +struct isys2401_dma_port_cfg_s { + uint32_t stride; + uint32_t elements; + uint32_t cropping; + uint32_t width; + }; +/** end of DMA Port */ + +/************************************************ + * + * DMA Device. + * + * The DMA device definition for the input system + * 2401 DMA is the duplicattion of the DMA device + * definition for the CSS system DMA. It is duplicated + * here just as the temporal step before the device libary + * is available. The device libary is suppose to provide + * the capability of reusing the control interface of the + * same device prototypes. The refactor team will work on + * this, right? + * + ************************************************/ +typedef enum { + isys2401_dma_ibuf_to_ddr_connection = HIVE_ISYS2401_DMA_IBUF_DDR_CONN, + isys2401_dma_ibuf_to_vmem_connection = HIVE_ISYS2401_DMA_IBUF_VMEM_CONN +} isys2401_dma_connection; + +typedef enum { + isys2401_dma_zero_extension = _DMA_ZERO_EXTEND, + isys2401_dma_sign_extension = _DMA_SIGN_EXTEND +} isys2401_dma_extension; + +typedef struct isys2401_dma_cfg_s isys2401_dma_cfg_t; +struct isys2401_dma_cfg_s { + isys2401_dma_channel channel; + isys2401_dma_connection connection; + isys2401_dma_extension extension; + uint32_t height; +}; +/** end of DMA Device */ + +/* isys2401_dma_channel limits per DMA ID */ +extern const isys2401_dma_channel N_ISYS2401_DMA_CHANNEL_PROCS[N_ISYS2401_DMA_ID]; + +#endif /* __ISYS_DMA_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_irq_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_irq_global.h new file mode 100644 index 0000000000000000000000000000000000000000..41d051db39876049d51ff4aaa0e4514b100f620a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_irq_global.h @@ -0,0 +1,35 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_IRQ_GLOBAL_H__ +#define __ISYS_IRQ_GLOBAL_H__ + +#if defined(USE_INPUT_SYSTEM_VERSION_2401) + +/* Register offset/index from base location */ +#define ISYS_IRQ_EDGE_REG_IDX (0) +#define ISYS_IRQ_MASK_REG_IDX (ISYS_IRQ_EDGE_REG_IDX + 1) +#define ISYS_IRQ_STATUS_REG_IDX (ISYS_IRQ_EDGE_REG_IDX + 2) +#define ISYS_IRQ_CLEAR_REG_IDX (ISYS_IRQ_EDGE_REG_IDX + 3) +#define ISYS_IRQ_ENABLE_REG_IDX (ISYS_IRQ_EDGE_REG_IDX + 4) +#define ISYS_IRQ_LEVEL_NO_REG_IDX (ISYS_IRQ_EDGE_REG_IDX + 5) + +/* Register values */ +#define ISYS_IRQ_MASK_REG_VALUE (0xFFFF) +#define ISYS_IRQ_CLEAR_REG_VALUE (0xFFFF) +#define ISYS_IRQ_ENABLE_REG_VALUE (0xFFFF) + +#endif /* defined(USE_INPUT_SYSTEM_VERSION_2401) */ + +#endif /* __ISYS_IRQ_GLOBAL_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_stream2mmio_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_stream2mmio_global.h new file mode 100644 index 0000000000000000000000000000000000000000..649f44fd240862ebc77f651803d99450dee33c40 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/isys_stream2mmio_global.h @@ -0,0 +1,39 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_STREAM2MMIO_GLOBAL_H_INCLUDED__ +#define __ISYS_STREAM2MMIO_GLOBAL_H_INCLUDED__ + +#include + +typedef struct stream2mmio_cfg_s stream2mmio_cfg_t; +struct stream2mmio_cfg_s { + uint32_t bits_per_pixel; + uint32_t enable_blocking; +}; + +/* Stream2MMIO limits per ID*/ +/* + * Stream2MMIO 0 has 8 SIDs that are indexed by + * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID7_ID]. + * + * Stream2MMIO 1 has 4 SIDs that are indexed by + * [STREAM2MMIO_SID0_ID...TREAM2MMIO_SID3_ID]. + * + * Stream2MMIO 2 has 4 SIDs that are indexed by + * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID3_ID]. + */ +extern const stream2mmio_sid_ID_t N_STREAM2MMIO_SID_PROCS[N_STREAM2MMIO_ID]; + +#endif /* __ISYS_STREAM2MMIO_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/pixelgen_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/pixelgen_global.h new file mode 100644 index 0000000000000000000000000000000000000000..216813e42a0aa5bdc9b92435462f9dccb3f69c3d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/pixelgen_global.h @@ -0,0 +1,91 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __PIXELGEN_GLOBAL_H_INCLUDED__ +#define __PIXELGEN_GLOBAL_H_INCLUDED__ + +#include + +/** + * Pixel-generator. ("pixelgen_global.h") + */ +/* + * Duplicates "sync_generator_cfg_t" in "input_system_global.h". + */ +typedef struct sync_generator_cfg_s sync_generator_cfg_t; +struct sync_generator_cfg_s { + uint32_t hblank_cycles; + uint32_t vblank_cycles; + uint32_t pixels_per_clock; + uint32_t nr_of_frames; + uint32_t pixels_per_line; + uint32_t lines_per_frame; +}; + +typedef enum { + PIXELGEN_TPG_MODE_RAMP = 0, + PIXELGEN_TPG_MODE_CHBO, + PIXELGEN_TPG_MODE_MONO, + N_PIXELGEN_TPG_MODE +} pixelgen_tpg_mode_t; + +/* + * "pixelgen_tpg_cfg_t" duplicates parts of + * "tpg_cfg_t" in "input_system_global.h". + */ +typedef struct pixelgen_tpg_cfg_s pixelgen_tpg_cfg_t; +struct pixelgen_tpg_cfg_s { + pixelgen_tpg_mode_t mode; /* CHBO, MONO */ + + struct { + /* be used by CHBO and MON */ + uint32_t R1; + uint32_t G1; + uint32_t B1; + + /* be used by CHBO only */ + uint32_t R2; + uint32_t G2; + uint32_t B2; + } color_cfg; + + struct { + uint32_t h_mask; /* horizontal mask */ + uint32_t v_mask; /* vertical mask */ + uint32_t hv_mask; /* horizontal+vertical mask? */ + } mask_cfg; + + struct { + int32_t h_delta; /* horizontal delta? */ + int32_t v_delta; /* vertical delta? */ + } delta_cfg; + + sync_generator_cfg_t sync_gen_cfg; +}; + +/* + * "pixelgen_prbs_cfg_t" duplicates parts of + * prbs_cfg_t" in "input_system_global.h". + */ +typedef struct pixelgen_prbs_cfg_s pixelgen_prbs_cfg_t; +struct pixelgen_prbs_cfg_s { + int32_t seed0; + int32_t seed1; + + sync_generator_cfg_t sync_gen_cfg; +}; + +/** end of Pixel-generator: TPG. ("pixelgen_global.h") */ +#endif /* __PIXELGEN_GLOBAL_H_INCLUDED__ */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/spmem_dump.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/spmem_dump.c new file mode 100644 index 0000000000000000000000000000000000000000..d733a3503a209996bf2a864c6576f1b5a0f28ae2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/spmem_dump.c @@ -0,0 +1,3686 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _sp_map_h_ +#define _sp_map_h_ + + +#ifndef _hrt_dummy_use_blob_sp +#define _hrt_dummy_use_blob_sp() +#endif + +#define _hrt_cell_load_program_sp(proc) _hrt_cell_load_program_embedded(proc, sp) + +#ifndef ISP2401 +/* function longjmp: 680D */ +#else +/* function longjmp: 6A0B */ +#endif + +#ifndef ISP2401 +/* function tmpmem_init_dmem: 6558 */ +#else +/* function tmpmem_init_dmem: 671E */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_set_addr_B: 3C50 */ +#else +/* function ia_css_dmaproxy_sp_set_addr_B: 3DC5 */ + +/* function ia_css_pipe_data_init_tagger_resources: AC7 */ +#endif + +/* function debug_buffer_set_ddr_addr: DD */ + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_vbuf_mipi +#define HIVE_MEM_vbuf_mipi scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_vbuf_mipi 0x7398 +#else +#define HIVE_ADDR_vbuf_mipi 0x7444 +#endif +#define HIVE_SIZE_vbuf_mipi 12 +#else +#endif +#endif +#define HIVE_MEM_sp_vbuf_mipi scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_vbuf_mipi 0x7398 +#else +#define HIVE_ADDR_sp_vbuf_mipi 0x7444 +#endif +#define HIVE_SIZE_sp_vbuf_mipi 12 + +#ifndef ISP2401 +/* function ia_css_event_sp_decode: 3E41 */ +#else +/* function ia_css_event_sp_decode: 3FB6 */ +#endif + +#ifndef ISP2401 +/* function ia_css_queue_get_size: 51BF */ +#else +/* function ia_css_queue_get_size: 53C8 */ +#endif + +#ifndef ISP2401 +/* function ia_css_queue_load: 5800 */ +#else +/* function ia_css_queue_load: 59DF */ +#endif + +#ifndef ISP2401 +/* function setjmp: 6816 */ +#else +/* function setjmp: 6A14 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_sfi_get_current_frame: 27BF */ +#else +/* function ia_css_pipeline_sp_sfi_get_current_frame: 2790 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_sp2host_isys_event_queue +#define HIVE_MEM_sem_for_sp2host_isys_event_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_sp2host_isys_event_queue 0x5760 +#else +#define HIVE_ADDR_sem_for_sp2host_isys_event_queue 0x57FC +#endif +#define HIVE_SIZE_sem_for_sp2host_isys_event_queue 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_sp2host_isys_event_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_sp2host_isys_event_queue 0x5760 +#else +#define HIVE_ADDR_sp_sem_for_sp2host_isys_event_queue 0x57FC +#endif +#define HIVE_SIZE_sp_sem_for_sp2host_isys_event_queue 20 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_wait_for_ack: 6DA9 */ +#else +/* function ia_css_dmaproxy_sp_wait_for_ack: 6FF7 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_rawcopy_func: 596B */ +#else +/* function ia_css_sp_rawcopy_func: 5B4A */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_pop_marked: 3339 */ +#else +/* function ia_css_tagger_buf_sp_pop_marked: 345C */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_N_CSI_RX_BE_SID_WIDTH +#define HIVE_MEM_N_CSI_RX_BE_SID_WIDTH scalar_processor_2400_dmem +#define HIVE_ADDR_N_CSI_RX_BE_SID_WIDTH 0x1D0 +#define HIVE_SIZE_N_CSI_RX_BE_SID_WIDTH 12 +#else +#endif +#endif +#define HIVE_MEM_sp_N_CSI_RX_BE_SID_WIDTH scalar_processor_2400_dmem +#define HIVE_ADDR_sp_N_CSI_RX_BE_SID_WIDTH 0x1D0 +#define HIVE_SIZE_sp_N_CSI_RX_BE_SID_WIDTH 12 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isp_stage +#define HIVE_MEM_isp_stage scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isp_stage 0x6C98 +#else +#define HIVE_ADDR_isp_stage 0x6D48 +#endif +#define HIVE_SIZE_isp_stage 832 +#else +#endif +#endif +#define HIVE_MEM_sp_isp_stage scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_stage 0x6C98 +#else +#define HIVE_ADDR_sp_isp_stage 0x6D48 +#endif +#define HIVE_SIZE_sp_isp_stage 832 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_vbuf_raw +#define HIVE_MEM_vbuf_raw scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_vbuf_raw 0x37C +#else +#define HIVE_ADDR_vbuf_raw 0x394 +#endif +#define HIVE_SIZE_vbuf_raw 4 +#else +#endif +#endif +#define HIVE_MEM_sp_vbuf_raw scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_vbuf_raw 0x37C +#else +#define HIVE_ADDR_sp_vbuf_raw 0x394 +#endif +#define HIVE_SIZE_sp_vbuf_raw 4 + +#ifndef ISP2401 +/* function ia_css_sp_bin_copy_func: 594C */ +#else +/* function ia_css_sp_bin_copy_func: 5B2B */ +#endif + +#ifndef ISP2401 +/* function ia_css_queue_item_store: 554E */ +#else +/* function ia_css_queue_item_store: 572D */ +#endif + +#ifndef ISP2401 +/* function input_system_reset: 1286 */ +#else +/* function input_system_reset: 1201 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_metadata_bufs +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_metadata_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_metadata_bufs 0x5B38 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_metadata_bufs 0x5BE4 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_metadata_bufs 20 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_metadata_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_metadata_bufs 0x5B38 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_metadata_bufs 0x5BE4 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_metadata_bufs 20 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_buffer_bufs +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_buffer_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_buffer_bufs 0x5B4C +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_buffer_bufs 0x5BF8 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_buffer_bufs 160 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_buffer_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_buffer_bufs 0x5B4C +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_buffer_bufs 0x5BF8 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_buffer_bufs 160 + +/* function sp_start_isp: 39C */ + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_binary_group +#define HIVE_MEM_sp_binary_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_binary_group 0x7088 +#else +#define HIVE_ADDR_sp_binary_group 0x7138 +#endif +#define HIVE_SIZE_sp_binary_group 32 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_binary_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_binary_group 0x7088 +#else +#define HIVE_ADDR_sp_sp_binary_group 0x7138 +#endif +#define HIVE_SIZE_sp_sp_binary_group 32 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_sw_state +#define HIVE_MEM_sp_sw_state scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sw_state 0x7344 +#else +#define HIVE_ADDR_sp_sw_state 0x73F0 +#endif +#define HIVE_SIZE_sp_sw_state 4 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_sw_state scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_sw_state 0x7344 +#else +#define HIVE_ADDR_sp_sp_sw_state 0x73F0 +#endif +#define HIVE_SIZE_sp_sp_sw_state 4 + +#ifndef ISP2401 +/* function ia_css_thread_sp_main: 13F7 */ +#else +/* function ia_css_thread_sp_main: 136D */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_init_internal_buffers: 4047 */ +#else +/* function ia_css_ispctrl_sp_init_internal_buffers: 41F7 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp2host_psys_event_queue_handle +#define HIVE_MEM_sp2host_psys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp2host_psys_event_queue_handle 0x5BEC +#else +#define HIVE_ADDR_sp2host_psys_event_queue_handle 0x5C98 +#endif +#define HIVE_SIZE_sp2host_psys_event_queue_handle 12 +#else +#endif +#endif +#define HIVE_MEM_sp_sp2host_psys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp2host_psys_event_queue_handle 0x5BEC +#else +#define HIVE_ADDR_sp_sp2host_psys_event_queue_handle 0x5C98 +#endif +#define HIVE_SIZE_sp_sp2host_psys_event_queue_handle 12 + +#ifndef ISP2401 +/* function pixelgen_unit_test: E68 */ +#else +/* function pixelgen_unit_test: E62 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_sp2host_psys_event_queue +#define HIVE_MEM_sem_for_sp2host_psys_event_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_sp2host_psys_event_queue 0x5774 +#else +#define HIVE_ADDR_sem_for_sp2host_psys_event_queue 0x5810 +#endif +#define HIVE_SIZE_sem_for_sp2host_psys_event_queue 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_sp2host_psys_event_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_sp2host_psys_event_queue 0x5774 +#else +#define HIVE_ADDR_sp_sem_for_sp2host_psys_event_queue 0x5810 +#endif +#define HIVE_SIZE_sp_sem_for_sp2host_psys_event_queue 20 + +#ifndef ISP2401 +/* function ia_css_tagger_sp_propagate_frame: 2D52 */ + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_stop_copy_preview +#define HIVE_MEM_sp_stop_copy_preview scalar_processor_2400_dmem +#define HIVE_ADDR_sp_stop_copy_preview 0x7328 +#define HIVE_SIZE_sp_stop_copy_preview 4 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_stop_copy_preview scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_stop_copy_preview 0x7328 +#define HIVE_SIZE_sp_sp_stop_copy_preview 4 +#else +/* function ia_css_tagger_sp_propagate_frame: 2D23 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_vbuf_handles +#define HIVE_MEM_vbuf_handles scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_vbuf_handles 0x73A4 +#else +#define HIVE_ADDR_vbuf_handles 0x7450 +#endif +#define HIVE_SIZE_vbuf_handles 960 +#else +#endif +#endif +#define HIVE_MEM_sp_vbuf_handles scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_vbuf_handles 0x73A4 +#else +#define HIVE_ADDR_sp_vbuf_handles 0x7450 +#endif +#define HIVE_SIZE_sp_vbuf_handles 960 + +#ifndef ISP2401 +/* function ia_css_queue_store: 56B4 */ + +/* function ia_css_sp_flash_register: 356E */ +#else +/* function ia_css_queue_store: 5893 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_rawcopy_dummy_function: 5CF7 */ +#else +/* function ia_css_sp_flash_register: 3691 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_init: 201C */ +#else +/* function ia_css_pipeline_sp_init: 1FD7 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_configure: 2C42 */ +#else +/* function ia_css_tagger_sp_configure: 2C13 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_end_binary: 3E8A */ +#else +/* function ia_css_ispctrl_sp_end_binary: 3FFF */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs +#define HIVE_MEM_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x5BF8 +#else +#define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x5CA4 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 20 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x5BF8 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x5CA4 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 20 + +#ifndef ISP2401 +/* function pixelgen_tpg_run: F1E */ +#else +/* function pixelgen_tpg_run: F18 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_event_is_pending_mask +#define HIVE_MEM_event_is_pending_mask scalar_processor_2400_dmem +#define HIVE_ADDR_event_is_pending_mask 0x5C +#define HIVE_SIZE_event_is_pending_mask 44 +#else +#endif +#endif +#define HIVE_MEM_sp_event_is_pending_mask scalar_processor_2400_dmem +#define HIVE_ADDR_sp_event_is_pending_mask 0x5C +#define HIVE_SIZE_sp_event_is_pending_mask 44 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cb_elems_frame +#define HIVE_MEM_sp_all_cb_elems_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cb_elems_frame 0x5788 +#else +#define HIVE_ADDR_sp_all_cb_elems_frame 0x5824 +#endif +#define HIVE_SIZE_sp_all_cb_elems_frame 16 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cb_elems_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cb_elems_frame 0x5788 +#else +#define HIVE_ADDR_sp_sp_all_cb_elems_frame 0x5824 +#endif +#define HIVE_SIZE_sp_sp_all_cb_elems_frame 16 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp2host_isys_event_queue_handle +#define HIVE_MEM_sp2host_isys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp2host_isys_event_queue_handle 0x5C0C +#else +#define HIVE_ADDR_sp2host_isys_event_queue_handle 0x5CB8 +#endif +#define HIVE_SIZE_sp2host_isys_event_queue_handle 12 +#else +#endif +#endif +#define HIVE_MEM_sp_sp2host_isys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp2host_isys_event_queue_handle 0x5C0C +#else +#define HIVE_ADDR_sp_sp2host_isys_event_queue_handle 0x5CB8 +#endif +#define HIVE_SIZE_sp_sp2host_isys_event_queue_handle 12 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host_sp_com +#define HIVE_MEM_host_sp_com scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host_sp_com 0x3E48 +#else +#define HIVE_ADDR_host_sp_com 0x3E6C +#endif +#define HIVE_SIZE_host_sp_com 220 +#else +#endif +#endif +#define HIVE_MEM_sp_host_sp_com scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host_sp_com 0x3E48 +#else +#define HIVE_ADDR_sp_host_sp_com 0x3E6C +#endif +#define HIVE_SIZE_sp_host_sp_com 220 + +#ifndef ISP2401 +/* function ia_css_queue_get_free_space: 5313 */ +#else +/* function ia_css_queue_get_free_space: 54F2 */ +#endif + +#ifndef ISP2401 +/* function exec_image_pipe: 5E6 */ +#else +/* function exec_image_pipe: 57A */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_init_dmem_data +#define HIVE_MEM_sp_init_dmem_data scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_init_dmem_data 0x7348 +#else +#define HIVE_ADDR_sp_init_dmem_data 0x73F4 +#endif +#define HIVE_SIZE_sp_init_dmem_data 24 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_init_dmem_data scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_init_dmem_data 0x7348 +#else +#define HIVE_ADDR_sp_sp_init_dmem_data 0x73F4 +#endif +#define HIVE_SIZE_sp_sp_init_dmem_data 24 + +#ifndef ISP2401 +/* function ia_css_sp_metadata_start: 5DD1 */ +#else +/* function ia_css_sp_metadata_start: 5EB3 */ +#endif + +#ifndef ISP2401 +/* function ia_css_bufq_sp_init_buffer_queues: 35BF */ +#else +/* function ia_css_bufq_sp_init_buffer_queues: 36E2 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_stop: 1FFF */ +#else +/* function ia_css_pipeline_sp_stop: 1FBA */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_connect_pipes: 312C */ +#else +/* function ia_css_tagger_sp_connect_pipes: 30FD */ +#endif + +#ifndef ISP2401 +/* function sp_isys_copy_wait: 644 */ +#else +/* function sp_isys_copy_wait: 5D8 */ +#endif + +/* function is_isp_debug_buffer_full: 337 */ + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_configure_channel_from_info: 3BD3 */ +#else +/* function ia_css_dmaproxy_sp_configure_channel_from_info: 3D35 */ +#endif + +#ifndef ISP2401 +/* function encode_and_post_timer_event: AA8 */ +#else +/* function encode_and_post_timer_event: A3C */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_input_system_bz2788_active +#define HIVE_MEM_input_system_bz2788_active scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_input_system_bz2788_active 0x250C +#else +#define HIVE_ADDR_input_system_bz2788_active 0x2524 +#endif +#define HIVE_SIZE_input_system_bz2788_active 4 +#else +#endif +#endif +#define HIVE_MEM_sp_input_system_bz2788_active scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_input_system_bz2788_active 0x250C +#else +#define HIVE_ADDR_sp_input_system_bz2788_active 0x2524 +#endif +#define HIVE_SIZE_sp_input_system_bz2788_active 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_N_IBUF_CTRL_PROCS +#define HIVE_MEM_N_IBUF_CTRL_PROCS scalar_processor_2400_dmem +#define HIVE_ADDR_N_IBUF_CTRL_PROCS 0x1FC +#define HIVE_SIZE_N_IBUF_CTRL_PROCS 12 +#else +#endif +#endif +#define HIVE_MEM_sp_N_IBUF_CTRL_PROCS scalar_processor_2400_dmem +#define HIVE_ADDR_sp_N_IBUF_CTRL_PROCS 0x1FC +#define HIVE_SIZE_sp_N_IBUF_CTRL_PROCS 12 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_per_frame_data +#define HIVE_MEM_sp_per_frame_data scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_per_frame_data 0x3F24 +#else +#define HIVE_ADDR_sp_per_frame_data 0x3F48 +#endif +#define HIVE_SIZE_sp_per_frame_data 4 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_per_frame_data scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_per_frame_data 0x3F24 +#else +#define HIVE_ADDR_sp_sp_per_frame_data 0x3F48 +#endif +#define HIVE_SIZE_sp_sp_per_frame_data 4 + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_vbuf_dequeue: 62AC */ +#else +/* function ia_css_rmgr_sp_vbuf_dequeue: 6472 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host2sp_psys_event_queue_handle +#define HIVE_MEM_host2sp_psys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host2sp_psys_event_queue_handle 0x5C18 +#else +#define HIVE_ADDR_host2sp_psys_event_queue_handle 0x5CC4 +#endif +#define HIVE_SIZE_host2sp_psys_event_queue_handle 12 +#else +#endif +#endif +#define HIVE_MEM_sp_host2sp_psys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host2sp_psys_event_queue_handle 0x5C18 +#else +#define HIVE_ADDR_sp_host2sp_psys_event_queue_handle 0x5CC4 +#endif +#define HIVE_SIZE_sp_host2sp_psys_event_queue_handle 12 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_xmem_bin_addr +#define HIVE_MEM_xmem_bin_addr scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_xmem_bin_addr 0x3F28 +#else +#define HIVE_ADDR_xmem_bin_addr 0x3F4C +#endif +#define HIVE_SIZE_xmem_bin_addr 4 +#else +#endif +#endif +#define HIVE_MEM_sp_xmem_bin_addr scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_xmem_bin_addr 0x3F28 +#else +#define HIVE_ADDR_sp_xmem_bin_addr 0x3F4C +#endif +#define HIVE_SIZE_sp_xmem_bin_addr 4 + +#ifndef ISP2401 +/* function tmr_clock_init: 16F9 */ +#else +/* function tmr_clock_init: 166F */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_run: 1ABF */ +#else +/* function ia_css_pipeline_sp_run: 1A61 */ +#endif + +#ifndef ISP2401 +/* function memcpy: 68B6 */ +#else +/* function memcpy: 6AB4 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_N_ISYS2401_DMA_CHANNEL_PROCS +#define HIVE_MEM_N_ISYS2401_DMA_CHANNEL_PROCS scalar_processor_2400_dmem +#define HIVE_ADDR_N_ISYS2401_DMA_CHANNEL_PROCS 0x214 +#define HIVE_SIZE_N_ISYS2401_DMA_CHANNEL_PROCS 4 +#else +#endif +#endif +#define HIVE_MEM_sp_N_ISYS2401_DMA_CHANNEL_PROCS scalar_processor_2400_dmem +#define HIVE_ADDR_sp_N_ISYS2401_DMA_CHANNEL_PROCS 0x214 +#define HIVE_SIZE_sp_N_ISYS2401_DMA_CHANNEL_PROCS 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_GP_DEVICE_BASE +#define HIVE_MEM_GP_DEVICE_BASE scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_GP_DEVICE_BASE 0x384 +#else +#define HIVE_ADDR_GP_DEVICE_BASE 0x39C +#endif +#define HIVE_SIZE_GP_DEVICE_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_GP_DEVICE_BASE scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_GP_DEVICE_BASE 0x384 +#else +#define HIVE_ADDR_sp_GP_DEVICE_BASE 0x39C +#endif +#define HIVE_SIZE_sp_GP_DEVICE_BASE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_thread_sp_ready_queue +#define HIVE_MEM_ia_css_thread_sp_ready_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_thread_sp_ready_queue 0x278 +#else +#define HIVE_ADDR_ia_css_thread_sp_ready_queue 0x27C +#endif +#define HIVE_SIZE_ia_css_thread_sp_ready_queue 12 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_thread_sp_ready_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_thread_sp_ready_queue 0x278 +#else +#define HIVE_ADDR_sp_ia_css_thread_sp_ready_queue 0x27C +#endif +#define HIVE_SIZE_sp_ia_css_thread_sp_ready_queue 12 + +#ifndef ISP2401 +/* function stream2mmio_send_command: E0A */ +#else +/* function stream2mmio_send_command: E04 */ +#endif + +#ifndef ISP2401 +/* function ia_css_uds_sp_scale_params: 65BF */ +#else +/* function ia_css_uds_sp_scale_params: 67BD */ +#endif + +#ifndef ISP2401 +/* function ia_css_circbuf_increase_size: 14DC */ +#else +/* function ia_css_circbuf_increase_size: 1452 */ +#endif + +#ifndef ISP2401 +/* function __divu: 6834 */ +#else +/* function __divu: 6A32 */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_get_state: 131F */ +#else +/* function ia_css_thread_sp_get_state: 1295 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_cont_capt_stop +#define HIVE_MEM_sem_for_cont_capt_stop scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_cont_capt_stop 0x5798 +#else +#define HIVE_ADDR_sem_for_cont_capt_stop 0x5834 +#endif +#define HIVE_SIZE_sem_for_cont_capt_stop 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_cont_capt_stop scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_cont_capt_stop 0x5798 +#else +#define HIVE_ADDR_sp_sem_for_cont_capt_stop 0x5834 +#endif +#define HIVE_SIZE_sp_sem_for_cont_capt_stop 20 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_N_SHORT_PACKET_LUT_ENTRIES +#define HIVE_MEM_N_SHORT_PACKET_LUT_ENTRIES scalar_processor_2400_dmem +#define HIVE_ADDR_N_SHORT_PACKET_LUT_ENTRIES 0x1AC +#define HIVE_SIZE_N_SHORT_PACKET_LUT_ENTRIES 12 +#else +#endif +#endif +#define HIVE_MEM_sp_N_SHORT_PACKET_LUT_ENTRIES scalar_processor_2400_dmem +#define HIVE_ADDR_sp_N_SHORT_PACKET_LUT_ENTRIES 0x1AC +#define HIVE_SIZE_sp_N_SHORT_PACKET_LUT_ENTRIES 12 + +#ifndef ISP2401 +/* function thread_fiber_sp_main: 14D5 */ +#else +/* function thread_fiber_sp_main: 144B */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_isp_pipe_thread +#define HIVE_MEM_sp_isp_pipe_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_pipe_thread 0x58DC +#define HIVE_SIZE_sp_isp_pipe_thread 340 +#else +#define HIVE_ADDR_sp_isp_pipe_thread 0x5978 +#define HIVE_SIZE_sp_isp_pipe_thread 360 +#endif +#else +#endif +#endif +#define HIVE_MEM_sp_sp_isp_pipe_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_isp_pipe_thread 0x58DC +#define HIVE_SIZE_sp_sp_isp_pipe_thread 340 +#else +#define HIVE_ADDR_sp_sp_isp_pipe_thread 0x5978 +#define HIVE_SIZE_sp_sp_isp_pipe_thread 360 +#endif + +#ifndef ISP2401 +/* function ia_css_parambuf_sp_handle_parameter_sets: 193F */ +#else +/* function ia_css_parambuf_sp_handle_parameter_sets: 18B5 */ +#endif + +#ifndef ISP2401 +/* function ia_css_spctrl_sp_set_state: 5DED */ +#else +/* function ia_css_spctrl_sp_set_state: 5ECF */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sem_sp_signal: 6A99 */ +#else +/* function ia_css_thread_sem_sp_signal: 6D18 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_IRQ_BASE +#define HIVE_MEM_IRQ_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_IRQ_BASE 0x2C +#define HIVE_SIZE_IRQ_BASE 16 +#else +#endif +#endif +#define HIVE_MEM_sp_IRQ_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_IRQ_BASE 0x2C +#define HIVE_SIZE_sp_IRQ_BASE 16 + +#ifndef ISP2401 +/* function ia_css_virtual_isys_sp_isr_init: 5E8C */ +#else +/* function ia_css_virtual_isys_sp_isr_init: 5F70 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_TIMED_CTRL_BASE +#define HIVE_MEM_TIMED_CTRL_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_TIMED_CTRL_BASE 0x40 +#define HIVE_SIZE_TIMED_CTRL_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_TIMED_CTRL_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_TIMED_CTRL_BASE 0x40 +#define HIVE_SIZE_sp_TIMED_CTRL_BASE 4 + +#ifndef ISP2401 +/* function ia_css_isys_sp_generate_exp_id: 613C */ + +/* function ia_css_rmgr_sp_init: 61A7 */ +#else +/* function ia_css_isys_sp_generate_exp_id: 6302 */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sem_sp_init: 6B6A */ +#else +/* function ia_css_rmgr_sp_init: 636D */ +#endif + +#ifndef ISP2401 +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_is_isp_requested +#define HIVE_MEM_is_isp_requested scalar_processor_2400_dmem +#define HIVE_ADDR_is_isp_requested 0x390 +#define HIVE_SIZE_is_isp_requested 4 +#else +#endif +#endif +#define HIVE_MEM_sp_is_isp_requested scalar_processor_2400_dmem +#define HIVE_ADDR_sp_is_isp_requested 0x390 +#define HIVE_SIZE_sp_is_isp_requested 4 +#else +/* function ia_css_thread_sem_sp_init: 6DE7 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_reading_cb_frame +#define HIVE_MEM_sem_for_reading_cb_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_reading_cb_frame 0x57AC +#else +#define HIVE_ADDR_sem_for_reading_cb_frame 0x5848 +#endif +#define HIVE_SIZE_sem_for_reading_cb_frame 40 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_reading_cb_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_reading_cb_frame 0x57AC +#else +#define HIVE_ADDR_sp_sem_for_reading_cb_frame 0x5848 +#endif +#define HIVE_SIZE_sp_sem_for_reading_cb_frame 40 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_execute: 3B3B */ +#else +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_is_isp_requested +#define HIVE_MEM_is_isp_requested scalar_processor_2400_dmem +#define HIVE_ADDR_is_isp_requested 0x3A8 +#define HIVE_SIZE_is_isp_requested 4 +#else +#endif +#endif +#define HIVE_MEM_sp_is_isp_requested scalar_processor_2400_dmem +#define HIVE_ADDR_sp_is_isp_requested 0x3A8 +#define HIVE_SIZE_sp_is_isp_requested 4 + +/* function ia_css_dmaproxy_sp_execute: 3C9B */ +#endif + +#ifndef ISP2401 +/* function csi_rx_backend_rst: CE6 */ +#else +/* function csi_rx_backend_rst: CE0 */ +#endif + +#ifndef ISP2401 +/* function ia_css_queue_is_empty: 51FA */ +#else +/* function ia_css_queue_is_empty: 7144 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_has_stopped: 1FF5 */ +#else +/* function ia_css_pipeline_sp_has_stopped: 1FB0 */ +#endif + +#ifndef ISP2401 +/* function ia_css_circbuf_extract: 15E0 */ +#else +/* function ia_css_circbuf_extract: 1556 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_is_locked_from_start: 344F */ +#else +/* function ia_css_tagger_buf_sp_is_locked_from_start: 3572 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_current_sp_thread +#define HIVE_MEM_current_sp_thread scalar_processor_2400_dmem +#define HIVE_ADDR_current_sp_thread 0x274 +#define HIVE_SIZE_current_sp_thread 4 +#else +#endif +#endif +#define HIVE_MEM_sp_current_sp_thread scalar_processor_2400_dmem +#define HIVE_ADDR_sp_current_sp_thread 0x274 +#define HIVE_SIZE_sp_current_sp_thread 4 + +#ifndef ISP2401 +/* function ia_css_spctrl_sp_get_spid: 5DF4 */ +#else +/* function ia_css_spctrl_sp_get_spid: 5ED6 */ +#endif + +#ifndef ISP2401 +/* function ia_css_bufq_sp_reset_buffers: 3646 */ +#else +/* function ia_css_bufq_sp_reset_buffers: 3769 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_read_byte_addr: 6DD7 */ +#else +/* function ia_css_dmaproxy_sp_read_byte_addr: 7025 */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_uninit: 61A0 */ +#else +/* function ia_css_rmgr_sp_uninit: 6366 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_threads_stack +#define HIVE_MEM_sp_threads_stack scalar_processor_2400_dmem +#define HIVE_ADDR_sp_threads_stack 0x164 +#define HIVE_SIZE_sp_threads_stack 24 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_threads_stack scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_threads_stack 0x164 +#define HIVE_SIZE_sp_sp_threads_stack 24 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_N_STREAM2MMIO_SID_PROCS +#define HIVE_MEM_N_STREAM2MMIO_SID_PROCS scalar_processor_2400_dmem +#define HIVE_ADDR_N_STREAM2MMIO_SID_PROCS 0x218 +#define HIVE_SIZE_N_STREAM2MMIO_SID_PROCS 12 +#else +#endif +#endif +#define HIVE_MEM_sp_N_STREAM2MMIO_SID_PROCS scalar_processor_2400_dmem +#define HIVE_ADDR_sp_N_STREAM2MMIO_SID_PROCS 0x218 +#define HIVE_SIZE_sp_N_STREAM2MMIO_SID_PROCS 12 + +#ifndef ISP2401 +/* function ia_css_circbuf_peek: 15C2 */ +#else +/* function ia_css_circbuf_peek: 1538 */ +#endif + +#ifndef ISP2401 +/* function ia_css_parambuf_sp_wait_for_in_param: 1708 */ +#else +/* function ia_css_parambuf_sp_wait_for_in_param: 167E */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cb_elems_param +#define HIVE_MEM_sp_all_cb_elems_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cb_elems_param 0x57D4 +#else +#define HIVE_ADDR_sp_all_cb_elems_param 0x5870 +#endif +#define HIVE_SIZE_sp_all_cb_elems_param 16 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cb_elems_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cb_elems_param 0x57D4 +#else +#define HIVE_ADDR_sp_sp_all_cb_elems_param 0x5870 +#endif +#define HIVE_SIZE_sp_sp_all_cb_elems_param 16 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_pipeline_sp_curr_binary_id +#define HIVE_MEM_pipeline_sp_curr_binary_id scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_pipeline_sp_curr_binary_id 0x284 +#else +#define HIVE_ADDR_pipeline_sp_curr_binary_id 0x288 +#endif +#define HIVE_SIZE_pipeline_sp_curr_binary_id 4 +#else +#endif +#endif +#define HIVE_MEM_sp_pipeline_sp_curr_binary_id scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_pipeline_sp_curr_binary_id 0x284 +#else +#define HIVE_ADDR_sp_pipeline_sp_curr_binary_id 0x288 +#endif +#define HIVE_SIZE_sp_pipeline_sp_curr_binary_id 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cbs_frame_desc +#define HIVE_MEM_sp_all_cbs_frame_desc scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cbs_frame_desc 0x57E4 +#else +#define HIVE_ADDR_sp_all_cbs_frame_desc 0x5880 +#endif +#define HIVE_SIZE_sp_all_cbs_frame_desc 8 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cbs_frame_desc scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cbs_frame_desc 0x57E4 +#else +#define HIVE_ADDR_sp_sp_all_cbs_frame_desc 0x5880 +#endif +#define HIVE_SIZE_sp_sp_all_cbs_frame_desc 8 + +#ifndef ISP2401 +/* function sp_isys_copy_func_v2: 629 */ +#else +/* function sp_isys_copy_func_v2: 5BD */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_reading_cb_param +#define HIVE_MEM_sem_for_reading_cb_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_reading_cb_param 0x57EC +#else +#define HIVE_ADDR_sem_for_reading_cb_param 0x5888 +#endif +#define HIVE_SIZE_sem_for_reading_cb_param 40 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_reading_cb_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_reading_cb_param 0x57EC +#else +#define HIVE_ADDR_sp_sem_for_reading_cb_param 0x5888 +#endif +#define HIVE_SIZE_sp_sem_for_reading_cb_param 40 + +#ifndef ISP2401 +/* function ia_css_queue_get_used_space: 52C7 */ +#else +/* function ia_css_queue_get_used_space: 54A6 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_cont_capt_start +#define HIVE_MEM_sem_for_cont_capt_start scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_cont_capt_start 0x5814 +#else +#define HIVE_ADDR_sem_for_cont_capt_start 0x58B0 +#endif +#define HIVE_SIZE_sem_for_cont_capt_start 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_cont_capt_start scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_cont_capt_start 0x5814 +#else +#define HIVE_ADDR_sp_sem_for_cont_capt_start 0x58B0 +#endif +#define HIVE_SIZE_sp_sem_for_cont_capt_start 20 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_tmp_heap +#define HIVE_MEM_tmp_heap scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_tmp_heap 0x70A8 +#else +#define HIVE_ADDR_tmp_heap 0x7158 +#endif +#define HIVE_SIZE_tmp_heap 640 +#else +#endif +#endif +#define HIVE_MEM_sp_tmp_heap scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_tmp_heap 0x70A8 +#else +#define HIVE_ADDR_sp_tmp_heap 0x7158 +#endif +#define HIVE_SIZE_sp_tmp_heap 640 + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_get_num_vbuf: 64B0 */ +#else +/* function ia_css_rmgr_sp_get_num_vbuf: 6676 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_output_compute_dma_info: 4863 */ +#else +/* function ia_css_ispctrl_sp_output_compute_dma_info: 4A27 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_lock_exp_id: 2A0F */ +#else +/* function ia_css_tagger_sp_lock_exp_id: 29E0 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_s3a_bufs +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_s3a_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_s3a_bufs 0x5C24 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_s3a_bufs 0x5CD0 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_s3a_bufs 60 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_s3a_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_s3a_bufs 0x5C24 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_s3a_bufs 0x5CD0 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_s3a_bufs 60 + +#ifndef ISP2401 +/* function ia_css_queue_is_full: 535E */ +#else +/* function ia_css_queue_is_full: 553D */ +#endif + +/* function debug_buffer_init_isp: E4 */ + +#ifndef ISP2401 +/* function ia_css_tagger_sp_exp_id_is_locked: 2945 */ +#else +/* function ia_css_tagger_sp_exp_id_is_locked: 2916 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_rmgr_sp_mipi_frame_sem +#define HIVE_MEM_ia_css_rmgr_sp_mipi_frame_sem scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_rmgr_sp_mipi_frame_sem 0x7764 +#else +#define HIVE_ADDR_ia_css_rmgr_sp_mipi_frame_sem 0x7810 +#endif +#define HIVE_SIZE_ia_css_rmgr_sp_mipi_frame_sem 60 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_rmgr_sp_mipi_frame_sem scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_rmgr_sp_mipi_frame_sem 0x7764 +#else +#define HIVE_ADDR_sp_ia_css_rmgr_sp_mipi_frame_sem 0x7810 +#endif +#define HIVE_SIZE_sp_ia_css_rmgr_sp_mipi_frame_sem 60 + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_refcount_dump: 6287 */ +#else +/* function ia_css_rmgr_sp_refcount_dump: 644D */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_isp_parameters_id +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_isp_parameters_id scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x5C60 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x5D0C +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_isp_parameters_id 20 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x5C60 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x5D0C +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id 20 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_pipe_threads +#define HIVE_MEM_sp_pipe_threads scalar_processor_2400_dmem +#define HIVE_ADDR_sp_pipe_threads 0x150 +#define HIVE_SIZE_sp_pipe_threads 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_pipe_threads scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_pipe_threads 0x150 +#define HIVE_SIZE_sp_sp_pipe_threads 20 + +#ifndef ISP2401 +/* function sp_event_proxy_func: 78D */ +#else +/* function sp_event_proxy_func: 721 */ +#endif + +#ifndef ISP2401 +/* function ibuf_ctrl_run: D7F */ +#else +/* function ibuf_ctrl_run: D79 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host2sp_isys_event_queue_handle +#define HIVE_MEM_host2sp_isys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host2sp_isys_event_queue_handle 0x5C74 +#else +#define HIVE_ADDR_host2sp_isys_event_queue_handle 0x5D20 +#endif +#define HIVE_SIZE_host2sp_isys_event_queue_handle 12 +#else +#endif +#endif +#define HIVE_MEM_sp_host2sp_isys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host2sp_isys_event_queue_handle 0x5C74 +#else +#define HIVE_ADDR_sp_host2sp_isys_event_queue_handle 0x5D20 +#endif +#define HIVE_SIZE_sp_host2sp_isys_event_queue_handle 12 + +#ifndef ISP2401 +/* function ia_css_thread_sp_yield: 6A12 */ +#else +/* function ia_css_thread_sp_yield: 6C96 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cbs_param_desc +#define HIVE_MEM_sp_all_cbs_param_desc scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cbs_param_desc 0x5828 +#else +#define HIVE_ADDR_sp_all_cbs_param_desc 0x58C4 +#endif +#define HIVE_SIZE_sp_all_cbs_param_desc 8 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cbs_param_desc scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cbs_param_desc 0x5828 +#else +#define HIVE_ADDR_sp_sp_all_cbs_param_desc 0x58C4 +#endif +#define HIVE_SIZE_sp_sp_all_cbs_param_desc 8 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_dmaproxy_sp_invalidate_tlb +#define HIVE_MEM_ia_css_dmaproxy_sp_invalidate_tlb scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb 0x6C8C +#else +#define HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb 0x6D38 +#endif +#define HIVE_SIZE_ia_css_dmaproxy_sp_invalidate_tlb 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_dmaproxy_sp_invalidate_tlb scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_dmaproxy_sp_invalidate_tlb 0x6C8C +#else +#define HIVE_ADDR_sp_ia_css_dmaproxy_sp_invalidate_tlb 0x6D38 +#endif +#define HIVE_SIZE_sp_ia_css_dmaproxy_sp_invalidate_tlb 4 + +#ifndef ISP2401 +/* function ia_css_thread_sp_fork: 13AC */ +#else +/* function ia_css_thread_sp_fork: 1322 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_destroy: 3136 */ +#else +/* function ia_css_tagger_sp_destroy: 3107 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_vmem_read: 3ADB */ +#else +/* function ia_css_dmaproxy_sp_vmem_read: 3C3B */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_N_LONG_PACKET_LUT_ENTRIES +#define HIVE_MEM_N_LONG_PACKET_LUT_ENTRIES scalar_processor_2400_dmem +#define HIVE_ADDR_N_LONG_PACKET_LUT_ENTRIES 0x1B8 +#define HIVE_SIZE_N_LONG_PACKET_LUT_ENTRIES 12 +#else +#endif +#endif +#define HIVE_MEM_sp_N_LONG_PACKET_LUT_ENTRIES scalar_processor_2400_dmem +#define HIVE_ADDR_sp_N_LONG_PACKET_LUT_ENTRIES 0x1B8 +#define HIVE_SIZE_sp_N_LONG_PACKET_LUT_ENTRIES 12 + +#ifndef ISP2401 +/* function initialize_sp_group: 5F6 */ +#else +/* function initialize_sp_group: 58A */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_peek: 325B */ +#else +/* function ia_css_tagger_buf_sp_peek: 337E */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_init: 13D8 */ +#else +/* function ia_css_thread_sp_init: 134E */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_reset_exp_id: 6133 */ +#else +/* function qos_scheduler_update_fps: 67AD */ +#endif + +#ifndef ISP2401 +/* function qos_scheduler_update_fps: 65AF */ +#else +/* function ia_css_isys_sp_reset_exp_id: 62F9 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_set_stream_base_addr: 4F38 */ +#else +/* function ia_css_ispctrl_sp_set_stream_base_addr: 5114 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_DMEM_BASE +#define HIVE_MEM_ISP_DMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_ISP_DMEM_BASE 0x10 +#define HIVE_SIZE_ISP_DMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_DMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ISP_DMEM_BASE 0x10 +#define HIVE_SIZE_sp_ISP_DMEM_BASE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_SP_DMEM_BASE +#define HIVE_MEM_SP_DMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_SP_DMEM_BASE 0x4 +#define HIVE_SIZE_SP_DMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_SP_DMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_SP_DMEM_BASE 0x4 +#define HIVE_SIZE_sp_SP_DMEM_BASE 4 + +#ifndef ISP2401 +/* function ibuf_ctrl_transfer: D67 */ +#else +/* function ibuf_ctrl_transfer: D61 */ + +/* function __ia_css_queue_is_empty_text: 5403 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_read: 3B51 */ +#else +/* function ia_css_dmaproxy_sp_read: 3CB1 */ +#endif + +#ifndef ISP2401 +/* function virtual_isys_stream_is_capture_done: 5EB0 */ +#else +/* function virtual_isys_stream_is_capture_done: 5F94 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_raw_copy_line_count +#define HIVE_MEM_raw_copy_line_count scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_raw_copy_line_count 0x360 +#else +#define HIVE_ADDR_raw_copy_line_count 0x378 +#endif +#define HIVE_SIZE_raw_copy_line_count 4 +#else +#endif +#endif +#define HIVE_MEM_sp_raw_copy_line_count scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_raw_copy_line_count 0x360 +#else +#define HIVE_ADDR_sp_raw_copy_line_count 0x378 +#endif +#define HIVE_SIZE_sp_raw_copy_line_count 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host2sp_tag_cmd_queue_handle +#define HIVE_MEM_host2sp_tag_cmd_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host2sp_tag_cmd_queue_handle 0x5C80 +#else +#define HIVE_ADDR_host2sp_tag_cmd_queue_handle 0x5D2C +#endif +#define HIVE_SIZE_host2sp_tag_cmd_queue_handle 12 +#else +#endif +#endif +#define HIVE_MEM_sp_host2sp_tag_cmd_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host2sp_tag_cmd_queue_handle 0x5C80 +#else +#define HIVE_ADDR_sp_host2sp_tag_cmd_queue_handle 0x5D2C +#endif +#define HIVE_SIZE_sp_host2sp_tag_cmd_queue_handle 12 + +#ifndef ISP2401 +/* function ia_css_queue_peek: 523D */ +#else +/* function ia_css_queue_peek: 541C */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_flash_sp_frame_cnt +#define HIVE_MEM_ia_css_flash_sp_frame_cnt scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_flash_sp_frame_cnt 0x5B2C +#else +#define HIVE_ADDR_ia_css_flash_sp_frame_cnt 0x5BD8 +#endif +#define HIVE_SIZE_ia_css_flash_sp_frame_cnt 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_flash_sp_frame_cnt scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_flash_sp_frame_cnt 0x5B2C +#else +#define HIVE_ADDR_sp_ia_css_flash_sp_frame_cnt 0x5BD8 +#endif +#define HIVE_SIZE_sp_ia_css_flash_sp_frame_cnt 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_event_can_send_token_mask +#define HIVE_MEM_event_can_send_token_mask scalar_processor_2400_dmem +#define HIVE_ADDR_event_can_send_token_mask 0x88 +#define HIVE_SIZE_event_can_send_token_mask 44 +#else +#endif +#endif +#define HIVE_MEM_sp_event_can_send_token_mask scalar_processor_2400_dmem +#define HIVE_ADDR_sp_event_can_send_token_mask 0x88 +#define HIVE_SIZE_sp_event_can_send_token_mask 44 + +#ifndef ISP2401 +/* function csi_rx_frontend_stop: C11 */ +#else +/* function csi_rx_frontend_stop: C0B */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isp_thread +#define HIVE_MEM_isp_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isp_thread 0x6FD8 +#else +#define HIVE_ADDR_isp_thread 0x7088 +#endif +#define HIVE_SIZE_isp_thread 4 +#else +#endif +#endif +#define HIVE_MEM_sp_isp_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_thread 0x6FD8 +#else +#define HIVE_ADDR_sp_isp_thread 0x7088 +#endif +#define HIVE_SIZE_sp_isp_thread 4 + +#ifndef ISP2401 +/* function encode_and_post_sp_event_non_blocking: AF0 */ +#else +/* function encode_and_post_sp_event_non_blocking: A84 */ +#endif + +/* function is_ddr_debug_buffer_full: 2CC */ + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_get_oldest_marked_offset: 32AB */ +#else +/* function ia_css_tagger_buf_sp_get_oldest_marked_offset: 33CE */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_threads_fiber +#define HIVE_MEM_sp_threads_fiber scalar_processor_2400_dmem +#define HIVE_ADDR_sp_threads_fiber 0x194 +#define HIVE_SIZE_sp_threads_fiber 24 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_threads_fiber scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_threads_fiber 0x194 +#define HIVE_SIZE_sp_sp_threads_fiber 24 + +#ifndef ISP2401 +/* function encode_and_post_sp_event: A79 */ +#else +/* function encode_and_post_sp_event: A0D */ +#endif + +/* function debug_enqueue_ddr: EE */ + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_refcount_init_vbuf: 6242 */ +#else +/* function ia_css_rmgr_sp_refcount_init_vbuf: 6408 */ +#endif + +#ifndef ISP2401 +/* function dmaproxy_sp_read_write: 6E86 */ +#else +/* function dmaproxy_sp_read_write: 70C3 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_dmaproxy_isp_dma_cmd_buffer +#define HIVE_MEM_ia_css_dmaproxy_isp_dma_cmd_buffer scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_dmaproxy_isp_dma_cmd_buffer 0x6C90 +#else +#define HIVE_ADDR_ia_css_dmaproxy_isp_dma_cmd_buffer 0x6D3C +#endif +#define HIVE_SIZE_ia_css_dmaproxy_isp_dma_cmd_buffer 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_dmaproxy_isp_dma_cmd_buffer scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_dmaproxy_isp_dma_cmd_buffer 0x6C90 +#else +#define HIVE_ADDR_sp_ia_css_dmaproxy_isp_dma_cmd_buffer 0x6D3C +#endif +#define HIVE_SIZE_sp_ia_css_dmaproxy_isp_dma_cmd_buffer 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host2sp_buffer_queue_handle +#define HIVE_MEM_host2sp_buffer_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host2sp_buffer_queue_handle 0x5C8C +#else +#define HIVE_ADDR_host2sp_buffer_queue_handle 0x5D38 +#endif +#define HIVE_SIZE_host2sp_buffer_queue_handle 480 +#else +#endif +#endif +#define HIVE_MEM_sp_host2sp_buffer_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host2sp_buffer_queue_handle 0x5C8C +#else +#define HIVE_ADDR_sp_host2sp_buffer_queue_handle 0x5D38 +#endif +#define HIVE_SIZE_sp_host2sp_buffer_queue_handle 480 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_flash_sp_in_service +#define HIVE_MEM_ia_css_flash_sp_in_service scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_flash_sp_in_service 0x3054 +#else +#define HIVE_ADDR_ia_css_flash_sp_in_service 0x3074 +#endif +#define HIVE_SIZE_ia_css_flash_sp_in_service 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_flash_sp_in_service scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_flash_sp_in_service 0x3054 +#else +#define HIVE_ADDR_sp_ia_css_flash_sp_in_service 0x3074 +#endif +#define HIVE_SIZE_sp_ia_css_flash_sp_in_service 4 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_process: 6B92 */ +#else +/* function ia_css_dmaproxy_sp_process: 6E0F */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_mark_from_end: 3533 */ +#else +/* function ia_css_tagger_buf_sp_mark_from_end: 3656 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_init_cs: 3F77 */ +#else +/* function ia_css_ispctrl_sp_init_cs: 40FA */ +#endif + +#ifndef ISP2401 +/* function ia_css_spctrl_sp_init: 5E02 */ +#else +/* function ia_css_spctrl_sp_init: 5EE4 */ +#endif + +#ifndef ISP2401 +/* function sp_event_proxy_init: 7A2 */ +#else +/* function sp_event_proxy_init: 736 */ +#endif + +#ifndef ISP2401 +/* function input_system_input_port_close: 109B */ +#else +/* function input_system_input_port_close: 1095 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_previous_clock_tick +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_previous_clock_tick scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x5E6C +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x5F18 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_previous_clock_tick 40 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x5E6C +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x5F18 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick 40 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_output +#define HIVE_MEM_sp_output scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_output 0x3F2C +#else +#define HIVE_ADDR_sp_output 0x3F50 +#endif +#define HIVE_SIZE_sp_output 16 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_output scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_output 0x3F2C +#else +#define HIVE_ADDR_sp_sp_output 0x3F50 +#endif +#define HIVE_SIZE_sp_sp_output 16 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_sems_for_host2sp_buf_queues +#define HIVE_MEM_ia_css_bufq_sp_sems_for_host2sp_buf_queues scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x5E94 +#else +#define HIVE_ADDR_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x5F40 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_sems_for_host2sp_buf_queues 800 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x5E94 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x5F40 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues 800 + +#ifndef ISP2401 +/* function pixelgen_prbs_config: E93 */ +#else +/* function pixelgen_prbs_config: E8D */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_CTRL_BASE +#define HIVE_MEM_ISP_CTRL_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_ISP_CTRL_BASE 0x8 +#define HIVE_SIZE_ISP_CTRL_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_CTRL_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ISP_CTRL_BASE 0x8 +#define HIVE_SIZE_sp_ISP_CTRL_BASE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_INPUT_FORMATTER_BASE +#define HIVE_MEM_INPUT_FORMATTER_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_INPUT_FORMATTER_BASE 0x4C +#define HIVE_SIZE_INPUT_FORMATTER_BASE 16 +#else +#endif +#endif +#define HIVE_MEM_sp_INPUT_FORMATTER_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_INPUT_FORMATTER_BASE 0x4C +#define HIVE_SIZE_sp_INPUT_FORMATTER_BASE 16 + +#ifndef ISP2401 +/* function sp_dma_proxy_reset_channels: 3DAB */ +#else +/* function sp_dma_proxy_reset_channels: 3F20 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_update_size: 322A */ +#else +/* function ia_css_tagger_sp_update_size: 334D */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_host_sp_queue +#define HIVE_MEM_ia_css_bufq_host_sp_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_host_sp_queue 0x61B4 +#else +#define HIVE_ADDR_ia_css_bufq_host_sp_queue 0x6260 +#endif +#define HIVE_SIZE_ia_css_bufq_host_sp_queue 2008 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_host_sp_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_host_sp_queue 0x61B4 +#else +#define HIVE_ADDR_sp_ia_css_bufq_host_sp_queue 0x6260 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_host_sp_queue 2008 + +#ifndef ISP2401 +/* function thread_fiber_sp_create: 1444 */ +#else +/* function thread_fiber_sp_create: 13BA */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_set_increments: 3C3D */ +#else +/* function ia_css_dmaproxy_sp_set_increments: 3DB2 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_writing_cb_frame +#define HIVE_MEM_sem_for_writing_cb_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_writing_cb_frame 0x5830 +#else +#define HIVE_ADDR_sem_for_writing_cb_frame 0x58CC +#endif +#define HIVE_SIZE_sem_for_writing_cb_frame 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_writing_cb_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_writing_cb_frame 0x5830 +#else +#define HIVE_ADDR_sp_sem_for_writing_cb_frame 0x58CC +#endif +#define HIVE_SIZE_sp_sem_for_writing_cb_frame 20 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_writing_cb_param +#define HIVE_MEM_sem_for_writing_cb_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_writing_cb_param 0x5844 +#else +#define HIVE_ADDR_sem_for_writing_cb_param 0x58E0 +#endif +#define HIVE_SIZE_sem_for_writing_cb_param 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_writing_cb_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_writing_cb_param 0x5844 +#else +#define HIVE_ADDR_sp_sem_for_writing_cb_param 0x58E0 +#endif +#define HIVE_SIZE_sp_sem_for_writing_cb_param 20 + +#ifndef ISP2401 +/* function pixelgen_tpg_is_done: F0D */ +#else +/* function pixelgen_tpg_is_done: F07 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_stream_capture_indication: 5FB6 */ +#else +/* function ia_css_isys_stream_capture_indication: 60D7 */ +#endif + +/* function sp_start_isp_entry: 392 */ +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifdef HIVE_ADDR_sp_start_isp_entry +#endif +#define HIVE_ADDR_sp_start_isp_entry 0x392 +#endif +#define HIVE_ADDR_sp_sp_start_isp_entry 0x392 + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_unmark_all: 34B7 */ +#else +/* function ia_css_tagger_buf_sp_unmark_all: 35DA */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_unmark_from_start: 34F8 */ +#else +/* function ia_css_tagger_buf_sp_unmark_from_start: 361B */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_channel_acquire: 3DD7 */ +#else +/* function ia_css_dmaproxy_sp_channel_acquire: 3F4C */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_add_num_vbuf: 648C */ +#else +/* function ia_css_rmgr_sp_add_num_vbuf: 6652 */ +#endif + +#ifndef ISP2401 +/* function ibuf_ctrl_config: D8B */ +#else +/* function ibuf_ctrl_config: D85 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_stream_stop: 602E */ +#else +/* function ia_css_isys_stream_stop: 61F4 */ +#endif + +#ifndef ISP2401 +/* function __ia_css_dmaproxy_sp_wait_for_ack_text: 3AA7 */ +#else +/* function __ia_css_dmaproxy_sp_wait_for_ack_text: 3C07 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_acquire_buf_elem: 291D */ +#else +/* function ia_css_tagger_sp_acquire_buf_elem: 28EE */ +#endif + +#ifndef ISP2401 +/* function ia_css_bufq_sp_is_dynamic_buffer: 3990 */ +#else +/* function ia_css_bufq_sp_is_dynamic_buffer: 3AB3 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_group +#define HIVE_MEM_sp_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_group 0x3F3C +#define HIVE_SIZE_sp_group 6176 +#else +#define HIVE_ADDR_sp_group 0x3F60 +#define HIVE_SIZE_sp_group 6296 +#endif +#else +#endif +#endif +#define HIVE_MEM_sp_sp_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_group 0x3F3C +#define HIVE_SIZE_sp_sp_group 6176 +#else +#define HIVE_ADDR_sp_sp_group 0x3F60 +#define HIVE_SIZE_sp_sp_group 6296 +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_event_proxy_thread +#define HIVE_MEM_sp_event_proxy_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_event_proxy_thread 0x5A30 +#define HIVE_SIZE_sp_event_proxy_thread 68 +#else +#define HIVE_ADDR_sp_event_proxy_thread 0x5AE0 +#define HIVE_SIZE_sp_event_proxy_thread 72 +#endif +#else +#endif +#endif +#define HIVE_MEM_sp_sp_event_proxy_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_event_proxy_thread 0x5A30 +#define HIVE_SIZE_sp_sp_event_proxy_thread 68 +#else +#define HIVE_ADDR_sp_sp_event_proxy_thread 0x5AE0 +#define HIVE_SIZE_sp_sp_event_proxy_thread 72 +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_kill: 1372 */ +#else +/* function ia_css_thread_sp_kill: 12E8 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_create: 31E4 */ +#else +/* function ia_css_tagger_sp_create: 32FB */ +#endif + +#ifndef ISP2401 +/* function tmpmem_acquire_dmem: 6539 */ +#else +/* function tmpmem_acquire_dmem: 66FF */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_MMU_BASE +#define HIVE_MEM_MMU_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_MMU_BASE 0x24 +#define HIVE_SIZE_MMU_BASE 8 +#else +#endif +#endif +#define HIVE_MEM_sp_MMU_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_MMU_BASE 0x24 +#define HIVE_SIZE_sp_MMU_BASE 8 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_channel_release: 3DC3 */ +#else +/* function ia_css_dmaproxy_sp_channel_release: 3F38 */ +#endif + +#ifndef ISP2401 +/* function pixelgen_prbs_run: E81 */ +#else +/* function pixelgen_prbs_run: E7B */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_is_idle: 3DA3 */ +#else +/* function ia_css_dmaproxy_sp_is_idle: 3F18 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_qos_start +#define HIVE_MEM_sem_for_qos_start scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_qos_start 0x5858 +#else +#define HIVE_ADDR_sem_for_qos_start 0x58F4 +#endif +#define HIVE_SIZE_sem_for_qos_start 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_qos_start scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_qos_start 0x5858 +#else +#define HIVE_ADDR_sp_sem_for_qos_start 0x58F4 +#endif +#define HIVE_SIZE_sp_sem_for_qos_start 20 + +#ifndef ISP2401 +/* function isp_hmem_load: B63 */ +#else +/* function isp_hmem_load: B5D */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_release_buf_elem: 28F9 */ +#else +/* function ia_css_tagger_sp_release_buf_elem: 28CA */ +#endif + +#ifndef ISP2401 +/* function ia_css_eventq_sp_send: 3E19 */ +#else +/* function ia_css_eventq_sp_send: 3F8E */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_unlock_from_start: 33E7 */ +#else +/* function ia_css_tagger_buf_sp_unlock_from_start: 350A */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_debug_buffer_ddr_address +#define HIVE_MEM_debug_buffer_ddr_address scalar_processor_2400_dmem +#define HIVE_ADDR_debug_buffer_ddr_address 0xBC +#define HIVE_SIZE_debug_buffer_ddr_address 4 +#else +#endif +#endif +#define HIVE_MEM_sp_debug_buffer_ddr_address scalar_processor_2400_dmem +#define HIVE_ADDR_sp_debug_buffer_ddr_address 0xBC +#define HIVE_SIZE_sp_debug_buffer_ddr_address 4 + +#ifndef ISP2401 +/* function sp_isys_copy_request: 6ED */ +#else +/* function sp_isys_copy_request: 681 */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_refcount_retain_vbuf: 631C */ +#else +/* function ia_css_rmgr_sp_refcount_retain_vbuf: 64E2 */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_set_priority: 136A */ +#else +/* function ia_css_thread_sp_set_priority: 12E0 */ +#endif + +#ifndef ISP2401 +/* function sizeof_hmem: C0A */ +#else +/* function sizeof_hmem: C04 */ +#endif + +#ifndef ISP2401 +/* function input_system_channel_open: 1241 */ +#else +/* function input_system_channel_open: 11BC */ +#endif + +#ifndef ISP2401 +/* function pixelgen_tpg_stop: EFB */ +#else +/* function pixelgen_tpg_stop: EF5 */ +#endif + +#ifndef ISP2401 +/* function tmpmem_release_dmem: 6528 */ +#else +/* function tmpmem_release_dmem: 66EE */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_set_width_exception: 3C28 */ +#else +/* function __ia_css_dmaproxy_sp_process_text: 3BAB */ +#endif + +#ifndef ISP2401 +/* function sp_event_assert: 929 */ +#else +/* function ia_css_dmaproxy_sp_set_width_exception: 3D9D */ +#endif + +#ifndef ISP2401 +/* function ia_css_flash_sp_init_internal_params: 35B4 */ +#else +/* function sp_event_assert: 8BD */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_pop_unmarked_and_unlocked: 32ED */ +#else +/* function ia_css_flash_sp_init_internal_params: 36D7 */ +#endif + +#ifndef ISP2401 +/* function __modu: 687A */ +#else +/* function ia_css_tagger_buf_sp_pop_unmarked_and_unlocked: 3410 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_init_isp_vector: 3AAD */ +#else +/* function __modu: 6A78 */ +#endif + +#ifndef ISP2401 +/* function input_system_channel_transfer: 122A */ +#else +/* function ia_css_dmaproxy_sp_init_isp_vector: 3C0D */ + +/* function input_system_channel_transfer: 11A5 */ +#endif + +/* function isp_vamem_store: 0 */ + +#ifdef ISP2401 +/* function ia_css_tagger_sp_set_copy_pipe: 32F2 */ + +#endif +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_GDC_BASE +#define HIVE_MEM_GDC_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_GDC_BASE 0x44 +#define HIVE_SIZE_GDC_BASE 8 +#else +#endif +#endif +#define HIVE_MEM_sp_GDC_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_GDC_BASE 0x44 +#define HIVE_SIZE_sp_GDC_BASE 8 + +#ifndef ISP2401 +/* function ia_css_queue_local_init: 5528 */ +#else +/* function ia_css_queue_local_init: 5707 */ +#endif + +#ifndef ISP2401 +/* function sp_event_proxy_callout_func: 6947 */ +#else +/* function sp_event_proxy_callout_func: 6B45 */ +#endif + +#ifndef ISP2401 +/* function qos_scheduler_schedule_stage: 6580 */ +#else +/* function qos_scheduler_schedule_stage: 6759 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_thread_sp_num_ready_threads +#define HIVE_MEM_ia_css_thread_sp_num_ready_threads scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_thread_sp_num_ready_threads 0x5A78 +#else +#define HIVE_ADDR_ia_css_thread_sp_num_ready_threads 0x5B28 +#endif +#define HIVE_SIZE_ia_css_thread_sp_num_ready_threads 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_thread_sp_num_ready_threads scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_thread_sp_num_ready_threads 0x5A78 +#else +#define HIVE_ADDR_sp_ia_css_thread_sp_num_ready_threads 0x5B28 +#endif +#define HIVE_SIZE_sp_ia_css_thread_sp_num_ready_threads 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_threads_stack_size +#define HIVE_MEM_sp_threads_stack_size scalar_processor_2400_dmem +#define HIVE_ADDR_sp_threads_stack_size 0x17C +#define HIVE_SIZE_sp_threads_stack_size 24 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_threads_stack_size scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_threads_stack_size 0x17C +#define HIVE_SIZE_sp_sp_threads_stack_size 24 + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_isp_done_row_striping: 4849 */ +#else +/* function ia_css_ispctrl_sp_isp_done_row_striping: 4A0D */ +#endif + +#ifndef ISP2401 +/* function __ia_css_virtual_isys_sp_isr_text: 5E45 */ +#else +/* function __ia_css_virtual_isys_sp_isr_text: 5F4E */ +#endif + +#ifndef ISP2401 +/* function ia_css_queue_dequeue: 53A6 */ +#else +/* function ia_css_queue_dequeue: 5585 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_configure_channel: 6DEE */ +#else +/* function is_qos_standalone_mode: 6734 */ + +/* function ia_css_dmaproxy_sp_configure_channel: 703C */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_current_thread_fiber_sp +#define HIVE_MEM_current_thread_fiber_sp scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_current_thread_fiber_sp 0x5A80 +#else +#define HIVE_ADDR_current_thread_fiber_sp 0x5B2C +#endif +#define HIVE_SIZE_current_thread_fiber_sp 4 +#else +#endif +#endif +#define HIVE_MEM_sp_current_thread_fiber_sp scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_current_thread_fiber_sp 0x5A80 +#else +#define HIVE_ADDR_sp_current_thread_fiber_sp 0x5B2C +#endif +#define HIVE_SIZE_sp_current_thread_fiber_sp 4 + +#ifndef ISP2401 +/* function ia_css_circbuf_pop: 1674 */ +#else +/* function ia_css_circbuf_pop: 15EA */ +#endif + +#ifndef ISP2401 +/* function memset: 68F9 */ +#else +/* function memset: 6AF7 */ +#endif + +/* function irq_raise_set_token: B6 */ + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_GPIO_BASE +#define HIVE_MEM_GPIO_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_GPIO_BASE 0x3C +#define HIVE_SIZE_GPIO_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_GPIO_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_GPIO_BASE 0x3C +#define HIVE_SIZE_sp_GPIO_BASE 4 + +#ifndef ISP2401 +/* function pixelgen_prbs_stop: E6F */ +#else +/* function pixelgen_prbs_stop: E69 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_acc_stage_enable: 1FC0 */ +#else +/* function ia_css_pipeline_acc_stage_enable: 1F69 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_unlock_exp_id: 296A */ +#else +/* function ia_css_tagger_sp_unlock_exp_id: 293B */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isp_ph +#define HIVE_MEM_isp_ph scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isp_ph 0x7360 +#else +#define HIVE_ADDR_isp_ph 0x740C +#endif +#define HIVE_SIZE_isp_ph 28 +#else +#endif +#endif +#define HIVE_MEM_sp_isp_ph scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_ph 0x7360 +#else +#define HIVE_ADDR_sp_isp_ph 0x740C +#endif +#define HIVE_SIZE_sp_isp_ph 28 + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_init_ds: 40D6 */ +#else +/* function ia_css_ispctrl_sp_init_ds: 4286 */ +#endif + +#ifndef ISP2401 +/* function get_xmem_base_addr_raw: 4479 */ +#else +/* function get_xmem_base_addr_raw: 4635 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cbs_param +#define HIVE_MEM_sp_all_cbs_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cbs_param 0x586C +#else +#define HIVE_ADDR_sp_all_cbs_param 0x5908 +#endif +#define HIVE_SIZE_sp_all_cbs_param 16 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cbs_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cbs_param 0x586C +#else +#define HIVE_ADDR_sp_sp_all_cbs_param 0x5908 +#endif +#define HIVE_SIZE_sp_sp_all_cbs_param 16 + +#ifndef ISP2401 +/* function pixelgen_tpg_config: F30 */ +#else +/* function pixelgen_tpg_config: F2A */ +#endif + +#ifndef ISP2401 +/* function ia_css_circbuf_create: 16C2 */ +#else +/* function ia_css_circbuf_create: 1638 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_sp_group +#define HIVE_MEM_sem_for_sp_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_sp_group 0x587C +#else +#define HIVE_ADDR_sem_for_sp_group 0x5918 +#endif +#define HIVE_SIZE_sem_for_sp_group 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_sp_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_sp_group 0x587C +#else +#define HIVE_ADDR_sp_sem_for_sp_group 0x5918 +#endif +#define HIVE_SIZE_sp_sem_for_sp_group 20 + +#ifndef ISP2401 +/* function csi_rx_frontend_run: C22 */ +#else +/* function csi_rx_frontend_run: C1C */ + +/* function __ia_css_dmaproxy_sp_configure_channel_text: 3D7C */ +#endif + +#ifndef ISP2401 +/* function ia_css_framebuf_sp_wait_for_in_frame: 64B7 */ +#else +/* function ia_css_framebuf_sp_wait_for_in_frame: 667D */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_stream_open: 60E3 */ +#else +/* function ia_css_isys_stream_open: 62A9 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_rawcopy_tag_frame: 5C71 */ +#else +/* function ia_css_sp_rawcopy_tag_frame: 5E35 */ +#endif + +#ifndef ISP2401 +/* function input_system_channel_configure: 125D */ +#else +/* function input_system_channel_configure: 11D8 */ +#endif + +#ifndef ISP2401 +/* function isp_hmem_clear: B33 */ +#else +/* function isp_hmem_clear: B2D */ +#endif + +#ifndef ISP2401 +/* function ia_css_framebuf_sp_release_in_frame: 64FA */ +#else +/* function ia_css_framebuf_sp_release_in_frame: 66C0 */ +#endif + +#ifndef ISP2401 +/* function stream2mmio_config: E1B */ +#else +/* function stream2mmio_config: E15 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_start_binary: 3F55 */ +#else +/* function ia_css_ispctrl_sp_start_binary: 40D8 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_h_pipe_private_ddr_ptrs +#define HIVE_MEM_ia_css_bufq_sp_h_pipe_private_ddr_ptrs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x698C +#else +#define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x6A38 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 20 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x698C +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x6A38 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 20 + +#ifndef ISP2401 +/* function ia_css_eventq_sp_recv: 3DEB */ +#else +/* function ia_css_eventq_sp_recv: 3F60 */ +#endif + +#ifndef ISP2401 +/* function csi_rx_frontend_config: C7A */ +#else +/* function csi_rx_frontend_config: C74 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isp_pool +#define HIVE_MEM_isp_pool scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isp_pool 0x370 +#else +#define HIVE_ADDR_isp_pool 0x388 +#endif +#define HIVE_SIZE_isp_pool 4 +#else +#endif +#endif +#define HIVE_MEM_sp_isp_pool scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_pool 0x370 +#else +#define HIVE_ADDR_sp_isp_pool 0x388 +#endif +#define HIVE_SIZE_sp_isp_pool 4 + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_rel_gen: 61E9 */ +#else +/* function ia_css_rmgr_sp_rel_gen: 63AF */ + +/* function ia_css_tagger_sp_unblock_clients: 31C3 */ +#endif + +#ifndef ISP2401 +/* function css_get_frame_processing_time_end: 28E9 */ +#else +/* function css_get_frame_processing_time_end: 28BA */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_event_any_pending_mask +#define HIVE_MEM_event_any_pending_mask scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_event_any_pending_mask 0x388 +#else +#define HIVE_ADDR_event_any_pending_mask 0x3A0 +#endif +#define HIVE_SIZE_event_any_pending_mask 8 +#else +#endif +#endif +#define HIVE_MEM_sp_event_any_pending_mask scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_event_any_pending_mask 0x388 +#else +#define HIVE_ADDR_sp_event_any_pending_mask 0x3A0 +#endif +#define HIVE_SIZE_sp_event_any_pending_mask 8 + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_get_pipe_io_status: 1AB8 */ +#else +/* function ia_css_pipeline_sp_get_pipe_io_status: 1A5A */ +#endif + +/* function sh_css_decode_tag_descr: 352 */ + +/* function debug_enqueue_isp: 27B */ + +#ifndef ISP2401 +/* function qos_scheduler_update_stage_budget: 656E */ +#else +/* function qos_scheduler_update_stage_budget: 673C */ +#endif + +#ifndef ISP2401 +/* function ia_css_spctrl_sp_uninit: 5DFB */ +#else +/* function ia_css_spctrl_sp_uninit: 5EDD */ +#endif + +#ifndef ISP2401 +/* function csi_rx_backend_run: C68 */ +#else +/* function csi_rx_backend_run: C62 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_dis_bufs +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_dis_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_dis_bufs 0x69A0 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_dis_bufs 0x6A4C +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_dis_bufs 140 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_dis_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_dis_bufs 0x69A0 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_dis_bufs 0x6A4C +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_dis_bufs 140 + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_lock_from_start: 341B */ +#else +/* function ia_css_tagger_buf_sp_lock_from_start: 353E */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_isp_idle +#define HIVE_MEM_sem_for_isp_idle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_isp_idle 0x5890 +#else +#define HIVE_ADDR_sem_for_isp_idle 0x592C +#endif +#define HIVE_SIZE_sem_for_isp_idle 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_isp_idle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_isp_idle 0x5890 +#else +#define HIVE_ADDR_sp_sem_for_isp_idle 0x592C +#endif +#define HIVE_SIZE_sp_sem_for_isp_idle 20 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_write_byte_addr: 3B0A */ +#else +/* function ia_css_dmaproxy_sp_write_byte_addr: 3C6A */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_init: 3A81 */ +#else +/* function ia_css_dmaproxy_sp_init: 3BE1 */ +#endif + +#ifndef ISP2401 +/* function ia_css_bufq_sp_release_dynamic_buf_clock_tick: 3686 */ +#else +/* function ia_css_bufq_sp_release_dynamic_buf_clock_tick: 37A9 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_VAMEM_BASE +#define HIVE_MEM_ISP_VAMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_ISP_VAMEM_BASE 0x14 +#define HIVE_SIZE_ISP_VAMEM_BASE 12 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_VAMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ISP_VAMEM_BASE 0x14 +#define HIVE_SIZE_sp_ISP_VAMEM_BASE 12 + +#ifndef ISP2401 +/* function input_system_channel_sync: 11A4 */ +#else +/* function input_system_channel_sync: 6C10 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_rawcopy_sp_tagger +#define HIVE_MEM_ia_css_rawcopy_sp_tagger scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_rawcopy_sp_tagger 0x732C +#else +#define HIVE_ADDR_ia_css_rawcopy_sp_tagger 0x73D8 +#endif +#define HIVE_SIZE_ia_css_rawcopy_sp_tagger 24 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_rawcopy_sp_tagger scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_rawcopy_sp_tagger 0x732C +#else +#define HIVE_ADDR_sp_ia_css_rawcopy_sp_tagger 0x73D8 +#endif +#define HIVE_SIZE_sp_ia_css_rawcopy_sp_tagger 24 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_exp_ids +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_exp_ids scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_exp_ids 0x6A2C +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_exp_ids 0x6AD8 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_exp_ids 70 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_exp_ids scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_exp_ids 0x6A2C +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_exp_ids 0x6AD8 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_exp_ids 70 + +#ifndef ISP2401 +/* function ia_css_queue_item_load: 561A */ +#else +/* function ia_css_queue_item_load: 57F9 */ +#endif + +#ifndef ISP2401 +/* function ia_css_spctrl_sp_get_state: 5DE6 */ +#else +/* function ia_css_spctrl_sp_get_state: 5EC8 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_callout_sp_thread +#define HIVE_MEM_callout_sp_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_callout_sp_thread 0x5A74 +#else +#define HIVE_ADDR_callout_sp_thread 0x278 +#endif +#define HIVE_SIZE_callout_sp_thread 4 +#else +#endif +#endif +#define HIVE_MEM_sp_callout_sp_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_callout_sp_thread 0x5A74 +#else +#define HIVE_ADDR_sp_callout_sp_thread 0x278 +#endif +#define HIVE_SIZE_sp_callout_sp_thread 4 + +#ifndef ISP2401 +/* function thread_fiber_sp_init: 14CB */ +#else +/* function thread_fiber_sp_init: 1441 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_SP_PMEM_BASE +#define HIVE_MEM_SP_PMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_SP_PMEM_BASE 0x0 +#define HIVE_SIZE_SP_PMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_SP_PMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_SP_PMEM_BASE 0x0 +#define HIVE_SIZE_sp_SP_PMEM_BASE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_isp_input_stream_format +#define HIVE_MEM_sp_isp_input_stream_format scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_input_stream_format 0x3E2C +#else +#define HIVE_ADDR_sp_isp_input_stream_format 0x3E50 +#endif +#define HIVE_SIZE_sp_isp_input_stream_format 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_isp_input_stream_format scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_isp_input_stream_format 0x3E2C +#else +#define HIVE_ADDR_sp_sp_isp_input_stream_format 0x3E50 +#endif +#define HIVE_SIZE_sp_sp_isp_input_stream_format 20 + +#ifndef ISP2401 +/* function __mod: 6866 */ +#else +/* function __mod: 6A64 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_init_dmem_channel: 3B6B */ +#else +/* function ia_css_dmaproxy_sp_init_dmem_channel: 3CCB */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_join: 139B */ +#else +/* function ia_css_thread_sp_join: 1311 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_add_command: 6EF1 */ +#else +/* function ia_css_dmaproxy_sp_add_command: 712E */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_metadata_thread_func: 5DDF */ +#else +/* function ia_css_sp_metadata_thread_func: 5EC1 */ +#endif + +#ifndef ISP2401 +/* function __sp_event_proxy_func_critical: 6934 */ +#else +/* function __sp_event_proxy_func_critical: 6B32 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_wait_for_isys_stream_N: 5F53 */ +#else +/* function ia_css_pipeline_sp_wait_for_isys_stream_N: 6074 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_metadata_wait: 5DD8 */ +#else +/* function ia_css_sp_metadata_wait: 5EBA */ +#endif + +#ifndef ISP2401 +/* function ia_css_circbuf_peek_from_start: 15A4 */ +#else +/* function ia_css_circbuf_peek_from_start: 151A */ +#endif + +#ifndef ISP2401 +/* function ia_css_event_sp_encode: 3E76 */ +#else +/* function ia_css_event_sp_encode: 3FEB */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_run: 140E */ +#else +/* function ia_css_thread_sp_run: 1384 */ +#endif + +#ifndef ISP2401 +/* function sp_isys_copy_func: 618 */ +#else +/* function sp_isys_copy_func: 5AC */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_isp_param_init_isp_memories: 50A3 */ +#else +/* function ia_css_sp_isp_param_init_isp_memories: 52AC */ +#endif + +#ifndef ISP2401 +/* function register_isr: 921 */ +#else +/* function register_isr: 8B5 */ +#endif + +/* function irq_raise: C8 */ + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_mmu_invalidate: 3A48 */ +#else +/* function ia_css_dmaproxy_sp_mmu_invalidate: 3B71 */ +#endif + +#ifndef ISP2401 +/* function csi_rx_backend_disable: C34 */ +#else +/* function csi_rx_backend_disable: C2E */ +#endif + +#ifndef ISP2401 +/* function pipeline_sp_initialize_stage: 2104 */ +#else +/* function pipeline_sp_initialize_stage: 20BF */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_N_CSI_RX_FE_CTRL_DLANES +#define HIVE_MEM_N_CSI_RX_FE_CTRL_DLANES scalar_processor_2400_dmem +#define HIVE_ADDR_N_CSI_RX_FE_CTRL_DLANES 0x1C4 +#define HIVE_SIZE_N_CSI_RX_FE_CTRL_DLANES 12 +#else +#endif +#endif +#define HIVE_MEM_sp_N_CSI_RX_FE_CTRL_DLANES scalar_processor_2400_dmem +#define HIVE_ADDR_sp_N_CSI_RX_FE_CTRL_DLANES 0x1C4 +#define HIVE_SIZE_sp_N_CSI_RX_FE_CTRL_DLANES 12 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_read_byte_addr_mmio: 6DC0 */ +#else +/* function ia_css_dmaproxy_sp_read_byte_addr_mmio: 700E */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_done_ds: 40BD */ +#else +/* function ia_css_ispctrl_sp_done_ds: 426D */ +#endif + +#ifndef ISP2401 +/* function csi_rx_backend_config: C8B */ +#else +/* function csi_rx_backend_config: C85 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_isp_param_get_mem_inits: 507E */ +#else +/* function ia_css_sp_isp_param_get_mem_inits: 5287 */ +#endif + +#ifndef ISP2401 +/* function ia_css_parambuf_sp_init_buffer_queues: 1A85 */ +#else +/* function ia_css_parambuf_sp_init_buffer_queues: 1A27 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_vbuf_pfp_spref +#define HIVE_MEM_vbuf_pfp_spref scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_vbuf_pfp_spref 0x378 +#else +#define HIVE_ADDR_vbuf_pfp_spref 0x390 +#endif +#define HIVE_SIZE_vbuf_pfp_spref 4 +#else +#endif +#endif +#define HIVE_MEM_sp_vbuf_pfp_spref scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_vbuf_pfp_spref 0x378 +#else +#define HIVE_ADDR_sp_vbuf_pfp_spref 0x390 +#endif +#define HIVE_SIZE_sp_vbuf_pfp_spref 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_HMEM_BASE +#define HIVE_MEM_ISP_HMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_ISP_HMEM_BASE 0x20 +#define HIVE_SIZE_ISP_HMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_HMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ISP_HMEM_BASE 0x20 +#define HIVE_SIZE_sp_ISP_HMEM_BASE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_frames +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_frames scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_frames 0x6A74 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_frames 0x6B20 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_frames 280 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_frames scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_frames 0x6A74 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_frames 0x6B20 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_frames 280 + +#ifndef ISP2401 +/* function qos_scheduler_init_stage_budget: 65A7 */ +#else +/* function qos_scheduler_init_stage_budget: 679A */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp2host_buffer_queue_handle +#define HIVE_MEM_sp2host_buffer_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp2host_buffer_queue_handle 0x6B8C +#else +#define HIVE_ADDR_sp2host_buffer_queue_handle 0x6C38 +#endif +#define HIVE_SIZE_sp2host_buffer_queue_handle 96 +#else +#endif +#endif +#define HIVE_MEM_sp_sp2host_buffer_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp2host_buffer_queue_handle 0x6B8C +#else +#define HIVE_ADDR_sp_sp2host_buffer_queue_handle 0x6C38 +#endif +#define HIVE_SIZE_sp_sp2host_buffer_queue_handle 96 + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_init_isp_vars: 4D9D */ +#else +/* function ia_css_ispctrl_sp_init_isp_vars: 4F79 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_stream_start: 6010 */ +#else +/* function ia_css_isys_stream_start: 6187 */ +#endif + +#ifndef ISP2401 +/* function sp_warning: 954 */ +#else +/* function sp_warning: 8E8 */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_vbuf_enqueue: 62DC */ +#else +/* function ia_css_rmgr_sp_vbuf_enqueue: 64A2 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_tag_exp_id: 2A84 */ +#else +/* function ia_css_tagger_sp_tag_exp_id: 2A55 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_sfi_release_current_frame: 276B */ +#else +/* function ia_css_pipeline_sp_sfi_release_current_frame: 273C */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_write: 3B21 */ +#else +/* function ia_css_dmaproxy_sp_write: 3C81 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_stream_start_async: 608A */ +#else +/* function ia_css_isys_stream_start_async: 6250 */ +#endif + +#ifndef ISP2401 +/* function ia_css_parambuf_sp_release_in_param: 1905 */ +#else +/* function ia_css_parambuf_sp_release_in_param: 187B */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_irq_sw_interrupt_token +#define HIVE_MEM_irq_sw_interrupt_token scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_irq_sw_interrupt_token 0x3E28 +#else +#define HIVE_ADDR_irq_sw_interrupt_token 0x3E4C +#endif +#define HIVE_SIZE_irq_sw_interrupt_token 4 +#else +#endif +#endif +#define HIVE_MEM_sp_irq_sw_interrupt_token scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_irq_sw_interrupt_token 0x3E28 +#else +#define HIVE_ADDR_sp_irq_sw_interrupt_token 0x3E4C +#endif +#define HIVE_SIZE_sp_irq_sw_interrupt_token 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_isp_addresses +#define HIVE_MEM_sp_isp_addresses scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_addresses 0x6FDC +#else +#define HIVE_ADDR_sp_isp_addresses 0x708C +#endif +#define HIVE_SIZE_sp_isp_addresses 172 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_isp_addresses scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_isp_addresses 0x6FDC +#else +#define HIVE_ADDR_sp_sp_isp_addresses 0x708C +#endif +#define HIVE_SIZE_sp_sp_isp_addresses 172 + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_acq_gen: 6201 */ +#else +/* function ia_css_rmgr_sp_acq_gen: 63C7 */ +#endif + +#ifndef ISP2401 +/* function input_system_input_port_open: 10ED */ +#else +/* function input_system_input_port_open: 10E7 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isps +#define HIVE_MEM_isps scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isps 0x737C +#else +#define HIVE_ADDR_isps 0x7428 +#endif +#define HIVE_SIZE_isps 28 +#else +#endif +#endif +#define HIVE_MEM_sp_isps scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isps 0x737C +#else +#define HIVE_ADDR_sp_isps 0x7428 +#endif +#define HIVE_SIZE_sp_isps 28 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host_sp_queues_initialized +#define HIVE_MEM_host_sp_queues_initialized scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host_sp_queues_initialized 0x3E40 +#else +#define HIVE_ADDR_host_sp_queues_initialized 0x3E64 +#endif +#define HIVE_SIZE_host_sp_queues_initialized 4 +#else +#endif +#endif +#define HIVE_MEM_sp_host_sp_queues_initialized scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host_sp_queues_initialized 0x3E40 +#else +#define HIVE_ADDR_sp_host_sp_queues_initialized 0x3E64 +#endif +#define HIVE_SIZE_sp_host_sp_queues_initialized 4 + +#ifndef ISP2401 +/* function ia_css_queue_uninit: 54E6 */ +#else +/* function ia_css_queue_uninit: 56C5 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_ispctrl_sp_isp_started +#define HIVE_MEM_ia_css_ispctrl_sp_isp_started scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_ispctrl_sp_isp_started 0x6C94 +#else +#define HIVE_ADDR_ia_css_ispctrl_sp_isp_started 0x6D40 +#endif +#define HIVE_SIZE_ia_css_ispctrl_sp_isp_started 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_ispctrl_sp_isp_started scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_ispctrl_sp_isp_started 0x6C94 +#else +#define HIVE_ADDR_sp_ia_css_ispctrl_sp_isp_started 0x6D40 +#endif +#define HIVE_SIZE_sp_ia_css_ispctrl_sp_isp_started 4 + +#ifndef ISP2401 +/* function ia_css_bufq_sp_release_dynamic_buf: 36F2 */ +#else +/* function ia_css_bufq_sp_release_dynamic_buf: 3815 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_set_height_exception: 3C19 */ +#else +/* function ia_css_dmaproxy_sp_set_height_exception: 3D8E */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_init_vmem_channel: 3B9E */ +#else +/* function ia_css_dmaproxy_sp_init_vmem_channel: 3CFF */ +#endif + +#ifndef ISP2401 +/* function csi_rx_backend_stop: C57 */ +#else +/* function csi_rx_backend_stop: C51 */ +#endif + +#ifndef ISP2401 +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_num_ready_threads +#define HIVE_MEM_num_ready_threads scalar_processor_2400_dmem +#define HIVE_ADDR_num_ready_threads 0x5A7C +#define HIVE_SIZE_num_ready_threads 4 +#else +#endif +#endif +#define HIVE_MEM_sp_num_ready_threads scalar_processor_2400_dmem +#define HIVE_ADDR_sp_num_ready_threads 0x5A7C +#define HIVE_SIZE_sp_num_ready_threads 4 + +/* function ia_css_dmaproxy_sp_write_byte_addr_mmio: 3AF3 */ +#else +/* function ia_css_dmaproxy_sp_write_byte_addr_mmio: 3C53 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_vbuf_spref +#define HIVE_MEM_vbuf_spref scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_vbuf_spref 0x374 +#else +#define HIVE_ADDR_vbuf_spref 0x38C +#endif +#define HIVE_SIZE_vbuf_spref 4 +#else +#endif +#endif +#define HIVE_MEM_sp_vbuf_spref scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_vbuf_spref 0x374 +#else +#define HIVE_ADDR_sp_vbuf_spref 0x38C +#endif +#define HIVE_SIZE_sp_vbuf_spref 4 + +#ifndef ISP2401 +/* function ia_css_queue_enqueue: 5430 */ +#else +/* function ia_css_queue_enqueue: 560F */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_flash_sp_request +#define HIVE_MEM_ia_css_flash_sp_request scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_flash_sp_request 0x5B30 +#else +#define HIVE_ADDR_ia_css_flash_sp_request 0x5BDC +#endif +#define HIVE_SIZE_ia_css_flash_sp_request 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_flash_sp_request scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_flash_sp_request 0x5B30 +#else +#define HIVE_ADDR_sp_ia_css_flash_sp_request 0x5BDC +#endif +#define HIVE_SIZE_sp_ia_css_flash_sp_request 4 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_vmem_write: 3AC4 */ +#else +/* function ia_css_dmaproxy_sp_vmem_write: 3C24 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_tagger_frames +#define HIVE_MEM_tagger_frames scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_tagger_frames 0x5A84 +#else +#define HIVE_ADDR_tagger_frames 0x5B30 +#endif +#define HIVE_SIZE_tagger_frames 168 +#else +#endif +#endif +#define HIVE_MEM_sp_tagger_frames scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_tagger_frames 0x5A84 +#else +#define HIVE_ADDR_sp_tagger_frames 0x5B30 +#endif +#define HIVE_SIZE_sp_tagger_frames 168 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_reading_if +#define HIVE_MEM_sem_for_reading_if scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_reading_if 0x58A4 +#else +#define HIVE_ADDR_sem_for_reading_if 0x5940 +#endif +#define HIVE_SIZE_sem_for_reading_if 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_reading_if scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_reading_if 0x58A4 +#else +#define HIVE_ADDR_sp_sem_for_reading_if 0x5940 +#endif +#define HIVE_SIZE_sp_sem_for_reading_if 20 + +#ifndef ISP2401 +/* function sp_generate_interrupts: 9D3 */ +#else +/* function sp_generate_interrupts: 967 */ + +/* function ia_css_pipeline_sp_start: 1FC2 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_start: 2007 */ +#else +/* function ia_css_thread_default_callout: 6C8F */ +#endif + +#ifndef ISP2401 +/* function csi_rx_backend_enable: C45 */ +#else +/* function csi_rx_backend_enable: C3F */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_rawcopy_init: 5953 */ +#else +/* function ia_css_sp_rawcopy_init: 5B32 */ +#endif + +#ifndef ISP2401 +/* function input_system_input_port_configure: 113F */ +#else +/* function input_system_input_port_configure: 1139 */ +#endif + +#ifndef ISP2401 +/* function tmr_clock_read: 16EF */ +#else +/* function tmr_clock_read: 1665 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_BAMEM_BASE +#define HIVE_MEM_ISP_BAMEM_BASE scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ISP_BAMEM_BASE 0x380 +#else +#define HIVE_ADDR_ISP_BAMEM_BASE 0x398 +#endif +#define HIVE_SIZE_ISP_BAMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_BAMEM_BASE scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ISP_BAMEM_BASE 0x380 +#else +#define HIVE_ADDR_sp_ISP_BAMEM_BASE 0x398 +#endif +#define HIVE_SIZE_sp_ISP_BAMEM_BASE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_sems_for_sp2host_buf_queues +#define HIVE_MEM_ia_css_bufq_sp_sems_for_sp2host_buf_queues scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x6BEC +#else +#define HIVE_ADDR_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x6C98 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_sems_for_sp2host_buf_queues 160 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x6BEC +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x6C98 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues 160 + +#ifndef ISP2401 +/* function isys2401_dma_config_legacy: DE0 */ +#else +/* function isys2401_dma_config_legacy: DDA */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ibuf_ctrl_master_ports +#define HIVE_MEM_ibuf_ctrl_master_ports scalar_processor_2400_dmem +#define HIVE_ADDR_ibuf_ctrl_master_ports 0x208 +#define HIVE_SIZE_ibuf_ctrl_master_ports 12 +#else +#endif +#endif +#define HIVE_MEM_sp_ibuf_ctrl_master_ports scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ibuf_ctrl_master_ports 0x208 +#define HIVE_SIZE_sp_ibuf_ctrl_master_ports 12 + +#ifndef ISP2401 +/* function css_get_frame_processing_time_start: 28F1 */ +#else +/* function css_get_frame_processing_time_start: 28C2 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cbs_frame +#define HIVE_MEM_sp_all_cbs_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cbs_frame 0x58B8 +#else +#define HIVE_ADDR_sp_all_cbs_frame 0x5954 +#endif +#define HIVE_SIZE_sp_all_cbs_frame 16 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cbs_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cbs_frame 0x58B8 +#else +#define HIVE_ADDR_sp_sp_all_cbs_frame 0x5954 +#endif +#define HIVE_SIZE_sp_sp_all_cbs_frame 16 + +#ifndef ISP2401 +/* function ia_css_virtual_isys_sp_isr: 6F07 */ +#else +/* function ia_css_virtual_isys_sp_isr: 716E */ +#endif + +#ifndef ISP2401 +/* function thread_sp_queue_print: 142B */ +#else +/* function thread_sp_queue_print: 13A1 */ +#endif + +#ifndef ISP2401 +/* function sp_notify_eof: 97F */ +#else +/* function sp_notify_eof: 913 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_str2mem +#define HIVE_MEM_sem_for_str2mem scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_str2mem 0x58C8 +#else +#define HIVE_ADDR_sem_for_str2mem 0x5964 +#endif +#define HIVE_SIZE_sem_for_str2mem 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_str2mem scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_str2mem 0x58C8 +#else +#define HIVE_ADDR_sp_sem_for_str2mem 0x5964 +#endif +#define HIVE_SIZE_sp_sem_for_str2mem 20 + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_is_marked_from_start: 3483 */ +#else +/* function ia_css_tagger_buf_sp_is_marked_from_start: 35A6 */ +#endif + +#ifndef ISP2401 +/* function ia_css_bufq_sp_acquire_dynamic_buf: 38AA */ +#else +/* function ia_css_bufq_sp_acquire_dynamic_buf: 39CD */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_sfi_mode_is_enabled: 28BF */ +#else +/* function ia_css_pipeline_sp_sfi_mode_is_enabled: 2890 */ +#endif + +#ifndef ISP2401 +/* function ia_css_circbuf_destroy: 16B9 */ +#else +/* function ia_css_circbuf_destroy: 162F */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_PMEM_BASE +#define HIVE_MEM_ISP_PMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_ISP_PMEM_BASE 0xC +#define HIVE_SIZE_ISP_PMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_PMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ISP_PMEM_BASE 0xC +#define HIVE_SIZE_sp_ISP_PMEM_BASE 4 + +#ifndef ISP2401 +/* function ia_css_sp_isp_param_mem_load: 5011 */ +#else +/* function ia_css_sp_isp_param_mem_load: 521A */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_pop_from_start: 326F */ +#else +/* function ia_css_tagger_buf_sp_pop_from_start: 3392 */ +#endif + +#ifndef ISP2401 +/* function __div: 681E */ +#else +/* function __div: 6A1C */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_refcount_release_vbuf: 62FB */ +#else +/* function ia_css_rmgr_sp_refcount_release_vbuf: 64C1 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_flash_sp_in_use +#define HIVE_MEM_ia_css_flash_sp_in_use scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_flash_sp_in_use 0x5B34 +#else +#define HIVE_ADDR_ia_css_flash_sp_in_use 0x5BE0 +#endif +#define HIVE_SIZE_ia_css_flash_sp_in_use 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_flash_sp_in_use scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_flash_sp_in_use 0x5B34 +#else +#define HIVE_ADDR_sp_ia_css_flash_sp_in_use 0x5BE0 +#endif +#define HIVE_SIZE_sp_ia_css_flash_sp_in_use 4 + +#ifndef ISP2401 +/* function ia_css_thread_sem_sp_wait: 6AE4 */ +#else +/* function ia_css_thread_sem_sp_wait: 6D63 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_sleep_mode +#define HIVE_MEM_sp_sleep_mode scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sleep_mode 0x3E44 +#else +#define HIVE_ADDR_sp_sleep_mode 0x3E68 +#endif +#define HIVE_SIZE_sp_sleep_mode 4 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_sleep_mode scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_sleep_mode 0x3E44 +#else +#define HIVE_ADDR_sp_sp_sleep_mode 0x3E68 +#endif +#define HIVE_SIZE_sp_sp_sleep_mode 4 + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_push: 337E */ +#else +/* function ia_css_tagger_buf_sp_push: 34A1 */ +#endif + +/* function mmu_invalidate_cache: D3 */ + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_max_cb_elems +#define HIVE_MEM_sp_max_cb_elems scalar_processor_2400_dmem +#define HIVE_ADDR_sp_max_cb_elems 0x148 +#define HIVE_SIZE_sp_max_cb_elems 8 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_max_cb_elems scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_max_cb_elems 0x148 +#define HIVE_SIZE_sp_sp_max_cb_elems 8 + +#ifndef ISP2401 +/* function ia_css_queue_remote_init: 5508 */ +#else +/* function ia_css_queue_remote_init: 56E7 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isp_stop_req +#define HIVE_MEM_isp_stop_req scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isp_stop_req 0x575C +#else +#define HIVE_ADDR_isp_stop_req 0x57F8 +#endif +#define HIVE_SIZE_isp_stop_req 4 +#else +#endif +#endif +#define HIVE_MEM_sp_isp_stop_req scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_stop_req 0x575C +#else +#define HIVE_ADDR_sp_isp_stop_req 0x57F8 +#endif +#define HIVE_SIZE_sp_isp_stop_req 4 + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_sfi_request_next_frame: 2781 */ +#else +/* function ia_css_pipeline_sp_sfi_request_next_frame: 2752 */ +#endif + +#ifndef ISP2401 +#define HIVE_ICACHE_sp_critical_SEGMENT_START 0 +#define HIVE_ICACHE_sp_critical_NUM_SEGMENTS 1 +#endif + +#endif /* _sp_map_h_ */ +#ifndef ISP2401 +extern void sh_css_dump_sp_dmem(void); +void sh_css_dump_sp_dmem(void) +{ +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/system_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/system_global.h new file mode 100644 index 0000000000000000000000000000000000000000..9f7ecac4627361871ac27524aca54ed7ecf1e58e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_csi2p_system/system_global.h @@ -0,0 +1,458 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SYSTEM_GLOBAL_H_INCLUDED__ +#define __SYSTEM_GLOBAL_H_INCLUDED__ + +#include +#include + +/* + * The longest allowed (uninteruptible) bus transfer, does not + * take stalling into account + */ +#define HIVE_ISP_MAX_BURST_LENGTH 1024 + +/* + * Maximum allowed burst length in words for the ISP DMA + * This value is set to 2 to prevent the ISP DMA from blocking + * the bus for too long; as the input system can only buffer + * 2 lines on Moorefield and Cherrytrail, the input system buffers + * may overflow if blocked for too long (BZ 2726). + */ +#define ISP_DMA_MAX_BURST_LENGTH 2 + +/* + * Create a list of HAS and IS properties that defines the system + * + * The configuration assumes the following + * - The system is hetereogeneous; Multiple cells and devices classes + * - The cell and device instances are homogeneous, each device type + * belongs to the same class + * - Device instances supporting a subset of the class capabilities are + * allowed + * + * We could manage different device classes through the enumerated + * lists (C) or the use of classes (C++), but that is presently not + * fully supported + * + * N.B. the 3 input formatters are of 2 different classess + */ + +#define USE_INPUT_SYSTEM_VERSION_2401 + +#define IS_ISP_2400_SYSTEM +/* + * Since this file is visible everywhere and the system definition + * macros are not, detect the separate definitions for {host, SP, ISP} + * + * The 2401 system has the nice property that it uses a vanilla 2400 SP + * so the SP will believe it is a 2400 system rather than 2401... + */ +/* #if defined(SYSTEM_hive_isp_css_2401_system) || defined(__isp2401_mamoiada) || defined(__scalar_processor_2401) */ +#if defined(SYSTEM_hive_isp_css_2401_system) || defined(__isp2401_mamoiada) +#define IS_ISP_2401_MAMOIADA_SYSTEM +#define HAS_ISP_2401_MAMOIADA +#define HAS_SP_2400 +/* #elif defined(SYSTEM_hive_isp_css_2400_system) || defined(__isp2400_mamoiada) || defined(__scalar_processor_2400)*/ +#elif defined(SYSTEM_hive_isp_css_2400_system) || defined(__isp2400_mamoiada) +#define IS_ISP_2400_MAMOIADA_SYSTEM +#define HAS_ISP_2400_MAMOIADA +#define HAS_SP_2400 +#else +#error "system_global.h: 2400_SYSTEM must be one of {2400, 2401 }" +#endif + +#define HAS_MMU_VERSION_2 +#define HAS_DMA_VERSION_2 +#define HAS_GDC_VERSION_2 +#define HAS_VAMEM_VERSION_2 +#define HAS_HMEM_VERSION_1 +#define HAS_BAMEM_VERSION_2 +#define HAS_IRQ_VERSION_2 +#define HAS_IRQ_MAP_VERSION_2 +#define HAS_INPUT_FORMATTER_VERSION_2 +/* 2401: HAS_INPUT_SYSTEM_VERSION_3 */ +/* 2400: HAS_INPUT_SYSTEM_VERSION_2 */ +#define HAS_INPUT_SYSTEM_VERSION_2 +#define HAS_INPUT_SYSTEM_VERSION_2401 +#define HAS_BUFFERED_SENSOR +#define HAS_FIFO_MONITORS_VERSION_2 +/* #define HAS_GP_REGS_VERSION_2 */ +#define HAS_GP_DEVICE_VERSION_2 +#define HAS_GPIO_VERSION_1 +#define HAS_TIMED_CTRL_VERSION_1 +#define HAS_RX_VERSION_2 +#define HAS_NO_INPUT_FORMATTER +/*#define HAS_NO_PACKED_RAW_PIXELS*/ +/*#define HAS_NO_DVS_6AXIS_CONFIG_UPDATE*/ + +#define DMA_DDR_TO_VAMEM_WORKAROUND +#define DMA_DDR_TO_HMEM_WORKAROUND + + +/* + * Semi global. "HRT" is accessible from SP, but + * the HRT types do not fully apply + */ +#define HRT_VADDRESS_WIDTH 32 +/* Surprise, this is a local property*/ +/*#define HRT_ADDRESS_WIDTH 64 */ +#define HRT_DATA_WIDTH 32 + +#define SIZEOF_HRT_REG (HRT_DATA_WIDTH>>3) +#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH/8) + +/* The main bus connecting all devices */ +#define HRT_BUS_WIDTH HIVE_ISP_CTRL_DATA_WIDTH +#define HRT_BUS_BYTES HIVE_ISP_CTRL_DATA_BYTES + +#define CSI2P_DISABLE_ISYS2401_ONLINE_MODE + +/* per-frame parameter handling support */ +#define SH_CSS_ENABLE_PER_FRAME_PARAMS + +typedef uint32_t hrt_bus_align_t; + +/* + * Enumerate the devices, device access through the API is by ID, + * through the DLI by address. The enumerator terminators are used + * to size the wiring arrays and as an exception value. + */ +typedef enum { + DDR0_ID = 0, + N_DDR_ID +} ddr_ID_t; + +typedef enum { + ISP0_ID = 0, + N_ISP_ID +} isp_ID_t; + +typedef enum { + SP0_ID = 0, + N_SP_ID +} sp_ID_t; + +#if defined(IS_ISP_2401_MAMOIADA_SYSTEM) +typedef enum { + MMU0_ID = 0, + MMU1_ID, + N_MMU_ID +} mmu_ID_t; +#elif defined(IS_ISP_2400_MAMOIADA_SYSTEM) +typedef enum { + MMU0_ID = 0, + MMU1_ID, + N_MMU_ID +} mmu_ID_t; +#else +#error "system_global.h: SYSTEM must be one of {2400, 2401}" +#endif + +typedef enum { + DMA0_ID = 0, + N_DMA_ID +} dma_ID_t; + +typedef enum { + GDC0_ID = 0, + GDC1_ID, + N_GDC_ID +} gdc_ID_t; + +/* this extra define is needed because we want to use it also + in the preprocessor, and that doesn't work with enums. + */ +#define N_GDC_ID_CPP 2 + +typedef enum { + VAMEM0_ID = 0, + VAMEM1_ID, + VAMEM2_ID, + N_VAMEM_ID +} vamem_ID_t; + +typedef enum { + BAMEM0_ID = 0, + N_BAMEM_ID +} bamem_ID_t; + +typedef enum { + HMEM0_ID = 0, + N_HMEM_ID +} hmem_ID_t; + +typedef enum { + ISYS_IRQ0_ID = 0, /* port a */ + ISYS_IRQ1_ID, /* port b */ + ISYS_IRQ2_ID, /* port c */ + N_ISYS_IRQ_ID +} isys_irq_ID_t; + +typedef enum { + IRQ0_ID = 0, /* GP IRQ block */ + IRQ1_ID, /* Input formatter */ + IRQ2_ID, /* input system */ + IRQ3_ID, /* input selector */ + N_IRQ_ID +} irq_ID_t; + +typedef enum { + FIFO_MONITOR0_ID = 0, + N_FIFO_MONITOR_ID +} fifo_monitor_ID_t; + +/* + * Deprecated: Since all gp_reg instances are different + * and put in the address maps of other devices we cannot + * enumerate them as that assumes the instrances are the + * same. + * + * We define a single GP_DEVICE containing all gp_regs + * w.r.t. a single base address + * +typedef enum { + GP_REGS0_ID = 0, + N_GP_REGS_ID +} gp_regs_ID_t; + */ +typedef enum { + GP_DEVICE0_ID = 0, + N_GP_DEVICE_ID +} gp_device_ID_t; + +typedef enum { + GP_TIMER0_ID = 0, + GP_TIMER1_ID, + GP_TIMER2_ID, + GP_TIMER3_ID, + GP_TIMER4_ID, + GP_TIMER5_ID, + GP_TIMER6_ID, + GP_TIMER7_ID, + N_GP_TIMER_ID +} gp_timer_ID_t; + +typedef enum { + GPIO0_ID = 0, + N_GPIO_ID +} gpio_ID_t; + +typedef enum { + TIMED_CTRL0_ID = 0, + N_TIMED_CTRL_ID +} timed_ctrl_ID_t; + +typedef enum { + INPUT_FORMATTER0_ID = 0, + INPUT_FORMATTER1_ID, + INPUT_FORMATTER2_ID, + INPUT_FORMATTER3_ID, + N_INPUT_FORMATTER_ID +} input_formatter_ID_t; + +/* The IF RST is outside the IF */ +#define INPUT_FORMATTER0_SRST_OFFSET 0x0824 +#define INPUT_FORMATTER1_SRST_OFFSET 0x0624 +#define INPUT_FORMATTER2_SRST_OFFSET 0x0424 +#define INPUT_FORMATTER3_SRST_OFFSET 0x0224 + +#define INPUT_FORMATTER0_SRST_MASK 0x0001 +#define INPUT_FORMATTER1_SRST_MASK 0x0002 +#define INPUT_FORMATTER2_SRST_MASK 0x0004 +#define INPUT_FORMATTER3_SRST_MASK 0x0008 + +typedef enum { + INPUT_SYSTEM0_ID = 0, + N_INPUT_SYSTEM_ID +} input_system_ID_t; + +typedef enum { + RX0_ID = 0, + N_RX_ID +} rx_ID_t; + +typedef enum { + MIPI_PORT0_ID = 0, + MIPI_PORT1_ID, + MIPI_PORT2_ID, + N_MIPI_PORT_ID +} mipi_port_ID_t; + +#define N_RX_CHANNEL_ID 4 + +/* Generic port enumeration with an internal port type ID */ +typedef enum { + CSI_PORT0_ID = 0, + CSI_PORT1_ID, + CSI_PORT2_ID, + TPG_PORT0_ID, + PRBS_PORT0_ID, + FIFO_PORT0_ID, + MEMORY_PORT0_ID, + N_INPUT_PORT_ID +} input_port_ID_t; + +typedef enum { + CAPTURE_UNIT0_ID = 0, + CAPTURE_UNIT1_ID, + CAPTURE_UNIT2_ID, + ACQUISITION_UNIT0_ID, + DMA_UNIT0_ID, + CTRL_UNIT0_ID, + GPREGS_UNIT0_ID, + FIFO_UNIT0_ID, + IRQ_UNIT0_ID, + N_SUB_SYSTEM_ID +} sub_system_ID_t; + +#define N_CAPTURE_UNIT_ID 3 +#define N_ACQUISITION_UNIT_ID 1 +#define N_CTRL_UNIT_ID 1 + +/* + * Input-buffer Controller. + */ +typedef enum { + IBUF_CTRL0_ID = 0, /* map to ISYS2401_IBUF_CNTRL_A */ + IBUF_CTRL1_ID, /* map to ISYS2401_IBUF_CNTRL_B */ + IBUF_CTRL2_ID, /* map ISYS2401_IBUF_CNTRL_C */ + N_IBUF_CTRL_ID +} ibuf_ctrl_ID_t; +/** end of Input-buffer Controller */ + +/* + * Stream2MMIO. + */ +typedef enum { + STREAM2MMIO0_ID = 0, /* map to ISYS2401_S2M_A */ + STREAM2MMIO1_ID, /* map to ISYS2401_S2M_B */ + STREAM2MMIO2_ID, /* map to ISYS2401_S2M_C */ + N_STREAM2MMIO_ID +} stream2mmio_ID_t; + +typedef enum { + /* + * Stream2MMIO 0 has 8 SIDs that are indexed by + * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID7_ID]. + * + * Stream2MMIO 1 has 4 SIDs that are indexed by + * [STREAM2MMIO_SID0_ID...TREAM2MMIO_SID3_ID]. + * + * Stream2MMIO 2 has 4 SIDs that are indexed by + * [STREAM2MMIO_SID0_ID...STREAM2MMIO_SID3_ID]. + */ + STREAM2MMIO_SID0_ID = 0, + STREAM2MMIO_SID1_ID, + STREAM2MMIO_SID2_ID, + STREAM2MMIO_SID3_ID, + STREAM2MMIO_SID4_ID, + STREAM2MMIO_SID5_ID, + STREAM2MMIO_SID6_ID, + STREAM2MMIO_SID7_ID, + N_STREAM2MMIO_SID_ID +} stream2mmio_sid_ID_t; +/** end of Stream2MMIO */ + +/** + * Input System 2401: CSI-MIPI recevier. + */ +typedef enum { + CSI_RX_BACKEND0_ID = 0, /* map to ISYS2401_MIPI_BE_A */ + CSI_RX_BACKEND1_ID, /* map to ISYS2401_MIPI_BE_B */ + CSI_RX_BACKEND2_ID, /* map to ISYS2401_MIPI_BE_C */ + N_CSI_RX_BACKEND_ID +} csi_rx_backend_ID_t; + +typedef enum { + CSI_RX_FRONTEND0_ID = 0, /* map to ISYS2401_CSI_RX_A */ + CSI_RX_FRONTEND1_ID, /* map to ISYS2401_CSI_RX_B */ + CSI_RX_FRONTEND2_ID, /* map to ISYS2401_CSI_RX_C */ +#define N_CSI_RX_FRONTEND_ID (CSI_RX_FRONTEND2_ID+1) +} csi_rx_frontend_ID_t; + +typedef enum { + CSI_RX_DLANE0_ID = 0, /* map to DLANE0 in CSI RX */ + CSI_RX_DLANE1_ID, /* map to DLANE1 in CSI RX */ + CSI_RX_DLANE2_ID, /* map to DLANE2 in CSI RX */ + CSI_RX_DLANE3_ID, /* map to DLANE3 in CSI RX */ + N_CSI_RX_DLANE_ID +} csi_rx_fe_dlane_ID_t; +/** end of CSI-MIPI receiver */ + +typedef enum { + ISYS2401_DMA0_ID = 0, + N_ISYS2401_DMA_ID +} isys2401_dma_ID_t; + +/** + * Pixel-generator. ("system_global.h") + */ +typedef enum { + PIXELGEN0_ID = 0, + PIXELGEN1_ID, + PIXELGEN2_ID, + N_PIXELGEN_ID +} pixelgen_ID_t; +/** end of pixel-generator. ("system_global.h") */ + +typedef enum { + INPUT_SYSTEM_CSI_PORT0_ID = 0, + INPUT_SYSTEM_CSI_PORT1_ID, + INPUT_SYSTEM_CSI_PORT2_ID, + + INPUT_SYSTEM_PIXELGEN_PORT0_ID, + INPUT_SYSTEM_PIXELGEN_PORT1_ID, + INPUT_SYSTEM_PIXELGEN_PORT2_ID, + + N_INPUT_SYSTEM_INPUT_PORT_ID +} input_system_input_port_ID_t; + +#define N_INPUT_SYSTEM_CSI_PORT 3 + +typedef enum { + ISYS2401_DMA_CHANNEL_0 = 0, + ISYS2401_DMA_CHANNEL_1, + ISYS2401_DMA_CHANNEL_2, + ISYS2401_DMA_CHANNEL_3, + ISYS2401_DMA_CHANNEL_4, + ISYS2401_DMA_CHANNEL_5, + ISYS2401_DMA_CHANNEL_6, + ISYS2401_DMA_CHANNEL_7, + ISYS2401_DMA_CHANNEL_8, + ISYS2401_DMA_CHANNEL_9, + ISYS2401_DMA_CHANNEL_10, + ISYS2401_DMA_CHANNEL_11, + N_ISYS2401_DMA_CHANNEL +} isys2401_dma_channel; + +enum ia_css_isp_memories { + IA_CSS_ISP_PMEM0 = 0, + IA_CSS_ISP_DMEM0, + IA_CSS_ISP_VMEM0, + IA_CSS_ISP_VAMEM0, + IA_CSS_ISP_VAMEM1, + IA_CSS_ISP_VAMEM2, + IA_CSS_ISP_HMEM0, + IA_CSS_SP_DMEM0, + IA_CSS_DDR, + N_IA_CSS_MEMORIES +}; +#define IA_CSS_NUM_MEMORIES 9 +/* For driver compatability */ +#define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES +#define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES + +#endif /* __SYSTEM_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_configs.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_configs.c new file mode 100644 index 0000000000000000000000000000000000000000..325b821f276cf504f5f2cf1b87ad48a9d7c9fc77 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_configs.c @@ -0,0 +1,360 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* Generated code: do not edit or commmit. */ + +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_pipeline.h" +#include "ia_css_isp_configs.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_iterator( + const struct ia_css_binary *binary, + const struct ia_css_iterator_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_iterator() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.iterator.size; + offset = binary->info->mem_offsets.offsets.config->dmem.iterator.offset; + } + if (size) { + ia_css_iterator_config((struct sh_css_isp_iterator_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_iterator() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_copy_output( + const struct ia_css_binary *binary, + const struct ia_css_copy_output_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_copy_output() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.copy_output.size; + offset = binary->info->mem_offsets.offsets.config->dmem.copy_output.offset; + } + if (size) { + ia_css_copy_output_config((struct sh_css_isp_copy_output_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_copy_output() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_crop( + const struct ia_css_binary *binary, + const struct ia_css_crop_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_crop() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.crop.size; + offset = binary->info->mem_offsets.offsets.config->dmem.crop.offset; + } + if (size) { + ia_css_crop_config((struct sh_css_isp_crop_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_crop() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_fpn( + const struct ia_css_binary *binary, + const struct ia_css_fpn_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_fpn() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.fpn.size; + offset = binary->info->mem_offsets.offsets.config->dmem.fpn.offset; + } + if (size) { + ia_css_fpn_config((struct sh_css_isp_fpn_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_fpn() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_dvs( + const struct ia_css_binary *binary, + const struct ia_css_dvs_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_dvs() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.dvs.size; + offset = binary->info->mem_offsets.offsets.config->dmem.dvs.offset; + } + if (size) { + ia_css_dvs_config((struct sh_css_isp_dvs_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_dvs() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_qplane( + const struct ia_css_binary *binary, + const struct ia_css_qplane_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_qplane() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.qplane.size; + offset = binary->info->mem_offsets.offsets.config->dmem.qplane.offset; + } + if (size) { + ia_css_qplane_config((struct sh_css_isp_qplane_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_qplane() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output0( + const struct ia_css_binary *binary, + const struct ia_css_output0_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output0() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.output0.size; + offset = binary->info->mem_offsets.offsets.config->dmem.output0.offset; + } + if (size) { + ia_css_output0_config((struct sh_css_isp_output_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output0() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output1( + const struct ia_css_binary *binary, + const struct ia_css_output1_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output1() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.output1.size; + offset = binary->info->mem_offsets.offsets.config->dmem.output1.offset; + } + if (size) { + ia_css_output1_config((struct sh_css_isp_output_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output1() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output( + const struct ia_css_binary *binary, + const struct ia_css_output_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.output.size; + offset = binary->info->mem_offsets.offsets.config->dmem.output.offset; + } + if (size) { + ia_css_output_config((struct sh_css_isp_output_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_output() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ +#ifdef ISP2401 + +void +ia_css_configure_sc( + const struct ia_css_binary *binary, + const struct ia_css_sc_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_sc() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.sc.size; + offset = binary->info->mem_offsets.offsets.config->dmem.sc.offset; + } + if (size) { + ia_css_sc_config((struct sh_css_isp_sc_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_sc() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ +#endif + +void +ia_css_configure_raw( + const struct ia_css_binary *binary, + const struct ia_css_raw_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_raw() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.raw.size; + offset = binary->info->mem_offsets.offsets.config->dmem.raw.offset; + } + if (size) { + ia_css_raw_config((struct sh_css_isp_raw_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_raw() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_tnr( + const struct ia_css_binary *binary, + const struct ia_css_tnr_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_tnr() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.tnr.size; + offset = binary->info->mem_offsets.offsets.config->dmem.tnr.offset; + } + if (size) { + ia_css_tnr_config((struct sh_css_isp_tnr_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_tnr() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_ref( + const struct ia_css_binary *binary, + const struct ia_css_ref_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_ref() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.ref.size; + offset = binary->info->mem_offsets.offsets.config->dmem.ref.offset; + } + if (size) { + ia_css_ref_config((struct sh_css_isp_ref_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_ref() leave:\n"); +} + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_vf( + const struct ia_css_binary *binary, + const struct ia_css_vf_configuration *config_dmem) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_vf() enter:\n"); + + { + unsigned offset = 0; + unsigned size = 0; + if (binary->info->mem_offsets.offsets.config) { + size = binary->info->mem_offsets.offsets.config->dmem.vf.size; + offset = binary->info->mem_offsets.offsets.config->dmem.vf.offset; + } + if (size) { + ia_css_vf_config((struct sh_css_isp_vf_isp_config *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_CONFIG][IA_CSS_ISP_DMEM].address[offset], + config_dmem, size); } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_configure_vf() leave:\n"); +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_configs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_configs.h new file mode 100644 index 0000000000000000000000000000000000000000..8aacd3dbc05a5263063f91a016f10329c24e61d9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_configs.h @@ -0,0 +1,189 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifdef IA_CSS_INCLUDE_CONFIGURATIONS +#include "isp/kernels/crop/crop_1.0/ia_css_crop.host.h" +#include "isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.h" +#include "isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h" +#include "isp/kernels/ob/ob_1.0/ia_css_ob.host.h" +#include "isp/kernels/output/output_1.0/ia_css_output.host.h" +#include "isp/kernels/qplane/qplane_2/ia_css_qplane.host.h" +#include "isp/kernels/raw/raw_1.0/ia_css_raw.host.h" +#include "isp/kernels/ref/ref_1.0/ia_css_ref.host.h" +#include "isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h" +#ifdef ISP2401 +#include "isp/kernels/sc/sc_1.0/ia_css_sc.host.h" +#endif +#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h" +#include "isp/kernels/vf/vf_1.0/ia_css_vf.host.h" +#include "isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.h" +#include "isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.h" +#endif /* IA_CSS_INCLUDE_CONFIGURATIONS */ +/* Generated code: do not edit or commmit. */ + +#ifndef _IA_CSS_ISP_CONFIG_H +#define _IA_CSS_ISP_CONFIG_H + +/* Code generated by genparam/gencode.c:gen_param_enum() */ + +enum ia_css_configuration_ids { + IA_CSS_ITERATOR_CONFIG_ID, + IA_CSS_COPY_OUTPUT_CONFIG_ID, + IA_CSS_CROP_CONFIG_ID, + IA_CSS_FPN_CONFIG_ID, + IA_CSS_DVS_CONFIG_ID, + IA_CSS_QPLANE_CONFIG_ID, + IA_CSS_OUTPUT0_CONFIG_ID, + IA_CSS_OUTPUT1_CONFIG_ID, + IA_CSS_OUTPUT_CONFIG_ID, +#ifdef ISP2401 + IA_CSS_SC_CONFIG_ID, +#endif + IA_CSS_RAW_CONFIG_ID, + IA_CSS_TNR_CONFIG_ID, + IA_CSS_REF_CONFIG_ID, + IA_CSS_VF_CONFIG_ID, + IA_CSS_NUM_CONFIGURATION_IDS +}; + +/* Code generated by genparam/gencode.c:gen_param_offsets() */ + +struct ia_css_config_memory_offsets { + struct { + struct ia_css_isp_parameter iterator; + struct ia_css_isp_parameter copy_output; + struct ia_css_isp_parameter crop; + struct ia_css_isp_parameter fpn; + struct ia_css_isp_parameter dvs; + struct ia_css_isp_parameter qplane; + struct ia_css_isp_parameter output0; + struct ia_css_isp_parameter output1; + struct ia_css_isp_parameter output; +#ifdef ISP2401 + struct ia_css_isp_parameter sc; +#endif + struct ia_css_isp_parameter raw; + struct ia_css_isp_parameter tnr; + struct ia_css_isp_parameter ref; + struct ia_css_isp_parameter vf; + } dmem; +}; + +#if defined(IA_CSS_INCLUDE_CONFIGURATIONS) + +#include "ia_css_stream.h" /* struct ia_css_stream */ +#include "ia_css_binary.h" /* struct ia_css_binary */ +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_iterator( + const struct ia_css_binary *binary, + const struct ia_css_iterator_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_copy_output( + const struct ia_css_binary *binary, + const struct ia_css_copy_output_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_crop( + const struct ia_css_binary *binary, + const struct ia_css_crop_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_fpn( + const struct ia_css_binary *binary, + const struct ia_css_fpn_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_dvs( + const struct ia_css_binary *binary, + const struct ia_css_dvs_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_qplane( + const struct ia_css_binary *binary, + const struct ia_css_qplane_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output0( + const struct ia_css_binary *binary, + const struct ia_css_output0_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output1( + const struct ia_css_binary *binary, + const struct ia_css_output1_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_output( + const struct ia_css_binary *binary, + const struct ia_css_output_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +#ifdef ISP2401 +void +ia_css_configure_sc( + const struct ia_css_binary *binary, + const struct ia_css_sc_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +#endif +void +ia_css_configure_raw( + const struct ia_css_binary *binary, + const struct ia_css_raw_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_tnr( + const struct ia_css_binary *binary, + const struct ia_css_tnr_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_ref( + const struct ia_css_binary *binary, + const struct ia_css_ref_configuration *config_dmem); + +/* Code generated by genparam/genconfig.c:gen_configure_function() */ + +void +ia_css_configure_vf( + const struct ia_css_binary *binary, + const struct ia_css_vf_configuration *config_dmem); + +#endif /* IA_CSS_INCLUDE_CONFIGURATION */ + +#endif /* _IA_CSS_ISP_CONFIG_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_params.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_params.c new file mode 100644 index 0000000000000000000000000000000000000000..fcc37d12d2279f6f1cf058ee03787475beee01c1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_params.c @@ -0,0 +1,3239 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#define IA_CSS_INCLUDE_PARAMETERS +#include "sh_css_params.h" +#include "isp/kernels/aa/aa_2/ia_css_aa2.host.h" +#include "isp/kernels/anr/anr_1.0/ia_css_anr.host.h" +#include "isp/kernels/anr/anr_2/ia_css_anr2.host.h" +#include "isp/kernels/bh/bh_2/ia_css_bh.host.h" +#include "isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.h" +#include "isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.h" +#include "isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h" +#include "isp/kernels/crop/crop_1.0/ia_css_crop.host.h" +#include "isp/kernels/csc/csc_1.0/ia_css_csc.host.h" +#include "isp/kernels/ctc/ctc_1.0/ia_css_ctc.host.h" +#include "isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.h" +#include "isp/kernels/ctc/ctc2/ia_css_ctc2.host.h" +#include "isp/kernels/de/de_1.0/ia_css_de.host.h" +#include "isp/kernels/de/de_2/ia_css_de2.host.h" +#include "isp/kernels/dp/dp_1.0/ia_css_dp.host.h" +#include "isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds.host.h" +#include "isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h" +#include "isp/kernels/gc/gc_1.0/ia_css_gc.host.h" +#include "isp/kernels/gc/gc_2/ia_css_gc2.host.h" +#include "isp/kernels/macc/macc_1.0/ia_css_macc.host.h" +#include "isp/kernels/macc/macc1_5/ia_css_macc1_5.host.h" +#include "isp/kernels/ob/ob_1.0/ia_css_ob.host.h" +#include "isp/kernels/ob/ob2/ia_css_ob2.host.h" +#include "isp/kernels/output/output_1.0/ia_css_output.host.h" +#include "isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.h" +#include "isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h" +#include "isp/kernels/sc/sc_1.0/ia_css_sc.host.h" +#include "isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.h" +#include "isp/kernels/sdis/sdis_2/ia_css_sdis2.host.h" +#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h" +#include "isp/kernels/uds/uds_1.0/ia_css_uds.host.h" +#include "isp/kernels/wb/wb_1.0/ia_css_wb.host.h" +#include "isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.h" +#include "isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.h" +#include "isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h" +#include "isp/kernels/ynr/ynr_2/ia_css_ynr2.host.h" +#include "isp/kernels/fc/fc_1.0/ia_css_formats.host.h" +#include "isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.h" +#include "isp/kernels/iefd2_6/ia_css_iefd2_6.host.h" +#include "isp/kernels/dpc2/ia_css_dpc2.host.h" +#include "isp/kernels/eed1_8/ia_css_eed1_8.host.h" +#include "isp/kernels/bnlm/ia_css_bnlm.host.h" +#include "isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.h" +/* Generated code: do not edit or commmit. */ + +#include "ia_css_pipeline.h" +#include "ia_css_isp_params.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_aa( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.aa.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.aa.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_aa() enter:\n"); + + ia_css_aa_encode((struct sh_css_isp_aa_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->aa_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_aa() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_anr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.anr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.anr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr() enter:\n"); + + ia_css_anr_encode((struct sh_css_isp_anr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->anr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_anr2( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.anr2.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.anr2.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr2() enter:\n"); + + ia_css_anr2_vmem_encode((struct ia_css_isp_anr2_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->anr_thres, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_anr2() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_bh( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bh.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bh.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() enter:\n"); + + ia_css_bh_encode((struct sh_css_isp_bh_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->s3a_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() leave:\n"); + } + + } + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->hmem0.bh.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->hmem0.bh.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() enter:\n"); + + ia_css_bh_hmem_encode((struct sh_css_isp_bh_hmem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_HMEM0].address[offset], + ¶ms->s3a_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_HMEM0] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bh() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_cnr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.cnr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.cnr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_cnr() enter:\n"); + + ia_css_cnr_encode((struct sh_css_isp_cnr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->cnr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_cnr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_crop( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.crop.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.crop.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_crop() enter:\n"); + + ia_css_crop_encode((struct sh_css_isp_crop_isp_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->crop_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_crop() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_csc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.csc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.csc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_csc() enter:\n"); + + ia_css_csc_encode((struct sh_css_isp_csc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->cc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_csc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_dp( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.dp.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.dp.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_dp() enter:\n"); + + ia_css_dp_encode((struct sh_css_isp_dp_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dp_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_dp() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_bnr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bnr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bnr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bnr() enter:\n"); + + ia_css_bnr_encode((struct sh_css_isp_bnr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->nr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bnr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_de( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.de.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.de.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_de() enter:\n"); + + ia_css_de_encode((struct sh_css_isp_de_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->de_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_de() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ecd( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ecd.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ecd.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ecd() enter:\n"); + + ia_css_ecd_encode((struct sh_css_isp_ecd_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ecd_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ecd() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_formats( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.formats.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.formats.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_formats() enter:\n"); + + ia_css_formats_encode((struct sh_css_isp_formats_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->formats_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_formats() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_fpn( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.fpn.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.fpn.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fpn() enter:\n"); + + ia_css_fpn_encode((struct sh_css_isp_fpn_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->fpn_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fpn() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_gc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.gc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.gc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() enter:\n"); + + ia_css_gc_encode((struct sh_css_isp_gc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->gc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() leave:\n"); + } + + } + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.gc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.gc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() enter:\n"); + + ia_css_gc_vamem_encode((struct sh_css_isp_gc_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM1].address[offset], + ¶ms->gc_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM1] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_gc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ce( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ce.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ce.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ce() enter:\n"); + + ia_css_ce_encode((struct sh_css_isp_ce_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ce_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ce() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_yuv2rgb( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.yuv2rgb.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yuv2rgb() enter:\n"); + + ia_css_yuv2rgb_encode((struct sh_css_isp_csc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->yuv2rgb_cc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yuv2rgb() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_rgb2yuv( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.rgb2yuv.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_rgb2yuv() enter:\n"); + + ia_css_rgb2yuv_encode((struct sh_css_isp_csc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->rgb2yuv_cc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_rgb2yuv() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_r_gamma( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem0.r_gamma.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_r_gamma() enter:\n"); + + ia_css_r_gamma_vamem_encode((struct sh_css_isp_rgb_gamma_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM0].address[offset], + ¶ms->r_gamma_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM0] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_r_gamma() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_g_gamma( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.g_gamma.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_g_gamma() enter:\n"); + + ia_css_g_gamma_vamem_encode((struct sh_css_isp_rgb_gamma_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM1].address[offset], + ¶ms->g_gamma_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM1] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_g_gamma() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_b_gamma( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem2.b_gamma.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_b_gamma() enter:\n"); + + ia_css_b_gamma_vamem_encode((struct sh_css_isp_rgb_gamma_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM2].address[offset], + ¶ms->b_gamma_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM2] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_b_gamma() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_uds( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.uds.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.uds.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_uds() enter:\n"); + + ia_css_uds_encode((struct sh_css_sp_uds_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->uds_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_uds() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_raa( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.raa.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.raa.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_raa() enter:\n"); + + ia_css_raa_encode((struct sh_css_isp_aa_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->raa_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_raa() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_s3a( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.s3a.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.s3a.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_s3a() enter:\n"); + + ia_css_s3a_encode((struct sh_css_isp_s3a_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->s3a_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_s3a() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ob( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ob.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ob.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() enter:\n"); + + ia_css_ob_encode((struct sh_css_isp_ob_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ob_config, +¶ms->stream_configs.ob, size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() leave:\n"); + } + + } + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.ob.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.ob.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() enter:\n"); + + ia_css_ob_vmem_encode((struct sh_css_isp_ob_vmem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->ob_config, +¶ms->stream_configs.ob, size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ob() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_output( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.output.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.output.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_output() enter:\n"); + + ia_css_output_encode((struct sh_css_isp_output_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->output_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_output() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sc() enter:\n"); + + ia_css_sc_encode((struct sh_css_isp_sc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->sc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_bds( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.bds.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.bds.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bds() enter:\n"); + + ia_css_bds_encode((struct sh_css_isp_bds_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->bds_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_bds() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_tnr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.tnr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.tnr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_tnr() enter:\n"); + + ia_css_tnr_encode((struct sh_css_isp_tnr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->tnr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_tnr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_macc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.macc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.macc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_macc() enter:\n"); + + ia_css_macc_encode((struct sh_css_isp_macc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->macc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_macc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis_horicoef( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_horicoef.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horicoef() enter:\n"); + + ia_css_sdis_horicoef_vmem_encode((struct sh_css_isp_sdis_hori_coef_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->dvs_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horicoef() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis_vertcoef( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis_vertcoef.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertcoef() enter:\n"); + + ia_css_sdis_vertcoef_vmem_encode((struct sh_css_isp_sdis_vert_coef_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->dvs_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertcoef() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis_horiproj( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_horiproj.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horiproj() enter:\n"); + + ia_css_sdis_horiproj_encode((struct sh_css_isp_sdis_hori_proj_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dvs_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_horiproj() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis_vertproj( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis_vertproj.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertproj() enter:\n"); + + ia_css_sdis_vertproj_encode((struct sh_css_isp_sdis_vert_proj_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dvs_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis_vertproj() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis2_horicoef( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_horicoef.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horicoef() enter:\n"); + + ia_css_sdis2_horicoef_vmem_encode((struct sh_css_isp_sdis_hori_coef_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->dvs2_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horicoef() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis2_vertcoef( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.sdis2_vertcoef.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertcoef() enter:\n"); + + ia_css_sdis2_vertcoef_vmem_encode((struct sh_css_isp_sdis_vert_coef_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->dvs2_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertcoef() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis2_horiproj( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_horiproj.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horiproj() enter:\n"); + + ia_css_sdis2_horiproj_encode((struct sh_css_isp_sdis_hori_proj_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dvs2_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_horiproj() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_sdis2_vertproj( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.sdis2_vertproj.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertproj() enter:\n"); + + ia_css_sdis2_vertproj_encode((struct sh_css_isp_sdis_vert_proj_tbl *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->dvs2_coefs, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_sdis2_vertproj() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_wb( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.wb.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.wb.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_wb() enter:\n"); + + ia_css_wb_encode((struct sh_css_isp_wb_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->wb_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_wb() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_nr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.nr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.nr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_nr() enter:\n"); + + ia_css_nr_encode((struct sh_css_isp_ynr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->nr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_nr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_yee( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.yee.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.yee.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yee() enter:\n"); + + ia_css_yee_encode((struct sh_css_isp_yee_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->yee_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_yee() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ynr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ynr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ynr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ynr() enter:\n"); + + ia_css_ynr_encode((struct sh_css_isp_yee2_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ynr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ynr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_fc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.fc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.fc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fc() enter:\n"); + + ia_css_fc_encode((struct sh_css_isp_fc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->fc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_fc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_ctc( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.ctc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.ctc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() enter:\n"); + + ia_css_ctc_encode((struct sh_css_isp_ctc_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->ctc_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() leave:\n"); + } + + } + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem0.ctc.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() enter:\n"); + + ia_css_ctc_vamem_encode((struct sh_css_isp_ctc_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM0].address[offset], + ¶ms->ctc_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM0] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_ctc() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_xnr_table( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vamem1.xnr_table.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr_table() enter:\n"); + + ia_css_xnr_table_vamem_encode((struct sh_css_isp_xnr_vamem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VAMEM1].address[offset], + ¶ms->xnr_table, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VAMEM1] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr_table() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_xnr( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.xnr.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.xnr.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr() enter:\n"); + + ia_css_xnr_encode((struct sh_css_isp_xnr_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->xnr_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr() leave:\n"); + } + + } +} + +/* Code generated by genparam/gencode.c:gen_process_function() */ + +static void +ia_css_process_xnr3( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.xnr3.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() enter:\n"); + + ia_css_xnr3_encode((struct sh_css_isp_xnr3_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->xnr3_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() leave:\n"); + } + + } +#ifdef ISP2401 + { + unsigned size = stage->binary->info->mem_offsets.offsets.param->vmem.xnr3.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->vmem.xnr3.offset; + + if (size) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() enter:\n"); + + ia_css_xnr3_vmem_encode((struct sh_css_isp_xnr3_vmem_params *) + &stage->binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_VMEM].address[offset], + ¶ms->xnr3_config, +size); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_VMEM] = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_process_xnr3() leave:\n"); + } + + } +#endif +} + +/* Code generated by genparam/gencode.c:gen_param_process_table() */ + +void (* ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) = { + ia_css_process_aa, + ia_css_process_anr, + ia_css_process_anr2, + ia_css_process_bh, + ia_css_process_cnr, + ia_css_process_crop, + ia_css_process_csc, + ia_css_process_dp, + ia_css_process_bnr, + ia_css_process_de, + ia_css_process_ecd, + ia_css_process_formats, + ia_css_process_fpn, + ia_css_process_gc, + ia_css_process_ce, + ia_css_process_yuv2rgb, + ia_css_process_rgb2yuv, + ia_css_process_r_gamma, + ia_css_process_g_gamma, + ia_css_process_b_gamma, + ia_css_process_uds, + ia_css_process_raa, + ia_css_process_s3a, + ia_css_process_ob, + ia_css_process_output, + ia_css_process_sc, + ia_css_process_bds, + ia_css_process_tnr, + ia_css_process_macc, + ia_css_process_sdis_horicoef, + ia_css_process_sdis_vertcoef, + ia_css_process_sdis_horiproj, + ia_css_process_sdis_vertproj, + ia_css_process_sdis2_horicoef, + ia_css_process_sdis2_vertcoef, + ia_css_process_sdis2_horiproj, + ia_css_process_sdis2_vertproj, + ia_css_process_wb, + ia_css_process_nr, + ia_css_process_yee, + ia_css_process_ynr, + ia_css_process_fc, + ia_css_process_ctc, + ia_css_process_xnr_table, + ia_css_process_xnr, + ia_css_process_xnr3, +}; + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_dp_config(const struct ia_css_isp_parameters *params, + struct ia_css_dp_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_dp_config() enter: " + "config=%p\n",config); + + *config = params->dp_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_dp_config() leave\n"); + ia_css_dp_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_dp_config(struct ia_css_isp_parameters *params, + const struct ia_css_dp_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_dp_config() enter:\n"); + ia_css_dp_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dp_config = *config; + params->config_changed[IA_CSS_DP_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_DP_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_dp_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_wb_config(const struct ia_css_isp_parameters *params, + struct ia_css_wb_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_wb_config() enter: " + "config=%p\n",config); + + *config = params->wb_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_wb_config() leave\n"); + ia_css_wb_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_wb_config(struct ia_css_isp_parameters *params, + const struct ia_css_wb_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_wb_config() enter:\n"); + ia_css_wb_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->wb_config = *config; + params->config_changed[IA_CSS_WB_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_WB_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_wb_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_tnr_config(const struct ia_css_isp_parameters *params, + struct ia_css_tnr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_tnr_config() enter: " + "config=%p\n",config); + + *config = params->tnr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_tnr_config() leave\n"); + ia_css_tnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_tnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_tnr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_tnr_config() enter:\n"); + ia_css_tnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->tnr_config = *config; + params->config_changed[IA_CSS_TNR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_TNR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_tnr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ob_config(const struct ia_css_isp_parameters *params, + struct ia_css_ob_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ob_config() enter: " + "config=%p\n",config); + + *config = params->ob_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ob_config() leave\n"); + ia_css_ob_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ob_config(struct ia_css_isp_parameters *params, + const struct ia_css_ob_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ob_config() enter:\n"); + ia_css_ob_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ob_config = *config; + params->config_changed[IA_CSS_OB_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_OB_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ob_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_de_config(const struct ia_css_isp_parameters *params, + struct ia_css_de_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_de_config() enter: " + "config=%p\n",config); + + *config = params->de_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_de_config() leave\n"); + ia_css_de_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_de_config(struct ia_css_isp_parameters *params, + const struct ia_css_de_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_de_config() enter:\n"); + ia_css_de_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->de_config = *config; + params->config_changed[IA_CSS_DE_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_DE_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_de_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_anr_config(const struct ia_css_isp_parameters *params, + struct ia_css_anr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr_config() enter: " + "config=%p\n",config); + + *config = params->anr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr_config() leave\n"); + ia_css_anr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_anr_config(struct ia_css_isp_parameters *params, + const struct ia_css_anr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_anr_config() enter:\n"); + ia_css_anr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->anr_config = *config; + params->config_changed[IA_CSS_ANR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_ANR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_anr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_anr2_config(const struct ia_css_isp_parameters *params, + struct ia_css_anr_thres *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr2_config() enter: " + "config=%p\n",config); + + *config = params->anr_thres; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_anr2_config() leave\n"); + ia_css_anr2_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_anr2_config(struct ia_css_isp_parameters *params, + const struct ia_css_anr_thres *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_anr2_config() enter:\n"); + ia_css_anr2_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->anr_thres = *config; + params->config_changed[IA_CSS_ANR2_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_ANR2_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_anr2_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ce_config(const struct ia_css_isp_parameters *params, + struct ia_css_ce_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ce_config() enter: " + "config=%p\n",config); + + *config = params->ce_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ce_config() leave\n"); + ia_css_ce_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ce_config(struct ia_css_isp_parameters *params, + const struct ia_css_ce_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ce_config() enter:\n"); + ia_css_ce_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ce_config = *config; + params->config_changed[IA_CSS_CE_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_CE_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ce_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ecd_config(const struct ia_css_isp_parameters *params, + struct ia_css_ecd_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ecd_config() enter: " + "config=%p\n",config); + + *config = params->ecd_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ecd_config() leave\n"); + ia_css_ecd_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ecd_config(struct ia_css_isp_parameters *params, + const struct ia_css_ecd_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ecd_config() enter:\n"); + ia_css_ecd_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ecd_config = *config; + params->config_changed[IA_CSS_ECD_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_ECD_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ecd_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ynr_config(const struct ia_css_isp_parameters *params, + struct ia_css_ynr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ynr_config() enter: " + "config=%p\n",config); + + *config = params->ynr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ynr_config() leave\n"); + ia_css_ynr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ynr_config(struct ia_css_isp_parameters *params, + const struct ia_css_ynr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ynr_config() enter:\n"); + ia_css_ynr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ynr_config = *config; + params->config_changed[IA_CSS_YNR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_YNR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ynr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_fc_config(const struct ia_css_isp_parameters *params, + struct ia_css_fc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_fc_config() enter: " + "config=%p\n",config); + + *config = params->fc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_fc_config() leave\n"); + ia_css_fc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_fc_config(struct ia_css_isp_parameters *params, + const struct ia_css_fc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_fc_config() enter:\n"); + ia_css_fc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->fc_config = *config; + params->config_changed[IA_CSS_FC_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_FC_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_fc_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_cnr_config(const struct ia_css_isp_parameters *params, + struct ia_css_cnr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_cnr_config() enter: " + "config=%p\n",config); + + *config = params->cnr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_cnr_config() leave\n"); + ia_css_cnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_cnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_cnr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_cnr_config() enter:\n"); + ia_css_cnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->cnr_config = *config; + params->config_changed[IA_CSS_CNR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_CNR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_cnr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_macc_config(const struct ia_css_isp_parameters *params, + struct ia_css_macc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_macc_config() enter: " + "config=%p\n",config); + + *config = params->macc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_macc_config() leave\n"); + ia_css_macc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_macc_config(struct ia_css_isp_parameters *params, + const struct ia_css_macc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_macc_config() enter:\n"); + ia_css_macc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->macc_config = *config; + params->config_changed[IA_CSS_MACC_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_MACC_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_macc_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_ctc_config(const struct ia_css_isp_parameters *params, + struct ia_css_ctc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ctc_config() enter: " + "config=%p\n",config); + + *config = params->ctc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_ctc_config() leave\n"); + ia_css_ctc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ctc_config(struct ia_css_isp_parameters *params, + const struct ia_css_ctc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_ctc_config() enter:\n"); + ia_css_ctc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->ctc_config = *config; + params->config_changed[IA_CSS_CTC_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_CTC_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_ctc_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_aa_config(const struct ia_css_isp_parameters *params, + struct ia_css_aa_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_aa_config() enter: " + "config=%p\n",config); + + *config = params->aa_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_aa_config() leave\n"); + ia_css_aa_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_aa_config(struct ia_css_isp_parameters *params, + const struct ia_css_aa_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_aa_config() enter:\n"); + ia_css_aa_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->aa_config = *config; + params->config_changed[IA_CSS_AA_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_AA_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_aa_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_yuv2rgb_config(const struct ia_css_isp_parameters *params, + struct ia_css_cc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_yuv2rgb_config() enter: " + "config=%p\n",config); + + *config = params->yuv2rgb_cc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_yuv2rgb_config() leave\n"); + ia_css_yuv2rgb_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_yuv2rgb_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_yuv2rgb_config() enter:\n"); + ia_css_yuv2rgb_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->yuv2rgb_cc_config = *config; + params->config_changed[IA_CSS_YUV2RGB_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_YUV2RGB_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_yuv2rgb_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_rgb2yuv_config(const struct ia_css_isp_parameters *params, + struct ia_css_cc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_rgb2yuv_config() enter: " + "config=%p\n",config); + + *config = params->rgb2yuv_cc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_rgb2yuv_config() leave\n"); + ia_css_rgb2yuv_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_rgb2yuv_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_rgb2yuv_config() enter:\n"); + ia_css_rgb2yuv_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->rgb2yuv_cc_config = *config; + params->config_changed[IA_CSS_RGB2YUV_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_RGB2YUV_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_rgb2yuv_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_csc_config(const struct ia_css_isp_parameters *params, + struct ia_css_cc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_csc_config() enter: " + "config=%p\n",config); + + *config = params->cc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_csc_config() leave\n"); + ia_css_csc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_csc_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_csc_config() enter:\n"); + ia_css_csc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->cc_config = *config; + params->config_changed[IA_CSS_CSC_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_CSC_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_csc_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_nr_config(const struct ia_css_isp_parameters *params, + struct ia_css_nr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_nr_config() enter: " + "config=%p\n",config); + + *config = params->nr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_nr_config() leave\n"); + ia_css_nr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_nr_config(struct ia_css_isp_parameters *params, + const struct ia_css_nr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_nr_config() enter:\n"); + ia_css_nr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->nr_config = *config; + params->config_changed[IA_CSS_BNR_ID] = true; + params->config_changed[IA_CSS_NR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_NR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_nr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_gc_config(const struct ia_css_isp_parameters *params, + struct ia_css_gc_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_gc_config() enter: " + "config=%p\n",config); + + *config = params->gc_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_gc_config() leave\n"); + ia_css_gc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_gc_config(struct ia_css_isp_parameters *params, + const struct ia_css_gc_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_gc_config() enter:\n"); + ia_css_gc_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->gc_config = *config; + params->config_changed[IA_CSS_GC_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_GC_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_gc_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis_horicoef_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horicoef_config() enter: " + "config=%p\n",config); + + *config = params->dvs_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horicoef_config() leave\n"); + ia_css_sdis_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_horicoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_horicoef_config() enter:\n"); + ia_css_sdis_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs_coefs = *config; + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_horicoef_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis_vertcoef_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertcoef_config() enter: " + "config=%p\n",config); + + *config = params->dvs_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertcoef_config() leave\n"); + ia_css_sdis_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_vertcoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_vertcoef_config() enter:\n"); + ia_css_sdis_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs_coefs = *config; + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_vertcoef_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis_horiproj_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horiproj_config() enter: " + "config=%p\n",config); + + *config = params->dvs_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_horiproj_config() leave\n"); + ia_css_sdis_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_horiproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_horiproj_config() enter:\n"); + ia_css_sdis_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs_coefs = *config; + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_horiproj_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis_vertproj_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertproj_config() enter: " + "config=%p\n",config); + + *config = params->dvs_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis_vertproj_config() leave\n"); + ia_css_sdis_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_vertproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis_vertproj_config() enter:\n"); + ia_css_sdis_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs_coefs = *config; + params->config_changed[IA_CSS_SDIS_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS_VERTPROJ_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis_vertproj_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis2_horicoef_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs2_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horicoef_config() enter: " + "config=%p\n",config); + + *config = params->dvs2_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horicoef_config() leave\n"); + ia_css_sdis2_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_horicoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_horicoef_config() enter:\n"); + ia_css_sdis2_horicoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs2_coefs = *config; + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_horicoef_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis2_vertcoef_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs2_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertcoef_config() enter: " + "config=%p\n",config); + + *config = params->dvs2_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertcoef_config() leave\n"); + ia_css_sdis2_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_vertcoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_vertcoef_config() enter:\n"); + ia_css_sdis2_vertcoef_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs2_coefs = *config; + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_vertcoef_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis2_horiproj_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs2_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horiproj_config() enter: " + "config=%p\n",config); + + *config = params->dvs2_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_horiproj_config() leave\n"); + ia_css_sdis2_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_horiproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_horiproj_config() enter:\n"); + ia_css_sdis2_horiproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs2_coefs = *config; + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_horiproj_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_sdis2_vertproj_config(const struct ia_css_isp_parameters *params, + struct ia_css_dvs2_coefficients *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertproj_config() enter: " + "config=%p\n",config); + + *config = params->dvs2_coefs; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_sdis2_vertproj_config() leave\n"); + ia_css_sdis2_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_vertproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_sdis2_vertproj_config() enter:\n"); + ia_css_sdis2_vertproj_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->dvs2_coefs = *config; + params->config_changed[IA_CSS_SDIS2_HORICOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTCOEF_ID] = true; + params->config_changed[IA_CSS_SDIS2_HORIPROJ_ID] = true; + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_SDIS2_VERTPROJ_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_sdis2_vertproj_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_r_gamma_config(const struct ia_css_isp_parameters *params, + struct ia_css_rgb_gamma_table *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_r_gamma_config() enter: " + "config=%p\n",config); + + *config = params->r_gamma_table; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_r_gamma_config() leave\n"); + ia_css_r_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_r_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_r_gamma_config() enter:\n"); + ia_css_r_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->r_gamma_table = *config; + params->config_changed[IA_CSS_R_GAMMA_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_R_GAMMA_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_r_gamma_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_g_gamma_config(const struct ia_css_isp_parameters *params, + struct ia_css_rgb_gamma_table *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_g_gamma_config() enter: " + "config=%p\n",config); + + *config = params->g_gamma_table; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_g_gamma_config() leave\n"); + ia_css_g_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_g_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_g_gamma_config() enter:\n"); + ia_css_g_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->g_gamma_table = *config; + params->config_changed[IA_CSS_G_GAMMA_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_G_GAMMA_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_g_gamma_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_b_gamma_config(const struct ia_css_isp_parameters *params, + struct ia_css_rgb_gamma_table *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_b_gamma_config() enter: " + "config=%p\n",config); + + *config = params->b_gamma_table; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_b_gamma_config() leave\n"); + ia_css_b_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_b_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_b_gamma_config() enter:\n"); + ia_css_b_gamma_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->b_gamma_table = *config; + params->config_changed[IA_CSS_B_GAMMA_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_B_GAMMA_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_b_gamma_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_xnr_table_config(const struct ia_css_isp_parameters *params, + struct ia_css_xnr_table *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_table_config() enter: " + "config=%p\n",config); + + *config = params->xnr_table; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_table_config() leave\n"); + ia_css_xnr_table_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr_table_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr_table *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr_table_config() enter:\n"); + ia_css_xnr_table_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->xnr_table = *config; + params->config_changed[IA_CSS_XNR_TABLE_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_XNR_TABLE_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr_table_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_formats_config(const struct ia_css_isp_parameters *params, + struct ia_css_formats_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_formats_config() enter: " + "config=%p\n",config); + + *config = params->formats_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_formats_config() leave\n"); + ia_css_formats_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_formats_config(struct ia_css_isp_parameters *params, + const struct ia_css_formats_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_formats_config() enter:\n"); + ia_css_formats_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->formats_config = *config; + params->config_changed[IA_CSS_FORMATS_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_FORMATS_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_formats_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_xnr_config(const struct ia_css_isp_parameters *params, + struct ia_css_xnr_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_config() enter: " + "config=%p\n",config); + + *config = params->xnr_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr_config() leave\n"); + ia_css_xnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr_config() enter:\n"); + ia_css_xnr_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->xnr_config = *config; + params->config_changed[IA_CSS_XNR_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_XNR_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_xnr3_config(const struct ia_css_isp_parameters *params, + struct ia_css_xnr3_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr3_config() enter: " + "config=%p\n",config); + + *config = params->xnr3_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_xnr3_config() leave\n"); + ia_css_xnr3_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr3_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr3_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_xnr3_config() enter:\n"); + ia_css_xnr3_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->xnr3_config = *config; + params->config_changed[IA_CSS_XNR3_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_XNR3_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_xnr3_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_s3a_config(const struct ia_css_isp_parameters *params, + struct ia_css_3a_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_s3a_config() enter: " + "config=%p\n",config); + + *config = params->s3a_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_s3a_config() leave\n"); + ia_css_s3a_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_s3a_config(struct ia_css_isp_parameters *params, + const struct ia_css_3a_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_s3a_config() enter:\n"); + ia_css_s3a_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->s3a_config = *config; + params->config_changed[IA_CSS_BH_ID] = true; + params->config_changed[IA_CSS_S3A_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_S3A_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_s3a_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_get_function() */ + +static void +ia_css_get_output_config(const struct ia_css_isp_parameters *params, + struct ia_css_output_config *config){ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_output_config() enter: " + "config=%p\n",config); + + *config = params->output_config; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_get_output_config() leave\n"); + ia_css_output_debug_dtrace(config, IA_CSS_DEBUG_TRACE); +} + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_output_config(struct ia_css_isp_parameters *params, + const struct ia_css_output_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_set_output_config() enter:\n"); + ia_css_output_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + params->output_config = *config; + params->config_changed[IA_CSS_OUTPUT_ID] = true; +#ifndef ISP2401 + params->config_changed[IA_CSS_OUTPUT_ID] = true; + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_set_output_config() leave: " + "return_void\n"); +} + +/* Code generated by genparam/gencode.c:gen_global_access_function() */ + +void +ia_css_get_configs(struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config) +{ + ia_css_get_dp_config(params, config->dp_config); + ia_css_get_wb_config(params, config->wb_config); + ia_css_get_tnr_config(params, config->tnr_config); + ia_css_get_ob_config(params, config->ob_config); + ia_css_get_de_config(params, config->de_config); + ia_css_get_anr_config(params, config->anr_config); + ia_css_get_anr2_config(params, config->anr_thres); + ia_css_get_ce_config(params, config->ce_config); + ia_css_get_ecd_config(params, config->ecd_config); + ia_css_get_ynr_config(params, config->ynr_config); + ia_css_get_fc_config(params, config->fc_config); + ia_css_get_cnr_config(params, config->cnr_config); + ia_css_get_macc_config(params, config->macc_config); + ia_css_get_ctc_config(params, config->ctc_config); + ia_css_get_aa_config(params, config->aa_config); + ia_css_get_yuv2rgb_config(params, config->yuv2rgb_cc_config); + ia_css_get_rgb2yuv_config(params, config->rgb2yuv_cc_config); + ia_css_get_csc_config(params, config->cc_config); + ia_css_get_nr_config(params, config->nr_config); + ia_css_get_gc_config(params, config->gc_config); + ia_css_get_sdis_horicoef_config(params, config->dvs_coefs); + ia_css_get_sdis_vertcoef_config(params, config->dvs_coefs); + ia_css_get_sdis_horiproj_config(params, config->dvs_coefs); + ia_css_get_sdis_vertproj_config(params, config->dvs_coefs); + ia_css_get_sdis2_horicoef_config(params, config->dvs2_coefs); + ia_css_get_sdis2_vertcoef_config(params, config->dvs2_coefs); + ia_css_get_sdis2_horiproj_config(params, config->dvs2_coefs); + ia_css_get_sdis2_vertproj_config(params, config->dvs2_coefs); + ia_css_get_r_gamma_config(params, config->r_gamma_table); + ia_css_get_g_gamma_config(params, config->g_gamma_table); + ia_css_get_b_gamma_config(params, config->b_gamma_table); + ia_css_get_xnr_table_config(params, config->xnr_table); + ia_css_get_formats_config(params, config->formats_config); + ia_css_get_xnr_config(params, config->xnr_config); + ia_css_get_xnr3_config(params, config->xnr3_config); + ia_css_get_s3a_config(params, config->s3a_config); + ia_css_get_output_config(params, config->output_config); +} + +/* Code generated by genparam/gencode.c:gen_global_access_function() */ + +void +ia_css_set_configs(struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config) +{ + ia_css_set_dp_config(params, config->dp_config); + ia_css_set_wb_config(params, config->wb_config); + ia_css_set_tnr_config(params, config->tnr_config); + ia_css_set_ob_config(params, config->ob_config); + ia_css_set_de_config(params, config->de_config); + ia_css_set_anr_config(params, config->anr_config); + ia_css_set_anr2_config(params, config->anr_thres); + ia_css_set_ce_config(params, config->ce_config); + ia_css_set_ecd_config(params, config->ecd_config); + ia_css_set_ynr_config(params, config->ynr_config); + ia_css_set_fc_config(params, config->fc_config); + ia_css_set_cnr_config(params, config->cnr_config); + ia_css_set_macc_config(params, config->macc_config); + ia_css_set_ctc_config(params, config->ctc_config); + ia_css_set_aa_config(params, config->aa_config); + ia_css_set_yuv2rgb_config(params, config->yuv2rgb_cc_config); + ia_css_set_rgb2yuv_config(params, config->rgb2yuv_cc_config); + ia_css_set_csc_config(params, config->cc_config); + ia_css_set_nr_config(params, config->nr_config); + ia_css_set_gc_config(params, config->gc_config); + ia_css_set_sdis_horicoef_config(params, config->dvs_coefs); + ia_css_set_sdis_vertcoef_config(params, config->dvs_coefs); + ia_css_set_sdis_horiproj_config(params, config->dvs_coefs); + ia_css_set_sdis_vertproj_config(params, config->dvs_coefs); + ia_css_set_sdis2_horicoef_config(params, config->dvs2_coefs); + ia_css_set_sdis2_vertcoef_config(params, config->dvs2_coefs); + ia_css_set_sdis2_horiproj_config(params, config->dvs2_coefs); + ia_css_set_sdis2_vertproj_config(params, config->dvs2_coefs); + ia_css_set_r_gamma_config(params, config->r_gamma_table); + ia_css_set_g_gamma_config(params, config->g_gamma_table); + ia_css_set_b_gamma_config(params, config->b_gamma_table); + ia_css_set_xnr_table_config(params, config->xnr_table); + ia_css_set_formats_config(params, config->formats_config); + ia_css_set_xnr_config(params, config->xnr_config); + ia_css_set_xnr3_config(params, config->xnr3_config); + ia_css_set_s3a_config(params, config->s3a_config); + ia_css_set_output_config(params, config->output_config); +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_params.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_params.h new file mode 100644 index 0000000000000000000000000000000000000000..5b3deb7f74aecf1de25749111f2cc7c81d6cd3e2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_params.h @@ -0,0 +1,399 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* Generated code: do not edit or commmit. */ + +#ifndef _IA_CSS_ISP_PARAM_H +#define _IA_CSS_ISP_PARAM_H + +/* Code generated by genparam/gencode.c:gen_param_enum() */ + +enum ia_css_parameter_ids { + IA_CSS_AA_ID, + IA_CSS_ANR_ID, + IA_CSS_ANR2_ID, + IA_CSS_BH_ID, + IA_CSS_CNR_ID, + IA_CSS_CROP_ID, + IA_CSS_CSC_ID, + IA_CSS_DP_ID, + IA_CSS_BNR_ID, + IA_CSS_DE_ID, + IA_CSS_ECD_ID, + IA_CSS_FORMATS_ID, + IA_CSS_FPN_ID, + IA_CSS_GC_ID, + IA_CSS_CE_ID, + IA_CSS_YUV2RGB_ID, + IA_CSS_RGB2YUV_ID, + IA_CSS_R_GAMMA_ID, + IA_CSS_G_GAMMA_ID, + IA_CSS_B_GAMMA_ID, + IA_CSS_UDS_ID, + IA_CSS_RAA_ID, + IA_CSS_S3A_ID, + IA_CSS_OB_ID, + IA_CSS_OUTPUT_ID, + IA_CSS_SC_ID, + IA_CSS_BDS_ID, + IA_CSS_TNR_ID, + IA_CSS_MACC_ID, + IA_CSS_SDIS_HORICOEF_ID, + IA_CSS_SDIS_VERTCOEF_ID, + IA_CSS_SDIS_HORIPROJ_ID, + IA_CSS_SDIS_VERTPROJ_ID, + IA_CSS_SDIS2_HORICOEF_ID, + IA_CSS_SDIS2_VERTCOEF_ID, + IA_CSS_SDIS2_HORIPROJ_ID, + IA_CSS_SDIS2_VERTPROJ_ID, + IA_CSS_WB_ID, + IA_CSS_NR_ID, + IA_CSS_YEE_ID, + IA_CSS_YNR_ID, + IA_CSS_FC_ID, + IA_CSS_CTC_ID, + IA_CSS_XNR_TABLE_ID, + IA_CSS_XNR_ID, + IA_CSS_XNR3_ID, + IA_CSS_NUM_PARAMETER_IDS +}; + +/* Code generated by genparam/gencode.c:gen_param_offsets() */ + +struct ia_css_memory_offsets { + struct { + struct ia_css_isp_parameter aa; + struct ia_css_isp_parameter anr; + struct ia_css_isp_parameter bh; + struct ia_css_isp_parameter cnr; + struct ia_css_isp_parameter crop; + struct ia_css_isp_parameter csc; + struct ia_css_isp_parameter dp; + struct ia_css_isp_parameter bnr; + struct ia_css_isp_parameter de; + struct ia_css_isp_parameter ecd; + struct ia_css_isp_parameter formats; + struct ia_css_isp_parameter fpn; + struct ia_css_isp_parameter gc; + struct ia_css_isp_parameter ce; + struct ia_css_isp_parameter yuv2rgb; + struct ia_css_isp_parameter rgb2yuv; + struct ia_css_isp_parameter uds; + struct ia_css_isp_parameter raa; + struct ia_css_isp_parameter s3a; + struct ia_css_isp_parameter ob; + struct ia_css_isp_parameter output; + struct ia_css_isp_parameter sc; + struct ia_css_isp_parameter bds; + struct ia_css_isp_parameter tnr; + struct ia_css_isp_parameter macc; + struct ia_css_isp_parameter sdis_horiproj; + struct ia_css_isp_parameter sdis_vertproj; + struct ia_css_isp_parameter sdis2_horiproj; + struct ia_css_isp_parameter sdis2_vertproj; + struct ia_css_isp_parameter wb; + struct ia_css_isp_parameter nr; + struct ia_css_isp_parameter yee; + struct ia_css_isp_parameter ynr; + struct ia_css_isp_parameter fc; + struct ia_css_isp_parameter ctc; + struct ia_css_isp_parameter xnr; + struct ia_css_isp_parameter xnr3; + struct ia_css_isp_parameter get; + struct ia_css_isp_parameter put; + } dmem; + struct { + struct ia_css_isp_parameter anr2; + struct ia_css_isp_parameter ob; + struct ia_css_isp_parameter sdis_horicoef; + struct ia_css_isp_parameter sdis_vertcoef; + struct ia_css_isp_parameter sdis2_horicoef; + struct ia_css_isp_parameter sdis2_vertcoef; +#ifdef ISP2401 + struct ia_css_isp_parameter xnr3; +#endif + } vmem; + struct { + struct ia_css_isp_parameter bh; + } hmem0; + struct { + struct ia_css_isp_parameter gc; + struct ia_css_isp_parameter g_gamma; + struct ia_css_isp_parameter xnr_table; + } vamem1; + struct { + struct ia_css_isp_parameter r_gamma; + struct ia_css_isp_parameter ctc; + } vamem0; + struct { + struct ia_css_isp_parameter b_gamma; + } vamem2; +}; + +#if defined(IA_CSS_INCLUDE_PARAMETERS) + +#include "ia_css_stream.h" /* struct ia_css_stream */ +#include "ia_css_binary.h" /* struct ia_css_binary */ +/* Code generated by genparam/gencode.c:gen_param_process_table() */ + +struct ia_css_pipeline_stage; /* forward declaration */ + +extern void (* ia_css_kernel_process_param[IA_CSS_NUM_PARAMETER_IDS])( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_dp_config(struct ia_css_isp_parameters *params, + const struct ia_css_dp_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_wb_config(struct ia_css_isp_parameters *params, + const struct ia_css_wb_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_tnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_tnr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ob_config(struct ia_css_isp_parameters *params, + const struct ia_css_ob_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_de_config(struct ia_css_isp_parameters *params, + const struct ia_css_de_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_anr_config(struct ia_css_isp_parameters *params, + const struct ia_css_anr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_anr2_config(struct ia_css_isp_parameters *params, + const struct ia_css_anr_thres *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ce_config(struct ia_css_isp_parameters *params, + const struct ia_css_ce_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ecd_config(struct ia_css_isp_parameters *params, + const struct ia_css_ecd_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ynr_config(struct ia_css_isp_parameters *params, + const struct ia_css_ynr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_fc_config(struct ia_css_isp_parameters *params, + const struct ia_css_fc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_cnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_cnr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_macc_config(struct ia_css_isp_parameters *params, + const struct ia_css_macc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_ctc_config(struct ia_css_isp_parameters *params, + const struct ia_css_ctc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_aa_config(struct ia_css_isp_parameters *params, + const struct ia_css_aa_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_yuv2rgb_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_rgb2yuv_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_csc_config(struct ia_css_isp_parameters *params, + const struct ia_css_cc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_nr_config(struct ia_css_isp_parameters *params, + const struct ia_css_nr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_gc_config(struct ia_css_isp_parameters *params, + const struct ia_css_gc_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_horicoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_vertcoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_horiproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis_vertproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_horicoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_vertcoef_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_horiproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_sdis2_vertproj_config(struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_r_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_g_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_b_gamma_config(struct ia_css_isp_parameters *params, + const struct ia_css_rgb_gamma_table *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr_table_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr_table *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_formats_config(struct ia_css_isp_parameters *params, + const struct ia_css_formats_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_xnr3_config(struct ia_css_isp_parameters *params, + const struct ia_css_xnr3_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_s3a_config(struct ia_css_isp_parameters *params, + const struct ia_css_3a_config *config); + +/* Code generated by genparam/gencode.c:gen_set_function() */ + +void +ia_css_set_output_config(struct ia_css_isp_parameters *params, + const struct ia_css_output_config *config); + +/* Code generated by genparam/gencode.c:gen_global_access_function() */ + +void +ia_css_get_configs(struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config) +; +#ifdef ISP2401 + +#endif +/* Code generated by genparam/gencode.c:gen_global_access_function() */ + +void +ia_css_set_configs(struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config) +; +#ifdef ISP2401 + +#endif +#endif /* IA_CSS_INCLUDE_PARAMETER */ + +#endif /* _IA_CSS_ISP_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_states.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_states.c new file mode 100644 index 0000000000000000000000000000000000000000..a445d4f1fa2b44da67712bc6d3a47ee26550bb5e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_states.c @@ -0,0 +1,218 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* Generated code: do not edit or commmit. */ + +#include "ia_css_pipeline.h" +#include "ia_css_isp_states.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_aa_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_aa_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.aa.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.aa.offset; + + if (size) { + ia_css_init_aa_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_aa_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_cnr_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.cnr.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.cnr.offset; + + if (size) { + ia_css_init_cnr_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_cnr2_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr2_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.cnr2.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.cnr2.offset; + + if (size) { + ia_css_init_cnr2_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_cnr2_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_dp_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_dp_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.dp.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.dp.offset; + + if (size) { + ia_css_init_dp_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_dp_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_de_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_de_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.de.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.de.offset; + + if (size) { + ia_css_init_de_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_de_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_tnr_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_tnr_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->dmem.tnr.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->dmem.tnr.offset; + + if (size) { + ia_css_init_tnr_state((struct sh_css_isp_tnr_dmem_state *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_tnr_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_ref_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ref_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->dmem.ref.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->dmem.ref.offset; + + if (size) { + ia_css_init_ref_state((struct sh_css_isp_ref_dmem_state *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_DMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ref_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_init_function() */ + +static void +ia_css_initialize_ynr_state( + const struct ia_css_binary *binary) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ynr_state() enter:\n"); + + { + unsigned size = binary->info->mem_offsets.offsets.state->vmem.ynr.size; + + unsigned offset = binary->info->mem_offsets.offsets.state->vmem.ynr.offset; + + if (size) { + ia_css_init_ynr_state( + &binary->mem_params.params[IA_CSS_PARAM_CLASS_STATE][IA_CSS_ISP_VMEM].address[offset], + size); + } + + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_initialize_ynr_state() leave:\n"); +} + +/* Code generated by genparam/genstate.c:gen_state_init_table() */ + +void (* ia_css_kernel_init_state[IA_CSS_NUM_STATE_IDS])(const struct ia_css_binary *binary) = { + ia_css_initialize_aa_state, + ia_css_initialize_cnr_state, + ia_css_initialize_cnr2_state, + ia_css_initialize_dp_state, + ia_css_initialize_de_state, + ia_css_initialize_tnr_state, + ia_css_initialize_ref_state, + ia_css_initialize_ynr_state, +}; + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_states.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_states.h new file mode 100644 index 0000000000000000000000000000000000000000..d658a005d694ce52062748bccc677b36aa0e50ad --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_states.h @@ -0,0 +1,74 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#define IA_CSS_INCLUDE_STATES +#include "ia_css_memory_access.h" +#include "isp/kernels/aa/aa_2/ia_css_aa2.host.h" +#include "isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.h" +#include "isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h" +#include "isp/kernels/de/de_1.0/ia_css_de.host.h" +#include "isp/kernels/dp/dp_1.0/ia_css_dp.host.h" +#include "isp/kernels/ref/ref_1.0/ia_css_ref.host.h" +#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h" +#include "isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h" +#include "isp/kernels/iefd2_6/ia_css_iefd2_6.host.h" +#include "isp/kernels/dpc2/ia_css_dpc2.host.h" +#include "isp/kernels/eed1_8/ia_css_eed1_8.host.h" +/* Generated code: do not edit or commmit. */ + +#ifndef _IA_CSS_ISP_STATE_H +#define _IA_CSS_ISP_STATE_H + +/* Code generated by genparam/gencode.c:gen_param_enum() */ + +enum ia_css_state_ids { + IA_CSS_AA_STATE_ID, + IA_CSS_CNR_STATE_ID, + IA_CSS_CNR2_STATE_ID, + IA_CSS_DP_STATE_ID, + IA_CSS_DE_STATE_ID, + IA_CSS_TNR_STATE_ID, + IA_CSS_REF_STATE_ID, + IA_CSS_YNR_STATE_ID, + IA_CSS_NUM_STATE_IDS +}; + +/* Code generated by genparam/gencode.c:gen_param_offsets() */ + +struct ia_css_state_memory_offsets { + struct { + struct ia_css_isp_parameter aa; + struct ia_css_isp_parameter cnr; + struct ia_css_isp_parameter cnr2; + struct ia_css_isp_parameter dp; + struct ia_css_isp_parameter de; + struct ia_css_isp_parameter ynr; + } vmem; + struct { + struct ia_css_isp_parameter tnr; + struct ia_css_isp_parameter ref; + } dmem; +}; + +#if defined(IA_CSS_INCLUDE_STATES) + +#include "ia_css_stream.h" /* struct ia_css_stream */ +#include "ia_css_binary.h" /* struct ia_css_binary */ +/* Code generated by genparam/genstate.c:gen_state_init_table() */ + +extern void (* ia_css_kernel_init_state[IA_CSS_NUM_STATE_IDS])(const struct ia_css_binary *binary); + +#endif /* IA_CSS_INCLUDE_STATE */ + +#endif /* _IA_CSS_ISP_STATE_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/bits.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/bits.h new file mode 100644 index 0000000000000000000000000000000000000000..e71e33d9d1434c91cd8317ea40d5719c02b86172 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/bits.h @@ -0,0 +1,104 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HRT_BITS_H +#define _HRT_BITS_H + +#include "defs.h" + +#define _hrt_ones(n) HRTCAT(_hrt_ones_, n) +#define _hrt_ones_0x0 0x00000000U +#define _hrt_ones_0x1 0x00000001U +#define _hrt_ones_0x2 0x00000003U +#define _hrt_ones_0x3 0x00000007U +#define _hrt_ones_0x4 0x0000000FU +#define _hrt_ones_0x5 0x0000001FU +#define _hrt_ones_0x6 0x0000003FU +#define _hrt_ones_0x7 0x0000007FU +#define _hrt_ones_0x8 0x000000FFU +#define _hrt_ones_0x9 0x000001FFU +#define _hrt_ones_0xA 0x000003FFU +#define _hrt_ones_0xB 0x000007FFU +#define _hrt_ones_0xC 0x00000FFFU +#define _hrt_ones_0xD 0x00001FFFU +#define _hrt_ones_0xE 0x00003FFFU +#define _hrt_ones_0xF 0x00007FFFU +#define _hrt_ones_0x10 0x0000FFFFU +#define _hrt_ones_0x11 0x0001FFFFU +#define _hrt_ones_0x12 0x0003FFFFU +#define _hrt_ones_0x13 0x0007FFFFU +#define _hrt_ones_0x14 0x000FFFFFU +#define _hrt_ones_0x15 0x001FFFFFU +#define _hrt_ones_0x16 0x003FFFFFU +#define _hrt_ones_0x17 0x007FFFFFU +#define _hrt_ones_0x18 0x00FFFFFFU +#define _hrt_ones_0x19 0x01FFFFFFU +#define _hrt_ones_0x1A 0x03FFFFFFU +#define _hrt_ones_0x1B 0x07FFFFFFU +#define _hrt_ones_0x1C 0x0FFFFFFFU +#define _hrt_ones_0x1D 0x1FFFFFFFU +#define _hrt_ones_0x1E 0x3FFFFFFFU +#define _hrt_ones_0x1F 0x7FFFFFFFU +#define _hrt_ones_0x20 0xFFFFFFFFU + +#define _hrt_ones_0 _hrt_ones_0x0 +#define _hrt_ones_1 _hrt_ones_0x1 +#define _hrt_ones_2 _hrt_ones_0x2 +#define _hrt_ones_3 _hrt_ones_0x3 +#define _hrt_ones_4 _hrt_ones_0x4 +#define _hrt_ones_5 _hrt_ones_0x5 +#define _hrt_ones_6 _hrt_ones_0x6 +#define _hrt_ones_7 _hrt_ones_0x7 +#define _hrt_ones_8 _hrt_ones_0x8 +#define _hrt_ones_9 _hrt_ones_0x9 +#define _hrt_ones_10 _hrt_ones_0xA +#define _hrt_ones_11 _hrt_ones_0xB +#define _hrt_ones_12 _hrt_ones_0xC +#define _hrt_ones_13 _hrt_ones_0xD +#define _hrt_ones_14 _hrt_ones_0xE +#define _hrt_ones_15 _hrt_ones_0xF +#define _hrt_ones_16 _hrt_ones_0x10 +#define _hrt_ones_17 _hrt_ones_0x11 +#define _hrt_ones_18 _hrt_ones_0x12 +#define _hrt_ones_19 _hrt_ones_0x13 +#define _hrt_ones_20 _hrt_ones_0x14 +#define _hrt_ones_21 _hrt_ones_0x15 +#define _hrt_ones_22 _hrt_ones_0x16 +#define _hrt_ones_23 _hrt_ones_0x17 +#define _hrt_ones_24 _hrt_ones_0x18 +#define _hrt_ones_25 _hrt_ones_0x19 +#define _hrt_ones_26 _hrt_ones_0x1A +#define _hrt_ones_27 _hrt_ones_0x1B +#define _hrt_ones_28 _hrt_ones_0x1C +#define _hrt_ones_29 _hrt_ones_0x1D +#define _hrt_ones_30 _hrt_ones_0x1E +#define _hrt_ones_31 _hrt_ones_0x1F +#define _hrt_ones_32 _hrt_ones_0x20 + +#define _hrt_mask(b, n) \ + (_hrt_ones(n) << (b)) +#define _hrt_get_bits(w, b, n) \ + (((w) >> (b)) & _hrt_ones(n)) +#define _hrt_set_bits(w, b, n, v) \ + (((w) & ~_hrt_mask(b, n)) | (((v) & _hrt_ones(n)) << (b))) +#define _hrt_get_bit(w, b) \ + (((w) >> (b)) & 1) +#define _hrt_set_bit(w, b, v) \ + (((w) & (~(1 << (b)))) | (((v)&1) << (b))) +#define _hrt_set_lower_half(w, v) \ + _hrt_set_bits(w, 0, 16, v) +#define _hrt_set_upper_half(w, v) \ + _hrt_set_bits(w, 16, 16, v) + +#endif /* _HRT_BITS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/cell_params.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/cell_params.h new file mode 100644 index 0000000000000000000000000000000000000000..b5756bfe8eb6b1e10c7f70659bc20e6537e8df1c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/cell_params.h @@ -0,0 +1,42 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _cell_params_h +#define _cell_params_h + +#define SP_PMEM_LOG_WIDTH_BITS 6 /*Width of PC, 64 bits, 8 bytes*/ +#define SP_ICACHE_TAG_BITS 4 /*size of tag*/ +#define SP_ICACHE_SET_BITS 8 /* 256 sets*/ +#define SP_ICACHE_BLOCKS_PER_SET_BITS 1 /* 2 way associative*/ +#define SP_ICACHE_BLOCK_ADDRESS_BITS 11 /* 2048 lines capacity*/ + +#define SP_ICACHE_ADDRESS_BITS \ + (SP_ICACHE_TAG_BITS+SP_ICACHE_BLOCK_ADDRESS_BITS) + +#define SP_PMEM_DEPTH (1< input_selector*/ +/* !! Changes here should be copied to systems/isp/isp_css/bin/conv_transmitter_cmd.tcl !! */ +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB888 0 // 36 'h24 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB555 1 // 33 'h +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB444 2 // 32 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB565 3 // 34 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RGB666 4 // 35 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW8 5 // 42 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW10 6 // 43 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW6 7 // 40 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW7 8 // 41 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW12 9 // 43 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW14 10 // 45 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8 11 // 30 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10 12 // 25 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_8 13 // 30 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV422_10 14 // 31 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_1 15 // 48 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8L 16 // 26 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_Emb 17 // 18 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_2 18 // 49 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_3 19 // 50 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_4 20 // 51 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_5 21 // 52 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_6 22 // 53 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_7 23 // 54 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_USR_DEF_8 24 // 55 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_8_CSPS 25 // 28 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_YUV420_10_CSPS 26 // 29 +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW16 27 // ? +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18 28 // ? +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_2 29 // ? Option 2 for depacketiser +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_RAW18_3 30 // ? Option 3 for depacketiser +#define _HRT_CSS_RECEIVER_2400_FMT_TYPE_CUSTOM 31 // to signal custom decoding + +/* definition for state machine of data FIFO for decode different type of data */ +#define _HRT_CSS_RECEIVER_2400_YUV420_8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV420_10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_YUV420_8L_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV422_8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_YUV422_10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_RGB444_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB555_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB565_REPEAT_PTN 2 +#define _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN 9 +#define _HRT_CSS_RECEIVER_2400_RGB888_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW6_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW7_REPEAT_PTN 7 +#define _HRT_CSS_RECEIVER_2400_RAW8_REPEAT_PTN 1 +#define _HRT_CSS_RECEIVER_2400_RAW10_REPEAT_PTN 5 +#define _HRT_CSS_RECEIVER_2400_RAW12_REPEAT_PTN 3 +#define _HRT_CSS_RECEIVER_2400_RAW14_REPEAT_PTN 7 + +#define _HRT_CSS_RECEIVER_2400_MAX_REPEAT_PTN _HRT_CSS_RECEIVER_2400_RGB666_REPEAT_PTN + +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FMT_WIDTH 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_IDX 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_PRED_WIDTH 1 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_USD_BITS 4 /* bits per USD type */ + +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_EN_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_OPTION_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_EN_IDX 8 + +#define _HRT_CSS_RECEIVER_2400_BE_COMP_NO_COMP 0 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_6_10 1 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_7_10 2 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_10_8_10 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_6_12 4 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_7_12 5 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_12_8_12 6 + + +/* packet bit definition */ +#define _HRT_CSS_RECEIVER_2400_PKT_SOP_IDX 32 +#define _HRT_CSS_RECEIVER_2400_PKT_SOP_BITS 1 +#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_IDX 22 +#define _HRT_CSS_RECEIVER_2400_PKT_CH_ID_BITS 2 +#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_IDX 16 +#define _HRT_CSS_RECEIVER_2400_PKT_FMT_ID_BITS 6 +#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_IDX 0 +#define _HRT_CSS_RECEIVER_2400_PH_DATA_FIELD_BITS 16 +#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_IDX 0 +#define _HRT_CSS_RECEIVER_2400_PKT_PAYLOAD_BITS 32 + + +/*************************************************************************************************/ +/* Custom Decoding */ +/* These Custom Defs are defined based on design-time config in "csi_be_pixel_formatter.chdl" !! */ +/*************************************************************************************************/ +#define BE_CUST_EN_IDX 0 /* 2bits */ +#define BE_CUST_EN_DATAID_IDX 2 /* 6bits MIPI DATA ID */ +#define BE_CUST_EN_WIDTH 8 +#define BE_CUST_MODE_ALL 1 /* Enable Custom Decoding for all DATA IDs */ +#define BE_CUST_MODE_ONE 3 /* Enable Custom Decoding for ONE DATA ID, programmed in CUST_EN_DATA_ID */ + +/* Data State config = {get_bits(6bits), valid(1bit)} */ +#define BE_CUST_DATA_STATE_S0_IDX 0 /* 7bits */ +#define BE_CUST_DATA_STATE_S1_IDX 7 /* 7bits */ +#define BE_CUST_DATA_STATE_S2_IDX 14 /* 7bits */ +#define BE_CUST_DATA_STATE_WIDTH 21 +#define BE_CUST_DATA_STATE_VALID_IDX 0 /* 1bits */ +#define BE_CUST_DATA_STATE_GETBITS_IDX 1 /* 6bits */ + +/* Pixel Extractor config */ +#define BE_CUST_PIX_EXT_DATA_ALIGN_IDX 0 /* 5bits */ +#define BE_CUST_PIX_EXT_PIX_ALIGN_IDX 5 /* 5bits */ +#define BE_CUST_PIX_EXT_PIX_MASK_IDX 10 /* 18bits */ +#define BE_CUST_PIX_EXT_PIX_EN_IDX 28 /* 1bits */ +#define BE_CUST_PIX_EXT_WIDTH 29 + +/* Pixel Valid & EoP config = {[eop,valid](especial), [eop,valid](normal)} */ +#define BE_CUST_PIX_VALID_EOP_P0_IDX 0 /* 4bits */ +#define BE_CUST_PIX_VALID_EOP_P1_IDX 4 /* 4bits */ +#define BE_CUST_PIX_VALID_EOP_P2_IDX 8 /* 4bits */ +#define BE_CUST_PIX_VALID_EOP_P3_IDX 12 /* 4bits */ +#define BE_CUST_PIX_VALID_EOP_WIDTH 16 +#define BE_CUST_PIX_VALID_EOP_NOR_VALID_IDX 0 /* Normal (NO less get_bits case) Valid - 1bits */ +#define BE_CUST_PIX_VALID_EOP_NOR_EOP_IDX 1 /* Normal (NO less get_bits case) EoP - 1bits */ +#define BE_CUST_PIX_VALID_EOP_ESP_VALID_IDX 2 /* Especial (less get_bits case) Valid - 1bits */ +#define BE_CUST_PIX_VALID_EOP_ESP_EOP_IDX 3 /* Especial (less get_bits case) EoP - 1bits */ + +#endif /* _mipi_backend_common_defs_h_ */ +#endif /* _css_receiver_2400_common_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/css_receiver_2400_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/css_receiver_2400_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..6f5b7d3d3715e905f55265a2774be86cc5eb9f08 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/css_receiver_2400_defs.h @@ -0,0 +1,258 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _css_receiver_2400_defs_h_ +#define _css_receiver_2400_defs_h_ + +#include "css_receiver_2400_common_defs.h" + +#define CSS_RECEIVER_DATA_WIDTH 8 +#define CSS_RECEIVER_RX_TRIG 4 +#define CSS_RECEIVER_RF_WORD 32 +#define CSS_RECEIVER_IMG_PROC_RF_ADDR 10 +#define CSS_RECEIVER_CSI_RF_ADDR 4 +#define CSS_RECEIVER_DATA_OUT 12 +#define CSS_RECEIVER_CHN_NO 2 +#define CSS_RECEIVER_DWORD_CNT 11 +#define CSS_RECEIVER_FORMAT_TYP 5 +#define CSS_RECEIVER_HRESPONSE 2 +#define CSS_RECEIVER_STATE_WIDTH 3 +#define CSS_RECEIVER_FIFO_DAT 32 +#define CSS_RECEIVER_CNT_VAL 2 +#define CSS_RECEIVER_PRED10_VAL 10 +#define CSS_RECEIVER_PRED12_VAL 12 +#define CSS_RECEIVER_CNT_WIDTH 8 +#define CSS_RECEIVER_WORD_CNT 16 +#define CSS_RECEIVER_PIXEL_LEN 6 +#define CSS_RECEIVER_PIXEL_CNT 5 +#define CSS_RECEIVER_COMP_8_BIT 8 +#define CSS_RECEIVER_COMP_7_BIT 7 +#define CSS_RECEIVER_COMP_6_BIT 6 + +#define CSI_CONFIG_WIDTH 4 + +/* division of gen_short data, ch_id and fmt_type over streaming data interface */ +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB 0 +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_DATA_WIDTH) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB + _HRT_CSS_RECEIVER_2400_GEN_SHORT_FMT_TYPE_WIDTH) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_DATA_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_LSB - 1) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_FMT_TYPE_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_LSB - 1) +#define _HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_CH_ID_BIT_MSB (_HRT_CSS_RECEIVER_2400_GEN_SHORT_STR_REAL_WIDTH - 1) + +#define _HRT_CSS_RECEIVER_2400_REG_ALIGN 4 +#define _HRT_CSS_RECEIVER_2400_BYTES_PER_PKT 4 + +#define hrt_css_receiver_2400_4_lane_port_offset 0x100 +#define hrt_css_receiver_2400_1_lane_port_offset 0x200 +#define hrt_css_receiver_2400_2_lane_port_offset 0x300 +#define hrt_css_receiver_2400_backend_port_offset 0x100 + +#define _HRT_CSS_RECEIVER_2400_DEVICE_READY_REG_IDX 0 +#define _HRT_CSS_RECEIVER_2400_IRQ_STATUS_REG_IDX 1 +#define _HRT_CSS_RECEIVER_2400_IRQ_ENABLE_REG_IDX 2 +#define _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX 3 +#define _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX 4 +#define _HRT_CSS_RECEIVER_2400_FS_TO_LS_DELAY_REG_IDX 7 +#define _HRT_CSS_RECEIVER_2400_LS_TO_DATA_DELAY_REG_IDX 8 +#define _HRT_CSS_RECEIVER_2400_DATA_TO_LE_DELAY_REG_IDX 9 +#define _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX 10 +#define _HRT_CSS_RECEIVER_2400_FE_TO_FS_DELAY_REG_IDX 11 +#define _HRT_CSS_RECEIVER_2400_LE_TO_LS_DELAY_REG_IDX 12 +#define _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX 13 +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_REG_IDX 14 +#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX 15 +#define _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX 16 +#define _HRT_CSS_RECEIVER_2400_BACKEND_RST_REG_IDX 17 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX 18 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX 19 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX 20 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX 21 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX 22 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX 23 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX 24 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX 25 +#define _HRT_CSS_RECEIVER_2400_RAW18_REG_IDX 26 +#define _HRT_CSS_RECEIVER_2400_FORCE_RAW8_REG_IDX 27 +#define _HRT_CSS_RECEIVER_2400_RAW16_REG_IDX 28 + +/* Interrupt bits for IRQ_STATUS and IRQ_ENABLE registers */ +#define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_BIT 0 +#define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_BIT 1 +#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_BIT 2 +#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_BIT 3 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_BIT 4 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_BIT 5 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_BIT 6 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_BIT 7 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_BIT 8 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_BIT 9 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT 10 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_BIT 11 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_BIT 12 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_BIT 13 +#define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_BIT 14 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_BIT 15 +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_BIT 16 + +#define _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_CAUSE_ "Fifo Overrun" +#define _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_CAUSE_ "Reserved" +#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_CAUSE_ "Sleep mode entry" +#define _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_CAUSE_ "Sleep mode exit" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_CAUSE_ "Error high speed SOT" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_CAUSE_ "Error high speed sync SOT" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_CAUSE_ "Error control" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_CAUSE_ "Error correction double bit" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_CAUSE_ "Error correction single bit" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_CAUSE_ "No error" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_CAUSE_ "Error cyclic redundancy check" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_CAUSE_ "Error id" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_CAUSE_ "Error frame sync" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_CAUSE_ "Error frame data" +#define _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_CAUSE_ "Data time-out" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_CAUSE_ "Error escape" +#define _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_CAUSE_ "Error line sync" + +/* Bits for CSI2_DEVICE_READY register */ +#define _HRT_CSS_RECEIVER_2400_CSI2_DEVICE_READY_IDX 0 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_INIT_TIME_OUT_ERR_IDX 2 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_OVER_RUN_ERR_IDX 3 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_SOT_SYNC_ERR_IDX 4 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_RECEIVE_DATA_TIME_OUT_ERR_IDX 5 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_ECC_TWO_BIT_ERR_IDX 6 +#define _HRT_CSS_RECEIVER_2400_CSI2_MASK_DATA_ID_ERR_IDX 7 + + +/* Bits for CSI2_FUNC_PROG register */ +#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS 19 + +/* Bits for INIT_COUNT register */ +#define _HRT_CSS_RECEIVER_2400_INIT_TIMER_IDX 0 +#define _HRT_CSS_RECEIVER_2400_INIT_TIMER_BITS 16 + +/* Bits for COUNT registers */ +#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_SYNC_COUNT_BITS 8 +#define _HRT_CSS_RECEIVER_2400_RX_COUNT_IDX 0 +#define _HRT_CSS_RECEIVER_2400_RX_COUNT_BITS 8 + +/* Bits for RAW116_18_DATAID register */ +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW16_BITS_BITS 6 +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_IDX 8 +#define _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_RAW18_BITS_BITS 6 + +/* Bits for COMP_FORMAT register, this selects the compression data format */ +#define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS 8 +#define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_IDX (_HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_IDX + _HRT_CSS_RECEIVER_2400_COMP_RAW_BITS_BITS) +#define _HRT_CSS_RECEIVER_2400_COMP_NUM_BITS_BITS 8 + +/* Bits for COMP_PREDICT register, this selects the predictor algorithm */ +#define _HRT_CSS_RECEIVER_2400_PREDICT_NO_COMP 0 +#define _HRT_CSS_RECEIVER_2400_PREDICT_1 1 +#define _HRT_CSS_RECEIVER_2400_PREDICT_2 2 + +/* Number of bits used for the delay registers */ +#define _HRT_CSS_RECEIVER_2400_DELAY_BITS 8 + +/* Bits for COMP_SCHEME register, this selects the compression scheme for a VC */ +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD1_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD2_BITS_IDX 5 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD3_BITS_IDX 10 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD4_BITS_IDX 15 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD5_BITS_IDX 20 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD6_BITS_IDX 25 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD7_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD8_BITS_IDX 5 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_BITS_BITS 5 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_IDX 0 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_FMT_BITS_BITS 3 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_IDX 3 +#define _HRT_CSS_RECEIVER_2400_COMP_SCHEME_USD_PRED_BITS_BITS 2 + + +/* BITS for backend RAW16 and RAW 18 registers */ + +#define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_RAW18_DATAID_BITS 6 +#define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_IDX 6 +#define _HRT_CSS_RECEIVER_2400_RAW18_OPTION_BITS 2 +#define _HRT_CSS_RECEIVER_2400_RAW18_EN_IDX 8 +#define _HRT_CSS_RECEIVER_2400_RAW18_EN_BITS 1 + +#define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_IDX 0 +#define _HRT_CSS_RECEIVER_2400_RAW16_DATAID_BITS 6 +#define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_IDX 6 +#define _HRT_CSS_RECEIVER_2400_RAW16_OPTION_BITS 2 +#define _HRT_CSS_RECEIVER_2400_RAW16_EN_IDX 8 +#define _HRT_CSS_RECEIVER_2400_RAW16_EN_BITS 1 + +/* These hsync and vsync values are for HSS simulation only */ +#define _HRT_CSS_RECEIVER_2400_HSYNC_VAL (1<<16) +#define _HRT_CSS_RECEIVER_2400_VSYNC_VAL (1<<17) + +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_WIDTH 28 +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB 0 +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_LSB + CSS_RECEIVER_DATA_OUT - 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_MSB + 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_A_VAL_BIT + 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_LSB + CSS_RECEIVER_DATA_OUT - 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_MSB + 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_PIX_B_VAL_BIT + 1) +#define _HRT_CSS_RECEIVER_2400_BE_STREAMING_EOP_BIT (_HRT_CSS_RECEIVER_2400_BE_STREAMING_SOP_BIT + 1) + +// SH Backend Register IDs +#define _HRT_CSS_RECEIVER_2400_BE_GSP_ACC_OVL_REG_IDX 0 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_REG_IDX 1 +#define _HRT_CSS_RECEIVER_2400_BE_TWO_PPC_REG_IDX 2 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG0_IDX 3 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG1_IDX 4 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG2_IDX 5 +#define _HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG3_IDX 6 +#define _HRT_CSS_RECEIVER_2400_BE_SEL_REG_IDX 7 +#define _HRT_CSS_RECEIVER_2400_BE_RAW16_CONFIG_REG_IDX 8 +#define _HRT_CSS_RECEIVER_2400_BE_RAW18_CONFIG_REG_IDX 9 +#define _HRT_CSS_RECEIVER_2400_BE_FORCE_RAW8_REG_IDX 10 +#define _HRT_CSS_RECEIVER_2400_BE_IRQ_STATUS_REG_IDX 11 +#define _HRT_CSS_RECEIVER_2400_BE_IRQ_CLEAR_REG_IDX 12 +#define _HRT_CSS_RECEIVER_2400_BE_CUST_EN_REG_IDX 13 +#define _HRT_CSS_RECEIVER_2400_BE_CUST_DATA_STATE_REG_IDX 14 /* Data State 0,1,2 config */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P0_REG_IDX 15 /* Pixel Extractor config for Data State 0 & Pix 0 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P1_REG_IDX 16 /* Pixel Extractor config for Data State 0 & Pix 1 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P2_REG_IDX 17 /* Pixel Extractor config for Data State 0 & Pix 2 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S0P3_REG_IDX 18 /* Pixel Extractor config for Data State 0 & Pix 3 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P0_REG_IDX 19 /* Pixel Extractor config for Data State 1 & Pix 0 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P1_REG_IDX 20 /* Pixel Extractor config for Data State 1 & Pix 1 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P2_REG_IDX 21 /* Pixel Extractor config for Data State 1 & Pix 2 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S1P3_REG_IDX 22 /* Pixel Extractor config for Data State 1 & Pix 3 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P0_REG_IDX 23 /* Pixel Extractor config for Data State 2 & Pix 0 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P1_REG_IDX 24 /* Pixel Extractor config for Data State 2 & Pix 1 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P2_REG_IDX 25 /* Pixel Extractor config for Data State 2 & Pix 2 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_EXT_S2P3_REG_IDX 26 /* Pixel Extractor config for Data State 2 & Pix 3 */ +#define _HRT_CSS_RECEIVER_2400_BE_CUST_PIX_VALID_EOP_REG_IDX 27 /* Pixel Valid & EoP config for Pix 0,1,2,3 */ + +#define _HRT_CSS_RECEIVER_2400_BE_NOF_REGISTERS 28 + +#define _HRT_CSS_RECEIVER_2400_BE_SRST_HE 0 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_RCF 1 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_PF 2 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_SM 3 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_PD 4 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_SD 5 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_OT 6 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_BC 7 +#define _HRT_CSS_RECEIVER_2400_BE_SRST_WIDTH 8 + +#endif /* _css_receiver_2400_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/defs.h new file mode 100644 index 0000000000000000000000000000000000000000..47505f41790c17ef0aa42727d9553666bb3961ae --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/defs.h @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HRT_DEFS_H_ +#define _HRT_DEFS_H_ + +#ifndef HRTCAT +#define _HRTCAT(m, n) m##n +#define HRTCAT(m, n) _HRTCAT(m, n) +#endif + +#ifndef HRTSTR +#define _HRTSTR(x) #x +#define HRTSTR(x) _HRTSTR(x) +#endif + +#ifndef HRTMIN +#define HRTMIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef HRTMAX +#define HRTMAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +#endif /* _HRT_DEFS_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/dma_v2_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/dma_v2_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..d184a8b313c91c6978c70b10c42f32231cc65cb9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/dma_v2_defs.h @@ -0,0 +1,199 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _dma_v2_defs_h +#define _dma_v2_defs_h + +#define _DMA_V2_NUM_CHANNELS_ID MaxNumChannels +#define _DMA_V2_CONNECTIONS_ID Connections +#define _DMA_V2_DEV_ELEM_WIDTHS_ID DevElemWidths +#define _DMA_V2_DEV_FIFO_DEPTH_ID DevFifoDepth +#define _DMA_V2_DEV_FIFO_RD_LAT_ID DevFifoRdLat +#define _DMA_V2_DEV_FIFO_LAT_BYPASS_ID DevFifoRdLatBypass +#define _DMA_V2_DEV_NO_BURST_ID DevNoBurst +#define _DMA_V2_DEV_RD_ACCEPT_ID DevRdAccept +#define _DMA_V2_DEV_SRMD_ID DevSRMD +#define _DMA_V2_DEV_HAS_CRUN_ID CRunMasters +#define _DMA_V2_CTRL_ACK_FIFO_DEPTH_ID CtrlAckFifoDepth +#define _DMA_V2_CMD_FIFO_DEPTH_ID CommandFifoDepth +#define _DMA_V2_CMD_FIFO_RD_LAT_ID CommandFifoRdLat +#define _DMA_V2_CMD_FIFO_LAT_BYPASS_ID CommandFifoRdLatBypass +#define _DMA_V2_NO_PACK_ID has_no_pack + +#define _DMA_V2_REG_ALIGN 4 +#define _DMA_V2_REG_ADDR_BITS 2 + +/* Command word */ +#define _DMA_V2_CMD_IDX 0 +#define _DMA_V2_CMD_BITS 6 +#define _DMA_V2_CHANNEL_IDX (_DMA_V2_CMD_IDX + _DMA_V2_CMD_BITS) +#define _DMA_V2_CHANNEL_BITS 5 + +/* The command to set a parameter contains the PARAM field next */ +#define _DMA_V2_PARAM_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS) +#define _DMA_V2_PARAM_BITS 4 + +/* Commands to read, write or init specific blocks contain these + three values */ +#define _DMA_V2_SPEC_DEV_A_XB_IDX (_DMA_V2_CHANNEL_IDX + _DMA_V2_CHANNEL_BITS) +#define _DMA_V2_SPEC_DEV_A_XB_BITS 8 +#define _DMA_V2_SPEC_DEV_B_XB_IDX (_DMA_V2_SPEC_DEV_A_XB_IDX + _DMA_V2_SPEC_DEV_A_XB_BITS) +#define _DMA_V2_SPEC_DEV_B_XB_BITS 8 +#define _DMA_V2_SPEC_YB_IDX (_DMA_V2_SPEC_DEV_B_XB_IDX + _DMA_V2_SPEC_DEV_B_XB_BITS) +#define _DMA_V2_SPEC_YB_BITS (32-_DMA_V2_SPEC_DEV_B_XB_BITS-_DMA_V2_SPEC_DEV_A_XB_BITS-_DMA_V2_CMD_BITS-_DMA_V2_CHANNEL_BITS) + +/* */ +#define _DMA_V2_CMD_CTRL_IDX 4 +#define _DMA_V2_CMD_CTRL_BITS 4 + +/* Packing setup word */ +#define _DMA_V2_CONNECTION_IDX 0 +#define _DMA_V2_CONNECTION_BITS 4 +#define _DMA_V2_EXTENSION_IDX (_DMA_V2_CONNECTION_IDX + _DMA_V2_CONNECTION_BITS) +#define _DMA_V2_EXTENSION_BITS 1 + +/* Elements packing word */ +#define _DMA_V2_ELEMENTS_IDX 0 +#define _DMA_V2_ELEMENTS_BITS 8 +#define _DMA_V2_LEFT_CROPPING_IDX (_DMA_V2_ELEMENTS_IDX + _DMA_V2_ELEMENTS_BITS) +#define _DMA_V2_LEFT_CROPPING_BITS 8 + +#define _DMA_V2_WIDTH_IDX 0 +#define _DMA_V2_WIDTH_BITS 16 + +#define _DMA_V2_HEIGHT_IDX 0 +#define _DMA_V2_HEIGHT_BITS 16 + +#define _DMA_V2_STRIDE_IDX 0 +#define _DMA_V2_STRIDE_BITS 32 + +/* Command IDs */ +#define _DMA_V2_MOVE_B2A_COMMAND 0 +#define _DMA_V2_MOVE_B2A_BLOCK_COMMAND 1 +#define _DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND 2 +#define _DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND 3 +#define _DMA_V2_MOVE_A2B_COMMAND 4 +#define _DMA_V2_MOVE_A2B_BLOCK_COMMAND 5 +#define _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND 6 +#define _DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND 7 +#define _DMA_V2_INIT_A_COMMAND 8 +#define _DMA_V2_INIT_A_BLOCK_COMMAND 9 +#define _DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND 10 +#define _DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND 11 +#define _DMA_V2_INIT_B_COMMAND 12 +#define _DMA_V2_INIT_B_BLOCK_COMMAND 13 +#define _DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND 14 +#define _DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND 15 +#define _DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_B2A_BLOCK_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_MOVE_A2B_BLOCK_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_INIT_A_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_A_BLOCK_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_INIT_B_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_NO_ACK_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND (_DMA_V2_INIT_B_BLOCK_NO_SYNC_CHK_COMMAND + 16) +#define _DMA_V2_CONFIG_CHANNEL_COMMAND 32 +#define _DMA_V2_SET_CHANNEL_PARAM_COMMAND 33 +#define _DMA_V2_SET_CRUN_COMMAND 62 + +/* Channel Parameter IDs */ +#define _DMA_V2_PACKING_SETUP_PARAM 0 +#define _DMA_V2_STRIDE_A_PARAM 1 +#define _DMA_V2_ELEM_CROPPING_A_PARAM 2 +#define _DMA_V2_WIDTH_A_PARAM 3 +#define _DMA_V2_STRIDE_B_PARAM 4 +#define _DMA_V2_ELEM_CROPPING_B_PARAM 5 +#define _DMA_V2_WIDTH_B_PARAM 6 +#define _DMA_V2_HEIGHT_PARAM 7 +#define _DMA_V2_QUEUED_CMDS 8 + +/* Parameter Constants */ +#define _DMA_V2_ZERO_EXTEND 0 +#define _DMA_V2_SIGN_EXTEND 1 + + /* SLAVE address map */ +#define _DMA_V2_SEL_FSM_CMD 0 +#define _DMA_V2_SEL_CH_REG 1 +#define _DMA_V2_SEL_CONN_GROUP 2 +#define _DMA_V2_SEL_DEV_INTERF 3 + +#define _DMA_V2_ADDR_SEL_COMP_IDX 12 +#define _DMA_V2_ADDR_SEL_COMP_BITS 4 +#define _DMA_V2_ADDR_SEL_CH_REG_IDX 2 +#define _DMA_V2_ADDR_SEL_CH_REG_BITS 6 +#define _DMA_V2_ADDR_SEL_PARAM_IDX (_DMA_V2_ADDR_SEL_CH_REG_BITS+_DMA_V2_ADDR_SEL_CH_REG_IDX) +#define _DMA_V2_ADDR_SEL_PARAM_BITS 4 + +#define _DMA_V2_ADDR_SEL_GROUP_COMP_IDX 2 +#define _DMA_V2_ADDR_SEL_GROUP_COMP_BITS 6 +#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_IDX (_DMA_V2_ADDR_SEL_GROUP_COMP_BITS + _DMA_V2_ADDR_SEL_GROUP_COMP_IDX) +#define _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_BITS 4 + +#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX 2 +#define _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS 6 +#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX (_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX+_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS) +#define _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS 4 + +#define _DMA_V2_FSM_GROUP_CMD_IDX 0 +#define _DMA_V2_FSM_GROUP_ADDR_SRC_IDX 1 +#define _DMA_V2_FSM_GROUP_ADDR_DEST_IDX 2 +#define _DMA_V2_FSM_GROUP_CMD_CTRL_IDX 3 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_IDX 4 +#define _DMA_V2_FSM_GROUP_FSM_PACK_IDX 5 +#define _DMA_V2_FSM_GROUP_FSM_REQ_IDX 6 +#define _DMA_V2_FSM_GROUP_FSM_WR_IDX 7 + +#define _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX 0 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX 1 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX 2 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX 3 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_XB_IDX 4 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_YB_IDX 5 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX 6 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX 7 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX 8 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX 9 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX 10 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX 11 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX 12 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX 13 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX 14 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX 15 +#define _DMA_V2_FSM_GROUP_FSM_CTRL_CMD_CTRL_IDX 15 + +#define _DMA_V2_FSM_GROUP_FSM_PACK_STATE_IDX 0 +#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_YB_IDX 1 +#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX 2 +#define _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX 3 + +#define _DMA_V2_FSM_GROUP_FSM_REQ_STATE_IDX 0 +#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_YB_IDX 1 +#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_XB_IDX 2 +#define _DMA_V2_FSM_GROUP_FSM_REQ_XB_REMAINING_IDX 3 +#define _DMA_V2_FSM_GROUP_FSM_REQ_CNT_BURST_IDX 4 + +#define _DMA_V2_FSM_GROUP_FSM_WR_STATE_IDX 0 +#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_YB_IDX 1 +#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_XB_IDX 2 +#define _DMA_V2_FSM_GROUP_FSM_WR_XB_REMAINING_IDX 3 +#define _DMA_V2_FSM_GROUP_FSM_WR_CNT_BURST_IDX 4 + +#define _DMA_V2_DEV_INTERF_REQ_SIDE_STATUS_IDX 0 +#define _DMA_V2_DEV_INTERF_SEND_SIDE_STATUS_IDX 1 +#define _DMA_V2_DEV_INTERF_FIFO_STATUS_IDX 2 +#define _DMA_V2_DEV_INTERF_REQ_ONLY_COMPLETE_BURST_IDX 3 +#define _DMA_V2_DEV_INTERF_MAX_BURST_IDX 4 +#define _DMA_V2_DEV_INTERF_CHK_ADDR_ALIGN 5 + +#endif /* _dma_v2_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/gdc_v2_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/gdc_v2_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..77722d20570108c94c8258640f679564ef0e40dc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/gdc_v2_defs.h @@ -0,0 +1,170 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef HRT_GDC_v2_defs_h_ +#define HRT_GDC_v2_defs_h_ + +#define HRT_GDC_IS_V2 + +#define HRT_GDC_N 1024 /* Top-level design constant, equal to the number of entries in the LUT */ +#define HRT_GDC_FRAC_BITS 10 /* Number of fractional bits in the GDC block, driven by the size of the LUT */ + +#define HRT_GDC_BLI_FRAC_BITS 4 /* Number of fractional bits for the bi-linear interpolation type */ +#define HRT_GDC_BLI_COEF_ONE (1 << HRT_GDC_BLI_FRAC_BITS) + +#define HRT_GDC_BCI_COEF_BITS 14 /* 14 bits per coefficient */ +#define HRT_GDC_BCI_COEF_ONE (1 << (HRT_GDC_BCI_COEF_BITS-2)) /* We represent signed 10 bit coefficients. */ + /* The supported range is [-256, .., +256] */ + /* in 14-bit signed notation, */ + /* We need all ten bits (MSB must be zero). */ + /* -s is inserted to solve this issue, and */ + /* therefore "1" is equal to +256. */ +#define HRT_GDC_BCI_COEF_MASK ((1 << HRT_GDC_BCI_COEF_BITS) - 1) + +#define HRT_GDC_LUT_BYTES (HRT_GDC_N*4*2) /* 1024 addresses, 4 coefficients per address, */ + /* 2 bytes per coefficient */ + +#define _HRT_GDC_REG_ALIGN 4 + + // 31 30 29 25 24 0 + // |-----|---|--------|------------------------| + // | CMD | C | Reg_ID | Value | + + + // There are just two commands possible for the GDC block: + // 1 - Configure reg + // 0 - Data token + + // C - Reserved bit + // Used in protocol to indicate whether it is C-run or other type of runs + // In case of C-run, this bit has a value of 1, for all the other runs, it is 0. + + // Reg_ID - Address of the register to be configured + + // Value - Value to store to the addressed register, maximum of 24 bits + + // Configure reg command is not followed by any other token. + // The address of the register and the data to be filled in is contained in the same token + + // When the first data token is received, it must be: + // 1. FRX and FRY (device configured in one of the scaling modes) ***DEFAULT MODE***, or, + // 2. P0'X (device configured in one of the tetragon modes) + // After the first data token is received, pre-defined number of tokens with the following meaning follow: + // 1. two tokens: SRC address ; DST address + // 2. nine tokens: P0'Y, .., P3'Y ; SRC address ; DST address + +#define HRT_GDC_CONFIG_CMD 1 +#define HRT_GDC_DATA_CMD 0 + + +#define HRT_GDC_CMD_POS 31 +#define HRT_GDC_CMD_BITS 1 +#define HRT_GDC_CRUN_POS 30 +#define HRT_GDC_REG_ID_POS 25 +#define HRT_GDC_REG_ID_BITS 5 +#define HRT_GDC_DATA_POS 0 +#define HRT_GDC_DATA_BITS 25 + +#define HRT_GDC_FRYIPXFRX_BITS 26 +#define HRT_GDC_P0X_BITS 23 + + +#define HRT_GDC_MAX_OXDIM (8192-64) +#define HRT_GDC_MAX_OYDIM 4095 +#define HRT_GDC_MAX_IXDIM (8192-64) +#define HRT_GDC_MAX_IYDIM 4095 +#define HRT_GDC_MAX_DS_FAC 16 +#define HRT_GDC_MAX_DX (HRT_GDC_MAX_DS_FAC*HRT_GDC_N - 1) +#define HRT_GDC_MAX_DY HRT_GDC_MAX_DX + + +/* GDC lookup tables entries are 10 bits values, but they're + stored 2 by 2 as 32 bit values, yielding 16 bits per entry. + A GDC lookup table contains 64 * 4 elements */ + +#define HRT_GDC_PERF_1_1_pix 0 +#define HRT_GDC_PERF_2_1_pix 1 +#define HRT_GDC_PERF_1_2_pix 2 +#define HRT_GDC_PERF_2_2_pix 3 + +#define HRT_GDC_NND_MODE 0 +#define HRT_GDC_BLI_MODE 1 +#define HRT_GDC_BCI_MODE 2 +#define HRT_GDC_LUT_MODE 3 + +#define HRT_GDC_SCAN_STB 0 +#define HRT_GDC_SCAN_STR 1 + +#define HRT_GDC_MODE_SCALING 0 +#define HRT_GDC_MODE_TETRAGON 1 + +#define HRT_GDC_LUT_COEFF_OFFSET 16 +#define HRT_GDC_FRY_BIT_OFFSET 16 +// FRYIPXFRX is the only register where we store two values in one field, +// to save one token in the scaling protocol. +// Like this, we have three tokens in the scaling protocol, +// Otherwise, we would have had four. +// The register bit-map is: +// 31 26 25 16 15 10 9 0 +// |------|----------|------|----------| +// | XXXX | FRY | IPX | FRX | + + +#define HRT_GDC_CE_FSM0_POS 0 +#define HRT_GDC_CE_FSM0_LEN 2 +#define HRT_GDC_CE_OPY_POS 2 +#define HRT_GDC_CE_OPY_LEN 14 +#define HRT_GDC_CE_OPX_POS 16 +#define HRT_GDC_CE_OPX_LEN 16 +// CHK_ENGINE register bit-map: +// 31 16 15 2 1 0 +// |----------------|-----------|----| +// | OPX | OPY |FSM0| +// However, for the time being at least, +// this implementation is meaningless in hss model, +// So, we just return 0 + + +#define HRT_GDC_CHK_ENGINE_IDX 0 +#define HRT_GDC_WOIX_IDX 1 +#define HRT_GDC_WOIY_IDX 2 +#define HRT_GDC_BPP_IDX 3 +#define HRT_GDC_FRYIPXFRX_IDX 4 +#define HRT_GDC_OXDIM_IDX 5 +#define HRT_GDC_OYDIM_IDX 6 +#define HRT_GDC_SRC_ADDR_IDX 7 +#define HRT_GDC_SRC_END_ADDR_IDX 8 +#define HRT_GDC_SRC_WRAP_ADDR_IDX 9 +#define HRT_GDC_SRC_STRIDE_IDX 10 +#define HRT_GDC_DST_ADDR_IDX 11 +#define HRT_GDC_DST_STRIDE_IDX 12 +#define HRT_GDC_DX_IDX 13 +#define HRT_GDC_DY_IDX 14 +#define HRT_GDC_P0X_IDX 15 +#define HRT_GDC_P0Y_IDX 16 +#define HRT_GDC_P1X_IDX 17 +#define HRT_GDC_P1Y_IDX 18 +#define HRT_GDC_P2X_IDX 19 +#define HRT_GDC_P2Y_IDX 20 +#define HRT_GDC_P3X_IDX 21 +#define HRT_GDC_P3Y_IDX 22 +#define HRT_GDC_PERF_POINT_IDX 23 // 1x1 ; 1x2 ; 2x1 ; 2x2 pixels per cc +#define HRT_GDC_INTERP_TYPE_IDX 24 // NND ; BLI ; BCI ; LUT +#define HRT_GDC_SCAN_IDX 25 // 0 = STB (Slide To Bottom) ; 1 = STR (Slide To Right) +#define HRT_GDC_PROC_MODE_IDX 26 // 0 = Scaling ; 1 = Tetragon + +#define HRT_GDC_LUT_IDX 32 + + +#endif /* HRT_GDC_v2_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/gp_regs_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/gp_regs_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..34e734f6648eb0ef6297cab46f912c933466310f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/gp_regs_defs.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _gp_regs_defs_h +#define _gp_regs_defs_h + +#define _HRT_GP_REGS_IS_FWD_REG_IDX 0 + +#define _HRT_GP_REGS_REG_ALIGN 4 + +#endif /* _gp_regs_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/gp_timer_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/gp_timer_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..3082e2f5e014117ccd1548cceae21fd5eb2bd430 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/gp_timer_defs.h @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _gp_timer_defs_h +#define _gp_timer_defs_h + +#define _HRT_GP_TIMER_REG_ALIGN 4 + +#define HIVE_GP_TIMER_RESET_REG_IDX 0 +#define HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX 1 +#define HIVE_GP_TIMER_ENABLE_REG_IDX(timer) (HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX + 1 + timer) +#define HIVE_GP_TIMER_VALUE_REG_IDX(timer,timers) (HIVE_GP_TIMER_ENABLE_REG_IDX(timers) + timer) +#define HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer,timers) (HIVE_GP_TIMER_VALUE_REG_IDX(timers, timers) + timer) +#define HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer,timers) (HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timers, timers) + timer) +#define HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq,timers) (HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timers, timers) + irq) +#define HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq,timers,irqs) (HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irqs, timers) + irq) +#define HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq,timers,irqs) (HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irqs, timers, irqs) + irq) + +#define HIVE_GP_TIMER_COUNT_TYPE_HIGH 0 +#define HIVE_GP_TIMER_COUNT_TYPE_LOW 1 +#define HIVE_GP_TIMER_COUNT_TYPE_POSEDGE 2 +#define HIVE_GP_TIMER_COUNT_TYPE_NEGEDGE 3 +#define HIVE_GP_TIMER_COUNT_TYPES 4 + +#endif /* _gp_timer_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/gpio_block_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/gpio_block_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..a807d4c990414af50c61c4e20075d385db25862f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/gpio_block_defs.h @@ -0,0 +1,42 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _gpio_block_defs_h_ +#define _gpio_block_defs_h_ + +#define _HRT_GPIO_BLOCK_REG_ALIGN 4 + +/* R/W registers */ +#define _gpio_block_reg_do_e 0 +#define _gpio_block_reg_do_select 1 +#define _gpio_block_reg_do_0 2 +#define _gpio_block_reg_do_1 3 +#define _gpio_block_reg_do_pwm_cnt_0 4 +#define _gpio_block_reg_do_pwm_cnt_1 5 +#define _gpio_block_reg_do_pwm_cnt_2 6 +#define _gpio_block_reg_do_pwm_cnt_3 7 +#define _gpio_block_reg_do_pwm_main_cnt 8 +#define _gpio_block_reg_do_pwm_enable 9 +#define _gpio_block_reg_di_debounce_sel 10 +#define _gpio_block_reg_di_debounce_cnt_0 11 +#define _gpio_block_reg_di_debounce_cnt_1 12 +#define _gpio_block_reg_di_debounce_cnt_2 13 +#define _gpio_block_reg_di_debounce_cnt_3 14 +#define _gpio_block_reg_di_active_level 15 + + +/* read-only registers */ +#define _gpio_block_reg_di 16 + +#endif /* _gpio_block_defs_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/hive_isp_css_2401_irq_types_hrt.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/hive_isp_css_2401_irq_types_hrt.h new file mode 100644 index 0000000000000000000000000000000000000000..7a94c1d85b087ac7293e19fa15b5c4cdd06b1f0b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/hive_isp_css_2401_irq_types_hrt.h @@ -0,0 +1,69 @@ +/* +#ifndef ISP2401 + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HIVE_ISP_CSS_2401_IRQ_TYPES_HRT_H_ +#define _HIVE_ISP_CSS_2401_IRQ_TYPES_HRT_H_ + +/* + * These are the indices of each interrupt in the interrupt + * controller's registers. these can be used as the irq_id + * argument to the hrt functions irq_controller.h. + * + * The definitions are taken from _defs.h + */ +typedef enum hrt_isp_css_irq { + hrt_isp_css_irq_gpio_pin_0 = HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID , + hrt_isp_css_irq_gpio_pin_1 = HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID , + hrt_isp_css_irq_gpio_pin_2 = HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID , + hrt_isp_css_irq_gpio_pin_3 = HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID , + hrt_isp_css_irq_gpio_pin_4 = HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID , + hrt_isp_css_irq_gpio_pin_5 = HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID , + hrt_isp_css_irq_gpio_pin_6 = HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID , + hrt_isp_css_irq_gpio_pin_7 = HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID , + hrt_isp_css_irq_gpio_pin_8 = HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID , + hrt_isp_css_irq_gpio_pin_9 = HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID , + hrt_isp_css_irq_gpio_pin_10 = HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID , + hrt_isp_css_irq_gpio_pin_11 = HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID , + hrt_isp_css_irq_sp = HIVE_GP_DEV_IRQ_SP_BIT_ID , + hrt_isp_css_irq_isp = HIVE_GP_DEV_IRQ_ISP_BIT_ID , + hrt_isp_css_irq_isys = HIVE_GP_DEV_IRQ_ISYS_BIT_ID , + hrt_isp_css_irq_isel = HIVE_GP_DEV_IRQ_ISEL_BIT_ID , + hrt_isp_css_irq_ifmt = HIVE_GP_DEV_IRQ_IFMT_BIT_ID , + hrt_isp_css_irq_sp_stream_mon = HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID , + hrt_isp_css_irq_isp_stream_mon = HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID , + hrt_isp_css_irq_mod_stream_mon = HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID , + hrt_isp_css_irq_is2401 = HIVE_GP_DEV_IRQ_IS2401_BIT_ID , + hrt_isp_css_irq_isp_bamem_error = HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID , + hrt_isp_css_irq_isp_dmem_error = HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID , + hrt_isp_css_irq_sp_icache_mem_error = HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID , + hrt_isp_css_irq_sp_dmem_error = HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID , + hrt_isp_css_irq_mmu_cache_mem_error = HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID , + hrt_isp_css_irq_gp_timer_0 = HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID , + hrt_isp_css_irq_gp_timer_1 = HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID , + hrt_isp_css_irq_sw_pin_0 = HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID , + hrt_isp_css_irq_sw_pin_1 = HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID , + hrt_isp_css_irq_dma = HIVE_GP_DEV_IRQ_DMA_BIT_ID , + hrt_isp_css_irq_sp_stream_mon_b = HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID , + /* this must (obviously) be the last on in the enum */ + hrt_isp_css_irq_num_irqs +} hrt_isp_css_irq_t; + +typedef enum hrt_isp_css_irq_status { + hrt_isp_css_irq_status_error, + hrt_isp_css_irq_status_more_irqs, + hrt_isp_css_irq_status_success +} hrt_isp_css_irq_status_t; + +#endif /* _HIVE_ISP_CSS_2401_IRQ_TYPES_HRT_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/hive_isp_css_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/hive_isp_css_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..5a2ce9108ae4968221b5690d3d641d579732e631 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/hive_isp_css_defs.h @@ -0,0 +1,435 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _hive_isp_css_defs_h__ +#define _hive_isp_css_defs_h__ + +#define _HIVE_ISP_CSS_2401_SYSTEM 1 +#define HIVE_ISP_CTRL_DATA_WIDTH 32 +#define HIVE_ISP_CTRL_ADDRESS_WIDTH 32 +#define HIVE_ISP_CTRL_MAX_BURST_SIZE 1 +#define HIVE_ISP_DDR_ADDRESS_WIDTH 36 + +#define HIVE_ISP_HOST_MAX_BURST_SIZE 8 /* host supports bursts in order to prevent repeating DDRAM accesses */ +#define HIVE_ISP_NUM_GPIO_PINS 12 + +/* This list of vector num_elems/elem_bits pairs is valid both in C as initializer + and in the DMA parameter list */ +#define HIVE_ISP_DDR_DMA_SPECS {{32, 8}, {16, 16}, {18, 14}, {25, 10}, {21, 12}} +#define HIVE_ISP_DDR_WORD_BITS 256 +#define HIVE_ISP_DDR_WORD_BYTES (HIVE_ISP_DDR_WORD_BITS/8) +#define HIVE_ISP_DDR_BYTES (512 * 1024 * 1024) +#define HIVE_ISP_DDR_BYTES_RTL (127 * 1024 * 1024) +#define HIVE_ISP_DDR_SMALL_BYTES (128 * 256 / 8) +#define HIVE_ISP_PAGE_SHIFT 12 +#define HIVE_ISP_PAGE_SIZE (1< + +#define _HIVE_ISP_CH_ID_MASK ((1U << HIVE_ISP_CH_ID_BITS)-1) +#define _HIVE_ISP_FMT_TYPE_MASK ((1U << HIVE_ISP_FMT_TYPE_BITS)-1) + +#define _HIVE_STR_TO_MIPI_FMT_TYPE_LSB (HIVE_STR_TO_MIPI_CH_ID_LSB + HIVE_ISP_CH_ID_BITS) +#define _HIVE_STR_TO_MIPI_DATA_B_LSB (HIVE_STR_TO_MIPI_DATA_A_LSB + HIVE_IF_PIXEL_WIDTH) + +#endif /* _hive_isp_css_streaming_to_mipi_types_hrt_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/hive_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/hive_types.h new file mode 100644 index 0000000000000000000000000000000000000000..58b0e6effbd068fe9f2d175072bb1e66c921428a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/hive_types.h @@ -0,0 +1,128 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HRT_HIVE_TYPES_H +#define _HRT_HIVE_TYPES_H + +#include "version.h" +#include "defs.h" + +#ifndef HRTCAT3 +#define _HRTCAT3(m,n,o) m##n##o +#define HRTCAT3(m,n,o) _HRTCAT3(m,n,o) +#endif + +#ifndef HRTCAT4 +#define _HRTCAT4(m,n,o,p) m##n##o##p +#define HRTCAT4(m,n,o,p) _HRTCAT4(m,n,o,p) +#endif + +#ifndef HRTMIN +#define HRTMIN(a,b) (((a)<(b))?(a):(b)) +#endif + +#ifndef HRTMAX +#define HRTMAX(a,b) (((a)>(b))?(a):(b)) +#endif + +/* boolean data type */ +typedef unsigned int hive_bool; +#define hive_false 0 +#define hive_true 1 + +typedef char hive_int8; +typedef short hive_int16; +typedef int hive_int32; +typedef long long hive_int64; + +typedef unsigned char hive_uint8; +typedef unsigned short hive_uint16; +typedef unsigned int hive_uint32; +typedef unsigned long long hive_uint64; + +/* by default assume 32 bit master port (both data and address) */ +#ifndef HRT_DATA_WIDTH +#define HRT_DATA_WIDTH 32 +#endif +#ifndef HRT_ADDRESS_WIDTH +#define HRT_ADDRESS_WIDTH 32 +#endif + +#define HRT_DATA_BYTES (HRT_DATA_WIDTH/8) +#define HRT_ADDRESS_BYTES (HRT_ADDRESS_WIDTH/8) + +#if HRT_DATA_WIDTH == 64 +typedef hive_uint64 hrt_data; +#elif HRT_DATA_WIDTH == 32 +typedef hive_uint32 hrt_data; +#else +#error data width not supported +#endif + +#if HRT_ADDRESS_WIDTH == 64 +typedef hive_uint64 hrt_address; +#elif HRT_ADDRESS_WIDTH == 32 +typedef hive_uint32 hrt_address; +#else +#error adddres width not supported +#endif + +/* The SP side representation of an HMM virtual address */ +typedef hive_uint32 hrt_vaddress; + +/* use 64 bit addresses in simulation, where possible */ +typedef hive_uint64 hive_sim_address; + +/* below is for csim, not for hrt, rename and move this elsewhere */ + +typedef unsigned int hive_uint; +typedef hive_uint32 hive_address; +typedef hive_address hive_slave_address; +typedef hive_address hive_mem_address; + +/* MMIO devices */ +typedef hive_uint hive_mmio_id; +typedef hive_mmio_id hive_slave_id; +typedef hive_mmio_id hive_port_id; +typedef hive_mmio_id hive_master_id; +typedef hive_mmio_id hive_mem_id; +typedef hive_mmio_id hive_dev_id; +typedef hive_mmio_id hive_fifo_id; + +typedef hive_uint hive_hier_id; +typedef hive_hier_id hive_device_id; +typedef hive_device_id hive_proc_id; +typedef hive_device_id hive_cell_id; +typedef hive_device_id hive_host_id; +typedef hive_device_id hive_bus_id; +typedef hive_device_id hive_bridge_id; +typedef hive_device_id hive_fifo_adapter_id; +typedef hive_device_id hive_custom_device_id; + +typedef hive_uint hive_slot_id; +typedef hive_uint hive_fu_id; +typedef hive_uint hive_reg_file_id; +typedef hive_uint hive_reg_id; + +/* Streaming devices */ +typedef hive_uint hive_outport_id; +typedef hive_uint hive_inport_id; + +typedef hive_uint hive_msink_id; + +/* HRT specific */ +typedef char* hive_program; +typedef char* hive_function; + +#endif /* _HRT_HIVE_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/if_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/if_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..7d39e45796ae17965aee2ef1fb61f0d76a03b88f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/if_defs.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IF_DEFS_H +#define _IF_DEFS_H + +#define HIVE_IF_FRAME_REQUEST 0xA000 +#define HIVE_IF_LINES_REQUEST 0xB000 +#define HIVE_IF_VECTORS_REQUEST 0xC000 + +#endif /* _IF_DEFS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_formatter_subsystem_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_formatter_subsystem_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..16bfe1d80bc96a1f0c25f7d818db5d1dfff5003b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_formatter_subsystem_defs.h @@ -0,0 +1,53 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _if_subsystem_defs_h +#define _if_subsystem_defs_h__ + +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0 0 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_1 1 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_2 2 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_3 3 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_4 4 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_5 5 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_6 6 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_7 7 +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_FSYNC_LUT_REG 8 +#define HIVE_IFMT_GP_REGS_SRST_IDX 9 +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IDX 10 + +#define HIVE_IFMT_GP_REGS_CH_ID_FMT_TYPE_IDX 11 + +#define HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_BASE HIVE_IFMT_GP_REGS_INPUT_SWITCH_LUT_REG_0 + +/* order of the input bits for the ifmt irq controller */ +#define HIVE_IFMT_IRQ_IFT_PRIM_BIT_ID 0 +#define HIVE_IFMT_IRQ_IFT_PRIM_B_BIT_ID 1 +#define HIVE_IFMT_IRQ_IFT_SEC_BIT_ID 2 +#define HIVE_IFMT_IRQ_MEM_CPY_BIT_ID 3 +#define HIVE_IFMT_IRQ_SIDEBAND_CHANGED_BIT_ID 4 + +/* order of the input bits for the ifmt Soft reset register */ +#define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_BIT_IDX 0 +#define HIVE_IFMT_GP_REGS_SRST_IFT_PRIM_B_BIT_IDX 1 +#define HIVE_IFMT_GP_REGS_SRST_IFT_SEC_BIT_IDX 2 +#define HIVE_IFMT_GP_REGS_SRST_MEM_CPY_BIT_IDX 3 + +/* order of the input bits for the ifmt Soft reset register */ +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_BIT_IDX 0 +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_PRIM_B_BIT_IDX 1 +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_IFT_SEC_BIT_IDX 2 +#define HIVE_IFMT_GP_REGS_SLV_REG_SRST_MEM_CPY_BIT_IDX 3 + +#endif /* _if_subsystem_defs_h__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_selector_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_selector_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..87fbf82edb5bc44d6c5ca761c06aa57a8606fc97 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_selector_defs.h @@ -0,0 +1,89 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _input_selector_defs_h +#define _input_selector_defs_h + +#ifndef HIVE_ISP_ISEL_SEL_BITS +#define HIVE_ISP_ISEL_SEL_BITS 2 +#endif + +#ifndef HIVE_ISP_CH_ID_BITS +#define HIVE_ISP_CH_ID_BITS 2 +#endif + +#ifndef HIVE_ISP_FMT_TYPE_BITS +#define HIVE_ISP_FMT_TYPE_BITS 5 +#endif + +/* gp_register register id's -- Outputs */ +#define HIVE_ISEL_GP_REGS_SYNCGEN_ENABLE_IDX 0 +#define HIVE_ISEL_GP_REGS_SYNCGEN_FREE_RUNNING_IDX 1 +#define HIVE_ISEL_GP_REGS_SYNCGEN_PAUSE_IDX 2 +#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_FRAMES_IDX 3 +#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_PIX_IDX 4 +#define HIVE_ISEL_GP_REGS_SYNCGEN_NR_LINES_IDX 5 +#define HIVE_ISEL_GP_REGS_SYNCGEN_HBLANK_CYCLES_IDX 6 +#define HIVE_ISEL_GP_REGS_SYNCGEN_VBLANK_CYCLES_IDX 7 + +#define HIVE_ISEL_GP_REGS_SOF_IDX 8 +#define HIVE_ISEL_GP_REGS_EOF_IDX 9 +#define HIVE_ISEL_GP_REGS_SOL_IDX 10 +#define HIVE_ISEL_GP_REGS_EOL_IDX 11 + +#define HIVE_ISEL_GP_REGS_PRBS_ENABLE 12 +#define HIVE_ISEL_GP_REGS_PRBS_ENABLE_PORT_B 13 +#define HIVE_ISEL_GP_REGS_PRBS_LFSR_RESET_VALUE 14 + +#define HIVE_ISEL_GP_REGS_TPG_ENABLE 15 +#define HIVE_ISEL_GP_REGS_TPG_ENABLE_PORT_B 16 +#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_MASK_IDX 17 +#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_MASK_IDX 18 +#define HIVE_ISEL_GP_REGS_TPG_XY_CNT_MASK_IDX 19 +#define HIVE_ISEL_GP_REGS_TPG_HOR_CNT_DELTA_IDX 20 +#define HIVE_ISEL_GP_REGS_TPG_VER_CNT_DELTA_IDX 21 +#define HIVE_ISEL_GP_REGS_TPG_MODE_IDX 22 +#define HIVE_ISEL_GP_REGS_TPG_R1_IDX 23 +#define HIVE_ISEL_GP_REGS_TPG_G1_IDX 24 +#define HIVE_ISEL_GP_REGS_TPG_B1_IDX 25 +#define HIVE_ISEL_GP_REGS_TPG_R2_IDX 26 +#define HIVE_ISEL_GP_REGS_TPG_G2_IDX 27 +#define HIVE_ISEL_GP_REGS_TPG_B2_IDX 28 + + +#define HIVE_ISEL_GP_REGS_CH_ID_IDX 29 +#define HIVE_ISEL_GP_REGS_FMT_TYPE_IDX 30 +#define HIVE_ISEL_GP_REGS_DATA_SEL_IDX 31 +#define HIVE_ISEL_GP_REGS_SBAND_SEL_IDX 32 +#define HIVE_ISEL_GP_REGS_SYNC_SEL_IDX 33 +#define HIVE_ISEL_GP_REGS_SRST_IDX 37 + +#define HIVE_ISEL_GP_REGS_SRST_SYNCGEN_BIT 0 +#define HIVE_ISEL_GP_REGS_SRST_PRBS_BIT 1 +#define HIVE_ISEL_GP_REGS_SRST_TPG_BIT 2 +#define HIVE_ISEL_GP_REGS_SRST_FIFO_BIT 3 + +/* gp_register register id's -- Inputs */ +#define HIVE_ISEL_GP_REGS_SYNCGEN_HOR_CNT_IDX 34 +#define HIVE_ISEL_GP_REGS_SYNCGEN_VER_CNT_IDX 35 +#define HIVE_ISEL_GP_REGS_SYNCGEN_FRAMES_CNT_IDX 36 + +/* irq sources isel irq controller */ +#define HIVE_ISEL_IRQ_SYNC_GEN_SOF_BIT_ID 0 +#define HIVE_ISEL_IRQ_SYNC_GEN_EOF_BIT_ID 1 +#define HIVE_ISEL_IRQ_SYNC_GEN_SOL_BIT_ID 2 +#define HIVE_ISEL_IRQ_SYNC_GEN_EOL_BIT_ID 3 +#define HIVE_ISEL_IRQ_NUM_IRQS 4 + +#endif /* _input_selector_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_switch_2400_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_switch_2400_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..20a13c4cdb562fc8773992317d0b9b4a06a149cb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_switch_2400_defs.h @@ -0,0 +1,30 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _input_switch_2400_defs_h +#define _input_switch_2400_defs_h + +#define _HIVE_INPUT_SWITCH_GET_LUT_REG_ID(ch_id, fmt_type) (((ch_id)*2) + ((fmt_type)>=16)) +#define _HIVE_INPUT_SWITCH_GET_LUT_REG_LSB(fmt_type) (((fmt_type)%16) * 2) + +#define HIVE_INPUT_SWITCH_SELECT_NO_OUTPUT 0 +#define HIVE_INPUT_SWITCH_SELECT_IF_PRIM 1 +#define HIVE_INPUT_SWITCH_SELECT_IF_SEC 2 +#define HIVE_INPUT_SWITCH_SELECT_STR_TO_MEM 3 +#define HIVE_INPUT_SWITCH_VSELECT_NO_OUTPUT 0 +#define HIVE_INPUT_SWITCH_VSELECT_IF_PRIM 1 +#define HIVE_INPUT_SWITCH_VSELECT_IF_SEC 2 +#define HIVE_INPUT_SWITCH_VSELECT_STR_TO_MEM 4 + +#endif /* _input_switch_2400_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_system_ctrl_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_system_ctrl_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..a7f0ca80bc9be0afed16a0726fdd068946aef12a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_system_ctrl_defs.h @@ -0,0 +1,254 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _input_system_ctrl_defs_h +#define _input_system_ctrl_defs_h + +#define _INPUT_SYSTEM_CTRL_REG_ALIGN 4 /* assuming 32 bit control bus width */ + +/* --------------------------------------------------*/ + +/* --------------------------------------------------*/ +/* REGISTER INFO */ +/* --------------------------------------------------*/ + +// Number of registers +#define ISYS_CTRL_NOF_REGS 23 + +// Register id's of MMIO slave accesible registers +#define ISYS_CTRL_CAPT_START_ADDR_A_REG_ID 0 +#define ISYS_CTRL_CAPT_START_ADDR_B_REG_ID 1 +#define ISYS_CTRL_CAPT_START_ADDR_C_REG_ID 2 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID 3 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID 4 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID 5 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID 6 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID 7 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID 8 +#define ISYS_CTRL_ACQ_START_ADDR_REG_ID 9 +#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID 10 +#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID 11 +#define ISYS_CTRL_INIT_REG_ID 12 +#define ISYS_CTRL_LAST_COMMAND_REG_ID 13 +#define ISYS_CTRL_NEXT_COMMAND_REG_ID 14 +#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_ID 15 +#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_ID 16 +#define ISYS_CTRL_FSM_STATE_INFO_REG_ID 17 +#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_ID 18 +#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_ID 19 +#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID 20 +#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID 21 +#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID 22 + + +/* register reset value */ +#define ISYS_CTRL_CAPT_START_ADDR_A_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_START_ADDR_B_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_START_ADDR_C_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_RSTVAL 128 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_RSTVAL 128 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_RSTVAL 128 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_RSTVAL 3 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_RSTVAL 3 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_RSTVAL 3 +#define ISYS_CTRL_ACQ_START_ADDR_REG_RSTVAL 0 +#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_RSTVAL 128 +#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3 +#define ISYS_CTRL_INIT_REG_RSTVAL 0 +#define ISYS_CTRL_LAST_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) +#define ISYS_CTRL_NEXT_COMMAND_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) +#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) +#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_RSTVAL 15 //0x0000_000F (to signal non-valid cmd/ack after reset/soft-reset) +#define ISYS_CTRL_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_RSTVAL 0 +#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_RSTVAL 0 + +/* register width value */ +#define ISYS_CTRL_CAPT_START_ADDR_A_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_START_ADDR_B_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_START_ADDR_C_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_WIDTH 9 +#define ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_WIDTH 9 +#define ISYS_CTRL_ACQ_START_ADDR_REG_WIDTH 9 +#define ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_WIDTH 9 +#define ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_WIDTH 9 +#define ISYS_CTRL_INIT_REG_WIDTH 3 +#define ISYS_CTRL_LAST_COMMAND_REG_WIDTH 32 /* slave data width */ +#define ISYS_CTRL_NEXT_COMMAND_REG_WIDTH 32 +#define ISYS_CTRL_LAST_ACKNOWLEDGE_REG_WIDTH 32 +#define ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_WIDTH 32 +#define ISYS_CTRL_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_WIDTH 32 +#define ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_WIDTH 1 + +/* bit definitions */ + +/* --------------------------------------------------*/ +/* TOKEN INFO */ +/* --------------------------------------------------*/ + +/* +InpSysCaptFramesAcq 1/0 [3:0] - 'b0000 +[7:4] - CaptPortId, + CaptA-'b0000 + CaptB-'b0001 + CaptC-'b0010 +[31:16] - NOF_frames +InpSysCaptFrameExt 2/0 [3:0] - 'b0001' +[7:4] - CaptPortId, + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + + 2/1 [31:0] - external capture address +InpSysAcqFrame 2/0 [3:0] - 'b0010, +[31:4] - NOF_ext_mem_words + 2/1 [31:0] - external memory read start address +InpSysOverruleON 1/0 [3:0] - 'b0011, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + +InpSysOverruleOFF 1/0 [3:0] - 'b0100, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + +InpSysOverruleCmd 2/0 [3:0] - 'b0101, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + + 2/1 [31:0] - command token value for port opid + + +acknowledge tokens: + +InpSysAckCFA 1/0 [3:0] - 'b0000 + [7:4] - CaptPortId, + CaptA-'b0000 + CaptB- 'b0001 + CaptC-'b0010 + [31:16] - NOF_frames +InpSysAckCFE 1/0 [3:0] - 'b0001' +[7:4] - CaptPortId, + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + +InpSysAckAF 1/0 [3:0] - 'b0010 +InpSysAckOverruleON 1/0 [3:0] - 'b0011, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + +InpSysAckOverruleOFF 1/0 [3:0] - 'b0100, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + +InpSysAckOverrule 2/0 [3:0] - 'b0101, +[7:4] - overrule port id (opid) + 'b0000 - CaptA + 'b0001 - CaptB + 'b0010 - CaptC + 'b0011 - Acq + 'b0100 - DMA + + + 2/1 [31:0] - acknowledge token value from port opid + + + +*/ + + +/* Command and acknowledge tokens IDs */ +#define ISYS_CTRL_CAPT_FRAMES_ACQ_TOKEN_ID 0 /* 0000b */ +#define ISYS_CTRL_CAPT_FRAME_EXT_TOKEN_ID 1 /* 0001b */ +#define ISYS_CTRL_ACQ_FRAME_TOKEN_ID 2 /* 0010b */ +#define ISYS_CTRL_OVERRULE_ON_TOKEN_ID 3 /* 0011b */ +#define ISYS_CTRL_OVERRULE_OFF_TOKEN_ID 4 /* 0100b */ +#define ISYS_CTRL_OVERRULE_TOKEN_ID 5 /* 0101b */ + +#define ISYS_CTRL_ACK_CFA_TOKEN_ID 0 +#define ISYS_CTRL_ACK_CFE_TOKEN_ID 1 +#define ISYS_CTRL_ACK_AF_TOKEN_ID 2 +#define ISYS_CTRL_ACK_OVERRULE_ON_TOKEN_ID 3 +#define ISYS_CTRL_ACK_OVERRULE_OFF_TOKEN_ID 4 +#define ISYS_CTRL_ACK_OVERRULE_TOKEN_ID 5 +#define ISYS_CTRL_ACK_DEVICE_ERROR_TOKEN_ID 6 + +#define ISYS_CTRL_TOKEN_ID_MSB 3 +#define ISYS_CTRL_TOKEN_ID_LSB 0 +#define ISYS_CTRL_PORT_ID_TOKEN_MSB 7 +#define ISYS_CTRL_PORT_ID_TOKEN_LSB 4 +#define ISYS_CTRL_NOF_CAPT_TOKEN_MSB 31 +#define ISYS_CTRL_NOF_CAPT_TOKEN_LSB 16 +#define ISYS_CTRL_NOF_EXT_TOKEN_MSB 31 +#define ISYS_CTRL_NOF_EXT_TOKEN_LSB 8 + +#define ISYS_CTRL_TOKEN_ID_IDX 0 +#define ISYS_CTRL_TOKEN_ID_BITS (ISYS_CTRL_TOKEN_ID_MSB - ISYS_CTRL_TOKEN_ID_LSB + 1) +#define ISYS_CTRL_PORT_ID_IDX (ISYS_CTRL_TOKEN_ID_IDX + ISYS_CTRL_TOKEN_ID_BITS) +#define ISYS_CTRL_PORT_ID_BITS (ISYS_CTRL_PORT_ID_TOKEN_MSB - ISYS_CTRL_PORT_ID_TOKEN_LSB +1) +#define ISYS_CTRL_NOF_CAPT_IDX ISYS_CTRL_NOF_CAPT_TOKEN_LSB +#define ISYS_CTRL_NOF_CAPT_BITS (ISYS_CTRL_NOF_CAPT_TOKEN_MSB - ISYS_CTRL_NOF_CAPT_TOKEN_LSB + 1) +#define ISYS_CTRL_NOF_EXT_IDX ISYS_CTRL_NOF_EXT_TOKEN_LSB +#define ISYS_CTRL_NOF_EXT_BITS (ISYS_CTRL_NOF_EXT_TOKEN_MSB - ISYS_CTRL_NOF_EXT_TOKEN_LSB + 1) + +#define ISYS_CTRL_PORT_ID_CAPT_A 0 /* device ID for capture unit A */ +#define ISYS_CTRL_PORT_ID_CAPT_B 1 /* device ID for capture unit B */ +#define ISYS_CTRL_PORT_ID_CAPT_C 2 /* device ID for capture unit C */ +#define ISYS_CTRL_PORT_ID_ACQUISITION 3 /* device ID for acquistion unit */ +#define ISYS_CTRL_PORT_ID_DMA_CAPT_A 4 /* device ID for dma unit */ +#define ISYS_CTRL_PORT_ID_DMA_CAPT_B 5 /* device ID for dma unit */ +#define ISYS_CTRL_PORT_ID_DMA_CAPT_C 6 /* device ID for dma unit */ +#define ISYS_CTRL_PORT_ID_DMA_ACQ 7 /* device ID for dma unit */ + +#define ISYS_CTRL_NO_ACQ_ACK 16 /* no ack from acquisition unit */ +#define ISYS_CTRL_NO_DMA_ACK 0 +#define ISYS_CTRL_NO_CAPT_ACK 16 + +#endif /* _input_system_ctrl_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_system_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_system_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..ae62163034a66d6bae8fb55feadcb2de8cbfbddd --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/input_system_defs.h @@ -0,0 +1,126 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _input_system_defs_h +#define _input_system_defs_h + +/* csi controller modes */ +#define HIVE_CSI_CONFIG_MAIN 0 +#define HIVE_CSI_CONFIG_STEREO1 4 +#define HIVE_CSI_CONFIG_STEREO2 8 + +/* general purpose register IDs */ + +/* Stream Multicast select modes */ +#define HIVE_ISYS_GPREG_MULTICAST_A_IDX 0 +#define HIVE_ISYS_GPREG_MULTICAST_B_IDX 1 +#define HIVE_ISYS_GPREG_MULTICAST_C_IDX 2 + +/* Stream Mux select modes */ +#define HIVE_ISYS_GPREG_MUX_IDX 3 + +/* streaming monitor status and control */ +#define HIVE_ISYS_GPREG_STRMON_STAT_IDX 4 +#define HIVE_ISYS_GPREG_STRMON_COND_IDX 5 +#define HIVE_ISYS_GPREG_STRMON_IRQ_EN_IDX 6 +#define HIVE_ISYS_GPREG_SRST_IDX 7 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_IDX 8 +#define HIVE_ISYS_GPREG_REG_PORT_A_IDX 9 +#define HIVE_ISYS_GPREG_REG_PORT_B_IDX 10 + +/* Bit numbers of the soft reset register */ +#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_A_BIT 0 +#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_B_BIT 1 +#define HIVE_ISYS_GPREG_SRST_CAPT_FIFO_C_BIT 2 +#define HIVE_ISYS_GPREG_SRST_MULTICAST_A_BIT 3 +#define HIVE_ISYS_GPREG_SRST_MULTICAST_B_BIT 4 +#define HIVE_ISYS_GPREG_SRST_MULTICAST_C_BIT 5 +#define HIVE_ISYS_GPREG_SRST_CAPT_A_BIT 6 +#define HIVE_ISYS_GPREG_SRST_CAPT_B_BIT 7 +#define HIVE_ISYS_GPREG_SRST_CAPT_C_BIT 8 +#define HIVE_ISYS_GPREG_SRST_ACQ_BIT 9 +/* For ISYS_CTRL 5bits are defined to allow soft-reset per sub-controller and top-ctrl */ +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_BIT 10 /*LSB for 5bit vector */ +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_A_BIT 10 +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_B_BIT 11 +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_CAPT_C_BIT 12 +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_ACQ_BIT 13 +#define HIVE_ISYS_GPREG_SRST_ISYS_CTRL_TOP_BIT 14 +/* -- */ +#define HIVE_ISYS_GPREG_SRST_STR_MUX_BIT 15 +#define HIVE_ISYS_GPREG_SRST_CIO2AHB_BIT 16 +#define HIVE_ISYS_GPREG_SRST_GEN_SHORT_FIFO_BIT 17 +#define HIVE_ISYS_GPREG_SRST_WIDE_BUS_BIT 18 // includes CIO conv +#define HIVE_ISYS_GPREG_SRST_DMA_BIT 19 +#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_A_BIT 20 +#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_B_BIT 21 +#define HIVE_ISYS_GPREG_SRST_SF_CTRL_CAPT_C_BIT 22 +#define HIVE_ISYS_GPREG_SRST_SF_CTRL_ACQ_BIT 23 +#define HIVE_ISYS_GPREG_SRST_CSI_BE_OUT_BIT 24 + +#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_A_BIT 0 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_B_BIT 1 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_CAPT_C_BIT 2 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_ACQ_BIT 3 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_DMA_BIT 4 +#define HIVE_ISYS_GPREG_SLV_REG_SRST_ISYS_CTRL_BIT 5 + +/* streaming monitor port id's */ +#define HIVE_ISYS_STR_MON_PORT_CAPA 0 +#define HIVE_ISYS_STR_MON_PORT_CAPB 1 +#define HIVE_ISYS_STR_MON_PORT_CAPC 2 +#define HIVE_ISYS_STR_MON_PORT_ACQ 3 +#define HIVE_ISYS_STR_MON_PORT_CSS_GENSH 4 +#define HIVE_ISYS_STR_MON_PORT_SF_GENSH 5 +#define HIVE_ISYS_STR_MON_PORT_SP2ISYS 6 +#define HIVE_ISYS_STR_MON_PORT_ISYS2SP 7 +#define HIVE_ISYS_STR_MON_PORT_PIXA 8 +#define HIVE_ISYS_STR_MON_PORT_PIXB 9 + +/* interrupt bit ID's */ +#define HIVE_ISYS_IRQ_CSI_SOF_BIT_ID 0 +#define HIVE_ISYS_IRQ_CSI_EOF_BIT_ID 1 +#define HIVE_ISYS_IRQ_CSI_SOL_BIT_ID 2 +#define HIVE_ISYS_IRQ_CSI_EOL_BIT_ID 3 +#define HIVE_ISYS_IRQ_CSI_RECEIVER_BIT_ID 4 +#define HIVE_ISYS_IRQ_CSI_RECEIVER_BE_BIT_ID 5 +#define HIVE_ISYS_IRQ_CAP_UNIT_A_NO_SOP 6 +#define HIVE_ISYS_IRQ_CAP_UNIT_A_LATE_SOP 7 +/*#define HIVE_ISYS_IRQ_CAP_UNIT_A_UNDEF_PH 7*/ +#define HIVE_ISYS_IRQ_CAP_UNIT_B_NO_SOP 8 +#define HIVE_ISYS_IRQ_CAP_UNIT_B_LATE_SOP 9 +/*#define HIVE_ISYS_IRQ_CAP_UNIT_B_UNDEF_PH 10*/ +#define HIVE_ISYS_IRQ_CAP_UNIT_C_NO_SOP 10 +#define HIVE_ISYS_IRQ_CAP_UNIT_C_LATE_SOP 11 +/*#define HIVE_ISYS_IRQ_CAP_UNIT_C_UNDEF_PH 13*/ +#define HIVE_ISYS_IRQ_ACQ_UNIT_SOP_MISMATCH 12 +/*#define HIVE_ISYS_IRQ_ACQ_UNIT_UNDEF_PH 15*/ +#define HIVE_ISYS_IRQ_INP_CTRL_CAPA 13 +#define HIVE_ISYS_IRQ_INP_CTRL_CAPB 14 +#define HIVE_ISYS_IRQ_INP_CTRL_CAPC 15 +#define HIVE_ISYS_IRQ_CIO2AHB 16 +#define HIVE_ISYS_IRQ_DMA_BIT_ID 17 +#define HIVE_ISYS_IRQ_STREAM_MON_BIT_ID 18 +#define HIVE_ISYS_IRQ_NUM_BITS 19 + +/* DMA */ +#define HIVE_ISYS_DMA_CHANNEL 0 +#define HIVE_ISYS_DMA_IBUF_DDR_CONN 0 +#define HIVE_ISYS_DMA_HEIGHT 1 +#define HIVE_ISYS_DMA_ELEMS 1 /* both master buses of same width */ +#define HIVE_ISYS_DMA_STRIDE 0 /* no stride required as height is fixed to 1 */ +#define HIVE_ISYS_DMA_CROP 0 /* no cropping */ +#define HIVE_ISYS_DMA_EXTENSION 0 /* no extension as elem width is same on both side */ + +#endif /* _input_system_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/irq_controller_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/irq_controller_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..ec6dd4487158e4fabf4e587684e4290ffdd23ed2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/irq_controller_defs.h @@ -0,0 +1,28 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _irq_controller_defs_h +#define _irq_controller_defs_h + +#define _HRT_IRQ_CONTROLLER_EDGE_REG_IDX 0 +#define _HRT_IRQ_CONTROLLER_MASK_REG_IDX 1 +#define _HRT_IRQ_CONTROLLER_STATUS_REG_IDX 2 +#define _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX 3 +#define _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX 4 +#define _HRT_IRQ_CONTROLLER_EDGE_NOT_PULSE_REG_IDX 5 +#define _HRT_IRQ_CONTROLLER_STR_OUT_ENABLE_REG_IDX 6 + +#define _HRT_IRQ_CONTROLLER_REG_ALIGN 4 + +#endif /* _irq_controller_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/isp2400_support.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/isp2400_support.h new file mode 100644 index 0000000000000000000000000000000000000000..e00bc841d0f0d2c00e942467981630e5051d040a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/isp2400_support.h @@ -0,0 +1,38 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _isp2400_support_h +#define _isp2400_support_h + +#ifndef ISP2400_VECTOR_TYPES +/* This typedef is to be able to include hive header files + in the host code which is useful in crun */ +typedef char *tmemvectors, *tmemvectoru, *tvector; +#endif + +#define hrt_isp_vamem1_store_16(cell, addr, val) hrt_mem_store_16(cell, HRT_PROC_TYPE_PROP(cell, _simd_vamem1), addr, val) +#define hrt_isp_vamem2_store_16(cell, addr, val) hrt_mem_store_16(cell, HRT_PROC_TYPE_PROP(cell, _simd_vamem2), addr, val) + +#define hrt_isp_dmem(cell) HRT_PROC_TYPE_PROP(cell, _base_dmem) +#define hrt_isp_vmem(cell) HRT_PROC_TYPE_PROP(cell, _simd_vmem) + +#define hrt_isp_dmem_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_dmem(cell)) +#define hrt_isp_vmem_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_vmem(cell)) + +#if ISP_HAS_HIST + #define hrt_isp_hist(cell) HRT_PROC_TYPE_PROP(cell, _simd_histogram) + #define hrt_isp_hist_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_isp_hist(cell)) +#endif + +#endif /* _isp2400_support_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/isp2401_mamoiada_params.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/isp2401_mamoiada_params.h new file mode 100644 index 0000000000000000000000000000000000000000..033e23bcf672ae5ddfabeec7b2978d7b9f1f05b8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/isp2401_mamoiada_params.h @@ -0,0 +1,258 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* Version */ +#define RTL_VERSION + +/* Cell name */ +#define ISP_CELL_TYPE isp2401_mamoiada +#define ISP_VMEM simd_vmem +#define _HRT_ISP_VMEM isp2401_mamoiada_simd_vmem + +/* instruction pipeline depth */ +#define ISP_BRANCHDELAY 5 + +/* bus */ +#define ISP_BUS_WIDTH 32 +#define ISP_BUS_ADDR_WIDTH 32 +#define ISP_BUS_BURST_SIZE 1 + +/* data-path */ +#define ISP_SCALAR_WIDTH 32 +#define ISP_SLICE_NELEMS 4 +#define ISP_VEC_NELEMS 64 +#define ISP_VEC_ELEMBITS 14 +#define ISP_VEC_ELEM8BITS 16 +#define ISP_CLONE_DATAPATH_IS_16 1 + +/* memories */ +#define ISP_DMEM_DEPTH 4096 +#define ISP_DMEM_BSEL_DOWNSAMPLE 8 +#define ISP_VMEM_DEPTH 3072 +#define ISP_VMEM_BSEL_DOWNSAMPLE 8 +#define ISP_VMEM_ELEMBITS 14 +#define ISP_VMEM_ELEM_PRECISION 14 +#define ISP_VMEM_IS_BAMEM 1 +#if ISP_VMEM_IS_BAMEM + #define ISP_VMEM_BAMEM_MAX_BOI_HEIGHT 8 + #define ISP_VMEM_BAMEM_LATENCY 5 + #define ISP_VMEM_BAMEM_BANK_NARROWING_FACTOR 2 + #define ISP_VMEM_BAMEM_NR_DATA_PLANES 8 + #define ISP_VMEM_BAMEM_NR_CFG_REGISTERS 16 + #define ISP_VMEM_BAMEM_LININT 0 + #define ISP_VMEM_BAMEM_DAP_BITS 3 + #define ISP_VMEM_BAMEM_LININT_FRAC_BITS 0 + #define ISP_VMEM_BAMEM_PID_BITS 3 + #define ISP_VMEM_BAMEM_OFFSET_BITS 19 + #define ISP_VMEM_BAMEM_ADDRESS_BITS 25 + #define ISP_VMEM_BAMEM_RID_BITS 4 + #define ISP_VMEM_BAMEM_TRANSPOSITION 1 + #define ISP_VMEM_BAMEM_VEC_PLUS_SLICE 1 + #define ISP_VMEM_BAMEM_ARB_SERVICE_CYCLE_BITS 1 + #define ISP_VMEM_BAMEM_LUT_ELEMS 16 + #define ISP_VMEM_BAMEM_LUT_ADDR_WIDTH 14 + #define ISP_VMEM_BAMEM_HALF_BLOCK_WRITE 1 + #define ISP_VMEM_BAMEM_SMART_FETCH 1 + #define ISP_VMEM_BAMEM_BIG_ENDIANNESS 0 +#endif /* ISP_VMEM_IS_BAMEM */ +#define ISP_PMEM_DEPTH 2048 +#define ISP_PMEM_WIDTH 640 +#define ISP_VAMEM_ADDRESS_BITS 12 +#define ISP_VAMEM_ELEMBITS 12 +#define ISP_VAMEM_DEPTH 2048 +#define ISP_VAMEM_ALIGNMENT 2 +#define ISP_VA_ADDRESS_WIDTH 896 +#define ISP_VEC_VALSU_LATENCY ISP_VEC_NELEMS +#define ISP_HIST_ADDRESS_BITS 12 +#define ISP_HIST_ALIGNMENT 4 +#define ISP_HIST_COMP_IN_PREC 12 +#define ISP_HIST_DEPTH 1024 +#define ISP_HIST_WIDTH 24 +#define ISP_HIST_COMPONENTS 4 + +/* program counter */ +#define ISP_PC_WIDTH 13 + +/* Template switches */ +#define ISP_SHIELD_INPUT_DMEM 0 +#define ISP_SHIELD_OUTPUT_DMEM 1 +#define ISP_SHIELD_INPUT_VMEM 0 +#define ISP_SHIELD_OUTPUT_VMEM 0 +#define ISP_SHIELD_INPUT_PMEM 1 +#define ISP_SHIELD_OUTPUT_PMEM 1 +#define ISP_SHIELD_INPUT_HIST 1 +#define ISP_SHIELD_OUTPUT_HIST 1 +/* When LUT is select the shielding is always on */ +#define ISP_SHIELD_INPUT_VAMEM 1 +#define ISP_SHIELD_OUTPUT_VAMEM 1 + +#define ISP_HAS_IRQ 1 +#define ISP_HAS_SOFT_RESET 1 +#define ISP_HAS_VEC_DIV 0 +#define ISP_HAS_VFU_W_2O 1 +#define ISP_HAS_DEINT3 1 +#define ISP_HAS_LUT 1 +#define ISP_HAS_HIST 1 +#define ISP_HAS_VALSU 1 +#define ISP_HAS_3rdVALSU 1 +#define ISP_VRF1_HAS_2P 1 + +#define ISP_SRU_GUARDING 1 +#define ISP_VLSU_GUARDING 1 + +#define ISP_VRF_RAM 1 +#define ISP_SRF_RAM 1 + +#define ISP_SPLIT_VMUL_VADD_IS 0 +#define ISP_RFSPLIT_FPGA 0 + +/* RSN or Bus pipelining */ +#define ISP_RSN_PIPE 1 +#define ISP_VSF_BUS_PIPE 0 + +/* extra slave port to vmem */ +#define ISP_IF_VMEM 0 +#define ISP_GDC_VMEM 0 + +/* Streaming ports */ +#define ISP_IF 1 +#define ISP_IF_B 1 +#define ISP_GDC 1 +#define ISP_SCL 1 +#define ISP_GPFIFO 1 +#define ISP_SP 1 + +/* Removing Issue Slot(s) */ +#define ISP_HAS_NOT_SIMD_IS2 0 +#define ISP_HAS_NOT_SIMD_IS3 0 +#define ISP_HAS_NOT_SIMD_IS4 0 +#define ISP_HAS_NOT_SIMD_IS4_VADD 0 +#define ISP_HAS_NOT_SIMD_IS5 0 +#define ISP_HAS_NOT_SIMD_IS6 0 +#define ISP_HAS_NOT_SIMD_IS7 0 +#define ISP_HAS_NOT_SIMD_IS8 0 + +/* ICache */ +#define ISP_ICACHE 1 +#define ISP_ICACHE_ONLY 0 +#define ISP_ICACHE_PREFETCH 1 +#define ISP_ICACHE_INDEX_BITS 8 +#define ISP_ICACHE_SET_BITS 5 +#define ISP_ICACHE_BLOCKS_PER_SET_BITS 1 + +/* Experimental Flags */ +#define ISP_EXP_1 0 +#define ISP_EXP_2 0 +#define ISP_EXP_3 0 +#define ISP_EXP_4 0 +#define ISP_EXP_5 0 +#define ISP_EXP_6 0 + +/* Derived values */ +#define ISP_LOG2_PMEM_WIDTH 10 +#define ISP_VEC_WIDTH 896 +#define ISP_SLICE_WIDTH 56 +#define ISP_VMEM_WIDTH 896 +#define ISP_VMEM_ALIGN 128 +#if ISP_VMEM_IS_BAMEM + #define ISP_VMEM_ALIGN_ELEM 2 +#endif /* ISP_VMEM_IS_BAMEM */ +#define ISP_SIMDLSU 1 +#define ISP_LSU_IMM_BITS 12 + +/* convenient shortcuts for software*/ +#define ISP_NWAY ISP_VEC_NELEMS +#define NBITS ISP_VEC_ELEMBITS + +#define _isp_ceil_div(a,b) (((a)+(b)-1)/(b)) + +#ifdef C_RUN +#define ISP_VEC_ALIGN (_isp_ceil_div(ISP_VEC_WIDTH, 64)*8) +#else +#define ISP_VEC_ALIGN ISP_VMEM_ALIGN +#endif + +/* HRT specific vector support */ +#define isp2401_mamoiada_vector_alignment ISP_VEC_ALIGN +#define isp2401_mamoiada_vector_elem_bits ISP_VMEM_ELEMBITS +#define isp2401_mamoiada_vector_elem_precision ISP_VMEM_ELEM_PRECISION +#define isp2401_mamoiada_vector_num_elems ISP_VEC_NELEMS + +/* register file sizes */ +#define ISP_RF0_SIZE 64 +#define ISP_RF1_SIZE 16 +#define ISP_RF2_SIZE 64 +#define ISP_RF3_SIZE 4 +#define ISP_RF4_SIZE 64 +#define ISP_RF5_SIZE 16 +#define ISP_RF6_SIZE 16 +#define ISP_RF7_SIZE 16 +#define ISP_RF8_SIZE 16 +#define ISP_RF9_SIZE 16 +#define ISP_RF10_SIZE 16 +#define ISP_RF11_SIZE 16 +#define ISP_VRF1_SIZE 32 +#define ISP_VRF2_SIZE 32 +#define ISP_VRF3_SIZE 32 +#define ISP_VRF4_SIZE 32 +#define ISP_VRF5_SIZE 32 +#define ISP_VRF6_SIZE 32 +#define ISP_VRF7_SIZE 32 +#define ISP_VRF8_SIZE 32 +#define ISP_SRF1_SIZE 4 +#define ISP_SRF2_SIZE 64 +#define ISP_SRF3_SIZE 64 +#define ISP_SRF4_SIZE 32 +#define ISP_SRF5_SIZE 64 +#define ISP_FRF0_SIZE 16 +#define ISP_FRF1_SIZE 4 +#define ISP_FRF2_SIZE 16 +#define ISP_FRF3_SIZE 4 +#define ISP_FRF4_SIZE 4 +#define ISP_FRF5_SIZE 8 +#define ISP_FRF6_SIZE 4 +/* register file read latency */ +#define ISP_VRF1_READ_LAT 1 +#define ISP_VRF2_READ_LAT 1 +#define ISP_VRF3_READ_LAT 1 +#define ISP_VRF4_READ_LAT 1 +#define ISP_VRF5_READ_LAT 1 +#define ISP_VRF6_READ_LAT 1 +#define ISP_VRF7_READ_LAT 1 +#define ISP_VRF8_READ_LAT 1 +#define ISP_SRF1_READ_LAT 1 +#define ISP_SRF2_READ_LAT 1 +#define ISP_SRF3_READ_LAT 1 +#define ISP_SRF4_READ_LAT 1 +#define ISP_SRF5_READ_LAT 1 +#define ISP_SRF5_READ_LAT 1 +/* immediate sizes */ +#define ISP_IS1_IMM_BITS 14 +#define ISP_IS2_IMM_BITS 13 +#define ISP_IS3_IMM_BITS 14 +#define ISP_IS4_IMM_BITS 14 +#define ISP_IS5_IMM_BITS 9 +#define ISP_IS6_IMM_BITS 16 +#define ISP_IS7_IMM_BITS 9 +#define ISP_IS8_IMM_BITS 16 +#define ISP_IS9_IMM_BITS 11 +/* fifo depths */ +#define ISP_IF_FIFO_DEPTH 0 +#define ISP_IF_B_FIFO_DEPTH 0 +#define ISP_DMA_FIFO_DEPTH 0 +#define ISP_OF_FIFO_DEPTH 0 +#define ISP_GDC_FIFO_DEPTH 0 +#define ISP_SCL_FIFO_DEPTH 0 +#define ISP_GPFIFO_FIFO_DEPTH 0 +#define ISP_SP_FIFO_DEPTH 0 diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/isp_acquisition_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/isp_acquisition_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..59362072162710fbc0d5a5a47c11c48dd38b6861 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/isp_acquisition_defs.h @@ -0,0 +1,234 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _isp_acquisition_defs_h +#define _isp_acquisition_defs_h + +#define _ISP_ACQUISITION_REG_ALIGN 4 /* assuming 32 bit control bus width */ +#define _ISP_ACQUISITION_BYTES_PER_ELEM 4 + +/* --------------------------------------------------*/ + +#define NOF_ACQ_IRQS 1 + +/* --------------------------------------------------*/ +/* FSM */ +/* --------------------------------------------------*/ +#define MEM2STREAM_FSM_STATE_BITS 2 +#define ACQ_SYNCHRONIZER_FSM_STATE_BITS 2 + +/* --------------------------------------------------*/ +/* REGISTER INFO */ +/* --------------------------------------------------*/ + +#define NOF_ACQ_REGS 12 + +// Register id's of MMIO slave accesible registers +#define ACQ_START_ADDR_REG_ID 0 +#define ACQ_MEM_REGION_SIZE_REG_ID 1 +#define ACQ_NUM_MEM_REGIONS_REG_ID 2 +#define ACQ_INIT_REG_ID 3 +#define ACQ_RECEIVED_SHORT_PACKETS_REG_ID 4 +#define ACQ_RECEIVED_LONG_PACKETS_REG_ID 5 +#define ACQ_LAST_COMMAND_REG_ID 6 +#define ACQ_NEXT_COMMAND_REG_ID 7 +#define ACQ_LAST_ACKNOWLEDGE_REG_ID 8 +#define ACQ_NEXT_ACKNOWLEDGE_REG_ID 9 +#define ACQ_FSM_STATE_INFO_REG_ID 10 +#define ACQ_INT_CNTR_INFO_REG_ID 11 + +// Register width +#define ACQ_START_ADDR_REG_WIDTH 9 +#define ACQ_MEM_REGION_SIZE_REG_WIDTH 9 +#define ACQ_NUM_MEM_REGIONS_REG_WIDTH 9 +#define ACQ_INIT_REG_WIDTH 3 +#define ACQ_RECEIVED_SHORT_PACKETS_REG_WIDTH 32 +#define ACQ_RECEIVED_LONG_PACKETS_REG_WIDTH 32 +#define ACQ_LAST_COMMAND_REG_WIDTH 32 +#define ACQ_NEXT_COMMAND_REG_WIDTH 32 +#define ACQ_LAST_ACKNOWLEDGE_REG_WIDTH 32 +#define ACQ_NEXT_ACKNOWLEDGE_REG_WIDTH 32 +#define ACQ_FSM_STATE_INFO_REG_WIDTH ((MEM2STREAM_FSM_STATE_BITS * 3) + (ACQ_SYNCHRONIZER_FSM_STATE_BITS *3)) +#define ACQ_INT_CNTR_INFO_REG_WIDTH 32 + +/* register reset value */ +#define ACQ_START_ADDR_REG_RSTVAL 0 +#define ACQ_MEM_REGION_SIZE_REG_RSTVAL 128 +#define ACQ_NUM_MEM_REGIONS_REG_RSTVAL 3 +#define ACQ_INIT_REG_RSTVAL 0 +#define ACQ_RECEIVED_SHORT_PACKETS_REG_RSTVAL 0 +#define ACQ_RECEIVED_LONG_PACKETS_REG_RSTVAL 0 +#define ACQ_LAST_COMMAND_REG_RSTVAL 0 +#define ACQ_NEXT_COMMAND_REG_RSTVAL 0 +#define ACQ_LAST_ACKNOWLEDGE_REG_RSTVAL 0 +#define ACQ_NEXT_ACKNOWLEDGE_REG_RSTVAL 0 +#define ACQ_FSM_STATE_INFO_REG_RSTVAL 0 +#define ACQ_INT_CNTR_INFO_REG_RSTVAL 0 + +/* bit definitions */ +#define ACQ_INIT_RST_REG_BIT 0 +#define ACQ_INIT_RESYNC_BIT 2 +#define ACQ_INIT_RST_IDX ACQ_INIT_RST_REG_BIT +#define ACQ_INIT_RST_BITS 1 +#define ACQ_INIT_RESYNC_IDX ACQ_INIT_RESYNC_BIT +#define ACQ_INIT_RESYNC_BITS 1 + +/* --------------------------------------------------*/ +/* TOKEN INFO */ +/* --------------------------------------------------*/ +#define ACQ_TOKEN_ID_LSB 0 +#define ACQ_TOKEN_ID_MSB 3 +#define ACQ_TOKEN_WIDTH (ACQ_TOKEN_ID_MSB - ACQ_TOKEN_ID_LSB + 1) // 4 +#define ACQ_TOKEN_ID_IDX 0 +#define ACQ_TOKEN_ID_BITS ACQ_TOKEN_WIDTH +#define ACQ_INIT_CMD_INIT_IDX 4 +#define ACQ_INIT_CMD_INIT_BITS 3 +#define ACQ_CMD_START_ADDR_IDX 4 +#define ACQ_CMD_START_ADDR_BITS 9 +#define ACQ_CMD_NOFWORDS_IDX 13 +#define ACQ_CMD_NOFWORDS_BITS 9 +#define ACQ_MEM_REGION_ID_IDX 22 +#define ACQ_MEM_REGION_ID_BITS 9 +#define ACQ_PACKET_LENGTH_TOKEN_MSB 21 +#define ACQ_PACKET_LENGTH_TOKEN_LSB 13 +#define ACQ_PACKET_DATA_FORMAT_ID_TOKEN_MSB 9 +#define ACQ_PACKET_DATA_FORMAT_ID_TOKEN_LSB 4 +#define ACQ_PACKET_CH_ID_TOKEN_MSB 11 +#define ACQ_PACKET_CH_ID_TOKEN_LSB 10 +#define ACQ_PACKET_MEM_REGION_ID_TOKEN_MSB 12 /* only for capt_end_of_packet_written */ +#define ACQ_PACKET_MEM_REGION_ID_TOKEN_LSB 4 /* only for capt_end_of_packet_written */ + + +/* Command tokens IDs */ +#define ACQ_READ_REGION_AUTO_INCR_TOKEN_ID 0 //0000b +#define ACQ_READ_REGION_TOKEN_ID 1 //0001b +#define ACQ_READ_REGION_SOP_TOKEN_ID 2 //0010b +#define ACQ_INIT_TOKEN_ID 8 //1000b + +/* Acknowledge token IDs */ +#define ACQ_READ_REGION_ACK_TOKEN_ID 0 //0000b +#define ACQ_END_OF_PACKET_TOKEN_ID 4 //0100b +#define ACQ_END_OF_REGION_TOKEN_ID 5 //0101b +#define ACQ_SOP_MISMATCH_TOKEN_ID 6 //0110b +#define ACQ_UNDEF_PH_TOKEN_ID 7 //0111b + +#define ACQ_TOKEN_MEMREGIONID_MSB 30 +#define ACQ_TOKEN_MEMREGIONID_LSB 22 +#define ACQ_TOKEN_NOFWORDS_MSB 21 +#define ACQ_TOKEN_NOFWORDS_LSB 13 +#define ACQ_TOKEN_STARTADDR_MSB 12 +#define ACQ_TOKEN_STARTADDR_LSB 4 + + +/* --------------------------------------------------*/ +/* MIPI */ +/* --------------------------------------------------*/ + +#define WORD_COUNT_WIDTH 16 +#define PKT_CODE_WIDTH 6 +#define CHN_NO_WIDTH 2 +#define ERROR_INFO_WIDTH 8 + +#define LONG_PKTCODE_MAX 63 +#define LONG_PKTCODE_MIN 16 +#define SHORT_PKTCODE_MAX 15 + +#define EOF_CODE 1 + +/* --------------------------------------------------*/ +/* Packet Info */ +/* --------------------------------------------------*/ +#define ACQ_START_OF_FRAME 0 +#define ACQ_END_OF_FRAME 1 +#define ACQ_START_OF_LINE 2 +#define ACQ_END_OF_LINE 3 +#define ACQ_LINE_PAYLOAD 4 +#define ACQ_GEN_SH_PKT 5 + + +/* bit definition */ +#define ACQ_PKT_TYPE_IDX 16 +#define ACQ_PKT_TYPE_BITS 6 +#define ACQ_PKT_SOP_IDX 32 +#define ACQ_WORD_CNT_IDX 0 +#define ACQ_WORD_CNT_BITS 16 +#define ACQ_PKT_INFO_IDX 16 +#define ACQ_PKT_INFO_BITS 8 +#define ACQ_HEADER_DATA_IDX 0 +#define ACQ_HEADER_DATA_BITS 16 +#define ACQ_ACK_TOKEN_ID_IDX ACQ_TOKEN_ID_IDX +#define ACQ_ACK_TOKEN_ID_BITS ACQ_TOKEN_ID_BITS +#define ACQ_ACK_NOFWORDS_IDX 13 +#define ACQ_ACK_NOFWORDS_BITS 9 +#define ACQ_ACK_PKT_LEN_IDX 4 +#define ACQ_ACK_PKT_LEN_BITS 16 + + +/* --------------------------------------------------*/ +/* Packet Data Type */ +/* --------------------------------------------------*/ + + +#define ACQ_YUV420_8_DATA 24 /* 01 1000 YUV420 8-bit */ +#define ACQ_YUV420_10_DATA 25 /* 01 1001 YUV420 10-bit */ +#define ACQ_YUV420_8L_DATA 26 /* 01 1010 YUV420 8-bit legacy */ +#define ACQ_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */ +#define ACQ_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */ +#define ACQ_RGB444_DATA 32 /* 10 0000 RGB444 */ +#define ACQ_RGB555_DATA 33 /* 10 0001 RGB555 */ +#define ACQ_RGB565_DATA 34 /* 10 0010 RGB565 */ +#define ACQ_RGB666_DATA 35 /* 10 0011 RGB666 */ +#define ACQ_RGB888_DATA 36 /* 10 0100 RGB888 */ +#define ACQ_RAW6_DATA 40 /* 10 1000 RAW6 */ +#define ACQ_RAW7_DATA 41 /* 10 1001 RAW7 */ +#define ACQ_RAW8_DATA 42 /* 10 1010 RAW8 */ +#define ACQ_RAW10_DATA 43 /* 10 1011 RAW10 */ +#define ACQ_RAW12_DATA 44 /* 10 1100 RAW12 */ +#define ACQ_RAW14_DATA 45 /* 10 1101 RAW14 */ +#define ACQ_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */ +#define ACQ_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */ +#define ACQ_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */ +#define ACQ_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */ +#define ACQ_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */ +#define ACQ_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */ +#define ACQ_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */ +#define ACQ_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */ +#define ACQ_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */ +#define ACQ_SOF_DATA 0 /* 00 0000 frame start */ +#define ACQ_EOF_DATA 1 /* 00 0001 frame end */ +#define ACQ_SOL_DATA 2 /* 00 0010 line start */ +#define ACQ_EOL_DATA 3 /* 00 0011 line end */ +#define ACQ_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */ +#define ACQ_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */ +#define ACQ_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */ +#define ACQ_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */ +#define ACQ_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */ +#define ACQ_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */ +#define ACQ_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */ +#define ACQ_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */ +#define ACQ_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */ +#define ACQ_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */ +#define ACQ_RESERVED_DATA_TYPE_MIN 56 +#define ACQ_RESERVED_DATA_TYPE_MAX 63 +#define ACQ_GEN_LONG_RESERVED_DATA_TYPE_MIN 19 +#define ACQ_GEN_LONG_RESERVED_DATA_TYPE_MAX 23 +#define ACQ_YUV_RESERVED_DATA_TYPE 27 +#define ACQ_RGB_RESERVED_DATA_TYPE_MIN 37 +#define ACQ_RGB_RESERVED_DATA_TYPE_MAX 39 +#define ACQ_RAW_RESERVED_DATA_TYPE_MIN 46 +#define ACQ_RAW_RESERVED_DATA_TYPE_MAX 47 + +/* --------------------------------------------------*/ + +#endif /* _isp_acquisition_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/isp_capture_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/isp_capture_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..aa413df022f2ed197fbec302d14b465b7deea48b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/isp_capture_defs.h @@ -0,0 +1,310 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _isp_capture_defs_h +#define _isp_capture_defs_h + +#define _ISP_CAPTURE_REG_ALIGN 4 /* assuming 32 bit control bus width */ +#define _ISP_CAPTURE_BITS_PER_ELEM 32 /* only for data, not SOP */ +#define _ISP_CAPTURE_BYTES_PER_ELEM (_ISP_CAPTURE_BITS_PER_ELEM/8 ) +#define _ISP_CAPTURE_BYTES_PER_WORD 32 /* 256/8 */ +#define _ISP_CAPTURE_ELEM_PER_WORD _ISP_CAPTURE_BYTES_PER_WORD / _ISP_CAPTURE_BYTES_PER_ELEM + +//#define CAPT_RCV_ACK 1 +//#define CAPT_WRT_ACK 2 +//#define CAPT_IRQ_ACK 3 + +/* --------------------------------------------------*/ + +#define NOF_IRQS 2 + +/* --------------------------------------------------*/ +/* REGISTER INFO */ +/* --------------------------------------------------*/ + +// Number of registers +#define CAPT_NOF_REGS 16 + +// Register id's of MMIO slave accesible registers +#define CAPT_START_MODE_REG_ID 0 +#define CAPT_START_ADDR_REG_ID 1 +#define CAPT_MEM_REGION_SIZE_REG_ID 2 +#define CAPT_NUM_MEM_REGIONS_REG_ID 3 +#define CAPT_INIT_REG_ID 4 +#define CAPT_START_REG_ID 5 +#define CAPT_STOP_REG_ID 6 + +#define CAPT_PACKET_LENGTH_REG_ID 7 +#define CAPT_RECEIVED_LENGTH_REG_ID 8 +#define CAPT_RECEIVED_SHORT_PACKETS_REG_ID 9 +#define CAPT_RECEIVED_LONG_PACKETS_REG_ID 10 +#define CAPT_LAST_COMMAND_REG_ID 11 +#define CAPT_NEXT_COMMAND_REG_ID 12 +#define CAPT_LAST_ACKNOWLEDGE_REG_ID 13 +#define CAPT_NEXT_ACKNOWLEDGE_REG_ID 14 +#define CAPT_FSM_STATE_INFO_REG_ID 15 + +// Register width +#define CAPT_START_MODE_REG_WIDTH 1 +//#define CAPT_START_ADDR_REG_WIDTH 9 +//#define CAPT_MEM_REGION_SIZE_REG_WIDTH 9 +//#define CAPT_NUM_MEM_REGIONS_REG_WIDTH 9 +#define CAPT_INIT_REG_WIDTH (22 + 4) + +#define CAPT_START_REG_WIDTH 1 +#define CAPT_STOP_REG_WIDTH 1 + +/* --------------------------------------------------*/ +/* FSM */ +/* --------------------------------------------------*/ +#define CAPT_WRITE2MEM_FSM_STATE_BITS 2 +#define CAPT_SYNCHRONIZER_FSM_STATE_BITS 3 + + +#define CAPT_PACKET_LENGTH_REG_WIDTH 17 +#define CAPT_RECEIVED_LENGTH_REG_WIDTH 17 +#define CAPT_RECEIVED_SHORT_PACKETS_REG_WIDTH 32 +#define CAPT_RECEIVED_LONG_PACKETS_REG_WIDTH 32 +#define CAPT_LAST_COMMAND_REG_WIDTH 32 +/* #define CAPT_NEXT_COMMAND_REG_WIDTH 32 */ +#define CAPT_LAST_ACKNOWLEDGE_REG_WIDTH 32 +#define CAPT_NEXT_ACKNOWLEDGE_REG_WIDTH 32 +#define CAPT_FSM_STATE_INFO_REG_WIDTH ((CAPT_WRITE2MEM_FSM_STATE_BITS * 3) + (CAPT_SYNCHRONIZER_FSM_STATE_BITS * 3)) + +//#define CAPT_INIT_RESTART_MEM_ADDR_WIDTH 9 +//#define CAPT_INIT_RESTART_MEM_REGION_WIDTH 9 + +/* register reset value */ +#define CAPT_START_MODE_REG_RSTVAL 0 +#define CAPT_START_ADDR_REG_RSTVAL 0 +#define CAPT_MEM_REGION_SIZE_REG_RSTVAL 128 +#define CAPT_NUM_MEM_REGIONS_REG_RSTVAL 3 +#define CAPT_INIT_REG_RSTVAL 0 + +#define CAPT_START_REG_RSTVAL 0 +#define CAPT_STOP_REG_RSTVAL 0 + +#define CAPT_PACKET_LENGTH_REG_RSTVAL 0 +#define CAPT_RECEIVED_LENGTH_REG_RSTVAL 0 +#define CAPT_RECEIVED_SHORT_PACKETS_REG_RSTVAL 0 +#define CAPT_RECEIVED_LONG_PACKETS_REG_RSTVAL 0 +#define CAPT_LAST_COMMAND_REG_RSTVAL 0 +#define CAPT_NEXT_COMMAND_REG_RSTVAL 0 +#define CAPT_LAST_ACKNOWLEDGE_REG_RSTVAL 0 +#define CAPT_NEXT_ACKNOWLEDGE_REG_RSTVAL 0 +#define CAPT_FSM_STATE_INFO_REG_RSTVAL 0 + +/* bit definitions */ +#define CAPT_INIT_RST_REG_BIT 0 +#define CAPT_INIT_FLUSH_BIT 1 +#define CAPT_INIT_RESYNC_BIT 2 +#define CAPT_INIT_RESTART_BIT 3 +#define CAPT_INIT_RESTART_MEM_ADDR_LSB 4 +#define CAPT_INIT_RESTART_MEM_ADDR_MSB 14 +#define CAPT_INIT_RESTART_MEM_REGION_LSB 15 +#define CAPT_INIT_RESTART_MEM_REGION_MSB 25 + + +#define CAPT_INIT_RST_REG_IDX CAPT_INIT_RST_REG_BIT +#define CAPT_INIT_RST_REG_BITS 1 +#define CAPT_INIT_FLUSH_IDX CAPT_INIT_FLUSH_BIT +#define CAPT_INIT_FLUSH_BITS 1 +#define CAPT_INIT_RESYNC_IDX CAPT_INIT_RESYNC_BIT +#define CAPT_INIT_RESYNC_BITS 1 +#define CAPT_INIT_RESTART_IDX CAPT_INIT_RESTART_BIT +#define CAPT_INIT_RESTART_BITS 1 +#define CAPT_INIT_RESTART_MEM_ADDR_IDX CAPT_INIT_RESTART_MEM_ADDR_LSB +#define CAPT_INIT_RESTART_MEM_ADDR_BITS (CAPT_INIT_RESTART_MEM_ADDR_MSB - CAPT_INIT_RESTART_MEM_ADDR_LSB + 1) +#define CAPT_INIT_RESTART_MEM_REGION_IDX CAPT_INIT_RESTART_MEM_REGION_LSB +#define CAPT_INIT_RESTART_MEM_REGION_BITS (CAPT_INIT_RESTART_MEM_REGION_MSB - CAPT_INIT_RESTART_MEM_REGION_LSB + 1) + + + +/* --------------------------------------------------*/ +/* TOKEN INFO */ +/* --------------------------------------------------*/ +#define CAPT_TOKEN_ID_LSB 0 +#define CAPT_TOKEN_ID_MSB 3 +#define CAPT_TOKEN_WIDTH (CAPT_TOKEN_ID_MSB - CAPT_TOKEN_ID_LSB + 1) /* 4 */ + +/* Command tokens IDs */ +#define CAPT_START_TOKEN_ID 0 /* 0000b */ +#define CAPT_STOP_TOKEN_ID 1 /* 0001b */ +#define CAPT_FREEZE_TOKEN_ID 2 /* 0010b */ +#define CAPT_RESUME_TOKEN_ID 3 /* 0011b */ +#define CAPT_INIT_TOKEN_ID 8 /* 1000b */ + +#define CAPT_START_TOKEN_BIT 0 +#define CAPT_STOP_TOKEN_BIT 0 +#define CAPT_FREEZE_TOKEN_BIT 0 +#define CAPT_RESUME_TOKEN_BIT 0 +#define CAPT_INIT_TOKEN_BIT 0 + +/* Acknowledge token IDs */ +#define CAPT_END_OF_PACKET_RECEIVED_TOKEN_ID 0 /* 0000b */ +#define CAPT_END_OF_PACKET_WRITTEN_TOKEN_ID 1 /* 0001b */ +#define CAPT_END_OF_REGION_WRITTEN_TOKEN_ID 2 /* 0010b */ +#define CAPT_FLUSH_DONE_TOKEN_ID 3 /* 0011b */ +#define CAPT_PREMATURE_SOP_TOKEN_ID 4 /* 0100b */ +#define CAPT_MISSING_SOP_TOKEN_ID 5 /* 0101b */ +#define CAPT_UNDEF_PH_TOKEN_ID 6 /* 0110b */ +#define CAPT_STOP_ACK_TOKEN_ID 7 /* 0111b */ + +#define CAPT_PACKET_LENGTH_TOKEN_MSB 19 +#define CAPT_PACKET_LENGTH_TOKEN_LSB 4 +#define CAPT_SUPER_PACKET_LENGTH_TOKEN_MSB 20 +#define CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB 4 +#define CAPT_PACKET_DATA_FORMAT_ID_TOKEN_MSB 25 +#define CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB 20 +#define CAPT_PACKET_CH_ID_TOKEN_MSB 27 +#define CAPT_PACKET_CH_ID_TOKEN_LSB 26 +#define CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB 29 +#define CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB 21 + +/* bit definition */ +#define CAPT_CMD_IDX CAPT_TOKEN_ID_LSB +#define CAPT_CMD_BITS (CAPT_TOKEN_ID_MSB - CAPT_TOKEN_ID_LSB + 1) +#define CAPT_SOP_IDX 32 +#define CAPT_SOP_BITS 1 +#define CAPT_PKT_INFO_IDX 16 +#define CAPT_PKT_INFO_BITS 8 +#define CAPT_PKT_TYPE_IDX 0 +#define CAPT_PKT_TYPE_BITS 6 +#define CAPT_HEADER_DATA_IDX 0 +#define CAPT_HEADER_DATA_BITS 16 +#define CAPT_PKT_DATA_IDX 0 +#define CAPT_PKT_DATA_BITS 32 +#define CAPT_WORD_CNT_IDX 0 +#define CAPT_WORD_CNT_BITS 16 +#define CAPT_ACK_TOKEN_ID_IDX 0 +#define CAPT_ACK_TOKEN_ID_BITS 4 +//#define CAPT_ACK_PKT_LEN_IDX CAPT_PACKET_LENGTH_TOKEN_LSB +//#define CAPT_ACK_PKT_LEN_BITS (CAPT_PACKET_LENGTH_TOKEN_MSB - CAPT_PACKET_LENGTH_TOKEN_LSB + 1) +//#define CAPT_ACK_PKT_INFO_IDX 20 +//#define CAPT_ACK_PKT_INFO_BITS 8 +//#define CAPT_ACK_MEM_REG_ID1_IDX 20 /* for capt_end_of_packet_written */ +//#define CAPT_ACK_MEM_REG_ID2_IDX 4 /* for capt_end_of_region_written */ +#define CAPT_ACK_PKT_LEN_IDX CAPT_PACKET_LENGTH_TOKEN_LSB +#define CAPT_ACK_PKT_LEN_BITS (CAPT_PACKET_LENGTH_TOKEN_MSB - CAPT_PACKET_LENGTH_TOKEN_LSB + 1) +#define CAPT_ACK_SUPER_PKT_LEN_IDX CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB +#define CAPT_ACK_SUPER_PKT_LEN_BITS (CAPT_SUPER_PACKET_LENGTH_TOKEN_MSB - CAPT_SUPER_PACKET_LENGTH_TOKEN_LSB + 1) +#define CAPT_ACK_PKT_INFO_IDX CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB +#define CAPT_ACK_PKT_INFO_BITS (CAPT_PACKET_CH_ID_TOKEN_MSB - CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB + 1) +#define CAPT_ACK_MEM_REGION_ID_IDX CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB +#define CAPT_ACK_MEM_REGION_ID_BITS (CAPT_PACKET_MEM_REGION_ID_TOKEN_MSB - CAPT_PACKET_MEM_REGION_ID_TOKEN_LSB + 1) +#define CAPT_ACK_PKT_TYPE_IDX CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB +#define CAPT_ACK_PKT_TYPE_BITS (CAPT_PACKET_DATA_FORMAT_ID_TOKEN_MSB - CAPT_PACKET_DATA_FORMAT_ID_TOKEN_LSB + 1) +#define CAPT_INIT_TOKEN_INIT_IDX 4 +#define CAPT_INIT_TOKEN_INIT_BITS 22 + + +/* --------------------------------------------------*/ +/* MIPI */ +/* --------------------------------------------------*/ + +#define CAPT_WORD_COUNT_WIDTH 16 +#define CAPT_PKT_CODE_WIDTH 6 +#define CAPT_CHN_NO_WIDTH 2 +#define CAPT_ERROR_INFO_WIDTH 8 + +#define LONG_PKTCODE_MAX 63 +#define LONG_PKTCODE_MIN 16 +#define SHORT_PKTCODE_MAX 15 + + +/* --------------------------------------------------*/ +/* Packet Info */ +/* --------------------------------------------------*/ +#define CAPT_START_OF_FRAME 0 +#define CAPT_END_OF_FRAME 1 +#define CAPT_START_OF_LINE 2 +#define CAPT_END_OF_LINE 3 +#define CAPT_LINE_PAYLOAD 4 +#define CAPT_GEN_SH_PKT 5 + + +/* --------------------------------------------------*/ +/* Packet Data Type */ +/* --------------------------------------------------*/ + +#define CAPT_YUV420_8_DATA 24 /* 01 1000 YUV420 8-bit */ +#define CAPT_YUV420_10_DATA 25 /* 01 1001 YUV420 10-bit */ +#define CAPT_YUV420_8L_DATA 26 /* 01 1010 YUV420 8-bit legacy */ +#define CAPT_YUV422_8_DATA 30 /* 01 1110 YUV422 8-bit */ +#define CAPT_YUV422_10_DATA 31 /* 01 1111 YUV422 10-bit */ +#define CAPT_RGB444_DATA 32 /* 10 0000 RGB444 */ +#define CAPT_RGB555_DATA 33 /* 10 0001 RGB555 */ +#define CAPT_RGB565_DATA 34 /* 10 0010 RGB565 */ +#define CAPT_RGB666_DATA 35 /* 10 0011 RGB666 */ +#define CAPT_RGB888_DATA 36 /* 10 0100 RGB888 */ +#define CAPT_RAW6_DATA 40 /* 10 1000 RAW6 */ +#define CAPT_RAW7_DATA 41 /* 10 1001 RAW7 */ +#define CAPT_RAW8_DATA 42 /* 10 1010 RAW8 */ +#define CAPT_RAW10_DATA 43 /* 10 1011 RAW10 */ +#define CAPT_RAW12_DATA 44 /* 10 1100 RAW12 */ +#define CAPT_RAW14_DATA 45 /* 10 1101 RAW14 */ +#define CAPT_USR_DEF_1_DATA 48 /* 11 0000 JPEG [User Defined 8-bit Data Type 1] */ +#define CAPT_USR_DEF_2_DATA 49 /* 11 0001 User Defined 8-bit Data Type 2 */ +#define CAPT_USR_DEF_3_DATA 50 /* 11 0010 User Defined 8-bit Data Type 3 */ +#define CAPT_USR_DEF_4_DATA 51 /* 11 0011 User Defined 8-bit Data Type 4 */ +#define CAPT_USR_DEF_5_DATA 52 /* 11 0100 User Defined 8-bit Data Type 5 */ +#define CAPT_USR_DEF_6_DATA 53 /* 11 0101 User Defined 8-bit Data Type 6 */ +#define CAPT_USR_DEF_7_DATA 54 /* 11 0110 User Defined 8-bit Data Type 7 */ +#define CAPT_USR_DEF_8_DATA 55 /* 11 0111 User Defined 8-bit Data Type 8 */ +#define CAPT_Emb_DATA 18 /* 01 0010 embedded eight bit non image data */ +#define CAPT_SOF_DATA 0 /* 00 0000 frame start */ +#define CAPT_EOF_DATA 1 /* 00 0001 frame end */ +#define CAPT_SOL_DATA 2 /* 00 0010 line start */ +#define CAPT_EOL_DATA 3 /* 00 0011 line end */ +#define CAPT_GEN_SH1_DATA 8 /* 00 1000 Generic Short Packet Code 1 */ +#define CAPT_GEN_SH2_DATA 9 /* 00 1001 Generic Short Packet Code 2 */ +#define CAPT_GEN_SH3_DATA 10 /* 00 1010 Generic Short Packet Code 3 */ +#define CAPT_GEN_SH4_DATA 11 /* 00 1011 Generic Short Packet Code 4 */ +#define CAPT_GEN_SH5_DATA 12 /* 00 1100 Generic Short Packet Code 5 */ +#define CAPT_GEN_SH6_DATA 13 /* 00 1101 Generic Short Packet Code 6 */ +#define CAPT_GEN_SH7_DATA 14 /* 00 1110 Generic Short Packet Code 7 */ +#define CAPT_GEN_SH8_DATA 15 /* 00 1111 Generic Short Packet Code 8 */ +#define CAPT_YUV420_8_CSPS_DATA 28 /* 01 1100 YUV420 8-bit (Chroma Shifted Pixel Sampling) */ +#define CAPT_YUV420_10_CSPS_DATA 29 /* 01 1101 YUV420 10-bit (Chroma Shifted Pixel Sampling) */ +#define CAPT_RESERVED_DATA_TYPE_MIN 56 +#define CAPT_RESERVED_DATA_TYPE_MAX 63 +#define CAPT_GEN_LONG_RESERVED_DATA_TYPE_MIN 19 +#define CAPT_GEN_LONG_RESERVED_DATA_TYPE_MAX 23 +#define CAPT_YUV_RESERVED_DATA_TYPE 27 +#define CAPT_RGB_RESERVED_DATA_TYPE_MIN 37 +#define CAPT_RGB_RESERVED_DATA_TYPE_MAX 39 +#define CAPT_RAW_RESERVED_DATA_TYPE_MIN 46 +#define CAPT_RAW_RESERVED_DATA_TYPE_MAX 47 + + +/* --------------------------------------------------*/ +/* Capture Unit State */ +/* --------------------------------------------------*/ +#define CAPT_FREE_RUN 0 +#define CAPT_NO_SYNC 1 +#define CAPT_SYNC_SWP 2 +#define CAPT_SYNC_MWP 3 +#define CAPT_SYNC_WAIT 4 +#define CAPT_FREEZE 5 +#define CAPT_RUN 6 + + +/* --------------------------------------------------*/ + +#endif /* _isp_capture_defs_h */ + + + + + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/mmu_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/mmu_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..c038f39ffd25e3f3d1b9afdbba93495642da5e6b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/mmu_defs.h @@ -0,0 +1,23 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _mmu_defs_h +#define _mmu_defs_h + +#define _HRT_MMU_INVALIDATE_TLB_REG_IDX 0 +#define _HRT_MMU_PAGE_TABLE_BASE_ADDRESS_REG_IDX 1 + +#define _HRT_MMU_REG_ALIGN 4 + +#endif /* _mmu_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/scalar_processor_2400_params.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/scalar_processor_2400_params.h new file mode 100644 index 0000000000000000000000000000000000000000..9b6c2893d950708458b4c82d4f5951923b57512e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/scalar_processor_2400_params.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _scalar_processor_2400_params_h +#define _scalar_processor_2400_params_h + +#include "cell_params.h" + +#endif /* _scalar_processor_2400_params_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/sp_hrt.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/sp_hrt.h new file mode 100644 index 0000000000000000000000000000000000000000..7ee4deba519ac9988da4ab01774a0899be97e7d5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/sp_hrt.h @@ -0,0 +1,24 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _sp_hrt_h_ +#define _sp_hrt_h_ + +#define hrt_sp_dmem(cell) HRT_PROC_TYPE_PROP(cell, _dmem) + +#define hrt_sp_dmem_master_port_address(cell) hrt_mem_master_port_address(cell, hrt_sp_dmem(cell)) + +#endif /* _sp_hrt_h_ */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/str2mem_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/str2mem_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..1cb62444cf68bc590aceb0f6d3958feec81d95e2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/str2mem_defs.h @@ -0,0 +1,39 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _ST2MEM_DEFS_H +#define _ST2MEM_DEFS_H + +#define _STR2MEM_CRUN_BIT 0x100000 +#define _STR2MEM_CMD_BITS 0x0F0000 +#define _STR2MEM_COUNT_BITS 0x00FFFF + +#define _STR2MEM_BLOCKS_CMD 0xA0000 +#define _STR2MEM_PACKETS_CMD 0xB0000 +#define _STR2MEM_BYTES_CMD 0xC0000 +#define _STR2MEM_BYTES_FROM_PACKET_CMD 0xD0000 + +#define _STR2MEM_SOFT_RESET_REG_ID 0 +#define _STR2MEM_INPUT_ENDIANNESS_REG_ID 1 +#define _STR2MEM_OUTPUT_ENDIANNESS_REG_ID 2 +#define _STR2MEM_BIT_SWAPPING_REG_ID 3 +#define _STR2MEM_BLOCK_SYNC_LEVEL_REG_ID 4 +#define _STR2MEM_PACKET_SYNC_LEVEL_REG_ID 5 +#define _STR2MEM_READ_POST_WRITE_SYNC_ENABLE_REG_ID 6 +#define _STR2MEM_DUAL_BYTE_INPUTS_ENABLED_REG_ID 7 +#define _STR2MEM_EN_STAT_UPDATE_ID 8 + +#define _STR2MEM_REG_ALIGN 4 + +#endif /* _ST2MEM_DEFS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/streaming_to_mipi_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/streaming_to_mipi_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..60143b8743a2d5a4079f557387033e83acf99870 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/streaming_to_mipi_defs.h @@ -0,0 +1,28 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _streaming_to_mipi_defs_h +#define _streaming_to_mipi_defs_h + +#define HIVE_STR_TO_MIPI_VALID_A_BIT 0 +#define HIVE_STR_TO_MIPI_VALID_B_BIT 1 +#define HIVE_STR_TO_MIPI_SOL_BIT 2 +#define HIVE_STR_TO_MIPI_EOL_BIT 3 +#define HIVE_STR_TO_MIPI_SOF_BIT 4 +#define HIVE_STR_TO_MIPI_EOF_BIT 5 +#define HIVE_STR_TO_MIPI_CH_ID_LSB 6 + +#define HIVE_STR_TO_MIPI_DATA_A_LSB (HIVE_STR_TO_MIPI_VALID_B_BIT + 1) + +#endif /* _streaming_to_mipi_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/timed_controller_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/timed_controller_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..d2b8972b0d9ec64ae887e8c6f96d586262737b0f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/timed_controller_defs.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _timed_controller_defs_h +#define _timed_controller_defs_h + +#define _HRT_TIMED_CONTROLLER_CMD_REG_IDX 0 + +#define _HRT_TIMED_CONTROLLER_REG_ALIGN 4 + +#endif /* _timed_controller_defs_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/var.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/var.h new file mode 100644 index 0000000000000000000000000000000000000000..19b19ef484f953867e311a95df2e48c418ffa156 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/var.h @@ -0,0 +1,99 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _HRT_VAR_H +#define _HRT_VAR_H + +#include "version.h" +#include "system_api.h" +#include "hive_types.h" + +#define hrt_int_type_of_char char +#define hrt_int_type_of_uchar unsigned char +#define hrt_int_type_of_short short +#define hrt_int_type_of_ushort unsigned short +#define hrt_int_type_of_int int +#define hrt_int_type_of_uint unsigned int +#define hrt_int_type_of_long long +#define hrt_int_type_of_ulong unsigned long +#define hrt_int_type_of_ptr unsigned int + +#define hrt_host_type_of_char char +#define hrt_host_type_of_uchar unsigned char +#define hrt_host_type_of_short short +#define hrt_host_type_of_ushort unsigned short +#define hrt_host_type_of_int int +#define hrt_host_type_of_uint unsigned int +#define hrt_host_type_of_long long +#define hrt_host_type_of_ulong unsigned long +#define hrt_host_type_of_ptr void* + +#define HRT_TYPE_BYTES(cell, type) (HRT_TYPE_BITS(cell, type)/8) +#define HRT_HOST_TYPE(cell_type) HRTCAT(hrt_host_type_of_, cell_type) +#define HRT_INT_TYPE(type) HRTCAT(hrt_int_type_of_, type) + +#ifdef C_RUN + +#ifdef C_RUN_DYNAMIC_LINK_PROGRAMS +extern void *csim_processor_get_crun_symbol(hive_proc_id p, const char *sym); +#define _hrt_cell_get_crun_symbol(cell,sym) csim_processor_get_crun_symbol(cell,HRTSTR(sym)) +#define _hrt_cell_get_crun_indexed_symbol(cell,sym) csim_processor_get_crun_symbol(cell,HRTSTR(sym)) +#else +#define _hrt_cell_get_crun_symbol(cell,sym) (&sym) +#define _hrt_cell_get_crun_indexed_symbol(cell,sym) (sym) +#endif // C_RUN_DYNAMIC_LINK_PROGRAMS + +#define hrt_scalar_store(cell, type, var, data) \ + ((*(HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_symbol(cell,var)) = (data)) +#define hrt_scalar_load(cell, type, var) \ + ((*(HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_symbol(cell,var))) + +#define hrt_indexed_store(cell, type, array, index, data) \ + ((((HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_indexed_symbol(cell,array))[index]) = (data)) +#define hrt_indexed_load(cell, type, array, index) \ + (((HRT_HOST_TYPE(type)*)_hrt_cell_get_crun_indexed_symbol(cell,array))[index]) + +#else /* C_RUN */ + +#define hrt_scalar_store(cell, type, var, data) \ + HRTCAT(hrt_mem_store_,HRT_TYPE_BITS(cell, type))(\ + cell, \ + HRTCAT(HIVE_MEM_,var), \ + HRTCAT(HIVE_ADDR_,var), \ + (HRT_INT_TYPE(type))(data)) + +#define hrt_scalar_load(cell, type, var) \ + (HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_,HRT_PROC_TYPE(cell),_,type) ( \ + cell, \ + HRTCAT(HIVE_MEM_,var), \ + HRTCAT(HIVE_ADDR_,var))) + +#define hrt_indexed_store(cell, type, array, index, data) \ + HRTCAT(hrt_mem_store_,HRT_TYPE_BITS(cell, type))(\ + cell, \ + HRTCAT(HIVE_MEM_,array), \ + (HRTCAT(HIVE_ADDR_,array))+((index)*HRT_TYPE_BYTES(cell, type)), \ + (HRT_INT_TYPE(type))(data)) + +#define hrt_indexed_load(cell, type, array, index) \ + (HRT_HOST_TYPE(type))(HRTCAT4(_hrt_mem_load_,HRT_PROC_TYPE(cell),_,type) ( \ + cell, \ + HRTCAT(HIVE_MEM_,array), \ + (HRTCAT(HIVE_ADDR_,array))+((index)*HRT_TYPE_BYTES(cell, type)))) + +#endif /* C_RUN */ + +#endif /* _HRT_VAR_H */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/version.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/version.h new file mode 100644 index 0000000000000000000000000000000000000000..bbc4948baea9b913b590d8992a2d50358503c5f4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/hrt/version.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef HRT_VERSION_H +#define HRT_VERSION_H +#define HRT_VERSION_MAJOR 1 +#define HRT_VERSION_MINOR 4 +#define HRT_VERSION 1_4 +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/spmem_dump.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/spmem_dump.c new file mode 100644 index 0000000000000000000000000000000000000000..09f0780f0c8002e5b630ece5204fbb9dce2794a3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_2401_system/spmem_dump.c @@ -0,0 +1,3634 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _sp_map_h_ +#define _sp_map_h_ + + +#ifndef _hrt_dummy_use_blob_sp +#define _hrt_dummy_use_blob_sp() +#endif + +#define _hrt_cell_load_program_sp(proc) _hrt_cell_load_program_embedded(proc, sp) + +#ifndef ISP2401 +/* function input_system_acquisition_stop: ADE */ +#else +/* function input_system_acquisition_stop: AD8 */ +#endif + +#ifndef ISP2401 +/* function longjmp: 684E */ +#else +/* function longjmp: 69C1 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_HIVE_IF_SRST_MASK +#define HIVE_MEM_HIVE_IF_SRST_MASK scalar_processor_2400_dmem +#define HIVE_ADDR_HIVE_IF_SRST_MASK 0x1C8 +#define HIVE_SIZE_HIVE_IF_SRST_MASK 16 +#else +#endif +#endif +#define HIVE_MEM_sp_HIVE_IF_SRST_MASK scalar_processor_2400_dmem +#define HIVE_ADDR_sp_HIVE_IF_SRST_MASK 0x1C8 +#define HIVE_SIZE_sp_HIVE_IF_SRST_MASK 16 + +#ifndef ISP2401 +/* function tmpmem_init_dmem: 6599 */ +#else +/* function tmpmem_init_dmem: 66D4 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_token_map_receive_ack: 5EDD */ +#else +/* function ia_css_isys_sp_token_map_receive_ack: 6018 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_set_addr_B: 3345 */ +#else +/* function ia_css_dmaproxy_sp_set_addr_B: 3539 */ + +/* function ia_css_pipe_data_init_tagger_resources: A4F */ +#endif + +/* function debug_buffer_set_ddr_addr: DD */ + +#ifndef ISP2401 +/* function receiver_port_reg_load: AC2 */ +#else +/* function receiver_port_reg_load: ABC */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_vbuf_mipi +#define HIVE_MEM_vbuf_mipi scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_vbuf_mipi 0x631C +#else +#define HIVE_ADDR_vbuf_mipi 0x6378 +#endif +#define HIVE_SIZE_vbuf_mipi 12 +#else +#endif +#endif +#define HIVE_MEM_sp_vbuf_mipi scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_vbuf_mipi 0x631C +#else +#define HIVE_ADDR_sp_vbuf_mipi 0x6378 +#endif +#define HIVE_SIZE_sp_vbuf_mipi 12 + +#ifndef ISP2401 +/* function ia_css_event_sp_decode: 3536 */ +#else +/* function ia_css_event_sp_decode: 372A */ +#endif + +#ifndef ISP2401 +/* function ia_css_queue_get_size: 48BE */ +#else +/* function ia_css_queue_get_size: 4B46 */ +#endif + +#ifndef ISP2401 +/* function ia_css_queue_load: 4EFF */ +#else +/* function ia_css_queue_load: 515D */ +#endif + +#ifndef ISP2401 +/* function setjmp: 6857 */ +#else +/* function setjmp: 69CA */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_sp2host_isys_event_queue +#define HIVE_MEM_sem_for_sp2host_isys_event_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_sp2host_isys_event_queue 0x4684 +#else +#define HIVE_ADDR_sem_for_sp2host_isys_event_queue 0x46CC +#endif +#define HIVE_SIZE_sem_for_sp2host_isys_event_queue 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_sp2host_isys_event_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_sp2host_isys_event_queue 0x4684 +#else +#define HIVE_ADDR_sp_sem_for_sp2host_isys_event_queue 0x46CC +#endif +#define HIVE_SIZE_sp_sem_for_sp2host_isys_event_queue 20 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_wait_for_ack: 6E07 */ +#else +/* function ia_css_dmaproxy_sp_wait_for_ack: 6F4B */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_rawcopy_func: 5124 */ +#else +/* function ia_css_sp_rawcopy_func: 5382 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_pop_marked: 2A10 */ +#else +/* function ia_css_tagger_buf_sp_pop_marked: 2BB2 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isp_stage +#define HIVE_MEM_isp_stage scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isp_stage 0x5C00 +#else +#define HIVE_ADDR_isp_stage 0x5C60 +#endif +#define HIVE_SIZE_isp_stage 832 +#else +#endif +#endif +#define HIVE_MEM_sp_isp_stage scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_stage 0x5C00 +#else +#define HIVE_ADDR_sp_isp_stage 0x5C60 +#endif +#define HIVE_SIZE_sp_isp_stage 832 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_vbuf_raw +#define HIVE_MEM_vbuf_raw scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_vbuf_raw 0x2F4 +#else +#define HIVE_ADDR_vbuf_raw 0x30C +#endif +#define HIVE_SIZE_vbuf_raw 4 +#else +#endif +#endif +#define HIVE_MEM_sp_vbuf_raw scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_vbuf_raw 0x2F4 +#else +#define HIVE_ADDR_sp_vbuf_raw 0x30C +#endif +#define HIVE_SIZE_sp_vbuf_raw 4 + +#ifndef ISP2401 +/* function ia_css_sp_bin_copy_func: 504B */ +#else +/* function ia_css_sp_bin_copy_func: 52A9 */ +#endif + +#ifndef ISP2401 +/* function ia_css_queue_item_store: 4C4D */ +#else +/* function ia_css_queue_item_store: 4EAB */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_metadata_bufs +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_metadata_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_metadata_bufs 0x4AA0 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_metadata_bufs 0x4AFC +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_metadata_bufs 20 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_metadata_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_metadata_bufs 0x4AA0 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_metadata_bufs 0x4AFC +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_metadata_bufs 20 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_buffer_bufs +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_buffer_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_buffer_bufs 0x4AB4 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_buffer_bufs 0x4B10 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_buffer_bufs 160 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_buffer_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_buffer_bufs 0x4AB4 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_buffer_bufs 0x4B10 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_buffer_bufs 160 + +/* function sp_start_isp: 45D */ + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_binary_group +#define HIVE_MEM_sp_binary_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_binary_group 0x5FF0 +#else +#define HIVE_ADDR_sp_binary_group 0x6050 +#endif +#define HIVE_SIZE_sp_binary_group 32 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_binary_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_binary_group 0x5FF0 +#else +#define HIVE_ADDR_sp_sp_binary_group 0x6050 +#endif +#define HIVE_SIZE_sp_sp_binary_group 32 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_sw_state +#define HIVE_MEM_sp_sw_state scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sw_state 0x62AC +#else +#define HIVE_ADDR_sp_sw_state 0x6308 +#endif +#define HIVE_SIZE_sp_sw_state 4 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_sw_state scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_sw_state 0x62AC +#else +#define HIVE_ADDR_sp_sp_sw_state 0x6308 +#endif +#define HIVE_SIZE_sp_sp_sw_state 4 + +#ifndef ISP2401 +/* function ia_css_thread_sp_main: D5B */ +#else +/* function ia_css_thread_sp_main: D50 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_init_internal_buffers: 373C */ +#else +/* function ia_css_ispctrl_sp_init_internal_buffers: 396B */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp2host_psys_event_queue_handle +#define HIVE_MEM_sp2host_psys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp2host_psys_event_queue_handle 0x4B54 +#else +#define HIVE_ADDR_sp2host_psys_event_queue_handle 0x4BB0 +#endif +#define HIVE_SIZE_sp2host_psys_event_queue_handle 12 +#else +#endif +#endif +#define HIVE_MEM_sp_sp2host_psys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp2host_psys_event_queue_handle 0x4B54 +#else +#define HIVE_ADDR_sp_sp2host_psys_event_queue_handle 0x4BB0 +#endif +#define HIVE_SIZE_sp_sp2host_psys_event_queue_handle 12 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_sp2host_psys_event_queue +#define HIVE_MEM_sem_for_sp2host_psys_event_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_sp2host_psys_event_queue 0x4698 +#else +#define HIVE_ADDR_sem_for_sp2host_psys_event_queue 0x46E0 +#endif +#define HIVE_SIZE_sem_for_sp2host_psys_event_queue 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_sp2host_psys_event_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_sp2host_psys_event_queue 0x4698 +#else +#define HIVE_ADDR_sp_sem_for_sp2host_psys_event_queue 0x46E0 +#endif +#define HIVE_SIZE_sp_sem_for_sp2host_psys_event_queue 20 + +#ifndef ISP2401 +/* function ia_css_tagger_sp_propagate_frame: 2429 */ + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_stop_copy_preview +#define HIVE_MEM_sp_stop_copy_preview scalar_processor_2400_dmem +#define HIVE_ADDR_sp_stop_copy_preview 0x6290 +#define HIVE_SIZE_sp_stop_copy_preview 4 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_stop_copy_preview scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_stop_copy_preview 0x6290 +#define HIVE_SIZE_sp_sp_stop_copy_preview 4 +#else +/* function ia_css_tagger_sp_propagate_frame: 2479 */ +#endif + +#ifndef ISP2401 +/* function input_system_reg_load: B17 */ +#else +/* function input_system_reg_load: B11 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_vbuf_handles +#define HIVE_MEM_vbuf_handles scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_vbuf_handles 0x6328 +#else +#define HIVE_ADDR_vbuf_handles 0x6384 +#endif +#define HIVE_SIZE_vbuf_handles 960 +#else +#endif +#endif +#define HIVE_MEM_sp_vbuf_handles scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_vbuf_handles 0x6328 +#else +#define HIVE_ADDR_sp_vbuf_handles 0x6384 +#endif +#define HIVE_SIZE_sp_vbuf_handles 960 + +#ifndef ISP2401 +/* function ia_css_queue_store: 4DB3 */ + +/* function ia_css_sp_flash_register: 2C45 */ +#else +/* function ia_css_queue_store: 5011 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_rawcopy_dummy_function: 566B */ +#else +/* function ia_css_sp_flash_register: 2DE7 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_backend_create: 5B50 */ +#else +/* function ia_css_isys_sp_backend_create: 5C8B */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_init: 184C */ +#else +/* function ia_css_pipeline_sp_init: 1886 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_configure: 2319 */ +#else +/* function ia_css_tagger_sp_configure: 2369 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_end_binary: 357F */ +#else +/* function ia_css_ispctrl_sp_end_binary: 3773 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs +#define HIVE_MEM_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x4B60 +#else +#define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x4BBC +#endif +#define HIVE_SIZE_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 20 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x4B60 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 0x4BBC +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_h_pipe_private_per_frame_ddr_ptrs 20 + +#ifndef ISP2401 +/* function receiver_port_reg_store: AC9 */ +#else +/* function receiver_port_reg_store: AC3 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_event_is_pending_mask +#define HIVE_MEM_event_is_pending_mask scalar_processor_2400_dmem +#define HIVE_ADDR_event_is_pending_mask 0x5C +#define HIVE_SIZE_event_is_pending_mask 44 +#else +#endif +#endif +#define HIVE_MEM_sp_event_is_pending_mask scalar_processor_2400_dmem +#define HIVE_ADDR_sp_event_is_pending_mask 0x5C +#define HIVE_SIZE_sp_event_is_pending_mask 44 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cb_elems_frame +#define HIVE_MEM_sp_all_cb_elems_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cb_elems_frame 0x46AC +#else +#define HIVE_ADDR_sp_all_cb_elems_frame 0x46F4 +#endif +#define HIVE_SIZE_sp_all_cb_elems_frame 16 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cb_elems_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cb_elems_frame 0x46AC +#else +#define HIVE_ADDR_sp_sp_all_cb_elems_frame 0x46F4 +#endif +#define HIVE_SIZE_sp_sp_all_cb_elems_frame 16 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp2host_isys_event_queue_handle +#define HIVE_MEM_sp2host_isys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp2host_isys_event_queue_handle 0x4B74 +#else +#define HIVE_ADDR_sp2host_isys_event_queue_handle 0x4BD0 +#endif +#define HIVE_SIZE_sp2host_isys_event_queue_handle 12 +#else +#endif +#endif +#define HIVE_MEM_sp_sp2host_isys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp2host_isys_event_queue_handle 0x4B74 +#else +#define HIVE_ADDR_sp_sp2host_isys_event_queue_handle 0x4BD0 +#endif +#define HIVE_SIZE_sp_sp2host_isys_event_queue_handle 12 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host_sp_com +#define HIVE_MEM_host_sp_com scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host_sp_com 0x4114 +#else +#define HIVE_ADDR_host_sp_com 0x4134 +#endif +#define HIVE_SIZE_host_sp_com 220 +#else +#endif +#endif +#define HIVE_MEM_sp_host_sp_com scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host_sp_com 0x4114 +#else +#define HIVE_ADDR_sp_host_sp_com 0x4134 +#endif +#define HIVE_SIZE_sp_host_sp_com 220 + +#ifndef ISP2401 +/* function ia_css_queue_get_free_space: 4A12 */ +#else +/* function ia_css_queue_get_free_space: 4C70 */ +#endif + +#ifndef ISP2401 +/* function exec_image_pipe: 6C4 */ +#else +/* function exec_image_pipe: 658 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_init_dmem_data +#define HIVE_MEM_sp_init_dmem_data scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_init_dmem_data 0x62B0 +#else +#define HIVE_ADDR_sp_init_dmem_data 0x630C +#endif +#define HIVE_SIZE_sp_init_dmem_data 24 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_init_dmem_data scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_init_dmem_data 0x62B0 +#else +#define HIVE_ADDR_sp_sp_init_dmem_data 0x630C +#endif +#define HIVE_SIZE_sp_sp_init_dmem_data 24 + +#ifndef ISP2401 +/* function ia_css_sp_metadata_start: 592D */ +#else +/* function ia_css_sp_metadata_start: 5A68 */ +#endif + +#ifndef ISP2401 +/* function ia_css_bufq_sp_init_buffer_queues: 2CB4 */ +#else +/* function ia_css_bufq_sp_init_buffer_queues: 2E56 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_stop: 182F */ +#else +/* function ia_css_pipeline_sp_stop: 1869 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_connect_pipes: 2803 */ +#else +/* function ia_css_tagger_sp_connect_pipes: 2853 */ +#endif + +#ifndef ISP2401 +/* function sp_isys_copy_wait: 70D */ +#else +/* function sp_isys_copy_wait: 6A1 */ +#endif + +/* function is_isp_debug_buffer_full: 337 */ + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_configure_channel_from_info: 32C8 */ +#else +/* function ia_css_dmaproxy_sp_configure_channel_from_info: 34A9 */ +#endif + +#ifndef ISP2401 +/* function encode_and_post_timer_event: A30 */ +#else +/* function encode_and_post_timer_event: 9C4 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_per_frame_data +#define HIVE_MEM_sp_per_frame_data scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_per_frame_data 0x41F0 +#else +#define HIVE_ADDR_sp_per_frame_data 0x4210 +#endif +#define HIVE_SIZE_sp_per_frame_data 4 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_per_frame_data scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_per_frame_data 0x41F0 +#else +#define HIVE_ADDR_sp_sp_per_frame_data 0x4210 +#endif +#define HIVE_SIZE_sp_sp_per_frame_data 4 + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_vbuf_dequeue: 62ED */ +#else +/* function ia_css_rmgr_sp_vbuf_dequeue: 6428 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host2sp_psys_event_queue_handle +#define HIVE_MEM_host2sp_psys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host2sp_psys_event_queue_handle 0x4B80 +#else +#define HIVE_ADDR_host2sp_psys_event_queue_handle 0x4BDC +#endif +#define HIVE_SIZE_host2sp_psys_event_queue_handle 12 +#else +#endif +#endif +#define HIVE_MEM_sp_host2sp_psys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host2sp_psys_event_queue_handle 0x4B80 +#else +#define HIVE_ADDR_sp_host2sp_psys_event_queue_handle 0x4BDC +#endif +#define HIVE_SIZE_sp_host2sp_psys_event_queue_handle 12 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_xmem_bin_addr +#define HIVE_MEM_xmem_bin_addr scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_xmem_bin_addr 0x41F4 +#else +#define HIVE_ADDR_xmem_bin_addr 0x4214 +#endif +#define HIVE_SIZE_xmem_bin_addr 4 +#else +#endif +#endif +#define HIVE_MEM_sp_xmem_bin_addr scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_xmem_bin_addr 0x41F4 +#else +#define HIVE_ADDR_sp_xmem_bin_addr 0x4214 +#endif +#define HIVE_SIZE_sp_xmem_bin_addr 4 + +#ifndef ISP2401 +/* function tmr_clock_init: 13FB */ +#else +/* function tmr_clock_init: 141C */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_run: 141C */ +#else +/* function ia_css_pipeline_sp_run: 143D */ +#endif + +#ifndef ISP2401 +/* function memcpy: 68F7 */ +#else +/* function memcpy: 6A6A */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_GP_DEVICE_BASE +#define HIVE_MEM_GP_DEVICE_BASE scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_GP_DEVICE_BASE 0x2FC +#else +#define HIVE_ADDR_GP_DEVICE_BASE 0x314 +#endif +#define HIVE_SIZE_GP_DEVICE_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_GP_DEVICE_BASE scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_GP_DEVICE_BASE 0x2FC +#else +#define HIVE_ADDR_sp_GP_DEVICE_BASE 0x314 +#endif +#define HIVE_SIZE_sp_GP_DEVICE_BASE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_thread_sp_ready_queue +#define HIVE_MEM_ia_css_thread_sp_ready_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_thread_sp_ready_queue 0x1E0 +#else +#define HIVE_ADDR_ia_css_thread_sp_ready_queue 0x1E4 +#endif +#define HIVE_SIZE_ia_css_thread_sp_ready_queue 12 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_thread_sp_ready_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_thread_sp_ready_queue 0x1E0 +#else +#define HIVE_ADDR_sp_ia_css_thread_sp_ready_queue 0x1E4 +#endif +#define HIVE_SIZE_sp_ia_css_thread_sp_ready_queue 12 + +#ifndef ISP2401 +/* function input_system_reg_store: B1E */ +#else +/* function input_system_reg_store: B18 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_frontend_start: 5D66 */ +#else +/* function ia_css_isys_sp_frontend_start: 5EA1 */ +#endif + +#ifndef ISP2401 +/* function ia_css_uds_sp_scale_params: 6600 */ +#else +/* function ia_css_uds_sp_scale_params: 6773 */ +#endif + +#ifndef ISP2401 +/* function ia_css_circbuf_increase_size: E40 */ +#else +/* function ia_css_circbuf_increase_size: E35 */ +#endif + +#ifndef ISP2401 +/* function __divu: 6875 */ +#else +/* function __divu: 69E8 */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_get_state: C83 */ +#else +/* function ia_css_thread_sp_get_state: C78 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_cont_capt_stop +#define HIVE_MEM_sem_for_cont_capt_stop scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_cont_capt_stop 0x46BC +#else +#define HIVE_ADDR_sem_for_cont_capt_stop 0x4704 +#endif +#define HIVE_SIZE_sem_for_cont_capt_stop 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_cont_capt_stop scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_cont_capt_stop 0x46BC +#else +#define HIVE_ADDR_sp_sem_for_cont_capt_stop 0x4704 +#endif +#define HIVE_SIZE_sp_sem_for_cont_capt_stop 20 + +#ifndef ISP2401 +/* function thread_fiber_sp_main: E39 */ +#else +/* function thread_fiber_sp_main: E2E */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_isp_pipe_thread +#define HIVE_MEM_sp_isp_pipe_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_pipe_thread 0x4800 +#define HIVE_SIZE_sp_isp_pipe_thread 340 +#else +#define HIVE_ADDR_sp_isp_pipe_thread 0x4848 +#define HIVE_SIZE_sp_isp_pipe_thread 360 +#endif +#else +#endif +#endif +#define HIVE_MEM_sp_sp_isp_pipe_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_isp_pipe_thread 0x4800 +#define HIVE_SIZE_sp_sp_isp_pipe_thread 340 +#else +#define HIVE_ADDR_sp_sp_isp_pipe_thread 0x4848 +#define HIVE_SIZE_sp_sp_isp_pipe_thread 360 +#endif + +#ifndef ISP2401 +/* function ia_css_parambuf_sp_handle_parameter_sets: 128A */ +#else +/* function ia_css_parambuf_sp_handle_parameter_sets: 127F */ +#endif + +#ifndef ISP2401 +/* function ia_css_spctrl_sp_set_state: 595C */ +#else +/* function ia_css_spctrl_sp_set_state: 5A97 */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sem_sp_signal: 6AF7 */ +#else +/* function ia_css_thread_sem_sp_signal: 6C6C */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_IRQ_BASE +#define HIVE_MEM_IRQ_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_IRQ_BASE 0x2C +#define HIVE_SIZE_IRQ_BASE 16 +#else +#endif +#endif +#define HIVE_MEM_sp_IRQ_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_IRQ_BASE 0x2C +#define HIVE_SIZE_sp_IRQ_BASE 16 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_TIMED_CTRL_BASE +#define HIVE_MEM_TIMED_CTRL_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_TIMED_CTRL_BASE 0x40 +#define HIVE_SIZE_TIMED_CTRL_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_TIMED_CTRL_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_TIMED_CTRL_BASE 0x40 +#define HIVE_SIZE_sp_TIMED_CTRL_BASE 4 + +#ifndef ISP2401 +/* function ia_css_isys_sp_isr: 6FDC */ + +/* function ia_css_isys_sp_generate_exp_id: 60FE */ +#else +/* function ia_css_isys_sp_isr: 7139 */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_init: 61E8 */ +#else +/* function ia_css_isys_sp_generate_exp_id: 6239 */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sem_sp_init: 6BC8 */ +#else +/* function ia_css_rmgr_sp_init: 6323 */ +#endif + +#ifndef ISP2401 +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_is_isp_requested +#define HIVE_MEM_is_isp_requested scalar_processor_2400_dmem +#define HIVE_ADDR_is_isp_requested 0x308 +#define HIVE_SIZE_is_isp_requested 4 +#else +#endif +#endif +#define HIVE_MEM_sp_is_isp_requested scalar_processor_2400_dmem +#define HIVE_ADDR_sp_is_isp_requested 0x308 +#define HIVE_SIZE_sp_is_isp_requested 4 +#else +/* function ia_css_thread_sem_sp_init: 6D3B */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_reading_cb_frame +#define HIVE_MEM_sem_for_reading_cb_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_reading_cb_frame 0x46D0 +#else +#define HIVE_ADDR_sem_for_reading_cb_frame 0x4718 +#endif +#define HIVE_SIZE_sem_for_reading_cb_frame 40 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_reading_cb_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_reading_cb_frame 0x46D0 +#else +#define HIVE_ADDR_sp_sem_for_reading_cb_frame 0x4718 +#endif +#define HIVE_SIZE_sp_sem_for_reading_cb_frame 40 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_execute: 3230 */ +#else +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_is_isp_requested +#define HIVE_MEM_is_isp_requested scalar_processor_2400_dmem +#define HIVE_ADDR_is_isp_requested 0x320 +#define HIVE_SIZE_is_isp_requested 4 +#else +#endif +#endif +#define HIVE_MEM_sp_is_isp_requested scalar_processor_2400_dmem +#define HIVE_ADDR_sp_is_isp_requested 0x320 +#define HIVE_SIZE_sp_is_isp_requested 4 + +/* function ia_css_dmaproxy_sp_execute: 340F */ +#endif + +#ifndef ISP2401 +/* function ia_css_queue_is_empty: 48F9 */ +#else +/* function ia_css_queue_is_empty: 7098 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_has_stopped: 1825 */ +#else +/* function ia_css_pipeline_sp_has_stopped: 185F */ +#endif + +#ifndef ISP2401 +/* function ia_css_circbuf_extract: F44 */ +#else +/* function ia_css_circbuf_extract: F39 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_is_locked_from_start: 2B26 */ +#else +/* function ia_css_tagger_buf_sp_is_locked_from_start: 2CC8 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_current_sp_thread +#define HIVE_MEM_current_sp_thread scalar_processor_2400_dmem +#define HIVE_ADDR_current_sp_thread 0x1DC +#define HIVE_SIZE_current_sp_thread 4 +#else +#endif +#endif +#define HIVE_MEM_sp_current_sp_thread scalar_processor_2400_dmem +#define HIVE_ADDR_sp_current_sp_thread 0x1DC +#define HIVE_SIZE_sp_current_sp_thread 4 + +#ifndef ISP2401 +/* function ia_css_spctrl_sp_get_spid: 5963 */ +#else +/* function ia_css_spctrl_sp_get_spid: 5A9E */ +#endif + +#ifndef ISP2401 +/* function ia_css_bufq_sp_reset_buffers: 2D3B */ +#else +/* function ia_css_bufq_sp_reset_buffers: 2EDD */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_read_byte_addr: 6E35 */ +#else +/* function ia_css_dmaproxy_sp_read_byte_addr: 6F79 */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_uninit: 61E1 */ +#else +/* function ia_css_rmgr_sp_uninit: 631C */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_threads_stack +#define HIVE_MEM_sp_threads_stack scalar_processor_2400_dmem +#define HIVE_ADDR_sp_threads_stack 0x164 +#define HIVE_SIZE_sp_threads_stack 28 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_threads_stack scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_threads_stack 0x164 +#define HIVE_SIZE_sp_sp_threads_stack 28 + +#ifndef ISP2401 +/* function ia_css_circbuf_peek: F26 */ +#else +/* function ia_css_circbuf_peek: F1B */ +#endif + +#ifndef ISP2401 +/* function ia_css_parambuf_sp_wait_for_in_param: 1053 */ +#else +/* function ia_css_parambuf_sp_wait_for_in_param: 1048 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_token_map_get_exp_id: 5FC6 */ +#else +/* function ia_css_isys_sp_token_map_get_exp_id: 6101 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cb_elems_param +#define HIVE_MEM_sp_all_cb_elems_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cb_elems_param 0x46F8 +#else +#define HIVE_ADDR_sp_all_cb_elems_param 0x4740 +#endif +#define HIVE_SIZE_sp_all_cb_elems_param 16 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cb_elems_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cb_elems_param 0x46F8 +#else +#define HIVE_ADDR_sp_sp_all_cb_elems_param 0x4740 +#endif +#define HIVE_SIZE_sp_sp_all_cb_elems_param 16 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_pipeline_sp_curr_binary_id +#define HIVE_MEM_pipeline_sp_curr_binary_id scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_pipeline_sp_curr_binary_id 0x1EC +#else +#define HIVE_ADDR_pipeline_sp_curr_binary_id 0x1F0 +#endif +#define HIVE_SIZE_pipeline_sp_curr_binary_id 4 +#else +#endif +#endif +#define HIVE_MEM_sp_pipeline_sp_curr_binary_id scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_pipeline_sp_curr_binary_id 0x1EC +#else +#define HIVE_ADDR_sp_pipeline_sp_curr_binary_id 0x1F0 +#endif +#define HIVE_SIZE_sp_pipeline_sp_curr_binary_id 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cbs_frame_desc +#define HIVE_MEM_sp_all_cbs_frame_desc scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cbs_frame_desc 0x4708 +#else +#define HIVE_ADDR_sp_all_cbs_frame_desc 0x4750 +#endif +#define HIVE_SIZE_sp_all_cbs_frame_desc 8 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cbs_frame_desc scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cbs_frame_desc 0x4708 +#else +#define HIVE_ADDR_sp_sp_all_cbs_frame_desc 0x4750 +#endif +#define HIVE_SIZE_sp_sp_all_cbs_frame_desc 8 + +#ifndef ISP2401 +/* function sp_isys_copy_func_v2: 706 */ +#else +/* function sp_isys_copy_func_v2: 69A */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_reading_cb_param +#define HIVE_MEM_sem_for_reading_cb_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_reading_cb_param 0x4710 +#else +#define HIVE_ADDR_sem_for_reading_cb_param 0x4758 +#endif +#define HIVE_SIZE_sem_for_reading_cb_param 40 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_reading_cb_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_reading_cb_param 0x4710 +#else +#define HIVE_ADDR_sp_sem_for_reading_cb_param 0x4758 +#endif +#define HIVE_SIZE_sp_sem_for_reading_cb_param 40 + +#ifndef ISP2401 +/* function ia_css_queue_get_used_space: 49C6 */ +#else +/* function ia_css_queue_get_used_space: 4C24 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_cont_capt_start +#define HIVE_MEM_sem_for_cont_capt_start scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_cont_capt_start 0x4738 +#else +#define HIVE_ADDR_sem_for_cont_capt_start 0x4780 +#endif +#define HIVE_SIZE_sem_for_cont_capt_start 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_cont_capt_start scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_cont_capt_start 0x4738 +#else +#define HIVE_ADDR_sp_sem_for_cont_capt_start 0x4780 +#endif +#define HIVE_SIZE_sp_sem_for_cont_capt_start 20 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_tmp_heap +#define HIVE_MEM_tmp_heap scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_tmp_heap 0x6010 +#else +#define HIVE_ADDR_tmp_heap 0x6070 +#endif +#define HIVE_SIZE_tmp_heap 640 +#else +#endif +#endif +#define HIVE_MEM_sp_tmp_heap scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_tmp_heap 0x6010 +#else +#define HIVE_ADDR_sp_tmp_heap 0x6070 +#endif +#define HIVE_SIZE_sp_tmp_heap 640 + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_get_num_vbuf: 64F1 */ +#else +/* function ia_css_rmgr_sp_get_num_vbuf: 662C */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_output_compute_dma_info: 3F62 */ +#else +/* function ia_css_ispctrl_sp_output_compute_dma_info: 41A5 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_lock_exp_id: 20E6 */ +#else +/* function ia_css_tagger_sp_lock_exp_id: 2136 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_s3a_bufs +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_s3a_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_s3a_bufs 0x4B8C +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_s3a_bufs 0x4BE8 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_s3a_bufs 60 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_s3a_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_s3a_bufs 0x4B8C +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_s3a_bufs 0x4BE8 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_s3a_bufs 60 + +#ifndef ISP2401 +/* function ia_css_queue_is_full: 4A5D */ +#else +/* function ia_css_queue_is_full: 4CBB */ +#endif + +/* function debug_buffer_init_isp: E4 */ + +#ifndef ISP2401 +/* function ia_css_isys_sp_frontend_uninit: 5D20 */ +#else +/* function ia_css_isys_sp_frontend_uninit: 5E5B */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_exp_id_is_locked: 201C */ +#else +/* function ia_css_tagger_sp_exp_id_is_locked: 206C */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_rmgr_sp_mipi_frame_sem +#define HIVE_MEM_ia_css_rmgr_sp_mipi_frame_sem scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_rmgr_sp_mipi_frame_sem 0x66E8 +#else +#define HIVE_ADDR_ia_css_rmgr_sp_mipi_frame_sem 0x6744 +#endif +#define HIVE_SIZE_ia_css_rmgr_sp_mipi_frame_sem 60 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_rmgr_sp_mipi_frame_sem scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_rmgr_sp_mipi_frame_sem 0x66E8 +#else +#define HIVE_ADDR_sp_ia_css_rmgr_sp_mipi_frame_sem 0x6744 +#endif +#define HIVE_SIZE_sp_ia_css_rmgr_sp_mipi_frame_sem 60 + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_refcount_dump: 62C8 */ +#else +/* function ia_css_rmgr_sp_refcount_dump: 6403 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_isp_parameters_id +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_isp_parameters_id scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x4BC8 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x4C24 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_isp_parameters_id 20 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x4BC8 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id 0x4C24 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_isp_parameters_id 20 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_pipe_threads +#define HIVE_MEM_sp_pipe_threads scalar_processor_2400_dmem +#define HIVE_ADDR_sp_pipe_threads 0x150 +#define HIVE_SIZE_sp_pipe_threads 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_pipe_threads scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_pipe_threads 0x150 +#define HIVE_SIZE_sp_sp_pipe_threads 20 + +#ifndef ISP2401 +/* function sp_event_proxy_func: 71B */ +#else +/* function sp_event_proxy_func: 6AF */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host2sp_isys_event_queue_handle +#define HIVE_MEM_host2sp_isys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host2sp_isys_event_queue_handle 0x4BDC +#else +#define HIVE_ADDR_host2sp_isys_event_queue_handle 0x4C38 +#endif +#define HIVE_SIZE_host2sp_isys_event_queue_handle 12 +#else +#endif +#endif +#define HIVE_MEM_sp_host2sp_isys_event_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host2sp_isys_event_queue_handle 0x4BDC +#else +#define HIVE_ADDR_sp_host2sp_isys_event_queue_handle 0x4C38 +#endif +#define HIVE_SIZE_sp_host2sp_isys_event_queue_handle 12 + +#ifndef ISP2401 +/* function ia_css_thread_sp_yield: 6A70 */ +#else +/* function ia_css_thread_sp_yield: 6BEA */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cbs_param_desc +#define HIVE_MEM_sp_all_cbs_param_desc scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cbs_param_desc 0x474C +#else +#define HIVE_ADDR_sp_all_cbs_param_desc 0x4794 +#endif +#define HIVE_SIZE_sp_all_cbs_param_desc 8 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cbs_param_desc scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cbs_param_desc 0x474C +#else +#define HIVE_ADDR_sp_sp_all_cbs_param_desc 0x4794 +#endif +#define HIVE_SIZE_sp_sp_all_cbs_param_desc 8 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_dmaproxy_sp_invalidate_tlb +#define HIVE_MEM_ia_css_dmaproxy_sp_invalidate_tlb scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb 0x5BF4 +#else +#define HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb 0x5C50 +#endif +#define HIVE_SIZE_ia_css_dmaproxy_sp_invalidate_tlb 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_dmaproxy_sp_invalidate_tlb scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_dmaproxy_sp_invalidate_tlb 0x5BF4 +#else +#define HIVE_ADDR_sp_ia_css_dmaproxy_sp_invalidate_tlb 0x5C50 +#endif +#define HIVE_SIZE_sp_ia_css_dmaproxy_sp_invalidate_tlb 4 + +#ifndef ISP2401 +/* function ia_css_thread_sp_fork: D10 */ +#else +/* function ia_css_thread_sp_fork: D05 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_destroy: 280D */ +#else +/* function ia_css_tagger_sp_destroy: 285D */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_vmem_read: 31D0 */ +#else +/* function ia_css_dmaproxy_sp_vmem_read: 33AF */ +#endif + +#ifndef ISP2401 +/* function ia_css_ifmtr_sp_init: 614F */ +#else +/* function ia_css_ifmtr_sp_init: 628A */ +#endif + +#ifndef ISP2401 +/* function initialize_sp_group: 6D4 */ +#else +/* function initialize_sp_group: 668 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_peek: 2932 */ +#else +/* function ia_css_tagger_buf_sp_peek: 2AD4 */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_init: D3C */ +#else +/* function ia_css_thread_sp_init: D31 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_reset_exp_id: 60F6 */ +#else +/* function ia_css_isys_sp_reset_exp_id: 6231 */ +#endif + +#ifndef ISP2401 +/* function qos_scheduler_update_fps: 65F0 */ +#else +/* function qos_scheduler_update_fps: 6763 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_set_stream_base_addr: 4637 */ +#else +/* function ia_css_ispctrl_sp_set_stream_base_addr: 4892 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_DMEM_BASE +#define HIVE_MEM_ISP_DMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_ISP_DMEM_BASE 0x10 +#define HIVE_SIZE_ISP_DMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_DMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ISP_DMEM_BASE 0x10 +#define HIVE_SIZE_sp_ISP_DMEM_BASE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_SP_DMEM_BASE +#define HIVE_MEM_SP_DMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_SP_DMEM_BASE 0x4 +#define HIVE_SIZE_SP_DMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_SP_DMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_SP_DMEM_BASE 0x4 +#define HIVE_SIZE_sp_SP_DMEM_BASE 4 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_read: 3246 */ +#else +/* function __ia_css_queue_is_empty_text: 4B81 */ + +/* function ia_css_dmaproxy_sp_read: 3425 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_raw_copy_line_count +#define HIVE_MEM_raw_copy_line_count scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_raw_copy_line_count 0x2C8 +#else +#define HIVE_ADDR_raw_copy_line_count 0x2E0 +#endif +#define HIVE_SIZE_raw_copy_line_count 4 +#else +#endif +#endif +#define HIVE_MEM_sp_raw_copy_line_count scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_raw_copy_line_count 0x2C8 +#else +#define HIVE_ADDR_sp_raw_copy_line_count 0x2E0 +#endif +#define HIVE_SIZE_sp_raw_copy_line_count 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host2sp_tag_cmd_queue_handle +#define HIVE_MEM_host2sp_tag_cmd_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host2sp_tag_cmd_queue_handle 0x4BE8 +#else +#define HIVE_ADDR_host2sp_tag_cmd_queue_handle 0x4C44 +#endif +#define HIVE_SIZE_host2sp_tag_cmd_queue_handle 12 +#else +#endif +#endif +#define HIVE_MEM_sp_host2sp_tag_cmd_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host2sp_tag_cmd_queue_handle 0x4BE8 +#else +#define HIVE_ADDR_sp_host2sp_tag_cmd_queue_handle 0x4C44 +#endif +#define HIVE_SIZE_sp_host2sp_tag_cmd_queue_handle 12 + +#ifndef ISP2401 +/* function ia_css_queue_peek: 493C */ +#else +/* function ia_css_queue_peek: 4B9A */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_flash_sp_frame_cnt +#define HIVE_MEM_ia_css_flash_sp_frame_cnt scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_flash_sp_frame_cnt 0x4A94 +#else +#define HIVE_ADDR_ia_css_flash_sp_frame_cnt 0x4AF0 +#endif +#define HIVE_SIZE_ia_css_flash_sp_frame_cnt 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_flash_sp_frame_cnt scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_flash_sp_frame_cnt 0x4A94 +#else +#define HIVE_ADDR_sp_ia_css_flash_sp_frame_cnt 0x4AF0 +#endif +#define HIVE_SIZE_sp_ia_css_flash_sp_frame_cnt 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_event_can_send_token_mask +#define HIVE_MEM_event_can_send_token_mask scalar_processor_2400_dmem +#define HIVE_ADDR_event_can_send_token_mask 0x88 +#define HIVE_SIZE_event_can_send_token_mask 44 +#else +#endif +#endif +#define HIVE_MEM_sp_event_can_send_token_mask scalar_processor_2400_dmem +#define HIVE_ADDR_sp_event_can_send_token_mask 0x88 +#define HIVE_SIZE_sp_event_can_send_token_mask 44 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isp_thread +#define HIVE_MEM_isp_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isp_thread 0x5F40 +#else +#define HIVE_ADDR_isp_thread 0x5FA0 +#endif +#define HIVE_SIZE_isp_thread 4 +#else +#endif +#endif +#define HIVE_MEM_sp_isp_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_thread 0x5F40 +#else +#define HIVE_ADDR_sp_isp_thread 0x5FA0 +#endif +#define HIVE_SIZE_sp_isp_thread 4 + +#ifndef ISP2401 +/* function encode_and_post_sp_event_non_blocking: A78 */ +#else +/* function encode_and_post_sp_event_non_blocking: A0C */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_frontend_destroy: 5DF8 */ +#else +/* function ia_css_isys_sp_frontend_destroy: 5F33 */ +#endif + +/* function is_ddr_debug_buffer_full: 2CC */ + +#ifndef ISP2401 +/* function ia_css_isys_sp_frontend_stop: 5D38 */ +#else +/* function ia_css_isys_sp_frontend_stop: 5E73 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_token_map_init: 6094 */ +#else +/* function ia_css_isys_sp_token_map_init: 61CF */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_get_oldest_marked_offset: 2982 */ +#else +/* function ia_css_tagger_buf_sp_get_oldest_marked_offset: 2B24 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_threads_fiber +#define HIVE_MEM_sp_threads_fiber scalar_processor_2400_dmem +#define HIVE_ADDR_sp_threads_fiber 0x19C +#define HIVE_SIZE_sp_threads_fiber 28 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_threads_fiber scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_threads_fiber 0x19C +#define HIVE_SIZE_sp_sp_threads_fiber 28 + +#ifndef ISP2401 +/* function encode_and_post_sp_event: A01 */ +#else +/* function encode_and_post_sp_event: 995 */ +#endif + +/* function debug_enqueue_ddr: EE */ + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_refcount_init_vbuf: 6283 */ +#else +/* function ia_css_rmgr_sp_refcount_init_vbuf: 63BE */ +#endif + +#ifndef ISP2401 +/* function dmaproxy_sp_read_write: 6EE4 */ +#else +/* function dmaproxy_sp_read_write: 7017 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_dmaproxy_isp_dma_cmd_buffer +#define HIVE_MEM_ia_css_dmaproxy_isp_dma_cmd_buffer scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_dmaproxy_isp_dma_cmd_buffer 0x5BF8 +#else +#define HIVE_ADDR_ia_css_dmaproxy_isp_dma_cmd_buffer 0x5C54 +#endif +#define HIVE_SIZE_ia_css_dmaproxy_isp_dma_cmd_buffer 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_dmaproxy_isp_dma_cmd_buffer scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_dmaproxy_isp_dma_cmd_buffer 0x5BF8 +#else +#define HIVE_ADDR_sp_ia_css_dmaproxy_isp_dma_cmd_buffer 0x5C54 +#endif +#define HIVE_SIZE_sp_ia_css_dmaproxy_isp_dma_cmd_buffer 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host2sp_buffer_queue_handle +#define HIVE_MEM_host2sp_buffer_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host2sp_buffer_queue_handle 0x4BF4 +#else +#define HIVE_ADDR_host2sp_buffer_queue_handle 0x4C50 +#endif +#define HIVE_SIZE_host2sp_buffer_queue_handle 480 +#else +#endif +#endif +#define HIVE_MEM_sp_host2sp_buffer_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host2sp_buffer_queue_handle 0x4BF4 +#else +#define HIVE_ADDR_sp_host2sp_buffer_queue_handle 0x4C50 +#endif +#define HIVE_SIZE_sp_host2sp_buffer_queue_handle 480 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_flash_sp_in_service +#define HIVE_MEM_ia_css_flash_sp_in_service scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_flash_sp_in_service 0x3178 +#else +#define HIVE_ADDR_ia_css_flash_sp_in_service 0x3198 +#endif +#define HIVE_SIZE_ia_css_flash_sp_in_service 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_flash_sp_in_service scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_flash_sp_in_service 0x3178 +#else +#define HIVE_ADDR_sp_ia_css_flash_sp_in_service 0x3198 +#endif +#define HIVE_SIZE_sp_ia_css_flash_sp_in_service 4 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_process: 6BF0 */ +#else +/* function ia_css_dmaproxy_sp_process: 6D63 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_mark_from_end: 2C0A */ +#else +/* function ia_css_tagger_buf_sp_mark_from_end: 2DAC */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_backend_rcv_acquire_ack: 5A05 */ +#else +/* function ia_css_isys_sp_backend_rcv_acquire_ack: 5B40 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_backend_pre_acquire_request: 5A1B */ +#else +/* function ia_css_isys_sp_backend_pre_acquire_request: 5B56 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_init_cs: 366C */ +#else +/* function ia_css_ispctrl_sp_init_cs: 386E */ +#endif + +#ifndef ISP2401 +/* function ia_css_spctrl_sp_init: 5971 */ +#else +/* function ia_css_spctrl_sp_init: 5AAC */ +#endif + +#ifndef ISP2401 +/* function sp_event_proxy_init: 730 */ +#else +/* function sp_event_proxy_init: 6C4 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_previous_clock_tick +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_previous_clock_tick scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x4DD4 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x4E30 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_previous_clock_tick 40 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x4DD4 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick 0x4E30 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_previous_clock_tick 40 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_output +#define HIVE_MEM_sp_output scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_output 0x41F8 +#else +#define HIVE_ADDR_sp_output 0x4218 +#endif +#define HIVE_SIZE_sp_output 16 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_output scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_output 0x41F8 +#else +#define HIVE_ADDR_sp_sp_output 0x4218 +#endif +#define HIVE_SIZE_sp_sp_output 16 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_sems_for_host2sp_buf_queues +#define HIVE_MEM_ia_css_bufq_sp_sems_for_host2sp_buf_queues scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x4DFC +#else +#define HIVE_ADDR_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x4E58 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_sems_for_host2sp_buf_queues 800 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x4DFC +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues 0x4E58 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_sems_for_host2sp_buf_queues 800 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_CTRL_BASE +#define HIVE_MEM_ISP_CTRL_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_ISP_CTRL_BASE 0x8 +#define HIVE_SIZE_ISP_CTRL_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_CTRL_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ISP_CTRL_BASE 0x8 +#define HIVE_SIZE_sp_ISP_CTRL_BASE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_INPUT_FORMATTER_BASE +#define HIVE_MEM_INPUT_FORMATTER_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_INPUT_FORMATTER_BASE 0x4C +#define HIVE_SIZE_INPUT_FORMATTER_BASE 16 +#else +#endif +#endif +#define HIVE_MEM_sp_INPUT_FORMATTER_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_INPUT_FORMATTER_BASE 0x4C +#define HIVE_SIZE_sp_INPUT_FORMATTER_BASE 16 + +#ifndef ISP2401 +/* function sp_dma_proxy_reset_channels: 34A0 */ +#else +/* function sp_dma_proxy_reset_channels: 3694 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_backend_acquire: 5B26 */ +#else +/* function ia_css_isys_sp_backend_acquire: 5C61 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_update_size: 2901 */ +#else +/* function ia_css_tagger_sp_update_size: 2AA3 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_host_sp_queue +#define HIVE_MEM_ia_css_bufq_host_sp_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_host_sp_queue 0x511C +#else +#define HIVE_ADDR_ia_css_bufq_host_sp_queue 0x5178 +#endif +#define HIVE_SIZE_ia_css_bufq_host_sp_queue 2008 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_host_sp_queue scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_host_sp_queue 0x511C +#else +#define HIVE_ADDR_sp_ia_css_bufq_host_sp_queue 0x5178 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_host_sp_queue 2008 + +#ifndef ISP2401 +/* function thread_fiber_sp_create: DA8 */ +#else +/* function thread_fiber_sp_create: D9D */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_set_increments: 3332 */ +#else +/* function ia_css_dmaproxy_sp_set_increments: 3526 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_writing_cb_frame +#define HIVE_MEM_sem_for_writing_cb_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_writing_cb_frame 0x4754 +#else +#define HIVE_ADDR_sem_for_writing_cb_frame 0x479C +#endif +#define HIVE_SIZE_sem_for_writing_cb_frame 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_writing_cb_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_writing_cb_frame 0x4754 +#else +#define HIVE_ADDR_sp_sem_for_writing_cb_frame 0x479C +#endif +#define HIVE_SIZE_sp_sem_for_writing_cb_frame 20 + +#ifndef ISP2401 +/* function receiver_reg_store: AD7 */ +#else +/* function receiver_reg_store: AD1 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_writing_cb_param +#define HIVE_MEM_sem_for_writing_cb_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_writing_cb_param 0x4768 +#else +#define HIVE_ADDR_sem_for_writing_cb_param 0x47B0 +#endif +#define HIVE_SIZE_sem_for_writing_cb_param 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_writing_cb_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_writing_cb_param 0x4768 +#else +#define HIVE_ADDR_sp_sem_for_writing_cb_param 0x47B0 +#endif +#define HIVE_SIZE_sp_sem_for_writing_cb_param 20 + +/* function sp_start_isp_entry: 453 */ +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifdef HIVE_ADDR_sp_start_isp_entry +#endif +#define HIVE_ADDR_sp_start_isp_entry 0x453 +#endif +#define HIVE_ADDR_sp_sp_start_isp_entry 0x453 + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_unmark_all: 2B8E */ +#else +/* function ia_css_tagger_buf_sp_unmark_all: 2D30 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_unmark_from_start: 2BCF */ +#else +/* function ia_css_tagger_buf_sp_unmark_from_start: 2D71 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_channel_acquire: 34CC */ +#else +/* function ia_css_dmaproxy_sp_channel_acquire: 36C0 */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_add_num_vbuf: 64CD */ +#else +/* function ia_css_rmgr_sp_add_num_vbuf: 6608 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_token_map_create: 60DD */ +#else +/* function ia_css_isys_sp_token_map_create: 6218 */ +#endif + +#ifndef ISP2401 +/* function __ia_css_dmaproxy_sp_wait_for_ack_text: 319C */ +#else +/* function __ia_css_dmaproxy_sp_wait_for_ack_text: 337B */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_acquire_buf_elem: 1FF4 */ +#else +/* function ia_css_tagger_sp_acquire_buf_elem: 2044 */ +#endif + +#ifndef ISP2401 +/* function ia_css_bufq_sp_is_dynamic_buffer: 3085 */ +#else +/* function ia_css_bufq_sp_is_dynamic_buffer: 3227 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_group +#define HIVE_MEM_sp_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_group 0x4208 +#define HIVE_SIZE_sp_group 1144 +#else +#define HIVE_ADDR_sp_group 0x4228 +#define HIVE_SIZE_sp_group 1184 +#endif +#else +#endif +#endif +#define HIVE_MEM_sp_sp_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_group 0x4208 +#define HIVE_SIZE_sp_sp_group 1144 +#else +#define HIVE_ADDR_sp_sp_group 0x4228 +#define HIVE_SIZE_sp_sp_group 1184 +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_event_proxy_thread +#define HIVE_MEM_sp_event_proxy_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_event_proxy_thread 0x4954 +#define HIVE_SIZE_sp_event_proxy_thread 68 +#else +#define HIVE_ADDR_sp_event_proxy_thread 0x49B0 +#define HIVE_SIZE_sp_event_proxy_thread 72 +#endif +#else +#endif +#endif +#define HIVE_MEM_sp_sp_event_proxy_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_event_proxy_thread 0x4954 +#define HIVE_SIZE_sp_sp_event_proxy_thread 68 +#else +#define HIVE_ADDR_sp_sp_event_proxy_thread 0x49B0 +#define HIVE_SIZE_sp_sp_event_proxy_thread 72 +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_kill: CD6 */ +#else +/* function ia_css_thread_sp_kill: CCB */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_create: 28BB */ +#else +/* function ia_css_tagger_sp_create: 2A51 */ +#endif + +#ifndef ISP2401 +/* function tmpmem_acquire_dmem: 657A */ +#else +/* function tmpmem_acquire_dmem: 66B5 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_MMU_BASE +#define HIVE_MEM_MMU_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_MMU_BASE 0x24 +#define HIVE_SIZE_MMU_BASE 8 +#else +#endif +#endif +#define HIVE_MEM_sp_MMU_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_MMU_BASE 0x24 +#define HIVE_SIZE_sp_MMU_BASE 8 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_channel_release: 34B8 */ +#else +/* function ia_css_dmaproxy_sp_channel_release: 36AC */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_is_idle: 3498 */ +#else +/* function ia_css_dmaproxy_sp_is_idle: 368C */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_qos_start +#define HIVE_MEM_sem_for_qos_start scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_qos_start 0x477C +#else +#define HIVE_ADDR_sem_for_qos_start 0x47C4 +#endif +#define HIVE_SIZE_sem_for_qos_start 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_qos_start scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_qos_start 0x477C +#else +#define HIVE_ADDR_sp_sem_for_qos_start 0x47C4 +#endif +#define HIVE_SIZE_sp_sem_for_qos_start 20 + +#ifndef ISP2401 +/* function isp_hmem_load: B55 */ +#else +/* function isp_hmem_load: B4F */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_release_buf_elem: 1FD0 */ +#else +/* function ia_css_tagger_sp_release_buf_elem: 2020 */ +#endif + +#ifndef ISP2401 +/* function ia_css_eventq_sp_send: 350E */ +#else +/* function ia_css_eventq_sp_send: 3702 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_isys_sp_error_cnt +#define HIVE_MEM_ia_css_isys_sp_error_cnt scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_isys_sp_error_cnt 0x62D4 +#else +#define HIVE_ADDR_ia_css_isys_sp_error_cnt 0x6330 +#endif +#define HIVE_SIZE_ia_css_isys_sp_error_cnt 16 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_isys_sp_error_cnt scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_isys_sp_error_cnt 0x62D4 +#else +#define HIVE_ADDR_sp_ia_css_isys_sp_error_cnt 0x6330 +#endif +#define HIVE_SIZE_sp_ia_css_isys_sp_error_cnt 16 + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_unlock_from_start: 2ABE */ +#else +/* function ia_css_tagger_buf_sp_unlock_from_start: 2C60 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_debug_buffer_ddr_address +#define HIVE_MEM_debug_buffer_ddr_address scalar_processor_2400_dmem +#define HIVE_ADDR_debug_buffer_ddr_address 0xBC +#define HIVE_SIZE_debug_buffer_ddr_address 4 +#else +#endif +#endif +#define HIVE_MEM_sp_debug_buffer_ddr_address scalar_processor_2400_dmem +#define HIVE_ADDR_sp_debug_buffer_ddr_address 0xBC +#define HIVE_SIZE_sp_debug_buffer_ddr_address 4 + +#ifndef ISP2401 +/* function sp_isys_copy_request: 714 */ +#else +/* function sp_isys_copy_request: 6A8 */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_refcount_retain_vbuf: 635D */ +#else +/* function ia_css_rmgr_sp_refcount_retain_vbuf: 6498 */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_set_priority: CCE */ +#else +/* function ia_css_thread_sp_set_priority: CC3 */ +#endif + +#ifndef ISP2401 +/* function sizeof_hmem: BFC */ +#else +/* function sizeof_hmem: BF6 */ +#endif + +#ifndef ISP2401 +/* function tmpmem_release_dmem: 6569 */ +#else +/* function tmpmem_release_dmem: 66A4 */ +#endif + +/* function cnd_input_system_cfg: 392 */ + +#ifndef ISP2401 +/* function __ia_css_sp_rawcopy_func_critical: 6F65 */ +#else +/* function __ia_css_sp_rawcopy_func_critical: 70C2 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_set_width_exception: 331D */ +#else +/* function __ia_css_dmaproxy_sp_process_text: 331F */ +#endif + +#ifndef ISP2401 +/* function sp_event_assert: 8B1 */ +#else +/* function ia_css_dmaproxy_sp_set_width_exception: 3511 */ +#endif + +#ifndef ISP2401 +/* function ia_css_flash_sp_init_internal_params: 2CA9 */ +#else +/* function sp_event_assert: 845 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_pop_unmarked_and_unlocked: 29C4 */ +#else +/* function ia_css_flash_sp_init_internal_params: 2E4B */ +#endif + +#ifndef ISP2401 +/* function __modu: 68BB */ +#else +/* function ia_css_tagger_buf_sp_pop_unmarked_and_unlocked: 2B66 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_init_isp_vector: 31A2 */ +#else +/* function __modu: 6A2E */ + +/* function ia_css_dmaproxy_sp_init_isp_vector: 3381 */ +#endif + +/* function isp_vamem_store: 0 */ + +#ifdef ISP2401 +/* function ia_css_tagger_sp_set_copy_pipe: 2A48 */ + +#endif +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_GDC_BASE +#define HIVE_MEM_GDC_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_GDC_BASE 0x44 +#define HIVE_SIZE_GDC_BASE 8 +#else +#endif +#endif +#define HIVE_MEM_sp_GDC_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_GDC_BASE 0x44 +#define HIVE_SIZE_sp_GDC_BASE 8 + +#ifndef ISP2401 +/* function ia_css_queue_local_init: 4C27 */ +#else +/* function ia_css_queue_local_init: 4E85 */ +#endif + +#ifndef ISP2401 +/* function sp_event_proxy_callout_func: 6988 */ +#else +/* function sp_event_proxy_callout_func: 6AFB */ +#endif + +#ifndef ISP2401 +/* function qos_scheduler_schedule_stage: 65C1 */ +#else +/* function qos_scheduler_schedule_stage: 670F */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_thread_sp_num_ready_threads +#define HIVE_MEM_ia_css_thread_sp_num_ready_threads scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_thread_sp_num_ready_threads 0x49E0 +#else +#define HIVE_ADDR_ia_css_thread_sp_num_ready_threads 0x4A40 +#endif +#define HIVE_SIZE_ia_css_thread_sp_num_ready_threads 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_thread_sp_num_ready_threads scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_thread_sp_num_ready_threads 0x49E0 +#else +#define HIVE_ADDR_sp_ia_css_thread_sp_num_ready_threads 0x4A40 +#endif +#define HIVE_SIZE_sp_ia_css_thread_sp_num_ready_threads 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_threads_stack_size +#define HIVE_MEM_sp_threads_stack_size scalar_processor_2400_dmem +#define HIVE_ADDR_sp_threads_stack_size 0x180 +#define HIVE_SIZE_sp_threads_stack_size 28 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_threads_stack_size scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_threads_stack_size 0x180 +#define HIVE_SIZE_sp_sp_threads_stack_size 28 + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_isp_done_row_striping: 3F48 */ +#else +/* function ia_css_ispctrl_sp_isp_done_row_striping: 418B */ +#endif + +#ifndef ISP2401 +/* function __ia_css_isys_sp_isr_text: 5E22 */ +#else +/* function __ia_css_isys_sp_isr_text: 5F5D */ +#endif + +#ifndef ISP2401 +/* function ia_css_queue_dequeue: 4AA5 */ +#else +/* function ia_css_queue_dequeue: 4D03 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_configure_channel: 6E4C */ +#else +/* function is_qos_standalone_mode: 66EA */ + +/* function ia_css_dmaproxy_sp_configure_channel: 6F90 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_current_thread_fiber_sp +#define HIVE_MEM_current_thread_fiber_sp scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_current_thread_fiber_sp 0x49E8 +#else +#define HIVE_ADDR_current_thread_fiber_sp 0x4A44 +#endif +#define HIVE_SIZE_current_thread_fiber_sp 4 +#else +#endif +#endif +#define HIVE_MEM_sp_current_thread_fiber_sp scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_current_thread_fiber_sp 0x49E8 +#else +#define HIVE_ADDR_sp_current_thread_fiber_sp 0x4A44 +#endif +#define HIVE_SIZE_sp_current_thread_fiber_sp 4 + +#ifndef ISP2401 +/* function ia_css_circbuf_pop: FD8 */ +#else +/* function ia_css_circbuf_pop: FCD */ +#endif + +#ifndef ISP2401 +/* function memset: 693A */ +#else +/* function memset: 6AAD */ +#endif + +/* function irq_raise_set_token: B6 */ + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_GPIO_BASE +#define HIVE_MEM_GPIO_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_GPIO_BASE 0x3C +#define HIVE_SIZE_GPIO_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_GPIO_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_GPIO_BASE 0x3C +#define HIVE_SIZE_sp_GPIO_BASE 4 + +#ifndef ISP2401 +/* function ia_css_pipeline_acc_stage_enable: 17F0 */ +#else +/* function ia_css_pipeline_acc_stage_enable: 1818 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_unlock_exp_id: 2041 */ +#else +/* function ia_css_tagger_sp_unlock_exp_id: 2091 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isp_ph +#define HIVE_MEM_isp_ph scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isp_ph 0x62E4 +#else +#define HIVE_ADDR_isp_ph 0x6340 +#endif +#define HIVE_SIZE_isp_ph 28 +#else +#endif +#endif +#define HIVE_MEM_sp_isp_ph scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_ph 0x62E4 +#else +#define HIVE_ADDR_sp_isp_ph 0x6340 +#endif +#define HIVE_SIZE_sp_isp_ph 28 + +#ifndef ISP2401 +/* function ia_css_isys_sp_token_map_flush: 6022 */ +#else +/* function ia_css_isys_sp_token_map_flush: 615D */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_init_ds: 37CB */ +#else +/* function ia_css_ispctrl_sp_init_ds: 39FA */ +#endif + +#ifndef ISP2401 +/* function get_xmem_base_addr_raw: 3B78 */ +#else +/* function get_xmem_base_addr_raw: 3DB3 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cbs_param +#define HIVE_MEM_sp_all_cbs_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cbs_param 0x4790 +#else +#define HIVE_ADDR_sp_all_cbs_param 0x47D8 +#endif +#define HIVE_SIZE_sp_all_cbs_param 16 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cbs_param scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cbs_param 0x4790 +#else +#define HIVE_ADDR_sp_sp_all_cbs_param 0x47D8 +#endif +#define HIVE_SIZE_sp_sp_all_cbs_param 16 + +#ifndef ISP2401 +/* function ia_css_circbuf_create: 1026 */ +#else +/* function ia_css_circbuf_create: 101B */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_sp_group +#define HIVE_MEM_sem_for_sp_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_sp_group 0x47A0 +#else +#define HIVE_ADDR_sem_for_sp_group 0x47E8 +#endif +#define HIVE_SIZE_sem_for_sp_group 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_sp_group scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_sp_group 0x47A0 +#else +#define HIVE_ADDR_sp_sem_for_sp_group 0x47E8 +#endif +#define HIVE_SIZE_sp_sem_for_sp_group 20 + +#ifndef ISP2401 +/* function ia_css_framebuf_sp_wait_for_in_frame: 64F8 */ +#else +/* function __ia_css_dmaproxy_sp_configure_channel_text: 34F0 */ + +/* function ia_css_framebuf_sp_wait_for_in_frame: 6633 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_rawcopy_tag_frame: 5588 */ +#else +/* function ia_css_sp_rawcopy_tag_frame: 57C9 */ +#endif + +#ifndef ISP2401 +/* function isp_hmem_clear: B25 */ +#else +/* function isp_hmem_clear: B1F */ +#endif + +#ifndef ISP2401 +/* function ia_css_framebuf_sp_release_in_frame: 653B */ +#else +/* function ia_css_framebuf_sp_release_in_frame: 6676 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_backend_snd_acquire_request: 5A78 */ +#else +/* function ia_css_isys_sp_backend_snd_acquire_request: 5BB3 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_token_map_is_full: 5EA9 */ +#else +/* function ia_css_isys_sp_token_map_is_full: 5FE4 */ +#endif + +#ifndef ISP2401 +/* function input_system_acquisition_run: AF9 */ +#else +/* function input_system_acquisition_run: AF3 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_start_binary: 364A */ +#else +/* function ia_css_ispctrl_sp_start_binary: 384C */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_h_pipe_private_ddr_ptrs +#define HIVE_MEM_ia_css_bufq_sp_h_pipe_private_ddr_ptrs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x58F4 +#else +#define HIVE_ADDR_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x5950 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 20 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x58F4 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 0x5950 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_h_pipe_private_ddr_ptrs 20 + +#ifndef ISP2401 +/* function ia_css_eventq_sp_recv: 34E0 */ +#else +/* function ia_css_eventq_sp_recv: 36D4 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isp_pool +#define HIVE_MEM_isp_pool scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isp_pool 0x2E8 +#else +#define HIVE_ADDR_isp_pool 0x300 +#endif +#define HIVE_SIZE_isp_pool 4 +#else +#endif +#endif +#define HIVE_MEM_sp_isp_pool scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_pool 0x2E8 +#else +#define HIVE_ADDR_sp_isp_pool 0x300 +#endif +#define HIVE_SIZE_sp_isp_pool 4 + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_rel_gen: 622A */ +#else +/* function ia_css_rmgr_sp_rel_gen: 6365 */ + +/* function ia_css_tagger_sp_unblock_clients: 2919 */ +#endif + +#ifndef ISP2401 +/* function css_get_frame_processing_time_end: 1FC0 */ +#else +/* function css_get_frame_processing_time_end: 2010 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_event_any_pending_mask +#define HIVE_MEM_event_any_pending_mask scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_event_any_pending_mask 0x300 +#else +#define HIVE_ADDR_event_any_pending_mask 0x318 +#endif +#define HIVE_SIZE_event_any_pending_mask 8 +#else +#endif +#endif +#define HIVE_MEM_sp_event_any_pending_mask scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_event_any_pending_mask 0x300 +#else +#define HIVE_ADDR_sp_event_any_pending_mask 0x318 +#endif +#define HIVE_SIZE_sp_event_any_pending_mask 8 + +#ifndef ISP2401 +/* function ia_css_isys_sp_backend_push: 5A2F */ +#else +/* function ia_css_isys_sp_backend_push: 5B6A */ +#endif + +/* function sh_css_decode_tag_descr: 352 */ + +/* function debug_enqueue_isp: 27B */ + +#ifndef ISP2401 +/* function qos_scheduler_update_stage_budget: 65AF */ +#else +/* function qos_scheduler_update_stage_budget: 66F2 */ +#endif + +#ifndef ISP2401 +/* function ia_css_spctrl_sp_uninit: 596A */ +#else +/* function ia_css_spctrl_sp_uninit: 5AA5 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_HIVE_IF_SWITCH_CODE +#define HIVE_MEM_HIVE_IF_SWITCH_CODE scalar_processor_2400_dmem +#define HIVE_ADDR_HIVE_IF_SWITCH_CODE 0x1D8 +#define HIVE_SIZE_HIVE_IF_SWITCH_CODE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_HIVE_IF_SWITCH_CODE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_HIVE_IF_SWITCH_CODE 0x1D8 +#define HIVE_SIZE_sp_HIVE_IF_SWITCH_CODE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_dis_bufs +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_dis_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_dis_bufs 0x5908 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_dis_bufs 0x5964 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_dis_bufs 140 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_dis_bufs scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_dis_bufs 0x5908 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_dis_bufs 0x5964 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_dis_bufs 140 + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_lock_from_start: 2AF2 */ +#else +/* function ia_css_tagger_buf_sp_lock_from_start: 2C94 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_isp_idle +#define HIVE_MEM_sem_for_isp_idle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_isp_idle 0x47B4 +#else +#define HIVE_ADDR_sem_for_isp_idle 0x47FC +#endif +#define HIVE_SIZE_sem_for_isp_idle 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_isp_idle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_isp_idle 0x47B4 +#else +#define HIVE_ADDR_sp_sem_for_isp_idle 0x47FC +#endif +#define HIVE_SIZE_sp_sem_for_isp_idle 20 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_write_byte_addr: 31FF */ +#else +/* function ia_css_dmaproxy_sp_write_byte_addr: 33DE */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_init: 3176 */ +#else +/* function ia_css_dmaproxy_sp_init: 3355 */ +#endif + +#ifndef ISP2401 +/* function ia_css_bufq_sp_release_dynamic_buf_clock_tick: 2D7B */ +#else +/* function ia_css_bufq_sp_release_dynamic_buf_clock_tick: 2F1D */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_VAMEM_BASE +#define HIVE_MEM_ISP_VAMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_ISP_VAMEM_BASE 0x14 +#define HIVE_SIZE_ISP_VAMEM_BASE 12 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_VAMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ISP_VAMEM_BASE 0x14 +#define HIVE_SIZE_sp_ISP_VAMEM_BASE 12 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_rawcopy_sp_tagger +#define HIVE_MEM_ia_css_rawcopy_sp_tagger scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_rawcopy_sp_tagger 0x6294 +#else +#define HIVE_ADDR_ia_css_rawcopy_sp_tagger 0x62F0 +#endif +#define HIVE_SIZE_ia_css_rawcopy_sp_tagger 24 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_rawcopy_sp_tagger scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_rawcopy_sp_tagger 0x6294 +#else +#define HIVE_ADDR_sp_ia_css_rawcopy_sp_tagger 0x62F0 +#endif +#define HIVE_SIZE_sp_ia_css_rawcopy_sp_tagger 24 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_exp_ids +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_exp_ids scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_exp_ids 0x5994 +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_exp_ids 0x59F0 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_exp_ids 70 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_exp_ids scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_exp_ids 0x5994 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_exp_ids 0x59F0 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_exp_ids 70 + +#ifndef ISP2401 +/* function ia_css_queue_item_load: 4D19 */ +#else +/* function ia_css_queue_item_load: 4F77 */ +#endif + +#ifndef ISP2401 +/* function ia_css_spctrl_sp_get_state: 5955 */ +#else +/* function ia_css_spctrl_sp_get_state: 5A90 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_token_map_uninit: 603F */ +#else +/* function ia_css_isys_sp_token_map_uninit: 617A */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_callout_sp_thread +#define HIVE_MEM_callout_sp_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_callout_sp_thread 0x49DC +#else +#define HIVE_ADDR_callout_sp_thread 0x1E0 +#endif +#define HIVE_SIZE_callout_sp_thread 4 +#else +#endif +#endif +#define HIVE_MEM_sp_callout_sp_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_callout_sp_thread 0x49DC +#else +#define HIVE_ADDR_sp_callout_sp_thread 0x1E0 +#endif +#define HIVE_SIZE_sp_callout_sp_thread 4 + +#ifndef ISP2401 +/* function thread_fiber_sp_init: E2F */ +#else +/* function thread_fiber_sp_init: E24 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_SP_PMEM_BASE +#define HIVE_MEM_SP_PMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_SP_PMEM_BASE 0x0 +#define HIVE_SIZE_SP_PMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_SP_PMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_SP_PMEM_BASE 0x0 +#define HIVE_SIZE_sp_SP_PMEM_BASE 4 + +#ifndef ISP2401 +/* function ia_css_isys_sp_token_map_snd_acquire_req: 5FAF */ +#else +/* function ia_css_isys_sp_token_map_snd_acquire_req: 60EA */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_isp_input_stream_format +#define HIVE_MEM_sp_isp_input_stream_format scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_input_stream_format 0x40F8 +#else +#define HIVE_ADDR_sp_isp_input_stream_format 0x4118 +#endif +#define HIVE_SIZE_sp_isp_input_stream_format 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_isp_input_stream_format scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_isp_input_stream_format 0x40F8 +#else +#define HIVE_ADDR_sp_sp_isp_input_stream_format 0x4118 +#endif +#define HIVE_SIZE_sp_sp_isp_input_stream_format 20 + +#ifndef ISP2401 +/* function __mod: 68A7 */ +#else +/* function __mod: 6A1A */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_init_dmem_channel: 3260 */ +#else +/* function ia_css_dmaproxy_sp_init_dmem_channel: 343F */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_join: CFF */ +#else +/* function ia_css_thread_sp_join: CF4 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_add_command: 6F4F */ +#else +/* function ia_css_dmaproxy_sp_add_command: 7082 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_metadata_thread_func: 5809 */ +#else +/* function ia_css_sp_metadata_thread_func: 5968 */ +#endif + +#ifndef ISP2401 +/* function __sp_event_proxy_func_critical: 6975 */ +#else +/* function __sp_event_proxy_func_critical: 6AE8 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_metadata_wait: 591C */ +#else +/* function ia_css_sp_metadata_wait: 5A57 */ +#endif + +#ifndef ISP2401 +/* function ia_css_circbuf_peek_from_start: F08 */ +#else +/* function ia_css_circbuf_peek_from_start: EFD */ +#endif + +#ifndef ISP2401 +/* function ia_css_event_sp_encode: 356B */ +#else +/* function ia_css_event_sp_encode: 375F */ +#endif + +#ifndef ISP2401 +/* function ia_css_thread_sp_run: D72 */ +#else +/* function ia_css_thread_sp_run: D67 */ +#endif + +#ifndef ISP2401 +/* function sp_isys_copy_func: 6F6 */ +#else +/* function sp_isys_copy_func: 68A */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_backend_flush: 5A98 */ +#else +/* function ia_css_isys_sp_backend_flush: 5BD3 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_backend_frame_exists: 59B4 */ +#else +/* function ia_css_isys_sp_backend_frame_exists: 5AEF */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_isp_param_init_isp_memories: 47A2 */ +#else +/* function ia_css_sp_isp_param_init_isp_memories: 4A2A */ +#endif + +#ifndef ISP2401 +/* function register_isr: 8A9 */ +#else +/* function register_isr: 83D */ +#endif + +/* function irq_raise: C8 */ + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_mmu_invalidate: 313D */ +#else +/* function ia_css_dmaproxy_sp_mmu_invalidate: 32E5 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_HIVE_IF_SRST_ADDRESS +#define HIVE_MEM_HIVE_IF_SRST_ADDRESS scalar_processor_2400_dmem +#define HIVE_ADDR_HIVE_IF_SRST_ADDRESS 0x1B8 +#define HIVE_SIZE_HIVE_IF_SRST_ADDRESS 16 +#else +#endif +#endif +#define HIVE_MEM_sp_HIVE_IF_SRST_ADDRESS scalar_processor_2400_dmem +#define HIVE_ADDR_sp_HIVE_IF_SRST_ADDRESS 0x1B8 +#define HIVE_SIZE_sp_HIVE_IF_SRST_ADDRESS 16 + +#ifndef ISP2401 +/* function pipeline_sp_initialize_stage: 1924 */ +#else +/* function pipeline_sp_initialize_stage: 195E */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_isys_sp_frontend_states +#define HIVE_MEM_ia_css_isys_sp_frontend_states scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_isys_sp_frontend_states 0x62C8 +#else +#define HIVE_ADDR_ia_css_isys_sp_frontend_states 0x6324 +#endif +#define HIVE_SIZE_ia_css_isys_sp_frontend_states 12 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_isys_sp_frontend_states scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_isys_sp_frontend_states 0x62C8 +#else +#define HIVE_ADDR_sp_ia_css_isys_sp_frontend_states 0x6324 +#endif +#define HIVE_SIZE_sp_ia_css_isys_sp_frontend_states 12 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_read_byte_addr_mmio: 6E1E */ +#else +/* function ia_css_dmaproxy_sp_read_byte_addr_mmio: 6F62 */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_done_ds: 37B2 */ +#else +/* function ia_css_ispctrl_sp_done_ds: 39E1 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_isp_param_get_mem_inits: 477D */ +#else +/* function ia_css_sp_isp_param_get_mem_inits: 4A05 */ +#endif + +#ifndef ISP2401 +/* function ia_css_parambuf_sp_init_buffer_queues: 13D0 */ +#else +/* function ia_css_parambuf_sp_init_buffer_queues: 13F1 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_vbuf_pfp_spref +#define HIVE_MEM_vbuf_pfp_spref scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_vbuf_pfp_spref 0x2F0 +#else +#define HIVE_ADDR_vbuf_pfp_spref 0x308 +#endif +#define HIVE_SIZE_vbuf_pfp_spref 4 +#else +#endif +#endif +#define HIVE_MEM_sp_vbuf_pfp_spref scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_vbuf_pfp_spref 0x2F0 +#else +#define HIVE_ADDR_sp_vbuf_pfp_spref 0x308 +#endif +#define HIVE_SIZE_sp_vbuf_pfp_spref 4 + +#ifndef ISP2401 +/* function input_system_cfg: ABB */ +#else +/* function input_system_cfg: AB5 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_HMEM_BASE +#define HIVE_MEM_ISP_HMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_ISP_HMEM_BASE 0x20 +#define HIVE_SIZE_ISP_HMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_HMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ISP_HMEM_BASE 0x20 +#define HIVE_SIZE_sp_ISP_HMEM_BASE 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_pipe_private_frames +#define HIVE_MEM_ia_css_bufq_sp_pipe_private_frames scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_frames 0x59DC +#else +#define HIVE_ADDR_ia_css_bufq_sp_pipe_private_frames 0x5A38 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_pipe_private_frames 280 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_pipe_private_frames scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_frames 0x59DC +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_pipe_private_frames 0x5A38 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_pipe_private_frames 280 + +#ifndef ISP2401 +/* function qos_scheduler_init_stage_budget: 65E8 */ +#else +/* function qos_scheduler_init_stage_budget: 6750 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_backend_release: 5B0D */ +#else +/* function ia_css_isys_sp_backend_release: 5C48 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_backend_destroy: 5B37 */ +#else +/* function ia_css_isys_sp_backend_destroy: 5C72 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp2host_buffer_queue_handle +#define HIVE_MEM_sp2host_buffer_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp2host_buffer_queue_handle 0x5AF4 +#else +#define HIVE_ADDR_sp2host_buffer_queue_handle 0x5B50 +#endif +#define HIVE_SIZE_sp2host_buffer_queue_handle 96 +#else +#endif +#endif +#define HIVE_MEM_sp_sp2host_buffer_queue_handle scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp2host_buffer_queue_handle 0x5AF4 +#else +#define HIVE_ADDR_sp_sp2host_buffer_queue_handle 0x5B50 +#endif +#define HIVE_SIZE_sp_sp2host_buffer_queue_handle 96 + +#ifndef ISP2401 +/* function ia_css_isys_sp_token_map_check_mipi_frame_size: 5F73 */ +#else +/* function ia_css_isys_sp_token_map_check_mipi_frame_size: 60AE */ +#endif + +#ifndef ISP2401 +/* function ia_css_ispctrl_sp_init_isp_vars: 449C */ +#else +/* function ia_css_ispctrl_sp_init_isp_vars: 46F7 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_frontend_has_empty_mipi_buffer_cb: 5B89 */ +#else +/* function ia_css_isys_sp_frontend_has_empty_mipi_buffer_cb: 5CC4 */ +#endif + +#ifndef ISP2401 +/* function sp_warning: 8DC */ +#else +/* function sp_warning: 870 */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_vbuf_enqueue: 631D */ +#else +/* function ia_css_rmgr_sp_vbuf_enqueue: 6458 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_sp_tag_exp_id: 215B */ +#else +/* function ia_css_tagger_sp_tag_exp_id: 21AB */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_write: 3216 */ +#else +/* function ia_css_dmaproxy_sp_write: 33F5 */ +#endif + +#ifndef ISP2401 +/* function ia_css_parambuf_sp_release_in_param: 1250 */ +#else +/* function ia_css_parambuf_sp_release_in_param: 1245 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_irq_sw_interrupt_token +#define HIVE_MEM_irq_sw_interrupt_token scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_irq_sw_interrupt_token 0x40F4 +#else +#define HIVE_ADDR_irq_sw_interrupt_token 0x4114 +#endif +#define HIVE_SIZE_irq_sw_interrupt_token 4 +#else +#endif +#endif +#define HIVE_MEM_sp_irq_sw_interrupt_token scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_irq_sw_interrupt_token 0x40F4 +#else +#define HIVE_ADDR_sp_irq_sw_interrupt_token 0x4114 +#endif +#define HIVE_SIZE_sp_irq_sw_interrupt_token 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_isp_addresses +#define HIVE_MEM_sp_isp_addresses scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_addresses 0x5F44 +#else +#define HIVE_ADDR_sp_isp_addresses 0x5FA4 +#endif +#define HIVE_SIZE_sp_isp_addresses 172 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_isp_addresses scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_isp_addresses 0x5F44 +#else +#define HIVE_ADDR_sp_sp_isp_addresses 0x5FA4 +#endif +#define HIVE_SIZE_sp_sp_isp_addresses 172 + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_acq_gen: 6242 */ +#else +/* function ia_css_rmgr_sp_acq_gen: 637D */ +#endif + +#ifndef ISP2401 +/* function receiver_reg_load: AD0 */ +#else +/* function receiver_reg_load: ACA */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isps +#define HIVE_MEM_isps scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isps 0x6300 +#else +#define HIVE_ADDR_isps 0x635C +#endif +#define HIVE_SIZE_isps 28 +#else +#endif +#endif +#define HIVE_MEM_sp_isps scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isps 0x6300 +#else +#define HIVE_ADDR_sp_isps 0x635C +#endif +#define HIVE_SIZE_sp_isps 28 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_host_sp_queues_initialized +#define HIVE_MEM_host_sp_queues_initialized scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_host_sp_queues_initialized 0x410C +#else +#define HIVE_ADDR_host_sp_queues_initialized 0x412C +#endif +#define HIVE_SIZE_host_sp_queues_initialized 4 +#else +#endif +#endif +#define HIVE_MEM_sp_host_sp_queues_initialized scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_host_sp_queues_initialized 0x410C +#else +#define HIVE_ADDR_sp_host_sp_queues_initialized 0x412C +#endif +#define HIVE_SIZE_sp_host_sp_queues_initialized 4 + +#ifndef ISP2401 +/* function ia_css_queue_uninit: 4BE5 */ +#else +/* function ia_css_queue_uninit: 4E43 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_ispctrl_sp_isp_started +#define HIVE_MEM_ia_css_ispctrl_sp_isp_started scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_ispctrl_sp_isp_started 0x5BFC +#else +#define HIVE_ADDR_ia_css_ispctrl_sp_isp_started 0x5C58 +#endif +#define HIVE_SIZE_ia_css_ispctrl_sp_isp_started 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_ispctrl_sp_isp_started scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_ispctrl_sp_isp_started 0x5BFC +#else +#define HIVE_ADDR_sp_ia_css_ispctrl_sp_isp_started 0x5C58 +#endif +#define HIVE_SIZE_sp_ia_css_ispctrl_sp_isp_started 4 + +#ifndef ISP2401 +/* function ia_css_bufq_sp_release_dynamic_buf: 2DE7 */ +#else +/* function ia_css_bufq_sp_release_dynamic_buf: 2F89 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_set_height_exception: 330E */ +#else +/* function ia_css_dmaproxy_sp_set_height_exception: 3502 */ +#endif + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_init_vmem_channel: 3293 */ +#else +/* function ia_css_dmaproxy_sp_init_vmem_channel: 3473 */ +#endif + +#ifndef ISP2401 +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_num_ready_threads +#define HIVE_MEM_num_ready_threads scalar_processor_2400_dmem +#define HIVE_ADDR_num_ready_threads 0x49E4 +#define HIVE_SIZE_num_ready_threads 4 +#else +#endif +#endif +#define HIVE_MEM_sp_num_ready_threads scalar_processor_2400_dmem +#define HIVE_ADDR_sp_num_ready_threads 0x49E4 +#define HIVE_SIZE_sp_num_ready_threads 4 + +/* function ia_css_dmaproxy_sp_write_byte_addr_mmio: 31E8 */ +#else +/* function ia_css_dmaproxy_sp_write_byte_addr_mmio: 33C7 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_vbuf_spref +#define HIVE_MEM_vbuf_spref scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_vbuf_spref 0x2EC +#else +#define HIVE_ADDR_vbuf_spref 0x304 +#endif +#define HIVE_SIZE_vbuf_spref 4 +#else +#endif +#endif +#define HIVE_MEM_sp_vbuf_spref scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_vbuf_spref 0x2EC +#else +#define HIVE_ADDR_sp_vbuf_spref 0x304 +#endif +#define HIVE_SIZE_sp_vbuf_spref 4 + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_metadata_thread +#define HIVE_MEM_sp_metadata_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_metadata_thread 0x4998 +#define HIVE_SIZE_sp_metadata_thread 68 +#else +#define HIVE_ADDR_sp_metadata_thread 0x49F8 +#define HIVE_SIZE_sp_metadata_thread 72 +#endif +#else +#endif +#endif +#define HIVE_MEM_sp_sp_metadata_thread scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_metadata_thread 0x4998 +#define HIVE_SIZE_sp_sp_metadata_thread 68 +#else +#define HIVE_ADDR_sp_sp_metadata_thread 0x49F8 +#define HIVE_SIZE_sp_sp_metadata_thread 72 +#endif + +#ifndef ISP2401 +/* function ia_css_queue_enqueue: 4B2F */ +#else +/* function ia_css_queue_enqueue: 4D8D */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_flash_sp_request +#define HIVE_MEM_ia_css_flash_sp_request scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_flash_sp_request 0x4A98 +#else +#define HIVE_ADDR_ia_css_flash_sp_request 0x4AF4 +#endif +#define HIVE_SIZE_ia_css_flash_sp_request 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_flash_sp_request scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_flash_sp_request 0x4A98 +#else +#define HIVE_ADDR_sp_ia_css_flash_sp_request 0x4AF4 +#endif +#define HIVE_SIZE_sp_ia_css_flash_sp_request 4 + +#ifndef ISP2401 +/* function ia_css_dmaproxy_sp_vmem_write: 31B9 */ +#else +/* function ia_css_dmaproxy_sp_vmem_write: 3398 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_tagger_frames +#define HIVE_MEM_tagger_frames scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_tagger_frames 0x49EC +#else +#define HIVE_ADDR_tagger_frames 0x4A48 +#endif +#define HIVE_SIZE_tagger_frames 168 +#else +#endif +#endif +#define HIVE_MEM_sp_tagger_frames scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_tagger_frames 0x49EC +#else +#define HIVE_ADDR_sp_tagger_frames 0x4A48 +#endif +#define HIVE_SIZE_sp_tagger_frames 168 + +#ifndef ISP2401 +/* function ia_css_isys_sp_token_map_snd_capture_req: 5FD1 */ +#else +/* function ia_css_isys_sp_token_map_snd_capture_req: 610C */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_reading_if +#define HIVE_MEM_sem_for_reading_if scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_reading_if 0x47C8 +#else +#define HIVE_ADDR_sem_for_reading_if 0x4810 +#endif +#define HIVE_SIZE_sem_for_reading_if 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_reading_if scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_reading_if 0x47C8 +#else +#define HIVE_ADDR_sp_sem_for_reading_if 0x4810 +#endif +#define HIVE_SIZE_sp_sem_for_reading_if 20 + +#ifndef ISP2401 +/* function sp_generate_interrupts: 95B */ +#else +/* function sp_generate_interrupts: 8EF */ + +/* function ia_css_pipeline_sp_start: 1871 */ +#endif + +#ifndef ISP2401 +/* function ia_css_pipeline_sp_start: 1837 */ +#else +/* function ia_css_thread_default_callout: 6BE3 */ +#endif + +#ifndef ISP2401 +/* function ia_css_sp_rawcopy_init: 510C */ +#else +/* function ia_css_sp_rawcopy_init: 536A */ +#endif + +#ifndef ISP2401 +/* function tmr_clock_read: 13F1 */ +#else +/* function tmr_clock_read: 1412 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_BAMEM_BASE +#define HIVE_MEM_ISP_BAMEM_BASE scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ISP_BAMEM_BASE 0x2F8 +#else +#define HIVE_ADDR_ISP_BAMEM_BASE 0x310 +#endif +#define HIVE_SIZE_ISP_BAMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_BAMEM_BASE scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ISP_BAMEM_BASE 0x2F8 +#else +#define HIVE_ADDR_sp_ISP_BAMEM_BASE 0x310 +#endif +#define HIVE_SIZE_sp_ISP_BAMEM_BASE 4 + +#ifndef ISP2401 +/* function ia_css_isys_sp_frontend_rcv_capture_ack: 5C38 */ +#else +/* function ia_css_isys_sp_frontend_rcv_capture_ack: 5D73 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_bufq_sp_sems_for_sp2host_buf_queues +#define HIVE_MEM_ia_css_bufq_sp_sems_for_sp2host_buf_queues scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x5B54 +#else +#define HIVE_ADDR_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x5BB0 +#endif +#define HIVE_SIZE_ia_css_bufq_sp_sems_for_sp2host_buf_queues 160 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x5B54 +#else +#define HIVE_ADDR_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues 0x5BB0 +#endif +#define HIVE_SIZE_sp_ia_css_bufq_sp_sems_for_sp2host_buf_queues 160 + +#ifndef ISP2401 +/* function css_get_frame_processing_time_start: 1FC8 */ +#else +/* function css_get_frame_processing_time_start: 2018 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_all_cbs_frame +#define HIVE_MEM_sp_all_cbs_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_all_cbs_frame 0x47DC +#else +#define HIVE_ADDR_sp_all_cbs_frame 0x4824 +#endif +#define HIVE_SIZE_sp_all_cbs_frame 16 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_all_cbs_frame scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_all_cbs_frame 0x47DC +#else +#define HIVE_ADDR_sp_sp_all_cbs_frame 0x4824 +#endif +#define HIVE_SIZE_sp_sp_all_cbs_frame 16 + +#ifndef ISP2401 +/* function thread_sp_queue_print: D8F */ +#else +/* function thread_sp_queue_print: D84 */ +#endif + +#ifndef ISP2401 +/* function sp_notify_eof: 907 */ +#else +/* function sp_notify_eof: 89B */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sem_for_str2mem +#define HIVE_MEM_sem_for_str2mem scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sem_for_str2mem 0x47EC +#else +#define HIVE_ADDR_sem_for_str2mem 0x4834 +#endif +#define HIVE_SIZE_sem_for_str2mem 20 +#else +#endif +#endif +#define HIVE_MEM_sp_sem_for_str2mem scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sem_for_str2mem 0x47EC +#else +#define HIVE_ADDR_sp_sem_for_str2mem 0x4834 +#endif +#define HIVE_SIZE_sp_sem_for_str2mem 20 + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_is_marked_from_start: 2B5A */ +#else +/* function ia_css_tagger_buf_sp_is_marked_from_start: 2CFC */ +#endif + +#ifndef ISP2401 +/* function ia_css_bufq_sp_acquire_dynamic_buf: 2F9F */ +#else +/* function ia_css_bufq_sp_acquire_dynamic_buf: 3141 */ +#endif + +#ifndef ISP2401 +/* function ia_css_circbuf_destroy: 101D */ +#else +/* function ia_css_circbuf_destroy: 1012 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ISP_PMEM_BASE +#define HIVE_MEM_ISP_PMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_ISP_PMEM_BASE 0xC +#define HIVE_SIZE_ISP_PMEM_BASE 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ISP_PMEM_BASE scalar_processor_2400_dmem +#define HIVE_ADDR_sp_ISP_PMEM_BASE 0xC +#define HIVE_SIZE_sp_ISP_PMEM_BASE 4 + +#ifndef ISP2401 +/* function ia_css_sp_isp_param_mem_load: 4710 */ +#else +/* function ia_css_sp_isp_param_mem_load: 4998 */ +#endif + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_pop_from_start: 2946 */ +#else +/* function ia_css_tagger_buf_sp_pop_from_start: 2AE8 */ +#endif + +#ifndef ISP2401 +/* function __div: 685F */ +#else +/* function __div: 69D2 */ +#endif + +#ifndef ISP2401 +/* function ia_css_isys_sp_frontend_create: 5E09 */ +#else +/* function ia_css_isys_sp_frontend_create: 5F44 */ +#endif + +#ifndef ISP2401 +/* function ia_css_rmgr_sp_refcount_release_vbuf: 633C */ +#else +/* function ia_css_rmgr_sp_refcount_release_vbuf: 6477 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_ia_css_flash_sp_in_use +#define HIVE_MEM_ia_css_flash_sp_in_use scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_ia_css_flash_sp_in_use 0x4A9C +#else +#define HIVE_ADDR_ia_css_flash_sp_in_use 0x4AF8 +#endif +#define HIVE_SIZE_ia_css_flash_sp_in_use 4 +#else +#endif +#endif +#define HIVE_MEM_sp_ia_css_flash_sp_in_use scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_ia_css_flash_sp_in_use 0x4A9C +#else +#define HIVE_ADDR_sp_ia_css_flash_sp_in_use 0x4AF8 +#endif +#define HIVE_SIZE_sp_ia_css_flash_sp_in_use 4 + +#ifndef ISP2401 +/* function ia_css_thread_sem_sp_wait: 6B42 */ +#else +/* function ia_css_thread_sem_sp_wait: 6CB7 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_sleep_mode +#define HIVE_MEM_sp_sleep_mode scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sleep_mode 0x4110 +#else +#define HIVE_ADDR_sp_sleep_mode 0x4130 +#endif +#define HIVE_SIZE_sp_sleep_mode 4 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_sleep_mode scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_sp_sleep_mode 0x4110 +#else +#define HIVE_ADDR_sp_sp_sleep_mode 0x4130 +#endif +#define HIVE_SIZE_sp_sp_sleep_mode 4 + +#ifndef ISP2401 +/* function ia_css_tagger_buf_sp_push: 2A55 */ +#else +/* function ia_css_tagger_buf_sp_push: 2BF7 */ +#endif + +/* function mmu_invalidate_cache: D3 */ + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_sp_max_cb_elems +#define HIVE_MEM_sp_max_cb_elems scalar_processor_2400_dmem +#define HIVE_ADDR_sp_max_cb_elems 0x148 +#define HIVE_SIZE_sp_max_cb_elems 8 +#else +#endif +#endif +#define HIVE_MEM_sp_sp_max_cb_elems scalar_processor_2400_dmem +#define HIVE_ADDR_sp_sp_max_cb_elems 0x148 +#define HIVE_SIZE_sp_sp_max_cb_elems 8 + +#ifndef ISP2401 +/* function ia_css_queue_remote_init: 4C07 */ +#else +/* function ia_css_queue_remote_init: 4E65 */ +#endif + +#ifndef HIVE_MULTIPLE_PROGRAMS +#ifndef HIVE_MEM_isp_stop_req +#define HIVE_MEM_isp_stop_req scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_isp_stop_req 0x4680 +#else +#define HIVE_ADDR_isp_stop_req 0x46C8 +#endif +#define HIVE_SIZE_isp_stop_req 4 +#else +#endif +#endif +#define HIVE_MEM_sp_isp_stop_req scalar_processor_2400_dmem +#ifndef ISP2401 +#define HIVE_ADDR_sp_isp_stop_req 0x4680 +#else +#define HIVE_ADDR_sp_isp_stop_req 0x46C8 +#endif +#define HIVE_SIZE_sp_isp_stop_req 4 + +#ifndef ISP2401 +#define HIVE_ICACHE_sp_critical_SEGMENT_START 0 +#define HIVE_ICACHE_sp_critical_NUM_SEGMENTS 1 +#endif + +#endif /* _sp_map_h_ */ +#ifndef ISP2401 +extern void sh_css_dump_sp_dmem(void); +void sh_css_dump_sp_dmem(void) +{ +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_api_version.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_api_version.h new file mode 100644 index 0000000000000000000000000000000000000000..1f6a55ff5db88c77f827fd238aaeca47ec7576d5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_api_version.h @@ -0,0 +1,673 @@ +/* +#ifndef ISP2401 + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. +#endif + +#ifdef ISP2401 +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif +#ifndef __CSS_API_VERSION_H +#define __CSS_API_VERSION_H + +/** @file + * CSS API version file. This file contains the version number of the CSS-API. + * + * This file is generated from a set of input files describing the CSS-API + * changes. Don't edit this file directly. + */ + + +/** + +The version string has four dot-separated numbers, read left to right: + The first two are the API version, and should not be changed. + The third number is incremented by a CSS firmware developer when the + API change is not backwards compatible. + The fourth number is incremented by the a CSS firmware developer for + every API change. + It should be zeroed when the third number changes. + +*/ + +#ifndef ISP2401 +#define CSS_API_VERSION_STRING "2.1.15.3" +#else +#define CSS_API_VERSION_STRING "2.1.20.9" +#endif + +/* +Change log + +v2.0.1.0, initial version: +- added API versioning + +v2.0.1.1, activate CSS-API versioning: +- added description of major and minor version numbers + +v2.0.1.2, modified struct ia_css_frame_info: +- added new member ia_css_crop_info + +v2.0.1.3, added IA_CSS_ERR_NOT_SUPPORTED + +v2.1.0.0 +- moved version number to 2.1.0.0 +- created new files for refactoring the code + +v2.1.1.0, modified struct ia_css_pipe_config and struct ia_css_pipe_info and struct ia_css_pipe: +- use array to handle multiple output ports + +v2.1.1.1 +- added api to lock/unlock of RAW Buffers to Support HALv3 Feature + +v2.1.1.2, modified struct ia_css_stream_config: +- to support multiple isys streams in one virtual channel, keep the old one for backward compatibility + +v2.1.2.0, modify ia_css_stream_config: +- add isys_config and input_config to support multiple isys stream within one virtual channel + +v2.1.2.1, add IA_CSS_STREAM_FORMAT_NUM +- add IA_CSS_STREAM_FORMAT_NUM definition to reflect the number of ia_css_stream_format enums + +v2.1.2.2, modified enum ia_css_stream_format +- Add 16bit YUV formats to ia_css_stream_format enum: +- IA_CSS_STREAM_FORMAT_YUV420_16 (directly after IA_CSS_STREAM_FORMAT_YUV420_10) +- IA_CSS_STREAM_FORMAT_YUV422_16 (directly after IA_CSS_STREAM_FORMAT_YUV422_10) + +v2.1.2.3 +- added api to enable/disable digital zoom for capture pipe. + +v2.1.2.4, change CSS API to generate the shading table which should be directly sent to ISP: +- keep the old CSS API (which uses the conversion of the shading table in CSS) for backward compatibility + +v2.1.2.5 +- Added SP frame time measurement (in ticks) and result is sent on a new member +- in ia_css_buffer.h. + +v2.1.2.6, add function ia_css_check_firmware_version() +- the function ia_css_check_firmware_version() returns true when the firmware version matches and returns false otherwise. + +v2.1.2.7 +- rename dynamic_data_index to dynamic_queue_id in struct ia_css_frame. +- update IA_CSS_PIPE_MODE_NUM + +v2.1.2.8 +- added flag for video full range + +v2.1.2.9 +- add public parameters for xnr3 kernel + +v2.1.2.10 +- add new interface to enable output mirroring + +v2.1.2.11, MIPI buffers optimization +- modified struct ia_css_mipi_buffer_config, added number of MIPI buffers needed for the stream +- backwards compatible, need another patch to remove legacy function and code + +v2.1.2.12 +- create consolidated firmware package for 2400, 2401, csi2p, bxtpoc + +v2.1.3.0 +- rename ia_css_output_config.enable_mirror +- add new interface to enable vertical output flipping + +v2.1.3.1 +- deprecated ia_css_rx_get_irq_info and ia_css_rx_clear_irq_info because both are hardcoded to work on CSI port 1. +- added new functions ia_css_rx_port_get_irq_info and ia_css_rx_port_clear_irq_info, both have a port ID as extra argument. + +v2.1.3.2 +- reverted v2.1.3.0 change + +v2.1.3.3 +- Added isys event queue. +- Renamed ia_css_dequeue_event to ia_css_dequeue_psys_event +- Made ia_css_dequeue_event deprecated + +v2.1.3.4 +- added new interface to support ACC extension QoS feature. +- added IA_CSS_EVENT_TYPE_ACC_STAGE_COMPLETE. + +v2.1.3.5 +- added tiled frame format IA_CSS_FRAME_FORMAT_NV12_TILEY + +v2.1.3.6 +- added functions ia_css_host_data_allocate and ia_css_host_data_free + +v2.1.4.0, default pipe config change +- disable enable_dz param by default + +v2.1.5.0 +- removed mix_range field from yuvp1_y_ee_nr_frng_public_config + +v2.1.5.1, exposure IDs per stream +- added MIN/MAX exposure ID macros +- made exposure ID sequence per-stream instead of global (across all streams) + +#ifdef ISP2401 +v2.1.5.1, Add parameters to mmgr routines via a macro. +- Replaced mmgr funtions with macros to add caller func name + line #. +- This is done to help debug memory access issues, allocation issues, etc. + +#endif +v2.1.6.0, Interface for vertical output flip +- add new interface to enable vertical output flipping +- rename ia_css_output_config.enable_mirror + +#ifndef ISP2401 +v2.1.6.1, Effective res on pipe +#else +v2.1.6.2 (2 changes parallel), Effective res on pipe +#endif +- Added input_effective_res to struct ia_css_pipe_config in ia_css_pipe_public.h. + +#ifndef ISP2401 +v2.1.6.2, CSS-API version file generated from individual changes +#else +v2.1.6.3 (2 changes parallel), CSS-API version file generated from individual changes +#endif +- Avoid merge-conflicts by generating version file from individual CSS-API changes. +- Parallel CSS-API changes can map to the same version number after this change. +- Version numbers for a change could increase due to parallel changes being merged. +- The version number would not decrease for a change. + +#ifndef ISP2401 +v2.1.6.5 (2 changes parallel), Add SP FW error event +#else +v2.1.6.6 (4 changes parallel), Add SP FW error event +#endif +- Added FW error event. This gets raised when the SP FW runs into an +- error situation from which it cannot recover. + +#ifndef ISP2401 +v2.1.6.5 (2 changes parallel), expose bnr FF enable bits in bnr public API +#else +v2.1.6.6 (4 changes parallel), expose bnr FF enable bits in bnr public API +#endif +- Added ff enable bits to bnr_public_config_dn_detect_ctrl_config_t struct + +#ifndef ISP2401 +v2.1.6.5 (2 changes parallel), ISP configuration per pipe +#else +v2.1.6.6 (4 changes parallel), ISP configuration per pipe +#endif +- Added ISP configuration per pipe support: p_isp_config field in +- struct ia_css_pipe_config and ia_css_pipe_set_isp_config_on_pipe +- and ia_css_pipe_set_isp_config functions + +#ifndef ISP2401 +v2.1.7.0, removed css_version.h +#else +v2.1.7.0 (2 changes parallel), removed css_version.h +#endif +- Removed css_version.h that was used for versioning in manual (non-CI) releases. + +#ifndef ISP2401 +v2.1.7.1, Add helpers (get and set) for ISP cfg per pipe +#else +v2.1.7.2 (2 changes parallel), Add helpers (get and set) for ISP cfg per pipe +#endif +- Add helpers (get and set) for ISP configuration per pipe + +#ifndef ISP2401 +v2.1.7.2, Add feature to lock all RAW buffers +#else +v2.1.7.3 (2 changes parallel), Add feature to lock all RAW buffers +#endif +- This API change adds a boolean flag (lock_all) in the stream_config struct. +- If this flag is set to true, then all frames will be locked if locking is +- enabled. By default this flag is set to false. +- When this flag is false, then only buffers that are sent to the preview pipe +- will be locked. If continuous viewfinder is disabled, the flag should be set +- to true. + +#ifndef ISP2401 +v2.1.8.0 (2 changes parallel), Various changes to support ACC configuration per pipe +#else +v2.1.8.0 (4 changes parallel), Various changes to support ACC configuration per pipe +#endif +- Add ia_css_pipe_get_isp_config() +- Remove ia_css_pipe_set_isp_config_on_pipe (duplicated +- by ia_css_pipe_set_isp_config) +- Add isp configuration as parameter for +- ia_css_pipe_set_isp_config +- Remove ia_css_pipe_isp_config_set() +- Remove ia_css_pipe_isp_config_get() + +#ifndef ISP2401 +v2.1.8.2 (2 changes parallel), Added member num_invalid_frames to ia_css_pipe_info structure. +#else +v2.1.8.3 (4 changes parallel), Added member num_invalid_frames to ia_css_pipe_info structure. +#endif +- Added member num_invalid_frames to ia_css_pipe_info structure. +- This helps the driver make sure that the first valid output +- frame goes into the first user-supplied output buffer. + +#ifndef ISP2401 +v2.1.8.4 (2 changes parallel), ISYS EOF timestamp for output buffers +#else +v2.1.8.5 (4 changes parallel), ISYS EOF timestamp for output buffers +#endif +- driver gets EOF timer to every out frame . ia_css_buffer modified to accomodate same. + +#ifndef ISP2401 +v2.1.8.4 (4 changes parallel), display_config +#else +v2.1.8.5 (6 changes parallel), display_config +#endif +- Added formats- and output config parameters for configuration of the (optional) display output. + +#ifndef ISP2401 +v2.1.8.4 (2 changes parallel), Adding zoom region parameters to CSS API +#else +v2.1.8.5 (4 changes parallel), Adding zoom region parameters to CSS API +#endif +- Adding ia_css_point and ia_css_region structures to css-api. +- Adding zoom_region(type ia_css_region) parameter to ia_css_dz_config structure. +- By using this user can do the zoom based on zoom region and +- the center of the zoom region is not restricted at the center of the input frame. + +#ifndef ISP2401 +v2.1.8.6 (1 changes parallel), Add new ia_css_fw_warning type +#else +v2.1.8.7 (3 changes parallel), Add new ia_css_fw_warning type +#endif +- Add IA_CSS_FW_WARNING_TAG_EXP_ID_FAILED enum to ia_css_fw_warning type +- Extend sp_warning() with exp_id parameter + +#ifndef ISP2401 +v2.1.8.6 (1 changes parallel), Add includes in GC, GC2 kernel interface files +#else +v2.1.8.7 (3 changes parallel), Add includes in GC, GC2 kernel interface files +#endif +- add ia_css_ctc_types.h includes in ia_css_gc_types.h and ia_css_gc2_types.h. Needed to get ia_css_vamem_type. + +#ifndef ISP2401 +v2.1.9.0 (1 changes parallel), Introduce sp assert event. +#else +v2.1.9.0 (3 changes parallel), Introduce sp assert event. +#endif +- Add IA_CSS_EVENT_TYPE_FW_ASSERT. The FW sends the event in case an assert goes off. + +#ifndef ISP2401 +v2.1.9.1 (1 changes parallel), Exclude driver part from ia_css_buffer.h as it is also used by SP +#else +v2.1.9.2 (3 changes parallel), Exclude driver part from ia_css_buffer.h as it is also used by SP +#endif +- Excluded driver part of the interface from SP/ISP code +- Driver I/F is not affected + +#ifndef ISP2401 +v2.1.9.2, added IA_CSS_EVENT_TYPE_TIMER +#else +v2.1.9.3 (2 changes parallel), added IA_CSS_EVENT_TYPE_TIMER +#endif +- Added a new event called IA_CSS_EVENT_TYPE_TIMER + +#ifndef ISP2401 +v2.1.10.0 (4 changes parallel), Add a flag "enable_dpc" to "struct ia_css_pipe_config" +#else +v2.1.10.0 (6 changes parallel), Add a flag "enable_dpc" to "struct ia_css_pipe_config" +#endif +- Add a flag "enable_dpc" to "struct ia_css_pipe_config" + +#ifndef ISP2401 +v2.1.10.6 (6 changes parallel), change the pipe version type from integer to enum +#else +v2.1.10.8 (9 changes parallel), change the pipe version type from integer to enum +#endif +- add new enum to enumerate ISP pipe version +- change the pipe version type in pipe_config from integer to enum + +#ifndef ISP2401 +v2.1.13.0 (8 changes parallel), Stop Support for Skycam B0 +#else +v2.1.14.0 (12 changes parallel), Stop Support for Skycam B0 +#endif +- Remove a few pre-processor defines for Skycam B0/C0 as support + +#ifndef ISP2401 +v2.1.14.0 (24 changes parallel), change the pipe version type from integer to enum +#else +v2.1.15.0 (28 changes parallel), change the pipe version type from integer to enum +#endif +- remove the temporary workaround for backward compatability + +#ifndef ISP2401 +v2.1.14.0 (13 changes parallel), expose_gamma_enable_option +#else +v2.1.15.0 (17 changes parallel), expose_gamma_enable_option +#endif +- added enable param to gamma_corr_public_config +- added documentation to rgbpp_public.h + +#ifndef ISP2401 +v2.1.14.0 (12 changes parallel), Remove deprecated FW_ERROR event. +#else +v2.1.15.0 (16 changes parallel), Remove deprecated FW_ERROR event. +#endif +- Remove code for deprecated FW_ERROR event. + +#ifndef ISP2401 +v2.1.14.3 (5 changes parallel), fix IEFD's puclic API types +#else +v2.1.15.5 (8 changes parallel), fix IEFD's puclic API types +#endif +- fix IEFD public API members types: rad_cu6_x1,rad_cu_unsharp_x1 & unsharp_amount + +#ifndef ISP2401 +v2.1.14.3 (5 changes parallel), Add IA_CSS_FW_WARNING_FRAME_PARAM_MISMATCH +#else +v2.1.15.5 (8 changes parallel), Add IA_CSS_FW_WARNING_FRAME_PARAM_MISMATCH +#endif +- Add IA_CSS_FW_WARNING_FRAME_PARAM_MISMATCH enum to ia_css_fw_warning type + +#ifndef ISP2401 +v2.1.14.4 (5 changes parallel), new API getter functions for gdc in buffer information +#else +v2.1.15.8 (11 changes parallel), add_flag_to_disable_continous_viewfinder +- add a new flag in stream_config to disable continuous viewfinder +- in ZSL use case. + +v2.1.16.0 (8 changes parallel), revert ia_css_skc_dvs_statistics field size change +- Reverted field size change, change was not ready for driver yet. + +v2.1.17.0 (7 changes parallel), change CSS API to fix the shading correction off-center issue +- update the ia_css_shading_info structure in ia_css_types.h + +v2.1.17.0 (32 changes parallel), add_flag_to_disable_continous_viewfinder_part2 +- remove the old interfaces + +v2.1.17.4 (8 changes parallel), Added public interface for setting the scaler LUT. +- Added the public struct to output system and modified the global config struct. + +v2.1.17.5 (7 changes parallel), Add parameters for new TNR3 component +- Add new parameters for new TNR3 component + +v2.1.17.6 (9 changes parallel), Update skycam DPC_MAX_NUMBER_OF_DP +- Automated tooling requires an API change request +- This change changes the implementation of #define DPC_MAX_NUMBER_OF_DP +- it now returns a different number + +v2.1.17.6 (8 changes parallel), Return an error when both DPC and BDS are enabled in a pipe config +- Return an error when both DPC and BDS are enabled in a pipe config + +v2.1.17.6 (9 changes parallel), new API getter functions for gdc in buffer information +#endif +- ia_css_pipe_get_dvs_filter() added +- ia_css_pipe_get_gdc_in_buffer_info() added + +#ifndef ISP2401 +v2.1.14.5 (8 changes parallel), Update CNR2 ineffective values +#else +v2.1.17.7 (12 changes parallel), Update CNR2 ineffective values +#endif +- Fixed Incorrect ineffective values listed in ia_css_cnr_config +- Correct Ineffective value is 8191 + +#ifndef ISP2401 +v2.1.14.5 (8 changes parallel), af_roi_api +#else +v2.1.17.7 (12 changes parallel), af_roi_api +#endif +- added a new function to set AF ROI ia_css_set_af_roi +- added a new struct ia_css_s3a_roi_offset + +#ifndef ISP2401 +v2.1.14.5 (8 changes parallel), remove x_y_end_from_ae_and_awb +#else +v2.1.17.7 (12 changes parallel), Enlarge AF AWB_FR stats buffers +- Enlarge AF and AWB_FR stats buffers to support max grid width per stripe as oppose to per frame + +v2.1.17.7 (12 changes parallel), remove x_y_end_from_ae_and_awb +#endif +- added a flag to prepare removal of x_end and y_end from ae grid public config +- added a flag to prepare removal of x_end and y_end from awb grid public config + +#ifndef ISP2401 +v2.1.14.5 (4 changes parallel), Added public interface for setting the scaler LUT. +- Added the public struct to output system and modified the global config struct. +#else +v2.1.17.8 (5 changes parallel) +- added input_yuv , input_raw to ia_css_binary_info.enable +- struct, these attributes were always there but not saved +- in the binary_info struct +#endif + +#ifndef ISP2401 +v2.1.14.6 (8 changes parallel), add_flag_to_disable_continous_viewfinder +- add a new flag in stream_config to disable continuous viewfinder +- in ZSL use case. +#else +v2.1.17.9 (6 changes parallel), cleanup_awb_ae_rgb_integration_flags +- this change only cleans up an approved api CR see wikis below +#endif + +#ifndef ISP2401 +v2.1.14.6 (8 changes parallel), Enlarge AF AWB_FR stats buffers +- Enlarge AF and AWB_FR stats buffers to support max grid width per stripe as oppose to per frame +#else +v2.1.17.10 (6 changes parallel), output_system_input_resolution +- adedd gdc_output_system_in_resolution to pipe config struct +#endif + +#ifndef ISP2401 +v2.1.14.8 (6 changes parallel), pipe config option for vf output bci mode downscaling +#else +v2.1.17.10 (5 changes parallel), Per pipe DPC configuration is added to ia_css_isp_parameters +- Per pipe DPC configuration is added to ia_css_isp_parameters + +v2.1.17.10 (10 changes parallel), pipe config option for vf output bci mode downscaling +#endif +- vf downscaling using yuv_scale binary. + +#ifndef ISP2401 +v2.1.14.10 (7 changes parallel), Add scale mode GDC V2 LUT to CSS API +#else +v2.1.17.12 (11 changes parallel), Add scale mode GDC V2 LUT to CSS API +#endif +- Allow client to set global LUT for gdc v2 (First step in this change. See wiki page for more details) + +#ifndef ISP2401 +v2.1.14.10 (8 changes parallel), Include added to type-support.h. +#else +v2.1.17.12 (12 changes parallel), Include added to type-support.h. +#endif +- Include of hive/cell_support.h was added to type-support.h, in order to +- have access to define HAVE_STDINT. + +#ifndef ISP2401 +v2.1.14.11 (7 changes parallel), Pipe configuration to enable BLI mode downscaling for +#else +v2.1.17.13 (11 changes parallel), Pipe configuration to enable BLI mode downscaling for +#endif +- BLI mode downscaling for capture post-processing + +#ifndef ISP2401 +v2.1.14.14 (9 changes parallel), Fix copyright headers (no functional change) +#else +v2.1.17.15 (8 changes parallel), Add copyright headers to css files +- Add copyright headers to css API files + +v2.1.17.15 (8 changes parallel), add copyright header to include files +- add copyright header to include files + +v2.1.17.15 (8 changes parallel), add copyright header to isp files +- add copyright header to isp files + +v2.1.17.15 (8 changes parallel), add copyright header to refactored code +- add copyright header to refactored code +- (base, camera, runtime directories) + +v2.1.17.16 (13 changes parallel), Fix copyright headers (no functional change) +#endif +- No functional change; only fixes copyright headers + +#ifndef ISP2401 +v2.1.14.14 (6 changes parallel), Remove continuous mode special case handling in ia_css_pipe_set_isp_config +#else +v2.1.17.16 (10 changes parallel), Remove continuous mode special case handling in ia_css_pipe_set_isp_config +#endif +- For continuous mode isp_config was being send to all pipes, +- even though API ia_css_pipe_set_isp_config is for single pipe +- Removed incorrect case + +#ifndef ISP2401 +v2.1.14.14 (6 changes parallel), DVS statistics grid produced by accelerator +#else +v2.1.17.16 (5 changes parallel), Added documentation to formats_config header file +- Added description of ranges for full-range flag + +v2.1.17.16 (10 changes parallel), DVS statistics grid produced by accelerator +#endif +- Add DVS statistics produced by accelerator grid to pipe info +- Add ia_css_pipe_has_dvs_stats function + +#ifndef ISP2401 +v2.1.14.15 (7 changes parallel), cont_remove_x_y_end_from_ae_and_awb +#else +v2.1.17.17 (5 changes parallel), Provide the CSS interface to select the luma only binaries +- Add a flag "enable_luma_only" to "struct ia_css_pipe_config" + +v2.1.17.17 (11 changes parallel), cont_remove_x_y_end_from_ae_and_awb +#endif +- this patch doesn't introduce any new api change, it only fixes a recent +- api merged change (#31938) , in order to have success CI i had to upload an api change request + +#ifndef ISP2401 +v2.1.14.17 (6 changes parallel), Add XNR3 blending strength to kernel interface +- Added a blending strength field to the XNR3 kernel interface to add +- support for blending. +#else +v2.1.17.17 (10 changes parallel), GAC state dump for debug +- added ia_css_dump_gac_state function + +v2.1.17.18 (23 changes parallel), output_format_nv12_16 +- added new output fromat nv12_16 +#endif + +#ifndef ISP2401 +v2.1.14.18 (22 changes parallel), eliminate two_pixels_per_clock field +#else +v2.1.17.18 (4 changes parallel), Remove author details from SKC src code +- remove author details from skc src code + +v2.1.17.19 (26 changes parallel), eliminate two_pixels_per_clock field +#endif +- remove obsolete field two_pixels_per_clock + +#ifndef ISP2401 +v2.1.14.19 (3 changes parallel), Fix copyright headers (no functional change) +#else +v2.1.17.20 (7 changes parallel), Fix copyright headers (no functional change) +#endif +- No functional change; only fixes copyright headers + +#ifndef ISP2401 +v2.1.14.21 (3 changes parallel), ia_css_skc_dvs_statistics field size change +- ia_css_skc_dvs_statistics field size change +#else +v2.1.17.20 (11 changes parallel), Add XNR3 blending strength to kernel interface +- Added a blending strength field to the XNR3 kernel interface to add +- support for blending. +#endif + +#ifndef ISP2401 +v2.1.15.0 (3 changes parallel), revert ia_css_skc_dvs_statistics field size change +- Reverted field size change, change was not ready for driver yet. +#else +v2.1.17.21 (24 changes parallel), Add N_CSS_PRBS_IDS and N_CSS_TPG_IDS +- Add N_CSS_PRBS_IDS to reflect the number of ia_css_prbs_id enum +- Add N_CSS_TPG_IDS to reflect the number of ia_css_tpg_id enum +#endif + +#ifndef ISP2401 +v2.1.15.2 (3 changes parallel), Return an error when both DPC and BDS are enabled in a pipe config +- Return an error when both DPC and BDS are enabled in a pipe config +#else +v2.1.17.23 (8 changes parallel), ia_css_skc_dvs_statistics field size change +- ia_css_skc_dvs_statistics field size change +#endif + +#ifndef ISP2401 +v2.1.15.3 (2 changes parallel), Update skycam DPC_MAX_NUMBER_OF_DP +- Automated tooling requires an API change request +- This change changes the implementation of #define DPC_MAX_NUMBER_OF_DP +- it now returns a different number +#else +v2.1.19.0 (6 changes parallel) +- Added code to calculate input_res using the Windows specification of binning +#endif + +#ifndef ISP2401 +v2.1.15.3 (18 changes parallel), output_format_nv12_16 +- added new output fromat nv12_16 +#else +v2.1.20.0 (7 changes parallel), Add interface to select TNR enabled binaries +- Add a bool "enable_tnr" to "struct ia_css_pipe_config" + +v2.1.20.0 (6 changes parallel), OSYS & GDC Debug dump function addition +- add GDC state dump function +- add OSYS state dump function + +v2.1.20.4 (7 changes parallel), Add ref_buf_select parameter for TNR3 to kernel interface +- Added a ref_buf_select parameter to the TNR3 kernel interface to add +- support for multiple reference buffers. + +v2.1.20.4 (6 changes parallel), DVS MAX grid dimensions to cover maximal resolution +- rename DVS_TABLE_HEIGHT/WIDTH to MAX_DVS_COORDS_TABLE_HEIGHT/WIDTH +- modify value of the above macros to cover max resolution + +v2.1.20.5 (54 changes parallel), add input feeder calculations getter +- add input_feeder_config public struct +- add get_input_feeder_config getter + +v2.1.20.5 (4 changes parallel), Enable runtime updating mapped args for QoS extension pipe +- added ia_css_pipe_update_qos_ext_mapped_arg() + +v2.1.20.7 (77 changes parallel), Add parameters to CPU routines via a macro. +- Replaced CPU memory allocation functions with macros to add caller func name + line number. +- This is done to help debug memory access issues, allocation issues, etc. +- Changed API: only ia_css_env.h + +v2.1.20.7 (2 changes parallel), Frame format override +- Added a function call to the pipe interface for overriding +- the frame format as set in the pipe. +- This is an optional interface that can be used under +- some strict conditions. + +v2.1.20.7 (2 changes parallel), Output_system_in_res Information +- Output_system_in_res_info field added to pipe_info struct + +v2.1.20.8, Temprarily disable memory debug features for SVOS. +- Temporary commented out the additions to allow SKC testing till root cause found +- Changed files ia_css_env.h and sh_css.c. + +v2.1.20.9, Enable ISP 2.7 naming +- Add IA_CSS_PIPE_VERSION_2_7 to enum ia_css_pipe_version +- Add #define SH_CSS_ISP_PIPE_VERSION_2_7 4 +#endif + +*/ + +#endif /*__CSS_API_VERSION_H*/ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_trace.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_trace.h new file mode 100644 index 0000000000000000000000000000000000000000..01f7c33b5b407b8e535f3166a4adbc4619eccf8a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/css_trace.h @@ -0,0 +1,388 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __CSS_TRACE_H_ +#define __CSS_TRACE_H_ + +#include +#ifdef ISP2401 +#include "sh_css_internal.h" /* for SH_CSS_MAX_SP_THREADS */ +#endif + +/* + structs and constants for tracing +*/ + +/* one tracer item: major, minor and counter. The counter value can be used for GP data */ +struct trace_item_t { + uint8_t major; + uint8_t minor; + uint16_t counter; +}; + +#ifdef ISP2401 +#define MAX_SCRATCH_DATA 4 +#define MAX_CMD_DATA 2 + +#endif +/* trace header: holds the version and the topology of the tracer. */ +struct trace_header_t { +#ifndef ISP2401 + /* 1st dword */ +#else + /* 1st dword: descriptor */ +#endif + uint8_t version; + uint8_t max_threads; + uint16_t max_tracer_points; +#ifdef ISP2401 + /* 2nd field: command + data */ +#endif + /* 2nd dword */ + uint32_t command; + /* 3rd & 4th dword */ +#ifndef ISP2401 + uint32_t data[2]; +#else + uint32_t data[MAX_CMD_DATA]; + /* 3rd field: debug pointer */ +#endif + /* 5th & 6th dword: debug pointer mechanism */ + uint32_t debug_ptr_signature; + uint32_t debug_ptr_value; +#ifdef ISP2401 + /* Rest of the header: status & scratch data */ + uint8_t thr_status_byte[SH_CSS_MAX_SP_THREADS]; + uint16_t thr_status_word[SH_CSS_MAX_SP_THREADS]; + uint32_t thr_status_dword[SH_CSS_MAX_SP_THREADS]; + uint32_t scratch_debug[MAX_SCRATCH_DATA]; +#endif +}; + +#ifndef ISP2401 +#define TRACER_VER 2 +#else +/* offsets for master_port read/write */ +#define HDR_HDR_OFFSET 0 /* offset of the header */ +#define HDR_COMMAND_OFFSET offsetof(struct trace_header_t, command) +#define HDR_DATA_OFFSET offsetof(struct trace_header_t, data) +#define HDR_DEBUG_SIGNATURE_OFFSET offsetof(struct trace_header_t, debug_ptr_signature) +#define HDR_DEBUG_POINTER_OFFSET offsetof(struct trace_header_t, debug_ptr_value) +#define HDR_STATUS_OFFSET offsetof(struct trace_header_t, thr_status_byte) +#define HDR_STATUS_OFFSET_BYTE offsetof(struct trace_header_t, thr_status_byte) +#define HDR_STATUS_OFFSET_WORD offsetof(struct trace_header_t, thr_status_word) +#define HDR_STATUS_OFFSET_DWORD offsetof(struct trace_header_t, thr_status_dword) +#define HDR_STATUS_OFFSET_SCRATCH offsetof(struct trace_header_t, scratch_debug) + +/* +Trace version history: + 1: initial version, hdr = descr, command & ptr. + 2: added ISP + 24-bit fields. + 3: added thread ID. + 4: added status in header. +*/ +#define TRACER_VER 4 + +#endif +#define TRACE_BUFF_ADDR 0xA000 +#define TRACE_BUFF_SIZE 0x1000 /* 4K allocated */ + +#define TRACE_ENABLE_SP0 0 +#define TRACE_ENABLE_SP1 0 +#define TRACE_ENABLE_ISP 0 + +#ifndef ISP2401 +typedef enum { +#else +enum TRACE_CORE_ID { +#endif + TRACE_SP0_ID, + TRACE_SP1_ID, + TRACE_ISP_ID +#ifndef ISP2401 +} TRACE_CORE_ID; +#else +}; +#endif + +/* TODO: add timing format? */ +#ifndef ISP2401 +typedef enum { + TRACE_DUMP_FORMAT_POINT, + TRACE_DUMP_FORMAT_VALUE24_HEX, + TRACE_DUMP_FORMAT_VALUE24_DEC, +#else +enum TRACE_DUMP_FORMAT { + TRACE_DUMP_FORMAT_POINT_NO_TID, + TRACE_DUMP_FORMAT_VALUE24, +#endif + TRACE_DUMP_FORMAT_VALUE24_TIMING, +#ifndef ISP2401 + TRACE_DUMP_FORMAT_VALUE24_TIMING_DELTA +} TRACE_DUMP_FORMAT; +#else + TRACE_DUMP_FORMAT_VALUE24_TIMING_DELTA, + TRACE_DUMP_FORMAT_POINT +}; +#endif + + +/* currently divided as follows:*/ +#if (TRACE_ENABLE_SP0 + TRACE_ENABLE_SP1 + TRACE_ENABLE_ISP == 3) +/* can be divided as needed */ +#define TRACE_SP0_SIZE (TRACE_BUFF_SIZE/4) +#define TRACE_SP1_SIZE (TRACE_BUFF_SIZE/4) +#define TRACE_ISP_SIZE (TRACE_BUFF_SIZE/2) +#elif (TRACE_ENABLE_SP0 + TRACE_ENABLE_SP1 + TRACE_ENABLE_ISP == 2) +#if TRACE_ENABLE_SP0 +#define TRACE_SP0_SIZE (TRACE_BUFF_SIZE/2) +#else +#define TRACE_SP0_SIZE (0) +#endif +#if TRACE_ENABLE_SP1 +#define TRACE_SP1_SIZE (TRACE_BUFF_SIZE/2) +#else +#define TRACE_SP1_SIZE (0) +#endif +#if TRACE_ENABLE_ISP +#define TRACE_ISP_SIZE (TRACE_BUFF_SIZE/2) +#else +#define TRACE_ISP_SIZE (0) +#endif +#elif (TRACE_ENABLE_SP0 + TRACE_ENABLE_SP1 + TRACE_ENABLE_ISP == 1) +#if TRACE_ENABLE_SP0 +#define TRACE_SP0_SIZE (TRACE_BUFF_SIZE) +#else +#define TRACE_SP0_SIZE (0) +#endif +#if TRACE_ENABLE_SP1 +#define TRACE_SP1_SIZE (TRACE_BUFF_SIZE) +#else +#define TRACE_SP1_SIZE (0) +#endif +#if TRACE_ENABLE_ISP +#define TRACE_ISP_SIZE (TRACE_BUFF_SIZE) +#else +#define TRACE_ISP_SIZE (0) +#endif +#else +#define TRACE_SP0_SIZE (0) +#define TRACE_SP1_SIZE (0) +#define TRACE_ISP_SIZE (0) +#endif + +#define TRACE_SP0_ADDR (TRACE_BUFF_ADDR) +#define TRACE_SP1_ADDR (TRACE_SP0_ADDR + TRACE_SP0_SIZE) +#define TRACE_ISP_ADDR (TRACE_SP1_ADDR + TRACE_SP1_SIZE) + +/* check if it's a legal division */ +#if (TRACE_BUFF_SIZE < TRACE_SP0_SIZE + TRACE_SP1_SIZE + TRACE_ISP_SIZE) +#error trace sizes are not divided correctly and are above limit +#endif + +#define TRACE_SP0_HEADER_ADDR (TRACE_SP0_ADDR) +#define TRACE_SP0_HEADER_SIZE (sizeof(struct trace_header_t)) +#ifndef ISP2401 +#define TRACE_SP0_ITEM_SIZE (sizeof(struct trace_item_t)) +#define TRACE_SP0_DATA_ADDR (TRACE_SP0_HEADER_ADDR + TRACE_SP0_HEADER_SIZE) +#define TRACE_SP0_DATA_SIZE (TRACE_SP0_SIZE - TRACE_SP0_HEADER_SIZE) +#define TRACE_SP0_MAX_POINTS (TRACE_SP0_DATA_SIZE / TRACE_SP0_ITEM_SIZE) +#else +#define TRACE_SP0_ITEM_SIZE (sizeof(struct trace_item_t)) +#define TRACE_SP0_DATA_ADDR (TRACE_SP0_HEADER_ADDR + TRACE_SP0_HEADER_SIZE) +#define TRACE_SP0_DATA_SIZE (TRACE_SP0_SIZE - TRACE_SP0_HEADER_SIZE) +#define TRACE_SP0_MAX_POINTS (TRACE_SP0_DATA_SIZE / TRACE_SP0_ITEM_SIZE) +#endif + +#define TRACE_SP1_HEADER_ADDR (TRACE_SP1_ADDR) +#define TRACE_SP1_HEADER_SIZE (sizeof(struct trace_header_t)) +#ifndef ISP2401 +#define TRACE_SP1_ITEM_SIZE (sizeof(struct trace_item_t)) +#define TRACE_SP1_DATA_ADDR (TRACE_SP1_HEADER_ADDR + TRACE_SP1_HEADER_SIZE) +#define TRACE_SP1_DATA_SIZE (TRACE_SP1_SIZE - TRACE_SP1_HEADER_SIZE) +#define TRACE_SP1_MAX_POINTS (TRACE_SP1_DATA_SIZE / TRACE_SP1_ITEM_SIZE) +#else +#define TRACE_SP1_ITEM_SIZE (sizeof(struct trace_item_t)) +#define TRACE_SP1_DATA_ADDR (TRACE_SP1_HEADER_ADDR + TRACE_SP1_HEADER_SIZE) +#define TRACE_SP1_DATA_SIZE (TRACE_SP1_SIZE - TRACE_SP1_HEADER_SIZE) +#define TRACE_SP1_MAX_POINTS (TRACE_SP1_DATA_SIZE / TRACE_SP1_ITEM_SIZE) +#endif + +#define TRACE_ISP_HEADER_ADDR (TRACE_ISP_ADDR) +#define TRACE_ISP_HEADER_SIZE (sizeof(struct trace_header_t)) +#ifndef ISP2401 +#define TRACE_ISP_ITEM_SIZE (sizeof(struct trace_item_t)) +#define TRACE_ISP_DATA_ADDR (TRACE_ISP_HEADER_ADDR + TRACE_ISP_HEADER_SIZE) +#define TRACE_ISP_DATA_SIZE (TRACE_ISP_SIZE - TRACE_ISP_HEADER_SIZE) +#define TRACE_ISP_MAX_POINTS (TRACE_ISP_DATA_SIZE / TRACE_ISP_ITEM_SIZE) + +#else +#define TRACE_ISP_ITEM_SIZE (sizeof(struct trace_item_t)) +#define TRACE_ISP_DATA_ADDR (TRACE_ISP_HEADER_ADDR + TRACE_ISP_HEADER_SIZE) +#define TRACE_ISP_DATA_SIZE (TRACE_ISP_SIZE - TRACE_ISP_HEADER_SIZE) +#define TRACE_ISP_MAX_POINTS (TRACE_ISP_DATA_SIZE / TRACE_ISP_ITEM_SIZE) +#endif + +#ifndef ISP2401 +/* offsets for master_port read/write */ +#define HDR_HDR_OFFSET 0 /* offset of the header */ +#define HDR_COMMAND_OFFSET 4 /* offset of the command */ +#define HDR_DATA_OFFSET 8 /* offset of the command data */ +#define HDR_DEBUG_SIGNATURE_OFFSET 16 /* offset of the param debug signature in trace_header_t */ +#define HDR_DEBUG_POINTER_OFFSET 20 /* offset of the param debug pointer in trace_header_t */ +#endif + +/* common majors */ +#ifdef ISP2401 +/* SP0 */ +#endif +#define MAJOR_MAIN 1 +#define MAJOR_ISP_STAGE_ENTRY 2 +#define MAJOR_DMA_PRXY 3 +#define MAJOR_START_ISP 4 +#ifdef ISP2401 +/* SP1 */ +#define MAJOR_OBSERVER_ISP0_EVENT 21 +#define MAJOR_OBSERVER_OUTPUT_FORM_EVENT 22 +#define MAJOR_OBSERVER_OUTPUT_SCAL_EVENT 23 +#define MAJOR_OBSERVER_IF_ACK 24 +#define MAJOR_OBSERVER_SP0_EVENT 25 +#define MAJOR_OBSERVER_SP_TERMINATE_EVENT 26 +#define MAJOR_OBSERVER_DMA_ACK 27 +#define MAJOR_OBSERVER_ACC_ACK 28 +#endif + +#define DEBUG_PTR_SIGNATURE 0xABCD /* signature for the debug parameter pointer */ + +/* command codes (1st byte) */ +typedef enum { + CMD_SET_ONE_MAJOR = 1, /* mask in one major. 2nd byte in the command is the major code */ + CMD_UNSET_ONE_MAJOR = 2, /* mask out one major. 2nd byte in the command is the major code */ + CMD_SET_ALL_MAJORS = 3, /* set the major print mask. the full mask is in the data DWORD */ + CMD_SET_VERBOSITY = 4 /* set verbosity level */ +} DBG_commands; + +/* command signature */ +#define CMD_SIGNATURE 0xAABBCC00 + +/* shared macros in traces infrastructure */ +/* increment the pointer cyclicly */ +#define DBG_NEXT_ITEM(x, max_items) (((x+1) >= max_items) ? 0 : x+1) +#define DBG_PREV_ITEM(x, max_items) ((x) ? x-1 : max_items-1) + +#define FIELD_MASK(width) (((1 << (width)) - 1)) +#define FIELD_PACK(value,mask,offset) (((value) & (mask)) << (offset)) +#define FIELD_UNPACK(value,mask,offset) (((value) >> (offset)) & (mask)) + + +#define FIELD_VALUE_OFFSET (0) +#define FIELD_VALUE_WIDTH (16) +#define FIELD_VALUE_MASK FIELD_MASK(FIELD_VALUE_WIDTH) +#define FIELD_VALUE_PACK(f) FIELD_PACK(f,FIELD_VALUE_MASK,FIELD_VALUE_OFFSET) +#ifndef ISP2401 +#define FIELD_VALUE_UNPACK(f) FIELD_UNPACK(f,FIELD_VALUE_MASK,FIELD_VALUE_OFFSET) +#else +#define FIELD_VALUE_UNPACK(f) FIELD_UNPACK(f,FIELD_VALUE_MASK,FIELD_VALUE_OFFSET) +#endif + +#define FIELD_MINOR_OFFSET (FIELD_VALUE_OFFSET + FIELD_VALUE_WIDTH) +#define FIELD_MINOR_WIDTH (8) +#define FIELD_MINOR_MASK FIELD_MASK(FIELD_MINOR_WIDTH) +#define FIELD_MINOR_PACK(f) FIELD_PACK(f,FIELD_MINOR_MASK,FIELD_MINOR_OFFSET) +#ifndef ISP2401 +#define FIELD_MINOR_UNPACK(f) FIELD_UNPACK(f,FIELD_MINOR_MASK,FIELD_MINOR_OFFSET) +#else +#define FIELD_MINOR_UNPACK(f) FIELD_UNPACK(f,FIELD_MINOR_MASK,FIELD_MINOR_OFFSET) +#endif + +#define FIELD_MAJOR_OFFSET (FIELD_MINOR_OFFSET + FIELD_MINOR_WIDTH) +#define FIELD_MAJOR_WIDTH (5) +#define FIELD_MAJOR_MASK FIELD_MASK(FIELD_MAJOR_WIDTH) +#define FIELD_MAJOR_PACK(f) FIELD_PACK(f,FIELD_MAJOR_MASK,FIELD_MAJOR_OFFSET) +#ifndef ISP2401 +#define FIELD_MAJOR_UNPACK(f) FIELD_UNPACK(f,FIELD_MAJOR_MASK,FIELD_MAJOR_OFFSET) +#else +#define FIELD_MAJOR_UNPACK(f) FIELD_UNPACK(f,FIELD_MAJOR_MASK,FIELD_MAJOR_OFFSET) +#endif + +#ifndef ISP2401 +#define FIELD_FORMAT_OFFSET (FIELD_MAJOR_OFFSET + FIELD_MAJOR_WIDTH) +#define FIELD_FORMAT_WIDTH (3) +#define FIELD_FORMAT_MASK FIELD_MASK(FIELD_FORMAT_WIDTH) +#define FIELD_FORMAT_PACK(f) FIELD_PACK(f,FIELD_FORMAT_MASK,FIELD_FORMAT_OFFSET) +#define FIELD_FORMAT_UNPACK(f) FIELD_UNPACK(f,FIELD_FORMAT_MASK,FIELD_FORMAT_OFFSET) +#else +/* for quick traces - only insertion, compatible with the regular point */ +#define FIELD_FULL_MAJOR_WIDTH (8) +#define FIELD_FULL_MAJOR_MASK FIELD_MASK(FIELD_FULL_MAJOR_WIDTH) +#define FIELD_FULL_MAJOR_PACK(f) FIELD_PACK(f,FIELD_FULL_MAJOR_MASK,FIELD_MAJOR_OFFSET) + +/* The following 2 fields are used only when FIELD_TID value is 111b. + * it means we don't want to use thread id, but format. In this case, + * the last 2 MSB bits of the major field will indicates the format + */ +#define FIELD_MAJOR_W_FMT_OFFSET FIELD_MAJOR_OFFSET +#define FIELD_MAJOR_W_FMT_WIDTH (3) +#define FIELD_MAJOR_W_FMT_MASK FIELD_MASK(FIELD_MAJOR_W_FMT_WIDTH) +#define FIELD_MAJOR_W_FMT_PACK(f) FIELD_PACK(f,FIELD_MAJOR_W_FMT_MASK,FIELD_MAJOR_W_FMT_OFFSET) +#define FIELD_MAJOR_W_FMT_UNPACK(f) FIELD_UNPACK(f,FIELD_MAJOR_W_FMT_MASK,FIELD_MAJOR_W_FMT_OFFSET) + +#define FIELD_FORMAT_OFFSET (FIELD_MAJOR_OFFSET + FIELD_MAJOR_W_FMT_WIDTH) +#define FIELD_FORMAT_WIDTH (2) +#define FIELD_FORMAT_MASK FIELD_MASK(FIELD_MAJOR_W_FMT_WIDTH) +#define FIELD_FORMAT_PACK(f) FIELD_PACK(f,FIELD_FORMAT_MASK,FIELD_FORMAT_OFFSET) +#define FIELD_FORMAT_UNPACK(f) FIELD_UNPACK(f,FIELD_FORMAT_MASK,FIELD_FORMAT_OFFSET) + +#define FIELD_TID_SEL_FORMAT_PAT (7) + +#define FIELD_TID_OFFSET (FIELD_MAJOR_OFFSET + FIELD_MAJOR_WIDTH) +#define FIELD_TID_WIDTH (3) +#define FIELD_TID_MASK FIELD_MASK(FIELD_TID_WIDTH) +#define FIELD_TID_PACK(f) FIELD_PACK(f,FIELD_TID_MASK,FIELD_TID_OFFSET) +#define FIELD_TID_UNPACK(f) FIELD_UNPACK(f,FIELD_TID_MASK,FIELD_TID_OFFSET) +#endif + +#define FIELD_VALUE_24_OFFSET (0) +#define FIELD_VALUE_24_WIDTH (24) +#ifndef ISP2401 +#define FIELD_VALUE_24_MASK FIELD_MASK(FIELD_VALUE_24_WIDTH) +#else +#define FIELD_VALUE_24_MASK FIELD_MASK(FIELD_VALUE_24_WIDTH) +#endif +#define FIELD_VALUE_24_PACK(f) FIELD_PACK(f,FIELD_VALUE_24_MASK,FIELD_VALUE_24_OFFSET) +#define FIELD_VALUE_24_UNPACK(f) FIELD_UNPACK(f,FIELD_VALUE_24_MASK,FIELD_VALUE_24_OFFSET) + +#ifndef ISP2401 +#define PACK_TRACEPOINT(format,major, minor, value) \ + (FIELD_FORMAT_PACK(format) | FIELD_MAJOR_PACK(major) | FIELD_MINOR_PACK(minor) | FIELD_VALUE_PACK(value)) +#else +#define PACK_TRACEPOINT(tid, major, minor, value) \ + (FIELD_TID_PACK(tid) | FIELD_MAJOR_PACK(major) | FIELD_MINOR_PACK(minor) | FIELD_VALUE_PACK(value)) + +#define PACK_QUICK_TRACEPOINT(major, minor) \ + (FIELD_FULL_MAJOR_PACK(major) | FIELD_MINOR_PACK(minor)) + +#define PACK_FORMATTED_TRACEPOINT(format, major, minor, value) \ + (FIELD_TID_PACK(FIELD_TID_SEL_FORMAT_PAT) | FIELD_FORMAT_PACK(format) | FIELD_MAJOR_PACK(major) | FIELD_MINOR_PACK(minor) | FIELD_VALUE_PACK(value)) +#endif + +#ifndef ISP2401 +#define PACK_TRACE_VALUE24(format, major, value) \ + (FIELD_FORMAT_PACK(format) | FIELD_MAJOR_PACK(major) | FIELD_VALUE_24_PACK(value)) +#else +#define PACK_TRACE_VALUE24(major, value) \ + (FIELD_TID_PACK(FIELD_TID_SEL_FORMAT_PAT) | FIELD_MAJOR_PACK(major) | FIELD_VALUE_24_PACK(value)) +#endif + +#endif /* __CSS_TRACE_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/debug_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/debug_global.h new file mode 100644 index 0000000000000000000000000000000000000000..076c4ba761753b619ba7aba117afd9a43eb69cc7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/debug_global.h @@ -0,0 +1,83 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __DEBUG_GLOBAL_H_INCLUDED__ +#define __DEBUG_GLOBAL_H_INCLUDED__ + +#include + +#define DEBUG_BUF_SIZE 1024 +#define DEBUG_BUF_MASK (DEBUG_BUF_SIZE - 1) + +#define DEBUG_DATA_ENABLE_ADDR 0x00 +#define DEBUG_DATA_BUF_MODE_ADDR 0x04 +#define DEBUG_DATA_HEAD_ADDR 0x08 +#define DEBUG_DATA_TAIL_ADDR 0x0C +#define DEBUG_DATA_BUF_ADDR 0x10 + +#define DEBUG_DATA_ENABLE_DDR_ADDR 0x00 +#define DEBUG_DATA_BUF_MODE_DDR_ADDR HIVE_ISP_DDR_WORD_BYTES +#define DEBUG_DATA_HEAD_DDR_ADDR (2 * HIVE_ISP_DDR_WORD_BYTES) +#define DEBUG_DATA_TAIL_DDR_ADDR (3 * HIVE_ISP_DDR_WORD_BYTES) +#define DEBUG_DATA_BUF_DDR_ADDR (4 * HIVE_ISP_DDR_WORD_BYTES) + +#define DEBUG_BUFFER_ISP_DMEM_ADDR 0x0 + +/* + * Enable HAS_WATCHDOG_SP_THREAD_DEBUG for additional SP thread and + * pipe information on watchdog output + * #undef HAS_WATCHDOG_SP_THREAD_DEBUG + * #define HAS_WATCHDOG_SP_THREAD_DEBUG + */ + + +/* + * The linear buffer mode will accept data until the first + * overflow and then stop accepting new data + * The circular buffer mode will accept if there is place + * and discard the data if the buffer is full + */ +typedef enum { + DEBUG_BUFFER_MODE_LINEAR = 0, + DEBUG_BUFFER_MODE_CIRCULAR, + N_DEBUG_BUFFER_MODE +} debug_buf_mode_t; + +struct debug_data_s { + uint32_t enable; + uint32_t bufmode; + uint32_t head; + uint32_t tail; + uint32_t buf[DEBUG_BUF_SIZE]; +}; + +/* thread.sp.c doesn't have a notion of HIVE_ISP_DDR_WORD_BYTES + still one point of control is needed for debug purposes */ + +#ifdef HIVE_ISP_DDR_WORD_BYTES +struct debug_data_ddr_s { + uint32_t enable; + int8_t padding1[HIVE_ISP_DDR_WORD_BYTES-sizeof(uint32_t)]; + uint32_t bufmode; + int8_t padding2[HIVE_ISP_DDR_WORD_BYTES-sizeof(uint32_t)]; + uint32_t head; + int8_t padding3[HIVE_ISP_DDR_WORD_BYTES-sizeof(uint32_t)]; + uint32_t tail; + int8_t padding4[HIVE_ISP_DDR_WORD_BYTES-sizeof(uint32_t)]; + uint32_t buf[DEBUG_BUF_SIZE]; +}; +#endif + +#endif /* __DEBUG_GLOBAL_H_INCLUDED__ */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/dma_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/dma_global.h new file mode 100644 index 0000000000000000000000000000000000000000..dff611014ba472d2d48fbf7452ba1c0f1737ab37 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/dma_global.h @@ -0,0 +1,307 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __DMA_GLOBAL_H_INCLUDED__ +#define __DMA_GLOBAL_H_INCLUDED__ + +#include + +#define IS_DMA_VERSION_2 + +#define HIVE_ISP_NUM_DMA_CONNS 3 +#define HIVE_ISP_NUM_DMA_CHANNELS 32 + +#define N_DMA_CHANNEL_ID HIVE_ISP_NUM_DMA_CHANNELS + +#include "dma_v2_defs.h" + +/* + * Command token bit mappings + * + * transfer / config + * param id[4] channel id[5] cmd id[6] + * | b14 .. b11 | b10 ... b6 | b5 ... b0 | + * + * + * fast transfer: + * height[5] width[8] width[8] channel id[5] cmd id[6] + * | b31 .. b26 | b25 .. b18 | b17 .. b11 | b10 ... b6 | b5 ... b0 | + * + */ + +#define _DMA_PACKING_SETUP_PARAM _DMA_V2_PACKING_SETUP_PARAM +#define _DMA_HEIGHT_PARAM _DMA_V2_HEIGHT_PARAM +#define _DMA_STRIDE_A_PARAM _DMA_V2_STRIDE_A_PARAM +#define _DMA_ELEM_CROPPING_A_PARAM _DMA_V2_ELEM_CROPPING_A_PARAM +#define _DMA_WIDTH_A_PARAM _DMA_V2_WIDTH_A_PARAM +#define _DMA_STRIDE_B_PARAM _DMA_V2_STRIDE_B_PARAM +#define _DMA_ELEM_CROPPING_B_PARAM _DMA_V2_ELEM_CROPPING_B_PARAM +#define _DMA_WIDTH_B_PARAM _DMA_V2_WIDTH_B_PARAM + +#define _DMA_ZERO_EXTEND _DMA_V2_ZERO_EXTEND +#define _DMA_SIGN_EXTEND _DMA_V2_SIGN_EXTEND + + +typedef unsigned int dma_channel; + +typedef enum { + dma_isp_to_bus_connection = HIVE_DMA_ISP_BUS_CONN, + dma_isp_to_ddr_connection = HIVE_DMA_ISP_DDR_CONN, + dma_bus_to_ddr_connection = HIVE_DMA_BUS_DDR_CONN, +} dma_connection; + +typedef enum { + dma_zero_extension = _DMA_ZERO_EXTEND, + dma_sign_extension = _DMA_SIGN_EXTEND +} dma_extension; + + +#define DMA_PROP_SHIFT(val, param) ((val) << _DMA_V2_ ## param ## _IDX) +#define DMA_PROP_MASK(param) ((1U << _DMA_V2_ ## param ## _BITS)-1) +#define DMA_PACK(val, param) DMA_PROP_SHIFT((val) & DMA_PROP_MASK(param), param) + +#define DMA_PACK_COMMAND(cmd) DMA_PACK(cmd, CMD) +#define DMA_PACK_CHANNEL(ch) DMA_PACK(ch, CHANNEL) +#define DMA_PACK_PARAM(par) DMA_PACK(par, PARAM) +#define DMA_PACK_EXTENSION(ext) DMA_PACK(ext, EXTENSION) +#define DMA_PACK_LEFT_CROPPING(lc) DMA_PACK(lc, LEFT_CROPPING) +#define DMA_PACK_WIDTH_A(w) DMA_PACK(w, SPEC_DEV_A_XB) +#define DMA_PACK_WIDTH_B(w) DMA_PACK(w, SPEC_DEV_B_XB) +#define DMA_PACK_HEIGHT(h) DMA_PACK(h, SPEC_YB) + +#define DMA_PACK_CMD_CHANNEL(cmd, ch) (DMA_PACK_COMMAND(cmd) | DMA_PACK_CHANNEL(ch)) +#define DMA_PACK_SETUP(conn, ext) ((conn) | DMA_PACK_EXTENSION(ext)) +#define DMA_PACK_CROP_ELEMS(elems, crop) ((elems) | DMA_PACK_LEFT_CROPPING(crop)) + +#define hive_dma_snd(dma_id, token) OP_std_snd(dma_id, (unsigned int)(token)) + +#define DMA_PACK_BLOCK_CMD(cmd, ch, width_a, width_b, height) \ + (DMA_PACK_COMMAND(cmd) | \ + DMA_PACK_CHANNEL(ch) | \ + DMA_PACK_WIDTH_A(width_a) | \ + DMA_PACK_WIDTH_B(width_b) | \ + DMA_PACK_HEIGHT(height)) + +#ifdef __HIVECC +#define hive_dma_move_data(dma_id, read, channel, addr_a, addr_b, to_is_var, from_is_var) \ +{ \ + /*hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(read?_DMA_V2_MOVE_B2A_COMMAND:_DMA_V2_MOVE_A2B_COMMAND, channel)); \ + hive_dma_snd(dma_id, read?(unsigned)(addr_b):(unsigned)(addr_a)); \ + hive_dma_snd(dma_id, read?(unsigned)(addr_a):(unsigned)(addr_b)); */\ + if (read) { \ + hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(_DMA_V2_MOVE_B2A_COMMAND, channel)); \ + hive_dma_snd(dma_id, (unsigned)(addr_b)); \ + hive_dma_snd(dma_id, (unsigned)(addr_a)); \ + } else { \ + hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(_DMA_V2_MOVE_A2B_COMMAND, channel)); \ + hive_dma_snd(dma_id, (unsigned)(addr_a)); \ + hive_dma_snd(dma_id, (unsigned)(addr_b)); \ + } \ +} +#define hive_dma_move_data_no_ack(dma_id, read, channel, addr_a, addr_b, to_is_var, from_is_var) \ +{ \ + /*hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(read?_DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND:_DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND, channel)); \ + hive_dma_snd(dma_id, read?(unsigned)(addr_b):(unsigned)(addr_a)); \ + hive_dma_snd(dma_id, read?(unsigned)(addr_a):(unsigned)(addr_b)); */\ + if (read) { \ + hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(_DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND, channel)); \ + hive_dma_snd(dma_id, (unsigned)(addr_b)); \ + hive_dma_snd(dma_id, (unsigned)(addr_a)); \ + } else { \ + hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(_DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND, channel)); \ + hive_dma_snd(dma_id, (unsigned)(addr_a)); \ + hive_dma_snd(dma_id, (unsigned)(addr_b)); \ + } \ +} +#else +#define hive_dma_move_data(dma_id, read, channel, addr_a, addr_b, to_is_var, from_is_var) \ +{ \ + hive_dma_snd(dma_id, DMA_PACK(_DMA_V2_SET_CRUN_COMMAND, CMD)); \ + hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(read?_DMA_V2_MOVE_B2A_COMMAND:_DMA_V2_MOVE_A2B_COMMAND, channel)); \ + hive_dma_snd(dma_id, read?(unsigned)(addr_b):(unsigned)(addr_a)); \ + hive_dma_snd(dma_id, read?(unsigned)(addr_a):(unsigned)(addr_b)); \ + hive_dma_snd(dma_id, to_is_var); \ + hive_dma_snd(dma_id, from_is_var); \ +} +#define hive_dma_move_data_no_ack(dma_id, read, channel, addr_a, addr_b, to_is_var, from_is_var) \ +{ \ + hive_dma_snd(dma_id, DMA_PACK(_DMA_V2_SET_CRUN_COMMAND, CMD)); \ + hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(read?_DMA_V2_NO_ACK_MOVE_B2A_NO_SYNC_CHK_COMMAND:_DMA_V2_NO_ACK_MOVE_A2B_NO_SYNC_CHK_COMMAND, channel)); \ + hive_dma_snd(dma_id, read?(unsigned)(addr_b):(unsigned)(addr_a)); \ + hive_dma_snd(dma_id, read?(unsigned)(addr_a):(unsigned)(addr_b)); \ + hive_dma_snd(dma_id, to_is_var); \ + hive_dma_snd(dma_id, from_is_var); \ +} +#endif + +#define hive_dma_move_b2a_data(dma_id, channel, to_addr, from_addr, to_is_var, from_is_var) \ +{ \ + hive_dma_move_data(dma_id, true, channel, to_addr, from_addr, to_is_var, from_is_var) \ +} + +#define hive_dma_move_a2b_data(dma_id, channel, from_addr, to_addr, from_is_var, to_is_var) \ +{ \ + hive_dma_move_data(dma_id, false, channel, from_addr, to_addr, from_is_var, to_is_var) \ +} + +#ifdef __HIVECC +#define hive_dma_set_data(dma_id, channel, address, value, is_var) \ +{ \ + hive_dma_snd(dma_id, _DMA_V2_PACK_CHANNEL_CMD(_DMA_V2_INIT_A_COMMAND, channel)); \ + hive_dma_snd(dma_id, value); \ + hive_dma_snd(dma_id, address); \ +} +#else +#define hive_dma_set_data(dma_id, channel, address, value, is_var) \ +{ \ + hive_dma_snd(dma_id, DMA_PACK(_DMA_V2_SET_CRUN_COMMAND, CMD)); \ + hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(_DMA_V2_INIT_A_COMMAND, channel)); \ + hive_dma_snd(dma_id, value); \ + hive_dma_snd(dma_id, address); \ + hive_dma_snd(dma_id, is_var); \ +} +#endif + +#define hive_dma_clear_data(dma_id, channel, address, is_var) hive_dma_set_data(dma_id, channel, address, 0, is_var) + +#define hive_dma_configure(dma_id, channel, connection, extension, height, \ + stride_A, elems_A, cropping_A, width_A, \ + stride_B, elems_B, cropping_B, width_B) \ +{ \ + hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(_DMA_V2_CONFIG_CHANNEL_COMMAND, channel)); \ + hive_dma_snd(dma_id, DMA_PACK_SETUP(connection, extension)); \ + hive_dma_snd(dma_id, stride_A); \ + hive_dma_snd(dma_id, DMA_PACK_CROP_ELEMS(elems_A, cropping_A)); \ + hive_dma_snd(dma_id, width_A); \ + hive_dma_snd(dma_id, stride_B); \ + hive_dma_snd(dma_id, DMA_PACK_CROP_ELEMS(elems_B, cropping_B)); \ + hive_dma_snd(dma_id, width_B); \ + hive_dma_snd(dma_id, height); \ +} + +#ifdef __HIVECC +/* If the command is "set" the 5th argument holds the value */ +#define hive_dma_execute(dma_id, channel, cmd, to_addr, from_addr_value, to_is_var, from_is_var) \ +{ \ + hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(cmd, channel)); \ + hive_dma_snd(dma_id, to_addr); \ + hive_dma_snd(dma_id, from_addr_value); \ +} +#else +#define hive_dma_execute(dma_id, channel, cmd, to_addr, from_addr_value, to_is_var, from_is_var) \ +{ \ + hive_dma_snd(dma_id, DMA_PACK(_DMA_V2_SET_CRUN_COMMAND, CMD)); \ + hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(cmd, channel)); \ + hive_dma_snd(dma_id, to_addr); \ + hive_dma_snd(dma_id, from_addr_value); \ + hive_dma_snd(dma_id, to_is_var); \ + if ((cmd & DMA_CLEAR_CMDBIT) == 0) { \ + hive_dma_snd(dma_id, from_is_var); \ + } \ +} +#endif + +#define hive_dma_configure_fast(dma_id, channel, connection, extension, elems_A, elems_B) \ +{ \ + hive_dma_snd(dma_id, DMA_PACK_CMD_CHANNEL(_DMA_V2_CONFIG_CHANNEL_COMMAND, channel)); \ + hive_dma_snd(dma_id, DMA_PACK_SETUP(connection, extension)); \ + hive_dma_snd(dma_id, 0); \ + hive_dma_snd(dma_id, DMA_PACK_CROP_ELEMS(elems_A, 0)); \ + hive_dma_snd(dma_id, 0); \ + hive_dma_snd(dma_id, 0); \ + hive_dma_snd(dma_id, DMA_PACK_CROP_ELEMS(elems_B, 0)); \ + hive_dma_snd(dma_id, 0); \ + hive_dma_snd(dma_id, 1); \ +} + +#define hive_dma_set_parameter(dma_id, channel, param, value) \ +{ \ + hive_dma_snd(dma_id, _DMA_V2_SET_CHANNEL_PARAM_COMMAND | DMA_PACK_CHANNEL(channel) | DMA_PACK_PARAM(param)); \ + hive_dma_snd(dma_id, value); \ +} + +#define DMA_SPECIFIC_CMDBIT 0x01 +#define DMA_CHECK_CMDBIT 0x02 +#define DMA_RW_CMDBIT 0x04 +#define DMA_CLEAR_CMDBIT 0x08 +#define DMA_ACK_CMDBIT 0x10 +#define DMA_CFG_CMDBIT 0x20 +#define DMA_PARAM_CMDBIT 0x01 + +/* Write complete check not necessary if there's no ack */ +#define DMA_NOACK_CMD (DMA_ACK_CMDBIT | DMA_CHECK_CMDBIT) +#define DMA_CFG_CMD (DMA_CFG_CMDBIT) +#define DMA_CFGPARAM_CMD (DMA_CFG_CMDBIT | DMA_PARAM_CMDBIT) + +#define DMA_CMD_NEEDS_ACK(cmd) ((cmd & DMA_NOACK_CMD) == 0) +#define DMA_CMD_IS_TRANSFER(cmd) ((cmd & DMA_CFG_CMDBIT) == 0) +#define DMA_CMD_IS_WR(cmd) ((cmd & DMA_RW_CMDBIT) != 0) +#define DMA_CMD_IS_RD(cmd) ((cmd & DMA_RW_CMDBIT) == 0) +#define DMA_CMD_IS_CLR(cmd) ((cmd & DMA_CLEAR_CMDBIT) != 0) +#define DMA_CMD_IS_CFG(cmd) ((cmd & DMA_CFG_CMDBIT) != 0) +#define DMA_CMD_IS_PARAMCFG(cmd) ((cmd & DMA_CFGPARAM_CMD) == DMA_CFGPARAM_CMD) + +/* As a matter of convention */ +#define DMA_TRANSFER_READ DMA_TRANSFER_B2A +#define DMA_TRANSFER_WRITE DMA_TRANSFER_A2B +/* store/load from the PoV of the system(memory) */ +#define DMA_TRANSFER_STORE DMA_TRANSFER_B2A +#define DMA_TRANSFER_LOAD DMA_TRANSFER_A2B +#define DMA_TRANSFER_CLEAR DMA_TRANSFER_CLEAR_A + +typedef enum { + DMA_TRANSFER_CLEAR_A = DMA_CLEAR_CMDBIT, /* 8 */ + DMA_TRANSFER_CLEAR_B = DMA_CLEAR_CMDBIT | DMA_RW_CMDBIT, /* 12 */ + DMA_TRANSFER_A2B = DMA_RW_CMDBIT, /* 4 */ + DMA_TRANSFER_B2A = 0, /* 0 */ + DMA_TRANSFER_CLEAR_A_NOACK = DMA_CLEAR_CMDBIT | DMA_NOACK_CMD, /* 26 */ + DMA_TRANSFER_CLEAR_B_NOACK = DMA_CLEAR_CMDBIT | DMA_RW_CMDBIT | DMA_NOACK_CMD, /* 30 */ + DMA_TRANSFER_A2B_NOACK = DMA_RW_CMDBIT | DMA_NOACK_CMD, /* 22 */ + DMA_TRANSFER_B2A_NOACK = DMA_NOACK_CMD, /* 18 */ + DMA_FASTTRANSFER_CLEAR_A = DMA_CLEAR_CMDBIT | DMA_SPECIFIC_CMDBIT, + DMA_FASTTRANSFER_CLEAR_B = DMA_CLEAR_CMDBIT | DMA_RW_CMDBIT | DMA_SPECIFIC_CMDBIT, + DMA_FASTTRANSFER_A2B = DMA_RW_CMDBIT | DMA_SPECIFIC_CMDBIT, + DMA_FASTTRANSFER_B2A = DMA_SPECIFIC_CMDBIT, + DMA_FASTTRANSFER_CLEAR_A_NOACK = DMA_CLEAR_CMDBIT | DMA_NOACK_CMD | DMA_SPECIFIC_CMDBIT, + DMA_FASTTRANSFER_CLEAR_B_NOACK = DMA_CLEAR_CMDBIT | DMA_RW_CMDBIT | DMA_NOACK_CMD | DMA_SPECIFIC_CMDBIT, + DMA_FASTTRANSFER_A2B_NOACK = DMA_RW_CMDBIT | DMA_NOACK_CMD | DMA_SPECIFIC_CMDBIT, + DMA_FASTTRANSFER_B2A_NOACK = DMA_NOACK_CMD | DMA_SPECIFIC_CMDBIT, +} dma_transfer_type_t; + +typedef enum { + DMA_CONFIG_SETUP = _DMA_V2_PACKING_SETUP_PARAM, + DMA_CONFIG_HEIGHT = _DMA_V2_HEIGHT_PARAM, + DMA_CONFIG_STRIDE_A_ = _DMA_V2_STRIDE_A_PARAM, + DMA_CONFIG_CROP_ELEM_A = _DMA_V2_ELEM_CROPPING_A_PARAM, + DMA_CONFIG_WIDTH_A = _DMA_V2_WIDTH_A_PARAM, + DMA_CONFIG_STRIDE_B_ = _DMA_V2_STRIDE_B_PARAM, + DMA_CONFIG_CROP_ELEM_B = _DMA_V2_ELEM_CROPPING_B_PARAM, + DMA_CONFIG_WIDTH_B = _DMA_V2_WIDTH_B_PARAM, +} dma_config_type_t; + +struct dma_port_config { + uint8_t crop, elems; + uint16_t width; + uint32_t stride; +}; + +/* Descriptor for dma configuration */ +struct dma_channel_config { + uint8_t connection; + uint8_t extension; + uint8_t height; + struct dma_port_config a, b; +}; + +#endif /* __DMA_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/event_fifo_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/event_fifo_global.h new file mode 100644 index 0000000000000000000000000000000000000000..4df7a405cdcf2ef25f8429d741b6c201e412d6d9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/event_fifo_global.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __EVENT_FIFO_GLOBAL_H +#define __EVENT_FIFO_GLOBAL_H + +/*#error "event_global.h: No global event information permitted"*/ + +#endif /* __EVENT_FIFO_GLOBAL_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/fifo_monitor_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/fifo_monitor_global.h new file mode 100644 index 0000000000000000000000000000000000000000..f43bf0ad246899be276a03467c11131ba679dd5f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/fifo_monitor_global.h @@ -0,0 +1,32 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __FIFO_MONITOR_GLOBAL_H_INCLUDED__ +#define __FIFO_MONITOR_GLOBAL_H_INCLUDED__ + +#define IS_FIFO_MONITOR_VERSION_2 + +/* +#define HIVE_ISP_CSS_STREAM_SWITCH_NONE 0 +#define HIVE_ISP_CSS_STREAM_SWITCH_SP 1 +#define HIVE_ISP_CSS_STREAM_SWITCH_ISP 2 + * + * Actually, "HIVE_ISP_CSS_STREAM_SWITCH_SP = 1", "HIVE_ISP_CSS_STREAM_SWITCH_ISP = 0" + * "hive_isp_css_stream_switch_hrt.h" + */ +#define HIVE_ISP_CSS_STREAM_SWITCH_ISP 0 +#define HIVE_ISP_CSS_STREAM_SWITCH_SP 1 +#define HIVE_ISP_CSS_STREAM_SWITCH_NONE 2 + +#endif /* __FIFO_MONITOR_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/gdc_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/gdc_global.h new file mode 100644 index 0000000000000000000000000000000000000000..4505775b224c9e811cb0f0193c9d23d519cbd448 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/gdc_global.h @@ -0,0 +1,90 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GDC_GLOBAL_H_INCLUDED__ +#define __GDC_GLOBAL_H_INCLUDED__ + +#define IS_GDC_VERSION_2 + +#include +#include "gdc_v2_defs.h" + +/* + * Storage addresses for packed data transfer + */ +#define GDC_PARAM_ICX_LEFT_ROUNDED_IDX 0 +#define GDC_PARAM_OXDIM_FLOORED_IDX 1 +#define GDC_PARAM_OXDIM_LAST_IDX 2 +#define GDC_PARAM_WOIX_LAST_IDX 3 +#define GDC_PARAM_IY_TOPLEFT_IDX 4 +#define GDC_PARAM_CHUNK_CNT_IDX 5 +/*#define GDC_PARAM_ELEMENTS_PER_XMEM_ADDR_IDX 6 */ /* Derived from bpp */ +#define GDC_PARAM_BPP_IDX 6 +#define GDC_PARAM_BLOCK_HEIGHT_IDX 7 +/*#define GDC_PARAM_DMA_CHANNEL_STRIDE_A_IDX 8*/ /* The DMA stride == the GDC buffer stride */ +#define GDC_PARAM_WOIX_IDX 8 +#define GDC_PARAM_DMA_CHANNEL_STRIDE_B_IDX 9 +#define GDC_PARAM_DMA_CHANNEL_WIDTH_A_IDX 10 +#define GDC_PARAM_DMA_CHANNEL_WIDTH_B_IDX 11 +#define GDC_PARAM_VECTORS_PER_LINE_IN_IDX 12 +#define GDC_PARAM_VECTORS_PER_LINE_OUT_IDX 13 +#define GDC_PARAM_VMEM_IN_DIMY_IDX 14 +#define GDC_PARAM_COMMAND_IDX 15 +#define N_GDC_PARAM 16 + +/* Because of the packed parameter transfer max(params) == max(fragments) */ +#define N_GDC_FRAGMENTS N_GDC_PARAM + +/* The GDC is capable of higher internal precision than the parameter data structures */ +#define HRT_GDC_COORD_SCALE_BITS 6 +#define HRT_GDC_COORD_SCALE (1 << HRT_GDC_COORD_SCALE_BITS) + +typedef enum { + GDC_CH0_ID = 0, + N_GDC_CHANNEL_ID +} gdc_channel_ID_t; + +typedef enum { + gdc_8_bpp = 8, + gdc_10_bpp = 10, + gdc_12_bpp = 12, + gdc_14_bpp = 14 +} gdc_bits_per_pixel_t; + +typedef struct gdc_scale_param_mem_s { + uint16_t params[N_GDC_PARAM]; + uint16_t ipx_start_array[N_GDC_PARAM]; + uint16_t ibuf_offset[N_GDC_PARAM]; + uint16_t obuf_offset[N_GDC_PARAM]; +} gdc_scale_param_mem_t; + +typedef struct gdc_warp_param_mem_s { + uint32_t origin_x; + uint32_t origin_y; + uint32_t in_addr_offset; + uint32_t in_block_width; + uint32_t in_block_height; + uint32_t p0_x; + uint32_t p0_y; + uint32_t p1_x; + uint32_t p1_y; + uint32_t p2_x; + uint32_t p2_y; + uint32_t p3_x; + uint32_t p3_y; + uint32_t padding[3]; +} gdc_warp_param_mem_t; + + +#endif /* __GDC_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/gp_device_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/gp_device_global.h new file mode 100644 index 0000000000000000000000000000000000000000..30ad77059d93c33e443e7663f05a3bb769617a25 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/gp_device_global.h @@ -0,0 +1,85 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GP_DEVICE_GLOBAL_H_INCLUDED__ +#define __GP_DEVICE_GLOBAL_H_INCLUDED__ + +#define IS_GP_DEVICE_VERSION_2 + +#define _REG_GP_IRQ_REQ0_ADDR 0x08 +#define _REG_GP_IRQ_REQ1_ADDR 0x0C +/* The SP sends SW interrupt info to this register */ +#define _REG_GP_IRQ_REQUEST0_ADDR _REG_GP_IRQ_REQ0_ADDR +#define _REG_GP_IRQ_REQUEST1_ADDR _REG_GP_IRQ_REQ1_ADDR + +/* The SP configures FIFO switches in these registers */ +#define _REG_GP_SWITCH_IF_ADDR 0x40 +#define _REG_GP_SWITCH_GDC1_ADDR 0x44 +#define _REG_GP_SWITCH_GDC2_ADDR 0x48 +/* @ INPUT_FORMATTER_BASE -> GP_DEVICE_BASE */ +#define _REG_GP_IFMT_input_switch_lut_reg0 0x00030800 +#define _REG_GP_IFMT_input_switch_lut_reg1 0x00030804 +#define _REG_GP_IFMT_input_switch_lut_reg2 0x00030808 +#define _REG_GP_IFMT_input_switch_lut_reg3 0x0003080C +#define _REG_GP_IFMT_input_switch_lut_reg4 0x00030810 +#define _REG_GP_IFMT_input_switch_lut_reg5 0x00030814 +#define _REG_GP_IFMT_input_switch_lut_reg6 0x00030818 +#define _REG_GP_IFMT_input_switch_lut_reg7 0x0003081C +#define _REG_GP_IFMT_input_switch_fsync_lut 0x00030820 +#define _REG_GP_IFMT_srst 0x00030824 +#define _REG_GP_IFMT_slv_reg_srst 0x00030828 +#define _REG_GP_IFMT_input_switch_ch_id_fmt_type 0x0003082C + +/* @ GP_DEVICE_BASE */ +#define _REG_GP_SYNCGEN_ENABLE_ADDR 0x00090000 +#define _REG_GP_SYNCGEN_FREE_RUNNING_ADDR 0x00090004 +#define _REG_GP_SYNCGEN_PAUSE_ADDR 0x00090008 +#define _REG_GP_NR_FRAMES_ADDR 0x0009000C +#define _REG_GP_SYNGEN_NR_PIX_ADDR 0x00090010 +#define _REG_GP_SYNGEN_NR_LINES_ADDR 0x00090014 +#define _REG_GP_SYNGEN_HBLANK_CYCLES_ADDR 0x00090018 +#define _REG_GP_SYNGEN_VBLANK_CYCLES_ADDR 0x0009001C +#define _REG_GP_ISEL_SOF_ADDR 0x00090020 +#define _REG_GP_ISEL_EOF_ADDR 0x00090024 +#define _REG_GP_ISEL_SOL_ADDR 0x00090028 +#define _REG_GP_ISEL_EOL_ADDR 0x0009002C +#define _REG_GP_ISEL_LFSR_ENABLE_ADDR 0x00090030 +#define _REG_GP_ISEL_LFSR_ENABLE_B_ADDR 0x00090034 +#define _REG_GP_ISEL_LFSR_RESET_VALUE_ADDR 0x00090038 +#define _REG_GP_ISEL_TPG_ENABLE_ADDR 0x0009003C +#define _REG_GP_ISEL_TPG_ENABLE_B_ADDR 0x00090040 +#define _REG_GP_ISEL_HOR_CNT_MASK_ADDR 0x00090044 +#define _REG_GP_ISEL_VER_CNT_MASK_ADDR 0x00090048 +#define _REG_GP_ISEL_XY_CNT_MASK_ADDR 0x0009004C +#define _REG_GP_ISEL_HOR_CNT_DELTA_ADDR 0x00090050 +#define _REG_GP_ISEL_VER_CNT_DELTA_ADDR 0x00090054 +#define _REG_GP_ISEL_TPG_MODE_ADDR 0x00090058 +#define _REG_GP_ISEL_TPG_RED1_ADDR 0x0009005C +#define _REG_GP_ISEL_TPG_GREEN1_ADDR 0x00090060 +#define _REG_GP_ISEL_TPG_BLUE1_ADDR 0x00090064 +#define _REG_GP_ISEL_TPG_RED2_ADDR 0x00090068 +#define _REG_GP_ISEL_TPG_GREEN2_ADDR 0x0009006C +#define _REG_GP_ISEL_TPG_BLUE2_ADDR 0x00090070 +#define _REG_GP_ISEL_CH_ID_ADDR 0x00090074 +#define _REG_GP_ISEL_FMT_TYPE_ADDR 0x00090078 +#define _REG_GP_ISEL_DATA_SEL_ADDR 0x0009007C +#define _REG_GP_ISEL_SBAND_SEL_ADDR 0x00090080 +#define _REG_GP_ISEL_SYNC_SEL_ADDR 0x00090084 +#define _REG_GP_SYNCGEN_HOR_CNT_ADDR 0x00090088 +#define _REG_GP_SYNCGEN_VER_CNT_ADDR 0x0009008C +#define _REG_GP_SYNCGEN_FRAME_CNT_ADDR 0x00090090 +#define _REG_GP_SOFT_RESET_ADDR 0x00090094 + + +#endif /* __GP_DEVICE_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/gp_timer_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/gp_timer_global.h new file mode 100644 index 0000000000000000000000000000000000000000..ee636ad6c5b34d6862822f7bcc6ce7345d6c0640 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/gp_timer_global.h @@ -0,0 +1,33 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GP_TIMER_GLOBAL_H_INCLUDED__ +#define __GP_TIMER_GLOBAL_H_INCLUDED__ + +#include "hive_isp_css_defs.h" /*HIVE_GP_TIMER_SP_DMEM_ERROR_IRQ */ + +/* from gp_timer_defs.h*/ +#define GP_TIMER_COUNT_TYPE_HIGH 0 +#define GP_TIMER_COUNT_TYPE_LOW 1 +#define GP_TIMER_COUNT_TYPE_POSEDGE 2 +#define GP_TIMER_COUNT_TYPE_NEGEDGE 3 +#define GP_TIMER_COUNT_TYPE_TYPES 4 + +/* timer - 3 is selected */ +#define GP_TIMER_SEL 3 + +/*HIVE_GP_TIMER_SP_DMEM_ERROR_IRQ is selected*/ +#define GP_TIMER_SIGNAL_SELECT HIVE_GP_TIMER_SP_DMEM_ERROR_IRQ + +#endif /* __GP_TIMER_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/gpio_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/gpio_global.h new file mode 100644 index 0000000000000000000000000000000000000000..a82ca2a8cadaf121c203b3e48f9722895dba964e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/gpio_global.h @@ -0,0 +1,45 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GPIO_GLOBAL_H_INCLUDED__ +#define __GPIO_GLOBAL_H_INCLUDED__ + +#define IS_GPIO_VERSION_1 + +#include + +/* pqiao: following part only defines in hive_isp_css_defs.h in fpga system. + port it here +*/ + +/* GPIO pin defines */ +/*#define HIVE_GPIO_CAMERA_BOARD_RESET_PIN_NR 0 +#define HIVE_GPIO_LCD_CLOCK_SELECT_PIN_NR 7 +#define HIVE_GPIO_HDMI_CLOCK_SELECT_PIN_NR 8 +#define HIVE_GPIO_LCD_VERT_FLIP_PIN_NR 8 +#define HIVE_GPIO_LCD_HOR_FLIP_PIN_NR 9 +#define HIVE_GPIO_AS3683_GPIO_P0_PIN_NR 1 +#define HIVE_GPIO_AS3683_DATA_P1_PIN_NR 2 +#define HIVE_GPIO_AS3683_CLK_P2_PIN_NR 3 +#define HIVE_GPIO_AS3683_T1_F0_PIN_NR 4 +#define HIVE_GPIO_AS3683_SFL_F1_PIN_NR 5 +#define HIVE_GPIO_AS3683_STROBE_F2_PIN_NR 6 +#define HIVE_GPIO_MAX1577_EN1_PIN_NR 1 +#define HIVE_GPIO_MAX1577_EN2_PIN_NR 2 +#define HIVE_GPIO_MAX8685A_EN_PIN_NR 3 +#define HIVE_GPIO_MAX8685A_TRIG_PIN_NR 4*/ + +#define HIVE_GPIO_STROBE_TRIGGER_PIN 2 + +#endif /* __GPIO_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/hmem_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/hmem_global.h new file mode 100644 index 0000000000000000000000000000000000000000..7e05d7d880d155ad2f6d0ff6beb8be615b4e8e01 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/hmem_global.h @@ -0,0 +1,45 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __HMEM_GLOBAL_H_INCLUDED__ +#define __HMEM_GLOBAL_H_INCLUDED__ + +#include + +#define IS_HMEM_VERSION_1 + +#include "isp.h" + +/* +#define ISP_HIST_ADDRESS_BITS 12 +#define ISP_HIST_ALIGNMENT 4 +#define ISP_HIST_COMP_IN_PREC 12 +#define ISP_HIST_DEPTH 1024 +#define ISP_HIST_WIDTH 24 +#define ISP_HIST_COMPONENTS 4 +*/ +#define ISP_HIST_ALIGNMENT_LOG2 2 + +#define HMEM_SIZE_LOG2 (ISP_HIST_ADDRESS_BITS-ISP_HIST_ALIGNMENT_LOG2) +#define HMEM_SIZE ISP_HIST_DEPTH + +#define HMEM_UNIT_SIZE (HMEM_SIZE/ISP_HIST_COMPONENTS) +#define HMEM_UNIT_COUNT ISP_HIST_COMPONENTS + +#define HMEM_RANGE_LOG2 ISP_HIST_WIDTH +#define HMEM_RANGE (1UL<head == debug_data_ptr->tail); +} + +STORAGE_CLASS_DEBUG_C hrt_data debug_dequeue(void) +{ + hrt_data value = 0; + + assert(debug_buffer_address != ((hrt_address)-1)); + + debug_synch_queue(); + + if (!is_debug_buffer_empty()) { + value = debug_data_ptr->buf[debug_data_ptr->head]; + debug_data_ptr->head = (debug_data_ptr->head + 1) & DEBUG_BUF_MASK; + sp_dmem_store_uint32(SP0_ID, debug_buffer_address + DEBUG_DATA_HEAD_ADDR, debug_data_ptr->head); + } + + return value; +} + +STORAGE_CLASS_DEBUG_C void debug_synch_queue(void) +{ + uint32_t remote_tail = sp_dmem_load_uint32(SP0_ID, debug_buffer_address + DEBUG_DATA_TAIL_ADDR); +/* We could move the remote head after the upload, but we would have to limit the upload w.r.t. the local head. This is easier */ + if (remote_tail > debug_data_ptr->tail) { + size_t delta = remote_tail - debug_data_ptr->tail; + sp_dmem_load(SP0_ID, debug_buffer_address + DEBUG_DATA_BUF_ADDR + debug_data_ptr->tail*sizeof(uint32_t), (void *)&(debug_data_ptr->buf[debug_data_ptr->tail]), delta*sizeof(uint32_t)); + } else if (remote_tail < debug_data_ptr->tail) { + size_t delta = DEBUG_BUF_SIZE - debug_data_ptr->tail; + sp_dmem_load(SP0_ID, debug_buffer_address + DEBUG_DATA_BUF_ADDR + debug_data_ptr->tail*sizeof(uint32_t), (void *)&(debug_data_ptr->buf[debug_data_ptr->tail]), delta*sizeof(uint32_t)); + sp_dmem_load(SP0_ID, debug_buffer_address + DEBUG_DATA_BUF_ADDR, (void *)&(debug_data_ptr->buf[0]), remote_tail*sizeof(uint32_t)); + } /* else we are up to date */ + debug_data_ptr->tail = remote_tail; +} + +STORAGE_CLASS_DEBUG_C void debug_synch_queue_isp(void) +{ + uint32_t remote_tail = isp_dmem_load_uint32(ISP0_ID, DEBUG_BUFFER_ISP_DMEM_ADDR + DEBUG_DATA_TAIL_ADDR); +/* We could move the remote head after the upload, but we would have to limit the upload w.r.t. the local head. This is easier */ + if (remote_tail > debug_data_ptr->tail) { + size_t delta = remote_tail - debug_data_ptr->tail; + isp_dmem_load(ISP0_ID, DEBUG_BUFFER_ISP_DMEM_ADDR + DEBUG_DATA_BUF_ADDR + debug_data_ptr->tail*sizeof(uint32_t), (void *)&(debug_data_ptr->buf[debug_data_ptr->tail]), delta*sizeof(uint32_t)); + } else if (remote_tail < debug_data_ptr->tail) { + size_t delta = DEBUG_BUF_SIZE - debug_data_ptr->tail; + isp_dmem_load(ISP0_ID, DEBUG_BUFFER_ISP_DMEM_ADDR + DEBUG_DATA_BUF_ADDR + debug_data_ptr->tail*sizeof(uint32_t), (void *)&(debug_data_ptr->buf[debug_data_ptr->tail]), delta*sizeof(uint32_t)); + isp_dmem_load(ISP0_ID, DEBUG_BUFFER_ISP_DMEM_ADDR + DEBUG_DATA_BUF_ADDR, (void *)&(debug_data_ptr->buf[0]), remote_tail*sizeof(uint32_t)); + } /* else we are up to date */ + debug_data_ptr->tail = remote_tail; +} + +STORAGE_CLASS_DEBUG_C void debug_synch_queue_ddr(void) +{ + uint32_t remote_tail; + + mmgr_load(debug_buffer_ddr_address + DEBUG_DATA_TAIL_DDR_ADDR, &remote_tail, sizeof(uint32_t)); +/* We could move the remote head after the upload, but we would have to limit the upload w.r.t. the local head. This is easier */ + if (remote_tail > debug_data_ptr->tail) { + size_t delta = remote_tail - debug_data_ptr->tail; + mmgr_load(debug_buffer_ddr_address + DEBUG_DATA_BUF_DDR_ADDR + debug_data_ptr->tail*sizeof(uint32_t), (void *)&(debug_data_ptr->buf[debug_data_ptr->tail]), delta*sizeof(uint32_t)); + } else if (remote_tail < debug_data_ptr->tail) { + size_t delta = DEBUG_BUF_SIZE - debug_data_ptr->tail; + mmgr_load(debug_buffer_ddr_address + DEBUG_DATA_BUF_DDR_ADDR + debug_data_ptr->tail*sizeof(uint32_t), (void *)&(debug_data_ptr->buf[debug_data_ptr->tail]), delta*sizeof(uint32_t)); + mmgr_load(debug_buffer_ddr_address + DEBUG_DATA_BUF_DDR_ADDR, (void *)&(debug_data_ptr->buf[0]), remote_tail*sizeof(uint32_t)); + } /* else we are up to date */ + debug_data_ptr->tail = remote_tail; +} + +#endif /* __DEBUG_PRIVATE_H_INCLUDED__ */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/dma.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/dma.c new file mode 100644 index 0000000000000000000000000000000000000000..87a25d4289ecd6938dfb3d29e017ccd63801e126 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/dma.c @@ -0,0 +1,299 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2016, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include /* NULL */ + +#include "dma.h" + +#include "assert_support.h" + +#ifndef __INLINE_DMA__ +#include "dma_private.h" +#endif /* __INLINE_DMA__ */ + +void dma_get_state(const dma_ID_t ID, dma_state_t *state) +{ + int i; + hrt_data tmp; + + assert(ID < N_DMA_ID); + assert(state != NULL); + + tmp = dma_reg_load(ID, DMA_COMMAND_FSM_REG_IDX); + //reg [3:0] : flags error [3], stall, run, idle [0] + //reg [9:4] : command + //reg[14:10] : channel + //reg [23:15] : param + state->fsm_command_idle = tmp & 0x1; + state->fsm_command_run = tmp & 0x2; + state->fsm_command_stalling = tmp & 0x4; + state->fsm_command_error = tmp & 0x8; + state->last_command_channel = (tmp>>10 & 0x1F); + state->last_command_param = (tmp>>15 & 0x0F); + tmp = (tmp>>4) & 0x3F; +/* state->last_command = (dma_commands_t)tmp; */ +/* if the enumerator is made non-linear */ + /* AM: the list below does not cover all the cases*/ + /* and these are not correct */ + /* therefore for just dumpinmg this command*/ + state->last_command = tmp; + +/* + if (tmp == 0) + state->last_command = DMA_COMMAND_READ; + if (tmp == 1) + state->last_command = DMA_COMMAND_WRITE; + if (tmp == 2) + state->last_command = DMA_COMMAND_SET_CHANNEL; + if (tmp == 3) + state->last_command = DMA_COMMAND_SET_PARAM; + if (tmp == 4) + state->last_command = DMA_COMMAND_READ_SPECIFIC; + if (tmp == 5) + state->last_command = DMA_COMMAND_WRITE_SPECIFIC; + if (tmp == 8) + state->last_command = DMA_COMMAND_INIT; + if (tmp == 12) + state->last_command = DMA_COMMAND_INIT_SPECIFIC; + if (tmp == 15) + state->last_command = DMA_COMMAND_RST; +*/ + +/* No sub-fields, idx = 0 */ + state->current_command = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX(0, _DMA_FSM_GROUP_CMD_IDX)); + state->current_addr_a = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX(0, _DMA_FSM_GROUP_ADDR_A_IDX)); + state->current_addr_b = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX(0, _DMA_FSM_GROUP_ADDR_B_IDX)); + + tmp = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_STATE_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_idle = tmp & 0x1; + state->fsm_ctrl_run = tmp & 0x2; + state->fsm_ctrl_stalling = tmp & 0x4; + state->fsm_ctrl_error = tmp & 0x8; + tmp = tmp >> 4; +/* state->fsm_ctrl_state = (dma_ctrl_states_t)tmp; */ + if (tmp == 0) + state->fsm_ctrl_state = DMA_CTRL_STATE_IDLE; + if (tmp == 1) + state->fsm_ctrl_state = DMA_CTRL_STATE_REQ_RCV; + if (tmp == 2) + state->fsm_ctrl_state = DMA_CTRL_STATE_RCV; + if (tmp == 3) + state->fsm_ctrl_state = DMA_CTRL_STATE_RCV_REQ; + if (tmp == 4) + state->fsm_ctrl_state = DMA_CTRL_STATE_INIT; + state->fsm_ctrl_source_dev = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_source_addr = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_source_stride = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_source_width = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_REQ_XB_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_source_height = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_REQ_YB_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_pack_source_dev = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_pack_dest_dev = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_dest_addr = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_dest_stride = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_pack_source_width = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_pack_dest_height = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_pack_dest_width = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_pack_source_elems = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_pack_dest_elems = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + state->fsm_ctrl_pack_extension = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX, + _DMA_FSM_GROUP_FSM_CTRL_IDX)); + + tmp = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_PACK_STATE_IDX, + _DMA_FSM_GROUP_FSM_PACK_IDX)); + state->pack_idle = tmp & 0x1; + state->pack_run = tmp & 0x2; + state->pack_stalling = tmp & 0x4; + state->pack_error = tmp & 0x8; + state->pack_cnt_height = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_PACK_CNT_YB_IDX, + _DMA_FSM_GROUP_FSM_PACK_IDX)); + state->pack_src_cnt_width = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX, + _DMA_FSM_GROUP_FSM_PACK_IDX)); + state->pack_dest_cnt_width = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX, + _DMA_FSM_GROUP_FSM_PACK_IDX)); + + tmp = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_REQ_STATE_IDX, + _DMA_FSM_GROUP_FSM_REQ_IDX)); +/* state->read_state = (dma_rw_states_t)tmp; */ + if (tmp == 0) + state->read_state = DMA_RW_STATE_IDLE; + if (tmp == 1) + state->read_state = DMA_RW_STATE_REQ; + if (tmp == 2) + state->read_state = DMA_RW_STATE_NEXT_LINE; + if (tmp == 3) + state->read_state = DMA_RW_STATE_UNLOCK_CHANNEL; + state->read_cnt_height = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_REQ_CNT_YB_IDX, + _DMA_FSM_GROUP_FSM_REQ_IDX)); + state->read_cnt_width = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_REQ_CNT_XB_IDX, + _DMA_FSM_GROUP_FSM_REQ_IDX)); + + tmp = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_WR_STATE_IDX, + _DMA_FSM_GROUP_FSM_WR_IDX)); +/* state->write_state = (dma_rw_states_t)tmp; */ + if (tmp == 0) + state->write_state = DMA_RW_STATE_IDLE; + if (tmp == 1) + state->write_state = DMA_RW_STATE_REQ; + if (tmp == 2) + state->write_state = DMA_RW_STATE_NEXT_LINE; + if (tmp == 3) + state->write_state = DMA_RW_STATE_UNLOCK_CHANNEL; + state->write_height = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_WR_CNT_YB_IDX, + _DMA_FSM_GROUP_FSM_WR_IDX)); + state->write_width = dma_reg_load(ID, + DMA_CG_INFO_REG_IDX( + _DMA_FSM_GROUP_FSM_WR_CNT_XB_IDX, + _DMA_FSM_GROUP_FSM_WR_IDX)); + + for (i = 0; i < HIVE_ISP_NUM_DMA_CONNS; i++) { + dma_port_state_t *port = &(state->port_states[i]); + + tmp = dma_reg_load(ID, DMA_DEV_INFO_REG_IDX(0, i)); + port->req_cs = ((tmp & 0x1) != 0); + port->req_we_n = ((tmp & 0x2) != 0); + port->req_run = ((tmp & 0x4) != 0); + port->req_ack = ((tmp & 0x8) != 0); + + tmp = dma_reg_load(ID, DMA_DEV_INFO_REG_IDX(1, i)); + port->send_cs = ((tmp & 0x1) != 0); + port->send_we_n = ((tmp & 0x2) != 0); + port->send_run = ((tmp & 0x4) != 0); + port->send_ack = ((tmp & 0x8) != 0); + + tmp = dma_reg_load(ID, DMA_DEV_INFO_REG_IDX(2, i)); + if (tmp & 0x1) + port->fifo_state = DMA_FIFO_STATE_WILL_BE_FULL; + if (tmp & 0x2) + port->fifo_state = DMA_FIFO_STATE_FULL; + if (tmp & 0x4) + port->fifo_state = DMA_FIFO_STATE_EMPTY; + port->fifo_counter = tmp >> 3; + } + + for (i = 0; i < HIVE_DMA_NUM_CHANNELS; i++) { + dma_channel_state_t *ch = &(state->channel_states[i]); + + ch->connection = DMA_GET_CONNECTION(dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_PACKING_SETUP_PARAM))); + ch->sign_extend = DMA_GET_EXTENSION(dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_PACKING_SETUP_PARAM))); + ch->height = dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_HEIGHT_PARAM)); + ch->stride_a = dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_STRIDE_A_PARAM)); + ch->elems_a = DMA_GET_ELEMENTS(dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_ELEM_CROPPING_A_PARAM))); + ch->cropping_a = DMA_GET_CROPPING(dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_ELEM_CROPPING_A_PARAM))); + ch->width_a = dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_WIDTH_A_PARAM)); + ch->stride_b = dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_STRIDE_B_PARAM)); + ch->elems_b = DMA_GET_ELEMENTS(dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_ELEM_CROPPING_B_PARAM))); + ch->cropping_b = DMA_GET_CROPPING(dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_ELEM_CROPPING_B_PARAM))); + ch->width_b = dma_reg_load(ID, + DMA_CHANNEL_PARAM_REG_IDX(i, + _DMA_WIDTH_B_PARAM)); + } +} + +void +dma_set_max_burst_size(const dma_ID_t ID, dma_connection conn, + uint32_t max_burst_size) +{ + assert(ID < N_DMA_ID); + assert(max_burst_size > 0); + dma_reg_store(ID, DMA_DEV_INFO_REG_IDX(_DMA_DEV_INTERF_MAX_BURST_IDX, conn), + max_burst_size - 1); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/dma_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/dma_local.h new file mode 100644 index 0000000000000000000000000000000000000000..ab631e6f64b505575b1c174978626d907b2f0a6f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/dma_local.h @@ -0,0 +1,207 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __DMA_LOCAL_H_INCLUDED__ +#define __DMA_LOCAL_H_INCLUDED__ + +#include +#include "dma_global.h" + +#include /* HRTCAT() */ +#include /* _hrt_get_bits() */ +#include /* HIVE_DMA_NUM_CHANNELS */ +#include + +#define _DMA_FSM_GROUP_CMD_IDX _DMA_V2_FSM_GROUP_CMD_IDX +#define _DMA_FSM_GROUP_ADDR_A_IDX _DMA_V2_FSM_GROUP_ADDR_SRC_IDX +#define _DMA_FSM_GROUP_ADDR_B_IDX _DMA_V2_FSM_GROUP_ADDR_DEST_IDX + +#define _DMA_FSM_GROUP_CMD_CTRL_IDX _DMA_V2_FSM_GROUP_CMD_CTRL_IDX + +#define _DMA_FSM_GROUP_FSM_CTRL_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_STATE_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_REQ_XB_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_XB_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_REQ_YB_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_YB_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX +#define _DMA_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX + +#define _DMA_FSM_GROUP_FSM_PACK_IDX _DMA_V2_FSM_GROUP_FSM_PACK_IDX +#define _DMA_FSM_GROUP_FSM_PACK_STATE_IDX _DMA_V2_FSM_GROUP_FSM_PACK_STATE_IDX +#define _DMA_FSM_GROUP_FSM_PACK_CNT_YB_IDX _DMA_V2_FSM_GROUP_FSM_PACK_CNT_YB_IDX +#define _DMA_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX +#define _DMA_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX + +#define _DMA_FSM_GROUP_FSM_REQ_IDX _DMA_V2_FSM_GROUP_FSM_REQ_IDX +#define _DMA_FSM_GROUP_FSM_REQ_STATE_IDX _DMA_V2_FSM_GROUP_FSM_REQ_STATE_IDX +#define _DMA_FSM_GROUP_FSM_REQ_CNT_YB_IDX _DMA_V2_FSM_GROUP_FSM_REQ_CNT_YB_IDX +#define _DMA_FSM_GROUP_FSM_REQ_CNT_XB_IDX _DMA_V2_FSM_GROUP_FSM_REQ_CNT_XB_IDX + +#define _DMA_FSM_GROUP_FSM_WR_IDX _DMA_V2_FSM_GROUP_FSM_WR_IDX +#define _DMA_FSM_GROUP_FSM_WR_STATE_IDX _DMA_V2_FSM_GROUP_FSM_WR_STATE_IDX +#define _DMA_FSM_GROUP_FSM_WR_CNT_YB_IDX _DMA_V2_FSM_GROUP_FSM_WR_CNT_YB_IDX +#define _DMA_FSM_GROUP_FSM_WR_CNT_XB_IDX _DMA_V2_FSM_GROUP_FSM_WR_CNT_XB_IDX + +#define _DMA_DEV_INTERF_MAX_BURST_IDX _DMA_V2_DEV_INTERF_MAX_BURST_IDX + +/* + * Macro's to compute the DMA parameter register indices + */ +#define DMA_SEL_COMP(comp) (((comp) & _hrt_ones(_DMA_V2_ADDR_SEL_COMP_BITS)) << _DMA_V2_ADDR_SEL_COMP_IDX) +#define DMA_SEL_CH(ch) (((ch) & _hrt_ones(_DMA_V2_ADDR_SEL_CH_REG_BITS)) << _DMA_V2_ADDR_SEL_CH_REG_IDX) +#define DMA_SEL_PARAM(param) (((param) & _hrt_ones(_DMA_V2_ADDR_SEL_PARAM_BITS)) << _DMA_V2_ADDR_SEL_PARAM_IDX) +/* CG = Connection Group */ +#define DMA_SEL_CG_INFO(info) (((info) & _hrt_ones(_DMA_V2_ADDR_SEL_GROUP_COMP_INFO_BITS)) << _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_IDX) +#define DMA_SEL_CG_COMP(comp) (((comp) & _hrt_ones(_DMA_V2_ADDR_SEL_GROUP_COMP_BITS)) << _DMA_V2_ADDR_SEL_GROUP_COMP_IDX) +#define DMA_SEL_DEV_INFO(info) (((info) & _hrt_ones(_DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS)) << _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX) +#define DMA_SEL_DEV_ID(dev) (((dev) & _hrt_ones(_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS)) << _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX) + +#define DMA_COMMAND_FSM_REG_IDX (DMA_SEL_COMP(_DMA_V2_SEL_FSM_CMD) >> 2) +#define DMA_CHANNEL_PARAM_REG_IDX(ch, param) ((DMA_SEL_COMP(_DMA_V2_SEL_CH_REG) | DMA_SEL_CH(ch) | DMA_SEL_PARAM(param)) >> 2) +#define DMA_CG_INFO_REG_IDX(info_id, comp_id) ((DMA_SEL_COMP(_DMA_V2_SEL_CONN_GROUP) | DMA_SEL_CG_INFO(info_id) | DMA_SEL_CG_COMP(comp_id)) >> 2) +#define DMA_DEV_INFO_REG_IDX(info_id, dev_id) ((DMA_SEL_COMP(_DMA_V2_SEL_DEV_INTERF) | DMA_SEL_DEV_INFO(info_id) | DMA_SEL_DEV_ID(dev_id)) >> 2) +#define DMA_RST_REG_IDX (DMA_SEL_COMP(_DMA_V2_SEL_RESET) >> 2) + +#define DMA_GET_CONNECTION(val) _hrt_get_bits(val, _DMA_V2_CONNECTION_IDX, _DMA_V2_CONNECTION_BITS) +#define DMA_GET_EXTENSION(val) _hrt_get_bits(val, _DMA_V2_EXTENSION_IDX, _DMA_V2_EXTENSION_BITS) +#define DMA_GET_ELEMENTS(val) _hrt_get_bits(val, _DMA_V2_ELEMENTS_IDX, _DMA_V2_ELEMENTS_BITS) +#define DMA_GET_CROPPING(val) _hrt_get_bits(val, _DMA_V2_LEFT_CROPPING_IDX, _DMA_V2_LEFT_CROPPING_BITS) + +typedef enum { + DMA_CTRL_STATE_IDLE, + DMA_CTRL_STATE_REQ_RCV, + DMA_CTRL_STATE_RCV, + DMA_CTRL_STATE_RCV_REQ, + DMA_CTRL_STATE_INIT, + N_DMA_CTRL_STATES +} dma_ctrl_states_t; + +typedef enum { + DMA_COMMAND_READ, + DMA_COMMAND_WRITE, + DMA_COMMAND_SET_CHANNEL, + DMA_COMMAND_SET_PARAM, + DMA_COMMAND_READ_SPECIFIC, + DMA_COMMAND_WRITE_SPECIFIC, + DMA_COMMAND_INIT, + DMA_COMMAND_INIT_SPECIFIC, + DMA_COMMAND_RST, + N_DMA_COMMANDS +} dma_commands_t; + +typedef enum { + DMA_RW_STATE_IDLE, + DMA_RW_STATE_REQ, + DMA_RW_STATE_NEXT_LINE, + DMA_RW_STATE_UNLOCK_CHANNEL, + N_DMA_RW_STATES +} dma_rw_states_t; + +typedef enum { + DMA_FIFO_STATE_WILL_BE_FULL, + DMA_FIFO_STATE_FULL, + DMA_FIFO_STATE_EMPTY, + N_DMA_FIFO_STATES +} dma_fifo_states_t; + +/* typedef struct dma_state_s dma_state_t; */ +typedef struct dma_channel_state_s dma_channel_state_t; +typedef struct dma_port_state_s dma_port_state_t; + +struct dma_port_state_s { + bool req_cs; + bool req_we_n; + bool req_run; + bool req_ack; + bool send_cs; + bool send_we_n; + bool send_run; + bool send_ack; + dma_fifo_states_t fifo_state; + int fifo_counter; +}; + +struct dma_channel_state_s { + int connection; + bool sign_extend; + int height; + int stride_a; + int elems_a; + int cropping_a; + int width_a; + int stride_b; + int elems_b; + int cropping_b; + int width_b; +}; + +struct dma_state_s { + bool fsm_command_idle; + bool fsm_command_run; + bool fsm_command_stalling; + bool fsm_command_error; + dma_commands_t last_command; + int last_command_channel; + int last_command_param; + dma_commands_t current_command; + int current_addr_a; + int current_addr_b; + bool fsm_ctrl_idle; + bool fsm_ctrl_run; + bool fsm_ctrl_stalling; + bool fsm_ctrl_error; + dma_ctrl_states_t fsm_ctrl_state; + int fsm_ctrl_source_dev; + int fsm_ctrl_source_addr; + int fsm_ctrl_source_stride; + int fsm_ctrl_source_width; + int fsm_ctrl_source_height; + int fsm_ctrl_pack_source_dev; + int fsm_ctrl_pack_dest_dev; + int fsm_ctrl_dest_addr; + int fsm_ctrl_dest_stride; + int fsm_ctrl_pack_source_width; + int fsm_ctrl_pack_dest_height; + int fsm_ctrl_pack_dest_width; + int fsm_ctrl_pack_source_elems; + int fsm_ctrl_pack_dest_elems; + int fsm_ctrl_pack_extension; + int pack_idle; + int pack_run; + int pack_stalling; + int pack_error; + int pack_cnt_height; + int pack_src_cnt_width; + int pack_dest_cnt_width; + dma_rw_states_t read_state; + int read_cnt_height; + int read_cnt_width; + dma_rw_states_t write_state; + int write_height; + int write_width; + dma_port_state_t port_states[HIVE_ISP_NUM_DMA_CONNS]; + dma_channel_state_t channel_states[HIVE_DMA_NUM_CHANNELS]; +}; + +#endif /* __DMA_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/dma_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/dma_private.h new file mode 100644 index 0000000000000000000000000000000000000000..ba54b1f0467b74d84b6ed1d0c30ab5b199160e71 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/dma_private.h @@ -0,0 +1,41 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __DMA_PRIVATE_H_INCLUDED__ +#define __DMA_PRIVATE_H_INCLUDED__ + +#include "dma_public.h" + +#include "device_access.h" + +#include "assert_support.h" + +STORAGE_CLASS_DMA_C void dma_reg_store(const dma_ID_t ID, + const unsigned int reg, + const hrt_data value) +{ + assert(ID < N_DMA_ID); + assert(DMA_BASE[ID] != (hrt_address)-1); + ia_css_device_store_uint32(DMA_BASE[ID] + reg*sizeof(hrt_data), value); +} + +STORAGE_CLASS_DMA_C hrt_data dma_reg_load(const dma_ID_t ID, + const unsigned int reg) +{ + assert(ID < N_DMA_ID); + assert(DMA_BASE[ID] != (hrt_address)-1); + return ia_css_device_load_uint32(DMA_BASE[ID] + reg*sizeof(hrt_data)); +} + +#endif /* __DMA_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/event_fifo.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/event_fifo.c new file mode 100644 index 0000000000000000000000000000000000000000..777670948d6f57169de488fa7d3c45b52b309a44 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/event_fifo.c @@ -0,0 +1,19 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "event_fifo.h" + +#ifndef __INLINE_EVENT__ +#include "event_fifo_private.h" +#endif /* __INLINE_EVENT__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/event_fifo_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/event_fifo_local.h new file mode 100644 index 0000000000000000000000000000000000000000..c595692c6ea9871a23416127d5c34b17a86f6b1e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/event_fifo_local.h @@ -0,0 +1,57 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _EVENT_FIFO_LOCAL_H +#define _EVENT_FIFO_LOCAL_H + +/* + * All events come from connections mapped on the system + * bus but do not use a global IRQ + */ +#include "event_fifo_global.h" + +typedef enum { + SP0_EVENT_ID, + ISP0_EVENT_ID, + STR2MIPI_EVENT_ID, + N_EVENT_ID +} event_ID_t; + +#define EVENT_QUERY_BIT 0 + +/* Events are read from FIFO */ +static const hrt_address event_source_addr[N_EVENT_ID] = { + 0x0000000000380000ULL, + 0x0000000000380004ULL, + 0xffffffffffffffffULL}; + +/* Read from FIFO are blocking, query data availability */ +static const hrt_address event_source_query_addr[N_EVENT_ID] = { + 0x0000000000380010ULL, + 0x0000000000380014ULL, + 0xffffffffffffffffULL}; + +/* Events are written to FIFO */ +static const hrt_address event_sink_addr[N_EVENT_ID] = { + 0x0000000000380008ULL, + 0x000000000038000CULL, + 0x0000000000090104ULL}; + +/* Writes to FIFO are blocking, query data space */ +static const hrt_address event_sink_query_addr[N_EVENT_ID] = { + 0x0000000000380018ULL, + 0x000000000038001CULL, + 0x000000000009010CULL}; + +#endif /* _EVENT_FIFO_LOCAL_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/event_fifo_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/event_fifo_private.h new file mode 100644 index 0000000000000000000000000000000000000000..9d3a29696094b22e50d371e45c4b5482a993ebd8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/event_fifo_private.h @@ -0,0 +1,75 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __EVENT_FIFO_PRIVATE_H +#define __EVENT_FIFO_PRIVATE_H + +#include "event_fifo_public.h" + +#include "device_access.h" + +#include "assert_support.h" + +#include /* _hrt_get_bits() */ + +STORAGE_CLASS_EVENT_C void event_wait_for(const event_ID_t ID) +{ + assert(ID < N_EVENT_ID); + assert(event_source_addr[ID] != ((hrt_address)-1)); + (void)ia_css_device_load_uint32(event_source_addr[ID]); +return; +} + +STORAGE_CLASS_EVENT_C void cnd_event_wait_for(const event_ID_t ID, + const bool cnd) +{ + if (cnd) { + event_wait_for(ID); + } +} + +STORAGE_CLASS_EVENT_C hrt_data event_receive_token(const event_ID_t ID) +{ + assert(ID < N_EVENT_ID); + assert(event_source_addr[ID] != ((hrt_address)-1)); + return ia_css_device_load_uint32(event_source_addr[ID]); +} + +STORAGE_CLASS_EVENT_C void event_send_token(const event_ID_t ID, + const hrt_data token) +{ + assert(ID < N_EVENT_ID); + assert(event_sink_addr[ID] != ((hrt_address)-1)); + ia_css_device_store_uint32(event_sink_addr[ID], token); +} + +STORAGE_CLASS_EVENT_C bool is_event_pending(const event_ID_t ID) +{ + hrt_data value; + assert(ID < N_EVENT_ID); + assert(event_source_query_addr[ID] != ((hrt_address)-1)); + value = ia_css_device_load_uint32(event_source_query_addr[ID]); + return !_hrt_get_bit(value, EVENT_QUERY_BIT); +} + +STORAGE_CLASS_EVENT_C bool can_event_send_token(const event_ID_t ID) +{ + hrt_data value; + assert(ID < N_EVENT_ID); + assert(event_sink_query_addr[ID] != ((hrt_address)-1)); + value = ia_css_device_load_uint32(event_sink_query_addr[ID]); + return !_hrt_get_bit(value, EVENT_QUERY_BIT); +} + +#endif /* __EVENT_FIFO_PRIVATE_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/fifo_monitor.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/fifo_monitor.c new file mode 100644 index 0000000000000000000000000000000000000000..1087944d637f8e9f070ccf3a0eb1ad15d51eab6a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/fifo_monitor.c @@ -0,0 +1,567 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "fifo_monitor.h" + +#include +#include "device_access.h" + +#include + +#include "gp_device.h" + +#include "assert_support.h" + +#ifndef __INLINE_FIFO_MONITOR__ +#define STORAGE_CLASS_FIFO_MONITOR_DATA static const +#else +#define STORAGE_CLASS_FIFO_MONITOR_DATA const +#endif /* __INLINE_FIFO_MONITOR__ */ + +STORAGE_CLASS_FIFO_MONITOR_DATA unsigned int FIFO_SWITCH_ADDR[N_FIFO_SWITCH] = { + _REG_GP_SWITCH_IF_ADDR, + _REG_GP_SWITCH_GDC1_ADDR, + _REG_GP_SWITCH_GDC2_ADDR}; + +#ifndef __INLINE_FIFO_MONITOR__ +#include "fifo_monitor_private.h" +#endif /* __INLINE_FIFO_MONITOR__ */ + +STORAGE_CLASS_INLINE bool fifo_monitor_status_valid ( + const fifo_monitor_ID_t ID, + const unsigned int reg, + const unsigned int port_id); + +STORAGE_CLASS_INLINE bool fifo_monitor_status_accept( + const fifo_monitor_ID_t ID, + const unsigned int reg, + const unsigned int port_id); + + +void fifo_channel_get_state( + const fifo_monitor_ID_t ID, + const fifo_channel_t channel_id, + fifo_channel_state_t *state) +{ + assert(channel_id < N_FIFO_CHANNEL); + assert(state != NULL); + + switch (channel_id) { + case FIFO_CHANNEL_ISP0_TO_SP0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_SP); /* ISP_STR_MON_PORT_ISP2SP */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_SP); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_ISP); /* ISP_STR_MON_PORT_SP2ISP */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_ISP); + break; + case FIFO_CHANNEL_SP0_TO_ISP0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_ISP); /* ISP_STR_MON_PORT_SP2ISP */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_ISP); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_SP); /* ISP_STR_MON_PORT_ISP2SP */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_SP); + break; + case FIFO_CHANNEL_ISP0_TO_IF0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_PIF_A); /* ISP_STR_MON_PORT_ISP2PIFA */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_PIF_A); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_PIF_A); /* MOD_STR_MON_PORT_CELLS2PIFA */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_PIF_A); + break; + case FIFO_CHANNEL_IF0_TO_ISP0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_PIF_A); /* MOD_STR_MON_PORT_PIFA2CELLS */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_PIF_A); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_PIF_A); /* ISP_STR_MON_PORT_PIFA2ISP */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_PIF_A); + break; + case FIFO_CHANNEL_ISP0_TO_IF1: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_PIF_B); /* ISP_STR_MON_PORT_ISP2PIFA */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_PIF_B); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_PIF_B); /* MOD_STR_MON_PORT_CELLS2PIFB */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_PIF_B); + break; + case FIFO_CHANNEL_IF1_TO_ISP0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_PIF_B); /* MOD_STR_MON_PORT_PIFB2CELLS */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_PIF_B); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_PIF_B); /* ISP_STR_MON_PORT_PIFB2ISP */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_PIF_B); + break; + case FIFO_CHANNEL_ISP0_TO_DMA0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_DMA); /* ISP_STR_MON_PORT_ISP2DMA */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_DMA); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_DMA_FR_ISP); /* MOD_STR_MON_PORT_ISP2DMA */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_DMA_FR_ISP); + break; + case FIFO_CHANNEL_DMA0_TO_ISP0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_DMA2ISP); /* MOD_STR_MON_PORT_DMA2ISP */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_DMA2ISP); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_DMA); /* ISP_STR_MON_PORT_DMA2ISP */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_DMA); + break; + case FIFO_CHANNEL_ISP0_TO_GDC0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_GDC); /* ISP_STR_MON_PORT_ISP2GDC1 */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_GDC); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_GDC); /* MOD_STR_MON_PORT_CELLS2GDC1 */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_GDC); + break; + case FIFO_CHANNEL_GDC0_TO_ISP0: + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_GDC); /* MOD_STR_MON_PORT_GDC12CELLS */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_GDC); + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_GDC); /* ISP_STR_MON_PORT_GDC12ISP */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_GDC); + break; + case FIFO_CHANNEL_ISP0_TO_GDC1: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_ISP2GDC2); + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_ISP2GDC2); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_CELLS2GDC2); + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_CELLS2GDC2); + break; + case FIFO_CHANNEL_GDC1_TO_ISP0: + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_GDC22CELLS); + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_GDC22CELLS); + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_GDC22ISP); + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_GDC22ISP); + break; + case FIFO_CHANNEL_ISP0_TO_HOST0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_GPD); /* ISP_STR_MON_PORT_ISP2GPD */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_SND_GPD); + { + hrt_data value = ia_css_device_load_uint32(0x0000000000380014ULL); + state->fifo_valid = !_hrt_get_bit(value, 0); + state->sink_accept = false; /* no monitor connected */ + } + break; + case FIFO_CHANNEL_HOST0_TO_ISP0: + { + hrt_data value = ia_css_device_load_uint32(0x000000000038001CULL); + state->fifo_valid = false; /* no monitor connected */ + state->sink_accept = !_hrt_get_bit(value, 0); + } + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_GPD); /* ISP_STR_MON_PORT_FA2ISP */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_ISP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_GPD); + break; + case FIFO_CHANNEL_SP0_TO_IF0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_PIF_A); /* SP_STR_MON_PORT_SP2PIFA */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_PIF_A); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_PIF_A); /* MOD_STR_MON_PORT_CELLS2PIFA */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_PIF_A); + break; + case FIFO_CHANNEL_IF0_TO_SP0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_PIF_A); /* MOD_STR_MON_PORT_PIFA2CELLS */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_PIF_A); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_PIF_A); /* SP_STR_MON_PORT_PIFA2SP */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_PIF_A); + break; + case FIFO_CHANNEL_SP0_TO_IF1: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_PIF_B); /* SP_STR_MON_PORT_SP2PIFB */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_PIF_B); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_PIF_B); /* MOD_STR_MON_PORT_CELLS2PIFB */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_PIF_B); + break; + case FIFO_CHANNEL_IF1_TO_SP0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_PIF_B); /* MOD_STR_MON_PORT_PIFB2CELLS */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_PIF_B); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_PIF_B); /* SP_STR_MON_PORT_PIFB2SP */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + ISP_STR_MON_PORT_RCV_PIF_B); + break; + case FIFO_CHANNEL_SP0_TO_IF2: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_SIF); /* SP_STR_MON_PORT_SP2SIF */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_SIF); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_SIF); /* MOD_STR_MON_PORT_SP2SIF */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_SIF); + break; + case FIFO_CHANNEL_IF2_TO_SP0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_SIF); /* MOD_STR_MON_PORT_SIF2SP */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_SIF); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_SIF); /* SP_STR_MON_PORT_SIF2SP */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_SIF); + break; + case FIFO_CHANNEL_SP0_TO_DMA0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_DMA); /* SP_STR_MON_PORT_SP2DMA */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_DMA); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_DMA_FR_SP); /* MOD_STR_MON_PORT_SP2DMA */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_DMA_FR_SP); + break; + case FIFO_CHANNEL_DMA0_TO_SP0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_DMA2SP); /* MOD_STR_MON_PORT_DMA2SP */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_DMA2SP); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_DMA); /* SP_STR_MON_PORT_DMA2SP */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_DMA); + break; + case FIFO_CHANNEL_SP0_TO_GDC0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_B_IDX, + SP_STR_MON_PORT_B_SP2GDC1); + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_B_IDX, + SP_STR_MON_PORT_B_SP2GDC1); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_CELLS2GDC1); + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_CELLS2GDC1); + break; + case FIFO_CHANNEL_GDC0_TO_SP0: + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_GDC12CELLS); + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_GDC12CELLS); + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_B_IDX, + SP_STR_MON_PORT_B_GDC12SP); + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_B_IDX, + SP_STR_MON_PORT_B_GDC12SP); + break; + case FIFO_CHANNEL_SP0_TO_GDC1: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_B_IDX, + SP_STR_MON_PORT_B_SP2GDC2); + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_B_IDX, + SP_STR_MON_PORT_B_SP2GDC2); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_CELLS2GDC2); + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_CELLS2GDC2); + break; + case FIFO_CHANNEL_GDC1_TO_SP0: + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_GDC22CELLS); + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_GDC22CELLS); + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_B_IDX, + SP_STR_MON_PORT_B_GDC22SP); + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_B_IDX, + SP_STR_MON_PORT_B_GDC22SP); + break; + case FIFO_CHANNEL_SP0_TO_HOST0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_GPD); /* SP_STR_MON_PORT_SP2GPD */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_GPD); + { + hrt_data value = ia_css_device_load_uint32(0x0000000000380010ULL); + state->fifo_valid = !_hrt_get_bit(value, 0); + state->sink_accept = false; /* no monitor connected */ + } + break; + case FIFO_CHANNEL_HOST0_TO_SP0: + { + hrt_data value = ia_css_device_load_uint32(0x0000000000380018ULL); + state->fifo_valid = false; /* no monitor connected */ + state->sink_accept = !_hrt_get_bit(value, 0); + } + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_GPD); /* SP_STR_MON_PORT_FA2SP */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_GPD); + break; + case FIFO_CHANNEL_SP0_TO_STREAM2MEM0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_MC); /* SP_STR_MON_PORT_SP2MC */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SND_MC); + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_MC); /* MOD_STR_MON_PORT_SP2MC */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_RCV_MC); + break; + case FIFO_CHANNEL_STREAM2MEM0_TO_SP0: + state->fifo_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_MC); /* SP_STR_MON_PORT_MC2SP */ + state->sink_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_MOD_STREAM_STAT_IDX, + MOD_STR_MON_PORT_SND_MC); + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_MC); /* MOD_STR_MON_PORT_MC2SP */ + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_RCV_MC); + break; + case FIFO_CHANNEL_SP0_TO_INPUT_SYSTEM0: + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SP2ISYS); + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_SP2ISYS); + state->fifo_valid = false; + state->sink_accept = false; + break; + case FIFO_CHANNEL_INPUT_SYSTEM0_TO_SP0: + state->fifo_valid = false; + state->sink_accept = false; + state->src_valid = fifo_monitor_status_valid(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_ISYS2SP); + state->fifo_accept = fifo_monitor_status_accept(ID, + HIVE_GP_REGS_SP_STREAM_STAT_IDX, + SP_STR_MON_PORT_ISYS2SP); + break; + default: + assert(0); + break; + } + + return; +} + +void fifo_switch_get_state( + const fifo_monitor_ID_t ID, + const fifo_switch_t switch_id, + fifo_switch_state_t *state) +{ + hrt_data data = (hrt_data)-1; + + assert(ID == FIFO_MONITOR0_ID); + assert(switch_id < N_FIFO_SWITCH); + assert(state != NULL); + + (void)ID; + + data = gp_device_reg_load(GP_DEVICE0_ID, FIFO_SWITCH_ADDR[switch_id]); + + state->is_none = (data == HIVE_ISP_CSS_STREAM_SWITCH_NONE); + state->is_sp = (data == HIVE_ISP_CSS_STREAM_SWITCH_SP); + state->is_isp = (data == HIVE_ISP_CSS_STREAM_SWITCH_ISP); + + return; +} + +void fifo_monitor_get_state( + const fifo_monitor_ID_t ID, + fifo_monitor_state_t *state) +{ + fifo_channel_t ch_id; + fifo_switch_t sw_id; + + assert(ID < N_FIFO_MONITOR_ID); + assert(state != NULL); + + for (ch_id = 0; ch_id < N_FIFO_CHANNEL; ch_id++) { + fifo_channel_get_state(ID, ch_id, + &(state->fifo_channels[ch_id])); + } + + for (sw_id = 0; sw_id < N_FIFO_SWITCH; sw_id++) { + fifo_switch_get_state(ID, sw_id, + &(state->fifo_switches[sw_id])); + } + return; +} + +STORAGE_CLASS_INLINE bool fifo_monitor_status_valid ( + const fifo_monitor_ID_t ID, + const unsigned int reg, + const unsigned int port_id) +{ + hrt_data data = fifo_monitor_reg_load(ID, reg); + + return (data >> (((port_id * 2) + _hive_str_mon_valid_offset))) & 0x1; +} + +STORAGE_CLASS_INLINE bool fifo_monitor_status_accept( + const fifo_monitor_ID_t ID, + const unsigned int reg, + const unsigned int port_id) +{ + hrt_data data = fifo_monitor_reg_load(ID, reg); + + return (data >> (((port_id * 2) + _hive_str_mon_accept_offset))) & 0x1; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/fifo_monitor_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/fifo_monitor_local.h new file mode 100644 index 0000000000000000000000000000000000000000..ed2f8618178866fa8996024afa2fad842b992c7b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/fifo_monitor_local.h @@ -0,0 +1,99 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __FIFO_MONITOR_LOCAL_H_INCLUDED__ +#define __FIFO_MONITOR_LOCAL_H_INCLUDED__ + +#include +#include "fifo_monitor_global.h" + +#include "hive_isp_css_defs.h" /* ISP_STR_MON_PORT_SND_SP, ... */ + +#define _hive_str_mon_valid_offset 0 +#define _hive_str_mon_accept_offset 1 + +#define FIFO_CHANNEL_SP_VALID_MASK 0x55555555 +#define FIFO_CHANNEL_SP_VALID_B_MASK 0x00000055 +#define FIFO_CHANNEL_ISP_VALID_MASK 0x15555555 +#define FIFO_CHANNEL_MOD_VALID_MASK 0x55555555 + +typedef enum fifo_switch { + FIFO_SWITCH_IF, + FIFO_SWITCH_GDC0, + FIFO_SWITCH_GDC1, + N_FIFO_SWITCH +} fifo_switch_t; + +typedef enum fifo_channel { + FIFO_CHANNEL_ISP0_TO_SP0, + FIFO_CHANNEL_SP0_TO_ISP0, + FIFO_CHANNEL_ISP0_TO_IF0, + FIFO_CHANNEL_IF0_TO_ISP0, + FIFO_CHANNEL_ISP0_TO_IF1, + FIFO_CHANNEL_IF1_TO_ISP0, + FIFO_CHANNEL_ISP0_TO_DMA0, + FIFO_CHANNEL_DMA0_TO_ISP0, + FIFO_CHANNEL_ISP0_TO_GDC0, + FIFO_CHANNEL_GDC0_TO_ISP0, + FIFO_CHANNEL_ISP0_TO_GDC1, + FIFO_CHANNEL_GDC1_TO_ISP0, + FIFO_CHANNEL_ISP0_TO_HOST0, + FIFO_CHANNEL_HOST0_TO_ISP0, + FIFO_CHANNEL_SP0_TO_IF0, + FIFO_CHANNEL_IF0_TO_SP0, + FIFO_CHANNEL_SP0_TO_IF1, + FIFO_CHANNEL_IF1_TO_SP0, + FIFO_CHANNEL_SP0_TO_IF2, + FIFO_CHANNEL_IF2_TO_SP0, + FIFO_CHANNEL_SP0_TO_DMA0, + FIFO_CHANNEL_DMA0_TO_SP0, + FIFO_CHANNEL_SP0_TO_GDC0, + FIFO_CHANNEL_GDC0_TO_SP0, + FIFO_CHANNEL_SP0_TO_GDC1, + FIFO_CHANNEL_GDC1_TO_SP0, + FIFO_CHANNEL_SP0_TO_HOST0, + FIFO_CHANNEL_HOST0_TO_SP0, + FIFO_CHANNEL_SP0_TO_STREAM2MEM0, + FIFO_CHANNEL_STREAM2MEM0_TO_SP0, + FIFO_CHANNEL_SP0_TO_INPUT_SYSTEM0, + FIFO_CHANNEL_INPUT_SYSTEM0_TO_SP0, +/* + * No clue what this is + * + FIFO_CHANNEL_SP0_TO_IRQ0, + FIFO_CHANNEL_IRQ0_TO_SP0, + */ + N_FIFO_CHANNEL +} fifo_channel_t; + +struct fifo_channel_state_s { + bool src_valid; + bool fifo_accept; + bool fifo_valid; + bool sink_accept; +}; + +/* The switch is tri-state */ +struct fifo_switch_state_s { + bool is_none; + bool is_isp; + bool is_sp; +}; + +struct fifo_monitor_state_s { + struct fifo_channel_state_s fifo_channels[N_FIFO_CHANNEL]; + struct fifo_switch_state_s fifo_switches[N_FIFO_SWITCH]; +}; + +#endif /* __FIFO_MONITOR_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/fifo_monitor_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/fifo_monitor_private.h new file mode 100644 index 0000000000000000000000000000000000000000..618b2f7e9c757245f927e6064e9f97ed99939c55 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/fifo_monitor_private.h @@ -0,0 +1,79 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __FIFO_MONITOR_PRIVATE_H_INCLUDED__ +#define __FIFO_MONITOR_PRIVATE_H_INCLUDED__ + +#include "fifo_monitor_public.h" + +#define __INLINE_GP_DEVICE__ +#include "gp_device.h" + +#include "device_access.h" + +#include "assert_support.h" + +#ifdef __INLINE_FIFO_MONITOR__ +extern const unsigned int FIFO_SWITCH_ADDR[N_FIFO_SWITCH]; +#endif + +STORAGE_CLASS_FIFO_MONITOR_C void fifo_switch_set( + const fifo_monitor_ID_t ID, + const fifo_switch_t switch_id, + const hrt_data sel) +{ +assert(ID == FIFO_MONITOR0_ID); +assert(FIFO_MONITOR_BASE[ID] != (hrt_address)-1); +assert(switch_id < N_FIFO_SWITCH); + (void)ID; + + gp_device_reg_store(GP_DEVICE0_ID, FIFO_SWITCH_ADDR[switch_id], sel); + +return; +} + +STORAGE_CLASS_FIFO_MONITOR_C hrt_data fifo_switch_get( + const fifo_monitor_ID_t ID, + const fifo_switch_t switch_id) +{ +assert(ID == FIFO_MONITOR0_ID); +assert(FIFO_MONITOR_BASE[ID] != (hrt_address)-1); +assert(switch_id < N_FIFO_SWITCH); + (void)ID; + +return gp_device_reg_load(GP_DEVICE0_ID, FIFO_SWITCH_ADDR[switch_id]); +} + + +STORAGE_CLASS_FIFO_MONITOR_C void fifo_monitor_reg_store( + const fifo_monitor_ID_t ID, + const unsigned int reg, + const hrt_data value) +{ +assert(ID < N_FIFO_MONITOR_ID); +assert(FIFO_MONITOR_BASE[ID] != (hrt_address)-1); + ia_css_device_store_uint32(FIFO_MONITOR_BASE[ID] + reg*sizeof(hrt_data), value); +return; +} + +STORAGE_CLASS_FIFO_MONITOR_C hrt_data fifo_monitor_reg_load( + const fifo_monitor_ID_t ID, + const unsigned int reg) +{ +assert(ID < N_FIFO_MONITOR_ID); +assert(FIFO_MONITOR_BASE[ID] != (hrt_address)-1); +return ia_css_device_load_uint32(FIFO_MONITOR_BASE[ID] + reg*sizeof(hrt_data)); +} + +#endif /* __FIFO_MONITOR_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gdc.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gdc.c new file mode 100644 index 0000000000000000000000000000000000000000..69fa616889b1614515502d9794a18e3ff1fce060 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gdc.c @@ -0,0 +1,127 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* The name "gdc.h is already taken" */ +#include "gdc_device.h" + +#include "device_access.h" + +#include "assert_support.h" + +/* + * Local function declarations + */ +STORAGE_CLASS_INLINE void gdc_reg_store( + const gdc_ID_t ID, + const unsigned int reg, + const hrt_data value); + +STORAGE_CLASS_INLINE hrt_data gdc_reg_load( + const gdc_ID_t ID, + const unsigned int reg); + + +#ifndef __INLINE_GDC__ +#include "gdc_private.h" +#endif /* __INLINE_GDC__ */ + +/* + * Exported function implementations + */ +void gdc_lut_store( + const gdc_ID_t ID, + const int data[4][HRT_GDC_N]) +{ + unsigned int i, lut_offset = HRT_GDC_LUT_IDX; + + assert(ID < N_GDC_ID); + assert(HRT_GDC_LUT_COEFF_OFFSET <= (4*sizeof(hrt_data))); + + for (i = 0; i < HRT_GDC_N; i++) { + hrt_data entry_0 = data[0][i] & HRT_GDC_BCI_COEF_MASK; + hrt_data entry_1 = data[1][i] & HRT_GDC_BCI_COEF_MASK; + hrt_data entry_2 = data[2][i] & HRT_GDC_BCI_COEF_MASK; + hrt_data entry_3 = data[3][i] & HRT_GDC_BCI_COEF_MASK; + + hrt_data word_0 = entry_0 | + (entry_1 << HRT_GDC_LUT_COEFF_OFFSET); + hrt_data word_1 = entry_2 | + (entry_3 << HRT_GDC_LUT_COEFF_OFFSET); + + gdc_reg_store(ID, lut_offset++, word_0); + gdc_reg_store(ID, lut_offset++, word_1); + } +return; +} + +/* + * Input LUT format: + * c0[0-1023], c1[0-1023], c2[0-1023] c3[0-1023] + * + * Output LUT format (interleaved): + * c0[0], c1[0], c2[0], c3[0], c0[1], c1[1], c2[1], c3[1], .... + * c0[1023], c1[1023], c2[1023], c3[1023] + * + * The first format needs c0[0], c1[0] (which are 1024 words apart) + * to program gdc LUT registers. This makes it difficult to do piecemeal + * reads in SP side gdc_lut_store + * + * Interleaved format allows use of contiguous bytes to store into + * gdc LUT registers. + * + * See gdc_lut_store() definition in host/gdc.c vs sp/gdc_private.h + * + */ +void gdc_lut_convert_to_isp_format(const int in_lut[4][HRT_GDC_N], + int out_lut[4][HRT_GDC_N]) +{ + unsigned int i; + int *out = (int *)out_lut; + + for (i = 0; i < HRT_GDC_N; i++) { + out[0] = in_lut[0][i]; + out[1] = in_lut[1][i]; + out[2] = in_lut[2][i]; + out[3] = in_lut[3][i]; + out += 4; + } +} + +int gdc_get_unity( + const gdc_ID_t ID) +{ + assert(ID < N_GDC_ID); + (void)ID; +return (int)(1UL << HRT_GDC_FRAC_BITS); +} + + +/* + * Local function implementations + */ +STORAGE_CLASS_INLINE void gdc_reg_store( + const gdc_ID_t ID, + const unsigned int reg, + const hrt_data value) +{ + ia_css_device_store_uint32(GDC_BASE[ID] + reg*sizeof(hrt_data), value); +return; +} + +STORAGE_CLASS_INLINE hrt_data gdc_reg_load( + const gdc_ID_t ID, + const unsigned int reg) +{ +return ia_css_device_load_uint32(GDC_BASE[ID] + reg*sizeof(hrt_data)); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gdc_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gdc_local.h new file mode 100644 index 0000000000000000000000000000000000000000..0c6de867e012b7f6d9541210efe14ccdb4c29924 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gdc_local.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GDC_LOCAL_H_INCLUDED__ +#define __GDC_LOCAL_H_INCLUDED__ + +#include "gdc_global.h" + +#endif /* __GDC_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gdc_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gdc_private.h new file mode 100644 index 0000000000000000000000000000000000000000..f7dec75adf781257f16a3dc94d946bc48a04b28a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gdc_private.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GDC_PRIVATE_H_INCLUDED__ +#define __GDC_PRIVATE_H_INCLUDED__ + +#include "gdc_public.h" + +#endif /* __GDC_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_device.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_device.c new file mode 100644 index 0000000000000000000000000000000000000000..9a34ac052adf4dfc20e96f4296ab2e9bbdad219f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_device.c @@ -0,0 +1,108 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "assert_support.h" +#include "gp_device.h" + +#ifndef __INLINE_GP_DEVICE__ +#include "gp_device_private.h" +#endif /* __INLINE_GP_DEVICE__ */ + +void gp_device_get_state( + const gp_device_ID_t ID, + gp_device_state_t *state) +{ + assert(ID < N_GP_DEVICE_ID); + assert(state != NULL); + + state->syncgen_enable = gp_device_reg_load(ID, + _REG_GP_SYNCGEN_ENABLE_ADDR); + state->syncgen_free_running = gp_device_reg_load(ID, + _REG_GP_SYNCGEN_FREE_RUNNING_ADDR); + state->syncgen_pause = gp_device_reg_load(ID, + _REG_GP_SYNCGEN_PAUSE_ADDR); + state->nr_frames = gp_device_reg_load(ID, + _REG_GP_NR_FRAMES_ADDR); + state->syngen_nr_pix = gp_device_reg_load(ID, + _REG_GP_SYNGEN_NR_PIX_ADDR); + state->syngen_nr_pix = gp_device_reg_load(ID, + _REG_GP_SYNGEN_NR_PIX_ADDR); + state->syngen_nr_lines = gp_device_reg_load(ID, + _REG_GP_SYNGEN_NR_LINES_ADDR); + state->syngen_hblank_cycles = gp_device_reg_load(ID, + _REG_GP_SYNGEN_HBLANK_CYCLES_ADDR); + state->syngen_vblank_cycles = gp_device_reg_load(ID, + _REG_GP_SYNGEN_VBLANK_CYCLES_ADDR); + state->isel_sof = gp_device_reg_load(ID, + _REG_GP_ISEL_SOF_ADDR); + state->isel_eof = gp_device_reg_load(ID, + _REG_GP_ISEL_EOF_ADDR); + state->isel_sol = gp_device_reg_load(ID, + _REG_GP_ISEL_SOL_ADDR); + state->isel_eol = gp_device_reg_load(ID, + _REG_GP_ISEL_EOL_ADDR); + state->isel_lfsr_enable = gp_device_reg_load(ID, + _REG_GP_ISEL_LFSR_ENABLE_ADDR); + state->isel_lfsr_enable_b = gp_device_reg_load(ID, + _REG_GP_ISEL_LFSR_ENABLE_B_ADDR); + state->isel_lfsr_reset_value = gp_device_reg_load(ID, + _REG_GP_ISEL_LFSR_RESET_VALUE_ADDR); + state->isel_tpg_enable = gp_device_reg_load(ID, + _REG_GP_ISEL_TPG_ENABLE_ADDR); + state->isel_tpg_enable_b = gp_device_reg_load(ID, + _REG_GP_ISEL_TPG_ENABLE_B_ADDR); + state->isel_hor_cnt_mask = gp_device_reg_load(ID, + _REG_GP_ISEL_HOR_CNT_MASK_ADDR); + state->isel_ver_cnt_mask = gp_device_reg_load(ID, + _REG_GP_ISEL_VER_CNT_MASK_ADDR); + state->isel_xy_cnt_mask = gp_device_reg_load(ID, + _REG_GP_ISEL_XY_CNT_MASK_ADDR); + state->isel_hor_cnt_delta = gp_device_reg_load(ID, + _REG_GP_ISEL_HOR_CNT_DELTA_ADDR); + state->isel_ver_cnt_delta = gp_device_reg_load(ID, + _REG_GP_ISEL_VER_CNT_DELTA_ADDR); + state->isel_tpg_mode = gp_device_reg_load(ID, + _REG_GP_ISEL_TPG_MODE_ADDR); + state->isel_tpg_red1 = gp_device_reg_load(ID, + _REG_GP_ISEL_TPG_RED1_ADDR); + state->isel_tpg_green1 = gp_device_reg_load(ID, + _REG_GP_ISEL_TPG_GREEN1_ADDR); + state->isel_tpg_blue1 = gp_device_reg_load(ID, + _REG_GP_ISEL_TPG_BLUE1_ADDR); + state->isel_tpg_red2 = gp_device_reg_load(ID, + _REG_GP_ISEL_TPG_RED2_ADDR); + state->isel_tpg_green2 = gp_device_reg_load(ID, + _REG_GP_ISEL_TPG_GREEN2_ADDR); + state->isel_tpg_blue2 = gp_device_reg_load(ID, + _REG_GP_ISEL_TPG_BLUE2_ADDR); + state->isel_ch_id = gp_device_reg_load(ID, + _REG_GP_ISEL_CH_ID_ADDR); + state->isel_fmt_type = gp_device_reg_load(ID, + _REG_GP_ISEL_FMT_TYPE_ADDR); + state->isel_data_sel = gp_device_reg_load(ID, + _REG_GP_ISEL_DATA_SEL_ADDR); + state->isel_sband_sel = gp_device_reg_load(ID, + _REG_GP_ISEL_SBAND_SEL_ADDR); + state->isel_sync_sel = gp_device_reg_load(ID, + _REG_GP_ISEL_SYNC_SEL_ADDR); + state->syncgen_hor_cnt = gp_device_reg_load(ID, + _REG_GP_SYNCGEN_HOR_CNT_ADDR); + state->syncgen_ver_cnt = gp_device_reg_load(ID, + _REG_GP_SYNCGEN_VER_CNT_ADDR); + state->syncgen_frame_cnt = gp_device_reg_load(ID, + _REG_GP_SYNCGEN_FRAME_CNT_ADDR); + state->soft_reset = gp_device_reg_load(ID, + _REG_GP_SOFT_RESET_ADDR); +return; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_device_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_device_local.h new file mode 100644 index 0000000000000000000000000000000000000000..113d5ed32d42162fee9fdd78ce7c50fc20de3e3f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_device_local.h @@ -0,0 +1,143 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GP_DEVICE_LOCAL_H_INCLUDED__ +#define __GP_DEVICE_LOCAL_H_INCLUDED__ + +#include "gp_device_global.h" + +/* @ GP_REGS_BASE -> GP_DEVICE_BASE */ +#define _REG_GP_SDRAM_WAKEUP_ADDR 0x00 +#define _REG_GP_IDLE_ADDR 0x04 +/* #define _REG_GP_IRQ_REQ0_ADDR 0x08 */ +/* #define _REG_GP_IRQ_REQ1_ADDR 0x0C */ +#define _REG_GP_SP_STREAM_STAT_ADDR 0x10 +#define _REG_GP_SP_STREAM_STAT_B_ADDR 0x14 +#define _REG_GP_ISP_STREAM_STAT_ADDR 0x18 +#define _REG_GP_MOD_STREAM_STAT_ADDR 0x1C +#define _REG_GP_SP_STREAM_STAT_IRQ_COND_ADDR 0x20 +#define _REG_GP_SP_STREAM_STAT_B_IRQ_COND_ADDR 0x24 +#define _REG_GP_ISP_STREAM_STAT_IRQ_COND_ADDR 0x28 +#define _REG_GP_MOD_STREAM_STAT_IRQ_COND_ADDR 0x2C +#define _REG_GP_SP_STREAM_STAT_IRQ_ENABLE_ADDR 0x30 +#define _REG_GP_SP_STREAM_STAT_B_IRQ_ENABLE_ADDR 0x34 +#define _REG_GP_ISP_STREAM_STAT_IRQ_ENABLE_ADDR 0x38 +#define _REG_GP_MOD_STREAM_STAT_IRQ_ENABLE_ADDR 0x3C +/* +#define _REG_GP_SWITCH_IF_ADDR 0x40 +#define _REG_GP_SWITCH_GDC1_ADDR 0x44 +#define _REG_GP_SWITCH_GDC2_ADDR 0x48 +*/ +#define _REG_GP_SLV_REG_RST_ADDR 0x50 +#define _REG_GP_SWITCH_ISYS2401_ADDR 0x54 + +/* @ INPUT_FORMATTER_BASE -> GP_DEVICE_BASE */ +/* +#define _REG_GP_IFMT_input_switch_lut_reg0 0x00030800 +#define _REG_GP_IFMT_input_switch_lut_reg1 0x00030804 +#define _REG_GP_IFMT_input_switch_lut_reg2 0x00030808 +#define _REG_GP_IFMT_input_switch_lut_reg3 0x0003080C +#define _REG_GP_IFMT_input_switch_lut_reg4 0x00030810 +#define _REG_GP_IFMT_input_switch_lut_reg5 0x00030814 +#define _REG_GP_IFMT_input_switch_lut_reg6 0x00030818 +#define _REG_GP_IFMT_input_switch_lut_reg7 0x0003081C +#define _REG_GP_IFMT_input_switch_fsync_lut 0x00030820 +#define _REG_GP_IFMT_srst 0x00030824 +#define _REG_GP_IFMT_slv_reg_srst 0x00030828 +#define _REG_GP_IFMT_input_switch_ch_id_fmt_type 0x0003082C +*/ +/* @ GP_DEVICE_BASE */ +/* +#define _REG_GP_SYNCGEN_ENABLE_ADDR 0x00090000 +#define _REG_GP_SYNCGEN_FREE_RUNNING_ADDR 0x00090004 +#define _REG_GP_SYNCGEN_PAUSE_ADDR 0x00090008 +#define _REG_GP_NR_FRAMES_ADDR 0x0009000C +#define _REG_GP_SYNGEN_NR_PIX_ADDR 0x00090010 +#define _REG_GP_SYNGEN_NR_LINES_ADDR 0x00090014 +#define _REG_GP_SYNGEN_HBLANK_CYCLES_ADDR 0x00090018 +#define _REG_GP_SYNGEN_VBLANK_CYCLES_ADDR 0x0009001C +#define _REG_GP_ISEL_SOF_ADDR 0x00090020 +#define _REG_GP_ISEL_EOF_ADDR 0x00090024 +#define _REG_GP_ISEL_SOL_ADDR 0x00090028 +#define _REG_GP_ISEL_EOL_ADDR 0x0009002C +#define _REG_GP_ISEL_LFSR_ENABLE_ADDR 0x00090030 +#define _REG_GP_ISEL_LFSR_ENABLE_B_ADDR 0x00090034 +#define _REG_GP_ISEL_LFSR_RESET_VALUE_ADDR 0x00090038 +#define _REG_GP_ISEL_TPG_ENABLE_ADDR 0x0009003C +#define _REG_GP_ISEL_TPG_ENABLE_B_ADDR 0x00090040 +#define _REG_GP_ISEL_HOR_CNT_MASK_ADDR 0x00090044 +#define _REG_GP_ISEL_VER_CNT_MASK_ADDR 0x00090048 +#define _REG_GP_ISEL_XY_CNT_MASK_ADDR 0x0009004C +#define _REG_GP_ISEL_HOR_CNT_DELTA_ADDR 0x00090050 +#define _REG_GP_ISEL_VER_CNT_DELTA_ADDR 0x00090054 +#define _REG_GP_ISEL_TPG_MODE_ADDR 0x00090058 +#define _REG_GP_ISEL_TPG_RED1_ADDR 0x0009005C +#define _REG_GP_ISEL_TPG_GREEN1_ADDR 0x00090060 +#define _REG_GP_ISEL_TPG_BLUE1_ADDR 0x00090064 +#define _REG_GP_ISEL_TPG_RED2_ADDR 0x00090068 +#define _REG_GP_ISEL_TPG_GREEN2_ADDR 0x0009006C +#define _REG_GP_ISEL_TPG_BLUE2_ADDR 0x00090070 +#define _REG_GP_ISEL_CH_ID_ADDR 0x00090074 +#define _REG_GP_ISEL_FMT_TYPE_ADDR 0x00090078 +#define _REG_GP_ISEL_DATA_SEL_ADDR 0x0009007C +#define _REG_GP_ISEL_SBAND_SEL_ADDR 0x00090080 +#define _REG_GP_ISEL_SYNC_SEL_ADDR 0x00090084 +#define _REG_GP_SYNCGEN_HOR_CNT_ADDR 0x00090088 +#define _REG_GP_SYNCGEN_VER_CNT_ADDR 0x0009008C +#define _REG_GP_SYNCGEN_FRAME_CNT_ADDR 0x00090090 +#define _REG_GP_SOFT_RESET_ADDR 0x00090094 +*/ + +struct gp_device_state_s { + int syncgen_enable; + int syncgen_free_running; + int syncgen_pause; + int nr_frames; + int syngen_nr_pix; + int syngen_nr_lines; + int syngen_hblank_cycles; + int syngen_vblank_cycles; + int isel_sof; + int isel_eof; + int isel_sol; + int isel_eol; + int isel_lfsr_enable; + int isel_lfsr_enable_b; + int isel_lfsr_reset_value; + int isel_tpg_enable; + int isel_tpg_enable_b; + int isel_hor_cnt_mask; + int isel_ver_cnt_mask; + int isel_xy_cnt_mask; + int isel_hor_cnt_delta; + int isel_ver_cnt_delta; + int isel_tpg_mode; + int isel_tpg_red1; + int isel_tpg_green1; + int isel_tpg_blue1; + int isel_tpg_red2; + int isel_tpg_green2; + int isel_tpg_blue2; + int isel_ch_id; + int isel_fmt_type; + int isel_data_sel; + int isel_sband_sel; + int isel_sync_sel; + int syncgen_hor_cnt; + int syncgen_ver_cnt; + int syncgen_frame_cnt; + int soft_reset; +}; + +#endif /* __GP_DEVICE_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_device_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_device_private.h new file mode 100644 index 0000000000000000000000000000000000000000..bce1fdf79114594501ac0cdcf848ae0c67d53921 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_device_private.h @@ -0,0 +1,46 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GP_DEVICE_PRIVATE_H_INCLUDED__ +#define __GP_DEVICE_PRIVATE_H_INCLUDED__ + +#include "gp_device_public.h" + +#include "device_access.h" + +#include "assert_support.h" + +STORAGE_CLASS_GP_DEVICE_C void gp_device_reg_store( + const gp_device_ID_t ID, + const unsigned int reg_addr, + const hrt_data value) +{ +assert(ID < N_GP_DEVICE_ID); +assert(GP_DEVICE_BASE[ID] != (hrt_address)-1); +assert((reg_addr % sizeof(hrt_data)) == 0); + ia_css_device_store_uint32(GP_DEVICE_BASE[ID] + reg_addr, value); +return; +} + +STORAGE_CLASS_GP_DEVICE_C hrt_data gp_device_reg_load( + const gp_device_ID_t ID, + const hrt_address reg_addr) +{ +assert(ID < N_GP_DEVICE_ID); +assert(GP_DEVICE_BASE[ID] != (hrt_address)-1); +assert((reg_addr % sizeof(hrt_data)) == 0); +return ia_css_device_load_uint32(GP_DEVICE_BASE[ID] + reg_addr); +} + +#endif /* __GP_DEVICE_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_timer.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_timer.c new file mode 100644 index 0000000000000000000000000000000000000000..5a4eabf79ee238db51b16e51d88a0e259fab91e9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_timer.c @@ -0,0 +1,70 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include /*uint32_t */ +#include "gp_timer.h" /*system_local.h, + gp_timer_public.h*/ + +#ifndef __INLINE_GP_TIMER__ +#include "gp_timer_private.h" /*device_access.h*/ +#endif /* __INLINE_GP_TIMER__ */ +#include "system_local.h" + +/** FIXME: not sure if reg_load(), reg_store() should be API. + */ +static uint32_t +gp_timer_reg_load(uint32_t reg); + +static void +gp_timer_reg_store(uint32_t reg, uint32_t value); + +uint32_t +gp_timer_reg_load(uint32_t reg) +{ + return ia_css_device_load_uint32( + GP_TIMER_BASE + + (reg * sizeof(uint32_t))); +} + +static void +gp_timer_reg_store(uint32_t reg, uint32_t value) +{ + ia_css_device_store_uint32((GP_TIMER_BASE + + (reg * sizeof(uint32_t))), + value); +} + +void gp_timer_init(gp_timer_ID_t ID) +{ + /* set_overall_enable*/ + gp_timer_reg_store(_REG_GP_TIMER_OVERALL_ENABLE, 1); + + /*set enable*/ + gp_timer_reg_store(_REG_GP_TIMER_ENABLE_ID(ID), 1); + + /* set signal select */ + gp_timer_reg_store(_REG_GP_TIMER_SIGNAL_SELECT_ID(ID), GP_TIMER_SIGNAL_SELECT); + + /*set count type */ + gp_timer_reg_store(_REG_GP_TIMER_COUNT_TYPE_ID(ID), GP_TIMER_COUNT_TYPE_LOW); + + /*reset gp timer */ + gp_timer_reg_store(_REG_GP_TIMER_RESET_REG, 0xFF); +} + +uint32_t +gp_timer_read(gp_timer_ID_t ID) +{ + return gp_timer_reg_load(_REG_GP_TIMER_VALUE_ID(ID)); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_timer_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_timer_local.h new file mode 100644 index 0000000000000000000000000000000000000000..19ce35d87291e3a8b20910029bc1f9e2b4cacf2d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_timer_local.h @@ -0,0 +1,45 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GP_TIMER_LOCAL_H_INCLUDED__ +#define __GP_TIMER_LOCAL_H_INCLUDED__ + +#include "gp_timer_global.h" /*GP_TIMER_SEL + GP_TIMER_SIGNAL_SELECT*/ + +#include "gp_timer_defs.h" /*HIVE_GP_TIMER_xxx registers*/ +#include "hive_isp_css_defs.h" /*HIVE_GP_TIMER_NUM_COUNTERS + HIVE_GP_TIMER_NUM_IRQS*/ + +#define _REG_GP_TIMER_RESET_REG HIVE_GP_TIMER_RESET_REG_IDX +#define _REG_GP_TIMER_OVERALL_ENABLE HIVE_GP_TIMER_OVERALL_ENABLE_REG_IDX + +/*Register offsets for timers [1,7] can be obtained + * by adding (GP_TIMERx_ID * sizeof(uint32_t))*/ +#define _REG_GP_TIMER_ENABLE_ID(timer_id) HIVE_GP_TIMER_ENABLE_REG_IDX(timer_id) +#define _REG_GP_TIMER_VALUE_ID(timer_id) HIVE_GP_TIMER_VALUE_REG_IDX(timer_id, HIVE_GP_TIMER_NUM_COUNTERS) +#define _REG_GP_TIMER_COUNT_TYPE_ID(timer_id) HIVE_GP_TIMER_COUNT_TYPE_REG_IDX(timer_id, HIVE_GP_TIMER_NUM_COUNTERS) +#define _REG_GP_TIMER_SIGNAL_SELECT_ID(timer_id) HIVE_GP_TIMER_SIGNAL_SELECT_REG_IDX(timer_id, HIVE_GP_TIMER_NUM_COUNTERS) + + +#define _REG_GP_TIMER_IRQ_TRIGGER_VALUE_ID(irq_id) HIVE_GP_TIMER_IRQ_TRIGGER_VALUE_REG_IDX(irq_id, HIVE_GP_TIMER_NUM_COUNTERS) + +#define _REG_GP_TIMER_IRQ_TIMER_SELECT_ID(irq_id) \ + HIVE_GP_TIMER_IRQ_TIMER_SELECT_REG_IDX(irq_id, HIVE_GP_TIMER_NUM_COUNTERS, HIVE_GP_TIMER_NUM_IRQS) + +#define _REG_GP_TIMER_IRQ_ENABLE_ID(irq_id) \ + HIVE_GP_TIMER_IRQ_ENABLE_REG_IDX(irq_id, HIVE_GP_TIMER_NUM_COUNTERS, HIVE_GP_TIMER_NUM_IRQS) + + +#endif /*__GP_TIMER_LOCAL_H_INCLUDED__*/ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_timer_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_timer_private.h new file mode 100644 index 0000000000000000000000000000000000000000..705be5e5cc7040d7a07e737e675eaf32ba3d00b9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gp_timer_private.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GP_TIMER_PRIVATE_H_INCLUDED__ +#define __GP_TIMER_PRIVATE_H_INCLUDED__ + +#include "gp_timer_public.h" +#include "device_access.h" +#include "assert_support.h" + +#endif /* __GP_TIMER_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gpio_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gpio_local.h new file mode 100644 index 0000000000000000000000000000000000000000..f4652b79734dab73e35d55696b64bb5da7572404 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gpio_local.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GPIO_LOCAL_H_INCLUDED__ +#define __GPIO_LOCAL_H_INCLUDED__ + +#include "gpio_global.h" + +#endif /* __GPIO_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gpio_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gpio_private.h new file mode 100644 index 0000000000000000000000000000000000000000..6ace2184b5223017b8ce0c077e6968167b69d46f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/gpio_private.h @@ -0,0 +1,44 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GPIO_PRIVATE_H_INCLUDED__ +#define __GPIO_PRIVATE_H_INCLUDED__ + +#include "gpio_public.h" + +#include "device_access.h" + +#include "assert_support.h" + +STORAGE_CLASS_GPIO_C void gpio_reg_store( + const gpio_ID_t ID, + const unsigned int reg, + const hrt_data value) +{ +OP___assert(ID < N_GPIO_ID); +OP___assert(GPIO_BASE[ID] != (hrt_address)-1); + ia_css_device_store_uint32(GPIO_BASE[ID] + reg*sizeof(hrt_data), value); +return; +} + +STORAGE_CLASS_GPIO_C hrt_data gpio_reg_load( + const gpio_ID_t ID, + const unsigned int reg) +{ +OP___assert(ID < N_GPIO_ID); +OP___assert(GPIO_BASE[ID] != (hrt_address)-1); +return ia_css_device_load_uint32(GPIO_BASE[ID] + reg*sizeof(hrt_data)); +} + +#endif /* __GPIO_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/hive_isp_css_ddr_hrt_modified.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/hive_isp_css_ddr_hrt_modified.h new file mode 100644 index 0000000000000000000000000000000000000000..39785aa214590111bf4520ecea3277fc1ac38109 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/hive_isp_css_ddr_hrt_modified.h @@ -0,0 +1,148 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _hive_isp_css_ddr_hrt_modified_h_ +#define _hive_isp_css_ddr_hrt_modified_h_ + +#include + +/* This function reads an image from DDR and stores it in the img_buf array + that has been allocated by the caller. + The specifics of how the pixels are stored into DDR by the DMA are taken + into account (bits padded to a width of 256, depending on the number of + elements per ddr word). + The DMA specific parameters give to this function (elems_per_xword and sign_extend) + should correspond to those given to the DMA engine. + The address is a virtual address which will be translated to a physical address before + data is loaded from or stored to that address. + + The return value is 0 in case of success and 1 in case of failure. + */ +unsigned int +hrt_isp_css_read_image_from_ddr( + unsigned short *img_buf, + unsigned int width, + unsigned int height, + unsigned int elems_per_xword, + unsigned int sign_extend, + hmm_ptr virt_addr); + +/* This function writes an image to DDR, keeping the same aspects into account as the read_image function + above. */ +unsigned int +hrt_isp_css_write_image_to_ddr( + const unsigned short *img_buf, + unsigned int width, + unsigned int height, + unsigned int elems_per_xword, + unsigned int sign_extend, + hmm_ptr virt_addr); + +/* return the size in bytes of an image (frame or plane). */ +unsigned int +hrt_isp_css_sizeof_image_in_ddr( + unsigned int width, + unsigned int height, + unsigned int bits_per_element); + +unsigned int +hrt_isp_css_stride_of_image_in_ddr( + unsigned int width, + unsigned int bits_per_element); + +hmm_ptr +hrt_isp_css_alloc_image_in_ddr( + unsigned int width, + unsigned int height, + unsigned int elems_per_xword); + +hmm_ptr +hrt_isp_css_calloc_image_in_ddr( + unsigned int width, + unsigned int height, + unsigned int elems_per_xword); + +#ifndef HIVE_ISP_NO_GDC +#include "gdc_v2_defs.h" + +hmm_ptr +hrt_isp_css_alloc_gdc_lut_in_ddr(void); + +void +hrt_isp_css_write_gdc_lut_to_ddr( + short values[4][HRT_GDC_N], + hmm_ptr virt_addr); +#endif + +#ifdef _HIVE_ISP_CSS_FPGA_SYSTEM +hmm_ptr +hrt_isp_css_alloc_image_for_display( + unsigned int width, + unsigned int height, + unsigned int elems_per_xword); + +hmm_ptr +hrt_isp_css_calloc_image_for_display( + unsigned int width, + unsigned int height, + unsigned int elems_per_xword); +#endif + +/* New set of functions, these do not require the elems_per_xword, but use bits_per_element instead, + this way the user does not need to know about the width of a DDR word. */ +unsigned int +hrt_isp_css_read_unsigned( + unsigned short *target, + unsigned int width, + unsigned int height, + unsigned int source_bits_per_element, + hmm_ptr source); + +unsigned int +hrt_isp_css_read_signed( + short *target, + unsigned int width, + unsigned int height, + unsigned int source_bits_per_element, + hmm_ptr source); + +unsigned int +hrt_isp_css_write_unsigned( + const unsigned short *source, + unsigned int width, + unsigned int height, + unsigned int target_bits_per_element, + hmm_ptr target); + +unsigned int +hrt_isp_css_write_signed( + const short *source, + unsigned int width, + unsigned int height, + unsigned int target_bits_per_element, + hmm_ptr target); + +hmm_ptr +hrt_isp_css_alloc( + unsigned int width, + unsigned int height, + unsigned int bits_per_element); + +hmm_ptr +hrt_isp_css_calloc( + unsigned int width, + unsigned int height, + unsigned int bits_per_element); + +#endif /* _hive_isp_css_ddr_hrt_modified_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/hive_isp_css_hrt_modified.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/hive_isp_css_hrt_modified.h new file mode 100644 index 0000000000000000000000000000000000000000..603ef1d2c5ef352aef6f7304cb0e14fdd1e10108 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/hive_isp_css_hrt_modified.h @@ -0,0 +1,95 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _hive_isp_css_hrt_h +#define _hive_isp_css_hrt_h + +#include "system_types.h" + +#include "hive_isp_css_host_ids_hrt.h" +#include "hive_isp_css_defs.h" + +#ifdef HRT_ISP_CSS_CUSTOM_HOST +#ifndef HRT_USE_VIR_ADDRS +#define HRT_USE_VIR_ADDRS +#endif +/*#include "hive_isp_css_custom_host_hrt.h"*/ +#endif + +#include +#include +#include +#ifdef _HIVE_ISP_CSS_FPGA_SYSTEM + #include + #include + #include + #include + #include + #include +#define hrt_gdc_slave_port(gdc_id) HRTCAT(gdc_id,_sl_in) + #include + #include + #include "isp_css_dev_flash_hrt.h" + #include "isp_css_dev_display_hrt.h" + #include "isp_css_dev_i2c_hrt.h" + #include "isp_css_dev_tb.h" +#else /* CSS ASIC system */ + #include +// #include +// #include + /* insert idle signal clearing and setting around hrt_main */ + #if !defined(HRT_HW) || defined(HRT_ISP_CSS_INSERT_IDLE_SIGNAL) + #define hrt_main _hrt_isp_css_main + #endif + #ifdef _HIVE_ISP_CSS_SPECMAN_SYSTEM + #include "hive_isp_css_2400_specman_system.h" + #else +#if defined(IS_ISP_2400_MAMOIADA_SYSTEM) + #include "hive_isp_css_2400_system.h" +#elif defined(IS_ISP_2401_MAMOIADA_SYSTEM) + #include "hive_isp_css_2401_system.h" +#else +#error "hive_isp_css_hrt_modified.h: SYSTEM must be one of {2400_MAMOIADA_SYSTEM, 2401_MAMOIADA_SYSTEM}" +#endif + #endif +#endif /* _HIVE_ISP_CSS_FPGA_SYSTEM */ +#include +#include +#include +#include + +#include "hive_isp_css_sdram_wakeup_hrt.h" +#include "hive_isp_css_idle_signal_hrt.h" +#include "hive_isp_css_sp_hrt.h" +#include "hive_isp_css_isp_hrt.h" +#include "hive_isp_css_streaming_to_mipi_hrt.h" +#include "hive_isp_css_testbench_hrt.h" +#include "hive_isp_css_streaming_monitors_hrt.h" +#include "hive_isp_css_gp_regs_hrt.h" +#if defined(IS_ISP_2400_MAMOIADA_SYSTEM) +#include "hive_isp_css_irq_hrt.h" +#elif defined(IS_ISP_2401_MAMOIADA_SYSTEM) +#include "hive_isp_css_2401_irq_hrt.h" +#else +#error "hive_isp_css_hrt_modified.h: SYSTEM must be one of {2400_MAMOIADA_SYSTEM, 2401_MAMOIADA_SYSTEM}" +#endif + +#include "hive_isp_css_stream_switch_hrt.h" + +#include "hive_isp_css_ddr_hrt_modified.h" +#include "hive_isp_css_dma_set_hrt.h" + +#define HIVE_ISP_CSS_NO_STREAM_SWITCH 1 + +#endif /* _hive_isp_css_hrt_h */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/hmem.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/hmem.c new file mode 100644 index 0000000000000000000000000000000000000000..e48f180c9507aefb289c64213329f2c13a19104f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/hmem.c @@ -0,0 +1,19 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "hmem.h" + +#ifndef __INLINE_HMEM__ +#include "hmem_private.h" +#endif /* __INLINE_HMEM__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/hmem_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/hmem_local.h new file mode 100644 index 0000000000000000000000000000000000000000..499f55f07253c84fce30518a8e9a826eb3a24f68 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/hmem_local.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __HMEM_LOCAL_H_INCLUDED__ +#define __HMEM_LOCAL_H_INCLUDED__ + +#include "hmem_global.h" + +#endif /* __HMEM_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/hmem_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/hmem_private.h new file mode 100644 index 0000000000000000000000000000000000000000..2b636e0e64824768ca4ec159e1f8c703c936c5f1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/hmem_private.h @@ -0,0 +1,30 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __HMEM_PRIVATE_H_INCLUDED__ +#define __HMEM_PRIVATE_H_INCLUDED__ + +#include "hmem_public.h" + +#include "assert_support.h" + +STORAGE_CLASS_HMEM_C size_t sizeof_hmem( + const hmem_ID_t ID) +{ +assert(ID < N_HMEM_ID); + (void)ID; +return HMEM_SIZE*sizeof(hmem_data_t); +} + +#endif /* __HMEM_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/input_formatter.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/input_formatter.c new file mode 100644 index 0000000000000000000000000000000000000000..b92e3ad8306df59fa29f30c174dc71adfb528d99 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/input_formatter.c @@ -0,0 +1,234 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "system_global.h" + +#ifdef USE_INPUT_SYSTEM_VERSION_2 + +#include "input_formatter.h" +#include +#include "gp_device.h" + +#include "assert_support.h" + +#ifndef __INLINE_INPUT_FORMATTER__ +#include "input_formatter_private.h" +#endif /* __INLINE_INPUT_FORMATTER__ */ + +const hrt_address HIVE_IF_SRST_ADDRESS[N_INPUT_FORMATTER_ID] = { + INPUT_FORMATTER0_SRST_OFFSET, + INPUT_FORMATTER1_SRST_OFFSET, + INPUT_FORMATTER2_SRST_OFFSET, + INPUT_FORMATTER3_SRST_OFFSET}; + +const hrt_data HIVE_IF_SRST_MASK[N_INPUT_FORMATTER_ID] = { + INPUT_FORMATTER0_SRST_MASK, + INPUT_FORMATTER1_SRST_MASK, + INPUT_FORMATTER2_SRST_MASK, + INPUT_FORMATTER3_SRST_MASK}; + +const uint8_t HIVE_IF_SWITCH_CODE[N_INPUT_FORMATTER_ID] = { + HIVE_INPUT_SWITCH_SELECT_IF_PRIM, + HIVE_INPUT_SWITCH_SELECT_IF_PRIM, + HIVE_INPUT_SWITCH_SELECT_IF_SEC, + HIVE_INPUT_SWITCH_SELECT_STR_TO_MEM}; + +/* MW Should be part of system_global.h, where we have the main enumeration */ +const bool HIVE_IF_BIN_COPY[N_INPUT_FORMATTER_ID] = { + false, false, false, true}; + +void input_formatter_rst( + const input_formatter_ID_t ID) +{ + hrt_address addr; + hrt_data rst; + + assert(ID < N_INPUT_FORMATTER_ID); + + addr = HIVE_IF_SRST_ADDRESS[ID]; + rst = HIVE_IF_SRST_MASK[ID]; + + /* TEMPORARY HACK: THIS RESET BREAKS THE METADATA FEATURE + * WICH USES THE STREAM2MEMRY BLOCK. + * MUST BE FIXED PROPERLY + */ + if (!HIVE_IF_BIN_COPY[ID]) { + input_formatter_reg_store(ID, addr, rst); + } + + return; +} + +unsigned int input_formatter_get_alignment( + const input_formatter_ID_t ID) +{ + assert(ID < N_INPUT_FORMATTER_ID); + + return input_formatter_alignment[ID]; +} + +void input_formatter_set_fifo_blocking_mode( + const input_formatter_ID_t ID, + const bool enable) +{ + assert(ID < N_INPUT_FORMATTER_ID); + + /* cnd_input_formatter_reg_store() */ + if (!HIVE_IF_BIN_COPY[ID]) { + input_formatter_reg_store(ID, + HIVE_IF_BLOCK_FIFO_NO_REQ_ADDRESS, enable); + } + return; +} + +void input_formatter_get_switch_state( + const input_formatter_ID_t ID, + input_formatter_switch_state_t *state) +{ + assert(ID < N_INPUT_FORMATTER_ID); + assert(state != NULL); + + /* We'll change this into an intelligent function to get switch info per IF */ + (void)ID; + + state->if_input_switch_lut_reg[0] = gp_device_reg_load(GP_DEVICE0_ID, _REG_GP_IFMT_input_switch_lut_reg0); + state->if_input_switch_lut_reg[1] = gp_device_reg_load(GP_DEVICE0_ID, _REG_GP_IFMT_input_switch_lut_reg1); + state->if_input_switch_lut_reg[2] = gp_device_reg_load(GP_DEVICE0_ID, _REG_GP_IFMT_input_switch_lut_reg2); + state->if_input_switch_lut_reg[3] = gp_device_reg_load(GP_DEVICE0_ID, _REG_GP_IFMT_input_switch_lut_reg3); + state->if_input_switch_lut_reg[4] = gp_device_reg_load(GP_DEVICE0_ID, _REG_GP_IFMT_input_switch_lut_reg4); + state->if_input_switch_lut_reg[5] = gp_device_reg_load(GP_DEVICE0_ID, _REG_GP_IFMT_input_switch_lut_reg5); + state->if_input_switch_lut_reg[6] = gp_device_reg_load(GP_DEVICE0_ID, _REG_GP_IFMT_input_switch_lut_reg6); + state->if_input_switch_lut_reg[7] = gp_device_reg_load(GP_DEVICE0_ID, _REG_GP_IFMT_input_switch_lut_reg7); + state->if_input_switch_fsync_lut = gp_device_reg_load(GP_DEVICE0_ID, _REG_GP_IFMT_input_switch_fsync_lut); + state->if_input_switch_ch_id_fmt_type = gp_device_reg_load(GP_DEVICE0_ID, _REG_GP_IFMT_input_switch_ch_id_fmt_type); + + return; +} + +void input_formatter_get_state( + const input_formatter_ID_t ID, + input_formatter_state_t *state) +{ + assert(ID < N_INPUT_FORMATTER_ID); + assert(state != NULL); +/* + state->reset = input_formatter_reg_load(ID, + HIVE_IF_RESET_ADDRESS); + */ + state->start_line = input_formatter_reg_load(ID, + HIVE_IF_START_LINE_ADDRESS); + state->start_column = input_formatter_reg_load(ID, + HIVE_IF_START_COLUMN_ADDRESS); + state->cropped_height = input_formatter_reg_load(ID, + HIVE_IF_CROPPED_HEIGHT_ADDRESS); + state->cropped_width = input_formatter_reg_load(ID, + HIVE_IF_CROPPED_WIDTH_ADDRESS); + state->ver_decimation = input_formatter_reg_load(ID, + HIVE_IF_VERTICAL_DECIMATION_ADDRESS); + state->hor_decimation = input_formatter_reg_load(ID, + HIVE_IF_HORIZONTAL_DECIMATION_ADDRESS); + state->hor_deinterleaving = input_formatter_reg_load(ID, + HIVE_IF_H_DEINTERLEAVING_ADDRESS); + state->left_padding = input_formatter_reg_load(ID, + HIVE_IF_LEFTPADDING_WIDTH_ADDRESS); + state->eol_offset = input_formatter_reg_load(ID, + HIVE_IF_END_OF_LINE_OFFSET_ADDRESS); + state->vmem_start_address = input_formatter_reg_load(ID, + HIVE_IF_VMEM_START_ADDRESS_ADDRESS); + state->vmem_end_address = input_formatter_reg_load(ID, + HIVE_IF_VMEM_END_ADDRESS_ADDRESS); + state->vmem_increment = input_formatter_reg_load(ID, + HIVE_IF_VMEM_INCREMENT_ADDRESS); + state->is_yuv420 = input_formatter_reg_load(ID, + HIVE_IF_YUV_420_FORMAT_ADDRESS); + state->vsync_active_low = input_formatter_reg_load(ID, + HIVE_IF_VSYNCK_ACTIVE_LOW_ADDRESS); + state->hsync_active_low = input_formatter_reg_load(ID, + HIVE_IF_HSYNCK_ACTIVE_LOW_ADDRESS); + state->allow_fifo_overflow = input_formatter_reg_load(ID, + HIVE_IF_ALLOW_FIFO_OVERFLOW_ADDRESS); + state->block_fifo_when_no_req = input_formatter_reg_load(ID, + HIVE_IF_BLOCK_FIFO_NO_REQ_ADDRESS); + state->ver_deinterleaving = input_formatter_reg_load(ID, + HIVE_IF_V_DEINTERLEAVING_ADDRESS); +/* FSM */ + state->fsm_sync_status = input_formatter_reg_load(ID, + HIVE_IF_FSM_SYNC_STATUS); + state->fsm_sync_counter = input_formatter_reg_load(ID, + HIVE_IF_FSM_SYNC_COUNTER); + state->fsm_crop_status = input_formatter_reg_load(ID, + HIVE_IF_FSM_CROP_STATUS); + state->fsm_crop_line_counter = input_formatter_reg_load(ID, + HIVE_IF_FSM_CROP_LINE_COUNTER); + state->fsm_crop_pixel_counter = input_formatter_reg_load(ID, + HIVE_IF_FSM_CROP_PIXEL_COUNTER); + state->fsm_deinterleaving_index = input_formatter_reg_load(ID, + HIVE_IF_FSM_DEINTERLEAVING_IDX); + state->fsm_dec_h_counter = input_formatter_reg_load(ID, + HIVE_IF_FSM_DECIMATION_H_COUNTER); + state->fsm_dec_v_counter = input_formatter_reg_load(ID, + HIVE_IF_FSM_DECIMATION_V_COUNTER); + state->fsm_dec_block_v_counter = input_formatter_reg_load(ID, + HIVE_IF_FSM_DECIMATION_BLOCK_V_COUNTER); + state->fsm_padding_status = input_formatter_reg_load(ID, + HIVE_IF_FSM_PADDING_STATUS); + state->fsm_padding_elem_counter = input_formatter_reg_load(ID, + HIVE_IF_FSM_PADDING_ELEMENT_COUNTER); + state->fsm_vector_support_error = input_formatter_reg_load(ID, + HIVE_IF_FSM_VECTOR_SUPPORT_ERROR); + state->fsm_vector_buffer_full = input_formatter_reg_load(ID, + HIVE_IF_FSM_VECTOR_SUPPORT_BUFF_FULL); + state->vector_support = input_formatter_reg_load(ID, + HIVE_IF_FSM_VECTOR_SUPPORT); + state->sensor_data_lost = input_formatter_reg_load(ID, + HIVE_IF_FIFO_SENSOR_STATUS); + + return; +} + +void input_formatter_bin_get_state( + const input_formatter_ID_t ID, + input_formatter_bin_state_t *state) +{ + assert(ID < N_INPUT_FORMATTER_ID); + assert(state != NULL); + +#ifdef HRT_CSIM + /* The compiled simulator mode of the input formatter + * does not support reading from the write-only reset + * register. */ + state->reset = 0; +#else + state->reset = input_formatter_reg_load(ID, + HIVE_STR2MEM_SOFT_RESET_REG_ADDRESS); +#endif + state->input_endianness = input_formatter_reg_load(ID, + HIVE_STR2MEM_INPUT_ENDIANNESS_REG_ADDRESS); + state->output_endianness = input_formatter_reg_load(ID, + HIVE_STR2MEM_OUTPUT_ENDIANNESS_REG_ADDRESS); + state->bitswap = input_formatter_reg_load(ID, + HIVE_STR2MEM_BIT_SWAPPING_REG_ADDRESS); + state->block_synch = input_formatter_reg_load(ID, + HIVE_STR2MEM_BLOCK_SYNC_LEVEL_REG_ADDRESS); + state->packet_synch = input_formatter_reg_load(ID, + HIVE_STR2MEM_PACKET_SYNC_LEVEL_REG_ADDRESS); + state->readpostwrite_synch = input_formatter_reg_load(ID, + HIVE_STR2MEM_READ_POST_WRITE_SYNC_ENABLE_REG_ADDRESS); + state->is_2ppc = input_formatter_reg_load(ID, + HIVE_STR2MEM_DUAL_BYTE_INPUTS_ENABLED_REG_ADDRESS); + state->en_status_update = input_formatter_reg_load(ID, + HIVE_STR2MEM_EN_STAT_UPDATE_ADDRESS); + return; +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/input_formatter_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/input_formatter_local.h new file mode 100644 index 0000000000000000000000000000000000000000..3e00b5e6bad7b30d6965a7af18dca6e171d4463e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/input_formatter_local.h @@ -0,0 +1,120 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_FORMATTER_LOCAL_H_INCLUDED__ +#define __INPUT_FORMATTER_LOCAL_H_INCLUDED__ + +#include "input_formatter_global.h" + +#include "isp.h" /* ISP_VEC_ALIGN */ + +typedef struct input_formatter_switch_state_s input_formatter_switch_state_t; +typedef struct input_formatter_state_s input_formatter_state_t; +typedef struct input_formatter_bin_state_s input_formatter_bin_state_t; + +#define HIVE_IF_FSM_SYNC_STATUS 0x100 +#define HIVE_IF_FSM_SYNC_COUNTER 0x104 +#define HIVE_IF_FSM_DEINTERLEAVING_IDX 0x114 +#define HIVE_IF_FSM_DECIMATION_H_COUNTER 0x118 +#define HIVE_IF_FSM_DECIMATION_V_COUNTER 0x11C +#define HIVE_IF_FSM_DECIMATION_BLOCK_V_COUNTER 0x120 +#define HIVE_IF_FSM_PADDING_STATUS 0x124 +#define HIVE_IF_FSM_PADDING_ELEMENT_COUNTER 0x128 +#define HIVE_IF_FSM_VECTOR_SUPPORT_ERROR 0x12C +#define HIVE_IF_FSM_VECTOR_SUPPORT_BUFF_FULL 0x130 +#define HIVE_IF_FSM_VECTOR_SUPPORT 0x134 +#define HIVE_IF_FIFO_SENSOR_STATUS 0x138 + +/* + * The switch LUT's coding defines a sink for each + * single channel ID + channel format type. Conversely + * the sink (i.e. an input formatter) can be reached + * from multiple channel & format type combinations + * + * LUT[0,1] channel=0, format type {0,1,...31} + * LUT[2,3] channel=1, format type {0,1,...31} + * LUT[4,5] channel=2, format type {0,1,...31} + * LUT[6,7] channel=3, format type {0,1,...31} + * + * Each register hold 16 2-bit fields encoding the sink + * {0,1,2,3}, "0" means unconnected. + * + * The single FSYNCH register uses four 3-bit fields of 1-hot + * encoded sink information, "0" means unconnected. + * + * The encoding is redundant. The FSYNCH setting will connect + * a channel to a sink. At that point the LUT's belonging to + * that channel can be directed to another sink. Thus the data + * goes to another place than the synch + */ +struct input_formatter_switch_state_s { + int if_input_switch_lut_reg[8]; + int if_input_switch_fsync_lut; + int if_input_switch_ch_id_fmt_type; + bool if_input_switch_map[HIVE_SWITCH_N_CHANNELS][HIVE_SWITCH_N_FORMATTYPES]; +}; + +struct input_formatter_state_s { +/* int reset; */ + int start_line; + int start_column; + int cropped_height; + int cropped_width; + int ver_decimation; + int hor_decimation; + int ver_deinterleaving; + int hor_deinterleaving; + int left_padding; + int eol_offset; + int vmem_start_address; + int vmem_end_address; + int vmem_increment; + int is_yuv420; + int vsync_active_low; + int hsync_active_low; + int allow_fifo_overflow; + int block_fifo_when_no_req; + int fsm_sync_status; + int fsm_sync_counter; + int fsm_crop_status; + int fsm_crop_line_counter; + int fsm_crop_pixel_counter; + int fsm_deinterleaving_index; + int fsm_dec_h_counter; + int fsm_dec_v_counter; + int fsm_dec_block_v_counter; + int fsm_padding_status; + int fsm_padding_elem_counter; + int fsm_vector_support_error; + int fsm_vector_buffer_full; + int vector_support; + int sensor_data_lost; +}; + +struct input_formatter_bin_state_s { + uint32_t reset; + uint32_t input_endianness; + uint32_t output_endianness; + uint32_t bitswap; + uint32_t block_synch; + uint32_t packet_synch; + uint32_t readpostwrite_synch; + uint32_t is_2ppc; + uint32_t en_status_update; +}; + +static const unsigned int input_formatter_alignment[N_INPUT_FORMATTER_ID] = { + ISP_VEC_ALIGN, ISP_VEC_ALIGN, HIVE_ISP_CTRL_DATA_BYTES}; + +#endif /* __INPUT_FORMATTER_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/input_formatter_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/input_formatter_private.h new file mode 100644 index 0000000000000000000000000000000000000000..d34933e44aa9c7ca3d6d689218c8c657cba9152d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/input_formatter_private.h @@ -0,0 +1,46 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_FORMATTER_PRIVATE_H_INCLUDED__ +#define __INPUT_FORMATTER_PRIVATE_H_INCLUDED__ + +#include "input_formatter_public.h" + +#include "device_access.h" + +#include "assert_support.h" + +STORAGE_CLASS_INPUT_FORMATTER_C void input_formatter_reg_store( + const input_formatter_ID_t ID, + const hrt_address reg_addr, + const hrt_data value) +{ +assert(ID < N_INPUT_FORMATTER_ID); +assert(INPUT_FORMATTER_BASE[ID] != (hrt_address)-1); +assert((reg_addr % sizeof(hrt_data)) == 0); + ia_css_device_store_uint32(INPUT_FORMATTER_BASE[ID] + reg_addr, value); +return; +} + +STORAGE_CLASS_INPUT_FORMATTER_C hrt_data input_formatter_reg_load( + const input_formatter_ID_t ID, + const unsigned int reg_addr) +{ +assert(ID < N_INPUT_FORMATTER_ID); +assert(INPUT_FORMATTER_BASE[ID] != (hrt_address)-1); +assert((reg_addr % sizeof(hrt_data)) == 0); +return ia_css_device_load_uint32(INPUT_FORMATTER_BASE[ID] + reg_addr); +} + +#endif /* __INPUT_FORMATTER_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/input_system.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/input_system.c new file mode 100644 index 0000000000000000000000000000000000000000..f35e18987b6744772fdbe8b2e672bf7fa7e4945a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/input_system.c @@ -0,0 +1,1823 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "system_global.h" + +#ifdef USE_INPUT_SYSTEM_VERSION_2 + +#include "input_system.h" +#include +#include "gp_device.h" + +#include "assert_support.h" + +#ifndef __INLINE_INPUT_SYSTEM__ +#include "input_system_private.h" +#endif /* __INLINE_INPUT_SYSTEM__ */ + +#define ZERO (0x0) +#define ONE (1U) + +const ib_buffer_t IB_BUFFER_NULL = {0 ,0, 0 }; + +static input_system_error_t input_system_configure_channel( + const channel_cfg_t channel); + +static input_system_error_t input_system_configure_channel_sensor( + const channel_cfg_t channel); + +static input_system_error_t input_buffer_configuration(void); + +static input_system_error_t configuration_to_registers(void); + +static void receiver_rst(const rx_ID_t ID); +static void input_system_network_rst(const input_system_ID_t ID); + +static void capture_unit_configure( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + const ib_buffer_t* const cfg); + +static void acquisition_unit_configure( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + const ib_buffer_t* const cfg); + +static void ctrl_unit_configure( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + const ctrl_unit_cfg_t* const cfg); + +static void input_system_network_configure( + const input_system_ID_t ID, + const input_system_network_cfg_t * const cfg); + +// MW: CSI is previously named as "rx" short for "receiver" +static input_system_error_t set_csi_cfg( + csi_cfg_t* const lhs, + const csi_cfg_t* const rhs, + input_system_config_flags_t* const flags); + +static input_system_error_t set_source_type( + input_system_source_t* const lhs, + const input_system_source_t rhs, + input_system_config_flags_t* const flags); + +static input_system_error_t input_system_multiplexer_cfg( + input_system_multiplex_t* const lhs, + const input_system_multiplex_t rhs, + input_system_config_flags_t* const flags); + + + +STORAGE_CLASS_INLINE void capture_unit_get_state( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + capture_unit_state_t *state); + +STORAGE_CLASS_INLINE void acquisition_unit_get_state( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + acquisition_unit_state_t *state); + +STORAGE_CLASS_INLINE void ctrl_unit_get_state( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + ctrl_unit_state_t *state); + +STORAGE_CLASS_INLINE void mipi_port_get_state( + const rx_ID_t ID, + const mipi_port_ID_t port_ID, + mipi_port_state_t *state); + +STORAGE_CLASS_INLINE void rx_channel_get_state( + const rx_ID_t ID, + const unsigned int ch_id, + rx_channel_state_t *state); + +static void gp_device_rst(const gp_device_ID_t ID); + +static void input_selector_cfg_for_sensor(const gp_device_ID_t ID); + +static void input_switch_rst(const gp_device_ID_t ID); + +static void input_switch_cfg( + const gp_device_ID_t ID, + const input_switch_cfg_t * const cfg +); + +void input_system_get_state( + const input_system_ID_t ID, + input_system_state_t *state) +{ + sub_system_ID_t sub_id; + + assert(ID < N_INPUT_SYSTEM_ID); + assert(state != NULL); + + state->str_multicastA_sel = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_A_IDX); + state->str_multicastB_sel = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_B_IDX); + state->str_multicastC_sel = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_C_IDX); + state->str_mux_sel = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MUX_IDX); + state->str_mon_status = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_STRMON_STAT_IDX); + state->str_mon_irq_cond = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_STRMON_COND_IDX); + state->str_mon_irq_en = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_STRMON_IRQ_EN_IDX); + state->isys_srst = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_SRST_IDX); + state->isys_slv_reg_srst = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_SLV_REG_SRST_IDX); + state->str_deint_portA_cnt = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_REG_PORT_A_IDX); + state->str_deint_portB_cnt = input_system_sub_system_reg_load(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_REG_PORT_B_IDX); + + for (sub_id = CAPTURE_UNIT0_ID; sub_id < CAPTURE_UNIT0_ID + N_CAPTURE_UNIT_ID; sub_id++) { + capture_unit_get_state(ID, sub_id, + &(state->capture_unit[sub_id - CAPTURE_UNIT0_ID])); + } + for (sub_id = ACQUISITION_UNIT0_ID; sub_id < ACQUISITION_UNIT0_ID + N_ACQUISITION_UNIT_ID; sub_id++) { + acquisition_unit_get_state(ID, sub_id, + &(state->acquisition_unit[sub_id - ACQUISITION_UNIT0_ID])); + } + for (sub_id = CTRL_UNIT0_ID; sub_id < CTRL_UNIT0_ID + N_CTRL_UNIT_ID; sub_id++) { + ctrl_unit_get_state(ID, sub_id, + &(state->ctrl_unit_state[sub_id - CTRL_UNIT0_ID])); + } + +return; +} + +void receiver_get_state( + const rx_ID_t ID, + receiver_state_t *state) +{ + mipi_port_ID_t port_id; + unsigned int ch_id; + + assert(ID < N_RX_ID); + assert(state != NULL); + + state->fs_to_ls_delay = (uint8_t)receiver_reg_load(ID, + _HRT_CSS_RECEIVER_FS_TO_LS_DELAY_REG_IDX); + state->ls_to_data_delay = (uint8_t)receiver_reg_load(ID, + _HRT_CSS_RECEIVER_LS_TO_DATA_DELAY_REG_IDX); + state->data_to_le_delay = (uint8_t)receiver_reg_load(ID, + _HRT_CSS_RECEIVER_DATA_TO_LE_DELAY_REG_IDX); + state->le_to_fe_delay = (uint8_t)receiver_reg_load(ID, + _HRT_CSS_RECEIVER_LE_TO_FE_DELAY_REG_IDX); + state->fe_to_fs_delay = (uint8_t)receiver_reg_load(ID, + _HRT_CSS_RECEIVER_FE_TO_FS_DELAY_REG_IDX); + state->le_to_fs_delay = (uint8_t)receiver_reg_load(ID, + _HRT_CSS_RECEIVER_LE_TO_LS_DELAY_REG_IDX); + state->is_two_ppc = (bool)receiver_reg_load(ID, + _HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX); + state->backend_rst = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BACKEND_RST_REG_IDX); + state->raw18 = (uint16_t)receiver_reg_load(ID, + _HRT_CSS_RECEIVER_RAW18_REG_IDX); + state->force_raw8 = (bool)receiver_reg_load(ID, + _HRT_CSS_RECEIVER_FORCE_RAW8_REG_IDX); + state->raw16 = (uint16_t)receiver_reg_load(ID, + _HRT_CSS_RECEIVER_RAW16_REG_IDX); + + for (port_id = (mipi_port_ID_t)0; port_id < N_MIPI_PORT_ID; port_id++) { + mipi_port_get_state(ID, port_id, + &(state->mipi_port_state[port_id])); + } + for (ch_id = (unsigned int)0; ch_id < N_RX_CHANNEL_ID; ch_id++) { + rx_channel_get_state(ID, ch_id, + &(state->rx_channel_state[ch_id])); + } + + state->be_gsp_acc_ovl = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_GSP_ACC_OVL_REG_IDX); + state->be_srst = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_SRST_REG_IDX); + state->be_is_two_ppc = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_TWO_PPC_REG_IDX); + state->be_comp_format0 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG0_IDX); + state->be_comp_format1 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG1_IDX); + state->be_comp_format2 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG2_IDX); + state->be_comp_format3 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG3_IDX); + state->be_sel = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_SEL_REG_IDX); + state->be_raw16_config = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_RAW16_CONFIG_REG_IDX); + state->be_raw18_config = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_RAW18_CONFIG_REG_IDX); + state->be_force_raw8 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_FORCE_RAW8_REG_IDX); + state->be_irq_status = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_IRQ_STATUS_REG_IDX); + state->be_irq_clear = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_BE_IRQ_CLEAR_REG_IDX); + +return; +} + +bool is_mipi_format_yuv420( + const mipi_format_t mipi_format) +{ + bool is_yuv420 = ( + (mipi_format == MIPI_FORMAT_YUV420_8) || + (mipi_format == MIPI_FORMAT_YUV420_10) || + (mipi_format == MIPI_FORMAT_YUV420_8_SHIFT) || + (mipi_format == MIPI_FORMAT_YUV420_10_SHIFT)); +/* MIPI_FORMAT_YUV420_8_LEGACY is not YUV420 */ + +return is_yuv420; +} + +void receiver_set_compression( + const rx_ID_t ID, + const unsigned int cfg_ID, + const mipi_compressor_t comp, + const mipi_predictor_t pred) +{ + const unsigned int field_id = cfg_ID % N_MIPI_FORMAT_CUSTOM; + const unsigned int ch_id = cfg_ID / N_MIPI_FORMAT_CUSTOM; + hrt_data val; + hrt_address addr = 0; + hrt_data reg; + + assert(ID < N_RX_ID); + assert(cfg_ID < N_MIPI_COMPRESSOR_CONTEXT); + assert(field_id < N_MIPI_FORMAT_CUSTOM); + assert(ch_id < N_RX_CHANNEL_ID); + assert(comp < N_MIPI_COMPRESSOR_METHODS); + assert(pred < N_MIPI_PREDICTOR_TYPES); + + val = (((uint8_t)pred) << 3) | comp; + + switch (ch_id) { + case 0: addr = ((field_id<6)?_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX:_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX); + break; + case 1: addr = ((field_id<6)?_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX:_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX); + break; + case 2: addr = ((field_id<6)?_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX:_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX); + break; + case 3: addr = ((field_id<6)?_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX:_HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX); + break; + default: + /* should not happen */ + assert(false); + return; + } + + reg = ((field_id < 6)?(val << (field_id * 5)):(val << ((field_id - 6) * 5))); + receiver_reg_store(ID, addr, reg); + +return; +} + +void receiver_port_enable( + const rx_ID_t ID, + const mipi_port_ID_t port_ID, + const bool cnd) +{ + hrt_data reg = receiver_port_reg_load(ID, port_ID, + _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX); + + if (cnd) { + reg |= 0x01; + } else { + reg &= ~0x01; + } + + receiver_port_reg_store(ID, port_ID, + _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX, reg); +return; +} + +bool is_receiver_port_enabled( + const rx_ID_t ID, + const mipi_port_ID_t port_ID) +{ + hrt_data reg = receiver_port_reg_load(ID, port_ID, + _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX); +return ((reg & 0x01) != 0); +} + +void receiver_irq_enable( + const rx_ID_t ID, + const mipi_port_ID_t port_ID, + const rx_irq_info_t irq_info) +{ + receiver_port_reg_store(ID, + port_ID, _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX, irq_info); +return; +} + +rx_irq_info_t receiver_get_irq_info( + const rx_ID_t ID, + const mipi_port_ID_t port_ID) +{ +return receiver_port_reg_load(ID, + port_ID, _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX); +} + +void receiver_irq_clear( + const rx_ID_t ID, + const mipi_port_ID_t port_ID, + const rx_irq_info_t irq_info) +{ + receiver_port_reg_store(ID, + port_ID, _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX, irq_info); +return; +} + +STORAGE_CLASS_INLINE void capture_unit_get_state( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + capture_unit_state_t *state) +{ + assert(/*(sub_id >= CAPTURE_UNIT0_ID) &&*/ (sub_id <= CAPTURE_UNIT2_ID)); + assert(state != NULL); + + state->StartMode = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_START_MODE_REG_ID); + state->Start_Addr = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_START_ADDR_REG_ID); + state->Mem_Region_Size = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_MEM_REGION_SIZE_REG_ID); + state->Num_Mem_Regions = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_NUM_MEM_REGIONS_REG_ID); +// AM: Illegal read from following registers. +/* state->Init = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_INIT_REG_ID); + state->Start = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_START_REG_ID); + state->Stop = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_STOP_REG_ID); +*/ + state->Packet_Length = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_PACKET_LENGTH_REG_ID); + state->Received_Length = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_RECEIVED_LENGTH_REG_ID); + state->Received_Short_Packets = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_RECEIVED_SHORT_PACKETS_REG_ID); + state->Received_Long_Packets = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_RECEIVED_LONG_PACKETS_REG_ID); + state->Last_Command = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_LAST_COMMAND_REG_ID); + state->Next_Command = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_NEXT_COMMAND_REG_ID); + state->Last_Acknowledge = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_LAST_ACKNOWLEDGE_REG_ID); + state->Next_Acknowledge = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_NEXT_ACKNOWLEDGE_REG_ID); + state->FSM_State_Info = input_system_sub_system_reg_load(ID, + sub_id, + CAPT_FSM_STATE_INFO_REG_ID); + +return; +} + +STORAGE_CLASS_INLINE void acquisition_unit_get_state( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + acquisition_unit_state_t *state) +{ + assert(sub_id == ACQUISITION_UNIT0_ID); + assert(state != NULL); + + state->Start_Addr = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_START_ADDR_REG_ID); + state->Mem_Region_Size = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_MEM_REGION_SIZE_REG_ID); + state->Num_Mem_Regions = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_NUM_MEM_REGIONS_REG_ID); +// AM: Illegal read from following registers. +/* state->Init = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_INIT_REG_ID); +*/ + state->Received_Short_Packets = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_RECEIVED_SHORT_PACKETS_REG_ID); + state->Received_Long_Packets = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_RECEIVED_LONG_PACKETS_REG_ID); + state->Last_Command = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_LAST_COMMAND_REG_ID); + state->Next_Command = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_NEXT_COMMAND_REG_ID); + state->Last_Acknowledge = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_LAST_ACKNOWLEDGE_REG_ID); + state->Next_Acknowledge = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_NEXT_ACKNOWLEDGE_REG_ID); + state->FSM_State_Info = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_FSM_STATE_INFO_REG_ID); + state->Int_Cntr_Info = input_system_sub_system_reg_load(ID, + sub_id, + ACQ_INT_CNTR_INFO_REG_ID); + +return; +} + +STORAGE_CLASS_INLINE void ctrl_unit_get_state( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + ctrl_unit_state_t *state) +{ + assert(sub_id == CTRL_UNIT0_ID); + assert(state != NULL); + + state->captA_start_addr = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_START_ADDR_A_REG_ID); + state->captB_start_addr = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_START_ADDR_B_REG_ID); + state->captC_start_addr = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_START_ADDR_C_REG_ID); + state->captA_mem_region_size = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID); + state->captB_mem_region_size = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID); + state->captC_mem_region_size = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID); + state->captA_num_mem_regions = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID); + state->captB_num_mem_regions = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID); + state->captC_num_mem_regions = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID); + state->acq_start_addr = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_ACQ_START_ADDR_REG_ID); + state->acq_mem_region_size = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID); + state->acq_num_mem_regions = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID); +// AM: Illegal read from following registers. +/* state->ctrl_init = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_INIT_REG_ID); +*/ + state->last_cmd = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_LAST_COMMAND_REG_ID); + state->next_cmd = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_NEXT_COMMAND_REG_ID); + state->last_ack = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_LAST_ACKNOWLEDGE_REG_ID); + state->next_ack = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_NEXT_ACKNOWLEDGE_REG_ID); + state->top_fsm_state = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_FSM_STATE_INFO_REG_ID); + state->captA_fsm_state = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_A_FSM_STATE_INFO_REG_ID); + state->captB_fsm_state = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_B_FSM_STATE_INFO_REG_ID); + state->captC_fsm_state = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_C_FSM_STATE_INFO_REG_ID); + state->acq_fsm_state = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_ACQ_FSM_STATE_INFO_REG_ID); + state->capt_reserve_one_mem_region = input_system_sub_system_reg_load(ID, + sub_id, + ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID); + +return; +} + +STORAGE_CLASS_INLINE void mipi_port_get_state( + const rx_ID_t ID, + const mipi_port_ID_t port_ID, + mipi_port_state_t *state) +{ + int i; + + assert(ID < N_RX_ID); + assert(port_ID < N_MIPI_PORT_ID); + assert(state != NULL); + + state->device_ready = receiver_port_reg_load(ID, + port_ID, _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX); + state->irq_status = receiver_port_reg_load(ID, + port_ID, _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX); + state->irq_enable = receiver_port_reg_load(ID, + port_ID, _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX); + state->timeout_count = receiver_port_reg_load(ID, + port_ID, _HRT_CSS_RECEIVER_TIMEOUT_COUNT_REG_IDX); + state->init_count = (uint16_t)receiver_port_reg_load(ID, + port_ID, _HRT_CSS_RECEIVER_INIT_COUNT_REG_IDX); + state->raw16_18 = (uint16_t)receiver_port_reg_load(ID, + port_ID, _HRT_CSS_RECEIVER_RAW16_18_DATAID_REG_IDX); + state->sync_count = receiver_port_reg_load(ID, + port_ID, _HRT_CSS_RECEIVER_SYNC_COUNT_REG_IDX); + state->rx_count = receiver_port_reg_load(ID, + port_ID, _HRT_CSS_RECEIVER_RX_COUNT_REG_IDX); + + for (i = 0; i < MIPI_4LANE_CFG ; i++) { + state->lane_sync_count[i] = (uint8_t)((state->sync_count)>>(i*8)); + state->lane_rx_count[i] = (uint8_t)((state->rx_count)>>(i*8)); + } + +return; +} + +STORAGE_CLASS_INLINE void rx_channel_get_state( + const rx_ID_t ID, + const unsigned int ch_id, + rx_channel_state_t *state) +{ + int i; + + assert(ID < N_RX_ID); + assert(ch_id < N_RX_CHANNEL_ID); + assert(state != NULL); + + switch (ch_id) { + case 0: + state->comp_scheme0 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX); + state->comp_scheme1 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX); + break; + case 1: + state->comp_scheme0 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX); + state->comp_scheme1 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX); + break; + case 2: + state->comp_scheme0 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX); + state->comp_scheme1 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX); + break; + case 3: + state->comp_scheme0 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX); + state->comp_scheme1 = receiver_reg_load(ID, + _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX); + break; + } + +/* See Table 7.1.17,..., 7.1.24 */ + for (i = 0; i < 6; i++) { + uint8_t val = (uint8_t)((state->comp_scheme0)>>(i*5)) & 0x1f; + state->comp[i] = (mipi_compressor_t)(val & 0x07); + state->pred[i] = (mipi_predictor_t)((val & 0x18) >> 3); + } + for (i = 6; i < N_MIPI_FORMAT_CUSTOM; i++) { + uint8_t val = (uint8_t)((state->comp_scheme0)>>((i-6)*5)) & 0x1f; + state->comp[i] = (mipi_compressor_t)(val & 0x07); + state->pred[i] = (mipi_predictor_t)((val & 0x18) >> 3); + } + +return; +} + +// MW: "2400" in the name is not good, but this is to avoid a naming conflict +input_system_cfg2400_t config; + +static void receiver_rst( + const rx_ID_t ID) +{ + mipi_port_ID_t port_id; + + assert(ID < N_RX_ID); + +// Disable all ports. + for (port_id = MIPI_PORT0_ID; port_id < N_MIPI_PORT_ID; port_id++) { + receiver_port_enable(ID, port_id, false); + } + + // AM: Additional actions for stopping receiver? + + return; +} + +//Single function to reset all the devices mapped via GP_DEVICE. +static void gp_device_rst(const gp_device_ID_t ID) +{ + assert(ID < N_GP_DEVICE_ID); + + gp_device_reg_store(ID, _REG_GP_SYNCGEN_ENABLE_ADDR, ZERO); + // gp_device_reg_store(ID, _REG_GP_SYNCGEN_FREE_RUNNING_ADDR, ZERO); + // gp_device_reg_store(ID, _REG_GP_SYNCGEN_PAUSE_ADDR, ONE); + // gp_device_reg_store(ID, _REG_GP_NR_FRAMES_ADDR, ZERO); + // gp_device_reg_store(ID, _REG_GP_SYNGEN_NR_PIX_ADDR, ZERO); + // gp_device_reg_store(ID, _REG_GP_SYNGEN_NR_PIX_ADDR, ZERO); + // gp_device_reg_store(ID, _REG_GP_SYNGEN_NR_LINES_ADDR, ZERO); + // gp_device_reg_store(ID, _REG_GP_SYNGEN_HBLANK_CYCLES_ADDR, ZERO); + // gp_device_reg_store(ID, _REG_GP_SYNGEN_VBLANK_CYCLES_ADDR, ZERO); +// AM: Following calls cause strange warnings. Probably they should not be initialized. +// gp_device_reg_store(ID, _REG_GP_ISEL_SOF_ADDR, ZERO); +// gp_device_reg_store(ID, _REG_GP_ISEL_EOF_ADDR, ZERO); +// gp_device_reg_store(ID, _REG_GP_ISEL_SOL_ADDR, ZERO); +// gp_device_reg_store(ID, _REG_GP_ISEL_EOL_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_LFSR_ENABLE_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_LFSR_ENABLE_B_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_LFSR_RESET_VALUE_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_TPG_ENABLE_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_TPG_ENABLE_B_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_HOR_CNT_MASK_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_VER_CNT_MASK_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_XY_CNT_MASK_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_HOR_CNT_DELTA_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_VER_CNT_DELTA_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_TPG_MODE_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_TPG_RED1_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_TPG_GREEN1_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_TPG_BLUE1_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_TPG_RED2_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_TPG_GREEN2_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_TPG_BLUE2_ADDR, ZERO); + //gp_device_reg_store(ID, _REG_GP_ISEL_CH_ID_ADDR, ZERO); + //gp_device_reg_store(ID, _REG_GP_ISEL_FMT_TYPE_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_DATA_SEL_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_SBAND_SEL_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_SYNC_SEL_ADDR, ZERO); + // gp_device_reg_store(ID, _REG_GP_SYNCGEN_HOR_CNT_ADDR, ZERO); + // gp_device_reg_store(ID, _REG_GP_SYNCGEN_VER_CNT_ADDR, ZERO); + // gp_device_reg_store(ID, _REG_GP_SYNCGEN_FRAME_CNT_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_SOFT_RESET_ADDR, ZERO); // AM: Maybe this soft reset is not safe. + + return; +} + +static void input_selector_cfg_for_sensor(const gp_device_ID_t ID) +{ + assert(ID < N_GP_DEVICE_ID); + + gp_device_reg_store(ID, _REG_GP_ISEL_SOF_ADDR, ONE); + gp_device_reg_store(ID, _REG_GP_ISEL_EOF_ADDR, ONE); + gp_device_reg_store(ID, _REG_GP_ISEL_SOL_ADDR, ONE); + gp_device_reg_store(ID, _REG_GP_ISEL_EOL_ADDR, ONE); + gp_device_reg_store(ID, _REG_GP_ISEL_CH_ID_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_FMT_TYPE_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_DATA_SEL_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_SBAND_SEL_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_ISEL_SYNC_SEL_ADDR, ZERO); + gp_device_reg_store(ID, _REG_GP_SOFT_RESET_ADDR, ZERO); + + return; +} + +static void input_switch_rst(const gp_device_ID_t ID) +{ + int addr; + + assert(ID < N_GP_DEVICE_ID); + + // Initialize the data&hsync LUT. + for (addr = _REG_GP_IFMT_input_switch_lut_reg0; + addr <= _REG_GP_IFMT_input_switch_lut_reg7; addr += SIZEOF_HRT_REG) { + + gp_device_reg_store(ID, addr, ZERO); + } + + // Initialize the vsync LUT. + gp_device_reg_store(ID, + _REG_GP_IFMT_input_switch_fsync_lut, + ZERO); + + return; +} + +static void input_switch_cfg( + const gp_device_ID_t ID, + const input_switch_cfg_t * const cfg) +{ + int addr_offset; + + assert(ID < N_GP_DEVICE_ID); + assert(cfg != NULL); + + // Initialize the data&hsync LUT. + for (addr_offset = 0; addr_offset < N_RX_CHANNEL_ID * 2; addr_offset++) { + assert(addr_offset * SIZEOF_HRT_REG + _REG_GP_IFMT_input_switch_lut_reg0 <= _REG_GP_IFMT_input_switch_lut_reg7); + gp_device_reg_store(ID, + _REG_GP_IFMT_input_switch_lut_reg0 + addr_offset * SIZEOF_HRT_REG, + cfg->hsync_data_reg[addr_offset]); + } + + // Initialize the vsync LUT. + gp_device_reg_store(ID, + _REG_GP_IFMT_input_switch_fsync_lut, + cfg->vsync_data_reg); + + return; +} + + +static void input_system_network_rst(const input_system_ID_t ID) +{ + unsigned int sub_id; + + // Reset all 3 multicasts. + input_system_sub_system_reg_store(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_A_IDX, + INPUT_SYSTEM_DISCARD_ALL); + input_system_sub_system_reg_store(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_B_IDX, + INPUT_SYSTEM_DISCARD_ALL); + input_system_sub_system_reg_store(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_C_IDX, + INPUT_SYSTEM_DISCARD_ALL); + + // Reset stream mux. + input_system_sub_system_reg_store(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MUX_IDX, + N_INPUT_SYSTEM_MULTIPLEX); + + // Reset 3 capture units. + for (sub_id = CAPTURE_UNIT0_ID; sub_id < CAPTURE_UNIT0_ID + N_CAPTURE_UNIT_ID; sub_id++) { + input_system_sub_system_reg_store(ID, + sub_id, + CAPT_INIT_REG_ID, + 1U << CAPT_INIT_RST_REG_BIT); + } + + // Reset acquisition unit. + for (sub_id = ACQUISITION_UNIT0_ID; sub_id < ACQUISITION_UNIT0_ID + N_ACQUISITION_UNIT_ID; sub_id++) { + input_system_sub_system_reg_store(ID, + sub_id, + ACQ_INIT_REG_ID, + 1U << ACQ_INIT_RST_REG_BIT); + } + + // DMA unit reset is not needed. + + // Reset controller units. + // NB: In future we need to keep part of ctrl_state for split capture and + for (sub_id = CTRL_UNIT0_ID; sub_id < CTRL_UNIT0_ID + N_CTRL_UNIT_ID; sub_id++) { + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_INIT_REG_ID, + 1U); //AM: Is there any named constant? + } + + return; +} + +// Function that resets current configuration. +input_system_error_t input_system_configuration_reset(void) +{ + unsigned int i; + + receiver_rst(RX0_ID); + + input_system_network_rst(INPUT_SYSTEM0_ID); + + gp_device_rst(INPUT_SYSTEM0_ID); + + input_switch_rst(INPUT_SYSTEM0_ID); + + //target_rst(); + + // Reset IRQ_CTRLs. + + // Reset configuration data structures. + for (i = 0; i < N_CHANNELS; i++ ) { + config.ch_flags[i] = INPUT_SYSTEM_CFG_FLAG_RESET; + config.target_isp_flags[i] = INPUT_SYSTEM_CFG_FLAG_RESET; + config.target_sp_flags[i] = INPUT_SYSTEM_CFG_FLAG_RESET; + config.target_strm2mem_flags[i] = INPUT_SYSTEM_CFG_FLAG_RESET; + } + + for (i = 0; i < N_CSI_PORTS; i++ ) { + config.csi_buffer_flags[i] = INPUT_SYSTEM_CFG_FLAG_RESET; + config.multicast[i] = INPUT_SYSTEM_CFG_FLAG_RESET; + } + + config.source_type_flags = INPUT_SYSTEM_CFG_FLAG_RESET; + config.acquisition_buffer_unique_flags = INPUT_SYSTEM_CFG_FLAG_RESET; + config.unallocated_ib_mem_words = IB_CAPACITY_IN_WORDS; + //config.acq_allocated_ib_mem_words = 0; + + // Set the start of the session cofiguration. + config.session_flags = INPUT_SYSTEM_CFG_FLAG_REQUIRED; + + return INPUT_SYSTEM_ERR_NO_ERROR; +} + +// MW: Comments are good, but doxygen is required, place it at the declaration +// Function that appends the channel to current configuration. +static input_system_error_t input_system_configure_channel( + const channel_cfg_t channel) +{ + input_system_error_t error = INPUT_SYSTEM_ERR_NO_ERROR; + // Check if channel is not already configured. + if (config.ch_flags[channel.ch_id] & INPUT_SYSTEM_CFG_FLAG_SET){ + return INPUT_SYSTEM_ERR_CHANNEL_ALREADY_SET; + } else { + switch (channel.source_type){ + case INPUT_SYSTEM_SOURCE_SENSOR : + error = input_system_configure_channel_sensor(channel); + break; + case INPUT_SYSTEM_SOURCE_TPG : + return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED; + break; + case INPUT_SYSTEM_SOURCE_PRBS : + return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED; + break; + case INPUT_SYSTEM_SOURCE_FIFO : + return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED; + break; + default : + return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED; + break; + } + + if (error != INPUT_SYSTEM_ERR_NO_ERROR) return error; + // Input switch channel configurations must be combined in united config. + config.input_switch_cfg.hsync_data_reg[channel.source_cfg.csi_cfg.csi_port * 2] = + channel.target_cfg.input_switch_channel_cfg.hsync_data_reg[0]; + config.input_switch_cfg.hsync_data_reg[channel.source_cfg.csi_cfg.csi_port * 2 + 1] = + channel.target_cfg.input_switch_channel_cfg.hsync_data_reg[1]; + config.input_switch_cfg.vsync_data_reg |= + (channel.target_cfg.input_switch_channel_cfg.vsync_data_reg & 0x7) << (channel.source_cfg.csi_cfg.csi_port * 3); + + // Other targets are just copied and marked as set. + config.target_isp[channel.source_cfg.csi_cfg.csi_port] = channel.target_cfg.target_isp_cfg; + config.target_sp[channel.source_cfg.csi_cfg.csi_port] = channel.target_cfg.target_sp_cfg; + config.target_strm2mem[channel.source_cfg.csi_cfg.csi_port] = channel.target_cfg.target_strm2mem_cfg; + config.target_isp_flags[channel.source_cfg.csi_cfg.csi_port] |= INPUT_SYSTEM_CFG_FLAG_SET; + config.target_sp_flags[channel.source_cfg.csi_cfg.csi_port] |= INPUT_SYSTEM_CFG_FLAG_SET; + config.target_strm2mem_flags[channel.source_cfg.csi_cfg.csi_port] |= INPUT_SYSTEM_CFG_FLAG_SET; + + config.ch_flags[channel.ch_id] = INPUT_SYSTEM_CFG_FLAG_SET; + } + return INPUT_SYSTEM_ERR_NO_ERROR; +} + +// Function that partitions input buffer space with determining addresses. +static input_system_error_t input_buffer_configuration(void) +{ + uint32_t current_address = 0; + uint32_t unallocated_memory = IB_CAPACITY_IN_WORDS; + + ib_buffer_t candidate_buffer_acq = IB_BUFFER_NULL; + uint32_t size_requested; + input_system_config_flags_t acq_already_specified = INPUT_SYSTEM_CFG_FLAG_RESET; + input_system_csi_port_t port; + for (port = INPUT_SYSTEM_PORT_A; port < N_INPUT_SYSTEM_PORTS; port++) { + + csi_cfg_t source = config.csi_value[port];//.csi_cfg; + + if ( config.csi_flags[port] & INPUT_SYSTEM_CFG_FLAG_SET) { + + // Check and set csi buffer in input buffer. + switch (source.buffering_mode) { + case INPUT_SYSTEM_FIFO_CAPTURE : + case INPUT_SYSTEM_XMEM_ACQUIRE : + config.csi_buffer_flags[port] = INPUT_SYSTEM_CFG_FLAG_BLOCKED; // Well, not used. + break; + + case INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING : + case INPUT_SYSTEM_SRAM_BUFFERING : + case INPUT_SYSTEM_XMEM_BUFFERING : + case INPUT_SYSTEM_XMEM_CAPTURE : + size_requested = source.csi_buffer.mem_reg_size * source.csi_buffer.nof_mem_regs; + if (source.csi_buffer.mem_reg_size > 0 + && source.csi_buffer.nof_mem_regs >0 + && size_requested <= unallocated_memory + ) { + config.csi_buffer[port].mem_reg_addr = current_address; + config.csi_buffer[port].mem_reg_size = source.csi_buffer.mem_reg_size; + config.csi_buffer[port].nof_mem_regs = source.csi_buffer.nof_mem_regs; + current_address += size_requested; + unallocated_memory -= size_requested; + config.csi_buffer_flags[port] = INPUT_SYSTEM_CFG_FLAG_SET; + } else { + config.csi_buffer_flags[port] |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE; + } + break; + + default : + config.csi_buffer_flags[port] |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED; + break; + } + + // Check acquisition buffer specified but set it later since it has to be unique. + switch (source.buffering_mode) { + case INPUT_SYSTEM_FIFO_CAPTURE : + case INPUT_SYSTEM_SRAM_BUFFERING : + case INPUT_SYSTEM_XMEM_CAPTURE : + // Nothing to do. + break; + + case INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING : + case INPUT_SYSTEM_XMEM_BUFFERING : + case INPUT_SYSTEM_XMEM_ACQUIRE : + if (acq_already_specified == INPUT_SYSTEM_CFG_FLAG_RESET) { + size_requested = source.acquisition_buffer.mem_reg_size + * source.acquisition_buffer.nof_mem_regs; + if (source.acquisition_buffer.mem_reg_size > 0 + && source.acquisition_buffer.nof_mem_regs >0 + && size_requested <= unallocated_memory + ) { + candidate_buffer_acq = source.acquisition_buffer; + acq_already_specified = INPUT_SYSTEM_CFG_FLAG_SET; + } + } else { + // Check if specified acquisition buffer is the same as specified before. + if (source.acquisition_buffer.mem_reg_size != candidate_buffer_acq.mem_reg_size + || source.acquisition_buffer.nof_mem_regs != candidate_buffer_acq.nof_mem_regs + ) { + config.acquisition_buffer_unique_flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE; + } + } + break; + + default : + return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED; + break; + } + } else { + config.csi_buffer_flags[port] = INPUT_SYSTEM_CFG_FLAG_BLOCKED; + } + } // end of for ( port ) + + // Set the acquisition buffer at the end. + size_requested = candidate_buffer_acq.mem_reg_size * candidate_buffer_acq.nof_mem_regs; + if (acq_already_specified == INPUT_SYSTEM_CFG_FLAG_SET + && size_requested <= unallocated_memory) { + config.acquisition_buffer_unique.mem_reg_addr = current_address; + config.acquisition_buffer_unique.mem_reg_size = candidate_buffer_acq.mem_reg_size; + config.acquisition_buffer_unique.nof_mem_regs = candidate_buffer_acq.nof_mem_regs; + current_address += size_requested; + unallocated_memory -= size_requested; + config.acquisition_buffer_unique_flags = INPUT_SYSTEM_CFG_FLAG_SET; + + assert(current_address <= IB_CAPACITY_IN_WORDS); + } + + return INPUT_SYSTEM_ERR_NO_ERROR; +} + +static void capture_unit_configure( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + const ib_buffer_t* const cfg) +{ + assert(ID < N_INPUT_SYSTEM_ID); + assert(/*(sub_id >= CAPTURE_UNIT0_ID) &&*/ (sub_id <= CAPTURE_UNIT2_ID)); // Commented part is always true. + assert(cfg != NULL); + + input_system_sub_system_reg_store(ID, + sub_id, + CAPT_START_ADDR_REG_ID, + cfg->mem_reg_addr); + input_system_sub_system_reg_store(ID, + sub_id, + CAPT_MEM_REGION_SIZE_REG_ID, + cfg->mem_reg_size); + input_system_sub_system_reg_store(ID, + sub_id, + CAPT_NUM_MEM_REGIONS_REG_ID, + cfg->nof_mem_regs); + + return; +} + + +static void acquisition_unit_configure( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + const ib_buffer_t* const cfg) +{ + assert(ID < N_INPUT_SYSTEM_ID); + assert(sub_id == ACQUISITION_UNIT0_ID); + assert(cfg != NULL); + + input_system_sub_system_reg_store(ID, + sub_id, + ACQ_START_ADDR_REG_ID, + cfg->mem_reg_addr); + input_system_sub_system_reg_store(ID, + sub_id, + ACQ_NUM_MEM_REGIONS_REG_ID, + cfg->nof_mem_regs); + input_system_sub_system_reg_store(ID, + sub_id, + ACQ_MEM_REGION_SIZE_REG_ID, + cfg->mem_reg_size); + + return; +} + + +static void ctrl_unit_configure( + const input_system_ID_t ID, + const sub_system_ID_t sub_id, + const ctrl_unit_cfg_t* const cfg) +{ + assert(ID < N_INPUT_SYSTEM_ID); + assert(sub_id == CTRL_UNIT0_ID); + assert(cfg != NULL); + + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_CAPT_START_ADDR_A_REG_ID, + cfg->buffer_mipi[CAPTURE_UNIT0_ID].mem_reg_addr); + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_CAPT_MEM_REGION_SIZE_A_REG_ID, + cfg->buffer_mipi[CAPTURE_UNIT0_ID].mem_reg_size); + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_CAPT_NUM_MEM_REGIONS_A_REG_ID, + cfg->buffer_mipi[CAPTURE_UNIT0_ID].nof_mem_regs); + + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_CAPT_START_ADDR_B_REG_ID, + cfg->buffer_mipi[CAPTURE_UNIT1_ID].mem_reg_addr); + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_CAPT_MEM_REGION_SIZE_B_REG_ID, + cfg->buffer_mipi[CAPTURE_UNIT1_ID].mem_reg_size); + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_CAPT_NUM_MEM_REGIONS_B_REG_ID, + cfg->buffer_mipi[CAPTURE_UNIT1_ID].nof_mem_regs); + + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_CAPT_START_ADDR_C_REG_ID, + cfg->buffer_mipi[CAPTURE_UNIT2_ID].mem_reg_addr); + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_CAPT_MEM_REGION_SIZE_C_REG_ID, + cfg->buffer_mipi[CAPTURE_UNIT2_ID].mem_reg_size); + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_CAPT_NUM_MEM_REGIONS_C_REG_ID, + cfg->buffer_mipi[CAPTURE_UNIT2_ID].nof_mem_regs); + + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_ACQ_START_ADDR_REG_ID, + cfg->buffer_acquire[ACQUISITION_UNIT0_ID - ACQUISITION_UNIT0_ID].mem_reg_addr); + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_ACQ_MEM_REGION_SIZE_REG_ID, + cfg->buffer_acquire[ACQUISITION_UNIT0_ID - ACQUISITION_UNIT0_ID].mem_reg_size); + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_ACQ_NUM_MEM_REGIONS_REG_ID, + cfg->buffer_acquire[ACQUISITION_UNIT0_ID - ACQUISITION_UNIT0_ID].nof_mem_regs); + input_system_sub_system_reg_store(ID, + sub_id, + ISYS_CTRL_CAPT_RESERVE_ONE_MEM_REGION_REG_ID, + 0); + return; +} + +static void input_system_network_configure( + const input_system_ID_t ID, + const input_system_network_cfg_t * const cfg) +{ + uint32_t sub_id; + + assert(ID < N_INPUT_SYSTEM_ID); + assert(cfg != NULL); + + // Set all 3 multicasts. + input_system_sub_system_reg_store(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_A_IDX, + cfg->multicast_cfg[CAPTURE_UNIT0_ID]); + input_system_sub_system_reg_store(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_B_IDX, + cfg->multicast_cfg[CAPTURE_UNIT1_ID]); + input_system_sub_system_reg_store(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_C_IDX, + cfg->multicast_cfg[CAPTURE_UNIT2_ID]); + + // Set stream mux. + input_system_sub_system_reg_store(ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MUX_IDX, + cfg->mux_cfg); + + // Set capture units. + for (sub_id = CAPTURE_UNIT0_ID; sub_id < CAPTURE_UNIT0_ID + N_CAPTURE_UNIT_ID; sub_id++) { + capture_unit_configure(ID, + sub_id, + &(cfg->ctrl_unit_cfg[ID].buffer_mipi[sub_id - CAPTURE_UNIT0_ID])); + } + + // Set acquisition units. + for (sub_id = ACQUISITION_UNIT0_ID; sub_id < ACQUISITION_UNIT0_ID + N_ACQUISITION_UNIT_ID; sub_id++) { + acquisition_unit_configure(ID, + sub_id, + &(cfg->ctrl_unit_cfg[sub_id - ACQUISITION_UNIT0_ID].buffer_acquire[sub_id - ACQUISITION_UNIT0_ID])); + } + + // No DMA configuration needed. Ctrl_unit will fully control it. + + // Set controller units. + for (sub_id = CTRL_UNIT0_ID; sub_id < CTRL_UNIT0_ID + N_CTRL_UNIT_ID; sub_id++) { + ctrl_unit_configure(ID, + sub_id, + &(cfg->ctrl_unit_cfg[sub_id - CTRL_UNIT0_ID])); + } + + return; +} + +static input_system_error_t configuration_to_registers(void) +{ + input_system_network_cfg_t input_system_network_cfg; + int i; + + assert(config.source_type_flags & INPUT_SYSTEM_CFG_FLAG_SET); + + switch (config.source_type) { + case INPUT_SYSTEM_SOURCE_SENSOR : + + // Determine stream multicasts setting based on the mode of csi_cfg_t. + // AM: This should be moved towards earlier function call, e.g. in + // the commit function. + for (i = MIPI_PORT0_ID; i < N_MIPI_PORT_ID; i++) { + if (config.csi_flags[i] & INPUT_SYSTEM_CFG_FLAG_SET) { + + switch (config.csi_value[i].buffering_mode) { + + case INPUT_SYSTEM_FIFO_CAPTURE: + config.multicast[i] = INPUT_SYSTEM_CSI_BACKEND; + break; + + case INPUT_SYSTEM_XMEM_CAPTURE: + case INPUT_SYSTEM_SRAM_BUFFERING: + case INPUT_SYSTEM_XMEM_BUFFERING: + config.multicast[i] = INPUT_SYSTEM_INPUT_BUFFER; + break; + + case INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING: + config.multicast[i] = INPUT_SYSTEM_MULTICAST; + break; + + case INPUT_SYSTEM_XMEM_ACQUIRE: + config.multicast[i] = INPUT_SYSTEM_DISCARD_ALL; + break; + + default: + config.multicast[i] = INPUT_SYSTEM_DISCARD_ALL; + return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED; + //break; + } + } else { + config.multicast[i]= INPUT_SYSTEM_DISCARD_ALL; + } + + input_system_network_cfg.multicast_cfg[i] = config.multicast[i]; + + } // for + + input_system_network_cfg.mux_cfg = config.multiplexer; + + input_system_network_cfg.ctrl_unit_cfg[CTRL_UNIT0_ID - CTRL_UNIT0_ID].buffer_mipi[CAPTURE_UNIT0_ID] = config.csi_buffer[MIPI_PORT0_ID]; + input_system_network_cfg.ctrl_unit_cfg[CTRL_UNIT0_ID - CTRL_UNIT0_ID].buffer_mipi[CAPTURE_UNIT1_ID] = config.csi_buffer[MIPI_PORT1_ID]; + input_system_network_cfg.ctrl_unit_cfg[CTRL_UNIT0_ID - CTRL_UNIT0_ID].buffer_mipi[CAPTURE_UNIT2_ID] = config.csi_buffer[MIPI_PORT2_ID]; + input_system_network_cfg.ctrl_unit_cfg[CTRL_UNIT0_ID - CTRL_UNIT0_ID].buffer_acquire[ACQUISITION_UNIT0_ID - ACQUISITION_UNIT0_ID] = + config.acquisition_buffer_unique; + + // First set input network around CSI receiver. + input_system_network_configure(INPUT_SYSTEM0_ID, &input_system_network_cfg); + + // Set the CSI receiver. + //... + break; + + case INPUT_SYSTEM_SOURCE_TPG : + + break; + + case INPUT_SYSTEM_SOURCE_PRBS : + + break; + + case INPUT_SYSTEM_SOURCE_FIFO : + break; + + default : + return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED; + break; + + } // end of switch (source_type) + + // Set input selector. + input_selector_cfg_for_sensor(INPUT_SYSTEM0_ID); + + // Set input switch. + input_switch_cfg(INPUT_SYSTEM0_ID, &config.input_switch_cfg); + + // Set input formatters. + // AM: IF are set dynamically. + return INPUT_SYSTEM_ERR_NO_ERROR; +} + + +// Function that applies the whole configuration. +input_system_error_t input_system_configuration_commit(void) +{ + // The last configuration step is to configure the input buffer. + input_system_error_t error = input_buffer_configuration(); + if (error != INPUT_SYSTEM_ERR_NO_ERROR) { + return error; + } + + // Translate the whole configuration into registers. + error = configuration_to_registers(); + if (error != INPUT_SYSTEM_ERR_NO_ERROR) { + return error; + } + + // Translate the whole configuration into ctrl commands etc. + + return INPUT_SYSTEM_ERR_NO_ERROR; +} + + + +// FIFO + +input_system_error_t input_system_csi_fifo_channel_cfg( + uint32_t ch_id, + input_system_csi_port_t port, + backend_channel_cfg_t backend_ch, + target_cfg2400_t target +) +{ + channel_cfg_t channel; + + channel.ch_id = ch_id; + channel.backend_ch = backend_ch; + channel.source_type = INPUT_SYSTEM_SOURCE_SENSOR; + //channel.source + channel.source_cfg.csi_cfg.csi_port = port; + channel.source_cfg.csi_cfg.buffering_mode = INPUT_SYSTEM_FIFO_CAPTURE; + channel.source_cfg.csi_cfg.csi_buffer = IB_BUFFER_NULL; + channel.source_cfg.csi_cfg.acquisition_buffer = IB_BUFFER_NULL; + channel.source_cfg.csi_cfg.nof_xmem_buffers = 0; + + channel.target_cfg = target; + return input_system_configure_channel(channel); +} + + +input_system_error_t input_system_csi_fifo_channel_with_counting_cfg( + uint32_t ch_id, + uint32_t nof_frames, + input_system_csi_port_t port, + backend_channel_cfg_t backend_ch, + uint32_t csi_mem_reg_size, + uint32_t csi_nof_mem_regs, + target_cfg2400_t target +) +{ + channel_cfg_t channel; + + channel.ch_id = ch_id; + channel.backend_ch = backend_ch; + channel.source_type = INPUT_SYSTEM_SOURCE_SENSOR; + //channel.source + channel.source_cfg.csi_cfg.csi_port = port; + channel.source_cfg.csi_cfg.buffering_mode = INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING; + channel.source_cfg.csi_cfg.csi_buffer.mem_reg_size = csi_mem_reg_size; + channel.source_cfg.csi_cfg.csi_buffer.nof_mem_regs = csi_nof_mem_regs; + channel.source_cfg.csi_cfg.csi_buffer.mem_reg_addr = 0; + channel.source_cfg.csi_cfg.acquisition_buffer = IB_BUFFER_NULL; + channel.source_cfg.csi_cfg.nof_xmem_buffers = nof_frames; + + channel.target_cfg = target; + return input_system_configure_channel(channel); +} + + +// SRAM + +input_system_error_t input_system_csi_sram_channel_cfg( + uint32_t ch_id, + input_system_csi_port_t port, + backend_channel_cfg_t backend_ch, + uint32_t csi_mem_reg_size, + uint32_t csi_nof_mem_regs, + // uint32_t acq_mem_reg_size, + // uint32_t acq_nof_mem_regs, + target_cfg2400_t target +) +{ + channel_cfg_t channel; + + channel.ch_id = ch_id; + channel.backend_ch = backend_ch; + channel.source_type = INPUT_SYSTEM_SOURCE_SENSOR; + //channel.source + channel.source_cfg.csi_cfg.csi_port = port; + channel.source_cfg.csi_cfg.buffering_mode = INPUT_SYSTEM_SRAM_BUFFERING; + channel.source_cfg.csi_cfg.csi_buffer.mem_reg_size = csi_mem_reg_size; + channel.source_cfg.csi_cfg.csi_buffer.nof_mem_regs = csi_nof_mem_regs; + channel.source_cfg.csi_cfg.csi_buffer.mem_reg_addr = 0; + channel.source_cfg.csi_cfg.acquisition_buffer = IB_BUFFER_NULL; + channel.source_cfg.csi_cfg.nof_xmem_buffers = 0; + + channel.target_cfg = target; + return input_system_configure_channel(channel); +} + + +//XMEM + +// Collects all parameters and puts them in channel_cfg_t. +input_system_error_t input_system_csi_xmem_channel_cfg( + uint32_t ch_id, + input_system_csi_port_t port, + backend_channel_cfg_t backend_ch, + uint32_t csi_mem_reg_size, + uint32_t csi_nof_mem_regs, + uint32_t acq_mem_reg_size, + uint32_t acq_nof_mem_regs, + target_cfg2400_t target, + uint32_t nof_xmem_buffers +) +{ + channel_cfg_t channel; + + channel.ch_id = ch_id; + channel.backend_ch = backend_ch; + channel.source_type = INPUT_SYSTEM_SOURCE_SENSOR; + //channel.source + channel.source_cfg.csi_cfg.csi_port = port; + channel.source_cfg.csi_cfg.buffering_mode = INPUT_SYSTEM_XMEM_BUFFERING; + channel.source_cfg.csi_cfg.csi_buffer.mem_reg_size = csi_mem_reg_size; + channel.source_cfg.csi_cfg.csi_buffer.nof_mem_regs = csi_nof_mem_regs; + channel.source_cfg.csi_cfg.csi_buffer.mem_reg_addr = 0; + channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_size = acq_mem_reg_size; + channel.source_cfg.csi_cfg.acquisition_buffer.nof_mem_regs = acq_nof_mem_regs; + channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_addr = 0; + channel.source_cfg.csi_cfg.nof_xmem_buffers = nof_xmem_buffers; + + channel.target_cfg = target; + return input_system_configure_channel(channel); +} + + + + +input_system_error_t input_system_csi_xmem_acquire_only_channel_cfg( + uint32_t ch_id, + uint32_t nof_frames, + input_system_csi_port_t port, + backend_channel_cfg_t backend_ch, + uint32_t acq_mem_reg_size, + uint32_t acq_nof_mem_regs, + target_cfg2400_t target) +{ + channel_cfg_t channel; + + channel.ch_id = ch_id; + channel.backend_ch = backend_ch; + channel.source_type = INPUT_SYSTEM_SOURCE_SENSOR; + //channel.source + channel.source_cfg.csi_cfg.csi_port = port; + channel.source_cfg.csi_cfg.buffering_mode = INPUT_SYSTEM_XMEM_ACQUIRE; + channel.source_cfg.csi_cfg.csi_buffer = IB_BUFFER_NULL; + channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_size = acq_mem_reg_size; + channel.source_cfg.csi_cfg.acquisition_buffer.nof_mem_regs = acq_nof_mem_regs; + channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_addr = 0; + channel.source_cfg.csi_cfg.nof_xmem_buffers = nof_frames; + + channel.target_cfg = target; + return input_system_configure_channel(channel); +} + + +input_system_error_t input_system_csi_xmem_capture_only_channel_cfg( + uint32_t ch_id, + uint32_t nof_frames, + input_system_csi_port_t port, + uint32_t csi_mem_reg_size, + uint32_t csi_nof_mem_regs, + uint32_t acq_mem_reg_size, + uint32_t acq_nof_mem_regs, + target_cfg2400_t target) +{ + channel_cfg_t channel; + + channel.ch_id = ch_id; + //channel.backend_ch = backend_ch; + channel.source_type = INPUT_SYSTEM_SOURCE_SENSOR; + //channel.source + channel.source_cfg.csi_cfg.csi_port = port; + //channel.source_cfg.csi_cfg.backend_ch = backend_ch; + channel.source_cfg.csi_cfg.buffering_mode = INPUT_SYSTEM_XMEM_CAPTURE; + channel.source_cfg.csi_cfg.csi_buffer.mem_reg_size = csi_mem_reg_size; + channel.source_cfg.csi_cfg.csi_buffer.nof_mem_regs = csi_nof_mem_regs; + channel.source_cfg.csi_cfg.csi_buffer.mem_reg_addr = 0; + channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_size = acq_mem_reg_size; + channel.source_cfg.csi_cfg.acquisition_buffer.nof_mem_regs = acq_nof_mem_regs; + channel.source_cfg.csi_cfg.acquisition_buffer.mem_reg_addr = 0; + channel.source_cfg.csi_cfg.nof_xmem_buffers = nof_frames; + + channel.target_cfg = target; + return input_system_configure_channel(channel); +} + + + +// Non - CSI + +input_system_error_t input_system_prbs_channel_cfg( + uint32_t ch_id, + uint32_t nof_frames,//not used yet + uint32_t seed, + uint32_t sync_gen_width, + uint32_t sync_gen_height, + uint32_t sync_gen_hblank_cycles, + uint32_t sync_gen_vblank_cycles, + target_cfg2400_t target +) +{ + channel_cfg_t channel; + + (void)nof_frames; + + channel.ch_id = ch_id; + channel.source_type= INPUT_SYSTEM_SOURCE_PRBS; + + channel.source_cfg.prbs_cfg.seed = seed; + channel.source_cfg.prbs_cfg.sync_gen_cfg.width = sync_gen_width; + channel.source_cfg.prbs_cfg.sync_gen_cfg.height = sync_gen_height; + channel.source_cfg.prbs_cfg.sync_gen_cfg.hblank_cycles = sync_gen_hblank_cycles; + channel.source_cfg.prbs_cfg.sync_gen_cfg.vblank_cycles = sync_gen_vblank_cycles; + + channel.target_cfg = target; + + return input_system_configure_channel(channel); +} + + + +input_system_error_t input_system_tpg_channel_cfg( + uint32_t ch_id, + uint32_t nof_frames,//not used yet + uint32_t x_mask, + uint32_t y_mask, + uint32_t x_delta, + uint32_t y_delta, + uint32_t xy_mask, + uint32_t sync_gen_width, + uint32_t sync_gen_height, + uint32_t sync_gen_hblank_cycles, + uint32_t sync_gen_vblank_cycles, + target_cfg2400_t target +) +{ + channel_cfg_t channel; + + (void)nof_frames; + + channel.ch_id = ch_id; + channel.source_type = INPUT_SYSTEM_SOURCE_TPG; + + channel.source_cfg.tpg_cfg.x_mask = x_mask; + channel.source_cfg.tpg_cfg.y_mask = y_mask; + channel.source_cfg.tpg_cfg.x_delta = x_delta; + channel.source_cfg.tpg_cfg.y_delta = y_delta; + channel.source_cfg.tpg_cfg.xy_mask = xy_mask; + channel.source_cfg.tpg_cfg.sync_gen_cfg.width = sync_gen_width; + channel.source_cfg.tpg_cfg.sync_gen_cfg.height = sync_gen_height; + channel.source_cfg.tpg_cfg.sync_gen_cfg.hblank_cycles = sync_gen_hblank_cycles; + channel.source_cfg.tpg_cfg.sync_gen_cfg.vblank_cycles = sync_gen_vblank_cycles; + + channel.target_cfg = target; + return input_system_configure_channel(channel); +} + +// MW: Don't use system specific names, (even in system specific files) "cfg2400" -> cfg +input_system_error_t input_system_gpfifo_channel_cfg( + uint32_t ch_id, + uint32_t nof_frames, //not used yet + target_cfg2400_t target) +{ + channel_cfg_t channel; + + (void)nof_frames; + + channel.ch_id = ch_id; + channel.source_type = INPUT_SYSTEM_SOURCE_FIFO; + + channel.target_cfg = target; + return input_system_configure_channel(channel); +} + +/////////////////////////////////////////////////////////////////////////// +// +// Private specialized functions for channel setting. +// +/////////////////////////////////////////////////////////////////////////// + +// Fills the parameters to config.csi_value[port] +static input_system_error_t input_system_configure_channel_sensor( + const channel_cfg_t channel) +{ + const uint32_t port = channel.source_cfg.csi_cfg.csi_port; + input_system_error_t status = INPUT_SYSTEM_ERR_NO_ERROR; + + input_system_multiplex_t mux; + + if (port >= N_INPUT_SYSTEM_PORTS) + return INPUT_SYSTEM_ERR_GENERIC; + + //check if port > N_INPUT_SYSTEM_MULTIPLEX + + status = set_source_type(&(config.source_type), channel.source_type, &config.source_type_flags); + if (status != INPUT_SYSTEM_ERR_NO_ERROR) return status; + + // Check for conflicts on source (implicitly on multicast, capture unit and input buffer). + + status = set_csi_cfg(&(config.csi_value[port]), &channel.source_cfg.csi_cfg, &(config.csi_flags[port])); + if (status != INPUT_SYSTEM_ERR_NO_ERROR) return status; + + + switch (channel.source_cfg.csi_cfg.buffering_mode){ + case INPUT_SYSTEM_FIFO_CAPTURE: + + // Check for conflicts on mux. + mux = INPUT_SYSTEM_MIPI_PORT0 + port; + status = input_system_multiplexer_cfg(&config.multiplexer, mux, &config.multiplexer_flags); + if (status != INPUT_SYSTEM_ERR_NO_ERROR) return status; + config.multicast[port] = INPUT_SYSTEM_CSI_BACKEND; + + // Shared resource, so it should be blocked. + //config.mux_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED; + //config.csi_buffer_flags[port] |= INPUT_SYSTEM_CFG_FLAG_BLOCKED; + //config.acquisition_buffer_unique_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED; + + break; + case INPUT_SYSTEM_SRAM_BUFFERING : + + // Check for conflicts on mux. + mux = INPUT_SYSTEM_ACQUISITION_UNIT; + status = input_system_multiplexer_cfg(&config.multiplexer, mux, &config.multiplexer_flags); + if (status != INPUT_SYSTEM_ERR_NO_ERROR) return status; + config.multicast[port] = INPUT_SYSTEM_INPUT_BUFFER; + + // Shared resource, so it should be blocked. + //config.mux_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED; + //config.csi_buffer_flags[port] |= INPUT_SYSTEM_CFG_FLAG_BLOCKED; + //config.acquisition_buffer_unique_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED; + + break; + case INPUT_SYSTEM_XMEM_BUFFERING : + + // Check for conflicts on mux. + mux = INPUT_SYSTEM_ACQUISITION_UNIT; + status = input_system_multiplexer_cfg(&config.multiplexer, mux, &config.multiplexer_flags); + if (status != INPUT_SYSTEM_ERR_NO_ERROR) return status; + config.multicast[port] = INPUT_SYSTEM_INPUT_BUFFER; + + // Shared resource, so it should be blocked. + //config.mux_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED; + //config.csi_buffer_flags[port] |= INPUT_SYSTEM_CFG_FLAG_BLOCKED; + //config.acquisition_buffer_unique_flags |= INPUT_SYSTEM_CFG_FLAG_BLOCKED; + + break; + case INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING : + return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED; + break; + case INPUT_SYSTEM_XMEM_CAPTURE : + return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED; + break; + case INPUT_SYSTEM_XMEM_ACQUIRE : + return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED; + break; + default : + return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED; + break; + } + return INPUT_SYSTEM_ERR_NO_ERROR; +} + +// Test flags and set structure. +static input_system_error_t set_source_type( + input_system_source_t * const lhs, + const input_system_source_t rhs, + input_system_config_flags_t * const flags) +{ + // MW: Not enough asserts + assert(lhs != NULL); + assert(flags != NULL); + + if ((*flags) & INPUT_SYSTEM_CFG_FLAG_BLOCKED) { + *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE; + } + + if ((*flags) & INPUT_SYSTEM_CFG_FLAG_SET) { + // Check for consistency with already set value. + if ((*lhs) == (rhs)) { + return INPUT_SYSTEM_ERR_NO_ERROR; + } + else { + *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE; + } + } + // Check the value (individually). + if (rhs >= N_INPUT_SYSTEM_SOURCE) { + *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE; + } + // Set the value. + *lhs = rhs; + + *flags |= INPUT_SYSTEM_CFG_FLAG_SET; + return INPUT_SYSTEM_ERR_NO_ERROR; +} + + +// Test flags and set structure. +static input_system_error_t set_csi_cfg( + csi_cfg_t* const lhs, + const csi_cfg_t* const rhs, + input_system_config_flags_t * const flags) +{ + uint32_t memory_required; + uint32_t acq_memory_required; + + assert(lhs != NULL); + assert(flags != NULL); + + if ((*flags) & INPUT_SYSTEM_CFG_FLAG_BLOCKED) { + *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE; + } + + if (*flags & INPUT_SYSTEM_CFG_FLAG_SET) { + // check for consistency with already set value. + if (/*lhs->backend_ch == rhs.backend_ch + &&*/ lhs->buffering_mode == rhs->buffering_mode + && lhs->csi_buffer.mem_reg_size == rhs->csi_buffer.mem_reg_size + && lhs->csi_buffer.nof_mem_regs == rhs->csi_buffer.nof_mem_regs + && lhs->acquisition_buffer.mem_reg_size == rhs->acquisition_buffer.mem_reg_size + && lhs->acquisition_buffer.nof_mem_regs == rhs->acquisition_buffer.nof_mem_regs + && lhs->nof_xmem_buffers == rhs->nof_xmem_buffers + ) { + return INPUT_SYSTEM_ERR_NO_ERROR; + } + else { + *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE; + } + } + // Check the value (individually). + // no check for backend_ch + // no check for nof_xmem_buffers + memory_required = rhs->csi_buffer.mem_reg_size * rhs->csi_buffer.nof_mem_regs; + acq_memory_required = rhs->acquisition_buffer.mem_reg_size * rhs->acquisition_buffer.nof_mem_regs; + if (rhs->buffering_mode >= N_INPUT_SYSTEM_BUFFERING_MODE + || + // Check if required memory is available in input buffer (SRAM). + (memory_required + acq_memory_required )> config.unallocated_ib_mem_words + + ) { + *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE; + } + // Set the value. + //lhs[port]->backend_ch = rhs.backend_ch; + lhs->buffering_mode = rhs->buffering_mode; + lhs->nof_xmem_buffers = rhs->nof_xmem_buffers; + + lhs->csi_buffer.mem_reg_size = rhs->csi_buffer.mem_reg_size; + lhs->csi_buffer.nof_mem_regs = rhs->csi_buffer.nof_mem_regs; + lhs->acquisition_buffer.mem_reg_size = rhs->acquisition_buffer.mem_reg_size; + lhs->acquisition_buffer.nof_mem_regs = rhs->acquisition_buffer.nof_mem_regs; + // ALX: NB: Here we just set buffer parameters, but still not allocate it + // (no addresses determined). That will be done during commit. + + // FIXIT: acq_memory_required is not deducted, since it can be allocated multiple times. + config.unallocated_ib_mem_words -= memory_required; +//assert(config.unallocated_ib_mem_words >=0); + *flags |= INPUT_SYSTEM_CFG_FLAG_SET; + return INPUT_SYSTEM_ERR_NO_ERROR; +} + + +// Test flags and set structure. +static input_system_error_t input_system_multiplexer_cfg( + input_system_multiplex_t* const lhs, + const input_system_multiplex_t rhs, + input_system_config_flags_t* const flags) +{ + assert(lhs != NULL); + assert(flags != NULL); + + if ((*flags) & INPUT_SYSTEM_CFG_FLAG_BLOCKED) { + *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE; + } + + if ((*flags) & INPUT_SYSTEM_CFG_FLAG_SET) { + // Check for consistency with already set value. + if ((*lhs) == (rhs)) { + return INPUT_SYSTEM_ERR_NO_ERROR; + } + else { + *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE; + } + } + // Check the value (individually). + if (rhs >= N_INPUT_SYSTEM_MULTIPLEX) { + *flags |= INPUT_SYSTEM_CFG_FLAG_CONFLICT; + return INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED; + } + // Set the value. + *lhs = rhs; + + *flags |= INPUT_SYSTEM_CFG_FLAG_SET; + return INPUT_SYSTEM_ERR_NO_ERROR; +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/input_system_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/input_system_local.h new file mode 100644 index 0000000000000000000000000000000000000000..3e8bd00082dcd4a4cc099216bdbdab32aefcf802 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/input_system_local.h @@ -0,0 +1,533 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_SYSTEM_LOCAL_H_INCLUDED__ +#define __INPUT_SYSTEM_LOCAL_H_INCLUDED__ + +#include + +#include "input_system_global.h" + +#include "input_system_defs.h" /* HIVE_ISYS_GPREG_MULTICAST_A_IDX,... */ +#include "css_receiver_2400_defs.h" /* _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX, _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX,... */ +#if defined(IS_ISP_2400_MAMOIADA_SYSTEM) +#include "isp_capture_defs.h" +#elif defined(IS_ISP_2401_MAMOIADA_SYSTEM) +/* Same name, but keep the distinction,it is a different device */ +#include "isp_capture_defs.h" +#else +#error "input_system_local.h: 2400_SYSTEM must be one of {2400, 2401 }" +#endif +#include "isp_acquisition_defs.h" +#include "input_system_ctrl_defs.h" + + +typedef enum { + INPUT_SYSTEM_ERR_NO_ERROR = 0, + INPUT_SYSTEM_ERR_GENERIC, + INPUT_SYSTEM_ERR_CHANNEL_ALREADY_SET, + INPUT_SYSTEM_ERR_CONFLICT_ON_RESOURCE, + INPUT_SYSTEM_ERR_PARAMETER_NOT_SUPPORTED, + N_INPUT_SYSTEM_ERR +} input_system_error_t; + +typedef enum { + INPUT_SYSTEM_PORT_A = 0, + INPUT_SYSTEM_PORT_B, + INPUT_SYSTEM_PORT_C, + N_INPUT_SYSTEM_PORTS +} input_system_csi_port_t; + +typedef struct ctrl_unit_cfg_s ctrl_unit_cfg_t; +typedef struct input_system_network_cfg_s input_system_network_cfg_t; +typedef struct target_cfg2400_s target_cfg2400_t; +typedef struct channel_cfg_s channel_cfg_t; +typedef struct backend_channel_cfg_s backend_channel_cfg_t; +typedef struct input_system_cfg2400_s input_system_cfg2400_t; +typedef struct mipi_port_state_s mipi_port_state_t; +typedef struct rx_channel_state_s rx_channel_state_t; +typedef struct input_switch_cfg_channel_s input_switch_cfg_channel_t; +typedef struct input_switch_cfg_s input_switch_cfg_t; + +struct ctrl_unit_cfg_s { + ib_buffer_t buffer_mipi[N_CAPTURE_UNIT_ID]; + ib_buffer_t buffer_acquire[N_ACQUISITION_UNIT_ID]; +}; + +struct input_system_network_cfg_s { + input_system_connection_t multicast_cfg[N_CAPTURE_UNIT_ID]; + input_system_multiplex_t mux_cfg; + ctrl_unit_cfg_t ctrl_unit_cfg[N_CTRL_UNIT_ID]; +}; + +typedef struct { +// TBD. + uint32_t dummy_parameter; +} target_isp_cfg_t; + + +typedef struct { +// TBD. + uint32_t dummy_parameter; +} target_sp_cfg_t; + + +typedef struct { +// TBD. + uint32_t dummy_parameter; +} target_strm2mem_cfg_t; + +struct input_switch_cfg_channel_s { + uint32_t hsync_data_reg[2]; + uint32_t vsync_data_reg; +}; + +struct target_cfg2400_s { + input_switch_cfg_channel_t input_switch_channel_cfg; + target_isp_cfg_t target_isp_cfg; + target_sp_cfg_t target_sp_cfg; + target_strm2mem_cfg_t target_strm2mem_cfg; +}; + +struct backend_channel_cfg_s { + uint32_t fmt_control_word_1; // Format config. + uint32_t fmt_control_word_2; + uint32_t no_side_band; +}; + +typedef union { + csi_cfg_t csi_cfg; + tpg_cfg_t tpg_cfg; + prbs_cfg_t prbs_cfg; + gpfifo_cfg_t gpfifo_cfg; +} source_cfg_t; + + +struct input_switch_cfg_s { + uint32_t hsync_data_reg[N_RX_CHANNEL_ID * 2]; + uint32_t vsync_data_reg; +}; + +// Configuration of a channel. +struct channel_cfg_s { + uint32_t ch_id; + backend_channel_cfg_t backend_ch; + input_system_source_t source_type; + source_cfg_t source_cfg; + target_cfg2400_t target_cfg; +}; + + +// Complete configuration for input system. +struct input_system_cfg2400_s { + + input_system_source_t source_type; input_system_config_flags_t source_type_flags; + //channel_cfg_t channel[N_CHANNELS]; + input_system_config_flags_t ch_flags[N_CHANNELS]; + // This is the place where the buffers' settings are collected, as given. + csi_cfg_t csi_value[N_CSI_PORTS]; input_system_config_flags_t csi_flags[N_CSI_PORTS]; + + // Possible another struct for ib. + // This buffers set at the end, based on the all configurations. + ib_buffer_t csi_buffer[N_CSI_PORTS]; input_system_config_flags_t csi_buffer_flags[N_CSI_PORTS]; + ib_buffer_t acquisition_buffer_unique; input_system_config_flags_t acquisition_buffer_unique_flags; + uint32_t unallocated_ib_mem_words; // Used for check.DEFAULT = IB_CAPACITY_IN_WORDS. + //uint32_t acq_allocated_ib_mem_words; + + input_system_connection_t multicast[N_CSI_PORTS]; + input_system_multiplex_t multiplexer; input_system_config_flags_t multiplexer_flags; + + + tpg_cfg_t tpg_value; input_system_config_flags_t tpg_flags; + prbs_cfg_t prbs_value; input_system_config_flags_t prbs_flags; + gpfifo_cfg_t gpfifo_value; input_system_config_flags_t gpfifo_flags; + + + input_switch_cfg_t input_switch_cfg; + + + target_isp_cfg_t target_isp [N_CHANNELS]; input_system_config_flags_t target_isp_flags [N_CHANNELS]; + target_sp_cfg_t target_sp [N_CHANNELS]; input_system_config_flags_t target_sp_flags [N_CHANNELS]; + target_strm2mem_cfg_t target_strm2mem [N_CHANNELS]; input_system_config_flags_t target_strm2mem_flags [N_CHANNELS]; + + input_system_config_flags_t session_flags; + +}; + +/* + * For each MIPI port + */ +#define _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX _HRT_CSS_RECEIVER_2400_DEVICE_READY_REG_IDX +#define _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX _HRT_CSS_RECEIVER_2400_IRQ_STATUS_REG_IDX +#define _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX _HRT_CSS_RECEIVER_2400_IRQ_ENABLE_REG_IDX +#define _HRT_CSS_RECEIVER_TIMEOUT_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX +#define _HRT_CSS_RECEIVER_INIT_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX +/* new regs for each MIPI port w.r.t. 2300 */ +#define _HRT_CSS_RECEIVER_RAW16_18_DATAID_REG_IDX _HRT_CSS_RECEIVER_2400_RAW16_18_DATAID_REG_IDX +#define _HRT_CSS_RECEIVER_SYNC_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX +#define _HRT_CSS_RECEIVER_RX_COUNT_REG_IDX _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX + +/* _HRT_CSS_RECEIVER_2400_COMP_FORMAT_REG_IDX is not defined per MIPI port but per channel */ +/* _HRT_CSS_RECEIVER_2400_COMP_PREDICT_REG_IDX is not defined per MIPI port but per channel */ +#define _HRT_CSS_RECEIVER_FS_TO_LS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_FS_TO_LS_DELAY_REG_IDX +#define _HRT_CSS_RECEIVER_LS_TO_DATA_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LS_TO_DATA_DELAY_REG_IDX +#define _HRT_CSS_RECEIVER_DATA_TO_LE_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_DATA_TO_LE_DELAY_REG_IDX +#define _HRT_CSS_RECEIVER_LE_TO_FE_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LE_TO_FE_DELAY_REG_IDX +#define _HRT_CSS_RECEIVER_FE_TO_FS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_FE_TO_FS_DELAY_REG_IDX +#define _HRT_CSS_RECEIVER_LE_TO_LS_DELAY_REG_IDX _HRT_CSS_RECEIVER_2400_LE_TO_LS_DELAY_REG_IDX +#define _HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX _HRT_CSS_RECEIVER_2400_TWO_PIXEL_EN_REG_IDX +#define _HRT_CSS_RECEIVER_BACKEND_RST_REG_IDX _HRT_CSS_RECEIVER_2400_BACKEND_RST_REG_IDX +#define _HRT_CSS_RECEIVER_RAW18_REG_IDX _HRT_CSS_RECEIVER_2400_RAW18_REG_IDX +#define _HRT_CSS_RECEIVER_FORCE_RAW8_REG_IDX _HRT_CSS_RECEIVER_2400_FORCE_RAW8_REG_IDX +#define _HRT_CSS_RECEIVER_RAW16_REG_IDX _HRT_CSS_RECEIVER_2400_RAW16_REG_IDX + +/* Previously MIPI port regs, now 2x2 logical channel regs */ +#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC0_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG0_IDX +#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC0_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC0_REG1_IDX +#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC1_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG0_IDX +#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC1_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC1_REG1_IDX +#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC2_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG0_IDX +#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC2_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC2_REG1_IDX +#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC3_REG0_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG0_IDX +#define _HRT_CSS_RECEIVER_COMP_SCHEME_VC3_REG1_IDX _HRT_CSS_RECEIVER_2400_COMP_SCHEME_VC3_REG1_IDX + +/* Second backend is at offset 0x0700 w.r.t. the first port at offset 0x0100 */ +#define _HRT_CSS_BE_OFFSET 448 +#define _HRT_CSS_RECEIVER_BE_GSP_ACC_OVL_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_GSP_ACC_OVL_REG_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_SRST_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_SRST_REG_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_TWO_PPC_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_TWO_PPC_REG_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG0_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG0_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG1_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG1_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG2_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG2_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_COMP_FORMAT_REG3_IDX (_HRT_CSS_RECEIVER_2400_BE_COMP_FORMAT_REG3_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_SEL_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_SEL_REG_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_RAW16_CONFIG_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_RAW16_CONFIG_REG_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_RAW18_CONFIG_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_RAW18_CONFIG_REG_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_FORCE_RAW8_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_FORCE_RAW8_REG_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_IRQ_STATUS_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_IRQ_STATUS_REG_IDX + _HRT_CSS_BE_OFFSET) +#define _HRT_CSS_RECEIVER_BE_IRQ_CLEAR_REG_IDX (_HRT_CSS_RECEIVER_2400_BE_IRQ_CLEAR_REG_IDX + _HRT_CSS_BE_OFFSET) + + +#define _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT _HRT_CSS_RECEIVER_2400_IRQ_OVERRUN_BIT +#define _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT _HRT_CSS_RECEIVER_2400_IRQ_RESERVED_BIT +#define _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_ENTRY_BIT +#define _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT _HRT_CSS_RECEIVER_2400_IRQ_SLEEP_MODE_EXIT_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_HS_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_SOT_SYNC_HS_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_CONTROL_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_DOUBLE_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_CORRECTED_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ECC_NO_CORRECTION_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_CRC_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ID_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_SYNC_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_FRAME_DATA_BIT +#define _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT _HRT_CSS_RECEIVER_2400_IRQ_DATA_TIMEOUT_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_ESCAPE_BIT +#define _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT _HRT_CSS_RECEIVER_2400_IRQ_ERR_LINE_SYNC_BIT + +#define _HRT_CSS_RECEIVER_FUNC_PROG_REG_IDX _HRT_CSS_RECEIVER_2400_CSI2_FUNC_PROG_REG_IDX +#define _HRT_CSS_RECEIVER_DATA_TIMEOUT_IDX _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_IDX +#define _HRT_CSS_RECEIVER_DATA_TIMEOUT_BITS _HRT_CSS_RECEIVER_2400_CSI2_DATA_TIMEOUT_BITS + +typedef struct capture_unit_state_s capture_unit_state_t; +typedef struct acquisition_unit_state_s acquisition_unit_state_t; +typedef struct ctrl_unit_state_s ctrl_unit_state_t; + +/* + * In 2300 ports can be configured independently and stream + * formats need to be specified. In 2400, there are only 8 + * supported configurations but the HW is fused to support + * only a single one. + * + * In 2300 the compressed format types are programmed by the + * user. In 2400 all stream formats are encoded on the stream. + * + * Use the enum to check validity of a user configuration + */ +typedef enum { + MONO_4L_1L_0L = 0, + MONO_3L_1L_0L, + MONO_2L_1L_0L, + MONO_1L_1L_0L, + STEREO_2L_1L_2L, + STEREO_3L_1L_1L, + STEREO_2L_1L_1L, + STEREO_1L_1L_1L, + N_RX_MODE +} rx_mode_t; + +typedef enum { + MIPI_PREDICTOR_NONE = 0, + MIPI_PREDICTOR_TYPE1, + MIPI_PREDICTOR_TYPE2, + N_MIPI_PREDICTOR_TYPES +} mipi_predictor_t; + +typedef enum { + MIPI_COMPRESSOR_NONE = 0, + MIPI_COMPRESSOR_10_6_10, + MIPI_COMPRESSOR_10_7_10, + MIPI_COMPRESSOR_10_8_10, + MIPI_COMPRESSOR_12_6_12, + MIPI_COMPRESSOR_12_7_12, + MIPI_COMPRESSOR_12_8_12, + N_MIPI_COMPRESSOR_METHODS +} mipi_compressor_t; + +typedef enum { + MIPI_FORMAT_RGB888 = 0, + MIPI_FORMAT_RGB555, + MIPI_FORMAT_RGB444, + MIPI_FORMAT_RGB565, + MIPI_FORMAT_RGB666, + MIPI_FORMAT_RAW8, /* 5 */ + MIPI_FORMAT_RAW10, + MIPI_FORMAT_RAW6, + MIPI_FORMAT_RAW7, + MIPI_FORMAT_RAW12, + MIPI_FORMAT_RAW14, /* 10 */ + MIPI_FORMAT_YUV420_8, + MIPI_FORMAT_YUV420_10, + MIPI_FORMAT_YUV422_8, + MIPI_FORMAT_YUV422_10, + MIPI_FORMAT_CUSTOM0, /* 15 */ + MIPI_FORMAT_YUV420_8_LEGACY, + MIPI_FORMAT_EMBEDDED, + MIPI_FORMAT_CUSTOM1, + MIPI_FORMAT_CUSTOM2, + MIPI_FORMAT_CUSTOM3, /* 20 */ + MIPI_FORMAT_CUSTOM4, + MIPI_FORMAT_CUSTOM5, + MIPI_FORMAT_CUSTOM6, + MIPI_FORMAT_CUSTOM7, + MIPI_FORMAT_YUV420_8_SHIFT, /* 25 */ + MIPI_FORMAT_YUV420_10_SHIFT, + MIPI_FORMAT_RAW16, + MIPI_FORMAT_RAW18, + N_MIPI_FORMAT, +} mipi_format_t; + +#define MIPI_FORMAT_JPEG MIPI_FORMAT_CUSTOM0 +#define MIPI_FORMAT_BINARY_8 MIPI_FORMAT_CUSTOM0 +#define N_MIPI_FORMAT_CUSTOM 8 + +/* The number of stores for compressed format types */ +#define N_MIPI_COMPRESSOR_CONTEXT (N_RX_CHANNEL_ID * N_MIPI_FORMAT_CUSTOM) + +typedef enum { + RX_IRQ_INFO_BUFFER_OVERRUN = 1UL << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT, + RX_IRQ_INFO_INIT_TIMEOUT = 1UL << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT, + RX_IRQ_INFO_ENTER_SLEEP_MODE = 1UL << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT, + RX_IRQ_INFO_EXIT_SLEEP_MODE = 1UL << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT, + RX_IRQ_INFO_ECC_CORRECTED = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT, + RX_IRQ_INFO_ERR_SOT = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT, + RX_IRQ_INFO_ERR_SOT_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT, + RX_IRQ_INFO_ERR_CONTROL = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT, + RX_IRQ_INFO_ERR_ECC_DOUBLE = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT, +/* RX_IRQ_INFO_NO_ERR = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT, */ + RX_IRQ_INFO_ERR_CRC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT, + RX_IRQ_INFO_ERR_UNKNOWN_ID = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT, + RX_IRQ_INFO_ERR_FRAME_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT, + RX_IRQ_INFO_ERR_FRAME_DATA = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT, + RX_IRQ_INFO_ERR_DATA_TIMEOUT = 1UL << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT, + RX_IRQ_INFO_ERR_UNKNOWN_ESC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT, + RX_IRQ_INFO_ERR_LINE_SYNC = 1UL << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT, +} rx_irq_info_t; + +typedef struct rx_cfg_s rx_cfg_t; + +/* + * Applied per port + */ +struct rx_cfg_s { + rx_mode_t mode; /* The HW config */ + mipi_port_ID_t port; /* The port ID to apply the control on */ + unsigned int timeout; + unsigned int initcount; + unsigned int synccount; + unsigned int rxcount; + mipi_predictor_t comp; /* Just for backward compatibility */ + bool is_two_ppc; +}; + +/* NOTE: The base has already an offset of 0x0100 */ +static const hrt_address MIPI_PORT_OFFSET[N_MIPI_PORT_ID] = { + 0x00000000UL, + 0x00000100UL, + 0x00000200UL}; + +static const mipi_lane_cfg_t MIPI_PORT_MAXLANES[N_MIPI_PORT_ID] = { + MIPI_4LANE_CFG, + MIPI_1LANE_CFG, + MIPI_2LANE_CFG}; + +static const bool MIPI_PORT_ACTIVE[N_RX_MODE][N_MIPI_PORT_ID] = { + {true, true, false}, + {true, true, false}, + {true, true, false}, + {true, true, false}, + {true, true, true}, + {true, true, true}, + {true, true, true}, + {true, true, true}}; + +static const mipi_lane_cfg_t MIPI_PORT_LANES[N_RX_MODE][N_MIPI_PORT_ID] = { + {MIPI_4LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG}, + {MIPI_3LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG}, + {MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG}, + {MIPI_1LANE_CFG, MIPI_1LANE_CFG, MIPI_0LANE_CFG}, + {MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_2LANE_CFG}, + {MIPI_3LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG}, + {MIPI_2LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG}, + {MIPI_1LANE_CFG, MIPI_1LANE_CFG, MIPI_1LANE_CFG}}; + +static const hrt_address SUB_SYSTEM_OFFSET[N_SUB_SYSTEM_ID] = { + 0x00001000UL, + 0x00002000UL, + 0x00003000UL, + 0x00004000UL, + 0x00005000UL, + 0x00009000UL, + 0x0000A000UL, + 0x0000B000UL, + 0x0000C000UL}; + +struct capture_unit_state_s { + int Packet_Length; + int Received_Length; + int Received_Short_Packets; + int Received_Long_Packets; + int Last_Command; + int Next_Command; + int Last_Acknowledge; + int Next_Acknowledge; + int FSM_State_Info; + int StartMode; + int Start_Addr; + int Mem_Region_Size; + int Num_Mem_Regions; +/* int Init; write-only registers + int Start; + int Stop; */ +}; + +struct acquisition_unit_state_s { +/* int Init; write-only register */ + int Received_Short_Packets; + int Received_Long_Packets; + int Last_Command; + int Next_Command; + int Last_Acknowledge; + int Next_Acknowledge; + int FSM_State_Info; + int Int_Cntr_Info; + int Start_Addr; + int Mem_Region_Size; + int Num_Mem_Regions; +}; + +struct ctrl_unit_state_s { + int last_cmd; + int next_cmd; + int last_ack; + int next_ack; + int top_fsm_state; + int captA_fsm_state; + int captB_fsm_state; + int captC_fsm_state; + int acq_fsm_state; + int captA_start_addr; + int captB_start_addr; + int captC_start_addr; + int captA_mem_region_size; + int captB_mem_region_size; + int captC_mem_region_size; + int captA_num_mem_regions; + int captB_num_mem_regions; + int captC_num_mem_regions; + int acq_start_addr; + int acq_mem_region_size; + int acq_num_mem_regions; +/* int ctrl_init; write only register */ + int capt_reserve_one_mem_region; +}; + +struct input_system_state_s { + int str_multicastA_sel; + int str_multicastB_sel; + int str_multicastC_sel; + int str_mux_sel; + int str_mon_status; + int str_mon_irq_cond; + int str_mon_irq_en; + int isys_srst; + int isys_slv_reg_srst; + int str_deint_portA_cnt; + int str_deint_portB_cnt; + struct capture_unit_state_s capture_unit[N_CAPTURE_UNIT_ID]; + struct acquisition_unit_state_s acquisition_unit[N_ACQUISITION_UNIT_ID]; + struct ctrl_unit_state_s ctrl_unit_state[N_CTRL_UNIT_ID]; +}; + +struct mipi_port_state_s { + int device_ready; + int irq_status; + int irq_enable; + uint32_t timeout_count; + uint16_t init_count; + uint16_t raw16_18; + uint32_t sync_count; /*4 x uint8_t */ + uint32_t rx_count; /*4 x uint8_t */ + uint8_t lane_sync_count[MIPI_4LANE_CFG]; + uint8_t lane_rx_count[MIPI_4LANE_CFG]; +}; + +struct rx_channel_state_s { + uint32_t comp_scheme0; + uint32_t comp_scheme1; + mipi_predictor_t pred[N_MIPI_FORMAT_CUSTOM]; + mipi_compressor_t comp[N_MIPI_FORMAT_CUSTOM]; +}; + +struct receiver_state_s { + uint8_t fs_to_ls_delay; + uint8_t ls_to_data_delay; + uint8_t data_to_le_delay; + uint8_t le_to_fe_delay; + uint8_t fe_to_fs_delay; + uint8_t le_to_fs_delay; + bool is_two_ppc; + int backend_rst; + uint16_t raw18; + bool force_raw8; + uint16_t raw16; + struct mipi_port_state_s mipi_port_state[N_MIPI_PORT_ID]; + struct rx_channel_state_s rx_channel_state[N_RX_CHANNEL_ID]; + int be_gsp_acc_ovl; + int be_srst; + int be_is_two_ppc; + int be_comp_format0; + int be_comp_format1; + int be_comp_format2; + int be_comp_format3; + int be_sel; + int be_raw16_config; + int be_raw18_config; + int be_force_raw8; + int be_irq_status; + int be_irq_clear; +}; + +#endif /* __INPUT_SYSTEM_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/input_system_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/input_system_private.h new file mode 100644 index 0000000000000000000000000000000000000000..ed1b947b00f93a3845e1407d456d2ec7070d7549 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/input_system_private.h @@ -0,0 +1,116 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_SYSTEM_PRIVATE_H_INCLUDED__ +#define __INPUT_SYSTEM_PRIVATE_H_INCLUDED__ + +#include "input_system_public.h" + +#include "device_access.h" + +#include "assert_support.h" + +STORAGE_CLASS_INPUT_SYSTEM_C void input_system_reg_store( + const input_system_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ +assert(ID < N_INPUT_SYSTEM_ID); +assert(INPUT_SYSTEM_BASE[ID] != (hrt_address)-1); + ia_css_device_store_uint32(INPUT_SYSTEM_BASE[ID] + reg*sizeof(hrt_data), value); +return; +} + +STORAGE_CLASS_INPUT_SYSTEM_C hrt_data input_system_reg_load( + const input_system_ID_t ID, + const hrt_address reg) +{ +assert(ID < N_INPUT_SYSTEM_ID); +assert(INPUT_SYSTEM_BASE[ID] != (hrt_address)-1); +return ia_css_device_load_uint32(INPUT_SYSTEM_BASE[ID] + reg*sizeof(hrt_data)); +} + +STORAGE_CLASS_INPUT_SYSTEM_C void receiver_reg_store( + const rx_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ +assert(ID < N_RX_ID); +assert(RX_BASE[ID] != (hrt_address)-1); + ia_css_device_store_uint32(RX_BASE[ID] + reg*sizeof(hrt_data), value); +return; +} + +STORAGE_CLASS_INPUT_SYSTEM_C hrt_data receiver_reg_load( + const rx_ID_t ID, + const hrt_address reg) +{ +assert(ID < N_RX_ID); +assert(RX_BASE[ID] != (hrt_address)-1); +return ia_css_device_load_uint32(RX_BASE[ID] + reg*sizeof(hrt_data)); +} + +STORAGE_CLASS_INPUT_SYSTEM_C void receiver_port_reg_store( + const rx_ID_t ID, + const mipi_port_ID_t port_ID, + const hrt_address reg, + const hrt_data value) +{ +assert(ID < N_RX_ID); +assert(port_ID < N_MIPI_PORT_ID); +assert(RX_BASE[ID] != (hrt_address)-1); +assert(MIPI_PORT_OFFSET[port_ID] != (hrt_address)-1); + ia_css_device_store_uint32(RX_BASE[ID] + MIPI_PORT_OFFSET[port_ID] + reg*sizeof(hrt_data), value); +return; +} + +STORAGE_CLASS_INPUT_SYSTEM_C hrt_data receiver_port_reg_load( + const rx_ID_t ID, + const mipi_port_ID_t port_ID, + const hrt_address reg) +{ +assert(ID < N_RX_ID); +assert(port_ID < N_MIPI_PORT_ID); +assert(RX_BASE[ID] != (hrt_address)-1); +assert(MIPI_PORT_OFFSET[port_ID] != (hrt_address)-1); +return ia_css_device_load_uint32(RX_BASE[ID] + MIPI_PORT_OFFSET[port_ID] + reg*sizeof(hrt_data)); +} + +STORAGE_CLASS_INPUT_SYSTEM_C void input_system_sub_system_reg_store( + const input_system_ID_t ID, + const sub_system_ID_t sub_ID, + const hrt_address reg, + const hrt_data value) +{ +assert(ID < N_INPUT_SYSTEM_ID); +assert(sub_ID < N_SUB_SYSTEM_ID); +assert(INPUT_SYSTEM_BASE[ID] != (hrt_address)-1); +assert(SUB_SYSTEM_OFFSET[sub_ID] != (hrt_address)-1); + ia_css_device_store_uint32(INPUT_SYSTEM_BASE[ID] + SUB_SYSTEM_OFFSET[sub_ID] + reg*sizeof(hrt_data), value); +return; +} + +STORAGE_CLASS_INPUT_SYSTEM_C hrt_data input_system_sub_system_reg_load( + const input_system_ID_t ID, + const sub_system_ID_t sub_ID, + const hrt_address reg) +{ +assert(ID < N_INPUT_SYSTEM_ID); +assert(sub_ID < N_SUB_SYSTEM_ID); +assert(INPUT_SYSTEM_BASE[ID] != (hrt_address)-1); +assert(SUB_SYSTEM_OFFSET[sub_ID] != (hrt_address)-1); +return ia_css_device_load_uint32(INPUT_SYSTEM_BASE[ID] + SUB_SYSTEM_OFFSET[sub_ID] + reg*sizeof(hrt_data)); +} + +#endif /* __INPUT_SYSTEM_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/irq.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/irq.c new file mode 100644 index 0000000000000000000000000000000000000000..0d4ceb63a446a187a93a8b428d252a7bae9b8595 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/irq.c @@ -0,0 +1,455 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "assert_support.h" +#include "irq.h" + +#ifndef __INLINE_GP_DEVICE__ +#define __INLINE_GP_DEVICE__ +#endif +#include "gp_device.h" /* _REG_GP_IRQ_REQUEST_ADDR */ + +#include "platform_support.h" /* hrt_sleep() */ + +STORAGE_CLASS_INLINE void irq_wait_for_write_complete( + const irq_ID_t ID); + +STORAGE_CLASS_INLINE bool any_irq_channel_enabled( + const irq_ID_t ID); + +STORAGE_CLASS_INLINE irq_ID_t virq_get_irq_id( + const virq_id_t irq_ID, + unsigned int *channel_ID); + +#ifndef __INLINE_IRQ__ +#include "irq_private.h" +#endif /* __INLINE_IRQ__ */ + +static unsigned short IRQ_N_CHANNEL[N_IRQ_ID] = { + IRQ0_ID_N_CHANNEL, + IRQ1_ID_N_CHANNEL, + IRQ2_ID_N_CHANNEL, + IRQ3_ID_N_CHANNEL}; + +static unsigned short IRQ_N_ID_OFFSET[N_IRQ_ID + 1] = { + IRQ0_ID_OFFSET, + IRQ1_ID_OFFSET, + IRQ2_ID_OFFSET, + IRQ3_ID_OFFSET, + IRQ_END_OFFSET}; + +static virq_id_t IRQ_NESTING_ID[N_IRQ_ID] = { + N_virq_id, + virq_ifmt, + virq_isys, + virq_isel}; + +void irq_clear_all( + const irq_ID_t ID) +{ + hrt_data mask = 0xFFFFFFFF; + + assert(ID < N_IRQ_ID); + assert(IRQ_N_CHANNEL[ID] <= HRT_DATA_WIDTH); + + if (IRQ_N_CHANNEL[ID] < HRT_DATA_WIDTH) { + mask = ~((~(hrt_data)0)>>IRQ_N_CHANNEL[ID]); + } + + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, mask); +return; +} + +/* + * Do we want the user to be able to set the signalling method ? + */ +void irq_enable_channel( + const irq_ID_t ID, + const unsigned int irq_id) +{ + unsigned int mask = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_MASK_REG_IDX); + unsigned int enable = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX); + unsigned int edge_in = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_EDGE_REG_IDX); + unsigned int me = 1U << irq_id; + + assert(ID < N_IRQ_ID); + assert(irq_id < IRQ_N_CHANNEL[ID]); + + mask |= me; + enable |= me; + edge_in |= me; /* rising edge */ + +/* to avoid mishaps configuration must follow the following order */ + +/* mask this interrupt */ + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_MASK_REG_IDX, mask & ~me); +/* rising edge at input */ + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_EDGE_REG_IDX, edge_in); +/* enable interrupt to output */ + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX, enable); +/* clear current irq only */ + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, me); +/* unmask interrupt from input */ + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_MASK_REG_IDX, mask); + + irq_wait_for_write_complete(ID); + +return; +} + +void irq_enable_pulse( + const irq_ID_t ID, + bool pulse) +{ + unsigned int edge_out = 0x0; + + if (pulse) { + edge_out = 0xffffffff; + } + /* output is given as edge, not pulse */ + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_EDGE_NOT_PULSE_REG_IDX, edge_out); +return; +} + +void irq_disable_channel( + const irq_ID_t ID, + const unsigned int irq_id) +{ + unsigned int mask = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_MASK_REG_IDX); + unsigned int enable = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX); + unsigned int me = 1U << irq_id; + + assert(ID < N_IRQ_ID); + assert(irq_id < IRQ_N_CHANNEL[ID]); + + mask &= ~me; + enable &= ~me; + +/* enable interrupt to output */ + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX, enable); +/* unmask interrupt from input */ + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_MASK_REG_IDX, mask); +/* clear current irq only */ + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, me); + + irq_wait_for_write_complete(ID); + +return; +} + +enum hrt_isp_css_irq_status irq_get_channel_id( + const irq_ID_t ID, + unsigned int *irq_id) +{ + unsigned int irq_status = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_STATUS_REG_IDX); + unsigned int idx; + enum hrt_isp_css_irq_status status = hrt_isp_css_irq_status_success; + + assert(ID < N_IRQ_ID); + assert(irq_id != NULL); + +/* find the first irq bit */ + for (idx = 0; idx < IRQ_N_CHANNEL[ID]; idx++) { + if (irq_status & (1U << idx)) + break; + } + if (idx == IRQ_N_CHANNEL[ID]) + return hrt_isp_css_irq_status_error; + +/* now check whether there are more bits set */ + if (irq_status != (1U << idx)) + status = hrt_isp_css_irq_status_more_irqs; + + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, 1U << idx); + + irq_wait_for_write_complete(ID); + + if (irq_id != NULL) + *irq_id = (unsigned int)idx; + +return status; +} + +static const hrt_address IRQ_REQUEST_ADDR[N_IRQ_SW_CHANNEL_ID] = { + _REG_GP_IRQ_REQUEST0_ADDR, + _REG_GP_IRQ_REQUEST1_ADDR}; + +void irq_raise( + const irq_ID_t ID, + const irq_sw_channel_id_t irq_id) +{ + hrt_address addr; + + OP___assert(ID == IRQ0_ID); + OP___assert(IRQ_BASE[ID] != (hrt_address)-1); + OP___assert(irq_id < N_IRQ_SW_CHANNEL_ID); + + (void)ID; + + addr = IRQ_REQUEST_ADDR[irq_id]; +/* The SW IRQ pins are remapped to offset zero */ + gp_device_reg_store(GP_DEVICE0_ID, + (unsigned int)addr, 1); +#ifdef HRT_CSIM + hrt_sleep(); +#endif + gp_device_reg_store(GP_DEVICE0_ID, + (unsigned int)addr, 0); +return; +} + +void irq_controller_get_state( + const irq_ID_t ID, + irq_controller_state_t *state) +{ + assert(ID < N_IRQ_ID); + assert(state != NULL); + + state->irq_edge = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_EDGE_REG_IDX); + state->irq_mask = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_MASK_REG_IDX); + state->irq_status = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_STATUS_REG_IDX); + state->irq_enable = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX); + state->irq_level_not_pulse = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_EDGE_NOT_PULSE_REG_IDX); +return; +} + +bool any_virq_signal(void) +{ + unsigned int irq_status = irq_reg_load(IRQ0_ID, + _HRT_IRQ_CONTROLLER_STATUS_REG_IDX); + +return (irq_status != 0); +} + +void cnd_virq_enable_channel( + const virq_id_t irq_ID, + const bool en) +{ + irq_ID_t i; + unsigned int channel_ID; + irq_ID_t ID = virq_get_irq_id(irq_ID, &channel_ID); + + assert(ID < N_IRQ_ID); + + for (i=IRQ1_ID;iirq_status_reg[ID] |= irq_data; + + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, irq_data); + + irq_wait_for_write_complete(ID); + } + } + +return irq_status; +} + +void virq_clear_info( + virq_info_t *irq_info) +{ + irq_ID_t ID; + + assert(irq_info != NULL); + + for (ID = (irq_ID_t)0 ; ID < N_IRQ_ID; ID++) { + irq_info->irq_status_reg[ID] = 0; + } +return; +} + +enum hrt_isp_css_irq_status virq_get_channel_id( + virq_id_t *irq_id) +{ + unsigned int irq_status = irq_reg_load(IRQ0_ID, + _HRT_IRQ_CONTROLLER_STATUS_REG_IDX); + unsigned int idx; + enum hrt_isp_css_irq_status status = hrt_isp_css_irq_status_success; + irq_ID_t ID; + + assert(irq_id != NULL); + +/* find the first irq bit on device 0 */ + for (idx = 0; idx < IRQ_N_CHANNEL[IRQ0_ID]; idx++) { + if (irq_status & (1U << idx)) + break; + } + + if (idx == IRQ_N_CHANNEL[IRQ0_ID]) { + return hrt_isp_css_irq_status_error; + } + +/* Check whether there are more bits set on device 0 */ + if (irq_status != (1U << idx)) { + status = hrt_isp_css_irq_status_more_irqs; + } + +/* Check whether we have an IRQ on one of the nested devices */ + for (ID = N_IRQ_ID-1 ; ID > (irq_ID_t)0; ID--) { + if (IRQ_NESTING_ID[ID] == (virq_id_t)idx) { + break; + } + } + +/* If we have a nested IRQ, load that state, discard the device 0 state */ + if (ID != IRQ0_ID) { + irq_status = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_STATUS_REG_IDX); +/* find the first irq bit on device "id" */ + for (idx = 0; idx < IRQ_N_CHANNEL[ID]; idx++) { + if (irq_status & (1U << idx)) + break; + } + + if (idx == IRQ_N_CHANNEL[ID]) { + return hrt_isp_css_irq_status_error; + } + +/* Alternatively check whether there are more bits set on this device */ + if (irq_status != (1U << idx)) { + status = hrt_isp_css_irq_status_more_irqs; + } else { +/* If this device is empty, clear the state on device 0 */ + irq_reg_store(IRQ0_ID, + _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, 1U << IRQ_NESTING_ID[ID]); + } + } /* if (ID != IRQ0_ID) */ + +/* Here we proceed to clear the IRQ on detected device, if no nested IRQ, this is device 0 */ + irq_reg_store(ID, + _HRT_IRQ_CONTROLLER_CLEAR_REG_IDX, 1U << idx); + + irq_wait_for_write_complete(ID); + + idx += IRQ_N_ID_OFFSET[ID]; + if (irq_id != NULL) + *irq_id = (virq_id_t)idx; + +return status; +} + +STORAGE_CLASS_INLINE void irq_wait_for_write_complete( + const irq_ID_t ID) +{ +assert(ID < N_IRQ_ID); +assert(IRQ_BASE[ID] != (hrt_address)-1); + (void)ia_css_device_load_uint32(IRQ_BASE[ID] + + _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX*sizeof(hrt_data)); +#ifdef HRT_CSIM + hrt_sleep(); +#endif +return; +} + +STORAGE_CLASS_INLINE bool any_irq_channel_enabled( + const irq_ID_t ID) +{ + hrt_data en_reg; + + assert(ID < N_IRQ_ID); + + en_reg = irq_reg_load(ID, + _HRT_IRQ_CONTROLLER_ENABLE_REG_IDX); + +return (en_reg != 0); +} + +STORAGE_CLASS_INLINE irq_ID_t virq_get_irq_id( + const virq_id_t irq_ID, + unsigned int *channel_ID) +{ + irq_ID_t ID; + + assert(channel_ID != NULL); + + for (ID = (irq_ID_t)0 ; ID < N_IRQ_ID; ID++) { + if (irq_ID < IRQ_N_ID_OFFSET[ID + 1]) { + break; + } + } + + *channel_ID = (unsigned int)irq_ID - IRQ_N_ID_OFFSET[ID]; + +return ID; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/irq_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/irq_local.h new file mode 100644 index 0000000000000000000000000000000000000000..f522dfd1a9f1a33c0daac921c1b5f0d6bbe92c5f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/irq_local.h @@ -0,0 +1,136 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IRQ_LOCAL_H_INCLUDED__ +#define __IRQ_LOCAL_H_INCLUDED__ + +#include "irq_global.h" + +#include + +/* IRQ0_ID */ +#include "hive_isp_css_defs.h" +#define HIVE_GP_DEV_IRQ_NUM_IRQS 32 +/* IRQ1_ID */ +#include "input_formatter_subsystem_defs.h" +#define HIVE_IFMT_IRQ_NUM_IRQS 5 +/* IRQ2_ID */ +#include "input_system_defs.h" +/* IRQ3_ID */ +#include "input_selector_defs.h" + + +#define IRQ_ID_OFFSET 32 +#define IRQ0_ID_OFFSET 0 +#define IRQ1_ID_OFFSET IRQ_ID_OFFSET +#define IRQ2_ID_OFFSET (2*IRQ_ID_OFFSET) +#define IRQ3_ID_OFFSET (3*IRQ_ID_OFFSET) +#define IRQ_END_OFFSET (4*IRQ_ID_OFFSET) + +#define IRQ0_ID_N_CHANNEL HIVE_GP_DEV_IRQ_NUM_IRQS +#define IRQ1_ID_N_CHANNEL HIVE_IFMT_IRQ_NUM_IRQS +#define IRQ2_ID_N_CHANNEL HIVE_ISYS_IRQ_NUM_BITS +#define IRQ3_ID_N_CHANNEL HIVE_ISEL_IRQ_NUM_IRQS + +typedef struct virq_info_s virq_info_t; +typedef struct irq_controller_state_s irq_controller_state_t; + + +typedef enum { + virq_gpio_pin_0 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_0_BIT_ID, + virq_gpio_pin_1 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_1_BIT_ID, + virq_gpio_pin_2 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_2_BIT_ID, + virq_gpio_pin_3 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_3_BIT_ID, + virq_gpio_pin_4 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_4_BIT_ID, + virq_gpio_pin_5 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_5_BIT_ID, + virq_gpio_pin_6 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_6_BIT_ID, + virq_gpio_pin_7 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_7_BIT_ID, + virq_gpio_pin_8 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_8_BIT_ID, + virq_gpio_pin_9 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_9_BIT_ID, + virq_gpio_pin_10 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_10_BIT_ID, + virq_gpio_pin_11 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GPIO_PIN_11_BIT_ID, + virq_sp = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_SP_BIT_ID, + virq_isp = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_ISP_BIT_ID, + virq_isys = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_ISYS_BIT_ID, + virq_isel = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_ISEL_BIT_ID, + virq_ifmt = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_IFMT_BIT_ID, + virq_sp_stream_mon = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_SP_STREAM_MON_BIT_ID, + virq_isp_stream_mon = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_ISP_STREAM_MON_BIT_ID, + virq_mod_stream_mon = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_MOD_STREAM_MON_BIT_ID, +#if defined(IS_ISP_2400_MAMOIADA_SYSTEM) + virq_isp_pmem_error = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_ISP_PMEM_ERROR_BIT_ID, +#elif defined(IS_ISP_2401_MAMOIADA_SYSTEM) + virq_isys_2401 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_IS2401_BIT_ID, +#else +#error "irq_local.h: 2400_SYSTEM must be one of {2400, 2401 }" +#endif + virq_isp_bamem_error = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_ISP_BAMEM_ERROR_BIT_ID, + virq_isp_dmem_error = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_ISP_DMEM_ERROR_BIT_ID, + virq_sp_icache_mem_error = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_SP_ICACHE_MEM_ERROR_BIT_ID, + virq_sp_dmem_error = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_SP_DMEM_ERROR_BIT_ID, + virq_mmu_cache_mem_error = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_MMU_CACHE_MEM_ERROR_BIT_ID, + virq_gp_timer_0 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GP_TIMER_0_BIT_ID, + virq_gp_timer_1 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_GP_TIMER_1_BIT_ID, + virq_sw_pin_0 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_SW_PIN_0_BIT_ID, + virq_sw_pin_1 = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_SW_PIN_1_BIT_ID, + virq_dma = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_DMA_BIT_ID, + virq_sp_stream_mon_b = IRQ0_ID_OFFSET + HIVE_GP_DEV_IRQ_SP_STREAM_MON_B_BIT_ID, + + virq_ifmt0_id = IRQ1_ID_OFFSET + HIVE_IFMT_IRQ_IFT_PRIM_BIT_ID, + virq_ifmt1_id = IRQ1_ID_OFFSET + HIVE_IFMT_IRQ_IFT_PRIM_B_BIT_ID, + virq_ifmt2_id = IRQ1_ID_OFFSET + HIVE_IFMT_IRQ_IFT_SEC_BIT_ID, + virq_ifmt3_id = IRQ1_ID_OFFSET + HIVE_IFMT_IRQ_MEM_CPY_BIT_ID, + virq_ifmt_sideband_changed = IRQ1_ID_OFFSET + HIVE_IFMT_IRQ_SIDEBAND_CHANGED_BIT_ID, + + virq_isys_sof = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CSI_SOF_BIT_ID, + virq_isys_eof = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CSI_EOF_BIT_ID, + virq_isys_sol = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CSI_SOL_BIT_ID, + virq_isys_eol = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CSI_EOL_BIT_ID, + virq_isys_csi = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CSI_RECEIVER_BIT_ID, + virq_isys_csi_be = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CSI_RECEIVER_BE_BIT_ID, + virq_isys_capt0_id_no_sop = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_A_NO_SOP, + virq_isys_capt0_id_late_sop= IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_A_LATE_SOP, + virq_isys_capt1_id_no_sop = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_B_NO_SOP, + virq_isys_capt1_id_late_sop= IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_B_LATE_SOP, + virq_isys_capt2_id_no_sop = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_C_NO_SOP, + virq_isys_capt2_id_late_sop= IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CAP_UNIT_C_LATE_SOP, + virq_isys_acq_sop_mismatch = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_ACQ_UNIT_SOP_MISMATCH, + virq_isys_ctrl_capt0 = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_INP_CTRL_CAPA, + virq_isys_ctrl_capt1 = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_INP_CTRL_CAPB, + virq_isys_ctrl_capt2 = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_INP_CTRL_CAPC, + virq_isys_cio_to_ahb = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_CIO2AHB, + virq_isys_dma = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_DMA_BIT_ID, + virq_isys_fifo_monitor = IRQ2_ID_OFFSET + HIVE_ISYS_IRQ_STREAM_MON_BIT_ID, + + virq_isel_sof = IRQ3_ID_OFFSET + HIVE_ISEL_IRQ_SYNC_GEN_SOF_BIT_ID, + virq_isel_eof = IRQ3_ID_OFFSET + HIVE_ISEL_IRQ_SYNC_GEN_EOF_BIT_ID, + virq_isel_sol = IRQ3_ID_OFFSET + HIVE_ISEL_IRQ_SYNC_GEN_SOL_BIT_ID, + virq_isel_eol = IRQ3_ID_OFFSET + HIVE_ISEL_IRQ_SYNC_GEN_EOL_BIT_ID, + + N_virq_id = IRQ_END_OFFSET +} virq_id_t; + +struct virq_info_s { + hrt_data irq_status_reg[N_IRQ_ID]; +}; + +struct irq_controller_state_s { + unsigned int irq_edge; + unsigned int irq_mask; + unsigned int irq_status; + unsigned int irq_enable; + unsigned int irq_level_not_pulse; +}; + +#endif /* __IRQ_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/irq_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/irq_private.h new file mode 100644 index 0000000000000000000000000000000000000000..eb325e870e88e6a4d4a159a873d6e7a324cf13d7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/irq_private.h @@ -0,0 +1,44 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IRQ_PRIVATE_H_INCLUDED__ +#define __IRQ_PRIVATE_H_INCLUDED__ + +#include "irq_public.h" + +#include "device_access.h" + +#include "assert_support.h" + +STORAGE_CLASS_IRQ_C void irq_reg_store( + const irq_ID_t ID, + const unsigned int reg, + const hrt_data value) +{ +assert(ID < N_IRQ_ID); +assert(IRQ_BASE[ID] != (hrt_address)-1); + ia_css_device_store_uint32(IRQ_BASE[ID] + reg*sizeof(hrt_data), value); +return; +} + +STORAGE_CLASS_IRQ_C hrt_data irq_reg_load( + const irq_ID_t ID, + const unsigned int reg) +{ +assert(ID < N_IRQ_ID); +assert(IRQ_BASE[ID] != (hrt_address)-1); +return ia_css_device_load_uint32(IRQ_BASE[ID] + reg*sizeof(hrt_data)); +} + +#endif /* __IRQ_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/isp.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/isp.c new file mode 100644 index 0000000000000000000000000000000000000000..211c7605801507cbd30ae8e41316212ce8322313 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/isp.c @@ -0,0 +1,148 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include "isp.h" + +#ifndef __INLINE_ISP__ +#include "isp_private.h" +#endif /* __INLINE_ISP__ */ + +#include "assert_support.h" +#include "platform_support.h" /* hrt_sleep() */ + +void cnd_isp_irq_enable( + const isp_ID_t ID, + const bool cnd) +{ + if (cnd) { + isp_ctrl_setbit(ID, ISP_IRQ_READY_REG, ISP_IRQ_READY_BIT); +/* Enabling the IRQ immediately triggers an interrupt, clear it */ + isp_ctrl_setbit(ID, ISP_IRQ_CLEAR_REG, ISP_IRQ_CLEAR_BIT); + } else { + isp_ctrl_clearbit(ID, ISP_IRQ_READY_REG, + ISP_IRQ_READY_BIT); + } +return; +} + +void isp_get_state( + const isp_ID_t ID, + isp_state_t *state, + isp_stall_t *stall) +{ + hrt_data sc = isp_ctrl_load(ID, ISP_SC_REG); + + assert(state != NULL); + assert(stall != NULL); + +#if defined(_hrt_sysmem_ident_address) + /* Patch to avoid compiler unused symbol warning in C_RUN build */ + (void)__hrt_sysmem_ident_address; + (void)_hrt_sysmem_map_var; +#endif + + state->pc = isp_ctrl_load(ID, ISP_PC_REG); + state->status_register = sc; + state->is_broken = isp_ctrl_getbit(ID, ISP_SC_REG, ISP_BROKEN_BIT); + state->is_idle = isp_ctrl_getbit(ID, ISP_SC_REG, ISP_IDLE_BIT); + state->is_sleeping = isp_ctrl_getbit(ID, ISP_SC_REG, ISP_SLEEPING_BIT); + state->is_stalling = isp_ctrl_getbit(ID, ISP_SC_REG, ISP_STALLING_BIT); + stall->stat_ctrl = + !isp_ctrl_getbit(ID, ISP_CTRL_SINK_REG, ISP_CTRL_SINK_BIT); + stall->pmem = + !isp_ctrl_getbit(ID, ISP_PMEM_SINK_REG, ISP_PMEM_SINK_BIT); + stall->dmem = + !isp_ctrl_getbit(ID, ISP_DMEM_SINK_REG, ISP_DMEM_SINK_BIT); + stall->vmem = + !isp_ctrl_getbit(ID, ISP_VMEM_SINK_REG, ISP_VMEM_SINK_BIT); + stall->fifo0 = + !isp_ctrl_getbit(ID, ISP_FIFO0_SINK_REG, ISP_FIFO0_SINK_BIT); + stall->fifo1 = + !isp_ctrl_getbit(ID, ISP_FIFO1_SINK_REG, ISP_FIFO1_SINK_BIT); + stall->fifo2 = + !isp_ctrl_getbit(ID, ISP_FIFO2_SINK_REG, ISP_FIFO2_SINK_BIT); + stall->fifo3 = + !isp_ctrl_getbit(ID, ISP_FIFO3_SINK_REG, ISP_FIFO3_SINK_BIT); + stall->fifo4 = + !isp_ctrl_getbit(ID, ISP_FIFO4_SINK_REG, ISP_FIFO4_SINK_BIT); + stall->fifo5 = + !isp_ctrl_getbit(ID, ISP_FIFO5_SINK_REG, ISP_FIFO5_SINK_BIT); + stall->fifo6 = + !isp_ctrl_getbit(ID, ISP_FIFO6_SINK_REG, ISP_FIFO6_SINK_BIT); + stall->vamem1 = + !isp_ctrl_getbit(ID, ISP_VAMEM1_SINK_REG, ISP_VAMEM1_SINK_BIT); + stall->vamem2 = + !isp_ctrl_getbit(ID, ISP_VAMEM2_SINK_REG, ISP_VAMEM2_SINK_BIT); + stall->vamem3 = + !isp_ctrl_getbit(ID, ISP_VAMEM3_SINK_REG, ISP_VAMEM3_SINK_BIT); + stall->hmem = + !isp_ctrl_getbit(ID, ISP_HMEM_SINK_REG, ISP_HMEM_SINK_BIT); +/* + stall->icache_master = + !isp_ctrl_getbit(ID, ISP_ICACHE_MT_SINK_REG, + ISP_ICACHE_MT_SINK_BIT); + */ +return; +} + +/* ISP functions to control the ISP state from the host, even in crun. */ +#ifdef C_RUN +volatile uint32_t isp_sleeping[N_ISP_ID] = { 0 }; /* Sleeping state per ISP */ +volatile uint32_t isp_ready [N_ISP_ID] = { 1 }; /* Ready state per ISP */ +#endif + +/* Inspect readiness of an ISP indexed by ID */ +unsigned isp_is_ready(isp_ID_t ID) +{ + assert (ID < N_ISP_ID); +#ifdef C_RUN + return isp_ready[ID]; +#else + return isp_ctrl_getbit(ID, ISP_SC_REG, ISP_IDLE_BIT); +#endif +} + +/* Inspect sleeping of an ISP indexed by ID */ +unsigned isp_is_sleeping(isp_ID_t ID) +{ + assert (ID < N_ISP_ID); +#ifdef C_RUN + return isp_sleeping[ID]; +#else + return isp_ctrl_getbit(ID, ISP_SC_REG, ISP_SLEEPING_BIT); +#endif +} + +/* To be called by the host immediately before starting ISP ID. */ +void isp_start(isp_ID_t ID) +{ + assert (ID < N_ISP_ID); +#ifdef C_RUN + isp_ready[ID] = 0; +#endif +} + +/* Wake up ISP ID. */ +void isp_wake(isp_ID_t ID) +{ + assert (ID < N_ISP_ID); +#ifdef C_RUN + isp_sleeping[ID] = 0; +#else + isp_ctrl_setbit(ID, ISP_SC_REG, ISP_START_BIT); + hrt_sleep(); +#endif +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/isp_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/isp_local.h new file mode 100644 index 0000000000000000000000000000000000000000..5dcc52dff3dd4c5c38cd0b7f4c22c6c5a49ccae8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/isp_local.h @@ -0,0 +1,57 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISP_LOCAL_H_INCLUDED__ +#define __ISP_LOCAL_H_INCLUDED__ + +#include + +#include "isp_global.h" + +#include + +#define HIVE_ISP_VMEM_MASK ((1U< +#endif + +#include "isp_public.h" + +#ifdef C_RUN +#include /* memcpy() */ +#endif + +#include "device_access.h" + +#include "assert_support.h" +#include "type_support.h" + +STORAGE_CLASS_ISP_C void isp_ctrl_store( + const isp_ID_t ID, + const unsigned int reg, + const hrt_data value) +{ + assert(ID < N_ISP_ID); + assert(ISP_CTRL_BASE[ID] != (hrt_address)-1); +#if !defined(HRT_MEMORY_ACCESS) + ia_css_device_store_uint32(ISP_CTRL_BASE[ID] + reg*sizeof(hrt_data), value); +#else + hrt_master_port_store_32(ISP_CTRL_BASE[ID] + reg*sizeof(hrt_data), value); +#endif + return; +} + +STORAGE_CLASS_ISP_C hrt_data isp_ctrl_load( + const isp_ID_t ID, + const unsigned int reg) +{ + assert(ID < N_ISP_ID); + assert(ISP_CTRL_BASE[ID] != (hrt_address)-1); +#if !defined(HRT_MEMORY_ACCESS) + return ia_css_device_load_uint32(ISP_CTRL_BASE[ID] + reg*sizeof(hrt_data)); +#else + return hrt_master_port_uload_32(ISP_CTRL_BASE[ID] + reg*sizeof(hrt_data)); +#endif +} + +STORAGE_CLASS_ISP_C bool isp_ctrl_getbit( + const isp_ID_t ID, + const unsigned int reg, + const unsigned int bit) +{ + hrt_data val = isp_ctrl_load(ID, reg); + return (val & (1UL << bit)) != 0; +} + +STORAGE_CLASS_ISP_C void isp_ctrl_setbit( + const isp_ID_t ID, + const unsigned int reg, + const unsigned int bit) +{ + hrt_data data = isp_ctrl_load(ID, reg); + isp_ctrl_store(ID, reg, (data | (1UL << bit))); + return; +} + +STORAGE_CLASS_ISP_C void isp_ctrl_clearbit( + const isp_ID_t ID, + const unsigned int reg, + const unsigned int bit) +{ + hrt_data data = isp_ctrl_load(ID, reg); + isp_ctrl_store(ID, reg, (data & ~(1UL << bit))); + return; +} + +STORAGE_CLASS_ISP_C void isp_dmem_store( + const isp_ID_t ID, + unsigned int addr, + const void *data, + const size_t size) +{ + assert(ID < N_ISP_ID); + assert(ISP_DMEM_BASE[ID] != (hrt_address)-1); +#ifdef C_RUN + memcpy((void *)addr, data, size); +#elif !defined(HRT_MEMORY_ACCESS) + ia_css_device_store(ISP_DMEM_BASE[ID] + addr, data, size); +#else + hrt_master_port_store(ISP_DMEM_BASE[ID] + addr, data, size); +#endif + return; +} + +STORAGE_CLASS_ISP_C void isp_dmem_load( + const isp_ID_t ID, + const unsigned int addr, + void *data, + const size_t size) +{ + assert(ID < N_ISP_ID); + assert(ISP_DMEM_BASE[ID] != (hrt_address)-1); +#ifdef C_RUN + memcpy(data, (void *)addr, size); +#elif !defined(HRT_MEMORY_ACCESS) + ia_css_device_load(ISP_DMEM_BASE[ID] + addr, data, size); +#else + hrt_master_port_load(ISP_DMEM_BASE[ID] + addr, data, size); +#endif + return; +} + +STORAGE_CLASS_ISP_C void isp_dmem_store_uint32( + const isp_ID_t ID, + unsigned int addr, + const uint32_t data) +{ + assert(ID < N_ISP_ID); + assert(ISP_DMEM_BASE[ID] != (hrt_address)-1); + (void)ID; +#ifdef C_RUN + *(uint32_t *)addr = data; +#elif !defined(HRT_MEMORY_ACCESS) + ia_css_device_store_uint32(ISP_DMEM_BASE[ID] + addr, data); +#else + hrt_master_port_store_32(ISP_DMEM_BASE[ID] + addr, data); +#endif + return; +} + +STORAGE_CLASS_ISP_C uint32_t isp_dmem_load_uint32( + const isp_ID_t ID, + const unsigned int addr) +{ + assert(ID < N_ISP_ID); + assert(ISP_DMEM_BASE[ID] != (hrt_address)-1); + (void)ID; +#ifdef C_RUN + return *(uint32_t *)addr; +#elif !defined(HRT_MEMORY_ACCESS) + return ia_css_device_load_uint32(ISP_DMEM_BASE[ID] + addr); +#else + return hrt_master_port_uload_32(ISP_DMEM_BASE[ID] + addr); +#endif +} + +STORAGE_CLASS_ISP_C uint32_t isp_2w_cat_1w( + const uint16_t x0, + const uint16_t x1) +{ + uint32_t out = ((uint32_t)(x1 & HIVE_ISP_VMEM_MASK) << ISP_VMEM_ELEMBITS) + | (x0 & HIVE_ISP_VMEM_MASK); + return out; +} + +#endif /* __ISP_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/mmu.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/mmu.c new file mode 100644 index 0000000000000000000000000000000000000000..b75d0f85d524d2cdac785643b764b5d4bf9fd4a3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/mmu.c @@ -0,0 +1,50 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* The name "mmu.h is already taken" */ +#include "mmu_device.h" + +#ifndef __INLINE_MMU__ +#include "mmu_private.h" +#endif /* __INLINE_MMU__ */ + +void mmu_set_page_table_base_index( + const mmu_ID_t ID, + const hrt_data base_index) +{ + mmu_reg_store(ID, _HRT_MMU_PAGE_TABLE_BASE_ADDRESS_REG_IDX, base_index); +return; +} + +hrt_data mmu_get_page_table_base_index( + const mmu_ID_t ID) +{ +return mmu_reg_load(ID, _HRT_MMU_PAGE_TABLE_BASE_ADDRESS_REG_IDX); +} + +void mmu_invalidate_cache( + const mmu_ID_t ID) +{ + mmu_reg_store(ID, _HRT_MMU_INVALIDATE_TLB_REG_IDX, 1); +return; +} + +void mmu_invalidate_cache_all(void) +{ + mmu_ID_t mmu_id; + for (mmu_id = (mmu_ID_t)0;mmu_id < N_MMU_ID; mmu_id++) { + mmu_invalidate_cache(mmu_id); + } +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/mmu_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/mmu_local.h new file mode 100644 index 0000000000000000000000000000000000000000..7c3ad157189f4a0fed41e56acd12bc85ee3c8791 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/mmu_local.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __MMU_LOCAL_H_INCLUDED__ +#define __MMU_LOCAL_H_INCLUDED__ + +#include "mmu_global.h" + +#endif /* __MMU_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/mmu_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/mmu_private.h new file mode 100644 index 0000000000000000000000000000000000000000..392b6cc24e8f2f5525fb7d0ec5dbfcc5587b1649 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/mmu_private.h @@ -0,0 +1,44 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __MMU_PRIVATE_H_INCLUDED__ +#define __MMU_PRIVATE_H_INCLUDED__ + +#include "mmu_public.h" + +#include "device_access.h" + +#include "assert_support.h" + +STORAGE_CLASS_MMU_H void mmu_reg_store( + const mmu_ID_t ID, + const unsigned int reg, + const hrt_data value) +{ +assert(ID < N_MMU_ID); +assert(MMU_BASE[ID] != (hrt_address)-1); + ia_css_device_store_uint32(MMU_BASE[ID] + reg*sizeof(hrt_data), value); +return; +} + +STORAGE_CLASS_MMU_H hrt_data mmu_reg_load( + const mmu_ID_t ID, + const unsigned int reg) +{ +assert(ID < N_MMU_ID); +assert(MMU_BASE[ID] != (hrt_address)-1); +return ia_css_device_load_uint32(MMU_BASE[ID] + reg*sizeof(hrt_data)); +} + +#endif /* __MMU_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/sp.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/sp.c new file mode 100644 index 0000000000000000000000000000000000000000..db694d3a6fbb60c5dacca139b480d8fb106a65e9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/sp.c @@ -0,0 +1,81 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "sp.h" + +#ifndef __INLINE_SP__ +#include "sp_private.h" +#endif /* __INLINE_SP__ */ + +#include "assert_support.h" + +void cnd_sp_irq_enable( + const sp_ID_t ID, + const bool cnd) +{ + if (cnd) { + sp_ctrl_setbit(ID, SP_IRQ_READY_REG, SP_IRQ_READY_BIT); +/* Enabling the IRQ immediately triggers an interrupt, clear it */ + sp_ctrl_setbit(ID, SP_IRQ_CLEAR_REG, SP_IRQ_CLEAR_BIT); + } else { + sp_ctrl_clearbit(ID, SP_IRQ_READY_REG, SP_IRQ_READY_BIT); + } +} + +void sp_get_state( + const sp_ID_t ID, + sp_state_t *state, + sp_stall_t *stall) +{ + hrt_data sc = sp_ctrl_load(ID, SP_SC_REG); + + assert(state != NULL); + assert(stall != NULL); + + state->pc = sp_ctrl_load(ID, SP_PC_REG); + state->status_register = sc; + state->is_broken = (sc & (1U << SP_BROKEN_BIT)) != 0; + state->is_idle = (sc & (1U << SP_IDLE_BIT)) != 0; + state->is_sleeping = (sc & (1U << SP_SLEEPING_BIT)) != 0; + state->is_stalling = (sc & (1U << SP_STALLING_BIT)) != 0; + stall->fifo0 = + !sp_ctrl_getbit(ID, SP_FIFO0_SINK_REG, SP_FIFO0_SINK_BIT); + stall->fifo1 = + !sp_ctrl_getbit(ID, SP_FIFO1_SINK_REG, SP_FIFO1_SINK_BIT); + stall->fifo2 = + !sp_ctrl_getbit(ID, SP_FIFO2_SINK_REG, SP_FIFO2_SINK_BIT); + stall->fifo3 = + !sp_ctrl_getbit(ID, SP_FIFO3_SINK_REG, SP_FIFO3_SINK_BIT); + stall->fifo4 = + !sp_ctrl_getbit(ID, SP_FIFO4_SINK_REG, SP_FIFO4_SINK_BIT); + stall->fifo5 = + !sp_ctrl_getbit(ID, SP_FIFO5_SINK_REG, SP_FIFO5_SINK_BIT); + stall->fifo6 = + !sp_ctrl_getbit(ID, SP_FIFO6_SINK_REG, SP_FIFO6_SINK_BIT); + stall->fifo7 = + !sp_ctrl_getbit(ID, SP_FIFO7_SINK_REG, SP_FIFO7_SINK_BIT); + stall->fifo8 = + !sp_ctrl_getbit(ID, SP_FIFO8_SINK_REG, SP_FIFO8_SINK_BIT); + stall->fifo9 = + !sp_ctrl_getbit(ID, SP_FIFO9_SINK_REG, SP_FIFO9_SINK_BIT); + stall->fifoa = + !sp_ctrl_getbit(ID, SP_FIFOA_SINK_REG, SP_FIFOA_SINK_BIT); + stall->dmem = + !sp_ctrl_getbit(ID, SP_DMEM_SINK_REG, SP_DMEM_SINK_BIT); + stall->control_master = + !sp_ctrl_getbit(ID, SP_CTRL_MT_SINK_REG, SP_CTRL_MT_SINK_BIT); + stall->icache_master = + !sp_ctrl_getbit(ID, SP_ICACHE_MT_SINK_REG, + SP_ICACHE_MT_SINK_BIT); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/sp_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/sp_local.h new file mode 100644 index 0000000000000000000000000000000000000000..59d85eb319c780fe6a63fa8ee934ecef90b25c02 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/sp_local.h @@ -0,0 +1,124 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SP_LOCAL_H_INCLUDED__ +#define __SP_LOCAL_H_INCLUDED__ + +#include +#include "sp_global.h" + +struct sp_state_s { + int pc; + int status_register; + bool is_broken; + bool is_idle; + bool is_sleeping; + bool is_stalling; +}; + +struct sp_stall_s { + bool fifo0; + bool fifo1; + bool fifo2; + bool fifo3; + bool fifo4; + bool fifo5; + bool fifo6; + bool fifo7; + bool fifo8; + bool fifo9; + bool fifoa; + bool dmem; + bool control_master; + bool icache_master; +}; + +#ifdef C_RUN +#include "hive_isp_css_sp_hrt.h" +#define sp_address_of(var) _hrt_cell_get_crun_indexed_symbol(SP, var) +#ifdef C_RUN_DYNAMIC_LINK_PROGRAMS +#ifndef DUMMY_HRT_SYSMEM_FUNCTIONS +#define DUMMY_HRT_SYSMEM_FUNCTIONS +/* These two inline functions prevent gcc from generating compiler warnings + * about unused static functions. */ +static inline void * +dummy__hrt_sysmem_ident_address(hive_device_id mem, const char *sym) +{ + return __hrt_sysmem_ident_address(mem, sym); +} + +static inline void +dummy_hrt_sysmem_map_var(hive_mem_id mem, const char *ident, volatile void *native_address, unsigned int size) +{ + _hrt_sysmem_map_var(mem, ident, native_address, size); +} +#endif /* DUMMY_HRT_SYSMEM_FUNCTIONS */ +#endif /* C_RUN */ +#else +#define sp_address_of(var) (HIVE_ADDR_ ## var) +#endif + +/* + * deprecated + */ +#define store_sp_int(var, value) \ + sp_dmem_store_uint32(SP0_ID, (unsigned)sp_address_of(var), \ + (uint32_t)(value)) + +#define store_sp_ptr(var, value) \ + sp_dmem_store_uint32(SP0_ID, (unsigned)sp_address_of(var), \ + (uint32_t)(value)) + +#define load_sp_uint(var) \ + sp_dmem_load_uint32(SP0_ID, (unsigned)sp_address_of(var)) + +#define load_sp_array_uint8(array_name, index) \ + sp_dmem_load_uint8(SP0_ID, (unsigned)sp_address_of(array_name) + \ + (index)*sizeof(uint8_t)) + +#define load_sp_array_uint16(array_name, index) \ + sp_dmem_load_uint16(SP0_ID, (unsigned)sp_address_of(array_name) + \ + (index)*sizeof(uint16_t)) + +#define load_sp_array_uint(array_name, index) \ + sp_dmem_load_uint32(SP0_ID, (unsigned)sp_address_of(array_name) + \ + (index)*sizeof(uint32_t)) + +#define store_sp_var(var, data, bytes) \ + sp_dmem_store(SP0_ID, (unsigned)sp_address_of(var), data, bytes) + +#define store_sp_array_uint8(array_name, index, value) \ + sp_dmem_store_uint8(SP0_ID, (unsigned)sp_address_of(array_name) + \ + (index)*sizeof(uint8_t), value) + +#define store_sp_array_uint16(array_name, index, value) \ + sp_dmem_store_uint16(SP0_ID, (unsigned)sp_address_of(array_name) + \ + (index)*sizeof(uint16_t), value) + +#define store_sp_array_uint(array_name, index, value) \ + sp_dmem_store_uint32(SP0_ID, (unsigned)sp_address_of(array_name) + \ + (index)*sizeof(uint32_t), value) + +#define store_sp_var_with_offset(var, offset, data, bytes) \ + sp_dmem_store(SP0_ID, (unsigned)sp_address_of(var) + \ + offset, data, bytes) + +#define load_sp_var(var, data, bytes) \ + sp_dmem_load(SP0_ID, (unsigned)sp_address_of(var), data, bytes) + +#define load_sp_var_with_offset(var, offset, data, bytes) \ + sp_dmem_load(SP0_ID, (unsigned)sp_address_of(var) + offset, \ + data, bytes) + +#endif /* __SP_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/sp_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/sp_private.h new file mode 100644 index 0000000000000000000000000000000000000000..3ee9ec2fdfa52862a888e1259f0cea0b56e2e7f6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/sp_private.h @@ -0,0 +1,198 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SP_PRIVATE_H_INCLUDED__ +#define __SP_PRIVATE_H_INCLUDED__ + +#include "sp_public.h" + +#include "device_access.h" +#ifdef C_RUN +#include /* memcpy() */ +#endif + +#include "assert_support.h" + +STORAGE_CLASS_SP_C void sp_ctrl_store( + const sp_ID_t ID, + const hrt_address reg, + const hrt_data value) +{ +assert(ID < N_SP_ID); +assert(SP_CTRL_BASE[ID] != (hrt_address)-1); + ia_css_device_store_uint32(SP_CTRL_BASE[ID] + reg*sizeof(hrt_data), value); +return; +} + +STORAGE_CLASS_SP_C hrt_data sp_ctrl_load( + const sp_ID_t ID, + const hrt_address reg) +{ +assert(ID < N_SP_ID); +assert(SP_CTRL_BASE[ID] != (hrt_address)-1); +return ia_css_device_load_uint32(SP_CTRL_BASE[ID] + reg*sizeof(hrt_data)); +} + +STORAGE_CLASS_SP_C bool sp_ctrl_getbit( + const sp_ID_t ID, + const hrt_address reg, + const unsigned int bit) +{ + hrt_data val = sp_ctrl_load(ID, reg); +return (val & (1UL << bit)) != 0; +} + +STORAGE_CLASS_SP_C void sp_ctrl_setbit( + const sp_ID_t ID, + const hrt_address reg, + const unsigned int bit) +{ + hrt_data data = sp_ctrl_load(ID, reg); + sp_ctrl_store(ID, reg, (data | (1UL << bit))); +return; +} + +STORAGE_CLASS_SP_C void sp_ctrl_clearbit( + const sp_ID_t ID, + const hrt_address reg, + const unsigned int bit) +{ + hrt_data data = sp_ctrl_load(ID, reg); + sp_ctrl_store(ID, reg, (data & ~(1UL << bit))); +return; +} + +STORAGE_CLASS_SP_C void sp_dmem_store( + const sp_ID_t ID, + hrt_address addr, + const void *data, + const size_t size) +{ +assert(ID < N_SP_ID); +assert(SP_DMEM_BASE[ID] != (hrt_address)-1); +#ifndef C_RUN + ia_css_device_store(SP_DMEM_BASE[ID] + addr, data, size); +#else + memcpy((void *)(uint32_t)addr, data, size); +#endif +return; +} + +STORAGE_CLASS_SP_C void sp_dmem_load( + const sp_ID_t ID, + const hrt_address addr, + void *data, + const size_t size) +{ +assert(ID < N_SP_ID); +assert(SP_DMEM_BASE[ID] != (hrt_address)-1); +#ifndef C_RUN + ia_css_device_load(SP_DMEM_BASE[ID] + addr, data, size); +#else + memcpy(data, (void *)(uint32_t)addr, size); +#endif +return; +} + +STORAGE_CLASS_SP_C void sp_dmem_store_uint8( + const sp_ID_t ID, + hrt_address addr, + const uint8_t data) +{ +assert(ID < N_SP_ID); +assert(SP_DMEM_BASE[ID] != (hrt_address)-1); + (void)ID; +#ifndef C_RUN + ia_css_device_store_uint8(SP_DMEM_BASE[SP0_ID] + addr, data); +#else + *(uint8_t *)(uint32_t)addr = data; +#endif +return; +} + +STORAGE_CLASS_SP_C void sp_dmem_store_uint16( + const sp_ID_t ID, + hrt_address addr, + const uint16_t data) +{ +assert(ID < N_SP_ID); +assert(SP_DMEM_BASE[ID] != (hrt_address)-1); + (void)ID; +#ifndef C_RUN + ia_css_device_store_uint16(SP_DMEM_BASE[SP0_ID] + addr, data); +#else + *(uint16_t *)(uint32_t)addr = data; +#endif +return; +} + +STORAGE_CLASS_SP_C void sp_dmem_store_uint32( + const sp_ID_t ID, + hrt_address addr, + const uint32_t data) +{ +assert(ID < N_SP_ID); +assert(SP_DMEM_BASE[ID] != (hrt_address)-1); + (void)ID; +#ifndef C_RUN + ia_css_device_store_uint32(SP_DMEM_BASE[SP0_ID] + addr, data); +#else + *(uint32_t *)(uint32_t)addr = data; +#endif +return; +} + +STORAGE_CLASS_SP_C uint8_t sp_dmem_load_uint8( + const sp_ID_t ID, + const hrt_address addr) +{ +assert(ID < N_SP_ID); +assert(SP_DMEM_BASE[ID] != (hrt_address)-1); + (void)ID; +#ifndef C_RUN + return ia_css_device_load_uint8(SP_DMEM_BASE[SP0_ID] + addr); +#else + return *(uint8_t *)(uint32_t)addr; +#endif +} + +STORAGE_CLASS_SP_C uint16_t sp_dmem_load_uint16( + const sp_ID_t ID, + const hrt_address addr) +{ +assert(ID < N_SP_ID); +assert(SP_DMEM_BASE[ID] != (hrt_address)-1); + (void)ID; +#ifndef C_RUN + return ia_css_device_load_uint16(SP_DMEM_BASE[SP0_ID] + addr); +#else + return *(uint16_t *)(uint32_t)addr; +#endif +} + +STORAGE_CLASS_SP_C uint32_t sp_dmem_load_uint32( + const sp_ID_t ID, + const hrt_address addr) +{ +assert(ID < N_SP_ID); +assert(SP_DMEM_BASE[ID] != (hrt_address)-1); + (void)ID; +#ifndef C_RUN + return ia_css_device_load_uint32(SP_DMEM_BASE[SP0_ID] + addr); +#else + return *(uint32_t *)(uint32_t)addr; +#endif +} + +#endif /* __SP_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/system_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/system_local.h new file mode 100644 index 0000000000000000000000000000000000000000..111b346dfafb7d37af6a0cd8924e46ba77049391 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/system_local.h @@ -0,0 +1,306 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SYSTEM_LOCAL_H_INCLUDED__ +#define __SYSTEM_LOCAL_H_INCLUDED__ + +#ifdef HRT_ISP_CSS_CUSTOM_HOST +#ifndef HRT_USE_VIR_ADDRS +#define HRT_USE_VIR_ADDRS +#endif +/* This interface is deprecated */ +/*#include "hive_isp_css_custom_host_hrt.h"*/ +#endif + +#include "system_global.h" + +#ifdef __FIST__ +#define HRT_ADDRESS_WIDTH 32 /* Surprise, this is a local property and even differs per platform */ +#else +/* HRT assumes 32 by default (see Linux/include/hrt/hive_types.h), overrule it in case it is different */ +#undef HRT_ADDRESS_WIDTH +#define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property */ +#endif + +#if !defined(__KERNEL__) || (1==1) +/* This interface is deprecated */ +#include "hrt/hive_types.h" +#else /* __KERNEL__ */ +#include + +#if HRT_ADDRESS_WIDTH==64 +typedef uint64_t hrt_address; +#elif HRT_ADDRESS_WIDTH==32 +typedef uint32_t hrt_address; +#else +#error "system_local.h: HRT_ADDRESS_WIDTH must be one of {32,64}" +#endif + +typedef uint32_t hrt_vaddress; +typedef uint32_t hrt_data; +#endif /* __KERNEL__ */ + +/* + * Cell specific address maps + */ +#if HRT_ADDRESS_WIDTH==64 + +#define GP_FIFO_BASE ((hrt_address)0x0000000000090104) /* This is NOT a base address */ + +/* DDR */ +static const hrt_address DDR_BASE[N_DDR_ID] = { + (hrt_address)0x0000000120000000ULL}; + +/* ISP */ +static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = { + (hrt_address)0x0000000000020000ULL}; + +static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = { + (hrt_address)0x0000000000200000ULL}; + +static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = { + (hrt_address)0x0000000000100000ULL}; + +static const hrt_address ISP_VAMEM_BASE[N_VAMEM_ID] = { + (hrt_address)0x00000000001C0000ULL, + (hrt_address)0x00000000001D0000ULL, + (hrt_address)0x00000000001E0000ULL}; + +static const hrt_address ISP_HMEM_BASE[N_HMEM_ID] = { + (hrt_address)0x00000000001F0000ULL}; + +/* SP */ +static const hrt_address SP_CTRL_BASE[N_SP_ID] = { + (hrt_address)0x0000000000010000ULL}; + +static const hrt_address SP_DMEM_BASE[N_SP_ID] = { + (hrt_address)0x0000000000300000ULL}; + +static const hrt_address SP_PMEM_BASE[N_SP_ID] = { + (hrt_address)0x00000000000B0000ULL}; + +/* MMU */ +#if defined (IS_ISP_2400_MAMOIADA_SYSTEM) || defined (IS_ISP_2401_MAMOIADA_SYSTEM) +/* + * MMU0_ID: The data MMU + * MMU1_ID: The icache MMU + */ +static const hrt_address MMU_BASE[N_MMU_ID] = { + (hrt_address)0x0000000000070000ULL, + (hrt_address)0x00000000000A0000ULL}; +#else +#error "system_local.h: SYSTEM must be one of {2400, 2401 }" +#endif + +/* DMA */ +static const hrt_address DMA_BASE[N_DMA_ID] = { + (hrt_address)0x0000000000040000ULL}; + +/* IRQ */ +static const hrt_address IRQ_BASE[N_IRQ_ID] = { + (hrt_address)0x0000000000000500ULL, + (hrt_address)0x0000000000030A00ULL, + (hrt_address)0x000000000008C000ULL, + (hrt_address)0x0000000000090200ULL}; +/* + (hrt_address)0x0000000000000500ULL}; + */ + +/* GDC */ +static const hrt_address GDC_BASE[N_GDC_ID] = { + (hrt_address)0x0000000000050000ULL, + (hrt_address)0x0000000000060000ULL}; + +/* FIFO_MONITOR (not a subset of GP_DEVICE) */ +static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = { + (hrt_address)0x0000000000000000ULL}; + +/* +static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = { + (hrt_address)0x0000000000000000ULL}; + +static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = { + (hrt_address)0x0000000000090000ULL}; +*/ + +/* GP_DEVICE (single base for all separate GP_REG instances) */ +static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = { + (hrt_address)0x0000000000000000ULL}; + +/*GP TIMER , all timer registers are inter-twined, + * so, having multiple base addresses for + * different timers does not help*/ +static const hrt_address GP_TIMER_BASE = + (hrt_address)0x0000000000000600ULL; +/* GPIO */ +static const hrt_address GPIO_BASE[N_GPIO_ID] = { + (hrt_address)0x0000000000000400ULL}; + +/* TIMED_CTRL */ +static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = { + (hrt_address)0x0000000000000100ULL}; + + +/* INPUT_FORMATTER */ +static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = { + (hrt_address)0x0000000000030000ULL, + (hrt_address)0x0000000000030200ULL, + (hrt_address)0x0000000000030400ULL, + (hrt_address)0x0000000000030600ULL}; /* memcpy() */ + +/* INPUT_SYSTEM */ +static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = { + (hrt_address)0x0000000000080000ULL}; +/* (hrt_address)0x0000000000081000ULL, */ /* capture A */ +/* (hrt_address)0x0000000000082000ULL, */ /* capture B */ +/* (hrt_address)0x0000000000083000ULL, */ /* capture C */ +/* (hrt_address)0x0000000000084000ULL, */ /* Acquisition */ +/* (hrt_address)0x0000000000085000ULL, */ /* DMA */ +/* (hrt_address)0x0000000000089000ULL, */ /* ctrl */ +/* (hrt_address)0x000000000008A000ULL, */ /* GP regs */ +/* (hrt_address)0x000000000008B000ULL, */ /* FIFO */ +/* (hrt_address)0x000000000008C000ULL, */ /* IRQ */ + +/* RX, the MIPI lane control regs start at offset 0 */ +static const hrt_address RX_BASE[N_RX_ID] = { + (hrt_address)0x0000000000080100ULL}; + +#elif HRT_ADDRESS_WIDTH==32 + +#define GP_FIFO_BASE ((hrt_address)0x00090104) /* This is NOT a base address */ + +/* DDR : Attention, this value not defined in 32-bit */ +static const hrt_address DDR_BASE[N_DDR_ID] = { + (hrt_address)0x00000000UL}; + +/* ISP */ +static const hrt_address ISP_CTRL_BASE[N_ISP_ID] = { + (hrt_address)0x00020000UL}; + +static const hrt_address ISP_DMEM_BASE[N_ISP_ID] = { + (hrt_address)0x00200000UL}; + +static const hrt_address ISP_BAMEM_BASE[N_BAMEM_ID] = { + (hrt_address)0x100000UL}; + +static const hrt_address ISP_VAMEM_BASE[N_VAMEM_ID] = { + (hrt_address)0xffffffffUL, + (hrt_address)0xffffffffUL, + (hrt_address)0xffffffffUL}; + +static const hrt_address ISP_HMEM_BASE[N_HMEM_ID] = { + (hrt_address)0xffffffffUL}; + +/* SP */ +static const hrt_address SP_CTRL_BASE[N_SP_ID] = { + (hrt_address)0x00010000UL}; + +static const hrt_address SP_DMEM_BASE[N_SP_ID] = { + (hrt_address)0x00300000UL}; + +static const hrt_address SP_PMEM_BASE[N_SP_ID] = { + (hrt_address)0x000B0000UL}; + +/* MMU */ +#if defined (IS_ISP_2400_MAMOIADA_SYSTEM) || defined (IS_ISP_2401_MAMOIADA_SYSTEM) +/* + * MMU0_ID: The data MMU + * MMU1_ID: The icache MMU + */ +static const hrt_address MMU_BASE[N_MMU_ID] = { + (hrt_address)0x00070000UL, + (hrt_address)0x000A0000UL}; +#else +#error "system_local.h: SYSTEM must be one of {2400, 2401 }" +#endif + +/* DMA */ +static const hrt_address DMA_BASE[N_DMA_ID] = { + (hrt_address)0x00040000UL}; + +/* IRQ */ +static const hrt_address IRQ_BASE[N_IRQ_ID] = { + (hrt_address)0x00000500UL, + (hrt_address)0x00030A00UL, + (hrt_address)0x0008C000UL, + (hrt_address)0x00090200UL}; +/* + (hrt_address)0x00000500UL}; + */ + +/* GDC */ +static const hrt_address GDC_BASE[N_GDC_ID] = { + (hrt_address)0x00050000UL, + (hrt_address)0x00060000UL}; + +/* FIFO_MONITOR (not a subset of GP_DEVICE) */ +static const hrt_address FIFO_MONITOR_BASE[N_FIFO_MONITOR_ID] = { + (hrt_address)0x00000000UL}; + +/* +static const hrt_address GP_REGS_BASE[N_GP_REGS_ID] = { + (hrt_address)0x00000000UL}; + +static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = { + (hrt_address)0x00090000UL}; +*/ + +/* GP_DEVICE (single base for all separate GP_REG instances) */ +static const hrt_address GP_DEVICE_BASE[N_GP_DEVICE_ID] = { + (hrt_address)0x00000000UL}; + +/*GP TIMER , all timer registers are inter-twined, + * so, having multiple base addresses for + * different timers does not help*/ +static const hrt_address GP_TIMER_BASE = + (hrt_address)0x00000600UL; + +/* GPIO */ +static const hrt_address GPIO_BASE[N_GPIO_ID] = { + (hrt_address)0x00000400UL}; + +/* TIMED_CTRL */ +static const hrt_address TIMED_CTRL_BASE[N_TIMED_CTRL_ID] = { + (hrt_address)0x00000100UL}; + + +/* INPUT_FORMATTER */ +static const hrt_address INPUT_FORMATTER_BASE[N_INPUT_FORMATTER_ID] = { + (hrt_address)0x00030000UL, + (hrt_address)0x00030200UL, + (hrt_address)0x00030400UL}; +/* (hrt_address)0x00030600UL, */ /* memcpy() */ + +/* INPUT_SYSTEM */ +static const hrt_address INPUT_SYSTEM_BASE[N_INPUT_SYSTEM_ID] = { + (hrt_address)0x00080000UL}; +/* (hrt_address)0x00081000UL, */ /* capture A */ +/* (hrt_address)0x00082000UL, */ /* capture B */ +/* (hrt_address)0x00083000UL, */ /* capture C */ +/* (hrt_address)0x00084000UL, */ /* Acquisition */ +/* (hrt_address)0x00085000UL, */ /* DMA */ +/* (hrt_address)0x00089000UL, */ /* ctrl */ +/* (hrt_address)0x0008A000UL, */ /* GP regs */ +/* (hrt_address)0x0008B000UL, */ /* FIFO */ +/* (hrt_address)0x0008C000UL, */ /* IRQ */ + +/* RX, the MIPI lane control regs start at offset 0 */ +static const hrt_address RX_BASE[N_RX_ID] = { + (hrt_address)0x00080100UL}; + +#else +#error "system_local.h: HRT_ADDRESS_WIDTH must be one of {32,64}" +#endif + +#endif /* __SYSTEM_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/timed_ctrl.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/timed_ctrl.c new file mode 100644 index 0000000000000000000000000000000000000000..cd12d74024f75f6a30c2e4fd7f00daf42758dfc1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/timed_ctrl.c @@ -0,0 +1,74 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "timed_ctrl.h" + +#ifndef __INLINE_TIMED_CTRL__ +#include "timed_ctrl_private.h" +#endif /* __INLINE_TIMED_CTRL__ */ + +#include "assert_support.h" + +void timed_ctrl_snd_commnd( + const timed_ctrl_ID_t ID, + hrt_data mask, + hrt_data condition, + hrt_data counter, + hrt_address addr, + hrt_data value) +{ + OP___assert(ID == TIMED_CTRL0_ID); + OP___assert(TIMED_CTRL_BASE[ID] != (hrt_address)-1); + + timed_ctrl_reg_store(ID, _HRT_TIMED_CONTROLLER_CMD_REG_IDX, mask); + timed_ctrl_reg_store(ID, _HRT_TIMED_CONTROLLER_CMD_REG_IDX, condition); + timed_ctrl_reg_store(ID, _HRT_TIMED_CONTROLLER_CMD_REG_IDX, counter); + timed_ctrl_reg_store(ID, _HRT_TIMED_CONTROLLER_CMD_REG_IDX, (hrt_data)addr); + timed_ctrl_reg_store(ID, _HRT_TIMED_CONTROLLER_CMD_REG_IDX, value); +} + +/* pqiao TODO: make sure the following commands get + correct BASE address both for csim and android */ + +void timed_ctrl_snd_sp_commnd( + const timed_ctrl_ID_t ID, + hrt_data mask, + hrt_data condition, + hrt_data counter, + const sp_ID_t SP_ID, + hrt_address offset, + hrt_data value) +{ + OP___assert(SP_ID < N_SP_ID); + OP___assert(SP_DMEM_BASE[SP_ID] != (hrt_address)-1); + + timed_ctrl_snd_commnd(ID, mask, condition, counter, + SP_DMEM_BASE[SP_ID]+offset, value); +} + +void timed_ctrl_snd_gpio_commnd( + const timed_ctrl_ID_t ID, + hrt_data mask, + hrt_data condition, + hrt_data counter, + const gpio_ID_t GPIO_ID, + hrt_address offset, + hrt_data value) +{ + OP___assert(GPIO_ID < N_GPIO_ID); + OP___assert(GPIO_BASE[GPIO_ID] != (hrt_address)-1); + + timed_ctrl_snd_commnd(ID, mask, condition, counter, + GPIO_BASE[GPIO_ID]+offset, value); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/timed_ctrl_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/timed_ctrl_local.h new file mode 100644 index 0000000000000000000000000000000000000000..e570813af28dc6d9c6ba4f22619eee7f40257ef3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/timed_ctrl_local.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TIMED_CTRL_LOCAL_H_INCLUDED__ +#define __TIMED_CTRL_LOCAL_H_INCLUDED__ + +#include "timed_ctrl_global.h" + +#endif /* __TIMED_CTRL_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/timed_ctrl_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/timed_ctrl_private.h new file mode 100644 index 0000000000000000000000000000000000000000..fb0fdbb884352c08c6172f8f9e6c51badf9ec829 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/timed_ctrl_private.h @@ -0,0 +1,34 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TIMED_CTRL_PRIVATE_H_INCLUDED__ +#define __TIMED_CTRL_PRIVATE_H_INCLUDED__ + +#include "timed_ctrl_public.h" + +#include "device_access.h" + +#include "assert_support.h" + +STORAGE_CLASS_TIMED_CTRL_C void timed_ctrl_reg_store( + const timed_ctrl_ID_t ID, + const unsigned int reg, + const hrt_data value) +{ +OP___assert(ID < N_TIMED_CTRL_ID); +OP___assert(TIMED_CTRL_BASE[ID] != (hrt_address)-1); + ia_css_device_store_uint32(TIMED_CTRL_BASE[ID] + reg*sizeof(hrt_data), value); +} + +#endif /* __GP_DEVICE_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/vamem_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/vamem_local.h new file mode 100644 index 0000000000000000000000000000000000000000..c4e99afe0d29519bc13b5eae8780ddde5eb3c20a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/vamem_local.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VAMEM_LOCAL_H_INCLUDED__ +#define __VAMEM_LOCAL_H_INCLUDED__ + +#include "vamem_global.h" + +#endif /* __VAMEM_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/vamem_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/vamem_private.h new file mode 100644 index 0000000000000000000000000000000000000000..5e05258673d55d1d1f0a164f353ec7edba0b8ff1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/vamem_private.h @@ -0,0 +1,37 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VAMEM_PRIVATE_H_INCLUDED__ +#define __VAMEM_PRIVATE_H_INCLUDED__ + +#include "vamem_public.h" + +#include + +#include "assert_support.h" + + +STORAGE_CLASS_ISP_C void isp_vamem_store( + const vamem_ID_t ID, + vamem_data_t *addr, + const vamem_data_t *data, + const size_t size) /* in vamem_data_t */ +{ + assert(ID < N_VAMEM_ID); + assert(ISP_VAMEM_BASE[ID] != (hrt_address)-1); + hrt_master_port_store(ISP_VAMEM_BASE[ID] + (unsigned)addr, data, size * sizeof(vamem_data_t)); +} + + +#endif /* __VAMEM_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/vmem.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/vmem.c new file mode 100644 index 0000000000000000000000000000000000000000..b30cceba06819503df236b1dc9b14c0c7d5b4908 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/vmem.c @@ -0,0 +1,279 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010 - 2016, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "isp.h" +#include "vmem.h" +#include "vmem_local.h" + +#if !defined(HRT_MEMORY_ACCESS) +#include "ia_css_device_access.h" +#endif +#include "assert_support.h" +#include "platform_support.h" /* hrt_sleep() */ + +typedef unsigned long long hive_uedge; +typedef hive_uedge *hive_wide; + +/* Copied from SDK: sim_semantics.c */ + +/* subword bits move like this: MSB[____xxxx____]LSB -> MSB[00000000xxxx]LSB */ +#define SUBWORD(w, start, end) (((w) & (((1ULL << ((end)-1))-1) << 1 | 1)) >> (start)) + +/* inverse subword bits move like this: MSB[xxxx____xxxx]LSB -> MSB[xxxx0000xxxx]LSB */ +#define INV_SUBWORD(w, start, end) ((w) & (~(((1ULL << ((end)-1))-1) << 1 | 1) | ((1ULL << (start))-1)) ) + +#define uedge_bits (8*sizeof(hive_uedge)) +#define move_lower_bits(target, target_bit, src, src_bit) move_subword(target, target_bit, src, 0, src_bit) +#define move_upper_bits(target, target_bit, src, src_bit) move_subword(target, target_bit, src, src_bit, uedge_bits) +#define move_word(target, target_bit, src) move_subword(target, target_bit, src, 0, uedge_bits) + +static void +move_subword ( + hive_uedge *target, + unsigned target_bit, + hive_uedge src, + unsigned src_start, + unsigned src_end) +{ + unsigned int start_elem = target_bit / uedge_bits; + unsigned int start_bit = target_bit % uedge_bits; + unsigned subword_width = src_end - src_start; + + hive_uedge src_subword = SUBWORD(src, src_start, src_end); + + if (subword_width + start_bit > uedge_bits) { /* overlap */ + hive_uedge old_val1; + hive_uedge old_val0 = INV_SUBWORD(target[start_elem], start_bit, uedge_bits); + target[start_elem] = old_val0 | (src_subword << start_bit); + old_val1 = INV_SUBWORD(target[start_elem+1], 0, subword_width + start_bit - uedge_bits); + target[start_elem+1] = old_val1 | (src_subword >> ( uedge_bits - start_bit)); + } else { + hive_uedge old_val = INV_SUBWORD(target[start_elem], start_bit, start_bit + subword_width); + target[start_elem] = old_val | (src_subword << start_bit); + } +} + +static void +hive_sim_wide_unpack( + hive_wide vector, + hive_wide elem, + hive_uint elem_bits, + hive_uint index) +{ + /* pointers into wide_type: */ + unsigned int start_elem = (elem_bits * index) / uedge_bits; + unsigned int start_bit = (elem_bits * index) % uedge_bits; + unsigned int end_elem = (elem_bits * (index + 1) - 1) / uedge_bits; + unsigned int end_bit = ((elem_bits * (index + 1) - 1) % uedge_bits) + 1; + + if (elem_bits == uedge_bits) { + /* easy case for speedup: */ + elem[0] = vector[index]; + } else if (start_elem == end_elem) { + /* only one (<=64 bits) element needs to be (partly) copied: */ + move_subword(elem, 0, vector[start_elem], start_bit, end_bit); + } else { + /* general case: handles edge spanning cases (includes >64bit elements) */ + unsigned int bits_written = 0; + unsigned int i; + move_upper_bits(elem, bits_written, vector[start_elem], start_bit); + bits_written += (64 - start_bit); + for(i = start_elem+1; i < end_elem; i++) { + move_word(elem, bits_written, vector[i]); + bits_written += uedge_bits; + } + move_lower_bits(elem, bits_written , vector[end_elem], end_bit); + } +} + +static void +hive_sim_wide_pack( + hive_wide vector, + hive_wide elem, + hive_uint elem_bits, + hive_uint index) +{ + /* pointers into wide_type: */ + unsigned int start_elem = (elem_bits * index) / uedge_bits; + + /* easy case for speedup: */ + if (elem_bits == uedge_bits) { + vector[start_elem] = elem[0]; + } else if (elem_bits > uedge_bits) { + unsigned bits_to_write = elem_bits; + unsigned start_bit = elem_bits * index; + unsigned i = 0; + for(; bits_to_write > uedge_bits; bits_to_write -= uedge_bits, i++, start_bit += uedge_bits) { + move_word(vector, start_bit, elem[i]); + } + move_lower_bits(vector, start_bit, elem[i], bits_to_write); + } else { + /* only one element needs to be (partly) copied: */ + move_lower_bits(vector, elem_bits * index, elem[0], elem_bits); + } +} + +static void load_vector ( + const isp_ID_t ID, + t_vmem_elem *to, + const t_vmem_elem *from) +{ + unsigned i; + hive_uedge *data; +#ifdef C_RUN + data = (hive_uedge *)from; + (void)ID; +#else + unsigned size = sizeof(short)*ISP_NWAY; + VMEM_ARRAY(v, 2*ISP_NWAY); /* Need 2 vectors to work around vmem hss bug */ + assert(ISP_BAMEM_BASE[ID] != (hrt_address)-1); +#if !defined(HRT_MEMORY_ACCESS) + ia_css_device_load(ISP_BAMEM_BASE[ID] + (unsigned long)from, &v[0][0], size); +#else + hrt_master_port_load(ISP_BAMEM_BASE[ID] + (unsigned long)from, &v[0][0], size); +#endif + data = (hive_uedge *)v; +#endif + for (i = 0; i < ISP_NWAY; i++) { + hive_uedge elem = 0; + hive_sim_wide_unpack(data, &elem, ISP_VEC_ELEMBITS, i); + to[i] = elem; + } + hrt_sleep(); /* Spend at least 1 cycles per vector */ +} + +static void store_vector ( + const isp_ID_t ID, + t_vmem_elem *to, + const t_vmem_elem *from) +{ + unsigned i; +#ifdef C_RUN + hive_uedge *data = (hive_uedge *)to; + (void)ID; + for (i = 0; i < ISP_NWAY; i++) { + hive_sim_wide_pack(data, (hive_wide)&from[i], ISP_VEC_ELEMBITS, i); + } +#else + unsigned size = sizeof(short)*ISP_NWAY; + VMEM_ARRAY(v, 2*ISP_NWAY); /* Need 2 vectors to work around vmem hss bug */ + //load_vector (&v[1][0], &to[ISP_NWAY]); /* Fetch the next vector, since it will be overwritten. */ + hive_uedge *data = (hive_uedge *)v; + for (i = 0; i < ISP_NWAY; i++) { + hive_sim_wide_pack(data, (hive_wide)&from[i], ISP_VEC_ELEMBITS, i); + } + assert(ISP_BAMEM_BASE[ID] != (hrt_address)-1); +#if !defined(HRT_MEMORY_ACCESS) + ia_css_device_store(ISP_BAMEM_BASE[ID] + (unsigned long)to, &v, size); +#else + //hrt_mem_store (ISP, VMEM, (unsigned)to, &v, siz); /* This will overwrite the next vector as well */ + hrt_master_port_store(ISP_BAMEM_BASE[ID] + (unsigned long)to, &v, size); +#endif + hrt_sleep(); /* Spend at least 1 cycles per vector */ +#endif +} + +void isp_vmem_load( + const isp_ID_t ID, + const t_vmem_elem *from, + t_vmem_elem *to, + unsigned elems) /* In t_vmem_elem */ +{ + unsigned c; + const t_vmem_elem *vp = from; + assert(ID < N_ISP_ID); +#ifndef C_RUN + assert((unsigned long)from % ISP_VEC_ALIGN == 0); +#endif + assert(elems % ISP_NWAY == 0); + for (c = 0; c < elems; c += ISP_NWAY) { + load_vector(ID, &to[c], vp); + vp = (t_vmem_elem *)((char*)vp + ISP_VEC_ALIGN); + } +} + +void isp_vmem_store( + const isp_ID_t ID, + t_vmem_elem *to, + const t_vmem_elem *from, + unsigned elems) /* In t_vmem_elem */ +{ + unsigned c; + t_vmem_elem *vp = to; + assert(ID < N_ISP_ID); +#ifndef C_RUN + assert((unsigned long)to % ISP_VEC_ALIGN == 0); +#endif + assert(elems % ISP_NWAY == 0); + for (c = 0; c < elems; c += ISP_NWAY) { + store_vector (ID, vp, &from[c]); + vp = (t_vmem_elem *)((char*)vp + ISP_VEC_ALIGN); + } +} + +void isp_vmem_2d_load ( + const isp_ID_t ID, + const t_vmem_elem *from, + t_vmem_elem *to, + unsigned height, + unsigned width, + unsigned stride_to, /* In t_vmem_elem */ + unsigned stride_from /* In t_vmem_elem */) +{ + unsigned h; + + assert(ID < N_ISP_ID); +#ifndef C_RUN + assert((unsigned long)from % ISP_VEC_ALIGN == 0); +#endif + assert(width % ISP_NWAY == 0); + assert(stride_from % ISP_NWAY == 0); + for (h = 0; h < height; h++) { + unsigned c; + const t_vmem_elem *vp = from; + for (c = 0; c < width; c += ISP_NWAY) { + load_vector(ID, &to[stride_to*h + c], vp); + vp = (t_vmem_elem *)((char*)vp + ISP_VEC_ALIGN); + } + from = (const t_vmem_elem *)((const char *)from + stride_from/ISP_NWAY*ISP_VEC_ALIGN); + } +} + +void isp_vmem_2d_store ( + const isp_ID_t ID, + t_vmem_elem *to, + const t_vmem_elem *from, + unsigned height, + unsigned width, + unsigned stride_to, /* In t_vmem_elem */ + unsigned stride_from /* In t_vmem_elem */) +{ + unsigned h; + + assert(ID < N_ISP_ID); +#ifndef C_RUN + assert((unsigned long)to % ISP_VEC_ALIGN == 0); +#endif + assert(width % ISP_NWAY == 0); + assert(stride_to % ISP_NWAY == 0); + for (h = 0; h < height; h++) { + unsigned c; + t_vmem_elem *vp = to; + for (c = 0; c < width; c += ISP_NWAY) { + store_vector (ID, vp, &from[stride_from*h + c]); + vp = (t_vmem_elem *)((char*)vp + ISP_VEC_ALIGN); + } + to = (t_vmem_elem *)((char *)to + stride_to/ISP_NWAY*ISP_VEC_ALIGN); + } +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/vmem_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/vmem_local.h new file mode 100644 index 0000000000000000000000000000000000000000..de85644b885e14f57c85a620381406de0e63c6c9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/vmem_local.h @@ -0,0 +1,55 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VMEM_LOCAL_H_INCLUDED__ +#define __VMEM_LOCAL_H_INCLUDED__ + +#include "type_support.h" +#include "vmem_global.h" + +typedef uint16_t t_vmem_elem; + +#define VMEM_ARRAY(x,s) t_vmem_elem x[s/ISP_NWAY][ISP_NWAY] + +void isp_vmem_load( + const isp_ID_t ID, + const t_vmem_elem *from, + t_vmem_elem *to, + unsigned elems); /* In t_vmem_elem */ + +void isp_vmem_store( + const isp_ID_t ID, + t_vmem_elem *to, + const t_vmem_elem *from, + unsigned elems); /* In t_vmem_elem */ + +void isp_vmem_2d_load ( + const isp_ID_t ID, + const t_vmem_elem *from, + t_vmem_elem *to, + unsigned height, + unsigned width, + unsigned stride_to, /* In t_vmem_elem */ + unsigned stride_from /* In t_vmem_elem */); + +void isp_vmem_2d_store ( + const isp_ID_t ID, + t_vmem_elem *to, + const t_vmem_elem *from, + unsigned height, + unsigned width, + unsigned stride_to, /* In t_vmem_elem */ + unsigned stride_from /* In t_vmem_elem */); + +#endif /* __VMEM_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/vmem_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/vmem_private.h new file mode 100644 index 0000000000000000000000000000000000000000..f48d1281b5a77feb5cda42595abee7af2473f5a6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/host/vmem_private.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2010-2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VMEM_PRIVATE_H_INCLUDED__ +#define __VMEM_PRIVATE_H_INCLUDED__ + +#include "vmem_public.h" + +#endif /* __VMEM_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/input_formatter_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/input_formatter_global.h new file mode 100644 index 0000000000000000000000000000000000000000..5654d911db652f48fa7ec7d7197ff9fcd2435b7f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/input_formatter_global.h @@ -0,0 +1,130 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_FORMATTER_GLOBAL_H_INCLUDED__ +#define __INPUT_FORMATTER_GLOBAL_H_INCLUDED__ + +#define IS_INPUT_FORMATTER_VERSION2 +#define IS_INPUT_SWITCH_VERSION2 + +#include +#include +#include "if_defs.h" +#include "str2mem_defs.h" +#include "input_switch_2400_defs.h" + +#define _HIVE_INPUT_SWITCH_GET_FSYNC_REG_LSB(ch_id) ((ch_id) * 3) + +#define HIVE_SWITCH_N_CHANNELS 4 +#define HIVE_SWITCH_N_FORMATTYPES 32 +#define HIVE_SWITCH_N_SWITCH_CODE 4 +#define HIVE_SWITCH_M_CHANNELS 0x00000003 +#define HIVE_SWITCH_M_FORMATTYPES 0x0000001f +#define HIVE_SWITCH_M_SWITCH_CODE 0x00000003 +#define HIVE_SWITCH_M_FSYNC 0x00000007 + +#define HIVE_SWITCH_ENCODE_FSYNC(x) \ + (1U<<(((x)-1)&HIVE_SWITCH_M_CHANNELS)) + +#define _HIVE_INPUT_SWITCH_GET_LUT_FIELD(reg, bit_index) \ + (((reg) >> (bit_index)) & HIVE_SWITCH_M_SWITCH_CODE) +#define _HIVE_INPUT_SWITCH_SET_LUT_FIELD(reg, bit_index, val) \ + (((reg) & ~(HIVE_SWITCH_M_SWITCH_CODE<<(bit_index))) | (((hrt_data)(val)&HIVE_SWITCH_M_SWITCH_CODE)<<(bit_index))) +#define _HIVE_INPUT_SWITCH_GET_FSYNC_FIELD(reg, bit_index) \ + (((reg) >> (bit_index)) & HIVE_SWITCH_M_FSYNC) +#define _HIVE_INPUT_SWITCH_SET_FSYNC_FIELD(reg, bit_index, val) \ + (((reg) & ~(HIVE_SWITCH_M_FSYNC<<(bit_index))) | (((hrt_data)(val)&HIVE_SWITCH_M_FSYNC)<<(bit_index))) + +typedef struct input_formatter_cfg_s input_formatter_cfg_t; + +/* Hardware registers */ +/*#define HIVE_IF_RESET_ADDRESS 0x000*/ /* deprecated */ +#define HIVE_IF_START_LINE_ADDRESS 0x004 +#define HIVE_IF_START_COLUMN_ADDRESS 0x008 +#define HIVE_IF_CROPPED_HEIGHT_ADDRESS 0x00C +#define HIVE_IF_CROPPED_WIDTH_ADDRESS 0x010 +#define HIVE_IF_VERTICAL_DECIMATION_ADDRESS 0x014 +#define HIVE_IF_HORIZONTAL_DECIMATION_ADDRESS 0x018 +#define HIVE_IF_H_DEINTERLEAVING_ADDRESS 0x01C +#define HIVE_IF_LEFTPADDING_WIDTH_ADDRESS 0x020 +#define HIVE_IF_END_OF_LINE_OFFSET_ADDRESS 0x024 +#define HIVE_IF_VMEM_START_ADDRESS_ADDRESS 0x028 +#define HIVE_IF_VMEM_END_ADDRESS_ADDRESS 0x02C +#define HIVE_IF_VMEM_INCREMENT_ADDRESS 0x030 +#define HIVE_IF_YUV_420_FORMAT_ADDRESS 0x034 +#define HIVE_IF_VSYNCK_ACTIVE_LOW_ADDRESS 0x038 +#define HIVE_IF_HSYNCK_ACTIVE_LOW_ADDRESS 0x03C +#define HIVE_IF_ALLOW_FIFO_OVERFLOW_ADDRESS 0x040 +#define HIVE_IF_BLOCK_FIFO_NO_REQ_ADDRESS 0x044 +#define HIVE_IF_V_DEINTERLEAVING_ADDRESS 0x048 +#define HIVE_IF_FSM_CROP_PIXEL_COUNTER 0x110 +#define HIVE_IF_FSM_CROP_LINE_COUNTER 0x10C +#define HIVE_IF_FSM_CROP_STATUS 0x108 + +/* Registers only for simulation */ +#define HIVE_IF_CRUN_MODE_ADDRESS 0x04C +#define HIVE_IF_DUMP_OUTPUT_ADDRESS 0x050 + +/* Follow the DMA syntax, "cmd" last */ +#define IF_PACK(val, cmd) ((val & 0x0fff) | (cmd /*& 0xf000*/)) + +#define HIVE_STR2MEM_SOFT_RESET_REG_ADDRESS (_STR2MEM_SOFT_RESET_REG_ID * _STR2MEM_REG_ALIGN) +#define HIVE_STR2MEM_INPUT_ENDIANNESS_REG_ADDRESS (_STR2MEM_INPUT_ENDIANNESS_REG_ID * _STR2MEM_REG_ALIGN) +#define HIVE_STR2MEM_OUTPUT_ENDIANNESS_REG_ADDRESS (_STR2MEM_OUTPUT_ENDIANNESS_REG_ID * _STR2MEM_REG_ALIGN) +#define HIVE_STR2MEM_BIT_SWAPPING_REG_ADDRESS (_STR2MEM_BIT_SWAPPING_REG_ID * _STR2MEM_REG_ALIGN) +#define HIVE_STR2MEM_BLOCK_SYNC_LEVEL_REG_ADDRESS (_STR2MEM_BLOCK_SYNC_LEVEL_REG_ID * _STR2MEM_REG_ALIGN) +#define HIVE_STR2MEM_PACKET_SYNC_LEVEL_REG_ADDRESS (_STR2MEM_PACKET_SYNC_LEVEL_REG_ID * _STR2MEM_REG_ALIGN) +#define HIVE_STR2MEM_READ_POST_WRITE_SYNC_ENABLE_REG_ADDRESS (_STR2MEM_READ_POST_WRITE_SYNC_ENABLE_REG_ID * _STR2MEM_REG_ALIGN) +#define HIVE_STR2MEM_DUAL_BYTE_INPUTS_ENABLED_REG_ADDRESS (_STR2MEM_DUAL_BYTE_INPUTS_ENABLED_REG_ID * _STR2MEM_REG_ALIGN) +#define HIVE_STR2MEM_EN_STAT_UPDATE_ADDRESS (_STR2MEM_EN_STAT_UPDATE_ID * _STR2MEM_REG_ALIGN) + +/* + * This data structure is shared between host and SP + */ +struct input_formatter_cfg_s { + uint32_t start_line; + uint32_t start_column; + uint32_t left_padding; + uint32_t cropped_height; + uint32_t cropped_width; + uint32_t deinterleaving; + uint32_t buf_vecs; + uint32_t buf_start_index; + uint32_t buf_increment; + uint32_t buf_eol_offset; + uint32_t is_yuv420_format; + uint32_t block_no_reqs; +}; + +#define DEFAULT_IF_CONFIG \ +{ \ + 0, /* start_line */\ + 0, /* start_column */\ + 0, /* left_padding */\ + 0, /* cropped_height */\ + 0, /* cropped_width */\ + 0, /* deinterleaving */\ + 0, /*.buf_vecs */\ + 0, /* buf_start_index */\ + 0, /* buf_increment */\ + 0, /* buf_eol_offset */\ + false, /* is_yuv420_format */\ + false /* block_no_reqs */\ +} + +extern const hrt_address HIVE_IF_SRST_ADDRESS[N_INPUT_FORMATTER_ID]; +extern const hrt_data HIVE_IF_SRST_MASK[N_INPUT_FORMATTER_ID]; +extern const uint8_t HIVE_IF_SWITCH_CODE[N_INPUT_FORMATTER_ID]; + +#endif /* __INPUT_FORMATTER_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/input_system_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/input_system_global.h new file mode 100644 index 0000000000000000000000000000000000000000..9ba36525e8d32ec76f9891e6ef225d91335b0291 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/input_system_global.h @@ -0,0 +1,155 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_SYSTEM_GLOBAL_H_INCLUDED__ +#define __INPUT_SYSTEM_GLOBAL_H_INCLUDED__ + +#define IS_INPUT_SYSTEM_VERSION_2 + +#include + +//CSI reveiver has 3 ports. +#define N_CSI_PORTS (3) +//AM: Use previous define for this. + +//MIPI allows upto 4 channels. +#define N_CHANNELS (4) +// 12KB = 256bit x 384 words +#define IB_CAPACITY_IN_WORDS (384) + +typedef enum { + MIPI_0LANE_CFG = 0, + MIPI_1LANE_CFG = 1, + MIPI_2LANE_CFG = 2, + MIPI_3LANE_CFG = 3, + MIPI_4LANE_CFG = 4 +} mipi_lane_cfg_t; + +typedef enum { + INPUT_SYSTEM_SOURCE_SENSOR = 0, + INPUT_SYSTEM_SOURCE_FIFO, + INPUT_SYSTEM_SOURCE_TPG, + INPUT_SYSTEM_SOURCE_PRBS, + INPUT_SYSTEM_SOURCE_MEMORY, + N_INPUT_SYSTEM_SOURCE +} input_system_source_t; + +/* internal routing configuration */ +typedef enum { + INPUT_SYSTEM_DISCARD_ALL = 0, + INPUT_SYSTEM_CSI_BACKEND = 1, + INPUT_SYSTEM_INPUT_BUFFER = 2, + INPUT_SYSTEM_MULTICAST = 3, + N_INPUT_SYSTEM_CONNECTION +} input_system_connection_t; + +typedef enum { + INPUT_SYSTEM_MIPI_PORT0, + INPUT_SYSTEM_MIPI_PORT1, + INPUT_SYSTEM_MIPI_PORT2, + INPUT_SYSTEM_ACQUISITION_UNIT, + N_INPUT_SYSTEM_MULTIPLEX +} input_system_multiplex_t; + +typedef enum { + INPUT_SYSTEM_SINK_MEMORY = 0, + INPUT_SYSTEM_SINK_ISP, + INPUT_SYSTEM_SINK_SP, + N_INPUT_SYSTEM_SINK +} input_system_sink_t; + +typedef enum { + INPUT_SYSTEM_FIFO_CAPTURE = 0, + INPUT_SYSTEM_FIFO_CAPTURE_WITH_COUNTING, + INPUT_SYSTEM_SRAM_BUFFERING, + INPUT_SYSTEM_XMEM_BUFFERING, + INPUT_SYSTEM_XMEM_CAPTURE, + INPUT_SYSTEM_XMEM_ACQUIRE, + N_INPUT_SYSTEM_BUFFERING_MODE +} buffering_mode_t; + +typedef struct input_system_cfg_s input_system_cfg_t; +typedef struct sync_generator_cfg_s sync_generator_cfg_t; +typedef struct tpg_cfg_s tpg_cfg_t; +typedef struct prbs_cfg_s prbs_cfg_t; + +/* MW: uint16_t should be sufficient */ +struct input_system_cfg_s { + uint32_t no_side_band; + uint32_t fmt_type; + uint32_t ch_id; + uint32_t input_mode; +}; + +struct sync_generator_cfg_s { + uint32_t width; + uint32_t height; + uint32_t hblank_cycles; + uint32_t vblank_cycles; +}; + +/* MW: tpg & prbs are exclusive */ +struct tpg_cfg_s { + uint32_t x_mask; + uint32_t y_mask; + uint32_t x_delta; + uint32_t y_delta; + uint32_t xy_mask; + sync_generator_cfg_t sync_gen_cfg; +}; + +struct prbs_cfg_s { + uint32_t seed; + sync_generator_cfg_t sync_gen_cfg; +}; + +struct gpfifo_cfg_s { +// TBD. + sync_generator_cfg_t sync_gen_cfg; +}; + +typedef struct gpfifo_cfg_s gpfifo_cfg_t; + +//ALX:Commented out to pass the compilation. +//typedef struct input_system_cfg_s input_system_cfg_t; + +struct ib_buffer_s { + uint32_t mem_reg_size; + uint32_t nof_mem_regs; + uint32_t mem_reg_addr; +}; + +typedef struct ib_buffer_s ib_buffer_t; + +struct csi_cfg_s { + uint32_t csi_port; + buffering_mode_t buffering_mode; + ib_buffer_t csi_buffer; + ib_buffer_t acquisition_buffer; + uint32_t nof_xmem_buffers; +}; + +typedef struct csi_cfg_s csi_cfg_t; + +typedef enum { + INPUT_SYSTEM_CFG_FLAG_RESET = 0, + INPUT_SYSTEM_CFG_FLAG_SET = 1U << 0, + INPUT_SYSTEM_CFG_FLAG_BLOCKED = 1U << 1, + INPUT_SYSTEM_CFG_FLAG_REQUIRED = 1U << 2, + INPUT_SYSTEM_CFG_FLAG_CONFLICT = 1U << 3 // To mark a conflicting configuration. +} input_system_cfg_flag_t; + +typedef uint32_t input_system_config_flags_t; + +#endif /* __INPUT_SYSTEM_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/irq_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/irq_global.h new file mode 100644 index 0000000000000000000000000000000000000000..64554d80dc0b6b31da59d4db9cc34654781d2ad3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/irq_global.h @@ -0,0 +1,45 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IRQ_GLOBAL_H_INCLUDED__ +#define __IRQ_GLOBAL_H_INCLUDED__ + +#include + +#define IS_IRQ_VERSION_2 +#define IS_IRQ_MAP_VERSION_2 + +/* We cannot include the (hrt host ID) file defining the "CSS_RECEIVER" property without side effects */ +#ifndef HAS_NO_RX +#if defined(IS_ISP_2400_MAMOIADA_SYSTEM) +/*#define CSS_RECEIVER testbench_isp_inp_sys_csi_receiver*/ +#include "hive_isp_css_irq_types_hrt.h" /* enum hrt_isp_css_irq */ +#elif defined(IS_ISP_2401_MAMOIADA_SYSTEM) +/*#define CSS_RECEIVER testbench_isp_is_2400_inp_sys_csi_receiver*/ +#include "hive_isp_css_2401_irq_types_hrt.h" /* enum hrt_isp_css_irq */ +#else +#error "irq_global.h: 2400_SYSTEM must be one of {2400, 2401 }" +#endif +#endif + +/* The IRQ is not mapped uniformly on its related interfaces */ +#define IRQ_SW_CHANNEL_OFFSET hrt_isp_css_irq_sw_pin_0 + +typedef enum { + IRQ_SW_CHANNEL0_ID = hrt_isp_css_irq_sw_pin_0 - IRQ_SW_CHANNEL_OFFSET, + IRQ_SW_CHANNEL1_ID = hrt_isp_css_irq_sw_pin_1 - IRQ_SW_CHANNEL_OFFSET, + N_IRQ_SW_CHANNEL_ID +} irq_sw_channel_id_t; + +#endif /* __IRQ_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/isp_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/isp_global.h new file mode 100644 index 0000000000000000000000000000000000000000..14d574849a5b1b954cbd725944801a7c0b209502 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/isp_global.h @@ -0,0 +1,115 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISP_GLOBAL_H_INCLUDED__ +#define __ISP_GLOBAL_H_INCLUDED__ + +#include + +#if defined (HAS_ISP_2401_MAMOIADA) +#define IS_ISP_2401_MAMOIADA + +#include "isp2401_mamoiada_params.h" +#elif defined (HAS_ISP_2400_MAMOIADA) +#define IS_ISP_2400_MAMOIADA + +#include "isp2400_mamoiada_params.h" +#else +#error "isp_global_h: ISP_2400_MAMOIDA must be one of {2400, 2401 }" +#endif + +#define ISP_PMEM_WIDTH_LOG2 ISP_LOG2_PMEM_WIDTH +#define ISP_PMEM_SIZE ISP_PMEM_DEPTH + +#define ISP_NWAY_LOG2 6 +#define ISP_VEC_NELEMS_LOG2 ISP_NWAY_LOG2 + +#ifdef ISP2401 +#ifdef PIPE_GENERATION +#define PIPEMEM(x) MEM(x) +#define ISP_NWAY (1< + +#endif /* __MMU_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/resource_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/resource_global.h new file mode 100644 index 0000000000000000000000000000000000000000..01c915c033a95e88b8ec52b77890df742cd97894 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/resource_global.h @@ -0,0 +1,35 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __RESOURCE_GLOBAL_H_INCLUDED__ +#define __RESOURCE_GLOBAL_H_INCLUDED__ + +#define IS_RESOURCE_VERSION_1 + +typedef enum { + DMA_CHANNEL_RESOURCE_TYPE, + IRQ_CHANNEL_RESOURCE_TYPE, + MEM_SECTION_RESOURCE_TYPE, + N_RESOURCE_TYPE +} resource_type_ID_t; + +typedef enum { + PERMANENT_RESOURCE_RESERVATION, + PERSISTENT_RESOURCE_RESERVATION, + DEDICTATED_RESOURCE_RESERVATION, + SHARED_RESOURCE_RESERVATION, + N_RESOURCE_RESERVATION +} resource_reservation_t; + +#endif /* __RESOURCE_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/sp_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/sp_global.h new file mode 100644 index 0000000000000000000000000000000000000000..6ec4e590e3b4a9489599804f2bff0b7caf95af0f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/sp_global.h @@ -0,0 +1,93 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SP_GLOBAL_H_INCLUDED__ +#define __SP_GLOBAL_H_INCLUDED__ + +#include + +#if defined(HAS_SP_2401) +#define IS_SP_2401 +/* 2401 uses 2400 */ +#include +#elif defined(HAS_SP_2400) +#define IS_SP_2400 + +#include +#else +#error "sp_global.h: SP_2400 must be one of {2400, 2401 }" +#endif + +#define SP_PMEM_WIDTH_LOG2 SP_PMEM_LOG_WIDTH_BITS +#define SP_PMEM_SIZE SP_PMEM_DEPTH + +#define SP_DMEM_SIZE 0x4000 + +/* SP Registers */ +#define SP_PC_REG 0x09 +#define SP_SC_REG 0x00 +#define SP_START_ADDR_REG 0x01 +#define SP_ICACHE_ADDR_REG 0x05 +#define SP_IRQ_READY_REG 0x00 +#define SP_IRQ_CLEAR_REG 0x00 +#define SP_ICACHE_INV_REG 0x00 +#define SP_CTRL_SINK_REG 0x0A + +/* SP Register bits */ +#define SP_RST_BIT 0x00 +#define SP_START_BIT 0x01 +#define SP_BREAK_BIT 0x02 +#define SP_RUN_BIT 0x03 +#define SP_BROKEN_BIT 0x04 +#define SP_IDLE_BIT 0x05 /* READY */ +#define SP_SLEEPING_BIT 0x06 +#define SP_STALLING_BIT 0x07 +#define SP_IRQ_CLEAR_BIT 0x08 +#define SP_IRQ_READY_BIT 0x0A +#define SP_IRQ_SLEEPING_BIT 0x0B + +#define SP_ICACHE_INV_BIT 0x0C +#define SP_IPREFETCH_EN_BIT 0x0D + +#define SP_FIFO0_SINK_BIT 0x00 +#define SP_FIFO1_SINK_BIT 0x01 +#define SP_FIFO2_SINK_BIT 0x02 +#define SP_FIFO3_SINK_BIT 0x03 +#define SP_FIFO4_SINK_BIT 0x04 +#define SP_FIFO5_SINK_BIT 0x05 +#define SP_FIFO6_SINK_BIT 0x06 +#define SP_FIFO7_SINK_BIT 0x07 +#define SP_FIFO8_SINK_BIT 0x08 +#define SP_FIFO9_SINK_BIT 0x09 +#define SP_FIFOA_SINK_BIT 0x0A +#define SP_DMEM_SINK_BIT 0x0B +#define SP_CTRL_MT_SINK_BIT 0x0C +#define SP_ICACHE_MT_SINK_BIT 0x0D + +#define SP_FIFO0_SINK_REG 0x0A +#define SP_FIFO1_SINK_REG 0x0A +#define SP_FIFO2_SINK_REG 0x0A +#define SP_FIFO3_SINK_REG 0x0A +#define SP_FIFO4_SINK_REG 0x0A +#define SP_FIFO5_SINK_REG 0x0A +#define SP_FIFO6_SINK_REG 0x0A +#define SP_FIFO7_SINK_REG 0x0A +#define SP_FIFO8_SINK_REG 0x0A +#define SP_FIFO9_SINK_REG 0x0A +#define SP_FIFOA_SINK_REG 0x0A +#define SP_DMEM_SINK_REG 0x0A +#define SP_CTRL_MT_SINK_REG 0x0A +#define SP_ICACHE_MT_SINK_REG 0x0A + +#endif /* __SP_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/system_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/system_global.h new file mode 100644 index 0000000000000000000000000000000000000000..d803efd7400ab3dce8fbbad7fe67320be19b469a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/system_global.h @@ -0,0 +1,348 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SYSTEM_GLOBAL_H_INCLUDED__ +#define __SYSTEM_GLOBAL_H_INCLUDED__ + +#include +#include + +/* + * The longest allowed (uninteruptible) bus transfer, does not + * take stalling into account + */ +#define HIVE_ISP_MAX_BURST_LENGTH 1024 + +/* + * Maximum allowed burst length in words for the ISP DMA + */ +#define ISP_DMA_MAX_BURST_LENGTH 128 + +/* + * Create a list of HAS and IS properties that defines the system + * + * The configuration assumes the following + * - The system is hetereogeneous; Multiple cells and devices classes + * - The cell and device instances are homogeneous, each device type + * belongs to the same class + * - Device instances supporting a subset of the class capabilities are + * allowed + * + * We could manage different device classes through the enumerated + * lists (C) or the use of classes (C++), but that is presently not + * fully supported + * + * N.B. the 3 input formatters are of 2 different classess + */ + +#define IS_ISP_2400_SYSTEM +/* + * Since this file is visible everywhere and the system definition + * macros are not, detect the separate definitions for {host, SP, ISP} + * + * The 2401 system has the nice property that it uses a vanilla 2400 SP + * so the SP will believe it is a 2400 system rather than 2401... + */ +//#if defined(SYSTEM_hive_isp_css_2401_system) || defined(__isp2401_mamoiada) || defined(__scalar_processor_2401) +#if defined(SYSTEM_hive_isp_css_2401_system) || defined(__isp2401_mamoiada) +#define IS_ISP_2401_MAMOIADA_SYSTEM +#define HAS_ISP_2401_MAMOIADA +#define HAS_SP_2400 +//#elif defined(SYSTEM_hive_isp_css_2400_system) || defined(__isp2400_mamoiada) || defined(__scalar_processor_2400) +#elif defined(SYSTEM_hive_isp_css_2400_system) || defined(__isp2400_mamoiada) +#define IS_ISP_2400_MAMOIADA_SYSTEM +#define HAS_ISP_2400_MAMOIADA +#define HAS_SP_2400 +#else +#error "system_global.h: 2400_SYSTEM must be one of {2400, 2401 }" +#endif + +#define USE_INPUT_SYSTEM_VERSION_2 + +#define HAS_MMU_VERSION_2 +#define HAS_DMA_VERSION_2 +#define HAS_GDC_VERSION_2 +#define HAS_VAMEM_VERSION_2 +#define HAS_HMEM_VERSION_1 +#define HAS_BAMEM_VERSION_2 +#define HAS_IRQ_VERSION_2 +#define HAS_IRQ_MAP_VERSION_2 +#define HAS_INPUT_FORMATTER_VERSION_2 +/* 2401: HAS_INPUT_SYSTEM_VERSION_2401 */ +#define HAS_INPUT_SYSTEM_VERSION_2 +#define HAS_BUFFERED_SENSOR +#define HAS_FIFO_MONITORS_VERSION_2 +/* #define HAS_GP_REGS_VERSION_2 */ +#define HAS_GP_DEVICE_VERSION_2 +#define HAS_GPIO_VERSION_1 +#define HAS_TIMED_CTRL_VERSION_1 +#define HAS_RX_VERSION_2 + +#define DMA_DDR_TO_VAMEM_WORKAROUND +#define DMA_DDR_TO_HMEM_WORKAROUND + +/* + * Semi global. "HRT" is accessible from SP, but the HRT types do not fully apply + */ +#define HRT_VADDRESS_WIDTH 32 +//#define HRT_ADDRESS_WIDTH 64 /* Surprise, this is a local property*/ +#define HRT_DATA_WIDTH 32 + +#define SIZEOF_HRT_REG (HRT_DATA_WIDTH>>3) +#define HIVE_ISP_CTRL_DATA_BYTES (HIVE_ISP_CTRL_DATA_WIDTH/8) + +/* The main bus connecting all devices */ +#define HRT_BUS_WIDTH HIVE_ISP_CTRL_DATA_WIDTH +#define HRT_BUS_BYTES HIVE_ISP_CTRL_DATA_BYTES + +/* per-frame parameter handling support */ +#define SH_CSS_ENABLE_PER_FRAME_PARAMS + +typedef uint32_t hrt_bus_align_t; + +/* + * Enumerate the devices, device access through the API is by ID, through the DLI by address + * The enumerator terminators are used to size the wiring arrays and as an exception value. + */ +typedef enum { + DDR0_ID = 0, + N_DDR_ID +} ddr_ID_t; + +typedef enum { + ISP0_ID = 0, + N_ISP_ID +} isp_ID_t; + +typedef enum { + SP0_ID = 0, + N_SP_ID +} sp_ID_t; + +#if defined (IS_ISP_2401_MAMOIADA_SYSTEM) +typedef enum { + MMU0_ID = 0, + MMU1_ID, + N_MMU_ID +} mmu_ID_t; +#elif defined (IS_ISP_2400_MAMOIADA_SYSTEM) +typedef enum { + MMU0_ID = 0, + MMU1_ID, + N_MMU_ID +} mmu_ID_t; +#else +#error "system_global.h: SYSTEM must be one of {2400, 2401}" +#endif + +typedef enum { + DMA0_ID = 0, + N_DMA_ID +} dma_ID_t; + +typedef enum { + GDC0_ID = 0, + GDC1_ID, + N_GDC_ID +} gdc_ID_t; + +#define N_GDC_ID_CPP 2 // this extra define is needed because we want to use it also in the preprocessor, and that doesn't work with enums. + +typedef enum { + VAMEM0_ID = 0, + VAMEM1_ID, + VAMEM2_ID, + N_VAMEM_ID +} vamem_ID_t; + +typedef enum { + BAMEM0_ID = 0, + N_BAMEM_ID +} bamem_ID_t; + +typedef enum { + HMEM0_ID = 0, + N_HMEM_ID +} hmem_ID_t; + +/* +typedef enum { + IRQ0_ID = 0, + N_IRQ_ID +} irq_ID_t; +*/ + +typedef enum { + IRQ0_ID = 0, // GP IRQ block + IRQ1_ID, // Input formatter + IRQ2_ID, // input system + IRQ3_ID, // input selector + N_IRQ_ID +} irq_ID_t; + +typedef enum { + FIFO_MONITOR0_ID = 0, + N_FIFO_MONITOR_ID +} fifo_monitor_ID_t; + +/* + * Deprecated: Since all gp_reg instances are different + * and put in the address maps of other devices we cannot + * enumerate them as that assumes the instrances are the + * same. + * + * We define a single GP_DEVICE containing all gp_regs + * w.r.t. a single base address + * +typedef enum { + GP_REGS0_ID = 0, + N_GP_REGS_ID +} gp_regs_ID_t; + */ +typedef enum { + GP_DEVICE0_ID = 0, + N_GP_DEVICE_ID +} gp_device_ID_t; + +typedef enum { + GP_TIMER0_ID = 0, + GP_TIMER1_ID, + GP_TIMER2_ID, + GP_TIMER3_ID, + GP_TIMER4_ID, + GP_TIMER5_ID, + GP_TIMER6_ID, + GP_TIMER7_ID, + N_GP_TIMER_ID +} gp_timer_ID_t; + +typedef enum { + GPIO0_ID = 0, + N_GPIO_ID +} gpio_ID_t; + +typedef enum { + TIMED_CTRL0_ID = 0, + N_TIMED_CTRL_ID +} timed_ctrl_ID_t; + +typedef enum { + INPUT_FORMATTER0_ID = 0, + INPUT_FORMATTER1_ID, + INPUT_FORMATTER2_ID, + INPUT_FORMATTER3_ID, + N_INPUT_FORMATTER_ID +} input_formatter_ID_t; + +/* The IF RST is outside the IF */ +#define INPUT_FORMATTER0_SRST_OFFSET 0x0824 +#define INPUT_FORMATTER1_SRST_OFFSET 0x0624 +#define INPUT_FORMATTER2_SRST_OFFSET 0x0424 +#define INPUT_FORMATTER3_SRST_OFFSET 0x0224 + +#define INPUT_FORMATTER0_SRST_MASK 0x0001 +#define INPUT_FORMATTER1_SRST_MASK 0x0002 +#define INPUT_FORMATTER2_SRST_MASK 0x0004 +#define INPUT_FORMATTER3_SRST_MASK 0x0008 + +typedef enum { + INPUT_SYSTEM0_ID = 0, + N_INPUT_SYSTEM_ID +} input_system_ID_t; + +typedef enum { + RX0_ID = 0, + N_RX_ID +} rx_ID_t; + +typedef enum { + MIPI_PORT0_ID = 0, + MIPI_PORT1_ID, + MIPI_PORT2_ID, + N_MIPI_PORT_ID +} mipi_port_ID_t; + +#define N_RX_CHANNEL_ID 4 + +/* Generic port enumeration with an internal port type ID */ +typedef enum { + CSI_PORT0_ID = 0, + CSI_PORT1_ID, + CSI_PORT2_ID, + TPG_PORT0_ID, + PRBS_PORT0_ID, + FIFO_PORT0_ID, + MEMORY_PORT0_ID, + N_INPUT_PORT_ID +} input_port_ID_t; + +typedef enum { + CAPTURE_UNIT0_ID = 0, + CAPTURE_UNIT1_ID, + CAPTURE_UNIT2_ID, + ACQUISITION_UNIT0_ID, + DMA_UNIT0_ID, + CTRL_UNIT0_ID, + GPREGS_UNIT0_ID, + FIFO_UNIT0_ID, + IRQ_UNIT0_ID, + N_SUB_SYSTEM_ID +} sub_system_ID_t; + +#define N_CAPTURE_UNIT_ID 3 +#define N_ACQUISITION_UNIT_ID 1 +#define N_CTRL_UNIT_ID 1 + +enum ia_css_isp_memories { + IA_CSS_ISP_PMEM0 = 0, + IA_CSS_ISP_DMEM0, + IA_CSS_ISP_VMEM0, + IA_CSS_ISP_VAMEM0, + IA_CSS_ISP_VAMEM1, + IA_CSS_ISP_VAMEM2, + IA_CSS_ISP_HMEM0, + IA_CSS_SP_DMEM0, + IA_CSS_DDR, + N_IA_CSS_MEMORIES +}; +#define IA_CSS_NUM_MEMORIES 9 +/* For driver compatability */ +#define N_IA_CSS_ISP_MEMORIES IA_CSS_NUM_MEMORIES +#define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES + +#if 0 +typedef enum { + dev_chn, /* device channels, external resource */ + ext_mem, /* external memories */ + int_mem, /* internal memories */ + int_chn /* internal channels, user defined */ +} resource_type_t; + +/* if this enum is extended with other memory resources, pls also extend the function resource_to_memptr() */ +typedef enum { + vied_nci_dev_chn_dma_ext0, + int_mem_vmem0, + int_mem_dmem0 +} resource_id_t; + +/* enum listing the different memories within a program group. + This enum is used in the mem_ptr_t type */ +typedef enum { + buf_mem_invalid = 0, + buf_mem_vmem_prog0, + buf_mem_dmem_prog0 +} buf_mem_t; + +#endif +#endif /* __SYSTEM_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/timed_ctrl_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/timed_ctrl_global.h new file mode 100644 index 0000000000000000000000000000000000000000..c3e8a01040924241a9eb2a893b3ec1121cdd4711 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/timed_ctrl_global.h @@ -0,0 +1,56 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TIMED_CTRL_GLOBAL_H_INCLUDED__ +#define __TIMED_CTRL_GLOBAL_H_INCLUDED__ + +#define IS_TIMED_CTRL_VERSION_1 + +#include + +/** + * Order of the input bits for the timed controller taken from + * ISP_CSS_2401 System Architecture Description valid for + * 2400, 2401. + * + * Check for other systems. + */ +#define HIVE_TIMED_CTRL_GPIO_PIN_0_BIT_ID 0 +#define HIVE_TIMED_CTRL_GPIO_PIN_1_BIT_ID 1 +#define HIVE_TIMED_CTRL_GPIO_PIN_2_BIT_ID 2 +#define HIVE_TIMED_CTRL_GPIO_PIN_3_BIT_ID 3 +#define HIVE_TIMED_CTRL_GPIO_PIN_4_BIT_ID 4 +#define HIVE_TIMED_CTRL_GPIO_PIN_5_BIT_ID 5 +#define HIVE_TIMED_CTRL_GPIO_PIN_6_BIT_ID 6 +#define HIVE_TIMED_CTRL_GPIO_PIN_7_BIT_ID 7 +#define HIVE_TIMED_CTRL_GPIO_PIN_8_BIT_ID 8 +#define HIVE_TIMED_CTRL_GPIO_PIN_9_BIT_ID 9 +#define HIVE_TIMED_CTRL_GPIO_PIN_10_BIT_ID 10 +#define HIVE_TIMED_CTRL_GPIO_PIN_11_BIT_ID 11 +#define HIVE_TIMED_CTRL_IRQ_SP_BIT_ID 12 +#define HIVE_TIMED_CTRL_IRQ_ISP_BIT_ID 13 +#define HIVE_TIMED_CTRL_IRQ_INPUT_SYSTEM_BIT_ID 14 +#define HIVE_TIMED_CTRL_IRQ_INPUT_SELECTOR_BIT_ID 15 +#define HIVE_TIMED_CTRL_IRQ_IF_BLOCK_BIT_ID 16 +#define HIVE_TIMED_CTRL_IRQ_GP_TIMER_0_BIT_ID 17 +#define HIVE_TIMED_CTRL_IRQ_GP_TIMER_1_BIT_ID 18 +#define HIVE_TIMED_CTRL_CSI_SOL_BIT_ID 19 +#define HIVE_TIMED_CTRL_CSI_EOL_BIT_ID 20 +#define HIVE_TIMED_CTRL_CSI_SOF_BIT_ID 21 +#define HIVE_TIMED_CTRL_CSI_EOF_BIT_ID 22 +#define HIVE_TIMED_CTRL_IRQ_IS_STREAMING_MONITOR_BIT_ID 23 + + + +#endif /* __TIMED_CTRL_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/vamem_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/vamem_global.h new file mode 100644 index 0000000000000000000000000000000000000000..58713c6583b96f10fa768bc52e4852d933b13fda --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_common/vamem_global.h @@ -0,0 +1,34 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VAMEM_GLOBAL_H_INCLUDED__ +#define __VAMEM_GLOBAL_H_INCLUDED__ + +#include + +#define IS_VAMEM_VERSION_2 + +/* (log) stepsize of linear interpolation */ +#define VAMEM_INTERP_STEP_LOG2 4 +#define VAMEM_INTERP_STEP (1< +#define assert(cnd) ASSERT(cnd) +#else +/* Windows usermode compilation */ +#include +#endif + +#elif defined(__HIVECC) + +/* enable assert for unsched, disable assert for sched and target */ +#if defined(HRT_UNSCHED) +#define assert(cnd) OP___csim_assert(cnd) +#else +#define assert(cnd) ((void)0) +#endif + +#elif defined(__KERNEL__) +#include + +/* TODO: it would be cleaner to use this: + * #define assert(cnd) BUG_ON(cnd) + * but that causes many compiler warnings (==errors) under Android + * because it seems that the BUG_ON() macro is not seen as a check by + * gcc like the BUG() macro is. */ +#define assert(cnd) \ + do { \ + if (!(cnd)) \ + BUG(); \ + } while (0) + +#elif defined(__FIST__) || defined(__GNUC__) + +/* enable assert for crun */ +#include "assert.h" + +#else /* default for unknown environments */ +#define assert(cnd) ((void)0) +#endif + +#endif /* NDEBUG */ + +#ifndef PIPE_GENERATION +/* Deprecated OP___assert, this is still used in ~1000 places + * in the code. This will be removed over time. + * The implemenation for the pipe generation tool is in see support.isp.h */ +#define OP___assert(cnd) assert(cnd) + +#ifdef C_RUN +#define compile_time_assert(cond) OP___assert(cond) +#else +STORAGE_CLASS_INLINE void compile_time_assert (unsigned cond) +{ + /* Call undefined function if cond is false */ + extern void _compile_time_assert (void); + if (!cond) _compile_time_assert(); +} +#endif +#endif /* PIPE_GENERATION */ + +#endif /* __ASSERT_SUPPORT_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/bamem.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/bamem.h new file mode 100644 index 0000000000000000000000000000000000000000..d71e08f27a42860087ba42e6d14d608a90cdc729 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/bamem.h @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __BAMEM_H_INCLUDED__ +#define __BAMEM_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the BAMEM device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "bamem_local.h" + +#ifndef __INLINE_BAMEM__ +#define STORAGE_CLASS_BAMEM_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_BAMEM_C +#include "bamem_public.h" +#else /* __INLINE_BAMEM__ */ +#define STORAGE_CLASS_BAMEM_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_BAMEM_C STORAGE_CLASS_INLINE +#include "bamem_private.h" +#endif /* __INLINE_BAMEM__ */ + +#endif /* __BAMEM_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/bbb_config.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/bbb_config.h new file mode 100644 index 0000000000000000000000000000000000000000..18bc5ef3d0bfa1b26359e7f0863e05f103af8ea8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/bbb_config.h @@ -0,0 +1,27 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __BBB_CONFIG_H_INCLUDED__ +#define __BBB_CONFIG_H_INCLUDED__ +/* This header contains BBB defines common to ISP and host */ + +#define BFA_MAX_KWAY (49) +#define BFA_RW_LUT_SIZE (7) + +#define SAD3x3_IN_SHIFT (2) /* input right shift value for SAD3x3 */ +#define SAD3x3_OUT_SHIFT (2) /* output right shift value for SAD3x3 */ + +/* XCU and BMA related defines shared between host and ISP + * also need to be moved here */ +#endif /* __BBB_CONFIG_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/bitop_support.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/bitop_support.h new file mode 100644 index 0000000000000000000000000000000000000000..1b271c3c6a254014d136b4c912fd5ceff4ed53fc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/bitop_support.h @@ -0,0 +1,25 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __BITOP_SUPPORT_H_INCLUDED__ +#define __BITOP_SUPPORT_H_INCLUDED__ + +#define bitop_setbit(a, b) ((a) |= (1UL << (b))) + +#define bitop_getbit(a, b) (((a) & (1UL << (b))) != 0) + +#define bitop_clearbit(a, b) ((a) &= ~(1UL << (b))) + +#endif /* __BITOP_SUPPORT_H_INCLUDED__ */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/cpu_mem_support.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/cpu_mem_support.h new file mode 100644 index 0000000000000000000000000000000000000000..6d014fafb713907d2246c30ebc65e3556cf20417 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/cpu_mem_support.h @@ -0,0 +1,59 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __CPU_MEM_SUPPORT_H_INCLUDED__ +#define __CPU_MEM_SUPPORT_H_INCLUDED__ + +#if defined (__KERNEL__) +#include /* memset */ +#else +#include /* memset */ +#endif + +#include "sh_css_internal.h" /* sh_css_malloc and sh_css_free */ + +static inline void* +ia_css_cpu_mem_alloc(unsigned int size) +{ + return sh_css_malloc(size); +} + +static inline void* +ia_css_cpu_mem_copy(void* dst, const void* src, unsigned int size) +{ + if(!src || !dst) + return NULL; + + return memcpy(dst, src, size); +} + +static inline void* +ia_css_cpu_mem_set_zero(void* dst, unsigned int size) +{ + if(!dst) + return NULL; + + return memset(dst, 0, size); +} + +static inline void +ia_css_cpu_mem_free(void* ptr) +{ + if(!ptr) + return; + + sh_css_free(ptr); +} + +#endif /* __CPU_MEM_SUPPORT_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/csi_rx.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/csi_rx.h new file mode 100644 index 0000000000000000000000000000000000000000..0398f5802f05aa6bf03d47be41edf881b2a7453a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/csi_rx.h @@ -0,0 +1,48 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __CSI_RX_H_INCLUDED__ +#define __CSI_RX_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the input system device(s). It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & + * inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "csi_rx_local.h" + +#ifndef __INLINE_CSI_RX__ +#define STORAGE_CLASS_CSI_RX_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_CSI_RX_C +#include "csi_rx_public.h" +#else /* __INLINE_CSI_RX__ */ +#define STORAGE_CLASS_CSI_RX_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_CSI_RX_C STORAGE_CLASS_INLINE +#include "csi_rx_private.h" +#endif /* __INLINE_CSI_RX__ */ + +#endif /* __CSI_RX_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/debug.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/debug.h new file mode 100644 index 0000000000000000000000000000000000000000..7d80117350332b70dec5a8a4a83de9151670f607 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/debug.h @@ -0,0 +1,48 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __DEBUG_H_INCLUDED__ +#define __DEBUG_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the DMA device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + * + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "debug_local.h" + +#ifndef __INLINE_DEBUG__ +#define STORAGE_CLASS_DEBUG_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_DEBUG_C +#include "debug_public.h" +#else /* __INLINE_DEBUG__ */ +#define STORAGE_CLASS_DEBUG_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_DEBUG_C STORAGE_CLASS_INLINE +#include "debug_private.h" +#endif /* __INLINE_DEBUG__ */ + +#endif /* __DEBUG_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/device_access/device_access.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/device_access/device_access.h new file mode 100644 index 0000000000000000000000000000000000000000..834e7c3e0814feaac851e9821f5573fea9d3d379 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/device_access/device_access.h @@ -0,0 +1,194 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef __DEVICE_ACCESS_H_INCLUDED__ +#define __DEVICE_ACCESS_H_INCLUDED__ + +/*! + * \brief + * Define the public interface for physical system + * access functions to SRAM and registers. Access + * types are limited to those defined in + * All accesses are aligned + * + * The address representation is private to the system + * and represented as/stored in "hrt_address". + * + * The system global address can differ by an offset; + * The device base address. This offset must be added + * by the implementation of the access function + * + * "store" is a transfer to the device + * "load" is a transfer from the device + */ + +#include + +/* + * User provided file that defines the system address types: + * - hrt_address a type that can hold the (sub)system address range + */ +#include "system_types.h" +/* + * We cannot assume that the global system address size is the size of + * a pointer because a (say) 64-bit host can be simulated in a 32-bit + * environment. Only if the host environment is modelled as on the target + * we could use a pointer. Even then, prototyping may need to be done + * before the target environment is available. AS we cannot wait for that + * we are stuck with integer addresses + */ + +/*typedef char *sys_address;*/ +typedef hrt_address sys_address; + +/*! Set the (sub)system base address + + \param base_addr[in] The offset on which the (sub)system is located + in the global address map + + \return none, + */ +extern void device_set_base_address( + const sys_address base_addr); + + +/*! Get the (sub)system base address + + \return base_address, + */ +extern sys_address device_get_base_address(void); + +/*! Read an 8-bit value from a device register or memory in the device + + \param addr[in] Local address + + \return device[addr] + */ +extern uint8_t ia_css_device_load_uint8( + const hrt_address addr); + +/*! Read a 16-bit value from a device register or memory in the device + + \param addr[in] Local address + + \return device[addr] + */ +extern uint16_t ia_css_device_load_uint16( + const hrt_address addr); + +/*! Read a 32-bit value from a device register or memory in the device + + \param addr[in] Local address + + \return device[addr] + */ +extern uint32_t ia_css_device_load_uint32( + const hrt_address addr); + +/*! Read a 64-bit value from a device register or memory in the device + + \param addr[in] Local address + + \return device[addr] + */ +extern uint64_t ia_css_device_load_uint64( + const hrt_address addr); + +/*! Write an 8-bit value to a device register or memory in the device + + \param addr[in] Local address + \param data[in] value + + \return none, device[addr] = value + */ +extern void ia_css_device_store_uint8( + const hrt_address addr, + const uint8_t data); + +/*! Write a 16-bit value to a device register or memory in the device + + \param addr[in] Local address + \param data[in] value + + \return none, device[addr] = value + */ +extern void ia_css_device_store_uint16( + const hrt_address addr, + const uint16_t data); + +/*! Write a 32-bit value to a device register or memory in the device + + \param addr[in] Local address + \param data[in] value + + \return none, device[addr] = value + */ +extern void ia_css_device_store_uint32( + const hrt_address addr, + const uint32_t data); + +/*! Write a 64-bit value to a device register or memory in the device + + \param addr[in] Local address + \param data[in] value + + \return none, device[addr] = value + */ +extern void ia_css_device_store_uint64( + const hrt_address addr, + const uint64_t data); + +/*! Read an array of bytes from device registers or memory in the device + + \param addr[in] Local address + \param data[out] pointer to the destination array + \param size[in] number of bytes to read + + \return none + */ +extern void ia_css_device_load( + const hrt_address addr, + void *data, + const size_t size); + +/*! Write an array of bytes to device registers or memory in the device + + \param addr[in] Local address + \param data[in] pointer to the source array + \param size[in] number of bytes to write + + \return none + */ +extern void ia_css_device_store( + const hrt_address addr, + const void *data, + const size_t size); + +#endif /* __DEVICE_ACCESS_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/dma.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/dma.h new file mode 100644 index 0000000000000000000000000000000000000000..b266191f21ef8cfe87863331464a524649bf3a0f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/dma.h @@ -0,0 +1,48 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __DMA_H_INCLUDED__ +#define __DMA_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the DMA device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + * + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "dma_local.h" + +#ifndef __INLINE_DMA__ +#define STORAGE_CLASS_DMA_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_DMA_C +#include "dma_public.h" +#else /* __INLINE_DMA__ */ +#define STORAGE_CLASS_DMA_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_DMA_C STORAGE_CLASS_INLINE +#include "dma_private.h" +#endif /* __INLINE_DMA__ */ + +#endif /* __DMA_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/error_support.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/error_support.h new file mode 100644 index 0000000000000000000000000000000000000000..46af7ec684077cb4567f101322f7980072ede7b9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/error_support.h @@ -0,0 +1,77 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ERROR_SUPPORT_H_INCLUDED__ +#define __ERROR_SUPPORT_H_INCLUDED__ + +#if defined(_MSC_VER) +#include +/* + * Put here everything _MSC_VER specific not covered in + * "errno.h" + */ +#define EINVAL 22 +#define EBADE 52 +#define ENODATA 61 +#define ENOTCONN 107 +#define ENOTSUP 252 +#define ENOBUFS 233 + + +#elif defined(__HIVECC) +#include +/* + * Put here everything __HIVECC specific not covered in + * "errno.h" + */ + +#elif defined(__KERNEL__) +#include +/* + * Put here everything __KERNEL__ specific not covered in + * "errno.h" + */ +#define ENOTSUP 252 + +#elif defined(__GNUC__) +#include +/* + * Put here everything __GNUC__ specific not covered in + * "errno.h" + */ + +#else /* default is for the FIST environment */ +#include +/* + * Put here everything FIST specific not covered in + * "errno.h" + */ + +#endif + +#define verifexit(cond,error_tag) \ +do { \ + if (!(cond)){ \ + goto EXIT; \ + } \ +} while(0) + +#define verifjmpexit(cond) \ +do { \ + if (!(cond)){ \ + goto EXIT; \ + } \ +} while(0) + +#endif /* __ERROR_SUPPORT_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/event_fifo.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/event_fifo.h new file mode 100644 index 0000000000000000000000000000000000000000..78827c554cc36109f8b24a970235b1180aae9920 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/event_fifo.h @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __EVENT_FIFO_H +#define __EVENT_FIFO_H + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the IRQ device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "event_fifo_local.h" + +#ifndef __INLINE_EVENT__ +#define STORAGE_CLASS_EVENT_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_EVENT_C +#include "event_fifo_public.h" +#else /* __INLINE_EVENT__ */ +#define STORAGE_CLASS_EVENT_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_EVENT_C STORAGE_CLASS_INLINE +#include "event_fifo_private.h" +#endif /* __INLINE_EVENT__ */ + +#endif /* __EVENT_FIFO_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/fifo_monitor.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/fifo_monitor.h new file mode 100644 index 0000000000000000000000000000000000000000..3bdd260bcaa5a761cd1ef8c0b28e93b2eb617fd4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/fifo_monitor.h @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __FIFO_MONITOR_H_INCLUDED__ +#define __FIFO_MONITOR_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the input system device(s). It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "fifo_monitor_local.h" + +#ifndef __INLINE_FIFO_MONITOR__ +#define STORAGE_CLASS_FIFO_MONITOR_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_FIFO_MONITOR_C +#include "fifo_monitor_public.h" +#else /* __INLINE_FIFO_MONITOR__ */ +#define STORAGE_CLASS_FIFO_MONITOR_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_FIFO_MONITOR_C STORAGE_CLASS_INLINE +#include "fifo_monitor_private.h" +#endif /* __INLINE_FIFO_MONITOR__ */ + +#endif /* __FIFO_MONITOR_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/gdc_device.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/gdc_device.h new file mode 100644 index 0000000000000000000000000000000000000000..016132ba0b7f461661451249cb97bcc9f7d18dfc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/gdc_device.h @@ -0,0 +1,49 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GDC_DEVICE_H_INCLUDED__ +#define __GDC_DEVICE_H_INCLUDED__ + +/* The file gdc.h already exists */ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the GDC device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "gdc_local.h" + +#ifndef __INLINE_GDC__ +#define STORAGE_CLASS_GDC_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_GDC_C +#include "gdc_public.h" +#else /* __INLINE_GDC__ */ +#define STORAGE_CLASS_GDC_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_GDC_C STORAGE_CLASS_INLINE +#include "gdc_private.h" +#endif /* __INLINE_GDC__ */ + +#endif /* __GDC_DEVICE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/gp_device.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/gp_device.h new file mode 100644 index 0000000000000000000000000000000000000000..766d2532d8f9b2126bc43dc3429900403e8138bd --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/gp_device.h @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GP_DEVICE_H_INCLUDED__ +#define __GP_DEVICE_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the input system device(s). It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "gp_device_local.h" + +#ifndef __INLINE_GP_DEVICE__ +#define STORAGE_CLASS_GP_DEVICE_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_GP_DEVICE_C +#include "gp_device_public.h" +#else /* __INLINE_GP_DEVICE__ */ +#define STORAGE_CLASS_GP_DEVICE_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_GP_DEVICE_C STORAGE_CLASS_INLINE +#include "gp_device_private.h" +#endif /* __INLINE_GP_DEVICE__ */ + +#endif /* __GP_DEVICE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/gp_timer.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/gp_timer.h new file mode 100644 index 0000000000000000000000000000000000000000..ca70f5603bf818e2fb032bcc549c9421f03fcac5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/gp_timer.h @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GP_TIMER_H_INCLUDED__ +#define __GP_TIMER_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the input system device(s). It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "storage_class.h" + +#include "system_local.h" /*GP_TIMER_BASE address */ +#include "gp_timer_local.h" /*GP_TIMER register offsets */ + +#ifndef __INLINE_GP_TIMER__ +#define STORAGE_CLASS_GP_TIMER_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_GP_TIMER_C +#include "gp_timer_public.h" /* functions*/ +#else /* __INLINE_GP_TIMER__ */ +#define STORAGE_CLASS_GP_TIMER_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_GP_TIMER_C STORAGE_CLASS_INLINE +#include "gp_timer_private.h" /* inline functions*/ +#endif /* __INLINE_GP_TIMER__ */ + +#endif /* __GP_TIMER_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/gpio.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..dec21bcb6f47168912eda1adcca036067c953579 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/gpio.h @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GPIO_H_INCLUDED__ +#define __GPIO_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the input system device(s). It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "gpio_local.h" + +#ifndef __INLINE_GPIO__ +#define STORAGE_CLASS_GPIO_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_GPIO_C +#include "gpio_public.h" +#else /* __INLINE_GPIO__ */ +#define STORAGE_CLASS_GPIO_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_GPIO_C STORAGE_CLASS_INLINE +#include "gpio_private.h" +#endif /* __INLINE_GPIO__ */ + +#endif /* __GPIO_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/hmem.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/hmem.h new file mode 100644 index 0000000000000000000000000000000000000000..671dd5b5fca618f6335dafc8edfeaef2928bd696 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/hmem.h @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __HMEM_H_INCLUDED__ +#define __HMEM_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the HMEM device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "hmem_local.h" + +#ifndef __INLINE_HMEM__ +#define STORAGE_CLASS_HMEM_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_HMEM_C +#include "hmem_public.h" +#else /* __INLINE_HMEM__ */ +#define STORAGE_CLASS_HMEM_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_HMEM_C STORAGE_CLASS_INLINE +#include "hmem_private.h" +#endif /* __INLINE_HMEM__ */ + +#endif /* __HMEM_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/csi_rx_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/csi_rx_public.h new file mode 100644 index 0000000000000000000000000000000000000000..396240954bed15332b03a8457f0db6efc16625e5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/csi_rx_public.h @@ -0,0 +1,135 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __CSI_RX_PUBLIC_H_INCLUDED__ +#define __CSI_RX_PUBLIC_H_INCLUDED__ + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 +/***************************************************** + * + * Native command interface (NCI). + * + *****************************************************/ +/** + * @brief Get the csi rx frontend state. + * Get the state of the csi rx frontend regiester-set. + * + * @param[in] id The global unique ID of the csi rx fe controller. + * @param[out] state Point to the register-state. + */ +STORAGE_CLASS_CSI_RX_H void csi_rx_fe_ctrl_get_state( + const csi_rx_frontend_ID_t ID, + csi_rx_fe_ctrl_state_t *state); +/** + * @brief Dump the csi rx frontend state. + * Dump the state of the csi rx frontend regiester-set. + * + * @param[in] id The global unique ID of the csi rx fe controller. + * @param[in] state Point to the register-state. + */ +STORAGE_CLASS_CSI_RX_H void csi_rx_fe_ctrl_dump_state( + const csi_rx_frontend_ID_t ID, + csi_rx_fe_ctrl_state_t *state); +/** + * @brief Get the state of the csi rx fe dlane. + * Get the state of the register set per dlane process. + * + * @param[in] id The global unique ID of the input-buffer controller. + * @param[in] lane The lane ID. + * @param[out] state Point to the dlane state. + */ +STORAGE_CLASS_CSI_RX_H void csi_rx_fe_ctrl_get_dlane_state( + const csi_rx_frontend_ID_t ID, + const uint32_t lane, + csi_rx_fe_ctrl_lane_t *dlane_state); +/** + * @brief Get the csi rx backend state. + * Get the state of the csi rx backend regiester-set. + * + * @param[in] id The global unique ID of the csi rx be controller. + * @param[out] state Point to the register-state. + */ +STORAGE_CLASS_CSI_RX_H void csi_rx_be_ctrl_get_state( + const csi_rx_backend_ID_t ID, + csi_rx_be_ctrl_state_t *state); +/** + * @brief Dump the csi rx backend state. + * Dump the state of the csi rx backend regiester-set. + * + * @param[in] id The global unique ID of the csi rx be controller. + * @param[in] state Point to the register-state. + */ +STORAGE_CLASS_CSI_RX_H void csi_rx_be_ctrl_dump_state( + const csi_rx_backend_ID_t ID, + csi_rx_be_ctrl_state_t *state); +/** end of NCI */ + +/***************************************************** + * + * Device level interface (DLI). + * + *****************************************************/ +/** + * @brief Load the register value. + * Load the value of the register of the csi rx fe. + * + * @param[in] ID The global unique ID for the ibuf-controller instance. + * @param[in] reg The offet address of the register. + * + * @return the value of the register. + */ +STORAGE_CLASS_CSI_RX_H hrt_data csi_rx_fe_ctrl_reg_load( + const csi_rx_frontend_ID_t ID, + const hrt_address reg); +/** + * @brief Store a value to the register. + * Store a value to the registe of the csi rx fe. + * + * @param[in] ID The global unique ID for the ibuf-controller instance. + * @param[in] reg The offet address of the register. + * @param[in] value The value to be stored. + * + */ +STORAGE_CLASS_CSI_RX_H void csi_rx_fe_ctrl_reg_store( + const csi_rx_frontend_ID_t ID, + const hrt_address reg, + const hrt_data value); +/** + * @brief Load the register value. + * Load the value of the register of the csirx be. + * + * @param[in] ID The global unique ID for the ibuf-controller instance. + * @param[in] reg The offet address of the register. + * + * @return the value of the register. + */ +STORAGE_CLASS_CSI_RX_H hrt_data csi_rx_be_ctrl_reg_load( + const csi_rx_backend_ID_t ID, + const hrt_address reg); +/** + * @brief Store a value to the register. + * Store a value to the registe of the csi rx be. + * + * @param[in] ID The global unique ID for the ibuf-controller instance. + * @param[in] reg The offet address of the register. + * @param[in] value The value to be stored. + * + */ +STORAGE_CLASS_CSI_RX_H void csi_rx_be_ctrl_reg_store( + const csi_rx_backend_ID_t ID, + const hrt_address reg, + const hrt_data value); +/** end of DLI */ +#endif /* USE_INPUT_SYSTEM_VERSION_2401 */ +#endif /* __CSI_RX_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/debug_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/debug_public.h new file mode 100644 index 0000000000000000000000000000000000000000..90b4ba7e023fe976debb71b9fb27a4bdca1745d3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/debug_public.h @@ -0,0 +1,99 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __DEBUG_PUBLIC_H_INCLUDED__ +#define __DEBUG_PUBLIC_H_INCLUDED__ + +#include +#include "system_types.h" + +/*! brief + * + * Simple queuing trace buffer for debug data + * instantiatable in SP DMEM + * + * The buffer has a remote and and a local store + * which contain duplicate data (when in sync). + * The buffers are automatically synched when the + * user dequeues, or manualy using the synch function + * + * An alternative (storage efficient) implementation + * could manage the buffers to contain unique data + * + * The buffer empty status is computed from local + * state which does not reflect the presence of data + * in the remote buffer (unless the alternative + * implementation is followed) + */ + +typedef struct debug_data_s debug_data_t; +typedef struct debug_data_ddr_s debug_data_ddr_t; + +extern debug_data_t *debug_data_ptr; +extern hrt_address debug_buffer_address; +extern hrt_vaddress debug_buffer_ddr_address; + +/*! Check the empty state of the local debug data buffer + + \return isEmpty(buffer) + */ +STORAGE_CLASS_DEBUG_H bool is_debug_buffer_empty(void); + +/*! Dequeue a token from the debug data buffer + + \return isEmpty(buffer)?0:buffer[head] + */ +STORAGE_CLASS_DEBUG_H hrt_data debug_dequeue(void); + +/*! Synchronise the remote buffer to the local buffer + + \return none + */ +STORAGE_CLASS_DEBUG_H void debug_synch_queue(void); + +/*! Synchronise the remote buffer to the local buffer + + \return none + */ +STORAGE_CLASS_DEBUG_H void debug_synch_queue_isp(void); + + +/*! Synchronise the remote buffer to the local buffer + + \return none + */ +STORAGE_CLASS_DEBUG_H void debug_synch_queue_ddr(void); + +/*! Set the offset/address of the (remote) debug buffer + + \return none + */ +extern void debug_buffer_init( + const hrt_address addr); + +/*! Set the offset/address of the (remote) debug buffer + + \return none + */ +extern void debug_buffer_ddr_init( + const hrt_vaddress addr); + +/*! Set the (remote) operating mode of the debug buffer + + \return none + */ +extern void debug_buffer_setmode( + const debug_buf_mode_t mode); + +#endif /* __DEBUG_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/dma_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/dma_public.h new file mode 100644 index 0000000000000000000000000000000000000000..1d5e38ffe9389ea75e9ce66b945aaaadb5ec6847 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/dma_public.h @@ -0,0 +1,73 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __DMA_PUBLIC_H_INCLUDED__ +#define __DMA_PUBLIC_H_INCLUDED__ + +#include "system_types.h" + +typedef struct dma_state_s dma_state_t; + +/*! Read the control registers of DMA[ID] + + \param ID[in] DMA identifier + \param state[out] input formatter state structure + + \return none, state = DMA[ID].state + */ +extern void dma_get_state( + const dma_ID_t ID, + dma_state_t *state); + +/*! Write to a control register of DMA[ID] + + \param ID[in] DMA identifier + \param reg[in] register index + \param value[in] The data to be written + + \return none, DMA[ID].ctrl[reg] = value + */ +STORAGE_CLASS_DMA_H void dma_reg_store( + const dma_ID_t ID, + const unsigned int reg, + const hrt_data value); + +/*! Read from a control register of DMA[ID] + + \param ID[in] DMA identifier + \param reg[in] register index + \param value[in] The data to be written + + \return DMA[ID].ctrl[reg] + */ +STORAGE_CLASS_DMA_H hrt_data dma_reg_load( + const dma_ID_t ID, + const unsigned int reg); + + +/*! Set maximum burst size of DMA[ID] + + \param ID[in] DMA identifier + \param conn[in] Connection to set max burst size for + \param max_burst_size[in] Maximum burst size in words + + \return none +*/ +void +dma_set_max_burst_size( + dma_ID_t ID, + dma_connection conn, + uint32_t max_burst_size); + +#endif /* __DMA_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/event_fifo_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/event_fifo_public.h new file mode 100644 index 0000000000000000000000000000000000000000..d95bc7070f4c23376eba8ef586f2e52e22cfdf27 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/event_fifo_public.h @@ -0,0 +1,79 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __EVENT_FIFO_PUBLIC_H +#define __EVENT_FIFO_PUBLIC_H + +#include +#include "system_types.h" + +/*! Blocking read from an event source EVENT[ID] + + \param ID[in] EVENT identifier + + \return none, dequeue(event_queue[ID]) + */ +STORAGE_CLASS_EVENT_H void event_wait_for( + const event_ID_t ID); + +/*! Conditional blocking wait for an event source EVENT[ID] + + \param ID[in] EVENT identifier + \param cnd[in] predicate + + \return none, if(cnd) dequeue(event_queue[ID]) + */ +STORAGE_CLASS_EVENT_H void cnd_event_wait_for( + const event_ID_t ID, + const bool cnd); + +/*! Blocking read from an event source EVENT[ID] + + \param ID[in] EVENT identifier + + \return dequeue(event_queue[ID]) + */ +STORAGE_CLASS_EVENT_H hrt_data event_receive_token( + const event_ID_t ID); + +/*! Blocking write to an event sink EVENT[ID] + + \param ID[in] EVENT identifier + \param token[in] token to be written on the event + + \return none, enqueue(event_queue[ID]) + */ +STORAGE_CLASS_EVENT_H void event_send_token( + const event_ID_t ID, + const hrt_data token); + +/*! Query an event source EVENT[ID] + + \param ID[in] EVENT identifier + + \return !isempty(event_queue[ID]) + */ +STORAGE_CLASS_EVENT_H bool is_event_pending( + const event_ID_t ID); + +/*! Query an event sink EVENT[ID] + + \param ID[in] EVENT identifier + + \return !isfull(event_queue[ID]) + */ +STORAGE_CLASS_EVENT_H bool can_event_send_token( + const event_ID_t ID); + +#endif /* __EVENT_FIFO_PUBLIC_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/fifo_monitor_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/fifo_monitor_public.h new file mode 100644 index 0000000000000000000000000000000000000000..329f5d5049f29696f449d8e9d9554755b99895f9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/fifo_monitor_public.h @@ -0,0 +1,110 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __FIFO_MONITOR_PUBLIC_H_INCLUDED__ +#define __FIFO_MONITOR_PUBLIC_H_INCLUDED__ + +#include "system_types.h" + +typedef struct fifo_channel_state_s fifo_channel_state_t; +typedef struct fifo_switch_state_s fifo_switch_state_t; +typedef struct fifo_monitor_state_s fifo_monitor_state_t; + +/*! Set a fifo switch multiplex + + \param ID[in] FIFO_MONITOR identifier + \param switch_id[in] fifo switch identifier + \param sel[in] fifo switch selector + + \return none, fifo_switch[switch_id].sel = sel + */ +STORAGE_CLASS_FIFO_MONITOR_H void fifo_switch_set( + const fifo_monitor_ID_t ID, + const fifo_switch_t switch_id, + const hrt_data sel); + +/*! Get a fifo switch multiplex + + \param ID[in] FIFO_MONITOR identifier + \param switch_id[in] fifo switch identifier + + \return fifo_switch[switch_id].sel + */ +STORAGE_CLASS_FIFO_MONITOR_H hrt_data fifo_switch_get( + const fifo_monitor_ID_t ID, + const fifo_switch_t switch_id); + +/*! Read the state of FIFO_MONITOR[ID] + + \param ID[in] FIFO_MONITOR identifier + \param state[out] fifo monitor state structure + + \return none, state = FIFO_MONITOR[ID].state + */ +extern void fifo_monitor_get_state( + const fifo_monitor_ID_t ID, + fifo_monitor_state_t *state); + +/*! Read the state of a fifo channel + + \param ID[in] FIFO_MONITOR identifier + \param channel_id[in] fifo channel identifier + \param state[out] fifo channel state structure + + \return none, state = fifo_channel[channel_id].state + */ +extern void fifo_channel_get_state( + const fifo_monitor_ID_t ID, + const fifo_channel_t channel_id, + fifo_channel_state_t *state); + +/*! Read the state of a fifo switch + + \param ID[in] FIFO_MONITOR identifier + \param switch_id[in] fifo switch identifier + \param state[out] fifo switch state structure + + \return none, state = fifo_switch[switch_id].state + */ +extern void fifo_switch_get_state( + const fifo_monitor_ID_t ID, + const fifo_switch_t switch_id, + fifo_switch_state_t *state); + +/*! Write to a control register of FIFO_MONITOR[ID] + + \param ID[in] FIFO_MONITOR identifier + \param reg[in] register index + \param value[in] The data to be written + + \return none, FIFO_MONITOR[ID].ctrl[reg] = value + */ +STORAGE_CLASS_FIFO_MONITOR_H void fifo_monitor_reg_store( + const fifo_monitor_ID_t ID, + const unsigned int reg, + const hrt_data value); + +/*! Read from a control register of FIFO_MONITOR[ID] + + \param ID[in] FIFO_MONITOR identifier + \param reg[in] register index + \param value[in] The data to be written + + \return FIFO_MONITOR[ID].ctrl[reg] + */ +STORAGE_CLASS_FIFO_MONITOR_H hrt_data fifo_monitor_reg_load( + const fifo_monitor_ID_t ID, + const unsigned int reg); + +#endif /* __FIFO_MONITOR_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/gdc_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/gdc_public.h new file mode 100644 index 0000000000000000000000000000000000000000..d27f87a719dbecf95a7826a52520660099a2c986 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/gdc_public.h @@ -0,0 +1,59 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GDC_PUBLIC_H_INCLUDED__ +#define __GDC_PUBLIC_H_INCLUDED__ + +/*! Write the bicubic interpolation table of GDC[ID] + + \param ID[in] GDC identifier + \param data[in] The data matrix to be written + + \pre + - data must point to a matrix[4][HRT_GDC_N] + + \implementation dependent + - The value of "HRT_GDC_N" is device specific + - The LUT should not be partially written + - The LUT format is a quadri-phase interpolation + table. The layout is device specific + - The range of the values data[n][m] is device + specific + + \return none, GDC[ID].lut[0...3][0...HRT_GDC_N-1] = data + */ +STORAGE_CLASS_EXTERN void gdc_lut_store( + const gdc_ID_t ID, + const int data[4][HRT_GDC_N]); + +/*! Convert the bicubic interpolation table of GDC[ID] to the ISP-specific format + + \param ID[in] GDC identifier + \param in_lut[in] The data matrix to be converted + \param out_lut[out] The data matrix as the output of conversion + */ +STORAGE_CLASS_EXTERN void gdc_lut_convert_to_isp_format( + const int in_lut[4][HRT_GDC_N], + int out_lut[4][HRT_GDC_N]); + +/*! Return the integer representation of 1.0 of GDC[ID] + + \param ID[in] GDC identifier + + \return unity + */ +STORAGE_CLASS_EXTERN int gdc_get_unity( + const gdc_ID_t ID); + +#endif /* __GDC_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/gp_device_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/gp_device_public.h new file mode 100644 index 0000000000000000000000000000000000000000..acbce0fd658fe1e278ac03b6ec5d0ffadc726e0f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/gp_device_public.h @@ -0,0 +1,58 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GP_DEVICE_PUBLIC_H_INCLUDED__ +#define __GP_DEVICE_PUBLIC_H_INCLUDED__ + +#include "system_types.h" + +typedef struct gp_device_state_s gp_device_state_t; + +/*! Read the state of GP_DEVICE[ID] + + \param ID[in] GP_DEVICE identifier + \param state[out] gp device state structure + + \return none, state = GP_DEVICE[ID].state + */ +extern void gp_device_get_state( + const gp_device_ID_t ID, + gp_device_state_t *state); + +/*! Write to a control register of GP_DEVICE[ID] + + \param ID[in] GP_DEVICE identifier + \param reg_addr[in] register byte address + \param value[in] The data to be written + + \return none, GP_DEVICE[ID].ctrl[reg] = value + */ +STORAGE_CLASS_GP_DEVICE_H void gp_device_reg_store( + const gp_device_ID_t ID, + const unsigned int reg_addr, + const hrt_data value); + +/*! Read from a control register of GP_DEVICE[ID] + + \param ID[in] GP_DEVICE identifier + \param reg_addr[in] register byte address + \param value[in] The data to be written + + \return GP_DEVICE[ID].ctrl[reg] + */ +STORAGE_CLASS_GP_DEVICE_H hrt_data gp_device_reg_load( + const gp_device_ID_t ID, + const hrt_address reg_addr); + +#endif /* __GP_DEVICE_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/gp_timer_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/gp_timer_public.h new file mode 100644 index 0000000000000000000000000000000000000000..276e2fa9b1e78d4ca59ff177458022299fddf678 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/gp_timer_public.h @@ -0,0 +1,34 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GP_TIMER_PUBLIC_H_INCLUDED__ +#define __GP_TIMER_PUBLIC_H_INCLUDED__ + +#include "system_types.h" + +/*! initialize mentioned timer +param ID timer_id +*/ +extern void +gp_timer_init(gp_timer_ID_t ID); + + +/*! read timer value for (platform selected)selected timer. +param ID timer_id + \return uint32_t 32 bit timer value +*/ +extern uint32_t +gp_timer_read(gp_timer_ID_t ID); + +#endif /* __GP_TIMER_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/gpio_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/gpio_public.h new file mode 100644 index 0000000000000000000000000000000000000000..82eaa0d48bee5d56db1296ab5ce82c8b6eb03302 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/gpio_public.h @@ -0,0 +1,45 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __GPIO_PUBLIC_H_INCLUDED__ +#define __GPIO_PUBLIC_H_INCLUDED__ + +#include "system_types.h" + +/*! Write to a control register of GPIO[ID] + + \param ID[in] GPIO identifier + \param reg_addr[in] register byte address + \param value[in] The data to be written + + \return none, GPIO[ID].ctrl[reg] = value + */ +STORAGE_CLASS_GPIO_H void gpio_reg_store( + const gpio_ID_t ID, + const unsigned int reg_addr, + const hrt_data value); + +/*! Read from a control register of GPIO[ID] + + \param ID[in] GPIO identifier + \param reg_addr[in] register byte address + \param value[in] The data to be written + + \return GPIO[ID].ctrl[reg] + */ +STORAGE_CLASS_GPIO_H hrt_data gpio_reg_load( + const gpio_ID_t ID, + const unsigned int reg_addr); + +#endif /* __GPIO_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/hmem_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/hmem_public.h new file mode 100644 index 0000000000000000000000000000000000000000..9b8e7c92442dac1e28d0bde731b1baa149d61e1b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/hmem_public.h @@ -0,0 +1,32 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __HMEM_PUBLIC_H_INCLUDED__ +#define __HMEM_PUBLIC_H_INCLUDED__ + +#include /* size_t */ + +/*! Return the size of HMEM[ID] + + \param ID[in] HMEM identifier + + \Note: The size is the byte size of the area it occupies + in the address map. I.e. disregarding internal structure + + \return sizeof(HMEM[ID]) + */ +STORAGE_CLASS_HMEM_H size_t sizeof_hmem( + const hmem_ID_t ID); + +#endif /* __HMEM_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/ibuf_ctrl_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/ibuf_ctrl_public.h new file mode 100644 index 0000000000000000000000000000000000000000..1ac0e64e539cb30154c62d5785c16ac2a108d477 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/ibuf_ctrl_public.h @@ -0,0 +1,93 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IBUF_CTRL_PUBLIC_H_INCLUDED__ +#define __IBUF_CTRL_PUBLIC_H_INCLUDED__ + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 +/***************************************************** + * + * Native command interface (NCI). + * + *****************************************************/ +/** + * @brief Get the ibuf-controller state. + * Get the state of the ibuf-controller regiester-set. + * + * @param[in] id The global unique ID of the input-buffer controller. + * @param[out] state Point to the register-state. + */ +STORAGE_CLASS_IBUF_CTRL_H void ibuf_ctrl_get_state( + const ibuf_ctrl_ID_t ID, + ibuf_ctrl_state_t *state); + +/** + * @brief Get the state of the ibuf-controller process. + * Get the state of the register set per buf-controller process. + * + * @param[in] id The global unique ID of the input-buffer controller. + * @param[in] proc_id The process ID. + * @param[out] state Point to the process state. + */ +STORAGE_CLASS_IBUF_CTRL_H void ibuf_ctrl_get_proc_state( + const ibuf_ctrl_ID_t ID, + const uint32_t proc_id, + ibuf_ctrl_proc_state_t *state); +/** + * @brief Dump the ibuf-controller state. + * Dump the state of the ibuf-controller regiester-set. + * + * @param[in] id The global unique ID of the input-buffer controller. + * @param[in] state Pointer to the register-state. + */ +STORAGE_CLASS_IBUF_CTRL_H void ibuf_ctrl_dump_state( + const ibuf_ctrl_ID_t ID, + ibuf_ctrl_state_t *state); +/** end of NCI */ + +/***************************************************** + * + * Device level interface (DLI). + * + *****************************************************/ +/** + * @brief Load the register value. + * Load the value of the register of the ibuf-controller. + * + * @param[in] ID The global unique ID for the ibuf-controller instance. + * @param[in] reg The offet address of the register. + * + * @return the value of the register. + */ +STORAGE_CLASS_IBUF_CTRL_H hrt_data ibuf_ctrl_reg_load( + const ibuf_ctrl_ID_t ID, + const hrt_address reg); + +/** + * @brief Store a value to the register. + * Store a value to the registe of the ibuf-controller. + * + * @param[in] ID The global unique ID for the ibuf-controller instance. + * @param[in] reg The offet address of the register. + * @param[in] value The value to be stored. + * + */ +STORAGE_CLASS_IBUF_CTRL_H void ibuf_ctrl_reg_store( + const ibuf_ctrl_ID_t ID, + const hrt_address reg, + const hrt_data value); +/** end of DLI */ + +#endif /* USE_INPUT_SYSTEM_VERSION_2401 */ +#endif /* __IBUF_CTRL_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/input_formatter_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/input_formatter_public.h new file mode 100644 index 0000000000000000000000000000000000000000..2db70893daf9cf508ff02bc3c13bfbd7c89cda01 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/input_formatter_public.h @@ -0,0 +1,115 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_FORMATTER_PUBLIC_H_INCLUDED__ +#define __INPUT_FORMATTER_PUBLIC_H_INCLUDED__ + +#include +#include "system_types.h" + +/*! Reset INPUT_FORMATTER[ID] + + \param ID[in] INPUT_FORMATTER identifier + + \return none, reset(INPUT_FORMATTER[ID]) + */ +extern void input_formatter_rst( + const input_formatter_ID_t ID); + +/*! Set the blocking mode of INPUT_FORMATTER[ID] + + \param ID[in] INPUT_FORMATTER identifier + \param enable[in] blocking enable flag + + \use + - In HW, the capture unit will deliver an infinite stream of frames, + the input formatter will synchronise on the first SOF. In simulation + there are only a fixed number of frames, presented only once. By + enabling blocking the inputformatter will wait on the first presented + frame, thus avoiding race in the simulation setup. + + \return none, INPUT_FORMATTER[ID].blocking_mode = enable + */ +extern void input_formatter_set_fifo_blocking_mode( + const input_formatter_ID_t ID, + const bool enable); + +/*! Return the data alignment of INPUT_FORMATTER[ID] + + \param ID[in] INPUT_FORMATTER identifier + + \return alignment(INPUT_FORMATTER[ID].data) + */ +extern unsigned int input_formatter_get_alignment( + const input_formatter_ID_t ID); + +/*! Read the source switch state into INPUT_FORMATTER[ID] + + \param ID[in] INPUT_FORMATTER identifier + \param state[out] input formatter switch state structure + + \return none, state = INPUT_FORMATTER[ID].switch_state + */ +extern void input_formatter_get_switch_state( + const input_formatter_ID_t ID, + input_formatter_switch_state_t *state); + +/*! Read the control registers of INPUT_FORMATTER[ID] + + \param ID[in] INPUT_FORMATTER identifier + \param state[out] input formatter state structure + + \return none, state = INPUT_FORMATTER[ID].state + */ +extern void input_formatter_get_state( + const input_formatter_ID_t ID, + input_formatter_state_t *state); + +/*! Read the control registers of bin copy INPUT_FORMATTER[ID] + + \param ID[in] INPUT_FORMATTER identifier + \param state[out] input formatter state structure + + \return none, state = INPUT_FORMATTER[ID].state + */ +extern void input_formatter_bin_get_state( + const input_formatter_ID_t ID, + input_formatter_bin_state_t *state); + +/*! Write to a control register of INPUT_FORMATTER[ID] + + \param ID[in] INPUT_FORMATTER identifier + \param reg_addr[in] register byte address + \param value[in] The data to be written + + \return none, INPUT_FORMATTER[ID].ctrl[reg] = value + */ +STORAGE_CLASS_INPUT_FORMATTER_H void input_formatter_reg_store( + const input_formatter_ID_t ID, + const hrt_address reg_addr, + const hrt_data value); + +/*! Read from a control register of INPUT_FORMATTER[ID] + + \param ID[in] INPUT_FORMATTER identifier + \param reg_addr[in] register byte address + \param value[in] The data to be written + + \return INPUT_FORMATTER[ID].ctrl[reg] + */ +STORAGE_CLASS_INPUT_FORMATTER_H hrt_data input_formatter_reg_load( + const input_formatter_ID_t ID, + const unsigned int reg_addr); + +#endif /* __INPUT_FORMATTER_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/input_system_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/input_system_public.h new file mode 100644 index 0000000000000000000000000000000000000000..1596757fe9ef86ce565f1ffa37a10f1cb10fa1f9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/input_system_public.h @@ -0,0 +1,376 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __INPUT_SYSTEM_PUBLIC_H_INCLUDED__ +#define __INPUT_SYSTEM_PUBLIC_H_INCLUDED__ + +#include +#ifdef USE_INPUT_SYSTEM_VERSION_2401 +#include "isys_public.h" +#else + +typedef struct input_system_state_s input_system_state_t; +typedef struct receiver_state_s receiver_state_t; + +/*! Read the state of INPUT_SYSTEM[ID] + + \param ID[in] INPUT_SYSTEM identifier + \param state[out] input system state structure + + \return none, state = INPUT_SYSTEM[ID].state + */ +extern void input_system_get_state( + const input_system_ID_t ID, + input_system_state_t *state); + +/*! Read the state of RECEIVER[ID] + + \param ID[in] RECEIVER identifier + \param state[out] receiver state structure + + \return none, state = RECEIVER[ID].state + */ +extern void receiver_get_state( + const rx_ID_t ID, + receiver_state_t *state); + +/*! Flag whether a MIPI format is YUV420 + + \param mipi_format[in] MIPI format + + \return mipi_format == YUV420 + */ +extern bool is_mipi_format_yuv420( + const mipi_format_t mipi_format); + +/*! Set compression parameters for cfg[cfg_ID] of RECEIVER[ID] + + \param ID[in] RECEIVER identifier + \param cfg_ID[in] Configuration identifier + \param comp[in] Compression method + \param pred[in] Predictor method + + \NOTE: the storage of compression configuration is + implementation specific. The config can be + carried either on MIPI ports or on MIPI channels + + \return none, RECEIVER[ID].cfg[cfg_ID] = {comp, pred} + */ +extern void receiver_set_compression( + const rx_ID_t ID, + const unsigned int cfg_ID, + const mipi_compressor_t comp, + const mipi_predictor_t pred); + +/*! Enable PORT[port_ID] of RECEIVER[ID] + + \param ID[in] RECEIVER identifier + \param port_ID[in] mipi PORT identifier + \param cnd[in] irq predicate + + \return None, enable(RECEIVER[ID].PORT[port_ID]) + */ +extern void receiver_port_enable( + const rx_ID_t ID, + const mipi_port_ID_t port_ID, + const bool cnd); + +/*! Flag if PORT[port_ID] of RECEIVER[ID] is enabled + + \param ID[in] RECEIVER identifier + \param port_ID[in] mipi PORT identifier + + \return enable(RECEIVER[ID].PORT[port_ID]) == true + */ +extern bool is_receiver_port_enabled( + const rx_ID_t ID, + const mipi_port_ID_t port_ID); + +/*! Enable the IRQ channels of PORT[port_ID] of RECEIVER[ID] + + \param ID[in] RECEIVER identifier + \param port_ID[in] mipi PORT identifier + \param irq_info[in] irq channels + + \return None, enable(RECEIVER[ID].PORT[port_ID].irq_info) + */ +extern void receiver_irq_enable( + const rx_ID_t ID, + const mipi_port_ID_t port_ID, + const rx_irq_info_t irq_info); + +/*! Return the IRQ status of PORT[port_ID] of RECEIVER[ID] + + \param ID[in] RECEIVER identifier + \param port_ID[in] mipi PORT identifier + + \return RECEIVER[ID].PORT[port_ID].irq_info + */ +extern rx_irq_info_t receiver_get_irq_info( + const rx_ID_t ID, + const mipi_port_ID_t port_ID); + +/*! Clear the IRQ status of PORT[port_ID] of RECEIVER[ID] + + \param ID[in] RECEIVER identifier + \param port_ID[in] mipi PORT identifier + \param irq_info[in] irq status + + \return None, clear(RECEIVER[ID].PORT[port_ID].irq_info) + */ +extern void receiver_irq_clear( + const rx_ID_t ID, + const mipi_port_ID_t port_ID, + const rx_irq_info_t irq_info); + +/*! Write to a control register of INPUT_SYSTEM[ID] + + \param ID[in] INPUT_SYSTEM identifier + \param reg[in] register index + \param value[in] The data to be written + + \return none, INPUT_SYSTEM[ID].ctrl[reg] = value + */ +STORAGE_CLASS_INPUT_SYSTEM_H void input_system_reg_store( + const input_system_ID_t ID, + const hrt_address reg, + const hrt_data value); + +/*! Read from a control register of INPUT_SYSTEM[ID] + + \param ID[in] INPUT_SYSTEM identifier + \param reg[in] register index + \param value[in] The data to be written + + \return INPUT_SYSTEM[ID].ctrl[reg] + */ +STORAGE_CLASS_INPUT_SYSTEM_H hrt_data input_system_reg_load( + const input_system_ID_t ID, + const hrt_address reg); + +/*! Write to a control register of RECEIVER[ID] + + \param ID[in] RECEIVER identifier + \param reg[in] register index + \param value[in] The data to be written + + \return none, RECEIVER[ID].ctrl[reg] = value + */ +STORAGE_CLASS_INPUT_SYSTEM_H void receiver_reg_store( + const rx_ID_t ID, + const hrt_address reg, + const hrt_data value); + +/*! Read from a control register of RECEIVER[ID] + + \param ID[in] RECEIVER identifier + \param reg[in] register index + \param value[in] The data to be written + + \return RECEIVER[ID].ctrl[reg] + */ +STORAGE_CLASS_INPUT_SYSTEM_H hrt_data receiver_reg_load( + const rx_ID_t ID, + const hrt_address reg); + +/*! Write to a control register of PORT[port_ID] of RECEIVER[ID] + + \param ID[in] RECEIVER identifier + \param port_ID[in] mipi PORT identifier + \param reg[in] register index + \param value[in] The data to be written + + \return none, RECEIVER[ID].PORT[port_ID].ctrl[reg] = value + */ +STORAGE_CLASS_INPUT_SYSTEM_H void receiver_port_reg_store( + const rx_ID_t ID, + const mipi_port_ID_t port_ID, + const hrt_address reg, + const hrt_data value); + +/*! Read from a control register PORT[port_ID] of of RECEIVER[ID] + + \param ID[in] RECEIVER identifier + \param port_ID[in] mipi PORT identifier + \param reg[in] register index + \param value[in] The data to be written + + \return RECEIVER[ID].PORT[port_ID].ctrl[reg] + */ +STORAGE_CLASS_INPUT_SYSTEM_H hrt_data receiver_port_reg_load( + const rx_ID_t ID, + const mipi_port_ID_t port_ID, + const hrt_address reg); + +/*! Write to a control register of SUB_SYSTEM[sub_ID] of INPUT_SYSTEM[ID] + + \param ID[in] INPUT_SYSTEM identifier + \param port_ID[in] sub system identifier + \param reg[in] register index + \param value[in] The data to be written + + \return none, INPUT_SYSTEM[ID].SUB_SYSTEM[sub_ID].ctrl[reg] = value + */ +STORAGE_CLASS_INPUT_SYSTEM_H void input_system_sub_system_reg_store( + const input_system_ID_t ID, + const sub_system_ID_t sub_ID, + const hrt_address reg, + const hrt_data value); + +/*! Read from a control register SUB_SYSTEM[sub_ID] of INPUT_SYSTEM[ID] + + \param ID[in] INPUT_SYSTEM identifier + \param port_ID[in] sub system identifier + \param reg[in] register index + \param value[in] The data to be written + + \return INPUT_SYSTEM[ID].SUB_SYSTEM[sub_ID].ctrl[reg] + */ +STORAGE_CLASS_INPUT_SYSTEM_H hrt_data input_system_sub_system_reg_load( + const input_system_ID_t ID, + const sub_system_ID_t sub_ID, + const hrt_address reg); + + + +/////////////////////////////////////////////////////////////////////////// +// +// Functions for configuration phase on input system. +// +/////////////////////////////////////////////////////////////////////////// + +// Function that resets current configuration. +// remove the argument since it should be private. +input_system_error_t input_system_configuration_reset(void); + +// Function that commits current configuration. +// remove the argument since it should be private. +input_system_error_t input_system_configuration_commit(void); + +/////////////////////////////////////////////////////////////////////////// +// +// User functions: +// (encoded generic function) +// - no checking +// - decoding name and agruments into the generic (channel) configuration +// function. +// +/////////////////////////////////////////////////////////////////////////// + + +// FIFO channel config function user + +input_system_error_t input_system_csi_fifo_channel_cfg( + uint32_t ch_id, + input_system_csi_port_t port, + backend_channel_cfg_t backend_ch, + target_cfg2400_t target +); + +input_system_error_t input_system_csi_fifo_channel_with_counting_cfg( + uint32_t ch_id, + uint32_t nof_frame, + input_system_csi_port_t port, + backend_channel_cfg_t backend_ch, + uint32_t mem_region_size, + uint32_t nof_mem_regions, + target_cfg2400_t target +); + + +// SRAM channel config function user + +input_system_error_t input_system_csi_sram_channel_cfg( + uint32_t ch_id, + input_system_csi_port_t port, + backend_channel_cfg_t backend_ch, + uint32_t csi_mem_region_size, + uint32_t csi_nof_mem_regions, + target_cfg2400_t target +); + + +//XMEM channel config function user + +input_system_error_t input_system_csi_xmem_channel_cfg( + uint32_t ch_id, + input_system_csi_port_t port, + backend_channel_cfg_t backend_ch, + uint32_t mem_region_size, + uint32_t nof_mem_regions, + uint32_t acq_mem_region_size, + uint32_t acq_nof_mem_regions, + target_cfg2400_t target, + uint32_t nof_xmem_buffers +); + +input_system_error_t input_system_csi_xmem_capture_only_channel_cfg( + uint32_t ch_id, + uint32_t nof_frames, + input_system_csi_port_t port, + uint32_t csi_mem_region_size, + uint32_t csi_nof_mem_regions, + uint32_t acq_mem_region_size, + uint32_t acq_nof_mem_regions, + target_cfg2400_t target +); + +input_system_error_t input_system_csi_xmem_acquire_only_channel_cfg( + uint32_t ch_id, + uint32_t nof_frames, + input_system_csi_port_t port, + backend_channel_cfg_t backend_ch, + uint32_t acq_mem_region_size, + uint32_t acq_nof_mem_regions, + target_cfg2400_t target +); + +// Non - CSI channel config function user + +input_system_error_t input_system_prbs_channel_cfg( + uint32_t ch_id, + uint32_t nof_frames, + uint32_t seed, + uint32_t sync_gen_width, + uint32_t sync_gen_height, + uint32_t sync_gen_hblank_cycles, + uint32_t sync_gen_vblank_cycles, + target_cfg2400_t target +); + + +input_system_error_t input_system_tpg_channel_cfg( + uint32_t ch_id, + uint32_t nof_frames,//not used yet + uint32_t x_mask, + uint32_t y_mask, + uint32_t x_delta, + uint32_t y_delta, + uint32_t xy_mask, + uint32_t sync_gen_width, + uint32_t sync_gen_height, + uint32_t sync_gen_hblank_cycles, + uint32_t sync_gen_vblank_cycles, + target_cfg2400_t target +); + + +input_system_error_t input_system_gpfifo_channel_cfg( + uint32_t ch_id, + uint32_t nof_frames, + target_cfg2400_t target +); +#endif /* #ifdef USE_INPUT_SYSTEM_VERSION_2401 */ + +#endif /* __INPUT_SYSTEM_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/irq_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/irq_public.h new file mode 100644 index 0000000000000000000000000000000000000000..9aeaf8f082d26e0762d0fd810b11b76a021953f1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/irq_public.h @@ -0,0 +1,184 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IRQ_PUBLIC_H_INCLUDED__ +#define __IRQ_PUBLIC_H_INCLUDED__ + +#include +#include "system_types.h" + +/*! Read the control registers of IRQ[ID] + + \param ID[in] IRQ identifier + \param state[out] irq controller state structure + + \return none, state = IRQ[ID].state + */ +extern void irq_controller_get_state( + const irq_ID_t ID, + irq_controller_state_t *state); + +/*! Write to a control register of IRQ[ID] + + \param ID[in] IRQ identifier + \param reg[in] register index + \param value[in] The data to be written + + \return none, IRQ[ID].ctrl[reg] = value + */ +STORAGE_CLASS_IRQ_H void irq_reg_store( + const irq_ID_t ID, + const unsigned int reg, + const hrt_data value); + +/*! Read from a control register of IRQ[ID] + + \param ID[in] IRQ identifier + \param reg[in] register index + \param value[in] The data to be written + + \return IRQ[ID].ctrl[reg] + */ +STORAGE_CLASS_IRQ_H hrt_data irq_reg_load( + const irq_ID_t ID, + const unsigned int reg); + +/*! Enable an IRQ channel of IRQ[ID] with a mode + + \param ID[in] IRQ (device) identifier + \param irq[in] IRQ (channel) identifier + + \return none, enable(IRQ[ID].channel[irq_ID]) + */ +extern void irq_enable_channel( + const irq_ID_t ID, + const unsigned int irq_ID); + +/*! Enable pulse interrupts for IRQ[ID] with a mode + + \param ID[in] IRQ (device) identifier + \param enable enable/disable pulse interrupts + + \return none + */ +extern void irq_enable_pulse( + const irq_ID_t ID, + bool pulse); + +/*! Disable an IRQ channel of IRQ[ID] + + \param ID[in] IRQ (device) identifier + \param irq[in] IRQ (channel) identifier + + \return none, disable(IRQ[ID].channel[irq_ID]) + */ +extern void irq_disable_channel( + const irq_ID_t ID, + const unsigned int irq); + +/*! Clear the state of all IRQ channels of IRQ[ID] + + \param ID[in] IRQ (device) identifier + + \return none, clear(IRQ[ID].channel[]) + */ +extern void irq_clear_all( + const irq_ID_t ID); + +/*! Return the ID of a signalling IRQ channel of IRQ[ID] + + \param ID[in] IRQ (device) identifier + \param irq_id[out] active IRQ (channel) identifier + + \Note: This function operates as strtok(), based on the return + state the user is informed if there are additional signalling + channels + + \return state(IRQ[ID]) + */ +extern enum hrt_isp_css_irq_status irq_get_channel_id( + const irq_ID_t ID, + unsigned int *irq_id); + +/*! Raise an interrupt on channel irq_id of device IRQ[ID] + + \param ID[in] IRQ (device) identifier + \param irq_id[in] IRQ (channel) identifier + + \return none, signal(IRQ[ID].channel[irq_id]) + */ +extern void irq_raise( + const irq_ID_t ID, + const irq_sw_channel_id_t irq_id); + +/*! Test if any IRQ channel of the virtual super IRQ has raised a signal + + \return any(VIRQ.channel[irq_ID] != 0) + */ +extern bool any_virq_signal(void); + +/*! Enable an IRQ channel of the virtual super IRQ + + \param irq[in] IRQ (channel) identifier + \param en[in] predicate channel enable + + \return none, VIRQ.channel[irq_ID].enable = en + */ +extern void cnd_virq_enable_channel( + const virq_id_t irq_ID, + const bool en); + +/*! Clear the state of all IRQ channels of the virtual super IRQ + + \return none, clear(VIRQ.channel[]) + */ +extern void virq_clear_all(void); + +/*! Clear the IRQ info state of the virtual super IRQ + + \param irq_info[in/out] The IRQ (channel) state + + \return none + */ +extern void virq_clear_info( + virq_info_t *irq_info); + +/*! Return the ID of a signalling IRQ channel of the virtual super IRQ + + \param irq_id[out] active IRQ (channel) identifier + + \Note: This function operates as strtok(), based on the return + state the user is informed if there are additional signalling + channels + + \return state(IRQ[...]) + */ +extern enum hrt_isp_css_irq_status virq_get_channel_id( + virq_id_t *irq_id); + +/*! Return the IDs of all signaling IRQ channels of the virtual super IRQ + + \param irq_info[out] all active IRQ (channel) identifiers + + \Note: Unlike "irq_get_channel_id()" this function returns all + channel signaling info. The new info is OR'd with the current + info state. N.B. this is the same as repeatedly calling the function + "irq_get_channel_id()" in a (non-blocked) handler routine + + \return (error(state(IRQ[...])) + */ +extern enum hrt_isp_css_irq_status virq_get_channel_signals( + virq_info_t *irq_info); + +#endif /* __IRQ_PUBLIC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp2400_config.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp2400_config.h new file mode 100644 index 0000000000000000000000000000000000000000..ab3391716c82f50669c402e541b33c6762509a4d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp2400_config.h @@ -0,0 +1,24 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISP2400_CONFIG_H_INCLUDED__ +#define __ISP2400_CONFIG_H_INCLUDED__ + +#define NUM_BITS 14 +#define NUM_SLICE_ELEMS 4 +#define ROUNDMODE ROUND_NEAREST_EVEN +#define MAX_SHIFT_1W (NUM_BITS-1) /* Max number of bits a 1w input can be shifted */ +#define MAX_SHIFT_2W (2*NUM_BITS-1) /* Max number of bits a 2w input can be shifted */ + +#endif /* __ISP2400_CONFIG_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp2500_config.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp2500_config.h new file mode 100644 index 0000000000000000000000000000000000000000..4fae856f5a2342a4f6485b616836014d0ffc9938 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp2500_config.h @@ -0,0 +1,29 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISP2500_CONFIG_H_INCLUDED__ +#define __ISP2500_CONFIG_H_INCLUDED__ + +#define NUM_BITS 12 +#define NUM_SLICE_ELEMS 4 +#define ROUNDMODE ROUND_NEAREST_EVEN +#define MAX_SHIFT_1W (NUM_BITS-1) /* Max number of bits a 1w input can be shifted */ +#define MAX_SHIFT_2W (2*NUM_BITS-1) /* Max number of bits a 2w input can be shifted */ + + +#define HAS_div_unit + +#define HAS_vec_sub + +#endif /* __ISP2500_CONFIG_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp2600_config.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp2600_config.h new file mode 100644 index 0000000000000000000000000000000000000000..6086be8cb0d37841790c23a946105a172af6c4f5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp2600_config.h @@ -0,0 +1,34 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISP2600_CONFIG_H_INCLUDED__ +#define __ISP2600_CONFIG_H_INCLUDED__ + + +#define NUM_BITS 16 + + +#define NUM_SLICE_ELEMS 8 +#define ROUNDMODE ROUND_NEAREST_EVEN +#define MAX_SHIFT_1W (NUM_BITS-1) /* Max number of bits a 1w input can be shifted */ +#define MAX_SHIFT_2W (2*NUM_BITS-1) /* Max number of bits a 2w input can be shifted */ +#define ISP_NWAY 32 /* Number of elements in a vector in ISP 2600 */ + +#define HAS_div_unit +#define HAS_1w_sqrt_u_unit +#define HAS_2w_sqrt_u_unit + +#define HAS_vec_sub + +#endif /* __ISP2600_CONFIG_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp2601_config.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp2601_config.h new file mode 100644 index 0000000000000000000000000000000000000000..beceefa24ca0b85443c41989ad17a904a6150b49 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp2601_config.h @@ -0,0 +1,70 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISP2601_CONFIG_H_INCLUDED__ +#define __ISP2601_CONFIG_H_INCLUDED__ + +#define NUM_BITS 16 +#define ISP_VEC_ELEMBITS NUM_BITS +#define ISP_NWAY 32 +#define NUM_SLICE_ELEMS 4 +#define ROUNDMODE ROUND_NEAREST_EVEN +#define MAX_SHIFT_1W (NUM_BITS-1) /* Max number of bits a 1w input can be shifted */ +#define MAX_SHIFT_2W (2*NUM_BITS-1) /* Max number of bits a 2w input can be shifted */ + +#define HAS_div_unit +#define HAS_bfa_unit +#define HAS_1w_sqrt_u_unit +#define HAS_2w_sqrt_u_unit + +#define HAS_vec_sub + +/* Bit widths and element widths defined in HW implementation of BFA */ +#define BFA_THRESHOLD_BIT_CNT (8) +#define BFA_THRESHOLD_MASK ((1<> 1 + * + * This function subtracts _b from _a and right shifts + * the result by 1 bit with rounding. + * No overflow can occur. + * result = (_a - _b) >> 1 + * + * Note: This function will be deprecated due to + * the naming confusion and it will be replaced + * by "OP_1w_subhalfrnd". + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_subasr1( + const tvector1w _a, + const tvector1w _b); + +/** @brief Subtraction with shift right and rounding + * + * @param[in] _a first operand + * @param[in] _b second operand + * + * @return (_a - _b) >> 1 + * + * This function subtracts _b from _a and right shifts + * the result by 1 bit with rounding. + * No overflow can occur. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_subhalfrnd( + const tvector1w _a, + const tvector1w _b); + +/** @brief Subtraction with shift right and no rounding + * + * @param[in] _a first operand + * @param[in] _b second operand + * + * @return (_a - _b) >> 1 + * + * This function subtracts _b from _a and right shifts + * the result by 1 bit without rounding (i.e. truncation). + * No overflow can occur. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_subhalf( + const tvector1w _a, + const tvector1w _b); + + +/** @brief saturated absolute value + * + * @param[in] _a input + * + * @return saturated absolute value of the input + * + * This function will calculate the saturated absolute value of the input. + * in case of overflow it will saturate. + * if (_a > 0) return _a;
+ * else return CLIP(-_a, MIN_RANGE, MAX_RANGE);
+ */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_abs( + const tvector1w _a); + +/** @brief saturated absolute difference + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return sat(abs(a-b)); + * + * This function will calculate the saturated absolute value + * of the saturated difference of both inputs. + * result = sat(abs(sat(_a - _b))); + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_subabssat( + const tvector1w _a, + const tvector1w _b); + +/* Multiplicative */ + +/** @brief doubling multiply + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return product of _a and _b + * + * This function will calculate the product + * of the input arguments and returns a double + * precision result. + * No overflow can occur. + * result = _a * _b; + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector2w OP_1w_muld( + const tvector1w _a, + const tvector1w _b); + +/** @brief integer multiply + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return product of _a and _b + * + * This function will calculate the product + * of the input arguments and returns the LSB + * aligned single precision result. + * In case of overflow it will wrap around. + * result = _a * _b; + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_mul( + const tvector1w _a, + const tvector1w _b); + +/** @brief fractional saturating multiply + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return saturated product of _a and _b + * + * This function will calculate the fixed point + * product of the input arguments + * and returns a single precision result. + * In case of overflow it will saturate. + * FP_UNITY * FP_UNITY => FP_UNITY. + * result = CLIP(_a * _b >> (NUM_BITS-1), MIN_RANGE, MAX_RANGE); + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_qmul( + const tvector1w _a, + const tvector1w _b); + +/** @brief fractional saturating multiply with rounding + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return product of _a and _b + * + * This function will calculate the fixed point + * product of the input arguments + * and returns a single precision result. + * FP_UNITY * FP_UNITY => FP_UNITY. + * Depending on the rounding mode of the core + * it will round to nearest or to nearest even. + * result = CLIP(_a * _b >> (NUM_BITS-1), MIN_RANGE, MAX_RANGE); + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_qrmul( + const tvector1w _a, + const tvector1w _b); + +/* Comparative */ + +/** @brief equal + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return _a == _b + * + * This function will return true if both inputs + * are equal, and false if not equal. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tflags OP_1w_eq( + const tvector1w _a, + const tvector1w _b); + +/** @brief not equal + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return _a != _b + * + * This function will return false if both inputs + * are equal, and true if not equal. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tflags OP_1w_ne( + const tvector1w _a, + const tvector1w _b); + +/** @brief less or equal + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return _a <= _b + * + * This function will return true if _a is smaller + * or equal than _b. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tflags OP_1w_le( + const tvector1w _a, + const tvector1w _b); + +/** @brief less then + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return _a < _b + * + * This function will return true if _a is smaller + * than _b. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tflags OP_1w_lt( + const tvector1w _a, + const tvector1w _b); + +/** @brief greater or equal + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return _a >= _b + * + * This function will return true if _a is greater + * or equal than _b. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tflags OP_1w_ge( + const tvector1w _a, + const tvector1w _b); + +/** @brief greater than + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return _a > _b + * + * This function will return true if _a is greater + * than _b. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tflags OP_1w_gt( + const tvector1w _a, + const tvector1w _b); + +/* Shift */ + +/** @brief aritmetic shift right + * + * @param[in] _a input + * @param[in] _b shift amount + * + * @return _a >> _b + * + * This function will shift _a with _b bits to the right, + * preserving the sign bit. + * It asserts 0 <= _b <= MAX_SHIFT_1W. + * + * The operation count for this function assumes that + * the shift amount is a cloned scalar input. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_asr( + const tvector1w _a, + const tvector1w _b); + +/** @brief aritmetic shift right with rounding + * + * @param[in] _a input + * @param[in] _b shift amount + * + * @return _a >> _b + * + * If _b < NUM_BITS, this function will shift _a with _b bits to the right, + * preserving the sign bit, and depending on the rounding mode of the core + * it will round to nearest or to nearest even. + * If _b >= NUM_BITS, this function will return 0. + * It asserts 0 <= _b <= MAX_SHIFT_1W. + * The operation count for this function assumes that + * the shift amount is a cloned scalar input. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_asrrnd( + const tvector1w _a, + const tvector1w _b); + +/** @brief saturating arithmetic shift left + * + * @param[in] _a input + * @param[in] _b shift amount + * + * @return _a << _b + * + * If _b < MAX_BITDEPTH, this function will shift _a with _b bits to the left, + * saturating at MIN_RANGE/MAX_RANGE in case of overflow. + * If _b >= MAX_BITDEPTH, this function will return MIN_RANGE if _a < 0, + * MAX_RANGE if _a > 0, 0 if _a == 0. + * (with MAX_BITDEPTH=64) + * It asserts 0 <= _b <= MAX_SHIFT_1W. + * The operation count for this function assumes that + * the shift amount is a cloned scalar input. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_asl( + const tvector1w _a, + const tvector1w _b); + +/** @brief saturating aritmetic shift left + * + * @param[in] _a input + * @param[in] _b shift amount + * + * @return _a << _b + * + * This function is identical to OP_1w_asl( ) + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_aslsat( + const tvector1w _a, + const tvector1w _b); + +/** @brief logical shift left + * + * @param[in] _a input + * @param[in] _b shift amount + * + * @return _a << _b + * + * This function will shift _a with _b bits to the left. + * It will insert zeroes on the right. + * It asserts 0 <= _b <= MAX_SHIFT_1W. + * The operation count for this function assumes that + * the shift amount is a cloned scalar input. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_lsl( + const tvector1w _a, + const tvector1w _b); + +/** @brief logical shift right + * + * @param[in] _a input + * @param[in] _b shift amount + * + * @return _a >> _b + * + * This function will shift _a with _b bits to the right. + * It will insert zeroes on the left. + * It asserts 0 <= _b <= MAX_SHIFT_1W. + * The operation count for this function assumes that + * the shift amount is a cloned scalar input. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_lsr( + const tvector1w _a, + const tvector1w _b); + +#ifdef ISP2401 +/** @brief bidirectional saturating arithmetic shift + * + * @param[in] _a input + * @param[in] _b shift amount + * + * @return _a << |_b| if _b is positive + * _a >> |_b| if _b is negative + * + * If _b > 0, this function will shift _a with _b bits to the left, + * saturating at MIN_RANGE/MAX_RANGE in case of overflow. + * if _b < 0, this function will shift _a with _b bits to the right. + * It asserts -MAX_SHIFT_1W <= _b <= MAX_SHIFT_1W. + * If _b = 0, it returns _a. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_ashift_sat( + const tvector1w _a, + const tvector1w _b); + +/** @brief bidirectional non-saturating arithmetic shift + * + * @param[in] _a input + * @param[in] _b shift amount + * + * @return _a << |_b| if _b is positive + * _a >> |_b| if _b is negative + * + * If _b > 0, this function will shift _a with _b bits to the left, + * no saturation is performed in case of overflow. + * if _b < 0, this function will shift _a with _b bits to the right. + * It asserts -MAX_SHIFT_1W <= _b <= MAX_SHIFT_1W. + * If _b = 0, it returns _a. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_ashift( + const tvector1w _a, + const tvector1w _b); + + +/** @brief bidirectional logical shift + * + * @param[in] _a input + * @param[in] _b shift amount + * + * @return _a << |_b| if _b is positive + * _a >> |_b| if _b is negative + * + * This function will shift _a with _b bits to the left if _b is positive. + * This function will shift _a with _b bits to the right if _b is negative. + * It asserts -MAX_SHIFT_1W <= _b <= MAX_SHIFT_1W. + * It inserts zeros on the left or right depending on the shift direction: + * right or left. + * The operation count for this function assumes that + * the shift amount is a cloned scalar input. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_lshift( + const tvector1w _a, + const tvector1w _b); + +#endif +/* Cast */ + +/** @brief Cast from int to 1w + * + * @param[in] _a input + * + * @return _a + * + * This function casts the input from integer type to + * single precision. It asserts there is no overflow. + * + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_int_cast_to_1w( + const int _a); + +/** @brief Cast from 1w to int + * + * @param[in] _a input + * + * @return _a + * + * This function casts the input from single precision type to + * integer, preserving value and sign. + * + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H int OP_1w_cast_to_int( + const tvector1w _a); + +/** @brief Cast from 1w to 2w + * + * @param[in] _a input + * + * @return _a + * + * This function casts the input from single precision type to + * double precision, preserving value and sign. + * + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector2w OP_1w_cast_to_2w( + const tvector1w _a); + +/** @brief Cast from 2w to 1w + * + * @param[in] _a input + * + * @return _a + * + * This function casts the input from double precision type to + * single precision. In case of overflow it will wrap around. + * + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_2w_cast_to_1w( + const tvector2w _a); + + +/** @brief Cast from 2w to 1w with saturation + * + * @param[in] _a input + * + * @return _a + * + * This function casts the input from double precision type to + * single precision after saturating it to the range of single + * precision. + * + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_2w_sat_cast_to_1w( + const tvector2w _a); + +/* clipping */ + +/** @brief Clip asymmetrical + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return _a clipped between ~_b and b + * + * This function will clip the first argument between + * (-_b - 1) and _b. + * It asserts _b >= 0. + * + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_clip_asym( + const tvector1w _a, + const tvector1w _b); + +/** @brief Clip zero + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return _a clipped beteween 0 and _b + * + * This function will clip the first argument between + * zero and _b. + * It asserts _b >= 0. + * + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_clipz( + const tvector1w _a, + const tvector1w _b); + +/* division */ + +/** @brief Truncated division + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return trunc( _a / _b ) + * + * This function will divide the first argument by + * the second argument, with rounding toward 0. + * If _b == 0 and _a < 0, the function will return MIN_RANGE. + * If _b == 0 and _a == 0, the function will return 0. + * If _b == 0 and _a > 0, the function will return MAX_RANGE. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_div( + const tvector1w _a, + const tvector1w _b); + +/** @brief Fractional saturating divide + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return _a / _b + * + * This function will perform fixed point division of + * the first argument by the second argument, with rounding toward 0. + * In case of overflow it will saturate. + * If _b == 0 and _a < 0, the function will return MIN_RANGE. + * If _b == 0 and _a == 0, the function will return 0. + * If _b == 0 and _a > 0, the function will return MAX_RANGE. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_qdiv( + const tvector1w _a, + const tvector1w _b); + +/** @brief Modulo + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return _a % _b + * + * This function will return the remainder r = _a - _b * trunc( _a / _b ), + * Note that the sign of the remainder is always equal to the sign of _a. + * If _b == 0 the function will return _a. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_mod( + const tvector1w _a, + const tvector1w _b); + +/** @brief Unsigned integer Square root + * + * @param[in] _a input + * + * @return Integer square root of _a + * + * This function will calculate the Integer square root of _a + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w_unsigned OP_1w_sqrt_u( + const tvector1w_unsigned _a); + +/* Miscellaneous */ + +/** @brief Multiplexer + * + * @param[in] _a first argument + * @param[in] _b second argument + * @param[in] _c condition + * + * @return _c ? _a : _b + * + * This function will return _a if the condition _c + * is true and _b otherwise. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_mux( + const tvector1w _a, + const tvector1w _b, + const tflags _c); + +/** @brief Average without rounding + * + * @param[in] _a first operand + * @param[in] _b second operand + * + * @return (_a + _b) >> 1 + * + * This function will add _a and _b, and right shift + * the result by one without rounding. No overflow + * will occur because addition is performed in the + * proper precision. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_avg( + const tvector1w _a, + const tvector1w _b); + +/** @brief Average with rounding + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return (_a + _b) >> 1 + * + * This function will add _a and _b at full precision, + * and right shift with rounding the result with 1 bit. + * Depending on the rounding mode of the core + * it will round to nearest or to nearest even. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_avgrnd( + const tvector1w _a, + const tvector1w _b); + +/** @brief Minimum + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return (_a < _b) ? _a : _b; + * + * This function will return the smallest of both + * input arguments. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_min( + const tvector1w _a, + const tvector1w _b); + +/** @brief Maximum + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return (_a > _b) ? _a : _b; + * + * This function will return the largest of both + * input arguments. + */ +STORAGE_CLASS_ISP_OP1W_FUNC_H tvector1w OP_1w_max( + const tvector1w _a, + const tvector1w _b); + +#ifndef INLINE_ISP_OP1W +#define STORAGE_CLASS_ISP_OP1W_FUNC_C +#define STORAGE_CLASS_ISP_OP1W_DATA_C const +#else /* INLINE_ISP_OP1W */ +#define STORAGE_CLASS_ISP_OP1W_FUNC_C STORAGE_CLASS_ISP_OP1W_FUNC_H +#define STORAGE_CLASS_ISP_OP1W_DATA_C STORAGE_CLASS_ISP_OP1W_DATA_H +#include "isp_op1w.c" +#define ISP_OP1W_INLINED +#endif /* INLINE_ISP_OP1W */ + +#endif /* __ISP_OP1W_H_INCLUDED__ */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_op1w_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_op1w_types.h new file mode 100644 index 0000000000000000000000000000000000000000..c81e587509a1ef9444af9b4dfa7f2fbb21fba989 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_op1w_types.h @@ -0,0 +1,54 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISP_OP1W_TYPES_H_INCLUDED__ +#define __ISP_OP1W_TYPES_H_INCLUDED__ + +/* + * This file is part of the Multi-precision vector operations exstension package. + */ + +/* + * Single-precision vector operations + */ + +/* + * Prerequisites: + * + */ + +#include "mpmath.h" + +/* + * Single-precision data type specification + */ + + +typedef mpsdata_t tvector1w; +typedef mpsdata_t tscalar1w; +typedef spsdata_t tflags; +typedef mpudata_t tvector1w_unsigned; +typedef mpsdata_t tscalar1w_weight; +typedef mpsdata_t tvector1w_signed_positive; +typedef mpsdata_t tvector1w_weight; +#ifdef ISP2401 +typedef bool tscalar_bool; +#endif + +typedef struct { + tvector1w d; + tflags f; +} tvector1w_tflags1w; + +#endif /* __ISP_OP1W_TYPES_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_op2w.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_op2w.h new file mode 100644 index 0000000000000000000000000000000000000000..1cfe6d71728356dbe121161ab5b2d4634f5aaf82 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_op2w.h @@ -0,0 +1,675 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISP_OP2W_H_INCLUDED__ +#define __ISP_OP2W_H_INCLUDED__ + +/* + * This file is part of the Multi-precision vector operations exstension package. + */ + +/* + * Double-precision vector operations + */ + +/* + * Prerequisites: + * + */ +#include "storage_class.h" + +#ifdef INLINE_ISP_OP2W +#define STORAGE_CLASS_ISP_OP2W_FUNC_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_ISP_OP2W_DATA_H STORAGE_CLASS_INLINE_DATA +#else /* INLINE_ISP_OP2W */ +#define STORAGE_CLASS_ISP_OP2W_FUNC_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_ISP_OP2W_DATA_H STORAGE_CLASS_EXTERN_DATA +#endif /* INLINE_ISP_OP2W */ + +/* + * Double-precision data type specification + */ + +#include "isp_op2w_types.h" + +/* + * Double-precision prototype specification + */ + +/* Arithmetic */ + +/** @brief bitwise AND + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return bitwise and of both input arguments + * + * This function will calculate the bitwise and. + * result = _a & _b + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_and( + const tvector2w _a, + const tvector2w _b); + +/** @brief bitwise OR + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return bitwise or of both input arguments + * + * This function will calculate the bitwise or. + * result = _a | _b + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_or( + const tvector2w _a, + const tvector2w _b); + +/** @brief bitwise XOR + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return bitwise xor of both input arguments + * + * This function will calculate the bitwise xor. + * result = _a ^ _b + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_xor( + const tvector2w _a, + const tvector2w _b); + +/** @brief bitwise inverse + * + * @param[in] _a first argument + * + * @return bitwise inverse of both input arguments + * + * This function will calculate the bitwise inverse. + * result = ~_a + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_inv( + const tvector2w _a); + +/* Additive */ + +/** @brief addition + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return sum of both input arguments + * + * This function will calculate the sum of the input arguments. + * in case of overflow it will wrap around. + * result = _a + _b + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_add( + const tvector2w _a, + const tvector2w _b); + +/** @brief subtraction + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return _b subtracted from _a. + * + * This function will subtract _b from _a. + * in case of overflow it will wrap around. + * result = _a - _b + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_sub( + const tvector2w _a, + const tvector2w _b); + +/** @brief saturated addition + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return saturated sum of both input arguments + * + * This function will calculate the sum of the input arguments. + * in case of overflow it will saturate + * result = CLIP(_a + _b, MIN_RANGE, MAX_RANGE); + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_addsat( + const tvector2w _a, + const tvector2w _b); + +/** @brief saturated subtraction + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return saturated subtraction of both input arguments + * + * This function will subtract _b from _a. + * in case of overflow it will saturate + * result = CLIP(_a - _b, MIN_RANGE, MAX_RANGE); + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_subsat( + const tvector2w _a, + const tvector2w _b); + +/** @brief subtraction with shift right and rounding + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return (a - b) >> 1 + * + * This function subtracts _b from _a and right shifts + * the result by 1 bit with rounding. + * No overflow can occur. + * result = (_a - _b) >> 1 + * + * Note: This function will be deprecated due to + * the naming confusion and it will be replaced + * by "OP_2w_subhalfrnd". + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_subasr1( + const tvector2w _a, + const tvector2w _b); + +/** @brief Subtraction with shift right and rounding + * + * @param[in] _a first operand + * @param[in] _b second operand + * + * @return (_a - _b) >> 1 + * + * This function subtracts _b from _a and right shifts + * the result by 1 bit with rounding. + * No overflow can occur. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_subhalfrnd( + const tvector2w _a, + const tvector2w _b); + +/** @brief Subtraction with shift right and no rounding + * + * @param[in] _a first operand + * @param[in] _b second operand + * + * @return (_a - _b) >> 1 + * + * This function subtracts _b from _a and right shifts + * the result by 1 bit without rounding (i.e. truncation). + * No overflow can occur. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_subhalf( + const tvector2w _a, + const tvector2w _b); + +/** @brief saturated absolute value + * + * @param[in] _a input + * + * @return saturated absolute value of the input + * + * This function will calculate the saturated absolute value of the input. + * In case of overflow it will saturate. + * if (_a > 0) return _a;
+ * else return CLIP(-_a, MIN_RANGE, MAX_RANGE);
+ */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_abs( + const tvector2w _a); + +/** @brief saturated absolute difference + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return sat(abs(sat(a-b))); + * + * This function will calculate the saturated absolute value + * of the saturated difference of both inputs. + * result = sat(abs(sat(_a - _b))); + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_subabssat( + const tvector2w _a, + const tvector2w _b); + +/* Multiplicative */ + +/** @brief integer multiply + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return product of _a and _b + * + * This function will calculate the product + * of the input arguments and returns the LSB + * aligned double precision result. + * In case of overflow it will wrap around. + * result = _a * _b; + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_mul( + const tvector2w _a, + const tvector2w _b); + +/** @brief fractional saturating multiply + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return saturated product of _a and _b + * + * This function will calculate the fixed point + * product of the input arguments + * and returns a double precision result. + * In case of overflow it will saturate. + * result =((_a * _b) << 1) >> (2*NUM_BITS); + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_qmul( + const tvector2w _a, + const tvector2w _b); + +/** @brief fractional saturating multiply with rounding + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return product of _a and _b + * + * This function will calculate the fixed point + * product of the input arguments + * and returns a double precision result. + * Depending on the rounding mode of the core + * it will round to nearest or to nearest even. + * In case of overflow it will saturate. + * result = ((_a * _b) << 1) >> (2*NUM_BITS); + */ + +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_qrmul( + const tvector2w _a, + const tvector2w _b); + +/* Comparative */ + +/** @brief equal + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return _a == _b + * + * This function will return true if both inputs + * are equal, and false if not equal. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tflags OP_2w_eq( + const tvector2w _a, + const tvector2w _b); + +/** @brief not equal + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return _a != _b + * + * This function will return false if both inputs + * are equal, and true if not equal. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tflags OP_2w_ne( + const tvector2w _a, + const tvector2w _b); + +/** @brief less or equal + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return _a <= _b + * + * This function will return true if _a is smaller + * or equal than _b. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tflags OP_2w_le( + const tvector2w _a, + const tvector2w _b); + +/** @brief less then + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return _a < _b + * + * This function will return true if _a is smaller + * than _b. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tflags OP_2w_lt( + const tvector2w _a, + const tvector2w _b); + +/** @brief greater or equal + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return _a >= _b + * + * This function will return true if _a is greater + * or equal than _b. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tflags OP_2w_ge( + const tvector2w _a, + const tvector2w _b); + +/** @brief greater than + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return _a > _b + * + * This function will return true if _a is greater + * than _b. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tflags OP_2w_gt( + const tvector2w _a, + const tvector2w _b); + +/* Shift */ + +/** @brief aritmetic shift right + * + * @param[in] _a input + * @param[in] _b shift amount + * + * @return _a >> _b + * + * This function will shift _a with _b bits to the right, + * preserving the sign bit. + * It asserts 0 <= _b <= MAX_SHIFT_2W. + * The operation count for this function assumes that + * the shift amount is a cloned scalar input. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_asr( + const tvector2w _a, + const tvector2w _b); + +/** @brief aritmetic shift right with rounding + * + * @param[in] _a input + * @param[in] _b shift amount + * + * @return _a >> _b + * + * If _b < 2*NUM_BITS, this function will shift _a with _b bits to the right, + * preserving the sign bit, and depending on the rounding mode of the core + * it will round to nearest or to nearest even. + * If _b >= 2*NUM_BITS, this function will return 0. + * It asserts 0 <= _b <= MAX_SHIFT_2W. + * The operation count for this function assumes that + * the shift amount is a cloned scalar input. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_asrrnd( + const tvector2w _a, + const tvector2w _b); + +/** @brief saturating aritmetic shift left + * + * @param[in] _a input + * @param[in] _b shift amount + * + * @return _a << _b + * + * If _b < MAX_BITDEPTH, this function will shift _a with _b bits to the left, + * saturating at MIN_RANGE/MAX_RANGE in case of overflow. + * If _b >= MAX_BITDEPTH, this function will return MIN_RANGE if _a < 0, + * MAX_RANGE if _a > 0, 0 if _a == 0. + * (with MAX_BITDEPTH=64) + * It asserts 0 <= _b <= MAX_SHIFT_2W. + * The operation count for this function assumes that + * the shift amount is a cloned scalar input. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_asl( + const tvector2w _a, + const tvector2w _b); + +/** @brief saturating aritmetic shift left + * + * @param[in] _a input + * @param[in] _b shift amount + * + * @return _a << _b + * + * This function is identical to OP_2w_asl( ) + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_aslsat( + const tvector2w _a, + const tvector2w _b); + +/** @brief logical shift left + * + * @param[in] _a input + * @param[in] _b shift amount + * + * @return _a << _b + * + * This function will shift _a with _b bits to the left. + * It will insert zeroes on the right. + * It asserts 0 <= _b <= MAX_SHIFT_2W. + * The operation count for this function assumes that + * the shift amount is a cloned scalar input. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_lsl( + const tvector2w _a, + const tvector2w _b); + +/** @brief logical shift right + * + * @param[in] _a input + * @param[in] _b shift amount + * + * @return _a >> _b + * + * This function will shift _a with _b bits to the right. + * It will insert zeroes on the left. + * It asserts 0 <= _b <= MAX_SHIFT_2W. + * The operation count for this function assumes that + * the shift amount is a cloned scalar input. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_lsr( + const tvector2w _a, + const tvector2w _b); + +/* clipping */ + +/** @brief Clip asymmetrical + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return _a clipped between ~_b and b + * + * This function will clip the first argument between + * (-_b - 1) and _b. + * It asserts _b >= 0. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_clip_asym( + const tvector2w _a, + const tvector2w _b); + +/** @brief Clip zero + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return _a clipped beteween 0 and _b + * + * This function will clip the first argument between + * zero and _b. + * It asserts _b >= 0. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_clipz( + const tvector2w _a, + const tvector2w _b); + +/* division */ + +/** @brief Truncated division + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return trunc( _a / _b ) + * + * This function will divide the first argument by + * the second argument, with rounding toward 0. + * If _b == 0 and _a < 0, the function will return MIN_RANGE. + * If _b == 0 and _a == 0, the function will return 0. + * If _b == 0 and _a > 0, the function will return MAX_RANGE. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_div( + const tvector2w _a, + const tvector2w _b); + +/** @brief Saturating truncated division + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return CLIP( trunc( _a / _b ), MIN_RANGE1w, MAX_RANGE1w ) + * + * This function will divide the first argument by + * the second argument, with rounding toward 0, and + * saturate the result to the range of single precision. + * If _b == 0 and _a < 0, the function will return MIN_RANGE. + * If _b == 0 and _a == 0, the function will return 0. + * If _b == 0 and _a > 0, the function will return MAX_RANGE. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector1w OP_2w_divh( + const tvector2w _a, + const tvector1w _b); + +/** @brief Modulo + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return n/a + * + * This function has not yet been implemented. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_mod( + const tvector2w _a, + const tvector2w _b); + +/** @brief Unsigned Integer Square root + * + * @param[in] _a input + * + * @return square root of _a + * + * This function will calculate the unsigned integer square root of _a + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector1w_unsigned OP_2w_sqrt_u( + const tvector2w_unsigned _a); + +/* Miscellaneous */ + +/** @brief Multiplexer + * + * @param[in] _a first argument + * @param[in] _b second argument + * @param[in] _c condition + * + * @return _c ? _a : _b + * + * This function will return _a if the condition _c + * is true and _b otherwise. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_mux( + const tvector2w _a, + const tvector2w _b, + const tflags _c); + +/** @brief Average without rounding + * + * @param[in] _a first operand + * @param[in] _b second operand + * + * @return (_a + _b) >> 1 + * + * This function will add _a and _b, and right shift + * the result by one without rounding. No overflow + * will occur because addition is performed in the + * proper precision. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_avg( + const tvector2w _a, + const tvector2w _b); + +/** @brief Average with rounding + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return (_a + _b) >> 1 + * + * This function will add _a and _b at full precision, + * and right shift with rounding the result with 1 bit. + * Depending on the rounding mode of the core + * it will round to nearest or to nearest even. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_avgrnd( + const tvector2w _a, + const tvector2w _b); + +/** @brief Minimum + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return (_a < _b) ? _a : _b; + * + * This function will return the smallest of both + * input arguments. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_min( + const tvector2w _a, + const tvector2w _b); + +/** @brief Maximum + * + * @param[in] _a first argument + * @param[in] _b second argument + * + * @return (_a > _b) ? _a : _b; + * + * This function will return the largest of both + * input arguments. + */ +STORAGE_CLASS_ISP_OP2W_FUNC_H tvector2w OP_2w_max( + const tvector2w _a, + const tvector2w _b); + +#ifndef INLINE_ISP_OP2W +#define STORAGE_CLASS_ISP_OP2W_FUNC_C +#define STORAGE_CLASS_ISP_OP2W_DATA_C const +#else /* INLINE_ISP_OP2W */ +#define STORAGE_CLASS_ISP_OP2W_FUNC_C STORAGE_CLASS_ISP_OP2W_FUNC_H +#define STORAGE_CLASS_ISP_OP2W_DATA_C STORAGE_CLASS_ISP_OP2W_DATA_H +#include "isp_op2w.c" +#define ISP_OP2W_INLINED +#endif /* INLINE_ISP_OP2W */ + +#endif /* __ISP_OP2W_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_op2w_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_op2w_types.h new file mode 100644 index 0000000000000000000000000000000000000000..7e86083a8a33da934df7d337750e0d756eebb3f5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_op2w_types.h @@ -0,0 +1,49 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISP_OP2W_TYPES_H_INCLUDED__ +#define __ISP_OP2W_TYPES_H_INCLUDED__ + +/* + * This file is part of the Multi-precision vector operations exstension package. + */ + +/* + * Double-precision vector operations + */ + +/* + * Prerequisites: + * + */ +#include "mpmath.h" +#include "isp_op1w_types.h" + +/* + * Single-precision data type specification + */ + + +typedef mpsdata_t tvector2w; +typedef mpsdata_t tscalar2w; +typedef mpsdata_t tvector2w_signed_positive; +typedef mpudata_t tvector2w_unsigned; + + +typedef struct { + tvector2w d; + tflags f; +} tvector2w_tflags; + +#endif /* __ISP_OP2W_TYPES_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_op_count.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_op_count.h new file mode 100644 index 0000000000000000000000000000000000000000..8e7b48d026b0c7aaeb420af11f8fa38bdfe1d033 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_op_count.h @@ -0,0 +1,226 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISP_OP_COUNT_H_INCLUDED__ +#define __ISP_OP_COUNT_H_INCLUDED__ + +#include + +typedef struct { + long long bbb_cnt; /* number of bbb */ + int bbb_op; /* operations per bbb */ + long long total_cnt; /* bbb_cnt * bbb_op */ +} bbb_stat_t; + +typedef enum { + bbb_func_OP_1w_and, + bbb_func_OP_1w_or, + bbb_func_OP_1w_xor, + bbb_func_OP_1w_inv, + bbb_func_OP_1w_add, + bbb_func_OP_1w_sub, + bbb_func_OP_1w_addsat, + bbb_func_OP_1w_subsat, + bbb_func_OP_1w_subasr1, + bbb_func_OP_1w_subhalf, + bbb_func_OP_1w_subhalfrnd, + bbb_func_OP_1w_abs, + bbb_func_OP_1w_subabssat, +#ifdef ISP2401 + bbb_func_OP_1w_subsat_u, +#endif + bbb_func_OP_1w_muld, + bbb_func_OP_1w_mul, + bbb_func_OP_1w_qmul, + bbb_func_OP_1w_qrmul, + bbb_func_OP_1w_eq, + bbb_func_OP_1w_ne, + bbb_func_OP_1w_le, + bbb_func_OP_1w_lt, + bbb_func_OP_1w_ge, + bbb_func_OP_1w_gt, + bbb_func_OP_1w_asr, + bbb_func_OP_1w_asrrnd, + bbb_func_OP_1w_asl, + bbb_func_OP_1w_aslsat, + bbb_func_OP_1w_lsl, + bbb_func_OP_1w_lsr, +#ifdef ISP2401 + bbb_func_OP_1w_ashift, + bbb_func_OP_1w_lshift, +#endif + bbb_func_OP_int_cast_to_1w , + bbb_func_OP_1w_cast_to_int , + bbb_func_OP_1w_cast_to_2w , + bbb_func_OP_2w_cast_to_1w , + bbb_func_OP_2w_sat_cast_to_1w , + bbb_func_OP_1w_clip_asym, + bbb_func_OP_1w_clipz, + bbb_func_OP_1w_div, + bbb_func_OP_1w_qdiv, + bbb_func_OP_1w_mod, + bbb_func_OP_1w_sqrt_u, + bbb_func_OP_1w_mux, + bbb_func_OP_1w_avg, + bbb_func_OP_1w_avgrnd, + bbb_func_OP_1w_min, + bbb_func_OP_1w_max, + bbb_func_OP_2w_and, + bbb_func_OP_2w_or, + bbb_func_OP_2w_xor, + bbb_func_OP_2w_inv, + bbb_func_OP_2w_add, + bbb_func_OP_2w_sub, + bbb_func_OP_2w_addsat, + bbb_func_OP_2w_subsat, + bbb_func_OP_2w_subasr1, + bbb_func_OP_2w_subhalf, + bbb_func_OP_2w_subhalfrnd, + bbb_func_OP_2w_abs, + bbb_func_OP_2w_subabssat, + bbb_func_OP_2w_mul, + bbb_func_OP_2w_qmul, + bbb_func_OP_2w_qrmul, + bbb_func_OP_2w_eq, + bbb_func_OP_2w_ne, + bbb_func_OP_2w_le, + bbb_func_OP_2w_lt, + bbb_func_OP_2w_ge, + bbb_func_OP_2w_gt, + bbb_func_OP_2w_asr, + bbb_func_OP_2w_asrrnd, + bbb_func_OP_2w_asl, + bbb_func_OP_2w_aslsat, + bbb_func_OP_2w_lsl, + bbb_func_OP_2w_lsr, + bbb_func_OP_2w_clip_asym, + bbb_func_OP_2w_clipz, + bbb_func_OP_2w_div, + bbb_func_OP_2w_divh, + bbb_func_OP_2w_mod, + bbb_func_OP_2w_sqrt_u, + bbb_func_OP_2w_mux, + bbb_func_OP_2w_avg, + bbb_func_OP_2w_avgrnd, + bbb_func_OP_2w_min, + bbb_func_OP_2w_max, + bbb_func_OP_1w_mul_realigning, +#ifdef ISP2401 + bbb_func_OP_1w_imax32, + bbb_func_OP_1w_imaxidx32, + bbb_func_OP_1w_cond_add, +#endif + + bbb_func_num_functions +} bbb_functions_t; + +typedef enum { + core_func_OP_and, + core_func_OP_or, + core_func_OP_xor, + core_func_OP_inv, + core_func_OP_add, + core_func_OP_sub, + core_func_OP_addsat, + core_func_OP_subsat, + core_func_OP_subasr1, + core_func_OP_abs, + core_func_OP_subabssat, +#ifdef ISP2401 + core_func_OP_subsat_u, +#endif + core_func_OP_muld, + core_func_OP_mul, + core_func_OP_qrmul, + core_func_OP_eq, + core_func_OP_ne, + core_func_OP_le, + core_func_OP_lt, + core_func_OP_ge, + core_func_OP_gt, + core_func_OP_asr, + core_func_OP_asl, + core_func_OP_asrrnd, + core_func_OP_lsl, + core_func_OP_lslsat, + core_func_OP_lsr, + core_func_OP_lsrrnd, + core_func_OP_clip_asym, + core_func_OP_clipz, + core_func_OP_div, + core_func_OP_mod, + core_func_OP_sqrt, + core_func_OP_mux, + core_func_OP_avgrnd, + core_func_OP_min, + core_func_OP_max, + + core_func_num_functions + +} core_functions_t; + +/* inc_bbb_count() can be used for building blocks that are implemented with one operation + inc_bbb_count_ext() will be used in case the operation count is not known or greater than one. + + For some operations there is a difference in operation count for the cloned version and the + not cloned version. this difference is not vissible on the reference code side. + We could add a min and max operation count for those operations, and keep track of those counts + separately. That way in the report the impact can be seen. */ + +#ifdef DISABLE_OPCNT +#define inc_bbb_count(func) +#define inc_bbb_count_ext(func, cnt) +#define enable_bbb_count() +#define disable_bbb_count() +#else +#define inc_bbb_count(func) _inc_bbb_count(func) +#define inc_bbb_count_ext(func, cnt) _inc_bbb_count_ext(func, cnt) +#define enable_bbb_count() _enable_bbb_count() +#define disable_bbb_count() _disable_bbb_count() +#endif + +void +inc_core_count_n( + core_functions_t func, + unsigned n); + +void +_enable_bbb_count(void); + +void +_disable_bbb_count(void); + +void +_inc_bbb_count( + bbb_functions_t func); + +void +_inc_bbb_count_ext( + bbb_functions_t func, + int op_count); + +void +bbb_func_reset_count(void); + +void +bbb_func_print_totals( + FILE * fp, + unsigned non_zero_only); + +void +core_func_print_totals( + FILE* fp, + unsigned non_zero_only); + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_public.h new file mode 100644 index 0000000000000000000000000000000000000000..808ec050efc0f095e1d27933fd7116f367e3af24 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/isp_public.h @@ -0,0 +1,186 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISP_PUBLIC_H_INCLUDED__ +#define __ISP_PUBLIC_H_INCLUDED__ + +#include +#include "system_types.h" + +/*! Enable or disable the program complete irq signal of ISP[ID] + + \param ID[in] SP identifier + \param cnd[in] predicate + + \return none, if(cnd) enable(ISP[ID].irq) else disable(ISP[ID].irq) + */ +extern void cnd_isp_irq_enable( + const isp_ID_t ID, + const bool cnd); + +/*! Read the state of cell ISP[ID] + + \param ID[in] ISP identifier + \param state[out] isp state structure + \param stall[out] isp stall conditions + + \return none, state = ISP[ID].state, stall = ISP[ID].stall + */ +extern void isp_get_state( + const isp_ID_t ID, + isp_state_t *state, + isp_stall_t *stall); + + +/*! Write to the status and control register of ISP[ID] + + \param ID[in] ISP identifier + \param reg[in] register index + \param value[in] The data to be written + + \return none, ISP[ID].sc[reg] = value + */ +STORAGE_CLASS_ISP_H void isp_ctrl_store( + const isp_ID_t ID, + const unsigned int reg, + const hrt_data value); + +/*! Read from the status and control register of ISP[ID] + + \param ID[in] ISP identifier + \param reg[in] register index + \param value[in] The data to be written + + \return ISP[ID].sc[reg] + */ +STORAGE_CLASS_ISP_H hrt_data isp_ctrl_load( + const isp_ID_t ID, + const unsigned int reg); + +/*! Get the status of a bitfield in the control register of ISP[ID] + + \param ID[in] ISP identifier + \param reg[in] register index + \param bit[in] The bit index to be checked + + \return (ISP[ID].sc[reg] & (1<>shift + * + * This function will multiply a with b, followed by a right + * shift with rounding. the result is saturated and casted + * to single precision. + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_mul_realigning( + tvector1w a, + tvector1w b, + tscalar1w shift ); + +/** @brief Leading bit index + * + * @param[in] a input + * + * @return index of the leading bit of each element + * + * This function finds the index of leading one (set) bit of the + * input. The index starts with 0 for the LSB and can go upto + * ISP_VEC_ELEMBITS-1 for the MSB. For an input equal to zero, + * the returned index is -1. + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_lod( + tvector1w a); + +/** @brief Config Unit Input Processing + * + * @param[in] a input + * @param[in] input_scale input scaling factor + * @param[in] input_offset input offset factor + * + * @return scaled & offset added input clamped to MAXVALUE + * + * As part of input processing for piecewise linear estimation config unit, + * this function will perform scaling followed by adding offset and + * then clamping to the MAX InputValue + * It asserts -MAX_SHIFT_1W <= input_scale <= MAX_SHIFT_1W, and + * -MAX_SHIFT_1W <= input_offset <= MAX_SHIFT_1W + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_input_scaling_offset_clamping( + tvector1w a, + tscalar1w_5bit_signed input_scale, + tscalar1w_5bit_signed input_offset); + +/** @brief Config Unit Output Processing + * + * @param[in] a output + * @param[in] output_scale output scaling factor + * + * @return scaled & clamped output value + * + * As part of output processing for piecewise linear estimation config unit, + * This function will perform scaling and then clamping to output + * MAX value. + * It asserts -MAX_SHIFT_1W <= output_scale <= MAX_SHIFT_1W + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_output_scaling_clamping( + tvector1w a, + tscalar1w_5bit_signed output_scale); + +/** @brief Config Unit Piecewiselinear estimation + * + * @param[in] a input + * @param[in] config_points config parameter structure + * + * @return piecewise linear estimated output + * + * Given a set of N points {(x1,y1),()x2,y2), ....,(xn,yn)}, to find + * the functional value at an arbitrary point around the input set, + * this function will perform input processing followed by piecewise + * linear estimation and then output processing to yield the final value. + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_piecewise_estimation( + tvector1w a, + ref_config_points config_points); + +/** @brief Fast Config Unit + * + * @param[in] x input + * @param[in] init_vectors LUT data structure + * + * @return piecewise linear estimated output + * This block gets an input x and a set of input configuration points stored in a look-up + * table of 32 elements. First, the x input is clipped to be within the range [x1, xn+1]. + * Then, it computes the interval in which the input lies. Finally, the output is computed + * by performing linear interpolation based on the interval properties (i.e. x_prev, slope, + * and offset). This block assumes that the points are equally spaced and that the interval + * size is a power of 2. + **/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_XCU( + tvector1w x, + xcu_ref_init_vectors init_vectors); + + +/** @brief LXCU + * + * @param[in] x input + * @param[in] init_vectors LUT data structure + * + * @return logarithmic piecewise linear estimated output. + * This block gets an input x and a set of input configuration points stored in a look-up + * table of 32 elements. It computes the interval in which the input lies. + * Then output is computed by performing linear interpolation based on the interval + * properties (i.e. x_prev, slope, * and offset). + * This BBB assumes spacing x-coordinates of "init vectors" increase exponentially as + * shown below. + * interval size : 2^0 2^1 2^2 2^3 + * x-coordinates: x0<--->x1<---->x2<---->x3<----> + **/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_LXCU( + tvector1w x, + xcu_ref_init_vectors init_vectors); + +/** @brief Coring + * + * @param[in] coring_vec Amount of coring based on brightness level + * @param[in] filt_input Vector of input pixels on which Coring is applied + * @param[in] m_CnrCoring0 Coring Level0 + * + * @return vector of filtered pixels after coring is applied + * + * This function will perform adaptive coring based on brightness level to + * remove noise + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w coring( + tvector1w coring_vec, + tvector1w filt_input, + tscalar1w m_CnrCoring0 ); + +/** @brief Normalised FIR with coefficients [3,4,1] + * + * @param[in] m 1x3 matrix with pixels + * + * @return filtered output + * + * This function will calculate the + * Normalised FIR with coefficients [3,4,1], + *-5dB at Fs/2, -90 degree phase shift (quarter pixel) + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_5dB_m90_nrm ( + const s_1w_1x3_matrix m); + +/** @brief Normalised FIR with coefficients [1,4,3] + * + * @param[in] m 1x3 matrix with pixels + * + * @return filtered output + * + * This function will calculate the + * Normalised FIR with coefficients [1,4,3], + *-5dB at Fs/2, +90 degree phase shift (quarter pixel) + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_5dB_p90_nrm ( + const s_1w_1x3_matrix m); + +/** @brief Normalised FIR with coefficients [1,2,1] + * + * @param[in] m 1x3 matrix with pixels + * + * @return filtered output + * + * This function will calculate the + * Normalised FIR with coefficients [1,2,1], -6dB at Fs/2 + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_6dB_nrm ( + const s_1w_1x3_matrix m); + +/** @brief Normalised FIR with coefficients [13,16,3] + * + * @param[in] m 1x3 matrix with pixels + * + * @return filtered output + * + * This function will calculate the + * Normalised FIR with coefficients [13,16,3], + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_6dB_nrm_ph0 ( + const s_1w_1x3_matrix m); + +/** @brief Normalised FIR with coefficients [9,16,7] + * + * @param[in] m 1x3 matrix with pixels + * + * @return filtered output + * + * This function will calculate the + * Normalised FIR with coefficients [9,16,7], + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_6dB_nrm_ph1 ( + const s_1w_1x3_matrix m); + +/** @brief Normalised FIR with coefficients [5,16,11] + * + * @param[in] m 1x3 matrix with pixels + * + * @return filtered output + * + * This function will calculate the + * Normalised FIR with coefficients [5,16,11], + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_6dB_nrm_ph2 ( + const s_1w_1x3_matrix m); + +/** @brief Normalised FIR with coefficients [1,16,15] + * + * @param[in] m 1x3 matrix with pixels + * + * @return filtered output + * + * This function will calculate the + * Normalised FIR with coefficients [1,16,15], + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_6dB_nrm_ph3 ( + const s_1w_1x3_matrix m); + +/** @brief Normalised FIR with programable phase shift + * + * @param[in] m 1x3 matrix with pixels + * @param[in] coeff phase shift + * + * @return filtered output + * + * This function will calculate the + * Normalised FIR with coefficients [8-coeff,16,8+coeff], + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_6dB_nrm_calc_coeff ( + const s_1w_1x3_matrix m, tscalar1w_3bit coeff); + +/** @brief 3 tap FIR with coefficients [1,1,1] + * + * @param[in] m 1x3 matrix with pixels + * + * @return filtered output + * + * This function will calculate the + * FIR with coefficients [1,1,1], -9dB at Fs/2 normalized with factor 1/2 + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x3m_9dB_nrm ( + const s_1w_1x3_matrix m); + +#ifdef ISP2401 +/** @brief symmetric 3 tap FIR acts as LPF or BSF + * + * @param[in] m 1x3 matrix with pixels + * @param[in] k filter coefficient shift + * @param[in] bsf_flag 1 for BSF and 0 for LPF + * + * @return filtered output + * + * This function performs variable coefficient symmetric 3 tap filter which can + * be either used as Low Pass Filter or Band Stop Filter. + * Symmetric 3tap tap filter with DC gain 1 has filter coefficients [a, 1-2a, a] + * For LPF 'a' can be approximated as (1 - 2^(-k))/4, k = 0, 1, 2, ... + * and filter output can be approximated as: + * out_LPF = ((v00 + v02) - ((v00 + v02) >> k) + (2 * (v01 + (v01 >> k)))) >> 2 + * For BSF 'a' can be approximated as (1 + 2^(-k))/4, k = 0, 1, 2, ... + * and filter output can be approximated as: + * out_BSF = ((v00 + v02) + ((v00 + v02) >> k) + (2 * (v01 - (v01 >> k)))) >> 2 + * For a given filter coefficient shift 'k' and bsf_flag this function + * behaves either as LPF or BSF. + * All computation is done using 1w arithmetic and implementation does not use + * any multiplication. + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w +sym_fir1x3m_lpf_bsf(s_1w_1x3_matrix m, + tscalar1w k, + tscalar_bool bsf_flag); +#endif + +/** @brief Normalised 2D FIR with coefficients [1;2;1] * [1,2,1] + * + * @param[in] m 3x3 matrix with pixels + * + * @return filtered output + * + * This function will calculate the + * Normalised FIR with coefficients [1;2;1] * [1,2,1] + * Unity gain filter through repeated scaling and rounding + * - 6 rotate operations per output + * - 8 vector operations per output + * _______ + * 14 total operations + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir3x3m_6dB_nrm ( + const s_1w_3x3_matrix m); + +/** @brief Normalised 2D FIR with coefficients [1;1;1] * [1,1,1] + * + * @param[in] m 3x3 matrix with pixels + * + * @return filtered output + * + * This function will calculate the + * Normalised FIR with coefficients [1;1;1] * [1,1,1] + * + * (near) Unity gain filter through repeated scaling and rounding + * - 6 rotate operations per output + * - 8 vector operations per output + * _______ + * 14 operations + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir3x3m_9dB_nrm ( + const s_1w_3x3_matrix m); + +/** @brief Normalised dual output 2D FIR with coefficients [1;2;1] * [1,2,1] + * + * @param[in] m 4x3 matrix with pixels + * + * @return two filtered outputs (2x1 matrix) + * + * This function will calculate the + * Normalised FIR with coefficients [1;2;1] * [1,2,1] + * and produce two outputs (vertical) + * Unity gain filter through repeated scaling and rounding + * compute two outputs per call to re-use common intermediates + * - 4 rotate operations per output + * - 6 vector operations per output (alternative possible, but in this + * form it's not obvious to re-use variables) + * _______ + * 10 total operations + */ + STORAGE_CLASS_REF_VECTOR_FUNC_H s_1w_2x1_matrix fir3x3m_6dB_out2x1_nrm ( + const s_1w_4x3_matrix m); + +/** @brief Normalised dual output 2D FIR with coefficients [1;1;1] * [1,1,1] + * + * @param[in] m 4x3 matrix with pixels + * + * @return two filtered outputs (2x1 matrix) + * + * This function will calculate the + * Normalised FIR with coefficients [1;1;1] * [1,1,1] + * and produce two outputs (vertical) + * (near) Unity gain filter through repeated scaling and rounding + * compute two outputs per call to re-use common intermediates + * - 4 rotate operations per output + * - 7 vector operations per output (alternative possible, but in this + * form it's not obvious to re-use variables) + * _______ + * 11 total operations + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H s_1w_2x1_matrix fir3x3m_9dB_out2x1_nrm ( + const s_1w_4x3_matrix m); + +/** @brief Normalised 2D FIR 5x5 + * + * @param[in] m 5x5 matrix with pixels + * + * @return filtered output + * + * This function will calculate the + * Normalised FIR with coefficients [1;1;1] * [1;2;1] * [1,2,1] * [1,1,1] + * and produce a filtered output + * (near) Unity gain filter through repeated scaling and rounding + * - 20 rotate operations per output + * - 28 vector operations per output + * _______ + * 48 total operations +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir5x5m_15dB_nrm ( + const s_1w_5x5_matrix m); + +/** @brief Normalised FIR 1x5 + * + * @param[in] m 1x5 matrix with pixels + * + * @return filtered output + * + * This function will calculate the + * Normalised FIR with coefficients [1,2,1] * [1,1,1] = [1,4,6,4,1] + * and produce a filtered output + * (near) Unity gain filter through repeated scaling and rounding + * - 4 rotate operations per output + * - 5 vector operations per output + * _______ + * 9 total operations +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x5m_12dB_nrm ( + const s_1w_1x5_matrix m); + +/** @brief Normalised 2D FIR 5x5 + * + * @param[in] m 5x5 matrix with pixels + * + * @return filtered output + * + * This function will calculate the + * Normalised FIR with coefficients [1;2;1] * [1;2;1] * [1,2,1] * [1,2,1] + * and produce a filtered output + * (near) Unity gain filter through repeated scaling and rounding + * - 20 rotate operations per output + * - 30 vector operations per output + * _______ + * 50 total operations +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir5x5m_12dB_nrm ( + const s_1w_5x5_matrix m); + +/** @brief Approximate averaging FIR 1x5 + * + * @param[in] m 1x5 matrix with pixels + * + * @return filtered output + * + * This function will produce filtered output by + * applying the filter coefficients (1/8) * [1,1,1,1,1] + * _______ + * 5 vector operations +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x5m_box ( + s_1w_1x5_matrix m); + +/** @brief Approximate averaging FIR 1x9 + * + * @param[in] m 1x9 matrix with pixels + * + * @return filtered output + * + * This function will produce filtered output by + * applying the filter coefficients (1/16) * [1,1,1,1,1,1,1,1,1] + * _______ + * 9 vector operations +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x9m_box ( + s_1w_1x9_matrix m); + +/** @brief Approximate averaging FIR 1x11 + * + * @param[in] m 1x11 matrix with pixels + * + * @return filtered output + * + * This function will produce filtered output by + * applying the filter coefficients (1/16) * [1,1,1,1,1,1,1,1,1,1,1] + * _______ + * 12 vector operations +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w fir1x11m_box ( + s_1w_1x11_matrix m); + +/** @brief Symmetric 7 tap filter with normalization + * + * @param[in] in 1x7 matrix with pixels + * @param[in] coeff 1x4 matrix with coefficients + * @param[in] out_shift output pixel shift value for normalization + * + * @return symmetric 7 tap filter output + * + * This function performs symmetric 7 tap filter over input pixels. + * Filter sum is normalized by shifting out_shift bits. + * Filter sum: p0*c3 + p1*c2 + p2*c1 + p3*c0 + p4*c1 + p5*c2 + p6*c3 + * is implemented as: (p0 + p6)*c3 + (p1 + p5)*c2 + (p2 + p4)*c1 + p3*c0 to + * reduce multiplication. + * Input pixels should to be scaled, otherwise overflow is possible during + * addition +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w +fir1x7m_sym_nrm(s_1w_1x7_matrix in, + s_1w_1x4_matrix coeff, + tvector1w out_shift); + +/** @brief Symmetric 7 tap filter with normalization at input side + * + * @param[in] in 1x7 matrix with pixels + * @param[in] coeff 1x4 matrix with coefficients + * + * @return symmetric 7 tap filter output + * + * This function performs symmetric 7 tap filter over input pixels. + * Filter sum: p0*c3 + p1*c2 + p2*c1 + p3*c0 + p4*c1 + p5*c2 + p6*c3 + * = (p0 + p6)*c3 + (p1 + p5)*c2 + (p2 + p4)*c1 + p3*c0 + * Input pixels and coefficients are in Qn format, where n = + * ISP_VEC_ELEMBITS - 1 (ie Q15 for Broxton) + * To avoid double precision arithmetic input pixel sum and final sum is + * implemented using avgrnd and coefficient multiplication using qrmul. + * Final result is in Qm format where m = ISP_VEC_ELEMBITS - 2 (ie Q14 for + * Broxton) +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w +fir1x7m_sym_innrm_approx(s_1w_1x7_matrix in, + s_1w_1x4_matrix coeff); + +/** @brief Symmetric 7 tap filter with normalization at output side + * + * @param[in] in 1x7 matrix with pixels + * @param[in] coeff 1x4 matrix with coefficients + * + * @return symmetric 7 tap filter output + * + * This function performs symmetric 7 tap filter over input pixels. + * Filter sum: p0*c3 + p1*c2 + p2*c1 + p3*c0 + p4*c1 + p5*c2 + p6*c3 + * = (p0 + p6)*c3 + (p1 + p5)*c2 + (p2 + p4)*c1 + p3*c0 + * Input pixels are in Qn and coefficients are in Qm format, where n = + * ISP_VEC_ELEMBITS - 2 and m = ISP_VEC_ELEMBITS - 1 (ie Q14 and Q15 + * respectively for Broxton) + * To avoid double precision arithmetic input pixel sum and final sum is + * implemented using addsat and coefficient multiplication using qrmul. + * Final sum is left shifted by 2 and saturated to produce result is Qm format + * (ie Q15 for Broxton) +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w +fir1x7m_sym_outnrm_approx(s_1w_1x7_matrix in, + s_1w_1x4_matrix coeff); + +/** @brief 4 tap filter with normalization + * + * @param[in] in 1x4 matrix with pixels + * @param[in] coeff 1x4 matrix with coefficients + * @param[in] out_shift output pixel shift value for normalization + * + * @return 4 tap filter output + * + * This function performs 4 tap filter over input pixels. + * Filter sum is normalized by shifting out_shift bits. + * Filter sum: p0*c0 + p1*c1 + p2*c2 + p3*c3 +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w +fir1x4m_nrm(s_1w_1x4_matrix in, + s_1w_1x4_matrix coeff, + tvector1w out_shift); + +/** @brief 4 tap filter with normalization for half pixel interpolation + * + * @param[in] in 1x4 matrix with pixels + * + * @return 4 tap filter output with filter tap [-1 9 9 -1]/16 + * + * This function performs 4 tap filter over input pixels. + * Filter sum: -p0 + 9*p1 + 9*p2 - p3 + * This filter implementation is completely free from multiplication and double + * precision arithmetic. + * Typical usage of this filter is to half pixel interpolation of Bezier + * surface + * */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w +fir1x4m_bicubic_bezier_half(s_1w_1x4_matrix in); + +/** @brief 4 tap filter with normalization for quarter pixel interpolation + * + * @param[in] in 1x4 matrix with pixels + * @param[in] coeff 1x4 matrix with coefficients + * + * @return 4 tap filter output + * + * This function performs 4 tap filter over input pixels. + * Filter sum: p0*c0 + p1*c1 + p2*c2 + p3*c3 + * To avoid double precision arithmetic we implemented multiplication using + * qrmul and addition using avgrnd. Coefficients( c0 to c3) formats are assumed + * to be: Qm, Qn, Qo, Qm, where m = n + 2 and o = n + 1. + * Typical usage of this filter is to quarter pixel interpolation of Bezier + * surface with filter coefficients:[-9 111 29 -3]/128. For which coefficient + * values should be: [-9216/2^17 28416/2^15 1484/2^16 -3072/2^17] for + * ISP_VEC_ELEMBITS = 16. +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w +fir1x4m_bicubic_bezier_quarter(s_1w_1x4_matrix in, + s_1w_1x4_matrix coeff); + + +/** @brief Symmetric 3 tap filter with normalization + * + * @param[in] in 1x3 matrix with pixels + * @param[in] coeff 1x2 matrix with coefficients + * @param[in] out_shift output pixel shift value for normalization + * + * @return symmetric 3 tap filter output + * + * This function performs symmetric 3 tap filter input pixels. + * Filter sum is normalized by shifting out_shift bits. + * Filter sum: p0*c1 + p1*c0 + p2*c1 + * is implemented as: (p0 + p2)*c1 + p1*c0 to reduce multiplication. + * Input pixels should to be scaled, otherwise overflow is possible during + * addition +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w +fir1x3m_sym_nrm(s_1w_1x3_matrix in, + s_1w_1x2_matrix coeff, + tvector1w out_shift); + +/** @brief Symmetric 3 tap filter with normalization + * + * @param[in] in 1x3 matrix with pixels + * @param[in] coeff 1x2 matrix with coefficients + * + * @return symmetric 3 tap filter output + * + * This function performs symmetric 3 tap filter over input pixels. + * Filter sum: p0*c1 + p1*c0 + p2*c1 = (p0 + p2)*c1 + p1*c0 + * Input pixels are in Qn and coefficient c0 is in Qm and c1 is in Qn format, + * where n = ISP_VEC_ELEMBITS - 1 and m = ISP_VEC_ELEMBITS - 2 ( ie Q15 and Q14 + * respectively for Broxton) + * To avoid double precision arithmetic input pixel sum is implemented using + * avgrnd, coefficient multiplication using qrmul and final sum using addsat + * Final sum is Qm format (ie Q14 for Broxton) +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w +fir1x3m_sym_nrm_approx(s_1w_1x3_matrix in, + s_1w_1x2_matrix coeff); + +/** @brief Mean of 1x3 matrix + * + * @param[in] m 1x3 matrix with pixels + * + * @return mean of 1x3 matrix + * + * This function calculates the mean of 1x3 pixels, + * with a factor of 4/3. +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean1x3m( + s_1w_1x3_matrix m); + +/** @brief Mean of 3x3 matrix + * + * @param[in] m 3x3 matrix with pixels + * + * @return mean of 3x3 matrix + * + * This function calculates the mean of 3x3 pixels, + * with a factor of 16/9. +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean3x3m( + s_1w_3x3_matrix m); + +/** @brief Mean of 1x4 matrix + * + * @param[in] m 1x4 matrix with pixels + * + * @return mean of 1x4 matrix + * + * This function calculates the mean of 1x4 pixels +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean1x4m( + s_1w_1x4_matrix m); + +/** @brief Mean of 4x4 matrix + * + * @param[in] m 4x4 matrix with pixels + * + * @return mean of 4x4 matrix + * + * This function calculates the mean of 4x4 matrix with pixels +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean4x4m( + s_1w_4x4_matrix m); + +/** @brief Mean of 2x3 matrix + * + * @param[in] m 2x3 matrix with pixels + * + * @return mean of 2x3 matrix + * + * This function calculates the mean of 2x3 matrix with pixels + * with a factor of 8/6. +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean2x3m( + s_1w_2x3_matrix m); + +/** @brief Mean of 1x5 matrix + * + * @param[in] m 1x5 matrix with pixels + * + * @return mean of 1x5 matrix + * + * This function calculates the mean of 1x5 matrix with pixels + * with a factor of 8/5. +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean1x5m(s_1w_1x5_matrix m); + +/** @brief Mean of 1x6 matrix + * + * @param[in] m 1x6 matrix with pixels + * + * @return mean of 1x6 matrix + * + * This function calculates the mean of 1x6 matrix with pixels + * with a factor of 8/6. +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean1x6m( + s_1w_1x6_matrix m); + +/** @brief Mean of 5x5 matrix + * + * @param[in] m 5x5 matrix with pixels + * + * @return mean of 5x5 matrix + * + * This function calculates the mean of 5x5 matrix with pixels + * with a factor of 32/25. +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean5x5m( + s_1w_5x5_matrix m); + +/** @brief Mean of 6x6 matrix + * + * @param[in] m 6x6 matrix with pixels + * + * @return mean of 6x6 matrix + * + * This function calculates the mean of 6x6 matrix with pixels + * with a factor of 64/36. +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w mean6x6m( + s_1w_6x6_matrix m); + +/** @brief Minimum of 4x4 matrix + * + * @param[in] m 4x4 matrix with pixels + * + * @return minimum of 4x4 matrix + * + * This function calculates the minimum of + * 4x4 matrix with pixels. +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w min4x4m( + s_1w_4x4_matrix m); + +/** @brief Maximum of 4x4 matrix + * + * @param[in] m 4x4 matrix with pixels + * + * @return maximum of 4x4 matrix + * + * This function calculates the maximum of + * 4x4 matrix with pixels. +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w max4x4m( + s_1w_4x4_matrix m); + +/** @brief SAD between two 3x3 matrices + * + * @param[in] a 3x3 matrix with pixels + * + * @param[in] b 3x3 matrix with pixels + * + * @return 3x3 matrix SAD + * + * This function calculates the sum of absolute difference between two matrices. + * Both input pixels and SAD are normalized by a factor of SAD3x3_IN_SHIFT and + * SAD3x3_OUT_SHIFT respectively. + * Computed SAD is 1/(2 ^ (SAD3x3_IN_SHIFT + SAD3x3_OUT_SHIFT)) ie 1/16 factor + * of original SAD and it's more precise than sad3x3m() +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w sad3x3m_precise( + s_1w_3x3_matrix a, + s_1w_3x3_matrix b); + +/** @brief SAD between two 3x3 matrices + * + * @param[in] a 3x3 matrix with pixels + * + * @param[in] b 3x3 matrix with pixels + * + * @return 3x3 matrix SAD + * + * This function calculates the sum of absolute difference between two matrices. + * This version saves cycles by avoiding input normalization and wide vector + * operation during sum computation + * Input pixel differences are computed by absolute of rounded, halved + * subtraction. Normalized sum is computed by rounded averages. + * Computed SAD is (1/2)*(1/16) = 1/32 factor of original SAD. Factor 1/2 comes + * from input halving operation and factor 1/16 comes from mean operation +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w sad3x3m( + s_1w_3x3_matrix a, + s_1w_3x3_matrix b); + +/** @brief SAD between two 5x5 matrices + * + * @param[in] a 5x5 matrix with pixels + * + * @param[in] b 5x5 matrix with pixels + * + * @return 5x5 matrix SAD + * + * Computed SAD is = 1/32 factor of original SAD. +*/ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w sad5x5m( + s_1w_5x5_matrix a, + s_1w_5x5_matrix b); + +/** @brief Absolute gradient between two sets of 1x5 matrices + * + * @param[in] m0 first set of 1x5 matrix with pixels + * @param[in] m1 second set of 1x5 matrix with pixels + * + * @return absolute gradient between two 1x5 matrices + * + * This function computes mean of two input 1x5 matrices and returns + * absolute difference between two mean values. + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w +absgrad1x5m(s_1w_1x5_matrix m0, s_1w_1x5_matrix m1); + +/** @brief Bi-linear Interpolation optimized(approximate) + * + * @param[in] a input0 + * @param[in] b input1 + * @param[in] c cloned weight factor + * + * @return (a-b)*c + b + * + * This function will do bi-linear Interpolation on + * inputs a and b using constant weight factor c + * + * Inputs a,b are assumed in S1.15 format + * Weight factor has to be in range [0,1] and is assumed to be in S2.14 format + * + * The bilinear interpolation equation is (a*c) + b*(1-c), + * But this is implemented as (a-b)*c + b for optimization + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_bilinear_interpol_approx_c( + tvector1w a, + tvector1w b, + tscalar1w_weight c); + +/** @brief Bi-linear Interpolation optimized(approximate) + * + * @param[in] a input0 + * @param[in] b input1 + * @param[in] c weight factor + * + * @return (a-b)*c + b + * + * This function will do bi-linear Interpolation on + * inputs a and b using weight factor c + * + * Inputs a,b are assumed in S1.15 format + * Weight factor has to be in range [0,1] and is assumed to be in S2.14 format + * + * The bilinear interpolation equation is (a*c) + b*(1-c), + * But this is implemented as (a-b)*c + b for optimization + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_bilinear_interpol_approx( + tvector1w a, + tvector1w b, + tvector1w_weight c); + +/** @brief Bi-linear Interpolation + * + * @param[in] a input0 + * @param[in] b input1 + * @param[in] c weight factor + * + * @return (a*c) + b*(1-c) + * + * This function will do bi-linear Interpolation on + * inputs a and b using weight factor c + * + * Inputs a,b are assumed in S1.15 format + * Weight factor has to be in range [0,1] and is assumed to be in S2.14 format + * + * The bilinear interpolation equation is (a*c) + b*(1-c), + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_bilinear_interpol( + tvector1w a, + tvector1w b, + tscalar1w_weight c); + +/** @brief Generic Block Matching Algorithm + * @param[in] search_window pointer to input search window of 16x16 pixels + * @param[in] ref_block pointer to input reference block of 8x8 pixels, where N<=M + * @param[in] output pointer to output sads + * @param[in] search_sz search size for SAD computation + * @param[in] ref_sz block size + * @param[in] pixel_shift pixel shift to search the data + * @param[in] search_block_sz search window block size + * @param[in] shift shift value, with which the output is shifted right + * + * @return 0 when the computation is successful. + + * * This function compares the reference block with a block of size NxN in the search + * window. Sum of absolute differences for each pixel in the reference block and the + * corresponding pixel in the search block. Whole search window os traversed with the + * reference block with the given pixel shift. + * + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H int generic_block_matching_algorithm( + tscalar1w **search_window, + tscalar1w **ref_block, + tscalar1w *output, + int search_sz, + int ref_sz, + int pixel_shift, + int search_block_sz, + tscalar1w_4bit_bma_shift shift); + +#ifndef ISP2401 +/** @brief OP_1w_asp_bma_16_1_32way +#else +/** @brief OP_1w_asp_bma_16_1_32way_nomask +#endif + * + * @param[in] search_area input search window of 16x16 pixels + * @param[in] input_block input reference block of 8x8 pixels, where N<=M + * @param[in] shift shift value, with which the output is shifted right + * + * @return 81 SADs for all the search blocks. + + * This function compares the reference block with a block of size 8x8 pixels in the + * search window of 16x16 pixels. Sum of absolute differences for each pixel in the + * reference block and the corresponding pixel in the search block is calculated. + * Whole search window is traversed with the reference block with the pixel shift of 1 + * pixels. The output is right shifted with the given shift value. The shift value is + * a 4 bit value. + * + */ + +#ifndef ISP2401 +STORAGE_CLASS_REF_VECTOR_FUNC_H bma_output_16_1 OP_1w_asp_bma_16_1_32way( +#else +STORAGE_CLASS_REF_VECTOR_FUNC_H bma_output_16_1 OP_1w_asp_bma_16_1_32way_nomask( +#endif + bma_16x16_search_window search_area, + ref_block_8x8 input_block, + tscalar1w_4bit_bma_shift shift); + +#ifndef ISP2401 +/** @brief OP_1w_asp_bma_16_2_32way +#else +/** @brief OP_1w_asp_bma_16_2_32way_nomask +#endif + * + * @param[in] search_area input search window of 16x16 pixels + * @param[in] input_block input reference block of 8x8 pixels, where N<=M + * @param[in] shift shift value, with which the output is shifted right + * + * @return 25 SADs for all the search blocks. + * This function compares the reference block with a block of size 8x8 in the search + * window of 16x61. Sum of absolute differences for each pixel in the reference block + * and the corresponding pixel in the search block is computed. Whole search window is + * traversed with the reference block with the given pixel shift of 2 pixels. The output + * is right shifted with the given shift value. The shift value is a 4 bit value. + * + */ + +#ifndef ISP2401 +STORAGE_CLASS_REF_VECTOR_FUNC_H bma_output_16_2 OP_1w_asp_bma_16_2_32way( +#else +STORAGE_CLASS_REF_VECTOR_FUNC_H bma_output_16_2 OP_1w_asp_bma_16_2_32way_nomask( +#endif + bma_16x16_search_window search_area, + ref_block_8x8 input_block, + tscalar1w_4bit_bma_shift shift); +#ifndef ISP2401 +/** @brief OP_1w_asp_bma_14_1_32way +#else +/** @brief OP_1w_asp_bma_14_1_32way_nomask +#endif + * + * @param[in] search_area input search block of 16x16 pixels with search window of 14x14 pixels + * @param[in] input_block input reference block of 8x8 pixels, where N<=M + * @param[in] shift shift value, with which the output is shifted right + * + * @return 49 SADs for all the search blocks. + * This function compares the reference block with a block of size 8x8 in the search + * window of 14x14. Sum of absolute differences for each pixel in the reference block + * and the corresponding pixel in the search block. Whole search window is traversed + * with the reference block with 2 pixel shift. The output is right shifted with the + * given shift value. The shift value is a 4 bit value. Input is always a 16x16 block + * but the search window is 14x14, with last 2 pixels of row and column are not used + * for computation. + * + */ + +#ifndef ISP2401 +STORAGE_CLASS_REF_VECTOR_FUNC_H bma_output_14_1 OP_1w_asp_bma_14_1_32way( +#else +STORAGE_CLASS_REF_VECTOR_FUNC_H bma_output_14_1 OP_1w_asp_bma_14_1_32way_nomask( +#endif + bma_16x16_search_window search_area, + ref_block_8x8 input_block, + tscalar1w_4bit_bma_shift shift); + +#ifndef ISP2401 +/** @brief OP_1w_asp_bma_14_2_32way +#else +/** @brief OP_1w_asp_bma_14_2_32way_nomask +#endif + * + * @param[in] search_area input search block of 16x16 pixels with search window of 14x14 pixels + * @param[in] input_block input reference block of 8x8 pixels, where N<=M + * @param[in] shift shift value, with which the output is shifted right + * + * @return 16 SADs for all the search blocks. + * This function compares the reference block with a block of size 8x8 in the search + * window of 14x14. Sum of absolute differences for each pixel in the reference block + * and the corresponding pixel in the search block. Whole search window is traversed + * with the reference block with 2 pixels shift. The output is right shifted with the + * given shift value. The shift value is a 4 bit value. + * + */ + +#ifndef ISP2401 +STORAGE_CLASS_REF_VECTOR_FUNC_H bma_output_14_2 OP_1w_asp_bma_14_2_32way( +#else +STORAGE_CLASS_REF_VECTOR_FUNC_H bma_output_14_2 OP_1w_asp_bma_14_2_32way_nomask( +#endif + bma_16x16_search_window search_area, + ref_block_8x8 input_block, + tscalar1w_4bit_bma_shift shift); + +#ifdef ISP2401 +/** @brief multiplex addition and passing + * + * @param[in] _a first pixel + * @param[in] _b second pixel + * @param[in] _c condition flag + * + * @return (_a + _b) if condition flag is true + * _a if condition flag is false + * + * This function does multiplex addition depending on the input condition flag + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H tvector1w OP_1w_cond_add( + tvector1w _a, + tvector1w _b, + tflags _c); + +#endif +#ifdef HAS_bfa_unit +/** @brief OP_1w_single_bfa_7x7 + * + * @param[in] weights - spatial and range weight lut + * @param[in] threshold - threshold plane, for range weight scaling + * @param[in] central_pix - central pixel plane + * @param[in] src_plane - src pixel plane + * + * @return Bilateral filter output + * + * This function implements, 7x7 single bilateral filter. + * Output = {sum(pixel * weight), sum(weight)} + * Where sum is summation over 7x7 block set. + * weight = spatial weight * range weight + * spatial weights are loaded from spatial_weight_lut depending on src pixel + * position in the 7x7 block + * range weights are computed by table look up from range_weight_lut depending + * on scaled absolute difference between src and central pixels. + * threshold is used as scaling factor. range_weight_lut consists of + * BFA_RW_LUT_SIZE numbers of LUT entries to model any distribution function. + * Piecewise linear approximation technique is used to compute range weight + * It computes absolute difference between central pixel and 61 src pixels. + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H bfa_7x7_output OP_1w_single_bfa_7x7( + bfa_weights weights, + tvector1w threshold, + tvector1w central_pix, + s_1w_7x7_matrix src_plane); + +/** @brief OP_1w_joint_bfa_7x7 + * + * @param[in] weights - spatial and range weight lut + * @param[in] threshold0 - 1st threshold plane, for range weight scaling + * @param[in] central_pix0 - 1st central pixel plane + * @param[in] src0_plane - 1st pixel plane + * @param[in] threshold1 - 2nd threshold plane, for range weight scaling + * @param[in] central_pix1 - 2nd central pixel plane + * @param[in] src1_plane - 2nd pixel plane + * + * @return Joint bilateral filter output + * + * This function implements, 7x7 joint bilateral filter. + * Output = {sum(pixel * weight), sum(weight)} + * Where sum is summation over 7x7 block set. + * weight = spatial weight * range weight + * spatial weights are loaded from spatial_weight_lut depending on src pixel + * position in the 7x7 block + * range weights are computed by table look up from range_weight_lut depending + * on sum of scaled absolute difference between central pixel and two src pixel + * planes. threshold is used as scaling factor. range_weight_lut consists of + * BFA_RW_LUT_SIZE numbers of LUT entries to model any distribution function. + * Piecewise linear approximation technique is used to compute range weight + * It computes absolute difference between central pixel and 61 src pixels. + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H bfa_7x7_output OP_1w_joint_bfa_7x7( + bfa_weights weights, + tvector1w threshold0, + tvector1w central_pix0, + s_1w_7x7_matrix src0_plane, + tvector1w threshold1, + tvector1w central_pix1, + s_1w_7x7_matrix src1_plane); + +/** @brief bbb_bfa_gen_spatial_weight_lut + * + * @param[in] in - 7x7 matrix of spatial weights + * @param[in] out - generated LUT + * + * @return None + * + * This function implements, creates spatial weight look up table used + * for bilaterl filter instruction. + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H void bbb_bfa_gen_spatial_weight_lut( + s_1w_7x7_matrix in, + tvector1w out[BFA_MAX_KWAY]); + +/** @brief bbb_bfa_gen_range_weight_lut + * + * @param[in] in - input range weight, + * @param[in] out - generated LUT + * + * @return None + * + * This function implements, creates range weight look up table used + * for bilaterl filter instruction. + * 8 unsigned 7b weights are represented in 7 16bits LUT + * LUT formation is done as follows: + * higher 8 bit: Point(N) = Point(N+1) - Point(N) + * lower 8 bit: Point(N) = Point(N) + * Weight function can be any monotonic decreasing function for x >= 0 + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H void bbb_bfa_gen_range_weight_lut( + tvector1w in[BFA_RW_LUT_SIZE+1], + tvector1w out[BFA_RW_LUT_SIZE]); +#endif + +#ifdef ISP2401 +/** @brief OP_1w_imax32 + * + * @param[in] src - structure that holds an array of 32 elements. + * + * @return maximum element among input array. + * + *This function gets maximum element from an array of 32 elements. + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H int OP_1w_imax32( + imax32_ref_in_vector src); + +/** @brief OP_1w_imaxidx32 + * + * @param[in] src - structure that holds a vector of elements. + * + * @return index of first element with maximum value among array. + * + * This function gets index of first element with maximum value + * from 32 elements. + */ +STORAGE_CLASS_REF_VECTOR_FUNC_H int OP_1w_imaxidx32( + imax32_ref_in_vector src); + +#endif +#ifndef INLINE_VECTOR_FUNC +#define STORAGE_CLASS_REF_VECTOR_FUNC_C +#define STORAGE_CLASS_REF_VECTOR_DATA_C const +#else /* INLINE_VECTOR_FUNC */ +#define STORAGE_CLASS_REF_VECTOR_FUNC_C STORAGE_CLASS_REF_VECTOR_FUNC_H +#define STORAGE_CLASS_REF_VECTOR_DATA_C STORAGE_CLASS_REF_VECTOR_DATA_H +#include "ref_vector_func.c" +#define VECTOR_FUNC_INLINED +#endif /* INLINE_VECTOR_FUNC */ + +#endif /*_REF_VECTOR_FUNC_H_INCLUDED_*/ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/ref_vector_func_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/ref_vector_func_types.h new file mode 100644 index 0000000000000000000000000000000000000000..4dd05eba852e1fce5ad4240f515d830ad1e4ae30 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/ref_vector_func_types.h @@ -0,0 +1,385 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __REF_VECTOR_FUNC_TYPES_H_INCLUDED__ +#define __REF_VECTOR_FUNC_TYPES_H_INCLUDED__ + + +/* + * Prerequisites: + * + */ +#include "mpmath.h" +#include "bbb_config.h" +#include "isp_op1w_types.h" +#include "isp_op2w_types.h" + +/* Defines for the Config Unit */ +#define MAX_CONFIG_POINTS 5 +#define INPUT_OFFSET_FACTOR 10 +#define INPUT_SCALE_FACTOR 10 +#define OUTPUT_SCALE_FACTOR 10 +#define SLOPE_A_RESOLUTION 10 +#define CONFIG_UNIT_LUT_SIZE_32 32 /*XCU works for ISP_NWAY = 32 */ +#define LXCU_LUT_SIZE 16 +#ifdef ISP2401 +#define IMAX32_ELEM_SIZE 32 +#endif + +#define ONE_IN_Q14 (1<<(NUM_BITS-2)) +#define Q29_TO_Q15_SHIFT_VAL (NUM_BITS-2) +#define Q28_TO_Q15_SHIFT_VAL (NUM_BITS-3) +#define MAX_ELEM(width_in_bits) ((1<<(width_in_bits))-1) + +/* Block matching algorithm related data */ +/* NUM_OF_SADS = ((SEARCH_AREA_HEIGHT - REF_BLOCK_HEIGHT)/PIXEL_SHIFT + 1)* \ + ((SEARCH_AREA_WIDTH - REF_BLOCK_WIDTH)/PIXEL_SHIFT + 1) */ + +#define SADS(sw_h,sw_w, ref_h, ref_w, p_sh) (((sw_h - ref_h)/p_sh + 1)*((sw_w - ref_w)/p_sh + 1)) +#define SADS_16x16_1 SADS(16, 16, 8, 8, 1) +#define SADS_16x16_2 SADS(16, 16, 8, 8, 2) +#define SADS_14x14_1 SADS(14, 14, 8, 8, 1) +#define SADS_14x14_2 SADS(14, 14, 8, 8, 2) + +#define BMA_OUTPUT_MATRIX_DIM(sw_h, ref_h, p_sh) ((sw_h - ref_h)/p_sh + 1) +#define BMA_OUT_16x16_2_32 BMA_OUTPUT_MATRIX_DIM(16, 8, 2) +#define BMA_OUT_14x14_2_32 BMA_OUTPUT_MATRIX_DIM(14, 8, 2) +#define BMA_OUT_16x16_1_32 BMA_OUTPUT_MATRIX_DIM(16, 8, 1) +#define BMA_OUT_14x14_1_32 BMA_OUTPUT_MATRIX_DIM(14, 8, 1) +#define BMA_SEARCH_BLOCK_SZ_16 16 +#define BMA_REF_BLOCK_SZ_8 8 +#define PIXEL_SHIFT_2 2 +#define PIXEL_SHIFT_1 1 +#define BMA_SEARCH_WIN_SZ_16 16 +#define BMA_SEARCH_WIN_SZ_14 14 + + +/* + * Struct type specification + */ + +typedef unsigned short tscalar1w_3bit; /* tscalar1w in interval [0, 2^3) */ +typedef short tscalar1w_5bit_signed; /* tscalar1w in interval [-2^(5-1), 2^(5-1)) */ +typedef unsigned short tscalar1w_5bit; /* tscalar1w in interval [0, 2^5) */ +typedef short tscalar1w_range1wbit; /* tscalar1w in interval [-NUM_BITS, NUM_BITS] */ +typedef short tscalar1w_unsigned_range1wbit; /* tscalar1w in interval [0, NUM_BITS] */ +typedef unsigned short tvector_8bit; /* 8 bit positive number */ +typedef unsigned short tvector_5bit; +typedef unsigned short tvector_4bit; +typedef unsigned short tscalar1w_16bit; +typedef unsigned short tscalar1w_4bit_bma_shift; + +typedef struct { + tvector1w v0 ; + tvector1w v1 ; +} s_1w_2x1_matrix; + +#define S_1W_2X1_MATRIX_DEFAULT ((s_1w_2x1_matrix)\ + { 0, 0 }) + +typedef struct { + tvector1w v00; + tvector1w v01; +} s_1w_1x2_matrix; + +#define S_1W_1X2_MATRIX_DEFAULT ((s_1w_1x2_matrix)\ + { 0, 0 }) + +typedef struct { + tvector1w v00 ; + tvector1w v01 ; + tvector1w v02 ; +} s_1w_1x3_matrix; + +#define S_1W_1X3_MATRIX_DEFAULT ((s_1w_1x3_matrix)\ + { 0, 0, 0, }) + +typedef struct { + tvector1w v00; tvector1w v01; tvector1w v02; + tvector1w v10; tvector1w v11; tvector1w v12; +} s_1w_2x3_matrix; + +#define S_1W_2X3_MATRIX_DEFAULT ((s_1w_2x3_matrix)\ + { 0, 0, 0, \ + 0, 0, 0 }) + +typedef struct { + tvector1w v00 ; tvector1w v01 ; tvector1w v02 ; + tvector1w v10 ; tvector1w v11 ; tvector1w v12 ; + tvector1w v20 ; tvector1w v21 ; tvector1w v22 ; +} s_1w_3x3_matrix; + +#define S_1W_3X3_MATRIX_DEFAULT ((s_1w_3x3_matrix)\ + { 0, 0, 0, \ + 0, 0, 0, \ + 0, 0, 0 }) + +typedef struct { + tvector1w v00 ; tvector1w v01 ; tvector1w v02 ; + tvector1w v10 ; tvector1w v11 ; tvector1w v12 ; + tvector1w v20 ; tvector1w v21 ; tvector1w v22 ; + tvector1w v30 ; tvector1w v31 ; tvector1w v32 ; +} s_1w_4x3_matrix; + +#define S_1W_4X3_MATRIX_DEFAULT ((s_1w_4x3_matrix)\ + { 0, 0, 0, \ + 0, 0, 0, \ + 0, 0, 0, \ + 0, 0, 0 }) + +typedef struct { + tvector1w v00 ; + tvector1w v01 ; + tvector1w v02 ; + tvector1w v03 ; + tvector1w v04 ; +} s_1w_1x5_matrix; + +#define S_1W_1X5_MATRIX_DEFAULT ((s_1w_1x5_matrix)\ + { 0, 0, 0, 0, 0 }) + +typedef struct { + tvector1w v00 ; tvector1w v01 ; tvector1w v02 ; tvector1w v03 ; tvector1w v04 ; + tvector1w v10 ; tvector1w v11 ; tvector1w v12 ; tvector1w v13 ; tvector1w v14 ; + tvector1w v20 ; tvector1w v21 ; tvector1w v22 ; tvector1w v23 ; tvector1w v24 ; + tvector1w v30 ; tvector1w v31 ; tvector1w v32 ; tvector1w v33 ; tvector1w v34 ; + tvector1w v40 ; tvector1w v41 ; tvector1w v42 ; tvector1w v43 ; tvector1w v44 ; +} s_1w_5x5_matrix; + +#define S_1W_5X5_MATRIX_DEFAULT ((s_1w_5x5_matrix)\ + { 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0 }) +#ifndef ISP2401 + +#else + +#endif +typedef struct { + tvector1w v00; + tvector1w v01; + tvector1w v02; + tvector1w v03; + tvector1w v04; + tvector1w v05; + tvector1w v06; +} s_1w_1x7_matrix; + +#define S_1W_1X7_MATRIX_DEFAULT ((s_1w_1x7_matrix)\ + { 0, 0, 0, 0, 0, 0, 0 }) + +typedef struct { + tvector1w v00; + tvector1w v01; + tvector1w v02; + tvector1w v03; + tvector1w v04; + tvector1w v05; + tvector1w v06; + tvector1w v07; + tvector1w v08; +} s_1w_1x9_matrix; + +#define S_1W_1X9_MATRIX_DEFAULT ((s_1w_1x9_matrix)\ + { 0, 0, 0, 0, 0, 0, 0, 0, 0 }) + +typedef struct { + tvector1w v00; + tvector1w v01; + tvector1w v02; + tvector1w v03; +} s_1w_1x4_matrix; + +#define S_1W_1X4_MATRIX ((s_1w_1x4_matrix)\ + { 0, 0, 0, 0 }) + +typedef struct { + tvector1w v00; tvector1w v01; tvector1w v02; tvector1w v03; + tvector1w v10; tvector1w v11; tvector1w v12; tvector1w v13; + tvector1w v20; tvector1w v21; tvector1w v22; tvector1w v23; + tvector1w v30; tvector1w v31; tvector1w v32; tvector1w v33; +} s_1w_4x4_matrix; + +#define S_1W_4X4_MATRIX_DEFAULT ((s_1w_4x4_matrix)\ + { 0, 0, 0, 0, \ + 0, 0, 0, 0, \ + 0, 0, 0, 0, \ + 0, 0, 0, 0 }) + +typedef struct { + tvector1w v00; + tvector1w v01; + tvector1w v02; + tvector1w v03; + tvector1w v04; + tvector1w v05; +} s_1w_1x6_matrix; + +#define S_1W_1X6_MATRIX_DEFAULT ((s_1w_1x6_matrix)\ + { 0, 0, 0, 0, 0, 0 }) + +typedef struct { + tvector1w v00; tvector1w v01; tvector1w v02; tvector1w v03; tvector1w v04; tvector1w v05; + tvector1w v10; tvector1w v11; tvector1w v12; tvector1w v13; tvector1w v14; tvector1w v15; + tvector1w v20; tvector1w v21; tvector1w v22; tvector1w v23; tvector1w v24; tvector1w v25; + tvector1w v30; tvector1w v31; tvector1w v32; tvector1w v33; tvector1w v34; tvector1w v35; + tvector1w v40; tvector1w v41; tvector1w v42; tvector1w v43; tvector1w v44; tvector1w v45; + tvector1w v50; tvector1w v51; tvector1w v52; tvector1w v53; tvector1w v54; tvector1w v55; +} s_1w_6x6_matrix; + +#define S_1W_6X6_MATRIX_DEFAULT ((s_1w_6x6_matrix)\ + { 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0 }) + +typedef struct { + tvector1w v00; tvector1w v01; tvector1w v02; tvector1w v03; tvector1w v04; + tvector1w v05; tvector1w v06; tvector1w v07; tvector1w v08; + tvector1w v10; tvector1w v11; tvector1w v12; tvector1w v13; tvector1w v14; + tvector1w v15; tvector1w v16; tvector1w v17; tvector1w v18; + tvector1w v20; tvector1w v21; tvector1w v22; tvector1w v23; tvector1w v24; + tvector1w v25; tvector1w v26; tvector1w v27; tvector1w v28; + tvector1w v30; tvector1w v31; tvector1w v32; tvector1w v33; tvector1w v34; + tvector1w v35; tvector1w v36; tvector1w v37; tvector1w v38; + tvector1w v40; tvector1w v41; tvector1w v42; tvector1w v43; tvector1w v44; + tvector1w v45; tvector1w v46; tvector1w v47; tvector1w v48; + tvector1w v50; tvector1w v51; tvector1w v52; tvector1w v53; tvector1w v54; + tvector1w v55; tvector1w v56; tvector1w v57; tvector1w v58; + tvector1w v60; tvector1w v61; tvector1w v62; tvector1w v63; tvector1w v64; + tvector1w v65; tvector1w v66; tvector1w v67; tvector1w v68; + tvector1w v70; tvector1w v71; tvector1w v72; tvector1w v73; tvector1w v74; + tvector1w v75; tvector1w v76; tvector1w v77; tvector1w v78; + tvector1w v80; tvector1w v81; tvector1w v82; tvector1w v83; tvector1w v84; + tvector1w v85; tvector1w v86; tvector1w v87; tvector1w v88; +} s_1w_9x9_matrix; + +#define S_1W_9X9_MATRIX_DEFAULT ((s_1w_9x9_matrix)\ + { 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, 0, 0 }) + +typedef struct { + tvector1w v00; tvector1w v01; tvector1w v02; tvector1w v03; tvector1w v04; + tvector1w v05; tvector1w v06; + tvector1w v10; tvector1w v11; tvector1w v12; tvector1w v13; tvector1w v14; + tvector1w v15; tvector1w v16; + tvector1w v20; tvector1w v21; tvector1w v22; tvector1w v23; tvector1w v24; + tvector1w v25; tvector1w v26; + tvector1w v30; tvector1w v31; tvector1w v32; tvector1w v33; tvector1w v34; + tvector1w v35; tvector1w v36; + tvector1w v40; tvector1w v41; tvector1w v42; tvector1w v43; tvector1w v44; + tvector1w v45; tvector1w v46; + tvector1w v50; tvector1w v51; tvector1w v52; tvector1w v53; tvector1w v54; + tvector1w v55; tvector1w v56; + tvector1w v60; tvector1w v61; tvector1w v62; tvector1w v63; tvector1w v64; + tvector1w v65; tvector1w v66; +} s_1w_7x7_matrix; + +#define S_1W_7X7_MATRIX_DEFAULT ((s_1w_7x7_matrix)\ + { 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0, \ + 0, 0, 0, 0, 0, 0, 0 }) + +typedef struct { + tvector1w v0_0; + tvector1w v0_1; + tvector1w v0_2; + tvector1w v0_3; + tvector1w v0_4; + tvector1w v0_5; + tvector1w v0_6; + tvector1w v0_7; + tvector1w v0_8; + tvector1w v0_9; + tvector1w v0_10; +} s_1w_1x11_matrix; + +#define S_1W_1X11_MATRIX_DEFAULT ((s_1w_1x11_matrix)\ + { 0, 0, 0, 0, 0, 0, 0, 0, 0 }) + +typedef struct { + tvector1w x_cord[MAX_CONFIG_POINTS]; + tvector1w slope[MAX_CONFIG_POINTS-1]; + tvector1w y_offset[MAX_CONFIG_POINTS-1]; +} ref_config_points; + +typedef struct { + tscalar1w_range1wbit slope_vec[CONFIG_UNIT_LUT_SIZE_32]; + tscalar1w_range1wbit offset_vec[CONFIG_UNIT_LUT_SIZE_32]; + tscalar1w_16bit x_cord_vec[CONFIG_UNIT_LUT_SIZE_32]; + tscalar1w_16bit x_cord_max; + tscalar1w_5bit exponent; + tscalar1w_5bit slope_resolution; +} xcu_ref_init_vectors; + +typedef struct { +#ifdef ISP2401 + tvector1w elem[IMAX32_ELEM_SIZE]; +} imax32_ref_in_vector; + +typedef struct { +#endif + tscalar1w search[BMA_SEARCH_BLOCK_SZ_16][BMA_SEARCH_BLOCK_SZ_16]; +} bma_16x16_search_window; + +typedef struct { + tscalar1w ref[BMA_REF_BLOCK_SZ_8][BMA_REF_BLOCK_SZ_8]; +} ref_block_8x8; + +typedef struct { + tscalar1w sads[SADS_16x16_1]; +} bma_output_16_1; + +typedef struct { + tscalar1w sads[SADS_16x16_2]; +} bma_output_16_2; + +typedef struct { + tscalar1w sads[SADS_14x14_2]; +} bma_output_14_2; + +typedef struct { + tscalar1w sads[SADS_14x14_1]; +} bma_output_14_1; + +typedef struct { + tvector1w spatial_weight_lut[BFA_MAX_KWAY]; /* spatial weight LUT */ + /* range weight LUT, (BFA_RW_LUT_SIZE + 1) numbers of LUT values are compressed in BFA_RW_LUT_SIZE buffer. + * range_weight_lut[k] = packed(drop[k], range_weight[k]) + * where, drop[k] = range_weight[k+1] - range_weight[k] + * pack(msb, lsb): two 8bits numbers packed in one 16bits number */ + tvector1w range_weight_lut[BFA_RW_LUT_SIZE]; +} bfa_weights; + +/* Return type for BFA BBBs */ +typedef struct { + tvector2w sop; /* weighted sum of pixels */ + tvector1w sow; /* sum of weights */ +} bfa_7x7_output; +#endif /* __REF_VECTOR_FUNC_TYPES_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/sp_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/sp_public.h new file mode 100644 index 0000000000000000000000000000000000000000..974ce6a33b4bcc0377e1d53268b6430333466d93 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/host/sp_public.h @@ -0,0 +1,223 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SP_PUBLIC_H_INCLUDED__ +#define __SP_PUBLIC_H_INCLUDED__ + +#include +#include "system_types.h" + +typedef struct sp_state_s sp_state_t; +typedef struct sp_stall_s sp_stall_t; + +/*! Enable or disable the program complete irq signal of SP[ID] + + \param ID[in] SP identifier + \param cnd[in] predicate + + \return none, if(cnd) enable(SP[ID].irq) else disable(SP[ID].irq) + */ +extern void cnd_sp_irq_enable( + const sp_ID_t ID, + const bool cnd); + +/*! Read the state of cell SP[ID] + + \param ID[in] SP identifier + \param state[out] sp state structure + \param stall[out] isp stall conditions + + \return none, state = SP[ID].state, stall = SP[ID].stall + */ +extern void sp_get_state( + const sp_ID_t ID, + sp_state_t *state, + sp_stall_t *stall); + +/*! Write to the status and control register of SP[ID] + + \param ID[in] SP identifier + \param reg[in] register index + \param value[in] The data to be written + + \return none, SP[ID].sc[reg] = value + */ +STORAGE_CLASS_SP_H void sp_ctrl_store( + const sp_ID_t ID, + const hrt_address reg, + const hrt_data value); + +/*! Read from the status and control register of SP[ID] + + \param ID[in] SP identifier + \param reg[in] register index + \param value[in] The data to be written + + \return SP[ID].sc[reg] + */ +STORAGE_CLASS_SP_H hrt_data sp_ctrl_load( + const sp_ID_t ID, + const hrt_address reg); + +/*! Get the status of a bitfield in the control register of SP[ID] + + \param ID[in] SP identifier + \param reg[in] register index + \param bit[in] The bit index to be checked + + \return (SP[ID].sc[reg] & (1< +#include +#include + +#if defined(USE_INPUT_SYSTEM_VERSION_2401) + +#ifndef __INLINE_ISYS2401_IRQ__ + +#define STORAGE_CLASS_ISYS2401_IRQ_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_ISYS2401_IRQ_C STORAGE_CLASS_EXTERN +#include "isys_irq_public.h" + +#else /* __INLINE_ISYS2401_IRQ__ */ + +#define STORAGE_CLASS_ISYS2401_IRQ_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_ISYS2401_IRQ_C STORAGE_CLASS_INLINE +#include "isys_irq_private.h" + +#endif /* __INLINE_ISYS2401_IRQ__ */ + +#endif /* defined(USE_INPUT_SYSTEM_VERSION_2401) */ + +#endif /* __IA_CSS_ISYS_IRQ_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/isys_stream2mmio.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/isys_stream2mmio.h new file mode 100644 index 0000000000000000000000000000000000000000..3e8cfe555ad5853cc831326cb91e0814c6ec65ca --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/isys_stream2mmio.h @@ -0,0 +1,49 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __ISYS_STREAM2MMIO_H_INCLUDED__ +#define __ISYS_STREAM2MMIO_H_INCLUDED__ + + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the input system device(s). It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & + * inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "isys_stream2mmio_local.h" + +#ifndef __INLINE_STREAM2MMIO__ +#define STORAGE_CLASS_STREAM2MMIO_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_STREAM2MMIO_C +#include "isys_stream2mmio_public.h" +#else /* __INLINE_STREAM2MMIO__ */ +#define STORAGE_CLASS_STREAM2MMIO_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_STREAM2MMIO_C STORAGE_CLASS_INLINE +#include "isys_stream2mmio_private.h" +#endif /* __INLINE_STREAM2MMIO__ */ + +#endif /* __ISYS_STREAM2MMIO_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/math_support.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/math_support.h new file mode 100644 index 0000000000000000000000000000000000000000..d08397d65e968680b86340fb1bea356645b78cee --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/math_support.h @@ -0,0 +1,224 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __MATH_SUPPORT_H +#define __MATH_SUPPORT_H + +#include "storage_class.h" /* for STORAGE_CLASS_INLINE */ +#if defined(__KERNEL__) +#include /* Override the definition of max/min from linux kernel*/ +#endif /*__KERNEL__*/ + +#if defined(_MSC_VER) +#include /* Override the definition of max/min from stdlib.h*/ +#endif /* _MSC_VER */ + +/* in case we have min/max/MIN/MAX macro's undefine them */ +#ifdef min +#undef min +#endif +#ifdef max +#undef max +#endif +#ifdef MIN /* also defined in include/hrt/numeric.h from SDK */ +#undef MIN +#endif +#ifdef MAX +#undef MAX +#endif +#ifdef ABS +#undef ABS +#endif + +#define IS_ODD(a) ((a) & 0x1) +#define IS_EVEN(a) (!IS_ODD(a)) + +/* force a value to a lower even value */ +#define EVEN_FLOOR(x) ((x) & ~1) + +#ifdef ISP2401 +/* If the number is odd, find the next even number */ +#define EVEN_CEIL(x) ((IS_ODD(x)) ? ((x) + 1) : (x)) + +#endif +/* A => B */ +#define IMPLIES(a, b) (!(a) || (b)) + +#define ABS(a) ((a) >= 0 ? (a) : -(a)) + +/* for preprocessor and array sizing use MIN and MAX + otherwise use min and max */ +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#ifdef ISP2401 +#define ROUND_DIV(a, b) ((b) ? ((a) + ((b) >> 1)) / (b) : 0) +#endif +#define CEIL_DIV(a, b) ((b) ? ((a) + (b) - 1) / (b) : 0) +#define CEIL_MUL(a, b) (CEIL_DIV(a, b) * (b)) +#define CEIL_MUL2(a, b) (((a) + (b) - 1) & ~((b) - 1)) +#define CEIL_SHIFT(a, b) (((a) + (1 << (b)) - 1)>>(b)) +#define CEIL_SHIFT_MUL(a, b) (CEIL_SHIFT(a, b) << (b)) +#ifdef ISP2401 +#define ROUND_HALF_DOWN_DIV(a, b) ((b) ? ((a) + (b / 2) - 1) / (b) : 0) +#define ROUND_HALF_DOWN_MUL(a, b) (ROUND_HALF_DOWN_DIV(a, b) * (b)) +#endif + + +/*To Find next power of 2 number from x */ +#define bit2(x) ((x) | ((x) >> 1)) +#define bit4(x) (bit2(x) | (bit2(x) >> 2)) +#define bit8(x) (bit4(x) | (bit4(x) >> 4)) +#define bit16(x) (bit8(x) | (bit8(x) >> 8)) +#define bit32(x) (bit16(x) | (bit16(x) >> 16)) +#define NEXT_POWER_OF_2(x) (bit32(x-1) + 1) + + +/* min and max should not be macros as they will evaluate their arguments twice. + if you really need a macro (e.g. for CPP or for initializing an array) + use MIN() and MAX(), otherwise use min() and max(). + + +*/ + +#if !defined(PIPE_GENERATION) + +#ifndef INLINE_MATH_SUPPORT_UTILS +/* +This macro versions are added back as we are mixing types in usage of inline. +This causes corner cases of calculations to be incorrect due to conversions +between signed and unsigned variables or overflows. +Before the addition of the inline functions, max, min and ceil_div were macros +and therefore adding them back. + +Leaving out the other math utility functions as they are newly added +*/ + +#define max(a, b) (MAX(a, b)) +#define min(a, b) (MIN(a, b)) +#define ceil_div(a, b) (CEIL_DIV(a, b)) + +#else /* !defined(INLINE_MATH_SUPPORT_UTILS) */ + +STORAGE_CLASS_INLINE int max(int a, int b) +{ + return MAX(a, b); +} + +STORAGE_CLASS_INLINE int min(int a, int b) +{ + return MIN(a, b); +} + +STORAGE_CLASS_INLINE unsigned int ceil_div(unsigned int a, unsigned int b) +{ + return CEIL_DIV(a, b); +} +#endif /* !defined(INLINE_MATH_SUPPORT_UTILS) */ + +STORAGE_CLASS_INLINE unsigned int umax(unsigned int a, unsigned int b) +{ + return MAX(a, b); +} + +STORAGE_CLASS_INLINE unsigned int umin(unsigned int a, unsigned int b) +{ + return MIN(a, b); +} + + +STORAGE_CLASS_INLINE unsigned int ceil_mul(unsigned int a, unsigned int b) +{ + return CEIL_MUL(a, b); +} + +STORAGE_CLASS_INLINE unsigned int ceil_mul2(unsigned int a, unsigned int b) +{ + return CEIL_MUL2(a, b); +} + +STORAGE_CLASS_INLINE unsigned int ceil_shift(unsigned int a, unsigned int b) +{ + return CEIL_SHIFT(a, b); +} + +STORAGE_CLASS_INLINE unsigned int ceil_shift_mul(unsigned int a, unsigned int b) +{ + return CEIL_SHIFT_MUL(a, b); +} + +#ifdef ISP2401 +STORAGE_CLASS_INLINE unsigned int round_half_down_div(unsigned int a, unsigned int b) +{ + return ROUND_HALF_DOWN_DIV(a, b); +} + +STORAGE_CLASS_INLINE unsigned int round_half_down_mul(unsigned int a, unsigned int b) +{ + return ROUND_HALF_DOWN_MUL(a, b); +} +#endif + +/** @brief Next Power of Two + * + * @param[in] unsigned number + * + * @return next power of two + * + * This function rounds input to the nearest power of 2 (2^x) + * towards infinity + * + * Input Range: 0 .. 2^(8*sizeof(int)-1) + * + * IF input is a power of 2 + * out = in + * OTHERWISE + * out = 2^(ceil(log2(in)) + * + */ + +STORAGE_CLASS_INLINE unsigned int ceil_pow2(unsigned int a) +{ + if (a == 0) { + return 1; + } + /* IF input is already a power of two*/ + else if ((!((a)&((a)-1)))) { + return a; + } + else { + unsigned int v = a; + v |= v>>1; + v |= v>>2; + v |= v>>4; + v |= v>>8; + v |= v>>16; + return (v+1); + } +} + +#endif /* !defined(PIPE_GENERATION) */ + +#if !defined(__ISP) && !defined(__SP) +/* + * For SP and ISP, SDK provides the definition of OP_std_modadd. + * We need it only for host + */ +#define OP_std_modadd(base, offset, size) ((base+offset)%(size)) +#endif /* !defined(__ISP) && !defined(__SP) */ + +#if !defined(__KERNEL__) +#define clamp(a, min_val, max_val) MIN(MAX((a), (min_val)), (max_val)) +#endif /* !defined(__KERNEL__) */ + +#endif /* __MATH_SUPPORT_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/memory_access/memory_access.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/memory_access/memory_access.h new file mode 100644 index 0000000000000000000000000000000000000000..9d105ecf5d7f1eb41e29a403fbb931a3a03e4129 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/memory_access/memory_access.h @@ -0,0 +1,317 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __MEMORY_ACCESS_H_INCLUDED__ +#define __MEMORY_ACCESS_H_INCLUDED__ + +/*! + * \brief + * Define the public interface for virtual memory + * access functions. Access types are limited to + * those defined in + * + * The address representation is private to the system + * and represented as "hrt_vaddress" rather than a + * pointer, as the memory allocation cannot be accessed + * by dereferencing but reaquires load and store access + * functions + * + * The page table selection or virtual memory context; + * The page table base index; Is implicit. This page + * table base index must be set by the implementation + * of the access function + * + * "store" is a transfer to the system + * "load" is a transfer from the system + * + * Allocation properties can be specified by setting + * attributes (see below) in case of multiple physical + * memories the memory ID is encoded on the attribute + * + * Allocations in the same physical memory, but in a + * different (set of) page tables can be shared through + * a page table information mapping function + */ + +#include +#include "platform_support.h" /* for __func__ */ + +/* + * User provided file that defines the (sub)system address types: + * - hrt_vaddress a type that can hold the (sub)system virtual address range + */ +#include "system_types.h" + +/* + * The MMU base address is a physical address, thus the same type is used + * as for the device base address + */ +#include "device_access.h" + +/*! + * \brief + * Bit masks for specialised allocation functions + * the default is "uncached", "not contiguous", + * "not page aligned" and "not cleared" + * + * Forcing alignment (usually) returns a pointer + * at an alignment boundary that is offset from + * the allocated pointer. Without storing this + * pointer/offset, we cannot free it. The memory + * manager is responsible for the bookkeeping, e.g. + * the allocation function creates a sentinel + * within the allocation referencable from the + * returned pointer/address. + */ +#define MMGR_ATTRIBUTE_MASK 0x000f +#define MMGR_ATTRIBUTE_CACHED 0x0001 +#define MMGR_ATTRIBUTE_CONTIGUOUS 0x0002 +#define MMGR_ATTRIBUTE_PAGEALIGN 0x0004 +#define MMGR_ATTRIBUTE_CLEARED 0x0008 +#define MMGR_ATTRIBUTE_UNUSED 0xfff0 + +/* #define MMGR_ATTRIBUTE_DEFAULT (MMGR_ATTRIBUTE_CACHED) */ +#define MMGR_ATTRIBUTE_DEFAULT 0 + +extern const hrt_vaddress mmgr_NULL; +extern const hrt_vaddress mmgr_EXCEPTION; + +/*! Set the (sub)system virtual memory page table base address + + \param base_addr[in] The address where page table 0 is located + + \Note: The base_addr is an absolute system address, thus it is not + relative to the DDR base address + + \return none, + */ +extern void mmgr_set_base_address( + const sys_address base_addr); + +/*! Get the (sub)system virtual memory page table base address + + \return base_address, + */ +/* unused */ +extern sys_address mmgr_get_base_address(void); + + +/*! Set the (sub)system virtual memory page table base index + + \param base_addr[in] The index where page table 0 is located + + \Note: The base_index is the MSB section of an absolute system address, + the in-page address bits are discared. The base address is not + relative to the DDR base address + + \return none, + */ +/* unused */ +extern void mmgr_set_base_index( + const hrt_data base_index); + +/*! Get the (sub)system virtual memory page table base index + + \return base_address, + */ +/* unused */ +extern hrt_data mmgr_get_base_index(void); + +/*! Return the address of an allocation in memory + + \param size[in] Size in bytes of the allocation + \param caller_func[in] Caller function name + \param caller_line[in] Caller function line number + + \return vaddress + */ +#define mmgr_malloc(__size) mmgr_malloc_ex(__size, __func__, __LINE__) +extern hrt_vaddress mmgr_malloc_ex( + const size_t size, + const char *caller_func, + int caller_line); + +/*! Return the address of a zero initialised allocation in memory + + \param N[in] Horizontal dimension of array + \param size[in] Vertical dimension of array Total size is N*size + \param caller_func[in] Caller function name + \param caller_line[in] Caller function line number + + \return vaddress + */ +#define mmgr_calloc(__N, __size) mmgr_calloc_ex(__N, __size, __func__, __LINE__) +extern hrt_vaddress mmgr_calloc_ex( + const size_t N, + const size_t size, + const char *caller_func, + int caller_line); + +/*! Return the address of a reallocated allocation in memory + + \param vaddr[in] Address of an allocation + \param size[in] Size in bytes of the allocation + + \Note + All limitations and particularities of the C stdlib + realloc function apply + + \return vaddress + */ +/* unused */ +extern hrt_vaddress mmgr_realloc( + hrt_vaddress vaddr, + const size_t size); + +/*! Free the memory allocation identified by the address + + \param vaddr[in] Address of the allocation + \param caller_func[in] Caller function name + \param caller_line[in] Caller function line number + + \return vaddress + */ +#define mmgr_free(__vaddr) mmgr_free_ex(__vaddr, __func__, __LINE__) +extern void mmgr_free_ex( + hrt_vaddress vaddr, + const char *caller_func, + int caller_line); + +/*! Return the address of an allocation in memory + + \param size[in] Size in bytes of the allocation + \param attribute[in] Bit vector specifying the properties + of the allocation including zero initialisation + \param caller_func[in] Caller function name + \param caller_line[in] Caller function line number + + \return vaddress + */ +#define mmgr_alloc_attr(__size, __attribute) mmgr_alloc_attr_ex(__size, __attribute, __func__, __LINE__) +extern hrt_vaddress mmgr_alloc_attr_ex( + const size_t size, + const uint16_t attribute, + const char *caller_func, + int caller_line); + +/*! Return the address of a reallocated allocation in memory + + \param vaddr[in] Address of an allocation + \param size[in] Size in bytes of the allocation + \param attribute[in] Bit vector specifying the properties + of the allocation +#endif + + \Note + All limitations and particularities of the C stdlib + realloc function apply + + \return vaddress + */ +/* unused */ +extern hrt_vaddress mmgr_realloc_attr( + hrt_vaddress vaddr, + const size_t size, + const uint16_t attribute); + +/*! Return the address of a mapped existing allocation in memory + + \param ptr[in] Pointer to an allocation in a different + virtual memory page table, but the same + physical memory + \param size[in] Size of the memory of the pointer + \param attribute[in] Bit vector specifying the properties + of the allocation + \param context Pointer of a context provided by + client/driver for additonal parameters + needed by the implementation + \Note + This interface is tentative, limited to the desired function + the actual interface may require furhter parameters + + \return vaddress + */ +extern hrt_vaddress mmgr_mmap( + const void *ptr, + const size_t size, + uint16_t attribute, + void *context); + +/*! Zero initialise an allocation in memory + + \param vaddr[in] Address of an allocation + \param size[in] Size in bytes of the area to be cleared + \param caller_func[in] Caller function name + \param caller_line[in] Caller function line number + + \return none + */ +#define mmgr_clear(__vaddr, __size) mmgr_clear_ex(__vaddr, __size, __func__, __LINE__) +extern void mmgr_clear_ex( + hrt_vaddress vaddr, + const size_t size, + const char *caller_func, + int caller_line); + +/*! Set an allocation in memory to a value + + \param vaddr[in] Address of an allocation + \param data[in] Value to set + \param size[in] Size in bytes of the area to be set + + \return none + */ +/* unused */ +extern void mmgr_set( + hrt_vaddress vaddr, + const uint8_t data, + const size_t size); + +/*! Read an array of bytes from a virtual memory address + + \param vaddr[in] Address of an allocation + \param data[out] pointer to the destination array + \param size[in] number of bytes to read + \param caller_func[in] Caller function name + \param caller_line[in] Caller function line number + + \return none + */ +#define mmgr_load(__vaddr, __data, __size) mmgr_load_ex(__vaddr, __data, __size, __func__, __LINE__) +extern void mmgr_load_ex( + const hrt_vaddress vaddr, + void *data, + const size_t size, + const char *caller_func, + int caller_line); + +/*! Write an array of bytes to device registers or memory in the device + + \param vaddr[in] Address of an allocation + \param data[in] pointer to the source array + \param size[in] number of bytes to write + \param caller_func[in] Caller function name + \param caller_line[in] Caller function line number + + \return none + */ +#define mmgr_store(__vaddr, __data, __size) mmgr_store_ex(__vaddr, __data, __size, __func__, __LINE__) +extern void mmgr_store_ex( + const hrt_vaddress vaddr, + const void *data, + const size_t size, + const char *caller_func, + int caller_line); + +#endif /* __MEMORY_ACCESS_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/memory_realloc.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/memory_realloc.h new file mode 100644 index 0000000000000000000000000000000000000000..f3b7273fed1b06b648ba95f24c27ecb9ef2e80c9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/memory_realloc.h @@ -0,0 +1,38 @@ +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#ifndef __MEMORY_REALLOC_H_INCLUDED__ +#define __MEMORY_REALLOC_H_INCLUDED__ + +/*! + * \brief + * Define the internal reallocation of private css memory + * + */ + +#include +/* + * User provided file that defines the (sub)system address types: + * - hrt_vaddress a type that can hold the (sub)system virtual address range + */ +#include "system_types.h" +#include "ia_css_err.h" + +bool reallocate_buffer( + hrt_vaddress *curr_buf, + size_t *curr_size, + size_t needed_size, + bool force, + enum ia_css_err *err); + +#endif /*__MEMORY_REALLOC_H_INCLUDED__*/ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/misc_support.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/misc_support.h new file mode 100644 index 0000000000000000000000000000000000000000..38db1ecef3c8dfca1b33d97e1d7672e43b4b3f8c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/misc_support.h @@ -0,0 +1,26 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __MISC_SUPPORT_H_INCLUDED__ +#define __MISC_SUPPORT_H_INCLUDED__ + +/* suppress compiler warnings on unused variables */ +#ifndef NOT_USED +#define NOT_USED(a) ((void)(a)) +#endif + +/* Calculate the total bytes for pow(2) byte alignment */ +#define tot_bytes_for_pow2_align(pow2, cur_bytes) ((cur_bytes + (pow2 - 1)) & ~(pow2 - 1)) + +#endif /* __MISC_SUPPORT_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/mmu_device.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/mmu_device.h new file mode 100644 index 0000000000000000000000000000000000000000..1b2017b029f281fceb2a9a3d307a594f06f4b6da --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/mmu_device.h @@ -0,0 +1,49 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __MMU_DEVICE_H_INCLUDED__ +#define __MMU_DEVICE_H_INCLUDED__ + +/* The file mmu.h already exists */ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the MMU device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "mmu_local.h" + +#ifndef __INLINE_MMU__ +#define STORAGE_CLASS_MMU_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_MMU_C +#include "mmu_public.h" +#else /* __INLINE_MMU__ */ +#define STORAGE_CLASS_MMU_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_MMU_C STORAGE_CLASS_INLINE +#include "mmu_private.h" +#endif /* __INLINE_MMU__ */ + +#endif /* __MMU_DEVICE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/mpmath.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/mpmath.h new file mode 100644 index 0000000000000000000000000000000000000000..565983aafa4d51d410364d0231d87937503078d3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/mpmath.h @@ -0,0 +1,330 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __MPMATH_H_INCLUDED__ +#define __MPMATH_H_INCLUDED__ + +#include "storage_class.h" + +#ifdef INLINE_MPMATH +#define STORAGE_CLASS_MPMATH_FUNC_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_MPMATH_DATA_H STORAGE_CLASS_INLINE_DATA +#else /* INLINE_MPMATH */ +#define STORAGE_CLASS_MPMATH_FUNC_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_MPMATH_DATA_H STORAGE_CLASS_EXTERN_DATA +#endif /* INLINE_MPMATH */ + +#include + +/* + * Implementation limits + */ +#define MIN_BITDEPTH 1 +#define MAX_BITDEPTH 64 + +#define ROUND_NEAREST_EVEN 0 +#define ROUND_NEAREST 1 + +/* + * The MP types + * + * "vector lane data" is scalar. With "scalar data" for limited range shift and address values + */ +typedef unsigned long long mpudata_t; /* Type of reference MP scalar / vector lane data; unsigned */ +typedef long long mpsdata_t; /* Type of reference MP scalar / vector lane data; signed */ +typedef unsigned short spudata_t; /* Type of reference SP scalar / vector lane data; unsigned */ +typedef short spsdata_t; /* Type of reference SP scalar / vector lane data; signed */ +typedef unsigned short bitdepth_t; + +typedef enum { + mp_zero_ID, + mp_one_ID, + mp_mone_ID, + mp_smin_ID, + mp_smax_ID, + mp_umin_ID, + mp_umax_ID, + N_mp_const_ID +} mp_const_ID_t; + +#ifdef ISP2401 +/* _isValidMpudata is for internal use by mpmath and bbb's. + * isValidMpudata is for external use by functions on top. + */ +#ifndef ENABLE_VALID_MP_DATA_CHECK +#define _isValidMpsdata(data,bitdepth) (1) +#define _isValidMpudata(data,bitdepth) (1) +#else +#define _isValidMpsdata(data,bitdepth) isValidMpsdata(data,bitdepth) +#define _isValidMpudata(data,bitdepth) isValidMpsdata(data,bitdepth) + +#endif +#endif +STORAGE_CLASS_MPMATH_FUNC_H bool isValidMpsdata( + const mpsdata_t data, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H bool isValidMpudata( + const mpudata_t data, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_castd ( + const mpsdata_t in0, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_casth ( + const mpsdata_t in0, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_scasth ( + const mpsdata_t in0, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_qcastd ( + const mpsdata_t in0, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_qcasth ( + const mpsdata_t in0, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_qrcasth ( + const mpsdata_t in0, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_abs ( + const mpsdata_t in0, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_limit ( + const mpsdata_t bnd_low, + const mpsdata_t in0, + const mpsdata_t bnd_high, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_max ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_min ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_mux ( + const spudata_t sel, + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_rmux ( + const spudata_t sel, + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_add ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_sadd ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_sub ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_ssub ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_addasr1 ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_subasr1 ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_lsr ( + const mpsdata_t in0, + const spsdata_t shft, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_asr ( + const mpsdata_t in0, + const spsdata_t shft, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_rasr ( + const mpsdata_t in0, + const spsdata_t shft, + const bitdepth_t bitdepth); + +/* "mp_rasr_u()" is implemented by "mp_rasr()" */ +STORAGE_CLASS_MPMATH_FUNC_H mpudata_t mp_rasr_u ( + const mpudata_t in0, + const spsdata_t shft, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_lsl ( + const mpsdata_t in0, + const spsdata_t shft, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_asl ( + const mpsdata_t in0, + const spsdata_t shft, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_muld ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_mul ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_qmul ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_qrmul ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_qdiv ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_qdivh ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_div ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_divh ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_and ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_compl ( + const mpsdata_t in0, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_or ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_xor ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H spudata_t mp_isEQ ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H spudata_t mp_isNE ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H spudata_t mp_isGT ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H spudata_t mp_isGE ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H spudata_t mp_isLT ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H spudata_t mp_isLE ( + const mpsdata_t in0, + const mpsdata_t in1, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H spudata_t mp_isEQZ ( + const mpsdata_t in0, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H spudata_t mp_isNEZ ( + const mpsdata_t in0, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H spudata_t mp_isGTZ ( + const mpsdata_t in0, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H spudata_t mp_isGEZ ( + const mpsdata_t in0, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H spudata_t mp_isLTZ ( + const mpsdata_t in0, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H spudata_t mp_isLEZ ( + const mpsdata_t in0, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpsdata_t mp_const ( + const mp_const_ID_t ID, + const bitdepth_t bitdepth); + +STORAGE_CLASS_MPMATH_FUNC_H mpudata_t mp_sqrt_u( + const mpudata_t in0, + const bitdepth_t bitdepth); + +#ifndef INLINE_MPMATH +#define STORAGE_CLASS_MPMATH_FUNC_C +#define STORAGE_CLASS_MPMATH_DATA_C const +#else /* INLINE_MPMATH */ +#define STORAGE_CLASS_MPMATH_FUNC_C STORAGE_CLASS_MPMATH_FUNC_H +#define STORAGE_CLASS_MPMATH_DATA_C STORAGE_CLASS_MPMATH_DATA_H +#include "mpmath.c" +#define MPMATH_INLINED +#endif /* INLINE_MPMATH */ + +#endif /* __MPMATH_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/osys.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/osys.h new file mode 100644 index 0000000000000000000000000000000000000000..6e48ea9afc297fd8ae9a417dc54bf5f66305d017 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/osys.h @@ -0,0 +1,48 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __OSYS_H_INCLUDED__ +#define __OSYS_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the OSYS device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + * + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "osys_local.h" + +#ifndef __INLINE_OSYS__ +#define STORAGE_CLASS_OSYS_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_OSYS_C +#include "osys_public.h" +#else /* __INLINE_OSYS__ */ +#define STORAGE_CLASS_OSYS_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_OSYS_C STORAGE_CLASS_INLINE +#include "osys_private.h" +#endif /* __INLINE_OSYS__ */ + +#endif /* __OSYS_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/pixelgen.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/pixelgen.h new file mode 100644 index 0000000000000000000000000000000000000000..67f7f3a142318e6d959be2dd47f29f8aeaa1996e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/pixelgen.h @@ -0,0 +1,49 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __PIXELGEN_H_INCLUDED__ +#define __PIXELGEN_H_INCLUDED__ + + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the input system device(s). It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & + * inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "pixelgen_local.h" + +#ifndef __INLINE_PIXELGEN__ +#define STORAGE_CLASS_PIXELGEN_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_PIXELGEN_C +#include "pixelgen_public.h" +#else /* __INLINE_PIXELGEN__ */ +#define STORAGE_CLASS_PIXELGEN_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_PIXELGEN_C STORAGE_CLASS_INLINE +#include "pixelgen_private.h" +#endif /* __INLINE_PIXELGEN__ */ + +#endif /* __PIXELGEN_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/platform_support.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/platform_support.h new file mode 100644 index 0000000000000000000000000000000000000000..02f9eee67ff365667bb12934b66a75986037a3a7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/platform_support.h @@ -0,0 +1,42 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __PLATFORM_SUPPORT_H_INCLUDED__ +#define __PLATFORM_SUPPORT_H_INCLUDED__ + +/** +* @file +* Platform specific includes and functionality. +*/ + +#include "storage_class.h" +#include +#include +#include + +/* For definition of hrt_sleep() */ +#include "hive_isp_css_custom_host_hrt.h" + +#define UINT16_MAX USHRT_MAX +#define UINT32_MAX UINT_MAX +#define UCHAR_MAX (255) + +#define CSS_ALIGN(d, a) d __attribute__((aligned(a))) + +/* + * Put here everything __KERNEL__ specific not covered in + * "assert_support.h", "math_support.h", etc + */ + +#endif /* __PLATFORM_SUPPORT_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/print_support.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/print_support.h new file mode 100644 index 0000000000000000000000000000000000000000..cfbc222ea0c1dcff6dfaa0626bf5a7f87d0c60c1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/print_support.h @@ -0,0 +1,45 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __PRINT_SUPPORT_H_INCLUDED__ +#define __PRINT_SUPPORT_H_INCLUDED__ + +#include "storage_class.h" + +#include +#if !defined(__KERNEL__) +#include +#endif + +extern int (*sh_css_printf) (const char *fmt, va_list args); +/* depends on host supplied print function in ia_css_init() */ +STORAGE_CLASS_INLINE void ia_css_print(const char *fmt, ...) +{ + va_list ap; + if (sh_css_printf) { + va_start(ap, fmt); + sh_css_printf(fmt, ap); + va_end(ap); + } +} + +/* Start adding support for bxt tracing functions for poc. From + * bxt_sandbox/support/print_support.h. */ +/* TODO: support these macros in userspace. */ +#define PWARN(format, ...) ia_css_print("warning: ", ##__VA_ARGS__) +#define PRINT(format, ...) ia_css_print(format, ##__VA_ARGS__) +#define PERROR(format, ...) ia_css_print("error: " format, ##__VA_ARGS__) +#define PDEBUG(format, ...) ia_css_print("debug: " format, ##__VA_ARGS__) + +#endif /* __PRINT_SUPPORT_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/queue.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/queue.h new file mode 100644 index 0000000000000000000000000000000000000000..a3d874b9516a6e26bd57ac2571fad71056a15948 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/queue.h @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __QUEUE_H_INCLUDED__ +#define __QUEUE_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and is system agnostic + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - system and cell agnostic interfaces, constants and identifiers + * - public: cell specific interfaces + * - private: cell specific inline implementations + * - global: inter cell constants and identifiers + * - local: cell specific constants and identifiers + * + */ + +#include + +#include "queue_local.h" + +#ifndef __INLINE_QUEUE__ +#define STORAGE_CLASS_QUEUE_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_QUEUE_C +/* #include "queue_public.h" */ +#include "ia_css_queue.h" +#else /* __INLINE_QUEUE__ */ +#define STORAGE_CLASS_QUEUE_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_QUEUE_C STORAGE_CLASS_INLINE +#include "queue_private.h" +#endif /* __INLINE_QUEUE__ */ + +#endif /* __QUEUE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/resource.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/resource.h new file mode 100644 index 0000000000000000000000000000000000000000..82c55acd0380f3a15da54887cf63bdd353efebae --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/resource.h @@ -0,0 +1,48 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __RESOURCE_H_INCLUDED__ +#define __RESOURCE_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses a RESOURCE manager. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + * + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "resource_local.h" + +#ifndef __INLINE_RESOURCE__ +#define STORAGE_CLASS_RESOURCE_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_RESOURCE_C +#include "resource_public.h" +#else /* __INLINE_RESOURCE__ */ +#define STORAGE_CLASS_RESOURCE_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_RESOURCE_C STORAGE_CLASS_INLINE +#include "resource_private.h" +#endif /* __INLINE_RESOURCE__ */ + +#endif /* __RESOURCE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/socket.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/socket.h new file mode 100644 index 0000000000000000000000000000000000000000..c34c2e75c51fa012bb7852bd81e76aeb4b9e1714 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/socket.h @@ -0,0 +1,48 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SOCKET_H_INCLUDED__ +#define __SOCKET_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the DMA device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + * + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "socket_local.h" + +#ifndef __INLINE_SOCKET__ +#define STORAGE_CLASS_SOCKET_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_SOCKET_C +#include "socket_public.h" +#else /* __INLINE_SOCKET__ */ +#define STORAGE_CLASS_SOCKET_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_SOCKET_C STORAGE_CLASS_INLINE +#include "socket_private.h" +#endif /* __INLINE_SOCKET__ */ + +#endif /* __SOCKET_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/sp.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/sp.h new file mode 100644 index 0000000000000000000000000000000000000000..150fc2f6129bbab0c6ba9033f33e9f890534a131 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/sp.h @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SP_H_INCLUDED__ +#define __SP_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the SP cell. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "sp_local.h" + +#ifndef __INLINE_SP__ +#define STORAGE_CLASS_SP_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_SP_C +#include "sp_public.h" +#else /* __INLINE_SP__ */ +#define STORAGE_CLASS_SP_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_SP_C STORAGE_CLASS_INLINE +#include "sp_private.h" +#endif /* __INLINE_SP__ */ + +#endif /* __SP_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/storage_class.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/storage_class.h new file mode 100644 index 0000000000000000000000000000000000000000..3812c801a662ccab950c7c55a361431e7ca476cb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/storage_class.h @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __STORAGE_CLASS_H_INCLUDED__ +#define __STORAGE_CLASS_H_INCLUDED__ + +/** +* @file +* Platform specific includes and functionality. +*/ + +#define STORAGE_CLASS_EXTERN extern + +#if defined(_MSC_VER) +#define STORAGE_CLASS_INLINE static __inline +#elif defined(__HIVECC) +#define STORAGE_CLASS_INLINE static inline +#else +#define STORAGE_CLASS_INLINE static inline +#endif + +#define STORAGE_CLASS_EXTERN_DATA extern const +#define STORAGE_CLASS_INLINE_DATA static const + +#endif /* __STORAGE_CLASS_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/stream_buffer.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/stream_buffer.h new file mode 100644 index 0000000000000000000000000000000000000000..8e41f60b5d397c4edc4d1aeb0e537b90e64a8959 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/stream_buffer.h @@ -0,0 +1,48 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __STREAM_BUFFER_H_INCLUDED__ +#define __STREAM_BUFFER_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the DMA device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + * + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "stream_buffer_local.h" + +#ifndef __INLINE_STREAM_BUFFER__ +#define STORAGE_CLASS_STREAM_BUFFER_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_STREAM_BUFFER_C +#include "stream_buffer_public.h" +#else /* __INLINE_STREAM_BUFFER__ */ +#define STORAGE_CLASS_STREAM_BUFFER_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_STREAM_BUFFER_C STORAGE_CLASS_INLINE +#include "stream_buffer_private.h" +#endif /* __INLINE_STREAM_BUFFER__ */ + +#endif /* __STREAM_BUFFER_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/string_support.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/string_support.h new file mode 100644 index 0000000000000000000000000000000000000000..568631698a3d458177ff55e71d6afb65295c4e79 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/string_support.h @@ -0,0 +1,167 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __STRING_SUPPORT_H_INCLUDED__ +#define __STRING_SUPPORT_H_INCLUDED__ +#include +#include +#include + +#if !defined(_MSC_VER) +/* + * For all non microsoft cases, we need the following functions + */ + + +/** @brief Copy from src_buf to dest_buf. + * + * @param[out] dest_buf. Destination buffer to copy to + * @param[in] dest_size. The size of the destination buffer in bytes + * @param[in] src_buf. The source buffer + * @param[in] src_size. The size of the source buffer in bytes + * @return 0 on success, error code on failure + * @return EINVAL on Invalid arguments + * @return ERANGE on Destination size too small + */ +STORAGE_CLASS_INLINE int memcpy_s( + void* dest_buf, + size_t dest_size, + const void* src_buf, + size_t src_size) +{ + if ((src_buf == NULL) || (dest_buf == NULL)) { + /* Invalid arguments*/ + return EINVAL; + } + + if ((dest_size < src_size) || (src_size == 0)) { + /* Destination too small*/ + return ERANGE; + } + + memcpy(dest_buf, src_buf, src_size); + return 0; +} + +/** @brief Get the length of the string, excluding the null terminator + * + * @param[in] src_str. The source string + * @param[in] max_len. Look only for max_len bytes in the string + * @return Return the string length excluding null character + * @return Return max_len if no null character in the first max_len bytes + * @return Returns 0 if src_str is NULL + */ +static size_t strnlen_s( + const char* src_str, + size_t max_len) +{ + size_t ix; + if (src_str == NULL) { + /* Invalid arguments*/ + return 0; + } + + for (ix=0; + ((src_str[ix] != '\0') && (ix< max_len)); + ++ix) /*Nothing else to do*/; + + /* On Error, it will return src_size == max_len*/ + return ix; +} + +/** @brief Copy string from src_str to dest_str + * + * @param[out] dest_str. Destination buffer to copy to + * @param[in] dest_size. The size of the destination buffer in bytes + * @param[in] src_str. The source buffer + * @param[in] src_size. The size of the source buffer in bytes + * @return Returns 0 on success + * @return Returns EINVAL on invalid arguments + * @return Returns ERANGE on destination size too small + */ +STORAGE_CLASS_INLINE int strncpy_s( + char* dest_str, + size_t dest_size, + const char* src_str, + size_t src_size) +{ + size_t len; + if (dest_str == NULL) { + /* Invalid arguments*/ + return EINVAL; + } + + if ((src_str == NULL) || (dest_size == 0)) { + /* Invalid arguments*/ + dest_str[0] = '\0'; + return EINVAL; + } + + len = strnlen_s(src_str, src_size); + + if (len >= dest_size) { + /* Destination too small*/ + dest_str[0] = '\0'; + return ERANGE; + } + + /* dest_str is big enough for the len */ + strncpy(dest_str, src_str, len); + dest_str[len+1] = '\0'; + return 0; +} + +/** @brief Copy string from src_str to dest_str + * + * @param[out] dest_str. Destination buffer to copy to + * @param[in] dest_size. The size of the destination buffer in bytes + * @param[in] src_str. The source buffer + * @return Returns 0 on success + * @return Returns EINVAL on invalid arguments + * @return Returns ERANGE on destination size too small + */ +STORAGE_CLASS_INLINE int strcpy_s( + char* dest_str, + size_t dest_size, + const char* src_str) +{ + size_t len; + if (dest_str == NULL) { + /* Invalid arguments*/ + return EINVAL; + } + + if ((src_str == NULL) || (dest_size == 0)) { + /* Invalid arguments*/ + dest_str[0] = '\0'; + return EINVAL; + } + + len = strnlen_s(src_str, dest_size); + + if (len >= dest_size) { + /* Destination too small*/ + dest_str[0] = '\0'; + return ERANGE; + } + + /* dest_str is big enough for the len */ + strncpy(dest_str, src_str, len); + dest_str[len+1] = '\0'; + return 0; +} + +#endif /*!defined(_MSC_VER)*/ + +#endif /* __STRING_SUPPORT_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/system_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/system_types.h new file mode 100644 index 0000000000000000000000000000000000000000..a8c19cee17da2011ff6d8be153ded605f081a5d0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/system_types.h @@ -0,0 +1,25 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef __SYSTEM_TYPES_H_INCLUDED__ +#define __SYSTEM_TYPES_H_INCLUDED__ + +/** +* @file +* Platform specific types. +*/ + + +#include "system_local.h" + +#endif /* __SYSTEM_TYPES_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/tag.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/tag.h new file mode 100644 index 0000000000000000000000000000000000000000..7385fd11c95f5f941abfbf79ab502bce4066d5a3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/tag.h @@ -0,0 +1,46 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TAG_H_INCLUDED__ +#define __TAG_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and is system agnostic + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: cell specific interfaces + * - private: cell specific inline implementations + * - global: inter cell constants and identifiers + * - local: cell specific constants and identifiers + * + */ + +#include "storage_class.h" + +#include "tag_local.h" + +#ifndef __INLINE_TAG__ +#define STORAGE_CLASS_TAG_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_TAG_C +#include "tag_public.h" +#else /* __INLINE_TAG__ */ +#define STORAGE_CLASS_TAG_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_TAG_C STORAGE_CLASS_INLINE +#include "tag_private.h" +#endif /* __INLINE_TAG__ */ + +#endif /* __TAG_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/timed_ctrl.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/timed_ctrl.h new file mode 100644 index 0000000000000000000000000000000000000000..ed13451c9261407ffd6d705aa842d8aa3b7d7fe7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/timed_ctrl.h @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TIMED_CTRL_H_INCLUDED__ +#define __TIMED_CTRL_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the input system device(s). It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "timed_ctrl_local.h" + +#ifndef __INLINE_TIMED_CTRL__ +#define STORAGE_CLASS_TIMED_CTRL_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_TIMED_CTRL_C +#include "timed_ctrl_public.h" +#else /* __INLINE_TIMED_CTRL__ */ +#define STORAGE_CLASS_TIMED_CTRL_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_TIMED_CTRL_C STORAGE_CLASS_INLINE +#include "timed_ctrl_private.h" +#endif /* __INLINE_TIMED_CTRL__ */ + +#endif /* __TIMED_CTRL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/type_support.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/type_support.h new file mode 100644 index 0000000000000000000000000000000000000000..1f991bbe5d71d15b1c6bbf735ad5d7e3fc1a542b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/type_support.h @@ -0,0 +1,93 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TYPE_SUPPORT_H_INCLUDED__ +#define __TYPE_SUPPORT_H_INCLUDED__ + +/** +* @file +* Platform specific types. +* +* Per the DLI spec, types are in "type_support.h" and +* "platform_support.h" is for unclassified/to be refactored +* platform specific definitions. +*/ + +#define IA_CSS_UINT8_T_BITS 8 +#define IA_CSS_UINT16_T_BITS 16 +#define IA_CSS_UINT32_T_BITS 32 +#define IA_CSS_INT32_T_BITS 32 +#define IA_CSS_UINT64_T_BITS 64 + +#if defined(_MSC_VER) +#include +/* For ATE compilation define the bool */ +#if defined(_ATE_) +#define bool int +#define true 1 +#define false 0 +#else +#include +#endif +#include +#include +#include +#if defined(_M_X64) +#define HOST_ADDRESS(x) (unsigned long long)(x) +#else +#define HOST_ADDRESS(x) (unsigned long)(x) +#endif + +#elif defined(__HIVECC) +#ifndef PIPE_GENERATION +#include /* for HAVE_STDINT */ +#endif +#define __INDIRECT_STDINT_INCLUDE +#include +#include +#include +#include +#define HOST_ADDRESS(x) (unsigned long)(x) + +#elif defined(__KERNEL__) + +#define CHAR_BIT (8) + +#include +#include +#include +#define HOST_ADDRESS(x) (unsigned long)(x) + +#elif defined(__GNUC__) +#ifndef __STDC_LIMIT_MACROS +#define __STDC_LIMIT_MACROS 1 +#endif +#include +#include +#include +#include +#include +#define HOST_ADDRESS(x) (unsigned long)(x) + +#else /* default is for the FIST environment */ +#include +#include +#include +#include +#include +#define HOST_ADDRESS(x) (unsigned long)(x) + +#endif + +#endif /* __TYPE_SUPPORT_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/vamem.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/vamem.h new file mode 100644 index 0000000000000000000000000000000000000000..acf932e1f56394bd06c453aa43b21f10d644b5e2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/vamem.h @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VAMEM_H_INCLUDED__ +#define __VAMEM_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the VAMEM device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "vamem_local.h" + +#ifndef __INLINE_VAMEM__ +#define STORAGE_CLASS_VAMEM_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_VAMEM_C +#include "vamem_public.h" +#else /* __INLINE_VAMEM__ */ +#define STORAGE_CLASS_VAMEM_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_VAMEM_C STORAGE_CLASS_INLINE +#include "vamem_private.h" +#endif /* __INLINE_VAMEM__ */ + +#endif /* __VAMEM_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/vector_func.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/vector_func.h new file mode 100644 index 0000000000000000000000000000000000000000..5d3be31759e444be4e5a8f0cc9bbbcfbda80163f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/vector_func.h @@ -0,0 +1,39 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VECTOR_FUNC_H_INCLUDED__ +#define __VECTOR_FUNC_H_INCLUDED__ + +#include "storage_class.h" + +/* TODO: Later filters will be moved to types directory, + * and we should only include matrix_MxN types */ +#include "filters/filters_1.0/filter_2x2.h" +#include "filters/filters_1.0/filter_3x3.h" +#include "filters/filters_1.0/filter_4x4.h" +#include "filters/filters_1.0/filter_5x5.h" + +#include "vector_func_local.h" + +#ifndef __INLINE_VECTOR_FUNC__ +#define STORAGE_CLASS_VECTOR_FUNC_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_VECTOR_FUNC_C +#include "vector_func_public.h" +#else /* __INLINE_VECTOR_FUNC__ */ +#define STORAGE_CLASS_VECTOR_FUNC_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_VECTOR_FUNC_C STORAGE_CLASS_INLINE +#include "vector_func_private.h" +#endif /* __INLINE_VECTOR_FUNC__ */ + +#endif /* __VECTOR_FUNC_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/vector_ops.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/vector_ops.h new file mode 100644 index 0000000000000000000000000000000000000000..261f87378ce58f6491c9218113c48bba08652cca --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/vector_ops.h @@ -0,0 +1,32 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VECTOR_OPS_H_INCLUDED__ +#define __VECTOR_OPS_H_INCLUDED__ + +#include "storage_class.h" + +#include "vector_ops_local.h" + +#ifndef __INLINE_VECTOR_OPS__ +#define STORAGE_CLASS_VECTOR_OPS_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_VECTOR_OPS_C +#include "vector_ops_public.h" +#else /* __INLINE_VECTOR_OPS__ */ +#define STORAGE_CLASS_VECTOR_OPS_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_VECTOR_OPS_C STORAGE_CLASS_INLINE +#include "vector_ops_private.h" +#endif /* __INLINE_VECTOR_OPS__ */ + +#endif /* __VECTOR_OPS_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/vmem.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/vmem.h new file mode 100644 index 0000000000000000000000000000000000000000..79a36755bfd9785fe0796558e719756a5743f538 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/vmem.h @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __VMEM_H_INCLUDED__ +#define __VMEM_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the VMEM device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "vmem_local.h" + +#ifndef __INLINE_VMEM__ +#define STORAGE_CLASS_VMEM_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_VMEM_C +#include "vmem_public.h" +#else /* __INLINE_VMEM__ */ +#define STORAGE_CLASS_VMEM_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_VMEM_C STORAGE_CLASS_INLINE +#include "vmem_private.h" +#endif /* __INLINE_VMEM__ */ + +#endif /* __VMEM_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/xmem.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/xmem.h new file mode 100644 index 0000000000000000000000000000000000000000..9169e04f9b4b69f8d0d8329046c88b029e49055a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_include/xmem.h @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __XMEM_H_INCLUDED__ +#define __XMEM_H_INCLUDED__ + +/* + * This file is included on every cell {SP,ISP,host} and on every system + * that uses the XMEM device. It defines the API to DLI bridge + * + * System and cell specific interfaces and inline code are included + * conditionally through Makefile path settings. + * + * - . system and cell agnostic interfaces, constants and identifiers + * - public: system agnostic, cell specific interfaces + * - private: system dependent, cell specific interfaces & inline implementations + * - global: system specific constants and identifiers + * - local: system and cell specific constants and identifiers + */ + +#include "storage_class.h" + +#include "system_local.h" +#include "xmem_local.h" + +#ifndef __INLINE_XMEM__ +#define STORAGE_CLASS_XMEM_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_XMEM_C +#include "xmem_public.h" +#else /* __INLINE_XMEM__ */ +#define STORAGE_CLASS_XMEM_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_XMEM_C STORAGE_CLASS_INLINE +#include "xmem_private.h" +#endif /* __INLINE_XMEM__ */ + +#endif /* __XMEM_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/host/queue_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/host/queue_local.h new file mode 100644 index 0000000000000000000000000000000000000000..9f4060319b4b3b8c41ddbda18d73eb2263c0d7a5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/host/queue_local.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __QUEUE_LOCAL_H_INCLUDED__ +#define __QUEUE_LOCAL_H_INCLUDED__ + +#include "queue_global.h" + +#endif /* __QUEUE_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/host/queue_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/host/queue_private.h new file mode 100644 index 0000000000000000000000000000000000000000..2b396955cdadf4ed62e2bd32409eab07d0d2b1f1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/host/queue_private.h @@ -0,0 +1,18 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __QUEUE_PRIVATE_H_INCLUDED__ +#define __QUEUE_PRIVATE_H_INCLUDED__ + +#endif /* __QUEUE_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/host/tag.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/host/tag.c new file mode 100644 index 0000000000000000000000000000000000000000..9aa8c168a8036df07f16182125afa298e6ed43f6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/host/tag.c @@ -0,0 +1,95 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "tag.h" +#include /* NULL */ +#include +#include "tag_local.h" + +/** + * @brief Creates the tag description from the given parameters. + * @param[in] num_captures + * @param[in] skip + * @param[in] offset + * @param[out] tag_descr + */ +void +sh_css_create_tag_descr(int num_captures, + unsigned int skip, + int offset, + unsigned int exp_id, + struct sh_css_tag_descr *tag_descr) +{ + assert(tag_descr != NULL); + + tag_descr->num_captures = num_captures; + tag_descr->skip = skip; + tag_descr->offset = offset; + tag_descr->exp_id = exp_id; +} + +/** + * @brief Encodes the members of tag description into a 32-bit value. + * @param[in] tag Pointer to the tag description + * @return (unsigned int) Encoded 32-bit tag-info + */ +unsigned int +sh_css_encode_tag_descr(struct sh_css_tag_descr *tag) +{ + int num_captures; + unsigned int num_captures_sign; + unsigned int skip; + int offset; + unsigned int offset_sign; + unsigned int exp_id; + unsigned int encoded_tag; + + assert(tag != NULL); + + if (tag->num_captures < 0) { + num_captures = -tag->num_captures; + num_captures_sign = 1; + } else { + num_captures = tag->num_captures; + num_captures_sign = 0; + } + skip = tag->skip; + if (tag->offset < 0) { + offset = -tag->offset; + offset_sign = 1; + } else { + offset = tag->offset; + offset_sign = 0; + } + exp_id = tag->exp_id; + + if (exp_id != 0) + { + /* we encode either an exp_id or capture data */ + assert((num_captures == 0) && (skip == 0) && (offset == 0)); + + encoded_tag = TAG_EXP | (exp_id & 0xFF) << TAG_EXP_ID_SHIFT; + } + else + { + encoded_tag = TAG_CAP + | ((num_captures_sign & 0x00000001) << TAG_NUM_CAPTURES_SIGN_SHIFT) + | ((offset_sign & 0x00000001) << TAG_OFFSET_SIGN_SHIFT) + | ((num_captures & 0x000000FF) << TAG_NUM_CAPTURES_SHIFT) + | ((skip & 0x000000FF) << TAG_OFFSET_SHIFT) + | ((offset & 0x000000FF) << TAG_SKIP_SHIFT); + + } + return encoded_tag; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/host/tag_local.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/host/tag_local.h new file mode 100644 index 0000000000000000000000000000000000000000..01a8977c189e97c9e19270bbbf3507188c481348 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/host/tag_local.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TAG_LOCAL_H_INCLUDED__ +#define __TAG_LOCAL_H_INCLUDED__ + +#include "tag_global.h" + +#define SH_CSS_MINIMUM_TAG_ID (-1) + +#endif /* __TAG_LOCAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/host/tag_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/host/tag_private.h new file mode 100644 index 0000000000000000000000000000000000000000..0570a95ec5bf23bb7adb497bbf7ac7a580ca1b2b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/host/tag_private.h @@ -0,0 +1,18 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TAG_PRIVATE_H_INCLUDED__ +#define __TAG_PRIVATE_H_INCLUDED__ + +#endif /* __TAG_PRIVATE_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/queue_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/queue_global.h new file mode 100644 index 0000000000000000000000000000000000000000..61330daab73444a3956d186791ea8713b15635cc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/queue_global.h @@ -0,0 +1,19 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __QUEUE_GLOBAL_H_INCLUDED__ +#define __QUEUE_GLOBAL_H_INCLUDED__ + +#endif /* __QUEUE_GLOBAL_H_INCLUDED__ */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/socket_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/socket_global.h new file mode 100644 index 0000000000000000000000000000000000000000..2b7025e90250c9f56df3aed54ecb4705313c8583 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/socket_global.h @@ -0,0 +1,53 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SOCKET_GLOBAL_H_INCLUDED__ +#define __SOCKET_GLOBAL_H_INCLUDED__ + +#include "stream_buffer.h" + +/* define the socket port direction */ +typedef enum { + SOCKET_PORT_DIRECTION_NULL, + SOCKET_PORT_DIRECTION_IN, + SOCKET_PORT_DIRECTION_OUT +} socket_port_direction_t; + +/* pointer to the port's callout function */ +typedef void (*socket_port_callout_fp)(void); +typedef struct socket_port_s socket_port_t; +typedef struct socket_s socket_t; + +/* data structure of the socket port */ +struct socket_port_s { + unsigned channel; /* the port entity */ + socket_port_direction_t direction; /* the port direction */ + socket_port_callout_fp callout; /* the port callout function */ + + socket_t *socket; /* point to the socket */ + + struct { + unsigned data; + } buf; /* the buffer at the port */ +}; + +/* data structure of the socket */ +struct socket_s { + socket_port_t *in; /* the in-direction port */ + socket_port_t *out; /* the out-direction port */ + stream_buffer_t buf; /* the buffer between in-ports and out-ports */ +}; + +#endif /* __SOCKET_GLOBAL_H_INCLUDED__ */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/stream_buffer_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/stream_buffer_global.h new file mode 100644 index 0000000000000000000000000000000000000000..b9664b9608dcfb2e51e2b7498cfd6595889eb006 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/stream_buffer_global.h @@ -0,0 +1,26 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __STREAM_BUFFER_GLOBAL_H_INCLUDED__ +#define __STREAM_BUFFER_GLOBAL_H_INCLUDED__ + +typedef struct stream_buffer_s stream_buffer_t; +struct stream_buffer_s { + unsigned base; + unsigned limit; + unsigned top; +}; + +#endif /* __STREAM_BUFFER_GLOBAL_H_INCLUDED__ */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/sw_event_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/sw_event_global.h new file mode 100644 index 0000000000000000000000000000000000000000..c0d2efadbbe3ddff2df1cab934c15f8ad3fad783 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/sw_event_global.h @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SW_EVENT_GLOBAL_H_INCLUDED__ +#define __SW_EVENT_GLOBAL_H_INCLUDED__ + +#define MAX_NR_OF_PAYLOADS_PER_SW_EVENT 4 + +enum ia_css_psys_sw_event { + IA_CSS_PSYS_SW_EVENT_BUFFER_ENQUEUED, /* from host to SP */ + IA_CSS_PSYS_SW_EVENT_BUFFER_DEQUEUED, /* from SP to host */ + IA_CSS_PSYS_SW_EVENT_EVENT_DEQUEUED, /* from SP to host, one way only */ + IA_CSS_PSYS_SW_EVENT_START_STREAM, + IA_CSS_PSYS_SW_EVENT_STOP_STREAM, + IA_CSS_PSYS_SW_EVENT_MIPI_BUFFERS_READY, + IA_CSS_PSYS_SW_EVENT_UNLOCK_RAW_BUFFER, + IA_CSS_PSYS_SW_EVENT_STAGE_ENABLE_DISABLE /* for extension state change enable/disable */ +}; + +enum ia_css_isys_sw_event { + IA_CSS_ISYS_SW_EVENT_EVENT_DEQUEUED +}; + +#endif /* __SW_EVENT_GLOBAL_H_INCLUDED__ */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/tag_global.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/tag_global.h new file mode 100644 index 0000000000000000000000000000000000000000..fda457792c9ca1da70648804af0ca28ff1e7c482 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/hive_isp_css_shared/tag_global.h @@ -0,0 +1,56 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __TAG_GLOBAL_H_INCLUDED__ +#define __TAG_GLOBAL_H_INCLUDED__ + +/* offsets for encoding/decoding the tag into an uint32_t */ + +#define TAG_CAP 1 +#define TAG_EXP 2 + +#define TAG_NUM_CAPTURES_SIGN_SHIFT 6 +#define TAG_OFFSET_SIGN_SHIFT 7 +#define TAG_NUM_CAPTURES_SHIFT 8 +#define TAG_OFFSET_SHIFT 16 +#define TAG_SKIP_SHIFT 24 + +#define TAG_EXP_ID_SHIFT 8 + +/* Data structure containing the tagging information which is used in + * continuous mode to specify which frames should be captured. + * num_captures The number of RAW frames to be processed to + * YUV. Setting this to -1 will make continuous + * capture run until it is stopped. + * skip Skip N frames in between captures. This can be + * used to select a slower capture frame rate than + * the sensor output frame rate. + * offset Start the RAW-to-YUV processing at RAW buffer + * with this offset. This allows the user to + * process RAW frames that were captured in the + * past or future. + * exp_id Exposure id of the RAW frame to tag. + * + * NOTE: Either exp_id = 0 or all other fields are 0 + * (so yeah, this could be a union) + */ + +struct sh_css_tag_descr { + int num_captures; + unsigned int skip; + int offset; + unsigned int exp_id; +}; + +#endif /* __TAG_GLOBAL_H_INCLUDED__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css.h new file mode 100644 index 0000000000000000000000000000000000000000..f67626f5258c33be74f056a6de9374d35427e9d0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css.h @@ -0,0 +1,58 @@ +/* Release Version: irci_stable_candrpv_0415_20150521_0458 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_H_ +#define _IA_CSS_H_ + +/** @file + * This file is the starting point of the CSS-API. It includes all CSS-API + * header files. + */ + +#include "ia_css_3a.h" +#include "ia_css_acc_types.h" +#include "ia_css_buffer.h" +#include "ia_css_control.h" +#include "ia_css_device_access.h" +#include "ia_css_dvs.h" +#include "ia_css_env.h" +#include "ia_css_err.h" +#include "ia_css_event_public.h" +#include "ia_css_firmware.h" +#include "ia_css_frame_public.h" +#include "ia_css_input_port.h" +#include "ia_css_irq.h" +#include "ia_css_metadata.h" +#include "ia_css_mipi.h" +#include "ia_css_pipe_public.h" +#include "ia_css_prbs.h" +#include "ia_css_properties.h" +#include "ia_css_stream_format.h" +#include "ia_css_stream_public.h" +#include "ia_css_tpg.h" +#include "ia_css_lace_stat.h" +#include "ia_css_version.h" +#include "ia_css_mmu.h" +#include "ia_css_morph.h" +#include "ia_css_shading.h" +#include "ia_css_timer.h" + +/* + Please do not add code to this file. Public functionality is to be + exposed in a function/data type specific header file. + Please add to the appropriate header file or create a new one. + */ + +#endif /* _IA_CSS_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_3a.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_3a.h new file mode 100644 index 0000000000000000000000000000000000000000..a80a7dbaf712e333fc0543eeb468bf416723850e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_3a.h @@ -0,0 +1,188 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_3A_H +#define __IA_CSS_3A_H + +/** @file + * This file contains types used for 3A statistics + */ + +#include +#include "ia_css_types.h" +#include "ia_css_err.h" +#include "system_global.h" + +enum ia_css_3a_tables { + IA_CSS_S3A_TBL_HI, + IA_CSS_S3A_TBL_LO, + IA_CSS_RGBY_TBL, + IA_CSS_NUM_3A_TABLES +}; + +/** Structure that holds 3A statistics in the ISP internal + * format. Use ia_css_get_3a_statistics() to translate + * this to the format used on the host (3A library). + * */ +struct ia_css_isp_3a_statistics { + union { + struct { + ia_css_ptr s3a_tbl; + } dmem; + struct { + ia_css_ptr s3a_tbl_hi; + ia_css_ptr s3a_tbl_lo; + } vmem; + } data; + struct { + ia_css_ptr rgby_tbl; + } data_hmem; + uint32_t exp_id; /**< exposure id, to match statistics to a frame, + see ia_css_event_public.h for more detail. */ + uint32_t isp_config_id;/**< Unique ID to track which config was actually applied to a particular frame */ + ia_css_ptr data_ptr; /**< pointer to base of all data */ + uint32_t size; /**< total size of all data */ + uint32_t dmem_size; + uint32_t vmem_size; /**< both lo and hi have this size */ + uint32_t hmem_size; +}; +#define SIZE_OF_DMEM_STRUCT \ + (SIZE_OF_IA_CSS_PTR) + +#define SIZE_OF_VMEM_STRUCT \ + (2 * SIZE_OF_IA_CSS_PTR) + +#define SIZE_OF_DATA_UNION \ + (MAX(SIZE_OF_DMEM_STRUCT, SIZE_OF_VMEM_STRUCT)) + +#define SIZE_OF_DATA_HMEM_STRUCT \ + (SIZE_OF_IA_CSS_PTR) + +#define SIZE_OF_IA_CSS_ISP_3A_STATISTICS_STRUCT \ + (SIZE_OF_DATA_UNION + \ + SIZE_OF_DATA_HMEM_STRUCT + \ + sizeof(uint32_t) + \ + sizeof(uint32_t) + \ + SIZE_OF_IA_CSS_PTR + \ + 4 * sizeof(uint32_t)) + +/** Map with host-side pointers to ISP-format statistics. + * These pointers can either be copies of ISP data or memory mapped + * ISP pointers. + * All of the data behind these pointers is allocated contiguously, the + * allocated pointer is stored in the data_ptr field. The other fields + * point into this one block of data. + */ +struct ia_css_isp_3a_statistics_map { + void *data_ptr; /**< Pointer to start of memory */ + struct ia_css_3a_output *dmem_stats; + uint16_t *vmem_stats_hi; + uint16_t *vmem_stats_lo; + struct ia_css_bh_table *hmem_stats; + uint32_t size; /**< total size in bytes of data_ptr */ + uint32_t data_allocated; /**< indicate whether data_ptr + was allocated or not. */ +}; + +/** @brief Copy and translate 3A statistics from an ISP buffer to a host buffer + * @param[out] host_stats Host buffer. + * @param[in] isp_stats ISP buffer. + * @return error value if temporary memory cannot be allocated + * + * This copies 3a statistics from an ISP pointer to a host pointer and then + * translates some of the statistics, details depend on which ISP binary is + * used. + * Always use this function, never copy the buffer directly. + */ +enum ia_css_err +ia_css_get_3a_statistics(struct ia_css_3a_statistics *host_stats, + const struct ia_css_isp_3a_statistics *isp_stats); + +/** @brief Translate 3A statistics from ISP format to host format. + * @param[out] host_stats host-format statistics + * @param[in] isp_stats ISP-format statistics + * @return None + * + * This function translates statistics from the internal ISP-format to + * the host-format. This function does not include an additional copy + * step. + * */ +void +ia_css_translate_3a_statistics( + struct ia_css_3a_statistics *host_stats, + const struct ia_css_isp_3a_statistics_map *isp_stats); + +/* Convenience functions for alloc/free of certain datatypes */ + +/** @brief Allocate memory for the 3a statistics on the ISP + * @param[in] grid The grid. + * @return Pointer to the allocated 3a statistics buffer on the ISP +*/ +struct ia_css_isp_3a_statistics * +ia_css_isp_3a_statistics_allocate(const struct ia_css_3a_grid_info *grid); + +/** @brief Free the 3a statistics memory on the isp + * @param[in] me Pointer to the 3a statistics buffer on the ISP. + * @return None +*/ +void +ia_css_isp_3a_statistics_free(struct ia_css_isp_3a_statistics *me); + +/** @brief Allocate memory for the 3a statistics on the host + * @param[in] grid The grid. + * @return Pointer to the allocated 3a statistics buffer on the host +*/ +struct ia_css_3a_statistics * +ia_css_3a_statistics_allocate(const struct ia_css_3a_grid_info *grid); + +/** @brief Free the 3a statistics memory on the host + * @param[in] me Pointer to the 3a statistics buffer on the host. + * @return None + */ +void +ia_css_3a_statistics_free(struct ia_css_3a_statistics *me); + +/** @brief Allocate a 3a statistics map structure + * @param[in] isp_stats pointer to ISP 3a statistis struct + * @param[in] data_ptr host-side pointer to ISP 3a statistics. + * @return Pointer to the allocated 3a statistics map + * + * This function allocates the ISP 3a statistics map structure + * and uses the data_ptr as base pointer to set the appropriate + * pointers to all relevant subsets of the 3a statistics (dmem, + * vmem, hmem). + * If the data_ptr is NULL, this function will allocate the host-side + * memory. This information is stored in the struct and used in the + * ia_css_isp_3a_statistics_map_free() function to determine whether + * the memory should be freed or not. + * Note that this function does not allocate or map any ISP + * memory. +*/ +struct ia_css_isp_3a_statistics_map * +ia_css_isp_3a_statistics_map_allocate( + const struct ia_css_isp_3a_statistics *isp_stats, + void *data_ptr); + +/** @brief Free the 3a statistics map + * @param[in] me Pointer to the 3a statistics map + * @return None + * + * This function frees the map struct. If the data_ptr inside it + * was allocated inside ia_css_isp_3a_statistics_map_allocate(), it + * will be freed in this function. Otherwise it will not be freed. + */ +void +ia_css_isp_3a_statistics_map_free(struct ia_css_isp_3a_statistics_map *me); + +#endif /* __IA_CSS_3A_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_acc_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_acc_types.h new file mode 100644 index 0000000000000000000000000000000000000000..18f3a13bc1e7f82c4fae41b2a1bfb4dffd75b88d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_acc_types.h @@ -0,0 +1,468 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_ACC_TYPES_H +#define _IA_CSS_ACC_TYPES_H + +/** @file + * This file contains types used for acceleration + */ + +#include /* HAS_IRQ_MAP_VERSION_# */ +#include +#include +#include + +#include "ia_css_types.h" +#include "ia_css_frame_format.h" + +/* Should be included without the path. + However, that requires adding the path to numerous makefiles + that have nothing to do with isp parameters. + */ +#include "runtime/isp_param/interface/ia_css_isp_param_types.h" + +/* Types for the acceleration API. + * These should be moved to sh_css_internal.h once the old acceleration + * argument handling has been completed. + * After that, interpretation of these structures is no longer needed + * in the kernel and HAL. +*/ + +/** Type of acceleration. + */ +enum ia_css_acc_type { + IA_CSS_ACC_NONE, /**< Normal binary */ + IA_CSS_ACC_OUTPUT, /**< Accelerator stage on output frame */ + IA_CSS_ACC_VIEWFINDER, /**< Accelerator stage on viewfinder frame */ + IA_CSS_ACC_STANDALONE, /**< Stand-alone acceleration */ +}; + +/** Cells types + */ +enum ia_css_cell_type { + IA_CSS_SP0 = 0, + IA_CSS_SP1, + IA_CSS_ISP, + MAX_NUM_OF_CELLS +}; + +/** Firmware types. + */ +enum ia_css_fw_type { + ia_css_sp_firmware, /**< Firmware for the SP */ + ia_css_isp_firmware, /**< Firmware for the ISP */ + ia_css_bootloader_firmware, /**< Firmware for the BootLoader */ + ia_css_acc_firmware /**< Firmware for accelrations */ +}; + +struct ia_css_blob_descr; + +/** Blob descriptor. + * This structure describes an SP or ISP blob. + * It describes the test, data and bss sections as well as position in a + * firmware file. + * For convenience, it contains dynamic data after loading. + */ +struct ia_css_blob_info { + /**< Static blob data */ + uint32_t offset; /**< Blob offset in fw file */ + struct ia_css_isp_param_memory_offsets memory_offsets; /**< offset wrt hdr in bytes */ + uint32_t prog_name_offset; /**< offset wrt hdr in bytes */ + uint32_t size; /**< Size of blob */ + uint32_t padding_size; /**< total cummulative of bytes added due to section alignment */ + uint32_t icache_source; /**< Position of icache in blob */ + uint32_t icache_size; /**< Size of icache section */ + uint32_t icache_padding;/**< bytes added due to icache section alignment */ + uint32_t text_source; /**< Position of text in blob */ + uint32_t text_size; /**< Size of text section */ + uint32_t text_padding; /**< bytes added due to text section alignment */ + uint32_t data_source; /**< Position of data in blob */ + uint32_t data_target; /**< Start of data in SP dmem */ + uint32_t data_size; /**< Size of text section */ + uint32_t data_padding; /**< bytes added due to data section alignment */ + uint32_t bss_target; /**< Start position of bss in SP dmem */ + uint32_t bss_size; /**< Size of bss section */ + /**< Dynamic data filled by loader */ + CSS_ALIGN(const void *code, 8); /**< Code section absolute pointer within fw, code = icache + text */ + CSS_ALIGN(const void *data, 8); /**< Data section absolute pointer within fw, data = data + bss */ +}; + +struct ia_css_binary_input_info { + uint32_t min_width; + uint32_t min_height; + uint32_t max_width; + uint32_t max_height; + uint32_t source; /* memory, sensor, variable */ +}; + +struct ia_css_binary_output_info { + uint32_t min_width; + uint32_t min_height; + uint32_t max_width; + uint32_t max_height; + uint32_t num_chunks; + uint32_t variable_format; +}; + +struct ia_css_binary_internal_info { + uint32_t max_width; + uint32_t max_height; +}; + +struct ia_css_binary_bds_info { + uint32_t supported_bds_factors; +}; + +struct ia_css_binary_dvs_info { + uint32_t max_envelope_width; + uint32_t max_envelope_height; +}; + +struct ia_css_binary_vf_dec_info { + uint32_t is_variable; + uint32_t max_log_downscale; +}; + +struct ia_css_binary_s3a_info { + uint32_t s3atbl_use_dmem; + uint32_t fixed_s3a_deci_log; +}; + +/** DPC related binary info */ +struct ia_css_binary_dpc_info { + uint32_t bnr_lite; /**< bnr lite enable flag */ +}; + +struct ia_css_binary_iterator_info { + uint32_t num_stripes; + uint32_t row_stripes_height; + uint32_t row_stripes_overlap_lines; +}; + +struct ia_css_binary_address_info { + uint32_t isp_addresses; /* Address in ISP dmem */ + uint32_t main_entry; /* Address of entry fct */ + uint32_t in_frame; /* Address in ISP dmem */ + uint32_t out_frame; /* Address in ISP dmem */ + uint32_t in_data; /* Address in ISP dmem */ + uint32_t out_data; /* Address in ISP dmem */ + uint32_t sh_dma_cmd_ptr; /* In ISP dmem */ +}; + +struct ia_css_binary_uds_info { + uint16_t bpp; + uint16_t use_bci; + uint16_t use_str; + uint16_t woix; + uint16_t woiy; + uint16_t extra_out_vecs; + uint16_t vectors_per_line_in; + uint16_t vectors_per_line_out; + uint16_t vectors_c_per_line_in; + uint16_t vectors_c_per_line_out; + uint16_t vmem_gdc_in_block_height_y; + uint16_t vmem_gdc_in_block_height_c; + /* uint16_t padding; */ +}; + +struct ia_css_binary_pipeline_info { + uint32_t mode; + uint32_t isp_pipe_version; + uint32_t pipelining; + uint32_t c_subsampling; + uint32_t top_cropping; + uint32_t left_cropping; + uint32_t variable_resolution; +}; + +struct ia_css_binary_block_info { + uint32_t block_width; + uint32_t block_height; + uint32_t output_block_height; +}; + +/** Structure describing an ISP binary. + * It describes the capabilities of a binary, like the maximum resolution, + * support features, dma channels, uds features, etc. + * This part is to be used by the SP. + * Future refactoring should move binary properties to ia_css_binary_xinfo, + * thereby making the SP code more binary independent. + */ +struct ia_css_binary_info { + CSS_ALIGN(uint32_t id, 8); /* IA_CSS_BINARY_ID_* */ + struct ia_css_binary_pipeline_info pipeline; + struct ia_css_binary_input_info input; + struct ia_css_binary_output_info output; + struct ia_css_binary_internal_info internal; + struct ia_css_binary_bds_info bds; + struct ia_css_binary_dvs_info dvs; + struct ia_css_binary_vf_dec_info vf_dec; + struct ia_css_binary_s3a_info s3a; + struct ia_css_binary_dpc_info dpc_bnr; /**< DPC related binary info */ + struct ia_css_binary_iterator_info iterator; + struct ia_css_binary_address_info addresses; + struct ia_css_binary_uds_info uds; + struct ia_css_binary_block_info block; + struct ia_css_isp_param_isp_segments mem_initializers; +/* MW: Packing (related) bools in an integer ?? */ + struct { +#ifdef ISP2401 + uint8_t luma_only; + uint8_t input_yuv; + uint8_t input_raw; +#endif + uint8_t reduced_pipe; + uint8_t vf_veceven; + uint8_t dis; + uint8_t dvs_envelope; + uint8_t uds; + uint8_t dvs_6axis; + uint8_t block_output; + uint8_t streaming_dma; + uint8_t ds; + uint8_t bayer_fir_6db; + uint8_t raw_binning; + uint8_t continuous; + uint8_t s3a; + uint8_t fpnr; + uint8_t sc; + uint8_t macc; + uint8_t output; + uint8_t ref_frame; + uint8_t tnr; + uint8_t xnr; + uint8_t params; + uint8_t ca_gdc; + uint8_t isp_addresses; + uint8_t in_frame; + uint8_t out_frame; + uint8_t high_speed; + uint8_t dpc; + uint8_t padding[2]; + } enable; + struct { +/* DMA channel ID: [0,...,HIVE_ISP_NUM_DMA_CHANNELS> */ + uint8_t ref_y_channel; + uint8_t ref_c_channel; + uint8_t tnr_channel; + uint8_t tnr_out_channel; + uint8_t dvs_coords_channel; + uint8_t output_channel; + uint8_t c_channel; + uint8_t vfout_channel; + uint8_t vfout_c_channel; + uint8_t vfdec_bits_per_pixel; + uint8_t claimed_by_isp; + uint8_t padding[2]; + } dma; +}; + +/** Structure describing an ISP binary. + * It describes the capabilities of a binary, like the maximum resolution, + * support features, dma channels, uds features, etc. + */ +struct ia_css_binary_xinfo { + /* Part that is of interest to the SP. */ + struct ia_css_binary_info sp; + + /* Rest of the binary info, only interesting to the host. */ + enum ia_css_acc_type type; + CSS_ALIGN(int32_t num_output_formats, 8); + enum ia_css_frame_format output_formats[IA_CSS_FRAME_FORMAT_NUM]; + CSS_ALIGN(int32_t num_vf_formats, 8); /**< number of supported vf formats */ + enum ia_css_frame_format vf_formats[IA_CSS_FRAME_FORMAT_NUM]; /**< types of supported vf formats */ + uint8_t num_output_pins; + ia_css_ptr xmem_addr; + CSS_ALIGN(const struct ia_css_blob_descr *blob, 8); + CSS_ALIGN(uint32_t blob_index, 8); + CSS_ALIGN(union ia_css_all_memory_offsets mem_offsets, 8); + CSS_ALIGN(struct ia_css_binary_xinfo *next, 8); +}; + +/** Structure describing the Bootloader (an ISP binary). + * It contains several address, either in ddr, isp_dmem or + * the entry function in icache. + */ +struct ia_css_bl_info { + uint32_t num_dma_cmds; /**< Number of cmds sent by CSS */ + uint32_t dma_cmd_list; /**< Dma command list sent by CSS */ + uint32_t sw_state; /**< Polled from css */ + /* Entry functions */ + uint32_t bl_entry; /**< The SP entry function */ +}; + +/** Structure describing the SP binary. + * It contains several address, either in ddr, sp_dmem or + * the entry function in pmem. + */ +struct ia_css_sp_info { + uint32_t init_dmem_data; /**< data sect config, stored to dmem */ + uint32_t per_frame_data; /**< Per frame data, stored to dmem */ + uint32_t group; /**< Per pipeline data, loaded by dma */ + uint32_t output; /**< SP output data, loaded by dmem */ + uint32_t host_sp_queue; /**< Host <-> SP queues */ + uint32_t host_sp_com;/**< Host <-> SP commands */ + uint32_t isp_started; /**< Polled from sensor thread, csim only */ + uint32_t sw_state; /**< Polled from css */ + uint32_t host_sp_queues_initialized; /**< Polled from the SP */ + uint32_t sleep_mode; /**< different mode to halt SP */ + uint32_t invalidate_tlb; /**< inform SP to invalidate mmu TLB */ +#ifndef ISP2401 + uint32_t stop_copy_preview; /**< suspend copy and preview pipe when capture */ +#endif + uint32_t debug_buffer_ddr_address; /**< inform SP the address + of DDR debug queue */ + uint32_t perf_counter_input_system_error; /**< input system perf + counter array */ +#ifdef HAS_WATCHDOG_SP_THREAD_DEBUG + uint32_t debug_wait; /**< thread/pipe post mortem debug */ + uint32_t debug_stage; /**< thread/pipe post mortem debug */ + uint32_t debug_stripe; /**< thread/pipe post mortem debug */ +#endif + uint32_t threads_stack; /**< sp thread's stack pointers */ + uint32_t threads_stack_size; /**< sp thread's stack sizes */ + uint32_t curr_binary_id; /**< current binary id */ + uint32_t raw_copy_line_count; /**< raw copy line counter */ + uint32_t ddr_parameter_address; /**< acc param ddrptr, sp dmem */ + uint32_t ddr_parameter_size; /**< acc param size, sp dmem */ + /* Entry functions */ + uint32_t sp_entry; /**< The SP entry function */ + uint32_t tagger_frames_addr; /**< Base address of tagger state */ +}; + +/* The following #if is there because this header file is also included + by SP and ISP code but they do not need this data and HIVECC has alignment + issue with the firmware struct/union's. + More permanent solution will be to refactor this include. +*/ +#if !defined(__ISP) && !defined(__SP) +/** Accelerator firmware information. + */ +struct ia_css_acc_info { + uint32_t per_frame_data; /**< Dummy for now */ +}; + +/** Firmware information. + */ +union ia_css_fw_union { + struct ia_css_binary_xinfo isp; /**< ISP info */ + struct ia_css_sp_info sp; /**< SP info */ + struct ia_css_bl_info bl; /**< Bootloader info */ + struct ia_css_acc_info acc; /**< Accelerator info */ +}; + +/** Firmware information. + */ +struct ia_css_fw_info { + size_t header_size; /**< size of fw header */ + CSS_ALIGN(uint32_t type, 8); + union ia_css_fw_union info; /**< Binary info */ + struct ia_css_blob_info blob; /**< Blob info */ + /* Dynamic part */ + struct ia_css_fw_info *next; + CSS_ALIGN(uint32_t loaded, 8); /**< Firmware has been loaded */ + CSS_ALIGN(const uint8_t *isp_code, 8); /**< ISP pointer to code */ + /**< Firmware handle between user space and kernel */ + CSS_ALIGN(uint32_t handle, 8); + /**< Sections to copy from/to ISP */ + struct ia_css_isp_param_css_segments mem_initializers; + /**< Initializer for local ISP memories */ +}; + +struct ia_css_blob_descr { + const unsigned char *blob; + struct ia_css_fw_info header; + const char *name; + union ia_css_all_memory_offsets mem_offsets; +}; + +struct ia_css_acc_fw; + +/** Structure describing the SP binary of a stand-alone accelerator. + */ +struct ia_css_acc_sp { + void (*init)(struct ia_css_acc_fw *); /**< init for crun */ + uint32_t sp_prog_name_offset; /**< program name offset wrt hdr in bytes */ + uint32_t sp_blob_offset; /**< blob offset wrt hdr in bytes */ + void *entry; /**< Address of sp entry point */ + uint32_t *css_abort; /**< SP dmem abort flag */ + void *isp_code; /**< SP dmem address holding xmem + address of isp code */ + struct ia_css_fw_info fw; /**< SP fw descriptor */ + const uint8_t *code; /**< ISP pointer of allocated SP code */ +}; + +/** Acceleration firmware descriptor. + * This descriptor descibes either SP code (stand-alone), or + * ISP code (a separate pipeline stage). + */ +struct ia_css_acc_fw_hdr { + enum ia_css_acc_type type; /**< Type of accelerator */ + uint32_t isp_prog_name_offset; /**< program name offset wrt + header in bytes */ + uint32_t isp_blob_offset; /**< blob offset wrt header + in bytes */ + uint32_t isp_size; /**< Size of isp blob */ + const uint8_t *isp_code; /**< ISP pointer to code */ + struct ia_css_acc_sp sp; /**< Standalone sp code */ + /**< Firmware handle between user space and kernel */ + uint32_t handle; + struct ia_css_data parameters; /**< Current SP parameters */ +}; + +/** Firmware structure. + * This contains the header and actual blobs. + * For standalone, it contains SP and ISP blob. + * For a pipeline stage accelerator, it contains ISP code only. + * Since its members are variable size, their offsets are described in the + * header and computed using the access macros below. + */ +struct ia_css_acc_fw { + struct ia_css_acc_fw_hdr header; /**< firmware header */ + /* + int8_t isp_progname[]; **< ISP program name + int8_t sp_progname[]; **< SP program name, stand-alone only + uint8_t sp_code[]; **< SP blob, stand-alone only + uint8_t isp_code[]; **< ISP blob + */ +}; + +/* Access macros for firmware */ +#define IA_CSS_ACC_OFFSET(t, f, n) ((t)((uint8_t *)(f)+(f->header.n))) +#define IA_CSS_ACC_SP_PROG_NAME(f) IA_CSS_ACC_OFFSET(const char *, f, \ + sp.sp_prog_name_offset) +#define IA_CSS_ACC_ISP_PROG_NAME(f) IA_CSS_ACC_OFFSET(const char *, f, \ + isp_prog_name_offset) +#define IA_CSS_ACC_SP_CODE(f) IA_CSS_ACC_OFFSET(uint8_t *, f, \ + sp.sp_blob_offset) +#define IA_CSS_ACC_SP_DATA(f) (IA_CSS_ACC_SP_CODE(f) + \ + (f)->header.sp.fw.blob.data_source) +#define IA_CSS_ACC_ISP_CODE(f) IA_CSS_ACC_OFFSET(uint8_t*, f,\ + isp_blob_offset) +#define IA_CSS_ACC_ISP_SIZE(f) ((f)->header.isp_size) + +/* Binary name follows header immediately */ +#define IA_CSS_EXT_ISP_PROG_NAME(f) ((const char *)(f)+(f)->blob.prog_name_offset) +#define IA_CSS_EXT_ISP_MEM_OFFSETS(f) \ + ((const struct ia_css_memory_offsets *)((const char *)(f)+(f)->blob.mem_offsets)) + +#endif /* !defined(__ISP) && !defined(__SP) */ + +enum ia_css_sp_sleep_mode { + SP_DISABLE_SLEEP_MODE = 0, + SP_SLEEP_AFTER_FRAME = 1 << 0, + SP_SLEEP_AFTER_IRQ = 1 << 1 +}; +#endif /* _IA_CSS_ACC_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_buffer.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_buffer.h new file mode 100644 index 0000000000000000000000000000000000000000..f0db4ebadc0420ed99bd321ad6596943b7c38869 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_buffer.h @@ -0,0 +1,85 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BUFFER_H +#define __IA_CSS_BUFFER_H + +/** @file + * This file contains datastructures and types for buffers used in CSS + */ + +#include +#include "ia_css_types.h" +#include "ia_css_timer.h" + +/** Enumeration of buffer types. Buffers can be queued and de-queued + * to hand them over between IA and ISP. + */ +enum ia_css_buffer_type { + IA_CSS_BUFFER_TYPE_INVALID = -1, + IA_CSS_BUFFER_TYPE_3A_STATISTICS = 0, + IA_CSS_BUFFER_TYPE_DIS_STATISTICS, + IA_CSS_BUFFER_TYPE_LACE_STATISTICS, + IA_CSS_BUFFER_TYPE_INPUT_FRAME, + IA_CSS_BUFFER_TYPE_OUTPUT_FRAME, + IA_CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME, + IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME, + IA_CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME, + IA_CSS_BUFFER_TYPE_RAW_OUTPUT_FRAME, + IA_CSS_BUFFER_TYPE_CUSTOM_INPUT, + IA_CSS_BUFFER_TYPE_CUSTOM_OUTPUT, + IA_CSS_BUFFER_TYPE_METADATA, + IA_CSS_BUFFER_TYPE_PARAMETER_SET, + IA_CSS_BUFFER_TYPE_PER_FRAME_PARAMETER_SET, + IA_CSS_NUM_DYNAMIC_BUFFER_TYPE, + IA_CSS_NUM_BUFFER_TYPE +}; + +/* Driver API is not SP/ISP visible, 64 bit types not supported on hivecc */ +#if !defined(__SP) && !defined(__ISP) +/** Buffer structure. This is a container structure that enables content + * independent buffer queues and access functions. + */ +struct ia_css_buffer { + enum ia_css_buffer_type type; /**< Buffer type. */ + unsigned int exp_id; + /**< exposure id for this buffer; 0 = not available + see ia_css_event_public.h for more detail. */ + union { + struct ia_css_isp_3a_statistics *stats_3a; /**< 3A statistics & optionally RGBY statistics. */ + struct ia_css_isp_dvs_statistics *stats_dvs; /**< DVS statistics. */ + struct ia_css_isp_skc_dvs_statistics *stats_skc_dvs; /**< SKC DVS statistics. */ + struct ia_css_isp_lace_statistics *stats_lace; /**< LACE statistics. */ + struct ia_css_frame *frame; /**< Frame buffer. */ + struct ia_css_acc_param *custom_data; /**< Custom buffer. */ + struct ia_css_metadata *metadata; /**< Sensor metadata. */ + } data; /**< Buffer data pointer. */ + uint64_t driver_cookie; /**< cookie for the driver */ + struct ia_css_time_meas timing_data; /**< timing data (readings from the timer) */ + struct ia_css_clock_tick isys_eof_clock_tick; /**< ISYS's end of frame timer tick*/ +}; + +/** @brief Dequeue param buffers from sp2host_queue + * + * @return None + * + * This function must be called at every driver interrupt handler to prevent + * overflow of sp2host_queue. + */ +void +ia_css_dequeue_param_buffers(void); + +#endif /* !__SP && !__ISP */ + +#endif /* __IA_CSS_BUFFER_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_control.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_control.h new file mode 100644 index 0000000000000000000000000000000000000000..a15d3e3683419b30f494406b0e8a2f2f37a7ad1d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_control.h @@ -0,0 +1,157 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CONTROL_H +#define __IA_CSS_CONTROL_H + +/** @file + * This file contains functionality for starting and controlling CSS + */ + +#include +#include +#include +#include + +/** @brief Initialize the CSS API. + * @param[in] env Environment, provides functions to access the + * environment in which the CSS code runs. This is + * used for host side memory access and message + * printing. May not be NULL. + * @param[in] fw Firmware package containing the firmware for all + * predefined ISP binaries. + * if fw is NULL the firmware must be loaded before + * through a call of ia_css_load_firmware + * @param[in] l1_base Base index (isp2400) + * of the L1 page table. This is a physical + * address or index. + * @param[in] irq_type The type of interrupt to be used (edge or level) + * @return Returns IA_CSS_ERR_INTERNAL_ERROR in case of any + * errors and IA_CSS_SUCCESS otherwise. + * + * This function initializes the API which includes allocating and initializing + * internal data structures. This also interprets the firmware package. All + * contents of this firmware package are copied into local data structures, so + * the fw pointer could be freed after this function completes. + */ +enum ia_css_err ia_css_init( + const struct ia_css_env *env, + const struct ia_css_fw *fw, + uint32_t l1_base, + enum ia_css_irq_type irq_type); + +/** @brief Un-initialize the CSS API. + * @return None + * + * This function deallocates all memory that has been allocated by the CSS API + * Exception: if you explicitly loaded firmware through ia_css_load_firmware + * you need to call ia_css_unload_firmware to deallocate the memory reserved + * for the firmware. + * After this function is called, no other CSS functions should be called + * with the exception of ia_css_init which will re-initialize the CSS code, + * ia_css_unload_firmware to unload the firmware or ia_css_load_firmware + * to load new firmware + */ +void +ia_css_uninit(void); + +/** @brief Suspend CSS API for power down + * @return success or faulure code + * + * suspend shuts down the system by: + * unloading all the streams + * stopping SP + * performing uninit + * + * Currently stream memory is deallocated because of rmmgr issues. + * Need to come up with a bypass that will leave the streams intact. + */ +enum ia_css_err +ia_css_suspend(void); + +/** @brief Resume CSS API from power down + * @return success or failure code + * + * After a power cycle, this function will bring the CSS API back into + * a state where it can be started. + * This will re-initialize the hardware and all the streams. + * Call this function only after ia_css_suspend() has been called. + */ +enum ia_css_err +ia_css_resume(void); + +/** @brief Enable use of a separate queue for ISYS events. + * + * @param[in] enable: enable or disable use of separate ISYS event queues. + * @return error if called when SP is running. + * + * @deprecated{This is a temporary function that allows drivers to migrate to + * the use of the separate ISYS event queue. Once all drivers supports this, it + * will be made the default and this function will be removed. + * This function should only be called when the SP is not running, calling it + * when the SP is running will result in an error value being returned. } + */ +enum ia_css_err +ia_css_enable_isys_event_queue(bool enable); + +/** @brief Test whether the ISP has started. + * + * @return Boolean flag true if the ISP has started or false otherwise. + * + * Temporary function to poll whether the ISP has been started. Once it has, + * the sensor can also be started. */ +bool +ia_css_isp_has_started(void); + +/** @brief Test whether the SP has initialized. + * + * @return Boolean flag true if the SP has initialized or false otherwise. + * + * Temporary function to poll whether the SP has been initialized. Once it has, + * we can enqueue buffers. */ +bool +ia_css_sp_has_initialized(void); + +/** @brief Test whether the SP has terminated. + * + * @return Boolean flag true if the SP has terminated or false otherwise. + * + * Temporary function to poll whether the SP has been terminated. Once it has, + * we can switch mode. */ +bool +ia_css_sp_has_terminated(void); + +/** @brief start SP hardware + * + * @return IA_CSS_SUCCESS or error code upon error. + * + * It will boot the SP hardware and start multi-threading infrastructure. + * All threads will be started and blocked by semaphore. This function should + * be called before any ia_css_stream_start(). + */ +enum ia_css_err +ia_css_start_sp(void); + + +/** @brief stop SP hardware + * + * @return IA_CSS_SUCCESS or error code upon error. + * + * This function will terminate all threads and shut down SP. It should be + * called after all ia_css_stream_stop(). + */ +enum ia_css_err +ia_css_stop_sp(void); + +#endif /* __IA_CSS_CONTROL_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_device_access.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_device_access.c new file mode 100644 index 0000000000000000000000000000000000000000..21b842379accbbeca68509890e31209cbd1518b6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_device_access.c @@ -0,0 +1,95 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_device_access.h" +#include /* for uint*, size_t */ +#include /* for hrt_address */ +#include /* for ia_css_hw_access_env */ +#include /* for assert */ + +static struct ia_css_hw_access_env my_env; + +void +ia_css_device_access_init(const struct ia_css_hw_access_env *env) +{ + assert(env != NULL); + + my_env = *env; +} + +uint8_t +ia_css_device_load_uint8(const hrt_address addr) +{ + return my_env.load_8(addr); +} + +uint16_t +ia_css_device_load_uint16(const hrt_address addr) +{ + return my_env.load_16(addr); +} + +uint32_t +ia_css_device_load_uint32(const hrt_address addr) +{ + return my_env.load_32(addr); +} + +uint64_t +ia_css_device_load_uint64(const hrt_address addr) +{ + assert(0); + + (void)addr; + return 0; +} + +void +ia_css_device_store_uint8(const hrt_address addr, const uint8_t data) +{ + my_env.store_8(addr, data); +} + +void +ia_css_device_store_uint16(const hrt_address addr, const uint16_t data) +{ + my_env.store_16(addr, data); +} + +void +ia_css_device_store_uint32(const hrt_address addr, const uint32_t data) +{ + my_env.store_32(addr, data); +} + +void +ia_css_device_store_uint64(const hrt_address addr, const uint64_t data) +{ + assert(0); + + (void)addr; + (void)data; +} + +void +ia_css_device_load(const hrt_address addr, void *data, const size_t size) +{ + my_env.load(addr, data, (uint32_t)size); +} + +void +ia_css_device_store(const hrt_address addr, const void *data, const size_t size) +{ + my_env.store(addr, data, (uint32_t)size); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_device_access.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_device_access.h new file mode 100644 index 0000000000000000000000000000000000000000..8e4518008eaae15b629bc12724460b8e1fb1677a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_device_access.h @@ -0,0 +1,65 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_DEVICE_ACCESS_H +#define _IA_CSS_DEVICE_ACCESS_H + +/** @file + * File containing internal functions for the CSS-API to access the CSS device. + */ + +#include /* for uint*, size_t */ +#include /* for hrt_address */ +#include /* for ia_css_hw_access_env */ + +void +ia_css_device_access_init(const struct ia_css_hw_access_env *env); + +uint8_t +ia_css_device_load_uint8(const hrt_address addr); + +uint16_t +ia_css_device_load_uint16(const hrt_address addr); + +uint32_t +ia_css_device_load_uint32(const hrt_address addr); + +/* 64 bit types not supported by hivecc */ +#ifndef __HIVECC +uint64_t +ia_css_device_load_uint64(const hrt_address addr); +#endif + +void +ia_css_device_store_uint8(const hrt_address addr, const uint8_t data); + +void +ia_css_device_store_uint16(const hrt_address addr, const uint16_t data); + +void +ia_css_device_store_uint32(const hrt_address addr, const uint32_t data); + +/* 64 bit types not supported by hivecc */ +#ifndef __HIVECC +void +ia_css_device_store_uint64(const hrt_address addr, const uint64_t data); +#endif + +void +ia_css_device_load(const hrt_address addr, void *data, const size_t size); + +void +ia_css_device_store(const hrt_address addr, const void *data, const size_t size); + +#endif /* _IA_CSS_DEVICE_ACCESS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_dvs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_dvs.h new file mode 100644 index 0000000000000000000000000000000000000000..147bf81959d3b1a5e113ac01497c778b49f62253 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_dvs.h @@ -0,0 +1,299 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DVS_H +#define __IA_CSS_DVS_H + +/** @file + * This file contains types for DVS statistics + */ + +#include +#include "ia_css_types.h" +#include "ia_css_err.h" +#include "ia_css_stream_public.h" + +enum dvs_statistics_type { + DVS_STATISTICS, + DVS2_STATISTICS, + SKC_DVS_STATISTICS +}; + + +/** Structure that holds DVS statistics in the ISP internal + * format. Use ia_css_get_dvs_statistics() to translate + * this to the format used on the host (DVS engine). + * */ +struct ia_css_isp_dvs_statistics { + ia_css_ptr hor_proj; + ia_css_ptr ver_proj; + uint32_t hor_size; + uint32_t ver_size; + uint32_t exp_id; /**< see ia_css_event_public.h for more detail */ + ia_css_ptr data_ptr; /* base pointer containing all memory */ + uint32_t size; /* size of allocated memory in data_ptr */ +}; + +/** Structure that holds SKC DVS statistics in the ISP internal + * format. Use ia_css_dvs_statistics_get() to translate this to + * the format used on the host. + * */ +struct ia_css_isp_skc_dvs_statistics; + + +#define SIZE_OF_IA_CSS_ISP_DVS_STATISTICS_STRUCT \ + ((3 * SIZE_OF_IA_CSS_PTR) + \ + (4 * sizeof(uint32_t))) + +/* Map with host-side pointers to ISP-format statistics. + * These pointers can either be copies of ISP data or memory mapped + * ISP pointers. + * All of the data behind these pointers is allocatd contiguously, the + * allocated pointer is stored in the data_ptr field. The other fields + * point into this one block of data. + */ +struct ia_css_isp_dvs_statistics_map { + void *data_ptr; + int32_t *hor_proj; + int32_t *ver_proj; + uint32_t size; /* total size in bytes */ + uint32_t data_allocated; /* indicate whether data was allocated */ +}; + +union ia_css_dvs_statistics_isp { + struct ia_css_isp_dvs_statistics *p_dvs_statistics_isp; + struct ia_css_isp_skc_dvs_statistics *p_skc_dvs_statistics_isp; +}; + +union ia_css_dvs_statistics_host { + struct ia_css_dvs_statistics *p_dvs_statistics_host; + struct ia_css_dvs2_statistics *p_dvs2_statistics_host; + struct ia_css_skc_dvs_statistics *p_skc_dvs_statistics_host; +}; + +/** @brief Copy DVS statistics from an ISP buffer to a host buffer. + * @param[in] host_stats Host buffer + * @param[in] isp_stats ISP buffer + * @return error value if temporary memory cannot be allocated + * + * This may include a translation step as well depending + * on the ISP version. + * Always use this function, never copy the buffer directly. + * Note that this function uses the mem_load function from the CSS + * environment struct. + * In certain environments this may be slow. In those cases it is + * advised to map the ISP memory into a host-side pointer and use + * the ia_css_translate_dvs_statistics() function instead. + */ +enum ia_css_err +ia_css_get_dvs_statistics(struct ia_css_dvs_statistics *host_stats, + const struct ia_css_isp_dvs_statistics *isp_stats); + +/** @brief Translate DVS statistics from ISP format to host format + * @param[in] host_stats Host buffer + * @param[in] isp_stats ISP buffer + * @return None + * + * This function translates the dvs statistics from the ISP-internal + * format to the format used by the DVS library on the CPU. + * This function takes a host-side pointer as input. This can either + * point to a copy of the data or be a memory mapped pointer to the + * ISP memory pages. + */ +void +ia_css_translate_dvs_statistics( + struct ia_css_dvs_statistics *host_stats, + const struct ia_css_isp_dvs_statistics_map *isp_stats); + +/** @brief Copy DVS 2.0 statistics from an ISP buffer to a host buffer. + * @param[in] host_stats Host buffer + * @param[in] isp_stats ISP buffer + * @return error value if temporary memory cannot be allocated + * + * This may include a translation step as well depending + * on the ISP version. + * Always use this function, never copy the buffer directly. + * Note that this function uses the mem_load function from the CSS + * environment struct. + * In certain environments this may be slow. In those cases it is + * advised to map the ISP memory into a host-side pointer and use + * the ia_css_translate_dvs2_statistics() function instead. + */ +enum ia_css_err +ia_css_get_dvs2_statistics(struct ia_css_dvs2_statistics *host_stats, + const struct ia_css_isp_dvs_statistics *isp_stats); + +/** @brief Translate DVS2 statistics from ISP format to host format + * @param[in] host_stats Host buffer + * @param[in] isp_stats ISP buffer + * @return None + * + * This function translates the dvs2 statistics from the ISP-internal + * format to the format used by the DVS2 library on the CPU. + * This function takes a host-side pointer as input. This can either + * point to a copy of the data or be a memory mapped pointer to the + * ISP memory pages. + */ +void +ia_css_translate_dvs2_statistics( + struct ia_css_dvs2_statistics *host_stats, + const struct ia_css_isp_dvs_statistics_map *isp_stats); + +/** @brief Copy DVS statistics from an ISP buffer to a host buffer. + * @param[in] type - DVS statistics type + * @param[in] host_stats Host buffer + * @param[in] isp_stats ISP buffer + * @return None + */ +void +ia_css_dvs_statistics_get(enum dvs_statistics_type type, + union ia_css_dvs_statistics_host *host_stats, + const union ia_css_dvs_statistics_isp *isp_stats); + +/** @brief Allocate the DVS statistics memory on the ISP + * @param[in] grid The grid. + * @return Pointer to the allocated DVS statistics buffer on the ISP +*/ +struct ia_css_isp_dvs_statistics * +ia_css_isp_dvs_statistics_allocate(const struct ia_css_dvs_grid_info *grid); + +/** @brief Free the DVS statistics memory on the ISP + * @param[in] me Pointer to the DVS statistics buffer on the ISP. + * @return None +*/ +void +ia_css_isp_dvs_statistics_free(struct ia_css_isp_dvs_statistics *me); + +/** @brief Allocate the DVS 2.0 statistics memory + * @param[in] grid The grid. + * @return Pointer to the allocated DVS statistics buffer on the ISP +*/ +struct ia_css_isp_dvs_statistics * +ia_css_isp_dvs2_statistics_allocate(const struct ia_css_dvs_grid_info *grid); + +/** @brief Free the DVS 2.0 statistics memory + * @param[in] me Pointer to the DVS statistics buffer on the ISP. + * @return None +*/ +void +ia_css_isp_dvs2_statistics_free(struct ia_css_isp_dvs_statistics *me); + +/** @brief Allocate the DVS statistics memory on the host + * @param[in] grid The grid. + * @return Pointer to the allocated DVS statistics buffer on the host +*/ +struct ia_css_dvs_statistics * +ia_css_dvs_statistics_allocate(const struct ia_css_dvs_grid_info *grid); + +/** @brief Free the DVS statistics memory on the host + * @param[in] me Pointer to the DVS statistics buffer on the host. + * @return None +*/ +void +ia_css_dvs_statistics_free(struct ia_css_dvs_statistics *me); + +/** @brief Allocate the DVS coefficients memory + * @param[in] grid The grid. + * @return Pointer to the allocated DVS coefficients buffer +*/ +struct ia_css_dvs_coefficients * +ia_css_dvs_coefficients_allocate(const struct ia_css_dvs_grid_info *grid); + +/** @brief Free the DVS coefficients memory + * @param[in] me Pointer to the DVS coefficients buffer. + * @return None + */ +void +ia_css_dvs_coefficients_free(struct ia_css_dvs_coefficients *me); + +/** @brief Allocate the DVS 2.0 statistics memory on the host + * @param[in] grid The grid. + * @return Pointer to the allocated DVS 2.0 statistics buffer on the host + */ +struct ia_css_dvs2_statistics * +ia_css_dvs2_statistics_allocate(const struct ia_css_dvs_grid_info *grid); + +/** @brief Free the DVS 2.0 statistics memory + * @param[in] me Pointer to the DVS 2.0 statistics buffer on the host. + * @return None +*/ +void +ia_css_dvs2_statistics_free(struct ia_css_dvs2_statistics *me); + +/** @brief Allocate the DVS 2.0 coefficients memory + * @param[in] grid The grid. + * @return Pointer to the allocated DVS 2.0 coefficients buffer +*/ +struct ia_css_dvs2_coefficients * +ia_css_dvs2_coefficients_allocate(const struct ia_css_dvs_grid_info *grid); + +/** @brief Free the DVS 2.0 coefficients memory + * @param[in] me Pointer to the DVS 2.0 coefficients buffer. + * @return None +*/ +void +ia_css_dvs2_coefficients_free(struct ia_css_dvs2_coefficients *me); + +/** @brief Allocate the DVS 2.0 6-axis config memory + * @param[in] stream The stream. + * @return Pointer to the allocated DVS 6axis configuration buffer +*/ +struct ia_css_dvs_6axis_config * +ia_css_dvs2_6axis_config_allocate(const struct ia_css_stream *stream); + +/** @brief Free the DVS 2.0 6-axis config memory + * @param[in] dvs_6axis_config Pointer to the DVS 6axis configuration buffer + * @return None + */ +void +ia_css_dvs2_6axis_config_free(struct ia_css_dvs_6axis_config *dvs_6axis_config); + +/** @brief Allocate a dvs statistics map structure + * @param[in] isp_stats pointer to ISP dvs statistis struct + * @param[in] data_ptr host-side pointer to ISP dvs statistics. + * @return Pointer to the allocated dvs statistics map + * + * This function allocates the ISP dvs statistics map structure + * and uses the data_ptr as base pointer to set the appropriate + * pointers to all relevant subsets of the dvs statistics (dmem, + * vmem, hmem). + * If the data_ptr is NULL, this function will allocate the host-side + * memory. This information is stored in the struct and used in the + * ia_css_isp_dvs_statistics_map_free() function to determine whether + * the memory should be freed or not. + * Note that this function does not allocate or map any ISP + * memory. +*/ +struct ia_css_isp_dvs_statistics_map * +ia_css_isp_dvs_statistics_map_allocate( + const struct ia_css_isp_dvs_statistics *isp_stats, + void *data_ptr); + +/** @brief Free the dvs statistics map + * @param[in] me Pointer to the dvs statistics map + * @return None + * + * This function frees the map struct. If the data_ptr inside it + * was allocated inside ia_css_isp_dvs_statistics_map_allocate(), it + * will be freed in this function. Otherwise it will not be freed. + */ +void +ia_css_isp_dvs_statistics_map_free(struct ia_css_isp_dvs_statistics_map *me); + +/** @brief Allocate memory for the SKC DVS statistics on the ISP + * @return Pointer to the allocated ACC DVS statistics buffer on the ISP +*/ +struct ia_css_isp_skc_dvs_statistics *ia_css_skc_dvs_statistics_allocate(void); + +#endif /* __IA_CSS_DVS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_env.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_env.h new file mode 100644 index 0000000000000000000000000000000000000000..b4bf842963985eb22092ed9372dfa26a255d6fef --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_env.h @@ -0,0 +1,159 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ENV_H +#define __IA_CSS_ENV_H + +#include +#include /* va_list */ +#include "ia_css_types.h" +#include "ia_css_acc_types.h" + +/** @file + * This file contains prototypes for functions that need to be provided to the + * CSS-API host-code by the environment in which the CSS-API code runs. + */ + +/** Memory allocation attributes, for use in ia_css_css_mem_env. */ +enum ia_css_mem_attr { + IA_CSS_MEM_ATTR_CACHED = 1 << 0, + IA_CSS_MEM_ATTR_ZEROED = 1 << 1, + IA_CSS_MEM_ATTR_PAGEALIGN = 1 << 2, + IA_CSS_MEM_ATTR_CONTIGUOUS = 1 << 3, +}; + +/** Environment with function pointers for local IA memory allocation. + * This provides the CSS code with environment specific functionality + * for memory allocation of small local buffers such as local data structures. + * This is never expected to allocate more than one page of memory (4K bytes). + */ +struct ia_css_cpu_mem_env { + void * (*alloc)(size_t bytes, bool zero_mem); + /**< Allocation function with boolean argument to indicate whether + the allocated memory should be zeroed out or not, true (or 1) + meaning the memory given to CSS must be zeroed */ + void (*free)(void *ptr); + /**< Corresponding free function. The function must also accept + a NULL argument, similar to C89 free(). */ + void (*flush)(struct ia_css_acc_fw *fw); + /**< Flush function to flush the cache for given accelerator. */ +#ifdef ISP2401 + + #if !defined(__SVOS__) + /* a set of matching functions with additional debug params */ + void * (*alloc_ex)(size_t bytes, bool zero_mem, const char *caller_func, int caller_line); + /**< same as alloc above, only with additional debug parameters */ + void (*free_ex)(void *ptr, const char *caller_func, int caller_line); + /**< same as free above, only with additional debug parameters */ + #endif +#endif +}; + +/** Environment with function pointers for allocation of memory for the CSS. + * The CSS uses its own MMU which has its own set of page tables. These + * functions are expected to use and/or update those page tables. + * This type of memory allocation is expected to be used for large buffers + * for images and statistics. + * ISP pointers are always 32 bits whereas IA pointer widths will depend + * on the platform. + * Attributes can be a combination (OR'ed) of ia_css_mem_attr values. + */ +struct ia_css_css_mem_env { + ia_css_ptr(*alloc)(size_t bytes, uint32_t attributes); + /**< Allocate memory, cached or uncached, zeroed out or not. */ + void (*free)(ia_css_ptr ptr); + /**< Free ISP shared memory. The function must also accept + a NULL argument, similar to C89 free(). */ + int (*load)(ia_css_ptr ptr, void *data, size_t bytes); + /**< Load from ISP shared memory. This function is necessary because + the IA MMU does not share page tables with the ISP MMU. This means + that the IA needs to do the virtual-to-physical address + translation in software. This function performs this translation.*/ + int (*store)(ia_css_ptr ptr, const void *data, size_t bytes); + /**< Same as the above load function but then to write data into ISP + shared memory. */ + int (*set)(ia_css_ptr ptr, int c, size_t bytes); + /**< Set an ISP shared memory region to a particular value. Each byte + in this region will be set to this value. In most cases this is + used to zero-out memory sections in which case the argument c + would have the value zero. */ + ia_css_ptr (*mmap)(const void *ptr, const size_t size, + uint16_t attribute, void *context); + /**< Map an pre-allocated memory region to an address. */ +#ifdef ISP2401 + + /* a set of matching functions with additional debug params */ + ia_css_ptr(*alloc_ex)(size_t bytes, uint32_t attributes, const char *caller_func, int caller_line); + /**< same as alloc above, only with additional debug parameters */ + void (*free_ex)(ia_css_ptr ptr, const char *caller_func, int caller_line); + /**< same as free above, only with additional debug parameters */ + int (*load_ex)(ia_css_ptr ptr, void *data, size_t bytes, const char *caller_func, int caller_line); + /**< same as load above, only with additional debug parameters */ + int (*store_ex)(ia_css_ptr ptr, const void *data, size_t bytes, const char *caller_func, int caller_line); + /**< same as store above, only with additional debug parameters */ + int (*set_ex)(ia_css_ptr ptr, int c, size_t bytes, const char *caller_func, int caller_line); + /**< same as set above, only with additional debug parameters */ +#endif +}; + +/** Environment with function pointers to access the CSS hardware. This includes + * registers and local memories. + */ +struct ia_css_hw_access_env { + void (*store_8)(hrt_address addr, uint8_t data); + /**< Store an 8 bit value into an address in the CSS HW address space. + The address must be an 8 bit aligned address. */ + void (*store_16)(hrt_address addr, uint16_t data); + /**< Store a 16 bit value into an address in the CSS HW address space. + The address must be a 16 bit aligned address. */ + void (*store_32)(hrt_address addr, uint32_t data); + /**< Store a 32 bit value into an address in the CSS HW address space. + The address must be a 32 bit aligned address. */ + uint8_t (*load_8)(hrt_address addr); + /**< Load an 8 bit value from an address in the CSS HW address + space. The address must be an 8 bit aligned address. */ + uint16_t (*load_16)(hrt_address addr); + /**< Load a 16 bit value from an address in the CSS HW address + space. The address must be a 16 bit aligned address. */ + uint32_t (*load_32)(hrt_address addr); + /**< Load a 32 bit value from an address in the CSS HW address + space. The address must be a 32 bit aligned address. */ + void (*store)(hrt_address addr, const void *data, uint32_t bytes); + /**< Store a number of bytes into a byte-aligned address in the CSS HW address space. */ + void (*load)(hrt_address addr, void *data, uint32_t bytes); + /**< Load a number of bytes from a byte-aligned address in the CSS HW address space. */ +}; + +/** Environment with function pointers to print error and debug messages. + */ +struct ia_css_print_env { + int (*debug_print)(const char *fmt, va_list args); + /**< Print a debug message. */ + int (*error_print)(const char *fmt, va_list args); + /**< Print an error message.*/ +}; + +/** Environment structure. This includes function pointers to access several + * features provided by the environment in which the CSS API is used. + * This is used to run the camera IP in multiple platforms such as Linux, + * Windows and several simulation environments. + */ +struct ia_css_env { + struct ia_css_cpu_mem_env cpu_mem_env; /**< local malloc and free. */ + struct ia_css_css_mem_env css_mem_env; /**< CSS/ISP buffer alloc/free */ + struct ia_css_hw_access_env hw_access_env; /**< CSS HW access functions */ + struct ia_css_print_env print_env; /**< Message printing env. */ +}; + +#endif /* __IA_CSS_ENV_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_err.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_err.h new file mode 100644 index 0000000000000000000000000000000000000000..572e4e55c69e29cb405746d0894e4de4cd8046f4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_err.h @@ -0,0 +1,63 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ERR_H +#define __IA_CSS_ERR_H + +/** @file + * This file contains possible return values for most + * functions in the CSS-API. + */ + +/** Errors, these values are used as the return value for most + * functions in this API. + */ +enum ia_css_err { + IA_CSS_SUCCESS, + IA_CSS_ERR_INTERNAL_ERROR, + IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY, + IA_CSS_ERR_INVALID_ARGUMENTS, + IA_CSS_ERR_SYSTEM_NOT_IDLE, + IA_CSS_ERR_MODE_HAS_NO_VIEWFINDER, + IA_CSS_ERR_QUEUE_IS_FULL, + IA_CSS_ERR_QUEUE_IS_EMPTY, + IA_CSS_ERR_RESOURCE_NOT_AVAILABLE, + IA_CSS_ERR_RESOURCE_LIST_TO_SMALL, + IA_CSS_ERR_RESOURCE_ITEMS_STILL_ALLOCATED, + IA_CSS_ERR_RESOURCE_EXHAUSTED, + IA_CSS_ERR_RESOURCE_ALREADY_ALLOCATED, + IA_CSS_ERR_VERSION_MISMATCH, + IA_CSS_ERR_NOT_SUPPORTED +}; + +/** FW warnings. This enum contains a value for each warning that + * the SP FW could indicate potential performance issue + */ +enum ia_css_fw_warning { + IA_CSS_FW_WARNING_NONE, + IA_CSS_FW_WARNING_ISYS_QUEUE_FULL, /** < CSS system delayed because of insufficient space in the ISys queue. + This warning can be avoided by de-queing ISYS buffers more timely. */ + IA_CSS_FW_WARNING_PSYS_QUEUE_FULL, /** < CSS system delayed because of insufficient space in the PSys queue. + This warning can be avoided by de-queing PSYS buffers more timely. */ + IA_CSS_FW_WARNING_CIRCBUF_ALL_LOCKED, /** < CSS system delayed because of insufficient available buffers. + This warning can be avoided by unlocking locked frame-buffers more timely. */ + IA_CSS_FW_WARNING_EXP_ID_LOCKED, /** < Exposure ID skipped because the frame associated to it was still locked. + This warning can be avoided by unlocking locked frame-buffers more timely. */ + IA_CSS_FW_WARNING_TAG_EXP_ID_FAILED, /** < Exposure ID cannot be found on the circular buffer. + This warning can be avoided by unlocking locked frame-buffers more timely. */ + IA_CSS_FW_WARNING_FRAME_PARAM_MISMATCH, /** < Frame and param pair mismatched in tagger. + This warning can be avoided by providing a param set for each frame. */ +}; + +#endif /* __IA_CSS_ERR_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_event_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_event_public.h new file mode 100644 index 0000000000000000000000000000000000000000..aaf349772abef324a7a296f065b0ece97346cc3d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_event_public.h @@ -0,0 +1,196 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_EVENT_PUBLIC_H +#define __IA_CSS_EVENT_PUBLIC_H + +/** @file + * This file contains CSS-API events functionality + */ + +#include /* uint8_t */ +#include /* ia_css_err */ +#include /* ia_css_pipe */ +#include /* ia_css_timer */ + +/** The event type, distinguishes the kind of events that + * can are generated by the CSS system. + * + * !!!IMPORTANT!!! KEEP THE FOLLOWING IN SYNC: + * 1) "enum ia_css_event_type" (ia_css_event_public.h) + * 2) "enum sh_css_sp_event_type" (sh_css_internal.h) + * 3) "enum ia_css_event_type event_id_2_event_mask" (event_handler.sp.c) + * 4) "enum ia_css_event_type convert_event_sp_to_host_domain" (sh_css.c) + */ +enum ia_css_event_type { + IA_CSS_EVENT_TYPE_OUTPUT_FRAME_DONE = 1 << 0, + /**< Output frame ready. */ + IA_CSS_EVENT_TYPE_SECOND_OUTPUT_FRAME_DONE = 1 << 1, + /**< Second output frame ready. */ + IA_CSS_EVENT_TYPE_VF_OUTPUT_FRAME_DONE = 1 << 2, + /**< Viewfinder Output frame ready. */ + IA_CSS_EVENT_TYPE_SECOND_VF_OUTPUT_FRAME_DONE = 1 << 3, + /**< Second viewfinder Output frame ready. */ + IA_CSS_EVENT_TYPE_3A_STATISTICS_DONE = 1 << 4, + /**< Indication that 3A statistics are available. */ + IA_CSS_EVENT_TYPE_DIS_STATISTICS_DONE = 1 << 5, + /**< Indication that DIS statistics are available. */ + IA_CSS_EVENT_TYPE_PIPELINE_DONE = 1 << 6, + /**< Pipeline Done event, sent after last pipeline stage. */ + IA_CSS_EVENT_TYPE_FRAME_TAGGED = 1 << 7, + /**< Frame tagged. */ + IA_CSS_EVENT_TYPE_INPUT_FRAME_DONE = 1 << 8, + /**< Input frame ready. */ + IA_CSS_EVENT_TYPE_METADATA_DONE = 1 << 9, + /**< Metadata ready. */ + IA_CSS_EVENT_TYPE_LACE_STATISTICS_DONE = 1 << 10, + /**< Indication that LACE statistics are available. */ + IA_CSS_EVENT_TYPE_ACC_STAGE_COMPLETE = 1 << 11, + /**< Extension stage complete. */ + IA_CSS_EVENT_TYPE_TIMER = 1 << 12, + /**< Timer event for measuring the SP side latencies. It contains the + 32-bit timer value from the SP */ + IA_CSS_EVENT_TYPE_PORT_EOF = 1 << 13, + /**< End Of Frame event, sent when in buffered sensor mode. */ + IA_CSS_EVENT_TYPE_FW_WARNING = 1 << 14, + /**< Performance warning encounter by FW */ + IA_CSS_EVENT_TYPE_FW_ASSERT = 1 << 15, + /**< Assertion hit by FW */ +}; + +#define IA_CSS_EVENT_TYPE_NONE 0 + +/** IA_CSS_EVENT_TYPE_ALL is a mask for all pipe related events. + * The other events (such as PORT_EOF) cannot be enabled/disabled + * and are hence excluded from this macro. + */ +#define IA_CSS_EVENT_TYPE_ALL \ + (IA_CSS_EVENT_TYPE_OUTPUT_FRAME_DONE | \ + IA_CSS_EVENT_TYPE_SECOND_OUTPUT_FRAME_DONE | \ + IA_CSS_EVENT_TYPE_VF_OUTPUT_FRAME_DONE | \ + IA_CSS_EVENT_TYPE_SECOND_VF_OUTPUT_FRAME_DONE | \ + IA_CSS_EVENT_TYPE_3A_STATISTICS_DONE | \ + IA_CSS_EVENT_TYPE_DIS_STATISTICS_DONE | \ + IA_CSS_EVENT_TYPE_PIPELINE_DONE | \ + IA_CSS_EVENT_TYPE_FRAME_TAGGED | \ + IA_CSS_EVENT_TYPE_INPUT_FRAME_DONE | \ + IA_CSS_EVENT_TYPE_METADATA_DONE | \ + IA_CSS_EVENT_TYPE_LACE_STATISTICS_DONE | \ + IA_CSS_EVENT_TYPE_ACC_STAGE_COMPLETE) + +/** The event struct, container for the event type and its related values. + * Depending on the event type, either pipe or port will be filled. + * Pipeline related events (like buffer/frame events) will return a valid and filled pipe handle. + * For non pipeline related events (but i.e. stream specific, like EOF event), the port will be + * filled. + */ +struct ia_css_event { + struct ia_css_pipe *pipe; + /**< Pipe handle on which event happened, NULL for non pipe related + events. */ + enum ia_css_event_type type; + /**< Type of Event, always valid/filled. */ + uint8_t port; + /**< Port number for EOF event (not valid for other events). */ + uint8_t exp_id; + /**< Exposure id for EOF/FRAME_TAGGED/FW_WARNING event (not valid for other events) + The exposure ID is unique only within a logical stream and it is + only generated on systems that have an input system (such as 2400 + and 2401). + Most outputs produced by the CSS are tagged with an exposure ID. + This allows users of the CSS API to keep track of which buffer + was generated from which sensor output frame. This includes: + EOF event, output frames, 3A statistics, DVS statistics and + sensor metadata. + Exposure IDs start at IA_CSS_MIN_EXPOSURE_ID, increment by one + until IA_CSS_MAX_EXPOSURE_ID is reached, after that they wrap + around to IA_CSS_MIN_EXPOSURE_ID again. + Note that in case frames are dropped, this will not be reflected + in the exposure IDs. Therefor applications should not use this + to detect frame drops. */ + uint32_t fw_handle; + /**< Firmware Handle for ACC_STAGE_COMPLETE event (not valid for other + events). */ + enum ia_css_fw_warning fw_warning; + /**< Firmware warning code, only for WARNING events. */ + uint8_t fw_assert_module_id; + /**< Firmware module id, only for ASSERT events, should be logged by driver. */ + uint16_t fw_assert_line_no; + /**< Firmware line number, only for ASSERT events, should be logged by driver. */ + clock_value_t timer_data; + /**< For storing the full 32-bit of the timer value. Valid only for TIMER + event */ + uint8_t timer_code; + /**< For storing the code of the TIMER event. Valid only for + TIMER event */ + uint8_t timer_subcode; + /**< For storing the subcode of the TIMER event. Valid only + for TIMER event */ +}; + +/** @brief Dequeue a PSYS event from the CSS system. + * + * @param[out] event Pointer to the event struct which will be filled by + * this function if an event is available. + * @return IA_CSS_ERR_QUEUE_IS_EMPTY if no events are + * available or + * IA_CSS_SUCCESS otherwise. + * + * This function dequeues an event from the PSYS event queue. The queue is + * between the Host CPU and the CSS system. This function can be + * called after an interrupt has been generated that signalled that a new event + * was available and can be used in a polling-like situation where the NO_EVENT + * return value is used to determine whether an event was available or not. + */ +enum ia_css_err +ia_css_dequeue_psys_event(struct ia_css_event *event); + +/** @brief Dequeue an event from the CSS system. + * + * @param[out] event Pointer to the event struct which will be filled by + * this function if an event is available. + * @return IA_CSS_ERR_QUEUE_IS_EMPTY if no events are + * available or + * IA_CSS_SUCCESS otherwise. + * + * deprecated{Use ia_css_dequeue_psys_event instead}. + * Unless the isys event queue is explicitly enabled, this function will + * dequeue both isys (EOF) and psys events (all others). + */ +enum ia_css_err +ia_css_dequeue_event(struct ia_css_event *event); + +/** @brief Dequeue an ISYS event from the CSS system. + * + * @param[out] event Pointer to the event struct which will be filled by + * this function if an event is available. + * @return IA_CSS_ERR_QUEUE_IS_EMPTY if no events are + * available or + * IA_CSS_SUCCESS otherwise. + * + * This function dequeues an event from the ISYS event queue. The queue is + * between host and the CSS system. + * Unlike the ia_css_dequeue_event() function, this function can be called + * directly from an interrupt service routine (ISR) and it is safe to call + * this function in parallel with other CSS API functions (but only one + * call to this function should be in flight at any point in time). + * + * The reason for having the ISYS events separate is to prevent them from + * incurring additional latency due to locks being held by other CSS API + * functions. + */ +enum ia_css_err +ia_css_dequeue_isys_event(struct ia_css_event *event); + +#endif /* __IA_CSS_EVENT_PUBLIC_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_firmware.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_firmware.h new file mode 100644 index 0000000000000000000000000000000000000000..06d375a09be27b83705adc9feae8b1eaac263e79 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_firmware.h @@ -0,0 +1,74 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FIRMWARE_H +#define __IA_CSS_FIRMWARE_H + +/** @file + * This file contains firmware loading/unloading support functionality + */ + +#include "ia_css_err.h" +#include "ia_css_env.h" + +/** CSS firmware package structure. + */ +struct ia_css_fw { + void *data; /**< pointer to the firmware data */ + unsigned int bytes; /**< length in bytes of firmware data */ +}; + +/** @brief Loads the firmware + * @param[in] env Environment, provides functions to access the + * environment in which the CSS code runs. This is + * used for host side memory access and message + * printing. + * @param[in] fw Firmware package containing the firmware for all + * predefined ISP binaries. + * @return Returns IA_CSS_ERR_INTERNAL_ERROR in case of any + * errors and IA_CSS_SUCCESS otherwise. + * + * This function interprets the firmware package. All + * contents of this firmware package are copied into local data structures, so + * the fw pointer could be freed after this function completes. + * + * Rationale for this function is that it can be called before ia_css_init, and thus + * speeds up ia_css_init (ia_css_init is called each time a stream is created but the + * firmware only needs to be loaded once). + */ +enum ia_css_err +ia_css_load_firmware(const struct ia_css_env *env, + const struct ia_css_fw *fw); + +/** @brief Unloads the firmware + * @return None + * + * This function unloads the firmware loaded by ia_css_load_firmware. + * It is pointless to call this function if no firmware is loaded, + * but it won't harm. Use this to deallocate all memory associated with the firmware. + */ +void +ia_css_unload_firmware(void); + +/** @brief Checks firmware version + * @param[in] fw Firmware package containing the firmware for all + * predefined ISP binaries. + * @return Returns true when the firmware version matches with the CSS + * host code version and returns false otherwise. + * This function checks if the firmware package version matches with the CSS host code version. + */ +bool +ia_css_check_firmware_version(const struct ia_css_fw *fw); + +#endif /* __IA_CSS_FIRMWARE_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frac.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frac.h new file mode 100644 index 0000000000000000000000000000000000000000..da9c60144c6dcaf6fe075ee626e7c49ed60ec301 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frac.h @@ -0,0 +1,37 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_FRAC_H +#define _IA_CSS_FRAC_H + +/** @file + * This file contains typedefs used for fractional numbers + */ + +#include + +/* Fixed point types. + * NOTE: the 16 bit fixed point types actually occupy 32 bits + * to save on extension operations in the ISP code. + */ +/** Unsigned fixed point value, 0 integer bits, 16 fractional bits */ +typedef uint32_t ia_css_u0_16; +/** Unsigned fixed point value, 5 integer bits, 11 fractional bits */ +typedef uint32_t ia_css_u5_11; +/** Unsigned fixed point value, 8 integer bits, 8 fractional bits */ +typedef uint32_t ia_css_u8_8; +/** Signed fixed point value, 0 integer bits, 15 fractional bits */ +typedef int32_t ia_css_s0_15; + +#endif /* _IA_CSS_FRAC_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frame_format.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frame_format.h new file mode 100644 index 0000000000000000000000000000000000000000..d534fbd913803ab37812a4b09f98396d56ab00e3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frame_format.h @@ -0,0 +1,101 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FRAME_FORMAT_H +#define __IA_CSS_FRAME_FORMAT_H + +/** @file + * This file contains information about formats supported in the ISP + */ + +/** Frame formats, some of these come from fourcc.org, others are + better explained by video4linux2. The NV11 seems to be described only + on MSDN pages, but even those seem to be gone now. + Frames can come in many forms, the main categories are RAW, RGB and YUV + (or YCbCr). The YUV frames come in 4 flavors, determined by how the U and V + values are subsampled: + 1. YUV420: hor = 2, ver = 2 + 2. YUV411: hor = 4, ver = 1 + 3. YUV422: hor = 2, ver = 1 + 4. YUV444: hor = 1, ver = 1 + + Warning: not all frame formats are supported as input or output to/from ISP. + Some of these formats are therefore not defined in the output table module. + Modifications in below frame format enum can require modifications in the + output table module. + + Warning2: Throughout the CSS code assumptions are made on the order + of formats in this enumeration type, or some sort of copy is maintained. + The following files are identified: + - FileSupport.h + - css/isp/kernels/fc/fc_1.0/formats.isp.c + - css/isp/kernels/output/output_1.0/output_table.isp.c + - css/isp/kernels/output/sc_output_1.0/formats.hive.c + - css/isp/modes/interface/isp_formats.isp.h + - css/bxt_sandbox/psyspoc/interface/ia_css_pg_info.h + - css/bxt_sandbox/psysapi/data/interface/ia_css_program_group_data.h + - css/bxt_sandbox/isysapi/interface/ia_css_isysapi_fw_types.h +*/ +enum ia_css_frame_format { + IA_CSS_FRAME_FORMAT_NV11 = 0, /**< 12 bit YUV 411, Y, UV plane */ + IA_CSS_FRAME_FORMAT_NV12, /**< 12 bit YUV 420, Y, UV plane */ + IA_CSS_FRAME_FORMAT_NV12_16, /**< 16 bit YUV 420, Y, UV plane */ + IA_CSS_FRAME_FORMAT_NV12_TILEY, /**< 12 bit YUV 420, Intel proprietary tiled format, TileY */ + IA_CSS_FRAME_FORMAT_NV16, /**< 16 bit YUV 422, Y, UV plane */ + IA_CSS_FRAME_FORMAT_NV21, /**< 12 bit YUV 420, Y, VU plane */ + IA_CSS_FRAME_FORMAT_NV61, /**< 16 bit YUV 422, Y, VU plane */ + IA_CSS_FRAME_FORMAT_YV12, /**< 12 bit YUV 420, Y, V, U plane */ + IA_CSS_FRAME_FORMAT_YV16, /**< 16 bit YUV 422, Y, V, U plane */ + IA_CSS_FRAME_FORMAT_YUV420, /**< 12 bit YUV 420, Y, U, V plane */ + IA_CSS_FRAME_FORMAT_YUV420_16, /**< yuv420, 16 bits per subpixel */ + IA_CSS_FRAME_FORMAT_YUV422, /**< 16 bit YUV 422, Y, U, V plane */ + IA_CSS_FRAME_FORMAT_YUV422_16, /**< yuv422, 16 bits per subpixel */ + IA_CSS_FRAME_FORMAT_UYVY, /**< 16 bit YUV 422, UYVY interleaved */ + IA_CSS_FRAME_FORMAT_YUYV, /**< 16 bit YUV 422, YUYV interleaved */ + IA_CSS_FRAME_FORMAT_YUV444, /**< 24 bit YUV 444, Y, U, V plane */ + IA_CSS_FRAME_FORMAT_YUV_LINE, /**< Internal format, 2 y lines followed + by a uvinterleaved line */ + IA_CSS_FRAME_FORMAT_RAW, /**< RAW, 1 plane */ + IA_CSS_FRAME_FORMAT_RGB565, /**< 16 bit RGB, 1 plane. Each 3 sub + pixels are packed into one 16 bit + value, 5 bits for R, 6 bits for G + and 5 bits for B. */ + IA_CSS_FRAME_FORMAT_PLANAR_RGB888, /**< 24 bit RGB, 3 planes */ + IA_CSS_FRAME_FORMAT_RGBA888, /**< 32 bit RGBA, 1 plane, A=Alpha + (alpha is unused) */ + IA_CSS_FRAME_FORMAT_QPLANE6, /**< Internal, for advanced ISP */ + IA_CSS_FRAME_FORMAT_BINARY_8, /**< byte stream, used for jpeg. For + frames of this type, we set the + height to 1 and the width to the + number of allocated bytes. */ + IA_CSS_FRAME_FORMAT_MIPI, /**< MIPI frame, 1 plane */ + IA_CSS_FRAME_FORMAT_RAW_PACKED, /**< RAW, 1 plane, packed */ + IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8, /**< 8 bit per Y/U/V. + Y odd line; UYVY + interleaved even line */ + IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8, /**< Legacy YUV420. UY odd + line; VY even line */ + IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_10 /**< 10 bit per Y/U/V. Y odd + line; UYVY interleaved + even line */ +}; + +/* NOTE: IA_CSS_FRAME_FORMAT_NUM was purposely defined outside of enum type ia_css_frame_format, */ +/* because of issues this would cause with the Clockwork code checking tool. */ +#define IA_CSS_FRAME_FORMAT_NUM (IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_10 + 1) + +/** Number of valid output frame formats for ISP **/ +#define IA_CSS_FRAME_OUT_FORMAT_NUM (IA_CSS_FRAME_FORMAT_RGBA888 + 1) + +#endif /* __IA_CSS_FRAME_FORMAT_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frame_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frame_public.h new file mode 100644 index 0000000000000000000000000000000000000000..92f2389176b2e0f825cdc94cb954340fb8ead303 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_frame_public.h @@ -0,0 +1,365 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FRAME_PUBLIC_H +#define __IA_CSS_FRAME_PUBLIC_H + +/** @file + * This file contains structs to describe various frame-formats supported by the ISP. + */ + +#include +#include "ia_css_err.h" +#include "ia_css_types.h" +#include "ia_css_frame_format.h" +#include "ia_css_buffer.h" + +/** For RAW input, the bayer order needs to be specified separately. There + * are 4 possible orders. The name is constructed by taking the first two + * colors on the first line and the first two colors from the second line. + */ +enum ia_css_bayer_order { + IA_CSS_BAYER_ORDER_GRBG, /**< GRGRGRGRGR .. BGBGBGBGBG */ + IA_CSS_BAYER_ORDER_RGGB, /**< RGRGRGRGRG .. GBGBGBGBGB */ + IA_CSS_BAYER_ORDER_BGGR, /**< BGBGBGBGBG .. GRGRGRGRGR */ + IA_CSS_BAYER_ORDER_GBRG, /**< GBGBGBGBGB .. RGRGRGRGRG */ +}; +#define IA_CSS_BAYER_ORDER_NUM (IA_CSS_BAYER_ORDER_GBRG + 1) + +/** Frame plane structure. This describes one plane in an image + * frame buffer. + */ +struct ia_css_frame_plane { + unsigned int height; /**< height of a plane in lines */ + unsigned int width; /**< width of a line, in DMA elements, note that + for RGB565 the three subpixels are stored in + one element. For all other formats this is + the number of subpixels per line. */ + unsigned int stride; /**< stride of a line in bytes */ + unsigned int offset; /**< offset in bytes to start of frame data. + offset is wrt data field in ia_css_frame */ +}; + +/** Binary "plane". This is used to story binary streams such as jpeg + * images. This is not actually a real plane. + */ +struct ia_css_frame_binary_plane { + unsigned int size; /**< number of bytes in the stream */ + struct ia_css_frame_plane data; /**< plane */ +}; + +/** Container for planar YUV frames. This contains 3 planes. + */ +struct ia_css_frame_yuv_planes { + struct ia_css_frame_plane y; /**< Y plane */ + struct ia_css_frame_plane u; /**< U plane */ + struct ia_css_frame_plane v; /**< V plane */ +}; + +/** Container for semi-planar YUV frames. + */ +struct ia_css_frame_nv_planes { + struct ia_css_frame_plane y; /**< Y plane */ + struct ia_css_frame_plane uv; /**< UV plane */ +}; + +/** Container for planar RGB frames. Each color has its own plane. + */ +struct ia_css_frame_rgb_planes { + struct ia_css_frame_plane r; /**< Red plane */ + struct ia_css_frame_plane g; /**< Green plane */ + struct ia_css_frame_plane b; /**< Blue plane */ +}; + +/** Container for 6-plane frames. These frames are used internally + * in the advanced ISP only. + */ +struct ia_css_frame_plane6_planes { + struct ia_css_frame_plane r; /**< Red plane */ + struct ia_css_frame_plane r_at_b; /**< Red at blue plane */ + struct ia_css_frame_plane gr; /**< Red-green plane */ + struct ia_css_frame_plane gb; /**< Blue-green plane */ + struct ia_css_frame_plane b; /**< Blue plane */ + struct ia_css_frame_plane b_at_r; /**< Blue at red plane */ +}; + +/* Crop info struct - stores the lines to be cropped in isp */ +struct ia_css_crop_info { + /* the final start column and start line + * sum of lines to be cropped + bayer offset + */ + unsigned int start_column; + unsigned int start_line; +}; + +/** Frame info struct. This describes the contents of an image frame buffer. + */ +struct ia_css_frame_info { + struct ia_css_resolution res; /**< Frame resolution (valid data) */ + unsigned int padded_width; /**< stride of line in memory (in pixels) */ + enum ia_css_frame_format format; /**< format of the frame data */ + unsigned int raw_bit_depth; /**< number of valid bits per pixel, + only valid for RAW bayer frames */ + enum ia_css_bayer_order raw_bayer_order; /**< bayer order, only valid + for RAW bayer frames */ + /* the params below are computed based on bayer_order + * we can remove the raw_bayer_order if it is redundant + * keeping it for now as bxt and fpn code seem to use it + */ + struct ia_css_crop_info crop_info; +}; + +#define IA_CSS_BINARY_DEFAULT_FRAME_INFO \ +{ \ + {0, /* width */ \ + 0}, /* height */ \ + 0, /* padded_width */ \ + IA_CSS_FRAME_FORMAT_NUM, /* format */ \ + 0, /* raw_bit_depth */ \ + IA_CSS_BAYER_ORDER_NUM, /* raw_bayer_order */ \ + {0, /*start col */ \ + 0}, /*start line */ \ +} + +/** + * Specifies the DVS loop delay in "frame periods" + */ +enum ia_css_frame_delay { + IA_CSS_FRAME_DELAY_0, /**< Frame delay = 0 */ + IA_CSS_FRAME_DELAY_1, /**< Frame delay = 1 */ + IA_CSS_FRAME_DELAY_2 /**< Frame delay = 2 */ +}; + +enum ia_css_frame_flash_state { + IA_CSS_FRAME_FLASH_STATE_NONE, + IA_CSS_FRAME_FLASH_STATE_PARTIAL, + IA_CSS_FRAME_FLASH_STATE_FULL +}; + +/** Frame structure. This structure describes an image buffer or frame. + * This is the main structure used for all input and output images. + */ +struct ia_css_frame { + struct ia_css_frame_info info; /**< info struct describing the frame */ + ia_css_ptr data; /**< pointer to start of image data */ + unsigned int data_bytes; /**< size of image data in bytes */ + /* LA: move this to ia_css_buffer */ + /* + * -1 if data address is static during life time of pipeline + * >=0 if data address can change per pipeline/frame iteration + * index to dynamic data: ia_css_frame_in, ia_css_frame_out + * ia_css_frame_out_vf + * index to host-sp queue id: queue_0, queue_1 etc. + */ + int dynamic_queue_id; + /* + * if it is dynamic frame, buf_type indicates which buffer type it + * should use for event generation. we have this because in vf_pp + * binary, we use output port, but we expect VF_OUTPUT_DONE event + */ + enum ia_css_buffer_type buf_type; + enum ia_css_frame_flash_state flash_state; + unsigned int exp_id; + /**< exposure id, see ia_css_event_public.h for more detail */ + uint32_t isp_config_id; /**< Unique ID to track which config was actually applied to a particular frame */ + bool valid; /**< First video output frame is not valid */ + bool contiguous; /**< memory is allocated physically contiguously */ + union { + unsigned int _initialisation_dummy; + struct ia_css_frame_plane raw; + struct ia_css_frame_plane rgb; + struct ia_css_frame_rgb_planes planar_rgb; + struct ia_css_frame_plane yuyv; + struct ia_css_frame_yuv_planes yuv; + struct ia_css_frame_nv_planes nv; + struct ia_css_frame_plane6_planes plane6; + struct ia_css_frame_binary_plane binary; + } planes; /**< frame planes, select the right one based on + info.format */ +}; + +#define DEFAULT_FRAME \ +{ \ + IA_CSS_BINARY_DEFAULT_FRAME_INFO, /* info */ \ + 0, /* data */ \ + 0, /* data_bytes */ \ + SH_CSS_INVALID_QUEUE_ID, /* dynamic_data_index */ \ + IA_CSS_BUFFER_TYPE_INVALID, /* buf_type */ \ + IA_CSS_FRAME_FLASH_STATE_NONE, /* flash_state */ \ + 0, /* exp_id */ \ + 0, /* isp_config_id */ \ + false, /* valid */ \ + false, /* contiguous */ \ + { 0 } /* planes */ \ +} + +/** @brief Fill a frame with zeros + * + * @param frame The frame. + * @return None + * + * Fill a frame with pixel values of zero + */ +void ia_css_frame_zero(struct ia_css_frame *frame); + +/** @brief Allocate a CSS frame structure + * + * @param frame The allocated frame. + * @param width The width (in pixels) of the frame. + * @param height The height (in lines) of the frame. + * @param format The frame format. + * @param stride The padded stride, in pixels. + * @param raw_bit_depth The raw bit depth, in bits. + * @return The error code. + * + * Allocate a CSS frame structure. The memory for the frame data will be + * allocated in the CSS address space. + */ +enum ia_css_err +ia_css_frame_allocate(struct ia_css_frame **frame, + unsigned int width, + unsigned int height, + enum ia_css_frame_format format, + unsigned int stride, + unsigned int raw_bit_depth); + +/** @brief Allocate a CSS frame structure using a frame info structure. + * + * @param frame The allocated frame. + * @param[in] info The frame info structure. + * @return The error code. + * + * Allocate a frame using the resolution and format from a frame info struct. + * This is a convenience function, implemented on top of + * ia_css_frame_allocate(). + */ +enum ia_css_err +ia_css_frame_allocate_from_info(struct ia_css_frame **frame, + const struct ia_css_frame_info *info); +/** @brief Free a CSS frame structure. + * + * @param[in] frame Pointer to the frame. + * @return None + * + * Free a CSS frame structure. This will free both the frame structure + * and the pixel data pointer contained within the frame structure. + */ +void +ia_css_frame_free(struct ia_css_frame *frame); + +/** @brief Allocate a contiguous CSS frame structure + * + * @param frame The allocated frame. + * @param width The width (in pixels) of the frame. + * @param height The height (in lines) of the frame. + * @param format The frame format. + * @param stride The padded stride, in pixels. + * @param raw_bit_depth The raw bit depth, in bits. + * @return The error code. + * + * Contiguous frame allocation, only for FPGA display driver which needs + * physically contiguous memory. + * Deprecated. + */ +enum ia_css_err +ia_css_frame_allocate_contiguous(struct ia_css_frame **frame, + unsigned int width, + unsigned int height, + enum ia_css_frame_format format, + unsigned int stride, + unsigned int raw_bit_depth); + +/** @brief Allocate a contiguous CSS frame from a frame info structure. + * + * @param frame The allocated frame. + * @param[in] info The frame info structure. + * @return The error code. + * + * Allocate a frame using the resolution and format from a frame info struct. + * This is a convenience function, implemented on top of + * ia_css_frame_allocate_contiguous(). + * Only for FPGA display driver which needs physically contiguous memory. + * Deprecated. + */ +enum ia_css_err +ia_css_frame_allocate_contiguous_from_info(struct ia_css_frame **frame, + const struct ia_css_frame_info *info); + +/** @brief Allocate a CSS frame structure using a frame info structure. + * + * @param frame The allocated frame. + * @param[in] info The frame info structure. + * @return The error code. + * + * Allocate an empty CSS frame with no data buffer using the parameters + * in the frame info. + */ +enum ia_css_err +ia_css_frame_create_from_info(struct ia_css_frame **frame, + const struct ia_css_frame_info *info); + +/** @brief Set a mapped data buffer to a CSS frame + * + * @param[in] frame Valid CSS frame pointer + * @param[in] mapped_data Mapped data buffer to be assigned to the CSS frame + * @param[in] data_size_bytes Size of the mapped_data in bytes + * @return The error code. + * + * Sets a mapped data buffer to this frame. This function can be called multiple + * times with different buffers or NULL to reset the data pointer. This API + * would not try free the mapped_data and its the callers responsiblity to + * free the mapped_data buffer. However if ia_css_frame_free() is called and + * the frame had a valid data buffer, it would be freed along with the frame. + */ +enum ia_css_err +ia_css_frame_set_data(struct ia_css_frame *frame, + const ia_css_ptr mapped_data, + size_t data_size_bytes); + +/** @brief Map an existing frame data pointer to a CSS frame. + * + * @param frame Pointer to the frame to be initialized + * @param[in] info The frame info. + * @param[in] data Pointer to the allocated frame data. + * @param[in] attribute Attributes to be passed to mmgr_mmap. + * @param[in] context Pointer to the a context to be passed to mmgr_mmap. + * @return The allocated frame structure. + * + * This function maps a pre-allocated pointer into a CSS frame. This can be + * used when an upper software layer is responsible for allocating the frame + * data and it wants to share that frame pointer with the CSS code. + * This function will fill the CSS frame structure just like + * ia_css_frame_allocate() does, but instead of allocating the memory, it will + * map the pre-allocated memory into the CSS address space. + */ +enum ia_css_err +ia_css_frame_map(struct ia_css_frame **frame, + const struct ia_css_frame_info *info, + const void *data, + uint16_t attribute, + void *context); + +/** @brief Unmap a CSS frame structure. + * + * @param[in] frame Pointer to the CSS frame. + * @return None + * + * This function unmaps the frame data pointer within a CSS frame and + * then frees the CSS frame structure. Use this for frame pointers created + * using ia_css_frame_map(). + */ +void +ia_css_frame_unmap(struct ia_css_frame *frame); + +#endif /* __IA_CSS_FRAME_PUBLIC_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_host_data.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_host_data.h new file mode 100644 index 0000000000000000000000000000000000000000..4557e66891dfbd36323a4bfbedaf490e6ede78ea --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_host_data.h @@ -0,0 +1,46 @@ +/* Release Version: irci_stable_candrpv_0415_20150521_0458 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SH_CSS_HOST_DATA_H +#define __SH_CSS_HOST_DATA_H + +#include /* ia_css_pipe */ + +/** + * @brief Allocate structure ia_css_host_data. + * + * @param[in] size Size of the requested host data + * + * @return + * - NULL, can't allocate requested size + * - pointer to structure, field address points to host data with size bytes + */ +struct ia_css_host_data * +ia_css_host_data_allocate(size_t size); + +/** + * @brief Free structure ia_css_host_data. + * + * @param[in] me Pointer to structure, if a NULL is passed functions + * returns without error. Otherwise a valid pointer to + * structure must be passed and a related memory + * is freed. + * + * @return + */ +void ia_css_host_data_free(struct ia_css_host_data *me); + +#endif /* __SH_CSS_HOST_DATA_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_input_port.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_input_port.h new file mode 100644 index 0000000000000000000000000000000000000000..8a17c3346caa0eb097d54f80a52c1bf4d21c6ba1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_input_port.h @@ -0,0 +1,66 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_INPUT_PORT_H +#define __IA_CSS_INPUT_PORT_H + +/** @file + * This file contains information about the possible input ports for CSS + */ + +/** Enumeration of the physical input ports on the CSS hardware. + * There are 3 MIPI CSI-2 ports. + */ +enum ia_css_csi2_port { + IA_CSS_CSI2_PORT0, /* Implicitly map to MIPI_PORT0_ID */ + IA_CSS_CSI2_PORT1, /* Implicitly map to MIPI_PORT1_ID */ + IA_CSS_CSI2_PORT2 /* Implicitly map to MIPI_PORT2_ID */ +}; + +/** Backward compatible for CSS API 2.0 only + * TO BE REMOVED when all drivers move to CSS API 2.1 + */ +#define IA_CSS_CSI2_PORT_4LANE IA_CSS_CSI2_PORT0 +#define IA_CSS_CSI2_PORT_1LANE IA_CSS_CSI2_PORT1 +#define IA_CSS_CSI2_PORT_2LANE IA_CSS_CSI2_PORT2 + +/** The CSI2 interface supports 2 types of compression or can + * be run without compression. + */ +enum ia_css_csi2_compression_type { + IA_CSS_CSI2_COMPRESSION_TYPE_NONE, /**< No compression */ + IA_CSS_CSI2_COMPRESSION_TYPE_1, /**< Compression scheme 1 */ + IA_CSS_CSI2_COMPRESSION_TYPE_2 /**< Compression scheme 2 */ +}; + +struct ia_css_csi2_compression { + enum ia_css_csi2_compression_type type; + /**< Compression used */ + unsigned int compressed_bits_per_pixel; + /**< Compressed bits per pixel (only when compression is enabled) */ + unsigned int uncompressed_bits_per_pixel; + /**< Uncompressed bits per pixel (only when compression is enabled) */ +}; + +/** Input port structure. + */ +struct ia_css_input_port { + enum ia_css_csi2_port port; /**< Physical CSI-2 port */ + unsigned int num_lanes; /**< Number of lanes used (4-lane port only) */ + unsigned int timeout; /**< Timeout value */ + unsigned int rxcount; /**< Register value, should include all lanes */ + struct ia_css_csi2_compression compression; /**< Compression used */ +}; + +#endif /* __IA_CSS_INPUT_PORT_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_irq.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_irq.h new file mode 100644 index 0000000000000000000000000000000000000000..416ca4d28732ea7c3dadd598653200a8c40104d7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_irq.h @@ -0,0 +1,235 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_IRQ_H +#define __IA_CSS_IRQ_H + +/** @file + * This file contains information for Interrupts/IRQs from CSS + */ + +#include "ia_css_err.h" +#include "ia_css_pipe_public.h" +#include "ia_css_input_port.h" + +/** Interrupt types, these enumerate all supported interrupt types. + */ +enum ia_css_irq_type { + IA_CSS_IRQ_TYPE_EDGE, /**< Edge (level) sensitive interrupt */ + IA_CSS_IRQ_TYPE_PULSE /**< Pulse-shaped interrupt */ +}; + +/** Interrupt request type. + * When the CSS hardware generates an interrupt, a function in this API + * needs to be called to retrieve information about the interrupt. + * This interrupt type is part of this information and indicates what + * type of information the interrupt signals. + * + * Note that one interrupt can carry multiple interrupt types. For + * example: the online video ISP will generate only 2 interrupts, one to + * signal that the statistics (3a and DIS) are ready and one to signal + * that all output frames are done (output and viewfinder). + * + * DEPRECATED, this interface is not portable it should only define user + * (SW) interrupts + */ +enum ia_css_irq_info { + IA_CSS_IRQ_INFO_CSS_RECEIVER_ERROR = 1 << 0, + /**< the css receiver has encountered an error */ + IA_CSS_IRQ_INFO_CSS_RECEIVER_FIFO_OVERFLOW = 1 << 1, + /**< the FIFO in the csi receiver has overflown */ + IA_CSS_IRQ_INFO_CSS_RECEIVER_SOF = 1 << 2, + /**< the css receiver received the start of frame */ + IA_CSS_IRQ_INFO_CSS_RECEIVER_EOF = 1 << 3, + /**< the css receiver received the end of frame */ + IA_CSS_IRQ_INFO_CSS_RECEIVER_SOL = 1 << 4, + /**< the css receiver received the start of line */ + IA_CSS_IRQ_INFO_PSYS_EVENTS_READY = 1 << 5, + /**< One or more events are available in the PSYS event queue */ + IA_CSS_IRQ_INFO_EVENTS_READY = IA_CSS_IRQ_INFO_PSYS_EVENTS_READY, + /**< deprecated{obsolete version of IA_CSS_IRQ_INFO_PSYS_EVENTS_READY, + * same functionality.} */ + IA_CSS_IRQ_INFO_CSS_RECEIVER_EOL = 1 << 6, + /**< the css receiver received the end of line */ + IA_CSS_IRQ_INFO_CSS_RECEIVER_SIDEBAND_CHANGED = 1 << 7, + /**< the css receiver received a change in side band signals */ + IA_CSS_IRQ_INFO_CSS_RECEIVER_GEN_SHORT_0 = 1 << 8, + /**< generic short packets (0) */ + IA_CSS_IRQ_INFO_CSS_RECEIVER_GEN_SHORT_1 = 1 << 9, + /**< generic short packets (1) */ + IA_CSS_IRQ_INFO_IF_PRIM_ERROR = 1 << 10, + /**< the primary input formatter (A) has encountered an error */ + IA_CSS_IRQ_INFO_IF_PRIM_B_ERROR = 1 << 11, + /**< the primary input formatter (B) has encountered an error */ + IA_CSS_IRQ_INFO_IF_SEC_ERROR = 1 << 12, + /**< the secondary input formatter has encountered an error */ + IA_CSS_IRQ_INFO_STREAM_TO_MEM_ERROR = 1 << 13, + /**< the stream-to-memory device has encountered an error */ + IA_CSS_IRQ_INFO_SW_0 = 1 << 14, + /**< software interrupt 0 */ + IA_CSS_IRQ_INFO_SW_1 = 1 << 15, + /**< software interrupt 1 */ + IA_CSS_IRQ_INFO_SW_2 = 1 << 16, + /**< software interrupt 2 */ + IA_CSS_IRQ_INFO_ISP_BINARY_STATISTICS_READY = 1 << 17, + /**< ISP binary statistics are ready */ + IA_CSS_IRQ_INFO_INPUT_SYSTEM_ERROR = 1 << 18, + /**< the input system in in error */ + IA_CSS_IRQ_INFO_IF_ERROR = 1 << 19, + /**< the input formatter in in error */ + IA_CSS_IRQ_INFO_DMA_ERROR = 1 << 20, + /**< the dma in in error */ + IA_CSS_IRQ_INFO_ISYS_EVENTS_READY = 1 << 21, + /**< end-of-frame events are ready in the isys_event queue */ +}; + +/** CSS receiver error types. Whenever the CSS receiver has encountered + * an error, this enumeration is used to indicate which errors have occurred. + * + * Note that multiple error flags can be enabled at once and that this is in + * fact common (whenever an error occurs, it usually results in multiple + * errors). + * + * DEPRECATED: This interface is not portable, different systems have + * different receiver types, or possibly none in case of tests systems. + */ +enum ia_css_rx_irq_info { + IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN = 1U << 0, /**< buffer overrun */ + IA_CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE = 1U << 1, /**< entering sleep mode */ + IA_CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE = 1U << 2, /**< exited sleep mode */ + IA_CSS_RX_IRQ_INFO_ECC_CORRECTED = 1U << 3, /**< ECC corrected */ + IA_CSS_RX_IRQ_INFO_ERR_SOT = 1U << 4, + /**< Start of transmission */ + IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC = 1U << 5, /**< SOT sync (??) */ + IA_CSS_RX_IRQ_INFO_ERR_CONTROL = 1U << 6, /**< Control (??) */ + IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE = 1U << 7, /**< Double ECC */ + IA_CSS_RX_IRQ_INFO_ERR_CRC = 1U << 8, /**< CRC error */ + IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID = 1U << 9, /**< Unknown ID */ + IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC = 1U << 10,/**< Frame sync error */ + IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA = 1U << 11,/**< Frame data error */ + IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT = 1U << 12,/**< Timeout occurred */ + IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC = 1U << 13,/**< Unknown escape seq. */ + IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC = 1U << 14,/**< Line Sync error */ + IA_CSS_RX_IRQ_INFO_INIT_TIMEOUT = 1U << 15, +}; + +/** Interrupt info structure. This structure contains information about an + * interrupt. This needs to be used after an interrupt is received on the IA + * to perform the correct action. + */ +struct ia_css_irq { + enum ia_css_irq_info type; /**< Interrupt type. */ + unsigned int sw_irq_0_val; /**< In case of SW interrupt 0, value. */ + unsigned int sw_irq_1_val; /**< In case of SW interrupt 1, value. */ + unsigned int sw_irq_2_val; /**< In case of SW interrupt 2, value. */ + struct ia_css_pipe *pipe; + /**< The image pipe that generated the interrupt. */ +}; + +/** @brief Obtain interrupt information. + * + * @param[out] info Pointer to the interrupt info. The interrupt + * information wil be written to this info. + * @return If an error is encountered during the interrupt info + * and no interrupt could be translated successfully, this + * will return IA_CSS_INTERNAL_ERROR. Otherwise + * IA_CSS_SUCCESS. + * + * This function is expected to be executed after an interrupt has been sent + * to the IA from the CSS. This function returns information about the interrupt + * which is needed by the IA code to properly handle the interrupt. This + * information includes the image pipe, buffer type etc. + */ +enum ia_css_err +ia_css_irq_translate(unsigned int *info); + +/** @brief Get CSI receiver error info. + * + * @param[out] irq_bits Pointer to the interrupt bits. The interrupt + * bits will be written this info. + * This will be the error bits that are enabled in the CSI + * receiver error register. + * @return None + * + * This function should be used whenever a CSI receiver error interrupt is + * generated. It provides the detailed information (bits) on the exact error + * that occurred. + * + *@deprecated {this function is DEPRECATED since it only works on CSI port 1. + * Use the function below instead and specify the appropriate port.} + */ +void +ia_css_rx_get_irq_info(unsigned int *irq_bits); + +/** @brief Get CSI receiver error info. + * + * @param[in] port Input port identifier. + * @param[out] irq_bits Pointer to the interrupt bits. The interrupt + * bits will be written this info. + * This will be the error bits that are enabled in the CSI + * receiver error register. + * @return None + * + * This function should be used whenever a CSI receiver error interrupt is + * generated. It provides the detailed information (bits) on the exact error + * that occurred. + */ +void +ia_css_rx_port_get_irq_info(enum ia_css_csi2_port port, unsigned int *irq_bits); + +/** @brief Clear CSI receiver error info. + * + * @param[in] irq_bits The bits that should be cleared from the CSI receiver + * interrupt bits register. + * @return None + * + * This function should be called after ia_css_rx_get_irq_info has been called + * and the error bits have been interpreted. It is advised to use the return + * value of that function as the argument to this function to make sure no new + * error bits get overwritten. + * + * @deprecated{this function is DEPRECATED since it only works on CSI port 1. + * Use the function below instead and specify the appropriate port.} + */ +void +ia_css_rx_clear_irq_info(unsigned int irq_bits); + +/** @brief Clear CSI receiver error info. + * + * @param[in] port Input port identifier. + * @param[in] irq_bits The bits that should be cleared from the CSI receiver + * interrupt bits register. + * @return None + * + * This function should be called after ia_css_rx_get_irq_info has been called + * and the error bits have been interpreted. It is advised to use the return + * value of that function as the argument to this function to make sure no new + * error bits get overwritten. + */ +void +ia_css_rx_port_clear_irq_info(enum ia_css_csi2_port port, unsigned int irq_bits); + +/** @brief Enable or disable specific interrupts. + * + * @param[in] type The interrupt type that will be enabled/disabled. + * @param[in] enable enable or disable. + * @return Returns IA_CSS_INTERNAL_ERROR if this interrupt + * type cannot be enabled/disabled which is true for + * CSS internal interrupts. Otherwise returns + * IA_CSS_SUCCESS. + */ +enum ia_css_err +ia_css_irq_enable(enum ia_css_irq_info type, bool enable); + +#endif /* __IA_CSS_IRQ_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_lace_stat.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_lace_stat.h new file mode 100644 index 0000000000000000000000000000000000000000..6fee1e200a8a335b7fb64f43740717e75ca8b36c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_lace_stat.h @@ -0,0 +1,37 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_LACE_STAT_H +#define __IA_CSS_LACE_STAT_H + +/** @file + * This file contains types used for LACE statistics + */ + +struct ia_css_isp_lace_statistics; + +/** @brief Allocate mem for the LACE statistics on the ISP + * @return Pointer to the allocated LACE statistics + * buffer on the ISP +*/ +struct ia_css_isp_lace_statistics *ia_css_lace_statistics_allocate(void); + +/** @brief Free the ACC LACE statistics memory on the isp + * @param[in] me Pointer to the LACE statistics buffer on the + * ISP. + * @return None +*/ +void ia_css_lace_statistics_free(struct ia_css_isp_lace_statistics *me); + +#endif /* __IA_CSS_LACE_STAT_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_memory_access.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_memory_access.c new file mode 100644 index 0000000000000000000000000000000000000000..8dfb67003a204c518586d9e1ac6279ce44281ab7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_memory_access.c @@ -0,0 +1,107 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_memory_access.h" +#include +#include +#include +#include +#include + +const hrt_vaddress mmgr_NULL = (hrt_vaddress)0; +const hrt_vaddress mmgr_EXCEPTION = (hrt_vaddress)-1; + +static struct ia_css_css_mem_env my_env; + +void +ia_css_memory_access_init(const struct ia_css_css_mem_env *env) +{ + assert(env != NULL); + + my_env = *env; +} + +hrt_vaddress +mmgr_malloc_ex(const size_t size, const char *caller_func, int caller_line) +{ + return mmgr_alloc_attr_ex(size, 0, caller_func, caller_line); +} + +hrt_vaddress mmgr_alloc_attr_ex(const size_t size, const uint16_t attrs, const char *caller_func, int caller_line) +{ + uint32_t my_attrs = 0; + uint16_t masked_attrs = attrs & MMGR_ATTRIBUTE_MASK; + hrt_vaddress ptr; + + if (masked_attrs & MMGR_ATTRIBUTE_CACHED) + my_attrs |= IA_CSS_MEM_ATTR_CACHED; + if (masked_attrs & MMGR_ATTRIBUTE_CLEARED) + my_attrs |= IA_CSS_MEM_ATTR_ZEROED; + if (masked_attrs & MMGR_ATTRIBUTE_CONTIGUOUS) + my_attrs |= IA_CSS_MEM_ATTR_CONTIGUOUS; + if (masked_attrs & MMGR_ATTRIBUTE_PAGEALIGN) + my_attrs |= IA_CSS_MEM_ATTR_PAGEALIGN; + + (void)caller_func; + (void)caller_line; + ptr = my_env.alloc(size, my_attrs); + return ptr; +} + +hrt_vaddress +mmgr_calloc_ex(const size_t N, const size_t size, const char *caller_func, int caller_line) +{ + (void)caller_func; + (void)caller_line; + return mmgr_alloc_attr(size * N, MMGR_ATTRIBUTE_CLEARED); +} + +void +mmgr_free_ex(hrt_vaddress vaddr, const char *caller_func, int caller_line) +{ + (void)caller_func; + (void)caller_line; + my_env.free(vaddr); +} + +void +mmgr_clear_ex(hrt_vaddress vaddr, const size_t size, const char *caller_func, int caller_line) +{ + (void)caller_func; + (void)caller_line; + my_env.set(vaddr, 0, size); +} + +void +mmgr_load_ex(const hrt_vaddress vaddr, void *data, const size_t size, const char *caller_func, int caller_line) +{ + (void)caller_func; + (void)caller_line; + my_env.load(vaddr, data, size); +} + +void +mmgr_store_ex(const hrt_vaddress vaddr, const void *data, const size_t size, const char *caller_func, int caller_line) +{ + (void)caller_func; + (void)caller_line; + my_env.store(vaddr, data, size); +} + +hrt_vaddress +mmgr_mmap(const void *ptr, const size_t size, + uint16_t attribute, void *context) +{ + return my_env.mmap(ptr, size, attribute, context); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_memory_access.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_memory_access.h new file mode 100644 index 0000000000000000000000000000000000000000..1d6db0be86a921ea05932f1116edf944920166d7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_memory_access.h @@ -0,0 +1,24 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_MEMORY_ACCESS_H_ +#define _IA_CSS_MEMORY_ACCESS_H_ + +#include "ia_css_env.h" + +void +ia_css_memory_access_init(const struct ia_css_css_mem_env *env); + +#endif /* _IA_CSS_MEMORY_ACCESS_H_ */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_metadata.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_metadata.h new file mode 100644 index 0000000000000000000000000000000000000000..c40c5a19bfe190a5580f10872489ccf2d8191485 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_metadata.h @@ -0,0 +1,71 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_METADATA_H +#define __IA_CSS_METADATA_H + +/** @file + * This file contains structure for processing sensor metadata. + */ + +#include +#include "ia_css_types.h" +#include "ia_css_stream_format.h" + +/** Metadata configuration. This data structure contains necessary info + * to process sensor metadata. + */ +struct ia_css_metadata_config { + enum ia_css_stream_format data_type; /**< Data type of CSI-2 embedded + data. The default value is IA_CSS_STREAM_FORMAT_EMBEDDED. For + certain sensors, user can choose non-default data type for embedded + data. */ + struct ia_css_resolution resolution; /**< Resolution */ +}; + +struct ia_css_metadata_info { + struct ia_css_resolution resolution; /**< Resolution */ + uint32_t stride; /**< Stride in bytes */ + uint32_t size; /**< Total size in bytes */ +}; + +struct ia_css_metadata { + struct ia_css_metadata_info info; /**< Layout info */ + ia_css_ptr address; /**< CSS virtual address */ + uint32_t exp_id; + /**< Exposure ID, see ia_css_event_public.h for more detail */ +}; +#define SIZE_OF_IA_CSS_METADATA_STRUCT sizeof(struct ia_css_metadata) + +/** @brief Allocate a metadata buffer. + * @param[in] metadata_info Metadata info struct, contains details on metadata buffers. + * @return Pointer of metadata buffer or NULL (if error) + * + * This function allocates a metadata buffer according to the properties + * specified in the metadata_info struct. + */ +struct ia_css_metadata * +ia_css_metadata_allocate(const struct ia_css_metadata_info *metadata_info); + +/** @brief Free a metadata buffer. + * + * @param[in] metadata Pointer of metadata buffer. + * @return None + * + * This function frees a metadata buffer. + */ +void +ia_css_metadata_free(struct ia_css_metadata *metadata); + +#endif /* __IA_CSS_METADATA_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_mipi.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_mipi.h new file mode 100644 index 0000000000000000000000000000000000000000..fd2c01b60b28127b55928a664d24a2ebe53b53ca --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_mipi.h @@ -0,0 +1,82 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MIPI_H +#define __IA_CSS_MIPI_H + +/** @file + * This file contains MIPI support functionality + */ + +#include +#include "ia_css_err.h" +#include "ia_css_stream_format.h" +#include "ia_css_input_port.h" + +/** Backward compatible for CSS API 2.0 only + * TO BE REMOVED when all drivers move to CSS API 2.1. + */ +/** @brief Specify a CSS MIPI frame buffer. + * + * @param[in] size_mem_words The frame size in memory words (32B). + * @param[in] contiguous Allocate memory physically contiguously or not. + * @return The error code. + * + * \deprecated{Use ia_css_mipi_buffer_config instead.} + * + * Specifies a CSS MIPI frame buffer: size in memory words (32B). + */ +enum ia_css_err +ia_css_mipi_frame_specify(const unsigned int size_mem_words, + const bool contiguous); + +#if !defined(HAS_NO_INPUT_SYSTEM) +/** @brief Register size of a CSS MIPI frame for check during capturing. + * + * @param[in] port CSI-2 port this check is registered. + * @param[in] size_mem_words The frame size in memory words (32B). + * @return Return the error in case of failure. E.g. MAX_NOF_ENTRIES REACHED + * + * Register size of a CSS MIPI frame to check during capturing. Up to + * IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES entries per port allowed. Entries are reset + * when stream is stopped. + * + * + */ +enum ia_css_err +ia_css_mipi_frame_enable_check_on_size(const enum ia_css_csi2_port port, + const unsigned int size_mem_words); +#endif + +/** @brief Calculate the size of a mipi frame. + * + * @param[in] width The width (in pixels) of the frame. + * @param[in] height The height (in lines) of the frame. + * @param[in] format The frame (MIPI) format. + * @param[in] hasSOLandEOL Whether frame (MIPI) contains (optional) SOL and EOF packets. + * @param[in] embedded_data_size_words Embedded data size in memory words. + * @param size_mem_words The mipi frame size in memory words (32B). + * @return The error code. + * + * Calculate the size of a mipi frame, based on the resolution and format. + */ +enum ia_css_err +ia_css_mipi_frame_calculate_size(const unsigned int width, + const unsigned int height, + const enum ia_css_stream_format format, + const bool hasSOLandEOL, + const unsigned int embedded_data_size_words, + unsigned int *size_mem_words); + +#endif /* __IA_CSS_MIPI_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_mmu.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_mmu.h new file mode 100644 index 0000000000000000000000000000000000000000..48f8855d61f6eb99422cb0aa35919c8562a01ebe --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_mmu.h @@ -0,0 +1,32 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MMU_H +#define __IA_CSS_MMU_H + +/** @file + * This file contains one support function for invalidating the CSS MMU cache + */ + +/** @brief Invalidate the MMU internal cache. + * @return None + * + * This function triggers an invalidation of the translate-look-aside + * buffer (TLB) that's inside the CSS MMU. This function should be called + * every time the page tables used by the MMU change. + */ +void +ia_css_mmu_invalidate_cache(void); + +#endif /* __IA_CSS_MMU_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_mmu_private.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_mmu_private.h new file mode 100644 index 0000000000000000000000000000000000000000..7c8500903b5c50938d94cc6ac80a22ff92507beb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_mmu_private.h @@ -0,0 +1,31 @@ +#ifdef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MMU_PRIVATE_H +#define __IA_CSS_MMU_PRIVATE_H + +#include "system_local.h" + +/* + * This function sets the L1 pagetable address. + * After power-up of the ISP the L1 pagetable can be set. + * Once being set the L1 pagetable is protected against + * further modifications. + */ +void +sh_css_mmu_set_page_table_base_index(hrt_data base_index); + +#endif /* __IA_CSS_MMU_PRIVATE_H */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_morph.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_morph.h new file mode 100644 index 0000000000000000000000000000000000000000..969840da52b2199af47b73b5fa8d8ac10c003a0a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_morph.h @@ -0,0 +1,39 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MORPH_H +#define __IA_CSS_MORPH_H + +/** @file + * This file contains supporting for morphing table + */ + +#include + +/** @brief Morphing table + * @param[in] width Width of the morphing table. + * @param[in] height Height of the morphing table. + * @return Pointer to the morphing table +*/ +struct ia_css_morph_table * +ia_css_morph_table_allocate(unsigned int width, unsigned int height); + +/** @brief Free the morph table + * @param[in] me Pointer to the morph table. + * @return None +*/ +void +ia_css_morph_table_free(struct ia_css_morph_table *me); + +#endif /* __IA_CSS_MORPH_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_pipe.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_pipe.h new file mode 100644 index 0000000000000000000000000000000000000000..d0c0e6b92025d578c16529f1495ccb5bc8244b9f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_pipe.h @@ -0,0 +1,228 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PIPE_H__ +#define __IA_CSS_PIPE_H__ + +#include +#include "ia_css_stream.h" +#include "ia_css_frame.h" +#include "ia_css_pipeline.h" +#include "ia_css_binary.h" +#include "sh_css_legacy.h" + +#define PIPE_ENTRY_EMPTY_TOKEN (~0U) +#define PIPE_ENTRY_RESERVED_TOKEN (0x1) + +struct ia_css_preview_settings { + struct ia_css_binary copy_binary; + struct ia_css_binary preview_binary; + struct ia_css_binary vf_pp_binary; + + /* 2401 only for these two - do we in fact use them for anything real */ + struct ia_css_frame *delay_frames[MAX_NUM_DELAY_FRAMES]; + struct ia_css_frame *tnr_frames[NUM_TNR_FRAMES]; + + struct ia_css_pipe *copy_pipe; + struct ia_css_pipe *capture_pipe; + struct ia_css_pipe *acc_pipe; +}; + +#define IA_CSS_DEFAULT_PREVIEW_SETTINGS \ +{ \ + IA_CSS_BINARY_DEFAULT_SETTINGS, /* copy_binary */\ + IA_CSS_BINARY_DEFAULT_SETTINGS, /* preview_binary */\ + IA_CSS_BINARY_DEFAULT_SETTINGS, /* vf_pp_binary */\ + { NULL }, /* dvs_frames */ \ + { NULL }, /* tnr_frames */ \ + NULL, /* copy_pipe */\ + NULL, /* capture_pipe */\ + NULL, /* acc_pipe */\ +} + +struct ia_css_capture_settings { + struct ia_css_binary copy_binary; + /* we extend primary binary to multiple stages because in ISP2.6.1 + * the computation load is too high to fit in one single binary. */ + struct ia_css_binary primary_binary[MAX_NUM_PRIMARY_STAGES]; + unsigned int num_primary_stage; + struct ia_css_binary pre_isp_binary; + struct ia_css_binary anr_gdc_binary; + struct ia_css_binary post_isp_binary; + struct ia_css_binary capture_pp_binary; + struct ia_css_binary vf_pp_binary; + struct ia_css_binary capture_ldc_binary; + struct ia_css_binary *yuv_scaler_binary; + struct ia_css_frame *delay_frames[MAX_NUM_VIDEO_DELAY_FRAMES]; + bool *is_output_stage; + unsigned int num_yuv_scaler; +}; + +#define IA_CSS_DEFAULT_CAPTURE_SETTINGS \ +{ \ + IA_CSS_BINARY_DEFAULT_SETTINGS, /* copy_binary */\ + {IA_CSS_BINARY_DEFAULT_SETTINGS}, /* primary_binary */\ + 0, /* num_primary_stage */\ + IA_CSS_BINARY_DEFAULT_SETTINGS, /* pre_isp_binary */\ + IA_CSS_BINARY_DEFAULT_SETTINGS, /* anr_gdc_binary */\ + IA_CSS_BINARY_DEFAULT_SETTINGS, /* post_isp_binary */\ + IA_CSS_BINARY_DEFAULT_SETTINGS, /* capture_pp_binary */\ + IA_CSS_BINARY_DEFAULT_SETTINGS, /* vf_pp_binary */\ + IA_CSS_BINARY_DEFAULT_SETTINGS, /* capture_ldc_binary */\ + NULL, /* yuv_scaler_binary */ \ + { NULL }, /* delay_frames[ref_frames] */ \ + NULL, /* is_output_stage */ \ + 0, /* num_yuv_scaler */ \ +} + +struct ia_css_video_settings { + struct ia_css_binary copy_binary; + struct ia_css_binary video_binary; + struct ia_css_binary vf_pp_binary; + struct ia_css_binary *yuv_scaler_binary; + struct ia_css_frame *delay_frames[MAX_NUM_VIDEO_DELAY_FRAMES]; +#ifndef ISP2401 + struct ia_css_frame *tnr_frames[NUM_VIDEO_TNR_FRAMES]; +#else + struct ia_css_frame *tnr_frames[NUM_TNR_FRAMES]; +#endif + struct ia_css_frame *vf_pp_in_frame; + struct ia_css_pipe *copy_pipe; + struct ia_css_pipe *capture_pipe; + bool *is_output_stage; + unsigned int num_yuv_scaler; +}; + +#define IA_CSS_DEFAULT_VIDEO_SETTINGS \ +{ \ + IA_CSS_BINARY_DEFAULT_SETTINGS, /* copy_binary */ \ + IA_CSS_BINARY_DEFAULT_SETTINGS, /* video_binary */ \ + IA_CSS_BINARY_DEFAULT_SETTINGS, /* vf_pp_binary */ \ + NULL, /* yuv_scaler_binary */ \ + { NULL }, /* delay_frames */ \ + { NULL }, /* tnr_frames */ \ + NULL, /* vf_pp_in_frame */ \ + NULL, /* copy_pipe */ \ + NULL, /* capture_pipe */ \ + NULL, /* is_output_stage */ \ + 0, /* num_yuv_scaler */ \ +} + +struct ia_css_yuvpp_settings { + struct ia_css_binary copy_binary; + struct ia_css_binary *yuv_scaler_binary; + struct ia_css_binary *vf_pp_binary; + bool *is_output_stage; + unsigned int num_yuv_scaler; + unsigned int num_vf_pp; + unsigned int num_output; +}; + +#define IA_CSS_DEFAULT_YUVPP_SETTINGS \ +{ \ + IA_CSS_BINARY_DEFAULT_SETTINGS, /* copy_binary */ \ + NULL, /* yuv_scaler_binary */ \ + NULL, /* vf_pp_binary */ \ + NULL, /* is_output_stage */ \ + 0, /* num_yuv_scaler */ \ + 0, /* num_vf_pp */ \ + 0, /* num_output */ \ +} + +struct osys_object; + +struct ia_css_pipe { + /* TODO: Remove stop_requested and use stop_requested in the pipeline */ + bool stop_requested; + struct ia_css_pipe_config config; + struct ia_css_pipe_extra_config extra_config; + struct ia_css_pipe_info info; + enum ia_css_pipe_id mode; + struct ia_css_shading_table *shading_table; + struct ia_css_pipeline pipeline; + struct ia_css_frame_info output_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + struct ia_css_frame_info bds_output_info; + struct ia_css_frame_info vf_output_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + struct ia_css_frame_info out_yuv_ds_input_info; + struct ia_css_frame_info vf_yuv_ds_input_info; + struct ia_css_fw_info *output_stage; /* extra output stage */ + struct ia_css_fw_info *vf_stage; /* extra vf_stage */ + unsigned int required_bds_factor; + unsigned int dvs_frame_delay; + int num_invalid_frames; + bool enable_viewfinder[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + struct ia_css_stream *stream; + struct ia_css_frame in_frame_struct; + struct ia_css_frame out_frame_struct; + struct ia_css_frame vf_frame_struct; + struct ia_css_frame *continuous_frames[NUM_CONTINUOUS_FRAMES]; + struct ia_css_metadata *cont_md_buffers[NUM_CONTINUOUS_FRAMES]; + union { + struct ia_css_preview_settings preview; + struct ia_css_video_settings video; + struct ia_css_capture_settings capture; + struct ia_css_yuvpp_settings yuvpp; + } pipe_settings; + hrt_vaddress scaler_pp_lut; + struct osys_object *osys_obj; + + /* This number is unique per pipe each instance of css. This number is + * reused as pipeline number also. There is a 1-1 mapping between pipe_num + * and sp thread id. Current logic limits pipe_num to + * SH_CSS_MAX_SP_THREADS */ + unsigned int pipe_num; +}; + +#define IA_CSS_DEFAULT_PIPE \ +{ \ + false, /* stop_requested */ \ + DEFAULT_PIPE_CONFIG, /* config */ \ + DEFAULT_PIPE_EXTRA_CONFIG, /* extra_config */ \ + DEFAULT_PIPE_INFO, /* info */ \ + IA_CSS_PIPE_ID_ACC, /* mode (pipe_id) */ \ + NULL, /* shading_table */ \ + DEFAULT_PIPELINE, /* pipeline */ \ + {IA_CSS_BINARY_DEFAULT_FRAME_INFO}, /* output_info */ \ + IA_CSS_BINARY_DEFAULT_FRAME_INFO, /* bds_output_info */ \ + {IA_CSS_BINARY_DEFAULT_FRAME_INFO}, /* vf_output_info */ \ + IA_CSS_BINARY_DEFAULT_FRAME_INFO, /* out_yuv_ds_input_info */ \ + IA_CSS_BINARY_DEFAULT_FRAME_INFO, /* vf_yuv_ds_input_info */ \ + NULL, /* output_stage */ \ + NULL, /* vf_stage */ \ + SH_CSS_BDS_FACTOR_1_00, /* required_bds_factor */ \ + 1, /* dvs_frame_delay */ \ + 0, /* num_invalid_frames */ \ + {true}, /* enable_viewfinder */ \ + NULL, /* stream */ \ + DEFAULT_FRAME, /* in_frame_struct */ \ + DEFAULT_FRAME, /* out_frame_struct */ \ + DEFAULT_FRAME, /* vf_frame_struct */ \ + { NULL }, /* continuous_frames */ \ + { NULL }, /* cont_md_buffers */ \ + { IA_CSS_DEFAULT_PREVIEW_SETTINGS }, /* pipe_settings */ \ + 0, /* scaler_pp_lut */ \ + NULL, /* osys object */ \ + PIPE_ENTRY_EMPTY_TOKEN, /* pipe_num */\ +} + +void ia_css_pipe_map_queue(struct ia_css_pipe *pipe, bool map); + +enum ia_css_err +sh_css_param_update_isp_params(struct ia_css_pipe *curr_pipe, + struct ia_css_isp_parameters *params, + bool commit, struct ia_css_pipe *pipe); + + + +#endif /* __IA_CSS_PIPE_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_pipe_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_pipe_public.h new file mode 100644 index 0000000000000000000000000000000000000000..733e0ef3afe8bdc0c430ec9a33bf73afd992a8ab --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_pipe_public.h @@ -0,0 +1,659 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PIPE_PUBLIC_H +#define __IA_CSS_PIPE_PUBLIC_H + +/** @file + * This file contains the public interface for CSS pipes. + */ + +#include +#include +#include +#include +#include +#ifdef ISP2401 +#include +#endif + +enum { + IA_CSS_PIPE_OUTPUT_STAGE_0 = 0, + IA_CSS_PIPE_OUTPUT_STAGE_1, + IA_CSS_PIPE_MAX_OUTPUT_STAGE, +}; + +/** Enumeration of pipe modes. This mode can be used to create + * an image pipe for this mode. These pipes can be combined + * to configure and run streams on the ISP. + * + * For example, one can create a preview and capture pipe to + * create a continuous capture stream. + */ +enum ia_css_pipe_mode { + IA_CSS_PIPE_MODE_PREVIEW, /**< Preview pipe */ + IA_CSS_PIPE_MODE_VIDEO, /**< Video pipe */ + IA_CSS_PIPE_MODE_CAPTURE, /**< Still capture pipe */ + IA_CSS_PIPE_MODE_ACC, /**< Accelerated pipe */ + IA_CSS_PIPE_MODE_COPY, /**< Copy pipe, only used for embedded/image data copying */ + IA_CSS_PIPE_MODE_YUVPP, /**< YUV post processing pipe, used for all use cases with YUV input, + for SoC sensor and external ISP */ +}; +/* Temporary define */ +#define IA_CSS_PIPE_MODE_NUM (IA_CSS_PIPE_MODE_YUVPP + 1) + +/** + * Enumeration of pipe versions. + * the order should match with definition in sh_css_defs.h + */ +enum ia_css_pipe_version { + IA_CSS_PIPE_VERSION_1 = 1, /**< ISP1.0 pipe */ + IA_CSS_PIPE_VERSION_2_2 = 2, /**< ISP2.2 pipe */ + IA_CSS_PIPE_VERSION_2_6_1 = 3, /**< ISP2.6.1 pipe */ + IA_CSS_PIPE_VERSION_2_7 = 4 /**< ISP2.7 pipe */ +}; + +/** + * Pipe configuration structure. + * Resolution properties are filled by Driver, kernel configurations are + * set by AIC + */ +struct ia_css_pipe_config { + enum ia_css_pipe_mode mode; + /**< mode, indicates which mode the pipe should use. */ + enum ia_css_pipe_version isp_pipe_version; + /**< pipe version, indicates which imaging pipeline the pipe should use. */ + struct ia_css_resolution input_effective_res; + /**< input effective resolution */ + struct ia_css_resolution bayer_ds_out_res; + /**< bayer down scaling */ + struct ia_css_resolution capt_pp_in_res; +#ifndef ISP2401 + /**< bayer down scaling */ +#else + /**< capture post processing input resolution */ +#endif + struct ia_css_resolution vf_pp_in_res; +#ifndef ISP2401 + /**< bayer down scaling */ +#else + /**< view finder post processing input resolution */ + struct ia_css_resolution output_system_in_res; + /**< For IPU3 only: use output_system_in_res to specify what input resolution + will OSYS receive, this resolution is equal to the output resolution of GDC + if not determined CSS will set output_system_in_res with main osys output pin resolution + All other IPUs may ignore this property */ +#endif + struct ia_css_resolution dvs_crop_out_res; + /**< dvs crop, video only, not in use yet. Use dvs_envelope below. */ + struct ia_css_frame_info output_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + /**< output of YUV scaling */ + struct ia_css_frame_info vf_output_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + /**< output of VF YUV scaling */ + struct ia_css_fw_info *acc_extension; + /**< Pipeline extension accelerator */ + struct ia_css_fw_info **acc_stages; + /**< Standalone accelerator stages */ + uint32_t num_acc_stages; + /**< Number of standalone accelerator stages */ + struct ia_css_capture_config default_capture_config; + /**< Default capture config for initial capture pipe configuration. */ + struct ia_css_resolution dvs_envelope; /**< temporary */ + enum ia_css_frame_delay dvs_frame_delay; + /**< indicates the DVS loop delay in frame periods */ + int acc_num_execs; + /**< For acceleration pipes only: determine how many times the pipe + should be run. Setting this to -1 means it will run until + stopped. */ + bool enable_dz; + /**< Disabling digital zoom for a pipeline, if this is set to false, + then setting a zoom factor will have no effect. + In some use cases this provides better performance. */ + bool enable_dpc; + /**< Disabling "Defect Pixel Correction" for a pipeline, if this is set + to false. In some use cases this provides better performance. */ + bool enable_vfpp_bci; + /**< Enabling BCI mode will cause yuv_scale binary to be picked up + instead of vf_pp. This only applies to viewfinder post + processing stages. */ +#ifdef ISP2401 + bool enable_luma_only; + /**< Enabling of monochrome mode for a pipeline. If enabled only luma processing + will be done. */ + bool enable_tnr; + /**< Enabling of TNR (temporal noise reduction). This is only applicable to video + pipes. Non video-pipes should always set this parameter to false. */ +#endif + struct ia_css_isp_config *p_isp_config; + /**< Pointer to ISP configuration */ + struct ia_css_resolution gdc_in_buffer_res; + /**< GDC in buffer resolution. */ + struct ia_css_point gdc_in_buffer_offset; + /**< GDC in buffer offset - indicates the pixel coordinates of the first valid pixel inside the buffer */ +#ifdef ISP2401 + struct ia_css_coordinate internal_frame_origin_bqs_on_sctbl; + /**< Origin of internal frame positioned on shading table at shading correction in ISP. + NOTE: Shading table is larger than or equal to internal frame. + Shading table has shading gains and internal frame has bayer data. + The origin of internal frame is used in shading correction in ISP + to retrieve shading gains which correspond to bayer data. */ +#endif +}; + + +#ifdef ISP2401 +/** + * Default origin of internal frame positioned on shading table. + */ +#define IA_CSS_PIPE_DEFAULT_INTERNAL_FRAME_ORIGIN_BQS_ON_SCTBL \ +{ \ + 0, /* x [bqs] */ \ + 0 /* y [bqs] */ \ +} + +/** + * Default settings for newly created pipe configurations. + */ +#define DEFAULT_PIPE_CONFIG \ +{ \ + IA_CSS_PIPE_MODE_PREVIEW, /* mode */ \ + 1, /* isp_pipe_version */ \ + { 0, 0 }, /* pipe_effective_input_res */ \ + { 0, 0 }, /* bayer_ds_out_res */ \ + { 0, 0 }, /* vf_pp_in_res */ \ + { 0, 0 }, /* capt_pp_in_res */ \ + { 0, 0 }, /* output_system_in_res */ \ + { 0, 0 }, /* dvs_crop_out_res */ \ + {IA_CSS_BINARY_DEFAULT_FRAME_INFO}, /* output_info */ \ + {IA_CSS_BINARY_DEFAULT_FRAME_INFO}, /* vf_output_info */ \ + NULL, /* acc_extension */ \ + NULL, /* acc_stages */ \ + 0, /* num_acc_stages */ \ + DEFAULT_CAPTURE_CONFIG, /* default_capture_config */ \ + { 0, 0 }, /* dvs_envelope */ \ + IA_CSS_FRAME_DELAY_1, /* dvs_frame_delay */ \ + -1, /* acc_num_execs */ \ + false, /* enable_dz */ \ + false, /* enable_dpc */ \ + false, /* enable_vfpp_bci */ \ + false, /* enable_luma_only */ \ + false, /* enable_tnr */ \ + NULL, /* p_isp_config */\ + { 0, 0 }, /* gdc_in_buffer_res */ \ + { 0, 0 }, /* gdc_in_buffer_offset */ \ + IA_CSS_PIPE_DEFAULT_INTERNAL_FRAME_ORIGIN_BQS_ON_SCTBL /* internal_frame_origin_bqs_on_sctbl */ \ +} + +#else + +/** + * Default settings for newly created pipe configurations. + */ +#define DEFAULT_PIPE_CONFIG \ +{ \ + IA_CSS_PIPE_MODE_PREVIEW, /* mode */ \ + 1, /* isp_pipe_version */ \ + { 0, 0 }, /* pipe_effective_input_res */ \ + { 0, 0 }, /* bayer_ds_out_res */ \ + { 0, 0 }, /* vf_pp_in_res */ \ + { 0, 0 }, /* capt_pp_in_res */ \ + { 0, 0 }, /* dvs_crop_out_res */ \ + {IA_CSS_BINARY_DEFAULT_FRAME_INFO}, /* output_info */ \ + {IA_CSS_BINARY_DEFAULT_FRAME_INFO}, /* vf_output_info */ \ + NULL, /* acc_extension */ \ + NULL, /* acc_stages */ \ + 0, /* num_acc_stages */ \ + DEFAULT_CAPTURE_CONFIG, /* default_capture_config */ \ + { 0, 0 }, /* dvs_envelope */ \ + IA_CSS_FRAME_DELAY_1, /* dvs_frame_delay */ \ + -1, /* acc_num_execs */ \ + false, /* enable_dz */ \ + false, /* enable_dpc */ \ + false, /* enable_vfpp_bci */ \ + NULL, /* p_isp_config */\ + { 0, 0 }, /* gdc_in_buffer_res */ \ + { 0, 0 } /* gdc_in_buffer_offset */ \ +} + +#endif + +/** Pipe info, this struct describes properties of a pipe after it's stream has + * been created. + * ~~~** DO NOT ADD NEW FIELD **~~~ This structure will be deprecated. + * - On the Behalf of CSS-API Committee. + */ +struct ia_css_pipe_info { + struct ia_css_frame_info output_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + /**< Info about output resolution. This contains the stride which + should be used for memory allocation. */ + struct ia_css_frame_info vf_output_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + /**< Info about viewfinder output resolution (optional). This contains + the stride that should be used for memory allocation. */ + struct ia_css_frame_info raw_output_info; + /**< Raw output resolution. This indicates the resolution of the + RAW bayer output for pipes that support this. Currently, only the + still capture pipes support this feature. When this resolution is + smaller than the input resolution, cropping will be performed by + the ISP. The first cropping that will be performed is on the upper + left corner where we crop 8 lines and 8 columns to remove the + pixels normally used to initialize the ISP filters. + This is why the raw output resolution should normally be set to + the input resolution - 8x8. */ +#ifdef ISP2401 + struct ia_css_resolution output_system_in_res_info; + /**< For IPU3 only. Info about output system in resolution which is considered + as gdc out resolution. */ +#endif + struct ia_css_shading_info shading_info; + /**< After an image pipe is created, this field will contain the info + for the shading correction. */ + struct ia_css_grid_info grid_info; + /**< After an image pipe is created, this field will contain the grid + info for 3A and DVS. */ + int num_invalid_frames; + /**< The very first frames in a started stream do not contain valid data. + In this field, the CSS-firmware communicates to the host-driver how + many initial frames will contain invalid data; this allows the + host-driver to discard those initial invalid frames and start it's + output at the first valid frame. */ +}; + +/** + * Defaults for ia_css_pipe_info structs. + */ +#ifdef ISP2401 + +#define DEFAULT_PIPE_INFO \ +{ \ + {IA_CSS_BINARY_DEFAULT_FRAME_INFO}, /* output_info */ \ + {IA_CSS_BINARY_DEFAULT_FRAME_INFO}, /* vf_output_info */ \ + IA_CSS_BINARY_DEFAULT_FRAME_INFO, /* raw_output_info */ \ + { 0, 0}, /* output system in res */ \ + DEFAULT_SHADING_INFO, /* shading_info */ \ + DEFAULT_GRID_INFO, /* grid_info */ \ + 0 /* num_invalid_frames */ \ +} + +#else + +#define DEFAULT_PIPE_INFO \ +{ \ + {IA_CSS_BINARY_DEFAULT_FRAME_INFO}, /* output_info */ \ + {IA_CSS_BINARY_DEFAULT_FRAME_INFO}, /* vf_output_info */ \ + IA_CSS_BINARY_DEFAULT_FRAME_INFO, /* raw_output_info */ \ + DEFAULT_SHADING_INFO, /* shading_info */ \ + DEFAULT_GRID_INFO, /* grid_info */ \ + 0 /* num_invalid_frames */ \ +} + +#endif + +/** @brief Load default pipe configuration + * @param[out] pipe_config The pipe configuration. + * @return None + * + * This function will load the default pipe configuration: +@code + struct ia_css_pipe_config def_config = { + IA_CSS_PIPE_MODE_PREVIEW, // mode + 1, // isp_pipe_version + {0, 0}, // bayer_ds_out_res + {0, 0}, // capt_pp_in_res + {0, 0}, // vf_pp_in_res + {0, 0}, // dvs_crop_out_res + {{0, 0}, 0, 0, 0, 0}, // output_info + {{0, 0}, 0, 0, 0, 0}, // second_output_info + {{0, 0}, 0, 0, 0, 0}, // vf_output_info + {{0, 0}, 0, 0, 0, 0}, // second_vf_output_info + NULL, // acc_extension + NULL, // acc_stages + 0, // num_acc_stages + { + IA_CSS_CAPTURE_MODE_RAW, // mode + false, // enable_xnr + false // enable_raw_output + }, // default_capture_config + {0, 0}, // dvs_envelope + 1, // dvs_frame_delay + -1, // acc_num_execs + true, // enable_dz + NULL, // p_isp_config + }; +@endcode + */ +void ia_css_pipe_config_defaults(struct ia_css_pipe_config *pipe_config); + +/** @brief Create a pipe + * @param[in] config The pipe configuration. + * @param[out] pipe The pipe. + * @return IA_CSS_SUCCESS or the error code. + * + * This function will create a pipe with the given + * configuration. + */ +enum ia_css_err +ia_css_pipe_create(const struct ia_css_pipe_config *config, + struct ia_css_pipe **pipe); + +/** @brief Destroy a pipe + * @param[in] pipe The pipe. + * @return IA_CSS_SUCCESS or the error code. + * + * This function will destroy a given pipe. + */ +enum ia_css_err +ia_css_pipe_destroy(struct ia_css_pipe *pipe); + +/** @brief Provides information about a pipe + * @param[in] pipe The pipe. + * @param[out] pipe_info The pipe information. + * @return IA_CSS_SUCCESS or IA_CSS_ERR_INVALID_ARGUMENTS. + * + * This function will provide information about a given pipe. + */ +enum ia_css_err +ia_css_pipe_get_info(const struct ia_css_pipe *pipe, + struct ia_css_pipe_info *pipe_info); + +/** @brief Configure a pipe with filter coefficients. + * @param[in] pipe The pipe. + * @param[in] config The pointer to ISP configuration. + * @return IA_CSS_SUCCESS or error code upon error. + * + * This function configures the filter coefficients for an image + * pipe. + */ +enum ia_css_err +ia_css_pipe_set_isp_config(struct ia_css_pipe *pipe, + struct ia_css_isp_config *config); + +/** @brief Controls when the Event generator raises an IRQ to the Host. + * + * @param[in] pipe The pipe. + * @param[in] or_mask Binary or of enum ia_css_event_irq_mask_type. Each pipe + related event that is part of this mask will directly + raise an IRQ to the Host when the event occurs in the + CSS. + * @param[in] and_mask Binary or of enum ia_css_event_irq_mask_type. An event + IRQ for the Host is only raised after all pipe related + events have occurred at least once for all the active + pipes. Events are remembered and don't need to occure + at the same moment in time. There is no control over + the order of these events. Once an IRQ has been raised + all remembered events are reset. + * @return IA_CSS_SUCCESS. + * + Controls when the Event generator in the CSS raises an IRQ to the Host. + The main purpose of this function is to reduce the amount of interrupts + between the CSS and the Host. This will help saving power as it wakes up the + Host less often. In case both or_mask and and_mask are + IA_CSS_EVENT_TYPE_NONE for all pipes, no event IRQ's will be raised. An + exception holds for IA_CSS_EVENT_TYPE_PORT_EOF, for this event an IRQ is always + raised. + Note that events are still queued and the Host can poll for them. The + or_mask and and_mask may be be active at the same time\n + \n + Default values, for all pipe id's, after ia_css_init:\n + or_mask = IA_CSS_EVENT_TYPE_ALL\n + and_mask = IA_CSS_EVENT_TYPE_NONE\n + \n + Examples\n + \code + ia_css_pipe_set_irq_mask(h_pipe, + IA_CSS_EVENT_TYPE_3A_STATISTICS_DONE | + IA_CSS_EVENT_TYPE_DIS_STATISTICS_DONE , + IA_CSS_EVENT_TYPE_NONE); + \endcode + The event generator will only raise an interrupt to the Host when there are + 3A or DIS statistics available from the preview pipe. It will not generate + an interrupt for any other event of the preview pipe e.g when there is an + output frame available. + + \code + ia_css_pipe_set_irq_mask(h_pipe_preview, + IA_CSS_EVENT_TYPE_NONE, + IA_CSS_EVENT_TYPE_OUTPUT_FRAME_DONE | + IA_CSS_EVENT_TYPE_3A_STATISTICS_DONE ); + + ia_css_pipe_set_irq_mask(h_pipe_capture, + IA_CSS_EVENT_TYPE_NONE, + IA_CSS_EVENT_TYPE_OUTPUT_FRAME_DONE ); + \endcode + The event generator will only raise an interrupt to the Host when there is + both a frame done and 3A event available from the preview pipe AND when there + is a frame done available from the capture pipe. Note that these events + may occur at different moments in time. Also the order of the events is not + relevant. + + \code + ia_css_pipe_set_irq_mask(h_pipe_preview, + IA_CSS_EVENT_TYPE_OUTPUT_FRAME_DONE, + IA_CSS_EVENT_TYPE_ALL ); + + ia_css_pipe_set_irq_mask(h_pipe_capture, + IA_CSS_EVENT_TYPE_OUTPUT_FRAME_DONE, + IA_CSS_EVENT_TYPE_ALL ); + \endcode + The event generator will only raise an interrupt to the Host when there is an + output frame from the preview pipe OR an output frame from the capture pipe. + All other events (3A, VF output, pipeline done) will not raise an interrupt + to the Host. These events are not lost but always stored in the event queue. + */ +enum ia_css_err +ia_css_pipe_set_irq_mask(struct ia_css_pipe *pipe, + unsigned int or_mask, + unsigned int and_mask); + +/** @brief Reads the current event IRQ mask from the CSS. + * + * @param[in] pipe The pipe. + * @param[out] or_mask Current or_mask. The bits in this mask are a binary or + of enum ia_css_event_irq_mask_type. Pointer may be NULL. + * @param[out] and_mask Current and_mask.The bits in this mask are a binary or + of enum ia_css_event_irq_mask_type. Pointer may be NULL. + * @return IA_CSS_SUCCESS. + * + Reads the current event IRQ mask from the CSS. Reading returns the actual + values as used by the SP and not any mirrored values stored at the Host.\n +\n +Precondition:\n +SP must be running.\n + +*/ +enum ia_css_err +ia_css_event_get_irq_mask(const struct ia_css_pipe *pipe, + unsigned int *or_mask, + unsigned int *and_mask); + +/** @brief Queue a buffer for an image pipe. + * + * @param[in] pipe The pipe that will own the buffer. + * @param[in] buffer Pointer to the buffer. + * Note that the caller remains owner of the buffer + * structure. Only the data pointer within it will + * be passed into the internal queues. + * @return IA_CSS_INTERNAL_ERROR in case of unexpected errors, + * IA_CSS_SUCCESS otherwise. + * + * This function adds a buffer (which has a certain buffer type) to the queue + * for this type. This queue is owned by the image pipe. After this function + * completes successfully, the buffer is now owned by the image pipe and should + * no longer be accessed by any other code until it gets dequeued. The image + * pipe will dequeue buffers from this queue, use them and return them to the + * host code via an interrupt. Buffers will be consumed in the same order they + * get queued, but may be returned to the host out of order. + */ +enum ia_css_err +ia_css_pipe_enqueue_buffer(struct ia_css_pipe *pipe, + const struct ia_css_buffer *buffer); + +/** @brief Dequeue a buffer from an image pipe. + * + * @param[in] pipe The pipeline that the buffer queue belongs to. + * @param[in,out] buffer The buffer is used to lookup the type which determines + * which internal queue to use. + * The resulting buffer pointer is written into the dta + * field. + * @return IA_CSS_ERR_NO_BUFFER if the queue is empty or + * IA_CSS_SUCCESS otherwise. + * + * This function dequeues a buffer from a buffer queue. The queue is indicated + * by the buffer type argument. This function can be called after an interrupt + * has been generated that signalled that a new buffer was available and can + * be used in a polling-like situation where the NO_BUFFER return value is used + * to determine whether a buffer was available or not. + */ +enum ia_css_err +ia_css_pipe_dequeue_buffer(struct ia_css_pipe *pipe, + struct ia_css_buffer *buffer); + + +/** @brief Set the state (Enable or Disable) of the Extension stage in the + * given pipe. + * @param[in] pipe Pipe handle. + * @param[in] fw_handle Extension firmware Handle (ia_css_fw_info.handle) + * @param[in] enable Enable Flag (1 to enable ; 0 to disable) + * + * @return + * IA_CSS_SUCCESS : Success + * IA_CSS_ERR_INVALID_ARGUMENTS : Invalid Parameters + * IA_CSS_ERR_RESOURCE_NOT_AVAILABLE : Inactive QOS Pipe + * (No active stream with this pipe) + * + * This function will request state change (enable or disable) for the Extension + * stage (firmware handle) in the given pipe. + * + * Note: + * 1. Extension can be enabled/disabled only on QOS Extensions + * 2. Extension can be enabled/disabled only with an active QOS Pipe + * 3. Initial(Default) state of QOS Extensions is Disabled + * 4. State change cannot be guaranteed immediately OR on frame boundary + * + */ +enum ia_css_err +ia_css_pipe_set_qos_ext_state (struct ia_css_pipe *pipe, + uint32_t fw_handle, + bool enable); + +/** @brief Get the state (Enable or Disable) of the Extension stage in the + * given pipe. + * @param[in] pipe Pipe handle. + * @param[in] fw_handle Extension firmware Handle (ia_css_fw_info.handle) + * @param[out] *enable Enable Flag + * + * @return + * IA_CSS_SUCCESS : Success + * IA_CSS_ERR_INVALID_ARGUMENTS : Invalid Parameters + * IA_CSS_ERR_RESOURCE_NOT_AVAILABLE : Inactive QOS Pipe + * (No active stream with this pipe) + * + * This function will query the state of the Extension stage (firmware handle) + * in the given Pipe. + * + * Note: + * 1. Extension state can be queried only on QOS Extensions + * 2. Extension can be enabled/disabled only with an active QOS Pipe + * 3. Initial(Default) state of QOS Extensions is Disabled. + * + */ +enum ia_css_err +ia_css_pipe_get_qos_ext_state (struct ia_css_pipe *pipe, + uint32_t fw_handle, + bool * enable); + +#ifdef ISP2401 +/** @brief Update mapped CSS and ISP arguments for QoS pipe during SP runtime. + * @param[in] pipe Pipe handle. + * @param[in] fw_handle Extension firmware Handle (ia_css_fw_info.handle). + * @param[in] css_seg Parameter memory descriptors for CSS segments. + * @param[in] isp_seg Parameter memory descriptors for ISP segments. + * + * @return + * IA_CSS_SUCCESS : Success + * IA_CSS_ERR_INVALID_ARGUMENTS : Invalid Parameters + * IA_CSS_ERR_RESOURCE_NOT_AVAILABLE : Inactive QOS Pipe + * (No active stream with this pipe) + * + * \deprecated{This interface is used to temporarily support a late-developed, + * specific use-case on a specific IPU2 platform. It will not be supported or + * maintained on IPU3 or further.} + */ +enum ia_css_err +ia_css_pipe_update_qos_ext_mapped_arg(struct ia_css_pipe *pipe, uint32_t fw_handle, + struct ia_css_isp_param_css_segments *css_seg, + struct ia_css_isp_param_isp_segments *isp_seg); + +#endif +/** @brief Get selected configuration settings + * @param[in] pipe The pipe. + * @param[out] config Configuration settings. + * @return None + */ +void +ia_css_pipe_get_isp_config(struct ia_css_pipe *pipe, + struct ia_css_isp_config *config); + +/** @brief Set the scaler lut on this pipe. A copy of lut is made in the inuit + * address space. So the LUT can be freed by caller. + * @param[in] pipe Pipe handle. + * @param[in] lut Look up tabel + * + * @return + * IA_CSS_SUCCESS : Success + * IA_CSS_ERR_INVALID_ARGUMENTS : Invalid Parameters + * + * Note: + * 1) Note that both GDC's are programmed with the same table. + * 2) Current implementation ignores the pipe and overrides the + * global lut. This will be fixed in the future + * 3) This function must be called before stream start + * + */ +enum ia_css_err +ia_css_pipe_set_bci_scaler_lut( struct ia_css_pipe *pipe, + const void *lut); +/** @brief Checking of DVS statistics ability + * @param[in] pipe_info The pipe info. + * @return true - has DVS statistics ability + * false - otherwise + */ +bool ia_css_pipe_has_dvs_stats(struct ia_css_pipe_info *pipe_info); + +#ifdef ISP2401 +/** @brief Override the frameformat set on the output pins. + * @param[in] pipe Pipe handle. + * @param[in] output_pin Pin index to set the format on + * 0 - main output pin + * 1 - display output pin + * @param[in] format Format to set + * + * @return + * IA_CSS_SUCCESS : Success + * IA_CSS_ERR_INVALID_ARGUMENTS : Invalid Parameters + * IA_CSS_ERR_INTERNAL_ERROR : Pipe misses binary info + * + * Note: + * 1) This is an optional function to override the formats set in the pipe. + * 2) Only overriding with IA_CSS_FRAME_FORMAT_NV12_TILEY is currently allowed. + * 3) This function is only to be used on pipes that use the output system. + * 4) If this function is used, it MUST be called after ia_css_pipe_create. + * 5) If this function is used, this function MUST be called before ia_css_stream_start. + */ +enum ia_css_err +ia_css_pipe_override_frame_format(struct ia_css_pipe *pipe, + int output_pin, + enum ia_css_frame_format format); + +#endif +#endif /* __IA_CSS_PIPE_PUBLIC_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_prbs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_prbs.h new file mode 100644 index 0000000000000000000000000000000000000000..9b0eeb08ca0493bdb48e39030a041dc463506a34 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_prbs.h @@ -0,0 +1,53 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PRBS_H +#define __IA_CSS_PRBS_H + +/** @file + * This file contains support for Pseudo Random Bit Sequence (PRBS) inputs + */ + +/** Enumerate the PRBS IDs. + */ +enum ia_css_prbs_id { + IA_CSS_PRBS_ID0, + IA_CSS_PRBS_ID1, + IA_CSS_PRBS_ID2 +}; + +/** + * Maximum number of PRBS IDs. + * + * Make sure the value of this define gets changed to reflect the correct + * number of ia_css_prbs_id enum if you add/delete an item in the enum. + */ +#define N_CSS_PRBS_IDS (IA_CSS_PRBS_ID2+1) + +/** + * PRBS configuration structure. + * + * Seed the for the Pseudo Random Bit Sequence. + * + * @deprecated{This interface is deprecated, it is not portable -> move to input system API} + */ +struct ia_css_prbs_config { + enum ia_css_prbs_id id; + unsigned int h_blank; /**< horizontal blank */ + unsigned int v_blank; /**< vertical blank */ + int seed; /**< random seed for the 1st 2-pixel-components/clock */ + int seed1; /**< random seed for the 2nd 2-pixel-components/clock */ +}; + +#endif /* __IA_CSS_PRBS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_properties.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_properties.h new file mode 100644 index 0000000000000000000000000000000000000000..19af4021b24c511091d98a7e591714e2c72501b5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_properties.h @@ -0,0 +1,41 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PROPERTIES_H +#define __IA_CSS_PROPERTIES_H + +/** @file + * This file contains support for retrieving properties of some hardware the CSS system + */ + +#include /* bool */ +#include /* ia_css_vamem_type */ + +struct ia_css_properties { + int gdc_coord_one; + bool l1_base_is_index; /**< Indicate whether the L1 page base + is a page index or a byte address. */ + enum ia_css_vamem_type vamem_type; +}; + +/** @brief Get hardware properties + * @param[in,out] properties The hardware properties + * @return None + * + * This function returns a number of hardware properties. + */ +void +ia_css_get_properties(struct ia_css_properties *properties); + +#endif /* __IA_CSS_PROPERTIES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_shading.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_shading.h new file mode 100644 index 0000000000000000000000000000000000000000..cb0f249e98c8b8dde2649e9297d433a49e058fd4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_shading.h @@ -0,0 +1,40 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SHADING_H +#define __IA_CSS_SHADING_H + +/** @file + * This file contains support for setting the shading table for CSS + */ + +#include + +/** @brief Shading table + * @param[in] width Width of the shading table. + * @param[in] height Height of the shading table. + * @return Pointer to the shading table +*/ +struct ia_css_shading_table * +ia_css_shading_table_alloc(unsigned int width, + unsigned int height); + +/** @brief Free shading table + * @param[in] table Pointer to the shading table. + * @return None +*/ +void +ia_css_shading_table_free(struct ia_css_shading_table *table); + +#endif /* __IA_CSS_SHADING_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream.h new file mode 100644 index 0000000000000000000000000000000000000000..453fe4db0133ad1568b1ce6410902c580de69398 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream.h @@ -0,0 +1,110 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_STREAM_H_ +#define _IA_CSS_STREAM_H_ + +#include +#include +#if !defined(HAS_NO_INPUT_SYSTEM) && !defined(USE_INPUT_SYSTEM_VERSION_2401) +#include +#endif +#include "ia_css_types.h" +#include "ia_css_stream_public.h" + +/** + * structure to hold all internal stream related information + */ +struct ia_css_stream { + struct ia_css_stream_config config; + struct ia_css_stream_info info; +#if !defined(HAS_NO_INPUT_SYSTEM) && !defined(USE_INPUT_SYSTEM_VERSION_2401) + rx_cfg_t csi_rx_config; +#endif + bool reconfigure_css_rx; + struct ia_css_pipe *last_pipe; + int num_pipes; + struct ia_css_pipe **pipes; + struct ia_css_pipe *continuous_pipe; + struct ia_css_isp_parameters *isp_params_configs; + struct ia_css_isp_parameters *per_frame_isp_params_configs; + + bool cont_capt; + bool disable_cont_vf; +#ifndef ISP2401 + bool stop_copy_preview; +#endif + bool started; +}; + +/** @brief Get a binary in the stream, which binary has the shading correction. + * + * @param[in] stream: The stream. + * @return The binary which has the shading correction. + * + */ +struct ia_css_binary * +ia_css_stream_get_shading_correction_binary(const struct ia_css_stream *stream); + +struct ia_css_binary * +ia_css_stream_get_dvs_binary(const struct ia_css_stream *stream); + +struct ia_css_binary * +ia_css_stream_get_3a_binary(const struct ia_css_stream *stream); + +unsigned int +ia_css_stream_input_format_bits_per_pixel(struct ia_css_stream *stream); + +bool +sh_css_params_set_binning_factor(struct ia_css_stream *stream, unsigned int sensor_binning); + +void +sh_css_invalidate_params(struct ia_css_stream *stream); + +/* The following functions are used for testing purposes only */ +const struct ia_css_fpn_table * +ia_css_get_fpn_table(struct ia_css_stream *stream); + +/** @brief Get a pointer to the shading table. + * + * @param[in] stream: The stream. + * @return The pointer to the shading table. + * + */ +struct ia_css_shading_table * +ia_css_get_shading_table(struct ia_css_stream *stream); + +void +ia_css_get_isp_dis_coefficients(struct ia_css_stream *stream, + short *horizontal_coefficients, + short *vertical_coefficients); + +void +ia_css_get_isp_dvs2_coefficients(struct ia_css_stream *stream, + short *hor_coefs_odd_real, + short *hor_coefs_odd_imag, + short *hor_coefs_even_real, + short *hor_coefs_even_imag, + short *ver_coefs_odd_real, + short *ver_coefs_odd_imag, + short *ver_coefs_even_real, + short *ver_coefs_even_imag); + +enum ia_css_err +ia_css_stream_isp_parameters_init(struct ia_css_stream *stream); + +void +ia_css_stream_isp_parameters_uninit(struct ia_css_stream *stream); + +#endif /*_IA_CSS_STREAM_H_*/ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream_format.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream_format.h new file mode 100644 index 0000000000000000000000000000000000000000..ae608a9c9051f14759f3ee0e710559091238c9ce --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream_format.h @@ -0,0 +1,94 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_STREAM_FORMAT_H +#define __IA_CSS_STREAM_FORMAT_H + +/** @file + * This file contains formats usable for ISP streaming input + */ + +#include /* bool */ + +/** The ISP streaming input interface supports the following formats. + * These match the corresponding MIPI formats. + */ +enum ia_css_stream_format { + IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY, /**< 8 bits per subpixel */ + IA_CSS_STREAM_FORMAT_YUV420_8, /**< 8 bits per subpixel */ + IA_CSS_STREAM_FORMAT_YUV420_10, /**< 10 bits per subpixel */ + IA_CSS_STREAM_FORMAT_YUV420_16, /**< 16 bits per subpixel */ + IA_CSS_STREAM_FORMAT_YUV422_8, /**< UYVY..UYVY, 8 bits per subpixel */ + IA_CSS_STREAM_FORMAT_YUV422_10, /**< UYVY..UYVY, 10 bits per subpixel */ + IA_CSS_STREAM_FORMAT_YUV422_16, /**< UYVY..UYVY, 16 bits per subpixel */ + IA_CSS_STREAM_FORMAT_RGB_444, /**< BGR..BGR, 4 bits per subpixel */ + IA_CSS_STREAM_FORMAT_RGB_555, /**< BGR..BGR, 5 bits per subpixel */ + IA_CSS_STREAM_FORMAT_RGB_565, /**< BGR..BGR, 5 bits B and R, 6 bits G */ + IA_CSS_STREAM_FORMAT_RGB_666, /**< BGR..BGR, 6 bits per subpixel */ + IA_CSS_STREAM_FORMAT_RGB_888, /**< BGR..BGR, 8 bits per subpixel */ + IA_CSS_STREAM_FORMAT_RAW_6, /**< RAW data, 6 bits per pixel */ + IA_CSS_STREAM_FORMAT_RAW_7, /**< RAW data, 7 bits per pixel */ + IA_CSS_STREAM_FORMAT_RAW_8, /**< RAW data, 8 bits per pixel */ + IA_CSS_STREAM_FORMAT_RAW_10, /**< RAW data, 10 bits per pixel */ + IA_CSS_STREAM_FORMAT_RAW_12, /**< RAW data, 12 bits per pixel */ + IA_CSS_STREAM_FORMAT_RAW_14, /**< RAW data, 14 bits per pixel */ + IA_CSS_STREAM_FORMAT_RAW_16, /**< RAW data, 16 bits per pixel, which is + not specified in CSI-MIPI standard*/ + IA_CSS_STREAM_FORMAT_BINARY_8, /**< Binary byte stream, which is target at + JPEG. */ + + /** CSI2-MIPI specific format: Generic short packet data. It is used to + * keep the timing information for the opening/closing of shutters, + * triggering of flashes and etc. + */ + IA_CSS_STREAM_FORMAT_GENERIC_SHORT1, /**< Generic Short Packet Code 1 */ + IA_CSS_STREAM_FORMAT_GENERIC_SHORT2, /**< Generic Short Packet Code 2 */ + IA_CSS_STREAM_FORMAT_GENERIC_SHORT3, /**< Generic Short Packet Code 3 */ + IA_CSS_STREAM_FORMAT_GENERIC_SHORT4, /**< Generic Short Packet Code 4 */ + IA_CSS_STREAM_FORMAT_GENERIC_SHORT5, /**< Generic Short Packet Code 5 */ + IA_CSS_STREAM_FORMAT_GENERIC_SHORT6, /**< Generic Short Packet Code 6 */ + IA_CSS_STREAM_FORMAT_GENERIC_SHORT7, /**< Generic Short Packet Code 7 */ + IA_CSS_STREAM_FORMAT_GENERIC_SHORT8, /**< Generic Short Packet Code 8 */ + + /** CSI2-MIPI specific format: YUV data. + */ + IA_CSS_STREAM_FORMAT_YUV420_8_SHIFT, /**< YUV420 8-bit (Chroma Shifted Pixel Sampling) */ + IA_CSS_STREAM_FORMAT_YUV420_10_SHIFT, /**< YUV420 8-bit (Chroma Shifted Pixel Sampling) */ + + /** CSI2-MIPI specific format: Generic long packet data + */ + IA_CSS_STREAM_FORMAT_EMBEDDED, /**< Embedded 8-bit non Image Data */ + + /** CSI2-MIPI specific format: User defined byte-based data. For example, + * the data transmitter (e.g. the SoC sensor) can keep the JPEG data as + * the User Defined Data Type 4 and the MPEG data as the + * User Defined Data Type 7. + */ + IA_CSS_STREAM_FORMAT_USER_DEF1, /**< User defined 8-bit data type 1 */ + IA_CSS_STREAM_FORMAT_USER_DEF2, /**< User defined 8-bit data type 2 */ + IA_CSS_STREAM_FORMAT_USER_DEF3, /**< User defined 8-bit data type 3 */ + IA_CSS_STREAM_FORMAT_USER_DEF4, /**< User defined 8-bit data type 4 */ + IA_CSS_STREAM_FORMAT_USER_DEF5, /**< User defined 8-bit data type 5 */ + IA_CSS_STREAM_FORMAT_USER_DEF6, /**< User defined 8-bit data type 6 */ + IA_CSS_STREAM_FORMAT_USER_DEF7, /**< User defined 8-bit data type 7 */ + IA_CSS_STREAM_FORMAT_USER_DEF8, /**< User defined 8-bit data type 8 */ +}; + +#define IA_CSS_STREAM_FORMAT_NUM IA_CSS_STREAM_FORMAT_USER_DEF8 + +unsigned int ia_css_util_input_format_bpp( + enum ia_css_stream_format format, + bool two_ppc); + +#endif /* __IA_CSS_STREAM_FORMAT_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream_public.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream_public.h new file mode 100644 index 0000000000000000000000000000000000000000..2c8d9de10a59fdd337c463729c11fc9c6e3e894f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_stream_public.h @@ -0,0 +1,582 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_STREAM_PUBLIC_H +#define __IA_CSS_STREAM_PUBLIC_H + +/** @file + * This file contains support for configuring and controlling streams + */ + +#include +#include "ia_css_types.h" +#include "ia_css_pipe_public.h" +#include "ia_css_metadata.h" +#include "ia_css_tpg.h" +#include "ia_css_prbs.h" +#include "ia_css_input_port.h" + +/** Input modes, these enumerate all supported input modes. + * Note that not all ISP modes support all input modes. + */ +enum ia_css_input_mode { + IA_CSS_INPUT_MODE_SENSOR, /**< data from sensor */ + IA_CSS_INPUT_MODE_FIFO, /**< data from input-fifo */ + IA_CSS_INPUT_MODE_TPG, /**< data from test-pattern generator */ + IA_CSS_INPUT_MODE_PRBS, /**< data from pseudo-random bit stream */ + IA_CSS_INPUT_MODE_MEMORY, /**< data from a frame in memory */ + IA_CSS_INPUT_MODE_BUFFERED_SENSOR /**< data is sent through mipi buffer */ +}; + +/** Structure of the MIPI buffer configuration + */ +struct ia_css_mipi_buffer_config { + unsigned int size_mem_words; /**< The frame size in the system memory + words (32B) */ + bool contiguous; /**< Allocated memory physically + contiguously or not. \deprecated{Will be false always.}*/ + unsigned int nof_mipi_buffers; /**< The number of MIPI buffers required for this + stream */ +}; + +enum { + IA_CSS_STREAM_ISYS_STREAM_0 = 0, + IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX = IA_CSS_STREAM_ISYS_STREAM_0, + IA_CSS_STREAM_ISYS_STREAM_1, + IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH +}; + +/** This is input data configuration for one MIPI data type. We can have + * multiple of this in one virtual channel. + */ +struct ia_css_stream_isys_stream_config { + struct ia_css_resolution input_res; /**< Resolution of input data */ + enum ia_css_stream_format format; /**< Format of input stream. This data + format will be mapped to MIPI data + type internally. */ + int linked_isys_stream_id; /**< default value is -1, other value means + current isys_stream shares the same buffer with + indicated isys_stream*/ + bool valid; /**< indicate whether other fields have valid value */ +}; + +struct ia_css_stream_input_config { + struct ia_css_resolution input_res; /**< Resolution of input data */ + struct ia_css_resolution effective_res; /**< Resolution of input data. + Used for CSS 2400/1 System and deprecated for other + systems (replaced by input_effective_res in + ia_css_pipe_config) */ + enum ia_css_stream_format format; /**< Format of input stream. This data + format will be mapped to MIPI data + type internally. */ + enum ia_css_bayer_order bayer_order; /**< Bayer order for RAW streams */ +}; + + +/** Input stream description. This describes how input will flow into the + * CSS. This is used to program the CSS hardware. + */ +struct ia_css_stream_config { + enum ia_css_input_mode mode; /**< Input mode */ + union { + struct ia_css_input_port port; /**< Port, for sensor only. */ + struct ia_css_tpg_config tpg; /**< TPG configuration */ + struct ia_css_prbs_config prbs; /**< PRBS configuration */ + } source; /**< Source of input data */ + unsigned int channel_id; /**< Channel on which input data + will arrive. Use this field + to specify virtual channel id. + Valid values are: 0, 1, 2, 3 */ + struct ia_css_stream_isys_stream_config isys_config[IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH]; + struct ia_css_stream_input_config input_config; + +#ifdef ISP2401 + /* Currently, Android and Windows platforms interpret the binning_factor parameter + * differently. In Android, the binning factor is expressed in the form + * 2^N * 2^N, whereas in Windows platform, the binning factor is N*N + * To use the Windows method of specification, the caller has to define + * macro USE_WINDOWS_BINNING_FACTOR. This is for backward compatibility only + * and will be deprecated. In the future,all platforms will use the N*N method + */ +#endif + unsigned int sensor_binning_factor; /**< Binning factor used by sensor + to produce image data. This is + used for shading correction. */ + unsigned int pixels_per_clock; /**< Number of pixels per clock, which can be + 1, 2 or 4. */ + bool online; /**< offline will activate RAW copy on SP, use this for + continuous capture. */ + /* ISYS2401 usage: ISP receives data directly from sensor, no copy. */ + unsigned init_num_cont_raw_buf; /**< initial number of raw buffers to + allocate */ + unsigned target_num_cont_raw_buf; /**< total number of raw buffers to + allocate */ + bool pack_raw_pixels; /**< Pack pixels in the raw buffers */ + bool continuous; /**< Use SP copy feature to continuously capture frames + to system memory and run pipes in offline mode */ + bool disable_cont_viewfinder; /**< disable continous viewfinder for ZSL use case */ + int32_t flash_gpio_pin; /**< pin on which the flash is connected, -1 for no flash */ + int left_padding; /**< The number of input-formatter left-paddings, -1 for default from binary.*/ + struct ia_css_mipi_buffer_config mipi_buffer_config; /**< mipi buffer configuration */ + struct ia_css_metadata_config metadata_config; /**< Metadata configuration. */ + bool ia_css_enable_raw_buffer_locking; /**< Enable Raw Buffer Locking for HALv3 Support */ + bool lock_all; + /**< Lock all RAW buffers (true) or lock only buffers processed by + video or preview pipe (false). + This setting needs to be enabled to allow raw buffer locking + without continuous viewfinder. */ +}; + +struct ia_css_stream; + +/** Stream info, this struct describes properties of a stream after it has been + * created. + */ +struct ia_css_stream_info { + struct ia_css_metadata_info metadata_info; + /**< Info about the metadata layout, this contains the stride. */ +}; + +/** @brief Load default stream configuration + * @param[in,out] stream_config The stream configuration. + * @return None + * + * This function will reset the stream configuration to the default state: +@code + memset(stream_config, 0, sizeof(*stream_config)); + stream_config->online = true; + stream_config->left_padding = -1; +@endcode + */ +void ia_css_stream_config_defaults(struct ia_css_stream_config *stream_config); + +/* + * create the internal structures and fill in the configuration data and pipes + */ + + /** @brief Creates a stream + * @param[in] stream_config The stream configuration. + * @param[in] num_pipes The number of pipes to incorporate in the stream. + * @param[in] pipes The pipes. + * @param[out] stream The stream. + * @return IA_CSS_SUCCESS or the error code. + * + * This function will create a stream with a given configuration and given pipes. + */ +enum ia_css_err +ia_css_stream_create(const struct ia_css_stream_config *stream_config, + int num_pipes, + struct ia_css_pipe *pipes[], + struct ia_css_stream **stream); + +/** @brief Destroys a stream + * @param[in] stream The stream. + * @return IA_CSS_SUCCESS or the error code. + * + * This function will destroy a given stream. + */ +enum ia_css_err +ia_css_stream_destroy(struct ia_css_stream *stream); + +/** @brief Provides information about a stream + * @param[in] stream The stream. + * @param[out] stream_info The information about the stream. + * @return IA_CSS_SUCCESS or the error code. + * + * This function will destroy a given stream. + */ +enum ia_css_err +ia_css_stream_get_info(const struct ia_css_stream *stream, + struct ia_css_stream_info *stream_info); + +/** @brief load (rebuild) a stream that was unloaded. + * @param[in] stream The stream + * @return IA_CSS_SUCCESS or the error code + * + * Rebuild a stream, including allocating structs, setting configuration and + * building the required pipes. + */ +enum ia_css_err +ia_css_stream_load(struct ia_css_stream *stream); + +/** @brief Starts the stream. + * @param[in] stream The stream. + * @return IA_CSS_SUCCESS or the error code. + * + * The dynamic data in + * the buffers are not used and need to be queued with a separate call + * to ia_css_pipe_enqueue_buffer. + * NOTE: this function will only send start event to corresponding + * thread and will not start SP any more. + */ +enum ia_css_err +ia_css_stream_start(struct ia_css_stream *stream); + +/** @brief Stop the stream. + * @param[in] stream The stream. + * @return IA_CSS_SUCCESS or the error code. + * + * NOTE: this function will send stop event to pipes belong to this + * stream but will not terminate threads. + */ +enum ia_css_err +ia_css_stream_stop(struct ia_css_stream *stream); + +/** @brief Check if a stream has stopped + * @param[in] stream The stream. + * @return boolean flag + * + * This function will check if the stream has stopped and return the correspondent boolean flag. + */ +bool +ia_css_stream_has_stopped(struct ia_css_stream *stream); + +/** @brief destroy a stream according to the stream seed previosly saved in the seed array. + * @param[in] stream The stream. + * @return IA_CSS_SUCCESS (no other errors are generated now) + * + * Destroy the stream and all the pipes related to it. + */ +enum ia_css_err +ia_css_stream_unload(struct ia_css_stream *stream); + +/** @brief Returns stream format + * @param[in] stream The stream. + * @return format of the string + * + * This function will return the stream format. + */ +enum ia_css_stream_format +ia_css_stream_get_format(const struct ia_css_stream *stream); + +/** @brief Check if the stream is configured for 2 pixels per clock + * @param[in] stream The stream. + * @return boolean flag + * + * This function will check if the stream is configured for 2 pixels per clock and + * return the correspondent boolean flag. + */ +bool +ia_css_stream_get_two_pixels_per_clock(const struct ia_css_stream *stream); + +/** @brief Sets the output frame stride (at the last pipe) + * @param[in] stream The stream + * @param[in] output_padded_width - the output buffer stride. + * @return ia_css_err + * + * This function will Set the output frame stride (at the last pipe) + */ +enum ia_css_err +ia_css_stream_set_output_padded_width(struct ia_css_stream *stream, unsigned int output_padded_width); + +/** @brief Return max number of continuous RAW frames. + * @param[in] stream The stream. + * @param[out] buffer_depth The maximum number of continuous RAW frames. + * @return IA_CSS_SUCCESS or IA_CSS_ERR_INVALID_ARGUMENTS + * + * This function will return the maximum number of continuous RAW frames + * the system can support. + */ +enum ia_css_err +ia_css_stream_get_max_buffer_depth(struct ia_css_stream *stream, int *buffer_depth); + +/** @brief Set nr of continuous RAW frames to use. + * + * @param[in] stream The stream. + * @param[in] buffer_depth Number of frames to set. + * @return IA_CSS_SUCCESS or error code upon error. + * + * Set the number of continuous frames to use during continuous modes. + */ +enum ia_css_err +ia_css_stream_set_buffer_depth(struct ia_css_stream *stream, int buffer_depth); + +/** @brief Get number of continuous RAW frames to use. + * @param[in] stream The stream. + * @param[out] buffer_depth The number of frames to use + * @return IA_CSS_SUCCESS or IA_CSS_ERR_INVALID_ARGUMENTS + * + * Get the currently set number of continuous frames + * to use during continuous modes. + */ +enum ia_css_err +ia_css_stream_get_buffer_depth(struct ia_css_stream *stream, int *buffer_depth); + +/* ===== CAPTURE ===== */ + +/** @brief Configure the continuous capture + * + * @param[in] stream The stream. + * @param[in] num_captures The number of RAW frames to be processed to + * YUV. Setting this to -1 will make continuous + * capture run until it is stopped. + * This number will also be used to allocate RAW + * buffers. To allow the viewfinder to also + * keep operating, 2 extra buffers will always be + * allocated. + * If the offset is negative and the skip setting + * is greater than 0, additional buffers may be + * needed. + * @param[in] skip Skip N frames in between captures. This can be + * used to select a slower capture frame rate than + * the sensor output frame rate. + * @param[in] offset Start the RAW-to-YUV processing at RAW buffer + * with this offset. This allows the user to + * process RAW frames that were captured in the + * past or future. + * @return IA_CSS_SUCCESS or error code upon error. + * + * For example, to capture the current frame plus the 2 previous + * frames and 2 subsequent frames, you would call + * ia_css_stream_capture(5, 0, -2). + */ +enum ia_css_err +ia_css_stream_capture(struct ia_css_stream *stream, + int num_captures, + unsigned int skip, + int offset); + +/** @brief Specify which raw frame to tag based on exp_id found in frame info + * + * @param[in] stream The stream. + * @param[in] exp_id The exposure id of the raw frame to tag. + * + * @return IA_CSS_SUCCESS or error code upon error. + * + * This function allows the user to tag a raw frame based on the exposure id + * found in the viewfinder frames' frame info. + */ +enum ia_css_err +ia_css_stream_capture_frame(struct ia_css_stream *stream, + unsigned int exp_id); + +/* ===== VIDEO ===== */ + +/** @brief Send streaming data into the css input FIFO + * + * @param[in] stream The stream. + * @param[in] data Pointer to the pixels to be send. + * @param[in] width Width of the input frame. + * @param[in] height Height of the input frame. + * @return None + * + * Send streaming data into the css input FIFO. This is for testing purposes + * only. This uses the channel ID and input format as set by the user with + * the regular functions for this. + * This function blocks until the entire frame has been written into the + * input FIFO. + * + * Note: + * For higher flexibility the ia_css_stream_send_input_frame is replaced by + * three separate functions: + * 1) ia_css_stream_start_input_frame + * 2) ia_css_stream_send_input_line + * 3) ia_css_stream_end_input_frame + * In this way it is possible to stream multiple frames on different + * channel ID's on a line basis. It will be possible to simulate + * line-interleaved Stereo 3D muxed on 1 mipi port. + * These 3 functions are for testing purpose only and can be used in + * conjunction with ia_css_stream_send_input_frame + */ +void +ia_css_stream_send_input_frame(const struct ia_css_stream *stream, + const unsigned short *data, + unsigned int width, + unsigned int height); + +/** @brief Start an input frame on the CSS input FIFO. + * + * @param[in] stream The stream. + * @return None + * + * Starts the streaming to mipi frame by sending SoF for channel channel_id. + * It will use the input_format and two_pixels_per_clock as provided by + * the user. + * For the "correct" use-case, input_format and two_pixels_per_clock must match + * with the values as set by the user with the regular functions. + * To simulate an error, the user can provide "incorrect" values for + * input_format and/or two_pixels_per_clock. + */ +void +ia_css_stream_start_input_frame(const struct ia_css_stream *stream); + +/** @brief Send a line of input data into the CSS input FIFO. + * + * @param[in] stream The stream. + * @param[in] data Array of the first line of image data. + * @param width The width (in pixels) of the first line. + * @param[in] data2 Array of the second line of image data. + * @param width2 The width (in pixels) of the second line. + * @return None + * + * Sends 1 frame line. Start with SoL followed by width bytes of data, followed + * by width2 bytes of data2 and followed by and EoL + * It will use the input_format and two_pixels_per_clock settings as provided + * with the ia_css_stream_start_input_frame function call. + * + * This function blocks until the entire line has been written into the + * input FIFO. + */ +void +ia_css_stream_send_input_line(const struct ia_css_stream *stream, + const unsigned short *data, + unsigned int width, + const unsigned short *data2, + unsigned int width2); + +/** @brief Send a line of input embedded data into the CSS input FIFO. + * + * @param[in] stream Pointer of the stream. + * @param[in] format Format of the embedded data. + * @param[in] data Pointer of the embedded data line. + * @param[in] width The width (in pixels) of the line. + * @return None + * + * Sends one embedded data line to input fifo. Start with SoL followed by + * width bytes of data, and followed by and EoL. + * It will use the two_pixels_per_clock settings as provided with the + * ia_css_stream_start_input_frame function call. + * + * This function blocks until the entire line has been written into the + * input FIFO. + */ +void +ia_css_stream_send_input_embedded_line(const struct ia_css_stream *stream, + enum ia_css_stream_format format, + const unsigned short *data, + unsigned int width); + +/** @brief End an input frame on the CSS input FIFO. + * + * @param[in] stream The stream. + * @return None + * + * Send the end-of-frame signal into the CSS input FIFO. + */ +void +ia_css_stream_end_input_frame(const struct ia_css_stream *stream); + +/** @brief send a request flash command to SP + * + * @param[in] stream The stream. + * @return None + * + * Driver needs to call this function to send a flash request command + * to SP, SP will be responsible for switching on/off the flash at proper + * time. Due to the SP multi-threading environment, this request may have + * one-frame delay, the driver needs to check the flashed flag in frame info + * to determine which frame is being flashed. + */ +void +ia_css_stream_request_flash(struct ia_css_stream *stream); + +/** @brief Configure a stream with filter coefficients. + * @deprecated {Replaced by + * ia_css_pipe_set_isp_config_on_pipe()} + * + * @param[in] stream The stream. + * @param[in] config The set of filter coefficients. + * @param[in] pipe Pipe to be updated when set isp config, NULL means to + * update all pipes in the stream. + * @return IA_CSS_SUCCESS or error code upon error. + * + * This function configures the filter coefficients for an image + * stream. For image pipes that do not execute any ISP filters, this + * function will have no effect. + * It is safe to call this function while the image stream is running, + * in fact this is the expected behavior most of the time. Proper + * resource locking and double buffering is in place to allow for this. + */ +enum ia_css_err +ia_css_stream_set_isp_config_on_pipe(struct ia_css_stream *stream, + const struct ia_css_isp_config *config, + struct ia_css_pipe *pipe); + +/** @brief Configure a stream with filter coefficients. + * @deprecated {Replaced by + * ia_css_pipe_set_isp_config()} + * @param[in] stream The stream. + * @param[in] config The set of filter coefficients. + * @return IA_CSS_SUCCESS or error code upon error. + * + * This function configures the filter coefficients for an image + * stream. For image pipes that do not execute any ISP filters, this + * function will have no effect. All pipes of a stream will be updated. + * See ::ia_css_stream_set_isp_config_on_pipe() for the per-pipe alternative. + * It is safe to call this function while the image stream is running, + * in fact this is the expected behaviour most of the time. Proper + * resource locking and double buffering is in place to allow for this. + */ +enum ia_css_err +ia_css_stream_set_isp_config( + struct ia_css_stream *stream, + const struct ia_css_isp_config *config); + +/** @brief Get selected configuration settings + * @param[in] stream The stream. + * @param[out] config Configuration settings. + * @return None + */ +void +ia_css_stream_get_isp_config(const struct ia_css_stream *stream, + struct ia_css_isp_config *config); + +/** @brief allocate continuous raw frames for continuous capture + * @param[in] stream The stream. + * @return IA_CSS_SUCCESS or error code. + * + * because this allocation takes a long time (around 120ms per frame), + * we separate the allocation part and update part to let driver call + * this function without locking. This function is the allocation part + * and next one is update part + */ +enum ia_css_err +ia_css_alloc_continuous_frame_remain(struct ia_css_stream *stream); + +/** @brief allocate continuous raw frames for continuous capture + * @param[in] stream The stream. + * @return IA_CSS_SUCCESS or error code. + * + * because this allocation takes a long time (around 120ms per frame), + * we separate the allocation part and update part to let driver call + * this function without locking. This function is the update part + */ +enum ia_css_err +ia_css_update_continuous_frames(struct ia_css_stream *stream); + +/** @brief ia_css_unlock_raw_frame . unlock a raw frame (HALv3 Support) + * @param[in] stream The stream. + * @param[in] exp_id exposure id that uniquely identifies the locked Raw Frame Buffer + * @return ia_css_err IA_CSS_SUCCESS or error code + * + * As part of HALv3 Feature requirement, SP locks raw buffer until the Application + * releases its reference to a raw buffer (which are managed by SP), this function allows + * application to explicitly unlock that buffer in SP. + */ +enum ia_css_err +ia_css_unlock_raw_frame(struct ia_css_stream *stream, uint32_t exp_id); + +/** @brief ia_css_en_dz_capt_pipe . Enable/Disable digital zoom for capture pipe + * @param[in] stream The stream. + * @param[in] enable - true, disable - false + * @return None + * + * Enables or disables digital zoom for capture pipe in provided stream, if capture pipe + * exists. This function sets enable_zoom flag in CAPTURE_PP stage of the capture pipe. + * In process_zoom_and_motion(), decision to enable or disable zoom for every stage depends + * on this flag. + */ +void +ia_css_en_dz_capt_pipe(struct ia_css_stream *stream, bool enable); +#endif /* __IA_CSS_STREAM_PUBLIC_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_timer.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_timer.h new file mode 100644 index 0000000000000000000000000000000000000000..575bb28b4becc09810b2009386fec9dbdfbe3166 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_timer.h @@ -0,0 +1,84 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef __IA_CSS_TIMER_H +#define __IA_CSS_TIMER_H + +/** @file + * Timer interface definitions + */ +#include /* for uint32_t */ +#include "ia_css_err.h" + +/** @brief timer reading definition */ +typedef uint32_t clock_value_t; + +/** @brief 32 bit clock tick,(timestamp based on timer-value of CSS-internal timer)*/ +struct ia_css_clock_tick { + clock_value_t ticks; /**< measured time in ticks.*/ +}; + +/** @brief TIMER event codes */ +enum ia_css_tm_event { + IA_CSS_TM_EVENT_AFTER_INIT, + /**< Timer Event after Initialization */ + IA_CSS_TM_EVENT_MAIN_END, + /**< Timer Event after end of Main */ + IA_CSS_TM_EVENT_THREAD_START, + /**< Timer Event after thread start */ + IA_CSS_TM_EVENT_FRAME_PROC_START, + /**< Timer Event after Frame Process Start */ + IA_CSS_TM_EVENT_FRAME_PROC_END + /**< Timer Event after Frame Process End */ +}; + +/** @brief code measurement common struct */ +struct ia_css_time_meas { + clock_value_t start_timer_value; /**< measured time in ticks */ + clock_value_t end_timer_value; /**< measured time in ticks */ +}; + +/**@brief SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT checks to ensure correct alignment for struct ia_css_clock_tick. */ +#define SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT sizeof(clock_value_t) +/** @brief checks to ensure correct alignment for ia_css_time_meas. */ +#define SIZE_OF_IA_CSS_TIME_MEAS_STRUCT (sizeof(clock_value_t) \ + + sizeof(clock_value_t)) + +/** @brief API to fetch timer count directly +* +* @param curr_ts [out] measured count value +* @return IA_CSS_SUCCESS if success +* +*/ +enum ia_css_err +ia_css_timer_get_current_tick( + struct ia_css_clock_tick *curr_ts); + +#endif /* __IA_CSS_TIMER_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_tpg.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_tpg.h new file mode 100644 index 0000000000000000000000000000000000000000..9238a3317a464cdddc4faa629e9aa9e6c72d079a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_tpg.h @@ -0,0 +1,78 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_TPG_H +#define __IA_CSS_TPG_H + +/** @file + * This file contains support for the test pattern generator (TPG) + */ + +/** Enumerate the TPG IDs. + */ +enum ia_css_tpg_id { + IA_CSS_TPG_ID0, + IA_CSS_TPG_ID1, + IA_CSS_TPG_ID2 +}; + +/** + * Maximum number of TPG IDs. + * + * Make sure the value of this define gets changed to reflect the correct + * number of ia_css_tpg_id enum if you add/delete an item in the enum. + */ +#define N_CSS_TPG_IDS (IA_CSS_TPG_ID2+1) + +/** Enumerate the TPG modes. + */ +enum ia_css_tpg_mode { + IA_CSS_TPG_MODE_RAMP, + IA_CSS_TPG_MODE_CHECKERBOARD, + IA_CSS_TPG_MODE_FRAME_BASED_COLOR, + IA_CSS_TPG_MODE_MONO +}; + +/** @brief Configure the test pattern generator. + * + * Configure the Test Pattern Generator, the way these values are used to + * generate the pattern can be seen in the HRT extension for the test pattern + * generator: + * devices/test_pat_gen/hrt/include/test_pat_gen.h: hrt_calc_tpg_data(). + * + * This interface is deprecated, it is not portable -> move to input system API + * +@code +unsigned int test_pattern_value(unsigned int x, unsigned int y) +{ + unsigned int x_val, y_val; + if (x_delta > 0) (x_val = (x << x_delta) & x_mask; + else (x_val = (x >> -x_delta) & x_mask; + if (y_delta > 0) (y_val = (y << y_delta) & y_mask; + else (y_val = (y >> -y_delta) & x_mask; + return (x_val + y_val) & xy_mask; +} +@endcode + */ +struct ia_css_tpg_config { + enum ia_css_tpg_id id; + enum ia_css_tpg_mode mode; + unsigned int x_mask; + int x_delta; + unsigned int y_mask; + int y_delta; + unsigned int xy_mask; +}; + +#endif /* __IA_CSS_TPG_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_types.h new file mode 100644 index 0000000000000000000000000000000000000000..5fec3d5c89d88186828f9692c4818dbf104b366d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_types.h @@ -0,0 +1,654 @@ +/* Release Version: irci_stable_candrpv_0415_20150521_0458 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_TYPES_H +#define _IA_CSS_TYPES_H + +/** @file + * This file contains types used for the ia_css parameters. + * These types are in a separate file because they are expected + * to be used in software layers that do not access the CSS API + * directly but still need to forward parameters for it. + */ + +#include + +#include "ia_css_frac.h" + +#include "isp/kernels/aa/aa_2/ia_css_aa2_types.h" +#include "isp/kernels/anr/anr_1.0/ia_css_anr_types.h" +#include "isp/kernels/anr/anr_2/ia_css_anr2_types.h" +#include "isp/kernels/cnr/cnr_2/ia_css_cnr2_types.h" +#include "isp/kernels/csc/csc_1.0/ia_css_csc_types.h" +#include "isp/kernels/ctc/ctc_1.0/ia_css_ctc_types.h" +#include "isp/kernels/dp/dp_1.0/ia_css_dp_types.h" +#include "isp/kernels/de/de_1.0/ia_css_de_types.h" +#include "isp/kernels/de/de_2/ia_css_de2_types.h" +#include "isp/kernels/fc/fc_1.0/ia_css_formats_types.h" +#include "isp/kernels/fpn/fpn_1.0/ia_css_fpn_types.h" +#include "isp/kernels/gc/gc_1.0/ia_css_gc_types.h" +#include "isp/kernels/gc/gc_2/ia_css_gc2_types.h" +#include "isp/kernels/macc/macc_1.0/ia_css_macc_types.h" +#include "isp/kernels/ob/ob_1.0/ia_css_ob_types.h" +#include "isp/kernels/s3a/s3a_1.0/ia_css_s3a_types.h" +#include "isp/kernels/sc/sc_1.0/ia_css_sc_types.h" +#include "isp/kernels/sdis/sdis_1.0/ia_css_sdis_types.h" +#include "isp/kernels/sdis/sdis_2/ia_css_sdis2_types.h" +#include "isp/kernels/tnr/tnr_1.0/ia_css_tnr_types.h" +#include "isp/kernels/wb/wb_1.0/ia_css_wb_types.h" +#include "isp/kernels/xnr/xnr_1.0/ia_css_xnr_types.h" +#include "isp/kernels/xnr/xnr_3.0/ia_css_xnr3_types.h" +#ifdef ISP2401 +#include "isp/kernels/tnr/tnr3/ia_css_tnr3_types.h" +#endif +#include "isp/kernels/ynr/ynr_1.0/ia_css_ynr_types.h" +#include "isp/kernels/ynr/ynr_2/ia_css_ynr2_types.h" +#include "isp/kernels/output/output_1.0/ia_css_output_types.h" + +#define IA_CSS_DVS_STAT_GRID_INFO_SUPPORTED +/**< Should be removed after Driver adaptation will be done */ + +#define IA_CSS_VERSION_MAJOR 2 +#define IA_CSS_VERSION_MINOR 0 +#define IA_CSS_VERSION_REVISION 2 + +#define IA_CSS_MORPH_TABLE_NUM_PLANES 6 + +/* Min and max exposure IDs. These macros are here to allow + * the drivers to get this information. Changing these macros + * constitutes a CSS API change. */ +#define IA_CSS_ISYS_MIN_EXPOSURE_ID 1 /**< Minimum exposure ID */ +#define IA_CSS_ISYS_MAX_EXPOSURE_ID 250 /**< Maximum exposure ID */ + +/* opaque types */ +struct ia_css_isp_parameters; +struct ia_css_pipe; +struct ia_css_memory_offsets; +struct ia_css_config_memory_offsets; +struct ia_css_state_memory_offsets; + +/** Virtual address within the CSS address space. */ +typedef uint32_t ia_css_ptr; + +/** Generic resolution structure. + */ +struct ia_css_resolution { + uint32_t width; /**< Width */ + uint32_t height; /**< Height */ +}; + +/** Generic coordinate structure. + */ +struct ia_css_coordinate { + int32_t x; /**< Value of a coordinate on the horizontal axis */ + int32_t y; /**< Value of a coordinate on the vertical axis */ +}; + +/** Vector with signed values. This is used to indicate motion for + * Digital Image Stabilization. + */ +struct ia_css_vector { + int32_t x; /**< horizontal motion (in pixels) */ + int32_t y; /**< vertical motion (in pixels) */ +}; + +/* Short hands */ +#define IA_CSS_ISP_DMEM IA_CSS_ISP_DMEM0 +#define IA_CSS_ISP_VMEM IA_CSS_ISP_VMEM0 + +/** CSS data descriptor */ +struct ia_css_data { + ia_css_ptr address; /**< CSS virtual address */ + uint32_t size; /**< Disabled if 0 */ +}; + +/** Host data descriptor */ +struct ia_css_host_data { + char *address; /**< Host address */ + uint32_t size; /**< Disabled if 0 */ +}; + +/** ISP data descriptor */ +struct ia_css_isp_data { + uint32_t address; /**< ISP address */ + uint32_t size; /**< Disabled if 0 */ +}; + +/** Shading Correction types. */ +enum ia_css_shading_correction_type { +#ifndef ISP2401 + IA_CSS_SHADING_CORRECTION_TYPE_1 /**< Shading Correction 1.0 (pipe 1.0 on ISP2300, pipe 2.2 on ISP2400) */ +#else + IA_CSS_SHADING_CORRECTION_NONE, /**< Shading Correction is not processed in the pipe. */ + IA_CSS_SHADING_CORRECTION_TYPE_1 /**< Shading Correction 1.0 (pipe 1.0 on ISP2300, pipe 2.2 on ISP2400/2401) */ +#endif + + /**< More shading correction types can be added in the future. */ +}; + +/** Shading Correction information. */ +struct ia_css_shading_info { + enum ia_css_shading_correction_type type; /**< Shading Correction type. */ + + union { /** Shading Correction information of each Shading Correction types. */ + + /** Shading Correction information of IA_CSS_SHADING_CORRECTION_TYPE_1. + * + * This structure contains the information necessary to generate + * the shading table required in the isp. + * This structure is filled in the css, + * and the driver needs to get it to generate the shading table. + * + * Before the shading correction is applied, NxN-filter and/or scaling + * are applied in the isp, depending on the isp binaries. + * Then, these should be considered in generating the shading table. + * - Bad pixels on left/top sides generated by NxN-filter + * (Bad pixels are NOT considered currently, + * because they are subtle.) + * - Down-scaling/Up-scaling factor + * + * Shading correction is applied to the area + * which has real sensor data and margin. + * Then, the shading table should cover the area including margin. + * This structure has this information. + * - Origin coordinate of bayer (real sensor data) + * on the shading table + * + * ------------------------ISP 2401----------------------- + * + * the shading table directly required from ISP. + * This structure is filled in CSS, and the driver needs to get it to generate the shading table. + * + * The shading correction is applied to the bayer area which contains sensor data and padding data. + * The shading table should cover this bayer area. + * + * The shading table size directly required from ISP is expressed by these parameters. + * 1. uint32_t num_hor_grids; + * 2. uint32_t num_ver_grids; + * 3. uint32_t bqs_per_grid_cell; + * + * In some isp binaries, the bayer scaling is applied before the shading correction is applied. + * Then, this scaling factor should be considered in generating the shading table. + * The scaling factor is expressed by these parameters. + * 4. uint32_t bayer_scale_hor_ratio_in; + * 5. uint32_t bayer_scale_hor_ratio_out; + * 6. uint32_t bayer_scale_ver_ratio_in; + * 7. uint32_t bayer_scale_ver_ratio_out; + * + * The sensor data size inputted to ISP is expressed by this parameter. + * This is the size BEFORE the bayer scaling is applied. + * 8. struct ia_css_resolution isp_input_sensor_data_res_bqs; + * + * The origin of the sensor data area positioned on the shading table at the shading correction + * is expressed by this parameter. + * The size of this area assumes the size AFTER the bayer scaling is applied + * to the isp_input_sensor_data_resolution_bqs. + * 9. struct ia_css_coordinate sensor_data_origin_bqs_on_sctbl; + * + * ****** Definitions of the shading table and the sensor data at the shading correction ****** + * + * (0,0)--------------------- TW ------------------------------- + * | shading table | + * | (ox,oy)---------- W -------------------------- | + * | | sensor data | | + * | | | | + * TH H sensor data center | | + * | | (cx,cy) | | + * | | | | + * | | | | + * | | | | + * | ------------------------------------------- | + * | | + * ---------------------------------------------------------- + * + * Example of still mode for output 1080p: + * + * num_hor_grids = 66 + * num_ver_grids = 37 + * bqs_per_grid_cell = 16 + * bayer_scale_hor_ratio_in = 1 + * bayer_scale_hor_ratio_out = 1 + * bayer_scale_ver_ratio_in = 1 + * bayer_scale_ver_ratio_out = 1 + * isp_input_sensor_data_resolution_bqs = {966, 546} + * sensor_data_origin_bqs_on_sctbl = {61, 15} + * + * TW, TH [bqs]: width and height of shading table + * TW = (num_hor_grids - 1) * bqs_per_grid_cell = (66 - 1) * 16 = 1040 + * TH = (num_ver_grids - 1) * bqs_per_grid_cell = (37 - 1) * 16 = 576 + * + * W, H [bqs]: width and height of sensor data at shading correction + * W = sensor_data_res_bqs.width + * = isp_input_sensor_data_res_bqs.width + * * bayer_scale_hor_ratio_out / bayer_scale_hor_ratio_in + 0.5 = 966 + * H = sensor_data_res_bqs.height + * = isp_input_sensor_data_res_bqs.height + * * bayer_scale_ver_ratio_out / bayer_scale_ver_ratio_in + 0.5 = 546 + * + * (ox, oy) [bqs]: origin of sensor data positioned on shading table at shading correction + * ox = sensor_data_origin_bqs_on_sctbl.x = 61 + * oy = sensor_data_origin_bqs_on_sctbl.y = 15 + * + * (cx, cy) [bqs]: center of sensor data positioned on shading table at shading correction + * cx = ox + W/2 = 61 + 966/2 = 544 + * cy = oy + H/2 = 15 + 546/2 = 288 + * + * ****** Relation between the shading table and the sensor data ****** + * + * The origin of the sensor data should be on the shading table. + * 0 <= ox < TW, 0 <= oy < TH + * + * ****** How to center the shading table on the sensor data ****** + * + * To center the shading table on the sensor data, + * CSS decides the shading table size so that a certain grid point is positioned + * on the center of the sensor data at the shading correction. + * CSS expects the shading center is set on this grid point + * when the shading table data is calculated in AIC. + * + * W, H [bqs]: width and height of sensor data at shading correction + * W = sensor_data_res_bqs.width + * H = sensor_data_res_bqs.height + * + * (cx, cy) [bqs]: center of sensor data positioned on shading table at shading correction + * cx = sensor_data_origin_bqs_on_sctbl.x + W/2 + * cy = sensor_data_origin_bqs_on_sctbl.y + H/2 + * + * CSS decides the shading table size and the sensor data position + * so that the (cx, cy) satisfies this condition. + * mod(cx, bqs_per_grid_cell) = 0 + * mod(cy, bqs_per_grid_cell) = 0 + * + * ****** How to change the sensor data size by processes in the driver and ISP ****** + * + * 1. sensor data size: Physical sensor size + * (The struct ia_css_shading_info does not have this information.) + * 2. process: Driver applies the sensor cropping/binning/scaling to physical sensor size. + * 3. sensor data size: ISP input size (== shading_info.isp_input_sensor_data_res_bqs) + * (ISP assumes the ISP input sensor data is centered on the physical sensor.) + * 4. process: ISP applies the bayer scaling by the factor of shading_info.bayer_scale_*. + * 5. sensor data size: Scaling factor * ISP input size (== shading_info.sensor_data_res_bqs) + * 6. process: ISP applies the shading correction. + * + * ISP block: SC1 + * ISP1: SC1 is used. + * ISP2: SC1 is used. + */ + struct { +#ifndef ISP2401 + uint32_t enable; /**< Shading correction enabled. + 0:disabled, 1:enabled */ + uint32_t num_hor_grids; /**< Number of data points per line + per color on shading table. */ + uint32_t num_ver_grids; /**< Number of lines of data points + per color on shading table. */ + uint32_t bqs_per_grid_cell; /**< Grid cell size + in BQ(Bayer Quad) unit. + (1BQ means {Gr,R,B,Gb}(2x2 pixels).) + Valid values are 8,16,32,64. */ +#else + uint32_t num_hor_grids; /**< Number of data points per line per color on shading table. */ + uint32_t num_ver_grids; /**< Number of lines of data points per color on shading table. */ + uint32_t bqs_per_grid_cell; /**< Grid cell size in BQ unit. + NOTE: bqs = size in BQ(Bayer Quad) unit. + 1BQ means {Gr,R,B,Gb} (2x2 pixels). + Horizontal 1 bqs corresponds to horizontal 2 pixels. + Vertical 1 bqs corresponds to vertical 2 pixels. */ +#endif + uint32_t bayer_scale_hor_ratio_in; + uint32_t bayer_scale_hor_ratio_out; +#ifndef ISP2401 + /**< Horizontal ratio of bayer scaling + between input width and output width, for the scaling + which should be done before shading correction. + output_width = input_width * bayer_scale_hor_ratio_out + / bayer_scale_hor_ratio_in */ +#else + /**< Horizontal ratio of bayer scaling between input width and output width, + for the scaling which should be done before shading correction. + output_width = input_width * bayer_scale_hor_ratio_out + / bayer_scale_hor_ratio_in + 0.5 */ +#endif + uint32_t bayer_scale_ver_ratio_in; + uint32_t bayer_scale_ver_ratio_out; +#ifndef ISP2401 + /**< Vertical ratio of bayer scaling + between input height and output height, for the scaling + which should be done before shading correction. + output_height = input_height * bayer_scale_ver_ratio_out + / bayer_scale_ver_ratio_in */ + uint32_t sc_bayer_origin_x_bqs_on_shading_table; + /**< X coordinate (in bqs) of bayer origin on shading table. + This indicates the left-most pixel of bayer + (not include margin) inputted to the shading correction. + This corresponds to the left-most pixel of bayer + inputted to isp from sensor. */ + uint32_t sc_bayer_origin_y_bqs_on_shading_table; + /**< Y coordinate (in bqs) of bayer origin on shading table. + This indicates the top pixel of bayer + (not include margin) inputted to the shading correction. + This corresponds to the top pixel of bayer + inputted to isp from sensor. */ +#else + /**< Vertical ratio of bayer scaling between input height and output height, + for the scaling which should be done before shading correction. + output_height = input_height * bayer_scale_ver_ratio_out + / bayer_scale_ver_ratio_in + 0.5 */ + struct ia_css_resolution isp_input_sensor_data_res_bqs; + /**< Sensor data size (in bqs) inputted to ISP. This is the size BEFORE bayer scaling. + NOTE: This is NOT the size of the physical sensor size. + CSS requests the driver that ISP inputs sensor data + by the size of isp_input_sensor_data_res_bqs. + The driver sends the sensor data to ISP, + after the adequate cropping/binning/scaling + are applied to the physical sensor data area. + ISP assumes the area of isp_input_sensor_data_res_bqs + is centered on the physical sensor. */ + struct ia_css_resolution sensor_data_res_bqs; + /**< Sensor data size (in bqs) at shading correction. + This is the size AFTER bayer scaling. */ + struct ia_css_coordinate sensor_data_origin_bqs_on_sctbl; + /**< Origin of sensor data area positioned on shading table at shading correction. + The coordinate x,y should be positive values. */ +#endif + } type_1; + + /**< More structures can be added here when more shading correction types will be added + in the future. */ + } info; +}; + +#ifndef ISP2401 + +/** Default Shading Correction information of Shading Correction Type 1. */ +#define DEFAULT_SHADING_INFO_TYPE_1 \ +{ \ + IA_CSS_SHADING_CORRECTION_TYPE_1, /* type */ \ + { /* info */ \ + { \ + 0, /* enable */ \ + 0, /* num_hor_grids */ \ + 0, /* num_ver_grids */ \ + 0, /* bqs_per_grid_cell */ \ + 1, /* bayer_scale_hor_ratio_in */ \ + 1, /* bayer_scale_hor_ratio_out */ \ + 1, /* bayer_scale_ver_ratio_in */ \ + 1, /* bayer_scale_ver_ratio_out */ \ + 0, /* sc_bayer_origin_x_bqs_on_shading_table */ \ + 0 /* sc_bayer_origin_y_bqs_on_shading_table */ \ + } \ + } \ +} + +#else + +/** Default Shading Correction information of Shading Correction Type 1. */ +#define DEFAULT_SHADING_INFO_TYPE_1 \ +{ \ + IA_CSS_SHADING_CORRECTION_TYPE_1, /* type */ \ + { /* info */ \ + { \ + 0, /* num_hor_grids */ \ + 0, /* num_ver_grids */ \ + 0, /* bqs_per_grid_cell */ \ + 1, /* bayer_scale_hor_ratio_in */ \ + 1, /* bayer_scale_hor_ratio_out */ \ + 1, /* bayer_scale_ver_ratio_in */ \ + 1, /* bayer_scale_ver_ratio_out */ \ + {0, 0}, /* isp_input_sensor_data_res_bqs */ \ + {0, 0}, /* sensor_data_res_bqs */ \ + {0, 0} /* sensor_data_origin_bqs_on_sctbl */ \ + } \ + } \ +} + +#endif + +/** Default Shading Correction information. */ +#define DEFAULT_SHADING_INFO DEFAULT_SHADING_INFO_TYPE_1 + +/** structure that describes the 3A and DIS grids */ +struct ia_css_grid_info { + /** \name ISP input size + * that is visible for user + * @{ + */ + uint32_t isp_in_width; + uint32_t isp_in_height; + /** @}*/ + + struct ia_css_3a_grid_info s3a_grid; /**< 3A grid info */ + union ia_css_dvs_grid_u dvs_grid; + /**< All types of DVS statistics grid info union */ + + enum ia_css_vamem_type vamem_type; +}; + +/** defaults for ia_css_grid_info structs */ +#define DEFAULT_GRID_INFO \ +{ \ + 0, /* isp_in_width */ \ + 0, /* isp_in_height */ \ + DEFAULT_3A_GRID_INFO, /* s3a_grid */ \ + DEFAULT_DVS_GRID_INFO, /* dvs_grid */ \ + IA_CSS_VAMEM_TYPE_1 /* vamem_type */ \ +} + +/** Morphing table, used for geometric distortion and chromatic abberration + * correction (GDCAC, also called GDC). + * This table describes the imperfections introduced by the lens, the + * advanced ISP can correct for these imperfections using this table. + */ +struct ia_css_morph_table { + uint32_t enable; /**< To disable GDC, set this field to false. The + coordinates fields can be set to NULL in this case. */ + uint32_t height; /**< Table height */ + uint32_t width; /**< Table width */ + uint16_t *coordinates_x[IA_CSS_MORPH_TABLE_NUM_PLANES]; + /**< X coordinates that describe the sensor imperfection */ + uint16_t *coordinates_y[IA_CSS_MORPH_TABLE_NUM_PLANES]; + /**< Y coordinates that describe the sensor imperfection */ +}; + +struct ia_css_dvs_6axis_config { + unsigned int exp_id; + /**< Exposure ID, see ia_css_event_public.h for more detail */ + uint32_t width_y; + uint32_t height_y; + uint32_t width_uv; + uint32_t height_uv; + uint32_t *xcoords_y; + uint32_t *ycoords_y; + uint32_t *xcoords_uv; + uint32_t *ycoords_uv; +}; + +/** + * This specifies the coordinates (x,y) + */ +struct ia_css_point { + int32_t x; /**< x coordinate */ + int32_t y; /**< y coordinate */ +}; + +/** + * This specifies the region + */ +struct ia_css_region { + struct ia_css_point origin; /**< Starting point coordinates for the region */ + struct ia_css_resolution resolution; /**< Region resolution */ +}; + +/** + * Digital zoom: + * This feature is currently available only for video, but will become + * available for preview and capture as well. + * Set the digital zoom factor, this is a logarithmic scale. The actual zoom + * factor will be 64/x. + * Setting dx or dy to 0 disables digital zoom for that direction. + * New API change for Digital zoom:(added struct ia_css_region zoom_region) + * zoom_region specifies the origin of the zoom region and width and + * height of that region. + * origin : This is the coordinate (x,y) within the effective input resolution + * of the stream. where, x >= 0 and y >= 0. (0,0) maps to the upper left of the + * effective input resolution. + * resolution : This is resolution of zoom region. + * where, x + width <= effective input width + * y + height <= effective input height + */ +struct ia_css_dz_config { + uint32_t dx; /**< Horizontal zoom factor */ + uint32_t dy; /**< Vertical zoom factor */ + struct ia_css_region zoom_region; /**< region for zoom */ +}; + +/** The still capture mode, this can be RAW (simply copy sensor input to DDR), + * Primary ISP, the Advanced ISP (GDC) or the low-light ISP (ANR). + */ +enum ia_css_capture_mode { + IA_CSS_CAPTURE_MODE_RAW, /**< no processing, copy data only */ + IA_CSS_CAPTURE_MODE_BAYER, /**< bayer processing, up to demosaic */ + IA_CSS_CAPTURE_MODE_PRIMARY, /**< primary ISP */ + IA_CSS_CAPTURE_MODE_ADVANCED, /**< advanced ISP (GDC) */ + IA_CSS_CAPTURE_MODE_LOW_LIGHT /**< low light ISP (ANR) */ +}; + +struct ia_css_capture_config { + enum ia_css_capture_mode mode; /**< Still capture mode */ + uint32_t enable_xnr; /**< Enable/disable XNR */ + uint32_t enable_raw_output; + bool enable_capture_pp_bli; /**< Enable capture_pp_bli mode */ +}; + +/** default settings for ia_css_capture_config structs */ +#define DEFAULT_CAPTURE_CONFIG \ +{ \ + IA_CSS_CAPTURE_MODE_PRIMARY, /* mode (capture) */ \ + false, /* enable_xnr */ \ + false, /* enable_raw_output */ \ + false /* enable_capture_pp_bli */ \ +} + + +/** ISP filter configuration. This is a collection of configurations + * for each of the ISP filters (modules). + * + * NOTE! The contents of all pointers is copied when get or set with the + * exception of the shading and morph tables. For these we only copy the + * pointer, so the caller must make sure the memory contents of these pointers + * remain valid as long as they are used by the CSS. This will be fixed in the + * future by copying the contents instead of just the pointer. + * + * Comment: + * ["ISP block", 1&2] : ISP block is used both for ISP1 and ISP2. + * ["ISP block", 1only] : ISP block is used only for ISP1. + * ["ISP block", 2only] : ISP block is used only for ISP2. + */ +struct ia_css_isp_config { + struct ia_css_wb_config *wb_config; /**< White Balance + [WB1, 1&2] */ + struct ia_css_cc_config *cc_config; /**< Color Correction + [CSC1, 1only] */ + struct ia_css_tnr_config *tnr_config; /**< Temporal Noise Reduction + [TNR1, 1&2] */ + struct ia_css_ecd_config *ecd_config; /**< Eigen Color Demosaicing + [DE2, 2only] */ + struct ia_css_ynr_config *ynr_config; /**< Y(Luma) Noise Reduction + [YNR2&YEE2, 2only] */ + struct ia_css_fc_config *fc_config; /**< Fringe Control + [FC2, 2only] */ + struct ia_css_formats_config *formats_config; /**< Formats Control for main output + [FORMATS, 1&2] */ + struct ia_css_cnr_config *cnr_config; /**< Chroma Noise Reduction + [CNR2, 2only] */ + struct ia_css_macc_config *macc_config; /**< MACC + [MACC2, 2only] */ + struct ia_css_ctc_config *ctc_config; /**< Chroma Tone Control + [CTC2, 2only] */ + struct ia_css_aa_config *aa_config; /**< YUV Anti-Aliasing + [AA2, 2only] + (not used currently) */ + struct ia_css_aa_config *baa_config; /**< Bayer Anti-Aliasing + [BAA2, 1&2] */ + struct ia_css_ce_config *ce_config; /**< Chroma Enhancement + [CE1, 1only] */ + struct ia_css_dvs_6axis_config *dvs_6axis_config; + struct ia_css_ob_config *ob_config; /**< Objective Black + [OB1, 1&2] */ + struct ia_css_dp_config *dp_config; /**< Defect Pixel Correction + [DPC1/DPC2, 1&2] */ + struct ia_css_nr_config *nr_config; /**< Noise Reduction + [BNR1&YNR1&CNR1, 1&2]*/ + struct ia_css_ee_config *ee_config; /**< Edge Enhancement + [YEE1, 1&2] */ + struct ia_css_de_config *de_config; /**< Demosaic + [DE1, 1only] */ + struct ia_css_gc_config *gc_config; /**< Gamma Correction (for YUV) + [GC1, 1only] */ + struct ia_css_anr_config *anr_config; /**< Advanced Noise Reduction */ + struct ia_css_3a_config *s3a_config; /**< 3A Statistics config */ + struct ia_css_xnr_config *xnr_config; /**< eXtra Noise Reduction */ + struct ia_css_dz_config *dz_config; /**< Digital Zoom */ + struct ia_css_cc_config *yuv2rgb_cc_config; /**< Color Correction + [CCM2, 2only] */ + struct ia_css_cc_config *rgb2yuv_cc_config; /**< Color Correction + [CSC2, 2only] */ + struct ia_css_macc_table *macc_table; /**< MACC + [MACC1/MACC2, 1&2]*/ + struct ia_css_gamma_table *gamma_table; /**< Gamma Correction (for YUV) + [GC1, 1only] */ + struct ia_css_ctc_table *ctc_table; /**< Chroma Tone Control + [CTC1, 1only] */ + + /** \deprecated */ + struct ia_css_xnr_table *xnr_table; /**< eXtra Noise Reduction + [XNR1, 1&2] */ + struct ia_css_rgb_gamma_table *r_gamma_table;/**< sRGB Gamma Correction + [GC2, 2only] */ + struct ia_css_rgb_gamma_table *g_gamma_table;/**< sRGB Gamma Correction + [GC2, 2only] */ + struct ia_css_rgb_gamma_table *b_gamma_table;/**< sRGB Gamma Correction + [GC2, 2only] */ + struct ia_css_vector *motion_vector; /**< For 2-axis DVS */ + struct ia_css_shading_table *shading_table; + struct ia_css_morph_table *morph_table; + struct ia_css_dvs_coefficients *dvs_coefs; /**< DVS 1.0 coefficients */ + struct ia_css_dvs2_coefficients *dvs2_coefs; /**< DVS 2.0 coefficients */ + struct ia_css_capture_config *capture_config; + struct ia_css_anr_thres *anr_thres; + /** @deprecated{Old shading settings, see bugzilla bz675 for details} */ + struct ia_css_shading_settings *shading_settings; + struct ia_css_xnr3_config *xnr3_config; /**< eXtreme Noise Reduction v3 */ + /** comment from Lasse: Be aware how this feature will affect coordinate + * normalization in different parts of the system. (e.g. face detection, + * touch focus, 3A statistics and windows of interest, shading correction, + * DVS, GDC) from IQ tool level and application level down-to ISP FW level. + * the risk for regression is not in the individual blocks, but how they + * integrate together. */ + struct ia_css_output_config *output_config; /**< Main Output Mirroring, flipping */ + +#ifdef ISP2401 + struct ia_css_tnr3_kernel_config *tnr3_config; /**< TNR3 config */ +#endif + struct ia_css_scaler_config *scaler_config; /**< Skylake: scaler config (optional) */ + struct ia_css_formats_config *formats_config_display;/**< Formats control for viewfinder/display output (optional) + [OSYS, n/a] */ + struct ia_css_output_config *output_config_display; /**< Viewfinder/display output mirroring, flipping (optional) */ + + struct ia_css_frame *output_frame; /**< Output frame the config is to be applied to (optional) */ + uint32_t isp_config_id; /**< Unique ID to track which config was actually applied to a particular frame */ +}; + +#endif /* _IA_CSS_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_version.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_version.h new file mode 100644 index 0000000000000000000000000000000000000000..48c59896e8479fa2185cf50e1b5e067bba35e5e8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_version.h @@ -0,0 +1,40 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_VERSION_H +#define __IA_CSS_VERSION_H + +/** @file + * This file contains functions to retrieve CSS-API version information + */ + +#include + +/** a common size for the version arrays */ +#define MAX_VERSION_SIZE 500 + +/** @brief Retrieves the current CSS version + * @param[out] version A pointer to a buffer where to put the generated + * version string. NULL is ignored. + * @param[in] max_size Size of the version buffer. If version string + * would be larger than max_size, an error is + * returned by this function. + * + * This function generates and returns the version string. If FW is loaded, it + * attaches the FW version. + */ +enum ia_css_err +ia_css_get_version(char *version, int max_size); + +#endif /* __IA_CSS_VERSION_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_version_data.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_version_data.h new file mode 100644 index 0000000000000000000000000000000000000000..aad592cb86ef0fbd96f38301ffc3bfb1b92d5dd1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/ia_css_version_data.h @@ -0,0 +1,33 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +// +// This file contains the version data for the CSS +// +// === Do not change - automatically generated === +// + +#ifndef __IA_CSS_VERSION_DATA_H +#define __IA_CSS_VERSION_DATA_H + + +#ifndef ISP2401 +#define CSS_VERSION_STRING "REL:20150521_21.4_0539; API:2.1.15.3; GIT:irci_candrpv_0415_20150504_35b345#35b345be52ac575f8934abb3a88fea26a94e7343; SDK:/nfs/iir/disks/iir_hivepackages_003/iir_hivepkgs_disk017/Css_Mizuchi/packages/Css_Mizuchi/int_css_mizuchi_20140829_1053; USER:viedifw; " +#else +#define CSS_VERSION_STRING "REL:20150911_37.5_1652; API:2.1.20.9; GIT:irci___#ebf437d53a8951bb7ff6d13fdb7270dab393a92a; SDK:; USER:viedifw; " +#endif + + +#endif + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/aa/aa_2/ia_css_aa2.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/aa/aa_2/ia_css_aa2.host.c new file mode 100644 index 0000000000000000000000000000000000000000..942ebe078739cd8618459dadf66835cb500517fb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/aa/aa_2/ia_css_aa2.host.c @@ -0,0 +1,66 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" +#endif + +#include "ia_css_aa2.host.h" + +/* YUV Anti-Aliasing configuration. */ +const struct ia_css_aa_config default_aa_config = { + 8191 /* default should be 0 */ +}; + +/* Bayer Anti-Aliasing configuration. */ +const struct ia_css_aa_config default_baa_config = { + 8191 /* default should be 0 */ +}; + +void +ia_css_aa_encode( + struct sh_css_isp_aa_params *to, + const struct ia_css_aa_config *from, + unsigned size) +{ + (void)size; + to->strength = from->strength; +} + +void +ia_css_init_aa_state( + void *state, + size_t size) +{ + memset(state, 0, size); +} + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_aa_dump( + const struct sh_css_isp_aa_params *aa, + unsigned level); + +void +ia_css_aa_debug_dtrace( + const struct ia_css_aa_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.strength=%d\n", + config->strength); +} +#endif /* IA_CSS_NO_DEBUG */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/aa/aa_2/ia_css_aa2.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/aa/aa_2/ia_css_aa2.host.h new file mode 100644 index 0000000000000000000000000000000000000000..c3785e0d7c0221edc7c9334c1630ce2ca70c3d70 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/aa/aa_2/ia_css_aa2.host.h @@ -0,0 +1,50 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_AA_HOST_H +#define __IA_CSS_AA_HOST_H + +#include "ia_css_aa2_types.h" +#include "ia_css_aa2_param.h" + +/* YUV Anti-Aliasing configuration. */ +extern const struct ia_css_aa_config default_aa_config; + +/* Bayer Anti-Aliasing configuration. */ +extern const struct ia_css_aa_config default_baa_config; + +void +ia_css_aa_encode( + struct sh_css_isp_aa_params *to, + const struct ia_css_aa_config *from, + unsigned size); + +void +ia_css_init_aa_state( + void *state, + size_t size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_aa_dump( + const struct sh_css_isp_aa_params *aa, + unsigned level); + +void +ia_css_aa_debug_dtrace( + const struct ia_css_aa_config *config, + unsigned level); +#endif /* IA_CSS_NO_DEBUG */ + +#endif /* __IA_CSS_AA_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/aa/aa_2/ia_css_aa2_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/aa/aa_2/ia_css_aa2_param.h new file mode 100644 index 0000000000000000000000000000000000000000..dbab4d6c6cd58270252664a5db92ef03be2eb8f5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/aa/aa_2/ia_css_aa2_param.h @@ -0,0 +1,24 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_AA_PARAM_H +#define __IA_CSS_AA_PARAM_H + +#include "type_support.h" + +struct sh_css_isp_aa_params { + int32_t strength; +}; + +#endif /* __IA_CSS_AA_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/aa/aa_2/ia_css_aa2_state.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/aa/aa_2/ia_css_aa2_state.h new file mode 100644 index 0000000000000000000000000000000000000000..cc404018b112a949bd877c4eec81b56c4e3269b4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/aa/aa_2/ia_css_aa2_state.h @@ -0,0 +1,41 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_AA2_STATE_H +#define __IA_CSS_AA2_STATE_H + +#include "type_support.h" +#include "vmem.h" /* for VMEM_ARRAY*/ + +/* Denotes the maximum number of pixels per line that can be processed: +* MAX_AA_VECTORS_PER_LINE = maximum_line_width / ISP_NWAY */ +#ifndef MAX_AA_VECTORS_PER_LINE +#error Please define MAX_AA_VECTORS_PER_LINE. +#endif + +/* This uses 2 history lines for both y, u and v*/ +#define AA_STATE_Y_BUFFER_HEIGHT 2 +#define AA_STATE_UV_BUFFER_HEIGHT 2 +#define AA_STATE_Y_BUFFER_WIDTH MAX_AA_VECTORS_PER_LINE +/* The number of u and v elements is half y due to yuv420 downsampling. */ +#define AA_STATE_UV_BUFFER_WIDTH (AA_STATE_Y_BUFFER_WIDTH/2) + + +struct ia_css_isp_aa_vmem_state { + VMEM_ARRAY(y[AA_STATE_Y_BUFFER_HEIGHT], AA_STATE_Y_BUFFER_WIDTH*ISP_NWAY); + VMEM_ARRAY(u[AA_STATE_UV_BUFFER_HEIGHT], AA_STATE_UV_BUFFER_WIDTH*ISP_NWAY); + VMEM_ARRAY(v[AA_STATE_UV_BUFFER_HEIGHT], AA_STATE_UV_BUFFER_WIDTH*ISP_NWAY); +}; + +#endif /* __IA_CSS_AA2_STATE_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/aa/aa_2/ia_css_aa2_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/aa/aa_2/ia_css_aa2_types.h new file mode 100644 index 0000000000000000000000000000000000000000..834eedbbeeff651e42baf9309abcb9e930c784b2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/aa/aa_2/ia_css_aa2_types.h @@ -0,0 +1,48 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_AA2_TYPES_H +#define __IA_CSS_AA2_TYPES_H + +/** @file +* CSS-API header file for Anti-Aliasing parameters. +*/ + + +/** Anti-Aliasing configuration. + * + * This structure is used both for YUV AA and Bayer AA. + * + * 1. YUV Anti-Aliasing + * struct ia_css_aa_config *aa_config + * + * ISP block: AA2 + * (ISP1: AA2 is not used.) + * ISP2: AA2 should be used. But, AA2 is not used currently. + * + * 2. Bayer Anti-Aliasing + * struct ia_css_aa_config *baa_config + * + * ISP block: BAA2 + * ISP1: BAA2 is used. + * ISP2: BAA2 is used. + */ +struct ia_css_aa_config { + uint16_t strength; /**< Strength of the filter. + u0.13, [0,8191], + default/ineffective 0 */ +}; + +#endif /* __IA_CSS_AA2_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_1.0/ia_css_anr.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_1.0/ia_css_anr.host.c new file mode 100644 index 0000000000000000000000000000000000000000..edc4f1ae6d5e8da7ab764b6b413ad89b671e6a76 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_1.0/ia_css_anr.host.c @@ -0,0 +1,60 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" + +#include "ia_css_anr.host.h" + +const struct ia_css_anr_config default_anr_config = { + 10, + { 0, 3, 1, 2, 3, 6, 4, 5, 1, 4, 2, 3, 2, 5, 3, 4, + 0, 3, 1, 2, 3, 6, 4, 5, 1, 4, 2, 3, 2, 5, 3, 4, + 0, 3, 1, 2, 3, 6, 4, 5, 1, 4, 2, 3, 2, 5, 3, 4, + 0, 3, 1, 2, 3, 6, 4, 5, 1, 4, 2, 3, 2, 5, 3, 4}, + {10, 20, 30} +}; + +void +ia_css_anr_encode( + struct sh_css_isp_anr_params *to, + const struct ia_css_anr_config *from, + unsigned size) +{ + (void)size; + to->threshold = from->threshold; +} + +void +ia_css_anr_dump( + const struct sh_css_isp_anr_params *anr, + unsigned level) +{ + if (!anr) return; + ia_css_debug_dtrace(level, "Advance Noise Reduction:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "anr_threshold", anr->threshold); +} + +void +ia_css_anr_debug_dtrace( + const struct ia_css_anr_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.threshold=%d\n", + config->threshold); +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_1.0/ia_css_anr.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_1.0/ia_css_anr.host.h new file mode 100644 index 0000000000000000000000000000000000000000..29566c07653cd3942353b1e0096959cc64ba5fc0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_1.0/ia_css_anr.host.h @@ -0,0 +1,39 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ANR_HOST_H +#define __IA_CSS_ANR_HOST_H + +#include "ia_css_anr_types.h" +#include "ia_css_anr_param.h" + +extern const struct ia_css_anr_config default_anr_config; + +void +ia_css_anr_encode( + struct sh_css_isp_anr_params *to, + const struct ia_css_anr_config *from, + unsigned size); + +void +ia_css_anr_dump( + const struct sh_css_isp_anr_params *anr, + unsigned level); + +void +ia_css_anr_debug_dtrace( + const struct ia_css_anr_config *config, unsigned level) +; + +#endif /* __IA_CSS_ANR_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_1.0/ia_css_anr_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_1.0/ia_css_anr_param.h new file mode 100644 index 0000000000000000000000000000000000000000..2621b920c3dca40f5b253d86566883b475b08bdb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_1.0/ia_css_anr_param.h @@ -0,0 +1,25 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ANR_PARAM_H +#define __IA_CSS_ANR_PARAM_H + +#include "type_support.h" + +/* ANR (Advanced Noise Reduction) */ +struct sh_css_isp_anr_params { + int32_t threshold; +}; + +#endif /* __IA_CSS_ANR_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_1.0/ia_css_anr_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_1.0/ia_css_anr_types.h new file mode 100644 index 0000000000000000000000000000000000000000..e205574098f2cf6b3c6260bdebcbf5f5a3accbd8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_1.0/ia_css_anr_types.h @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ANR_TYPES_H +#define __IA_CSS_ANR_TYPES_H + +/** @file +* CSS-API header file for Advanced Noise Reduction kernel v1 +*/ + +/* Application specific DMA settings */ +#define ANR_BPP 10 +#define ANR_ELEMENT_BITS ((CEIL_DIV(ANR_BPP, 8))*8) + +/** Advanced Noise Reduction configuration. + * This is also known as Low-Light. + */ +struct ia_css_anr_config { + int32_t threshold; /**< Threshold */ + int32_t thresholds[4*4*4]; + int32_t factors[3]; +}; + +#endif /* __IA_CSS_ANR_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr2.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr2.host.c new file mode 100644 index 0000000000000000000000000000000000000000..b338c434453e9ecbf4b8ce4b8c9cac973dbf64be --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr2.host.c @@ -0,0 +1,46 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" + +#include "ia_css_anr2.host.h" + +void +ia_css_anr2_vmem_encode( + struct ia_css_isp_anr2_params *to, + const struct ia_css_anr_thres *from, + size_t size) +{ + unsigned i; + + (void)size; + for (i = 0; i < ANR_PARAM_SIZE; i++) { + unsigned j; + for (j = 0; j < ISP_VEC_NELEMS; j++) { + to->data[i][j] = from->data[i*ISP_VEC_NELEMS+j]; + } + } +} + +void +ia_css_anr2_debug_dtrace( + const struct ia_css_anr_thres *config, + unsigned level) +{ + (void)config; + (void)level; +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr2.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr2.host.h new file mode 100644 index 0000000000000000000000000000000000000000..83c37e328591ef056f7d3d5b5a90f2f6609fbe3a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr2.host.h @@ -0,0 +1,35 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ANR2_HOST_H +#define __IA_CSS_ANR2_HOST_H + +#include "sh_css_params.h" + +#include "ia_css_anr2_types.h" +#include "ia_css_anr_param.h" +#include "ia_css_anr2_table.host.h" + +void +ia_css_anr2_vmem_encode( + struct ia_css_isp_anr2_params *to, + const struct ia_css_anr_thres *from, + size_t size); + +void +ia_css_anr2_debug_dtrace( + const struct ia_css_anr_thres *config, unsigned level) +; + +#endif /* __IA_CSS_ANR2_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr2_table.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr2_table.host.c new file mode 100644 index 0000000000000000000000000000000000000000..2de51fe45623f58ed291173a9e45f1e16b439423 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr2_table.host.c @@ -0,0 +1,52 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "system_global.h" +#include "ia_css_types.h" +#include "ia_css_anr2_table.host.h" + +#if 1 +const struct ia_css_anr_thres default_anr_thres = { +{128, 384, 640, 896, 896, 640, 384, 128, 384, 1152, 1920, 2688, 2688, 1920, 1152, 384, 640, 1920, 3200, 4480, 4480, 3200, 1920, 640, 896, 2688, 4480, 6272, 6272, 4480, 2688, 896, 896, 2688, 4480, 6272, 6272, 4480, 2688, 896, 640, 1920, 3200, 4480, 4480, 3200, 1920, 640, 384, 1152, 1920, 2688, 2688, 1920, 1152, 384, 128, 384, 640, 896, 896, 640, 384, 128, +0, 0, 30, 30, 10, 10, 20, 20, 0, 0, 30, 30, 10, 10, 20, 20, 0, 0, 30, 30, 10, 10, 20, 20, 0, 0, 30, 30, 10, 10, 20, 20, 0, 0, 30, 30, 10, 10, 20, 20, 0, 0, 30, 30, 10, 10, 20, 20, 0, 0, 30, 30, 10, 10, 20, 20, 0, 0, 30, 30, 10, 10, 20, 20, +0, 0, 60, 60, 20, 20, 40, 40, 0, 0, 60, 60, 20, 20, 40, 40, 0, 0, 60, 60, 20, 20, 40, 40, 0, 0, 60, 60, 20, 20, 40, 40, 0, 0, 60, 60, 20, 20, 40, 40, 0, 0, 60, 60, 20, 20, 40, 40, 0, 0, 60, 60, 20, 20, 40, 40, 0, 0, 60, 60, 20, 20, 40, 40, +0, 0, 90, 90, 30, 30, 60, 60, 0, 0, 90, 90, 30, 30, 60, 60, 0, 0, 90, 90, 30, 30, 60, 60, 0, 0, 90, 90, 30, 30, 60, 60, 0, 0, 90, 90, 30, 30, 60, 60, 0, 0, 90, 90, 30, 30, 60, 60, 0, 0, 90, 90, 30, 30, 60, 60, 0, 0, 90, 90, 30, 30, 60, 60, +30, 30, 60, 60, 40, 40, 50, 50, 30, 30, 60, 60, 40, 40, 50, 50, 30, 30, 60, 60, 40, 40, 50, 50, 30, 30, 60, 60, 40, 40, 50, 50, 30, 30, 60, 60, 40, 40, 50, 50, 30, 30, 60, 60, 40, 40, 50, 50, 30, 30, 60, 60, 40, 40, 50, 50, 30, 30, 60, 60, 40, 40, 50, 50, +60, 60, 120, 120, 80, 80, 100, 100, 60, 60, 120, 120, 80, 80, 100, 100, 60, 60, 120, 120, 80, 80, 100, 100, 60, 60, 120, 120, 80, 80, 100, 100, 60, 60, 120, 120, 80, 80, 100, 100, 60, 60, 120, 120, 80, 80, 100, 100, 60, 60, 120, 120, 80, 80, 100, 100, 60, 60, 120, 120, 80, 80, 100, 100, +90, 90, 180, 180, 120, 120, 150, 150, 90, 90, 180, 180, 120, 120, 150, 150, 90, 90, 180, 180, 120, 120, 150, 150, 90, 90, 180, 180, 120, 120, 150, 150, 90, 90, 180, 180, 120, 120, 150, 150, 90, 90, 180, 180, 120, 120, 150, 150, 90, 90, 180, 180, 120, 120, 150, 150, 90, 90, 180, 180, 120, 120, 150, 150, +10, 10, 40, 40, 20, 20, 30, 30, 10, 10, 40, 40, 20, 20, 30, 30, 10, 10, 40, 40, 20, 20, 30, 30, 10, 10, 40, 40, 20, 20, 30, 30, 10, 10, 40, 40, 20, 20, 30, 30, 10, 10, 40, 40, 20, 20, 30, 30, 10, 10, 40, 40, 20, 20, 30, 30, 10, 10, 40, 40, 20, 20, 30, 30, +20, 20, 80, 80, 40, 40, 60, 60, 20, 20, 80, 80, 40, 40, 60, 60, 20, 20, 80, 80, 40, 40, 60, 60, 20, 20, 80, 80, 40, 40, 60, 60, 20, 20, 80, 80, 40, 40, 60, 60, 20, 20, 80, 80, 40, 40, 60, 60, 20, 20, 80, 80, 40, 40, 60, 60, 20, 20, 80, 80, 40, 40, 60, 60, +30, 30, 120, 120, 60, 60, 90, 90, 30, 30, 120, 120, 60, 60, 90, 90, 30, 30, 120, 120, 60, 60, 90, 90, 30, 30, 120, 120, 60, 60, 90, 90, 30, 30, 120, 120, 60, 60, 90, 90, 30, 30, 120, 120, 60, 60, 90, 90, 30, 30, 120, 120, 60, 60, 90, 90, 30, 30, 120, 120, 60, 60, 90, 90, +20, 20, 50, 50, 30, 30, 40, 40, 20, 20, 50, 50, 30, 30, 40, 40, 20, 20, 50, 50, 30, 30, 40, 40, 20, 20, 50, 50, 30, 30, 40, 40, 20, 20, 50, 50, 30, 30, 40, 40, 20, 20, 50, 50, 30, 30, 40, 40, 20, 20, 50, 50, 30, 30, 40, 40, 20, 20, 50, 50, 30, 30, 40, 40, +40, 40, 100, 100, 60, 60, 80, 80, 40, 40, 100, 100, 60, 60, 80, 80, 40, 40, 100, 100, 60, 60, 80, 80, 40, 40, 100, 100, 60, 60, 80, 80, 40, 40, 100, 100, 60, 60, 80, 80, 40, 40, 100, 100, 60, 60, 80, 80, 40, 40, 100, 100, 60, 60, 80, 80, 40, 40, 100, 100, 60, 60, 80, 80, +60, 60, 150, 150, 90, 90, 120, 120, 60, 60, 150, 150, 90, 90, 120, 120, 60, 60, 150, 150, 90, 90, 120, 120, 60, 60, 150, 150, 90, 90, 120, 120, 60, 60, 150, 150, 90, 90, 120, 120, 60, 60, 150, 150, 90, 90, 120, 120, 60, 60, 150, 150, 90, 90, 120, 120, 60, 60, 150, 150, 90, 90, 120, 120} +}; +#else +const struct ia_css_anr_thres default_anr_thres = { +{0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} +}; +#endif + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr2_table.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr2_table.host.h new file mode 100644 index 0000000000000000000000000000000000000000..534119e064c14166825c6b3aa754c2774bd968e2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr2_table.host.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ANR2_TABLE_HOST_H +#define __IA_CSS_ANR2_TABLE_HOST_H + +#include "ia_css_anr2_types.h" + +extern const struct ia_css_anr_thres default_anr_thres; + +#endif /* __IA_CSS_ANR2_TABLE_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr2_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr2_types.h new file mode 100644 index 0000000000000000000000000000000000000000..3832ada433ec4b5aa2404baaceeece9476d1c8ba --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr2_types.h @@ -0,0 +1,32 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ANR2_TYPES_H +#define __IA_CSS_ANR2_TYPES_H + +/** @file +* CSS-API header file for Advanced Noise Reduction kernel v2 +*/ + +#include "type_support.h" + +#define ANR_PARAM_SIZE 13 + +/** Advanced Noise Reduction (ANR) thresholds */ +struct ia_css_anr_thres { + int16_t data[13*64]; +}; + +#endif /* __IA_CSS_ANR2_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr_param.h new file mode 100644 index 0000000000000000000000000000000000000000..4a289853367ab1acc0c5e0466035fac61aa0c697 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/anr/anr_2/ia_css_anr_param.h @@ -0,0 +1,27 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ANR2_PARAM_H +#define __IA_CSS_ANR2_PARAM_H + +#include "vmem.h" +#include "ia_css_anr2_types.h" + +/** Advanced Noise Reduction (ANR) thresholds */ + +struct ia_css_isp_anr2_params { + VMEM_ARRAY(data, ANR_PARAM_SIZE*ISP_VEC_NELEMS); +}; + +#endif /* __IA_CSS_ANR2_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bayer_ls/bayer_ls_1.0/ia_css_bayer_load_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bayer_ls/bayer_ls_1.0/ia_css_bayer_load_param.h new file mode 100644 index 0000000000000000000000000000000000000000..8e1f300bcd39f51d3b6ea3cf93f1057295c75ed0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bayer_ls/bayer_ls_1.0/ia_css_bayer_load_param.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BAYER_LOAD_PARAM_H +#define __IA_CSS_BAYER_LOAD_PARAM_H + +#include "ia_css_bayer_ls_param.h" + +#endif /* __IA_CSS_BAYER_LOAD_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bayer_ls/bayer_ls_1.0/ia_css_bayer_ls_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bayer_ls/bayer_ls_1.0/ia_css_bayer_ls_param.h new file mode 100644 index 0000000000000000000000000000000000000000..75ca7606b95cfdd81e1b01e826fea1d0b1b206df --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bayer_ls/bayer_ls_1.0/ia_css_bayer_ls_param.h @@ -0,0 +1,42 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BAYER_LS_PARAM_H +#define __IA_CSS_BAYER_LS_PARAM_H + +#include "type_support.h" +#ifndef ISP2401 + +#define NUM_BAYER_LS 2 +#define BAYER_IDX_GR 0 +#define BAYER_IDX_R 1 +#define BAYER_IDX_B 2 +#define BAYER_IDX_GB 3 +#define BAYER_QUAD_WIDTH 2 +#define BAYER_QUAD_HEIGHT 2 +#define NOF_BAYER_VECTORS 4 + +/** bayer load/store */ +struct sh_css_isp_bayer_ls_isp_config { + uint32_t base_address[NUM_BAYER_LS]; + uint32_t width[NUM_BAYER_LS]; + uint32_t height[NUM_BAYER_LS]; + uint32_t stride[NUM_BAYER_LS]; +}; + +#else +#include "../../io_ls/common/ia_css_common_io_types.h" +#endif + +#endif /* __IA_CSS_BAYER_LS_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bayer_ls/bayer_ls_1.0/ia_css_bayer_store_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bayer_ls/bayer_ls_1.0/ia_css_bayer_store_param.h new file mode 100644 index 0000000000000000000000000000000000000000..f330be80efa66160e46c34eafeee3b0850f41bec --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bayer_ls/bayer_ls_1.0/ia_css_bayer_store_param.h @@ -0,0 +1,21 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BAYER_STORE_PARAM_H +#define __IA_CSS_BAYER_STORE_PARAM_H + +#include "ia_css_bayer_ls_param.h" + + +#endif /* __IA_CSS_BAYER_STORE_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bh/bh_2/ia_css_bh.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bh/bh_2/ia_css_bh.host.c new file mode 100644 index 0000000000000000000000000000000000000000..69e708f594521d6aae7c52b14a94554fe42ecb0d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bh/bh_2/ia_css_bh.host.c @@ -0,0 +1,78 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#if !defined(HAS_NO_HMEM) + +#include "ia_css_memory_access.h" +#include "memory_access.h" +#include "ia_css_types.h" +#include "sh_css_internal.h" +#include "assert_support.h" +#include "sh_css_frac.h" + +#include "ia_css_bh.host.h" + +void +ia_css_bh_hmem_decode( + struct ia_css_3a_rgby_output *out_ptr, + const struct ia_css_bh_table *hmem_buf) +{ + int i; + + /* + * No weighted histogram, hence no grid definition + */ + if(!hmem_buf) + return; + assert(sizeof_hmem(HMEM0_ID) == sizeof(*hmem_buf)); + + /* Deinterleave */ + for (i = 0; i < HMEM_UNIT_SIZE; i++) { + out_ptr[i].r = hmem_buf->hmem[BH_COLOR_R][i]; + out_ptr[i].g = hmem_buf->hmem[BH_COLOR_G][i]; + out_ptr[i].b = hmem_buf->hmem[BH_COLOR_B][i]; + out_ptr[i].y = hmem_buf->hmem[BH_COLOR_Y][i]; + /* sh_css_print ("hmem[%d] = %d, %d, %d, %d\n", + i, out_ptr[i].r, out_ptr[i].g, out_ptr[i].b, out_ptr[i].y); */ + } +} + +void +ia_css_bh_encode( + struct sh_css_isp_bh_params *to, + const struct ia_css_3a_config *from, + unsigned size) +{ + (void)size; + /* coefficients to calculate Y */ + to->y_coef_r = + uDIGIT_FITTING(from->ae_y_coef_r, 16, SH_CSS_AE_YCOEF_SHIFT); + to->y_coef_g = + uDIGIT_FITTING(from->ae_y_coef_g, 16, SH_CSS_AE_YCOEF_SHIFT); + to->y_coef_b = + uDIGIT_FITTING(from->ae_y_coef_b, 16, SH_CSS_AE_YCOEF_SHIFT); +} + +void +ia_css_bh_hmem_encode( + struct sh_css_isp_bh_hmem_params *to, + const struct ia_css_3a_config *from, + unsigned size) +{ + (void)size; + (void)from; + (void)to; +} + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bh/bh_2/ia_css_bh.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bh/bh_2/ia_css_bh.host.h new file mode 100644 index 0000000000000000000000000000000000000000..339e954a90690afcc8a0cf972a7f0adc1aafbedb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bh/bh_2/ia_css_bh.host.h @@ -0,0 +1,38 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BH_HOST_H +#define __IA_CSS_BH_HOST_H + +#include "ia_css_bh_param.h" +#include "s3a/s3a_1.0/ia_css_s3a_types.h" + +void +ia_css_bh_hmem_decode( + struct ia_css_3a_rgby_output *out_ptr, + const struct ia_css_bh_table *hmem_buf); + +void +ia_css_bh_encode( + struct sh_css_isp_bh_params *to, + const struct ia_css_3a_config *from, + unsigned size); + +void +ia_css_bh_hmem_encode( + struct sh_css_isp_bh_hmem_params *to, + const struct ia_css_3a_config *from, + unsigned size); + +#endif /* __IA_CSS_BH_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bh/bh_2/ia_css_bh_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bh/bh_2/ia_css_bh_param.h new file mode 100644 index 0000000000000000000000000000000000000000..b0a8ef3862e0910167cfb3193fb6296ecbd0caf7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bh/bh_2/ia_css_bh_param.h @@ -0,0 +1,40 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_HB_PARAM_H +#define __IA_CSS_HB_PARAM_H + +#include "type_support.h" + +#ifndef PIPE_GENERATION +#define __INLINE_HMEM__ +#include "hmem.h" +#endif + +#include "ia_css_bh_types.h" + +/* AE (3A Support) */ +struct sh_css_isp_bh_params { + /* coefficients to calculate Y */ + int32_t y_coef_r; + int32_t y_coef_g; + int32_t y_coef_b; +}; + +/* This should be hmem_data_t, but that breaks the pipe generator */ +struct sh_css_isp_bh_hmem_params { + uint32_t bh[ISP_HIST_COMPONENTS][IA_CSS_HMEM_BH_UNIT_SIZE]; +}; + +#endif /* __IA_CSS_HB_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bh/bh_2/ia_css_bh_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bh/bh_2/ia_css_bh_types.h new file mode 100644 index 0000000000000000000000000000000000000000..9ae27a9e0baa546f81a4e88c96622da665355756 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bh/bh_2/ia_css_bh_types.h @@ -0,0 +1,37 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BH_TYPES_H +#define __IA_CSS_BH_TYPES_H + +/** Number of elements in the BH table. + * Should be consistent with hmem.h + */ +#define IA_CSS_HMEM_BH_TABLE_SIZE ISP_HIST_DEPTH +#define IA_CSS_HMEM_BH_UNIT_SIZE (ISP_HIST_DEPTH/ISP_HIST_COMPONENTS) + +#define BH_COLOR_R (0) +#define BH_COLOR_G (1) +#define BH_COLOR_B (2) +#define BH_COLOR_Y (3) +#define BH_COLOR_NUM (4) + +/** BH table */ +struct ia_css_bh_table { + uint32_t hmem[ISP_HIST_COMPONENTS][IA_CSS_HMEM_BH_UNIT_SIZE]; +}; + +#endif /* __IA_CSS_BH_TYPES_H */ + + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm.host.c new file mode 100644 index 0000000000000000000000000000000000000000..3af107d46e37f2c53bb29010f535c13ddd7d2df3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm.host.c @@ -0,0 +1,183 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "type_support.h" +#include "ia_css_bnlm.host.h" + +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" /* ia_css_debug_dtrace() */ +#endif +#include + +#define BNLM_DIV_LUT_SIZE (12) +static const int32_t div_lut_nearests[BNLM_DIV_LUT_SIZE] = { + 0, 454, 948, 1484, 2070, 2710, 3412, 4184, 5035, 5978, 7025, 8191 +}; + +static const int32_t div_lut_slopes[BNLM_DIV_LUT_SIZE] = { + -7760, -6960, -6216, -5536, -4912, -4344, -3832, -3360, -2936, -2552, -2208, -2208 +}; + +static const int32_t div_lut_intercepts[BNLM_DIV_LUT_SIZE] = { + 8184, 7752, 7336, 6928, 6536, 6152, 5776, 5416, 5064, 4728, 4408, 4408 +}; + +/* Encodes a look-up table from BNLM public parameters to vmem parameters. + * Input: + * lut : bnlm_lut struct containing encoded vmem parameters look-up table + * lut_thr : array containing threshold values for lut + * lut_val : array containing output values related to lut_thr + * lut_size: Size of lut_val array + * */ +static inline void +bnlm_lut_encode(struct bnlm_lut *lut, const int32_t *lut_thr, const int32_t *lut_val, const uint32_t lut_size) +{ + uint32_t blk, i; + const uint32_t block_size = 16; + const uint32_t total_blocks = (ISP_VEC_NELEMS / block_size); + + /* Create VMEM LUTs from the threshold and value arrays. + * + * Min size of the LUT is 2 entries. + * + * Max size of the LUT is 16 entries, so that the LUT can fit into a + * single group of 16 elements inside a vector. + * Then these elements are copied into other groups inside the same + * vector. If the LUT size is less than 16, then remaining elements are + * set to 0. + * */ + assert((lut_size >= 2) && (lut_size <= block_size)); + /* array lut_thr has (lut_size-1) entries */ + for (i = 0; i < lut_size-2; i++) { + /* Check if the lut_thr is monotonically increasing */ + assert(lut_thr[i] <= lut_thr[i+1]); + } + + /* Intialize */ + for (i = 0; i < total_blocks * block_size; i++) { + lut->thr[0][i] = 0; + lut->val[0][i] = 0; + } + + /* Copy all data */ + for (i = 0; i < lut_size - 1; i++) { + lut->thr[0][i] = lut_thr[i]; + lut->val[0][i] = lut_val[i]; + } + lut->val[0][i] = lut_val[i]; /* val has one more element than thr */ + + /* Copy data from first block to all blocks */ + for (blk = 1; blk < total_blocks; blk++) { + uint32_t blk_offset = blk * block_size; + for (i = 1; i < lut_size; i++) { + lut->thr[0][blk_offset + i] = lut->thr[0][i]; + lut->val[0][blk_offset + i] = lut->val[0][i]; + } + } +} + +/* + * - Encodes BNLM public parameters into VMEM parameters + * - Generates VMEM parameters which will needed internally ISP + * */ +void +ia_css_bnlm_vmem_encode( + struct bnlm_vmem_params *to, + const struct ia_css_bnlm_config *from, + size_t size) +{ + int i; + (void)size; + + /* Initialize LUTs in VMEM parameters */ + bnlm_lut_encode(&to->mu_root_lut, from->mu_root_lut_thr, from->mu_root_lut_val, 16); + bnlm_lut_encode(&to->sad_norm_lut, from->sad_norm_lut_thr, from->sad_norm_lut_val, 16); + bnlm_lut_encode(&to->sig_detail_lut, from->sig_detail_lut_thr, from->sig_detail_lut_val, 16); + bnlm_lut_encode(&to->sig_rad_lut, from->sig_rad_lut_thr, from->sig_rad_lut_val, 16); + bnlm_lut_encode(&to->rad_pow_lut, from->rad_pow_lut_thr, from->rad_pow_lut_val, 16); + bnlm_lut_encode(&to->nl_0_lut, from->nl_0_lut_thr, from->nl_0_lut_val, 16); + bnlm_lut_encode(&to->nl_1_lut, from->nl_1_lut_thr, from->nl_1_lut_val, 16); + bnlm_lut_encode(&to->nl_2_lut, from->nl_2_lut_thr, from->nl_2_lut_val, 16); + bnlm_lut_encode(&to->nl_3_lut, from->nl_3_lut_thr, from->nl_3_lut_val, 16); + + /* Initialize arrays in VMEM parameters */ + memset(to->nl_th, 0, sizeof(to->nl_th)); + to->nl_th[0][0] = from->nl_th[0]; + to->nl_th[0][1] = from->nl_th[1]; + to->nl_th[0][2] = from->nl_th[2]; + + memset(to->match_quality_max_idx, 0, sizeof(to->match_quality_max_idx)); + to->match_quality_max_idx[0][0] = from->match_quality_max_idx[0]; + to->match_quality_max_idx[0][1] = from->match_quality_max_idx[1]; + to->match_quality_max_idx[0][2] = from->match_quality_max_idx[2]; + to->match_quality_max_idx[0][3] = from->match_quality_max_idx[3]; + + bnlm_lut_encode(&to->div_lut, div_lut_nearests, div_lut_slopes, BNLM_DIV_LUT_SIZE); + memset(to->div_lut_intercepts, 0, sizeof(to->div_lut_intercepts)); + for(i = 0; i < BNLM_DIV_LUT_SIZE; i++) { + to->div_lut_intercepts[0][i] = div_lut_intercepts[i]; + } + + memset(to->power_of_2, 0, sizeof(to->power_of_2)); + for (i = 0; i < (ISP_VEC_ELEMBITS-1); i++) { + to->power_of_2[0][i] = 1 << i; + } +} + +/* - Encodes BNLM public parameters into DMEM parameters */ +void +ia_css_bnlm_encode( + struct bnlm_dmem_params *to, + const struct ia_css_bnlm_config *from, + size_t size) +{ + (void)size; + to->rad_enable = from->rad_enable; + to->rad_x_origin = from->rad_x_origin; + to->rad_y_origin = from->rad_y_origin; + to->avg_min_th = from->avg_min_th; + to->max_min_th = from->max_min_th; + + to->exp_coeff_a = from->exp_coeff_a; + to->exp_coeff_b = from->exp_coeff_b; + to->exp_coeff_c = from->exp_coeff_c; + to->exp_exponent = from->exp_exponent; +} + +/* Prints debug traces for BNLM public parameters */ +void +ia_css_bnlm_debug_trace( + const struct ia_css_bnlm_config *config, + unsigned level) +{ + if (!config) + return; + +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(level, "BNLM:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "rad_enable", config->rad_enable); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "rad_x_origin", config->rad_x_origin); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "rad_y_origin", config->rad_y_origin); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "avg_min_th", config->avg_min_th); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "max_min_th", config->max_min_th); + + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "exp_coeff_a", config->exp_coeff_a); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "exp_coeff_b", config->exp_coeff_b); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "exp_coeff_c", config->exp_coeff_c); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "exp_exponent", config->exp_exponent); + + /* ToDo: print traces for LUTs */ +#endif /* IA_CSS_NO_DEBUG */ + +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm.host.h new file mode 100644 index 0000000000000000000000000000000000000000..b99c0644ab38bb305527654f23c1721a455bc77e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm.host.h @@ -0,0 +1,41 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BNLM_HOST_H +#define __IA_CSS_BNLM_HOST_H + +#include "ia_css_bnlm_types.h" +#include "ia_css_bnlm_param.h" +#include "ia_css_bnlm_default.host.h" + +void +ia_css_bnlm_vmem_encode( + struct bnlm_vmem_params *to, + const struct ia_css_bnlm_config *from, + size_t size); + +void +ia_css_bnlm_encode( + struct bnlm_dmem_params *to, + const struct ia_css_bnlm_config *from, + size_t size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_bnlm_debug_trace( + const struct ia_css_bnlm_config *config, + unsigned level); +#endif + +#endif /* __IA_CSS_BNLM_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm_default.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm_default.host.c new file mode 100644 index 0000000000000000000000000000000000000000..e2eb88c0f1236fc0108d7692bf49a4ccb2467da6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm_default.host.c @@ -0,0 +1,71 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_bnlm_types.h" + +const struct ia_css_bnlm_config default_bnlm_config = { + + .rad_enable = true, + .rad_x_origin = 0, + .rad_y_origin = 0, + .avg_min_th = 127, + .max_min_th = 2047, + + .exp_coeff_a = 6048, + .exp_coeff_b = 7828, + .exp_coeff_c = 0, + .exp_exponent = 3, + + .nl_th = {2252, 2251, 2250}, + .match_quality_max_idx = {2, 3, 3, 1}, + + .mu_root_lut_thr = { + 26, 56, 128, 216, 462, 626, 932, 1108, 1480, 1564, 1824, 1896, 2368, 3428, 4560}, + .mu_root_lut_val = { + 384, 320, 320, 264, 248, 240, 224, 192, 192, 160, 160, 160, 136, 130, 96, 80}, + .sad_norm_lut_thr = { + 236, 328, 470, 774, 964, 1486, 2294, 3244, 4844, 6524, 6524, 6524, 6524, 6524, 6524}, + .sad_norm_lut_val = { + 8064, 7680, 7168, 6144, 5120, 3840, 2560, 2304, 1984, 1792, 1792, 1792, 1792, 1792, 1792, 1792}, + .sig_detail_lut_thr = { + 2936, 3354, 3943, 4896, 5230, 5682, 5996, 7299, 7299, 7299, 7299, 7299, 7299, 7299, 7299}, + .sig_detail_lut_val = { + 8191, 7680, 7168, 6144, 5120, 4608, 4224, 4032, 4032, 4032, 4032, 4032, 4032, 4032, 4032, 4032}, + .sig_rad_lut_thr = { + 18, 19, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}, + .sig_rad_lut_val = { + 2560, 7168, 8188, 8188, 8188, 8188, 8188, 8188, 8188, 8188, 8188, 8188, 8188, 8188, 8188, 8188}, + .rad_pow_lut_thr = { + 0, 7013, 7013, 7013, 7013, 7013, 7013, 7013, 7013, 7013, 7013, 7013, 7013, 7013, 7013}, + .rad_pow_lut_val = { + 8191, 8191, 8191, 8191, 8191, 8191, 8191, 8191, 8191, 8191, 8191, 8191, 8191, 8191, 8191, 8191}, + .nl_0_lut_thr = { + 1072, 7000, 8000, 8000, 8000, 8000, 8000, 8000, 8000, 8000, 8000, 8000, 8000, 8000, 8000}, + .nl_0_lut_val = { + 2560, 3072, 5120, 5120, 5120, 5120, 5120, 5120, 5120, 5120, 5120, 5120, 5120, 5120, 5120, 5120}, + .nl_1_lut_thr = { + 624, 3224, 3392, 7424, 7424, 7424, 7424, 7424, 7424, 7424, 7424, 7424, 7424, 7424, 7424}, + .nl_1_lut_val = { + 3584, 4608, 5120, 6144, 6144, 6144, 6144, 6144, 6144, 6144, 6144, 6144, 6144, 6144, 6144, 6144}, + .nl_2_lut_thr = { + 745, 2896, 3720, 6535, 7696, 8040, 8040, 8040, 8040, 8040, 8040, 8040, 8040, 8040, 8040}, + .nl_2_lut_val = { + 3584, 4608, 6144, 7168, 7936, 8191, 8191, 8191, 8191, 8191, 8191, 8191, 8191, 8191, 8191, 8191}, + .nl_3_lut_thr = { + 4848, 4984, 5872, 6000, 6517, 6960, 7944, 8088, 8161, 8161, 8161, 8161, 8161, 8161, 8161}, + .nl_3_lut_val = { + 3072, 4104, 4608, 5120, 6144, 7168, 7680, 8128, 8191, 8191, 8191, 8191, 8191, 8191, 8191, 8191}, + +}; + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm_default.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm_default.host.h new file mode 100644 index 0000000000000000000000000000000000000000..f18c8070abba85395ca08284578f4cf9fab36729 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm_default.host.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BNLM_DEFAULT_HOST_H +#define __IA_CSS_BNLM_DEFAULT_HOST_H + +#include "ia_css_bnlm_types.h" +extern const struct ia_css_bnlm_config default_bnlm_config; + +#endif /* __IA_CSS_BNLM_DEFAULT_HOST_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm_param.h new file mode 100644 index 0000000000000000000000000000000000000000..2f4be43e594ed751a355b78c457adfa9b77b18af --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm_param.h @@ -0,0 +1,63 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BNLM_PARAM_H +#define __IA_CSS_BNLM_PARAM_H + +#include "type_support.h" +#include "vmem.h" /* needed for VMEM_ARRAY */ + +struct bnlm_lut { + VMEM_ARRAY(thr, ISP_VEC_NELEMS); /* thresholds */ + VMEM_ARRAY(val, ISP_VEC_NELEMS); /* values */ +}; + +struct bnlm_vmem_params { + VMEM_ARRAY(nl_th, ISP_VEC_NELEMS); + VMEM_ARRAY(match_quality_max_idx, ISP_VEC_NELEMS); + struct bnlm_lut mu_root_lut; + struct bnlm_lut sad_norm_lut; + struct bnlm_lut sig_detail_lut; + struct bnlm_lut sig_rad_lut; + struct bnlm_lut rad_pow_lut; + struct bnlm_lut nl_0_lut; + struct bnlm_lut nl_1_lut; + struct bnlm_lut nl_2_lut; + struct bnlm_lut nl_3_lut; + + /* LUTs used for division approximiation */ + struct bnlm_lut div_lut; + VMEM_ARRAY(div_lut_intercepts, ISP_VEC_NELEMS); + + /* 240x does not have an ISP instruction to left shift each element of a + * vector by different shift value. Hence it will be simulated by multiplying + * the elements by required 2^shift. */ + VMEM_ARRAY(power_of_2, ISP_VEC_NELEMS); +}; + +/* BNLM ISP parameters */ +struct bnlm_dmem_params { + bool rad_enable; + int32_t rad_x_origin; + int32_t rad_y_origin; + int32_t avg_min_th; + int32_t max_min_th; + + int32_t exp_coeff_a; + uint32_t exp_coeff_b; + int32_t exp_coeff_c; + uint32_t exp_exponent; +}; + +#endif /* __IA_CSS_BNLM_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm_state.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm_state.h new file mode 100644 index 0000000000000000000000000000000000000000..79cce0e40e825e16ca01ced557256336665ecd2f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm_state.h @@ -0,0 +1,31 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BNLM_STATE_H +#define __IA_CSS_BNLM_STATE_H + + +#include "type_support.h" +#include "vmem.h" /* for VMEM_ARRAY*/ +#include "bnlm.isp.h" + +struct bnlm_vmem_state { + /* State buffers required for BNLM */ + VMEM_ARRAY(buf[BNLM_STATE_BUF_HEIGHT], BNLM_STATE_BUF_WIDTH*ISP_NWAY); +}; + + + +#endif /* __IA_CSS_BNLM_STATE_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm_types.h new file mode 100644 index 0000000000000000000000000000000000000000..219fb835cb26bd12020ce7ad5a344fb9ab1d8cdc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnlm/ia_css_bnlm_types.h @@ -0,0 +1,106 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BNLM_TYPES_H +#define __IA_CSS_BNLM_TYPES_H + +/** @file +* CSS-API header file for Bayer Non-Linear Mean parameters. +*/ + +#include "type_support.h" /* int32_t */ + +/** Bayer Non-Linear Mean configuration + * + * \brief BNLM public parameters. + * \details Struct with all parameters for the BNLM kernel that can be set + * from the CSS API. + * + * ISP2.6.1: BNLM is used. + */ +struct ia_css_bnlm_config { + bool rad_enable; /**< Enable a radial dependency in a weight calculation */ + int32_t rad_x_origin; /**< Initial x coordinate for a radius calculation */ + int32_t rad_y_origin; /**< Initial x coordinate for a radius calculation */ + /* a threshold for average of weights if this < Th, do not denoise pixel */ + int32_t avg_min_th; + /* minimum weight for denoising if max < th, do not denoise pixel */ + int32_t max_min_th; + + /**@{*/ + /** Coefficient for approximation, in the form of (1 + x / N)^N, + * that fits the first-order exp() to default exp_lut in BNLM sheet + * */ + int32_t exp_coeff_a; + uint32_t exp_coeff_b; + int32_t exp_coeff_c; + uint32_t exp_exponent; + /**@}*/ + + int32_t nl_th[3]; /**< Detail thresholds */ + + /** Index for n-th maximum candidate weight for each detail group */ + int32_t match_quality_max_idx[4]; + + /**@{*/ + /** A lookup table for 1/sqrt(1+mu) approximation */ + int32_t mu_root_lut_thr[15]; + int32_t mu_root_lut_val[16]; + /**@}*/ + /**@{*/ + /** A lookup table for SAD normalization */ + int32_t sad_norm_lut_thr[15]; + int32_t sad_norm_lut_val[16]; + /**@}*/ + /**@{*/ + /** A lookup table that models a weight's dependency on textures */ + int32_t sig_detail_lut_thr[15]; + int32_t sig_detail_lut_val[16]; + /**@}*/ + /**@{*/ + /** A lookup table that models a weight's dependency on a pixel's radial distance */ + int32_t sig_rad_lut_thr[15]; + int32_t sig_rad_lut_val[16]; + /**@}*/ + /**@{*/ + /** A lookup table to control denoise power depending on a pixel's radial distance */ + int32_t rad_pow_lut_thr[15]; + int32_t rad_pow_lut_val[16]; + /**@}*/ + /**@{*/ + /** Non linear transfer functions to calculate the blending coefficient depending on detail group */ + /** detail group 0 */ + /**@{*/ + int32_t nl_0_lut_thr[15]; + int32_t nl_0_lut_val[16]; + /**@}*/ + /**@{*/ + /** detail group 1 */ + int32_t nl_1_lut_thr[15]; + int32_t nl_1_lut_val[16]; + /**@}*/ + /**@{*/ + /** detail group 2 */ + int32_t nl_2_lut_thr[15]; + int32_t nl_2_lut_val[16]; + /**@}*/ + /**@{*/ + /** detail group 3 */ + int32_t nl_3_lut_thr[15]; + int32_t nl_3_lut_val[16]; + /**@}*/ + /**@}*/ +}; + +#endif /* __IA_CSS_BNLM_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.c new file mode 100644 index 0000000000000000000000000000000000000000..a7de6ecb950d101eb89813d218206eed4b8a30a9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.c @@ -0,0 +1,122 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "type_support.h" +#include "ia_css_bnr2_2.host.h" + +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" /* ia_css_debug_dtrace() */ +#endif + +/* Default kernel parameters. */ +const struct ia_css_bnr2_2_config default_bnr2_2_config = { + 200, + 200, + 200, + 0, + 0, + 0, + 200, + 200, + 200, + 0, + 0, + 0, + 0, + 4096, + 8191, + 128, + 1, + 0, + 0, + 0, + 8191, + 0, + 8191 +}; + +void +ia_css_bnr2_2_encode( + struct sh_css_isp_bnr2_2_params *to, + const struct ia_css_bnr2_2_config *from, + size_t size) +{ + (void)size; + to->d_var_gain_r = from->d_var_gain_r; + to->d_var_gain_g = from->d_var_gain_g; + to->d_var_gain_b = from->d_var_gain_b; + to->d_var_gain_slope_r = from->d_var_gain_slope_r; + to->d_var_gain_slope_g = from->d_var_gain_slope_g; + to->d_var_gain_slope_b = from->d_var_gain_slope_b; + + to->n_var_gain_r = from->n_var_gain_r; + to->n_var_gain_g = from->n_var_gain_g; + to->n_var_gain_b = from->n_var_gain_b; + to->n_var_gain_slope_r = from->n_var_gain_slope_r; + to->n_var_gain_slope_g = from->n_var_gain_slope_g; + to->n_var_gain_slope_b = from->n_var_gain_slope_b; + + to->dir_thres = from->dir_thres; + to->dir_thres_w = from->dir_thres_w; + to->var_offset_coef = from->var_offset_coef; + + to->dir_gain = from->dir_gain; + to->detail_gain = from->detail_gain; + to->detail_gain_divisor = from->detail_gain_divisor; + to->detail_level_offset = from->detail_level_offset; + + to->d_var_th_min = from->d_var_th_min; + to->d_var_th_max = from->d_var_th_max; + to->n_var_th_min = from->n_var_th_min; + to->n_var_th_max = from->n_var_th_max; +} + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_bnr2_2_debug_dtrace( + const struct ia_css_bnr2_2_config *bnr, + unsigned level) +{ + if (!bnr) + return; + + ia_css_debug_dtrace(level, "Bayer Noise Reduction 2.2:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "d_var_gain_r", bnr->d_var_gain_r); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "d_var_gain_g", bnr->d_var_gain_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "d_var_gain_b", bnr->d_var_gain_b); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "d_var_gain_slope_r", bnr->d_var_gain_slope_r); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "d_var_gain_slope_g", bnr->d_var_gain_slope_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "d_var_gain_slope_b", bnr->d_var_gain_slope_b); + + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "n_var_gain_r", bnr->n_var_gain_r); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "n_var_gain_g", bnr->n_var_gain_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "n_var_gain_b", bnr->n_var_gain_b); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "n_var_gain_slope_r", bnr->n_var_gain_slope_r); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "n_var_gain_slope_g", bnr->n_var_gain_slope_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "n_var_gain_slope_b", bnr->n_var_gain_slope_b); + + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "dir_thres", bnr->dir_thres); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "dir_thres_w", bnr->dir_thres_w); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "var_offset_coef", bnr->var_offset_coef); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "dir_gain", bnr->dir_gain); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "detail_gain", bnr->detail_gain); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "detail_gain_divisor", bnr->detail_gain_divisor); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "detail_level_offset", bnr->detail_level_offset); + + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "d_var_th_min", bnr->d_var_th_min); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "d_var_th_max", bnr->d_var_th_max); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "n_var_th_min", bnr->n_var_th_min); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "n_var_th_max", bnr->n_var_th_max); +} +#endif /* IA_CSS_NO_DEBUG */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.h new file mode 100644 index 0000000000000000000000000000000000000000..c94b366b814200eb732d61a642cbd81645583964 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.h @@ -0,0 +1,35 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#ifndef __IA_CSS_BNR2_2_HOST_H +#define __IA_CSS_BNR2_2_HOST_H + +#include "ia_css_bnr2_2_types.h" +#include "ia_css_bnr2_2_param.h" + +extern const struct ia_css_bnr2_2_config default_bnr2_2_config; + +void +ia_css_bnr2_2_encode( + struct sh_css_isp_bnr2_2_params *to, + const struct ia_css_bnr2_2_config *from, + size_t size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_bnr2_2_debug_dtrace( + const struct ia_css_bnr2_2_config *config, + unsigned level); +#endif + +#endif /* __IA_CSS_BNR2_2_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2_param.h new file mode 100644 index 0000000000000000000000000000000000000000..6dec27a99d8fbb32a4f31268d8da3facca7f69ef --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2_param.h @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BNR2_2_PARAM_H +#define __IA_CSS_BNR2_2_PARAM_H + +#include "type_support.h" + +/* BNR (Bayer Noise Reduction) ISP parameters */ +struct sh_css_isp_bnr2_2_params { + int32_t d_var_gain_r; + int32_t d_var_gain_g; + int32_t d_var_gain_b; + int32_t d_var_gain_slope_r; + int32_t d_var_gain_slope_g; + int32_t d_var_gain_slope_b; + int32_t n_var_gain_r; + int32_t n_var_gain_g; + int32_t n_var_gain_b; + int32_t n_var_gain_slope_r; + int32_t n_var_gain_slope_g; + int32_t n_var_gain_slope_b; + int32_t dir_thres; + int32_t dir_thres_w; + int32_t var_offset_coef; + int32_t dir_gain; + int32_t detail_gain; + int32_t detail_gain_divisor; + int32_t detail_level_offset; + int32_t d_var_th_min; + int32_t d_var_th_max; + int32_t n_var_th_min; + int32_t n_var_th_max; +}; + +#endif /* __IA_CSS_BNR2_2_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2_types.h new file mode 100644 index 0000000000000000000000000000000000000000..be80f705d8a173525c96e9f0be1da56256b7bde2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2_types.h @@ -0,0 +1,71 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BNR2_2_TYPES_H +#define __IA_CSS_BNR2_2_TYPES_H + +/** @file +* CSS-API header file for Bayer Noise Reduction parameters. +*/ + +#include "type_support.h" /* int32_t */ + +/** Bayer Noise Reduction 2.2 configuration + * + * \brief BNR2_2 public parameters. + * \details Struct with all parameters for the BNR2.2 kernel that can be set + * from the CSS API. + * + * ISP2.6.1: BNR2.2 is used. + */ +struct ia_css_bnr2_2_config { + /**@{*/ + /** Directional variance gain for R/G/B components in dark region */ + int32_t d_var_gain_r; + int32_t d_var_gain_g; + int32_t d_var_gain_b; + /**@}*/ + /**@{*/ + /** Slope of Directional variance gain between dark and bright region */ + int32_t d_var_gain_slope_r; + int32_t d_var_gain_slope_g; + int32_t d_var_gain_slope_b; + /**@}*/ + /**@{*/ + /** Non-Directional variance gain for R/G/B components in dark region */ + int32_t n_var_gain_r; + int32_t n_var_gain_g; + int32_t n_var_gain_b; + /**@}*/ + /**@{*/ + /** Slope of Non-Directional variance gain between dark and bright region */ + int32_t n_var_gain_slope_r; + int32_t n_var_gain_slope_g; + int32_t n_var_gain_slope_b; + /**@}*/ + + int32_t dir_thres; /**< Threshold for directional filtering */ + int32_t dir_thres_w; /**< Threshold width for directional filtering */ + int32_t var_offset_coef; /**< Variance offset coefficient */ + int32_t dir_gain; /**< Gain for directional coefficient */ + int32_t detail_gain; /**< Gain for low contrast texture control */ + int32_t detail_gain_divisor; /**< Gain divisor for low contrast texture control */ + int32_t detail_level_offset; /**< Bias value for low contrast texture control */ + int32_t d_var_th_min; /**< Minimum clipping value for directional variance*/ + int32_t d_var_th_max; /**< Maximum clipping value for diretional variance*/ + int32_t n_var_th_min; /**< Minimum clipping value for non-directional variance*/ + int32_t n_var_th_max; /**< Maximum clipping value for non-directional variance*/ +}; + +#endif /* __IA_CSS_BNR2_2_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.c new file mode 100644 index 0000000000000000000000000000000000000000..d1baca54c3ad4f587fa56c4e0faabc81c9519a27 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.c @@ -0,0 +1,64 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "sh_css_frac.h" + +#include "ia_css_bnr.host.h" + +void +ia_css_bnr_encode( + struct sh_css_isp_bnr_params *to, + const struct ia_css_nr_config *from, + unsigned size) +{ + (void)size; + /* BNR (Bayer Noise Reduction) */ + to->threshold_low = + uDIGIT_FITTING(from->direction, 16, SH_CSS_BAYER_BITS); + to->threshold_width_log2 = uFRACTION_BITS_FITTING(8); + to->threshold_width = + 1 << to->threshold_width_log2; + to->gain_all = + uDIGIT_FITTING(from->bnr_gain, 16, SH_CSS_BNR_GAIN_SHIFT); + to->gain_dir = + uDIGIT_FITTING(from->bnr_gain, 16, SH_CSS_BNR_GAIN_SHIFT); + to->clip = uDIGIT_FITTING((unsigned)16384, 16, SH_CSS_BAYER_BITS); +} + +void +ia_css_bnr_dump( + const struct sh_css_isp_bnr_params *bnr, + unsigned level) +{ + if (!bnr) return; + ia_css_debug_dtrace(level, "Bayer Noise Reduction:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "bnr_gain_all", bnr->gain_all); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "bnr_gain_dir", bnr->gain_dir); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "bnr_threshold_low", + bnr->threshold_low); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "bnr_threshold_width_log2", + bnr->threshold_width_log2); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "bnr_threshold_width", + bnr->threshold_width); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "bnr_clip", bnr->clip); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.h new file mode 100644 index 0000000000000000000000000000000000000000..ccd2abc60537655ca7390e636075aac96c62f548 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.h @@ -0,0 +1,34 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BNR_HOST_H +#define __IA_CSS_BNR_HOST_H + +#include "sh_css_params.h" + +#include "ynr/ynr_1.0/ia_css_ynr_types.h" +#include "ia_css_bnr_param.h" + +void +ia_css_bnr_encode( + struct sh_css_isp_bnr_params *to, + const struct ia_css_nr_config *from, + unsigned size); + +void +ia_css_bnr_dump( + const struct sh_css_isp_bnr_params *bnr, + unsigned level); + +#endif /* __IA_CSS_DP_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr_1.0/ia_css_bnr_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr_1.0/ia_css_bnr_param.h new file mode 100644 index 0000000000000000000000000000000000000000..331e05885ef4d02ff56f3ad8b7ee7b25f3988204 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/bnr/bnr_1.0/ia_css_bnr_param.h @@ -0,0 +1,30 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BNR_PARAM_H +#define __IA_CSS_BNR_PARAM_H + +#include "type_support.h" + +/* BNR (Bayer Noise Reduction) */ +struct sh_css_isp_bnr_params { + int32_t gain_all; + int32_t gain_dir; + int32_t threshold_low; + int32_t threshold_width_log2; + int32_t threshold_width; + int32_t clip; +}; + +#endif /* __IA_CSS_BNR_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.c new file mode 100644 index 0000000000000000000000000000000000000000..d14fd8fc08b1e1caaf06f2346282b84551311adf --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.c @@ -0,0 +1,28 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" + +#include "ia_css_cnr.host.h" + +/* keep the interface here, it is not enabled yet because host doesn't know the size of individual state */ +void +ia_css_init_cnr_state( + void/*struct sh_css_isp_cnr_vmem_state*/ *state, + size_t size) +{ + memset(state, 0, size); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.h new file mode 100644 index 0000000000000000000000000000000000000000..6f00d280b7d6e305cb1a9f9e100573f6c6377ac8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.h @@ -0,0 +1,25 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CNR_HOST_H +#define __IA_CSS_CNR_HOST_H + +#include "ia_css_cnr_param.h" + +void +ia_css_init_cnr_state( + void/*struct sh_css_isp_cnr_vmem_state*/ *state, + size_t size); + +#endif /* __IA_CSS_CNR_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_1.0/ia_css_cnr_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_1.0/ia_css_cnr_param.h new file mode 100644 index 0000000000000000000000000000000000000000..c1af207cbf9afb2a21917a6b5abeb97a57308b1b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_1.0/ia_css_cnr_param.h @@ -0,0 +1,24 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CNR_PARAM_H +#define __IA_CSS_CNR_PARAM_H + +#include "type_support.h" + +/* CNR (Chroma Noise Reduction) */ +/* Reuse YNR1 param structure */ +#include "../../ynr/ynr_1.0/ia_css_ynr_param.h" + +#endif /* __IA_CSS_CNR_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_1.0/ia_css_cnr_state.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_1.0/ia_css_cnr_state.h new file mode 100644 index 0000000000000000000000000000000000000000..795fba76bb20b741031744f77702fb0e109e8958 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_1.0/ia_css_cnr_state.h @@ -0,0 +1,33 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CNR_STATE_H +#define __IA_CSS_CNR_STATE_H + +#include "type_support.h" + +#include "vmem.h" + +typedef struct +{ + VMEM_ARRAY(u, ISP_NWAY); + VMEM_ARRAY(v, ISP_NWAY); +} s_cnr_buf; + +/* CNR (color noise reduction) */ +struct sh_css_isp_cnr_vmem_state { + s_cnr_buf cnr_buf[2][MAX_VECTORS_PER_BUF_LINE/2]; +}; + +#endif /* __IA_CSS_CNR_STATE_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr2.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr2.host.c new file mode 100644 index 0000000000000000000000000000000000000000..4b4b2b7154075941f045043dfa00d61bf453b021 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr2.host.c @@ -0,0 +1,76 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" + +#include "ia_css_cnr2.host.h" + +const struct ia_css_cnr_config default_cnr_config = { + 0, + 0, + 100, + 100, + 100, + 50, + 50, + 50 +}; + +void +ia_css_cnr_encode( + struct sh_css_isp_cnr_params *to, + const struct ia_css_cnr_config *from, + unsigned size) +{ + (void)size; + to->coring_u = from->coring_u; + to->coring_v = from->coring_v; + to->sense_gain_vy = from->sense_gain_vy; + to->sense_gain_vu = from->sense_gain_vu; + to->sense_gain_vv = from->sense_gain_vv; + to->sense_gain_hy = from->sense_gain_hy; + to->sense_gain_hu = from->sense_gain_hu; + to->sense_gain_hv = from->sense_gain_hv; +} + +void +ia_css_cnr_dump( + const struct sh_css_isp_cnr_params *cnr, + unsigned level); + +void +ia_css_cnr_debug_dtrace( + const struct ia_css_cnr_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.coring_u=%d, config.coring_v=%d, " + "config.sense_gain_vy=%d, config.sense_gain_hy=%d, " + "config.sense_gain_vu=%d, config.sense_gain_hu=%d, " + "config.sense_gain_vv=%d, config.sense_gain_hv=%d\n", + config->coring_u, config->coring_v, + config->sense_gain_vy, config->sense_gain_hy, + config->sense_gain_vu, config->sense_gain_hu, + config->sense_gain_vv, config->sense_gain_hv); +} + +void +ia_css_init_cnr2_state( + void/*struct sh_css_isp_cnr_vmem_state*/ *state, + size_t size) +{ + memset(state, 0, size); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h new file mode 100644 index 0000000000000000000000000000000000000000..abcf0eba706f4ef1ac1da97c9f8460e1080066cd --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr2.host.h @@ -0,0 +1,43 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CNR2_HOST_H +#define __IA_CSS_CNR2_HOST_H + +#include "ia_css_cnr2_types.h" +#include "ia_css_cnr2_param.h" + +extern const struct ia_css_cnr_config default_cnr_config; + +void +ia_css_cnr_encode( + struct sh_css_isp_cnr_params *to, + const struct ia_css_cnr_config *from, + unsigned size); + +void +ia_css_cnr_dump( + const struct sh_css_isp_cnr_params *cnr, + unsigned level); + +void +ia_css_cnr_debug_dtrace( + const struct ia_css_cnr_config *config, + unsigned level); + +void +ia_css_init_cnr2_state( + void/*struct sh_css_isp_cnr_vmem_state*/ *state, + size_t size); +#endif /* __IA_CSS_CNR2_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr2_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr2_param.h new file mode 100644 index 0000000000000000000000000000000000000000..d6f490e26c94d02f05aef49e6f843b7dd5ae5b17 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr2_param.h @@ -0,0 +1,32 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CNR2_PARAM_H +#define __IA_CSS_CNR2_PARAM_H + +#include "type_support.h" + +/* CNR (Chroma Noise Reduction) */ +struct sh_css_isp_cnr_params { + int32_t coring_u; + int32_t coring_v; + int32_t sense_gain_vy; + int32_t sense_gain_vu; + int32_t sense_gain_vv; + int32_t sense_gain_hy; + int32_t sense_gain_hu; + int32_t sense_gain_hv; +}; + +#endif /* __IA_CSS_CNR2_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr2_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr2_types.h new file mode 100644 index 0000000000000000000000000000000000000000..6df6c2be9a70db6b4fd38704798c21e7f1e09130 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr2_types.h @@ -0,0 +1,55 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CNR2_TYPES_H +#define __IA_CSS_CNR2_TYPES_H + +/** @file +* CSS-API header file for Chroma Noise Reduction (CNR) parameters +*/ + +/** Chroma Noise Reduction configuration. + * + * Small sensitivity of edge means strong smoothness and NR performance. + * If you see blurred color on vertical edges, + * set higher values on sense_gain_h*. + * If you see blurred color on horizontal edges, + * set higher values on sense_gain_v*. + * + * ISP block: CNR2 + * (ISP1: CNR1 is used.) + * (ISP2: CNR1 is used for Preview/Video.) + * ISP2: CNR2 is used for Still. + */ +struct ia_css_cnr_config { + uint16_t coring_u; /**< Coring level of U. + u0.13, [0,8191], default/ineffective 0 */ + uint16_t coring_v; /**< Coring level of V. + u0.13, [0,8191], default/ineffective 0 */ + uint16_t sense_gain_vy; /**< Sensitivity of horizontal edge of Y. + u13.0, [0,8191], default 100, ineffective 8191 */ + uint16_t sense_gain_vu; /**< Sensitivity of horizontal edge of U. + u13.0, [0,8191], default 100, ineffective 8191 */ + uint16_t sense_gain_vv; /**< Sensitivity of horizontal edge of V. + u13.0, [0,8191], default 100, ineffective 8191 */ + uint16_t sense_gain_hy; /**< Sensitivity of vertical edge of Y. + u13.0, [0,8191], default 50, ineffective 8191 */ + uint16_t sense_gain_hu; /**< Sensitivity of vertical edge of U. + u13.0, [0,8191], default 50, ineffective 8191 */ + uint16_t sense_gain_hv; /**< Sensitivity of vertical edge of V. + u13.0, [0,8191], default 50, ineffective 8191 */ +}; + +#endif /* __IA_CSS_CNR2_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr_param.h new file mode 100644 index 0000000000000000000000000000000000000000..56651ba62598eeafff6d7c0c4d5951edd6612116 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr_param.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CNRX_PARAM_H +#define __IA_CSS_CNRX_PARAM_H + +#include "ia_css_cnr2_param.h" + +#endif /* __IA_CSS_CNRX_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr_state.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr_state.h new file mode 100644 index 0000000000000000000000000000000000000000..e533e2fa8cd5faa5ab4d06c710ec86956c69fb7e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/cnr/cnr_2/ia_css_cnr_state.h @@ -0,0 +1,33 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CNR2_STATE_H +#define __IA_CSS_CNR2_STATE_H + +#include "type_support.h" +#include "vmem.h" + +typedef struct +{ + VMEM_ARRAY(y, (MAX_VECTORS_PER_BUF_LINE/2)*ISP_NWAY); + VMEM_ARRAY(u, (MAX_VECTORS_PER_BUF_LINE/2)*ISP_NWAY); + VMEM_ARRAY(v, (MAX_VECTORS_PER_BUF_LINE/2)*ISP_NWAY); +} s_cnr_buf; + +/* CNR (color noise reduction) */ +struct sh_css_isp_cnr_vmem_state { + s_cnr_buf cnr_buf; +}; + +#endif /* __IA_CSS_CNR2_STATE_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.c new file mode 100644 index 0000000000000000000000000000000000000000..8f25ee180cda6434925447372b46d1c15f4027ca --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.c @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "ia_css_conversion.host.h" + +const struct ia_css_conversion_config default_conversion_config = { + 0, + 0, + 0, + 0, +}; + +void +ia_css_conversion_encode( + struct sh_css_isp_conversion_params *to, + const struct ia_css_conversion_config *from, + unsigned size) +{ + (void)size; + to->en = from->en; + to->dummy0 = from->dummy0; + to->dummy1 = from->dummy1; + to->dummy2 = from->dummy2; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.h new file mode 100644 index 0000000000000000000000000000000000000000..da7a0a034a71568e3acdc62e56e1d20def6e6f68 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.h @@ -0,0 +1,33 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CONVERSION_HOST_H +#define __IA_CSS_CONVERSION_HOST_H + +#include "ia_css_conversion_types.h" +#include "ia_css_conversion_param.h" + +extern const struct ia_css_conversion_config default_conversion_config; + +void +ia_css_conversion_encode( + struct sh_css_isp_conversion_params *to, + const struct ia_css_conversion_config *from, + unsigned size); + +#ifdef ISP2401 +/* workaround until code generation in isp_kernelparameters.host.c is fixed */ +#define ia_css_conversion_par_encode(to, from, size) ia_css_conversion_encode(to, from, size) +#endif +#endif /* __IA_CSS_CONVERSION_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/conversion/conversion_1.0/ia_css_conversion_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/conversion/conversion_1.0/ia_css_conversion_param.h new file mode 100644 index 0000000000000000000000000000000000000000..301d506f447e358daf5cc453cd0b9bc0cc344268 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/conversion/conversion_1.0/ia_css_conversion_param.h @@ -0,0 +1,28 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CONVERSION_PARAM_H +#define __IA_CSS_CONVERSION_PARAM_H + +#include "type_support.h" + +/* CONVERSION */ +struct sh_css_isp_conversion_params { + uint32_t en; + uint32_t dummy0; + uint32_t dummy1; + uint32_t dummy2; +}; + +#endif /* __IA_CSS_CONVERSION_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/conversion/conversion_1.0/ia_css_conversion_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/conversion/conversion_1.0/ia_css_conversion_types.h new file mode 100644 index 0000000000000000000000000000000000000000..3f11442500f036cc4fd157bc54b517d4c3746415 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/conversion/conversion_1.0/ia_css_conversion_types.h @@ -0,0 +1,32 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CONVERSION_TYPES_H +#define __IA_CSS_CONVERSION_TYPES_H + +/** + * Conversion Kernel parameters. + * Deinterleave bayer quad into isys format + * + * ISP block: CONVERSION + * + */ +struct ia_css_conversion_config { + uint32_t en; /**< en parameter */ + uint32_t dummy0; /**< dummy0 dummy parameter 0 */ + uint32_t dummy1; /**< dummy1 dummy parameter 1 */ + uint32_t dummy2; /**< dummy2 dummy parameter 2 */ +}; + +#endif /* __IA_CSS_CONVERSION_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.c new file mode 100644 index 0000000000000000000000000000000000000000..45e1ea8b1fb0e7ef60f5bbe23073305191727dbf --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.c @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_copy_output.host.h" +#include "ia_css_binary.h" +#include "type_support.h" +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" +#include "isp.h" + +static const struct ia_css_copy_output_configuration default_config = { + .enable = false, +}; + +void +ia_css_copy_output_config( + struct sh_css_isp_copy_output_isp_config *to, + const struct ia_css_copy_output_configuration *from, + unsigned size) +{ + (void)size; + to->enable = from->enable; +} + +void +ia_css_copy_output_configure( + const struct ia_css_binary *binary, + bool enable) +{ + struct ia_css_copy_output_configuration config = default_config; + + config.enable = enable; + + ia_css_configure_copy_output(binary, &config); +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.h new file mode 100644 index 0000000000000000000000000000000000000000..3eb77365f8d0124bf8ecf50006a519741af8c437 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.h @@ -0,0 +1,34 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_COPY_OUTPUT_HOST_H +#define __IA_CSS_COPY_OUTPUT_HOST_H + +#include "type_support.h" +#include "ia_css_binary.h" + +#include "ia_css_copy_output_param.h" + +void +ia_css_copy_output_config( + struct sh_css_isp_copy_output_isp_config *to, + const struct ia_css_copy_output_configuration *from, + unsigned size); + +void +ia_css_copy_output_configure( + const struct ia_css_binary *binary, + bool enable); + +#endif /* __IA_CSS_COPY_OUTPUT_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output_param.h new file mode 100644 index 0000000000000000000000000000000000000000..622d9181e13fb337890001ce495974aec61b9b22 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output_param.h @@ -0,0 +1,26 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_COPY_PARAM_H +#define __IA_CSS_COPY_PARAM_H + +struct ia_css_copy_output_configuration { + bool enable; +}; + +struct sh_css_isp_copy_output_isp_config { + uint32_t enable; +}; + +#endif /* __IA_CSS_COPY_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/crop/crop_1.0/ia_css_crop.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/crop/crop_1.0/ia_css_crop.host.c new file mode 100644 index 0000000000000000000000000000000000000000..92905220d862e1405c2e62891c018df3bc9fd0c9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/crop/crop_1.0/ia_css_crop.host.c @@ -0,0 +1,64 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" +#include "isp.h" +#include "ia_css_crop.host.h" + +static const struct ia_css_crop_configuration default_config = { + .info = (struct ia_css_frame_info *)NULL, +}; + +void +ia_css_crop_encode( + struct sh_css_isp_crop_isp_params *to, + const struct ia_css_crop_config *from, + unsigned size) +{ + (void)size; + to->crop_pos = from->crop_pos; +} + +void +ia_css_crop_config( + struct sh_css_isp_crop_isp_config *to, + const struct ia_css_crop_configuration *from, + unsigned size) +{ + unsigned elems_a = ISP_VEC_NELEMS; + + (void)size; + ia_css_dma_configure_from_info(&to->port_b, from->info); + to->width_a_over_b = elems_a / to->port_b.elems; + + /* Assume divisiblity here, may need to generalize to fixed point. */ + assert (elems_a % to->port_b.elems == 0); +} + +void +ia_css_crop_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame_info *info) +{ + struct ia_css_crop_configuration config = default_config; + + config.info = info; + + ia_css_configure_crop(binary, &config); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/crop/crop_1.0/ia_css_crop.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/crop/crop_1.0/ia_css_crop.host.h new file mode 100644 index 0000000000000000000000000000000000000000..9c1a4c7cac983406e06bcb4122fe00a86316f4cb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/crop/crop_1.0/ia_css_crop.host.h @@ -0,0 +1,41 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CROP_HOST_H +#define __IA_CSS_CROP_HOST_H + +#include +#include + +#include "ia_css_crop_types.h" +#include "ia_css_crop_param.h" + +void +ia_css_crop_encode( + struct sh_css_isp_crop_isp_params *to, + const struct ia_css_crop_config *from, + unsigned size); + +void +ia_css_crop_config( + struct sh_css_isp_crop_isp_config *to, + const struct ia_css_crop_configuration *from, + unsigned size); + +void +ia_css_crop_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame_info *from); + +#endif /* __IA_CSS_CROP_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/crop/crop_1.0/ia_css_crop_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/crop/crop_1.0/ia_css_crop_param.h new file mode 100644 index 0000000000000000000000000000000000000000..8bfc8dad37a87ef20d577266c0e9a05338a569cd --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/crop/crop_1.0/ia_css_crop_param.h @@ -0,0 +1,32 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CROP_PARAM_H +#define __IA_CSS_CROP_PARAM_H + +#include +#include "dma.h" +#include "sh_css_internal.h" /* sh_css_crop_pos */ + +/** Crop frame */ +struct sh_css_isp_crop_isp_config { + uint32_t width_a_over_b; + struct dma_port_config port_b; +}; + +struct sh_css_isp_crop_isp_params { + struct sh_css_crop_pos crop_pos; +}; + +#endif /* __IA_CSS_CROP_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/crop/crop_1.0/ia_css_crop_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/crop/crop_1.0/ia_css_crop_types.h new file mode 100644 index 0000000000000000000000000000000000000000..8091ad4d46024b02c690895c0b6dcc55eb90a501 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/crop/crop_1.0/ia_css_crop_types.h @@ -0,0 +1,35 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CROP_TYPES_H +#define __IA_CSS_CROP_TYPES_H + +/** Crop frame + * + * ISP block: crop frame + */ + +#include +#include "sh_css_uds.h" /* sh_css_crop_pos */ + +struct ia_css_crop_config { + struct sh_css_crop_pos crop_pos; +}; + +struct ia_css_crop_configuration { + const struct ia_css_frame_info *info; +}; + +#endif /* __IA_CSS_CROP_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/csc/csc_1.0/ia_css_csc.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/csc/csc_1.0/ia_css_csc.host.c new file mode 100644 index 0000000000000000000000000000000000000000..9f94ef1de5725df5b7b74ed919d888a79b76d713 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/csc/csc_1.0/ia_css_csc.host.c @@ -0,0 +1,132 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#ifndef IA_CSS_NO_DEBUG +/* FIXME: See BZ 4427 */ +#include "ia_css_debug.h" +#endif + +#include "ia_css_csc.host.h" + +const struct ia_css_cc_config default_cc_config = { + 8, + {255, 29, 120, 0, -374, -342, 0, -672, 301}, +}; + +void +ia_css_encode_cc( + struct sh_css_isp_csc_params *to, + const struct ia_css_cc_config *from, + unsigned size) +{ + (void)size; +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_encode_cc() enter:\n"); +#endif + + to->m_shift = (int16_t) from->fraction_bits; + to->m00 = (int16_t) from->matrix[0]; + to->m01 = (int16_t) from->matrix[1]; + to->m02 = (int16_t) from->matrix[2]; + to->m10 = (int16_t) from->matrix[3]; + to->m11 = (int16_t) from->matrix[4]; + to->m12 = (int16_t) from->matrix[5]; + to->m20 = (int16_t) from->matrix[6]; + to->m21 = (int16_t) from->matrix[7]; + to->m22 = (int16_t) from->matrix[8]; + +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_encode_cc() leave:\n"); +#endif +} + +void +ia_css_csc_encode( + struct sh_css_isp_csc_params *to, + const struct ia_css_cc_config *from, + unsigned size) +{ + ia_css_encode_cc(to, from, size); +} + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_cc_dump( + const struct sh_css_isp_csc_params *csc, + unsigned level, + const char *name) +{ + if (!csc) return; + ia_css_debug_dtrace(level, "%s\n", name); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "m_shift", + csc->m_shift); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "m00", + csc->m00); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "m01", + csc->m01); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "m02", + csc->m02); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "m10", + csc->m10); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "m11", + csc->m11); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "m12", + csc->m12); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "m20", + csc->m20); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "m21", + csc->m21); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "m22", + csc->m22); +} + +void +ia_css_csc_dump( + const struct sh_css_isp_csc_params *csc, + unsigned level) +{ + ia_css_cc_dump(csc, level, "Color Space Conversion"); +} + +void +ia_css_cc_config_debug_dtrace( + const struct ia_css_cc_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.m[0]=%d, " + "config.m[1]=%d, config.m[2]=%d, " + "config.m[3]=%d, config.m[4]=%d, " + "config.m[5]=%d, config.m[6]=%d, " + "config.m[7]=%d, config.m[8]=%d\n", + config->matrix[0], + config->matrix[1], config->matrix[2], + config->matrix[3], config->matrix[4], + config->matrix[5], config->matrix[6], + config->matrix[7], config->matrix[8]); +} +#endif + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/csc/csc_1.0/ia_css_csc.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/csc/csc_1.0/ia_css_csc.host.h new file mode 100644 index 0000000000000000000000000000000000000000..eb10d8a5709da15fd52f4ccb33692809f8c60018 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/csc/csc_1.0/ia_css_csc.host.h @@ -0,0 +1,54 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CSC_HOST_H +#define __IA_CSS_CSC_HOST_H + +#include "ia_css_csc_types.h" +#include "ia_css_csc_param.h" + +extern const struct ia_css_cc_config default_cc_config; + +void +ia_css_encode_cc( + struct sh_css_isp_csc_params *to, + const struct ia_css_cc_config *from, + unsigned size); + +void +ia_css_csc_encode( + struct sh_css_isp_csc_params *to, + const struct ia_css_cc_config *from, + unsigned size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_cc_dump( + const struct sh_css_isp_csc_params *csc, unsigned level, + const char *name); + +void +ia_css_csc_dump( + const struct sh_css_isp_csc_params *csc, + unsigned level); + +void +ia_css_cc_config_debug_dtrace( + const struct ia_css_cc_config *config, + unsigned level); + +#define ia_css_csc_debug_dtrace ia_css_cc_config_debug_dtrace +#endif + +#endif /* __IA_CSS_CSC_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/csc/csc_1.0/ia_css_csc_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/csc/csc_1.0/ia_css_csc_param.h new file mode 100644 index 0000000000000000000000000000000000000000..0b054a939baf8cc767cba5edaea0332f4e78e717 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/csc/csc_1.0/ia_css_csc_param.h @@ -0,0 +1,34 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CSC_PARAM_H +#define __IA_CSS_CSC_PARAM_H + +#include "type_support.h" +/* CSC (Color Space Conversion) */ +struct sh_css_isp_csc_params { + uint16_t m_shift; + int16_t m00; + int16_t m01; + int16_t m02; + int16_t m10; + int16_t m11; + int16_t m12; + int16_t m20; + int16_t m21; + int16_t m22; +}; + + +#endif /* __IA_CSS_CSC_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/csc/csc_1.0/ia_css_csc_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/csc/csc_1.0/ia_css_csc_types.h new file mode 100644 index 0000000000000000000000000000000000000000..54ced072467f9903ce70313dc3dc29c1daa4fbe5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/csc/csc_1.0/ia_css_csc_types.h @@ -0,0 +1,78 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CSC_TYPES_H +#define __IA_CSS_CSC_TYPES_H + +/** @file +* CSS-API header file for Color Space Conversion parameters. +*/ + +/** Color Correction configuration. + * + * This structure is used for 3 cases. + * ("YCgCo" is the output format of Demosaic.) + * + * 1. Color Space Conversion (YCgCo to YUV) for ISP1. + * ISP block: CSC1 (Color Space Conversion) + * struct ia_css_cc_config *cc_config + * + * 2. Color Correction Matrix (YCgCo to RGB) for ISP2. + * ISP block: CCM2 (Color Correction Matrix) + * struct ia_css_cc_config *yuv2rgb_cc_config + * + * 3. Color Space Conversion (RGB to YUV) for ISP2. + * ISP block: CSC2 (Color Space Conversion) + * struct ia_css_cc_config *rgb2yuv_cc_config + * + * default/ineffective: + * 1. YCgCo -> YUV + * 1 0.174 0.185 + * 0 -0.66252 -0.66874 + * 0 -0.83738 0.58131 + * + * fraction_bits = 12 + * 4096 713 758 + * 0 -2714 -2739 + * 0 -3430 2381 + * + * 2. YCgCo -> RGB + * 1 -1 1 + * 1 1 0 + * 1 -1 -1 + * + * fraction_bits = 12 + * 4096 -4096 4096 + * 4096 4096 0 + * 4096 -4096 -4096 + * + * 3. RGB -> YUV + * 0.299 0.587 0.114 + * -0.16874 -0.33126 0.5 + * 0.5 -0.41869 -0.08131 + * + * fraction_bits = 13 + * 2449 4809 934 + * -1382 -2714 4096 + * 4096 -3430 -666 + */ +struct ia_css_cc_config { + uint32_t fraction_bits;/**< Fractional bits of matrix. + u8.0, [0,13] */ + int32_t matrix[3 * 3]; /**< Conversion matrix. + s[13-fraction_bits].[fraction_bits], + [-8192,8191] */ +}; + +#endif /* __IA_CSS_CSC_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.c new file mode 100644 index 0000000000000000000000000000000000000000..e27648c46a258e19650f6c63f06ef909e635083b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.c @@ -0,0 +1,120 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +#include "ctc/ctc_1.0/ia_css_ctc.host.h" +#include "ia_css_ctc1_5.host.h" + +static void ctc_gradient( + int *dydx, int *shift, + int y1, int y0, int x1, int x0) +{ + int frc_bits = max(IA_CSS_CTC_COEF_SHIFT, 16); + int dy = y1 - y0; + int dx = x1 - x0; + int dydx_int; + int dydx_frc; + int sft; + /* max_dydx = the maxinum gradient = the maximum y (gain) */ + int max_dydx = (1 << IA_CSS_CTC_COEF_SHIFT) - 1; + + if (dx == 0) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ctc_gradient() error, illegal division operation\n"); + return; + } else { + dydx_int = dy / dx; + dydx_frc = ((dy - dydx_int * dx) << frc_bits) / dx; + } + + assert(y0 >= 0 && y0 <= max_dydx); + assert(y1 >= 0 && y1 <= max_dydx); + assert(x0 < x1); + assert(dydx != NULL); + assert(shift != NULL); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ctc_gradient() enter:\n"); + + /* search "sft" which meets this condition: + (1 << (IA_CSS_CTC_COEF_SHIFT - 1)) + <= (((float)dy / (float)dx) * (1 << sft)) + <= ((1 << IA_CSS_CTC_COEF_SHIFT) - 1) */ + for (sft = 0; sft <= IA_CSS_CTC_COEF_SHIFT; sft++) { + int tmp_dydx = (dydx_int << sft) + + (dydx_frc >> (frc_bits - sft)); + if (tmp_dydx <= max_dydx) { + *dydx = tmp_dydx; + *shift = sft; + } + if (tmp_dydx >= max_dydx) + break; + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ctc_gradient() leave:\n"); +} + +void +ia_css_ctc_encode( + struct sh_css_isp_ctc_params *to, + const struct ia_css_ctc_config *from, + unsigned size) +{ + (void)size; + to->y0 = from->y0; + to->y1 = from->y1; + to->y2 = from->y2; + to->y3 = from->y3; + to->y4 = from->y4; + to->y5 = from->y5; + + to->ce_gain_exp = from->ce_gain_exp; + + to->x1 = from->x1; + to->x2 = from->x2; + to->x3 = from->x3; + to->x4 = from->x4; + + ctc_gradient(&(to->dydx0), + &(to->dydx0_shift), + from->y1, from->y0, + from->x1, 0); + + ctc_gradient(&(to->dydx1), + &(to->dydx1_shift), + from->y2, from->y1, + from->x2, from->x1); + + ctc_gradient(&to->dydx2, + &to->dydx2_shift, + from->y3, from->y2, + from->x3, from->x2); + + ctc_gradient(&to->dydx3, + &to->dydx3_shift, + from->y4, from->y3, + from->x4, from->x3); + + ctc_gradient(&(to->dydx4), + &(to->dydx4_shift), + from->y5, from->y4, + SH_CSS_BAYER_MAXVAL, from->x4); +} + +void +ia_css_ctc_dump( + const struct sh_css_isp_ctc_params *ctc, + unsigned level); diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.h new file mode 100644 index 0000000000000000000000000000000000000000..d943aff28152486cad41df111068ecac7276339c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.h @@ -0,0 +1,33 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CTC1_5_HOST_H +#define __IA_CSS_CTC1_5_HOST_H + +#include "sh_css_params.h" + +#include "ia_css_ctc1_5_param.h" + +void +ia_css_ctc_encode( + struct sh_css_isp_ctc_params *to, + const struct ia_css_ctc_config *from, + unsigned size); + +void +ia_css_ctc_dump( + const struct sh_css_isp_ctc_params *ctc, + unsigned level); + +#endif /* __IA_CSS_CTC1_5_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5_param.h new file mode 100644 index 0000000000000000000000000000000000000000..8d9ac2b1832c3f2a4369019fdb490bae13da670d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5_param.h @@ -0,0 +1,46 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CTC1_5_PARAM_H +#define __IA_CSS_CTC1_5_PARAM_H + +#include "type_support.h" +#include "ctc/ctc_1.0/ia_css_ctc_param.h" /* vamem params */ + +/* CTC (Color Tone Control) */ +struct sh_css_isp_ctc_params { + int32_t y0; + int32_t y1; + int32_t y2; + int32_t y3; + int32_t y4; + int32_t y5; + int32_t ce_gain_exp; + int32_t x1; + int32_t x2; + int32_t x3; + int32_t x4; + int32_t dydx0; + int32_t dydx0_shift; + int32_t dydx1; + int32_t dydx1_shift; + int32_t dydx2; + int32_t dydx2_shift; + int32_t dydx3; + int32_t dydx3_shift; + int32_t dydx4; + int32_t dydx4_shift; +}; + +#endif /* __IA_CSS_CTC1_5_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc1_5/ia_css_ctc_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc1_5/ia_css_ctc_param.h new file mode 100644 index 0000000000000000000000000000000000000000..dcd471f9bd6650d7555a455d226ab47e766cec99 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc1_5/ia_css_ctc_param.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CTCX_PARAM_H +#define __IA_CSS_CTCX_PARAM_H + +#include "ia_css_ctc1_5_param.h" + +#endif /* __IA_CSS_CTCX_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc2/ia_css_ctc2.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc2/ia_css_ctc2.host.c new file mode 100644 index 0000000000000000000000000000000000000000..1890d59e867c335d52601fc59f565236d1a527e1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc2/ia_css_ctc2.host.c @@ -0,0 +1,160 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "assert_support.h" + +#include "ia_css_ctc2.host.h" + +#define INEFFECTIVE_VAL 4096 +#define BASIC_VAL 819 + +/*Default configuration of parameters for Ctc2 +*/ +const struct ia_css_ctc2_config default_ctc2_config = { + INEFFECTIVE_VAL, INEFFECTIVE_VAL, INEFFECTIVE_VAL, + INEFFECTIVE_VAL, INEFFECTIVE_VAL, INEFFECTIVE_VAL, + BASIC_VAL * 2, BASIC_VAL * 4, BASIC_VAL * 6, + BASIC_VAL * 8, INEFFECTIVE_VAL, INEFFECTIVE_VAL, + BASIC_VAL >> 1, BASIC_VAL}; + + + +/* (dydx) = ctc2_slope(y1, y0, x1, x0) + * ----------------------------------------------- + * Calculation of the Slope of a Line = ((y1 - y0) >> 8)/(x1 - x0) + * + * Note: y1, y0 , x1 & x0 must lie within the range 0 <-> 8191 + */ +static int ctc2_slope(int y1, int y0, int x1, int x0) +{ + const int shift_val = 8; + const int max_slope = (1 << IA_CSS_CTC_COEF_SHIFT) - 1; + int dy = y1 - y0; + int dx = x1 - x0; + int rounding = (dx+1) >> 1; + int dy_shift = dy << shift_val; + int slope, dydx; + + /*Protection for paramater values, & avoiding zero divisions*/ + assert(y0 >= 0 && y0 <= max_slope); + assert(y1 >= 0 && y1 <= max_slope); + assert(x0 >= 0 && x0 <= max_slope); + assert(x1 > 0 && x1 <= max_slope); + assert(dx > 0); + + if (dy < 0) { + rounding = -rounding; + } + slope = (int) (dy_shift + rounding) / dx; + + /*the slope must lie within the range + (-max_slope-1) >= (dydx) >= (max_slope) + */ + if (slope <= -max_slope-1) { + dydx = -max_slope-1; + } else if (slope >= max_slope) { + dydx = max_slope; + } else { + dydx = slope; + } + + return dydx; +} + +/* (void) = ia_css_ctc2_vmem_encode(*to, *from) + * ----------------------------------------------- + * VMEM Encode Function to translate Y parameters from userspace into ISP space + */ +void ia_css_ctc2_vmem_encode(struct ia_css_isp_ctc2_vmem_params *to, + const struct ia_css_ctc2_config *from, + size_t size) +{ + unsigned i, j; + const unsigned shffl_blck = 4; + const unsigned lenght_zeros = 11; + short dydx0, dydx1, dydx2, dydx3, dydx4; + + (void)size; + /* + * Calculation of slopes of lines interconnecting + * 0.0 -> y_x1 -> y_x2 -> y _x3 -> y_x4 -> 1.0 + */ + dydx0 = ctc2_slope(from->y_y1, from->y_y0, + from->y_x1, 0); + dydx1 = ctc2_slope(from->y_y2, from->y_y1, + from->y_x2, from->y_x1); + dydx2 = ctc2_slope(from->y_y3, from->y_y2, + from->y_x3, from->y_x2); + dydx3 = ctc2_slope(from->y_y4, from->y_y3, + from->y_x4, from->y_x3); + dydx4 = ctc2_slope(from->y_y5, from->y_y4, + SH_CSS_BAYER_MAXVAL, from->y_x4); + + /*Fill 3 arrays with: + * - Luma input gain values y_y0, y_y1, y_y2, y_3, y_y4 + * - Luma kneepoints 0, y_x1, y_x2, y_x3, y_x4 + * - Calculated slopes dydx0, dyxd1, dydx2, dydx3, dydx4 + * + * - Each 64-element array is divided in blocks of 16 elements: + * the 5 parameters + zeros in the remaining 11 positions + * - All blocks of the same array will contain the same data + */ + for (i = 0; i < shffl_blck; i++) { + to->y_x[0][(i << shffl_blck)] = 0; + to->y_x[0][(i << shffl_blck) + 1] = from->y_x1; + to->y_x[0][(i << shffl_blck) + 2] = from->y_x2; + to->y_x[0][(i << shffl_blck) + 3] = from->y_x3; + to->y_x[0][(i << shffl_blck) + 4] = from->y_x4; + + to->y_y[0][(i << shffl_blck)] = from->y_y0; + to->y_y[0][(i << shffl_blck) + 1] = from->y_y1; + to->y_y[0][(i << shffl_blck) + 2] = from->y_y2; + to->y_y[0][(i << shffl_blck) + 3] = from->y_y3; + to->y_y[0][(i << shffl_blck) + 4] = from->y_y4; + + to->e_y_slope[0][(i << shffl_blck)] = dydx0; + to->e_y_slope[0][(i << shffl_blck) +1] = dydx1; + to->e_y_slope[0][(i << shffl_blck) +2] = dydx2; + to->e_y_slope[0][(i << shffl_blck) +3] = dydx3; + to->e_y_slope[0][(i << shffl_blck) +4] = dydx4; + + for (j = 0; j < lenght_zeros; j++) { + to->y_x[0][(i << shffl_blck)+ 5 + j] = 0; + to->y_y[0][(i << shffl_blck)+ 5 + j] = 0; + to->e_y_slope[0][(i << shffl_blck)+ 5 + j] = 0; + } + } +} + +/* (void) = ia_css_ctc2_encode(*to, *from) + * ----------------------------------------------- + * DMEM Encode Function to translate UV parameters from userspace into ISP space + */ +void ia_css_ctc2_encode(struct ia_css_isp_ctc2_dmem_params *to, + struct ia_css_ctc2_config *from, + size_t size) +{ + (void)size; + + to->uv_y0 = from->uv_y0; + to->uv_y1 = from->uv_y1; + to->uv_x0 = from->uv_x0; + to->uv_x1 = from->uv_x1; + + /*Slope Calculation*/ + to->uv_dydx = ctc2_slope(from->uv_y1, from->uv_y0, + from->uv_x1, from->uv_x0); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc2/ia_css_ctc2.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc2/ia_css_ctc2.host.h new file mode 100644 index 0000000000000000000000000000000000000000..3733aee24dcd1b940ef1dc88a3f486870cc4e3fa --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc2/ia_css_ctc2.host.h @@ -0,0 +1,33 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CTC2_HOST_H +#define __IA_CSS_CTC2_HOST_H + +#include "ia_css_ctc2_param.h" +#include "ia_css_ctc2_types.h" + +extern const struct ia_css_ctc2_config default_ctc2_config; + +/*Encode Functions to translate parameters from userspace into ISP space*/ + +void ia_css_ctc2_vmem_encode(struct ia_css_isp_ctc2_vmem_params *to, + const struct ia_css_ctc2_config *from, + size_t size); + +void ia_css_ctc2_encode(struct ia_css_isp_ctc2_dmem_params *to, + struct ia_css_ctc2_config *from, + size_t size); + +#endif /* __IA_CSS_CTC2_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc2/ia_css_ctc2_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc2/ia_css_ctc2_param.h new file mode 100644 index 0000000000000000000000000000000000000000..c66e823618f608a866f7432193a96a513637e7f7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc2/ia_css_ctc2_param.h @@ -0,0 +1,49 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CTC2_PARAM_H +#define __IA_CSS_CTC2_PARAM_H + +#define IA_CSS_CTC_COEF_SHIFT 13 +#include "vmem.h" /* needed for VMEM_ARRAY */ + +/* CTC (Chroma Tone Control)ISP Parameters */ + +/*VMEM Luma params*/ +struct ia_css_isp_ctc2_vmem_params { + /**< Gains by Y(Luma) at Y = 0.0,Y_X1, Y_X2, Y_X3, Y_X4*/ + VMEM_ARRAY(y_x, ISP_VEC_NELEMS); + /** kneepoints by Y(Luma) 0.0, y_x1, y_x2, y _x3, y_x4*/ + VMEM_ARRAY(y_y, ISP_VEC_NELEMS); + /** Slopes of lines interconnecting + * 0.0 -> y_x1 -> y_x2 -> y _x3 -> y_x4 -> 1.0*/ + VMEM_ARRAY(e_y_slope, ISP_VEC_NELEMS); +}; + +/*DMEM Chroma params*/ +struct ia_css_isp_ctc2_dmem_params { + + /** Gains by UV(Chroma) under kneepoints uv_x0 and uv_x1*/ + int32_t uv_y0; + int32_t uv_y1; + + /** Kneepoints by UV(Chroma)- uv_x0 and uv_x1*/ + int32_t uv_x0; + int32_t uv_x1; + + /** Slope of line interconnecting uv_x0 -> uv_x1*/ + int32_t uv_dydx; + +}; +#endif /* __IA_CSS_CTC2_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc2/ia_css_ctc2_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc2/ia_css_ctc2_types.h new file mode 100644 index 0000000000000000000000000000000000000000..7b75f01e2ad2ab85b7691ea8c6c78b75d4a1641a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc2/ia_css_ctc2_types.h @@ -0,0 +1,55 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CTC2_TYPES_H +#define __IA_CSS_CTC2_TYPES_H + +/** Chroma Tone Control configuration. +* +* ISP block: CTC2 (CTC by polygonal approximation) +* (ISP1: CTC1 (CTC by look-up table) is used.) +* ISP2: CTC2 is used. +* ISP261: CTC2 (CTC by Fast Approximate Distance) +*/ +struct ia_css_ctc2_config { + + /**< Gains by Y(Luma) at Y =0.0,Y_X1, Y_X2, Y_X3, Y_X4 and Y_X5 + * --default/ineffective value: 4096(0.5f) + */ + int32_t y_y0; + int32_t y_y1; + int32_t y_y2; + int32_t y_y3; + int32_t y_y4; + int32_t y_y5; + /** 1st-4th kneepoints by Y(Luma) --default/ineffective value:n/a + * requirement: 0.0 < y_x1 < y_x2 ctc, &from->data, sizeof(to->ctc)); +} + +void +ia_css_ctc_debug_dtrace( + const struct ia_css_ctc_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.ce_gain_exp=%d, config.y0=%d, " + "config.x1=%d, config.y1=%d, " + "config.x2=%d, config.y2=%d, " + "config.x3=%d, config.y3=%d, " + "config.x4=%d, config.y4=%d\n", + config->ce_gain_exp, config->y0, + config->x1, config->y1, + config->x2, config->y2, + config->x3, config->y3, + config->x4, config->y4); +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc.host.h new file mode 100644 index 0000000000000000000000000000000000000000..bec52a6519f9752f4b7d2acf4c5edac16ac47385 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc.host.h @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CTC_HOST_H +#define __IA_CSS_CTC_HOST_H + +#include "sh_css_params.h" + +#include "ia_css_ctc_param.h" +#include "ia_css_ctc_table.host.h" + +extern const struct ia_css_ctc_config default_ctc_config; + +void +ia_css_ctc_vamem_encode( + struct sh_css_isp_ctc_vamem_params *to, + const struct ia_css_ctc_table *from, + unsigned size); + +void +ia_css_ctc_debug_dtrace( + const struct ia_css_ctc_config *config, unsigned level) +; + +#endif /* __IA_CSS_CTC_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc_param.h new file mode 100644 index 0000000000000000000000000000000000000000..6e88ad3d24201d0e9a57130ebb0af07df5d4a9a8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc_param.h @@ -0,0 +1,44 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CTC_PARAM_H +#define __IA_CSS_CTC_PARAM_H + +#include "type_support.h" +#include + +#include "ia_css_ctc_types.h" + +#ifndef PIPE_GENERATION +#if defined(HAS_VAMEM_VERSION_2) +#define SH_CSS_ISP_CTC_TABLE_SIZE_LOG2 IA_CSS_VAMEM_2_CTC_TABLE_SIZE_LOG2 +#define SH_CSS_ISP_CTC_TABLE_SIZE IA_CSS_VAMEM_2_CTC_TABLE_SIZE +#elif defined(HAS_VAMEM_VERSION_1) +#define SH_CSS_ISP_CTC_TABLE_SIZE_LOG2 IA_CSS_VAMEM_1_CTC_TABLE_SIZE_LOG2 +#define SH_CSS_ISP_CTC_TABLE_SIZE IA_CSS_VAMEM_1_CTC_TABLE_SIZE +#else +#error "VAMEM should be {VERSION1, VERSION2}" +#endif + +#else +/* For pipe generation, the size is not relevant */ +#define SH_CSS_ISP_CTC_TABLE_SIZE 0 +#endif + +/* This should be vamem_data_t, but that breaks the pipe generator */ +struct sh_css_isp_ctc_vamem_params { + uint16_t ctc[SH_CSS_ISP_CTC_TABLE_SIZE]; +}; + +#endif /* __IA_CSS_CTC_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc_table.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc_table.host.c new file mode 100644 index 0000000000000000000000000000000000000000..edf85aba77165af36c181d0929a1e449ab6bdd1f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc_table.host.c @@ -0,0 +1,215 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include /* memcpy */ +#include "system_global.h" +#include "vamem.h" +#include "ia_css_types.h" +#include "ia_css_ctc_table.host.h" + +struct ia_css_ctc_table default_ctc_table; + +#if defined(HAS_VAMEM_VERSION_2) + +static const uint16_t +default_ctc_table_data[IA_CSS_VAMEM_2_CTC_TABLE_SIZE] = { + 0, 384, 837, 957, 1011, 1062, 1083, 1080, +1078, 1077, 1053, 1039, 1012, 992, 969, 951, + 929, 906, 886, 866, 845, 823, 809, 790, + 772, 758, 741, 726, 711, 701, 688, 675, + 666, 656, 648, 639, 633, 626, 618, 612, + 603, 594, 582, 572, 557, 545, 529, 516, + 504, 491, 480, 467, 459, 447, 438, 429, + 419, 412, 404, 397, 389, 382, 376, 368, + 363, 357, 351, 345, 340, 336, 330, 326, + 321, 318, 312, 308, 304, 300, 297, 294, + 291, 286, 284, 281, 278, 275, 271, 268, + 261, 257, 251, 245, 240, 235, 232, 225, + 223, 218, 213, 209, 206, 204, 199, 197, + 193, 189, 186, 185, 183, 179, 177, 175, + 172, 170, 169, 167, 164, 164, 162, 160, + 158, 157, 156, 154, 154, 152, 151, 150, + 149, 148, 146, 147, 146, 144, 143, 143, + 142, 141, 140, 141, 139, 138, 138, 138, + 137, 136, 136, 135, 134, 134, 134, 133, + 132, 132, 131, 130, 131, 130, 129, 128, + 129, 127, 127, 127, 127, 125, 125, 125, + 123, 123, 122, 120, 118, 115, 114, 111, + 110, 108, 106, 105, 103, 102, 100, 99, + 97, 97, 96, 95, 94, 93, 93, 91, + 91, 91, 90, 90, 89, 89, 88, 88, + 89, 88, 88, 87, 87, 87, 87, 86, + 87, 87, 86, 87, 86, 86, 84, 84, + 82, 80, 78, 76, 74, 72, 70, 68, + 67, 65, 62, 60, 58, 56, 55, 54, + 53, 51, 49, 49, 47, 45, 45, 45, + 41, 40, 39, 39, 34, 33, 34, 32, + 25, 23, 24, 20, 13, 9, 12, 0, + 0 +}; + +#elif defined(HAS_VAMEM_VERSION_1) + +/* Default Parameters */ +static const uint16_t +default_ctc_table_data[IA_CSS_VAMEM_1_CTC_TABLE_SIZE] = { + 0, 0, 256, 384, 384, 497, 765, 806, + 837, 851, 888, 901, 957, 981, 993, 1001, + 1011, 1029, 1028, 1039, 1062, 1059, 1073, 1080, + 1083, 1085, 1085, 1098, 1080, 1084, 1085, 1093, + 1078, 1073, 1070, 1069, 1077, 1066, 1072, 1063, + 1053, 1044, 1046, 1053, 1039, 1028, 1025, 1024, + 1012, 1013, 1016, 996, 992, 990, 990, 980, + 969, 968, 961, 955, 951, 949, 933, 930, + 929, 925, 921, 916, 906, 901, 895, 893, + 886, 877, 872, 869, 866, 861, 857, 849, + 845, 838, 836, 832, 823, 821, 815, 813, + 809, 805, 796, 793, 790, 785, 784, 778, + 772, 768, 766, 763, 758, 752, 749, 745, + 741, 740, 736, 730, 726, 724, 723, 718, + 711, 709, 706, 704, 701, 698, 691, 689, + 688, 683, 683, 678, 675, 673, 671, 669, + 666, 663, 661, 660, 656, 656, 653, 650, + 648, 647, 646, 643, 639, 638, 637, 635, + 633, 632, 629, 627, 626, 625, 622, 621, + 618, 618, 614, 614, 612, 609, 606, 606, + 603, 600, 600, 597, 594, 591, 590, 586, + 582, 581, 578, 575, 572, 569, 563, 560, + 557, 554, 551, 548, 545, 539, 536, 533, + 529, 527, 524, 519, 516, 513, 510, 507, + 504, 501, 498, 493, 491, 488, 485, 484, + 480, 476, 474, 471, 467, 466, 464, 460, + 459, 455, 453, 449, 447, 446, 443, 441, + 438, 435, 432, 432, 429, 427, 426, 422, + 419, 418, 416, 414, 412, 410, 408, 406, + 404, 402, 401, 398, 397, 395, 393, 390, + 389, 388, 387, 384, 382, 380, 378, 377, + 376, 375, 372, 370, 368, 368, 366, 364, + 363, 361, 360, 358, 357, 355, 354, 352, + 351, 350, 349, 346, 345, 344, 344, 342, + 340, 339, 337, 337, 336, 335, 333, 331, + 330, 329, 328, 326, 326, 324, 324, 322, + 321, 320, 318, 318, 318, 317, 315, 313, + 312, 311, 311, 310, 308, 307, 306, 306, + 304, 304, 302, 301, 300, 300, 299, 297, + 297, 296, 296, 294, 294, 292, 291, 291, + 291, 290, 288, 287, 286, 286, 287, 285, + 284, 283, 282, 282, 281, 281, 279, 278, + 278, 278, 276, 276, 275, 274, 274, 273, + 271, 270, 269, 268, 268, 267, 265, 262, + 261, 260, 260, 259, 257, 254, 252, 252, + 251, 251, 249, 246, 245, 244, 243, 242, + 240, 239, 239, 237, 235, 235, 233, 231, + 232, 230, 229, 226, 225, 224, 225, 224, + 223, 220, 219, 219, 218, 217, 217, 214, + 213, 213, 212, 211, 209, 209, 209, 208, + 206, 205, 204, 203, 204, 203, 201, 200, + 199, 197, 198, 198, 197, 195, 194, 194, + 193, 192, 192, 191, 189, 190, 189, 188, + 186, 187, 186, 185, 185, 184, 183, 181, + 183, 182, 181, 180, 179, 178, 178, 178, + 177, 176, 175, 176, 175, 174, 174, 173, + 172, 173, 172, 171, 170, 170, 169, 169, + 169, 168, 167, 166, 167, 167, 166, 165, + 164, 164, 164, 163, 164, 163, 162, 163, + 162, 161, 160, 161, 160, 160, 160, 159, + 158, 157, 158, 158, 157, 157, 156, 156, + 156, 156, 155, 155, 154, 154, 154, 154, + 154, 153, 152, 153, 152, 152, 151, 152, + 151, 152, 151, 150, 150, 149, 149, 150, + 149, 149, 148, 148, 148, 149, 148, 147, + 146, 146, 147, 146, 147, 146, 145, 146, + 146, 145, 144, 145, 144, 145, 144, 144, + 143, 143, 143, 144, 143, 142, 142, 142, + 142, 142, 142, 141, 141, 141, 141, 140, + 140, 141, 140, 140, 141, 140, 139, 139, + 139, 140, 139, 139, 138, 138, 137, 139, + 138, 138, 138, 137, 138, 137, 137, 137, + 137, 136, 137, 136, 136, 136, 136, 135, + 136, 135, 135, 135, 135, 136, 135, 135, + 134, 134, 133, 135, 134, 134, 134, 133, + 134, 133, 134, 133, 133, 132, 133, 133, + 132, 133, 132, 132, 132, 132, 131, 131, + 131, 132, 131, 131, 130, 131, 130, 132, + 131, 130, 130, 129, 130, 129, 130, 129, + 129, 129, 130, 129, 128, 128, 128, 128, + 129, 128, 128, 127, 127, 128, 128, 127, + 127, 126, 126, 127, 127, 126, 126, 126, + 127, 126, 126, 126, 125, 125, 126, 125, + 125, 124, 124, 124, 125, 125, 124, 124, + 123, 124, 124, 123, 123, 122, 122, 122, + 122, 122, 121, 120, 120, 119, 118, 118, + 118, 117, 117, 116, 115, 115, 115, 114, + 114, 113, 113, 112, 111, 111, 111, 110, + 110, 109, 109, 108, 108, 108, 107, 107, + 106, 106, 105, 105, 105, 104, 104, 103, + 103, 102, 102, 102, 102, 101, 101, 100, + 100, 99, 99, 99, 99, 99, 99, 98, + 97, 98, 97, 97, 97, 96, 96, 95, + 96, 95, 96, 95, 95, 94, 94, 95, + 94, 94, 94, 93, 93, 92, 93, 93, + 93, 93, 92, 92, 91, 92, 92, 92, + 91, 91, 90, 90, 91, 91, 91, 90, + 90, 90, 90, 91, 90, 90, 90, 89, + 89, 89, 90, 89, 89, 89, 89, 89, + 88, 89, 89, 88, 88, 88, 88, 87, + 89, 88, 88, 88, 88, 88, 87, 88, + 88, 88, 87, 87, 87, 87, 87, 88, + 87, 87, 87, 87, 87, 87, 88, 87, + 87, 87, 87, 86, 86, 87, 87, 87, + 87, 86, 86, 86, 87, 87, 86, 87, + 86, 86, 86, 87, 87, 86, 86, 86, + 86, 86, 87, 87, 86, 85, 85, 85, + 84, 85, 85, 84, 84, 83, 83, 82, + 82, 82, 81, 81, 80, 79, 79, 79, + 78, 77, 77, 76, 76, 76, 75, 74, + 74, 74, 73, 73, 72, 71, 71, 71, + 70, 70, 69, 69, 68, 68, 67, 67, + 67, 66, 66, 65, 65, 64, 64, 63, + 62, 62, 62, 61, 60, 60, 59, 59, + 58, 58, 57, 57, 56, 56, 56, 55, + 55, 54, 55, 55, 54, 53, 53, 52, + 53, 53, 52, 51, 51, 50, 51, 50, + 49, 49, 50, 49, 49, 48, 48, 47, + 47, 48, 46, 45, 45, 45, 46, 45, + 45, 44, 45, 45, 45, 43, 42, 42, + 41, 43, 41, 40, 40, 39, 40, 41, + 39, 39, 39, 39, 39, 38, 35, 35, + 34, 37, 36, 34, 33, 33, 33, 35, + 34, 32, 32, 31, 32, 30, 29, 26, + 25, 25, 27, 26, 23, 23, 23, 25, + 24, 24, 22, 21, 20, 19, 16, 14, + 13, 13, 13, 10, 9, 7, 7, 7, + 12, 12, 12, 7, 0, 0, 0, 0 +}; + +#else +#error "VAMEM version must be one of {VAMEM_VERSION_1, VAMEM_VERSION_2}" +#endif + +void +ia_css_config_ctc_table(void) +{ +#if defined(HAS_VAMEM_VERSION_2) + memcpy(default_ctc_table.data.vamem_2, default_ctc_table_data, + sizeof(default_ctc_table_data)); + default_ctc_table.vamem_type = IA_CSS_VAMEM_TYPE_2; +#else + memcpy(default_ctc_table.data.vamem_1, default_ctc_table_data, + sizeof(default_ctc_table_data)); + default_ctc_table.vamem_type = 1IA_CSS_VAMEM_TYPE_1; +#endif +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc_table.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc_table.host.h new file mode 100644 index 0000000000000000000000000000000000000000..a350dec8b4adbfa796e12cb208237369bfb7fb3b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc_table.host.h @@ -0,0 +1,24 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CTC_TABLE_HOST_H +#define __IA_CSS_CTC_TABLE_HOST_H + +#include "ia_css_ctc_types.h" + +extern struct ia_css_ctc_table default_ctc_table; + +void ia_css_config_ctc_table(void); + +#endif /* __IA_CSS_CTC_TABLE_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc_types.h new file mode 100644 index 0000000000000000000000000000000000000000..1da215bb966d15d166b2ccbaf5421b8c81178e00 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc_types.h @@ -0,0 +1,110 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_CTC_TYPES_H +#define __IA_CSS_CTC_TYPES_H + +/** @file +* CSS-API header file for Chroma Tone Control parameters. +*/ + +/** Fractional bits for CTC gain (used only for ISP1). + * + * IA_CSS_CTC_COEF_SHIFT(=13) includes not only the fractional bits + * of gain(=8), but also the bits(=5) to convert chroma + * from 13bit precision to 8bit precision. + * + * Gain (struct ia_css_ctc_table) : u5.8 + * Input(Chorma) : s0.12 (13bit precision) + * Output(Chorma): s0.7 (8bit precision) + * Output = (Input * Gain) >> IA_CSS_CTC_COEF_SHIFT + */ +#define IA_CSS_CTC_COEF_SHIFT 13 + +/** Number of elements in the CTC table. */ +#define IA_CSS_VAMEM_1_CTC_TABLE_SIZE_LOG2 10 +/** Number of elements in the CTC table. */ +#define IA_CSS_VAMEM_1_CTC_TABLE_SIZE (1U<pixelnoise = + uDIGIT_FITTING(from->pixelnoise, 16, SH_CSS_BAYER_BITS); + to->c1_coring_threshold = + uDIGIT_FITTING(from->c1_coring_threshold, 16, + SH_CSS_BAYER_BITS); + to->c2_coring_threshold = + uDIGIT_FITTING(from->c2_coring_threshold, 16, + SH_CSS_BAYER_BITS); +} + +void +ia_css_de_dump( + const struct sh_css_isp_de_params *de, + unsigned level) +{ + if (!de) return; + ia_css_debug_dtrace(level, "Demosaic:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "de_pixelnoise", de->pixelnoise); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "de_c1_coring_threshold", + de->c1_coring_threshold); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "de_c2_coring_threshold", + de->c2_coring_threshold); +} + +void +ia_css_de_debug_dtrace( + const struct ia_css_de_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.pixelnoise=%d, " + "config.c1_coring_threshold=%d, config.c2_coring_threshold=%d\n", + config->pixelnoise, + config->c1_coring_threshold, config->c2_coring_threshold); +} + +void +ia_css_init_de_state( + void/*struct sh_css_isp_de_vmem_state*/ *state, + size_t size) +{ + memset(state, 0, size); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_1.0/ia_css_de.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_1.0/ia_css_de.host.h new file mode 100644 index 0000000000000000000000000000000000000000..5dd6f06f2bf14051337e07671e30ea55439e6c2b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_1.0/ia_css_de.host.h @@ -0,0 +1,44 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DE_HOST_H +#define __IA_CSS_DE_HOST_H + +#include "ia_css_de_types.h" +#include "ia_css_de_param.h" + +extern const struct ia_css_de_config default_de_config; + +void +ia_css_de_encode( + struct sh_css_isp_de_params *to, + const struct ia_css_de_config *from, + unsigned size); + +void +ia_css_de_dump( + const struct sh_css_isp_de_params *de, + unsigned level); + +void +ia_css_de_debug_dtrace( + const struct ia_css_de_config *config, + unsigned level); + +void +ia_css_init_de_state( + void/*struct sh_css_isp_de_vmem_state*/ *state, + size_t size); + +#endif /* __IA_CSS_DE_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_1.0/ia_css_de_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_1.0/ia_css_de_param.h new file mode 100644 index 0000000000000000000000000000000000000000..833c80afc7a848c8df950b3afafdff4f65d3c6ee --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_1.0/ia_css_de_param.h @@ -0,0 +1,27 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DE_PARAM_H +#define __IA_CSS_DE_PARAM_H + +#include "type_support.h" + +/* DE (Demosaic) */ +struct sh_css_isp_de_params { + int32_t pixelnoise; + int32_t c1_coring_threshold; + int32_t c2_coring_threshold; +}; + +#endif /* __IA_CSS_DE_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_1.0/ia_css_de_state.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_1.0/ia_css_de_state.h new file mode 100644 index 0000000000000000000000000000000000000000..d64511763436208637f28732c6868b2350cd1a21 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_1.0/ia_css_de_state.h @@ -0,0 +1,26 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DE_STATE_H +#define __IA_CSS_DE_STATE_H + +#include "type_support.h" +#include "vmem.h" + +/* DE (Demosaic) */ +struct sh_css_isp_de_vmem_state { + VMEM_ARRAY(de_buf[4], MAX_VECTORS_PER_BUF_LINE*ISP_NWAY); +}; + +#endif /* __IA_CSS_DE_STATE_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_1.0/ia_css_de_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_1.0/ia_css_de_types.h new file mode 100644 index 0000000000000000000000000000000000000000..525c838d5a99c113f3453d3b91db7c3dabcd8fab --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_1.0/ia_css_de_types.h @@ -0,0 +1,43 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DE_TYPES_H +#define __IA_CSS_DE_TYPES_H + +/** @file +* CSS-API header file for Demosaic (bayer-to-YCgCo) parameters. +*/ + +/** Demosaic (bayer-to-YCgCo) configuration. + * + * ISP block: DE1 + * ISP1: DE1 is used. + * (ISP2: DE2 is used.) + */ +struct ia_css_de_config { + ia_css_u0_16 pixelnoise; /**< Pixel noise used in moire elimination. + u0.16, [0,65535], + default 0, ineffective 0 */ + ia_css_u0_16 c1_coring_threshold; /**< Coring threshold for C1. + This is the same as nr_config.threshold_cb. + u0.16, [0,65535], + default 128(0.001953125), ineffective 0 */ + ia_css_u0_16 c2_coring_threshold; /**< Coring threshold for C2. + This is the same as nr_config.threshold_cr. + u0.16, [0,65535], + default 128(0.001953125), ineffective 0 */ +}; + +#endif /* __IA_CSS_DE_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_2/ia_css_de2.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_2/ia_css_de2.host.c new file mode 100644 index 0000000000000000000000000000000000000000..a5247a57bafbbed43f8ec637a8c8e49523e50834 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_2/ia_css_de2.host.c @@ -0,0 +1,54 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" + +#include "ia_css_de2.host.h" + +const struct ia_css_ecd_config default_ecd_config = { + (1 << (ISP_VEC_ELEMBITS - 1)) * 2 / 3, /* 2/3 */ + (1 << (ISP_VEC_ELEMBITS - 1)) - 1, /* 1.0 */ + 0, /* 0.0 */ +}; + +void +ia_css_ecd_encode( + struct sh_css_isp_ecd_params *to, + const struct ia_css_ecd_config *from, + unsigned size) +{ + (void)size; + to->zip_strength = from->zip_strength; + to->fc_strength = from->fc_strength; + to->fc_debias = from->fc_debias; +} + +void +ia_css_ecd_dump( + const struct sh_css_isp_ecd_params *ecd, + unsigned level); + +void +ia_css_ecd_debug_dtrace( + const struct ia_css_ecd_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.zip_strength=%d, " + "config.fc_strength=%d, config.fc_debias=%d\n", + config->zip_strength, + config->fc_strength, config->fc_debias); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_2/ia_css_de2.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_2/ia_css_de2.host.h new file mode 100644 index 0000000000000000000000000000000000000000..f7cd8448cb304b455cfc9b8542115724e38eb6d8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_2/ia_css_de2.host.h @@ -0,0 +1,38 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DE2_HOST_H +#define __IA_CSS_DE2_HOST_H + +#include "ia_css_de2_types.h" +#include "ia_css_de2_param.h" + +extern const struct ia_css_ecd_config default_ecd_config; + +void +ia_css_ecd_encode( + struct sh_css_isp_ecd_params *to, + const struct ia_css_ecd_config *from, + unsigned size); + +void +ia_css_ecd_dump( + const struct sh_css_isp_ecd_params *ecd, + unsigned level); + +void +ia_css_ecd_debug_dtrace( + const struct ia_css_ecd_config *config, unsigned level); + +#endif /* __IA_CSS_DE2_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_2/ia_css_de2_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_2/ia_css_de2_param.h new file mode 100644 index 0000000000000000000000000000000000000000..ea2da73a4927273a7e0af1e25e85b545e6f944cc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_2/ia_css_de2_param.h @@ -0,0 +1,30 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DE2_PARAM_H +#define __IA_CSS_DE2_PARAM_H + +#include "type_support.h" + +/* Reuse DE1 params and extend them */ +#include "../de_1.0/ia_css_de_param.h" + +/* DE (Demosaic) */ +struct sh_css_isp_ecd_params { + int32_t zip_strength; + int32_t fc_strength; + int32_t fc_debias; +}; + +#endif /* __IA_CSS_DE2_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_2/ia_css_de2_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_2/ia_css_de2_types.h new file mode 100644 index 0000000000000000000000000000000000000000..eac1b27798574de3b1f26983ef6cbc988a573e88 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_2/ia_css_de2_types.h @@ -0,0 +1,42 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DE2_TYPES_H +#define __IA_CSS_DE2_TYPES_H + +/** @file +* CSS-API header file for Demosaicing parameters. +*/ + +/** Eigen Color Demosaicing configuration. + * + * ISP block: DE2 + * (ISP1: DE1 is used.) + * ISP2: DE2 is used. + */ +struct ia_css_ecd_config { + uint16_t zip_strength; /**< Strength of zipper reduction. + u0.13, [0,8191], + default 5489(0.67), ineffective 0 */ + uint16_t fc_strength; /**< Strength of false color reduction. + u0.13, [0,8191], + default 8191(almost 1.0), ineffective 0 */ + uint16_t fc_debias; /**< Prevent color change + on noise or Gr/Gb imbalance. + u0.13, [0,8191], + default 0, ineffective 0 */ +}; + +#endif /* __IA_CSS_DE2_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_2/ia_css_de_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_2/ia_css_de_param.h new file mode 100644 index 0000000000000000000000000000000000000000..59af9523604d675541c490021853299d375bdeb1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_2/ia_css_de_param.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DEX_PARAM_H +#define __IA_CSS_DEX_PARAM_H + +#include "ia_css_de2_param.h" + +#endif /* __IA_CSS_DEX_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_2/ia_css_de_state.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_2/ia_css_de_state.h new file mode 100644 index 0000000000000000000000000000000000000000..f2c65ba589830dd84c4c6d663df1acd551e8d923 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/de/de_2/ia_css_de_state.h @@ -0,0 +1,21 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DE2_STATE_H +#define __IA_CSS_DE2_STATE_H + +/* Reuse DE1 states */ +#include "../de_1.0/ia_css_de_state.h" + +#endif /* __IA_CSS_DE2_STATE_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dp/dp_1.0/ia_css_dp.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dp/dp_1.0/ia_css_dp.host.c new file mode 100644 index 0000000000000000000000000000000000000000..b1f9dc8d662d64f3fa761a86e73df5b28bf59e7c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dp/dp_1.0/ia_css_dp.host.c @@ -0,0 +1,132 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "sh_css_frac.h" + +#include "ia_css_dp.host.h" + +#ifdef ISP2401 +/* We use a different set of DPC configuration parameters when + * DPC is used before OBC and NORM. Currently these parameters + * are used in usecases which selects both BDS and DPC. + **/ +const struct ia_css_dp_config default_dp_10bpp_config = { + 1024, + 2048, + 32768, + 32768, + 32768, + 32768 +}; +#endif +const struct ia_css_dp_config default_dp_config = { + 8192, + 2048, + 32768, + 32768, + 32768, + 32768 +}; + +void +ia_css_dp_encode( + struct sh_css_isp_dp_params *to, + const struct ia_css_dp_config *from, + unsigned size) +{ + int gain = from->gain; + int gr = from->gr; + int r = from->r; + int b = from->b; + int gb = from->gb; + + (void)size; + to->threshold_single = + SH_CSS_BAYER_MAXVAL; + to->threshold_2adjacent = + uDIGIT_FITTING(from->threshold, 16, SH_CSS_BAYER_BITS); + to->gain = + uDIGIT_FITTING(from->gain, 8, SH_CSS_DP_GAIN_SHIFT); + + to->coef_rr_gr = + uDIGIT_FITTING (gain * gr / r, 8, SH_CSS_DP_GAIN_SHIFT); + to->coef_rr_gb = + uDIGIT_FITTING (gain * gb / r, 8, SH_CSS_DP_GAIN_SHIFT); + to->coef_bb_gb = + uDIGIT_FITTING (gain * gb / b, 8, SH_CSS_DP_GAIN_SHIFT); + to->coef_bb_gr = + uDIGIT_FITTING (gain * gr / b, 8, SH_CSS_DP_GAIN_SHIFT); + to->coef_gr_rr = + uDIGIT_FITTING (gain * r / gr, 8, SH_CSS_DP_GAIN_SHIFT); + to->coef_gr_bb = + uDIGIT_FITTING (gain * b / gr, 8, SH_CSS_DP_GAIN_SHIFT); + to->coef_gb_bb = + uDIGIT_FITTING (gain * b / gb, 8, SH_CSS_DP_GAIN_SHIFT); + to->coef_gb_rr = + uDIGIT_FITTING (gain * r / gb, 8, SH_CSS_DP_GAIN_SHIFT); +} + +void +ia_css_dp_dump( + const struct sh_css_isp_dp_params *dp, + unsigned level) +{ + if (!dp) return; + ia_css_debug_dtrace(level, "Defect Pixel Correction:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dp_threshold_single_w_2adj_on", + dp->threshold_single); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dp_threshold_2adj_w_2adj_on", + dp->threshold_2adjacent); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dp_gain", dp->gain); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dpc_coef_rr_gr", dp->coef_rr_gr); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dpc_coef_rr_gb", dp->coef_rr_gb); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dpc_coef_bb_gb", dp->coef_bb_gb); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dpc_coef_bb_gr", dp->coef_bb_gr); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dpc_coef_gr_rr", dp->coef_gr_rr); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dpc_coef_gr_bb", dp->coef_gr_bb); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dpc_coef_gb_bb", dp->coef_gb_bb); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "dpc_coef_gb_rr", dp->coef_gb_rr); +} + +void +ia_css_dp_debug_dtrace( + const struct ia_css_dp_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.threshold=%d, config.gain=%d\n", + config->threshold, config->gain); +} + +void +ia_css_init_dp_state( + void/*struct sh_css_isp_dp_vmem_state*/ *state, + size_t size) +{ + memset(state, 0, size); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dp/dp_1.0/ia_css_dp.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dp/dp_1.0/ia_css_dp.host.h new file mode 100644 index 0000000000000000000000000000000000000000..db21814ad3db856066f5403fee57f9f26722c50b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dp/dp_1.0/ia_css_dp.host.h @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DP_HOST_H +#define __IA_CSS_DP_HOST_H + +#include "ia_css_dp_types.h" +#include "ia_css_dp_param.h" + +extern const struct ia_css_dp_config default_dp_config; +#ifdef ISP2401 +extern const struct ia_css_dp_config default_dp_10bpp_config; +#endif + +void +ia_css_dp_encode( + struct sh_css_isp_dp_params *to, + const struct ia_css_dp_config *from, + unsigned size); + +void +ia_css_dp_dump( + const struct sh_css_isp_dp_params *dp, + unsigned level); + +void +ia_css_dp_debug_dtrace( + const struct ia_css_dp_config *config, + unsigned level); + +void +ia_css_init_dp_state( + void/*struct sh_css_isp_dp_vmem_state*/ *state, + size_t size); + +#endif /* __IA_CSS_DP_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dp/dp_1.0/ia_css_dp_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dp/dp_1.0/ia_css_dp_param.h new file mode 100644 index 0000000000000000000000000000000000000000..fc9035a98d9221f9d34b4c896abdba34aa5fa435 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dp/dp_1.0/ia_css_dp_param.h @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DP_PARAM_H +#define __IA_CSS_DP_PARAM_H + +#include "type_support.h" +#include "bnr/bnr_1.0/ia_css_bnr_param.h" + +/* DP (Defect Pixel Correction) */ +struct sh_css_isp_dp_params { + int32_t threshold_single; + int32_t threshold_2adjacent; + int32_t gain; + int32_t coef_rr_gr; + int32_t coef_rr_gb; + int32_t coef_bb_gb; + int32_t coef_bb_gr; + int32_t coef_gr_rr; + int32_t coef_gr_bb; + int32_t coef_gb_bb; + int32_t coef_gb_rr; +}; + +#endif /* __IA_CSS_DP_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dp/dp_1.0/ia_css_dp_state.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dp/dp_1.0/ia_css_dp_state.h new file mode 100644 index 0000000000000000000000000000000000000000..f832b3697908eea504835845c4db33e8b1acef80 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dp/dp_1.0/ia_css_dp_state.h @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DP_STATE_H +#define __IA_CSS_DP_STATE_H + +#include "type_support.h" + +#include "vmem.h" +#ifndef ISP2401 +#if NEED_BDS_OTHER_THAN_1_00 +#else +#if ENABLE_FIXED_BAYER_DS +#endif +#define MAX_VECTORS_PER_DP_LINE MAX_VECTORS_PER_BUF_INPUT_LINE +#else +#define MAX_VECTORS_PER_DP_LINE MAX_VECTORS_PER_BUF_LINE +#endif + +/* DP (Defect Pixel Correction) */ +struct sh_css_isp_dp_vmem_state { + VMEM_ARRAY(dp_buf[4], MAX_VECTORS_PER_DP_LINE*ISP_NWAY); +}; + +#endif /* __IA_CSS_DP_STATE_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dp/dp_1.0/ia_css_dp_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dp/dp_1.0/ia_css_dp_types.h new file mode 100644 index 0000000000000000000000000000000000000000..b5d7b6b175b642d19400c36c67eda9c2b6ad3360 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dp/dp_1.0/ia_css_dp_types.h @@ -0,0 +1,50 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DP_TYPES_H +#define __IA_CSS_DP_TYPES_H + +/** @file +* CSS-API header file for Defect Pixel Correction (DPC) parameters. +*/ + + +/** Defect Pixel Correction configuration. + * + * ISP block: DPC1 (DPC after WB) + * DPC2 (DPC before WB) + * ISP1: DPC1 is used. + * ISP2: DPC2 is used. + */ +struct ia_css_dp_config { + ia_css_u0_16 threshold; /**< The threshold of defect pixel correction, + representing the permissible difference of + intensity between one pixel and its + surrounding pixels. Smaller values result + in more frequent pixel corrections. + u0.16, [0,65535], + default 8192, ineffective 65535 */ + ia_css_u8_8 gain; /**< The sensitivity of mis-correction. ISP will + miss a lot of defects if the value is set + too large. + u8.8, [0,65535], + default 4096, ineffective 65535 */ + uint32_t gr; /* unsigned .<16-integer_bits> */ + uint32_t r; /* unsigned .<16-integer_bits> */ + uint32_t b; /* unsigned .<16-integer_bits> */ + uint32_t gb; /* unsigned .<16-integer_bits> */ +}; + +#endif /* __IA_CSS_DP_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2.host.c new file mode 100644 index 0000000000000000000000000000000000000000..bc14b85cf952767b1654b921b986deeb0d0bd9a4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2.host.c @@ -0,0 +1,65 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_dpc2.host.h" +#include "assert_support.h" + +void +ia_css_dpc2_encode( + struct ia_css_isp_dpc2_params *to, + const struct ia_css_dpc2_config *from, + size_t size) +{ + (void)size; + + assert ((from->metric1 >= 0) && (from->metric1 <= METRIC1_ONE_FP)); + assert ((from->metric3 >= 0) && (from->metric3 <= METRIC3_ONE_FP)); + assert ((from->metric2 >= METRIC2_ONE_FP) && + (from->metric2 < 256*METRIC2_ONE_FP)); + assert ((from->wb_gain_gr > 0) && (from->wb_gain_gr < 16*WBGAIN_ONE_FP)); + assert ((from->wb_gain_r > 0) && (from->wb_gain_r < 16*WBGAIN_ONE_FP)); + assert ((from->wb_gain_b > 0) && (from->wb_gain_b < 16*WBGAIN_ONE_FP)); + assert ((from->wb_gain_gb > 0) && (from->wb_gain_gb < 16*WBGAIN_ONE_FP)); + + to->metric1 = from->metric1; + to->metric2 = from->metric2; + to->metric3 = from->metric3; + + to->wb_gain_gr = from->wb_gain_gr; + to->wb_gain_r = from->wb_gain_r; + to->wb_gain_b = from->wb_gain_b; + to->wb_gain_gb = from->wb_gain_gb; +} + +/* TODO: AM: This needs a proper implementation. */ +void +ia_css_init_dpc2_state( + void *state, + size_t size) +{ + (void)state; + (void)size; +} + +#ifndef IA_CSS_NO_DEBUG +/* TODO: AM: This needs a proper implementation. */ +void +ia_css_dpc2_debug_dtrace( + const struct ia_css_dpc2_config *config, + unsigned level) +{ + (void)config; + (void)level; +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2.host.h new file mode 100644 index 0000000000000000000000000000000000000000..641564b4af8e59c393d4969d3657d049c2caa86a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2.host.h @@ -0,0 +1,40 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DPC2_HOST_H +#define __IA_CSS_DPC2_HOST_H + +#include "ia_css_dpc2_types.h" +#include "ia_css_dpc2_param.h" +#include "ia_css_dpc2_default.host.h" + +void +ia_css_dpc2_encode( + struct ia_css_isp_dpc2_params *to, + const struct ia_css_dpc2_config *from, + size_t size); + +void +ia_css_init_dpc2_state( + void *state, + size_t size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_dpc2_debug_dtrace( + const struct ia_css_dpc2_config *config, + unsigned level); +#endif + +#endif /* __IA_CSS_DPC2_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2_default.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2_default.host.c new file mode 100644 index 0000000000000000000000000000000000000000..c102601cc6357cd7a2788dc28e8f4c272b4cd191 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2_default.host.c @@ -0,0 +1,26 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_dpc2_types.h" + +const struct ia_css_dpc2_config default_dpc2_config = { + .metric1 = 1638, + .metric2 = 128, + .metric3 = 1638, + .wb_gain_gr = 512, + .wb_gain_r = 512, + .wb_gain_b = 512, + .wb_gain_gb = 512 +}; + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2_default.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2_default.host.h new file mode 100644 index 0000000000000000000000000000000000000000..a1527ce3eddc14e29c649cab2315b6150a7f3603 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2_default.host.h @@ -0,0 +1,23 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DPC2_DEFAULT_HOST_H +#define __IA_CSS_DPC2_DEFAULT_HOST_H + +#include "ia_css_dpc2_types.h" + +extern const struct ia_css_dpc2_config default_dpc2_config; + +#endif /* __IA_CSS_DPC2_DEFAULT_HOST_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2_param.h new file mode 100644 index 0000000000000000000000000000000000000000..ef668d54fe16d3ace48bdb4e7f57dc48b008d6a2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2_param.h @@ -0,0 +1,53 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DPC2_PARAM_H +#define __IA_CSS_DPC2_PARAM_H + +#include "type_support.h" +#include "vmem.h" /* for VMEM_ARRAY*/ + + +/* 4 planes : GR, R, B, GB */ +#define NUM_PLANES 4 + +/* ToDo: Move this to testsetup */ +#define MAX_FRAME_SIMDWIDTH 30 + +/* 3 lines state per color plane input_line_state */ +#define DPC2_STATE_INPUT_BUFFER_HEIGHT (3 * NUM_PLANES) +/* Each plane has width equal to half frame line */ +#define DPC2_STATE_INPUT_BUFFER_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* 1 line state per color plane for local deviation state*/ +#define DPC2_STATE_LOCAL_DEVIATION_BUFFER_HEIGHT (1 * NUM_PLANES) +/* Each plane has width equal to half frame line */ +#define DPC2_STATE_LOCAL_DEVIATION_BUFFER_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* MINMAX state buffer stores 1 full input line (GR-R color line) */ +#define DPC2_STATE_SECOND_MINMAX_BUFFER_HEIGHT 1 +#define DPC2_STATE_SECOND_MINMAX_BUFFER_WIDTH MAX_FRAME_SIMDWIDTH + + +struct ia_css_isp_dpc2_params { + int32_t metric1; + int32_t metric2; + int32_t metric3; + int32_t wb_gain_gr; + int32_t wb_gain_r; + int32_t wb_gain_b; + int32_t wb_gain_gb; +}; + +#endif /* __IA_CSS_DPC2_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2_state.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2_state.h new file mode 100644 index 0000000000000000000000000000000000000000..cbf1e81e83a6f323b748eae0b5ac100c7d561176 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2_state.h @@ -0,0 +1,30 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DPC2_STATE_H +#define __IA_CSS_DPC2_STATE_H + +#include "type_support.h" +#include "vmem.h" /* for VMEM_ARRAY*/ + +#include "ia_css_dpc2_param.h" + +struct sh_css_isp_dpc2_vmem_state { + VMEM_ARRAY(dpc2_input_lines[DPC2_STATE_INPUT_BUFFER_HEIGHT], DPC2_STATE_INPUT_BUFFER_WIDTH*ISP_NWAY); + VMEM_ARRAY(dpc2_local_deviations[DPC2_STATE_LOCAL_DEVIATION_BUFFER_HEIGHT], DPC2_STATE_LOCAL_DEVIATION_BUFFER_WIDTH*ISP_NWAY); + VMEM_ARRAY(dpc2_second_min[DPC2_STATE_SECOND_MINMAX_BUFFER_HEIGHT], DPC2_STATE_SECOND_MINMAX_BUFFER_WIDTH*ISP_NWAY); + VMEM_ARRAY(dpc2_second_max[DPC2_STATE_SECOND_MINMAX_BUFFER_HEIGHT], DPC2_STATE_SECOND_MINMAX_BUFFER_WIDTH*ISP_NWAY); +}; + +#endif /* __IA_CSS_DPC2_STATE_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2_types.h new file mode 100644 index 0000000000000000000000000000000000000000..b2c974196ce8201324a434141668941866bdcdfb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dpc2/ia_css_dpc2_types.h @@ -0,0 +1,59 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DPC2_TYPES_H +#define __IA_CSS_DPC2_TYPES_H + +/** @file +* CSS-API header file for Defect Pixel Correction 2 (DPC2) parameters. +*/ + +#include "type_support.h" + +/**@{*/ +/** Floating point constants for different metrics. */ +#define METRIC1_ONE_FP (1<<12) +#define METRIC2_ONE_FP (1<<5) +#define METRIC3_ONE_FP (1<<12) +#define WBGAIN_ONE_FP (1<<9) +/**@}*/ + +/**@{*/ +/** Defect Pixel Correction 2 configuration. + * + * \brief DPC2 public parameters. + * \details Struct with all parameters for the Defect Pixel Correction 2 + * kernel that can be set from the CSS API. + * + * ISP block: DPC1 (DPC after WB) + * DPC2 (DPC before WB) + * ISP1: DPC1 is used. + * ISP2: DPC2 is used. + * + */ +struct ia_css_dpc2_config { + /**@{*/ + int32_t metric1; + int32_t metric2; + int32_t metric3; + int32_t wb_gain_gr; + int32_t wb_gain_r; + int32_t wb_gain_b; + int32_t wb_gain_gb; + /**@}*/ +}; +/**@}*/ + +#endif /* __IA_CSS_DPC2_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.c new file mode 100644 index 0000000000000000000000000000000000000000..955adc4d6ab09c88d75d061b46896d15ba008be3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.c @@ -0,0 +1,306 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_frame_public.h" +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" + +#include "ia_css_types.h" +#include "ia_css_host_data.h" +#include "sh_css_param_dvs.h" +#include "sh_css_params.h" +#include "ia_css_binary.h" +#include "ia_css_debug.h" +#include "memory_access.h" +#include "assert_support.h" + +#include "ia_css_dvs.host.h" + +static const struct ia_css_dvs_configuration default_config = { + .info = (struct ia_css_frame_info *)NULL, +}; + +void +ia_css_dvs_config( + struct sh_css_isp_dvs_isp_config *to, + const struct ia_css_dvs_configuration *from, + unsigned size) +{ + (void)size; + to->num_horizontal_blocks = + DVS_NUM_BLOCKS_X(from->info->res.width); + to->num_vertical_blocks = + DVS_NUM_BLOCKS_Y(from->info->res.height); +} + +void +ia_css_dvs_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame_info *info) +{ + struct ia_css_dvs_configuration config = default_config; + + config.info = info; + + ia_css_configure_dvs(binary, &config); +} + +static void +convert_coords_to_ispparams( + struct ia_css_host_data *gdc_warp_table, + const struct ia_css_dvs_6axis_config *config, + unsigned int i_stride, + unsigned int o_width, + unsigned int o_height, + unsigned int uv_flag) +{ + unsigned int i, j; +#ifndef ISP2401 + /* Coverity CID 298073 - initialize */ +#endif + gdc_warp_param_mem_t s = { 0 }; + unsigned int x00, x01, x10, x11, + y00, y01, y10, y11; + + unsigned int xmin, ymin, xmax, ymax; + unsigned int topleft_x, topleft_y, bottom_x, bottom_y, + topleft_x_frac, topleft_y_frac; + unsigned int dvs_interp_envelope = (DVS_GDC_INTERP_METHOD == HRT_GDC_BLI_MODE ? + DVS_GDC_BLI_INTERP_ENVELOPE : DVS_GDC_BCI_INTERP_ENVELOPE); + + /* number of blocks per height and width */ + unsigned int num_blocks_y = (uv_flag ? DVS_NUM_BLOCKS_Y_CHROMA(o_height) : DVS_NUM_BLOCKS_Y(o_height) ); + unsigned int num_blocks_x = (uv_flag ? DVS_NUM_BLOCKS_X_CHROMA(o_width) : DVS_NUM_BLOCKS_X(o_width) ); // round num_x up to blockdim_x, if it concerns the Y0Y1 block (uv_flag==0) round up to even + + + unsigned int in_stride = i_stride * DVS_INPUT_BYTES_PER_PIXEL; + unsigned width, height; + unsigned int *xbuff = NULL; + unsigned int *ybuff = NULL; + struct gdc_warp_param_mem_s *ptr; + + assert(config != NULL); + assert(gdc_warp_table != NULL); + assert(gdc_warp_table->address != NULL); + + ptr = (struct gdc_warp_param_mem_s *)gdc_warp_table->address; + + ptr += (2 * uv_flag); /* format is Y0 Y1 UV, so UV starts at 3rd position */ + + if(uv_flag == 0) + { + xbuff = config->xcoords_y; + ybuff = config->ycoords_y; + width = config->width_y; + height = config->height_y; + } + else + { + xbuff = config->xcoords_uv; + ybuff = config->ycoords_uv; + width = config->width_uv; + height = config->height_uv; + } + + IA_CSS_LOG("blockdim_x %d blockdim_y %d", + DVS_BLOCKDIM_X, DVS_BLOCKDIM_Y_LUMA >> uv_flag); + IA_CSS_LOG("num_blocks_x %d num_blocks_y %d", num_blocks_x,num_blocks_y); + IA_CSS_LOG("width %d height %d", width, height); + + assert(width == num_blocks_x + 1); // the width and height of the provided morphing table should be 1 more than the number of blocks + assert(height == num_blocks_y + 1); + + for (j = 0; j < num_blocks_y; j++) { + for (i = 0; i < num_blocks_x; i++) { + + x00 = xbuff[j * width + i]; + x01 = xbuff[j * width + (i+1)]; + x10 = xbuff[(j+1) * width + i]; + x11 = xbuff[(j+1) * width + (i+1)]; + + y00 = ybuff[j * width + i]; + y01 = ybuff[j * width + (i+1)]; + y10 = ybuff[(j+1) * width + i]; + y11 = ybuff[(j+1) * width + (i+1)]; + + xmin = min(x00, x10); + xmax = max(x01, x11); + ymin = min(y00, y01); + ymax = max(y10, y11); + + /* Assert that right column's X is greater */ + assert ( x01 >= xmin); + assert ( x11 >= xmin); + /* Assert that bottom row's Y is greater */ + assert ( y10 >= ymin); + assert ( y11 >= ymin); + + topleft_y = ymin >> DVS_COORD_FRAC_BITS; + topleft_x = ((xmin >> DVS_COORD_FRAC_BITS) + >> XMEM_ALIGN_LOG2) + << (XMEM_ALIGN_LOG2); + s.in_addr_offset = topleft_y * in_stride + topleft_x; + + /* similar to topleft_y calculation, but round up if ymax + * has any fraction bits */ + bottom_y = CEIL_DIV(ymax, 1 << DVS_COORD_FRAC_BITS); + s.in_block_height = bottom_y - topleft_y + dvs_interp_envelope; + + bottom_x = CEIL_DIV(xmax, 1 << DVS_COORD_FRAC_BITS); + s.in_block_width = bottom_x - topleft_x + dvs_interp_envelope; + + topleft_x_frac = topleft_x << (DVS_COORD_FRAC_BITS); + topleft_y_frac = topleft_y << (DVS_COORD_FRAC_BITS); + + s.p0_x = x00 - topleft_x_frac; + s.p1_x = x01 - topleft_x_frac; + s.p2_x = x10 - topleft_x_frac; + s.p3_x = x11 - topleft_x_frac; + + s.p0_y = y00 - topleft_y_frac; + s.p1_y = y01 - topleft_y_frac; + s.p2_y = y10 - topleft_y_frac; + s.p3_y = y11 - topleft_y_frac; + + // block should fit within the boundingbox. + assert(s.p0_x < (s.in_block_width << DVS_COORD_FRAC_BITS)); + assert(s.p1_x < (s.in_block_width << DVS_COORD_FRAC_BITS)); + assert(s.p2_x < (s.in_block_width << DVS_COORD_FRAC_BITS)); + assert(s.p3_x < (s.in_block_width << DVS_COORD_FRAC_BITS)); + assert(s.p0_y < (s.in_block_height << DVS_COORD_FRAC_BITS)); + assert(s.p1_y < (s.in_block_height << DVS_COORD_FRAC_BITS)); + assert(s.p2_y < (s.in_block_height << DVS_COORD_FRAC_BITS)); + assert(s.p3_y < (s.in_block_height << DVS_COORD_FRAC_BITS)); + + // block size should be greater than zero. + assert(s.p0_x < s.p1_x); + assert(s.p2_x < s.p3_x); + assert(s.p0_y < s.p2_y); + assert(s.p1_y < s.p3_y); + +#if 0 + printf("j: %d\ti:%d\n", j, i); + printf("offset: %d\n", s.in_addr_offset); + printf("p0_x: %d\n", s.p0_x); + printf("p0_y: %d\n", s.p0_y); + printf("p1_x: %d\n", s.p1_x); + printf("p1_y: %d\n", s.p1_y); + printf("p2_x: %d\n", s.p2_x); + printf("p2_y: %d\n", s.p2_y); + printf("p3_x: %d\n", s.p3_x); + printf("p3_y: %d\n", s.p3_y); + + printf("p0_x_nofrac[0]: %d\n", s.p0_x>>DVS_COORD_FRAC_BITS); + printf("p0_y_nofrac[1]: %d\n", s.p0_y>>DVS_COORD_FRAC_BITS); + printf("p1_x_nofrac[2]: %d\n", s.p1_x>>DVS_COORD_FRAC_BITS); + printf("p1_y_nofrac[3]: %d\n", s.p1_y>>DVS_COORD_FRAC_BITS); + printf("p2_x_nofrac[0]: %d\n", s.p2_x>>DVS_COORD_FRAC_BITS); + printf("p2_y_nofrac[1]: %d\n", s.p2_y>>DVS_COORD_FRAC_BITS); + printf("p3_x_nofrac[2]: %d\n", s.p3_x>>DVS_COORD_FRAC_BITS); + printf("p3_y_nofrac[3]: %d\n", s.p3_y>>DVS_COORD_FRAC_BITS); + printf("\n"); +#endif + + *ptr = s; + + // storage format: + // Y0 Y1 UV0 Y2 Y3 UV1 + /* if uv_flag equals true increment with 2 incase x is odd, this to + skip the uv position. */ + if (uv_flag) + ptr += 3; + else + ptr += (1 + (i&1)); + } + } +} + +struct ia_css_host_data * +convert_allocate_dvs_6axis_config( + const struct ia_css_dvs_6axis_config *dvs_6axis_config, + const struct ia_css_binary *binary, + const struct ia_css_frame_info *dvs_in_frame_info) +{ + unsigned int i_stride; + unsigned int o_width; + unsigned int o_height; + struct ia_css_host_data *me; + struct gdc_warp_param_mem_s *isp_data_ptr; + + assert(binary != NULL); + assert(dvs_6axis_config != NULL); + assert(dvs_in_frame_info != NULL); + + me = ia_css_host_data_allocate((size_t)((DVS_6AXIS_BYTES(binary) / 2) * 3)); + + if (!me) + return NULL; + + /*DVS only supports input frame of YUV420 or NV12. Fail for all other cases*/ + assert((dvs_in_frame_info->format == IA_CSS_FRAME_FORMAT_NV12) + || (dvs_in_frame_info->format == IA_CSS_FRAME_FORMAT_YUV420)); + + isp_data_ptr = (struct gdc_warp_param_mem_s *)me->address; + + i_stride = dvs_in_frame_info->padded_width; + + o_width = binary->out_frame_info[0].res.width; + o_height = binary->out_frame_info[0].res.height; + + /* Y plane */ + convert_coords_to_ispparams(me, dvs_6axis_config, + i_stride, o_width, o_height, 0); + + if (dvs_in_frame_info->format == IA_CSS_FRAME_FORMAT_YUV420) { + /*YUV420 has half the stride for U/V plane*/ + i_stride /=2; + } + + /* UV plane (packed inside the y plane) */ + convert_coords_to_ispparams(me, dvs_6axis_config, + i_stride, o_width/2, o_height/2, 1); + + return me; +} + +enum ia_css_err +store_dvs_6axis_config( + const struct ia_css_dvs_6axis_config *dvs_6axis_config, + const struct ia_css_binary *binary, + const struct ia_css_frame_info *dvs_in_frame_info, + hrt_vaddress ddr_addr_y) +{ + + struct ia_css_host_data *me; + assert(dvs_6axis_config != NULL); + assert(ddr_addr_y != mmgr_NULL); + assert(dvs_in_frame_info != NULL); + + me = convert_allocate_dvs_6axis_config(dvs_6axis_config, + binary, + dvs_in_frame_info); + + if (!me) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY); + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + } + + ia_css_params_store_ia_css_host_data( + ddr_addr_y, + me); + ia_css_host_data_free(me); + + return IA_CSS_SUCCESS; +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.h new file mode 100644 index 0000000000000000000000000000000000000000..2f513e29d88c98d1c7f455f448c8d99acb2489e3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.h @@ -0,0 +1,60 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DVS_HOST_H +#define __IA_CSS_DVS_HOST_H + +#include "ia_css_frame_public.h" +#include "ia_css_binary.h" +#include "sh_css_params.h" + +#include "ia_css_types.h" +#include "ia_css_dvs_types.h" +#include "ia_css_dvs_param.h" + +/* For bilinear interpolation, we need to add +1 to input block height calculation. + * For bicubic interpolation, we will need to add +3 instaed */ +#define DVS_GDC_BLI_INTERP_ENVELOPE 1 +#define DVS_GDC_BCI_INTERP_ENVELOPE 3 + +void +ia_css_dvs_config( + struct sh_css_isp_dvs_isp_config *to, + const struct ia_css_dvs_configuration *from, + unsigned size); + +void +ia_css_dvs_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame_info *from); + +void +convert_dvs_6axis_config( + struct ia_css_isp_parameters *params, + const struct ia_css_binary *binary); + +struct ia_css_host_data * +convert_allocate_dvs_6axis_config( + const struct ia_css_dvs_6axis_config *dvs_6axis_config, + const struct ia_css_binary *binary, + const struct ia_css_frame_info *dvs_in_frame_info); + +enum ia_css_err +store_dvs_6axis_config( + const struct ia_css_dvs_6axis_config *dvs_6axis_config, + const struct ia_css_binary *binary, + const struct ia_css_frame_info *dvs_in_frame_info, + hrt_vaddress ddr_addr_y); + +#endif /* __IA_CSS_DVS_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dvs/dvs_1.0/ia_css_dvs_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dvs/dvs_1.0/ia_css_dvs_param.h new file mode 100644 index 0000000000000000000000000000000000000000..4d0abfe4d0fd2c2ba4d048208a37dd79a77f30be --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dvs/dvs_1.0/ia_css_dvs_param.h @@ -0,0 +1,39 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DVS_PARAM_H +#define __IA_CSS_DVS_PARAM_H + +#include +#ifdef ISP2401 + +#if !defined(ENABLE_TPROXY) && !defined(ENABLE_CRUN_FOR_TD) && !defined(PARAMBIN_GENERATION) +#endif +#include "dma.h" +#ifdef ISP2401 +#endif /* !defined(ENABLE_TPROXY) && !defined(ENABLE_CRUN_FOR_TD) */ + +#endif +#include "uds/uds_1.0/ia_css_uds_param.h" + +#ifdef ISP2401 + +#endif +/** dvserence frame */ +struct sh_css_isp_dvs_isp_config { + uint32_t num_horizontal_blocks; + uint32_t num_vertical_blocks; +}; + +#endif /* __IA_CSS_DVS_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dvs/dvs_1.0/ia_css_dvs_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dvs/dvs_1.0/ia_css_dvs_types.h new file mode 100644 index 0000000000000000000000000000000000000000..216c54a21ea59d3b3683eaa196fb3e966bac7574 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/dvs/dvs_1.0/ia_css_dvs_types.h @@ -0,0 +1,30 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_DVS_TYPES_H +#define __IA_CSS_DVS_TYPES_H + +/** DVS frame + * + * ISP block: dvs frame + */ + +#include "ia_css_frame_public.h" + +struct ia_css_dvs_configuration { + const struct ia_css_frame_info *info; +}; + +#endif /* __IA_CSS_DVS_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8.host.c new file mode 100644 index 0000000000000000000000000000000000000000..682f8b709ff94881d69f71cdbb652100ec7949a9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8.host.c @@ -0,0 +1,321 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" +#endif + +#include "type_support.h" +#include "assert_support.h" +#include "math_support.h" /* for min and max */ + +#include "ia_css_eed1_8.host.h" + +/* WARNING1: Number of inv points should be less or equal to 16, + * due to implementation limitation. See kernel design document + * for more details. + * WARNING2: Do not modify the number of inv points without correcting + * the EED1_8 kernel implementation assumptions. + */ +#define NUMBER_OF_CHGRINV_POINTS 15 +#define NUMBER_OF_TCINV_POINTS 9 +#define NUMBER_OF_FCINV_POINTS 9 + +const int16_t chgrinv_x[NUMBER_OF_CHGRINV_POINTS] = { +0, 16, 64, 144, 272, 448, 672, 976, +1376, 1888, 2528, 3312, 4256, 5376, 6688}; + +const int16_t chgrinv_a[NUMBER_OF_CHGRINV_POINTS] = { +-7171, -256, -29, -3456, -1071, -475, -189, -102, +-48, -38, -10, -9, -7, -6, 0}; + +const int16_t chgrinv_b[NUMBER_OF_CHGRINV_POINTS] = { +8191, 1021, 256, 114, 60, 37, 24, 17, +12, 9, 6, 5, 4, 3, 2}; + +const int16_t chgrinv_c[NUMBER_OF_CHGRINV_POINTS] = { +1, 1, 1, 0, 0, 0, 0, 0, +0, 0, 0, 0, 0, 0, 0}; + +const int16_t tcinv_x[NUMBER_OF_TCINV_POINTS] = { +0, 4, 11, 23, 42, 68, 102, 148, 205}; + +const int16_t tcinv_a[NUMBER_OF_TCINV_POINTS] = { +-6364, -631, -126, -34, -13, -6, -4452, -2156, 0}; + +const int16_t tcinv_b[NUMBER_OF_TCINV_POINTS] = { +8191, 1828, 726, 352, 197, 121, 80, 55, 40}; + +const int16_t tcinv_c[NUMBER_OF_TCINV_POINTS] = { +1, 1, 1, 1, 1, 1, 0, 0, 0}; + +const int16_t fcinv_x[NUMBER_OF_FCINV_POINTS] = { +0, 80, 216, 456, 824, 1344, 2040, 2952, 4096}; + +const int16_t fcinv_a[NUMBER_OF_FCINV_POINTS] = { +-5244, -486, -86, -2849, -961, -400, -180, -86, 0}; + +const int16_t fcinv_b[NUMBER_OF_FCINV_POINTS] = { +8191, 1637, 607, 287, 159, 98, 64, 44, 32}; + +const int16_t fcinv_c[NUMBER_OF_FCINV_POINTS] = { +1, 1, 1, 0, 0, 0, 0, 0, 0}; + + +void +ia_css_eed1_8_vmem_encode( + struct eed1_8_vmem_params *to, + const struct ia_css_eed1_8_config *from, + size_t size) +{ + unsigned i, j, base; + const unsigned total_blocks = 4; + const unsigned shuffle_block = 16; + + (void)size; + + /* Init */ + for (i = 0; i < ISP_VEC_NELEMS; i++) { + to->e_dew_enh_x[0][i] = 0; + to->e_dew_enh_y[0][i] = 0; + to->e_dew_enh_a[0][i] = 0; + to->e_dew_enh_f[0][i] = 0; + to->chgrinv_x[0][i] = 0; + to->chgrinv_a[0][i] = 0; + to->chgrinv_b[0][i] = 0; + to->chgrinv_c[0][i] = 0; + to->tcinv_x[0][i] = 0; + to->tcinv_a[0][i] = 0; + to->tcinv_b[0][i] = 0; + to->tcinv_c[0][i] = 0; + to->fcinv_x[0][i] = 0; + to->fcinv_a[0][i] = 0; + to->fcinv_b[0][i] = 0; + to->fcinv_c[0][i] = 0; + } + + /* Constraints on dew_enhance_seg_x and dew_enhance_seg_y: + * - values should be greater or equal to 0. + * - values should be ascending. + * - value of index zero is equal to 0. + */ + + /* Checking constraints: */ + /* TODO: investigate if an assert is the right way to report that + * the constraints are violated. + */ + for (j = 0; j < IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS; j++) { + assert(from->dew_enhance_seg_x[j] > -1); + assert(from->dew_enhance_seg_y[j] > -1); + } + + for (j = 1; j < IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS; j++) { + assert(from->dew_enhance_seg_x[j] > from->dew_enhance_seg_x[j-1]); + assert(from->dew_enhance_seg_y[j] > from->dew_enhance_seg_y[j-1]); + } + + assert(from->dew_enhance_seg_x[0] == 0); + assert(from->dew_enhance_seg_y[0] == 0); + + /* Constraints on chgrinv_x, tcinv_x and fcinv_x: + * - values should be greater or equal to 0. + * - values should be ascending. + * - value of index zero is equal to 0. + */ + assert(chgrinv_x[0] == 0); + assert(tcinv_x[0] == 0); + assert(fcinv_x[0] == 0); + + for (j = 1; j < NUMBER_OF_CHGRINV_POINTS; j++) { + assert(chgrinv_x[j] > chgrinv_x[j-1]); + } + + for (j = 1; j < NUMBER_OF_TCINV_POINTS; j++) { + assert(tcinv_x[j] > tcinv_x[j-1]); + } + + for (j = 1; j < NUMBER_OF_FCINV_POINTS; j++) { + assert(fcinv_x[j] > fcinv_x[j-1]); + } + + /* The implementation of the calulating 1/x is based on the availability + * of the OP_vec_shuffle16 operation. + * A 64 element vector is split up in 4 blocks of 16 element. Each array is copied to + * a vector 4 times, (starting at 0, 16, 32 and 48). All array elements are copied or + * initialised as described in the KFS. The remaining elements of a vector are set to 0. + */ + /* TODO: guard this code with above assumptions */ + for(i = 0; i < total_blocks; i++) { + base = shuffle_block * i; + + for (j = 0; j < IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS; j++) { + to->e_dew_enh_x[0][base + j] = min(max(from->dew_enhance_seg_x[j], 0), 8191); + to->e_dew_enh_y[0][base + j] = min(max(from->dew_enhance_seg_y[j], -8192), 8191); + } + + for (j = 0; j < (IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1); j++) { + to->e_dew_enh_a[0][base + j] = min(max(from->dew_enhance_seg_slope[j], -8192), 8191); + /* Convert dew_enhance_seg_exp to flag: + * 0 -> 0 + * 1...13 -> 1 + */ + to->e_dew_enh_f[0][base + j] = (min(max(from->dew_enhance_seg_exp[j], 0), 13) > 0); + } + + /* Hard-coded to 0, in order to be able to handle out of + * range input in the same way as the other segments. + * See KFS for more details. + */ + to->e_dew_enh_a[0][base + (IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1)] = 0; + to->e_dew_enh_f[0][base + (IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1)] = 0; + + for (j = 0; j < NUMBER_OF_CHGRINV_POINTS; j++) { + to->chgrinv_x[0][base + j] = chgrinv_x[j]; + to->chgrinv_a[0][base + j] = chgrinv_a[j]; + to->chgrinv_b[0][base + j] = chgrinv_b[j]; + to->chgrinv_c[0][base + j] = chgrinv_c[j]; + } + + for (j = 0; j < NUMBER_OF_TCINV_POINTS; j++) { + to->tcinv_x[0][base + j] = tcinv_x[j]; + to->tcinv_a[0][base + j] = tcinv_a[j]; + to->tcinv_b[0][base + j] = tcinv_b[j]; + to->tcinv_c[0][base + j] = tcinv_c[j]; + } + + for (j = 0; j < NUMBER_OF_FCINV_POINTS; j++) { + to->fcinv_x[0][base + j] = fcinv_x[j]; + to->fcinv_a[0][base + j] = fcinv_a[j]; + to->fcinv_b[0][base + j] = fcinv_b[j]; + to->fcinv_c[0][base + j] = fcinv_c[j]; + } + } +} + + +void +ia_css_eed1_8_encode( + struct eed1_8_dmem_params *to, + const struct ia_css_eed1_8_config *from, + size_t size) +{ + int i; + int min_exp = 0; + + (void)size; + + to->rbzp_strength = from->rbzp_strength; + + to->fcstrength = from->fcstrength; + to->fcthres_0 = from->fcthres_0; + to->fc_sat_coef = from->fc_sat_coef; + to->fc_coring_prm = from->fc_coring_prm; + to->fc_slope = from->fcthres_1 - from->fcthres_0; + + to->aerel_thres0 = from->aerel_thres0; + to->aerel_gain0 = from->aerel_gain0; + to->aerel_thres_diff = from->aerel_thres1 - from->aerel_thres0; + to->aerel_gain_diff = from->aerel_gain1 - from->aerel_gain0; + + to->derel_thres0 = from->derel_thres0; + to->derel_gain0 = from->derel_gain0; + to->derel_thres_diff = (from->derel_thres1 - from->derel_thres0); + to->derel_gain_diff = (from->derel_gain1 - from->derel_gain0); + + to->coring_pos0 = from->coring_pos0; + to->coring_pos_diff = (from->coring_pos1 - from->coring_pos0); + to->coring_neg0 = from->coring_neg0; + to->coring_neg_diff = (from->coring_neg1 - from->coring_neg0); + + /* Note: (ISP_VEC_ELEMBITS -1) + * TODO: currently the testbench does not support to use + * ISP_VEC_ELEMBITS. Investigate how to fix this + */ + to->gain_exp = (13 - from->gain_exp); + to->gain_pos0 = from->gain_pos0; + to->gain_pos_diff = (from->gain_pos1 - from->gain_pos0); + to->gain_neg0 = from->gain_neg0; + to->gain_neg_diff = (from->gain_neg1 - from->gain_neg0); + + to->margin_pos0 = from->pos_margin0; + to->margin_pos_diff = (from->pos_margin1 - from->pos_margin0); + to->margin_neg0 = from->neg_margin0; + to->margin_neg_diff = (from->neg_margin1 - from->neg_margin0); + + /* Encode DEWEnhance exp (e_dew_enh_asr) */ + for (i = 0; i < (IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1); i++) { + min_exp = max(min_exp, from->dew_enhance_seg_exp[i]); + } + to->e_dew_enh_asr = 13 - min(max(min_exp, 0), 13); + + to->dedgew_max = from->dedgew_max; +} + + +void +ia_css_init_eed1_8_state( + void *state, + size_t size) +{ + memset(state, 0, size); +} + + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_eed1_8_debug_dtrace( + const struct ia_css_eed1_8_config *eed, + unsigned level) +{ + if (!eed) + return; + + ia_css_debug_dtrace(level, "Edge Enhancing Demosaic 1.8:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "rbzp_strength", eed->rbzp_strength); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "fcstrength", eed->fcstrength); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "fcthres_0", eed->fcthres_0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "fcthres_1", eed->fcthres_1); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "fc_sat_coef", eed->fc_sat_coef); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "fc_coring_prm", eed->fc_coring_prm); + + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "aerel_thres0", eed->aerel_thres0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "aerel_gain0", eed->aerel_gain0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "aerel_thres1", eed->aerel_thres1); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "aerel_gain1", eed->aerel_gain1); + + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "derel_thres0", eed->derel_thres0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "derel_gain0", eed->derel_gain0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "derel_thres1", eed->derel_thres1); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "derel_gain1", eed->derel_gain1); + + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "coring_pos0", eed->coring_pos0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "coring_pos1", eed->coring_pos1); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "coring_neg0", eed->coring_neg0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "coring_neg1", eed->coring_neg1); + + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "gain_exp", eed->gain_exp); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "gain_pos0", eed->gain_pos0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "gain_pos1", eed->gain_pos1); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "gain_neg0", eed->gain_neg0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "gain_neg1", eed->gain_neg1); + + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "pos_margin0", eed->pos_margin0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "pos_margin1", eed->pos_margin1); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "neg_margin0", eed->neg_margin0); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "neg_margin1", eed->neg_margin1); + + ia_css_debug_dtrace(level, "\t%-32s = %d\n", "dedgew_max", eed->dedgew_max); +} +#endif + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8.host.h new file mode 100644 index 0000000000000000000000000000000000000000..355ff13273b0465196b22417777b24b77060dd93 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8.host.h @@ -0,0 +1,46 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_EED1_8_HOST_H +#define __IA_CSS_EED1_8_HOST_H + +#include "ia_css_eed1_8_types.h" +#include "ia_css_eed1_8_param.h" +#include "ia_css_eed1_8_default.host.h" + +void +ia_css_eed1_8_vmem_encode( + struct eed1_8_vmem_params *to, + const struct ia_css_eed1_8_config *from, + size_t size); + +void +ia_css_eed1_8_encode( + struct eed1_8_dmem_params *to, + const struct ia_css_eed1_8_config *from, + size_t size); + +void +ia_css_init_eed1_8_state( + void *state, + size_t size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_eed1_8_debug_dtrace( + const struct ia_css_eed1_8_config *config, + unsigned level); +#endif + +#endif /* __IA_CSS_EED1_8_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8_default.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8_default.host.c new file mode 100644 index 0000000000000000000000000000000000000000..3622719dafa5e65715c3d3c2cca1a803eb0f6a14 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8_default.host.c @@ -0,0 +1,94 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_eed1_8_types.h" + +/* The default values for the kernel parameters are based on + * ISP261 CSS API public parameter list_all.xlsx from 12-09-2014 + * The parameter list is available on the ISP261 sharepoint + */ + +/* Default kernel parameters. */ +const struct ia_css_eed1_8_config default_eed1_8_config = { + .rbzp_strength = 5489, + .fcstrength = 6554, + .fcthres_0 = 0, + .fcthres_1 = 0, + .fc_sat_coef = 8191, + .fc_coring_prm = 128, + .aerel_thres0 = 0, + .aerel_gain0 = 8191, + .aerel_thres1 = 16, + .aerel_gain1 = 20, + .derel_thres0 = 1229, + .derel_gain0 = 1, + .derel_thres1 = 819, + .derel_gain1 = 1, + .coring_pos0 = 0, + .coring_pos1 = 0, + .coring_neg0 = 0, + .coring_neg1 = 0, + .gain_exp = 2, + .gain_pos0 = 6144, + .gain_pos1 = 2048, + .gain_neg0 = 2048, + .gain_neg1 = 6144, + .pos_margin0 = 1475, + .pos_margin1 = 1475, + .neg_margin0 = 1475, + .neg_margin1 = 1475, + .dew_enhance_seg_x = { + 0, + 64, + 272, + 688, + 1376, + 2400, + 3840, + 5744, + 8191 + }, + .dew_enhance_seg_y = { + 0, + 144, + 480, + 1040, + 1852, + 2945, + 4357, + 6094, + 8191 + }, + .dew_enhance_seg_slope = { + 4608, + 3308, + 2757, + 2417, + 2186, + 8033, + 7473, + 7020 + }, + .dew_enhance_seg_exp = { + 2, + 2, + 2, + 2, + 2, + 0, + 0, + 0 + }, + .dedgew_max = 6144 +}; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8_default.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8_default.host.h new file mode 100644 index 0000000000000000000000000000000000000000..782f739ca8b577302b88e9e96719a238c8949dad --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8_default.host.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_EED1_8_DEFAULT_HOST_H +#define __IA_CSS_EED1_8_DEFAULT_HOST_H + +#include "ia_css_eed1_8_types.h" + +extern const struct ia_css_eed1_8_config default_eed1_8_config; + +#endif /* __IA_CSS_EED1_8_DEFAULT_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8_param.h new file mode 100644 index 0000000000000000000000000000000000000000..bc3a07fd07ebb02887b34a9e309a7b49bd041d83 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8_param.h @@ -0,0 +1,154 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_EED1_8_PARAM_H +#define __IA_CSS_EED1_8_PARAM_H + +#include "type_support.h" +#include "vmem.h" /* needed for VMEM_ARRAY */ + +#include "ia_css_eed1_8_types.h" /* IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS */ + + +/* Configuration parameters: */ + +/* Enable median for false color correction + * 0: Do not use median + * 1: Use median + * Default: 1 + */ +#define EED1_8_FC_ENABLE_MEDIAN 1 + +/* Coring Threshold minima + * Used in Tint color suppression. + * Default: 1 + */ +#define EED1_8_CORINGTHMIN 1 + +/* Define size of the state..... TODO: check if this is the correct place */ +/* 4 planes : GR, R, B, GB */ +#define NUM_PLANES 4 + +/* 5 lines state per color plane input_line_state */ +#define EED1_8_STATE_INPUT_BUFFER_HEIGHT (5 * NUM_PLANES) + +/* Each plane has width equal to half frame line */ +#define EED1_8_STATE_INPUT_BUFFER_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* 1 line state per color plane LD_H state */ +#define EED1_8_STATE_LD_H_HEIGHT (1 * NUM_PLANES) +#define EED1_8_STATE_LD_H_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* 1 line state per color plane LD_V state */ +#define EED1_8_STATE_LD_V_HEIGHT (1 * NUM_PLANES) +#define EED1_8_STATE_LD_V_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* 1 line (single plane) state for D_Hr state */ +#define EED1_8_STATE_D_HR_HEIGHT 1 +#define EED1_8_STATE_D_HR_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* 1 line (single plane) state for D_Hb state */ +#define EED1_8_STATE_D_HB_HEIGHT 1 +#define EED1_8_STATE_D_HB_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* 2 lines (single plane) state for D_Vr state */ +#define EED1_8_STATE_D_VR_HEIGHT 2 +#define EED1_8_STATE_D_VR_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* 2 line (single plane) state for D_Vb state */ +#define EED1_8_STATE_D_VB_HEIGHT 2 +#define EED1_8_STATE_D_VB_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* 2 lines state for R and B (= 2 planes) rb_zipped_state */ +#define EED1_8_STATE_RB_ZIPPED_HEIGHT (2 * 2) +#define EED1_8_STATE_RB_ZIPPED_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +#if EED1_8_FC_ENABLE_MEDIAN +/* 1 full input line (GR-R color line) for Yc state */ +#define EED1_8_STATE_YC_HEIGHT 1 +#define EED1_8_STATE_YC_WIDTH MAX_FRAME_SIMDWIDTH + +/* 1 line state per color plane Cg_state */ +#define EED1_8_STATE_CG_HEIGHT (1 * NUM_PLANES) +#define EED1_8_STATE_CG_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* 1 line state per color plane Co_state */ +#define EED1_8_STATE_CO_HEIGHT (1 * NUM_PLANES) +#define EED1_8_STATE_CO_WIDTH CEIL_DIV(MAX_FRAME_SIMDWIDTH, 2) + +/* 1 full input line (GR-R color line) for AbsK state */ +#define EED1_8_STATE_ABSK_HEIGHT 1 +#define EED1_8_STATE_ABSK_WIDTH MAX_FRAME_SIMDWIDTH +#endif + +struct eed1_8_vmem_params { + VMEM_ARRAY(e_dew_enh_x, ISP_VEC_NELEMS); + VMEM_ARRAY(e_dew_enh_y, ISP_VEC_NELEMS); + VMEM_ARRAY(e_dew_enh_a, ISP_VEC_NELEMS); + VMEM_ARRAY(e_dew_enh_f, ISP_VEC_NELEMS); + VMEM_ARRAY(chgrinv_x, ISP_VEC_NELEMS); + VMEM_ARRAY(chgrinv_a, ISP_VEC_NELEMS); + VMEM_ARRAY(chgrinv_b, ISP_VEC_NELEMS); + VMEM_ARRAY(chgrinv_c, ISP_VEC_NELEMS); + VMEM_ARRAY(fcinv_x, ISP_VEC_NELEMS); + VMEM_ARRAY(fcinv_a, ISP_VEC_NELEMS); + VMEM_ARRAY(fcinv_b, ISP_VEC_NELEMS); + VMEM_ARRAY(fcinv_c, ISP_VEC_NELEMS); + VMEM_ARRAY(tcinv_x, ISP_VEC_NELEMS); + VMEM_ARRAY(tcinv_a, ISP_VEC_NELEMS); + VMEM_ARRAY(tcinv_b, ISP_VEC_NELEMS); + VMEM_ARRAY(tcinv_c, ISP_VEC_NELEMS); +}; + +/* EED (Edge Enhancing Demosaic) ISP parameters */ +struct eed1_8_dmem_params { + int32_t rbzp_strength; + + int32_t fcstrength; + int32_t fcthres_0; + int32_t fc_sat_coef; + int32_t fc_coring_prm; + int32_t fc_slope; + + int32_t aerel_thres0; + int32_t aerel_gain0; + int32_t aerel_thres_diff; + int32_t aerel_gain_diff; + + int32_t derel_thres0; + int32_t derel_gain0; + int32_t derel_thres_diff; + int32_t derel_gain_diff; + + int32_t coring_pos0; + int32_t coring_pos_diff; + int32_t coring_neg0; + int32_t coring_neg_diff; + + int32_t gain_exp; + int32_t gain_pos0; + int32_t gain_pos_diff; + int32_t gain_neg0; + int32_t gain_neg_diff; + + int32_t margin_pos0; + int32_t margin_pos_diff; + int32_t margin_neg0; + int32_t margin_neg_diff; + + int32_t e_dew_enh_asr; + int32_t dedgew_max; +}; + +#endif /* __IA_CSS_EED1_8_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8_state.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8_state.h new file mode 100644 index 0000000000000000000000000000000000000000..47e451b15044b774046aa114b0df27ac243f95d5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8_state.h @@ -0,0 +1,40 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_EED1_8_STATE_H +#define __IA_CSS_EED1_8_STATE_H + +#include "type_support.h" +#include "vmem.h" /* for VMEM_ARRAY*/ + +#include "ia_css_eed1_8_param.h" + +struct eed1_8_vmem_state { + VMEM_ARRAY(eed1_8_input_lines[EED1_8_STATE_INPUT_BUFFER_HEIGHT], EED1_8_STATE_INPUT_BUFFER_WIDTH*ISP_NWAY); + VMEM_ARRAY(eed1_8_LD_H[EED1_8_STATE_LD_H_HEIGHT], EED1_8_STATE_LD_H_WIDTH*ISP_NWAY); + VMEM_ARRAY(eed1_8_LD_V[EED1_8_STATE_LD_V_HEIGHT], EED1_8_STATE_LD_V_WIDTH*ISP_NWAY); + VMEM_ARRAY(eed1_8_D_Hr[EED1_8_STATE_D_HR_HEIGHT], EED1_8_STATE_D_HR_WIDTH*ISP_NWAY); + VMEM_ARRAY(eed1_8_D_Hb[EED1_8_STATE_D_HB_HEIGHT], EED1_8_STATE_D_HB_WIDTH*ISP_NWAY); + VMEM_ARRAY(eed1_8_D_Vr[EED1_8_STATE_D_VR_HEIGHT], EED1_8_STATE_D_VR_WIDTH*ISP_NWAY); + VMEM_ARRAY(eed1_8_D_Vb[EED1_8_STATE_D_VB_HEIGHT], EED1_8_STATE_D_VB_WIDTH*ISP_NWAY); + VMEM_ARRAY(eed1_8_rb_zipped[EED1_8_STATE_RB_ZIPPED_HEIGHT], EED1_8_STATE_RB_ZIPPED_WIDTH*ISP_NWAY); +#if EED1_8_FC_ENABLE_MEDIAN + VMEM_ARRAY(eed1_8_Yc[EED1_8_STATE_YC_HEIGHT], EED1_8_STATE_YC_WIDTH*ISP_NWAY); + VMEM_ARRAY(eed1_8_Cg[EED1_8_STATE_CG_HEIGHT], EED1_8_STATE_CG_WIDTH*ISP_NWAY); + VMEM_ARRAY(eed1_8_Co[EED1_8_STATE_CO_HEIGHT], EED1_8_STATE_CO_WIDTH*ISP_NWAY); + VMEM_ARRAY(eed1_8_AbsK[EED1_8_STATE_ABSK_HEIGHT], EED1_8_STATE_ABSK_WIDTH*ISP_NWAY); +#endif +}; + +#endif /* __IA_CSS_EED1_8_STATE_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8_types.h new file mode 100644 index 0000000000000000000000000000000000000000..07651f0ac558be7ee64dc0389f3f985b2ac71ae3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/eed1_8/ia_css_eed1_8_types.h @@ -0,0 +1,86 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_EED1_8_TYPES_H +#define __IA_CSS_EED1_8_TYPES_H + +/** @file +* CSS-API header file for Edge Enhanced Demosaic parameters. +*/ + + +#include "type_support.h" + +/** + * \brief EED1_8 public parameters. + * \details Struct with all parameters for the EED1.8 kernel that can be set + * from the CSS API. + */ + +/* parameter list is based on ISP261 CSS API public parameter list_all.xlsx from 28-01-2015 */ + +/* Number of segments + 1 segment used in edge reliability enhancement + * Ineffective: N/A + * Default: 9 + */ +#define IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS 9 + +/** Edge Enhanced Demosaic configuration + * + * ISP2.6.1: EED1_8 is used. + */ + +struct ia_css_eed1_8_config { + int32_t rbzp_strength; /**< Strength of zipper reduction. */ + + int32_t fcstrength; /**< Strength of false color reduction. */ + int32_t fcthres_0; /**< Threshold to prevent chroma coring due to noise or green disparity in dark region. */ + int32_t fcthres_1; /**< Threshold to prevent chroma coring due to noise or green disparity in bright region. */ + int32_t fc_sat_coef; /**< How much color saturation to maintain in high color saturation region. */ + int32_t fc_coring_prm; /**< Chroma coring coefficient for tint color suppression. */ + + int32_t aerel_thres0; /**< Threshold for Non-Directional Reliability at dark region. */ + int32_t aerel_gain0; /**< Gain for Non-Directional Reliability at dark region. */ + int32_t aerel_thres1; /**< Threshold for Non-Directional Reliability at bright region. */ + int32_t aerel_gain1; /**< Gain for Non-Directional Reliability at bright region. */ + + int32_t derel_thres0; /**< Threshold for Directional Reliability at dark region. */ + int32_t derel_gain0; /**< Gain for Directional Reliability at dark region. */ + int32_t derel_thres1; /**< Threshold for Directional Reliability at bright region. */ + int32_t derel_gain1; /**< Gain for Directional Reliability at bright region. */ + + int32_t coring_pos0; /**< Positive Edge Coring Threshold in dark region. */ + int32_t coring_pos1; /**< Positive Edge Coring Threshold in bright region. */ + int32_t coring_neg0; /**< Negative Edge Coring Threshold in dark region. */ + int32_t coring_neg1; /**< Negative Edge Coring Threshold in bright region. */ + + int32_t gain_exp; /**< Common Exponent of Gain. */ + int32_t gain_pos0; /**< Gain for Positive Edge in dark region. */ + int32_t gain_pos1; /**< Gain for Positive Edge in bright region. */ + int32_t gain_neg0; /**< Gain for Negative Edge in dark region. */ + int32_t gain_neg1; /**< Gain for Negative Edge in bright region. */ + + int32_t pos_margin0; /**< Margin for Positive Edge in dark region. */ + int32_t pos_margin1; /**< Margin for Positive Edge in bright region. */ + int32_t neg_margin0; /**< Margin for Negative Edge in dark region. */ + int32_t neg_margin1; /**< Margin for Negative Edge in bright region. */ + + int32_t dew_enhance_seg_x[IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS]; /**< Segment data for directional edge weight: X. */ + int32_t dew_enhance_seg_y[IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS]; /**< Segment data for directional edge weight: Y. */ + int32_t dew_enhance_seg_slope[(IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1)]; /**< Segment data for directional edge weight: Slope. */ + int32_t dew_enhance_seg_exp[(IA_CSS_NUMBER_OF_DEW_ENHANCE_SEGMENTS - 1)]; /**< Segment data for directional edge weight: Exponent. */ + int32_t dedgew_max; /**< Max Weight for Directional Edge. */ +}; + +#endif /* __IA_CSS_EED1_8_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fc/fc_1.0/ia_css_formats.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fc/fc_1.0/ia_css_formats.host.c new file mode 100644 index 0000000000000000000000000000000000000000..94631eee8614246cc393de165d2d497d1897e6bf --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fc/fc_1.0/ia_css_formats.host.c @@ -0,0 +1,62 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_formats.host.h" +#include "ia_css_types.h" +#include "sh_css_defs.h" + +/*#include "sh_css_frac.h"*/ +#ifndef IA_CSS_NO_DEBUG +/* FIXME: See BZ 4427 */ +#include "ia_css_debug.h" +#endif + +const struct ia_css_formats_config default_formats_config = { + 1 +}; + +void +ia_css_formats_encode( + struct sh_css_isp_formats_params *to, + const struct ia_css_formats_config *from, + unsigned size) +{ + (void)size; + to->video_full_range_flag = from->video_full_range_flag; +} +#ifndef IA_CSS_NO_DEBUG +/* FIXME: See BZ 4427 */ +void +ia_css_formats_dump( + const struct sh_css_isp_formats_params *formats, + unsigned level) +{ + if (!formats) return; + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "video_full_range_flag", formats->video_full_range_flag); +} +#endif + +#ifndef IA_CSS_NO_DEBUG +/* FIXME: See BZ 4427 */ +void +ia_css_formats_debug_dtrace( + const struct ia_css_formats_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.video_full_range_flag=%d\n", + config->video_full_range_flag); +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fc/fc_1.0/ia_css_formats.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fc/fc_1.0/ia_css_formats.host.h new file mode 100644 index 0000000000000000000000000000000000000000..8a90cd83b248b8cbdffb8c2d22bb14e349dd1301 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fc/fc_1.0/ia_css_formats.host.h @@ -0,0 +1,45 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FORMATS_HOST_H +#define __IA_CSS_FORMATS_HOST_H + +#include "ia_css_formats_types.h" +#include "ia_css_formats_param.h" + +extern const struct ia_css_formats_config default_formats_config; + +void +ia_css_formats_encode( + struct sh_css_isp_formats_params *to, + const struct ia_css_formats_config *from, + unsigned size); +#ifndef IA_CSS_NO_DEBUG +/* FIXME: See BZ 4427 */ +void +ia_css_formats_dump( + const struct sh_css_isp_formats_params *formats, + unsigned level); +#endif + +#ifndef IA_CSS_NO_DEBUG +/* FIXME: See BZ 4427 */ +void +ia_css_formats_debug_dtrace( + const struct ia_css_formats_config *formats, + unsigned level); +#endif /*IA_CSS_NO_DEBUG*/ + +#endif /* __IA_CSS_FORMATS_HOST_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fc/fc_1.0/ia_css_formats_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fc/fc_1.0/ia_css_formats_param.h new file mode 100644 index 0000000000000000000000000000000000000000..2eb6030b60812c9500a9ed0d4cee80491e8f5bc8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fc/fc_1.0/ia_css_formats_param.h @@ -0,0 +1,25 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FORMATS_PARAM_H +#define __IA_CSS_FORMATS_PARAM_H + +#include "type_support.h" + +/* FORMATS (Format conversion) */ +struct sh_css_isp_formats_params { + int32_t video_full_range_flag; +}; + +#endif /* __IA_CSS_FORMATS_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fc/fc_1.0/ia_css_formats_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fc/fc_1.0/ia_css_formats_types.h new file mode 100644 index 0000000000000000000000000000000000000000..df1565a5914c18886d65a581868a9635e9886c02 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fc/fc_1.0/ia_css_formats_types.h @@ -0,0 +1,38 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FORMATS_TYPES_H +#define __IA_CSS_FORMATS_TYPES_H + +/** @file +* CSS-API header file for output format parameters. +*/ + +#include "type_support.h" + +/** Formats configuration. + * + * ISP block: FORMATS + * ISP1: FORMATS is used. + * ISP2: FORMATS is used. + */ +struct ia_css_formats_config { + uint32_t video_full_range_flag; /**< selects the range of YUV output. + u8.0, [0,1], + default 1, ineffective n/a\n + 1 - full range, luma 0-255, chroma 0-255\n + 0 - reduced range, luma 16-235, chroma 16-240 */ +}; + +#endif /* __IA_CSS_FORMATS_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds.host.c new file mode 100644 index 0000000000000000000000000000000000000000..0ce5acecc8ee10fb088929a1c8919cbf46352bd5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds.host.c @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" + +#include "ia_css_fixedbds.host.h" + +void +ia_css_bds_encode( + struct sh_css_isp_bds_params *to, + const struct ia_css_aa_config *from, + unsigned size) +{ + (void)size; + to->baf_strength = from->strength; +} + +void +ia_css_bds_dump( + const struct sh_css_isp_bds_params *bds, + unsigned level) +{ + (void)bds; + (void)level; +} + +void +ia_css_bds_debug_dtrace( + const struct ia_css_aa_config *config, + unsigned level) +{ + (void)config; + (void)level; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds.host.h new file mode 100644 index 0000000000000000000000000000000000000000..fdc27caf01d0e6c7eb5101c7a0348817841422ec --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds.host.h @@ -0,0 +1,37 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FIXEDBDS_HOST_H +#define __IA_CSS_FIXEDBDS_HOST_H + +#include "ia_css_binary.h" +#include "ia_css_fixedbds_param.h" + +void +ia_css_bds_encode( + struct sh_css_isp_bds_params *to, + const struct ia_css_aa_config *from, + unsigned size); + +void +ia_css_bds_dump( + const struct sh_css_isp_bds_params *bds, + unsigned level); + +void +ia_css_bds_debug_dtrace( + const struct ia_css_aa_config *config, + unsigned level); + +#endif /* __IA_CSS_FIXEDBDS_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds_param.h new file mode 100644 index 0000000000000000000000000000000000000000..cc8dd1a7007fe87a356a6500cbac392b2cf837cf --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds_param.h @@ -0,0 +1,33 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FIXEDBDS_PARAM_H +#define __IA_CSS_FIXEDBDS_PARAM_H + +#include "type_support.h" + +#ifdef ISP2401 +#define BDS_UNIT 8 +#define FRAC_LOG 3 +#define FRAC_ACC (1< +#include +#include +#include +#include +#include +#include + +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" +#include "isp.h" + +#include "ia_css_fpn.host.h" + +void +ia_css_fpn_encode( + struct sh_css_isp_fpn_params *to, + const struct ia_css_fpn_table *from, + unsigned size) +{ + (void)size; + to->shift = from->shift; + to->enabled = from->data != NULL; +} + +void +ia_css_fpn_dump( + const struct sh_css_isp_fpn_params *fpn, + unsigned level) +{ + if (!fpn) return; + ia_css_debug_dtrace(level, "Fixed Pattern Noise Reduction:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "fpn_shift", fpn->shift); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "fpn_enabled", fpn->enabled); +} + +void +ia_css_fpn_config( + struct sh_css_isp_fpn_isp_config *to, + const struct ia_css_fpn_configuration *from, + unsigned size) +{ + unsigned elems_a = ISP_VEC_NELEMS; + + (void)size; + ia_css_dma_configure_from_info(&to->port_b, from->info); + to->width_a_over_b = elems_a / to->port_b.elems; + + /* Assume divisiblity here, may need to generalize to fixed point. */ + assert (elems_a % to->port_b.elems == 0); +} + +void +ia_css_fpn_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame_info *info) +{ + struct ia_css_frame_info my_info = IA_CSS_BINARY_DEFAULT_FRAME_INFO; + const struct ia_css_fpn_configuration config = { + &my_info + }; + + my_info.res.width = CEIL_DIV(info->res.width, 2); /* Packed by 2x */ + my_info.res.height = info->res.height; + my_info.padded_width = CEIL_DIV(info->padded_width, 2); /* Packed by 2x */ + my_info.format = info->format; + my_info.raw_bit_depth = FPN_BITS_PER_PIXEL; + my_info.raw_bayer_order = info->raw_bayer_order; + my_info.crop_info = info->crop_info; + + ia_css_configure_fpn(binary, &config); +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h new file mode 100644 index 0000000000000000000000000000000000000000..bb905c8db8c8232e82be36f4433ba5aae67de3f5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.h @@ -0,0 +1,44 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FPN_HOST_H +#define __IA_CSS_FPN_HOST_H + +#include "ia_css_binary.h" +#include "ia_css_fpn_types.h" +#include "ia_css_fpn_param.h" + +void +ia_css_fpn_encode( + struct sh_css_isp_fpn_params *to, + const struct ia_css_fpn_table *from, + unsigned size); + +void +ia_css_fpn_dump( + const struct sh_css_isp_fpn_params *fpn, + unsigned level); + +void +ia_css_fpn_config( + struct sh_css_isp_fpn_isp_config *to, + const struct ia_css_fpn_configuration *from, + unsigned size); + +void +ia_css_fpn_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame_info *from); + +#endif /* __IA_CSS_FPN_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fpn/fpn_1.0/ia_css_fpn_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fpn/fpn_1.0/ia_css_fpn_param.h new file mode 100644 index 0000000000000000000000000000000000000000..68765c3f3bf753dfe77b39acc3933e6761e2b1fc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fpn/fpn_1.0/ia_css_fpn_param.h @@ -0,0 +1,35 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FPN_PARAM_H +#define __IA_CSS_FPN_PARAM_H + +#include "type_support.h" + +#include "dma.h" + +#define FPN_BITS_PER_PIXEL 16 + +/* FPNR (Fixed Pattern Noise Reduction) */ +struct sh_css_isp_fpn_params { + int32_t shift; + int32_t enabled; +}; + +struct sh_css_isp_fpn_isp_config { + uint32_t width_a_over_b; + struct dma_port_config port_b; +}; + +#endif /* __IA_CSS_FPN_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fpn/fpn_1.0/ia_css_fpn_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fpn/fpn_1.0/ia_css_fpn_types.h new file mode 100644 index 0000000000000000000000000000000000000000..5a2f0c06a80d3c4d4b4a60f2acaf516289bfc5b5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/fpn/fpn_1.0/ia_css_fpn_types.h @@ -0,0 +1,52 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_FPN_TYPES_H +#define __IA_CSS_FPN_TYPES_H + +/** @file +* CSS-API header file for Fixed Pattern Noise parameters. +*/ + +/** Fixed Pattern Noise table. + * + * This contains the fixed patterns noise values + * obtained from a black frame capture. + * + * "shift" should be set as the smallest value + * which satisfies the requirement the maximum data is less than 64. + * + * ISP block: FPN1 + * ISP1: FPN1 is used. + * ISP2: FPN1 is used. + */ + +struct ia_css_fpn_table { + int16_t *data; /**< Table content (fixed patterns noise). + u0.[13-shift], [0,63] */ + uint32_t width; /**< Table width (in pixels). + This is the input frame width. */ + uint32_t height; /**< Table height (in pixels). + This is the input frame height. */ + uint32_t shift; /**< Common exponent of table content. + u8.0, [0,13] */ + uint32_t enabled; /**< Fpn is enabled. + bool */ +}; + +struct ia_css_fpn_configuration { + const struct ia_css_frame_info *info; +}; + +#endif /* __IA_CSS_FPN_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_1.0/ia_css_gc.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_1.0/ia_css_gc.host.c new file mode 100644 index 0000000000000000000000000000000000000000..0cfb5c94447f51e11599724acbae8b26f8d580cd --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_1.0/ia_css_gc.host.c @@ -0,0 +1,118 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#ifndef IA_CSS_NO_DEBUG +/* FIXME: See BZ 4427 */ +#include "ia_css_debug.h" +#endif +#include "sh_css_frac.h" +#include "vamem.h" + +#include "ia_css_gc.host.h" + +const struct ia_css_gc_config default_gc_config = { + 0, + 0 +}; + +const struct ia_css_ce_config default_ce_config = { + 0, + 255 +}; + +void +ia_css_gc_encode( + struct sh_css_isp_gc_params *to, + const struct ia_css_gc_config *from, + unsigned size) +{ + (void)size; + to->gain_k1 = + uDIGIT_FITTING((int)from->gain_k1, 16, + IA_CSS_GAMMA_GAIN_K_SHIFT); + to->gain_k2 = + uDIGIT_FITTING((int)from->gain_k2, 16, + IA_CSS_GAMMA_GAIN_K_SHIFT); +} + +void +ia_css_ce_encode( + struct sh_css_isp_ce_params *to, + const struct ia_css_ce_config *from, + unsigned size) +{ + (void)size; + to->uv_level_min = from->uv_level_min; + to->uv_level_max = from->uv_level_max; +} + +void +ia_css_gc_vamem_encode( + struct sh_css_isp_gc_vamem_params *to, + const struct ia_css_gamma_table *from, + unsigned size) +{ + (void)size; + memcpy (&to->gc, &from->data, sizeof(to->gc)); +} + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_gc_dump( + const struct sh_css_isp_gc_params *gc, + unsigned level) +{ + if (!gc) return; + ia_css_debug_dtrace(level, "Gamma Correction:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "gamma_gain_k1", gc->gain_k1); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "gamma_gain_k2", gc->gain_k2); +} + +void +ia_css_ce_dump( + const struct sh_css_isp_ce_params *ce, + unsigned level) +{ + ia_css_debug_dtrace(level, "Chroma Enhancement:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ce_uv_level_min", ce->uv_level_min); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ce_uv_level_max", ce->uv_level_max); +} + +void +ia_css_gc_debug_dtrace( + const struct ia_css_gc_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.gain_k1=%d, config.gain_k2=%d\n", + config->gain_k1, config->gain_k2); +} + +void +ia_css_ce_debug_dtrace( + const struct ia_css_ce_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.uv_level_min=%d, config.uv_level_max=%d\n", + config->uv_level_min, config->uv_level_max); +} +#endif + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_1.0/ia_css_gc.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_1.0/ia_css_gc.host.h new file mode 100644 index 0000000000000000000000000000000000000000..06f08840563ec9bde59a2ae5fa66171cf249e6df --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_1.0/ia_css_gc.host.h @@ -0,0 +1,65 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_GC_HOST_H +#define __IA_CSS_GC_HOST_H + +#include "ia_css_gc_param.h" +#include "ia_css_gc_table.host.h" + +extern const struct ia_css_gc_config default_gc_config; +extern const struct ia_css_ce_config default_ce_config; + +void +ia_css_gc_encode( + struct sh_css_isp_gc_params *to, + const struct ia_css_gc_config *from, + unsigned size); + +void +ia_css_gc_vamem_encode( + struct sh_css_isp_gc_vamem_params *to, + const struct ia_css_gamma_table *from, + unsigned size); + +void +ia_css_ce_encode( + struct sh_css_isp_ce_params *to, + const struct ia_css_ce_config *from, + unsigned size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_gc_dump( + const struct sh_css_isp_gc_params *gc, + unsigned level); + +void +ia_css_ce_dump( + const struct sh_css_isp_ce_params *ce, + unsigned level); + +void +ia_css_gc_debug_dtrace( + const struct ia_css_gc_config *config, + unsigned level); + +void +ia_css_ce_debug_dtrace( + const struct ia_css_ce_config *config, + unsigned level); + +#endif + +#endif /* __IA_CSS_GC_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_1.0/ia_css_gc_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_1.0/ia_css_gc_param.h new file mode 100644 index 0000000000000000000000000000000000000000..52972b1a07ff8e10e722aa01a4c22acaec3f2ef9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_1.0/ia_css_gc_param.h @@ -0,0 +1,61 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_GC_PARAM_H +#define __IA_CSS_GC_PARAM_H + +#include "type_support.h" +#ifndef PIPE_GENERATION +#ifdef __ISP +#define __INLINE_VAMEM__ +#endif +#include "vamem.h" +#include "ia_css_gc_types.h" + +#if defined(IS_VAMEM_VERSION_1) +#define SH_CSS_ISP_GAMMA_TABLE_SIZE_LOG2 IA_CSS_VAMEM_1_GAMMA_TABLE_SIZE_LOG2 +#define SH_CSS_ISP_GC_TABLE_SIZE IA_CSS_VAMEM_1_GAMMA_TABLE_SIZE +#elif defined(IS_VAMEM_VERSION_2) +#define SH_CSS_ISP_GAMMA_TABLE_SIZE_LOG2 IA_CSS_VAMEM_2_GAMMA_TABLE_SIZE_LOG2 +#define SH_CSS_ISP_GC_TABLE_SIZE IA_CSS_VAMEM_2_GAMMA_TABLE_SIZE +#else +#error "Undefined vamem version" +#endif + +#else +/* For pipe generation, the size is not relevant */ +#define SH_CSS_ISP_GC_TABLE_SIZE 0 +#endif + +#define GAMMA_OUTPUT_BITS 8 +#define GAMMA_OUTPUT_MAX_VAL ((1< +#include /* memcpy */ +#include "system_global.h" +#include "vamem.h" +#include "ia_css_types.h" +#include "ia_css_gc_table.host.h" + +#if defined(HAS_VAMEM_VERSION_2) + +struct ia_css_gamma_table default_gamma_table; + +static const uint16_t +default_gamma_table_data[IA_CSS_VAMEM_2_GAMMA_TABLE_SIZE] = { + 0, 4, 8, 12, 17, 21, 27, 32, + 38, 44, 49, 55, 61, 66, 71, 76, + 80, 84, 88, 92, 95, 98, 102, 105, +108, 110, 113, 116, 118, 121, 123, 126, +128, 130, 132, 135, 137, 139, 141, 143, +145, 146, 148, 150, 152, 153, 155, 156, +158, 160, 161, 162, 164, 165, 166, 168, +169, 170, 171, 172, 174, 175, 176, 177, +178, 179, 180, 181, 182, 183, 184, 184, +185, 186, 187, 188, 189, 189, 190, 191, +192, 192, 193, 194, 195, 195, 196, 197, +197, 198, 198, 199, 200, 200, 201, 201, +202, 203, 203, 204, 204, 205, 205, 206, +206, 207, 207, 208, 208, 209, 209, 210, +210, 210, 211, 211, 212, 212, 213, 213, +214, 214, 214, 215, 215, 216, 216, 216, +217, 217, 218, 218, 218, 219, 219, 220, +220, 220, 221, 221, 222, 222, 222, 223, +223, 223, 224, 224, 225, 225, 225, 226, +226, 226, 227, 227, 227, 228, 228, 228, +229, 229, 229, 230, 230, 230, 231, 231, +231, 232, 232, 232, 233, 233, 233, 234, +234, 234, 234, 235, 235, 235, 236, 236, +236, 237, 237, 237, 237, 238, 238, 238, +239, 239, 239, 239, 240, 240, 240, 241, +241, 241, 241, 242, 242, 242, 242, 243, +243, 243, 243, 244, 244, 244, 245, 245, +245, 245, 246, 246, 246, 246, 247, 247, +247, 247, 248, 248, 248, 248, 249, 249, +249, 249, 250, 250, 250, 250, 251, 251, +251, 251, 252, 252, 252, 252, 253, 253, +253, 253, 254, 254, 254, 254, 255, 255, +255 +}; + +#elif defined(HAS_VAMEM_VERSION_1) + +static const uint16_t +default_gamma_table_data[IA_CSS_VAMEM_1_GAMMA_TABLE_SIZE] = { + 0, 1, 2, 3, 4, 5, 6, 7, + 8, 9, 10, 11, 12, 13, 14, 16, + 17, 18, 19, 20, 21, 23, 24, 25, + 27, 28, 29, 31, 32, 33, 35, 36, + 38, 39, 41, 42, 44, 45, 47, 48, + 49, 51, 52, 54, 55, 57, 58, 60, + 61, 62, 64, 65, 66, 68, 69, 70, + 71, 72, 74, 75, 76, 77, 78, 79, + 80, 81, 82, 83, 84, 85, 86, 87, + 88, 89, 90, 91, 92, 93, 93, 94, + 95, 96, 97, 98, 98, 99, 100, 101, + 102, 102, 103, 104, 105, 105, 106, 107, + 108, 108, 109, 110, 110, 111, 112, 112, + 113, 114, 114, 115, 116, 116, 117, 118, + 118, 119, 120, 120, 121, 121, 122, 123, + 123, 124, 125, 125, 126, 126, 127, 127, /* 128 */ + 128, 129, 129, 130, 130, 131, 131, 132, + 132, 133, 134, 134, 135, 135, 136, 136, + 137, 137, 138, 138, 139, 139, 140, 140, + 141, 141, 142, 142, 143, 143, 144, 144, + 145, 145, 145, 146, 146, 147, 147, 148, + 148, 149, 149, 150, 150, 150, 151, 151, + 152, 152, 152, 153, 153, 154, 154, 155, + 155, 155, 156, 156, 156, 157, 157, 158, + 158, 158, 159, 159, 160, 160, 160, 161, + 161, 161, 162, 162, 162, 163, 163, 163, + 164, 164, 164, 165, 165, 165, 166, 166, + 166, 167, 167, 167, 168, 168, 168, 169, + 169, 169, 170, 170, 170, 170, 171, 171, + 171, 172, 172, 172, 172, 173, 173, 173, + 174, 174, 174, 174, 175, 175, 175, 176, + 176, 176, 176, 177, 177, 177, 177, 178, /* 256 */ + 178, 178, 178, 179, 179, 179, 179, 180, + 180, 180, 180, 181, 181, 181, 181, 182, + 182, 182, 182, 182, 183, 183, 183, 183, + 184, 184, 184, 184, 184, 185, 185, 185, + 185, 186, 186, 186, 186, 186, 187, 187, + 187, 187, 187, 188, 188, 188, 188, 188, + 189, 189, 189, 189, 189, 190, 190, 190, + 190, 190, 191, 191, 191, 191, 191, 192, + 192, 192, 192, 192, 192, 193, 193, 193, + 193, 193, 194, 194, 194, 194, 194, 194, + 195, 195, 195, 195, 195, 195, 196, 196, + 196, 196, 196, 196, 197, 197, 197, 197, + 197, 197, 198, 198, 198, 198, 198, 198, + 198, 199, 199, 199, 199, 199, 199, 200, + 200, 200, 200, 200, 200, 200, 201, 201, + 201, 201, 201, 201, 201, 202, 202, 202, /* 384 */ + 202, 202, 202, 202, 203, 203, 203, 203, + 203, 203, 203, 204, 204, 204, 204, 204, + 204, 204, 204, 205, 205, 205, 205, 205, + 205, 205, 205, 206, 206, 206, 206, 206, + 206, 206, 206, 207, 207, 207, 207, 207, + 207, 207, 207, 208, 208, 208, 208, 208, + 208, 208, 208, 209, 209, 209, 209, 209, + 209, 209, 209, 209, 210, 210, 210, 210, + 210, 210, 210, 210, 210, 211, 211, 211, + 211, 211, 211, 211, 211, 211, 212, 212, + 212, 212, 212, 212, 212, 212, 212, 213, + 213, 213, 213, 213, 213, 213, 213, 213, + 214, 214, 214, 214, 214, 214, 214, 214, + 214, 214, 215, 215, 215, 215, 215, 215, + 215, 215, 215, 216, 216, 216, 216, 216, + 216, 216, 216, 216, 216, 217, 217, 217, /* 512 */ + 217, 217, 217, 217, 217, 217, 217, 218, + 218, 218, 218, 218, 218, 218, 218, 218, + 218, 219, 219, 219, 219, 219, 219, 219, + 219, 219, 219, 220, 220, 220, 220, 220, + 220, 220, 220, 220, 220, 221, 221, 221, + 221, 221, 221, 221, 221, 221, 221, 221, + 222, 222, 222, 222, 222, 222, 222, 222, + 222, 222, 223, 223, 223, 223, 223, 223, + 223, 223, 223, 223, 223, 224, 224, 224, + 224, 224, 224, 224, 224, 224, 224, 224, + 225, 225, 225, 225, 225, 225, 225, 225, + 225, 225, 225, 226, 226, 226, 226, 226, + 226, 226, 226, 226, 226, 226, 226, 227, + 227, 227, 227, 227, 227, 227, 227, 227, + 227, 227, 228, 228, 228, 228, 228, 228, + 228, 228, 228, 228, 228, 228, 229, 229, + 229, 229, 229, 229, 229, 229, 229, 229, + 229, 229, 230, 230, 230, 230, 230, 230, + 230, 230, 230, 230, 230, 230, 231, 231, + 231, 231, 231, 231, 231, 231, 231, 231, + 231, 231, 231, 232, 232, 232, 232, 232, + 232, 232, 232, 232, 232, 232, 232, 233, + 233, 233, 233, 233, 233, 233, 233, 233, + 233, 233, 233, 233, 234, 234, 234, 234, + 234, 234, 234, 234, 234, 234, 234, 234, + 234, 235, 235, 235, 235, 235, 235, 235, + 235, 235, 235, 235, 235, 235, 236, 236, + 236, 236, 236, 236, 236, 236, 236, 236, + 236, 236, 236, 236, 237, 237, 237, 237, + 237, 237, 237, 237, 237, 237, 237, 237, + 237, 237, 238, 238, 238, 238, 238, 238, + 238, 238, 238, 238, 238, 238, 238, 238, + 239, 239, 239, 239, 239, 239, 239, 239, + 239, 239, 239, 239, 239, 239, 240, 240, + 240, 240, 240, 240, 240, 240, 240, 240, + 240, 240, 240, 240, 241, 241, 241, 241, + 241, 241, 241, 241, 241, 241, 241, 241, + 241, 241, 241, 242, 242, 242, 242, 242, + 242, 242, 242, 242, 242, 242, 242, 242, + 242, 242, 243, 243, 243, 243, 243, 243, + 243, 243, 243, 243, 243, 243, 243, 243, + 243, 244, 244, 244, 244, 244, 244, 244, + 244, 244, 244, 244, 244, 244, 244, 244, + 245, 245, 245, 245, 245, 245, 245, 245, + 245, 245, 245, 245, 245, 245, 245, 246, + 246, 246, 246, 246, 246, 246, 246, 246, + 246, 246, 246, 246, 246, 246, 246, 247, + 247, 247, 247, 247, 247, 247, 247, 247, + 247, 247, 247, 247, 247, 247, 247, 248, + 248, 248, 248, 248, 248, 248, 248, 248, + 248, 248, 248, 248, 248, 248, 248, 249, + 249, 249, 249, 249, 249, 249, 249, 249, + 249, 249, 249, 249, 249, 249, 249, 250, + 250, 250, 250, 250, 250, 250, 250, 250, + 250, 250, 250, 250, 250, 250, 250, 251, + 251, 251, 251, 251, 251, 251, 251, 251, + 251, 251, 251, 251, 251, 251, 251, 252, + 252, 252, 252, 252, 252, 252, 252, 252, + 252, 252, 252, 252, 252, 252, 252, 253, + 253, 253, 253, 253, 253, 253, 253, 253, + 253, 253, 253, 253, 253, 253, 253, 253, + 254, 254, 254, 254, 254, 254, 254, 254, + 254, 254, 254, 254, 254, 254, 254, 254, + 255, 255, 255, 255, 255, 255, 255, 255 +}; + +#else +#error "VAMEM version must be one of {VAMEM_VERSION_1, VAMEM_VERSION_2}" +#endif + +void +ia_css_config_gamma_table(void) +{ +#if defined(HAS_VAMEM_VERSION_2) + memcpy(default_gamma_table.data.vamem_2, default_gamma_table_data, + sizeof(default_gamma_table_data)); + default_gamma_table.vamem_type = IA_CSS_VAMEM_TYPE_2; +#else + memcpy(default_gamma_table.data.vamem_1, default_gamma_table_data, + sizeof(default_gamma_table_data)); + default_gamma_table.vamem_type = IA_CSS_VAMEM_TYPE_1; +#endif +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_1.0/ia_css_gc_table.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_1.0/ia_css_gc_table.host.h new file mode 100644 index 0000000000000000000000000000000000000000..9686623d9cdd4503412e6f45b2ddb6dc45d62ff7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_1.0/ia_css_gc_table.host.h @@ -0,0 +1,24 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_GC_TABLE_HOST_H +#define __IA_CSS_GC_TABLE_HOST_H + +#include "ia_css_gc_types.h" + +extern struct ia_css_gamma_table default_gamma_table; + +void ia_css_config_gamma_table(void); + +#endif /* __IA_CSS_GC_TABLE_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_1.0/ia_css_gc_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_1.0/ia_css_gc_types.h new file mode 100644 index 0000000000000000000000000000000000000000..dd9f0eda3353119a96b5a6b4ba436089e6a0de6b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_1.0/ia_css_gc_types.h @@ -0,0 +1,97 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_GC_TYPES_H +#define __IA_CSS_GC_TYPES_H + +/** @file +* CSS-API header file for Gamma Correction parameters. +*/ + +#include "isp/kernels/ctc/ctc_1.0/ia_css_ctc_types.h" /* FIXME: Needed for ia_css_vamem_type */ + +/** Fractional bits for GAMMA gain */ +#define IA_CSS_GAMMA_GAIN_K_SHIFT 13 + +/** Number of elements in the gamma table. */ +#define IA_CSS_VAMEM_1_GAMMA_TABLE_SIZE_LOG2 10 +#define IA_CSS_VAMEM_1_GAMMA_TABLE_SIZE (1U<gc, &from->data, sizeof(to->gc)); +} + +void +ia_css_g_gamma_vamem_encode( + struct sh_css_isp_rgb_gamma_vamem_params *to, + const struct ia_css_rgb_gamma_table *from, + unsigned size) +{ + (void)size; + memcpy (&to->gc, &from->data, sizeof(to->gc)); +} + +void +ia_css_b_gamma_vamem_encode( + struct sh_css_isp_rgb_gamma_vamem_params *to, + const struct ia_css_rgb_gamma_table *from, + unsigned size) +{ + (void)size; + memcpy (&to->gc, &from->data, sizeof(to->gc)); +} + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_yuv2rgb_dump( + const struct sh_css_isp_csc_params *yuv2rgb, + unsigned level) +{ + ia_css_cc_dump(yuv2rgb, level, "YUV to RGB Conversion"); +} + +void +ia_css_rgb2yuv_dump( + const struct sh_css_isp_csc_params *rgb2yuv, + unsigned level) +{ + ia_css_cc_dump(rgb2yuv, level, "RGB to YUV Conversion"); +} + +void +ia_css_rgb_gamma_table_debug_dtrace( + const struct ia_css_rgb_gamma_table *config, + unsigned level) +{ + (void)config; + (void)level; +} +#endif + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_2/ia_css_gc2.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_2/ia_css_gc2.host.h new file mode 100644 index 0000000000000000000000000000000000000000..ba140eefd5256c0269b309ae4db697716214a238 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_2/ia_css_gc2.host.h @@ -0,0 +1,79 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_GC2_HOST_H +#define __IA_CSS_GC2_HOST_H + +#include "ia_css_gc2_types.h" +#include "ia_css_gc2_param.h" +#include "ia_css_gc2_table.host.h" + +extern const struct ia_css_cc_config default_yuv2rgb_cc_config; +extern const struct ia_css_cc_config default_rgb2yuv_cc_config; + +void +ia_css_yuv2rgb_encode( + struct sh_css_isp_csc_params *to, + const struct ia_css_cc_config *from, + unsigned size); + +void +ia_css_rgb2yuv_encode( + struct sh_css_isp_csc_params *to, + const struct ia_css_cc_config *from, + unsigned size); + +void +ia_css_r_gamma_vamem_encode( + struct sh_css_isp_rgb_gamma_vamem_params *to, + const struct ia_css_rgb_gamma_table *from, + unsigned size); + +void +ia_css_g_gamma_vamem_encode( + struct sh_css_isp_rgb_gamma_vamem_params *to, + const struct ia_css_rgb_gamma_table *from, + unsigned size); + +void +ia_css_b_gamma_vamem_encode( + struct sh_css_isp_rgb_gamma_vamem_params *to, + const struct ia_css_rgb_gamma_table *from, + unsigned size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_yuv2rgb_dump( + const struct sh_css_isp_csc_params *yuv2rgb, + unsigned level); + +void +ia_css_rgb2yuv_dump( + const struct sh_css_isp_csc_params *rgb2yuv, + unsigned level); + +void +ia_css_rgb_gamma_table_debug_dtrace( + const struct ia_css_rgb_gamma_table *config, + unsigned level); + +#define ia_css_yuv2rgb_debug_dtrace ia_css_cc_config_debug_dtrace +#define ia_css_rgb2yuv_debug_dtrace ia_css_cc_config_debug_dtrace +#define ia_css_r_gamma_debug_dtrace ia_css_rgb_gamma_table_debug_dtrace +#define ia_css_g_gamma_debug_dtrace ia_css_rgb_gamma_table_debug_dtrace +#define ia_css_b_gamma_debug_dtrace ia_css_rgb_gamma_table_debug_dtrace + +#endif + +#endif /* __IA_CSS_GC2_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_2/ia_css_gc2_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_2/ia_css_gc2_param.h new file mode 100644 index 0000000000000000000000000000000000000000..d25239f4d86f09f7389127ac4571d477be06defe --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_2/ia_css_gc2_param.h @@ -0,0 +1,43 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_GC2_PARAM_H +#define __IA_CSS_GC2_PARAM_H + +#include "type_support.h" +/* Extend GC1 */ +#include "ia_css_gc2_types.h" +#include "gc/gc_1.0/ia_css_gc_param.h" +#include "csc/csc_1.0/ia_css_csc_param.h" + +#ifndef PIPE_GENERATION +#if defined(IS_VAMEM_VERSION_1) +#define SH_CSS_ISP_RGB_GAMMA_TABLE_SIZE IA_CSS_VAMEM_1_RGB_GAMMA_TABLE_SIZE +#elif defined(IS_VAMEM_VERSION_2) +#define SH_CSS_ISP_RGB_GAMMA_TABLE_SIZE IA_CSS_VAMEM_2_RGB_GAMMA_TABLE_SIZE +#else +#error "Undefined vamem version" +#endif + +#else +/* For pipe generation, the size is not relevant */ +#define SH_CSS_ISP_RGB_GAMMA_TABLE_SIZE 0 +#endif + +/* This should be vamem_data_t, but that breaks the pipe generator */ +struct sh_css_isp_rgb_gamma_vamem_params { + uint16_t gc[SH_CSS_ISP_RGB_GAMMA_TABLE_SIZE]; +}; + +#endif /* __IA_CSS_GC2_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_2/ia_css_gc2_table.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_2/ia_css_gc2_table.host.c new file mode 100644 index 0000000000000000000000000000000000000000..f14a66b78714ffc47e895de7a87a22c84823a989 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_2/ia_css_gc2_table.host.c @@ -0,0 +1,132 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include /* memcpy */ +#include "system_global.h" +#include "vamem.h" +#include "ia_css_types.h" +#include "ia_css_gc2_table.host.h" + +struct ia_css_rgb_gamma_table default_r_gamma_table; +struct ia_css_rgb_gamma_table default_g_gamma_table; +struct ia_css_rgb_gamma_table default_b_gamma_table; + +/* Identical default gamma table for R, G, and B. */ + +#if defined(HAS_VAMEM_VERSION_2) + +static const uint16_t +default_gamma_table_data[IA_CSS_VAMEM_2_RGB_GAMMA_TABLE_SIZE] = { + 0, 72, 144, 216, 288, 360, 426, 486, + 541, 592, 641, 687, 730, 772, 812, 850, + 887, 923, 958, 991, 1024, 1055, 1086, 1117, +1146, 1175, 1203, 1230, 1257, 1284, 1310, 1335, +1360, 1385, 1409, 1433, 1457, 1480, 1502, 1525, +1547, 1569, 1590, 1612, 1632, 1653, 1674, 1694, +1714, 1734, 1753, 1772, 1792, 1811, 1829, 1848, +1866, 1884, 1902, 1920, 1938, 1955, 1973, 1990, +2007, 2024, 2040, 2057, 2074, 2090, 2106, 2122, +2138, 2154, 2170, 2185, 2201, 2216, 2231, 2247, +2262, 2277, 2291, 2306, 2321, 2335, 2350, 2364, +2378, 2393, 2407, 2421, 2435, 2449, 2462, 2476, +2490, 2503, 2517, 2530, 2543, 2557, 2570, 2583, +2596, 2609, 2622, 2634, 2647, 2660, 2673, 2685, +2698, 2710, 2722, 2735, 2747, 2759, 2771, 2783, +2795, 2807, 2819, 2831, 2843, 2855, 2867, 2878, +2890, 2901, 2913, 2924, 2936, 2947, 2958, 2970, +2981, 2992, 3003, 3014, 3025, 3036, 3047, 3058, +3069, 3080, 3091, 3102, 3112, 3123, 3134, 3144, +3155, 3165, 3176, 3186, 3197, 3207, 3217, 3228, +3238, 3248, 3258, 3268, 3279, 3289, 3299, 3309, +3319, 3329, 3339, 3349, 3358, 3368, 3378, 3388, +3398, 3407, 3417, 3427, 3436, 3446, 3455, 3465, +3474, 3484, 3493, 3503, 3512, 3521, 3531, 3540, +3549, 3559, 3568, 3577, 3586, 3595, 3605, 3614, +3623, 3632, 3641, 3650, 3659, 3668, 3677, 3686, +3694, 3703, 3712, 3721, 3730, 3739, 3747, 3756, +3765, 3773, 3782, 3791, 3799, 3808, 3816, 3825, +3833, 3842, 3850, 3859, 3867, 3876, 3884, 3893, +3901, 3909, 3918, 3926, 3934, 3942, 3951, 3959, +3967, 3975, 3984, 3992, 4000, 4008, 4016, 4024, +4032, 4040, 4048, 4056, 4064, 4072, 4080, 4088, +4095 +}; +#elif defined(HAS_VAMEM_VERSION_1) + +static const uint16_t +default_gamma_table_data[IA_CSS_VAMEM_1_RGB_GAMMA_TABLE_SIZE] = { + 0, 72, 144, 216, 288, 360, 426, 486, + 541, 592, 641, 687, 730, 772, 812, 850, + 887, 923, 958, 991, 1024, 1055, 1086, 1117, +1146, 1175, 1203, 1230, 1257, 1284, 1310, 1335, +1360, 1385, 1409, 1433, 1457, 1480, 1502, 1525, +1547, 1569, 1590, 1612, 1632, 1653, 1674, 1694, +1714, 1734, 1753, 1772, 1792, 1811, 1829, 1848, +1866, 1884, 1902, 1920, 1938, 1955, 1973, 1990, +2007, 2024, 2040, 2057, 2074, 2090, 2106, 2122, +2138, 2154, 2170, 2185, 2201, 2216, 2231, 2247, +2262, 2277, 2291, 2306, 2321, 2335, 2350, 2364, +2378, 2393, 2407, 2421, 2435, 2449, 2462, 2476, +2490, 2503, 2517, 2530, 2543, 2557, 2570, 2583, +2596, 2609, 2622, 2634, 2647, 2660, 2673, 2685, +2698, 2710, 2722, 2735, 2747, 2759, 2771, 2783, +2795, 2807, 2819, 2831, 2843, 2855, 2867, 2878, +2890, 2901, 2913, 2924, 2936, 2947, 2958, 2970, +2981, 2992, 3003, 3014, 3025, 3036, 3047, 3058, +3069, 3080, 3091, 3102, 3112, 3123, 3134, 3144, +3155, 3165, 3176, 3186, 3197, 3207, 3217, 3228, +3238, 3248, 3258, 3268, 3279, 3289, 3299, 3309, +3319, 3329, 3339, 3349, 3358, 3368, 3378, 3388, +3398, 3407, 3417, 3427, 3436, 3446, 3455, 3465, +3474, 3484, 3493, 3503, 3512, 3521, 3531, 3540, +3549, 3559, 3568, 3577, 3586, 3595, 3605, 3614, +3623, 3632, 3641, 3650, 3659, 3668, 3677, 3686, +3694, 3703, 3712, 3721, 3730, 3739, 3747, 3756, +3765, 3773, 3782, 3791, 3799, 3808, 3816, 3825, +3833, 3842, 3850, 3859, 3867, 3876, 3884, 3893, +3901, 3909, 3918, 3926, 3934, 3942, 3951, 3959, +3967, 3975, 3984, 3992, 4000, 4008, 4016, 4024, +4032, 4040, 4048, 4056, 4064, 4072, 4080, 4088 +}; +#else +#error "VAMEM version must be one of {VAMEM_VERSION_1, VAMEM_VERSION_2}" +#endif + +void +ia_css_config_rgb_gamma_tables(void) +{ +#if defined(HAS_VAMEM_VERSION_2) + default_r_gamma_table.vamem_type = IA_CSS_VAMEM_TYPE_2; + default_g_gamma_table.vamem_type = IA_CSS_VAMEM_TYPE_2; + default_b_gamma_table.vamem_type = IA_CSS_VAMEM_TYPE_2; + memcpy(default_r_gamma_table.data.vamem_2, default_gamma_table_data, + sizeof(default_gamma_table_data)); + memcpy(default_g_gamma_table.data.vamem_2, default_gamma_table_data, + sizeof(default_gamma_table_data)); + memcpy(default_b_gamma_table.data.vamem_2, default_gamma_table_data, + sizeof(default_gamma_table_data)); +#else + memcpy(default_r_gamma_table.data.vamem_1, default_gamma_table_data, + sizeof(default_gamma_table_data)); + memcpy(default_g_gamma_table.data.vamem_1, default_gamma_table_data, + sizeof(default_gamma_table_data)); + memcpy(default_b_gamma_table.data.vamem_1, default_gamma_table_data, + sizeof(default_gamma_table_data)); + default_r_gamma_table.vamem_type = IA_CSS_VAMEM_TYPE_1; + default_g_gamma_table.vamem_type = IA_CSS_VAMEM_TYPE_1; + default_b_gamma_table.vamem_type = IA_CSS_VAMEM_TYPE_1; +#endif +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_2/ia_css_gc2_table.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_2/ia_css_gc2_table.host.h new file mode 100644 index 0000000000000000000000000000000000000000..8686e6e3586cea100ef0c835f18a7c898570724d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_2/ia_css_gc2_table.host.h @@ -0,0 +1,26 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_GC2_TABLE_HOST_H +#define __IA_CSS_GC2_TABLE_HOST_H + +#include "ia_css_gc2_types.h" + +extern struct ia_css_rgb_gamma_table default_r_gamma_table; +extern struct ia_css_rgb_gamma_table default_g_gamma_table; +extern struct ia_css_rgb_gamma_table default_b_gamma_table; + +void ia_css_config_rgb_gamma_tables(void); + +#endif /* __IA_CSS_GC2_TABLE_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_2/ia_css_gc2_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_2/ia_css_gc2_types.h new file mode 100644 index 0000000000000000000000000000000000000000..e439583bdfb6f2e8ae0d5b7f7f0bb20225a6c012 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/gc/gc_2/ia_css_gc2_types.h @@ -0,0 +1,54 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_GC2_TYPES_H +#define __IA_CSS_GC2_TYPES_H + +#include "isp/kernels/ctc/ctc_1.0/ia_css_ctc_types.h" /* FIXME: needed for ia_css_vamem_type */ + +/** @file +* CSS-API header file for Gamma Correction parameters. +*/ + +/** sRGB Gamma table, used for sRGB Gamma Correction. + * + * ISP block: GC2 (sRGB Gamma Correction) + * (ISP1: GC1(YUV Gamma Correction) is used.) + * ISP2: GC2 is used. + */ + +/** Number of elements in the sRGB gamma table. */ +#define IA_CSS_VAMEM_1_RGB_GAMMA_TABLE_SIZE_LOG2 8 +#define IA_CSS_VAMEM_1_RGB_GAMMA_TABLE_SIZE (1U<irradiance.match_shift[i] = from->irradiance.match_shift[i]; + to->irradiance.match_mul[i] = from->irradiance.match_mul[i]; + to->irradiance.thr_low[i] = from->irradiance.thr_low[i]; + to->irradiance.thr_high[i] = from->irradiance.thr_high[i]; + to->irradiance.thr_coeff[i] = from->irradiance.thr_coeff[i]; + to->irradiance.thr_shift[i] = from->irradiance.thr_shift[i]; + } + to->irradiance.test_irr = from->irradiance.test_irr; + to->irradiance.weight_bpp = from->irradiance.weight_bpp; + + to->deghost.test_deg = from->deghost.test_deg; + to->exclusion.test_excl = from->exclusion.test_excl; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/hdr/ia_css_hdr.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/hdr/ia_css_hdr.host.h new file mode 100644 index 0000000000000000000000000000000000000000..8f89bc8f1ca2b5e6693fa7555bc7cad8ebe4b03a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/hdr/ia_css_hdr.host.h @@ -0,0 +1,31 @@ +/* Release Version: irci_stable_candrpv_0415_20150521_0458 */ +/* Release Version: irci_ecr-master_20150911_0724 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_HDR_HOST_H +#define __IA_CSS_HDR_HOST_H + +#include "ia_css_hdr_param.h" +#include "ia_css_hdr_types.h" + +extern const struct ia_css_hdr_config default_hdr_config; + +void +ia_css_hdr_init_config( + struct sh_css_isp_hdr_params *to, + const struct ia_css_hdr_config *from, + unsigned size); + +#endif /* __IA_CSS_HDR_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/hdr/ia_css_hdr_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/hdr/ia_css_hdr_param.h new file mode 100644 index 0000000000000000000000000000000000000000..1c053af7d0d355e270b1377834d73f115e44dae1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/hdr/ia_css_hdr_param.h @@ -0,0 +1,53 @@ +/* Release Version: irci_stable_candrpv_0415_20150521_0458 */ +/* Release Version: irci_ecr-master_20150911_0724 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_HDR_PARAMS_H +#define __IA_CSS_HDR_PARAMS_H + +#include "type_support.h" + +#define HDR_NUM_INPUT_FRAMES (3) + +/* HDR irradiance map parameters on ISP. */ +struct sh_css_hdr_irradiance_params { + int32_t test_irr; + int32_t match_shift[HDR_NUM_INPUT_FRAMES - 1]; /* Histogram matching shift parameter */ + int32_t match_mul[HDR_NUM_INPUT_FRAMES - 1]; /* Histogram matching multiplication parameter */ + int32_t thr_low[HDR_NUM_INPUT_FRAMES - 1]; /* Weight map soft threshold low bound parameter */ + int32_t thr_high[HDR_NUM_INPUT_FRAMES - 1]; /* Weight map soft threshold high bound parameter */ + int32_t thr_coeff[HDR_NUM_INPUT_FRAMES - 1]; /* Soft threshold linear function coefficient */ + int32_t thr_shift[HDR_NUM_INPUT_FRAMES - 1]; /* Soft threshold precision shift parameter */ + int32_t weight_bpp; /* Weight map bits per pixel */ +}; + +/* HDR deghosting parameters on ISP */ +struct sh_css_hdr_deghost_params { + int32_t test_deg; +}; + +/* HDR exclusion parameters on ISP */ +struct sh_css_hdr_exclusion_params { + int32_t test_excl; +}; + +/* HDR ISP parameters */ +struct sh_css_isp_hdr_params { + struct sh_css_hdr_irradiance_params irradiance; + struct sh_css_hdr_deghost_params deghost; + struct sh_css_hdr_exclusion_params exclusion; +}; + +#endif /* __IA_CSS_HDR_PARAMS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/hdr/ia_css_hdr_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/hdr/ia_css_hdr_types.h new file mode 100644 index 0000000000000000000000000000000000000000..c3345b32e3e6e6f300374a9739de59f49e194933 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/hdr/ia_css_hdr_types.h @@ -0,0 +1,64 @@ +/* Release Version: irci_stable_candrpv_0415_20150521_0458 */ +/* Release Version: irci_ecr-master_20150911_0724 */ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_HDR_TYPES_H +#define __IA_CSS_HDR_TYPES_H + +#define IA_CSS_HDR_MAX_NUM_INPUT_FRAMES (3) + +/** + * \brief HDR Irradiance Parameters + * \detail Currently HDR paramters are used only for testing purposes + */ +struct ia_css_hdr_irradiance_params { + int test_irr; /**< Test parameter */ + int match_shift[IA_CSS_HDR_MAX_NUM_INPUT_FRAMES - 1]; /**< Histogram matching shift parameter */ + int match_mul[IA_CSS_HDR_MAX_NUM_INPUT_FRAMES - 1]; /**< Histogram matching multiplication parameter */ + int thr_low[IA_CSS_HDR_MAX_NUM_INPUT_FRAMES - 1]; /**< Weight map soft threshold low bound parameter */ + int thr_high[IA_CSS_HDR_MAX_NUM_INPUT_FRAMES - 1]; /**< Weight map soft threshold high bound parameter */ + int thr_coeff[IA_CSS_HDR_MAX_NUM_INPUT_FRAMES - 1]; /**< Soft threshold linear function coefficien */ + int thr_shift[IA_CSS_HDR_MAX_NUM_INPUT_FRAMES - 1]; /**< Soft threshold precision shift parameter */ + int weight_bpp; /**< Weight map bits per pixel */ +}; + +/** + * \brief HDR Deghosting Parameters + * \detail Currently HDR paramters are used only for testing purposes + */ +struct ia_css_hdr_deghost_params { + int test_deg; /**< Test parameter */ +}; + +/** + * \brief HDR Exclusion Parameters + * \detail Currently HDR paramters are used only for testing purposes + */ +struct ia_css_hdr_exclusion_params { + int test_excl; /**< Test parameter */ +}; + +/** + * \brief HDR public paramterers. + * \details Struct with all paramters for HDR that can be seet from + * the CSS API. Currenly, only test paramters are defined. + */ +struct ia_css_hdr_config { + struct ia_css_hdr_irradiance_params irradiance; /**< HDR irradiance paramaters */ + struct ia_css_hdr_deghost_params deghost; /**< HDR deghosting parameters */ + struct ia_css_hdr_exclusion_params exclusion; /**< HDR exclusion parameters */ +}; + +#endif /* __IA_CSS_HDR_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6.host.c new file mode 100644 index 0000000000000000000000000000000000000000..270f423b23d9361999e47c980f49e24f0bc9e87f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6.host.c @@ -0,0 +1,200 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" +#endif +#include "ia_css_iefd2_6.host.h" + +/* Copy parameters to VMEM + */ +void +ia_css_iefd2_6_vmem_encode( + struct iefd2_6_vmem_params *to, + const struct ia_css_iefd2_6_config *from, + size_t size) +{ + const unsigned total_blocks = 4; + const unsigned shuffle_block = 16; + unsigned i, j, base; + (void)size; + + /* For configurable units parameters are copied to vmem. Per CU 3 arrays are copied: + * x containing the x coordinates + * a containing the slopes + * b containing the intercept values. + * + * A 64 element vector is split up in 4 blocks of 16 element. Each array is copied to + * a vector 4 times, (starting at 0, 16, 32 and 48). All array elements are copied or + * initialised as described in the KFS. The remaining elements of a vector are set to 0. + */ + /* first init the vectors */ + for(i = 0; i < total_blocks*shuffle_block; i++) { + to->e_cued_x[0][i] = 0; + to->e_cued_a[0][i] = 0; + to->e_cued_b[0][i] = 0; + + to->e_cu_dir_x[0][i] = 0; + to->e_cu_dir_a[0][i] = 0; + to->e_cu_dir_b[0][i] = 0; + + to->e_cu_non_dir_x[0][i] = 0; + to->e_cu_non_dir_a[0][i] = 0; + to->e_cu_non_dir_b[0][i] = 0; + + to->e_curad_x[0][i] = 0; + to->e_curad_a[0][i] = 0; + to->e_curad_b[0][i] = 0; + } + + /* Copy all data */ + for(i = 0; i < total_blocks; i++) { + base = shuffle_block*i; + + + to->e_cued_x[0][base] = 0; + to->e_cued_a[0][base] = 0; + to->e_cued_b[0][base] = from->cu_ed_slopes_b[0]; + + to->e_cu_dir_x[0][base] = 0; + to->e_cu_dir_a[0][base] = 0; + to->e_cu_dir_b[0][base] = from->cu_dir_sharp_slopes_b[0]; + + to->e_cu_non_dir_x[0][base] = 0; + to->e_cu_non_dir_a[0][base] = 0; + to->e_cu_non_dir_b[0][base] = from->cu_non_dir_sharp_slopes_b[0]; + + to->e_curad_x[0][base] = 0; + to->e_curad_a[0][base] = 0; + to->e_curad_b[0][base] = from->cu_radial_slopes_b[0]; + + for (j = 1; j < 4; j++) { + to->e_cu_dir_a[0][base+j] = from->cu_dir_sharp_slopes_a[j-1]; + to->e_cu_dir_b[0][base+j] = from->cu_dir_sharp_slopes_b[j-1]; + to->e_cu_non_dir_a[0][base+j] = from->cu_non_dir_sharp_slopes_a[j-1]; + to->e_cu_non_dir_b[0][base+j] = from->cu_non_dir_sharp_slopes_b[j-1]; + } + + for (j = 1; j < 5; j++) { + to->e_cu_dir_x[0][base+j] = from->cu_dir_sharp_points_x[j-1]; + to->e_cu_non_dir_x[0][base+j] = from->cu_non_dir_sharp_points_x[j-1]; + } + + + for (j = 1; j < 6; j++) { + to->e_cued_x[0][base+j] = from->cu_ed_points_x[j-1]; + to->e_cued_a[0][base+j] = from->cu_ed_slopes_a[j-1]; + to->e_cued_b[0][base+j] = from->cu_ed_slopes_b[j-1]; + } + to->e_cued_x[0][base+6] = from->cu_ed_points_x[5]; + + for (j = 1; j < 6; j++) { + to->e_curad_x[0][base+j] = from->cu_radial_points_x[j-1]; + to->e_curad_a[0][base+j] = from->cu_radial_slopes_a[j-1]; + to->e_curad_b[0][base+j] = from->cu_radial_slopes_b[j-1]; + } + to->e_curad_x[0][base+6] = from->cu_radial_points_x[5]; + + /* Init asrrnd_lut */ + to->asrrnd_lut[0][base] = 8192; + to->asrrnd_lut[0][base+1] = 4096; + to->asrrnd_lut[0][base+2] = 2048; + to->asrrnd_lut[0][base+3] = 1024; + to->asrrnd_lut[0][base+4] = 512; + to->asrrnd_lut[0][base+5] = 256; + to->asrrnd_lut[0][base+6] = 128; + to->asrrnd_lut[0][base+7] = 64; + to->asrrnd_lut[0][base+8] = 32; + } + +} + +void +ia_css_iefd2_6_encode( + struct iefd2_6_dmem_params *to, + const struct ia_css_iefd2_6_config *from, + size_t size) +{ + (void)size; + + /* Copy parameters to dmem, as described in the KFS + */ + to->horver_diag_coeff = from->horver_diag_coeff; + to->ed_horver_diag_coeff = from->ed_horver_diag_coeff; + to->dir_smooth_enable = from->dir_smooth_enable; + to->dir_metric_update = from->dir_metric_update; + to->unsharp_c00 = from->unsharp_c00; + to->unsharp_c01 = from->unsharp_c01; + to->unsharp_c02 = from->unsharp_c02; + to->unsharp_c11 = from->unsharp_c11; + to->unsharp_c12 = from->unsharp_c12; + to->unsharp_c22 = from->unsharp_c22; + to->unsharp_weight = from->unsharp_weight; + to->unsharp_amount = from->unsharp_amount; + to->cu_dir_sharp_pow = from->cu_dir_sharp_pow; + to->cu_dir_sharp_pow_bright = from->cu_dir_sharp_pow_bright; + to->cu_non_dir_sharp_pow = from->cu_non_dir_sharp_pow; + to->cu_non_dir_sharp_pow_bright = from->cu_non_dir_sharp_pow_bright; + to->dir_far_sharp_weight = from->dir_far_sharp_weight; + to->rad_cu_dir_sharp_x1 = from->rad_cu_dir_sharp_x1; + to->rad_cu_non_dir_sharp_x1 = from->rad_cu_non_dir_sharp_x1; + to->rad_dir_far_sharp_weight = from->rad_dir_far_sharp_weight; + to->sharp_nega_lmt_txt = from->sharp_nega_lmt_txt; + to->sharp_posi_lmt_txt = from->sharp_posi_lmt_txt; + to->sharp_nega_lmt_dir = from->sharp_nega_lmt_dir; + to->sharp_posi_lmt_dir = from->sharp_posi_lmt_dir; + to->clamp_stitch = from->clamp_stitch; + to->rad_enable = from->rad_enable; + to->rad_x_origin = from->rad_x_origin; + to->rad_y_origin = from->rad_y_origin; + to->rad_nf = from->rad_nf; + to->rad_inv_r2 = from->rad_inv_r2; + to->vssnlm_enable = from->vssnlm_enable; + to->vssnlm_x0 = from->vssnlm_x0; + to->vssnlm_x1 = from->vssnlm_x1; + to->vssnlm_x2 = from->vssnlm_x2; + to->vssnlm_y1 = from->vssnlm_y1; + to->vssnlm_y2 = from->vssnlm_y2; + to->vssnlm_y3 = from->vssnlm_y3; + + /* Setup for configurable units */ + to->e_cued2_a = from->cu_ed2_slopes_a; + to->e_cu_vssnlm_a = from->cu_vssnlm_slopes_a; + to->e_cued2_x1 = from->cu_ed2_points_x[0]; + to->e_cued2_x_diff = from->cu_ed2_points_x[1] - from->cu_ed2_points_x[0]; + to->e_cu_vssnlm_x1 = from->cu_vssnlm_points_x[0]; + to->e_cu_vssnlm_x_diff = from->cu_vssnlm_points_x[1] - from->cu_vssnlm_points_x[0]; +} + +/* TODO: AM: This needs a proper implementation. */ +void +ia_css_init_iefd2_6_state( + void *state, + size_t size) +{ + (void)state; + (void)size; +} + +#ifndef IA_CSS_NO_DEBUG +/* TODO: AM: This needs a proper implementation. */ +void +ia_css_iefd2_6_debug_dtrace( + const struct ia_css_iefd2_6_config *config, + unsigned level) +{ + (void)config; + (void)level; +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6.host.h new file mode 100644 index 0000000000000000000000000000000000000000..580d51fe9b2a0bb4efaf1408ed2f3863d4010087 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6.host.h @@ -0,0 +1,46 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_IEFD2_6_HOST_H +#define __IA_CSS_IEFD2_6_HOST_H + +#include "ia_css_iefd2_6_types.h" +#include "ia_css_iefd2_6_param.h" +#include "ia_css_iefd2_6_default.host.h" + +void +ia_css_iefd2_6_vmem_encode( + struct iefd2_6_vmem_params *to, + const struct ia_css_iefd2_6_config *from, + size_t size); + +void +ia_css_iefd2_6_encode( + struct iefd2_6_dmem_params *to, + const struct ia_css_iefd2_6_config *from, + size_t size); + +void +ia_css_init_iefd2_6_state( + void *state, + size_t size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_iefd2_6_debug_dtrace( + const struct ia_css_iefd2_6_config *config, unsigned level) +; +#endif + +#endif /* __IA_CSS_IEFD2_6_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6_default.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6_default.host.c new file mode 100644 index 0000000000000000000000000000000000000000..b43ffd89c5bc2d684f76c42f407e459a2a0e6d65 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6_default.host.c @@ -0,0 +1,144 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_iefd2_6_types.h" + +const struct ia_css_iefd2_6_config default_iefd2_6_config = { + .horver_diag_coeff = 45, + .ed_horver_diag_coeff = 64, + .dir_smooth_enable = true, + .dir_metric_update = 16, + .unsharp_c00 = 60, + .unsharp_c01 = 30, + .unsharp_c02 = 16, + .unsharp_c11 = 1, + .unsharp_c12 = 2, + .unsharp_c22 = 0, + .unsharp_weight = 32, + .unsharp_amount = 128, + .cu_dir_sharp_pow = 20, + .cu_dir_sharp_pow_bright = 20, + .cu_non_dir_sharp_pow = 24, + .cu_non_dir_sharp_pow_bright = 24, + .dir_far_sharp_weight = 2, + .rad_cu_dir_sharp_x1 = 0, + .rad_cu_non_dir_sharp_x1 = 128, + .rad_dir_far_sharp_weight = 8, + .sharp_nega_lmt_txt = 1024, + .sharp_posi_lmt_txt = 1024, + .sharp_nega_lmt_dir = 128, + .sharp_posi_lmt_dir = 128, + .clamp_stitch = 0, + .rad_enable = true, + .rad_x_origin = 0, + .rad_y_origin = 0, + .rad_nf = 7, + .rad_inv_r2 = 157, + .vssnlm_enable = true, + .vssnlm_x0 = 24, + .vssnlm_x1 = 96, + .vssnlm_x2 = 172, + .vssnlm_y1 = 1, + .vssnlm_y2 = 3, + .vssnlm_y3 = 8, + .cu_ed_points_x = { + 0, + 256, + 656, + 2456, + 3272, + 4095 + }, + .cu_ed_slopes_a = { + 4, + 160, + 0, + 0, + 0 + }, + .cu_ed_slopes_b = { + 0, + 9, + 510, + 511, + 511 + }, + .cu_ed2_points_x = { + 218, + 308 + }, + .cu_ed2_slopes_a = 11, + .cu_ed2_slopes_b = 0, + .cu_dir_sharp_points_x = { + 247, + 298, + 342, + 448 + }, + .cu_dir_sharp_slopes_a = { + 14, + 4, + 0 + }, + .cu_dir_sharp_slopes_b = { + 1, + 46, + 58 + }, + .cu_non_dir_sharp_points_x = { + 26, + 45, + 81, + 500 + }, + .cu_non_dir_sharp_slopes_a = { + 39, + 7, + 0 + }, + .cu_non_dir_sharp_slopes_b = { + 1, + 47, + 63 + }, + .cu_radial_points_x = { + 50, + 86, + 142, + 189, + 224, + 255 + }, + .cu_radial_slopes_a = { + 713, + 278, + 295, + 286, + -1 + }, + .cu_radial_slopes_b = { + 1, + 101, + 162, + 216, + 255 + }, + .cu_vssnlm_points_x = { + 100, + 141 + }, + .cu_vssnlm_slopes_a = 25, + .cu_vssnlm_slopes_b = 0 +}; + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6_default.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6_default.host.h new file mode 100644 index 0000000000000000000000000000000000000000..38f06de5df0d34dfcf368f092a33dff0523b4477 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6_default.host.h @@ -0,0 +1,23 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_IEFD2_6_DEFAULT_HOST_H +#define __IA_CSS_IEFD2_6_DEFAULT_HOST_H + +#include "ia_css_iefd2_6_types.h" + +extern const struct ia_css_iefd2_6_config default_iefd2_6_config; + +#endif /* __IA_CSS_IEFD2_6_DEFAULT_HOST_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6_param.h new file mode 100644 index 0000000000000000000000000000000000000000..307909688bd88d12e572a2fe4231e09108edfe51 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6_param.h @@ -0,0 +1,83 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_IEFD2_6_PARAM_H +#define __IA_CSS_IEFD2_6_PARAM_H + +#include "type_support.h" +#include "vmem.h" /* needed for VMEM_ARRAY */ + +struct iefd2_6_vmem_params { + VMEM_ARRAY(e_cued_x, ISP_VEC_NELEMS); + VMEM_ARRAY(e_cued_a, ISP_VEC_NELEMS); + VMEM_ARRAY(e_cued_b, ISP_VEC_NELEMS); + VMEM_ARRAY(e_cu_dir_x, ISP_VEC_NELEMS); + VMEM_ARRAY(e_cu_dir_a, ISP_VEC_NELEMS); + VMEM_ARRAY(e_cu_dir_b, ISP_VEC_NELEMS); + VMEM_ARRAY(e_cu_non_dir_x, ISP_VEC_NELEMS); + VMEM_ARRAY(e_cu_non_dir_a, ISP_VEC_NELEMS); + VMEM_ARRAY(e_cu_non_dir_b, ISP_VEC_NELEMS); + VMEM_ARRAY(e_curad_x, ISP_VEC_NELEMS); + VMEM_ARRAY(e_curad_a, ISP_VEC_NELEMS); + VMEM_ARRAY(e_curad_b, ISP_VEC_NELEMS); + VMEM_ARRAY(asrrnd_lut, ISP_VEC_NELEMS); +}; + +struct iefd2_6_dmem_params { + int32_t horver_diag_coeff; + int32_t ed_horver_diag_coeff; + bool dir_smooth_enable; + int32_t dir_metric_update; + int32_t unsharp_c00; + int32_t unsharp_c01; + int32_t unsharp_c02; + int32_t unsharp_c11; + int32_t unsharp_c12; + int32_t unsharp_c22; + int32_t unsharp_weight; + int32_t unsharp_amount; + int32_t cu_dir_sharp_pow; + int32_t cu_dir_sharp_pow_bright; + int32_t cu_non_dir_sharp_pow; + int32_t cu_non_dir_sharp_pow_bright; + int32_t dir_far_sharp_weight; + int32_t rad_cu_dir_sharp_x1; + int32_t rad_cu_non_dir_sharp_x1; + int32_t rad_dir_far_sharp_weight; + int32_t sharp_nega_lmt_txt; + int32_t sharp_posi_lmt_txt; + int32_t sharp_nega_lmt_dir; + int32_t sharp_posi_lmt_dir; + int32_t clamp_stitch; + bool rad_enable; + int32_t rad_x_origin; + int32_t rad_y_origin; + int32_t rad_nf; + int32_t rad_inv_r2; + bool vssnlm_enable; + int32_t vssnlm_x0; + int32_t vssnlm_x1; + int32_t vssnlm_x2; + int32_t vssnlm_y1; + int32_t vssnlm_y2; + int32_t vssnlm_y3; + int32_t e_cued2_a; + int32_t e_cued2_x1; + int32_t e_cued2_x_diff; + int32_t e_cu_vssnlm_a; + int32_t e_cu_vssnlm_x1; + int32_t e_cu_vssnlm_x_diff; +}; + +#endif /* __IA_CSS_IEFD2_6_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6_state.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6_state.h new file mode 100644 index 0000000000000000000000000000000000000000..0915f1467414af39c7ef1d9979517e6a6fec59cc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6_state.h @@ -0,0 +1,32 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_IEFD2_6_STATE_H +#define _IA_CSS_IEFD2_6_STATE_H + +#include "type_support.h" +#include "vmem.h" /* for VMEM_ARRAY*/ +#include "iefd2_6_vssnlm.isp.h" +#include "iefd2_6.isp.h" + +struct iefd2_6_vmem_state { + /* State buffers required for main IEFD2_6 */ + VMEM_ARRAY(iefd2_6_input_lines[IEFD2_6_STATE_INPUT_BUFFER_HEIGHT], IEFD2_6_STATE_INPUT_BUFFER_WIDTH*ISP_NWAY); + /* State buffers required for VSSNLM sub-kernel */ + VMEM_ARRAY(vssnlm_input_y[VSSNLM_STATE_INPUT_BUFFER_HEIGHT], VSSNLM_STATE_INPUT_BUFFER_WIDTH*ISP_NWAY); + VMEM_ARRAY(vssnlm_input_diff_grad[1], VSSNLM_STATE_INPUT_BUFFER_WIDTH*ISP_NWAY); +}; + +#endif /* _IA_CSS_IEFD2_6_STATE_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6_types.h new file mode 100644 index 0000000000000000000000000000000000000000..b0eadab42537b5d38d62ab87adb1a64b9a6c2eb5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iefd2_6/ia_css_iefd2_6_types.h @@ -0,0 +1,164 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_IEFD2_6_TYPES_H +#define __IA_CSS_IEFD2_6_TYPES_H + +/** @file +* CSS-API header file for Image Enhancement Filter directed algorithm parameters. +*/ + +#include "type_support.h" + +/** Image Enhancement Filter directed configuration + * + * ISP2.6.1: IEFd2_6 is used. + */ + +struct ia_css_iefd2_6_config { + int32_t horver_diag_coeff; /**< Coefficient that compensates for different + distance for vertical/horizontal and + diagonal gradient calculation (~1/sqrt(2)). + u1.6, [0,64], default 45, ineffective 0 */ + int32_t ed_horver_diag_coeff; /**< Radial Coefficient that compensates for + different distance for vertical/horizontal + and diagonal gradient calculation (~1/sqrt(2)). + u1.6, [0,64], default 64, ineffective 0 */ + bool dir_smooth_enable; /**< Enable smooth best direction with second best. + bool, [false, true], default true, ineffective false */ + int32_t dir_metric_update; /**< Update coefficient for direction metric. + u1.4, [0,31], default 16, ineffective 0 */ + int32_t unsharp_c00; /**< Unsharp Mask filter coefs 0,0 (center). + s0.8, [-256,255], default 60, ineffective 255 */ + int32_t unsharp_c01; /**< Unsharp Mask filter coefs 0,1. + s0.8, [-256,255], default 30, ineffective 0 */ + int32_t unsharp_c02; /**< Unsharp Mask filter coefs 0,2. + s0.8, [-256,255], default 16, ineffective 0 */ + int32_t unsharp_c11; /**< Unsharp Mask filter coefs 1,1. + s0.8, [-256,255], default 1, ineffective 0 */ + int32_t unsharp_c12; /**< Unsharp Mask filter coefs 1,2. + s1.8, [-512,511], default 2, ineffective 0 */ + int32_t unsharp_c22; /**< Unsharp Mask filter coefs 2,2. + s0.8, [-256,255], default 0, ineffective 0 */ + int32_t unsharp_weight; /**< Unsharp Mask blending weight. + u1.12, [0,4096], default 32, ineffective 0 */ + int32_t unsharp_amount; /**< Unsharp Mask amount. + u3.6, [0,511], default 128, ineffective 0 */ + int32_t cu_dir_sharp_pow; /**< Power of cu_dir_sharp (power of direct sharpening). + u2.4, [0,63], default 20, ineffective 0 */ + int32_t cu_dir_sharp_pow_bright; /**< Power of cu_dir_sharp (power of direct sharpening) for + Bright. + u2.4, [0,63], default 20, ineffective 0 */ + int32_t cu_non_dir_sharp_pow; /**< Power of cu_non_dir_sharp (power of unsharp mask). + u2.4, [0,63], default 24, ineffective 0 */ + int32_t cu_non_dir_sharp_pow_bright; /**< Power of cu_non_dir_sharp (power of unsharp mask) + for Bright. + u2.4, [0,63], default 24, ineffective 0 */ + int32_t dir_far_sharp_weight; /**< Weight of wide direct sharpening. + u1.12, [0,4096], default 2, ineffective 0 */ + int32_t rad_cu_dir_sharp_x1; /**< X1point of cu_dir_sharp for radial/corner point. + u9.0, [0,511], default 0, ineffective 0 */ + int32_t rad_cu_non_dir_sharp_x1; /**< X1 point for cu_non_dir_sharp for radial/corner point. + u9.0, [0,511], default 128, ineffective 0 */ + int32_t rad_dir_far_sharp_weight; /**< Weight of wide direct sharpening. + u1.12, [0,4096], default 8, ineffective 0 */ + int32_t sharp_nega_lmt_txt; /**< Sharpening limit for negative overshoots for texture. + u13.0, [0,8191], default 1024, ineffective 0 */ + int32_t sharp_posi_lmt_txt; /**< Sharpening limit for positive overshoots for texture. + u13.0, [0,8191], default 1024, ineffective 0 */ + int32_t sharp_nega_lmt_dir; /**< Sharpening limit for negative overshoots for direction + (edge). + u13.0, [0,8191], default 128, ineffective 0 */ + int32_t sharp_posi_lmt_dir; /**< Sharpening limit for positive overshoots for direction + (edge). + u13.0, [0,8191], default 128, ineffective 0 */ + int32_t clamp_stitch; /**< Slope to stitch between clamped and unclamped edge values. + u6.0, [0,63], default 0, ineffective 0 */ + bool rad_enable; /**< Enable bit to update radial dependent parameters. + bool, [false,true], default true, ineffective false */ + int32_t rad_x_origin; /**< Initial x coord. for radius computation. + s13.0, [-8192,8191], default 0, ineffective 0 */ + int32_t rad_y_origin; /**< Initial y coord. for radius computation. + s13.0, [-8192,8191], default 0, ineffective 0 */ + int32_t rad_nf; /**< Radial. R^2 normalization factor is scale down by + 2^-(15+scale). + u4.0, [0,15], default 7, ineffective 0 */ + int32_t rad_inv_r2; /**< Radial R^-2 normelized to (0.5..1). + u(8-m_rad_NF).m_rad_NF, [0,255], default 157, + ineffective 0 */ + bool vssnlm_enable; /**< Enable bit to use VSSNLM output filter. + bool, [false, true], default true, ineffective false */ + int32_t vssnlm_x0; /**< Vssnlm LUT x0. + u8.0, [0,255], default 24, ineffective 0 */ + int32_t vssnlm_x1; /**< Vssnlm LUT x1. + u8.0, [0,255], default 96, ineffective 0 */ + int32_t vssnlm_x2; /**< Vssnlm LUT x2. + u8.0, [0,255], default 172, ineffective 0 */ + int32_t vssnlm_y1; /**< Vssnlm LUT y1. + u4.0, [0,8], default 1, ineffective 8 */ + int32_t vssnlm_y2; /**< Vssnlm LUT y2. + u4.0, [0,8], default 3, ineffective 8 */ + int32_t vssnlm_y3; /**< Vssnlm LUT y3. + u4.0, [0,8], default 8, ineffective 8 */ + int32_t cu_ed_points_x[6]; /**< PointsX of config unit ED. + u0.12, [0,4095], default 0,256,656,2456,3272,4095, + ineffective 0,0,0,0,0,0 */ + int32_t cu_ed_slopes_a[5]; /**< SlopesA of config unit ED. + s6.7, [-8192, 8191], default 4,160,0,0,0, + ineffective 0,0,0,0,0 */ + int32_t cu_ed_slopes_b[5]; /**< SlopesB of config unit ED. + u0.9, [0,511], default 0,9,510,511,511, + ineffective 0,0,0,0,0 */ + int32_t cu_ed2_points_x[2]; /**< PointsX of config unit ED2.. + u0.9, [0,511], default 218,308, ineffective 0,0 */ + int32_t cu_ed2_slopes_a; /**< SlopesA of config unit ED2. + s7,4, [-1024, 1024]. default 11, ineffective 0 */ + int32_t cu_ed2_slopes_b; /**< SlopesB of config unit ED2. + u1.6, [0,0], default 0, ineffective 0 */ + int32_t cu_dir_sharp_points_x[4]; /**< PointsX of config unit DirSharp. + u0.9, [0,511], default 247,298,342,448, + ineffective 0,0,0,0 */ + int32_t cu_dir_sharp_slopes_a[3]; /**< SlopesA of config unit DirSharp + s7,4, [0,511], default 14,4,0, ineffective 0,0,0 */ + int32_t cu_dir_sharp_slopes_b[3]; /**< SlopesB of config unit DirSharp. + u1.6, [0,64], default 1,46,58, ineffective 0,0,0 */ + int32_t cu_non_dir_sharp_points_x[4]; /**< PointsX of config unit NonDirSharp. + u0.9, [0,511], default 26,45,81,500, + ineffective 0,0,0,0 */ + int32_t cu_non_dir_sharp_slopes_a[3]; /**< SlopesA of config unit NonDirSharp. + s7.4, [-1024, 1024], default 39,7,0, + ineffective 0,0,0 */ + int32_t cu_non_dir_sharp_slopes_b[3]; /**< SlopesB of config unit NonDirSharp. + u1.6, [0,64], default 1,47,63, + ineffective 0,0,0 */ + int32_t cu_radial_points_x[6]; /**< PointsX of Config Unit Radial. + u0.8, [0,255], default 50,86,142,189,224,255, + ineffective 0,0,0,0,0,0 */ + int32_t cu_radial_slopes_a[5]; /**< SlopesA of Config Unit Radial. + s5.8, [-8192, 8191], default 713,278,295,286,-1, + ineffective 0,0,0,0,0 */ + int32_t cu_radial_slopes_b[5]; /**< SlopesB of Config Unit Radial. + u0.8, [0,255], default 1,101,162,216,255, + ineffective 0,0,0,0,0 */ + int32_t cu_vssnlm_points_x[2]; /**< PointsX of config unit VSSNLM. + u0.9, [0,511], default 100,141, ineffective 0,0 */ + int32_t cu_vssnlm_slopes_a; /**< SlopesA of config unit VSSNLM. + s7.4, [-1024,1024], default 25, ineffective 0 */ + int32_t cu_vssnlm_slopes_b; /**< SlopesB of config unit VSSNLM. + u1.6, [0,0], default 0, ineffective 0 */ +}; + + +#endif /* __IA_CSS_IEFD2_6_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/bayer_io_ls/ia_css_bayer_io.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/bayer_io_ls/ia_css_bayer_io.host.c new file mode 100644 index 0000000000000000000000000000000000000000..a31c9e828e22543f11b7a97b932a0ebef8058b4f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/bayer_io_ls/ia_css_bayer_io.host.c @@ -0,0 +1,86 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_bayer_io.host.h" +#include "dma.h" +#include "math_support.h" +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" +#endif +#include "ia_css_isp_params.h" +#include "ia_css_frame.h" + +void +ia_css_bayer_io_config( + const struct ia_css_binary *binary, + const struct sh_css_binary_args *args) +{ + const struct ia_css_frame *in_frame = args->in_frame; + const struct ia_css_frame **out_frames = (const struct ia_css_frame **)& args->out_frame; + const struct ia_css_frame_info *in_frame_info = (in_frame) ? &in_frame->info : &binary->in_frame_info; + + const unsigned ddr_bits_per_element = sizeof(short) * 8; + const unsigned ddr_elems_per_word = ceil_div(HIVE_ISP_DDR_WORD_BITS, ddr_bits_per_element); + unsigned size_get = 0, size_put = 0; + unsigned offset = 0; + + if (binary->info->mem_offsets.offsets.param) { + size_get = binary->info->mem_offsets.offsets.param->dmem.get.size; + offset = binary->info->mem_offsets.offsets.param->dmem.get.offset; + } + + if (size_get) { + struct ia_css_common_io_config *to = (struct ia_css_common_io_config *)&binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; + struct dma_port_config config; +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_bayer_io_config() get part enter:\n"); +#endif + + ia_css_dma_configure_from_info(&config, in_frame_info); + // The base_address of the input frame will be set in the ISP + to->width = in_frame_info->res.width; + to->height = in_frame_info->res.height; + to->stride = config.stride; + to->ddr_elems_per_word = ddr_elems_per_word; +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_bayer_io_config() get part leave:\n"); +#endif + } + + if (binary->info->mem_offsets.offsets.param) { + size_put = binary->info->mem_offsets.offsets.param->dmem.put.size; + offset = binary->info->mem_offsets.offsets.param->dmem.put.offset; + } + + if (size_put) { + struct ia_css_common_io_config *to = (struct ia_css_common_io_config *)&binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; + struct dma_port_config config; +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_bayer_io_config() put part enter:\n"); +#endif + + ia_css_dma_configure_from_info(&config, &out_frames[0]->info); + to->base_address = out_frames[0]->data; + to->width = out_frames[0]->info.res.width; + to->height = out_frames[0]->info.res.height; + to->stride = config.stride; + to->ddr_elems_per_word = ddr_elems_per_word; + +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_bayer_io_config() put part leave:\n"); +#endif + } +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/bayer_io_ls/ia_css_bayer_io.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/bayer_io_ls/ia_css_bayer_io.host.h new file mode 100644 index 0000000000000000000000000000000000000000..7e5d4cfe3454a88a43e226b4e7fd10a167cbdb40 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/bayer_io_ls/ia_css_bayer_io.host.h @@ -0,0 +1,31 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __BAYER_IO_HOST_H +#define __BAYER_IO_HOST_H + +#include "ia_css_bayer_io_param.h" +#include "ia_css_bayer_io_types.h" +#include "ia_css_binary.h" +#include "sh_css_internal.h" + + +void +ia_css_bayer_io_config( + const struct ia_css_binary *binary, + const struct sh_css_binary_args *args); + +#endif /*__BAYER_IO_HOST_H */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/bayer_io_ls/ia_css_bayer_io_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/bayer_io_ls/ia_css_bayer_io_param.h new file mode 100644 index 0000000000000000000000000000000000000000..7b6f581c4a803353030d065865f8218721972617 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/bayer_io_ls/ia_css_bayer_io_param.h @@ -0,0 +1,22 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BAYER_IO_PARAM +#define __IA_CSS_BAYER_IO_PARAM + +#include "../common/ia_css_common_io_param.h" + +#endif /* __IA_CSS_BAYER_IO_PARAM */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/bayer_io_ls/ia_css_bayer_io_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/bayer_io_ls/ia_css_bayer_io_types.h new file mode 100644 index 0000000000000000000000000000000000000000..2291b01452f8a5bf03768acb790f1ed4b63e2438 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/bayer_io_ls/ia_css_bayer_io_types.h @@ -0,0 +1,22 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_BAYER_IO_TYPES_H +#define __IA_CSS_BAYER_IO_TYPES_H + +#include "../common/ia_css_common_io_types.h" + +#endif /* __IA_CSS_BAYER_IO_TYPES_H */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/common/ia_css_common_io_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/common/ia_css_common_io_param.h new file mode 100644 index 0000000000000000000000000000000000000000..f1ce03aa7951a243fda99cb8484280b436b7bd1f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/common/ia_css_common_io_param.h @@ -0,0 +1,22 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_COMMON_IO_PARAM +#define __IA_CSS_COMMON_IO_PARAM + +#include "../common/ia_css_common_io_types.h" + +#endif /* __IA_CSS_COMMON_IO_PARAM */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/common/ia_css_common_io_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/common/ia_css_common_io_types.h new file mode 100644 index 0000000000000000000000000000000000000000..8a9a97063264859479f30a7e46ab550afb8cd5dc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/common/ia_css_common_io_types.h @@ -0,0 +1,31 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_COMMON_IO_TYPES +#define __IA_CSS_COMMON_IO_TYPES + +#define MAX_IO_DMA_CHANNELS 2 + +struct ia_css_common_io_config { + unsigned base_address; + unsigned width; + unsigned height; + unsigned stride; + unsigned ddr_elems_per_word; + unsigned dma_channel[MAX_IO_DMA_CHANNELS]; +}; + +#endif /* __IA_CSS_COMMON_IO_TYPES */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/plane_io_ls/ia_css_plane_io_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/plane_io_ls/ia_css_plane_io_param.h new file mode 100644 index 0000000000000000000000000000000000000000..213ef3b385aabc385d017e2a0ac0762c2d8246da --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/plane_io_ls/ia_css_plane_io_param.h @@ -0,0 +1,22 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PLANE_IO_PARAM_H +#define __IA_CSS_PLANE_IO_PARAM_H + +#include "../common/ia_css_common_io_param.h" + +#endif /* __IA_CSS_PLANE_IO_PARAM_H */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/plane_io_ls/ia_css_plane_io_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/plane_io_ls/ia_css_plane_io_types.h new file mode 100644 index 0000000000000000000000000000000000000000..d635741505e2952afb0b2304f0c9c380625bbd8c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/plane_io_ls/ia_css_plane_io_types.h @@ -0,0 +1,30 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PLANE_IO_TYPES_H +#define __IA_CSS_PLANE_IO_TYPES_H + +#include "../common/ia_css_common_io_types.h" + +#define PLANE_IO_LS_NUM_PLANES 3 + +struct ia_css_plane_io_config { + struct ia_css_common_io_config get_plane_io_config[PLANE_IO_LS_NUM_PLANES]; + struct ia_css_common_io_config put_plane_io_config[PLANE_IO_LS_NUM_PLANES]; +}; + +#endif /* __IA_CSS_PLANE_IO_TYPES_H */ + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/yuv420_io_ls/ia_css_yuv420_io_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/yuv420_io_ls/ia_css_yuv420_io_param.h new file mode 100644 index 0000000000000000000000000000000000000000..52450a9a55a1c58af4bf0ba20800eeb070de6d36 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/yuv420_io_ls/ia_css_yuv420_io_param.h @@ -0,0 +1,22 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YUV420_IO_PARAM +#define __IA_CSS_YUV420_IO_PARAM + +#include "../common/ia_css_common_io_param.h" + +#endif +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/yuv420_io_ls/ia_css_yuv420_io_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/yuv420_io_ls/ia_css_yuv420_io_types.h new file mode 100644 index 0000000000000000000000000000000000000000..99ec1143b214da8d96e6cea83e2844cf0ae990b8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/yuv420_io_ls/ia_css_yuv420_io_types.h @@ -0,0 +1,22 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YUV420_IO_TYPES +#define __IA_CSS_YUV420_IO_TYPES + +#include "../common/ia_css_common_io_types.h" + +#endif +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/yuv444_io_ls/ia_css_yuv444_io_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/yuv444_io_ls/ia_css_yuv444_io_param.h new file mode 100644 index 0000000000000000000000000000000000000000..91fb5168c357f53c0716e51fcda47a9ed2b2b44e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/yuv444_io_ls/ia_css_yuv444_io_param.h @@ -0,0 +1,22 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YUV444_IO_PARAM +#define __IA_CSS_YUV444_IO_PARAM + +#include "../common/ia_css_common_io_param.h" + +#endif +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/yuv444_io_ls/ia_css_yuv444_io_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/yuv444_io_ls/ia_css_yuv444_io_types.h new file mode 100644 index 0000000000000000000000000000000000000000..dac44030939486a937eb68bfdc749f2d86fbd82e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/io_ls/yuv444_io_ls/ia_css_yuv444_io_types.h @@ -0,0 +1,22 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YUV444_IO_TYPES +#define __IA_CSS_YUV444_IO_TYPES + +#include "../common/ia_css_common_io_types.h" + +#endif +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io.host.c new file mode 100644 index 0000000000000000000000000000000000000000..78e159c04851d6cb225e5e041fac14db35acf58f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io.host.c @@ -0,0 +1,86 @@ +#ifdef ISP2401 +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#include "ia_css_bayer_io.host.h" +#include "dma.h" +#include "math_support.h" +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" +#endif +#include "ia_css_isp_params.h" +#include "ia_css_frame.h" + +void +ia_css_bayer_io_config( + const struct ia_css_binary *binary, + const struct sh_css_binary_args *args) +{ + const struct ia_css_frame *in_frame = args->in_frame; + const struct ia_css_frame **out_frames = (const struct ia_css_frame **)& args->out_frame; + const struct ia_css_frame_info *in_frame_info = (in_frame) ? &in_frame->info : &binary->in_frame_info; + + const unsigned ddr_bits_per_element = sizeof(short) * 8; + const unsigned ddr_elems_per_word = ceil_div(HIVE_ISP_DDR_WORD_BITS, ddr_bits_per_element); + unsigned size_get = 0, size_put = 0; + unsigned offset = 0; + + if (binary->info->mem_offsets.offsets.param) { + size_get = binary->info->mem_offsets.offsets.param->dmem.get.size; + offset = binary->info->mem_offsets.offsets.param->dmem.get.offset; + } + + if (size_get) { + struct ia_css_common_io_config *to = (struct ia_css_common_io_config *)&binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; + struct dma_port_config config; +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_bayer_io_config() get part enter:\n"); +#endif + + ia_css_dma_configure_from_info(&config, in_frame_info); + // The base_address of the input frame will be set in the ISP + to->width = in_frame_info->res.width; + to->height = in_frame_info->res.height; + to->stride = config.stride; + to->ddr_elems_per_word = ddr_elems_per_word; +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_bayer_io_config() get part leave:\n"); +#endif + } + + if (binary->info->mem_offsets.offsets.param) { + size_put = binary->info->mem_offsets.offsets.param->dmem.put.size; + offset = binary->info->mem_offsets.offsets.param->dmem.put.offset; + } + + if (size_put) { + struct ia_css_common_io_config *to = (struct ia_css_common_io_config *)&binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; + struct dma_port_config config; +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_bayer_io_config() put part enter:\n"); +#endif + + ia_css_dma_configure_from_info(&config, &out_frames[0]->info); + to->base_address = out_frames[0]->data; + to->width = out_frames[0]->info.res.width; + to->height = out_frames[0]->info.res.height; + to->stride = config.stride; + to->ddr_elems_per_word = ddr_elems_per_word; + +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_bayer_io_config() put part leave:\n"); +#endif + } +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io.host.h new file mode 100644 index 0000000000000000000000000000000000000000..ab9fa31bfc5ee868b3c9f4505e6fe2b9cc121990 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io.host.h @@ -0,0 +1,31 @@ +#ifdef ISP2401 +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __BAYER_IO_HOST_H +#define __BAYER_IO_HOST_H + +#include "ia_css_bayer_io_param.h" +#include "ia_css_bayer_io_types.h" +#include "ia_css_binary.h" +#include "sh_css_internal.h" + + +void +ia_css_bayer_io_config( + const struct ia_css_binary *binary, + const struct sh_css_binary_args *args); + +#endif /*__BAYER_IO_HOST_H */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io_param.h new file mode 100644 index 0000000000000000000000000000000000000000..bf5a3eccb3307f37b2b44300c06fa574ff90f5d5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io_param.h @@ -0,0 +1,22 @@ +#ifdef ISP2401 +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __IA_CSS_BAYER_IO_PARAM +#define __IA_CSS_BAYER_IO_PARAM + +#include "../common/ia_css_common_io_param.h" + +#endif /* __IA_CSS_BAYER_IO_PARAM */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io_types.h new file mode 100644 index 0000000000000000000000000000000000000000..9e3c622db4d422a10a92d814c900ca807179b3f5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io_types.h @@ -0,0 +1,22 @@ +#ifdef ISP2401 +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __IA_CSS_BAYER_IO_TYPES_H +#define __IA_CSS_BAYER_IO_TYPES_H + +#include "../common/ia_css_common_io_types.h" + +#endif /* __IA_CSS_BAYER_IO_TYPES_H */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/common/ia_css_common_io_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/common/ia_css_common_io_param.h new file mode 100644 index 0000000000000000000000000000000000000000..e5fdcfff0cf7bf620646a6d2ef4b09dc4ce25762 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/common/ia_css_common_io_param.h @@ -0,0 +1,22 @@ +#ifdef ISP2401 +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __IA_CSS_COMMON_IO_PARAM +#define __IA_CSS_COMMON_IO_PARAM + +#include "../common/ia_css_common_io_types.h" + +#endif /* __IA_CSS_COMMON_IO_PARAM */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/common/ia_css_common_io_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/common/ia_css_common_io_types.h new file mode 100644 index 0000000000000000000000000000000000000000..0a19e2d1aff4a219ff5e158d558df501bed8f011 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/common/ia_css_common_io_types.h @@ -0,0 +1,31 @@ +#ifdef ISP2401 +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __IA_CSS_COMMON_IO_TYPES +#define __IA_CSS_COMMON_IO_TYPES + +#define MAX_IO_DMA_CHANNELS 3 + +struct ia_css_common_io_config { + unsigned base_address; + unsigned width; + unsigned height; + unsigned stride; + unsigned ddr_elems_per_word; + unsigned dma_channel[MAX_IO_DMA_CHANNELS]; +}; + +#endif /* __IA_CSS_COMMON_IO_TYPES */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/plane_io_ls/ia_css_plane_io_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/plane_io_ls/ia_css_plane_io_param.h new file mode 100644 index 0000000000000000000000000000000000000000..881b7e5236dce9c63c2f61a812bbb742ceddbd49 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/plane_io_ls/ia_css_plane_io_param.h @@ -0,0 +1,22 @@ +#ifdef ISP2401 +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __IA_CSS_PLANE_IO_PARAM_H +#define __IA_CSS_PLANE_IO_PARAM_H + +#include "../common/ia_css_common_io_param.h" + +#endif /* __IA_CSS_PLANE_IO_PARAM_H */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/plane_io_ls/ia_css_plane_io_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/plane_io_ls/ia_css_plane_io_types.h new file mode 100644 index 0000000000000000000000000000000000000000..f4b9e8de3d8ef99df3a4af1cbaf9859b08520ea3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/plane_io_ls/ia_css_plane_io_types.h @@ -0,0 +1,30 @@ +#ifdef ISP2401 +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __IA_CSS_PLANE_IO_TYPES_H +#define __IA_CSS_PLANE_IO_TYPES_H + +#include "../common/ia_css_common_io_types.h" + +#define PLANE_IO_LS_NUM_PLANES 3 + +struct ia_css_plane_io_config { + struct ia_css_common_io_config get_plane_io_config[PLANE_IO_LS_NUM_PLANES]; + struct ia_css_common_io_config put_plane_io_config[PLANE_IO_LS_NUM_PLANES]; +}; + +#endif /* __IA_CSS_PLANE_IO_TYPES_H */ + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/yuv420_io_ls/ia_css_yuv420_io_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/yuv420_io_ls/ia_css_yuv420_io_param.h new file mode 100644 index 0000000000000000000000000000000000000000..86184b545fede33d19606e9bae0d00adc0a7f573 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/yuv420_io_ls/ia_css_yuv420_io_param.h @@ -0,0 +1,22 @@ +#ifdef ISP2401 +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __IA_CSS_YUV420_IO_PARAM +#define __IA_CSS_YUV420_IO_PARAM + +#include "../common/ia_css_common_io_param.h" + +#endif +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/yuv420_io_ls/ia_css_yuv420_io_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/yuv420_io_ls/ia_css_yuv420_io_types.h new file mode 100644 index 0000000000000000000000000000000000000000..ad750f530013237d8bb7ac18ac42c55f2f195fc3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/yuv420_io_ls/ia_css_yuv420_io_types.h @@ -0,0 +1,22 @@ +#ifdef ISP2401 +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __IA_CSS_YUV420_IO_TYPES +#define __IA_CSS_YUV420_IO_TYPES + +#include "../common/ia_css_common_io_types.h" + +#endif +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io.host.c new file mode 100644 index 0000000000000000000000000000000000000000..f7e1a632c47e4c9ebc938ea4926c52668b527f1e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io.host.c @@ -0,0 +1,86 @@ +#ifdef ISP2401 +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#include "ia_css_yuv444_io.host.h" +#include "dma.h" +#include "math_support.h" +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" +#endif +#include "ia_css_isp_params.h" +#include "ia_css_frame.h" + +void +ia_css_yuv444_io_config( + const struct ia_css_binary *binary, + const struct sh_css_binary_args *args) +{ + const struct ia_css_frame *in_frame = args->in_frame; + const struct ia_css_frame **out_frames = (const struct ia_css_frame **)& args->out_frame; + const struct ia_css_frame_info *in_frame_info = (in_frame) ? &in_frame->info : &binary->in_frame_info; + + const unsigned ddr_bits_per_element = sizeof(short) * 8; + const unsigned ddr_elems_per_word = ceil_div(HIVE_ISP_DDR_WORD_BITS, ddr_bits_per_element); + unsigned size_get = 0, size_put = 0; + unsigned offset = 0; + + if (binary->info->mem_offsets.offsets.param) { + size_get = binary->info->mem_offsets.offsets.param->dmem.get.size; + offset = binary->info->mem_offsets.offsets.param->dmem.get.offset; + } + + if (size_get) { + struct ia_css_common_io_config *to = (struct ia_css_common_io_config *)&binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; + struct dma_port_config config; +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_yuv444_io_config() get part enter:\n"); +#endif + + ia_css_dma_configure_from_info(&config, in_frame_info); + // The base_address of the input frame will be set in the ISP + to->width = in_frame_info->res.width; + to->height = in_frame_info->res.height; + to->stride = config.stride; + to->ddr_elems_per_word = ddr_elems_per_word; +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_yuv444_io_config() get part leave:\n"); +#endif + } + + if (binary->info->mem_offsets.offsets.param) { + size_put = binary->info->mem_offsets.offsets.param->dmem.put.size; + offset = binary->info->mem_offsets.offsets.param->dmem.put.offset; + } + + if (size_put) { + struct ia_css_common_io_config *to = (struct ia_css_common_io_config *)&binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset]; + struct dma_port_config config; +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_yuv444_io_config() put part enter:\n"); +#endif + + ia_css_dma_configure_from_info(&config, &out_frames[0]->info); + to->base_address = out_frames[0]->data; + to->width = out_frames[0]->info.res.width; + to->height = out_frames[0]->info.res.height; + to->stride = config.stride; + to->ddr_elems_per_word = ddr_elems_per_word; + +#ifndef IA_CSS_NO_DEBUG + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_yuv444_io_config() put part leave:\n"); +#endif + } +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io.host.h new file mode 100644 index 0000000000000000000000000000000000000000..480172d39aeeed6316de2aaebfb3f38b54dd7e66 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io.host.h @@ -0,0 +1,31 @@ +#ifdef ISP2401 +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __YUV444_IO_HOST_H +#define __YUV444_IO_HOST_H + +#include "ia_css_yuv444_io_param.h" +#include "ia_css_yuv444_io_types.h" +#include "ia_css_binary.h" +#include "sh_css_internal.h" + + +void +ia_css_yuv444_io_config( + const struct ia_css_binary *binary, + const struct sh_css_binary_args *args); + +#endif /*__YUV44_IO_HOST_H */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io_param.h new file mode 100644 index 0000000000000000000000000000000000000000..cc8eda19c6e8404c94073c17350992e4241bca8a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io_param.h @@ -0,0 +1,22 @@ +#ifdef ISP2401 +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __IA_CSS_YUV444_IO_PARAM +#define __IA_CSS_YUV444_IO_PARAM + +#include "../common/ia_css_common_io_param.h" + +#endif +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io_types.h new file mode 100644 index 0000000000000000000000000000000000000000..343325a111e1376ff88f4c5de4d63513390f15bd --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io_types.h @@ -0,0 +1,22 @@ +#ifdef ISP2401 +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __IA_CSS_YUV444_IO_TYPES +#define __IA_CSS_YUV444_IO_TYPES + +#include "../common/ia_css_common_io_types.h" + +#endif +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.c new file mode 100644 index 0000000000000000000000000000000000000000..9e41cc0a307f025876127e052ddc5c8ed41342d4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.c @@ -0,0 +1,80 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_iterator.host.h" +#include "ia_css_frame_public.h" +#include "ia_css_binary.h" +#include "ia_css_err.h" +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" + +static const struct ia_css_iterator_configuration default_config = { + .input_info = (struct ia_css_frame_info *)NULL, +}; + +void +ia_css_iterator_config( + struct sh_css_isp_iterator_isp_config *to, + const struct ia_css_iterator_configuration *from, + unsigned size) +{ + (void)size; + ia_css_frame_info_to_frame_sp_info(&to->input_info, from->input_info); + ia_css_frame_info_to_frame_sp_info(&to->internal_info, from->internal_info); + ia_css_frame_info_to_frame_sp_info(&to->output_info, from->output_info); + ia_css_frame_info_to_frame_sp_info(&to->vf_info, from->vf_info); + ia_css_resolution_to_sp_resolution(&to->dvs_envelope, from->dvs_envelope); +} + +enum ia_css_err +ia_css_iterator_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame_info *in_info) +{ + struct ia_css_frame_info my_info = IA_CSS_BINARY_DEFAULT_FRAME_INFO; + struct ia_css_iterator_configuration config = default_config; + + config.input_info = &binary->in_frame_info; + config.internal_info = &binary->internal_frame_info; + config.output_info = &binary->out_frame_info[0]; + config.vf_info = &binary->vf_frame_info; + config.dvs_envelope = &binary->dvs_envelope; + + /* Use in_info iso binary->in_frame_info. + * They can differ in padded width in case of scaling, e.g. for capture_pp. + * Find out why. + */ + if (in_info) + config.input_info = in_info; + if (binary->out_frame_info[0].res.width == 0) + config.output_info = &binary->out_frame_info[1]; + my_info = *config.output_info; + config.output_info = &my_info; + /* we do this only for preview pipe because in fill_binary_info function + * we assign vf_out res to out res, but for ISP internal processing, we need + * the original out res. for video pipe, it has two output pins --- out and + * vf_out, so it can keep these two resolutions already. */ + if (binary->info->sp.pipeline.mode == IA_CSS_BINARY_MODE_PREVIEW && + binary->vf_downscale_log2 > 0) { + /* TODO: Remove this after preview output decimation is fixed + * by configuring out&vf info files properly */ + my_info.padded_width <<= binary->vf_downscale_log2; + my_info.res.width <<= binary->vf_downscale_log2; + my_info.res.height <<= binary->vf_downscale_log2; + } + + ia_css_configure_iterator(binary, &config); + + return IA_CSS_SUCCESS; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.h new file mode 100644 index 0000000000000000000000000000000000000000..d8f249c5a53b41ab0d04135d9eec4a5ee1f7d7a3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.h @@ -0,0 +1,34 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ITERATOR_HOST_H +#define __IA_CSS_ITERATOR_HOST_H + +#include "ia_css_frame_public.h" +#include "ia_css_binary.h" +#include "ia_css_err.h" +#include "ia_css_iterator_param.h" + +void +ia_css_iterator_config( + struct sh_css_isp_iterator_isp_config *to, + const struct ia_css_iterator_configuration *from, + unsigned size); + +enum ia_css_err +ia_css_iterator_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame_info *in_info); + +#endif /* __IA_CSS_ITERATOR_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iterator/iterator_1.0/ia_css_iterator_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iterator/iterator_1.0/ia_css_iterator_param.h new file mode 100644 index 0000000000000000000000000000000000000000..d308126e41d347d818c087c6c833d42530191853 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/iterator/iterator_1.0/ia_css_iterator_param.h @@ -0,0 +1,38 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_ITERATOR_PARAM_H +#define __IA_CSS_ITERATOR_PARAM_H + +#include "ia_css_types.h" /* ia_css_resolution */ +#include "ia_css_frame_public.h" /* ia_css_frame_info */ +#include "ia_css_frame_comm.h" /* ia_css_frame_sp_info */ + +struct ia_css_iterator_configuration { + const struct ia_css_frame_info *input_info; + const struct ia_css_frame_info *internal_info; + const struct ia_css_frame_info *output_info; + const struct ia_css_frame_info *vf_info; + const struct ia_css_resolution *dvs_envelope; +}; + +struct sh_css_isp_iterator_isp_config { + struct ia_css_frame_sp_info input_info; + struct ia_css_frame_sp_info internal_info; + struct ia_css_frame_sp_info output_info; + struct ia_css_frame_sp_info vf_info; + struct ia_css_sp_resolution dvs_envelope; +}; + +#endif /* __IA_CSS_ITERATOR_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5.host.c new file mode 100644 index 0000000000000000000000000000000000000000..836a3b93c4274952287b1d4b8017dbb5e7f88ede --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5.host.c @@ -0,0 +1,74 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" + +#ifndef IA_CSS_NO_DEBUG +/* FIXME: See BZ 4427 */ +#include "ia_css_debug.h" +#endif + +#include "ia_css_macc1_5.host.h" + +const struct ia_css_macc1_5_config default_macc1_5_config = { + 1 +}; + +void +ia_css_macc1_5_encode( + struct sh_css_isp_macc1_5_params *to, + const struct ia_css_macc1_5_config *from, + unsigned size) +{ + (void)size; + to->exp = from->exp; +} + +void +ia_css_macc1_5_vmem_encode( + struct sh_css_isp_macc1_5_vmem_params *params, + const struct ia_css_macc1_5_table *from, + unsigned size) +{ + unsigned int i, j, k, idx; + unsigned int idx_map[] = { + 0, 1, 3, 2, 6, 7, 5, 4, 12, 13, 15, 14, 10, 11, 9, 8}; + + (void)size; + + for (k = 0; k < 4; k++) + for (i = 0; i < IA_CSS_MACC_NUM_AXES; i++) { + idx = (idx_map[i] + (k*IA_CSS_MACC_NUM_AXES)); + j = 4*i; + + params->data[0][(idx)] = from->data[j]; + params->data[1][(idx)] = from->data[j+1]; + params->data[2][(idx)] = from->data[j+2]; + params->data[3][(idx)] = from->data[j+3]; + } + +} + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_macc1_5_debug_dtrace( + const struct ia_css_macc1_5_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.exp=%d\n", + config->exp); +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5.host.h new file mode 100644 index 0000000000000000000000000000000000000000..8f0a78f5a20f7666169128ce3bd50e88eb009162 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5.host.h @@ -0,0 +1,41 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MACC1_5_HOST_H +#define __IA_CSS_MACC1_5_HOST_H + +#include "ia_css_macc1_5_param.h" +#include "ia_css_macc1_5_table.host.h" + +extern const struct ia_css_macc1_5_config default_macc1_5_config; + +void +ia_css_macc1_5_encode( + struct sh_css_isp_macc1_5_params *to, + const struct ia_css_macc1_5_config *from, + unsigned size); + +void +ia_css_macc1_5_vmem_encode( + struct sh_css_isp_macc1_5_vmem_params *params, + const struct ia_css_macc1_5_table *from, + unsigned size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_macc1_5_debug_dtrace( + const struct ia_css_macc1_5_config *config, + unsigned level); +#endif +#endif /* __IA_CSS_MACC1_5_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5_param.h new file mode 100644 index 0000000000000000000000000000000000000000..41a2da460dcf38d050891fef834f08121b1da5ee --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5_param.h @@ -0,0 +1,31 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MACC1_5_PARAM_H +#define __IA_CSS_MACC1_5_PARAM_H + +#include "type_support.h" +#include "vmem.h" +#include "ia_css_macc1_5_types.h" + +/* MACC */ +struct sh_css_isp_macc1_5_params { + int32_t exp; +}; + +struct sh_css_isp_macc1_5_vmem_params { + VMEM_ARRAY(data, IA_CSS_MACC_NUM_COEFS*ISP_NWAY); +}; + +#endif /* __IA_CSS_MACC1_5_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5_table.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5_table.host.c new file mode 100644 index 0000000000000000000000000000000000000000..89714bf87b5295fc784baf77bd2e42b7495f3525 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5_table.host.c @@ -0,0 +1,32 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "system_global.h" +#include "ia_css_types.h" +#include "ia_css_macc1_5_table.host.h" + +/* Multi-Axes Color Correction table for ISP2. + * 64values = 2x2matrix for 16area, [s1.12] + * ineffective: 16 of "identity 2x2 matix" {4096,0,0,4096} + */ +const struct ia_css_macc1_5_table default_macc1_5_table = { + { 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096 } +}; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5_table.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5_table.host.h new file mode 100644 index 0000000000000000000000000000000000000000..10a50aa82be80bb79e7b3664bec74503a4f33a75 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5_table.host.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MACC1_5_TABLE_HOST_H +#define __IA_CSS_MACC1_5_TABLE_HOST_H + +#include "macc/macc1_5/ia_css_macc1_5_types.h" + +extern const struct ia_css_macc1_5_table default_macc1_5_table; + +#endif /* __IA_CSS_MACC1_5_TABLE_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5_types.h new file mode 100644 index 0000000000000000000000000000000000000000..3d510bf5886a95c7dc2aaec8345cbc29fbf36e67 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5_types.h @@ -0,0 +1,74 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MACC1_5_TYPES_H +#define __IA_CSS_MACC1_5_TYPES_H + +/** @file +* CSS-API header file for Multi-Axis Color Conversion algorithm parameters. +*/ + +/** Multi-Axis Color Conversion configuration + * + * ISP2.6.1: MACC1_5 is used. + */ + + +/** Number of axes in the MACC table. */ +#define IA_CSS_MACC_NUM_AXES 16 +/** Number of coefficients per MACC axes. */ +#define IA_CSS_MACC_NUM_COEFS 4 + +/** Multi-Axes Color Correction (MACC) table. + * + * ISP block: MACC (MACC by only matrix) + * MACC1_5 (MACC by matrix and exponent(ia_css_macc_config)) + * ISP1: MACC is used. + * ISP2: MACC1_5 is used. + * + * [MACC] + * OutU = (data00 * InU + data01 * InV) >> 13 + * OutV = (data10 * InU + data11 * InV) >> 13 + * + * default/ineffective: + * OutU = (8192 * InU + 0 * InV) >> 13 + * OutV = ( 0 * InU + 8192 * InV) >> 13 + * + * [MACC1_5] + * OutU = (data00 * InU + data01 * InV) >> (13 - exp) + * OutV = (data10 * InU + data11 * InV) >> (13 - exp) + * + * default/ineffective: (exp=1) + * OutU = (4096 * InU + 0 * InV) >> (13 - 1) + * OutV = ( 0 * InU + 4096 * InV) >> (13 - 1) + */ +struct ia_css_macc1_5_table { + int16_t data[IA_CSS_MACC_NUM_COEFS * IA_CSS_MACC_NUM_AXES]; + /**< 16 of 2x2 matix + MACC1_5: s[macc_config.exp].[13-macc_config.exp], [-8192,8191] + default/ineffective: (s1.12) + 16 of "identity 2x2 matix" {4096,0,0,4096} */ +}; + +/** Multi-Axes Color Correction (MACC) configuration. + * + * ISP block: MACC1_5 (MACC by matrix and exponent(ia_css_macc_config)) + * ISP2: MACC1_5 is used. + */ +struct ia_css_macc1_5_config { + uint8_t exp; /**< Common exponent of ia_css_macc_table. + u8.0, [0,13], default 1, ineffective 1 */ +}; + +#endif /* __IA_CSS_MACC1_5_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc_1.0/ia_css_macc.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc_1.0/ia_css_macc.host.c new file mode 100644 index 0000000000000000000000000000000000000000..1f7e9e4eec3c572ff116c11e9466d55331a7e505 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc_1.0/ia_css_macc.host.c @@ -0,0 +1,49 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "sh_css_frac.h" + +#include "ia_css_macc.host.h" + +const struct ia_css_macc_config default_macc_config = { + 1, +}; + +void +ia_css_macc_encode( + struct sh_css_isp_macc_params *to, + const struct ia_css_macc_config *from, + unsigned size) +{ + (void)size; + to->exp = from->exp; +} + +void +ia_css_macc_dump( + const struct sh_css_isp_macc_params *macc, + unsigned level); + +void +ia_css_macc_debug_dtrace( + const struct ia_css_macc_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.exp=%d\n", + config->exp); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc_1.0/ia_css_macc.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc_1.0/ia_css_macc.host.h new file mode 100644 index 0000000000000000000000000000000000000000..044b01d38ad62d0f88e47e728d5375ab95f6f9d2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc_1.0/ia_css_macc.host.h @@ -0,0 +1,42 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MACC_HOST_H +#define __IA_CSS_MACC_HOST_H + +#include "sh_css_params.h" + +#include "ia_css_macc_param.h" +#include "ia_css_macc_table.host.h" + +extern const struct ia_css_macc_config default_macc_config; + +void +ia_css_macc_encode( + struct sh_css_isp_macc_params *to, + const struct ia_css_macc_config *from, + unsigned size); + + +void +ia_css_macc_dump( + const struct sh_css_isp_macc_params *macc, + unsigned level); + +void +ia_css_macc_debug_dtrace( + const struct ia_css_macc_config *config, + unsigned level); + +#endif /* __IA_CSS_MACC_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc_1.0/ia_css_macc_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc_1.0/ia_css_macc_param.h new file mode 100644 index 0000000000000000000000000000000000000000..6a12b922c48584a53dfc2714ee6c52ecdbb76831 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc_1.0/ia_css_macc_param.h @@ -0,0 +1,25 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MACC_PARAM_H +#define __IA_CSS_MACC_PARAM_H + +#include "type_support.h" + +/* MACC */ +struct sh_css_isp_macc_params { + int32_t exp; +}; + +#endif /* __IA_CSS_MACC_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc_1.0/ia_css_macc_table.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc_1.0/ia_css_macc_table.host.c new file mode 100644 index 0000000000000000000000000000000000000000..8a6c3cafabdc8c6328c4aa5826f96f6b6fba2ac8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc_1.0/ia_css_macc_table.host.c @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "system_global.h" +#include "ia_css_types.h" +#include "ia_css_macc_table.host.h" + +/* Multi-Axes Color Correction table for ISP1. + * 64values = 2x2matrix for 16area, [s2.13] + * ineffective: 16 of "identity 2x2 matix" {8192,0,0,8192} + */ +const struct ia_css_macc_table default_macc_table = { + { 8192, 0, 0, 8192, 8192, 0, 0, 8192, + 8192, 0, 0, 8192, 8192, 0, 0, 8192, + 8192, 0, 0, 8192, 8192, 0, 0, 8192, + 8192, 0, 0, 8192, 8192, 0, 0, 8192, + 8192, 0, 0, 8192, 8192, 0, 0, 8192, + 8192, 0, 0, 8192, 8192, 0, 0, 8192, + 8192, 0, 0, 8192, 8192, 0, 0, 8192, + 8192, 0, 0, 8192, 8192, 0, 0, 8192 } +}; + +/* Multi-Axes Color Correction table for ISP2. + * 64values = 2x2matrix for 16area, [s1.12] + * ineffective: 16 of "identity 2x2 matix" {4096,0,0,4096} + */ +const struct ia_css_macc_table default_macc2_table = { + { 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096, + 4096, 0, 0, 4096, 4096, 0, 0, 4096 } +}; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc_1.0/ia_css_macc_table.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc_1.0/ia_css_macc_table.host.h new file mode 100644 index 0000000000000000000000000000000000000000..96d62c9912b84c9fb256edfdf7c736e7d2481a5f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc_1.0/ia_css_macc_table.host.h @@ -0,0 +1,23 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MACC_TABLE_HOST_H +#define __IA_CSS_MACC_TABLE_HOST_H + +#include "ia_css_macc_types.h" + +extern const struct ia_css_macc_table default_macc_table; +extern const struct ia_css_macc_table default_macc2_table; + +#endif /* __IA_CSS_MACC_TABLE_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc_1.0/ia_css_macc_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc_1.0/ia_css_macc_types.h new file mode 100644 index 0000000000000000000000000000000000000000..a25581c6f3ac4cb82ac3de70f1853a6a6cdb7002 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/macc/macc_1.0/ia_css_macc_types.h @@ -0,0 +1,63 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_MACC_TYPES_H +#define __IA_CSS_MACC_TYPES_H + +/** @file +* CSS-API header file for Multi-Axis Color Correction (MACC) parameters. +*/ + +/** Number of axes in the MACC table. */ +#define IA_CSS_MACC_NUM_AXES 16 +/** Number of coefficients per MACC axes. */ +#define IA_CSS_MACC_NUM_COEFS 4 +/** The number of planes in the morphing table. */ + +/** Multi-Axis Color Correction (MACC) table. + * + * ISP block: MACC1 (MACC by only matrix) + * MACC2 (MACC by matrix and exponent(ia_css_macc_config)) + * ISP1: MACC1 is used. + * ISP2: MACC2 is used. + * + * [MACC1] + * OutU = (data00 * InU + data01 * InV) >> 13 + * OutV = (data10 * InU + data11 * InV) >> 13 + * + * default/ineffective: + * OutU = (8192 * InU + 0 * InV) >> 13 + * OutV = ( 0 * InU + 8192 * InV) >> 13 + * + * [MACC2] + * OutU = (data00 * InU + data01 * InV) >> (13 - exp) + * OutV = (data10 * InU + data11 * InV) >> (13 - exp) + * + * default/ineffective: (exp=1) + * OutU = (4096 * InU + 0 * InV) >> (13 - 1) + * OutV = ( 0 * InU + 4096 * InV) >> (13 - 1) + */ + +struct ia_css_macc_table { + int16_t data[IA_CSS_MACC_NUM_COEFS * IA_CSS_MACC_NUM_AXES]; + /**< 16 of 2x2 matix + MACC1: s2.13, [-65536,65535] + default/ineffective: + 16 of "identity 2x2 matix" {8192,0,0,8192} + MACC2: s[macc_config.exp].[13-macc_config.exp], [-8192,8191] + default/ineffective: (s1.12) + 16 of "identity 2x2 matix" {4096,0,0,4096} */ +}; + +#endif /* __IA_CSS_MACC_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/norm/norm_1.0/ia_css_norm.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/norm/norm_1.0/ia_css_norm.host.c new file mode 100644 index 0000000000000000000000000000000000000000..2c2c5a5854a03bc13157215c80fdf5487f557e75 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/norm/norm_1.0/ia_css_norm.host.c @@ -0,0 +1,16 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_norm.host.h" + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/norm/norm_1.0/ia_css_norm.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/norm/norm_1.0/ia_css_norm.host.h new file mode 100644 index 0000000000000000000000000000000000000000..42b5143ef78ffc350901c454415f244924d6baad --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/norm/norm_1.0/ia_css_norm.host.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_NORM_HOST_H +#define __IA_CSS_NORM_HOST_H + +#include "ia_css_norm_param.h" + +#endif /* __IA_CSS_NORM_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/norm/norm_1.0/ia_css_norm_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/norm/norm_1.0/ia_css_norm_param.h new file mode 100644 index 0000000000000000000000000000000000000000..85dc6fc0a56b39e3b865f10d1d26f5696a655b62 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/norm/norm_1.0/ia_css_norm_param.h @@ -0,0 +1,19 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_NORM_PARAM_H +#define __IA_CSS_NORM_PARAM_H + + +#endif /* __IA_CSS_NORM_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/norm/norm_1.0/ia_css_norm_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/norm/norm_1.0/ia_css_norm_types.h new file mode 100644 index 0000000000000000000000000000000000000000..5581bddf9f9b70a67802879d22e968d652c036e8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/norm/norm_1.0/ia_css_norm_types.h @@ -0,0 +1,21 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_NORM_TYPES_H +#define __IA_CSS_NORM_TYPES_H + + +#endif /* __IA_CSS_NORM_TYPES_H */ + + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob2/ia_css_ob2.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob2/ia_css_ob2.host.c new file mode 100644 index 0000000000000000000000000000000000000000..f77aff13f8e3cd91529e986ec20ab54f898e6b32 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob2/ia_css_ob2.host.c @@ -0,0 +1,79 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "sh_css_frac.h" +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" +#endif +#include "isp.h" +#include "ia_css_ob2.host.h" + +const struct ia_css_ob2_config default_ob2_config = { + 0, + 0, + 0, + 0 +}; + +void +ia_css_ob2_encode( + struct sh_css_isp_ob2_params *to, + const struct ia_css_ob2_config *from, + unsigned size) +{ + (void)size; + + /* Blacklevels types are u0_16 */ + to->blacklevel_gr = uDIGIT_FITTING(from->level_gr, 16, SH_CSS_BAYER_BITS); + to->blacklevel_r = uDIGIT_FITTING(from->level_r, 16, SH_CSS_BAYER_BITS); + to->blacklevel_b = uDIGIT_FITTING(from->level_b, 16, SH_CSS_BAYER_BITS); + to->blacklevel_gb = uDIGIT_FITTING(from->level_gb, 16, SH_CSS_BAYER_BITS); +} + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_ob2_dump( + const struct sh_css_isp_ob2_params *ob2, + unsigned level) +{ + if (!ob2) + return; + + ia_css_debug_dtrace(level, "Optical Black 2:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ob2_blacklevel_gr", ob2->blacklevel_gr); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ob2_blacklevel_r", ob2->blacklevel_r); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ob2_blacklevel_b", ob2->blacklevel_b); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ob2_blacklevel_gb", ob2->blacklevel_gb); + +} + + +void +ia_css_ob2_debug_dtrace( + const struct ia_css_ob2_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.level_gr=%d, config.level_r=%d, " + "config.level_b=%d, config.level_gb=%d, ", + config->level_gr, config->level_r, + config->level_b, config->level_gb); +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob2/ia_css_ob2.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob2/ia_css_ob2.host.h new file mode 100644 index 0000000000000000000000000000000000000000..06846502eca3cc3da5a06230d06bd37b485b35f8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob2/ia_css_ob2.host.h @@ -0,0 +1,40 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_OB2_HOST_H +#define __IA_CSS_OB2_HOST_H + +#include "ia_css_ob2_types.h" +#include "ia_css_ob2_param.h" + +extern const struct ia_css_ob2_config default_ob2_config; + +void +ia_css_ob2_encode( + struct sh_css_isp_ob2_params *to, + const struct ia_css_ob2_config *from, + unsigned size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_ob2_dump( + const struct sh_css_isp_ob2_params *ob2, + unsigned level); + +void +ia_css_ob2_debug_dtrace( + const struct ia_css_ob2_config *config, unsigned level); +#endif + +#endif /* __IA_CSS_OB2_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob2/ia_css_ob2_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob2/ia_css_ob2_param.h new file mode 100644 index 0000000000000000000000000000000000000000..5c21d6a3911b1a99f29484b82ec198d9763e96ed --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob2/ia_css_ob2_param.h @@ -0,0 +1,29 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_OB2_PARAM_H +#define __IA_CSS_OB2_PARAM_H + +#include "type_support.h" + + +/* OB2 (Optical Black) */ +struct sh_css_isp_ob2_params { + int32_t blacklevel_gr; + int32_t blacklevel_r; + int32_t blacklevel_b; + int32_t blacklevel_gb; +}; + +#endif /* __IA_CSS_OB2_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob2/ia_css_ob2_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob2/ia_css_ob2_types.h new file mode 100644 index 0000000000000000000000000000000000000000..eeaadfeb5a1ec4be4942523885007e58cbaa354b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob2/ia_css_ob2_types.h @@ -0,0 +1,45 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_OB2_TYPES_H +#define __IA_CSS_OB2_TYPES_H + +/** @file +* CSS-API header file for Optical Black algorithm parameters. +*/ + +/** Optical Black configuration + * + * ISP2.6.1: OB2 is used. + */ + +#include "ia_css_frac.h" + +struct ia_css_ob2_config { + ia_css_u0_16 level_gr; /**< Black level for GR pixels. + u0.16, [0,65535], + default/ineffective 0 */ + ia_css_u0_16 level_r; /**< Black level for R pixels. + u0.16, [0,65535], + default/ineffective 0 */ + ia_css_u0_16 level_b; /**< Black level for B pixels. + u0.16, [0,65535], + default/ineffective 0 */ + ia_css_u0_16 level_gb; /**< Black level for GB pixels. + u0.16, [0,65535], + default/ineffective 0 */ +}; + +#endif /* __IA_CSS_OB2_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob_1.0/ia_css_ob.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob_1.0/ia_css_ob.host.c new file mode 100644 index 0000000000000000000000000000000000000000..fd891ac092edf69efba5ed1a4212e2818b88a7f1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob_1.0/ia_css_ob.host.c @@ -0,0 +1,159 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "isp.h" + +#include "ia_css_ob.host.h" + +const struct ia_css_ob_config default_ob_config = { + IA_CSS_OB_MODE_NONE, + 0, + 0, + 0, + 0, + 0, + 0 +}; + +/* TODO: include ob.isp.h to get isp knowledge and + add assert on platform restrictions */ + +void +ia_css_ob_configure( + struct sh_css_isp_ob_stream_config *config, + unsigned int isp_pipe_version, + unsigned int raw_bit_depth) +{ + config->isp_pipe_version = isp_pipe_version; + config->raw_bit_depth = raw_bit_depth; +} + +void +ia_css_ob_encode( + struct sh_css_isp_ob_params *to, + const struct ia_css_ob_config *from, + const struct sh_css_isp_ob_stream_config *config, + unsigned size) +{ + unsigned int ob_bit_depth + = config->isp_pipe_version == 2 ? SH_CSS_BAYER_BITS : config->raw_bit_depth; + unsigned int scale = 16 - ob_bit_depth; + + (void)size; + switch (from->mode) { + case IA_CSS_OB_MODE_FIXED: + to->blacklevel_gr = from->level_gr >> scale; + to->blacklevel_r = from->level_r >> scale; + to->blacklevel_b = from->level_b >> scale; + to->blacklevel_gb = from->level_gb >> scale; + to->area_start_bq = 0; + to->area_length_bq = 0; + to->area_length_bq_inverse = 0; + break; + case IA_CSS_OB_MODE_RASTER: + to->blacklevel_gr = 0; + to->blacklevel_r = 0; + to->blacklevel_b = 0; + to->blacklevel_gb = 0; + to->area_start_bq = from->start_position; + to->area_length_bq = + (from->end_position - from->start_position) + 1; + to->area_length_bq_inverse = AREA_LENGTH_UNIT / to->area_length_bq; + break; + default: + to->blacklevel_gr = 0; + to->blacklevel_r = 0; + to->blacklevel_b = 0; + to->blacklevel_gb = 0; + to->area_start_bq = 0; + to->area_length_bq = 0; + to->area_length_bq_inverse = 0; + break; + } +} + +void +ia_css_ob_vmem_encode( + struct sh_css_isp_ob_vmem_params *to, + const struct ia_css_ob_config *from, + const struct sh_css_isp_ob_stream_config *config, + unsigned size) +{ + struct sh_css_isp_ob_params tmp; + struct sh_css_isp_ob_params *ob = &tmp; + + (void)size; + ia_css_ob_encode(&tmp, from, config, sizeof(tmp)); + + { + unsigned i; + unsigned sp_obarea_start_bq = ob->area_start_bq; + unsigned sp_obarea_length_bq = ob->area_length_bq; + unsigned low = sp_obarea_start_bq; + unsigned high = low + sp_obarea_length_bq; + uint16_t all_ones = ~0; + + for (i = 0; i < OBAREA_MASK_SIZE; i++) { + if (i >= low && i < high) + to->vmask[i/ISP_VEC_NELEMS][i%ISP_VEC_NELEMS] = all_ones; + else + to->vmask[i/ISP_VEC_NELEMS][i%ISP_VEC_NELEMS] = 0; + } + } +} + +void +ia_css_ob_dump( + const struct sh_css_isp_ob_params *ob, + unsigned level) +{ + if (!ob) return; + ia_css_debug_dtrace(level, "Optical Black:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ob_blacklevel_gr", ob->blacklevel_gr); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ob_blacklevel_r", ob->blacklevel_r); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ob_blacklevel_b", ob->blacklevel_b); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ob_blacklevel_gb", ob->blacklevel_gb); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "obarea_start_bq", ob->area_start_bq); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "obarea_length_bq", ob->area_length_bq); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "obarea_length_bq_inverse", + ob->area_length_bq_inverse); +} + + +void +ia_css_ob_debug_dtrace( + const struct ia_css_ob_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.mode=%d, " + "config.level_gr=%d, config.level_r=%d, " + "config.level_b=%d, config.level_gb=%d, " + "config.start_position=%d, config.end_position=%d\n", + config->mode, + config->level_gr, config->level_r, + config->level_b, config->level_gb, + config->start_position, config->end_position); +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob_1.0/ia_css_ob.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob_1.0/ia_css_ob.host.h new file mode 100644 index 0000000000000000000000000000000000000000..4af181470f8d2a1f24571b1e914db8e374f0a8d7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob_1.0/ia_css_ob.host.h @@ -0,0 +1,53 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_OB_HOST_H +#define __IA_CSS_OB_HOST_H + +#include "ia_css_ob_types.h" +#include "ia_css_ob_param.h" + +extern const struct ia_css_ob_config default_ob_config; + +void +ia_css_ob_configure( + struct sh_css_isp_ob_stream_config *config, + unsigned int isp_pipe_version, + unsigned int raw_bit_depth); + +void +ia_css_ob_encode( + struct sh_css_isp_ob_params *to, + const struct ia_css_ob_config *from, + const struct sh_css_isp_ob_stream_config *config, + unsigned size); + +void +ia_css_ob_vmem_encode( + struct sh_css_isp_ob_vmem_params *to, + const struct ia_css_ob_config *from, + const struct sh_css_isp_ob_stream_config *config, + unsigned size); + +void +ia_css_ob_dump( + const struct sh_css_isp_ob_params *ob, + unsigned level); + +void +ia_css_ob_debug_dtrace( + const struct ia_css_ob_config *config, unsigned level) +; + +#endif /* __IA_CSS_OB_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob_1.0/ia_css_ob_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob_1.0/ia_css_ob_param.h new file mode 100644 index 0000000000000000000000000000000000000000..a60a644bb4ff75f1920dbae37593477d792663a3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob_1.0/ia_css_ob_param.h @@ -0,0 +1,48 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_OB_PARAM_H +#define __IA_CSS_OB_PARAM_H + +#include "type_support.h" +#include "vmem.h" + +#define OBAREA_MASK_SIZE 64 +#define OBAREA_LENGTHBQ_INVERSE_SHIFT 12 + +/* AREA_LENGTH_UNIT is dependent on NWAY, requires rewrite */ +#define AREA_LENGTH_UNIT (1<<12) + + +/* OB (Optical Black) */ +struct sh_css_isp_ob_stream_config { + unsigned isp_pipe_version; + unsigned raw_bit_depth; +}; + +struct sh_css_isp_ob_params { + int32_t blacklevel_gr; + int32_t blacklevel_r; + int32_t blacklevel_b; + int32_t blacklevel_gb; + int32_t area_start_bq; + int32_t area_length_bq; + int32_t area_length_bq_inverse; +}; + +struct sh_css_isp_ob_vmem_params { + VMEM_ARRAY(vmask, OBAREA_MASK_SIZE); +}; + +#endif /* __IA_CSS_OB_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob_1.0/ia_css_ob_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob_1.0/ia_css_ob_types.h new file mode 100644 index 0000000000000000000000000000000000000000..88459b6c003d180f35f9eb82def73e29c0b1b6d9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ob/ob_1.0/ia_css_ob_types.h @@ -0,0 +1,69 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_OB_TYPES_H +#define __IA_CSS_OB_TYPES_H + +/** @file +* CSS-API header file for Optical Black level parameters. +*/ + +#include "ia_css_frac.h" + +/** Optical black mode. + */ +enum ia_css_ob_mode { + IA_CSS_OB_MODE_NONE, /**< OB has no effect. */ + IA_CSS_OB_MODE_FIXED, /**< Fixed OB */ + IA_CSS_OB_MODE_RASTER /**< Raster OB */ +}; + +/** Optical Black level configuration. + * + * ISP block: OB1 + * ISP1: OB1 is used. + * ISP2: OB1 is used. + */ +struct ia_css_ob_config { + enum ia_css_ob_mode mode; /**< Mode (None / Fixed / Raster). + enum, [0,2], + default 1, ineffective 0 */ + ia_css_u0_16 level_gr; /**< Black level for GR pixels + (used for Fixed Mode only). + u0.16, [0,65535], + default/ineffective 0 */ + ia_css_u0_16 level_r; /**< Black level for R pixels + (used for Fixed Mode only). + u0.16, [0,65535], + default/ineffective 0 */ + ia_css_u0_16 level_b; /**< Black level for B pixels + (used for Fixed Mode only). + u0.16, [0,65535], + default/ineffective 0 */ + ia_css_u0_16 level_gb; /**< Black level for GB pixels + (used for Fixed Mode only). + u0.16, [0,65535], + default/ineffective 0 */ + uint16_t start_position; /**< Start position of OB area + (used for Raster Mode only). + u16.0, [0,63], + default/ineffective 0 */ + uint16_t end_position; /**< End position of OB area + (used for Raster Mode only). + u16.0, [0,63], + default/ineffective 0 */ +}; + +#endif /* __IA_CSS_OB_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/output/output_1.0/ia_css_output.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/output/output_1.0/ia_css_output.host.c new file mode 100644 index 0000000000000000000000000000000000000000..8fdf47c9310c8e69b61852f1c94063932338456a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/output/output_1.0/ia_css_output.host.c @@ -0,0 +1,162 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_frame.h" +#include "ia_css_debug.h" +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" +#include "ia_css_output.host.h" +#include "isp.h" + +#include "assert_support.h" + +const struct ia_css_output_config default_output_config = { + 0, + 0 +}; + +static const struct ia_css_output_configuration default_output_configuration = { + .info = (struct ia_css_frame_info *)NULL, +}; + +static const struct ia_css_output0_configuration default_output0_configuration = { + .info = (struct ia_css_frame_info *)NULL, +}; + +static const struct ia_css_output1_configuration default_output1_configuration = { + .info = (struct ia_css_frame_info *)NULL, +}; + +void +ia_css_output_encode( + struct sh_css_isp_output_params *to, + const struct ia_css_output_config *from, + unsigned size) +{ + (void)size; + to->enable_hflip = from->enable_hflip; + to->enable_vflip = from->enable_vflip; +} + +void +ia_css_output_config( + struct sh_css_isp_output_isp_config *to, + const struct ia_css_output_configuration *from, + unsigned size) +{ + unsigned elems_a = ISP_VEC_NELEMS; + + (void)size; + ia_css_dma_configure_from_info(&to->port_b, from->info); + to->width_a_over_b = elems_a / to->port_b.elems; + to->height = from->info->res.height; + to->enable = from->info != NULL; + ia_css_frame_info_to_frame_sp_info(&to->info, from->info); + + /* Assume divisiblity here, may need to generalize to fixed point. */ + assert (elems_a % to->port_b.elems == 0); +} + +void +ia_css_output0_config( + struct sh_css_isp_output_isp_config *to, + const struct ia_css_output0_configuration *from, + unsigned size) +{ + ia_css_output_config ( + to, (const struct ia_css_output_configuration *)from, size); +} + +void +ia_css_output1_config( + struct sh_css_isp_output_isp_config *to, + const struct ia_css_output1_configuration *from, + unsigned size) +{ + ia_css_output_config ( + to, (const struct ia_css_output_configuration *)from, size); +} + +void +ia_css_output_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame_info *info) +{ + if (NULL != info) { + struct ia_css_output_configuration config = + default_output_configuration; + + config.info = info; + + ia_css_configure_output(binary, &config); + } +} + +void +ia_css_output0_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame_info *info) +{ + if (NULL != info) { + struct ia_css_output0_configuration config = + default_output0_configuration; + + config.info = info; + + ia_css_configure_output0(binary, &config); + } +} + +void +ia_css_output1_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame_info *info) +{ + + if (NULL != info) { + struct ia_css_output1_configuration config = + default_output1_configuration; + + config.info = info; + + ia_css_configure_output1(binary, &config); + } +} + +void +ia_css_output_dump( + const struct sh_css_isp_output_params *output, + unsigned level) +{ + if (!output) return; + ia_css_debug_dtrace(level, "Horizontal Output Flip:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "enable", output->enable_hflip); + ia_css_debug_dtrace(level, "Vertical Output Flip:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "enable", output->enable_vflip); +} + +void +ia_css_output_debug_dtrace( + const struct ia_css_output_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.enable_hflip=%d", + config->enable_hflip); + ia_css_debug_dtrace(level, + "config.enable_vflip=%d", + config->enable_vflip); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/output/output_1.0/ia_css_output.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/output/output_1.0/ia_css_output.host.h new file mode 100644 index 0000000000000000000000000000000000000000..530f934ce81e799671778da3800df00b497e08aa --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/output/output_1.0/ia_css_output.host.h @@ -0,0 +1,75 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_OUTPUT_HOST_H +#define __IA_CSS_OUTPUT_HOST_H + +#include "ia_css_frame_public.h" +#include "ia_css_binary.h" + +#include "ia_css_output_types.h" +#include "ia_css_output_param.h" + +extern const struct ia_css_output_config default_output_config; + +void +ia_css_output_encode( + struct sh_css_isp_output_params *to, + const struct ia_css_output_config *from, + unsigned size); + +void +ia_css_output_config( + struct sh_css_isp_output_isp_config *to, + const struct ia_css_output_configuration *from, + unsigned size); + +void +ia_css_output0_config( + struct sh_css_isp_output_isp_config *to, + const struct ia_css_output0_configuration *from, + unsigned size); + +void +ia_css_output1_config( + struct sh_css_isp_output_isp_config *to, + const struct ia_css_output1_configuration *from, + unsigned size); + +void +ia_css_output_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame_info *from); + +void +ia_css_output0_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame_info *from); + +void +ia_css_output1_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame_info *from); + +void +ia_css_output_dump( + const struct sh_css_isp_output_params *output, + unsigned level); + +void +ia_css_output_debug_dtrace( + const struct ia_css_output_config *config, + unsigned level); + +#endif /* __IA_CSS_OUTPUT_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/output/output_1.0/ia_css_output_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/output/output_1.0/ia_css_output_param.h new file mode 100644 index 0000000000000000000000000000000000000000..26ec27e085c1da60a6b3d035deda02f24b3b5906 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/output/output_1.0/ia_css_output_param.h @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_OUTPUT_PARAM_H +#define __IA_CSS_OUTPUT_PARAM_H + +#include +#include "dma.h" +#include "ia_css_frame_comm.h" /* ia_css_frame_sp_info */ + +/** output frame */ +struct sh_css_isp_output_isp_config { + uint32_t width_a_over_b; + uint32_t height; + uint32_t enable; + struct ia_css_frame_sp_info info; + struct dma_port_config port_b; +}; + +struct sh_css_isp_output_params { + uint8_t enable_hflip; + uint8_t enable_vflip; +}; + +#endif /* __IA_CSS_OUTPUT_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/output/output_1.0/ia_css_output_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/output/output_1.0/ia_css_output_types.h new file mode 100644 index 0000000000000000000000000000000000000000..4335ac28b31d76fec890dff2e4fbb0e208f8a0df --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/output/output_1.0/ia_css_output_types.h @@ -0,0 +1,48 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_OUTPUT_TYPES_H +#define __IA_CSS_OUTPUT_TYPES_H + +/** @file +* CSS-API header file for parameters of output frames. +*/ + +/** Output frame + * + * ISP block: output frame + */ + +//#include "ia_css_frame_public.h" +struct ia_css_frame_info; + +struct ia_css_output_configuration { + const struct ia_css_frame_info *info; +}; + +struct ia_css_output0_configuration { + const struct ia_css_frame_info *info; +}; + +struct ia_css_output1_configuration { + const struct ia_css_frame_info *info; +}; + +struct ia_css_output_config { + uint8_t enable_hflip; /**< enable horizontal output mirroring */ + uint8_t enable_vflip; /**< enable vertical output mirroring */ +}; + +#endif /* __IA_CSS_OUTPUT_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/pdaf/ia_css_pdaf.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/pdaf/ia_css_pdaf.host.c new file mode 100644 index 0000000000000000000000000000000000000000..79ddef6f416b40286ec2f75ac133150d0697a668 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/pdaf/ia_css_pdaf.host.c @@ -0,0 +1,84 @@ +#ifdef ISP2600 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "sh_css_frac.h" +#include "ia_css_pdaf.host.h" + +const struct ia_css_pdaf_config default_pdaf_config; + +void +ia_css_pdaf_dmem_encode( + struct isp_pdaf_dmem_params *to, + const struct ia_css_pdaf_config *from, + unsigned size) +{ + (void)size; + to->frm_length = from->frm_length; + to->frm_width = from->frm_width; + + to->ext_cfg_l_data.num_valid_patterns = from->ext_cfg_data.l_pixel_grid.num_valid_patterns; + + to->ext_cfg_r_data.num_valid_patterns = from->ext_cfg_data.r_pixel_grid.num_valid_patterns; + + to->stats_calc_data.num_valid_elm = from->stats_calc_cfg_data.num_valid_elm; +} + +void +ia_css_pdaf_vmem_encode( + struct isp_pdaf_vmem_params *to, + const struct ia_css_pdaf_config *from, + unsigned size) +{ + + unsigned int i; + (void)size; + /* Initialize left pixel grid */ + for ( i=0 ; i < from->ext_cfg_data.l_pixel_grid.num_valid_patterns ; i++) { + + to->ext_cfg_l_data.y_offset[0][i] = from->ext_cfg_data.l_pixel_grid.y_offset[i]; + to->ext_cfg_l_data.x_offset[0][i] = from->ext_cfg_data.l_pixel_grid.x_offset[i]; + to->ext_cfg_l_data.y_step_size[0][i] = from->ext_cfg_data.l_pixel_grid.y_step_size[i]; + to->ext_cfg_l_data.x_step_size[0][i] = from->ext_cfg_data.l_pixel_grid.x_step_size[i]; + } + + for ( ; i < ISP_NWAY ; i++) { + + to->ext_cfg_l_data.y_offset[0][i] = PDAF_INVALID_VAL; + to->ext_cfg_l_data.x_offset[0][i] = PDAF_INVALID_VAL; + to->ext_cfg_l_data.y_step_size[0][i] = PDAF_INVALID_VAL; + to->ext_cfg_l_data.x_step_size[0][i] = PDAF_INVALID_VAL; + } + + /* Initialize left pixel grid */ + + for ( i=0 ; i < from->ext_cfg_data.r_pixel_grid.num_valid_patterns ; i++) { + + to->ext_cfg_r_data.y_offset[0][i] = from->ext_cfg_data.r_pixel_grid.y_offset[i]; + to->ext_cfg_r_data.x_offset[0][i] = from->ext_cfg_data.r_pixel_grid.x_offset[i]; + to->ext_cfg_r_data.y_step_size[0][i] = from->ext_cfg_data.r_pixel_grid.y_step_size[i]; + to->ext_cfg_r_data.x_step_size[0][i] = from->ext_cfg_data.r_pixel_grid.x_step_size[i]; + } + + for ( ; i < ISP_NWAY ; i++) { + + to->ext_cfg_r_data.y_offset[0][i] = PDAF_INVALID_VAL; + to->ext_cfg_r_data.x_offset[0][i] = PDAF_INVALID_VAL; + to->ext_cfg_r_data.y_step_size[0][i] = PDAF_INVALID_VAL; + to->ext_cfg_r_data.x_step_size[0][i] = PDAF_INVALID_VAL; + } +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/pdaf/ia_css_pdaf.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/pdaf/ia_css_pdaf.host.h new file mode 100644 index 0000000000000000000000000000000000000000..e0e91550185684baa8ff9d97ecc7c523ab11b0b9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/pdaf/ia_css_pdaf.host.h @@ -0,0 +1,37 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PDAF_HOST_H +#define __IA_CSS_PDAF_HOST_H + +#include "ia_css_pdaf_types.h" +#include "ia_css_pdaf_param.h" + +extern const struct ia_css_pdaf_config default_pdaf_config; + +void +ia_css_pdaf_dmem_encode( + struct isp_pdaf_dmem_params *to, + const struct ia_css_pdaf_config *from, + unsigned size); + +void +ia_css_pdaf_vmem_encode( + struct isp_pdaf_vmem_params *to, + const struct ia_css_pdaf_config *from, + unsigned size); + +#endif /* __IA_CSS_PDAF_HOST_H */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/pdaf/ia_css_pdaf_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/pdaf/ia_css_pdaf_param.h new file mode 100644 index 0000000000000000000000000000000000000000..8535c9f7b47fa461b0e21a42df39e75b70dbe934 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/pdaf/ia_css_pdaf_param.h @@ -0,0 +1,62 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PDAF_PARAM_H +#define __IA_CSS_PDAF_PARAM_H + +#define PDAF_INVALID_VAL 0x7FFF +#include "vmem.h" + +struct isp_stats_calc_dmem_params { + + uint16_t num_valid_elm; +}; +/* + * Extraction configuration parameters + */ + +struct isp_extraction_dmem_params { + + uint8_t num_valid_patterns; +}; + +struct isp_extraction_vmem_params { + + VMEM_ARRAY(y_step_size, ISP_VEC_NELEMS); + VMEM_ARRAY(y_offset, ISP_VEC_NELEMS); + VMEM_ARRAY(x_step_size, ISP_VEC_NELEMS); + VMEM_ARRAY(x_offset, ISP_VEC_NELEMS); +}; + +/* + * PDAF configuration parameters + */ +struct isp_pdaf_vmem_params { + + struct isp_extraction_vmem_params ext_cfg_l_data; + struct isp_extraction_vmem_params ext_cfg_r_data; +}; + +struct isp_pdaf_dmem_params { + + uint16_t frm_length; + uint16_t frm_width; + struct isp_stats_calc_dmem_params stats_calc_data; + struct isp_extraction_dmem_params ext_cfg_l_data; + struct isp_extraction_dmem_params ext_cfg_r_data; +}; + +#endif /* __IA_CSS_PDAF_PARAM_H */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/pdaf/ia_css_pdaf_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/pdaf/ia_css_pdaf_types.h new file mode 100644 index 0000000000000000000000000000000000000000..3e42877c1d718916df6df27718f733dc5e721f86 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/pdaf/ia_css_pdaf_types.h @@ -0,0 +1,54 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_PDAF_TYPES_H +#define __IA_CSS_PDAF_TYPES_H + +#include "type_support.h" +#include "isp2600_config.h" +/* + * Header file for PDAF parameters + * These parameters shall be filled by host/driver + * and will be converted to ISP parameters in encode + * function. + */ + +struct ia_css_statistics_calc_config { + + uint16_t num_valid_elm; +}; +struct ia_css_pixel_grid_config { + + uint8_t num_valid_patterns; + int16_t y_step_size[ISP_NWAY]; + int16_t y_offset[ISP_NWAY]; + int16_t x_step_size[ISP_NWAY]; + int16_t x_offset[ISP_NWAY]; +}; + +struct ia_css_extraction_config { + + struct ia_css_pixel_grid_config l_pixel_grid; /* Left PDAF pixel grid */ + struct ia_css_pixel_grid_config r_pixel_grid; /* Right PDAF pixel grid */ +}; + +struct ia_css_pdaf_config { + + uint16_t frm_length; + uint16_t frm_width; + struct ia_css_extraction_config ext_cfg_data; + struct ia_css_statistics_calc_config stats_calc_cfg_data; +}; + +#endif /* __IA_CSS_PDAF_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/qplane/qplane_2/ia_css_qplane.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/qplane/qplane_2/ia_css_qplane.host.c new file mode 100644 index 0000000000000000000000000000000000000000..d1fb4b11600393f57c16b8208c339090bb76e448 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/qplane/qplane_2/ia_css_qplane.host.c @@ -0,0 +1,61 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_frame.h" +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "assert_support.h" +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" +#include "isp.h" + +#include "ia_css_qplane.host.h" + +static const struct ia_css_qplane_configuration default_config = { + .pipe = (struct sh_css_sp_pipeline *)NULL, +}; + +void +ia_css_qplane_config( + struct sh_css_isp_qplane_isp_config *to, + const struct ia_css_qplane_configuration *from, + unsigned size) +{ + unsigned elems_a = ISP_VEC_NELEMS; + + (void)size; + ia_css_dma_configure_from_info(&to->port_b, from->info); + to->width_a_over_b = elems_a / to->port_b.elems; + + /* Assume divisiblity here, may need to generalize to fixed point. */ + assert (elems_a % to->port_b.elems == 0); + + to->inout_port_config = from->pipe->inout_port_config; + to->format = from->info->format; +} + +void +ia_css_qplane_configure( + const struct sh_css_sp_pipeline *pipe, + const struct ia_css_binary *binary, + const struct ia_css_frame_info *info) +{ + struct ia_css_qplane_configuration config = default_config; + + config.pipe = pipe; + config.info = info; + + ia_css_configure_qplane(binary, &config); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/qplane/qplane_2/ia_css_qplane.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/qplane/qplane_2/ia_css_qplane.host.h new file mode 100644 index 0000000000000000000000000000000000000000..c41e9e5e0fd7a4bcee0d08182caaecd7d1c2202a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/qplane/qplane_2/ia_css_qplane.host.h @@ -0,0 +1,43 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_QPLANE_HOST_H +#define __IA_CSS_QPLANE_HOST_H + +#include +#include + +#if 0 +/* Cannot be included, since sh_css_internal.h is too generic + * e.g. for FW generation. +*/ +#include "sh_css_internal.h" /* sh_css_sp_pipeline */ +#endif + +#include "ia_css_qplane_types.h" +#include "ia_css_qplane_param.h" + +void +ia_css_qplane_config( + struct sh_css_isp_qplane_isp_config *to, + const struct ia_css_qplane_configuration *from, + unsigned size); + +void +ia_css_qplane_configure( + const struct sh_css_sp_pipeline *pipe, + const struct ia_css_binary *binary, + const struct ia_css_frame_info *from); + +#endif /* __IA_CSS_QPLANE_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/qplane/qplane_2/ia_css_qplane_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/qplane/qplane_2/ia_css_qplane_param.h new file mode 100644 index 0000000000000000000000000000000000000000..5885f621de88a59e6a629e805cd385fd435fbe26 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/qplane/qplane_2/ia_css_qplane_param.h @@ -0,0 +1,30 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_QPLANE_PARAM_H +#define __IA_CSS_QPLANE_PARAM_H + +#include +#include "dma.h" + +/* qplane channel */ +struct sh_css_isp_qplane_isp_config { + uint32_t width_a_over_b; + struct dma_port_config port_b; + uint32_t inout_port_config; + uint32_t input_needs_raw_binning; + uint32_t format; /* enum ia_css_frame_format */ +}; + +#endif /* __IA_CSS_QPLANE_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/qplane/qplane_2/ia_css_qplane_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/qplane/qplane_2/ia_css_qplane_types.h new file mode 100644 index 0000000000000000000000000000000000000000..955fd472a2414b939023b789fa35c76c22f3860b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/qplane/qplane_2/ia_css_qplane_types.h @@ -0,0 +1,33 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_QPLANE_TYPES_H +#define __IA_CSS_QPLANE_TYPES_H + +#include +#include "sh_css_internal.h" + +/** qplane frame + * + * ISP block: qplane frame + */ + + +struct ia_css_qplane_configuration { + const struct sh_css_sp_pipeline *pipe; + const struct ia_css_frame_info *info; +}; + +#endif /* __IA_CSS_QPLANE_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw/raw_1.0/ia_css_raw.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw/raw_1.0/ia_css_raw.host.c new file mode 100644 index 0000000000000000000000000000000000000000..68a27f0cfba0845172c0c4ebb0e8d7d507d3425f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw/raw_1.0/ia_css_raw.host.c @@ -0,0 +1,136 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_frame.h" +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "assert_support.h" +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" +#include "isp.h" +#include "isp/modes/interface/isp_types.h" + +#include "ia_css_raw.host.h" + + +static const struct ia_css_raw_configuration default_config = { + .pipe = (struct sh_css_sp_pipeline *)NULL, +}; + +static inline unsigned +sh_css_elems_bytes_from_info (unsigned raw_bit_depth) +{ + return CEIL_DIV(raw_bit_depth,8); +} + +/* MW: These areMIPI / ISYS properties, not camera function properties */ +static enum sh_stream_format +css2isp_stream_format(enum ia_css_stream_format from) +{ + switch (from) { + case IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY: + return sh_stream_format_yuv420_legacy; + case IA_CSS_STREAM_FORMAT_YUV420_8: + case IA_CSS_STREAM_FORMAT_YUV420_10: + case IA_CSS_STREAM_FORMAT_YUV420_16: + return sh_stream_format_yuv420; + case IA_CSS_STREAM_FORMAT_YUV422_8: + case IA_CSS_STREAM_FORMAT_YUV422_10: + case IA_CSS_STREAM_FORMAT_YUV422_16: + return sh_stream_format_yuv422; + case IA_CSS_STREAM_FORMAT_RGB_444: + case IA_CSS_STREAM_FORMAT_RGB_555: + case IA_CSS_STREAM_FORMAT_RGB_565: + case IA_CSS_STREAM_FORMAT_RGB_666: + case IA_CSS_STREAM_FORMAT_RGB_888: + return sh_stream_format_rgb; + case IA_CSS_STREAM_FORMAT_RAW_6: + case IA_CSS_STREAM_FORMAT_RAW_7: + case IA_CSS_STREAM_FORMAT_RAW_8: + case IA_CSS_STREAM_FORMAT_RAW_10: + case IA_CSS_STREAM_FORMAT_RAW_12: + case IA_CSS_STREAM_FORMAT_RAW_14: + case IA_CSS_STREAM_FORMAT_RAW_16: + return sh_stream_format_raw; + case IA_CSS_STREAM_FORMAT_BINARY_8: + default: + return sh_stream_format_raw; + } +} + +void +ia_css_raw_config( + struct sh_css_isp_raw_isp_config *to, + const struct ia_css_raw_configuration *from, + unsigned size) +{ + unsigned elems_a = ISP_VEC_NELEMS; + const struct ia_css_frame_info *in_info = from->in_info; + const struct ia_css_frame_info *internal_info = from->internal_info; + + (void)size; +#if !defined(USE_INPUT_SYSTEM_VERSION_2401) + /* 2401 input system uses input width width */ + in_info = internal_info; +#else + /*in some cases, in_info is NULL*/ + if (in_info) + (void)internal_info; + else + in_info = internal_info; + +#endif + ia_css_dma_configure_from_info(&to->port_b, in_info); + + /* Assume divisiblity here, may need to generalize to fixed point. */ + assert((in_info->format == IA_CSS_FRAME_FORMAT_RAW_PACKED) || + (elems_a % to->port_b.elems == 0)); + + to->width_a_over_b = elems_a / to->port_b.elems; + to->inout_port_config = from->pipe->inout_port_config; + to->format = in_info->format; + to->required_bds_factor = from->pipe->required_bds_factor; + to->two_ppc = from->two_ppc; + to->stream_format = css2isp_stream_format(from->stream_format); + to->deinterleaved = from->deinterleaved; +#if (defined(USE_INPUT_SYSTEM_VERSION_2401) || defined(CONFIG_CSI2_PLUS)) + to->start_column = in_info->crop_info.start_column; + to->start_line = in_info->crop_info.start_line; + to->enable_left_padding = from->enable_left_padding; +#endif +} + +void +ia_css_raw_configure( + const struct sh_css_sp_pipeline *pipe, + const struct ia_css_binary *binary, + const struct ia_css_frame_info *in_info, + const struct ia_css_frame_info *internal_info, + bool two_ppc, + bool deinterleaved) +{ + uint8_t enable_left_padding = (uint8_t)((binary->left_padding) ? 1 : 0); + struct ia_css_raw_configuration config = default_config; + + config.pipe = pipe; + config.in_info = in_info; + config.internal_info = internal_info; + config.two_ppc = two_ppc; + config.stream_format = binary->input_format; + config.deinterleaved = deinterleaved; + config.enable_left_padding = enable_left_padding; + + ia_css_configure_raw(binary, &config); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw/raw_1.0/ia_css_raw.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw/raw_1.0/ia_css_raw.host.h new file mode 100644 index 0000000000000000000000000000000000000000..ac6b7f6b59c62987f934f0d10af82680919f039f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw/raw_1.0/ia_css_raw.host.h @@ -0,0 +1,38 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_RAW_HOST_H +#define __IA_CSS_RAW_HOST_H + +#include "ia_css_binary.h" + +#include "ia_css_raw_types.h" +#include "ia_css_raw_param.h" + +void +ia_css_raw_config( + struct sh_css_isp_raw_isp_config *to, + const struct ia_css_raw_configuration *from, + unsigned size); + +void +ia_css_raw_configure( + const struct sh_css_sp_pipeline *pipe, + const struct ia_css_binary *binary, + const struct ia_css_frame_info *in_info, + const struct ia_css_frame_info *internal_info, + bool two_ppc, + bool deinterleaved); + +#endif /* __IA_CSS_RAW_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw/raw_1.0/ia_css_raw_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw/raw_1.0/ia_css_raw_param.h new file mode 100644 index 0000000000000000000000000000000000000000..12168b2dec2d013e68eab478a66423c0ab3e807c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw/raw_1.0/ia_css_raw_param.h @@ -0,0 +1,38 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_RAW_PARAM_H +#define __IA_CSS_RAW_PARAM_H + +#include "type_support.h" + +#include "dma.h" + +/* Raw channel */ +struct sh_css_isp_raw_isp_config { + uint32_t width_a_over_b; + struct dma_port_config port_b; + uint32_t inout_port_config; + uint32_t input_needs_raw_binning; + uint32_t format; /* enum ia_css_frame_format */ + uint32_t required_bds_factor; + uint32_t two_ppc; + uint32_t stream_format; /* enum sh_stream_format */ + uint32_t deinterleaved; + uint32_t start_column; /*left crop offset*/ + uint32_t start_line; /*top crop offset*/ + uint8_t enable_left_padding; /*need this for multiple binary case*/ +}; + +#endif /* __IA_CSS_RAW_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw/raw_1.0/ia_css_raw_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw/raw_1.0/ia_css_raw_types.h new file mode 100644 index 0000000000000000000000000000000000000000..54f8c299d22730092c10fcd80720fbafd6a0a2cd --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw/raw_1.0/ia_css_raw_types.h @@ -0,0 +1,37 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_RAW_TYPES_H +#define __IA_CSS_RAW_TYPES_H + +#include +#include "sh_css_internal.h" + +/** Raw frame + * + * ISP block: Raw frame + */ + +struct ia_css_raw_configuration { + const struct sh_css_sp_pipeline *pipe; + const struct ia_css_frame_info *in_info; + const struct ia_css_frame_info *internal_info; + bool two_ppc; + enum ia_css_stream_format stream_format; + bool deinterleaved; + uint8_t enable_left_padding; +}; + +#endif /* __IA_CSS_RAW_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.c new file mode 100644 index 0000000000000000000000000000000000000000..74521c90ca9abf6b59026da08ab0c501875be9f3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.c @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#if !defined(HAS_NO_HMEM) + +#include "ia_css_memory_access.h" +#include "memory_access.h" +#include "ia_css_types.h" +#include "sh_css_internal.h" +#include "sh_css_frac.h" + +#include "ia_css_raa.host.h" + +void +ia_css_raa_encode( + struct sh_css_isp_aa_params *to, + const struct ia_css_aa_config *from, + unsigned size) +{ + (void)size; + (void)to; + (void)from; +} + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.h new file mode 100644 index 0000000000000000000000000000000000000000..b4f245c19f18b76901d939079064e3cc742be8c0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.h @@ -0,0 +1,27 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_RAA_HOST_H +#define __IA_CSS_RAA_HOST_H + +#include "aa/aa_2/ia_css_aa2_types.h" +#include "aa/aa_2/ia_css_aa2_param.h" + +void +ia_css_raa_encode( + struct sh_css_isp_aa_params *to, + const struct ia_css_aa_config *from, + unsigned size); + +#endif /* __IA_CSS_RAA_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref.host.c new file mode 100644 index 0000000000000000000000000000000000000000..4c0ed5d4d971fc1e9f541e1ac63515f456aaa8b9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref.host.c @@ -0,0 +1,74 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include +#include +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" +#include "isp.h" +#include "ia_css_ref.host.h" + +void +ia_css_ref_config( + struct sh_css_isp_ref_isp_config *to, + const struct ia_css_ref_configuration *from, + unsigned size) +{ + unsigned elems_a = ISP_VEC_NELEMS, i; + + (void)size; + ia_css_dma_configure_from_info(&to->port_b, &(from->ref_frames[0]->info)); + to->width_a_over_b = elems_a / to->port_b.elems; + to->dvs_frame_delay = from->dvs_frame_delay; + for (i = 0; i < MAX_NUM_VIDEO_DELAY_FRAMES; i++) { + if (from->ref_frames[i]) { + to->ref_frame_addr_y[i] = from->ref_frames[i]->data + from->ref_frames[i]->planes.yuv.y.offset; + to->ref_frame_addr_c[i] = from->ref_frames[i]->data + from->ref_frames[i]->planes.yuv.u.offset; + } else { + to->ref_frame_addr_y[i] = 0; + to->ref_frame_addr_c[i] = 0; + } + } + + /* Assume divisiblity here, may need to generalize to fixed point. */ + assert (elems_a % to->port_b.elems == 0); +} + +void +ia_css_ref_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame **ref_frames, + const uint32_t dvs_frame_delay) +{ + struct ia_css_ref_configuration config; + unsigned i; + + for (i = 0; i < MAX_NUM_VIDEO_DELAY_FRAMES; i++) + config.ref_frames[i] = ref_frames[i]; + config.dvs_frame_delay = dvs_frame_delay; + ia_css_configure_ref(binary, &config); +} + +void +ia_css_init_ref_state( + struct sh_css_isp_ref_dmem_state *state, + unsigned size) +{ + (void)size; + assert(MAX_NUM_VIDEO_DELAY_FRAMES >= 2); + state->ref_in_buf_idx = 0; + state->ref_out_buf_idx = 1; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref.host.h new file mode 100644 index 0000000000000000000000000000000000000000..3c6d728d49ec688a979f8938e0969c18f367d5a0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref.host.h @@ -0,0 +1,41 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_REF_HOST_H +#define __IA_CSS_REF_HOST_H + +#include +#include + +#include "ia_css_ref_types.h" +#include "ia_css_ref_param.h" +#include "ia_css_ref_state.h" + +void +ia_css_ref_config( + struct sh_css_isp_ref_isp_config *to, + const struct ia_css_ref_configuration *from, + unsigned size); + +void +ia_css_ref_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame **ref_frames, + const uint32_t dvs_frame_delay); + +void +ia_css_init_ref_state( + struct sh_css_isp_ref_dmem_state *state, + unsigned size); +#endif /* __IA_CSS_REF_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref_param.h new file mode 100644 index 0000000000000000000000000000000000000000..1f1b72a417d1d9ed3e51c8b8920154e19b23c787 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref_param.h @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_REF_PARAM_H +#define __IA_CSS_REF_PARAM_H + +#include +#include "sh_css_defs.h" +#include "dma.h" + +/** Reference frame */ +struct ia_css_ref_configuration { + const struct ia_css_frame *ref_frames[MAX_NUM_VIDEO_DELAY_FRAMES]; + uint32_t dvs_frame_delay; +}; + +struct sh_css_isp_ref_isp_config { + uint32_t width_a_over_b; + struct dma_port_config port_b; + hrt_vaddress ref_frame_addr_y[MAX_NUM_VIDEO_DELAY_FRAMES]; + hrt_vaddress ref_frame_addr_c[MAX_NUM_VIDEO_DELAY_FRAMES]; + uint32_t dvs_frame_delay; +}; + +#endif /* __IA_CSS_REF_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref_state.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref_state.h new file mode 100644 index 0000000000000000000000000000000000000000..7867be8a7958f83e081b582c9645d2d1191d8fed --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref_state.h @@ -0,0 +1,26 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_REF_STATE_H +#define __IA_CSS_REF_STATE_H + +#include "type_support.h" + +/* REF (temporal noise reduction) */ +struct sh_css_isp_ref_dmem_state { + int32_t ref_in_buf_idx; + int32_t ref_out_buf_idx; +}; + +#endif /* __IA_CSS_REF_STATE_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref_types.h new file mode 100644 index 0000000000000000000000000000000000000000..ce0eaeeee9c6ef3fac5528812a88ebc0b1138666 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ref/ref_1.0/ia_css_ref_types.h @@ -0,0 +1,28 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_REF_TYPES_H +#define __IA_CSS_REF_TYPES_H + +/** Reference frame + * + * ISP block: reference frame + */ + +#include + + + +#endif /* __IA_CSS_REF_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.c new file mode 100644 index 0000000000000000000000000000000000000000..39de3697555d6a0096588930ac75695de51991e9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.c @@ -0,0 +1,386 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" +#endif +#include "sh_css_frac.h" +#include "assert_support.h" + +#include "bh/bh_2/ia_css_bh.host.h" +#include "ia_css_s3a.host.h" + +const struct ia_css_3a_config default_3a_config = { + 25559, + 32768, + 7209, + 65535, + 0, + 65535, + {-3344, -6104, -19143, 19143, 6104, 3344, 0}, + {1027, 0, -9219, 16384, -9219, 1027, 0} +}; + +static unsigned int s3a_raw_bit_depth; + +void +ia_css_s3a_configure(unsigned int raw_bit_depth) +{ + s3a_raw_bit_depth = raw_bit_depth; +} + +static void +ia_css_ae_encode( + struct sh_css_isp_ae_params *to, + const struct ia_css_3a_config *from, + unsigned size) +{ + (void)size; + /* coefficients to calculate Y */ + to->y_coef_r = + uDIGIT_FITTING(from->ae_y_coef_r, 16, SH_CSS_AE_YCOEF_SHIFT); + to->y_coef_g = + uDIGIT_FITTING(from->ae_y_coef_g, 16, SH_CSS_AE_YCOEF_SHIFT); + to->y_coef_b = + uDIGIT_FITTING(from->ae_y_coef_b, 16, SH_CSS_AE_YCOEF_SHIFT); +} + +static void +ia_css_awb_encode( + struct sh_css_isp_awb_params *to, + const struct ia_css_3a_config *from, + unsigned size) +{ + (void)size; + /* AWB level gate */ + to->lg_high_raw = + uDIGIT_FITTING(from->awb_lg_high_raw, 16, s3a_raw_bit_depth); + to->lg_low = + uDIGIT_FITTING(from->awb_lg_low, 16, SH_CSS_BAYER_BITS); + to->lg_high = + uDIGIT_FITTING(from->awb_lg_high, 16, SH_CSS_BAYER_BITS); +} + +static void +ia_css_af_encode( + struct sh_css_isp_af_params *to, + const struct ia_css_3a_config *from, + unsigned size) +{ + unsigned int i; + (void)size; + + /* af fir coefficients */ + for (i = 0; i < 7; ++i) { + to->fir1[i] = + sDIGIT_FITTING(from->af_fir1_coef[i], 15, + SH_CSS_AF_FIR_SHIFT); + to->fir2[i] = + sDIGIT_FITTING(from->af_fir2_coef[i], 15, + SH_CSS_AF_FIR_SHIFT); + } +} + +void +ia_css_s3a_encode( + struct sh_css_isp_s3a_params *to, + const struct ia_css_3a_config *from, + unsigned size) +{ + (void)size; + + ia_css_ae_encode(&to->ae, from, sizeof(to->ae)); + ia_css_awb_encode(&to->awb, from, sizeof(to->awb)); + ia_css_af_encode(&to->af, from, sizeof(to->af)); +} + +#if 0 +void +ia_css_process_s3a( + unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params) +{ + short dmem_offset = stage->binary->info->mem_offsets->dmem.s3a; + + assert(params != NULL); + + if (dmem_offset >= 0) { + ia_css_s3a_encode((struct sh_css_isp_s3a_params *) + &stage->isp_mem_params[IA_CSS_ISP_DMEM0].address[dmem_offset], + ¶ms->s3a_config); + ia_css_bh_encode((struct sh_css_isp_bh_params *) + &stage->isp_mem_params[IA_CSS_ISP_DMEM0].address[dmem_offset], + ¶ms->s3a_config); + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM0] = true; + } + + params->isp_params_changed = true; +} +#endif + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_ae_dump( + const struct sh_css_isp_ae_params *ae, + unsigned level) +{ + if (!ae) return; + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ae_y_coef_r", ae->y_coef_r); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ae_y_coef_g", ae->y_coef_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ae_y_coef_b", ae->y_coef_b); +} + +void +ia_css_awb_dump( + const struct sh_css_isp_awb_params *awb, + unsigned level) +{ + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "awb_lg_high_raw", awb->lg_high_raw); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "awb_lg_low", awb->lg_low); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "awb_lg_high", awb->lg_high); +} + +void +ia_css_af_dump( + const struct sh_css_isp_af_params *af, + unsigned level) +{ + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[0]", af->fir1[0]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[1]", af->fir1[1]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[2]", af->fir1[2]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[3]", af->fir1[3]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[4]", af->fir1[4]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[5]", af->fir1[5]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir1[6]", af->fir1[6]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[0]", af->fir2[0]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[1]", af->fir2[1]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[2]", af->fir2[2]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[3]", af->fir2[3]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[4]", af->fir2[4]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[5]", af->fir2[5]); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "af_fir2[6]", af->fir2[6]); +} + +void +ia_css_s3a_dump( + const struct sh_css_isp_s3a_params *s3a, + unsigned level) +{ + ia_css_debug_dtrace(level, "S3A Support:\n"); + ia_css_ae_dump (&s3a->ae, level); + ia_css_awb_dump (&s3a->awb, level); + ia_css_af_dump (&s3a->af, level); +} + +void +ia_css_s3a_debug_dtrace( + const struct ia_css_3a_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.ae_y_coef_r=%d, config.ae_y_coef_g=%d, " + "config.ae_y_coef_b=%d, config.awb_lg_high_raw=%d, " + "config.awb_lg_low=%d, config.awb_lg_high=%d\n", + config->ae_y_coef_r, config->ae_y_coef_g, + config->ae_y_coef_b, config->awb_lg_high_raw, + config->awb_lg_low, config->awb_lg_high); +} +#endif + +void +ia_css_s3a_hmem_decode( + struct ia_css_3a_statistics *host_stats, + const struct ia_css_bh_table *hmem_buf) +{ +#if defined(HAS_NO_HMEM) + (void)host_stats; + (void)hmem_buf; +#else + struct ia_css_3a_rgby_output *out_ptr; + int i; + + /* pixel counts(BQ) for 3A area */ + int count_for_3a; + int sum_r, diff; + + assert(host_stats != NULL); + assert(host_stats->rgby_data != NULL); + assert(hmem_buf != NULL); + + count_for_3a = host_stats->grid.width * host_stats->grid.height + * host_stats->grid.bqs_per_grid_cell + * host_stats->grid.bqs_per_grid_cell; + + out_ptr = host_stats->rgby_data; + + ia_css_bh_hmem_decode(out_ptr, hmem_buf); + + /* Calculate sum of histogram of R, + which should not be less than count_for_3a */ + sum_r = 0; + for (i = 0; i < HMEM_UNIT_SIZE; i++) { + sum_r += out_ptr[i].r; + } + if (sum_r < count_for_3a) { + /* histogram is invalid */ + return; + } + + /* Verify for sum of histogram of R/G/B/Y */ +#if 0 + { + int sum_g = 0; + int sum_b = 0; + int sum_y = 0; + for (i = 0; i < HMEM_UNIT_SIZE; i++) { + sum_g += out_ptr[i].g; + sum_b += out_ptr[i].b; + sum_y += out_ptr[i].y; + } + if (sum_g != sum_r || sum_b != sum_r || sum_y != sum_r) { + /* histogram is invalid */ + return; + } + } +#endif + + /* + * Limit the histogram area only to 3A area. + * In DSP, the histogram of 0 is incremented for pixels + * which are outside of 3A area. That amount should be subtracted here. + * hist[0] = hist[0] - ((sum of all hist[]) - (pixel count for 3A area)) + */ + diff = sum_r - count_for_3a; + out_ptr[0].r -= diff; + out_ptr[0].g -= diff; + out_ptr[0].b -= diff; + out_ptr[0].y -= diff; +#endif +} + +void +ia_css_s3a_dmem_decode( + struct ia_css_3a_statistics *host_stats, + const struct ia_css_3a_output *isp_stats) +{ + int isp_width, host_width, height, i; + struct ia_css_3a_output *host_ptr; + + assert(host_stats != NULL); + assert(host_stats->data != NULL); + assert(isp_stats != NULL); + + isp_width = host_stats->grid.aligned_width; + host_width = host_stats->grid.width; + height = host_stats->grid.height; + host_ptr = host_stats->data; + + /* Getting 3A statistics from DMEM does not involve any + * transformation (like the VMEM version), we just copy the data + * using a different output width. */ + for (i = 0; i < height; i++) { + memcpy(host_ptr, isp_stats, host_width * sizeof(*host_ptr)); + isp_stats += isp_width; + host_ptr += host_width; + } +} + +/* MW: this is an ISP function */ +STORAGE_CLASS_INLINE int +merge_hi_lo_14(unsigned short hi, unsigned short lo) +{ + int val = (int) ((((unsigned int) hi << 14) & 0xfffc000) | + ((unsigned int) lo & 0x3fff)); + return val; +} + +void +ia_css_s3a_vmem_decode( + struct ia_css_3a_statistics *host_stats, + const uint16_t *isp_stats_hi, + const uint16_t *isp_stats_lo) +{ + int out_width, out_height, chunk, rest, kmax, y, x, k, elm_start, elm, ofs; + const uint16_t *hi, *lo; + struct ia_css_3a_output *output; + + assert(host_stats!= NULL); + assert(host_stats->data != NULL); + assert(isp_stats_hi != NULL); + assert(isp_stats_lo != NULL); + + output = host_stats->data; + out_width = host_stats->grid.width; + out_height = host_stats->grid.height; + hi = isp_stats_hi; + lo = isp_stats_lo; + + chunk = (ISP_VEC_NELEMS >> host_stats->grid.deci_factor_log2); + chunk = max(chunk, 1); + + for (y = 0; y < out_height; y++) { + elm_start = y * ISP_S3ATBL_HI_LO_STRIDE; + rest = out_width; + x = 0; + while (x < out_width) { + kmax = (rest > chunk) ? chunk : rest; + ofs = y * out_width + x; + elm = elm_start + x * sizeof(*output) / sizeof(int32_t); + for (k = 0; k < kmax; k++, elm++) { + output[ofs + k].ae_y = merge_hi_lo_14( + hi[elm + chunk * 0], lo[elm + chunk * 0]); + output[ofs + k].awb_cnt = merge_hi_lo_14( + hi[elm + chunk * 1], lo[elm + chunk * 1]); + output[ofs + k].awb_gr = merge_hi_lo_14( + hi[elm + chunk * 2], lo[elm + chunk * 2]); + output[ofs + k].awb_r = merge_hi_lo_14( + hi[elm + chunk * 3], lo[elm + chunk * 3]); + output[ofs + k].awb_b = merge_hi_lo_14( + hi[elm + chunk * 4], lo[elm + chunk * 4]); + output[ofs + k].awb_gb = merge_hi_lo_14( + hi[elm + chunk * 5], lo[elm + chunk * 5]); + output[ofs + k].af_hpf1 = merge_hi_lo_14( + hi[elm + chunk * 6], lo[elm + chunk * 6]); + output[ofs + k].af_hpf2 = merge_hi_lo_14( + hi[elm + chunk * 7], lo[elm + chunk * 7]); + } + x += chunk; + rest -= chunk; + } + } +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h new file mode 100644 index 0000000000000000000000000000000000000000..4bc6c0bf478f88353696ec7df7365e1cf85bdf16 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.h @@ -0,0 +1,77 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_S3A_HOST_H +#define __IA_CSS_S3A_HOST_H + +#include "ia_css_s3a_types.h" +#include "ia_css_s3a_param.h" +#include "bh/bh_2/ia_css_bh.host.h" + +extern const struct ia_css_3a_config default_3a_config; + +void +ia_css_s3a_configure( + unsigned int raw_bit_depth); + +void +ia_css_s3a_encode( + struct sh_css_isp_s3a_params *to, + const struct ia_css_3a_config *from, + unsigned size); + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_ae_dump( + const struct sh_css_isp_ae_params *ae, + unsigned level); + +void +ia_css_awb_dump( + const struct sh_css_isp_awb_params *awb, + unsigned level); + +void +ia_css_af_dump( + const struct sh_css_isp_af_params *af, + unsigned level); + +void +ia_css_s3a_dump( + const struct sh_css_isp_s3a_params *s3a, + unsigned level); + +void +ia_css_s3a_debug_dtrace( + const struct ia_css_3a_config *config, + unsigned level); +#endif + +void +ia_css_s3a_hmem_decode( + struct ia_css_3a_statistics *host_stats, + const struct ia_css_bh_table *hmem_buf); + +void +ia_css_s3a_dmem_decode( + struct ia_css_3a_statistics *host_stats, + const struct ia_css_3a_output *isp_stats); + +void +ia_css_s3a_vmem_decode( + struct ia_css_3a_statistics *host_stats, + const uint16_t *isp_stats_hi, + const uint16_t *isp_stats_lo); + +#endif /* __IA_CSS_S3A_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a_param.h new file mode 100644 index 0000000000000000000000000000000000000000..35fb0a2c921a19ac1c53797c5ab8e3bebe22c84c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a_param.h @@ -0,0 +1,54 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_S3A_PARAM_H +#define __IA_CSS_S3A_PARAM_H + +#include "type_support.h" + +/* AE (3A Support) */ +struct sh_css_isp_ae_params { + /* coefficients to calculate Y */ + int32_t y_coef_r; + int32_t y_coef_g; + int32_t y_coef_b; +}; + +/* AWB (3A Support) */ +struct sh_css_isp_awb_params { + int32_t lg_high_raw; + int32_t lg_low; + int32_t lg_high; +}; + +/* AF (3A Support) */ +struct sh_css_isp_af_params { + int32_t fir1[7]; + int32_t fir2[7]; +}; + +/* S3A (3A Support) */ +struct sh_css_isp_s3a_params { + /* coefficients to calculate Y */ + struct sh_css_isp_ae_params ae; + + /* AWB level gate */ + struct sh_css_isp_awb_params awb; + + /* af fir coefficients */ + struct sh_css_isp_af_params af; +}; + + +#endif /* __IA_CSS_S3A_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a_types.h new file mode 100644 index 0000000000000000000000000000000000000000..f57ed1ec5981a4f17c19fff115bfcdbcc6c818c1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a_types.h @@ -0,0 +1,266 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_S3A_TYPES_H +#define __IA_CSS_S3A_TYPES_H + +/** @file +* CSS-API header file for 3A statistics parameters. +*/ + +#include + +#if (defined(SYSTEM_css_skycam_c0_system)) && (! defined(PIPE_GENERATION) ) +#include "../../../../components/stats_3a/src/stats_3a_public.h" +#endif + +/** 3A configuration. This configures the 3A statistics collection + * module. + */ + +/** 3A statistics grid + * + * ISP block: S3A1 (3A Support for 3A ver.1 (Histogram is not used for AE)) + * S3A2 (3A Support for 3A ver.2 (Histogram is used for AE)) + * ISP1: S3A1 is used. + * ISP2: S3A2 is used. + */ +struct ia_css_3a_grid_info { + +#if defined(SYSTEM_css_skycam_c0_system) + uint32_t ae_enable; /**< ae enabled in binary, + 0:disabled, 1:enabled */ + struct ae_public_config_grid_config ae_grd_info; /**< see description in ae_public.h*/ + + uint32_t awb_enable; /**< awb enabled in binary, + 0:disabled, 1:enabled */ + struct awb_public_config_grid_config awb_grd_info; /**< see description in awb_public.h*/ + + uint32_t af_enable; /**< af enabled in binary, + 0:disabled, 1:enabled */ + struct af_public_grid_config af_grd_info; /**< see description in af_public.h*/ + + uint32_t awb_fr_enable; /**< awb_fr enabled in binary, + 0:disabled, 1:enabled */ + struct awb_fr_public_grid_config awb_fr_grd_info;/**< see description in awb_fr_public.h*/ + + uint32_t elem_bit_depth; /**< TODO:Taken from BYT - need input from AIQ + if needed for SKC + Bit depth of element used + to calculate 3A statistics. + This is 13, which is the normalized + bayer bit depth in DSP. */ + +#else + uint32_t enable; /**< 3A statistics enabled. + 0:disabled, 1:enabled */ + uint32_t use_dmem; /**< DMEM or VMEM determines layout. + 0:3A statistics are stored to VMEM, + 1:3A statistics are stored to DMEM */ + uint32_t has_histogram; /**< Statistics include histogram. + 0:no histogram, 1:has histogram */ + uint32_t width; /**< Width of 3A grid table. + (= Horizontal number of grid cells + in table, which cells have effective + statistics.) */ + uint32_t height; /**< Height of 3A grid table. + (= Vertical number of grid cells + in table, which cells have effective + statistics.) */ + uint32_t aligned_width; /**< Horizontal stride (for alloc). + (= Horizontal number of grid cells + in table, which means + the allocated width.) */ + uint32_t aligned_height; /**< Vertical stride (for alloc). + (= Vertical number of grid cells + in table, which means + the allocated height.) */ + uint32_t bqs_per_grid_cell; /**< Grid cell size in BQ(Bayer Quad) unit. + (1BQ means {Gr,R,B,Gb}(2x2 pixels).) + Valid values are 8,16,32,64. */ + uint32_t deci_factor_log2; /**< log2 of bqs_per_grid_cell. */ + uint32_t elem_bit_depth; /**< Bit depth of element used + to calculate 3A statistics. + This is 13, which is the normalized + bayer bit depth in DSP. */ +#endif +}; + + +#if defined(SYSTEM_css_skycam_c0_system) +#if defined USE_NEW_AE_STRUCT || defined USE_NEW_AWB_STRUCT +#define DEFAULT_3A_GRID_INFO \ +{ \ + 0, /* ae_enable */ \ + {0,0,0,0,0,0,0}, /* AE: width,height,b_width,b_height,x_start,y_start*/ \ + 0, /* awb_enable */ \ + {0,0,0,0,0,0}, /* AWB: width,height,b_width,b_height,x_start,y_start*/ \ + 0, /* af_enable */ \ + {0,0,0,0,0,0,0}, /* AF: width,height,b_width,b_height,x_start,y_start,ff_en*/ \ + 0, /* awb_fr_enable */ \ + {0,0,0,0,0,0,0}, /* AWB_FR: width,height,b_width,b_height,x_start,y_start,ff_en*/ \ + 0, /* elem_bit_depth */ \ +} +#else +#define DEFAULT_3A_GRID_INFO \ +{ \ + 0, /* ae_enable */ \ + {0,0,0,0,0,0,0,0,0}, /* AE: width,height,b_width,b_height,x_start,y_start,x_end,y_end*/ \ + 0, /* awb_enable */ \ + {0,0,0,0,0,0,0,0}, /* AWB: width,height,b_width,b_height,x_start,y_start,x_end,y_end*/ \ + 0, /* af_enable */ \ + {0,0,0,0,0,0,0}, /* AF: width,height,b_width,b_height,x_start,y_start,ff_en*/ \ + 0, /* awb_fr_enable */ \ + {0,0,0,0,0,0,0}, /* AWB_FR: width,height,b_width,b_height,x_start,y_start,ff_en*/ \ + 0, /* elem_bit_depth */ \ +} +#endif /* USE_NEW_AE_STRUCT || defined USE_NEW_AWB_STRUCT */ + +#else +#define DEFAULT_3A_GRID_INFO \ +{ \ + 0, /* enable */ \ + 0, /* use_dmem */ \ + 0, /* has_histogram */ \ + 0, /* width */ \ + 0, /* height */ \ + 0, /* aligned_width */ \ + 0, /* aligned_height */ \ + 0, /* bqs_per_grid_cell */ \ + 0, /* deci_factor_log2 */ \ + 0, /* elem_bit_depth */ \ +} + +#endif + +/* This struct should be split into 3, for AE, AWB and AF. + * However, that will require driver/ 3A lib modifications. + */ + +/** 3A configuration. This configures the 3A statistics collection + * module. + * + * ae_y_*: Coefficients to calculate luminance from bayer. + * awb_lg_*: Thresholds to check the saturated bayer pixels for AWB. + * Condition of effective pixel for AWB level gate check: + * bayer(sensor) <= awb_lg_high_raw && + * bayer(when AWB statisitcs is calculated) >= awb_lg_low && + * bayer(when AWB statisitcs is calculated) <= awb_lg_high + * af_fir*: Coefficients of high pass filter to calculate AF statistics. + * + * ISP block: S3A1(ae_y_* for AE/AF, awb_lg_* for AWB) + * S3A2(ae_y_* for AF, awb_lg_* for AWB) + * SDVS1(ae_y_*) + * SDVS2(ae_y_*) + * ISP1: S3A1 and SDVS1 are used. + * ISP2: S3A2 and SDVS2 are used. + */ +struct ia_css_3a_config { + ia_css_u0_16 ae_y_coef_r; /**< Weight of R for Y. + u0.16, [0,65535], + default/ineffective 25559 */ + ia_css_u0_16 ae_y_coef_g; /**< Weight of G for Y. + u0.16, [0,65535], + default/ineffective 32768 */ + ia_css_u0_16 ae_y_coef_b; /**< Weight of B for Y. + u0.16, [0,65535], + default/ineffective 7209 */ + ia_css_u0_16 awb_lg_high_raw; /**< AWB level gate high for raw. + u0.16, [0,65535], + default 65472(=1023*64), + ineffective 65535 */ + ia_css_u0_16 awb_lg_low; /**< AWB level gate low. + u0.16, [0,65535], + default 64(=1*64), + ineffective 0 */ + ia_css_u0_16 awb_lg_high; /**< AWB level gate high. + u0.16, [0,65535], + default 65535, + ineffective 65535 */ + ia_css_s0_15 af_fir1_coef[7]; /**< AF FIR coefficients of fir1. + s0.15, [-32768,32767], + default/ineffective + -6689,-12207,-32768,32767,12207,6689,0 */ + ia_css_s0_15 af_fir2_coef[7]; /**< AF FIR coefficients of fir2. + s0.15, [-32768,32767], + default/ineffective + 2053,0,-18437,32767,-18437,2053,0 */ +}; + +/** 3A statistics. This structure describes the data stored + * in each 3A grid point. + * + * ISP block: S3A1 (3A Support for 3A ver.1) (Histogram is not used for AE) + * S3A2 (3A Support for 3A ver.2) (Histogram is used for AE) + * - ae_y is used only for S3A1. + * - awb_* and af_* are used both for S3A1 and S3A2. + * ISP1: S3A1 is used. + * ISP2: S3A2 is used. + */ +struct ia_css_3a_output { + int32_t ae_y; /**< Sum of Y in a statistics window, for AE. + (u19.13) */ + int32_t awb_cnt; /**< Number of effective pixels + in a statistics window. + Pixels passed by the AWB level gate check are + judged as "effective". (u32) */ + int32_t awb_gr; /**< Sum of Gr in a statistics window, for AWB. + All Gr pixels (not only for effective pixels) + are summed. (u19.13) */ + int32_t awb_r; /**< Sum of R in a statistics window, for AWB. + All R pixels (not only for effective pixels) + are summed. (u19.13) */ + int32_t awb_b; /**< Sum of B in a statistics window, for AWB. + All B pixels (not only for effective pixels) + are summed. (u19.13) */ + int32_t awb_gb; /**< Sum of Gb in a statistics window, for AWB. + All Gb pixels (not only for effective pixels) + are summed. (u19.13) */ + int32_t af_hpf1; /**< Sum of |Y| following high pass filter af_fir1 + within a statistics window, for AF. (u19.13) */ + int32_t af_hpf2; /**< Sum of |Y| following high pass filter af_fir2 + within a statistics window, for AF. (u19.13) */ +}; + + +/** 3A Statistics. This structure describes the statistics that are generated + * using the provided configuration (ia_css_3a_config). + */ +struct ia_css_3a_statistics { + struct ia_css_3a_grid_info grid; /**< grid info contains the dimensions of the 3A grid */ + struct ia_css_3a_output *data; /**< the pointer to 3a_output[grid.width * grid.height] + containing the 3A statistics */ + struct ia_css_3a_rgby_output *rgby_data;/**< the pointer to 3a_rgby_output[256] + containing the histogram */ +}; + +/** Histogram (Statistics for AE). + * + * 4 histograms(r,g,b,y), + * 256 bins for each histogram, unsigned 24bit value for each bin. + * struct ia_css_3a_rgby_output data[256]; + + * ISP block: HIST2 + * (ISP1: HIST2 is not used.) + * ISP2: HIST2 is used. + */ +struct ia_css_3a_rgby_output { + uint32_t r; /**< Number of R of one bin of the histogram R. (u24) */ + uint32_t g; /**< Number of G of one bin of the histogram G. (u24) */ + uint32_t b; /**< Number of B of one bin of the histogram B. (u24) */ + uint32_t y; /**< Number of Y of one bin of the histogram Y. (u24) */ +}; + +#endif /* __IA_CSS_S3A_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a_stat_ls/ia_css_s3a_stat_ls_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a_stat_ls/ia_css_s3a_stat_ls_param.h new file mode 100644 index 0000000000000000000000000000000000000000..8b2b56b0310b6f27de2f1d748acf9b7fda1b96cf --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a_stat_ls/ia_css_s3a_stat_ls_param.h @@ -0,0 +1,45 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_S3A_STAT_LS_PARAM_H +#define __IA_CSS_S3A_STAT_LS_PARAM_H + +#include "type_support.h" +#ifdef ISP2401 +#include "../../io_ls/common/ia_css_common_io_types.h" +#endif + +#define NUM_S3A_LS 1 + +/** s3a statistics store */ +#ifdef ISP2401 +struct ia_css_s3a_stat_ls_configuration { + uint32_t s3a_grid_size_log2; +}; + +#endif +struct sh_css_isp_s3a_stat_ls_isp_config { +#ifndef ISP2401 + uint32_t base_address[NUM_S3A_LS]; + uint32_t width[NUM_S3A_LS]; + uint32_t height[NUM_S3A_LS]; + uint32_t stride[NUM_S3A_LS]; +#endif + uint32_t s3a_grid_size_log2[NUM_S3A_LS]; +}; + +#ifndef ISP2401 + +#endif +#endif /* __IA_CSS_S3A_STAT_LS_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a_stat_ls/ia_css_s3a_stat_store_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a_stat_ls/ia_css_s3a_stat_store_param.h new file mode 100644 index 0000000000000000000000000000000000000000..676b42d364e8830e310d772a6c763aad1ce714f4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/s3a_stat_ls/ia_css_s3a_stat_store_param.h @@ -0,0 +1,21 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_S3A_STAT_STORE_PARAM_H +#define __IA_CSS_S3A_STAT_STORE_PARAM_H + +#include "ia_css_s3a_stat_ls_param.h" + + +#endif /* __IA_CSS_S3A_STAT_STORE_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/satm/ia_css_satm.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/satm/ia_css_satm.host.c new file mode 100644 index 0000000000000000000000000000000000000000..d35194b91164133fea179712a1534535c2a54784 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/satm/ia_css_satm.host.c @@ -0,0 +1,27 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_satm.host.h" + + +void +ia_css_satm_init_config( + struct sh_css_isp_satm_params *to, + const struct ia_css_satm_config *from, + unsigned size) +{ + (void) size; + + to->params.test_satm = from->params.test_satm; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/satm/ia_css_satm.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/satm/ia_css_satm.host.h new file mode 100644 index 0000000000000000000000000000000000000000..807b716e05eced53b9fb9f2e044082bf6a88fc31 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/satm/ia_css_satm.host.h @@ -0,0 +1,29 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SATM_HOST_H +#define __IA_CSS_SATM_HOST_H + +#include "ia_css_satm_param.h" +#include "ia_css_satm_types.h" + +extern const struct ia_css_satm_config default_satm_config; + +void +ia_css_satm_init_config( + struct sh_css_isp_satm_params *to, + const struct ia_css_satm_config *from, + unsigned size); + +#endif /* __IA_CSS_SATM_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/satm/ia_css_satm_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/satm/ia_css_satm_param.h new file mode 100644 index 0000000000000000000000000000000000000000..062f79aa465b4977ba0807f1b36b3346959425a9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/satm/ia_css_satm_param.h @@ -0,0 +1,30 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SATM_PARAMS_H +#define __IA_CSS_SATM_PARAMS_H + +#include "type_support.h" + +/* SATM parameters on ISP. */ +struct sh_css_satm_params { + int32_t test_satm; +}; + +/* SATM ISP parameters */ +struct sh_css_isp_satm_params { + struct sh_css_satm_params params; +}; + +#endif /* __IA_CSS_SATM_PARAMS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/satm/ia_css_satm_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/satm/ia_css_satm_types.h new file mode 100644 index 0000000000000000000000000000000000000000..94f10e35b80a6d5bb66560d2853b143aba1ea445 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/satm/ia_css_satm_types.h @@ -0,0 +1,35 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SATM_TYPES_H +#define __IA_CSS_SATM_TYPES_H + +/** + * \brief SATM Parameters + * \detail Currently SATM paramters are used only for testing purposes + */ +struct ia_css_satm_params { + int test_satm; /**< Test parameter */ +}; + +/** + * \brief SATM public paramterers. + * \details Struct with all paramters for SATM that can be seet from + * the CSS API. Currenly, only test paramters are defined. + */ +struct ia_css_satm_config { + struct ia_css_satm_params params; /**< SATM paramaters */ +}; + +#endif /* __IA_CSS_SATM_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sc/sc_1.0/ia_css_sc.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sc/sc_1.0/ia_css_sc.host.c new file mode 100644 index 0000000000000000000000000000000000000000..565ae45b75417264144f673b7f974738287a58c7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sc/sc_1.0/ia_css_sc.host.c @@ -0,0 +1,130 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "assert_support.h" +#ifdef ISP2401 +#include "math_support.h" /* min() */ + +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" +#endif + +#include "ia_css_sc.host.h" + +void +ia_css_sc_encode( + struct sh_css_isp_sc_params *to, + struct ia_css_shading_table **from, + unsigned size) +{ + (void)size; + to->gain_shift = (*from)->fraction_bits; +} + +void +ia_css_sc_dump( + const struct sh_css_isp_sc_params *sc, + unsigned level) +{ + if (!sc) return; + ia_css_debug_dtrace(level, "Shading Correction:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "sc_gain_shift", sc->gain_shift); +} + +#ifdef ISP2401 +void +ia_css_sc_config( + struct sh_css_isp_sc_isp_config *to, + const struct ia_css_sc_configuration *from, + unsigned size) +{ + uint32_t internal_org_x_bqs = from->internal_frame_origin_x_bqs_on_sctbl; + uint32_t internal_org_y_bqs = from->internal_frame_origin_y_bqs_on_sctbl; + uint32_t slice, rest, i; + + (void)size; + + /* The internal_frame_origin_x_bqs_on_sctbl is separated to 8 times of slice_vec. */ + rest = internal_org_x_bqs; + for (i = 0; i < SH_CSS_SC_INTERPED_GAIN_HOR_SLICE_TIMES; i++) { + slice = min(rest, ((uint32_t)ISP_SLICE_NELEMS)); + rest = rest - slice; + to->interped_gain_hor_slice_bqs[i] = slice; + } + + to->internal_frame_origin_y_bqs_on_sctbl = internal_org_y_bqs; +} + +void +ia_css_sc_configure( + const struct ia_css_binary *binary, + uint32_t internal_frame_origin_x_bqs_on_sctbl, + uint32_t internal_frame_origin_y_bqs_on_sctbl) +{ + const struct ia_css_sc_configuration config = { + internal_frame_origin_x_bqs_on_sctbl, + internal_frame_origin_y_bqs_on_sctbl }; + + ia_css_configure_sc(binary, &config); +} + +#endif +/* ------ deprecated(bz675) : from ------ */ +/* It looks like @parameter{} (in *.pipe) is used to generate the process/get/set functions, + for parameters which should be used in the isp kernels. + However, the ia_css_shading_settings structure has a parameter which is used only in the css, + and does not have a parameter which is used in the isp kernels. + Then, I did not use @parameter{} to generate the get/set function + for the ia_css_shading_settings structure. (michie) */ +void +sh_css_get_shading_settings(const struct ia_css_isp_parameters *params, + struct ia_css_shading_settings *settings) +{ + if (settings == NULL) + return; + assert(params != NULL); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_get_shading_settings() enter: settings=%p\n", settings); + + *settings = params->shading_settings; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_get_shading_settings() leave: settings.enable_shading_table_conversion=%d\n", + settings->enable_shading_table_conversion); +} + +void +sh_css_set_shading_settings(struct ia_css_isp_parameters *params, + const struct ia_css_shading_settings *settings) +{ + if (settings == NULL) + return; + assert(params != NULL); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_set_shading_settings() enter: settings.enable_shading_table_conversion=%d\n", + settings->enable_shading_table_conversion); + + params->shading_settings = *settings; + params->shading_settings_changed = true; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_set_shading_settings() leave: return_void\n"); +} +/* ------ deprecated(bz675) : to ------ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sc/sc_1.0/ia_css_sc.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sc/sc_1.0/ia_css_sc.host.h new file mode 100644 index 0000000000000000000000000000000000000000..44e3c43a5d4a6d503b2c5dcbaf05372e27d8e85b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sc/sc_1.0/ia_css_sc.host.h @@ -0,0 +1,77 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SC_HOST_H +#define __IA_CSS_SC_HOST_H + +#include "sh_css_params.h" + +#include "ia_css_sc_types.h" +#include "ia_css_sc_param.h" + +void +ia_css_sc_encode( + struct sh_css_isp_sc_params *to, + struct ia_css_shading_table **from, + unsigned size); + +void +ia_css_sc_dump( + const struct sh_css_isp_sc_params *sc, + unsigned level); + +#ifdef ISP2401 +/** @brief Configure the shading correction. + * @param[out] to Parameters used in the shading correction kernel in the isp. + * @param[in] from Parameters passed from the host. + * @param[in] size Size of the sh_css_isp_sc_isp_config structure. + * + * This function passes the parameters for the shading correction from the host to the isp. + */ +void +ia_css_sc_config( + struct sh_css_isp_sc_isp_config *to, + const struct ia_css_sc_configuration *from, + unsigned size); + +/** @brief Configure the shading correction. + * @param[in] binary The binary, which has the shading correction. + * @param[in] internal_frame_origin_x_bqs_on_sctbl + * X coordinate (in bqs) of the origin of the internal frame on the shading table. + * @param[in] internal_frame_origin_y_bqs_on_sctbl + * Y coordinate (in bqs) of the origin of the internal frame on the shading table. + * + * This function calls the ia_css_configure_sc() function. + * (The ia_css_configure_sc() function is automatically generated in ia_css_isp.configs.c.) + * The ia_css_configure_sc() function calls the ia_css_sc_config() function + * to pass the parameters for the shading correction from the host to the isp. + */ +void +ia_css_sc_configure( + const struct ia_css_binary *binary, + uint32_t internal_frame_origin_x_bqs_on_sctbl, + uint32_t internal_frame_origin_y_bqs_on_sctbl); + +#endif +/* ------ deprecated(bz675) : from ------ */ +void +sh_css_get_shading_settings(const struct ia_css_isp_parameters *params, + struct ia_css_shading_settings *settings); + +void +sh_css_set_shading_settings(struct ia_css_isp_parameters *params, + const struct ia_css_shading_settings *settings); +/* ------ deprecated(bz675) : to ------ */ + +#endif /* __IA_CSS_SC_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sc/sc_1.0/ia_css_sc_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sc/sc_1.0/ia_css_sc_param.h new file mode 100644 index 0000000000000000000000000000000000000000..d997d5137634c7df2047412c681389e0581239e1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sc/sc_1.0/ia_css_sc_param.h @@ -0,0 +1,71 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SC_PARAM_H +#define __IA_CSS_SC_PARAM_H + +#include "type_support.h" + +#ifdef ISP2401 +/* To position the shading center grid point on the center of output image, + * one more grid cell is needed as margin. */ +#define SH_CSS_SCTBL_CENTERING_MARGIN 1 + +/* The shading table width and height are the number of grids, not cells. The last grid should be counted. */ +#define SH_CSS_SCTBL_LAST_GRID_COUNT 1 + +/* Number of horizontal grids per color in the shading table. */ +#define _ISP_SCTBL_WIDTH_PER_COLOR(input_width, deci_factor_log2) \ + (ISP_BQ_GRID_WIDTH(input_width, deci_factor_log2) + \ + SH_CSS_SCTBL_CENTERING_MARGIN + SH_CSS_SCTBL_LAST_GRID_COUNT) + +/* Number of vertical grids per color in the shading table. */ +#define _ISP_SCTBL_HEIGHT(input_height, deci_factor_log2) \ + (ISP_BQ_GRID_HEIGHT(input_height, deci_factor_log2) + \ + SH_CSS_SCTBL_CENTERING_MARGIN + SH_CSS_SCTBL_LAST_GRID_COUNT) + +/* Legacy API: Number of horizontal grids per color in the shading table. */ +#define _ISP_SCTBL_LEGACY_WIDTH_PER_COLOR(input_width, deci_factor_log2) \ + (ISP_BQ_GRID_WIDTH(input_width, deci_factor_log2) + SH_CSS_SCTBL_LAST_GRID_COUNT) + +/* Legacy API: Number of vertical grids per color in the shading table. */ +#define _ISP_SCTBL_LEGACY_HEIGHT(input_height, deci_factor_log2) \ + (ISP_BQ_GRID_HEIGHT(input_height, deci_factor_log2) + SH_CSS_SCTBL_LAST_GRID_COUNT) + +#endif +/* SC (Shading Corrction) */ +struct sh_css_isp_sc_params { + int32_t gain_shift; +}; + +#ifdef ISP2401 +/* Number of horizontal slice times for interpolated gain: + * + * The start position of the internal frame does not match the start position of the shading table. + * To get a vector of shading gains (interpolated horizontally and vertically) + * which matches a vector on the internal frame, + * vec_slice is used for 2 adjacent vectors of shading gains. + * The number of shift times by vec_slice is 8. + * Max grid cell bqs to support the shading table centerting: N = 32 + * CEIL_DIV(N-1, ISP_SLICE_NELEMS) = CEIL_DIV(31, 4) = 8 + */ +#define SH_CSS_SC_INTERPED_GAIN_HOR_SLICE_TIMES 8 + +struct sh_css_isp_sc_isp_config { + uint32_t interped_gain_hor_slice_bqs[SH_CSS_SC_INTERPED_GAIN_HOR_SLICE_TIMES]; + uint32_t internal_frame_origin_y_bqs_on_sctbl; +}; + +#endif +#endif /* __IA_CSS_SC_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sc/sc_1.0/ia_css_sc_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sc/sc_1.0/ia_css_sc_types.h new file mode 100644 index 0000000000000000000000000000000000000000..5a833bc48af1f58509786b79e9af6cba34c39a1d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sc/sc_1.0/ia_css_sc_types.h @@ -0,0 +1,136 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SC_TYPES_H +#define __IA_CSS_SC_TYPES_H + +/** @file +* CSS-API header file for Lens Shading Correction (SC) parameters. +*/ + + +/** Number of color planes in the shading table. */ +#define IA_CSS_SC_NUM_COLORS 4 + +/** The 4 colors that a shading table consists of. + * For each color we store a grid of values. + */ +enum ia_css_sc_color { + IA_CSS_SC_COLOR_GR, /**< Green on a green-red line */ + IA_CSS_SC_COLOR_R, /**< Red */ + IA_CSS_SC_COLOR_B, /**< Blue */ + IA_CSS_SC_COLOR_GB /**< Green on a green-blue line */ +}; + +/** Lens Shading Correction table. + * + * This describes the color shading artefacts + * introduced by lens imperfections. To correct artefacts, + * bayer values should be multiplied by gains in this table. + * + *------------ deprecated(bz675) : from --------------------------- + * When shading_settings.enable_shading_table_conversion is set as 0, + * this shading table is directly sent to the isp. This table should contain + * the data based on the ia_css_shading_info information filled in the css. + * So, the driver needs to get the ia_css_shading_info information + * from the css, prior to generating the shading table. + * + * When shading_settings.enable_shading_table_conversion is set as 1, + * this shading table is converted in the legacy way in the css + * before it is sent to the isp. + * The driver does not need to get the ia_css_shading_info information. + * + * NOTE: + * The shading table conversion will be removed from the css in the near future, + * because it does not support the bayer scaling by sensor. + * Also, we had better generate the shading table only in one place(AIC). + * At the moment, to support the old driver which assumes the conversion is done in the css, + * shading_settings.enable_shading_table_conversion is set as 1 by default. + *------------ deprecated(bz675) : to --------------------------- + * + * ISP block: SC1 + * ISP1: SC1 is used. + * ISP2: SC1 is used. + */ +struct ia_css_shading_table { + uint32_t enable; /**< Set to false for no shading correction. + The data field can be NULL when enable == true */ +/* ------ deprecated(bz675) : from ------ */ + uint32_t sensor_width; /**< Native sensor width in pixels. */ + uint32_t sensor_height; /**< Native sensor height in lines. + When shading_settings.enable_shading_table_conversion is set + as 0, sensor_width and sensor_height are NOT used. + These are used only in the legacy shading table conversion + in the css, when shading_settings. + enable_shading_table_conversion is set as 1. */ +/* ------ deprecated(bz675) : to ------ */ + uint32_t width; /**< Number of data points per line per color. + u8.0, [0,81] */ + uint32_t height; /**< Number of lines of data points per color. + u8.0, [0,61] */ + uint32_t fraction_bits; /**< Bits of fractional part in the data + points. + u8.0, [0,13] */ + uint16_t *data[IA_CSS_SC_NUM_COLORS]; + /**< Table data, one array for each color. + Use ia_css_sc_color to index this array. + u[13-fraction_bits].[fraction_bits], [0,8191] */ +}; + +/* ------ deprecated(bz675) : from ------ */ +/** Shading Correction settings. + * + * NOTE: + * This structure should be removed when the shading table conversion is + * removed from the css. + */ +struct ia_css_shading_settings { + uint32_t enable_shading_table_conversion; /**< Set to 0, + if the conversion of the shading table should be disabled + in the css. (default 1) + 0: The shading table is directly sent to the isp. + The shading table should contain the data based on the + ia_css_shading_info information filled in the css. + 1: The shading table is converted in the css, to be fitted + to the shading table definition required in the isp. + NOTE: + Previously, the shading table was always converted in the css + before it was sent to the isp, and this config was not defined. + Currently, the driver is supposed to pass the shading table + which should be directly sent to the isp. + However, some drivers may still pass the shading table which + needs the conversion without setting this config as 1. + To support such an unexpected case for the time being, + enable_shading_table_conversion is set as 1 by default + in the css. */ +}; +/* ------ deprecated(bz675) : to ------ */ + +#ifdef ISP2401 + +/** Shading Correction configuration. + * + * NOTE: The shading table size is larger than or equal to the internal frame size. + */ +struct ia_css_sc_configuration { + uint32_t internal_frame_origin_x_bqs_on_sctbl; /**< Origin X (in bqs) of internal frame on shading table. */ + uint32_t internal_frame_origin_y_bqs_on_sctbl; /**< Origin Y (in bqs) of internal frame on shading table. */ + /**< NOTE: bqs = size in BQ(Bayer Quad) unit. + 1BQ means {Gr,R,B,Gb}(2x2 pixels). + Horizontal 1 bqs corresponds to horizontal 2 pixels. + Vertical 1 bqs corresponds to vertical 2 pixels. */ +}; +#endif + +#endif /* __IA_CSS_SC_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/scale/scale_1.0/ia_css_scale_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/scale/scale_1.0/ia_css_scale_param.h new file mode 100644 index 0000000000000000000000000000000000000000..fd19f008ff91f190ef75bc4e309960b6ff2634d5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/scale/scale_1.0/ia_css_scale_param.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_SCALE_PARAM_H +#define _IA_CSS_SCALE_PARAM_H + +#include "uds/uds_1.0/ia_css_uds_param.h" + +#endif /* _IA_CSS_SCALE_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_common.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_common.host.h new file mode 100644 index 0000000000000000000000000000000000000000..4eb4910798fab27f596d1a17511ab0df5d4f99a9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_common.host.h @@ -0,0 +1,99 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_SDIS_COMMON_HOST_H +#define _IA_CSS_SDIS_COMMON_HOST_H + +#define ISP_MAX_SDIS_HOR_PROJ_NUM_ISP \ + __ISP_SDIS_HOR_PROJ_NUM_ISP(ISP_MAX_INTERNAL_WIDTH, ISP_MAX_INTERNAL_HEIGHT, \ + SH_CSS_DIS_DECI_FACTOR_LOG2, ISP_PIPE_VERSION) +#define ISP_MAX_SDIS_VER_PROJ_NUM_ISP \ + __ISP_SDIS_VER_PROJ_NUM_ISP(ISP_MAX_INTERNAL_WIDTH, \ + SH_CSS_DIS_DECI_FACTOR_LOG2) + +#define _ISP_SDIS_HOR_COEF_NUM_VECS \ + __ISP_SDIS_HOR_COEF_NUM_VECS(ISP_INTERNAL_WIDTH) +#define ISP_MAX_SDIS_HOR_COEF_NUM_VECS \ + __ISP_SDIS_HOR_COEF_NUM_VECS(ISP_MAX_INTERNAL_WIDTH) +#define ISP_MAX_SDIS_VER_COEF_NUM_VECS \ + __ISP_SDIS_VER_COEF_NUM_VECS(ISP_MAX_INTERNAL_HEIGHT) + +/* SDIS Coefficients: */ +/* The ISP uses vectors to store the coefficients, so we round + the number of coefficients up to vectors. */ +#define __ISP_SDIS_HOR_COEF_NUM_VECS(in_width) _ISP_VECS(_ISP_BQS(in_width)) +#define __ISP_SDIS_VER_COEF_NUM_VECS(in_height) _ISP_VECS(_ISP_BQS(in_height)) + +/* SDIS Projections: + * SDIS1: Horizontal projections are calculated for each line. + * Vertical projections are calculated for each column. + * SDIS2: Projections are calculated for each grid cell. + * Grid cells that do not fall completely within the image are not + * valid. The host needs to use the bigger one for the stride but + * should only return the valid ones to the 3A. */ +#define __ISP_SDIS_HOR_PROJ_NUM_ISP(in_width, in_height, deci_factor_log2, \ + isp_pipe_version) \ + ((isp_pipe_version == 1) ? \ + CEIL_SHIFT(_ISP_BQS(in_height), deci_factor_log2) : \ + CEIL_SHIFT(_ISP_BQS(in_width), deci_factor_log2)) + +#define __ISP_SDIS_VER_PROJ_NUM_ISP(in_width, deci_factor_log2) \ + CEIL_SHIFT(_ISP_BQS(in_width), deci_factor_log2) + +#define SH_CSS_DIS_VER_NUM_COEF_TYPES(b) \ + (((b)->info->sp.pipeline.isp_pipe_version == 2) ? \ + IA_CSS_DVS2_NUM_COEF_TYPES : \ + IA_CSS_DVS_NUM_COEF_TYPES) + +#ifndef PIPE_GENERATION +#if defined(__ISP) || defined (MK_FIRMWARE) + +/* Array cannot be 2-dimensional, since driver ddr allocation does not know stride */ +struct sh_css_isp_sdis_hori_proj_tbl { + int32_t tbl[ISP_DVS_NUM_COEF_TYPES * ISP_MAX_SDIS_HOR_PROJ_NUM_ISP]; +#if DVS2_PROJ_MARGIN > 0 + int32_t margin[DVS2_PROJ_MARGIN]; +#endif +}; + +struct sh_css_isp_sdis_vert_proj_tbl { + int32_t tbl[ISP_DVS_NUM_COEF_TYPES * ISP_MAX_SDIS_VER_PROJ_NUM_ISP]; +#if DVS2_PROJ_MARGIN > 0 + int32_t margin[DVS2_PROJ_MARGIN]; +#endif +}; + +struct sh_css_isp_sdis_hori_coef_tbl { + VMEM_ARRAY(tbl[ISP_DVS_NUM_COEF_TYPES], ISP_MAX_SDIS_HOR_COEF_NUM_VECS*ISP_NWAY); +}; + +struct sh_css_isp_sdis_vert_coef_tbl { + VMEM_ARRAY(tbl[ISP_DVS_NUM_COEF_TYPES], ISP_MAX_SDIS_VER_COEF_NUM_VECS*ISP_NWAY); +}; + +#endif /* defined(__ISP) || defined (MK_FIRMWARE) */ +#endif /* PIPE_GENERATION */ + +#ifndef PIPE_GENERATION +struct s_sdis_config { + unsigned horicoef_vectors; + unsigned vertcoef_vectors; + unsigned horiproj_num; + unsigned vertproj_num; +}; + +extern struct s_sdis_config sdis_config; +#endif + +#endif /* _IA_CSS_SDIS_COMMON_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_common_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_common_types.h new file mode 100644 index 0000000000000000000000000000000000000000..295dc60b778c1016c3b556ddbaa48c4f7f0c4237 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_common_types.h @@ -0,0 +1,232 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SDIS_COMMON_TYPES_H +#define __IA_CSS_SDIS_COMMON_TYPES_H + +/** @file +* CSS-API header file for DVS statistics parameters. +*/ + +#include + +/** DVS statistics grid dimensions in number of cells. + */ + +struct ia_css_dvs_grid_dim { + uint32_t width; /**< Width of DVS grid table in cells */ + uint32_t height; /**< Height of DVS grid table in cells */ +}; + +/** DVS statistics dimensions in number of cells for + * grid, coeffieicient and projection. + */ + +struct ia_css_sdis_info { + struct { + struct ia_css_dvs_grid_dim dim; /* Dimensions */ + struct ia_css_dvs_grid_dim pad; /* Padded dimensions */ + } grid, coef, proj; + uint32_t deci_factor_log2; +}; + +#define IA_CSS_DEFAULT_SDIS_INFO \ + { \ + { { 0, 0 }, /* dim */ \ + { 0, 0 }, /* pad */ \ + }, /* grid */ \ + { { 0, 0 }, /* dim */ \ + { 0, 0 }, /* pad */ \ + }, /* coef */ \ + { { 0, 0 }, /* dim */ \ + { 0, 0 }, /* pad */ \ + }, /* proj */ \ + 0, /* dis_deci_factor_log2 */ \ + } + +/** DVS statistics grid + * + * ISP block: SDVS1 (DIS/DVS Support for DIS/DVS ver.1 (2-axes)) + * SDVS2 (DVS Support for DVS ver.2 (6-axes)) + * ISP1: SDVS1 is used. + * ISP2: SDVS2 is used. + */ +struct ia_css_dvs_grid_res { + uint32_t width; /**< Width of DVS grid table. + (= Horizontal number of grid cells + in table, which cells have effective + statistics.) + For DVS1, this is equal to + the number of vertical statistics. */ + uint32_t aligned_width; /**< Stride of each grid line. + (= Horizontal number of grid cells + in table, which means + the allocated width.) */ + uint32_t height; /**< Height of DVS grid table. + (= Vertical number of grid cells + in table, which cells have effective + statistics.) + For DVS1, This is equal to + the number of horizontal statistics. */ + uint32_t aligned_height;/**< Stride of each grid column. + (= Vertical number of grid cells + in table, which means + the allocated height.) */ +}; + +/* TODO: use ia_css_dvs_grid_res in here. + * However, that implies driver I/F changes + */ +struct ia_css_dvs_grid_info { + uint32_t enable; /**< DVS statistics enabled. + 0:disabled, 1:enabled */ + uint32_t width; /**< Width of DVS grid table. + (= Horizontal number of grid cells + in table, which cells have effective + statistics.) + For DVS1, this is equal to + the number of vertical statistics. */ + uint32_t aligned_width; /**< Stride of each grid line. + (= Horizontal number of grid cells + in table, which means + the allocated width.) */ + uint32_t height; /**< Height of DVS grid table. + (= Vertical number of grid cells + in table, which cells have effective + statistics.) + For DVS1, This is equal to + the number of horizontal statistics. */ + uint32_t aligned_height;/**< Stride of each grid column. + (= Vertical number of grid cells + in table, which means + the allocated height.) */ + uint32_t bqs_per_grid_cell; /**< Grid cell size in BQ(Bayer Quad) unit. + (1BQ means {Gr,R,B,Gb}(2x2 pixels).) + For DVS1, valid value is 64. + For DVS2, valid value is only 64, + currently. */ + uint32_t num_hor_coefs; /**< Number of horizontal coefficients. */ + uint32_t num_ver_coefs; /**< Number of vertical coefficients. */ +}; + +/** Number of DVS statistics levels + */ +#define IA_CSS_DVS_STAT_NUM_OF_LEVELS 3 + +/** DVS statistics generated by accelerator global configuration + */ +struct dvs_stat_public_dvs_global_cfg { + unsigned char kappa; + /**< DVS statistics global configuration - kappa */ + unsigned char match_shift; + /**< DVS statistics global configuration - match_shift */ + unsigned char ybin_mode; + /**< DVS statistics global configuration - y binning mode */ +}; + +/** DVS statistics generated by accelerator level grid + * configuration + */ +struct dvs_stat_public_dvs_level_grid_cfg { + unsigned char grid_width; + /**< DVS statistics grid width */ + unsigned char grid_height; + /**< DVS statistics grid height */ + unsigned char block_width; + /**< DVS statistics block width */ + unsigned char block_height; + /**< DVS statistics block height */ +}; + +/** DVS statistics generated by accelerator level grid start + * configuration + */ +struct dvs_stat_public_dvs_level_grid_start { + unsigned short x_start; + /**< DVS statistics level x start */ + unsigned short y_start; + /**< DVS statistics level y start */ + unsigned char enable; + /**< DVS statistics level enable */ +}; + +/** DVS statistics generated by accelerator level grid end + * configuration + */ +struct dvs_stat_public_dvs_level_grid_end { + unsigned short x_end; + /**< DVS statistics level x end */ + unsigned short y_end; + /**< DVS statistics level y end */ +}; + +/** DVS statistics generated by accelerator Feature Extraction + * Region Of Interest (FE-ROI) configuration + */ +struct dvs_stat_public_dvs_level_fe_roi_cfg { + unsigned char x_start; + /**< DVS statistics fe-roi level x start */ + unsigned char y_start; + /**< DVS statistics fe-roi level y start */ + unsigned char x_end; + /**< DVS statistics fe-roi level x end */ + unsigned char y_end; + /**< DVS statistics fe-roi level y end */ +}; + +/** DVS statistics generated by accelerator public configuration + */ +struct dvs_stat_public_dvs_grd_cfg { + struct dvs_stat_public_dvs_level_grid_cfg grd_cfg; + /**< DVS statistics level grid configuration */ + struct dvs_stat_public_dvs_level_grid_start grd_start; + /**< DVS statistics level grid start configuration */ + struct dvs_stat_public_dvs_level_grid_end grd_end; + /**< DVS statistics level grid end configuration */ +}; + +/** DVS statistics grid generated by accelerator + */ +struct ia_css_dvs_stat_grid_info { + struct dvs_stat_public_dvs_global_cfg dvs_gbl_cfg; + /**< DVS statistics global configuration (kappa, match, binning) */ + struct dvs_stat_public_dvs_grd_cfg grd_cfg[IA_CSS_DVS_STAT_NUM_OF_LEVELS]; + /**< DVS statistics grid configuration (blocks and grids) */ + struct dvs_stat_public_dvs_level_fe_roi_cfg fe_roi_cfg[IA_CSS_DVS_STAT_NUM_OF_LEVELS]; + /**< DVS statistics FE ROI (region of interest) configuration */ +}; + +/** DVS statistics generated by accelerator default grid info + */ +#define DEFAULT_DVS_GRID_INFO { \ +{ \ + { 0, 0, 0}, /* GBL CFG reg: kappa, match_shifrt, binning mode*/ \ + {{{0, 0, 0, 0}, {0, 0, 0}, {0, 0} }, \ + {{0, 0, 0, 0}, {0, 0, 0}, {0, 0} }, \ + {{0, 0, 0, 0}, {0, 0, 0}, {0, 0} } }, \ + {{0, 0, 0, 0}, {4, 0, 0, 0}, {0, 0, 0, 0} } } \ +} + + +/** Union that holds all types of DVS statistics grid info in + * CSS format + * */ +union ia_css_dvs_grid_u { + struct ia_css_dvs_stat_grid_info dvs_stat_grid_info; + /**< DVS statistics produced by accelerator grid info */ + struct ia_css_dvs_grid_info dvs_grid_info; + /**< DVS (DVS1/DVS2) grid info */ +}; + +#endif /* __IA_CSS_SDIS_COMMON_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_param.h new file mode 100644 index 0000000000000000000000000000000000000000..586cc4315c1fef2eaa0ef7d52b04a6178dbb42a9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/common/ia_css_sdis_param.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SDIS_PARAM_COMMON_H +#define __IA_CSS_SDIS_PARAM_COMMON_H + + +#include "sdis/common/ia_css_sdis_common.host.h" + +#endif /* __IA_CSS_SDIS_PARAM_COMMON_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.c new file mode 100644 index 0000000000000000000000000000000000000000..0dde8425c67d714e78d1417782458b0b825bbfa8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.c @@ -0,0 +1,424 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "memory_access.h" +#include "assert_support.h" +#include "ia_css_debug.h" +#include "ia_css_sdis_types.h" +#include "sdis/common/ia_css_sdis_common.host.h" +#include "ia_css_sdis.host.h" + +const struct ia_css_dvs_coefficients default_sdis_config = { + .grid = { 0, 0, 0, 0, 0, 0, 0, 0 }, + .hor_coefs = NULL, + .ver_coefs = NULL +}; + +static void +fill_row(short *private, const short *public, unsigned width, unsigned padding) +{ + assert((int)width >= 0); + assert((int)padding >= 0); + memcpy (private, public, width*sizeof(short)); + memset (&private[width], 0, padding*sizeof(short)); +} + +void ia_css_sdis_horicoef_vmem_encode ( + struct sh_css_isp_sdis_hori_coef_tbl *to, + const struct ia_css_dvs_coefficients *from, + unsigned size) +{ + unsigned aligned_width = from->grid.aligned_width * from->grid.bqs_per_grid_cell; + unsigned width = from->grid.num_hor_coefs; + int padding = aligned_width-width; + unsigned stride = size/IA_CSS_DVS_NUM_COEF_TYPES/sizeof(short); + unsigned total_bytes = aligned_width*IA_CSS_DVS_NUM_COEF_TYPES*sizeof(short); + short *public = from->hor_coefs; + short *private = (short*)to; + unsigned type; + + /* Copy the table, add padding */ + assert(padding >= 0); + assert(total_bytes <= size); + assert(size % (IA_CSS_DVS_NUM_COEF_TYPES*ISP_VEC_NELEMS*sizeof(short)) == 0); + + for (type = 0; type < IA_CSS_DVS_NUM_COEF_TYPES; type++) { + fill_row(&private[type*stride], &public[type*width], width, padding); + } +} + +void ia_css_sdis_vertcoef_vmem_encode ( + struct sh_css_isp_sdis_vert_coef_tbl *to, + const struct ia_css_dvs_coefficients *from, + unsigned size) +{ + unsigned aligned_height = from->grid.aligned_height * from->grid.bqs_per_grid_cell; + unsigned height = from->grid.num_ver_coefs; + int padding = aligned_height-height; + unsigned stride = size/IA_CSS_DVS_NUM_COEF_TYPES/sizeof(short); + unsigned total_bytes = aligned_height*IA_CSS_DVS_NUM_COEF_TYPES*sizeof(short); + short *public = from->ver_coefs; + short *private = (short*)to; + unsigned type; + + /* Copy the table, add padding */ + assert(padding >= 0); + assert(total_bytes <= size); + assert(size % (IA_CSS_DVS_NUM_COEF_TYPES*ISP_VEC_NELEMS*sizeof(short)) == 0); + + for (type = 0; type < IA_CSS_DVS_NUM_COEF_TYPES; type++) { + fill_row(&private[type*stride], &public[type*height], height, padding); + } +} + +void ia_css_sdis_horiproj_encode ( + struct sh_css_isp_sdis_hori_proj_tbl *to, + const struct ia_css_dvs_coefficients *from, + unsigned size) +{ + (void)to; + (void)from; + (void)size; +} + +void ia_css_sdis_vertproj_encode ( + struct sh_css_isp_sdis_vert_proj_tbl *to, + const struct ia_css_dvs_coefficients *from, + unsigned size) +{ + (void)to; + (void)from; + (void)size; +} + +void ia_css_get_isp_dis_coefficients( + struct ia_css_stream *stream, + short *horizontal_coefficients, + short *vertical_coefficients) +{ + struct ia_css_isp_parameters *params; + unsigned int hor_num_isp, ver_num_isp; + unsigned int hor_num_3a, ver_num_3a; + int i; + struct ia_css_binary *dvs_binary; + + IA_CSS_ENTER("void"); + + assert(horizontal_coefficients != NULL); + assert(vertical_coefficients != NULL); + + params = stream->isp_params_configs; + + /* Only video pipe supports DVS */ + dvs_binary = ia_css_stream_get_dvs_binary(stream); + if (!dvs_binary) + return; + + hor_num_isp = dvs_binary->dis.coef.pad.width; + ver_num_isp = dvs_binary->dis.coef.pad.height; + hor_num_3a = dvs_binary->dis.coef.dim.width; + ver_num_3a = dvs_binary->dis.coef.dim.height; + + for (i = 0; i < IA_CSS_DVS_NUM_COEF_TYPES; i++) { + fill_row(&horizontal_coefficients[i*hor_num_isp], + ¶ms->dvs_coefs.hor_coefs[i*hor_num_3a], hor_num_3a, hor_num_isp-hor_num_3a); + } + for (i = 0; i < SH_CSS_DIS_VER_NUM_COEF_TYPES(dvs_binary); i++) { + fill_row(&vertical_coefficients[i*ver_num_isp], + ¶ms->dvs_coefs.ver_coefs[i*ver_num_3a], ver_num_3a, ver_num_isp-ver_num_3a); + } + + IA_CSS_LEAVE("void"); +} + +size_t +ia_css_sdis_hor_coef_tbl_bytes( + const struct ia_css_binary *binary) +{ + if (binary->info->sp.pipeline.isp_pipe_version == 1) + return sizeof(short) * IA_CSS_DVS_NUM_COEF_TYPES * binary->dis.coef.pad.width; + else + return sizeof(short) * IA_CSS_DVS2_NUM_COEF_TYPES * binary->dis.coef.pad.width; +} + +size_t +ia_css_sdis_ver_coef_tbl_bytes( + const struct ia_css_binary *binary) +{ + return sizeof(short) * SH_CSS_DIS_VER_NUM_COEF_TYPES(binary) * binary->dis.coef.pad.height; +} + +void +ia_css_sdis_init_info( + struct ia_css_sdis_info *dis, + unsigned sc_3a_dis_width, + unsigned sc_3a_dis_padded_width, + unsigned sc_3a_dis_height, + unsigned isp_pipe_version, + unsigned enabled) +{ + if (!enabled) { + struct ia_css_sdis_info default_dis = IA_CSS_DEFAULT_SDIS_INFO; + *dis = default_dis; + return; + } + + dis->deci_factor_log2 = SH_CSS_DIS_DECI_FACTOR_LOG2; + + dis->grid.dim.width = + _ISP_BQS(sc_3a_dis_width) >> SH_CSS_DIS_DECI_FACTOR_LOG2; + dis->grid.dim.height = + _ISP_BQS(sc_3a_dis_height) >> SH_CSS_DIS_DECI_FACTOR_LOG2; + dis->grid.pad.width = + CEIL_SHIFT(_ISP_BQS(sc_3a_dis_padded_width), SH_CSS_DIS_DECI_FACTOR_LOG2); + dis->grid.pad.height = + CEIL_SHIFT(_ISP_BQS(sc_3a_dis_height), SH_CSS_DIS_DECI_FACTOR_LOG2); + + dis->coef.dim.width = + (_ISP_BQS(sc_3a_dis_width) >> SH_CSS_DIS_DECI_FACTOR_LOG2) << SH_CSS_DIS_DECI_FACTOR_LOG2; + dis->coef.dim.height = + (_ISP_BQS(sc_3a_dis_height) >> SH_CSS_DIS_DECI_FACTOR_LOG2) << SH_CSS_DIS_DECI_FACTOR_LOG2; + dis->coef.pad.width = + __ISP_SDIS_HOR_COEF_NUM_VECS(sc_3a_dis_padded_width) * ISP_VEC_NELEMS; + dis->coef.pad.height = + __ISP_SDIS_VER_COEF_NUM_VECS(sc_3a_dis_height) * ISP_VEC_NELEMS; + if (isp_pipe_version == 1) { + dis->proj.dim.width = + _ISP_BQS(sc_3a_dis_height) >> SH_CSS_DIS_DECI_FACTOR_LOG2; + dis->proj.dim.height = + _ISP_BQS(sc_3a_dis_width) >> SH_CSS_DIS_DECI_FACTOR_LOG2; + } else { + dis->proj.dim.width = + (_ISP_BQS(sc_3a_dis_width) >> SH_CSS_DIS_DECI_FACTOR_LOG2) * + (_ISP_BQS(sc_3a_dis_height) >> SH_CSS_DIS_DECI_FACTOR_LOG2); + dis->proj.dim.height = + (_ISP_BQS(sc_3a_dis_width) >> SH_CSS_DIS_DECI_FACTOR_LOG2) * + (_ISP_BQS(sc_3a_dis_height) >> SH_CSS_DIS_DECI_FACTOR_LOG2); + } + dis->proj.pad.width = + __ISP_SDIS_HOR_PROJ_NUM_ISP(sc_3a_dis_padded_width, + sc_3a_dis_height, + SH_CSS_DIS_DECI_FACTOR_LOG2, + isp_pipe_version); + dis->proj.pad.height = + __ISP_SDIS_VER_PROJ_NUM_ISP(sc_3a_dis_padded_width, + SH_CSS_DIS_DECI_FACTOR_LOG2); +} + +void ia_css_sdis_clear_coefficients( + struct ia_css_dvs_coefficients *dvs_coefs) +{ + dvs_coefs->hor_coefs = NULL; + dvs_coefs->ver_coefs = NULL; +} + +enum ia_css_err +ia_css_get_dvs_statistics( + struct ia_css_dvs_statistics *host_stats, + const struct ia_css_isp_dvs_statistics *isp_stats) +{ + struct ia_css_isp_dvs_statistics_map *map; + enum ia_css_err ret = IA_CSS_SUCCESS; + + IA_CSS_ENTER("host_stats=%p, isp_stats=%p", host_stats, isp_stats); + + assert(host_stats != NULL); + assert(isp_stats != NULL); + + map = ia_css_isp_dvs_statistics_map_allocate(isp_stats, NULL); + if (map) { + mmgr_load(isp_stats->data_ptr, map->data_ptr, isp_stats->size); + ia_css_translate_dvs_statistics(host_stats, map); + ia_css_isp_dvs_statistics_map_free(map); + } else { + IA_CSS_ERROR("out of memory"); + ret = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + } + + IA_CSS_LEAVE_ERR(ret); + return ret; +} + +void +ia_css_translate_dvs_statistics( + struct ia_css_dvs_statistics *host_stats, + const struct ia_css_isp_dvs_statistics_map *isp_stats) +{ + unsigned int hor_num_isp, ver_num_isp, hor_num_dvs, ver_num_dvs, i; + int32_t *hor_ptr_dvs, *ver_ptr_dvs, *hor_ptr_isp, *ver_ptr_isp; + + assert(host_stats != NULL); + assert(host_stats->hor_proj != NULL); + assert(host_stats->ver_proj != NULL); + assert(isp_stats != NULL); + assert(isp_stats->hor_proj != NULL); + assert(isp_stats->ver_proj != NULL); + + IA_CSS_ENTER("hproj=%p, vproj=%p, haddr=%x, vaddr=%x", + host_stats->hor_proj, host_stats->ver_proj, + isp_stats->hor_proj, isp_stats->ver_proj); + + hor_num_isp = host_stats->grid.aligned_height; + ver_num_isp = host_stats->grid.aligned_width; + hor_ptr_isp = isp_stats->hor_proj; + ver_ptr_isp = isp_stats->ver_proj; + hor_num_dvs = host_stats->grid.height; + ver_num_dvs = host_stats->grid.width; + hor_ptr_dvs = host_stats->hor_proj; + ver_ptr_dvs = host_stats->ver_proj; + + for (i = 0; i < IA_CSS_DVS_NUM_COEF_TYPES; i++) { + memcpy(hor_ptr_dvs, hor_ptr_isp, hor_num_dvs * sizeof(int32_t)); + hor_ptr_isp += hor_num_isp; + hor_ptr_dvs += hor_num_dvs; + + memcpy(ver_ptr_dvs, ver_ptr_isp, ver_num_dvs * sizeof(int32_t)); + ver_ptr_isp += ver_num_isp; + ver_ptr_dvs += ver_num_dvs; + } + + IA_CSS_LEAVE("void"); +} + +struct ia_css_isp_dvs_statistics * +ia_css_isp_dvs_statistics_allocate( + const struct ia_css_dvs_grid_info *grid) +{ + struct ia_css_isp_dvs_statistics *me; + int hor_size, ver_size; + + assert(grid != NULL); + + IA_CSS_ENTER("grid=%p", grid); + + if (!grid->enable) + return NULL; + + me = sh_css_calloc(1,sizeof(*me)); + if (!me) + goto err; + + hor_size = CEIL_MUL(sizeof(int) * IA_CSS_DVS_NUM_COEF_TYPES * grid->aligned_height, + HIVE_ISP_DDR_WORD_BYTES); + ver_size = CEIL_MUL(sizeof(int) * IA_CSS_DVS_NUM_COEF_TYPES * grid->aligned_width, + HIVE_ISP_DDR_WORD_BYTES); + + + me->size = hor_size + ver_size; + me->data_ptr = mmgr_malloc(me->size); + if (me->data_ptr == mmgr_NULL) + goto err; + me->hor_size = hor_size; + me->hor_proj = me->data_ptr; + me->ver_size = ver_size; + me->ver_proj = me->data_ptr + hor_size; + + IA_CSS_LEAVE("return=%p", me); + + return me; +err: + ia_css_isp_dvs_statistics_free(me); + + IA_CSS_LEAVE("return=%p", NULL); + + return NULL; +} + +struct ia_css_isp_dvs_statistics_map * +ia_css_isp_dvs_statistics_map_allocate( + const struct ia_css_isp_dvs_statistics *isp_stats, + void *data_ptr) +{ + struct ia_css_isp_dvs_statistics_map *me; + /* Windows compiler does not like adding sizes to a void * + * so we use a local char * instead. */ + char *base_ptr; + + me = sh_css_malloc(sizeof(*me)); + if (!me) { + IA_CSS_LOG("cannot allocate memory"); + goto err; + } + + me->data_ptr = data_ptr; + me->data_allocated = data_ptr == NULL; + + if (!me->data_ptr) { + me->data_ptr = sh_css_malloc(isp_stats->size); + if (!me->data_ptr) { + IA_CSS_LOG("cannot allocate memory"); + goto err; + } + } + base_ptr = me->data_ptr; + + me->size = isp_stats->size; + /* GCC complains when we assign a char * to a void *, so these + * casts are necessary unfortunately. */ + me->hor_proj = (void*)base_ptr; + me->ver_proj = (void*)(base_ptr + isp_stats->hor_size); + + return me; +err: + if (me) + sh_css_free(me); + return NULL; +} + +void +ia_css_isp_dvs_statistics_map_free(struct ia_css_isp_dvs_statistics_map *me) +{ + if (me) { + if (me->data_allocated) + sh_css_free(me->data_ptr); + sh_css_free(me); + } +} + +void +ia_css_isp_dvs_statistics_free(struct ia_css_isp_dvs_statistics *me) +{ + if (me != NULL) { + mmgr_free(me->data_ptr); + sh_css_free(me); + } +} + +void ia_css_sdis_horicoef_debug_dtrace( + const struct ia_css_dvs_coefficients *config, unsigned level) +{ + (void)config; + (void)level; +} + +void ia_css_sdis_vertcoef_debug_dtrace( + const struct ia_css_dvs_coefficients *config, unsigned level) +{ + (void)config; + (void)level; +} + +void ia_css_sdis_horiproj_debug_dtrace( + const struct ia_css_dvs_coefficients *config, unsigned level) +{ + (void)config; + (void)level; +} + +void ia_css_sdis_vertproj_debug_dtrace( + const struct ia_css_dvs_coefficients *config, unsigned level) +{ + (void)config; + (void)level; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.h new file mode 100644 index 0000000000000000000000000000000000000000..95e2c61bbcbab8fc7fee1eb1035d8c39887b67e4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.h @@ -0,0 +1,101 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SDIS_HOST_H +#define __IA_CSS_SDIS_HOST_H + +#include "ia_css_sdis_types.h" +#include "ia_css_binary.h" +#include "ia_css_stream.h" +#include "sh_css_params.h" + +extern const struct ia_css_dvs_coefficients default_sdis_config; + +/* Opaque here, since size is binary dependent. */ +struct sh_css_isp_sdis_hori_coef_tbl; +struct sh_css_isp_sdis_vert_coef_tbl; +struct sh_css_isp_sdis_hori_proj_tbl; +struct sh_css_isp_sdis_vert_proj_tbl; + +void ia_css_sdis_horicoef_vmem_encode ( + struct sh_css_isp_sdis_hori_coef_tbl *to, + const struct ia_css_dvs_coefficients *from, + unsigned size); + +void ia_css_sdis_vertcoef_vmem_encode ( + struct sh_css_isp_sdis_vert_coef_tbl *to, + const struct ia_css_dvs_coefficients *from, + unsigned size); + +void ia_css_sdis_horiproj_encode ( + struct sh_css_isp_sdis_hori_proj_tbl *to, + const struct ia_css_dvs_coefficients *from, + unsigned size); + +void ia_css_sdis_vertproj_encode ( + struct sh_css_isp_sdis_vert_proj_tbl *to, + const struct ia_css_dvs_coefficients *from, + unsigned size); + +void ia_css_get_isp_dis_coefficients( + struct ia_css_stream *stream, + short *horizontal_coefficients, + short *vertical_coefficients); + +enum ia_css_err +ia_css_get_dvs_statistics( + struct ia_css_dvs_statistics *host_stats, + const struct ia_css_isp_dvs_statistics *isp_stats); + +void +ia_css_translate_dvs_statistics( + struct ia_css_dvs_statistics *host_stats, + const struct ia_css_isp_dvs_statistics_map *isp_stats); + +struct ia_css_isp_dvs_statistics * +ia_css_isp_dvs_statistics_allocate( + const struct ia_css_dvs_grid_info *grid); + +void +ia_css_isp_dvs_statistics_free( + struct ia_css_isp_dvs_statistics *me); + +size_t ia_css_sdis_hor_coef_tbl_bytes(const struct ia_css_binary *binary); +size_t ia_css_sdis_ver_coef_tbl_bytes(const struct ia_css_binary *binary); + +void +ia_css_sdis_init_info( + struct ia_css_sdis_info *dis, + unsigned sc_3a_dis_width, + unsigned sc_3a_dis_padded_width, + unsigned sc_3a_dis_height, + unsigned isp_pipe_version, + unsigned enabled); + +void ia_css_sdis_clear_coefficients( + struct ia_css_dvs_coefficients *dvs_coefs); + +void ia_css_sdis_horicoef_debug_dtrace( + const struct ia_css_dvs_coefficients *config, unsigned level); + +void ia_css_sdis_vertcoef_debug_dtrace( + const struct ia_css_dvs_coefficients *config, unsigned level); + +void ia_css_sdis_horiproj_debug_dtrace( + const struct ia_css_dvs_coefficients *config, unsigned level); + +void ia_css_sdis_vertproj_debug_dtrace( + const struct ia_css_dvs_coefficients *config, unsigned level); + +#endif /* __IA_CSS_SDIS_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_1.0/ia_css_sdis_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_1.0/ia_css_sdis_param.h new file mode 100644 index 0000000000000000000000000000000000000000..2dd8696802d0511ac41a15a0b38f3aac8fd59b9e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_1.0/ia_css_sdis_param.h @@ -0,0 +1,21 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SDIS_PARAM_H +#define __IA_CSS_SDIS_PARAM_H + +#include "sdis.isp.h" + +#endif /* __IA_CSS_SDIS_PARAM_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_1.0/ia_css_sdis_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_1.0/ia_css_sdis_types.h new file mode 100644 index 0000000000000000000000000000000000000000..d408b58a027d957c06624e595d6ec4bde543d848 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_1.0/ia_css_sdis_types.h @@ -0,0 +1,53 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SDIS_TYPES_H +#define __IA_CSS_SDIS_TYPES_H + +/** @file +* CSS-API header file for DVS statistics parameters. +*/ + +/** Number of DVS coefficient types */ +#define IA_CSS_DVS_NUM_COEF_TYPES 6 + +#ifndef PIPE_GENERATION +#include "isp/kernels/sdis/common/ia_css_sdis_common_types.h" +#endif + +/** DVS 1.0 Coefficients. + * This structure describes the coefficients that are needed for the dvs statistics. + */ + +struct ia_css_dvs_coefficients { + struct ia_css_dvs_grid_info grid;/**< grid info contains the dimensions of the dvs grid */ + int16_t *hor_coefs; /**< the pointer to int16_t[grid.num_hor_coefs * IA_CSS_DVS_NUM_COEF_TYPES] + containing the horizontal coefficients */ + int16_t *ver_coefs; /**< the pointer to int16_t[grid.num_ver_coefs * IA_CSS_DVS_NUM_COEF_TYPES] + containing the vertical coefficients */ +}; + +/** DVS 1.0 Statistics. + * This structure describes the statistics that are generated using the provided coefficients. + */ + +struct ia_css_dvs_statistics { + struct ia_css_dvs_grid_info grid;/**< grid info contains the dimensions of the dvs grid */ + int32_t *hor_proj; /**< the pointer to int16_t[grid.height * IA_CSS_DVS_NUM_COEF_TYPES] + containing the horizontal projections */ + int32_t *ver_proj; /**< the pointer to int16_t[grid.width * IA_CSS_DVS_NUM_COEF_TYPES] + containing the vertical projections */ +}; + +#endif /* __IA_CSS_SDIS_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_2/ia_css_sdis2.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_2/ia_css_sdis2.host.c new file mode 100644 index 0000000000000000000000000000000000000000..930061d48df7bb2b8eef4c40f515ca58dfc8e389 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_2/ia_css_sdis2.host.c @@ -0,0 +1,338 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include "memory_access.h" +#include "ia_css_debug.h" +#include "ia_css_sdis2.host.h" + +const struct ia_css_dvs2_coefficients default_sdis2_config = { + .grid = { 0, 0, 0, 0, 0, 0, 0, 0 }, + .hor_coefs = { NULL, NULL, NULL, NULL }, + .ver_coefs = { NULL, NULL, NULL, NULL }, +}; + +static void +fill_row(short *private, const short *public, unsigned width, unsigned padding) +{ + memcpy (private, public, width*sizeof(short)); + memset (&private[width], 0, padding*sizeof(short)); +} + +void ia_css_sdis2_horicoef_vmem_encode ( + struct sh_css_isp_sdis_hori_coef_tbl *to, + const struct ia_css_dvs2_coefficients *from, + unsigned size) +{ + unsigned aligned_width = from->grid.aligned_width * from->grid.bqs_per_grid_cell; + unsigned width = from->grid.num_hor_coefs; + int padding = aligned_width-width; + unsigned stride = size/IA_CSS_DVS2_NUM_COEF_TYPES/sizeof(short); + unsigned total_bytes = aligned_width*IA_CSS_DVS2_NUM_COEF_TYPES*sizeof(short); + short *private = (short*)to; + + + /* Copy the table, add padding */ + assert(padding >= 0); + assert(total_bytes <= size); + assert(size % (IA_CSS_DVS2_NUM_COEF_TYPES*ISP_VEC_NELEMS*sizeof(short)) == 0); + fill_row(&private[0*stride], from->hor_coefs.odd_real, width, padding); + fill_row(&private[1*stride], from->hor_coefs.odd_imag, width, padding); + fill_row(&private[2*stride], from->hor_coefs.even_real, width, padding); + fill_row(&private[3*stride], from->hor_coefs.even_imag, width, padding); +} + +void ia_css_sdis2_vertcoef_vmem_encode ( + struct sh_css_isp_sdis_vert_coef_tbl *to, + const struct ia_css_dvs2_coefficients *from, + unsigned size) +{ + unsigned aligned_height = from->grid.aligned_height * from->grid.bqs_per_grid_cell; + unsigned height = from->grid.num_ver_coefs; + int padding = aligned_height-height; + unsigned stride = size/IA_CSS_DVS2_NUM_COEF_TYPES/sizeof(short); + unsigned total_bytes = aligned_height*IA_CSS_DVS2_NUM_COEF_TYPES*sizeof(short); + short *private = (short*)to; + + /* Copy the table, add padding */ + assert(padding >= 0); + assert(total_bytes <= size); + assert(size % (IA_CSS_DVS2_NUM_COEF_TYPES*ISP_VEC_NELEMS*sizeof(short)) == 0); + fill_row(&private[0*stride], from->ver_coefs.odd_real, height, padding); + fill_row(&private[1*stride], from->ver_coefs.odd_imag, height, padding); + fill_row(&private[2*stride], from->ver_coefs.even_real, height, padding); + fill_row(&private[3*stride], from->ver_coefs.even_imag, height, padding); +} + +void ia_css_sdis2_horiproj_encode ( + struct sh_css_isp_sdis_hori_proj_tbl *to, + const struct ia_css_dvs2_coefficients *from, + unsigned size) +{ + (void)to; + (void)from; + (void)size; +} + +void ia_css_sdis2_vertproj_encode ( + struct sh_css_isp_sdis_vert_proj_tbl *to, + const struct ia_css_dvs2_coefficients *from, + unsigned size) +{ + (void)to; + (void)from; + (void)size; +} + +void ia_css_get_isp_dvs2_coefficients( + struct ia_css_stream *stream, + short *hor_coefs_odd_real, + short *hor_coefs_odd_imag, + short *hor_coefs_even_real, + short *hor_coefs_even_imag, + short *ver_coefs_odd_real, + short *ver_coefs_odd_imag, + short *ver_coefs_even_real, + short *ver_coefs_even_imag) +{ + struct ia_css_isp_parameters *params; + unsigned int hor_num_3a, ver_num_3a; + unsigned int hor_num_isp, ver_num_isp; + struct ia_css_binary *dvs_binary; + + IA_CSS_ENTER("void"); + + assert(stream != NULL); + assert(hor_coefs_odd_real != NULL); + assert(hor_coefs_odd_imag != NULL); + assert(hor_coefs_even_real != NULL); + assert(hor_coefs_even_imag != NULL); + assert(ver_coefs_odd_real != NULL); + assert(ver_coefs_odd_imag != NULL); + assert(ver_coefs_even_real != NULL); + assert(ver_coefs_even_imag != NULL); + + params = stream->isp_params_configs; + + /* Only video pipe supports DVS */ + dvs_binary = ia_css_stream_get_dvs_binary(stream); + if (!dvs_binary) + return; + + hor_num_3a = dvs_binary->dis.coef.dim.width; + ver_num_3a = dvs_binary->dis.coef.dim.height; + hor_num_isp = dvs_binary->dis.coef.pad.width; + ver_num_isp = dvs_binary->dis.coef.pad.height; + + memcpy (hor_coefs_odd_real, params->dvs2_coefs.hor_coefs.odd_real, hor_num_3a * sizeof(short)); + memcpy (hor_coefs_odd_imag, params->dvs2_coefs.hor_coefs.odd_imag, hor_num_3a * sizeof(short)); + memcpy (hor_coefs_even_real, params->dvs2_coefs.hor_coefs.even_real, hor_num_3a * sizeof(short)); + memcpy (hor_coefs_even_imag, params->dvs2_coefs.hor_coefs.even_imag, hor_num_3a * sizeof(short)); + memcpy (ver_coefs_odd_real, params->dvs2_coefs.ver_coefs.odd_real, ver_num_3a * sizeof(short)); + memcpy (ver_coefs_odd_imag, params->dvs2_coefs.ver_coefs.odd_imag, ver_num_3a * sizeof(short)); + memcpy (ver_coefs_even_real, params->dvs2_coefs.ver_coefs.even_real, ver_num_3a * sizeof(short)); + memcpy (ver_coefs_even_imag, params->dvs2_coefs.ver_coefs.even_imag, ver_num_3a * sizeof(short)); + + IA_CSS_LEAVE("void"); +} + +void ia_css_sdis2_clear_coefficients( + struct ia_css_dvs2_coefficients *dvs2_coefs) +{ + dvs2_coefs->hor_coefs.odd_real = NULL; + dvs2_coefs->hor_coefs.odd_imag = NULL; + dvs2_coefs->hor_coefs.even_real = NULL; + dvs2_coefs->hor_coefs.even_imag = NULL; + dvs2_coefs->ver_coefs.odd_real = NULL; + dvs2_coefs->ver_coefs.odd_imag = NULL; + dvs2_coefs->ver_coefs.even_real = NULL; + dvs2_coefs->ver_coefs.even_imag = NULL; +} + +enum ia_css_err +ia_css_get_dvs2_statistics( + struct ia_css_dvs2_statistics *host_stats, + const struct ia_css_isp_dvs_statistics *isp_stats) +{ + struct ia_css_isp_dvs_statistics_map *map; + enum ia_css_err ret = IA_CSS_SUCCESS; + + IA_CSS_ENTER("host_stats=%p, isp_stats=%p", host_stats, isp_stats); + + assert(host_stats != NULL); + assert(isp_stats != NULL); + + map = ia_css_isp_dvs_statistics_map_allocate(isp_stats, NULL); + if (map) { + mmgr_load(isp_stats->data_ptr, map->data_ptr, isp_stats->size); + ia_css_translate_dvs2_statistics(host_stats, map); + ia_css_isp_dvs_statistics_map_free(map); + } else { + IA_CSS_ERROR("out of memory"); + ret = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + } + + IA_CSS_LEAVE_ERR(ret); + return ret; +} + +void +ia_css_translate_dvs2_statistics( + struct ia_css_dvs2_statistics *host_stats, + const struct ia_css_isp_dvs_statistics_map *isp_stats) +{ + unsigned int size_bytes, table_width, table_size, height; + unsigned int src_offset = 0, dst_offset = 0; + int32_t *htemp_ptr, *vtemp_ptr; + + assert(host_stats != NULL); + assert(host_stats->hor_prod.odd_real != NULL); + assert(host_stats->hor_prod.odd_imag != NULL); + assert(host_stats->hor_prod.even_real != NULL); + assert(host_stats->hor_prod.even_imag != NULL); + assert(host_stats->ver_prod.odd_real != NULL); + assert(host_stats->ver_prod.odd_imag != NULL); + assert(host_stats->ver_prod.even_real != NULL); + assert(host_stats->ver_prod.even_imag != NULL); + assert(isp_stats != NULL); + assert(isp_stats->hor_proj != NULL); + assert(isp_stats->ver_proj != NULL); + + IA_CSS_ENTER("hor_coefs.odd_real=%p, hor_coefs.odd_imag=%p, " + "hor_coefs.even_real=%p, hor_coefs.even_imag=%p, " + "ver_coefs.odd_real=%p, ver_coefs.odd_imag=%p, " + "ver_coefs.even_real=%p, ver_coefs.even_imag=%p, " + "haddr=%x, vaddr=%x", + host_stats->hor_prod.odd_real, host_stats->hor_prod.odd_imag, + host_stats->hor_prod.even_real, host_stats->hor_prod.even_imag, + host_stats->ver_prod.odd_real, host_stats->ver_prod.odd_imag, + host_stats->ver_prod.even_real, host_stats->ver_prod.even_imag, + isp_stats->hor_proj, isp_stats->ver_proj); + + /* Host side: reflecting the true width in bytes */ + size_bytes = host_stats->grid.aligned_width * sizeof(*htemp_ptr); + + /* DDR side: need to be aligned to the system bus width */ + /* statistics table width in terms of 32-bit words*/ + table_width = CEIL_MUL(size_bytes, HIVE_ISP_DDR_WORD_BYTES) / sizeof(*htemp_ptr); + table_size = table_width * host_stats->grid.aligned_height; + + htemp_ptr = isp_stats->hor_proj; /* horizontal stats */ + vtemp_ptr = isp_stats->ver_proj; /* vertical stats */ + for (height = 0; height < host_stats->grid.aligned_height; height++) { + /* hor stats */ + memcpy(host_stats->hor_prod.odd_real + dst_offset, + &htemp_ptr[0*table_size+src_offset], size_bytes); + memcpy(host_stats->hor_prod.odd_imag + dst_offset, + &htemp_ptr[1*table_size+src_offset], size_bytes); + memcpy(host_stats->hor_prod.even_real + dst_offset, + &htemp_ptr[2*table_size+src_offset], size_bytes); + memcpy(host_stats->hor_prod.even_imag + dst_offset, + &htemp_ptr[3*table_size+src_offset], size_bytes); + + /* ver stats */ + memcpy(host_stats->ver_prod.odd_real + dst_offset, + &vtemp_ptr[0*table_size+src_offset], size_bytes); + memcpy(host_stats->ver_prod.odd_imag + dst_offset, + &vtemp_ptr[1*table_size+src_offset], size_bytes); + memcpy(host_stats->ver_prod.even_real + dst_offset, + &vtemp_ptr[2*table_size+src_offset], size_bytes); + memcpy(host_stats->ver_prod.even_imag + dst_offset, + &vtemp_ptr[3*table_size+src_offset], size_bytes); + + src_offset += table_width; /* aligned table width */ + dst_offset += host_stats->grid.aligned_width; + } + + IA_CSS_LEAVE("void"); +} + +struct ia_css_isp_dvs_statistics * +ia_css_isp_dvs2_statistics_allocate( + const struct ia_css_dvs_grid_info *grid) +{ + struct ia_css_isp_dvs_statistics *me; + int size; + + assert(grid != NULL); + + IA_CSS_ENTER("grid=%p", grid); + + if (!grid->enable) + return NULL; + + me = sh_css_calloc(1,sizeof(*me)); + if (!me) + goto err; + + /* on ISP 2 SDIS DMA model, every row of projection table width must be + aligned to HIVE_ISP_DDR_WORD_BYTES + */ + size = CEIL_MUL(sizeof(int) * grid->aligned_width, HIVE_ISP_DDR_WORD_BYTES) + * grid->aligned_height * IA_CSS_DVS2_NUM_COEF_TYPES; + + me->size = 2*size; + me->data_ptr = mmgr_malloc(me->size); + if (me->data_ptr == mmgr_NULL) + goto err; + me->hor_proj = me->data_ptr; + me->hor_size = size; + me->ver_proj = me->data_ptr + size; + me->ver_size = size; + + IA_CSS_LEAVE("return=%p", me); + return me; +err: + ia_css_isp_dvs2_statistics_free(me); + IA_CSS_LEAVE("return=%p", NULL); + + return NULL; +} + +void +ia_css_isp_dvs2_statistics_free(struct ia_css_isp_dvs_statistics *me) +{ + if (me != NULL) { + mmgr_free(me->data_ptr); + sh_css_free(me); + } +} + +void ia_css_sdis2_horicoef_debug_dtrace( + const struct ia_css_dvs2_coefficients *config, unsigned level) +{ + (void)config; + (void)level; +} + +void ia_css_sdis2_vertcoef_debug_dtrace( + const struct ia_css_dvs2_coefficients *config, unsigned level) +{ + (void)config; + (void)level; +} + +void ia_css_sdis2_horiproj_debug_dtrace( + const struct ia_css_dvs2_coefficients *config, unsigned level) +{ + (void)config; + (void)level; +} + +void ia_css_sdis2_vertproj_debug_dtrace( + const struct ia_css_dvs2_coefficients *config, unsigned level) +{ + (void)config; + (void)level; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_2/ia_css_sdis2.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_2/ia_css_sdis2.host.h new file mode 100644 index 0000000000000000000000000000000000000000..60198d4279b41e47a0ec62a2b96284c28391f5e7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_2/ia_css_sdis2.host.h @@ -0,0 +1,95 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SDIS2_HOST_H +#define __IA_CSS_SDIS2_HOST_H + +#include "ia_css_sdis2_types.h" +#include "ia_css_binary.h" +#include "ia_css_stream.h" +#include "sh_css_params.h" + +extern const struct ia_css_dvs2_coefficients default_sdis2_config; + +/* Opaque here, since size is binary dependent. */ +struct sh_css_isp_sdis_hori_coef_tbl; +struct sh_css_isp_sdis_vert_coef_tbl; +struct sh_css_isp_sdis_hori_proj_tbl; +struct sh_css_isp_sdis_vert_proj_tbl; + +void ia_css_sdis2_horicoef_vmem_encode ( + struct sh_css_isp_sdis_hori_coef_tbl *to, + const struct ia_css_dvs2_coefficients *from, + unsigned size); + +void ia_css_sdis2_vertcoef_vmem_encode ( + struct sh_css_isp_sdis_vert_coef_tbl *to, + const struct ia_css_dvs2_coefficients *from, + unsigned size); + +void ia_css_sdis2_horiproj_encode ( + struct sh_css_isp_sdis_hori_proj_tbl *to, + const struct ia_css_dvs2_coefficients *from, + unsigned size); + +void ia_css_sdis2_vertproj_encode ( + struct sh_css_isp_sdis_vert_proj_tbl *to, + const struct ia_css_dvs2_coefficients *from, + unsigned size); + +void ia_css_get_isp_dvs2_coefficients( + struct ia_css_stream *stream, + short *hor_coefs_odd_real, + short *hor_coefs_odd_imag, + short *hor_coefs_even_real, + short *hor_coefs_even_imag, + short *ver_coefs_odd_real, + short *ver_coefs_odd_imag, + short *ver_coefs_even_real, + short *ver_coefs_even_imag); + +void ia_css_sdis2_clear_coefficients( + struct ia_css_dvs2_coefficients *dvs2_coefs); + +enum ia_css_err +ia_css_get_dvs2_statistics( + struct ia_css_dvs2_statistics *host_stats, + const struct ia_css_isp_dvs_statistics *isp_stats); + +void +ia_css_translate_dvs2_statistics( + struct ia_css_dvs2_statistics *host_stats, + const struct ia_css_isp_dvs_statistics_map *isp_stats); + +struct ia_css_isp_dvs_statistics * +ia_css_isp_dvs2_statistics_allocate( + const struct ia_css_dvs_grid_info *grid); + +void +ia_css_isp_dvs2_statistics_free( + struct ia_css_isp_dvs_statistics *me); + +void ia_css_sdis2_horicoef_debug_dtrace( + const struct ia_css_dvs2_coefficients *config, unsigned level); + +void ia_css_sdis2_vertcoef_debug_dtrace( + const struct ia_css_dvs2_coefficients *config, unsigned level); + +void ia_css_sdis2_horiproj_debug_dtrace( + const struct ia_css_dvs2_coefficients *config, unsigned level); + +void ia_css_sdis2_vertproj_debug_dtrace( + const struct ia_css_dvs2_coefficients *config, unsigned level); + +#endif /* __IA_CSS_SDIS2_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_2/ia_css_sdis2_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_2/ia_css_sdis2_types.h new file mode 100644 index 0000000000000000000000000000000000000000..7db7dd10fe0081bc3ce4325f55f3a2e72d40e383 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_2/ia_css_sdis2_types.h @@ -0,0 +1,69 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SDIS2_TYPES_H +#define __IA_CSS_SDIS2_TYPES_H + +/** @file +* CSS-API header file for DVS statistics parameters. +*/ + +/** Number of DVS coefficient types */ +#define IA_CSS_DVS2_NUM_COEF_TYPES 4 + +#ifndef PIPE_GENERATION +#include "isp/kernels/sdis/common/ia_css_sdis_common_types.h" +#endif + +/** DVS 2.0 Coefficient types. This structure contains 4 pointers to + * arrays that contain the coeffients for each type. + */ +struct ia_css_dvs2_coef_types { + int16_t *odd_real; /**< real part of the odd coefficients*/ + int16_t *odd_imag; /**< imaginary part of the odd coefficients*/ + int16_t *even_real;/**< real part of the even coefficients*/ + int16_t *even_imag;/**< imaginary part of the even coefficients*/ +}; + +/** DVS 2.0 Coefficients. This structure describes the coefficients that are needed for the dvs statistics. + * e.g. hor_coefs.odd_real is the pointer to int16_t[grid.num_hor_coefs] containing the horizontal odd real + * coefficients. + */ +struct ia_css_dvs2_coefficients { + struct ia_css_dvs_grid_info grid; /**< grid info contains the dimensions of the dvs grid */ + struct ia_css_dvs2_coef_types hor_coefs; /**< struct with pointers that contain the horizontal coefficients */ + struct ia_css_dvs2_coef_types ver_coefs; /**< struct with pointers that contain the vertical coefficients */ +}; + +/** DVS 2.0 Statistic types. This structure contains 4 pointers to + * arrays that contain the statistics for each type. + */ +struct ia_css_dvs2_stat_types { + int32_t *odd_real; /**< real part of the odd statistics*/ + int32_t *odd_imag; /**< imaginary part of the odd statistics*/ + int32_t *even_real;/**< real part of the even statistics*/ + int32_t *even_imag;/**< imaginary part of the even statistics*/ +}; + +/** DVS 2.0 Statistics. This structure describes the statistics that are generated using the provided coefficients. + * e.g. hor_prod.odd_real is the pointer to int16_t[grid.aligned_height][grid.aligned_width] containing + * the horizontal odd real statistics. Valid statistics data area is int16_t[0..grid.height-1][0..grid.width-1] + */ +struct ia_css_dvs2_statistics { + struct ia_css_dvs_grid_info grid; /**< grid info contains the dimensions of the dvs grid */ + struct ia_css_dvs2_stat_types hor_prod; /**< struct with pointers that contain the horizontal statistics */ + struct ia_css_dvs2_stat_types ver_prod; /**< struct with pointers that contain the vertical statistics */ +}; + +#endif /* __IA_CSS_SDIS2_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_2/ia_css_sdis_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_2/ia_css_sdis_param.h new file mode 100644 index 0000000000000000000000000000000000000000..cea352e457139ece06e00e4ff357cc74b8d15ebb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/sdis/sdis_2/ia_css_sdis_param.h @@ -0,0 +1,21 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_SDIS2_PARAM_H +#define __IA_CSS_SDIS2_PARAM_H + +#include "sdis.isp.h" + +#endif /* __IA_CSS_SDIS2_PARAM_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.c new file mode 100644 index 0000000000000000000000000000000000000000..e775af51c0c055da77d5496f6dec7e2b57dbdb48 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.c @@ -0,0 +1,76 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_debug.h" +#include "ia_css_tdf.host.h" + +const int16_t g_pyramid[8][8] = { +{128, 384, 640, 896, 896, 640, 384, 128}, +{384, 1152, 1920, 2688, 2688, 1920, 1152, 384}, +{640, 1920, 3200, 4480, 4480, 3200, 1920, 640}, +{896, 2688, 4480, 6272, 6272, 4480, 2688, 896}, +{896, 2688, 4480, 6272, 6272, 4480, 2688, 896}, +{640, 1920, 3200, 4480, 4480, 3200, 1920, 640}, +{384, 1152, 1920, 2688, 2688, 1920, 1152, 384}, +{128, 384, 640, 896, 896, 640, 384, 128} +}; + +void +ia_css_tdf_vmem_encode( + struct ia_css_isp_tdf_vmem_params *to, + const struct ia_css_tdf_config *from, + size_t size) +{ + unsigned i; + (void)size; + + for (i = 0; i < ISP_VEC_NELEMS; i++) { + to->pyramid[0][i] = g_pyramid[i/8][i%8]; + to->threshold_flat[0][i] = from->thres_flat_table[i]; + to->threshold_detail[0][i] = from->thres_detail_table[i]; + } + +} + +void +ia_css_tdf_encode( + struct ia_css_isp_tdf_dmem_params *to, + const struct ia_css_tdf_config *from, + size_t size) +{ + (void)size; + to->Epsilon_0 = from->epsilon_0; + to->Epsilon_1 = from->epsilon_1; + to->EpsScaleText = from->eps_scale_text; + to->EpsScaleEdge = from->eps_scale_edge; + to->Sepa_flat = from->sepa_flat; + to->Sepa_Edge = from->sepa_edge; + to->Blend_Flat = from->blend_flat; + to->Blend_Text = from->blend_text; + to->Blend_Edge = from->blend_edge; + to->Shading_Gain = from->shading_gain; + to->Shading_baseGain = from->shading_base_gain; + to->LocalY_Gain = from->local_y_gain; + to->LocalY_baseGain = from->local_y_base_gain; +} + +void +ia_css_tdf_debug_dtrace( + const struct ia_css_tdf_config *config, + unsigned level) +{ + (void)config; + (void)level; +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.h new file mode 100644 index 0000000000000000000000000000000000000000..1b3e759e41a35ca304cf3e0c99da4809aba19b26 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.h @@ -0,0 +1,39 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_TDF_HOST_H +#define __IA_CSS_TDF_HOST_H + +#include "ia_css_tdf_types.h" +#include "ia_css_tdf_param.h" +#include "ia_css_tdf_default.host.h" + +void +ia_css_tdf_vmem_encode( + struct ia_css_isp_tdf_vmem_params *to, + const struct ia_css_tdf_config *from, + size_t size); + +void +ia_css_tdf_encode( + struct ia_css_isp_tdf_dmem_params *to, + const struct ia_css_tdf_config *from, + size_t size); + +void +ia_css_tdf_debug_dtrace( + const struct ia_css_tdf_config *config, unsigned level) +; + +#endif /* __IA_CSS_TDF_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf_default.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf_default.host.c new file mode 100644 index 0000000000000000000000000000000000000000..9bb42daf070d8f315530837f92fbfae316d9c63e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf_default.host.c @@ -0,0 +1,36 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_tdf_types.h" + +const struct ia_css_tdf_config default_tdf_config = { + .thres_flat_table = {0}, + .thres_detail_table = {0}, + .epsilon_0 = 4095, + .epsilon_1 = 5733, + .eps_scale_text = 409, + .eps_scale_edge = 3686, + .sepa_flat = 1294, + .sepa_edge = 4095, + .blend_flat = 819, + .blend_text = 819, + .blend_edge = 8191, + .shading_gain = 1024, + .shading_base_gain = 8191, + .local_y_gain = 0, + .local_y_base_gain = 2047, + .rad_x_origin = 0, + .rad_y_origin = 0 +}; + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf_default.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf_default.host.h new file mode 100644 index 0000000000000000000000000000000000000000..cd8fb70e5a8710dde8948ae253f5625cf7f8c80c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf_default.host.h @@ -0,0 +1,23 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_TDF_DEFAULT_HOST_H +#define __IA_CSS_TDF_DEFAULT_HOST_H + +#include "ia_css_tdf_types.h" + +extern const struct ia_css_tdf_config default_tdf_config; + +#endif /* __IA_CSS_TDF_DEFAULT_HOST_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf_param.h new file mode 100644 index 0000000000000000000000000000000000000000..9334f2e0698b40510d5cc445fc83c3e2972e076f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf_param.h @@ -0,0 +1,43 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_TDF_PARAM_H +#define __IA_CSS_TDF_PARAM_H + +#include "type_support.h" +#include "vmem.h" /* needed for VMEM_ARRAY */ + +struct ia_css_isp_tdf_vmem_params { + VMEM_ARRAY(pyramid, ISP_VEC_NELEMS); + VMEM_ARRAY(threshold_flat, ISP_VEC_NELEMS); + VMEM_ARRAY(threshold_detail, ISP_VEC_NELEMS); +}; + +struct ia_css_isp_tdf_dmem_params { + int32_t Epsilon_0; + int32_t Epsilon_1; + int32_t EpsScaleText; + int32_t EpsScaleEdge; + int32_t Sepa_flat; + int32_t Sepa_Edge; + int32_t Blend_Flat; + int32_t Blend_Text; + int32_t Blend_Edge; + int32_t Shading_Gain; + int32_t Shading_baseGain; + int32_t LocalY_Gain; + int32_t LocalY_baseGain; +}; + +#endif /* __IA_CSS_TDF_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf_types.h new file mode 100644 index 0000000000000000000000000000000000000000..cc47a50e5ad55b620ef67b415356fe13c373db06 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf_types.h @@ -0,0 +1,53 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_TDF_TYPES_H +#define __IA_CSS_TDF_TYPES_H + +/** @file +* CSS-API header file for Transform Domain Filter parameters. +*/ + +#include "type_support.h" + +/** Transform Domain Filter configuration + * + * \brief TDF public parameters. + * \details Struct with all parameters for the TDF kernel that can be set + * from the CSS API. + * + * ISP2.6.1: TDF is used. + */ +struct ia_css_tdf_config { + int32_t thres_flat_table[64]; /**< Final optimized strength table of NR for flat region. */ + int32_t thres_detail_table[64]; /**< Final optimized strength table of NR for detail region. */ + int32_t epsilon_0; /**< Coefficient to control variance for dark area (for flat region). */ + int32_t epsilon_1; /**< Coefficient to control variance for bright area (for flat region). */ + int32_t eps_scale_text; /**< Epsilon scaling coefficient for texture region. */ + int32_t eps_scale_edge; /**< Epsilon scaling coefficient for edge region. */ + int32_t sepa_flat; /**< Threshold to judge flat (edge < m_Flat_thre). */ + int32_t sepa_edge; /**< Threshold to judge edge (edge > m_Edge_thre). */ + int32_t blend_flat; /**< Blending ratio at flat region. */ + int32_t blend_text; /**< Blending ratio at texture region. */ + int32_t blend_edge; /**< Blending ratio at edge region. */ + int32_t shading_gain; /**< Gain of Shading control. */ + int32_t shading_base_gain; /**< Base Gain of Shading control. */ + int32_t local_y_gain; /**< Gain of local luminance control. */ + int32_t local_y_base_gain; /**< Base gain of local luminance control. */ + int32_t rad_x_origin; /**< Initial x coord. for radius computation. */ + int32_t rad_y_origin; /**< Initial y coord. for radius computation. */ +}; + +#endif /* __IA_CSS_TDF_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr3/ia_css_tnr3_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr3/ia_css_tnr3_types.h new file mode 100644 index 0000000000000000000000000000000000000000..135563f52174512e0aed99050731aff54496edd5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr3/ia_css_tnr3_types.h @@ -0,0 +1,61 @@ +#ifdef ISP2401 +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef _IA_CSS_TNR3_TYPES_H +#define _IA_CSS_TNR3_TYPES_H + +/** @file +* CSS-API header file for Temporal Noise Reduction v3 (TNR3) kernel +*/ + +/** + * \brief Number of piecewise linear segments. + * \details The parameters to TNR3 are specified as a piecewise linear segment. + * The number of such segments is fixed at 3. + */ +#define TNR3_NUM_SEGMENTS 3 + +/** Temporal Noise Reduction v3 (TNR3) configuration. + * The parameter to this kernel is fourfold + * 1. Three piecewise linear graphs (one for each plane) with three segments + * each. Each line graph has Luma values on the x axis and sigma values for + * each plane on the y axis. The three linear segments may have a different + * slope and the point of Luma value which where the slope may change is called + * a "Knee" point. As there are three such segments, four points need to be + * specified each on the Luma axis and the per plane Sigma axis. On the Luma + * axis two points are fixed (namely 0 and maximum luma value - depending on + * ISP bit depth). The other two points are the points where the slope may + * change its value. These two points are called knee points. The four points on + * the per plane sigma axis are also specified at the interface. + * 2. One rounding adjustment parameter for each plane + * 3. One maximum feedback threshold value for each plane + * 4. Selection of the reference frame buffer to be used for noise reduction. + */ +struct ia_css_tnr3_kernel_config { + unsigned int maxfb_y; /**< Maximum Feedback Gain for Y */ + unsigned int maxfb_u; /**< Maximum Feedback Gain for U */ + unsigned int maxfb_v; /**< Maximum Feedback Gain for V */ + unsigned int round_adj_y; /**< Rounding Adjust for Y */ + unsigned int round_adj_u; /**< Rounding Adjust for U */ + unsigned int round_adj_v; /**< Rounding Adjust for V */ + unsigned int knee_y[TNR3_NUM_SEGMENTS - 1]; /**< Knee points */ + unsigned int sigma_y[TNR3_NUM_SEGMENTS + 1]; /**< Standard deviation for Y at points Y0, Y1, Y2, Y3 */ + unsigned int sigma_u[TNR3_NUM_SEGMENTS + 1]; /**< Standard deviation for U at points U0, U1, U2, U3 */ + unsigned int sigma_v[TNR3_NUM_SEGMENTS + 1]; /**< Standard deviation for V at points V0, V1, V2, V3 */ + unsigned int ref_buf_select; /**< Selection of the reference buffer */ +}; + +#endif +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.c new file mode 100644 index 0000000000000000000000000000000000000000..804c19ab448554bf9ff1914f17c171bde94d2ada --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.c @@ -0,0 +1,130 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "ia_css_frame.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "sh_css_frac.h" +#include "assert_support.h" +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" +#include "isp.h" + +#include "ia_css_tnr.host.h" +const struct ia_css_tnr_config default_tnr_config = { + 32768, + 32, + 32, +}; + +void +ia_css_tnr_encode( + struct sh_css_isp_tnr_params *to, + const struct ia_css_tnr_config *from, + unsigned size) +{ + (void)size; + to->coef = + uDIGIT_FITTING(from->gain, 16, SH_CSS_TNR_COEF_SHIFT); + to->threshold_Y = + uDIGIT_FITTING(from->threshold_y, 16, SH_CSS_ISP_YUV_BITS); + to->threshold_C = + uDIGIT_FITTING(from->threshold_uv, 16, SH_CSS_ISP_YUV_BITS); +} + +void +ia_css_tnr_dump( + const struct sh_css_isp_tnr_params *tnr, + unsigned level) +{ + if (!tnr) return; + ia_css_debug_dtrace(level, "Temporal Noise Reduction:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "tnr_coef", tnr->coef); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "tnr_threshold_Y", tnr->threshold_Y); + ia_css_debug_dtrace(level, "\t%-32s = %d\n" + "tnr_threshold_C", tnr->threshold_C); +} + +void +ia_css_tnr_debug_dtrace( + const struct ia_css_tnr_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.gain=%d, " + "config.threshold_y=%d, config.threshold_uv=%d\n", + config->gain, + config->threshold_y, config->threshold_uv); +} + +void +ia_css_tnr_config( + struct sh_css_isp_tnr_isp_config *to, + const struct ia_css_tnr_configuration *from, + unsigned size) +{ + unsigned elems_a = ISP_VEC_NELEMS; + unsigned i; + + (void)size; + ia_css_dma_configure_from_info(&to->port_b, &from->tnr_frames[0]->info); + to->width_a_over_b = elems_a / to->port_b.elems; + to->frame_height = from->tnr_frames[0]->info.res.height; +#ifndef ISP2401 + for (i = 0; i < NUM_VIDEO_TNR_FRAMES; i++) { +#else + for (i = 0; i < NUM_TNR_FRAMES; i++) { +#endif + to->tnr_frame_addr[i] = from->tnr_frames[i]->data + from->tnr_frames[i]->planes.yuyv.offset; + } + + /* Assume divisiblity here, may need to generalize to fixed point. */ + assert (elems_a % to->port_b.elems == 0); +} + +void +ia_css_tnr_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame **frames) +{ + struct ia_css_tnr_configuration config; + unsigned i; + +#ifndef ISP2401 + for (i = 0; i < NUM_VIDEO_TNR_FRAMES; i++) +#else + for (i = 0; i < NUM_TNR_FRAMES; i++) +#endif + config.tnr_frames[i] = frames[i]; + + ia_css_configure_tnr(binary, &config); +} + +void +ia_css_init_tnr_state( + struct sh_css_isp_tnr_dmem_state *state, + size_t size) +{ + (void)size; + +#ifndef ISP2401 + assert(NUM_VIDEO_TNR_FRAMES >= 2); +#endif + assert(sizeof(*state) == size); + state->tnr_in_buf_idx = 0; + state->tnr_out_buf_idx = 1; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h new file mode 100644 index 0000000000000000000000000000000000000000..9290dfad574eb3ed79e823dd4a76e2d59b685d63 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.h @@ -0,0 +1,56 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_TNR_HOST_H +#define __IA_CSS_TNR_HOST_H + +#include "ia_css_binary.h" +#include "ia_css_tnr_state.h" +#include "ia_css_tnr_types.h" +#include "ia_css_tnr_param.h" + +extern const struct ia_css_tnr_config default_tnr_config; + +void +ia_css_tnr_encode( + struct sh_css_isp_tnr_params *to, + const struct ia_css_tnr_config *from, + unsigned size); + +void +ia_css_tnr_dump( + const struct sh_css_isp_tnr_params *tnr, + unsigned level); + +void +ia_css_tnr_debug_dtrace( + const struct ia_css_tnr_config *config, + unsigned level); + +void +ia_css_tnr_config( + struct sh_css_isp_tnr_isp_config *to, + const struct ia_css_tnr_configuration *from, + unsigned size); + +void +ia_css_tnr_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame **frames); + +void +ia_css_init_tnr_state( + struct sh_css_isp_tnr_dmem_state *state, + size_t size); +#endif /* __IA_CSS_TNR_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr_param.h new file mode 100644 index 0000000000000000000000000000000000000000..db4a7cced2649afde21cc6875fe5ba261fc49eb8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr_param.h @@ -0,0 +1,48 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_TNR_PARAM_H +#define __IA_CSS_TNR_PARAM_H + +#include "type_support.h" +#include "sh_css_defs.h" +#include "dma.h" + +/* TNR (Temporal Noise Reduction) */ +struct sh_css_isp_tnr_params { + int32_t coef; + int32_t threshold_Y; + int32_t threshold_C; +}; + +struct ia_css_tnr_configuration { +#ifndef ISP2401 + const struct ia_css_frame *tnr_frames[NUM_VIDEO_TNR_FRAMES]; +#else + const struct ia_css_frame *tnr_frames[NUM_TNR_FRAMES]; +#endif +}; + +struct sh_css_isp_tnr_isp_config { + uint32_t width_a_over_b; + uint32_t frame_height; + struct dma_port_config port_b; +#ifndef ISP2401 + hrt_vaddress tnr_frame_addr[NUM_VIDEO_TNR_FRAMES]; +#else + hrt_vaddress tnr_frame_addr[NUM_TNR_FRAMES]; +#endif +}; + +#endif /* __IA_CSS_TNR_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr_state.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr_state.h new file mode 100644 index 0000000000000000000000000000000000000000..8b1218f7235dc55618b9bbbdc55e956a89e986ef --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr_state.h @@ -0,0 +1,26 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_TNR_STATE_H +#define __IA_CSS_TNR_STATE_H + +#include "type_support.h" + +/* TNR (temporal noise reduction) */ +struct sh_css_isp_tnr_dmem_state { + uint32_t tnr_in_buf_idx; + uint32_t tnr_out_buf_idx; +}; + +#endif /* __IA_CSS_TNR_STATE_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr_types.h new file mode 100644 index 0000000000000000000000000000000000000000..4fd35e6ccd704ceb4a6aac9467d30b83cd70c9b2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr_types.h @@ -0,0 +1,60 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_TNR_TYPES_H +#define __IA_CSS_TNR_TYPES_H + +/** @file +* CSS-API header file for Temporal Noise Reduction (TNR) parameters. +*/ + +/** Temporal Noise Reduction (TNR) configuration. + * + * When difference between current frame and previous frame is less than or + * equal to threshold, TNR works and current frame is mixed + * with previous frame. + * When difference between current frame and previous frame is greater + * than threshold, we judge motion is detected. Then, TNR does not work and + * current frame is outputted as it is. + * Therefore, when threshold_y and threshold_uv are set as 0, TNR can be disabled. + * + * ISP block: TNR1 + * ISP1: TNR1 is used. + * ISP2: TNR1 is used. + */ + + +struct ia_css_tnr_config { + ia_css_u0_16 gain; /**< Interpolation ratio of current frame + and previous frame. + gain=0.0 -> previous frame is outputted. + gain=1.0 -> current frame is outputted. + u0.16, [0,65535], + default 32768(0.5), ineffective 65535(almost 1.0) */ + ia_css_u0_16 threshold_y; /**< Threshold to enable interpolation of Y. + If difference between current frame and + previous frame is greater than threshold_y, + TNR for Y is disabled. + u0.16, [0,65535], default/ineffective 0 */ + ia_css_u0_16 threshold_uv; /**< Threshold to enable interpolation of + U/V. + If difference between current frame and + previous frame is greater than threshold_uv, + TNR for UV is disabled. + u0.16, [0,65535], default/ineffective 0 */ +}; + + +#endif /* __IA_CSS_TNR_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/uds/uds_1.0/ia_css_uds.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/uds/uds_1.0/ia_css_uds.host.c new file mode 100644 index 0000000000000000000000000000000000000000..20fd68bc23b3b06911b002240be15ddad7cd9f1b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/uds/uds_1.0/ia_css_uds.host.c @@ -0,0 +1,35 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" + +#include "ia_css_uds.host.h" + +void +ia_css_uds_encode( + struct sh_css_sp_uds_params *to, + const struct ia_css_uds_config *from, + unsigned size) +{ + (void)size; + to->crop_pos = from->crop_pos; + to->uds = from->uds; +} + +void +ia_css_uds_dump( + const struct sh_css_sp_uds_params *uds, + unsigned level); diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/uds/uds_1.0/ia_css_uds.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/uds/uds_1.0/ia_css_uds.host.h new file mode 100644 index 0000000000000000000000000000000000000000..984c5bdb064126226b4d2c1464eb9f356925cc25 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/uds/uds_1.0/ia_css_uds.host.h @@ -0,0 +1,33 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_UDS_HOST_H +#define __IA_CSS_UDS_HOST_H + +#include "sh_css_params.h" + +#include "ia_css_uds_param.h" + +void +ia_css_uds_encode( + struct sh_css_sp_uds_params *to, + const struct ia_css_uds_config *from, + unsigned size); + +void +ia_css_uds_dump( + const struct sh_css_sp_uds_params *uds, + unsigned level); + +#endif /* __IA_CSS_UDS_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/uds/uds_1.0/ia_css_uds_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/uds/uds_1.0/ia_css_uds_param.h new file mode 100644 index 0000000000000000000000000000000000000000..26b7b5bc93911eb9473b4a842f54450e40a79231 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/uds/uds_1.0/ia_css_uds_param.h @@ -0,0 +1,31 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_UDS_PARAM_H +#define __IA_CSS_UDS_PARAM_H + +#include "sh_css_uds.h" + +/* uds (Up and Down scaling) */ +struct ia_css_uds_config { + struct sh_css_crop_pos crop_pos; + struct sh_css_uds_info uds; +}; + +struct sh_css_sp_uds_params { + struct sh_css_crop_pos crop_pos; + struct sh_css_uds_info uds; +}; + +#endif /* __IA_CSS_UDS_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/vf/vf_1.0/ia_css_vf.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/vf/vf_1.0/ia_css_vf.host.c new file mode 100644 index 0000000000000000000000000000000000000000..ab756253e6b64b3b6c2f29ee36443469f623215c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/vf/vf_1.0/ia_css_vf.host.c @@ -0,0 +1,141 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_vf.host.h" +#include +#include +#include +#include +#include +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" +#include + +#include "isp.h" + +void +ia_css_vf_config( + struct sh_css_isp_vf_isp_config *to, + const struct ia_css_vf_configuration *from, + unsigned size) +{ + unsigned elems_a = ISP_VEC_NELEMS; + + (void)size; + to->vf_downscale_bits = from->vf_downscale_bits; + to->enable = from->info != NULL; + + if (from->info) { + ia_css_frame_info_to_frame_sp_info(&to->info, from->info); + ia_css_dma_configure_from_info(&to->dma.port_b, from->info); + to->dma.width_a_over_b = elems_a / to->dma.port_b.elems; + + /* Assume divisiblity here, may need to generalize to fixed point. */ + assert (elems_a % to->dma.port_b.elems == 0); + } +} + +/* compute the log2 of the downscale factor needed to get closest + * to the requested viewfinder resolution on the upper side. The output cannot + * be smaller than the requested viewfinder resolution. + */ +enum ia_css_err +sh_css_vf_downscale_log2( + const struct ia_css_frame_info *out_info, + const struct ia_css_frame_info *vf_info, + unsigned int *downscale_log2) +{ + unsigned int ds_log2 = 0; + unsigned int out_width; + + if ((out_info == NULL) | (vf_info == NULL)) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + out_width = out_info->res.width; + + if (out_width == 0) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + /* downscale until width smaller than the viewfinder width. We don't + * test for the height since the vmem buffers only put restrictions on + * the width of a line, not on the number of lines in a frame. + */ + while (out_width >= vf_info->res.width) { + ds_log2++; + out_width /= 2; + } + /* now width is smaller, so we go up one step */ + if ((ds_log2 > 0) && (out_width < ia_css_binary_max_vf_width())) + ds_log2--; + /* TODO: use actual max input resolution of vf_pp binary */ + if ((out_info->res.width >> ds_log2) >= 2 * ia_css_binary_max_vf_width()) + return IA_CSS_ERR_INVALID_ARGUMENTS; + *downscale_log2 = ds_log2; + return IA_CSS_SUCCESS; +} + +static enum ia_css_err +configure_kernel( + const struct ia_css_binary_info *info, + const struct ia_css_frame_info *out_info, + const struct ia_css_frame_info *vf_info, + unsigned int *downscale_log2, + struct ia_css_vf_configuration *config) +{ + enum ia_css_err err; + unsigned vf_log_ds = 0; + + /* First compute value */ + if (vf_info) { + err = sh_css_vf_downscale_log2(out_info, vf_info, &vf_log_ds); + if (err != IA_CSS_SUCCESS) + return err; + } + vf_log_ds = min(vf_log_ds, info->vf_dec.max_log_downscale); + *downscale_log2 = vf_log_ds; + + /* Then store it in isp config section */ + config->vf_downscale_bits = vf_log_ds; + return IA_CSS_SUCCESS; +} + +static void +configure_dma( + struct ia_css_vf_configuration *config, + const struct ia_css_frame_info *vf_info) +{ + config->info = vf_info; +} + +enum ia_css_err +ia_css_vf_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info, + unsigned int *downscale_log2) +{ + enum ia_css_err err; + struct ia_css_vf_configuration config; + const struct ia_css_binary_info *info = &binary->info->sp; + + err = configure_kernel(info, out_info, vf_info, downscale_log2, &config); + configure_dma(&config, vf_info); + if (binary) { + if (vf_info) + vf_info->raw_bit_depth = info->dma.vfdec_bits_per_pixel; + ia_css_configure_vf (binary, &config); + } + return IA_CSS_SUCCESS; +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/vf/vf_1.0/ia_css_vf.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/vf/vf_1.0/ia_css_vf.host.h new file mode 100644 index 0000000000000000000000000000000000000000..c7c3625a9a96777898494b4de4c49480448666bf --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/vf/vf_1.0/ia_css_vf.host.h @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_VF_HOST_H +#define __IA_CSS_VF_HOST_H + +#include "ia_css_frame_public.h" +#include "ia_css_binary.h" + +#include "ia_css_vf_types.h" +#include "ia_css_vf_param.h" + +/* compute the log2 of the downscale factor needed to get closest + * to the requested viewfinder resolution on the upper side. The output cannot + * be smaller than the requested viewfinder resolution. + */ +enum ia_css_err +sh_css_vf_downscale_log2( + const struct ia_css_frame_info *out_info, + const struct ia_css_frame_info *vf_info, + unsigned int *downscale_log2); + +void +ia_css_vf_config( + struct sh_css_isp_vf_isp_config *to, + const struct ia_css_vf_configuration *from, + unsigned size); + +enum ia_css_err +ia_css_vf_configure( + const struct ia_css_binary *binary, + const struct ia_css_frame_info *out_info, + struct ia_css_frame_info *vf_info, + unsigned int *downscale_log2); + +#endif /* __IA_CSS_VF_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/vf/vf_1.0/ia_css_vf_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/vf/vf_1.0/ia_css_vf_param.h new file mode 100644 index 0000000000000000000000000000000000000000..df5d37c8c946401c01347711add4ef153034d41b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/vf/vf_1.0/ia_css_vf_param.h @@ -0,0 +1,37 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_VF_PARAM_H +#define __IA_CSS_VF_PARAM_H + +#include "type_support.h" +#include "dma.h" +#include "gc/gc_1.0/ia_css_gc_param.h" /* GAMMA_OUTPUT_BITS */ +#include "ia_css_frame_comm.h" /* ia_css_frame_sp_info */ +#include "ia_css_vf_types.h" + +#define VFDEC_BITS_PER_PIXEL GAMMA_OUTPUT_BITS + +/** Viewfinder decimation */ +struct sh_css_isp_vf_isp_config { + uint32_t vf_downscale_bits; /**< Log VF downscale value */ + uint32_t enable; + struct ia_css_frame_sp_info info; + struct { + uint32_t width_a_over_b; + struct dma_port_config port_b; + } dma; +}; + +#endif /* __IA_CSS_VF_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/vf/vf_1.0/ia_css_vf_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/vf/vf_1.0/ia_css_vf_types.h new file mode 100644 index 0000000000000000000000000000000000000000..d8cfdfbc8c0bd1af7f938f88985516d8367ab29a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/vf/vf_1.0/ia_css_vf_types.h @@ -0,0 +1,32 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_VF_TYPES_H +#define __IA_CSS_VF_TYPES_H + +/** Viewfinder decimation + * + * ISP block: vfeven_horizontal_downscale + */ + +#include +#include + +struct ia_css_vf_configuration { + uint32_t vf_downscale_bits; /**< Log VF downscale value */ + const struct ia_css_frame_info *info; +}; + +#endif /* __IA_CSS_VF_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/wb/wb_1.0/ia_css_wb.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/wb/wb_1.0/ia_css_wb.host.c new file mode 100644 index 0000000000000000000000000000000000000000..b43cb88c6ae452e620aa5c97a28ad32175edccda --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/wb/wb_1.0/ia_css_wb.host.c @@ -0,0 +1,89 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#ifndef IA_CSS_NO_DEBUG +#include "ia_css_debug.h" +#endif +#include "sh_css_frac.h" + +#include "ia_css_wb.host.h" + +const struct ia_css_wb_config default_wb_config = { + 1, + 32768, + 32768, + 32768, + 32768 +}; + +void +ia_css_wb_encode( + struct sh_css_isp_wb_params *to, + const struct ia_css_wb_config *from, + unsigned size) +{ + (void)size; + to->gain_shift = + uISP_REG_BIT - from->integer_bits; + to->gain_gr = + uDIGIT_FITTING(from->gr, 16 - from->integer_bits, + to->gain_shift); + to->gain_r = + uDIGIT_FITTING(from->r, 16 - from->integer_bits, + to->gain_shift); + to->gain_b = + uDIGIT_FITTING(from->b, 16 - from->integer_bits, + to->gain_shift); + to->gain_gb = + uDIGIT_FITTING(from->gb, 16 - from->integer_bits, + to->gain_shift); +} + +#ifndef IA_CSS_NO_DEBUG +void +ia_css_wb_dump( + const struct sh_css_isp_wb_params *wb, + unsigned level) +{ + if (!wb) return; + ia_css_debug_dtrace(level, "White Balance:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "wb_gain_shift", wb->gain_shift); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "wb_gain_gr", wb->gain_gr); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "wb_gain_r", wb->gain_r); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "wb_gain_b", wb->gain_b); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "wb_gain_gb", wb->gain_gb); +} + +void +ia_css_wb_debug_dtrace( + const struct ia_css_wb_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.integer_bits=%d, " + "config.gr=%d, config.r=%d, " + "config.b=%d, config.gb=%d\n", + config->integer_bits, + config->gr, config->r, + config->b, config->gb); +} +#endif + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/wb/wb_1.0/ia_css_wb.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/wb/wb_1.0/ia_css_wb.host.h new file mode 100644 index 0000000000000000000000000000000000000000..18666baf9f76b2703761150ef5fe0b54eaff21f4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/wb/wb_1.0/ia_css_wb.host.h @@ -0,0 +1,39 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_WB_HOST_H +#define __IA_CSS_WB_HOST_H + +#include "ia_css_wb_types.h" +#include "ia_css_wb_param.h" + +extern const struct ia_css_wb_config default_wb_config; + +void +ia_css_wb_encode( + struct sh_css_isp_wb_params *to, + const struct ia_css_wb_config *from, + unsigned size); + +void +ia_css_wb_dump( + const struct sh_css_isp_wb_params *wb, + unsigned level); + +void +ia_css_wb_debug_dtrace( + const struct ia_css_wb_config *wb, + unsigned level); + +#endif /* __IA_CSS_WB_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/wb/wb_1.0/ia_css_wb_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/wb/wb_1.0/ia_css_wb_param.h new file mode 100644 index 0000000000000000000000000000000000000000..c95c53a2406702122ca2bc38ef30a26502a1ef36 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/wb/wb_1.0/ia_css_wb_param.h @@ -0,0 +1,29 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_WB_PARAM_H +#define __IA_CSS_WB_PARAM_H + +#include "type_support.h" + +/* WB (White Balance) */ +struct sh_css_isp_wb_params { + int32_t gain_shift; + int32_t gain_gr; + int32_t gain_r; + int32_t gain_b; + int32_t gain_gb; +}; + +#endif /* __IA_CSS_WB_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/wb/wb_1.0/ia_css_wb_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/wb/wb_1.0/ia_css_wb_types.h new file mode 100644 index 0000000000000000000000000000000000000000..6bcfa274be884c3aa95cf4efb6e59a18580ff12d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/wb/wb_1.0/ia_css_wb_types.h @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_WB_TYPES_H +#define __IA_CSS_WB_TYPES_H + +/** @file +* CSS-API header file for White Balance parameters. +*/ + + +/** White Balance configuration (Gain Adjust). + * + * ISP block: WB1 + * ISP1: WB1 is used. + * ISP2: WB1 is used. + */ +struct ia_css_wb_config { + uint32_t integer_bits; /**< Common exponent of gains. + u8.0, [0,3], + default 1, ineffective 1 */ + uint32_t gr; /**< Significand of Gr gain. + u[integer_bits].[16-integer_bits], [0,65535], + default/ineffective 32768(u1.15, 1.0) */ + uint32_t r; /**< Significand of R gain. + u[integer_bits].[16-integer_bits], [0,65535], + default/ineffective 32768(u1.15, 1.0) */ + uint32_t b; /**< Significand of B gain. + u[integer_bits].[16-integer_bits], [0,65535], + default/ineffective 32768(u1.15, 1.0) */ + uint32_t gb; /**< Significand of Gb gain. + u[integer_bits].[16-integer_bits], [0,65535], + default/ineffective 32768(u1.15, 1.0) */ +}; + +#endif /* __IA_CSS_WB_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_11/ia_css_xnr3_0_11.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_11/ia_css_xnr3_0_11.host.c new file mode 100644 index 0000000000000000000000000000000000000000..7e86bc8be0542b33645226ac17ca722a0aad16f3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_11/ia_css_xnr3_0_11.host.c @@ -0,0 +1,155 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "type_support.h" +#include "math_support.h" +#include "sh_css_defs.h" +#include "assert_support.h" +#include "ia_css_xnr3_0_11.host.h" + +/* + * XNR 3.0.11 division look-up table + */ +#define XNR3_0_11_LOOK_UP_TABLE_POINTS 16 + +static const int16_t x[XNR3_0_11_LOOK_UP_TABLE_POINTS] = { +512, 637, 782, 952, 1147, 1372, 1627, 1917, 2242, +2597, 2992, 3427, 3907, 4432, 5007, 5632}; + +static const int16_t a[XNR3_0_11_LOOK_UP_TABLE_POINTS] = { +-6587, -4309, -2886, -1970, -1362, -7710, -5508, +-4008, -2931, -2219, -1676, -1280, -999, -769, -616, 0}; + +static const int16_t b[XNR3_0_11_LOOK_UP_TABLE_POINTS] = { +4096, 3292, 2682, 2203, 1828, 1529, 1289, 1094, +935, 808, 701, 612, 537, 473, 419, 372}; + +static const int16_t c[XNR3_0_11_LOOK_UP_TABLE_POINTS] = { +1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + + +/* + * Default kernel parameters (weights). In general, default is bypass mode or as close + * to the ineffective values as possible. Due to the chroma down+upsampling, + * perfect bypass mode is not possible for xnr3. + */ +const struct ia_css_xnr3_0_11_config default_xnr3_0_11_config = { + 7, 7, 7, 7, 7, 2 }; + + +/* (void) = ia_css_xnr3_0_11_vmem_encode(*to, *from) + * ----------------------------------------------- + * VMEM Encode Function to translate UV parameters from userspace into ISP space +*/ +void +ia_css_xnr3_0_11_vmem_encode( + struct sh_css_isp_xnr3_0_11_vmem_params *to, + const struct ia_css_xnr3_0_11_config *from, + unsigned size) +{ + unsigned i, j, base; + const unsigned total_blocks = 4; + const unsigned shuffle_block = 16; + + (void)from; + (void)size; + + /* Init */ + for (i = 0; i < ISP_VEC_NELEMS; i++) { + to->x[0][i] = 0; + to->a[0][i] = 0; + to->b[0][i] = 0; + to->c[0][i] = 0; + } + + + /* Constraints on "x": + * - values should be greater or equal to 0. + * - values should be ascending. + */ + assert(x[0] >= 0); + + for (j = 1; j < XNR3_0_11_LOOK_UP_TABLE_POINTS; j++) { + assert(x[j] >= 0); + assert(x[j] > x[j-1]); + + } + + + /* The implementation of the calulating 1/x is based on the availability + * of the OP_vec_shuffle16 operation. + * A 64 element vector is split up in 4 blocks of 16 element. Each array is copied to + * a vector 4 times, (starting at 0, 16, 32 and 48). All array elements are copied or + * initialised as described in the KFS. The remaining elements of a vector are set to 0. + */ + /* TODO: guard this code with above assumptions */ + for(i = 0; i < total_blocks; i++) { + base = shuffle_block * i; + + for (j = 0; j < XNR3_0_11_LOOK_UP_TABLE_POINTS; j++) { + to->x[0][base + j] = x[j]; + to->a[0][base + j] = a[j]; + to->b[0][base + j] = b[j]; + to->c[0][base + j] = c[j]; + } + } + +} + + + +/* (void) = ia_css_xnr3_0_11_encode(*to, *from) + * ----------------------------------------------- + * DMEM Encode Function to translate UV parameters from userspace into ISP space + */ +void +ia_css_xnr3_0_11_encode( + struct sh_css_isp_xnr3_0_11_params *to, + const struct ia_css_xnr3_0_11_config *from, + unsigned size) +{ + int kernel_size = XNR_FILTER_SIZE; + /* The adjust factor is the next power of 2 + w.r.t. the kernel size*/ + int adjust_factor = ceil_pow2(kernel_size); + + int32_t weight_y0 = from->weight_y0; + int32_t weight_y1 = from->weight_y1; + int32_t weight_u0 = from->weight_u0; + int32_t weight_u1 = from->weight_u1; + int32_t weight_v0 = from->weight_v0; + int32_t weight_v1 = from->weight_v1; + + (void)size; + + to->weight_y0 = weight_y0; + to->weight_u0 = weight_u0; + to->weight_v0 = weight_v0; + to->weight_ydiff = (weight_y1 - weight_y0) * adjust_factor / kernel_size; + to->weight_udiff = (weight_u1 - weight_u0) * adjust_factor / kernel_size; + to->weight_vdiff = (weight_v1 - weight_v0) * adjust_factor / kernel_size; +} + +/* (void) = ia_css_xnr3_0_11_debug_dtrace(*config, level) + * ----------------------------------------------- + * Dummy Function added as the tool expects it + */ +void +ia_css_xnr3_0_11_debug_dtrace( + const struct ia_css_xnr3_0_11_config *config, + unsigned level) +{ + (void)config; + (void)level; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_11/ia_css_xnr3_0_11.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_11/ia_css_xnr3_0_11.host.h new file mode 100644 index 0000000000000000000000000000000000000000..8e8b85f7ea872578c0eb9fcce0a0d5f5fccf966b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_11/ia_css_xnr3_0_11.host.h @@ -0,0 +1,58 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR3_0_11_HOST_H +#define __IA_CSS_XNR3_0_11_HOST_H + +#include "ia_css_xnr3_0_11_param.h" +#include "ia_css_xnr3_0_11_types.h" + +/* + * Default kernel parameters (weights). In general, default is bypass mode or as close + * to the ineffective values as possible. Due to the chroma down+upsampling, + * perfect bypass mode is not possible for xnr3. + */ +extern const struct ia_css_xnr3_0_11_config default_xnr3_0_11_config; + + +/* (void) = ia_css_xnr3_0_11_vmem_encode(*to, *from) + * ----------------------------------------------- + * VMEM Encode Function to translate UV parameters from userspace into ISP space +*/ +void +ia_css_xnr3_0_11_vmem_encode( + struct sh_css_isp_xnr3_0_11_vmem_params *to, + const struct ia_css_xnr3_0_11_config *from, + unsigned size); + +/* (void) = ia_css_xnr3_0_11_encode(*to, *from) + * ----------------------------------------------- + * DMEM Encode Function to translate UV parameters from userspace into ISP space + */ +void +ia_css_xnr3_0_11_encode( + struct sh_css_isp_xnr3_0_11_params *to, + const struct ia_css_xnr3_0_11_config *from, + unsigned size); + +/* (void) = ia_css_xnr3_0_11_debug_dtrace(*config, level) + * ----------------------------------------------- + * Dummy Function added as the tool expects it + */ +void +ia_css_xnr3_0_11_debug_dtrace( + const struct ia_css_xnr3_0_11_config *config, + unsigned level); + +#endif /* __IA_CSS_XNR3_0_11_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_11/ia_css_xnr3_0_11_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_11/ia_css_xnr3_0_11_param.h new file mode 100644 index 0000000000000000000000000000000000000000..a28cfd4cd6100c7025fd50c481fd6b2e2bdc88a3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_11/ia_css_xnr3_0_11_param.h @@ -0,0 +1,50 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR3_0_11_PARAM_H +#define __IA_CSS_XNR3_0_11_PARAM_H + +#include "type_support.h" +#include "vmem.h" /* needed for VMEM_ARRAY */ + +/* XNR3.0.11 filter size */ +#define XNR_FILTER_SIZE 11 + +/* + * STRUCT sh_css_isp_xnr3_0_11_vmem_params + * ----------------------------------------------- + * XNR3.0.11 ISP VMEM parameters + */ +struct sh_css_isp_xnr3_0_11_vmem_params { + VMEM_ARRAY(x, ISP_VEC_NELEMS); + VMEM_ARRAY(a, ISP_VEC_NELEMS); + VMEM_ARRAY(b, ISP_VEC_NELEMS); + VMEM_ARRAY(c, ISP_VEC_NELEMS); +}; + + /* + * STRUCT sh_css_isp_xnr3_0_11_params + * ----------------------------------------------- + * XNR3.0.11 ISP parameters + */ +struct sh_css_isp_xnr3_0_11_params { + int32_t weight_y0; + int32_t weight_u0; + int32_t weight_v0; + int32_t weight_ydiff; + int32_t weight_udiff; + int32_t weight_vdiff; +}; + +#endif /*__IA_CSS_XNR3_0_11_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_11/ia_css_xnr3_0_11_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_11/ia_css_xnr3_0_11_types.h new file mode 100644 index 0000000000000000000000000000000000000000..b6bf449ecdff8cfc4cf27189bdf2901683da6c78 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_11/ia_css_xnr3_0_11_types.h @@ -0,0 +1,33 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR3_0_11_TYPES_H +#define __IA_CSS_XNR3_0_11_TYPES_H + + /* + * STRUCT ia_css_xnr3_0_11_config + * ----------------------------------------------- + * Struct with all parameters for the XNR3.0.11 kernel that can be set + * from the CSS API + */ +struct ia_css_xnr3_0_11_config { + int32_t weight_y0; /**< Weight for Y range similarity in dark area */ + int32_t weight_y1; /**< Weight for Y range similarity in bright area */ + int32_t weight_u0; /**< Weight for U range similarity in dark area */ + int32_t weight_u1; /**< Weight for U range similarity in bright area */ + int32_t weight_v0; /**< Weight for V range similarity in dark area */ + int32_t weight_v1; /**< Weight for V range similarity in bright area */ +}; + +#endif /* __IA_CSS_XNR3_0_11_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_5/ia_css_xnr3_0_5.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_5/ia_css_xnr3_0_5.host.c new file mode 100644 index 0000000000000000000000000000000000000000..d29b314f395e9d1bc3fda9dfb958a773e4545fcb --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_5/ia_css_xnr3_0_5.host.c @@ -0,0 +1,154 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "type_support.h" +#include "math_support.h" +#include "sh_css_defs.h" +#include "assert_support.h" +#include "ia_css_xnr3_0_5.host.h" + +/* + * XNR 3.0.5 division look-up table + */ +#define XNR3_0_5_LOOK_UP_TABLE_POINTS 16 + +static const int16_t x[XNR3_0_5_LOOK_UP_TABLE_POINTS] = { +1024, 1164, 1320, 1492, 1680, 1884, 2108, 2352, +2616, 2900, 3208, 3540, 3896, 4276, 4684, 5120}; + +static const int16_t a[XNR3_0_5_LOOK_UP_TABLE_POINTS] = { +-7213, -5580, -4371, -3421, -2722, -2159, -6950, -5585, +-4529, -3697, -3010, -2485, -2070, -1727, -1428, 0}; + +static const int16_t b[XNR3_0_5_LOOK_UP_TABLE_POINTS] = { +4096, 3603, 3178, 2811, 2497, 2226, 1990, 1783, +1603, 1446, 1307, 1185, 1077, 981, 895, 819}; + +static const int16_t c[XNR3_0_5_LOOK_UP_TABLE_POINTS] = { +1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}; + +/* + * Default kernel parameters(weights). In general, default is bypass mode or as close + * to the ineffective values as possible. Due to the chroma down+upsampling, + * perfect bypass mode is not possible for xnr3. + */ +const struct ia_css_xnr3_0_5_config default_xnr3_0_5_config = { + 8191, 8191, 8191, 8191, 8191, 8191 }; + + +/* (void) = ia_css_xnr3_0_5_vmem_encode(*to, *from) + * ----------------------------------------------- + * VMEM Encode Function to translate UV parameters from userspace into ISP space +*/ +void +ia_css_xnr3_0_5_vmem_encode( + struct sh_css_isp_xnr3_0_5_vmem_params *to, + const struct ia_css_xnr3_0_5_config *from, + unsigned size) +{ + unsigned i, j, base; + const unsigned total_blocks = 4; + const unsigned shuffle_block = 16; + + (void)from; + (void)size; + + /* Init */ + for (i = 0; i < ISP_VEC_NELEMS; i++) { + to->x[0][i] = 0; + to->a[0][i] = 0; + to->b[0][i] = 0; + to->c[0][i] = 0; + } + + + /* Constraints on "x": + * - values should be greater or equal to 0. + * - values should be ascending. + */ + assert(x[0] >= 0); + + for (j = 1; j < XNR3_0_5_LOOK_UP_TABLE_POINTS; j++) { + assert(x[j] >= 0); + assert(x[j] > x[j-1]); + + } + + + /* The implementation of the calulating 1/x is based on the availability + * of the OP_vec_shuffle16 operation. + * A 64 element vector is split up in 4 blocks of 16 element. Each array is copied to + * a vector 4 times, (starting at 0, 16, 32 and 48). All array elements are copied or + * initialised as described in the KFS. The remaining elements of a vector are set to 0. + */ + /* TODO: guard this code with above assumptions */ + for(i = 0; i < total_blocks; i++) { + base = shuffle_block * i; + + for (j = 0; j < XNR3_0_5_LOOK_UP_TABLE_POINTS; j++) { + to->x[0][base + j] = x[j]; + to->a[0][base + j] = a[j]; + to->b[0][base + j] = b[j]; + to->c[0][base + j] = c[j]; + } + } + +} + + + +/* (void) = ia_css_xnr3_0_5_encode(*to, *from) + * ----------------------------------------------- + * DMEM Encode Function to translate UV parameters from userspace into ISP space + */ +void +ia_css_xnr3_0_5_encode( + struct sh_css_isp_xnr3_0_5_params *to, + const struct ia_css_xnr3_0_5_config *from, + unsigned size) +{ + int kernel_size = XNR_FILTER_SIZE; + /* The adjust factor is the next power of 2 + w.r.t. the kernel size*/ + int adjust_factor = ceil_pow2(kernel_size); + + int32_t weight_y0 = from->weight_y0; + int32_t weight_y1 = from->weight_y1; + int32_t weight_u0 = from->weight_u0; + int32_t weight_u1 = from->weight_u1; + int32_t weight_v0 = from->weight_v0; + int32_t weight_v1 = from->weight_v1; + + (void)size; + + to->weight_y0 = weight_y0; + to->weight_u0 = weight_u0; + to->weight_v0 = weight_v0; + to->weight_ydiff = (weight_y1 - weight_y0) * adjust_factor / kernel_size; + to->weight_udiff = (weight_u1 - weight_u0) * adjust_factor / kernel_size; + to->weight_vdiff = (weight_v1 - weight_v0) * adjust_factor / kernel_size; +} + +/* (void) = ia_css_xnr3_0_5_debug_dtrace(*config, level) + * ----------------------------------------------- + * Dummy Function added as the tool expects it + */ +void +ia_css_xnr3_0_5_debug_dtrace( + const struct ia_css_xnr3_0_5_config *config, + unsigned level) +{ + (void)config; + (void)level; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_5/ia_css_xnr3_0_5.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_5/ia_css_xnr3_0_5.host.h new file mode 100644 index 0000000000000000000000000000000000000000..69817a60022eb0d5b9f63c37bd1e42776a6a191f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_5/ia_css_xnr3_0_5.host.h @@ -0,0 +1,59 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR3_0_5_HOST_H +#define __IA_CSS_XNR3_0_5_HOST_H + +#include "ia_css_xnr3_0_5_param.h" +#include "ia_css_xnr3_0_5_types.h" + +/* + * Default kernel parameters (weights). In general, default is bypass mode or as close + * to the ineffective values as possible. Due to the chroma down+upsampling, + * perfect bypass mode is not possible for xnr3. +*/ +extern const struct ia_css_xnr3_0_5_config default_xnr3_0_5_config; + + + +/* (void) = ia_css_xnr3_0_5_vmem_encode(*to, *from) + * ----------------------------------------------- + * VMEM Encode Function to translate UV parameters from userspace into ISP space +*/ +void +ia_css_xnr3_0_5_vmem_encode( + struct sh_css_isp_xnr3_0_5_vmem_params *to, + const struct ia_css_xnr3_0_5_config *from, + unsigned size); + +/* (void) = ia_css_xnr3_0_5_encode(*to, *from) + * ----------------------------------------------- + * DMEM Encode Function to translate UV parameters from userspace into ISP space +*/ +void +ia_css_xnr3_0_5_encode( + struct sh_css_isp_xnr3_0_5_params *to, + const struct ia_css_xnr3_0_5_config *from, + unsigned size); + +/* (void) = ia_css_xnr3_0_5_debug_dtrace(*config, level) + * ----------------------------------------------- + * Dummy Function added as the tool expects it + */ +void +ia_css_xnr3_0_5_debug_dtrace( + const struct ia_css_xnr3_0_5_config *config, + unsigned level); + +#endif /* __IA_CSS_XNR3_0_5_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_5/ia_css_xnr3_0_5_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_5/ia_css_xnr3_0_5_param.h new file mode 100644 index 0000000000000000000000000000000000000000..fc1d9ccaf881d06820ed5e4c64b97e62c65081e8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_5/ia_css_xnr3_0_5_param.h @@ -0,0 +1,50 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR3_0_5_PARAM_H +#define __IA_CSS_XNR3_0_5_PARAM_H + +#include "type_support.h" +#include "vmem.h" /* needed for VMEM_ARRAY */ + +/* XNR3.0.5 filter size */ +#define XNR_FILTER_SIZE 5 + +/* + * STRUCT sh_css_isp_xnr3_0_5_vmem_params + * ----------------------------------------------- + * XNR3.0.5 ISP VMEM parameters + */ +struct sh_css_isp_xnr3_0_5_vmem_params { + VMEM_ARRAY(x, ISP_VEC_NELEMS); + VMEM_ARRAY(a, ISP_VEC_NELEMS); + VMEM_ARRAY(b, ISP_VEC_NELEMS); + VMEM_ARRAY(c, ISP_VEC_NELEMS); +}; + +/* + * STRUCT sh_css_isp_xnr3_0_5_params + * ----------------------------------------------- + * XNR3.0.5 ISP parameters + */ +struct sh_css_isp_xnr3_0_5_params { + int32_t weight_y0; + int32_t weight_u0; + int32_t weight_v0; + int32_t weight_ydiff; + int32_t weight_udiff; + int32_t weight_vdiff; +}; + +#endif /*__IA_CSS_XNR3_0_5_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_5/ia_css_xnr3_0_5_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_5/ia_css_xnr3_0_5_types.h new file mode 100644 index 0000000000000000000000000000000000000000..ba7c81ece58de1dab19c3c9b49e8034de65e0d04 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr3_0_5/ia_css_xnr3_0_5_types.h @@ -0,0 +1,33 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR3_0_5_TYPES_H +#define __IA_CSS_XNR3_0_5_TYPES_H + +/* + * STRUCT ia_css_xnr3_0_5_config + * ----------------------------------------------- + * Struct with all parameters for the XNR3.0.5 kernel that can be set + * from the CSS API +*/ +struct ia_css_xnr3_0_5_config { + int32_t weight_y0; /**< Weight for Y range similarity in dark area */ + int32_t weight_y1; /**< Weight for Y range similarity in bright area */ + int32_t weight_u0; /**< Weight for U range similarity in dark area */ + int32_t weight_u1; /**< Weight for U range similarity in bright area */ + int32_t weight_v0; /**< Weight for V range similarity in dark area */ + int32_t weight_v1; /**< Weight for V range similarity in bright area */ +}; + +#endif /* __IA_CSS_XNR3_0_5_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.c new file mode 100644 index 0000000000000000000000000000000000000000..3018100f6f767b15d14a1f539b4be65ae6a1fded --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.c @@ -0,0 +1,66 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "sh_css_frac.h" + +#include "ia_css_xnr.host.h" + +const struct ia_css_xnr_config default_xnr_config = { + /** default threshold 6400 translates to 25 on ISP. */ + 6400 +}; + +void +ia_css_xnr_table_vamem_encode( + struct sh_css_isp_xnr_vamem_params *to, + const struct ia_css_xnr_table *from, + unsigned size) +{ + (void)size; + memcpy (&to->xnr, &from->data, sizeof(to->xnr)); +} + +void +ia_css_xnr_encode( + struct sh_css_isp_xnr_params *to, + const struct ia_css_xnr_config *from, + unsigned size) +{ + (void)size; + + to->threshold = + (uint16_t)uDIGIT_FITTING(from->threshold, 16, SH_CSS_ISP_YUV_BITS); +} + +void +ia_css_xnr_table_debug_dtrace( + const struct ia_css_xnr_table *config, + unsigned level) +{ + (void)config; + (void)level; +} + +void +ia_css_xnr_debug_dtrace( + const struct ia_css_xnr_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.threshold=%d\n", config->threshold); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.h new file mode 100644 index 0000000000000000000000000000000000000000..eb3425eafbbef6cf93aad9f21a08ce4884531858 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.h @@ -0,0 +1,47 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR_HOST_H +#define __IA_CSS_XNR_HOST_H + +#include "sh_css_params.h" + +#include "ia_css_xnr_param.h" +#include "ia_css_xnr_table.host.h" + +extern const struct ia_css_xnr_config default_xnr_config; + +void +ia_css_xnr_table_vamem_encode( + struct sh_css_isp_xnr_vamem_params *to, + const struct ia_css_xnr_table *from, + unsigned size); + +void +ia_css_xnr_encode( + struct sh_css_isp_xnr_params *to, + const struct ia_css_xnr_config *from, + unsigned size); + +void +ia_css_xnr_table_debug_dtrace( + const struct ia_css_xnr_table *s3a, + unsigned level); + +void +ia_css_xnr_debug_dtrace( + const struct ia_css_xnr_config *config, + unsigned level); + +#endif /* __IA_CSS_XNR_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_param.h new file mode 100644 index 0000000000000000000000000000000000000000..806c9f8f0e2eb68fd638a7bbb842f63ec0d5fd0a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_param.h @@ -0,0 +1,51 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR_PARAM_H +#define __IA_CSS_XNR_PARAM_H + +#include "type_support.h" +#include + +#ifndef PIPE_GENERATION +#if defined(HAS_VAMEM_VERSION_2) +#define SH_CSS_ISP_XNR_TABLE_SIZE_LOG2 IA_CSS_VAMEM_2_XNR_TABLE_SIZE_LOG2 +#define SH_CSS_ISP_XNR_TABLE_SIZE IA_CSS_VAMEM_2_XNR_TABLE_SIZE +#elif defined(HAS_VAMEM_VERSION_1) +#define SH_CSS_ISP_XNR_TABLE_SIZE_LOG2 IA_CSS_VAMEM_1_XNR_TABLE_SIZE_LOG2 +#define SH_CSS_ISP_XNR_TABLE_SIZE IA_CSS_VAMEM_1_XNR_TABLE_SIZE +#else +#error "Unknown vamem type" +#endif + + +#else +/* For pipe generation, the size is not relevant */ +#define SH_CSS_ISP_XNR_TABLE_SIZE 0 +#endif + +/* This should be vamem_data_t, but that breaks the pipe generator */ +struct sh_css_isp_xnr_vamem_params { + uint16_t xnr[SH_CSS_ISP_XNR_TABLE_SIZE]; +}; + +struct sh_css_isp_xnr_params { + /** XNR threshold. + * type:u0.16 but actual valid range is:[0,255] + * valid range is dependent on SH_CSS_ISP_YUV_BITS (currently 8bits) + * default: 25 */ + uint16_t threshold; +}; + +#endif /* __IA_CSS_XNR_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_table.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_table.host.c new file mode 100644 index 0000000000000000000000000000000000000000..cd5fb72fce3fd2ea99b863fafbab224ae409e8ac --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_table.host.c @@ -0,0 +1,81 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include /* memcpy */ +#include "system_global.h" +#include "vamem.h" +#include "ia_css_types.h" +#include "ia_css_xnr_table.host.h" + +struct ia_css_xnr_table default_xnr_table; + +#if defined(HAS_VAMEM_VERSION_2) + +static const uint16_t +default_xnr_table_data[IA_CSS_VAMEM_2_XNR_TABLE_SIZE] = { + /* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 */ + 8191>>1, 4096>>1, 2730>>1, 2048>>1, 1638>>1, 1365>>1, 1170>>1, 1024>>1, 910>>1, 819>>1, 744>>1, 682>>1, 630>>1, 585>>1, + 546>>1, 512>>1, + + /* 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 */ + 481>>1, 455>>1, 431>>1, 409>>1, 390>>1, 372>>1, 356>>1, 341>>1, 327>>1, 315>>1, 303>>1, 292>>1, 282>>1, 273>>1, 264>>1, + 256>>1, + + /* 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 */ + 248>>1, 240>>1, 234>>1, 227>>1, 221>>1, 215>>1, 210>>1, 204>>1, 199>>1, 195>>1, 190>>1, 186>>1, 182>>1, 178>>1, 174>>1, + 170>>1, + + /* 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 */ + 167>>1, 163>>1, 160>>1, 157>>1, 154>>1, 151>>1, 148>>1, 146>>1, 143>>1, 141>>1, 138>>1, 136>>1, 134>>1, 132>>1, 130>>1, 128>>1 +}; + +#elif defined(HAS_VAMEM_VERSION_1) + +static const uint16_t +default_xnr_table_data[IA_CSS_VAMEM_1_XNR_TABLE_SIZE] = { + /* 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 */ + 8191>>1, 4096>>1, 2730>>1, 2048>>1, 1638>>1, 1365>>1, 1170>>1, 1024>>1, 910>>1, 819>>1, 744>>1, 682>>1, 630>>1, 585>>1, + 546>>1, 512>>1, + + /* 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 */ + 481>>1, 455>>1, 431>>1, 409>>1, 390>>1, 372>>1, 356>>1, 341>>1, 327>>1, 315>>1, 303>>1, 292>>1, 282>>1, 273>>1, 264>>1, + 256>>1, + + /* 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 */ + 248>>1, 240>>1, 234>>1, 227>>1, 221>>1, 215>>1, 210>>1, 204>>1, 199>>1, 195>>1, 190>>1, 186>>1, 182>>1, 178>>1, 174>>1, + 170>>1, + + /* 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 */ + 167>>1, 163>>1, 160>>1, 157>>1, 154>>1, 151>>1, 148>>1, 146>>1, 143>>1, 141>>1, 138>>1, 136>>1, 134>>1, 132>>1, 130>>1, 128>>1 +}; + +#else +#error "sh_css_params.c: VAMEM version must \ + be one of {VAMEM_VERSION_1, VAMEM_VERSION_2}" +#endif + +void +ia_css_config_xnr_table(void) +{ +#if defined(HAS_VAMEM_VERSION_2) + memcpy(default_xnr_table.data.vamem_2, default_xnr_table_data, + sizeof(default_xnr_table_data)); + default_xnr_table.vamem_type = IA_CSS_VAMEM_TYPE_2; +#else + memcpy(default_xnr_table.data.vamem_1, default_xnr_table_data, + sizeof(default_xnr_table_data)); + default_xnr_table.vamem_type = IA_CSS_VAMEM_TYPE_1; +#endif +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_table.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_table.host.h new file mode 100644 index 0000000000000000000000000000000000000000..130086713a7f22fa99db7fda3553a36777cbf6c3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_table.host.h @@ -0,0 +1,22 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR_TABLE_HOST_H +#define __IA_CSS_XNR_TABLE_HOST_H + +extern struct ia_css_xnr_table default_xnr_table; + +void ia_css_config_xnr_table(void); + +#endif /* __IA_CSS_XNR_TABLE_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_types.h new file mode 100644 index 0000000000000000000000000000000000000000..89e8b0f17e8cf90184c458ac0b08625ff767fd9e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_types.h @@ -0,0 +1,71 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR_TYPES_H +#define __IA_CSS_XNR_TYPES_H + +/** @file +* CSS-API header file for Extra Noise Reduction (XNR) parameters. +*/ + +/** XNR table. + * + * NOTE: The driver does not need to set this table, + * because the default values are set inside the css. + * + * This table contains coefficients used for division in XNR. + * + * u0.12, [0,4095], + * {4095, 2048, 1365, .........., 65, 64} + * ({1/1, 1/2, 1/3, ............., 1/63, 1/64}) + * + * ISP block: XNR1 + * ISP1: XNR1 is used. + * ISP2: XNR1 is used. + * + */ + +/** Number of elements in the xnr table. */ +#define IA_CSS_VAMEM_1_XNR_TABLE_SIZE_LOG2 6 +/** Number of elements in the xnr table. */ +#define IA_CSS_VAMEM_1_XNR_TABLE_SIZE (1U< XNR_MAX_ALPHA) { + alpha = XNR_MAX_ALPHA; + } + } + + return alpha; +} + +/* + * Compute the scaled coring value for the ISP kernel from the value on the + * host parameter interface. + */ +static int32_t +compute_coring(int coring) +{ + int32_t isp_coring; + int32_t isp_scale = XNR_CORING_SCALE_FACTOR; + int32_t host_scale = IA_CSS_XNR3_CORING_SCALE; + int32_t offset = host_scale / 2; /* fixed-point 0.5 */ + + /* Convert from public host-side scale factor to isp-side scale + * factor. Clip to [0, isp_scale-1). */ + isp_coring = ((coring * isp_scale) + offset) / host_scale; + return min(max(isp_coring, 0), isp_scale - 1); +} + +/* + * Compute the scaled blending strength for the ISP kernel from the value on + * the host parameter interface. + */ +static int32_t +compute_blending(int strength) +{ + int32_t isp_strength; + int32_t isp_scale = XNR_BLENDING_SCALE_FACTOR; + int32_t host_scale = IA_CSS_XNR3_BLENDING_SCALE; + int32_t offset = host_scale / 2; /* fixed-point 0.5 */ + + /* Convert from public host-side scale factor to isp-side scale + * factor. The blending factor is positive on the host side, but + * negative on the ISP side because +1.0 cannot be represented + * exactly as s0.11 fixed point, but -1.0 can. */ + isp_strength = -(((strength * isp_scale) + offset) / host_scale); + return max(min(isp_strength, 0), -XNR_BLENDING_SCALE_FACTOR); +} + +void +ia_css_xnr3_encode( + struct sh_css_isp_xnr3_params *to, + const struct ia_css_xnr3_config *from, + unsigned size) +{ + int kernel_size = XNR_FILTER_SIZE; + /* The adjust factor is the next power of 2 + w.r.t. the kernel size*/ + int adjust_factor = ceil_pow2(kernel_size); + int32_t max_diff = (1 << (ISP_VEC_ELEMBITS - 1)) - 1; + int32_t min_diff = -(1 << (ISP_VEC_ELEMBITS - 1)); + + int32_t alpha_y0 = compute_alpha(from->sigma.y0); + int32_t alpha_y1 = compute_alpha(from->sigma.y1); + int32_t alpha_u0 = compute_alpha(from->sigma.u0); + int32_t alpha_u1 = compute_alpha(from->sigma.u1); + int32_t alpha_v0 = compute_alpha(from->sigma.v0); + int32_t alpha_v1 = compute_alpha(from->sigma.v1); + int32_t alpha_ydiff = (alpha_y1 - alpha_y0) * adjust_factor / kernel_size; + int32_t alpha_udiff = (alpha_u1 - alpha_u0) * adjust_factor / kernel_size; + int32_t alpha_vdiff = (alpha_v1 - alpha_v0) * adjust_factor / kernel_size; + + int32_t coring_u0 = compute_coring(from->coring.u0); + int32_t coring_u1 = compute_coring(from->coring.u1); + int32_t coring_v0 = compute_coring(from->coring.v0); + int32_t coring_v1 = compute_coring(from->coring.v1); + int32_t coring_udiff = (coring_u1 - coring_u0) * adjust_factor / kernel_size; + int32_t coring_vdiff = (coring_v1 - coring_v0) * adjust_factor / kernel_size; + + int32_t blending = compute_blending(from->blending.strength); + + (void)size; + + /* alpha's are represented in qN.5 format */ + to->alpha.y0 = alpha_y0; + to->alpha.u0 = alpha_u0; + to->alpha.v0 = alpha_v0; + to->alpha.ydiff = min(max(alpha_ydiff, min_diff), max_diff); + to->alpha.udiff = min(max(alpha_udiff, min_diff), max_diff); + to->alpha.vdiff = min(max(alpha_vdiff, min_diff), max_diff); + + /* coring parameters are expressed in q1.NN format */ + to->coring.u0 = coring_u0; + to->coring.v0 = coring_v0; + to->coring.udiff = min(max(coring_udiff, min_diff), max_diff); + to->coring.vdiff = min(max(coring_vdiff, min_diff), max_diff); + + /* blending strength is expressed in q1.NN format */ + to->blending.strength = blending; +} + +#ifdef ISP2401 +/* (void) = ia_css_xnr3_vmem_encode(*to, *from) + * ----------------------------------------------- + * VMEM Encode Function to translate UV parameters from userspace into ISP space +*/ +void +ia_css_xnr3_vmem_encode( + struct sh_css_isp_xnr3_vmem_params *to, + const struct ia_css_xnr3_config *from, + unsigned size) +{ + unsigned i, j, base; + const unsigned total_blocks = 4; + const unsigned shuffle_block = 16; + + (void)from; + (void)size; + + /* Init */ + for (i = 0; i < ISP_VEC_NELEMS; i++) { + to->x[0][i] = 0; + to->a[0][i] = 0; + to->b[0][i] = 0; + to->c[0][i] = 0; + } + + + /* Constraints on "x": + * - values should be greater or equal to 0. + * - values should be ascending. + */ + assert(x[0] >= 0); + + for (j = 1; j < XNR3_LOOK_UP_TABLE_POINTS; j++) { + assert(x[j] >= 0); + assert(x[j] > x[j-1]); + + } + + + /* The implementation of the calulating 1/x is based on the availability + * of the OP_vec_shuffle16 operation. + * A 64 element vector is split up in 4 blocks of 16 element. Each array is copied to + * a vector 4 times, (starting at 0, 16, 32 and 48). All array elements are copied or + * initialised as described in the KFS. The remaining elements of a vector are set to 0. + */ + /* TODO: guard this code with above assumptions */ + for (i = 0; i < total_blocks; i++) { + base = shuffle_block * i; + + for (j = 0; j < XNR3_LOOK_UP_TABLE_POINTS; j++) { + to->x[0][base + j] = x[j]; + to->a[0][base + j] = a[j]; + to->b[0][base + j] = b[j]; + to->c[0][base + j] = c[j]; + } + } +} + + + +#endif +/* Dummy Function added as the tool expects it*/ +void +ia_css_xnr3_debug_dtrace( + const struct ia_css_xnr3_config *config, + unsigned level) +{ + (void)config; + (void)level; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.h new file mode 100644 index 0000000000000000000000000000000000000000..6a86924a71fe1ac36fde4865b02a71c457ab5f94 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.h @@ -0,0 +1,42 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR3_HOST_H +#define __IA_CSS_XNR3_HOST_H + +#include "ia_css_xnr3_param.h" +#include "ia_css_xnr3_types.h" + +extern const struct ia_css_xnr3_config default_xnr3_config; + +void +ia_css_xnr3_encode( + struct sh_css_isp_xnr3_params *to, + const struct ia_css_xnr3_config *from, + unsigned size); + +#ifdef ISP2401 +void +ia_css_xnr3_vmem_encode( + struct sh_css_isp_xnr3_vmem_params *to, + const struct ia_css_xnr3_config *from, + unsigned size); + +#endif +void +ia_css_xnr3_debug_dtrace( + const struct ia_css_xnr3_config *config, + unsigned level); + +#endif /* __IA_CSS_XNR3_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_3.0/ia_css_xnr3_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_3.0/ia_css_xnr3_param.h new file mode 100644 index 0000000000000000000000000000000000000000..06c24e848234308606a625016f88cd704919aefa --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_3.0/ia_css_xnr3_param.h @@ -0,0 +1,96 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR3_PARAM_H +#define __IA_CSS_XNR3_PARAM_H + +#include "type_support.h" +#ifdef ISP2401 +#include "vmem.h" /* needed for VMEM_ARRAY */ + +#endif + +/* Scaling factor of the alpha values: which fixed-point value represents 1.0? + * It must be chosen such that 1/min_sigma still fits in an ISP vector + * element. */ +#define XNR_ALPHA_SCALE_LOG2 5 +#define XNR_ALPHA_SCALE_FACTOR (1 << XNR_ALPHA_SCALE_LOG2) + +/* Scaling factor of the coring values on the ISP. */ +#define XNR_CORING_SCALE_LOG2 (ISP_VEC_ELEMBITS-1) +#define XNR_CORING_SCALE_FACTOR (1 << XNR_CORING_SCALE_LOG2) + +/* Scaling factor of the blending strength on the ISP. */ +#define XNR_BLENDING_SCALE_LOG2 (ISP_VEC_ELEMBITS-1) +#define XNR_BLENDING_SCALE_FACTOR (1 << XNR_BLENDING_SCALE_LOG2) + +/* XNR3 filter size. Must be 11x11, 9x9 or 5x5. */ +#ifdef FLT_KERNEL_9x9 +#define XNR_FILTER_SIZE 9 +#else +#ifdef FLT_KERNEL_11x11 +#define XNR_FILTER_SIZE 11 +#else +#define XNR_FILTER_SIZE 5 +#endif +#endif + +/* XNR3 alpha (1/sigma) parameters on the ISP, expressed as a base (0) value + * for dark areas, and a scaled diff towards the value for bright areas. */ +struct sh_css_xnr3_alpha_params { + int32_t y0; + int32_t u0; + int32_t v0; + int32_t ydiff; + int32_t udiff; + int32_t vdiff; +}; + +/* XNR3 coring parameters on the ISP, expressed as a base (0) value + * for dark areas, and a scaled diff towards the value for bright areas. */ +struct sh_css_xnr3_coring_params { + int32_t u0; + int32_t v0; + int32_t udiff; + int32_t vdiff; +}; + +/* XNR3 blending strength on the ISP. */ +struct sh_css_xnr3_blending_params { + int32_t strength; +}; + +/* XNR3 ISP parameters */ +struct sh_css_isp_xnr3_params { + struct sh_css_xnr3_alpha_params alpha; + struct sh_css_xnr3_coring_params coring; + struct sh_css_xnr3_blending_params blending; +}; + +#ifdef ISP2401 +/* + * STRUCT sh_css_isp_xnr3_vmem_params + * ----------------------------------------------- + * ISP VMEM parameters + */ +struct sh_css_isp_xnr3_vmem_params { + VMEM_ARRAY(x, ISP_VEC_NELEMS); + VMEM_ARRAY(a, ISP_VEC_NELEMS); + VMEM_ARRAY(b, ISP_VEC_NELEMS); + VMEM_ARRAY(c, ISP_VEC_NELEMS); +}; + + +#endif +#endif /*__IA_CSS_XNR3_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_3.0/ia_css_xnr3_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_3.0/ia_css_xnr3_types.h new file mode 100644 index 0000000000000000000000000000000000000000..8f14d10806515c9bec9f10cb9b12da61e25740f4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_3.0/ia_css_xnr3_types.h @@ -0,0 +1,98 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR3_TYPES_H +#define __IA_CSS_XNR3_TYPES_H + +/** @file +* CSS-API header file for Extra Noise Reduction (XNR) parameters. +*/ + +/** + * \brief Scale of the XNR sigma parameters. + * \details The define specifies which fixed-point value represents 1.0. + */ +#define IA_CSS_XNR3_SIGMA_SCALE (1 << 10) + +/** + * \brief Scale of the XNR coring parameters. + * \details The define specifies which fixed-point value represents 1.0. + */ +#define IA_CSS_XNR3_CORING_SCALE (1 << 15) + +/** + * \brief Scale of the XNR blending parameter. + * \details The define specifies which fixed-point value represents 1.0. + */ +#define IA_CSS_XNR3_BLENDING_SCALE (1 << 11) + + +/** + * \brief XNR3 Sigma Parameters. + * \details Sigma parameters define the strength of the XNR filter. + * A higher number means stronger filtering. There are two values for each of + * the three YUV planes: one for dark areas and one for bright areas. All + * sigma parameters are fixed-point values between 0.0 and 1.0, scaled with + * IA_CSS_XNR3_SIGMA_SCALE. + */ +struct ia_css_xnr3_sigma_params { + int y0; /**< Sigma for Y range similarity in dark area */ + int y1; /**< Sigma for Y range similarity in bright area */ + int u0; /**< Sigma for U range similarity in dark area */ + int u1; /**< Sigma for U range similarity in bright area */ + int v0; /**< Sigma for V range similarity in dark area */ + int v1; /**< Sigma for V range similarity in bright area */ +}; + +/** + * \brief XNR3 Coring Parameters + * \details Coring parameters define the "coring" strength, which is a soft + * thresholding technique to avoid false coloring. There are two values for + * each of the two chroma planes: one for dark areas and one for bright areas. + * All coring parameters are fixed-point values between 0.0 and 1.0, scaled + * with IA_CSS_XNR3_CORING_SCALE. The ineffective value is 0. + */ +struct ia_css_xnr3_coring_params { + int u0; /**< Coring threshold of U channel in dark area */ + int u1; /**< Coring threshold of U channel in bright area */ + int v0; /**< Coring threshold of V channel in dark area */ + int v1; /**< Coring threshold of V channel in bright area */ +}; + +/** + * \brief XNR3 Blending Parameters + * \details Blending parameters define the blending strength of filtered + * output pixels with the original chroma pixels from before xnr3. The + * blending strength is a fixed-point value between 0.0 and 1.0 (inclusive), + * scaled with IA_CSS_XNR3_BLENDING_SCALE. + * A higher number applies xnr filtering more strongly. A value of 1.0 + * disables the blending and returns the xnr3 filtered output, while a + * value of 0.0 bypasses the entire xnr3 filter. + */ +struct ia_css_xnr3_blending_params { + int strength; /**< Blending strength */ +}; + +/** + * \brief XNR3 public parameters. + * \details Struct with all parameters for the XNR3 kernel that can be set + * from the CSS API. + */ +struct ia_css_xnr3_config { + struct ia_css_xnr3_sigma_params sigma; /**< XNR3 sigma parameters */ + struct ia_css_xnr3_coring_params coring; /**< XNR3 coring parameters */ + struct ia_css_xnr3_blending_params blending; /**< XNR3 blending parameters */ +}; + +#endif /* __IA_CSS_XNR3_TYPES_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_3.0/ia_css_xnr3_wrapper_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_3.0/ia_css_xnr3_wrapper_param.h new file mode 100644 index 0000000000000000000000000000000000000000..1a98555fd5d9adc48c2a2cf625a3feb69ee33c0b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/xnr/xnr_3.0/ia_css_xnr3_wrapper_param.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_XNR3_WRAPPER_PARAM_H +#define __IA_CSS_XNR3_WRAPPER_PARAM_H + +#include "ia_css_xnr3_param.h" + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.c new file mode 100644 index 0000000000000000000000000000000000000000..d8dccce772a9432a273884ad3d04a6b4bd54f3d5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.c @@ -0,0 +1,219 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "sh_css_frac.h" + +#include "bnr/bnr_1.0/ia_css_bnr.host.h" +#include "ia_css_ynr.host.h" + +const struct ia_css_nr_config default_nr_config = { + 16384, + 8192, + 1280, + 0, + 0 +}; + +const struct ia_css_ee_config default_ee_config = { + 8192, + 128, + 2048 +}; + +void +ia_css_nr_encode( + struct sh_css_isp_ynr_params *to, + const struct ia_css_nr_config *from, + unsigned size) +{ + (void)size; + /* YNR (Y Noise Reduction) */ + to->threshold = + uDIGIT_FITTING((unsigned)8192, 16, SH_CSS_BAYER_BITS); + to->gain_all = + uDIGIT_FITTING(from->ynr_gain, 16, SH_CSS_YNR_GAIN_SHIFT); + to->gain_dir = + uDIGIT_FITTING(from->ynr_gain, 16, SH_CSS_YNR_GAIN_SHIFT); + to->threshold_cb = + uDIGIT_FITTING(from->threshold_cb, 16, SH_CSS_BAYER_BITS); + to->threshold_cr = + uDIGIT_FITTING(from->threshold_cr, 16, SH_CSS_BAYER_BITS); +} + +void +ia_css_yee_encode( + struct sh_css_isp_yee_params *to, + const struct ia_css_yee_config *from, + unsigned size) +{ + int asiWk1 = (int) from->ee.gain; + int asiWk2 = asiWk1 / 8; + int asiWk3 = asiWk1 / 4; + + (void)size; + /* YEE (Y Edge Enhancement) */ + to->dirthreshold_s = + min((uDIGIT_FITTING(from->nr.direction, 16, SH_CSS_BAYER_BITS) + << 1), + SH_CSS_BAYER_MAXVAL); + to->dirthreshold_g = + min((uDIGIT_FITTING(from->nr.direction, 16, SH_CSS_BAYER_BITS) + << 4), + SH_CSS_BAYER_MAXVAL); + to->dirthreshold_width_log2 = + uFRACTION_BITS_FITTING(8); + to->dirthreshold_width = + 1 << to->dirthreshold_width_log2; + to->detailgain = + uDIGIT_FITTING(from->ee.detail_gain, 11, + SH_CSS_YEE_DETAIL_GAIN_SHIFT); + to->coring_s = + (uDIGIT_FITTING((unsigned)56, 16, SH_CSS_BAYER_BITS) * + from->ee.threshold) >> 8; + to->coring_g = + (uDIGIT_FITTING((unsigned)224, 16, SH_CSS_BAYER_BITS) * + from->ee.threshold) >> 8; + /* 8; // *1.125 ->[s4.8] */ + to->scale_plus_s = + (asiWk1 + asiWk2) >> (11 - SH_CSS_YEE_SCALE_SHIFT); + /* 8; // ( * -.25)->[s4.8] */ + to->scale_plus_g = + (0 - asiWk3) >> (11 - SH_CSS_YEE_SCALE_SHIFT); + /* 8; // *0.875 ->[s4.8] */ + to->scale_minus_s = + (asiWk1 - asiWk2) >> (11 - SH_CSS_YEE_SCALE_SHIFT); + /* 8; // ( *.25 ) ->[s4.8] */ + to->scale_minus_g = + (asiWk3) >> (11 - SH_CSS_YEE_SCALE_SHIFT); + to->clip_plus_s = + uDIGIT_FITTING((unsigned)32760, 16, SH_CSS_BAYER_BITS); + to->clip_plus_g = 0; + to->clip_minus_s = + uDIGIT_FITTING((unsigned)504, 16, SH_CSS_BAYER_BITS); + to->clip_minus_g = + uDIGIT_FITTING((unsigned)32256, 16, SH_CSS_BAYER_BITS); + to->Yclip = SH_CSS_BAYER_MAXVAL; +} + +void +ia_css_nr_dump( + const struct sh_css_isp_ynr_params *ynr, + unsigned level) +{ + if (!ynr) return; + ia_css_debug_dtrace(level, + "Y Noise Reduction:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ynr_threshold", ynr->threshold); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ynr_gain_all", ynr->gain_all); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ynr_gain_dir", ynr->gain_dir); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ynr_threshold_cb", ynr->threshold_cb); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ynr_threshold_cr", ynr->threshold_cr); +} + +void +ia_css_yee_dump( + const struct sh_css_isp_yee_params *yee, + unsigned level) +{ + ia_css_debug_dtrace(level, + "Y Edge Enhancement:\n"); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ynryee_dirthreshold_s", + yee->dirthreshold_s); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ynryee_dirthreshold_g", + yee->dirthreshold_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ynryee_dirthreshold_width_log2", + yee->dirthreshold_width_log2); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ynryee_dirthreshold_width", + yee->dirthreshold_width); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_detailgain", + yee->detailgain); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_coring_s", + yee->coring_s); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_coring_g", + yee->coring_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_scale_plus_s", + yee->scale_plus_s); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_scale_plus_g", + yee->scale_plus_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_scale_minus_s", + yee->scale_minus_s); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_scale_minus_g", + yee->scale_minus_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_clip_plus_s", + yee->clip_plus_s); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_clip_plus_g", + yee->clip_plus_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_clip_minus_s", + yee->clip_minus_s); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "yee_clip_minus_g", + yee->clip_minus_g); + ia_css_debug_dtrace(level, "\t%-32s = %d\n", + "ynryee_Yclip", + yee->Yclip); +} + +void +ia_css_nr_debug_dtrace( + const struct ia_css_nr_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.direction=%d, " + "config.bnr_gain=%d, config.ynr_gain=%d, " + "config.threshold_cb=%d, config.threshold_cr=%d\n", + config->direction, + config->bnr_gain, config->ynr_gain, + config->threshold_cb, config->threshold_cr); +} + +void +ia_css_ee_debug_dtrace( + const struct ia_css_ee_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.threshold=%d, config.gain=%d, config.detail_gain=%d\n", + config->threshold, config->gain, config->detail_gain); +} + +void +ia_css_init_ynr_state( + void/*struct sh_css_isp_ynr_vmem_state*/ *state, + size_t size) +{ + memset(state, 0, size); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h new file mode 100644 index 0000000000000000000000000000000000000000..b5730df313ef56fbc85acb6205a29110c9053dc6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.h @@ -0,0 +1,60 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YNR_HOST_H +#define __IA_CSS_YNR_HOST_H + +#include "ia_css_ynr_types.h" +#include "ia_css_ynr_param.h" + +extern const struct ia_css_nr_config default_nr_config; +extern const struct ia_css_ee_config default_ee_config; + +void +ia_css_nr_encode( + struct sh_css_isp_ynr_params *to, + const struct ia_css_nr_config *from, + unsigned size); + +void +ia_css_yee_encode( + struct sh_css_isp_yee_params *to, + const struct ia_css_yee_config *from, + unsigned size); + +void +ia_css_nr_dump( + const struct sh_css_isp_ynr_params *ynr, + unsigned level); + +void +ia_css_yee_dump( + const struct sh_css_isp_yee_params *yee, + unsigned level); + +void +ia_css_nr_debug_dtrace( + const struct ia_css_nr_config *config, + unsigned level); + +void +ia_css_ee_debug_dtrace( + const struct ia_css_ee_config *config, + unsigned level); + +void +ia_css_init_ynr_state( + void/*struct sh_css_isp_ynr_vmem_state*/ *state, + size_t size); +#endif /* __IA_CSS_YNR_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_1.0/ia_css_ynr_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_1.0/ia_css_ynr_param.h new file mode 100644 index 0000000000000000000000000000000000000000..ad61ec1211e81604907c28ae4efb0f5a4788ccad --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_1.0/ia_css_ynr_param.h @@ -0,0 +1,49 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YNR_PARAM_H +#define __IA_CSS_YNR_PARAM_H + +#include "type_support.h" + +/* YNR (Y Noise Reduction) */ +struct sh_css_isp_ynr_params { + int32_t threshold; + int32_t gain_all; + int32_t gain_dir; + int32_t threshold_cb; + int32_t threshold_cr; +}; + +/* YEE (Y Edge Enhancement) */ +struct sh_css_isp_yee_params { + int32_t dirthreshold_s; + int32_t dirthreshold_g; + int32_t dirthreshold_width_log2; + int32_t dirthreshold_width; + int32_t detailgain; + int32_t coring_s; + int32_t coring_g; + int32_t scale_plus_s; + int32_t scale_plus_g; + int32_t scale_minus_s; + int32_t scale_minus_g; + int32_t clip_plus_s; + int32_t clip_plus_g; + int32_t clip_minus_s; + int32_t clip_minus_g; + int32_t Yclip; +}; + +#endif /* __IA_CSS_YNR_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_1.0/ia_css_ynr_state.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_1.0/ia_css_ynr_state.h new file mode 100644 index 0000000000000000000000000000000000000000..b2348b19c3cd1735464c01a5d0a368d1c694045f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_1.0/ia_css_ynr_state.h @@ -0,0 +1,26 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YNR_STATE_H +#define __IA_CSS_YNR_STATE_H + +#include "type_support.h" +#include "vmem.h" + +/* YNR (luminance noise reduction) */ +struct sh_css_isp_ynr_vmem_state { + VMEM_ARRAY(ynr_buf[4], MAX_VECTORS_PER_BUF_LINE*ISP_NWAY); +}; + +#endif /* __IA_CSS_YNR_STATE_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_1.0/ia_css_ynr_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_1.0/ia_css_ynr_types.h new file mode 100644 index 0000000000000000000000000000000000000000..3f46655bee57fd9af3d52f3a8f6209d04a349bac --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_1.0/ia_css_ynr_types.h @@ -0,0 +1,81 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YNR_TYPES_H +#define __IA_CSS_YNR_TYPES_H + +/** @file +* CSS-API header file for Noise Reduction (BNR) and YCC Noise Reduction (YNR,CNR). +*/ + +/** Configuration used by Bayer Noise Reduction (BNR) and + * YCC Noise Reduction (YNR,CNR). + * + * ISP block: BNR1, YNR1, CNR1 + * ISP1: BNR1,YNR1,CNR1 are used. + * ISP2: BNR1,YNR1,CNR1 are used for Preview/Video. + * BNR1,YNR2,CNR2 are used for Still. + */ +struct ia_css_nr_config { + ia_css_u0_16 bnr_gain; /**< Strength of noise reduction (BNR). + u0.16, [0,65535], + default 14336(0.21875), ineffective 0 */ + ia_css_u0_16 ynr_gain; /**< Strength of noise reduction (YNR). + u0.16, [0,65535], + default 14336(0.21875), ineffective 0 */ + ia_css_u0_16 direction; /**< Sensitivity of edge (BNR). + u0.16, [0,65535], + default 512(0.0078125), ineffective 0 */ + ia_css_u0_16 threshold_cb; /**< Coring threshold for Cb (CNR). + This is the same as + de_config.c1_coring_threshold. + u0.16, [0,65535], + default 0(0), ineffective 0 */ + ia_css_u0_16 threshold_cr; /**< Coring threshold for Cr (CNR). + This is the same as + de_config.c2_coring_threshold. + u0.16, [0,65535], + default 0(0), ineffective 0 */ +}; + +/** Edge Enhancement (sharpen) configuration. + * + * ISP block: YEE1 + * ISP1: YEE1 is used. + * ISP2: YEE1 is used for Preview/Video. + * (YEE2 is used for Still.) + */ +struct ia_css_ee_config { + ia_css_u5_11 gain; /**< The strength of sharpness. + u5.11, [0,65535], + default 8192(4.0), ineffective 0 */ + ia_css_u8_8 threshold; /**< The threshold that divides noises from + edge. + u8.8, [0,65535], + default 256(1.0), ineffective 65535 */ + ia_css_u5_11 detail_gain; /**< The strength of sharpness in pell-mell + area. + u5.11, [0,65535], + default 2048(1.0), ineffective 0 */ +}; + +/** YNR and YEE (sharpen) configuration. + */ +struct ia_css_yee_config { + struct ia_css_nr_config nr; /**< The NR configuration. */ + struct ia_css_ee_config ee; /**< The EE configuration. */ +}; + +#endif /* __IA_CSS_YNR_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_2/ia_css_ynr2.host.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_2/ia_css_ynr2.host.c new file mode 100644 index 0000000000000000000000000000000000000000..44b0050042389d7a6770219abec03b3db9aaf75a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_2/ia_css_ynr2.host.c @@ -0,0 +1,125 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "assert_support.h" + +#include "ia_css_ynr2.host.h" + +const struct ia_css_ynr_config default_ynr_config = { + 0, + 0, + 0, + 0, +}; + +const struct ia_css_fc_config default_fc_config = { + 1, + 0, /* 0 -> ineffective */ + 0, /* 0 -> ineffective */ + 0, /* 0 -> ineffective */ + 0, /* 0 -> ineffective */ + (1 << (ISP_VEC_ELEMBITS - 2)), /* 0.5 */ + (1 << (ISP_VEC_ELEMBITS - 2)), /* 0.5 */ + (1 << (ISP_VEC_ELEMBITS - 2)), /* 0.5 */ + (1 << (ISP_VEC_ELEMBITS - 2)), /* 0.5 */ + (1 << (ISP_VEC_ELEMBITS - 1)) - 1, /* 1 */ + (1 << (ISP_VEC_ELEMBITS - 1)) - 1, /* 1 */ + (int16_t)- (1 << (ISP_VEC_ELEMBITS - 1)), /* -1 */ + (int16_t)- (1 << (ISP_VEC_ELEMBITS - 1)), /* -1 */ +}; + +void +ia_css_ynr_encode( + struct sh_css_isp_yee2_params *to, + const struct ia_css_ynr_config *from, + unsigned size) +{ + (void)size; + to->edge_sense_gain_0 = from->edge_sense_gain_0; + to->edge_sense_gain_1 = from->edge_sense_gain_1; + to->corner_sense_gain_0 = from->corner_sense_gain_0; + to->corner_sense_gain_1 = from->corner_sense_gain_1; +} + +void +ia_css_fc_encode( + struct sh_css_isp_fc_params *to, + const struct ia_css_fc_config *from, + unsigned size) +{ + (void)size; + to->gain_exp = from->gain_exp; + + to->coring_pos_0 = from->coring_pos_0; + to->coring_pos_1 = from->coring_pos_1; + to->coring_neg_0 = from->coring_neg_0; + to->coring_neg_1 = from->coring_neg_1; + + to->gain_pos_0 = from->gain_pos_0; + to->gain_pos_1 = from->gain_pos_1; + to->gain_neg_0 = from->gain_neg_0; + to->gain_neg_1 = from->gain_neg_1; + + to->crop_pos_0 = from->crop_pos_0; + to->crop_pos_1 = from->crop_pos_1; + to->crop_neg_0 = from->crop_neg_0; + to->crop_neg_1 = from->crop_neg_1; +} + +void +ia_css_ynr_dump( + const struct sh_css_isp_yee2_params *yee2, + unsigned level); + +void +ia_css_fc_dump( + const struct sh_css_isp_fc_params *fc, + unsigned level); + +void +ia_css_fc_debug_dtrace( + const struct ia_css_fc_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.gain_exp=%d, " + "config.coring_pos_0=%d, config.coring_pos_1=%d, " + "config.coring_neg_0=%d, config.coring_neg_1=%d, " + "config.gain_pos_0=%d, config.gain_pos_1=%d, " + "config.gain_neg_0=%d, config.gain_neg_1=%d, " + "config.crop_pos_0=%d, config.crop_pos_1=%d, " + "config.crop_neg_0=%d, config.crop_neg_1=%d\n", + config->gain_exp, + config->coring_pos_0, config->coring_pos_1, + config->coring_neg_0, config->coring_neg_1, + config->gain_pos_0, config->gain_pos_1, + config->gain_neg_0, config->gain_neg_1, + config->crop_pos_0, config->crop_pos_1, + config->crop_neg_0, config->crop_neg_1); +} + +void +ia_css_ynr_debug_dtrace( + const struct ia_css_ynr_config *config, + unsigned level) +{ + ia_css_debug_dtrace(level, + "config.edge_sense_gain_0=%d, config.edge_sense_gain_1=%d, " + "config.corner_sense_gain_0=%d, config.corner_sense_gain_1=%d\n", + config->edge_sense_gain_0, config->edge_sense_gain_1, + config->corner_sense_gain_0, config->corner_sense_gain_1); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_2/ia_css_ynr2.host.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_2/ia_css_ynr2.host.h new file mode 100644 index 0000000000000000000000000000000000000000..71e89c469e4c6f6afec3fb8cd0af53361415db83 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_2/ia_css_ynr2.host.h @@ -0,0 +1,56 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YNR2_HOST_H +#define __IA_CSS_YNR2_HOST_H + +#include "ia_css_ynr2_types.h" +#include "ia_css_ynr2_param.h" + +extern const struct ia_css_ynr_config default_ynr_config; +extern const struct ia_css_fc_config default_fc_config; + +void +ia_css_ynr_encode( + struct sh_css_isp_yee2_params *to, + const struct ia_css_ynr_config *from, + unsigned size); + +void +ia_css_fc_encode( + struct sh_css_isp_fc_params *to, + const struct ia_css_fc_config *from, + unsigned size); + +void +ia_css_ynr_dump( + const struct sh_css_isp_yee2_params *yee2, + unsigned level); + +void +ia_css_fc_dump( + const struct sh_css_isp_fc_params *fc, + unsigned level); + +void +ia_css_fc_debug_dtrace( + const struct ia_css_fc_config *config, + unsigned level); + +void +ia_css_ynr_debug_dtrace( + const struct ia_css_ynr_config *config, + unsigned level); + +#endif /* __IA_CSS_YNR2_HOST_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_2/ia_css_ynr2_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_2/ia_css_ynr2_param.h new file mode 100644 index 0000000000000000000000000000000000000000..e56b695bef2787a3e1836bc00e7298f4494de6c2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_2/ia_css_ynr2_param.h @@ -0,0 +1,45 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YNR2_PARAM_H +#define __IA_CSS_YNR2_PARAM_H + +#include "type_support.h" + +/* YNR (Y Noise Reduction), YEE (Y Edge Enhancement) */ +struct sh_css_isp_yee2_params { + int32_t edge_sense_gain_0; + int32_t edge_sense_gain_1; + int32_t corner_sense_gain_0; + int32_t corner_sense_gain_1; +}; + +/* Fringe Control */ +struct sh_css_isp_fc_params { + int32_t gain_exp; + uint16_t coring_pos_0; + uint16_t coring_pos_1; + uint16_t coring_neg_0; + uint16_t coring_neg_1; + int32_t gain_pos_0; + int32_t gain_pos_1; + int32_t gain_neg_0; + int32_t gain_neg_1; + int32_t crop_pos_0; + int32_t crop_pos_1; + int32_t crop_neg_0; + int32_t crop_neg_1; +}; + +#endif /* __IA_CSS_YNR2_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_2/ia_css_ynr2_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_2/ia_css_ynr2_types.h new file mode 100644 index 0000000000000000000000000000000000000000..e0a0b10ac5fa540c0e569e3f4b57f3ca2047ec54 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_2/ia_css_ynr2_types.h @@ -0,0 +1,94 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YNR2_TYPES_H +#define __IA_CSS_YNR2_TYPES_H + +/** @file +* CSS-API header file for Y(Luma) Noise Reduction. +*/ + +/** Y(Luma) Noise Reduction configuration. + * + * ISP block: YNR2 & YEE2 + * (ISP1: YNR1 and YEE1 are used.) + * (ISP2: YNR1 and YEE1 are used for Preview/Video.) + * ISP2: YNR2 and YEE2 are used for Still. + */ +struct ia_css_ynr_config { + uint16_t edge_sense_gain_0; /**< Sensitivity of edge in dark area. + u13.0, [0,8191], + default 1000, ineffective 0 */ + uint16_t edge_sense_gain_1; /**< Sensitivity of edge in bright area. + u13.0, [0,8191], + default 1000, ineffective 0 */ + uint16_t corner_sense_gain_0; /**< Sensitivity of corner in dark area. + u13.0, [0,8191], + default 1000, ineffective 0 */ + uint16_t corner_sense_gain_1; /**< Sensitivity of corner in bright area. + u13.0, [0,8191], + default 1000, ineffective 0 */ +}; + +/** Fringe Control configuration. + * + * ISP block: FC2 (FC2 is used with YNR2/YEE2.) + * (ISP1: FC2 is not used.) + * (ISP2: FC2 is not for Preview/Video.) + * ISP2: FC2 is used for Still. + */ +struct ia_css_fc_config { + uint8_t gain_exp; /**< Common exponent of gains. + u8.0, [0,13], + default 1, ineffective 0 */ + uint16_t coring_pos_0; /**< Coring threshold for positive edge in dark area. + u0.13, [0,8191], + default 0(0), ineffective 0 */ + uint16_t coring_pos_1; /**< Coring threshold for positive edge in bright area. + u0.13, [0,8191], + default 0(0), ineffective 0 */ + uint16_t coring_neg_0; /**< Coring threshold for negative edge in dark area. + u0.13, [0,8191], + default 0(0), ineffective 0 */ + uint16_t coring_neg_1; /**< Coring threshold for negative edge in bright area. + u0.13, [0,8191], + default 0(0), ineffective 0 */ + uint16_t gain_pos_0; /**< Gain for positive edge in dark area. + u0.13, [0,8191], + default 4096(0.5), ineffective 0 */ + uint16_t gain_pos_1; /**< Gain for positive edge in bright area. + u0.13, [0,8191], + default 4096(0.5), ineffective 0 */ + uint16_t gain_neg_0; /**< Gain for negative edge in dark area. + u0.13, [0,8191], + default 4096(0.5), ineffective 0 */ + uint16_t gain_neg_1; /**< Gain for negative edge in bright area. + u0.13, [0,8191], + default 4096(0.5), ineffective 0 */ + uint16_t crop_pos_0; /**< Limit for positive edge in dark area. + u0.13, [0,8191], + default/ineffective 8191(almost 1.0) */ + uint16_t crop_pos_1; /**< Limit for positive edge in bright area. + u0.13, [0,8191], + default/ineffective 8191(almost 1.0) */ + int16_t crop_neg_0; /**< Limit for negative edge in dark area. + s0.13, [-8192,0], + default/ineffective -8192(-1.0) */ + int16_t crop_neg_1; /**< Limit for negative edge in bright area. + s0.13, [-8192,0], + default/ineffective -8192(-1.0) */ +}; + +#endif /* __IA_CSS_YNR2_TYPES_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_2/ia_css_ynr_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_2/ia_css_ynr_param.h new file mode 100644 index 0000000000000000000000000000000000000000..48fb7d22d7c139b2f62436620394aa2b44a1ec4b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_2/ia_css_ynr_param.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YNRX_PARAM_H +#define __IA_CSS_YNRX_PARAM_H + +#include "ia_css_ynr2_param.h" + +#endif /* __IA_CSS_YNRX_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_2/ia_css_ynr_state.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_2/ia_css_ynr_state.h new file mode 100644 index 0000000000000000000000000000000000000000..2516dd3dc12b7a1032a4ddc3bb7592de1bed5b14 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/ynr/ynr_2/ia_css_ynr_state.h @@ -0,0 +1,21 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YNR2_STATE_H +#define __IA_CSS_YNR2_STATE_H + +/* Reuse YNR1 states */ +#include "../ynr_1.0/ia_css_ynr_state.h" + +#endif /* __IA_CSS_YNR2_STATE_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/yuv_ls/yuv_ls_1.0/ia_css_yuv_load_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/yuv_ls/yuv_ls_1.0/ia_css_yuv_load_param.h new file mode 100644 index 0000000000000000000000000000000000000000..400c6790cbf504ee0865d21cfb6d749a83a7a0d4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/yuv_ls/yuv_ls_1.0/ia_css_yuv_load_param.h @@ -0,0 +1,20 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YUV_LOAD_PARAM_H +#define __IA_CSS_YUV_LOAD_PARAM_H + +#include "ia_css_yuv_ls_param.h" + +#endif /* __IA_CSS_YUV_LOAD_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/yuv_ls/yuv_ls_1.0/ia_css_yuv_ls_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/yuv_ls/yuv_ls_1.0/ia_css_yuv_ls_param.h new file mode 100644 index 0000000000000000000000000000000000000000..63a8703c9c44bc0a4e1f8b8527bd0ac7bc8734e6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/yuv_ls/yuv_ls_1.0/ia_css_yuv_ls_param.h @@ -0,0 +1,39 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YUV_LS_PARAM_H +#define __IA_CSS_YUV_LS_PARAM_H + +#include "type_support.h" +#ifndef ISP2401 + +/* The number of load/store kernels in a pipeline can be greater than one. + * A kernel can consume more than one input or can produce more + * than one output. + */ +#define NUM_YUV_LS 2 + +/** YUV load/store */ +struct sh_css_isp_yuv_ls_isp_config { + unsigned base_address[NUM_YUV_LS]; + unsigned width[NUM_YUV_LS]; + unsigned height[NUM_YUV_LS]; + unsigned stride[NUM_YUV_LS]; +}; + +#else +#include "../../io_ls/common/ia_css_common_io_types.h" +#endif + +#endif /* __IA_CSS_YUV_LS_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/yuv_ls/yuv_ls_1.0/ia_css_yuv_store_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/yuv_ls/yuv_ls_1.0/ia_css_yuv_store_param.h new file mode 100644 index 0000000000000000000000000000000000000000..69c474ea1ffdb5834e45d955760479f0967dcc2a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/kernels/yuv_ls/yuv_ls_1.0/ia_css_yuv_store_param.h @@ -0,0 +1,21 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __IA_CSS_YUV_STORE_PARAM_H +#define __IA_CSS_YUV_STORE_PARAM_H + +#include "ia_css_yuv_ls_param.h" + + +#endif /* __IA_CSS_YUV_STORE_PARAM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/modes/interface/input_buf.isp.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/modes/interface/input_buf.isp.h new file mode 100644 index 0000000000000000000000000000000000000000..32714d5870cf98f8eab0f82ddbce6d82d7084c44 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/modes/interface/input_buf.isp.h @@ -0,0 +1,73 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef _INPUT_BUF_ISP_H_ +#define _INPUT_BUF_ISP_H_ + +/* Temporary include, since IA_CSS_BINARY_MODE_COPY is still needed */ +#include "sh_css_defs.h" +#include "isp_const.h" /* MAX_VECTORS_PER_INPUT_LINE */ + +#define INPUT_BUF_HEIGHT 2 /* double buffer */ +#define INPUT_BUF_LINES 2 + +#ifndef ENABLE_CONTINUOUS +#define ENABLE_CONTINUOUS 0 +#endif + +/* In continuous mode, the input buffer must be a fixed size for all binaries + * and at a fixed address since it will be used by the SP. */ +#define EXTRA_INPUT_VECTORS 2 /* For left padding */ +#define MAX_VECTORS_PER_INPUT_LINE_CONT (CEIL_DIV(SH_CSS_MAX_SENSOR_WIDTH, ISP_NWAY) + EXTRA_INPUT_VECTORS) + +/* The input buffer should be on a fixed address in vmem, for continuous capture */ +#define INPUT_BUF_ADDR 0x0 +#if (defined(__ISP) && (!defined(MODE) || MODE != IA_CSS_BINARY_MODE_COPY)) + +#if ENABLE_CONTINUOUS +typedef struct { + tmemvectoru raw[INPUT_BUF_HEIGHT][INPUT_BUF_LINES][MAX_VECTORS_PER_INPUT_LINE_CONT]; /* 2 bayer lines */ + /* Two more lines for SP raw copy efficiency */ +#ifndef ENABLE_REDUCED_INPUT_BUFFER + /* "Workaround" solution in the case that space needed vmem exceeds the size of the vmem. */ + /* Since in theory this buffer is not needed for IPU 2.2/2.3, */ + /* the workaround solution will not be needed (and the whole buffer) after the code refactoring. */ + tmemvectoru _raw[INPUT_BUF_HEIGHT][INPUT_BUF_LINES][MAX_VECTORS_PER_INPUT_LINE_CONT]; /* 2 bayer lines */ +#endif +} input_line_type; +#else /* ENABLE CONTINUOUS == 0 */ +typedef struct { + tmemvectoru raw[INPUT_BUF_HEIGHT][INPUT_BUF_LINES][MAX_VECTORS_PER_INPUT_LINE]; /* 2 bayer lines */ +} input_line_type; +#endif /* ENABLE_CONTINUOUS */ + +#endif /*MODE*/ + +#endif /* _INPUT_BUF_ISP_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/modes/interface/isp_const.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/modes/interface/isp_const.h new file mode 100644 index 0000000000000000000000000000000000000000..b3f5b781bed9f93e458bf01845ea22ef56b044ce --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/modes/interface/isp_const.h @@ -0,0 +1,506 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef _COMMON_ISP_CONST_H_ +#define _COMMON_ISP_CONST_H_ + +/*#include "isp.h"*/ /* ISP_VEC_NELEMS */ + +/* Binary independent constants */ + +#ifdef MODE +//#error __FILE__ "is mode independent" +#endif + +#ifndef NO_HOIST +# define NO_HOIST HIVE_ATTRIBUTE (( no_hoist )) +#endif + +#define NO_HOIST_CSE HIVE_ATTRIBUTE ((no_hoist, no_cse)) + +#ifdef __HIVECC +#define UNION union +#else +#define UNION struct /* Union constructors not allowed in C++ */ +#endif + +/* ISP binary identifiers. + These determine the order in which the binaries are looked up, do not change + this! + Also, the SP firmware uses this same order (isp_loader.hive.c). + Also, gen_firmware.c uses this order in its firmware_header. +*/ +/* The binary id is used in pre-processor expressions so we cannot + * use an enum here. */ + /* 24xx pipelines*/ +#define SH_CSS_BINARY_ID_COPY 0 +#define SH_CSS_BINARY_ID_BAYER_DS 1 +#define SH_CSS_BINARY_ID_VF_PP_FULL 2 +#define SH_CSS_BINARY_ID_VF_PP_OPT 3 +#define SH_CSS_BINARY_ID_YUV_SCALE 4 +#define SH_CSS_BINARY_ID_CAPTURE_PP 5 +#define SH_CSS_BINARY_ID_PRE_ISP 6 +#define SH_CSS_BINARY_ID_PRE_ISP_ISP2 7 +#define SH_CSS_BINARY_ID_GDC 8 +#define SH_CSS_BINARY_ID_POST_ISP 9 +#define SH_CSS_BINARY_ID_POST_ISP_ISP2 10 +#define SH_CSS_BINARY_ID_ANR 11 +#define SH_CSS_BINARY_ID_ANR_ISP2 12 +#define SH_CSS_BINARY_ID_PREVIEW_CONT_DS 13 +#define SH_CSS_BINARY_ID_PREVIEW_DS 14 +#define SH_CSS_BINARY_ID_PREVIEW_DEC 15 +#define SH_CSS_BINARY_ID_PREVIEW_CONT_BDS125_ISP2 16 +#define SH_CSS_BINARY_ID_PREVIEW_CONT_DPC_BDS150_ISP2 17 +#define SH_CSS_BINARY_ID_PREVIEW_CONT_BDS150_ISP2 18 +#define SH_CSS_BINARY_ID_PREVIEW_CONT_DPC_BDS200_ISP2 19 +#define SH_CSS_BINARY_ID_PREVIEW_CONT_BDS200_ISP2 20 +#define SH_CSS_BINARY_ID_PREVIEW_DZ 21 +#define SH_CSS_BINARY_ID_PREVIEW_DZ_ISP2 22 +#define SH_CSS_BINARY_ID_PRIMARY_DS 23 +#define SH_CSS_BINARY_ID_PRIMARY_VAR 24 +#define SH_CSS_BINARY_ID_PRIMARY_VAR_ISP2 25 +#define SH_CSS_BINARY_ID_PRIMARY_SMALL 26 +#define SH_CSS_BINARY_ID_PRIMARY_STRIPED 27 +#define SH_CSS_BINARY_ID_PRIMARY_STRIPED_ISP2 28 +#define SH_CSS_BINARY_ID_PRIMARY_8MP 29 +#define SH_CSS_BINARY_ID_PRIMARY_14MP 30 +#define SH_CSS_BINARY_ID_PRIMARY_16MP 31 +#define SH_CSS_BINARY_ID_PRIMARY_REF 32 +#define SH_CSS_BINARY_ID_PRIMARY_ISP261_STAGE0 33 +#define SH_CSS_BINARY_ID_PRIMARY_ISP261_STAGE1 34 +#define SH_CSS_BINARY_ID_PRIMARY_ISP261_STAGE2 35 +#define SH_CSS_BINARY_ID_PRIMARY_ISP261_STAGE3 36 +#define SH_CSS_BINARY_ID_PRIMARY_ISP261_STAGE4 37 +#define SH_CSS_BINARY_ID_PRIMARY_ISP261_STAGE5 38 +#define SH_CSS_BINARY_ID_VIDEO_OFFLINE 39 +#define SH_CSS_BINARY_ID_VIDEO_DS 40 +#define SH_CSS_BINARY_ID_VIDEO_YUV_DS 41 +#define SH_CSS_BINARY_ID_VIDEO_DZ 42 +#define SH_CSS_BINARY_ID_VIDEO_DZ_2400_ONLY 43 +#define SH_CSS_BINARY_ID_VIDEO_HIGH 44 +#define SH_CSS_BINARY_ID_VIDEO_NODZ 45 +#define SH_CSS_BINARY_ID_VIDEO_CONT_MULTIBDS_ISP2_MIN 46 +#define SH_CSS_BINARY_ID_VIDEO_CONT_BDS_300_600_ISP2_MIN 47 +#define SH_CSS_BINARY_ID_VIDEO_CONT_DPC_BDS150_ISP2_MIN 48 +#define SH_CSS_BINARY_ID_VIDEO_CONT_BDS150_ISP2_MIN 49 +#define SH_CSS_BINARY_ID_VIDEO_CONT_DPC_BDS200_ISP2_MIN 50 +#define SH_CSS_BINARY_ID_VIDEO_CONT_BDS200_ISP2_MIN 51 +#define SH_CSS_BINARY_ID_VIDEO_CONT_NOBDS_ISP2_MIN 52 +#define SH_CSS_BINARY_ID_VIDEO_DZ_ISP2_MIN 53 +#define SH_CSS_BINARY_ID_VIDEO_DZ_ISP2 54 +#define SH_CSS_BINARY_ID_VIDEO_LP_ISP2 55 +#define SH_CSS_BINARY_ID_RESERVED1 56 +#define SH_CSS_BINARY_ID_ACCELERATION 57 +#define SH_CSS_BINARY_ID_PRE_DE_ISP2 58 +#define SH_CSS_BINARY_ID_KERNEL_TEST_LOAD_STORE 59 +#define SH_CSS_BINARY_ID_CAPTURE_PP_BLI 60 +#define SH_CSS_BINARY_ID_CAPTURE_PP_LDC 61 +#ifdef ISP2401 +#define SH_CSS_BINARY_ID_PRIMARY_STRIPED_ISP2_XNR 62 +#endif + +/* skycam kerneltest pipelines */ +#ifndef ISP2401 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_NORM 120 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_NORM_STRIPED 121 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_LIN 122 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_LIN_STRIPED 123 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_ACC_SHD 124 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_ACC_SHD_STRIPED 125 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_ACC_AWB 126 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_3A 127 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_3A_STRIPED 128 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_ACC_AF 129 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_OBGRID 130 +#define SH_CSS_BINARY_ID_VIDEO_TEST_ACC_BAYER_DENOISE 131 +#define SH_CSS_BINARY_ID_VIDEO_TEST_ACC_BAYER_DENOISE_STRIPED 132 +#define SH_CSS_BINARY_ID_VIDEO_TEST_ACC_DEMOSAIC 133 +#define SH_CSS_BINARY_ID_VIDEO_TEST_ACC_YUVP1_C0 134 +#define SH_CSS_BINARY_ID_VIDEO_TEST_ACC_YUVP2 135 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_REF 136 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_REF_STRIPED 137 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_XNR_REF 138 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_DVS 139 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_XNR 140 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_XNR_STRIPED 141 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_XNR_BLENDING 142 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_TNR_BLOCK 143 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_ACC_AE 144 +#define SH_CSS_BINARY_ID_VIDEO_RAW 145 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_ACC_AWB_FR 146 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_DM_RGBPP 147 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_DM_RGBPP_STRIPED 148 +#define SH_CSS_BINARY_ID_VIDEO_TEST_ACC_ANR 149 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_IF 150 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_IF_STRIPED 151 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_OUTPUT_SYSTEM 152 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_TNR_STRIPED 153 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_DVS_STRIPED 154 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_OBGRID_STRIPED 155 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_COPY_YUV 156 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_COPY_YUV_BLOCK 157 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_COPY_YUV16_BLOCK 158 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_COPY_YUV16_STRIPED 159 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_COPY_BLOCK_STRIPED 160 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_INPUT_YUV 161 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_OUTPUT_YUV 162 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_OUTPUT_YUV_16 163 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_OUTPUT_SPLIT 164 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_OUTPUT_SYSTEM_STRIPED 165 + +#else +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_NORM 121 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_NORM_STRIPED 122 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_OBGRID 123 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_OBGRID_STRIPED 124 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_LIN 125 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_LIN_STRIPED 126 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_ACC_SHD 127 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_ACC_SHD_STRIPED 128 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_ACC_AE 129 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_ACC_AWB 130 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_ACC_AF 131 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_ACC_AWB_FR 132 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_3A 133 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_3A_STRIPED 134 +#define SH_CSS_BINARY_ID_VIDEO_TEST_ACC_BAYER_DENOISE 135 +#define SH_CSS_BINARY_ID_VIDEO_TEST_ACC_BAYER_DENOISE_STRIPED 136 +#define SH_CSS_BINARY_ID_VIDEO_TEST_ACC_ANR 137 +#define SH_CSS_BINARY_ID_VIDEO_TEST_ACC_ANR_STRIPED 138 +#define SH_CSS_BINARY_ID_VIDEO_TEST_ACC_DEMOSAIC 139 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_DM_RGBPP 140 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_DM_RGBPP_STRIPED 141 +#define SH_CSS_BINARY_ID_VIDEO_TEST_ACC_YUVP1_C0 142 +#define SH_CSS_BINARY_ID_VIDEO_TEST_ACC_YUVP2 143 +#define SH_CSS_BINARY_ID_VIDEO_TEST_ACC_YUVP2_STRIPED 144 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_XNR_REF 145 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_XNR 146 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_XNR_STRIPED 147 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_XNR_BLENDING 148 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_REF 149 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_REF_STRIPED 150 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_DVS 151 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_DVS_STRIPED 152 +#define SH_CSS_BINARY_ID_VIDEO_TEST_ACC_DVS_STAT_C0 153 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_TNR_BLOCK 154 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_TNR_STRIPED 155 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_OUTPUT_SYSTEM 156 +#define SH_CSS_BINARY_ID_VIDEO_RAW 157 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_COPY_YUV 158 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_COPY_YUV_BLOCK 159 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_COPY_YUV16_BLOCK 160 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_COPY_YUV16_STRIPED 161 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_COPY_BLOCK_STRIPED 162 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_INPUT_YUV 163 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_OUTPUT_YUV 164 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_OUTPUT_YUV_16 165 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_OUTPUT_SPLIT 166 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_OUTPUT_SYSTEM_STRIPED 167 +#define SH_CSS_BINARY_ID_COPY_KERNELTEST_OUTPUT_SYSTEM 168 +#endif + +/* skycam partial test pipelines*/ +#ifndef ISP2401 +#define SH_CSS_BINARY_ID_IF_TO_DPC 201 +#define SH_CSS_BINARY_ID_IF_TO_BDS 202 +#else +#define SH_CSS_BINARY_ID_IF_TO_BDS 201 +#define SH_CSS_BINARY_ID_IF_TO_BDS_STRIPED 202 +#endif +#define SH_CSS_BINARY_ID_IF_TO_NORM 203 +#ifndef ISP2401 +#define SH_CSS_BINARY_ID_IF_TO_OB 204 +#define SH_CSS_BINARY_ID_IF_TO_LIN 205 +#define SH_CSS_BINARY_ID_IF_TO_SHD 206 +#define SH_CSS_BINARY_ID_IF_TO_BNR 207 +#define SH_CSS_BINARY_ID_IF_TO_RGBPP_NV12_16 208 +#define SH_CSS_BINARY_ID_IF_TO_RGBPP 210 +#define SH_CSS_BINARY_ID_IF_TO_YUVP1 211 +#define SH_CSS_BINARY_ID_IF_TO_DM 214 +#define SH_CSS_BINARY_ID_IF_TO_YUVP2_C0 216 +#define SH_CSS_BINARY_ID_IF_TO_YUVP2_ANR_VIA_ISP 217 +#define SH_CSS_BINARY_ID_VIDEO_IF_TO_DVS 218 +#define SH_CSS_BINARY_ID_VIDEO_IF_TO_TNR 219 +#define SH_CSS_BINARY_ID_IF_TO_BDS_STRIPED 224 +#define SH_CSS_BINARY_ID_VIDEO_TEST_ACC_ANR_STRIPED 225 +#define SH_CSS_BINARY_ID_VIDEO_TEST_ACC_YUVP2_STRIPED 227 +#define SH_CSS_BINARY_ID_IF_TO_BDS_RGBP_DVS_STAT_C0 228 +#define SH_CSS_BINARY_ID_IF_TO_BDS_RGBP_DVS_STAT_C0_STRIPED 229 +#define SH_CSS_BINARY_ID_IF_TO_REF 236 +#define SH_CSS_BINARY_ID_IF_TO_DVS_STRIPED 237 +#define SH_CSS_BINARY_ID_IF_TO_YUVP2_STRIPED 238 +#define SH_CSS_BINARY_ID_IF_TO_YUVP1_STRIPED 239 +#define SH_CSS_BINARY_ID_IF_TO_RGBPP_STRIPED 240 +#define SH_CSS_BINARY_ID_IF_TO_ANR_STRIPED 241 +#define SH_CSS_BINARY_ID_IF_TO_BNR_STRIPED 242 +#define SH_CSS_BINARY_ID_IF_TO_SHD_STRIPED 243 +#define SH_CSS_BINARY_ID_IF_TO_LIN_STRIPED 244 +#define SH_CSS_BINARY_ID_IF_TO_OB_STRIPED 245 +#define SH_CSS_BINARY_ID_IF_TO_NORM_STRIPED 248 +#define SH_CSS_BINARY_ID_COPY_KERNELTEST_OUTPUT_SYSTEM 253 +#define SH_CSS_BINARY_ID_IF_TO_XNR 256 +#define SH_CSS_BINARY_ID_IF_TO_XNR_STRIPED 257 +#define SH_CSS_BINARY_ID_IF_TO_REF_STRIPED 258 +#define SH_CSS_BINARY_ID_VIDEO_IF_TO_OSYS 259 +#define SH_CSS_BINARY_ID_IF_TO_YUVP1_C0 262 +#define SH_CSS_BINARY_ID_IF_TO_XNR_PRIMARY 263 +#define SH_CSS_BINARY_ID_IF_TO_XNR_PRIMARY_STRIPED 264 +#define SH_CSS_BINARY_ID_IF_TO_ANR 265 +#define SH_CSS_BINARY_ID_VIDEO_TEST_ACC_DVS_STAT_C0 266 +#define SH_CSS_BINARY_ID_VIDEO_IF_TO_OSYS_STRIPED 270 +#define SH_CSS_BINARY_ID_IF_TO_OSYS_PRIMARY 276 +#define SH_CSS_BINARY_ID_IF_TO_OSYS_PRIMARY_STRIPED 277 +#define SH_CSS_BINARY_ID_IF_TO_YUVP1_C0_STRIPED 278 +#else +#define SH_CSS_BINARY_ID_IF_TO_NORM_STRIPED 204 +#define SH_CSS_BINARY_ID_IF_TO_OB 205 +#define SH_CSS_BINARY_ID_IF_TO_OB_STRIPED 206 +#define SH_CSS_BINARY_ID_IF_TO_LIN 207 +#define SH_CSS_BINARY_ID_IF_TO_LIN_STRIPED 208 +#define SH_CSS_BINARY_ID_IF_TO_SHD 209 +#define SH_CSS_BINARY_ID_IF_TO_SHD_STRIPED 210 +#define SH_CSS_BINARY_ID_IF_TO_BNR 211 +#define SH_CSS_BINARY_ID_IF_TO_BNR_STRIPED 212 +#define SH_CSS_BINARY_ID_IF_TO_ANR 213 +#define SH_CSS_BINARY_ID_IF_TO_ANR_STRIPED 214 +#define SH_CSS_BINARY_ID_IF_TO_DM 215 +#define SH_CSS_BINARY_ID_IF_TO_BDS_RGBP_DVS_STAT_C0 216 +#define SH_CSS_BINARY_ID_IF_TO_BDS_RGBP_DVS_STAT_C0_STRIPED 217 +#define SH_CSS_BINARY_ID_IF_TO_RGBPP 218 +#define SH_CSS_BINARY_ID_IF_TO_RGBPP_NV12_16 219 +#define SH_CSS_BINARY_ID_IF_TO_RGBPP_STRIPED 220 +#define SH_CSS_BINARY_ID_IF_TO_YUVP1 221 +#define SH_CSS_BINARY_ID_IF_TO_YUVP1_STRIPED 222 +#define SH_CSS_BINARY_ID_IF_TO_YUVP1_C0 223 +#define SH_CSS_BINARY_ID_IF_TO_YUVP2_C0 224 +#define SH_CSS_BINARY_ID_IF_TO_YUVP2_STRIPED 225 +#define SH_CSS_BINARY_ID_IF_TO_XNR 226 +#define SH_CSS_BINARY_ID_IF_TO_XNR_STRIPED 227 +#define SH_CSS_BINARY_ID_IF_TO_XNR_PRIMARY 228 +#define SH_CSS_BINARY_ID_IF_TO_XNR_PRIMARY_STRIPED 229 +#define SH_CSS_BINARY_ID_IF_TO_REF 230 +#define SH_CSS_BINARY_ID_IF_TO_REF_STRIPED 231 +#define SH_CSS_BINARY_ID_VIDEO_IF_TO_DVS 232 +#define SH_CSS_BINARY_ID_IF_TO_DVS_STRIPED 233 +#define SH_CSS_BINARY_ID_VIDEO_IF_TO_TNR 234 +#define SH_CSS_BINARY_ID_VIDEO_IF_TO_OSYS 235 +#define SH_CSS_BINARY_ID_VIDEO_IF_TO_OSYS_STRIPED 236 +#define SH_CSS_BINARY_ID_IF_TO_OSYS_PRIMARY 237 +#define SH_CSS_BINARY_ID_IF_TO_OSYS_PRIMARY_STRIPED 238 +#define SH_CSS_BINARY_ID_IF_TO_YUVP1_C0_STRIPED 239 +#define SH_CSS_BINARY_ID_VIDEO_YUVP1_TO_OSYS 240 +#define SH_CSS_BINARY_ID_IF_TO_OSYS_PREVIEW 241 +#define SH_CSS_BINARY_ID_IF_TO_OSYS_PREVIEW_STRIPED 242 +#endif + +/* Skycam IR camera binaries */ +#ifndef ISP2401 +#define SH_CSS_BINARY_ID_IR_IF_TO_OSYS_NO_XNR 300 +#define SH_CSS_BINARY_ID_VIDEO_IR_IF_TO_OSYS_NO_DVS_NO_TNR_NO_XNR 301 +#define SH_CSS_BINARY_ID_IR_IF_TO_OSYS_NO_XNR_NO_DVS_PRIMARY 302 +#else +#define SH_CSS_BINARY_ID_IR_IF_TO_OSYS 300 +#define SH_CSS_BINARY_ID_IR_IF_TO_OSYS_NO_TNR3 301 +#define SH_CSS_BINARY_ID_IR_IF_TO_OSYS_PRIMARY 302 + +/* Binaries under development */ +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_TNR3 401 +#define SH_CSS_BINARY_ID_VIDEO_KERNELTEST_TNR3_STRIPED 402 + +#endif + +#define XMEM_WIDTH_BITS HIVE_ISP_DDR_WORD_BITS +#define XMEM_SHORTS_PER_WORD (HIVE_ISP_DDR_WORD_BITS/16) +#define XMEM_INTS_PER_WORD (HIVE_ISP_DDR_WORD_BITS/32) +#define XMEM_POW2_BYTES_PER_WORD HIVE_ISP_DDR_WORD_BYTES + +#define BITS8_ELEMENTS_PER_XMEM_ADDR CEIL_DIV(XMEM_WIDTH_BITS, 8) +#define BITS16_ELEMENTS_PER_XMEM_ADDR CEIL_DIV(XMEM_WIDTH_BITS, 16) + +#if ISP_VEC_NELEMS == 64 +#define ISP_NWAY_LOG2 6 +#elif ISP_VEC_NELEMS == 32 +#define ISP_NWAY_LOG2 5 +#elif ISP_VEC_NELEMS == 16 +#define ISP_NWAY_LOG2 4 +#elif ISP_VEC_NELEMS == 8 +#define ISP_NWAY_LOG2 3 +#else +#error "isp_const.h ISP_VEC_NELEMS must be one of {8, 16, 32, 64}" +#endif + +/* ***************************** + * ISP input/output buffer sizes + * ****************************/ +/* input image */ +#define INPUT_BUF_DMA_HEIGHT 2 +#define INPUT_BUF_HEIGHT 2 /* double buffer */ +#define OUTPUT_BUF_DMA_HEIGHT 2 +#define OUTPUT_BUF_HEIGHT 2 /* double buffer */ +#define OUTPUT_NUM_TRANSFERS 4 + +/* GDC accelerator: Up/Down Scaling */ +/* These should be moved to the gdc_defs.h in the device */ +#define UDS_SCALING_N HRT_GDC_N +/* AB: This should cover the zooming up to 16MP */ +#define UDS_MAX_OXDIM 5000 +/* We support maximally 2 planes with different parameters + - luma and chroma (YUV420) */ +#define UDS_MAX_PLANES 2 +#define UDS_BLI_BLOCK_HEIGHT 2 +#define UDS_BCI_BLOCK_HEIGHT 4 +#define UDS_BLI_INTERP_ENVELOPE 1 +#define UDS_BCI_INTERP_ENVELOPE 3 +#define UDS_MAX_ZOOM_FAC 64 +/* Make it always one FPGA vector. + Four FPGA vectors are required and + four of them fit in one ASIC vector.*/ +#define UDS_MAX_CHUNKS 16 + +#define ISP_LEFT_PADDING _ISP_LEFT_CROP_EXTRA(ISP_LEFT_CROPPING) +#define ISP_LEFT_PADDING_VECS CEIL_DIV(ISP_LEFT_PADDING, ISP_VEC_NELEMS) +/* in case of continuous the croppong of the current binary doesn't matter for the buffer calculation, but the cropping of the sp copy should be used */ +#define ISP_LEFT_PADDING_CONT _ISP_LEFT_CROP_EXTRA(SH_CSS_MAX_LEFT_CROPPING) +#define ISP_LEFT_PADDING_VECS_CONT CEIL_DIV(ISP_LEFT_PADDING_CONT, ISP_VEC_NELEMS) + +#define CEIL_ROUND_DIV_STRIPE(width, stripe, padding) \ + CEIL_MUL(padding + CEIL_DIV(width - padding, stripe), ((ENABLE_RAW_BINNING || ENABLE_FIXED_BAYER_DS)?4:2)) + +/* output (Y,U,V) image, 4:2:0 */ +#define MAX_VECTORS_PER_LINE \ + CEIL_ROUND_DIV_STRIPE(CEIL_DIV(ISP_MAX_INTERNAL_WIDTH, ISP_VEC_NELEMS), \ + ISP_NUM_STRIPES, \ + ISP_LEFT_PADDING_VECS) + +/* + * ITERATOR_VECTOR_INCREMENT' explanation: + * when striping an even number of iterations, one of the stripes is + * one iteration wider than the other to account for overlap + * so the calc for the output buffer vmem size is: + * ((width[vectors]/num_of_stripes) + 2[vectors]) + */ +#if defined(HAS_RES_MGR) +#define MAX_VECTORS_PER_OUTPUT_LINE \ + (CEIL_DIV(CEIL_DIV(ISP_MAX_OUTPUT_WIDTH, ISP_NUM_STRIPES) + ISP_LEFT_PADDING, ISP_VEC_NELEMS) + \ + ITERATOR_VECTOR_INCREMENT) + +#define MAX_VECTORS_PER_INPUT_LINE CEIL_DIV(ISP_MAX_INPUT_WIDTH, ISP_VEC_NELEMS) +#define MAX_VECTORS_PER_INPUT_STRIPE (CEIL_ROUND_DIV_STRIPE(CEIL_DIV(ISP_MAX_INPUT_WIDTH, ISP_VEC_NELEMS) , \ + ISP_NUM_STRIPES, \ + ISP_LEFT_PADDING_VECS) + \ + ITERATOR_VECTOR_INCREMENT) +#else /* !defined(HAS_RES_MGR)*/ +#define MAX_VECTORS_PER_OUTPUT_LINE \ + CEIL_DIV(CEIL_DIV(ISP_MAX_OUTPUT_WIDTH, ISP_NUM_STRIPES) + ISP_LEFT_PADDING, ISP_VEC_NELEMS) + +/* Must be even due to interlaced bayer input */ +#define MAX_VECTORS_PER_INPUT_LINE CEIL_MUL((CEIL_DIV(ISP_MAX_INPUT_WIDTH, ISP_VEC_NELEMS) + ISP_LEFT_PADDING_VECS), 2) +#define MAX_VECTORS_PER_INPUT_STRIPE CEIL_ROUND_DIV_STRIPE(MAX_VECTORS_PER_INPUT_LINE, \ + ISP_NUM_STRIPES, \ + ISP_LEFT_PADDING_VECS) +#endif /* HAS_RES_MGR */ + + +/* Add 2 for left croppping */ +#define MAX_SP_RAW_COPY_VECTORS_PER_INPUT_LINE (CEIL_DIV(ISP_MAX_INPUT_WIDTH, ISP_VEC_NELEMS) + 2) + +#define MAX_VECTORS_PER_BUF_LINE \ + (MAX_VECTORS_PER_LINE + DUMMY_BUF_VECTORS) +#define MAX_VECTORS_PER_BUF_INPUT_LINE \ + (MAX_VECTORS_PER_INPUT_STRIPE + DUMMY_BUF_VECTORS) +#define MAX_OUTPUT_Y_FRAME_WIDTH \ + (MAX_VECTORS_PER_LINE * ISP_VEC_NELEMS) +#define MAX_OUTPUT_Y_FRAME_SIMDWIDTH \ + MAX_VECTORS_PER_LINE +#define MAX_OUTPUT_C_FRAME_WIDTH \ + (MAX_OUTPUT_Y_FRAME_WIDTH / 2) +#define MAX_OUTPUT_C_FRAME_SIMDWIDTH \ + CEIL_DIV(MAX_OUTPUT_C_FRAME_WIDTH, ISP_VEC_NELEMS) + +/* should be even */ +#define NO_CHUNKING (OUTPUT_NUM_CHUNKS == 1) + +#define MAX_VECTORS_PER_CHUNK \ + (NO_CHUNKING ? MAX_VECTORS_PER_LINE \ + : 2*CEIL_DIV(MAX_VECTORS_PER_LINE, \ + 2*OUTPUT_NUM_CHUNKS)) + +#define MAX_C_VECTORS_PER_CHUNK \ + (MAX_VECTORS_PER_CHUNK/2) + +/* should be even */ +#define MAX_VECTORS_PER_OUTPUT_CHUNK \ + (NO_CHUNKING ? MAX_VECTORS_PER_OUTPUT_LINE \ + : 2*CEIL_DIV(MAX_VECTORS_PER_OUTPUT_LINE, \ + 2*OUTPUT_NUM_CHUNKS)) + +#define MAX_C_VECTORS_PER_OUTPUT_CHUNK \ + (MAX_VECTORS_PER_OUTPUT_CHUNK/2) + + + +/* should be even */ +#define MAX_VECTORS_PER_INPUT_CHUNK \ + (INPUT_NUM_CHUNKS == 1 ? MAX_VECTORS_PER_INPUT_STRIPE \ + : 2*CEIL_DIV(MAX_VECTORS_PER_INPUT_STRIPE, \ + 2*OUTPUT_NUM_CHUNKS)) + +#define DEFAULT_C_SUBSAMPLING 2 + +/****** DMA buffer properties */ + +#define RAW_BUF_LINES ((ENABLE_RAW_BINNING || ENABLE_FIXED_BAYER_DS) ? 4 : 2) + +#if defined(HAS_RES_MGR) +#define RAW_BUF_STRIDE (MAX_VECTORS_PER_INPUT_STRIPE) +#else /* !defined(HAS_RES_MGR) */ +#define RAW_BUF_STRIDE \ + (BINARY_ID == SH_CSS_BINARY_ID_POST_ISP ? MAX_VECTORS_PER_INPUT_CHUNK : \ + ISP_NUM_STRIPES > 1 ? MAX_VECTORS_PER_INPUT_STRIPE+_ISP_EXTRA_PADDING_VECS : \ + !ENABLE_CONTINUOUS ? MAX_VECTORS_PER_INPUT_LINE : \ + MAX_VECTORS_PER_INPUT_CHUNK) +#endif /* HAS_RES_MGR */ + +/* [isp vmem] table size[vectors] per line per color (GR,R,B,GB), + multiples of NWAY */ +#define SCTBL_VECTORS_PER_LINE_PER_COLOR \ + CEIL_DIV(SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR, ISP_VEC_NELEMS) +/* [isp vmem] table size[vectors] per line for 4colors (GR,R,B,GB), + multiples of NWAY */ +#define SCTBL_VECTORS_PER_LINE \ + (SCTBL_VECTORS_PER_LINE_PER_COLOR * IA_CSS_SC_NUM_COLORS) + +/*************/ + +/* Format for fixed primaries */ + +#define ISP_FIXED_PRIMARY_FORMAT IA_CSS_FRAME_FORMAT_NV12 + +#endif /* _COMMON_ISP_CONST_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/modes/interface/isp_exprs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/modes/interface/isp_exprs.h new file mode 100644 index 0000000000000000000000000000000000000000..2f65d71c36d0aa75244abdbef5009bbaff3a2287 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/modes/interface/isp_exprs.h @@ -0,0 +1,314 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef _COMMON_ISP_EXPRS_H_ +#define _COMMON_ISP_EXPRS_H_ + +/* Binary independent pre-processor expressions */ + +#include "sh_css_defs.h" +#include "isp_const.h" + +#ifdef __HOST +#error "isp_exprs.h: Do not include on HOST, contains ISP specific defines" +#endif + +#ifndef __ISP +#if defined(MODE) +#define MODE aap +#error "isp_exprs.h: is mode independent, but MODE is set" +#endif +#if defined(VARIABLE_RESOLUTION) +#define VARIABLE_RESOLUTION noot +#error "isp_exprs.h: is mode independent, but VARIABLE_RESOLUTION is set" +#endif +#if defined(DECI_FACTOR_LOG2) +#define DECI_FACTOR_LOG2 mies +#error "isp_exprs.h: is mode independent, but DECI_FACTOR_LOG2 is set" +#endif +#endif + +#define LOG_VECTOR_STEP _ISP_LOG_VECTOR_STEP(MODE) +/* should be even and multiple of vf downscaling */ +#define ISP_OUTPUT_CHUNK_LOG_FACTOR (MAX_VF_LOG_DOWNSCALE<=1 ? LOG_VECTOR_STEP : \ + umax(VF_LOG_DOWNSCALE, LOG_VECTOR_STEP)) + +#define CEIL_DIV_CHUNKS(n,c) ((c) == 1 ? (n) \ + : CEIL_SHIFT(CEIL_DIV((n), (c)), ISP_OUTPUT_CHUNK_LOG_FACTOR)<dvs_envelope.width : 0) +#define ISP_DVS_ENVELOPE_HEIGHT (ENABLE_DVS_ENVELOPE ? stage->dvs_envelope.height : 0) +#else +#define ISP_DVS_ENVELOPE_WIDTH 0 +#define ISP_DVS_ENVELOPE_HEIGHT 0 +#endif + +#define _ISP_INPUT_WIDTH_VECS _ISP_VECS(ISP_INPUT_WIDTH) + +#if !defined(__ISP) || (VARIABLE_RESOLUTION && !__HOST) +#define ISP_INPUT_WIDTH_VECS isp_vectors_per_input_line +#else +#define ISP_INPUT_WIDTH_VECS _ISP_INPUT_WIDTH_VECS +#endif + +#if !defined(__ISP) || VARIABLE_RESOLUTION +#define ISP_INTERNAL_WIDTH_VECS isp_vectors_per_line +#else +#define ISP_INTERNAL_WIDTH_VECS _ISP_INTERNAL_WIDTH_VECS +#endif + +#define _ISP_INTERNAL_HEIGHT __ISP_INTERNAL_HEIGHT(isp_output_height, ISP_TOP_CROPPING, ISP_DVS_ENVELOPE_HEIGHT) + +#define ISP_INTERNAL_HEIGHT isp_internal_height + +#define _ISP_INTERNAL_WIDTH __ISP_INTERNAL_WIDTH(ISP_OUTPUT_WIDTH, ISP_DVS_ENVELOPE_WIDTH, \ + ISP_LEFT_CROPPING, MODE, ISP_C_SUBSAMPLING, \ + OUTPUT_NUM_CHUNKS, ISP_PIPELINING) + +#define ISP_UV_INTERNAL_WIDTH (ISP_INTERNAL_WIDTH / 2) +#define ISP_UV_INTERNAL_HEIGHT (ISP_INTERNAL_HEIGHT / 2) + +#define _ISP_INTERNAL_WIDTH_VECS (_ISP_INTERNAL_WIDTH / ISP_VEC_NELEMS) +#define _ISP_UV_INTERNAL_WIDTH_VECS CEIL_DIV(ISP_UV_INTERNAL_WIDTH, ISP_VEC_NELEMS) + +#define ISP_VF_OUTPUT_WIDTH _ISP_VF_OUTPUT_WIDTH(ISP_VF_OUTPUT_WIDTH_VECS) +#define ISP_VF_OUTPUT_HEIGHT _ISP_VF_OUTPUT_HEIGHT(isp_output_height, VF_LOG_DOWNSCALE) + +#if defined (__ISP) && !VARIABLE_RESOLUTION +#define ISP_INTERNAL_WIDTH _ISP_INTERNAL_WIDTH +#define ISP_VF_OUTPUT_WIDTH_VECS _ISP_VF_OUTPUT_WIDTH_VECS +#else +#define ISP_INTERNAL_WIDTH (VARIABLE_RESOLUTION ? isp_internal_width : _ISP_INTERNAL_WIDTH) +#define ISP_VF_OUTPUT_WIDTH_VECS (VARIABLE_RESOLUTION ? isp_vf_output_width_vecs : _ISP_VF_OUTPUT_WIDTH_VECS) +#endif + +#if defined(__ISP) && !VARIABLE_RESOLUTION +#define ISP_OUTPUT_WIDTH ISP_MAX_OUTPUT_WIDTH +#define VF_LOG_DOWNSCALE MAX_VF_LOG_DOWNSCALE +#else +#define ISP_OUTPUT_WIDTH isp_output_width +#define VF_LOG_DOWNSCALE isp_vf_downscale_bits +#endif + +#if !defined(__ISP) || VARIABLE_RESOLUTION +#define _ISP_MAX_VF_OUTPUT_WIDTH __ISP_MAX_VF_OUTPUT_WIDTH(2*SH_CSS_MAX_VF_WIDTH, ISP_LEFT_CROPPING) +#elif defined(MODE) && MODE == IA_CSS_BINARY_MODE_PRIMARY && ISP_OUTPUT_WIDTH > 3328 +/* Because of vmem issues, should be fixed later */ +#define _ISP_MAX_VF_OUTPUT_WIDTH (SH_CSS_MAX_VF_WIDTH - 2*ISP_VEC_NELEMS + (ISP_LEFT_CROPPING ? 2 * ISP_VEC_NELEMS : 0)) +#else +#define _ISP_MAX_VF_OUTPUT_WIDTH (ISP_VF_OUTPUT_WIDTH + (ISP_LEFT_CROPPING ? (2 >> VF_LOG_DOWNSCALE) * ISP_VEC_NELEMS : 0)) +#endif + +#define ISP_MAX_VF_OUTPUT_VECS CEIL_DIV(_ISP_MAX_VF_OUTPUT_WIDTH, ISP_VEC_NELEMS) + + + +#define ISP_MIN_STRIPE_WIDTH (ISP_PIPELINING * (1<<_ISP_LOG_VECTOR_STEP(MODE))) + +/******* STRIPING-RELATED MACROS *******/ +#define NO_STRIPING (ISP_NUM_STRIPES == 1) + +#if defined(HAS_RES_MGR) + +#define ISP_OUTPUT_CHUNK_VECS ISP_INTERNAL_WIDTH_VECS + +#if defined(__ISP) +#define VECTORS_PER_LINE ISP_INTERNAL_WIDTH_VECS +#else +#define VECTORS_PER_LINE \ + (NO_STRIPING ? ISP_INTERNAL_WIDTH_VECS \ + : ISP_IO_STRIPE_WIDTH_VECS(ISP_INTERNAL_WIDTH_VECS, ISP_LEFT_PADDING_VECS, ISP_NUM_STRIPES, ISP_MIN_STRIPE_WIDTH) ) +#endif + +#define VECTORS_PER_INPUT_LINE \ + (NO_STRIPING ? ISP_INPUT_WIDTH_VECS \ + : ISP_IO_STRIPE_WIDTH_VECS(ISP_INPUT_WIDTH_VECS, ISP_LEFT_PADDING_VECS, ISP_NUM_STRIPES, ISP_MIN_STRIPE_WIDTH) ) + +#else + +#define ISP_OUTPUT_CHUNK_VECS \ + (NO_STRIPING ? CEIL_DIV_CHUNKS(ISP_OUTPUT_VECS_EXTRA_CROP, OUTPUT_NUM_CHUNKS) \ + : ISP_IO_STRIPE_WIDTH_VECS(ISP_OUTPUT_VECS_EXTRA_CROP, ISP_LEFT_PADDING_VECS, ISP_NUM_STRIPES, ISP_MIN_STRIPE_WIDTH) ) + +#define VECTORS_PER_LINE \ + (NO_STRIPING ? ISP_INTERNAL_WIDTH_VECS \ + : ISP_IO_STRIPE_WIDTH_VECS(ISP_INTERNAL_WIDTH_VECS, ISP_LEFT_PADDING_VECS, ISP_NUM_STRIPES, ISP_MIN_STRIPE_WIDTH) ) + +#define VECTORS_PER_INPUT_LINE \ + (NO_STRIPING ? ISP_INPUT_WIDTH_VECS \ + : ISP_IO_STRIPE_WIDTH_VECS(ISP_INPUT_WIDTH_VECS, ISP_LEFT_PADDING_VECS, ISP_NUM_STRIPES, ISP_MIN_STRIPE_WIDTH)+_ISP_EXTRA_PADDING_VECS) + +#endif + +#define ISP_MAX_VF_OUTPUT_STRIPE_VECS \ + (NO_STRIPING ? ISP_MAX_VF_OUTPUT_VECS \ + : CEIL_MUL(CEIL_DIV(ISP_MAX_VF_OUTPUT_VECS, ISP_NUM_STRIPES), 2)) +#define _ISP_VF_OUTPUT_WIDTH_VECS \ + (NO_STRIPING ? __ISP_VF_OUTPUT_WIDTH_VECS(ISP_OUTPUT_WIDTH, VF_LOG_DOWNSCALE) \ + : __ISP_VF_OUTPUT_WIDTH_VECS(CEIL_DIV(ISP_OUTPUT_WIDTH, ISP_NUM_STRIPES), VF_LOG_DOWNSCALE)) + +#define ISP_IO_STRIPE_WIDTH_VECS(width, padding, num_stripes, min_stripe) \ + MAX(CEIL_MUL(padding + CEIL_DIV(width-padding, num_stripes) \ + , 2) \ + , min_stripe) +////////// INPUT & INTERNAL +/* should be even */ +#define INPUT_NUM_CHUNKS OUTPUT_NUM_CHUNKS + +#define INPUT_VECTORS_PER_CHUNK CEIL_DIV_CHUNKS(VECTORS_PER_INPUT_LINE, INPUT_NUM_CHUNKS) + +/* only for ISP code, will be removed: */ +#define VECTORS_PER_FULL_LINE ISP_INTERNAL_WIDTH_VECS +#define VECTORS_PER_INPUT_FULL_LINE ISP_INPUT_WIDTH_VECS + +////////// OUTPUT +/* should at least even and also multiple of vf scaling */ +#define ISP_OUTPUT_VECS_EXTRA_CROP CEIL_DIV(ISP_OUTPUT_WIDTH_EXTRA_CROP, ISP_VEC_NELEMS) + +/* Output is decoupled from input */ +#define ISP_OUTPUT_WIDTH_EXTRA_CROP CEIL_MUL(CEIL_MUL((ENABLE_DVS_ENVELOPE ? ISP_OUTPUT_WIDTH : ISP_INTERNAL_WIDTH), 2*ISP_VEC_NELEMS), \ + ISP_C_SUBSAMPLING * OUTPUT_NUM_CHUNKS * HIVE_ISP_DDR_WORD_BYTES) + +#define ISP_MAX_VF_OUTPUT_CHUNK_VECS \ + (NO_CHUNKING ? ISP_MAX_VF_OUTPUT_STRIPE_VECS \ + : 2*CEIL_DIV(ISP_MAX_VF_OUTPUT_STRIPE_VECS, 2*OUTPUT_NUM_CHUNKS)) + +#define OUTPUT_VECTORS_PER_CHUNK CEIL_DIV_CHUNKS(VECTORS_PER_LINE,OUTPUT_NUM_CHUNKS) + +/* should be even?? */ +#if !defined(HAS_RES_MGR) +#define OUTPUT_C_VECTORS_PER_CHUNK CEIL_DIV(OUTPUT_VECTORS_PER_CHUNK, 2) +#else +#define OUTPUT_C_VECTORS_PER_CHUNK CEIL_DIV(MAX_VECTORS_PER_CHUNK, 2) +#endif + +#ifndef ISP2401 +/**** SCTBL defs *******/ +#define ISP_SCTBL_HEIGHT \ + _ISP_SCTBL_HEIGHT(ISP_INPUT_HEIGHT, DECI_FACTOR_LOG2) + +#endif +/**** UDS defs *********/ +#define UDS_DMACH_STRIDE_B_IN_Y (( ISP_INTERNAL_WIDTH /BITS8_ELEMENTS_PER_XMEM_ADDR)*HIVE_ISP_DDR_WORD_BYTES) +#define UDS_DMACH_STRIDE_B_IN_C (((ISP_INTERNAL_WIDTH/2)/BITS8_ELEMENTS_PER_XMEM_ADDR)*HIVE_ISP_DDR_WORD_BYTES) + +#else /* defined(__ISP) || defined(INIT_VARS) */ + +#define ISP_INTERNAL_WIDTH isp_internal_width +#define ISP_INTERNAL_HEIGHT isp_internal_height + +#endif /* defined(__ISP) || defined(INIT_VARS) */ + +#endif /* _COMMON_ISP_EXPRS_H_ */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/modes/interface/isp_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/modes/interface/isp_types.h new file mode 100644 index 0000000000000000000000000000000000000000..4fa18761f007f6f21d7c29afb2770fd461b8e79b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/isp/modes/interface/isp_types.h @@ -0,0 +1,128 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef _ISP_TYPES_H_ +#define _ISP_TYPES_H_ + +/* Workaround: hivecc complains about "tag "sh_css_3a_output" already declared" + without this extra decl. */ +struct ia_css_3a_output; + +#if defined(__ISP) || defined(__SP) +struct isp_uds_config { + int hive_dx; + int hive_dy; + unsigned hive_woix; + unsigned hive_bpp; /* gdc_bits_per_pixel */ + unsigned hive_bci; +}; + +struct s_isp_gdcac_config { + unsigned nbx; + unsigned nby; +}; + +/* output.hive.c request information */ +typedef enum { + output_y_channel, + output_c_channel, + OUTPUT_NUM_CHANNELS +} output_channel_type; + +typedef struct s_output_dma_info { + unsigned cond; /* Condition for transfer */ + output_channel_type channel_type; + dma_channel channel; + unsigned width_a; + unsigned width_b; + unsigned stride; + unsigned v_delta; /* Offset for v address to do cropping */ + char *x_base; /* X base address */ +} output_dma_info_type; +#endif + +/* Input stream formats, these correspond to the MIPI formats and the way + * the CSS receiver sends these to the input formatter. + * The bit depth of each pixel element is stored in the global variable + * isp_bits_per_pixel. + * NOTE: for rgb565, we set isp_bits_per_pixel to 565, for all other rgb + * formats it's the actual depth (4, for 444, 8 for 888 etc). + */ +enum sh_stream_format { + sh_stream_format_yuv420_legacy, + sh_stream_format_yuv420, + sh_stream_format_yuv422, + sh_stream_format_rgb, + sh_stream_format_raw, + sh_stream_format_binary, /* bytestream such as jpeg */ +}; + +struct s_isp_frames { + /* global variables that are written to by either the SP or the host, + every ISP binary needs these. */ + /* output frame */ + char *xmem_base_addr_y; + char *xmem_base_addr_uv; + char *xmem_base_addr_u; + char *xmem_base_addr_v; + /* 2nd output frame */ + char *xmem_base_addr_second_out_y; + char *xmem_base_addr_second_out_u; + char *xmem_base_addr_second_out_v; + /* input yuv frame */ + char *xmem_base_addr_y_in; + char *xmem_base_addr_u_in; + char *xmem_base_addr_v_in; + /* input raw frame */ + char *xmem_base_addr_raw; + /* output raw frame */ + char *xmem_base_addr_raw_out; + /* viewfinder output (vf_veceven) */ + char *xmem_base_addr_vfout_y; + char *xmem_base_addr_vfout_u; + char *xmem_base_addr_vfout_v; + /* overlay frame (for vf_pp) */ + char *xmem_base_addr_overlay_y; + char *xmem_base_addr_overlay_u; + char *xmem_base_addr_overlay_v; + /* pre-gdc output frame (gdc input) */ + char *xmem_base_addr_qplane_r; + char *xmem_base_addr_qplane_ratb; + char *xmem_base_addr_qplane_gr; + char *xmem_base_addr_qplane_gb; + char *xmem_base_addr_qplane_b; + char *xmem_base_addr_qplane_batr; + /* YUV as input, used by postisp binary */ + char *xmem_base_addr_yuv_16_y; + char *xmem_base_addr_yuv_16_u; + char *xmem_base_addr_yuv_16_v; +}; + +#endif /* _ISP_TYPES_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/memory_realloc.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/memory_realloc.c new file mode 100644 index 0000000000000000000000000000000000000000..e814f1bf19f792d3c1d848f59145d15964a4453d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/memory_realloc.c @@ -0,0 +1,81 @@ +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#include "memory_realloc.h" +#include "ia_css_debug.h" +#include "ia_css_refcount.h" +#include "memory_access.h" + +static bool realloc_isp_css_mm_buf( + hrt_vaddress *curr_buf, + size_t *curr_size, + size_t needed_size, + bool force, + enum ia_css_err *err, + uint16_t mmgr_attribute); + + +bool reallocate_buffer( + hrt_vaddress *curr_buf, + size_t *curr_size, + size_t needed_size, + bool force, + enum ia_css_err *err) +{ + bool ret; + uint16_t mmgr_attribute = MMGR_ATTRIBUTE_DEFAULT; + + IA_CSS_ENTER_PRIVATE("void"); + + ret = realloc_isp_css_mm_buf(curr_buf, + curr_size, needed_size, force, err, mmgr_attribute); + + IA_CSS_LEAVE_PRIVATE("ret=%d", ret); + return ret; +} + +static bool realloc_isp_css_mm_buf( + hrt_vaddress *curr_buf, + size_t *curr_size, + size_t needed_size, + bool force, + enum ia_css_err *err, + uint16_t mmgr_attribute) +{ + int32_t id; + + *err = IA_CSS_SUCCESS; + /* Possible optimization: add a function sh_css_isp_css_mm_realloc() + * and implement on top of hmm. */ + + IA_CSS_ENTER_PRIVATE("void"); + + if (ia_css_refcount_is_single(*curr_buf) && !force && *curr_size >= needed_size) { + IA_CSS_LEAVE_PRIVATE("false"); + return false; + } + + id = IA_CSS_REFCOUNT_PARAM_BUFFER; + ia_css_refcount_decrement(id, *curr_buf); + *curr_buf = ia_css_refcount_increment(id, mmgr_alloc_attr(needed_size, + mmgr_attribute)); + + if (!*curr_buf) { + *err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + *curr_size = 0; + } else { + *curr_size = needed_size; + } + IA_CSS_LEAVE_PRIVATE("true"); + return true; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/binary/interface/ia_css_binary.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/binary/interface/ia_css_binary.h new file mode 100644 index 0000000000000000000000000000000000000000..c65194619a34a832febcbb395a82b82c11980bf2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/binary/interface/ia_css_binary.h @@ -0,0 +1,333 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef _IA_CSS_BINARY_H_ +#define _IA_CSS_BINARY_H_ + +#include +#include "ia_css_types.h" +#include "ia_css_err.h" +#include "ia_css_stream_format.h" +#include "ia_css_stream_public.h" +#include "ia_css_frame_public.h" +#include "sh_css_metrics.h" +#include "isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds_types.h" + +/* The binary mode is used in pre-processor expressions so we cannot + * use an enum here. */ +#define IA_CSS_BINARY_MODE_COPY 0 +#define IA_CSS_BINARY_MODE_PREVIEW 1 +#define IA_CSS_BINARY_MODE_PRIMARY 2 +#define IA_CSS_BINARY_MODE_VIDEO 3 +#define IA_CSS_BINARY_MODE_PRE_ISP 4 +#define IA_CSS_BINARY_MODE_GDC 5 +#define IA_CSS_BINARY_MODE_POST_ISP 6 +#define IA_CSS_BINARY_MODE_ANR 7 +#define IA_CSS_BINARY_MODE_CAPTURE_PP 8 +#define IA_CSS_BINARY_MODE_VF_PP 9 +#define IA_CSS_BINARY_MODE_PRE_DE 10 +#define IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE0 11 +#define IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE1 12 +#define IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE2 13 +#define IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE3 14 +#define IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE4 15 +#define IA_CSS_BINARY_MODE_PRIMARY_HQ_STAGE5 16 +#define IA_CSS_BINARY_NUM_MODES 17 + +#define MAX_NUM_PRIMARY_STAGES 6 +#define NUM_PRIMARY_HQ_STAGES 6 /* number of primary stages for ISP2.6.1 high quality pipe */ +#define NUM_PRIMARY_STAGES 1 /* number of primary satges for ISP1/ISP2.2 pipe */ + +/* Indicate where binaries can read input from */ +#define IA_CSS_BINARY_INPUT_SENSOR 0 +#define IA_CSS_BINARY_INPUT_MEMORY 1 +#define IA_CSS_BINARY_INPUT_VARIABLE 2 + +/* Should be included without the path. + However, that requires adding the path to numerous makefiles + that have nothing to do with isp parameters. + */ +#include "runtime/isp_param/interface/ia_css_isp_param_types.h" + +/* now these ports only include output ports but not vf output ports */ +enum { + IA_CSS_BINARY_OUTPUT_PORT_0 = 0, + IA_CSS_BINARY_OUTPUT_PORT_1 = 1, + IA_CSS_BINARY_MAX_OUTPUT_PORTS = 2 +}; + +struct ia_css_cas_binary_descr { + unsigned int num_stage; + unsigned int num_output_stage; + struct ia_css_frame_info *in_info; + struct ia_css_frame_info *internal_out_info; + struct ia_css_frame_info *out_info; + struct ia_css_frame_info *vf_info; + bool *is_output_stage; +}; + +#define IA_CSS_DEFAULT_CAS_BINARY_DESCR \ +{ \ + 0, \ + 0, \ + NULL, \ + NULL, \ + NULL, \ + NULL, \ + NULL, \ +} + +struct ia_css_binary_descr { + int mode; + bool online; + bool continuous; + bool striped; + bool two_ppc; + bool enable_yuv_ds; + bool enable_high_speed; + bool enable_dvs_6axis; + bool enable_reduced_pipe; + bool enable_dz; + bool enable_xnr; + bool enable_fractional_ds; + bool enable_dpc; +#ifdef ISP2401 + bool enable_luma_only; + bool enable_tnr; +#endif + bool enable_capture_pp_bli; + struct ia_css_resolution dvs_env; + enum ia_css_stream_format stream_format; + struct ia_css_frame_info *in_info; /* the info of the input-frame with the + ISP required resolution. */ + struct ia_css_frame_info *bds_out_info; + struct ia_css_frame_info *out_info[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_frame_info *vf_info; + unsigned int isp_pipe_version; + unsigned int required_bds_factor; + int stream_config_left_padding; +}; + +struct ia_css_binary { + const struct ia_css_binary_xinfo *info; + enum ia_css_stream_format input_format; + struct ia_css_frame_info in_frame_info; + struct ia_css_frame_info internal_frame_info; + struct ia_css_frame_info out_frame_info[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_resolution effective_in_frame_res; + struct ia_css_frame_info vf_frame_info; + int input_buf_vectors; + int deci_factor_log2; + int vf_downscale_log2; + int s3atbl_width; + int s3atbl_height; + int s3atbl_isp_width; + int s3atbl_isp_height; + unsigned int morph_tbl_width; + unsigned int morph_tbl_aligned_width; + unsigned int morph_tbl_height; + int sctbl_width_per_color; + int sctbl_aligned_width_per_color; + int sctbl_height; +#ifdef ISP2401 + int sctbl_legacy_width_per_color; + int sctbl_legacy_height; +#endif + struct ia_css_sdis_info dis; + struct ia_css_resolution dvs_envelope; + bool online; + unsigned int uds_xc; + unsigned int uds_yc; + unsigned int left_padding; + struct sh_css_binary_metrics metrics; + struct ia_css_isp_param_host_segments mem_params; + struct ia_css_isp_param_css_segments css_params; +}; + +#ifdef ISP2401 + +#define IA_CSS_BINARY_DEFAULT_SETTINGS \ +{ \ + NULL, \ + IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY, \ + IA_CSS_BINARY_DEFAULT_FRAME_INFO, \ + IA_CSS_BINARY_DEFAULT_FRAME_INFO, \ + {IA_CSS_BINARY_DEFAULT_FRAME_INFO}, \ + { 0, 0},/* effective_in_frame_res */ \ + IA_CSS_BINARY_DEFAULT_FRAME_INFO, \ + 0, /* input_buf_vectors */ \ + 0, /* deci_factor_log2 */ \ + 0, /* vf_downscale_log2 */ \ + 0, /* s3atbl_width */ \ + 0, /* s3atbl_height */ \ + 0, /* s3atbl_isp_width */ \ + 0, /* s3atbl_isp_height */ \ + 0, /* morph_tbl_width */ \ + 0, /* morph_tbl_aligned_width */ \ + 0, /* morph_tbl_height */ \ + 0, /* sctbl_width_per_color */ \ + 0, /* sctbl_aligned_width_per_color */ \ + 0, /* sctbl_height */ \ + 0, /* sctbl_legacy_width_per_color */ \ + 0, /* sctbl_legacy_height */ \ + IA_CSS_DEFAULT_SDIS_INFO, /* dis */ \ + { 0, 0},/* dvs_envelope_info */ \ + false, /* online */ \ + 0, /* uds_xc */ \ + 0, /* uds_yc */ \ + 0, /* left_padding */ \ + DEFAULT_BINARY_METRICS, /* metrics */ \ + IA_CSS_DEFAULT_ISP_MEM_PARAMS, /* mem_params */ \ + IA_CSS_DEFAULT_ISP_CSS_PARAMS, /* css_params */ \ +} + +#else + +#define IA_CSS_BINARY_DEFAULT_SETTINGS \ +{ \ + NULL, \ + IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY, \ + IA_CSS_BINARY_DEFAULT_FRAME_INFO, \ + IA_CSS_BINARY_DEFAULT_FRAME_INFO, \ + {IA_CSS_BINARY_DEFAULT_FRAME_INFO}, \ + { 0, 0},/* effective_in_frame_res */ \ + IA_CSS_BINARY_DEFAULT_FRAME_INFO, \ + 0, /* input_buf_vectors */ \ + 0, /* deci_factor_log2 */ \ + 0, /* vf_downscale_log2 */ \ + 0, /* s3atbl_width */ \ + 0, /* s3atbl_height */ \ + 0, /* s3atbl_isp_width */ \ + 0, /* s3atbl_isp_height */ \ + 0, /* morph_tbl_width */ \ + 0, /* morph_tbl_aligned_width */ \ + 0, /* morph_tbl_height */ \ + 0, /* sctbl_width_per_color */ \ + 0, /* sctbl_aligned_width_per_color */ \ + 0, /* sctbl_height */ \ + IA_CSS_DEFAULT_SDIS_INFO, /* dis */ \ + { 0, 0},/* dvs_envelope_info */ \ + false, /* online */ \ + 0, /* uds_xc */ \ + 0, /* uds_yc */ \ + 0, /* left_padding */ \ + DEFAULT_BINARY_METRICS, /* metrics */ \ + IA_CSS_DEFAULT_ISP_MEM_PARAMS, /* mem_params */ \ + IA_CSS_DEFAULT_ISP_CSS_PARAMS, /* css_params */ \ +} + +#endif + +enum ia_css_err +ia_css_binary_init_infos(void); + +enum ia_css_err +ia_css_binary_uninit(void); + +enum ia_css_err +ia_css_binary_fill_info(const struct ia_css_binary_xinfo *xinfo, + bool online, + bool two_ppc, + enum ia_css_stream_format stream_format, + const struct ia_css_frame_info *in_info, + const struct ia_css_frame_info *bds_out_info, + const struct ia_css_frame_info *out_info[], + const struct ia_css_frame_info *vf_info, + struct ia_css_binary *binary, + struct ia_css_resolution *dvs_env, + int stream_config_left_padding, + bool accelerator); + +enum ia_css_err +ia_css_binary_find(struct ia_css_binary_descr *descr, + struct ia_css_binary *binary); + +/** @brief Get the shading information of the specified shading correction type. + * + * @param[in] binary: The isp binary which has the shading correction. + * @param[in] type: The shading correction type. + * @param[in] required_bds_factor: The bayer downscaling factor required in the pipe. + * @param[in] stream_config: The stream configuration. +#ifndef ISP2401 + * @param[out] info: The shading information. +#else + * @param[out] shading_info: The shading information. + * The shading information necessary as API is stored in the shading_info. +#endif + * The driver needs to get this information to generate +#ifndef ISP2401 + * the shading table directly required in the isp. +#else + * the shading table directly required from ISP. + * @param[out] pipe_config: The pipe configuration. + * The shading information related to ISP (but, not necessary as API) is stored in the pipe_config. +#endif + * @return IA_CSS_SUCCESS or error code upon error. + * + */ +enum ia_css_err +ia_css_binary_get_shading_info(const struct ia_css_binary *binary, + enum ia_css_shading_correction_type type, + unsigned int required_bds_factor, + const struct ia_css_stream_config *stream_config, +#ifndef ISP2401 + struct ia_css_shading_info *info); +#else + struct ia_css_shading_info *shading_info, + struct ia_css_pipe_config *pipe_config); +#endif + +enum ia_css_err +ia_css_binary_3a_grid_info(const struct ia_css_binary *binary, + struct ia_css_grid_info *info, + struct ia_css_pipe *pipe); + +void +ia_css_binary_dvs_grid_info(const struct ia_css_binary *binary, + struct ia_css_grid_info *info, + struct ia_css_pipe *pipe); + +void +ia_css_binary_dvs_stat_grid_info( + const struct ia_css_binary *binary, + struct ia_css_grid_info *info, + struct ia_css_pipe *pipe); + +unsigned +ia_css_binary_max_vf_width(void); + +void +ia_css_binary_destroy_isp_parameters(struct ia_css_binary *binary); + +void +ia_css_binary_get_isp_binaries(struct ia_css_binary_xinfo **binaries, + uint32_t *num_isp_binaries); + +#endif /* _IA_CSS_BINARY_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/binary/src/binary.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/binary/src/binary.c new file mode 100644 index 0000000000000000000000000000000000000000..34ca534f7b4acddcd61b6bc15bc9f1903236ff25 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/binary/src/binary.c @@ -0,0 +1,1873 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include /* HR_GDC_N */ +#include "isp.h" /* ISP_VEC_NELEMS */ + +#include "ia_css_binary.h" +#include "ia_css_debug.h" +#include "ia_css_util.h" +#include "ia_css_isp_param.h" +#include "sh_css_internal.h" +#include "sh_css_sp.h" +#include "sh_css_firmware.h" +#include "sh_css_defs.h" +#include "sh_css_legacy.h" + +#include "vf/vf_1.0/ia_css_vf.host.h" +#ifdef ISP2401 +#include "sc/sc_1.0/ia_css_sc.host.h" +#endif +#include "sdis/sdis_1.0/ia_css_sdis.host.h" +#ifdef ISP2401 +#include "fixedbds/fixedbds_1.0/ia_css_fixedbds_param.h" /* FRAC_ACC */ +#endif + +#include "camera/pipe/interface/ia_css_pipe_binarydesc.h" +#if defined(HAS_RES_MGR) +#include +#include +#endif + +#include "memory_access.h" + +#include "assert_support.h" + +#define IMPLIES(a, b) (!(a) || (b)) /* A => B */ + +static struct ia_css_binary_xinfo *all_binaries; /* ISP binaries only (no SP) */ +static struct ia_css_binary_xinfo + *binary_infos[IA_CSS_BINARY_NUM_MODES] = { NULL, }; + +static void +ia_css_binary_dvs_env(const struct ia_css_binary_info *info, + const struct ia_css_resolution *dvs_env, + struct ia_css_resolution *binary_dvs_env) +{ + if (info->enable.dvs_envelope) { + assert(dvs_env != NULL); + binary_dvs_env->width = max(dvs_env->width, SH_CSS_MIN_DVS_ENVELOPE); + binary_dvs_env->height = max(dvs_env->height, SH_CSS_MIN_DVS_ENVELOPE); + } +} + +static void +ia_css_binary_internal_res(const struct ia_css_frame_info *in_info, + const struct ia_css_frame_info *bds_out_info, + const struct ia_css_frame_info *out_info, + const struct ia_css_resolution *dvs_env, + const struct ia_css_binary_info *info, + struct ia_css_resolution *internal_res) +{ + unsigned int isp_tmp_internal_width = 0, + isp_tmp_internal_height = 0; + bool binary_supports_yuv_ds = info->enable.ds & 2; + struct ia_css_resolution binary_dvs_env; + + binary_dvs_env.width = 0; + binary_dvs_env.height = 0; + ia_css_binary_dvs_env(info, dvs_env, &binary_dvs_env); + + if (binary_supports_yuv_ds) { + if (in_info != NULL) { + isp_tmp_internal_width = in_info->res.width + + info->pipeline.left_cropping + binary_dvs_env.width; + isp_tmp_internal_height = in_info->res.height + + info->pipeline.top_cropping + binary_dvs_env.height; + } + } else if ((bds_out_info != NULL) && (out_info != NULL) && + /* TODO: hack to make video_us case work. this should be reverted after + a nice solution in ISP */ + (bds_out_info->res.width >= out_info->res.width)) { + isp_tmp_internal_width = bds_out_info->padded_width; + isp_tmp_internal_height = bds_out_info->res.height; + } else { + if (out_info != NULL) { + isp_tmp_internal_width = out_info->padded_width; + isp_tmp_internal_height = out_info->res.height; + } + } + + /* We first calculate the resolutions used by the ISP. After that, + * we use those resolutions to compute sizes for tables etc. */ + internal_res->width = __ISP_INTERNAL_WIDTH(isp_tmp_internal_width, + (int)binary_dvs_env.width, + info->pipeline.left_cropping, info->pipeline.mode, + info->pipeline.c_subsampling, + info->output.num_chunks, info->pipeline.pipelining); + internal_res->height = __ISP_INTERNAL_HEIGHT(isp_tmp_internal_height, + info->pipeline.top_cropping, + binary_dvs_env.height); +#if defined(HAS_RES_MGR) + internal_res->height = (bds_out_info == NULL) ? internal_res->height : bds_out_info->res.height; + internal_res->width = (bds_out_info == NULL) ? internal_res->width: bds_out_info->res.width; +#endif +} + +#ifndef ISP2401 +/* Computation results of the origin coordinate of bayer on the shading table. */ +struct sh_css_shading_table_bayer_origin_compute_results { + uint32_t bayer_scale_hor_ratio_in; /* Horizontal ratio (in) of bayer scaling. */ + uint32_t bayer_scale_hor_ratio_out; /* Horizontal ratio (out) of bayer scaling. */ + uint32_t bayer_scale_ver_ratio_in; /* Vertical ratio (in) of bayer scaling. */ + uint32_t bayer_scale_ver_ratio_out; /* Vertical ratio (out) of bayer scaling. */ + uint32_t sc_bayer_origin_x_bqs_on_shading_table; /* X coordinate (in bqs) of bayer origin on shading table. */ + uint32_t sc_bayer_origin_y_bqs_on_shading_table; /* Y coordinate (in bqs) of bayer origin on shading table. */ +#else +/* Requirements for the shading correction. */ +struct sh_css_binary_sc_requirements { + /* Bayer scaling factor, for the scaling which is applied before shading correction. */ + uint32_t bayer_scale_hor_ratio_in; /* Horizontal ratio (in) of scaling applied BEFORE shading correction. */ + uint32_t bayer_scale_hor_ratio_out; /* Horizontal ratio (out) of scaling applied BEFORE shading correction. */ + uint32_t bayer_scale_ver_ratio_in; /* Vertical ratio (in) of scaling applied BEFORE shading correction. */ + uint32_t bayer_scale_ver_ratio_out; /* Vertical ratio (out) of scaling applied BEFORE shading correction. */ + + /* ISP internal frame is composed of the real sensor data and the padding data. */ + uint32_t sensor_data_origin_x_bqs_on_internal; /* X origin (in bqs) of sensor data on internal frame + at shading correction. */ + uint32_t sensor_data_origin_y_bqs_on_internal; /* Y origin (in bqs) of sensor data on internal frame + at shading correction. */ +#endif +}; + +/* Get the requirements for the shading correction. */ +static enum ia_css_err +#ifndef ISP2401 +ia_css_binary_compute_shading_table_bayer_origin( + const struct ia_css_binary *binary, /* [in] */ + unsigned int required_bds_factor, /* [in] */ + const struct ia_css_stream_config *stream_config, /* [in] */ + struct sh_css_shading_table_bayer_origin_compute_results *res) /* [out] */ +#else +sh_css_binary_get_sc_requirements( + const struct ia_css_binary *binary, /* [in] */ + unsigned int required_bds_factor, /* [in] */ + const struct ia_css_stream_config *stream_config, /* [in] */ + struct sh_css_binary_sc_requirements *scr) /* [out] */ +#endif +{ + enum ia_css_err err; + +#ifndef ISP2401 + /* Numerator and denominator of the fixed bayer downscaling factor. + (numerator >= denominator) */ +#else + /* Numerator and denominator of the fixed bayer downscaling factor. (numerator >= denominator) */ +#endif + unsigned int bds_num, bds_den; + +#ifndef ISP2401 + /* Horizontal/Vertical ratio of bayer scaling + between input area and output area. */ + unsigned int bs_hor_ratio_in; + unsigned int bs_hor_ratio_out; + unsigned int bs_ver_ratio_in; + unsigned int bs_ver_ratio_out; +#else + /* Horizontal/Vertical ratio of bayer scaling between input area and output area. */ + unsigned int bs_hor_ratio_in, bs_hor_ratio_out, bs_ver_ratio_in, bs_ver_ratio_out; +#endif + + /* Left padding set by InputFormatter. */ +#ifndef ISP2401 + unsigned int left_padding_bqs; /* in bqs */ +#else + unsigned int left_padding_bqs; +#endif + +#ifndef ISP2401 + /* Flag for the NEED_BDS_FACTOR_2_00 macro defined in isp kernels. */ + unsigned int need_bds_factor_2_00; + + /* Left padding adjusted inside the isp. */ + unsigned int left_padding_adjusted_bqs; /* in bqs */ + + /* Bad pixels caused by filters. + NxN-filter (before/after bayer scaling) moves the image position + to right/bottom directions by a few pixels. + It causes bad pixels at left/top sides, + and effective bayer size decreases. */ + unsigned int bad_bqs_on_left_before_bs; /* in bqs */ + unsigned int bad_bqs_on_left_after_bs; /* in bqs */ + unsigned int bad_bqs_on_top_before_bs; /* in bqs */ + unsigned int bad_bqs_on_top_after_bs; /* in bqs */ + + /* Get the numerator and denominator of bayer downscaling factor. */ + err = sh_css_bds_factor_get_numerator_denominator + (required_bds_factor, &bds_num, &bds_den); + if (err != IA_CSS_SUCCESS) +#else + /* Flags corresponding to NEED_BDS_FACTOR_2_00/NEED_BDS_FACTOR_1_50/NEED_BDS_FACTOR_1_25 macros + * defined in isp kernels. */ + unsigned int need_bds_factor_2_00, need_bds_factor_1_50, need_bds_factor_1_25; + + /* Left padding adjusted inside the isp kernels. */ + unsigned int left_padding_adjusted_bqs; + + /* Top padding padded inside the isp kernel for bayer downscaling binaries. */ + unsigned int top_padding_bqs; + + /* Bayer downscaling factor 1.0 by fixed-point. */ + int bds_frac_acc = FRAC_ACC; /* FRAC_ACC is defined in ia_css_fixedbds_param.h. */ + + /* Right/Down shift amount caused by filters applied BEFORE shading corrertion. */ + unsigned int right_shift_bqs_before_bs; /* right shift before bayer scaling */ + unsigned int right_shift_bqs_after_bs; /* right shift after bayer scaling */ + unsigned int down_shift_bqs_before_bs; /* down shift before bayer scaling */ + unsigned int down_shift_bqs_after_bs; /* down shift after bayer scaling */ + + /* Origin of the real sensor data area on the internal frame at shading correction. */ + unsigned int sensor_data_origin_x_bqs_on_internal; + unsigned int sensor_data_origin_y_bqs_on_internal; + + IA_CSS_ENTER_PRIVATE("binary=%p, required_bds_factor=%d, stream_config=%p", + binary, required_bds_factor, stream_config); + + /* Get the numerator and denominator of the required bayer downscaling factor. */ + err = sh_css_bds_factor_get_numerator_denominator(required_bds_factor, &bds_num, &bds_den); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); +#endif + return err; +#ifdef ISP2401 + } +#endif + +#ifndef ISP2401 + /* Set the horizontal/vertical ratio of bayer scaling + between input area and output area. */ +#else + IA_CSS_LOG("bds_num=%d, bds_den=%d", bds_num, bds_den); + + /* Set the horizontal/vertical ratio of bayer scaling between input area and output area. */ +#endif + bs_hor_ratio_in = bds_num; + bs_hor_ratio_out = bds_den; + bs_ver_ratio_in = bds_num; + bs_ver_ratio_out = bds_den; + +#ifndef ISP2401 + /* Set the left padding set by InputFormatter. (ifmtr.c) */ +#else + /* Set the left padding set by InputFormatter. (ia_css_ifmtr_configure() in ifmtr.c) */ +#endif + if (stream_config->left_padding == -1) + left_padding_bqs = _ISP_BQS(binary->left_padding); + else +#ifndef ISP2401 + left_padding_bqs = (unsigned int)((int)ISP_VEC_NELEMS + - _ISP_BQS(stream_config->left_padding)); +#else + left_padding_bqs = (unsigned int)((int)ISP_VEC_NELEMS - _ISP_BQS(stream_config->left_padding)); +#endif + +#ifndef ISP2401 + /* Set the left padding adjusted inside the isp. + When bds_factor 2.00 is needed, some padding is added to left_padding + inside the isp, before bayer downscaling. (raw.isp.c) + (Hopefully, left_crop/left_padding/top_crop should be defined in css + appropriately, depending on bds_factor.) + */ +#else + IA_CSS_LOG("stream.left_padding=%d, binary.left_padding=%d, left_padding_bqs=%d", + stream_config->left_padding, binary->left_padding, left_padding_bqs); + + /* Set the left padding adjusted inside the isp kernels. + * When the bds_factor isn't 1.00, the left padding size is adjusted inside the isp, + * before bayer downscaling. (scaled_hor_plane_index(), raw_compute_hphase() in raw.isp.c) + */ +#endif + need_bds_factor_2_00 = ((binary->info->sp.bds.supported_bds_factors & + (PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_2_00) | + PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_2_50) | + PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_3_00) | + PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_4_00) | + PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_4_50) | + PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_5_00) | + PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_6_00) | + PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_8_00))) != 0); + +#ifndef ISP2401 + if (need_bds_factor_2_00 && binary->info->sp.pipeline.left_cropping > 0) + left_padding_adjusted_bqs = left_padding_bqs + ISP_VEC_NELEMS; + else +#else + need_bds_factor_1_50 = ((binary->info->sp.bds.supported_bds_factors & + (PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_1_50) | + PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_2_25) | + PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_3_00) | + PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_4_50) | + PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_6_00))) != 0); + + need_bds_factor_1_25 = ((binary->info->sp.bds.supported_bds_factors & + (PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_1_25) | + PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_2_50) | + PACK_BDS_FACTOR(SH_CSS_BDS_FACTOR_5_00))) != 0); + + if (binary->info->sp.pipeline.left_cropping > 0 && + (need_bds_factor_2_00 || need_bds_factor_1_50 || need_bds_factor_1_25)) { + /* + * downscale 2.0 -> first_vec_adjusted_bqs = 128 + * downscale 1.5 -> first_vec_adjusted_bqs = 96 + * downscale 1.25 -> first_vec_adjusted_bqs = 80 + */ + unsigned int first_vec_adjusted_bqs + = ISP_VEC_NELEMS * bs_hor_ratio_in / bs_hor_ratio_out; + left_padding_adjusted_bqs = first_vec_adjusted_bqs + - _ISP_BQS(binary->info->sp.pipeline.left_cropping); + } else +#endif + left_padding_adjusted_bqs = left_padding_bqs; + +#ifndef ISP2401 + /* Currently, the bad pixel caused by filters before bayer scaling + is NOT considered, because the bad pixel is subtle. + When some large filter is used in the future, + we need to consider the bad pixel. + + Currently, when bds_factor isn't 1.00, 3x3 anti-alias filter is applied + to each color plane(Gr/R/B/Gb) before bayer downscaling. + This filter moves each color plane to right/bottom directions + by 1 pixel at the most, depending on downscaling factor. + */ + bad_bqs_on_left_before_bs = 0; + bad_bqs_on_top_before_bs = 0; +#else + IA_CSS_LOG("supported_bds_factors=%d, need_bds_factor:2_00=%d, 1_50=%d, 1_25=%d", + binary->info->sp.bds.supported_bds_factors, + need_bds_factor_2_00, need_bds_factor_1_50, need_bds_factor_1_25); + IA_CSS_LOG("left_cropping=%d, left_padding_adjusted_bqs=%d", + binary->info->sp.pipeline.left_cropping, left_padding_adjusted_bqs); + + /* Set the top padding padded inside the isp kernel for bayer downscaling binaries. + * When the bds_factor isn't 1.00, the top padding is padded inside the isp + * before bayer downscaling, because the top cropping size (input margin) is not enough. + * (calculate_input_line(), raw_compute_vphase(), dma_read_raw() in raw.isp.c) + * NOTE: In dma_read_raw(), the factor passed to raw_compute_vphase() is got by get_bds_factor_for_dma_read(). + * This factor is BDS_FPVAL_100/BDS_FPVAL_125/BDS_FPVAL_150/BDS_FPVAL_200. + */ + top_padding_bqs = 0; + if (binary->info->sp.pipeline.top_cropping > 0 && + (required_bds_factor == SH_CSS_BDS_FACTOR_1_25 || + required_bds_factor == SH_CSS_BDS_FACTOR_1_50 || + required_bds_factor == SH_CSS_BDS_FACTOR_2_00)) { + /* Calculation from calculate_input_line() and raw_compute_vphase() in raw.isp.c. */ + int top_cropping_bqs = _ISP_BQS(binary->info->sp.pipeline.top_cropping); + /* top cropping (in bqs) */ + int factor = bds_num * bds_frac_acc / bds_den; /* downscaling factor by fixed-point */ + int top_padding_bqsxfrac_acc = (top_cropping_bqs * factor - top_cropping_bqs * bds_frac_acc) + + (2 * bds_frac_acc - factor); /* top padding by fixed-point (in bqs) */ + + top_padding_bqs = (unsigned int)((top_padding_bqsxfrac_acc + bds_frac_acc/2 - 1) / bds_frac_acc); + } + + IA_CSS_LOG("top_cropping=%d, top_padding_bqs=%d", binary->info->sp.pipeline.top_cropping, top_padding_bqs); + + /* Set the right/down shift amount caused by filters applied BEFORE bayer scaling, + * which scaling is applied BEFORE shading corrertion. + * + * When the bds_factor isn't 1.00, 3x3 anti-alias filter is applied to each color plane(Gr/R/B/Gb) + * before bayer downscaling. + * This filter shifts each color plane (Gr/R/B/Gb) to right/down directions by 1 pixel. + */ + right_shift_bqs_before_bs = 0; + down_shift_bqs_before_bs = 0; +#endif + +#ifndef ISP2401 + /* Currently, the bad pixel caused by filters after bayer scaling + is NOT considered, because the bad pixel is subtle. + When some large filter is used in the future, + we need to consider the bad pixel. + + Currently, when DPC&BNR is processed between bayer scaling and + shading correction, DPC&BNR moves each color plane to + right/bottom directions by 1 pixel. + */ + bad_bqs_on_left_after_bs = 0; + bad_bqs_on_top_after_bs = 0; +#else + if (need_bds_factor_2_00 || need_bds_factor_1_50 || need_bds_factor_1_25) { + right_shift_bqs_before_bs = 1; + down_shift_bqs_before_bs = 1; + } + + IA_CSS_LOG("right_shift_bqs_before_bs=%d, down_shift_bqs_before_bs=%d", + right_shift_bqs_before_bs, down_shift_bqs_before_bs); + + /* Set the right/down shift amount caused by filters applied AFTER bayer scaling, + * which scaling is applied BEFORE shading corrertion. + * + * When DPC&BNR is processed between bayer scaling and shading correction, + * DPC&BNR moves each color plane (Gr/R/B/Gb) to right/down directions by 1 pixel. + */ + right_shift_bqs_after_bs = 0; + down_shift_bqs_after_bs = 0; +#endif + +#ifndef ISP2401 + /* Calculate the origin of bayer (real sensor data area) + located on the shading table during the shading correction. */ + res->sc_bayer_origin_x_bqs_on_shading_table + = ((left_padding_adjusted_bqs + bad_bqs_on_left_before_bs) + * bs_hor_ratio_out + bs_hor_ratio_in/2) / bs_hor_ratio_in + + bad_bqs_on_left_after_bs; + /* "+ bs_hor_ratio_in/2": rounding for division by bs_hor_ratio_in */ + res->sc_bayer_origin_y_bqs_on_shading_table + = (bad_bqs_on_top_before_bs + * bs_ver_ratio_out + bs_ver_ratio_in/2) / bs_ver_ratio_in + + bad_bqs_on_top_after_bs; + /* "+ bs_ver_ratio_in/2": rounding for division by bs_ver_ratio_in */ + + res->bayer_scale_hor_ratio_in = (uint32_t)bs_hor_ratio_in; + res->bayer_scale_hor_ratio_out = (uint32_t)bs_hor_ratio_out; + res->bayer_scale_ver_ratio_in = (uint32_t)bs_ver_ratio_in; + res->bayer_scale_ver_ratio_out = (uint32_t)bs_ver_ratio_out; +#else + if (binary->info->mem_offsets.offsets.param->dmem.dp.size != 0) { /* if DPC&BNR is enabled in the binary */ + right_shift_bqs_after_bs = 1; + down_shift_bqs_after_bs = 1; + } + + IA_CSS_LOG("right_shift_bqs_after_bs=%d, down_shift_bqs_after_bs=%d", + right_shift_bqs_after_bs, down_shift_bqs_after_bs); + + /* Set the origin of the sensor data area on the internal frame at shading correction. */ + { + unsigned int bs_frac = bds_frac_acc; /* scaling factor 1.0 in fixed point */ + unsigned int bs_out, bs_in; /* scaling ratio in fixed point */ + + bs_out = bs_hor_ratio_out * bs_frac; + bs_in = bs_hor_ratio_in * bs_frac; + sensor_data_origin_x_bqs_on_internal + = ((left_padding_adjusted_bqs + right_shift_bqs_before_bs) * bs_out + bs_in/2) / bs_in + + right_shift_bqs_after_bs; /* "+ bs_in/2": rounding */ + + bs_out = bs_ver_ratio_out * bs_frac; + bs_in = bs_ver_ratio_in * bs_frac; + sensor_data_origin_y_bqs_on_internal + = ((top_padding_bqs + down_shift_bqs_before_bs) * bs_out + bs_in/2) / bs_in + + down_shift_bqs_after_bs; /* "+ bs_in/2": rounding */ + } + + scr->bayer_scale_hor_ratio_in = (uint32_t)bs_hor_ratio_in; + scr->bayer_scale_hor_ratio_out = (uint32_t)bs_hor_ratio_out; + scr->bayer_scale_ver_ratio_in = (uint32_t)bs_ver_ratio_in; + scr->bayer_scale_ver_ratio_out = (uint32_t)bs_ver_ratio_out; + scr->sensor_data_origin_x_bqs_on_internal = (uint32_t)sensor_data_origin_x_bqs_on_internal; + scr->sensor_data_origin_y_bqs_on_internal = (uint32_t)sensor_data_origin_y_bqs_on_internal; + + IA_CSS_LOG("sc_requirements: %d, %d, %d, %d, %d, %d", + scr->bayer_scale_hor_ratio_in, scr->bayer_scale_hor_ratio_out, + scr->bayer_scale_ver_ratio_in, scr->bayer_scale_ver_ratio_out, + scr->sensor_data_origin_x_bqs_on_internal, scr->sensor_data_origin_y_bqs_on_internal); +#endif + +#ifdef ISP2401 + IA_CSS_LEAVE_ERR_PRIVATE(err); +#endif + return err; +} + +/* Get the shading information of Shading Correction Type 1. */ +static enum ia_css_err +ia_css_binary_get_shading_info_type_1(const struct ia_css_binary *binary, /* [in] */ + unsigned int required_bds_factor, /* [in] */ + const struct ia_css_stream_config *stream_config, /* [in] */ +#ifndef ISP2401 + struct ia_css_shading_info *info) /* [out] */ +#else + struct ia_css_shading_info *shading_info, /* [out] */ + struct ia_css_pipe_config *pipe_config) /* [out] */ +#endif +{ + enum ia_css_err err; +#ifndef ISP2401 + struct sh_css_shading_table_bayer_origin_compute_results res; +#else + struct sh_css_binary_sc_requirements scr; + struct ia_css_shading_info default_shading_info_type_1 = DEFAULT_SHADING_INFO_TYPE_1; +#endif + +#ifndef ISP2401 + assert(binary != NULL); + assert(info != NULL); +#else + uint32_t in_width_bqs, in_height_bqs, internal_width_bqs, internal_height_bqs; + uint32_t num_hor_grids, num_ver_grids, bqs_per_grid_cell, tbl_width_bqs, tbl_height_bqs; + uint32_t sensor_org_x_bqs_on_internal, sensor_org_y_bqs_on_internal, sensor_width_bqs, sensor_height_bqs; + uint32_t sensor_center_x_bqs_on_internal, sensor_center_y_bqs_on_internal; + uint32_t left, right, upper, lower; + uint32_t adjust_left, adjust_right, adjust_upper, adjust_lower, adjust_width_bqs, adjust_height_bqs; + uint32_t internal_org_x_bqs_on_tbl, internal_org_y_bqs_on_tbl; + uint32_t sensor_org_x_bqs_on_tbl, sensor_org_y_bqs_on_tbl; +#endif + +#ifndef ISP2401 + info->type = IA_CSS_SHADING_CORRECTION_TYPE_1; +#else + assert(binary != NULL); + assert(stream_config != NULL); + assert(shading_info != NULL); + assert(pipe_config != NULL); +#endif + +#ifndef ISP2401 + info->info.type_1.enable = binary->info->sp.enable.sc; + info->info.type_1.num_hor_grids = binary->sctbl_width_per_color; + info->info.type_1.num_ver_grids = binary->sctbl_height; + info->info.type_1.bqs_per_grid_cell = (1 << binary->deci_factor_log2); +#else + IA_CSS_ENTER_PRIVATE("binary=%p, required_bds_factor=%d, stream_config=%p", + binary, required_bds_factor, stream_config); +#endif + + /* Initialize by default values. */ +#ifndef ISP2401 + info->info.type_1.bayer_scale_hor_ratio_in = 1; + info->info.type_1.bayer_scale_hor_ratio_out = 1; + info->info.type_1.bayer_scale_ver_ratio_in = 1; + info->info.type_1.bayer_scale_ver_ratio_out = 1; + info->info.type_1.sc_bayer_origin_x_bqs_on_shading_table = 0; + info->info.type_1.sc_bayer_origin_y_bqs_on_shading_table = 0; + + err = ia_css_binary_compute_shading_table_bayer_origin( + binary, + required_bds_factor, + stream_config, + &res); + if (err != IA_CSS_SUCCESS) +#else + *shading_info = default_shading_info_type_1; + + err = sh_css_binary_get_sc_requirements(binary, required_bds_factor, stream_config, &scr); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); +#endif + return err; +#ifdef ISP2401 + } + + IA_CSS_LOG("binary: id=%d, sctbl=%dx%d, deci=%d", + binary->info->sp.id, binary->sctbl_width_per_color, binary->sctbl_height, binary->deci_factor_log2); + IA_CSS_LOG("binary: in=%dx%d, in_padded_w=%d, int=%dx%d, int_padded_w=%d, out=%dx%d, out_padded_w=%d", + binary->in_frame_info.res.width, binary->in_frame_info.res.height, binary->in_frame_info.padded_width, + binary->internal_frame_info.res.width, binary->internal_frame_info.res.height, + binary->internal_frame_info.padded_width, + binary->out_frame_info[0].res.width, binary->out_frame_info[0].res.height, + binary->out_frame_info[0].padded_width); + + /* Set the input size from sensor, which includes left/top crop size. */ + in_width_bqs = _ISP_BQS(binary->in_frame_info.res.width); + in_height_bqs = _ISP_BQS(binary->in_frame_info.res.height); + + /* Frame size internally used in ISP, including sensor data and padding. + * This is the frame size, to which the shading correction is applied. + */ + internal_width_bqs = _ISP_BQS(binary->internal_frame_info.res.width); + internal_height_bqs = _ISP_BQS(binary->internal_frame_info.res.height); + + /* Shading table. */ + num_hor_grids = binary->sctbl_width_per_color; + num_ver_grids = binary->sctbl_height; + bqs_per_grid_cell = (1 << binary->deci_factor_log2); + tbl_width_bqs = (num_hor_grids - 1) * bqs_per_grid_cell; + tbl_height_bqs = (num_ver_grids - 1) * bqs_per_grid_cell; +#endif + +#ifndef ISP2401 + info->info.type_1.bayer_scale_hor_ratio_in = res.bayer_scale_hor_ratio_in; + info->info.type_1.bayer_scale_hor_ratio_out = res.bayer_scale_hor_ratio_out; + info->info.type_1.bayer_scale_ver_ratio_in = res.bayer_scale_ver_ratio_in; + info->info.type_1.bayer_scale_ver_ratio_out = res.bayer_scale_ver_ratio_out; + info->info.type_1.sc_bayer_origin_x_bqs_on_shading_table = res.sc_bayer_origin_x_bqs_on_shading_table; + info->info.type_1.sc_bayer_origin_y_bqs_on_shading_table = res.sc_bayer_origin_y_bqs_on_shading_table; +#else + IA_CSS_LOG("tbl_width_bqs=%d, tbl_height_bqs=%d", tbl_width_bqs, tbl_height_bqs); +#endif + +#ifdef ISP2401 + /* Real sensor data area on the internal frame at shading correction. + * Filters and scaling are applied to the internal frame before shading correction, depending on the binary. + */ + sensor_org_x_bqs_on_internal = scr.sensor_data_origin_x_bqs_on_internal; + sensor_org_y_bqs_on_internal = scr.sensor_data_origin_y_bqs_on_internal; + { + unsigned int bs_frac = 8; /* scaling factor 1.0 in fixed point (8 == FRAC_ACC macro in ISP) */ + unsigned int bs_out, bs_in; /* scaling ratio in fixed point */ + + bs_out = scr.bayer_scale_hor_ratio_out * bs_frac; + bs_in = scr.bayer_scale_hor_ratio_in * bs_frac; + sensor_width_bqs = (in_width_bqs * bs_out + bs_in/2) / bs_in; /* "+ bs_in/2": rounding */ + + bs_out = scr.bayer_scale_ver_ratio_out * bs_frac; + bs_in = scr.bayer_scale_ver_ratio_in * bs_frac; + sensor_height_bqs = (in_height_bqs * bs_out + bs_in/2) / bs_in; /* "+ bs_in/2": rounding */ + } + + /* Center of the sensor data on the internal frame at shading correction. */ + sensor_center_x_bqs_on_internal = sensor_org_x_bqs_on_internal + sensor_width_bqs / 2; + sensor_center_y_bqs_on_internal = sensor_org_y_bqs_on_internal + sensor_height_bqs / 2; + + /* Size of left/right/upper/lower sides of the sensor center on the internal frame. */ + left = sensor_center_x_bqs_on_internal; + right = internal_width_bqs - sensor_center_x_bqs_on_internal; + upper = sensor_center_y_bqs_on_internal; + lower = internal_height_bqs - sensor_center_y_bqs_on_internal; + + /* Align the size of left/right/upper/lower sides to a multiple of the grid cell size. */ + adjust_left = CEIL_MUL(left, bqs_per_grid_cell); + adjust_right = CEIL_MUL(right, bqs_per_grid_cell); + adjust_upper = CEIL_MUL(upper, bqs_per_grid_cell); + adjust_lower = CEIL_MUL(lower, bqs_per_grid_cell); + + /* Shading table should cover the adjusted frame size. */ + adjust_width_bqs = adjust_left + adjust_right; + adjust_height_bqs = adjust_upper + adjust_lower; + + IA_CSS_LOG("adjust_width_bqs=%d, adjust_height_bqs=%d", adjust_width_bqs, adjust_height_bqs); + + if (adjust_width_bqs > tbl_width_bqs || adjust_height_bqs > tbl_height_bqs) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INTERNAL_ERROR); + return IA_CSS_ERR_INTERNAL_ERROR; + } + + /* Origin of the internal frame on the shading table. */ + internal_org_x_bqs_on_tbl = adjust_left - left; + internal_org_y_bqs_on_tbl = adjust_upper - upper; + + /* Origin of the real sensor data area on the shading table. */ + sensor_org_x_bqs_on_tbl = internal_org_x_bqs_on_tbl + sensor_org_x_bqs_on_internal; + sensor_org_y_bqs_on_tbl = internal_org_y_bqs_on_tbl + sensor_org_y_bqs_on_internal; + + /* The shading information necessary as API is stored in the shading_info. */ + shading_info->info.type_1.num_hor_grids = num_hor_grids; + shading_info->info.type_1.num_ver_grids = num_ver_grids; + shading_info->info.type_1.bqs_per_grid_cell = bqs_per_grid_cell; + + shading_info->info.type_1.bayer_scale_hor_ratio_in = scr.bayer_scale_hor_ratio_in; + shading_info->info.type_1.bayer_scale_hor_ratio_out = scr.bayer_scale_hor_ratio_out; + shading_info->info.type_1.bayer_scale_ver_ratio_in = scr.bayer_scale_ver_ratio_in; + shading_info->info.type_1.bayer_scale_ver_ratio_out = scr.bayer_scale_ver_ratio_out; + + shading_info->info.type_1.isp_input_sensor_data_res_bqs.width = in_width_bqs; + shading_info->info.type_1.isp_input_sensor_data_res_bqs.height = in_height_bqs; + + shading_info->info.type_1.sensor_data_res_bqs.width = sensor_width_bqs; + shading_info->info.type_1.sensor_data_res_bqs.height = sensor_height_bqs; + + shading_info->info.type_1.sensor_data_origin_bqs_on_sctbl.x = (int32_t)sensor_org_x_bqs_on_tbl; + shading_info->info.type_1.sensor_data_origin_bqs_on_sctbl.y = (int32_t)sensor_org_y_bqs_on_tbl; + + /* The shading information related to ISP (but, not necessary as API) is stored in the pipe_config. */ + pipe_config->internal_frame_origin_bqs_on_sctbl.x = (int32_t)internal_org_x_bqs_on_tbl; + pipe_config->internal_frame_origin_bqs_on_sctbl.y = (int32_t)internal_org_y_bqs_on_tbl; + + IA_CSS_LOG("shading_info: grids=%dx%d, cell=%d, scale=%d,%d,%d,%d, input=%dx%d, data=%dx%d, origin=(%d,%d)", + shading_info->info.type_1.num_hor_grids, + shading_info->info.type_1.num_ver_grids, + shading_info->info.type_1.bqs_per_grid_cell, + shading_info->info.type_1.bayer_scale_hor_ratio_in, + shading_info->info.type_1.bayer_scale_hor_ratio_out, + shading_info->info.type_1.bayer_scale_ver_ratio_in, + shading_info->info.type_1.bayer_scale_ver_ratio_out, + shading_info->info.type_1.isp_input_sensor_data_res_bqs.width, + shading_info->info.type_1.isp_input_sensor_data_res_bqs.height, + shading_info->info.type_1.sensor_data_res_bqs.width, + shading_info->info.type_1.sensor_data_res_bqs.height, + shading_info->info.type_1.sensor_data_origin_bqs_on_sctbl.x, + shading_info->info.type_1.sensor_data_origin_bqs_on_sctbl.y); + + IA_CSS_LOG("pipe_config: origin=(%d,%d)", + pipe_config->internal_frame_origin_bqs_on_sctbl.x, + pipe_config->internal_frame_origin_bqs_on_sctbl.y); + + IA_CSS_LEAVE_ERR_PRIVATE(err); +#endif + return err; +} + +enum ia_css_err +ia_css_binary_get_shading_info(const struct ia_css_binary *binary, /* [in] */ + enum ia_css_shading_correction_type type, /* [in] */ + unsigned int required_bds_factor, /* [in] */ + const struct ia_css_stream_config *stream_config, /* [in] */ +#ifndef ISP2401 + struct ia_css_shading_info *info) /* [out] */ +#else + struct ia_css_shading_info *shading_info, /* [out] */ + struct ia_css_pipe_config *pipe_config) /* [out] */ +#endif +{ + enum ia_css_err err; + + assert(binary != NULL); +#ifndef ISP2401 + assert(info != NULL); +#else + assert(shading_info != NULL); + + IA_CSS_ENTER_PRIVATE("binary=%p, type=%d, required_bds_factor=%d, stream_config=%p", + binary, type, required_bds_factor, stream_config); +#endif + + if (type == IA_CSS_SHADING_CORRECTION_TYPE_1) +#ifndef ISP2401 + err = ia_css_binary_get_shading_info_type_1(binary, required_bds_factor, stream_config, info); +#else + err = ia_css_binary_get_shading_info_type_1(binary, required_bds_factor, stream_config, + shading_info, pipe_config); +#endif + + /* Other function calls can be added here when other shading correction types will be added in the future. */ + + else + err = IA_CSS_ERR_NOT_SUPPORTED; + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static void sh_css_binary_common_grid_info(const struct ia_css_binary *binary, + struct ia_css_grid_info *info) +{ + assert(binary != NULL); + assert(info != NULL); + + info->isp_in_width = binary->internal_frame_info.res.width; + info->isp_in_height = binary->internal_frame_info.res.height; + + info->vamem_type = IA_CSS_VAMEM_TYPE_2; +} + +void +ia_css_binary_dvs_grid_info(const struct ia_css_binary *binary, + struct ia_css_grid_info *info, + struct ia_css_pipe *pipe) +{ + struct ia_css_dvs_grid_info *dvs_info; + + (void)pipe; + assert(binary != NULL); + assert(info != NULL); + + dvs_info = &info->dvs_grid.dvs_grid_info; + + /* for DIS, we use a division instead of a ceil_div. If this is smaller + * than the 3a grid size, it indicates that the outer values are not + * valid for DIS. + */ + dvs_info->enable = binary->info->sp.enable.dis; + dvs_info->width = binary->dis.grid.dim.width; + dvs_info->height = binary->dis.grid.dim.height; + dvs_info->aligned_width = binary->dis.grid.pad.width; + dvs_info->aligned_height = binary->dis.grid.pad.height; + dvs_info->bqs_per_grid_cell = 1 << binary->dis.deci_factor_log2; + dvs_info->num_hor_coefs = binary->dis.coef.dim.width; + dvs_info->num_ver_coefs = binary->dis.coef.dim.height; + + sh_css_binary_common_grid_info(binary, info); +} + +void +ia_css_binary_dvs_stat_grid_info( + const struct ia_css_binary *binary, + struct ia_css_grid_info *info, + struct ia_css_pipe *pipe) +{ +#if defined(HAS_RES_MGR) + struct ia_css_dvs_stat_grid_info *dvs_stat_info; + unsigned int i; + + assert(binary != NULL); + assert(info != NULL); + dvs_stat_info = &info->dvs_grid.dvs_stat_grid_info; + + if (binary->info->sp.enable.dvs_stats) { + for (i = 0; i < IA_CSS_SKC_DVS_STAT_NUM_OF_LEVELS; i++) { + dvs_stat_info->grd_cfg[i].grd_start.enable = 1; + } + ia_css_dvs_stat_grid_calculate(pipe, dvs_stat_info); + } + else { + memset(dvs_stat_info, 0, sizeof(struct ia_css_dvs_stat_grid_info)); + } + +#endif + (void)pipe; + sh_css_binary_common_grid_info(binary, info); + return; +} + +enum ia_css_err +ia_css_binary_3a_grid_info(const struct ia_css_binary *binary, + struct ia_css_grid_info *info, + struct ia_css_pipe *pipe) +{ + struct ia_css_3a_grid_info *s3a_info; + enum ia_css_err err = IA_CSS_SUCCESS; + + IA_CSS_ENTER_PRIVATE("binary=%p, info=%p, pipe=%p", + binary, info, pipe); + + assert(binary != NULL); + assert(info != NULL); + s3a_info = &info->s3a_grid; + + + /* 3A statistics grid */ + s3a_info->enable = binary->info->sp.enable.s3a; + s3a_info->width = binary->s3atbl_width; + s3a_info->height = binary->s3atbl_height; + s3a_info->aligned_width = binary->s3atbl_isp_width; + s3a_info->aligned_height = binary->s3atbl_isp_height; + s3a_info->bqs_per_grid_cell = (1 << binary->deci_factor_log2); + s3a_info->deci_factor_log2 = binary->deci_factor_log2; + s3a_info->elem_bit_depth = SH_CSS_BAYER_BITS; + s3a_info->use_dmem = binary->info->sp.s3a.s3atbl_use_dmem; +#if defined(HAS_NO_HMEM) + s3a_info->has_histogram = 1; +#else + s3a_info->has_histogram = 0; +#endif + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static void +binary_init_pc_histogram(struct sh_css_pc_histogram *histo) +{ + assert(histo != NULL); + + histo->length = 0; + histo->run = NULL; + histo->stall = NULL; +} + +static void +binary_init_metrics(struct sh_css_binary_metrics *metrics, + const struct ia_css_binary_info *info) +{ + assert(metrics != NULL); + assert(info != NULL); + + metrics->mode = info->pipeline.mode; + metrics->id = info->id; + metrics->next = NULL; + binary_init_pc_histogram(&metrics->isp_histogram); + binary_init_pc_histogram(&metrics->sp_histogram); +} + +/* move to host part of output module */ +static bool +binary_supports_output_format(const struct ia_css_binary_xinfo *info, + enum ia_css_frame_format format) +{ + int i; + + assert(info != NULL); + + for (i = 0; i < info->num_output_formats; i++) { + if (info->output_formats[i] == format) + return true; + } + return false; +} + +#ifdef ISP2401 +static bool +binary_supports_input_format(const struct ia_css_binary_xinfo *info, + enum ia_css_stream_format format) +{ + + assert(info != NULL); + (void)format; + + return true; +} +#endif + +static bool +binary_supports_vf_format(const struct ia_css_binary_xinfo *info, + enum ia_css_frame_format format) +{ + int i; + + assert(info != NULL); + + for (i = 0; i < info->num_vf_formats; i++) { + if (info->vf_formats[i] == format) + return true; + } + return false; +} + +/* move to host part of bds module */ +static bool +supports_bds_factor(uint32_t supported_factors, + uint32_t bds_factor) +{ + return ((supported_factors & PACK_BDS_FACTOR(bds_factor)) != 0); +} + +static enum ia_css_err +binary_init_info(struct ia_css_binary_xinfo *info, unsigned int i, + bool *binary_found) +{ + const unsigned char *blob = sh_css_blob_info[i].blob; + unsigned size = sh_css_blob_info[i].header.blob.size; + + if ((info == NULL) || (binary_found == NULL)) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + *info = sh_css_blob_info[i].header.info.isp; + *binary_found = blob != NULL; + info->blob_index = i; + /* we don't have this binary, skip it */ + if (!size) + return IA_CSS_SUCCESS; + + info->xmem_addr = sh_css_load_blob(blob, size); + if (!info->xmem_addr) + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + return IA_CSS_SUCCESS; +} + +/* When binaries are put at the beginning, they will only + * be selected if no other primary matches. + */ +enum ia_css_err +ia_css_binary_init_infos(void) +{ + unsigned int i; + unsigned int num_of_isp_binaries = sh_css_num_binaries - NUM_OF_SPS - NUM_OF_BLS; + + if (num_of_isp_binaries == 0) + return IA_CSS_SUCCESS; + + all_binaries = sh_css_malloc(num_of_isp_binaries * + sizeof(*all_binaries)); + if (all_binaries == NULL) + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + + for (i = 0; i < num_of_isp_binaries; i++) { + enum ia_css_err ret; + struct ia_css_binary_xinfo *binary = &all_binaries[i]; + bool binary_found; + + ret = binary_init_info(binary, i, &binary_found); + if (ret != IA_CSS_SUCCESS) + return ret; + if (!binary_found) + continue; + /* Prepend new binary information */ + binary->next = binary_infos[binary->sp.pipeline.mode]; + binary_infos[binary->sp.pipeline.mode] = binary; + binary->blob = &sh_css_blob_info[i]; + binary->mem_offsets = sh_css_blob_info[i].mem_offsets; + } + return IA_CSS_SUCCESS; +} + +enum ia_css_err +ia_css_binary_uninit(void) +{ + unsigned int i; + struct ia_css_binary_xinfo *b; + + for (i = 0; i < IA_CSS_BINARY_NUM_MODES; i++) { + for (b = binary_infos[i]; b; b = b->next) { + if (b->xmem_addr) + mmgr_free(b->xmem_addr); + b->xmem_addr = mmgr_NULL; + } + binary_infos[i] = NULL; + } + sh_css_free(all_binaries); + return IA_CSS_SUCCESS; +} + +/** @brief Compute decimation factor for 3A statistics and shading correction. + * + * @param[in] width Frame width in pixels. + * @param[in] height Frame height in pixels. + * @return Log2 of decimation factor (= grid cell size) in bayer quads. + */ +static int +binary_grid_deci_factor_log2(int width, int height) +{ +/* 3A/Shading decimation factor spcification (at August 2008) + * ------------------------------------------------------------------ + * [Image Width (BQ)] [Decimation Factor (BQ)] [Resulting grid cells] +#ifndef ISP2401 + * 1280 ?c 32 40 ?c + * 640 ?c 1279 16 40 ?c 80 + * ?c 639 8 ?c 80 +#else + * from 1280 32 from 40 + * from 640 to 1279 16 from 40 to 80 + * to 639 8 to 80 +#endif + * ------------------------------------------------------------------ + */ +/* Maximum and minimum decimation factor by the specification */ +#define MAX_SPEC_DECI_FACT_LOG2 5 +#define MIN_SPEC_DECI_FACT_LOG2 3 +/* the smallest frame width in bayer quads when decimation factor (log2) is 5 or 4, by the specification */ +#define DECI_FACT_LOG2_5_SMALLEST_FRAME_WIDTH_BQ 1280 +#define DECI_FACT_LOG2_4_SMALLEST_FRAME_WIDTH_BQ 640 + + int smallest_factor; /* the smallest factor (log2) where the number of cells does not exceed the limitation */ + int spec_factor; /* the factor (log2) which satisfies the specification */ + + /* Currently supported maximum width and height are 5120(=80*64) and 3840(=60*64). */ + assert(ISP_BQ_GRID_WIDTH(width, MAX_SPEC_DECI_FACT_LOG2) <= SH_CSS_MAX_BQ_GRID_WIDTH); + assert(ISP_BQ_GRID_HEIGHT(height, MAX_SPEC_DECI_FACT_LOG2) <= SH_CSS_MAX_BQ_GRID_HEIGHT); + + /* Compute the smallest factor. */ + smallest_factor = MAX_SPEC_DECI_FACT_LOG2; + while (ISP_BQ_GRID_WIDTH(width, smallest_factor - 1) <= SH_CSS_MAX_BQ_GRID_WIDTH && + ISP_BQ_GRID_HEIGHT(height, smallest_factor - 1) <= SH_CSS_MAX_BQ_GRID_HEIGHT + && smallest_factor > MIN_SPEC_DECI_FACT_LOG2) + smallest_factor--; + + /* Get the factor by the specification. */ + if (_ISP_BQS(width) >= DECI_FACT_LOG2_5_SMALLEST_FRAME_WIDTH_BQ) + spec_factor = 5; + else if (_ISP_BQS(width) >= DECI_FACT_LOG2_4_SMALLEST_FRAME_WIDTH_BQ) + spec_factor = 4; + else + spec_factor = 3; + + /* If smallest_factor is smaller than or equal to spec_factor, choose spec_factor to follow the specification. + If smallest_factor is larger than spec_factor, choose smallest_factor. + + ex. width=2560, height=1920 + smallest_factor=4, spec_factor=5 + smallest_factor < spec_factor -> return spec_factor + + ex. width=300, height=3000 + smallest_factor=5, spec_factor=3 + smallest_factor > spec_factor -> return smallest_factor + */ + return max(smallest_factor, spec_factor); + +#undef MAX_SPEC_DECI_FACT_LOG2 +#undef MIN_SPEC_DECI_FACT_LOG2 +#undef DECI_FACT_LOG2_5_SMALLEST_FRAME_WIDTH_BQ +#undef DECI_FACT_LOG2_4_SMALLEST_FRAME_WIDTH_BQ +} + +static int +binary_in_frame_padded_width(int in_frame_width, + int isp_internal_width, + int dvs_env_width, + int stream_config_left_padding, + int left_cropping, + bool need_scaling) +{ + int rval; + int nr_of_left_paddings; /* number of paddings pixels on the left of an image line */ + +#if defined(USE_INPUT_SYSTEM_VERSION_2401) + /* the output image line of Input System 2401 does not have the left paddings */ + nr_of_left_paddings = 0; +#else + /* in other cases, the left padding pixels are always 128 */ + nr_of_left_paddings = 2*ISP_VEC_NELEMS; +#endif +#if defined(HAS_RES_MGR) + (void)dvs_env_width; +#endif + if (need_scaling) { + /* In SDV use-case, we need to match left-padding of + * primary and the video binary. */ + if (stream_config_left_padding != -1) { + /* Different than before, we do left&right padding. */ + rval = + CEIL_MUL(in_frame_width + nr_of_left_paddings, + 2*ISP_VEC_NELEMS); + } else { + /* Different than before, we do left&right padding. */ +#if !defined(HAS_RES_MGR) /* dvs env is included already */ + in_frame_width += dvs_env_width; +#endif + rval = + CEIL_MUL(in_frame_width + + (left_cropping ? nr_of_left_paddings : 0), + 2*ISP_VEC_NELEMS); + } + } else { + rval = isp_internal_width; + } + + return rval; +} + + +enum ia_css_err +ia_css_binary_fill_info(const struct ia_css_binary_xinfo *xinfo, + bool online, + bool two_ppc, + enum ia_css_stream_format stream_format, + const struct ia_css_frame_info *in_info, /* can be NULL */ + const struct ia_css_frame_info *bds_out_info, /* can be NULL */ + const struct ia_css_frame_info *out_info[], /* can be NULL */ + const struct ia_css_frame_info *vf_info, /* can be NULL */ + struct ia_css_binary *binary, + struct ia_css_resolution *dvs_env, + int stream_config_left_padding, + bool accelerator) +{ + const struct ia_css_binary_info *info = &xinfo->sp; + unsigned int dvs_env_width = 0, + dvs_env_height = 0, + vf_log_ds = 0, + s3a_log_deci = 0, + bits_per_pixel = 0, + /* Resolution at SC/3A/DIS kernel. */ + sc_3a_dis_width = 0, + /* Resolution at SC/3A/DIS kernel. */ + sc_3a_dis_padded_width = 0, + /* Resolution at SC/3A/DIS kernel. */ + sc_3a_dis_height = 0, + isp_internal_width = 0, + isp_internal_height = 0, + s3a_isp_width = 0; + + bool need_scaling = false; + struct ia_css_resolution binary_dvs_env, internal_res; + enum ia_css_err err; + unsigned int i; + const struct ia_css_frame_info *bin_out_info = NULL; + + assert(info != NULL); + assert(binary != NULL); + + binary->info = xinfo; + if (!accelerator) { + /* binary->css_params has been filled by accelerator itself. */ + err = ia_css_isp_param_allocate_isp_parameters( + &binary->mem_params, &binary->css_params, + &info->mem_initializers); + if (err != IA_CSS_SUCCESS) { + return err; + } + } + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + if (out_info[i] && (out_info[i]->res.width != 0)) { + bin_out_info = out_info[i]; + break; + } + } + if (in_info != NULL && bin_out_info != NULL) { + need_scaling = (in_info->res.width != bin_out_info->res.width) || + (in_info->res.height != bin_out_info->res.height); + } + + + /* binary_dvs_env has to be equal or larger than SH_CSS_MIN_DVS_ENVELOPE */ + binary_dvs_env.width = 0; + binary_dvs_env.height = 0; + ia_css_binary_dvs_env(info, dvs_env, &binary_dvs_env); + dvs_env_width = binary_dvs_env.width; + dvs_env_height = binary_dvs_env.height; + binary->dvs_envelope.width = dvs_env_width; + binary->dvs_envelope.height = dvs_env_height; + + /* internal resolution calculation */ + internal_res.width = 0; + internal_res.height = 0; + ia_css_binary_internal_res(in_info, bds_out_info, bin_out_info, dvs_env, + info, &internal_res); + isp_internal_width = internal_res.width; + isp_internal_height = internal_res.height; + + /* internal frame info */ + if (bin_out_info != NULL) /* { */ + binary->internal_frame_info.format = bin_out_info->format; + /* } */ + binary->internal_frame_info.res.width = isp_internal_width; + binary->internal_frame_info.padded_width = CEIL_MUL(isp_internal_width, 2*ISP_VEC_NELEMS); + binary->internal_frame_info.res.height = isp_internal_height; + binary->internal_frame_info.raw_bit_depth = bits_per_pixel; + + if (in_info != NULL) { + binary->effective_in_frame_res.width = in_info->res.width; + binary->effective_in_frame_res.height = in_info->res.height; + + bits_per_pixel = in_info->raw_bit_depth; + + /* input info */ + binary->in_frame_info.res.width = in_info->res.width + info->pipeline.left_cropping; + binary->in_frame_info.res.height = in_info->res.height + info->pipeline.top_cropping; + +#if !defined(HAS_RES_MGR) /* dvs env is included already */ + binary->in_frame_info.res.width += dvs_env_width; + binary->in_frame_info.res.height += dvs_env_height; +#endif + + binary->in_frame_info.padded_width = + binary_in_frame_padded_width(in_info->res.width, + isp_internal_width, + dvs_env_width, + stream_config_left_padding, + info->pipeline.left_cropping, + need_scaling); + + binary->in_frame_info.format = in_info->format; + binary->in_frame_info.raw_bayer_order = in_info->raw_bayer_order; + binary->in_frame_info.crop_info = in_info->crop_info; + } + + if (online) { + bits_per_pixel = ia_css_util_input_format_bpp( + stream_format, two_ppc); + } + binary->in_frame_info.raw_bit_depth = bits_per_pixel; + + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + if (out_info[i] != NULL) { + binary->out_frame_info[i].res.width = out_info[i]->res.width; + binary->out_frame_info[i].res.height = out_info[i]->res.height; + binary->out_frame_info[i].padded_width = out_info[i]->padded_width; + if (info->pipeline.mode == IA_CSS_BINARY_MODE_COPY) { + binary->out_frame_info[i].raw_bit_depth = bits_per_pixel; + } else { + /* Only relevant for RAW format. + * At the moment, all outputs are raw, 16 bit per pixel, except for copy. + * To do this cleanly, the binary should specify in its info + * the bit depth per output channel. + */ + binary->out_frame_info[i].raw_bit_depth = 16; + } + binary->out_frame_info[i].format = out_info[i]->format; + } + } + + if (vf_info && (vf_info->res.width != 0)) { + err = ia_css_vf_configure(binary, bin_out_info, (struct ia_css_frame_info *)vf_info, &vf_log_ds); + if (err != IA_CSS_SUCCESS) { + if (!accelerator) { + ia_css_isp_param_destroy_isp_parameters( + &binary->mem_params, + &binary->css_params); + } + return err; + } + } + binary->vf_downscale_log2 = vf_log_ds; + + binary->online = online; + binary->input_format = stream_format; + + /* viewfinder output info */ + if ((vf_info != NULL) && (vf_info->res.width != 0)) { + unsigned int vf_out_vecs, vf_out_width, vf_out_height; + binary->vf_frame_info.format = vf_info->format; + if (bin_out_info == NULL) + return IA_CSS_ERR_INTERNAL_ERROR; + vf_out_vecs = __ISP_VF_OUTPUT_WIDTH_VECS(bin_out_info->padded_width, + vf_log_ds); + vf_out_width = _ISP_VF_OUTPUT_WIDTH(vf_out_vecs); + vf_out_height = _ISP_VF_OUTPUT_HEIGHT(bin_out_info->res.height, + vf_log_ds); + + /* For preview mode, output pin is used instead of vf. */ + if (info->pipeline.mode == IA_CSS_BINARY_MODE_PREVIEW) { + binary->out_frame_info[0].res.width = + (bin_out_info->res.width >> vf_log_ds); + binary->out_frame_info[0].padded_width = vf_out_width; + binary->out_frame_info[0].res.height = vf_out_height; + + binary->vf_frame_info.res.width = 0; + binary->vf_frame_info.padded_width = 0; + binary->vf_frame_info.res.height = 0; + } else { + /* we also store the raw downscaled width. This is + * used for digital zoom in preview to zoom only on + * the width that we actually want to keep, not on + * the aligned width. */ + binary->vf_frame_info.res.width = + (bin_out_info->res.width >> vf_log_ds); + binary->vf_frame_info.padded_width = vf_out_width; + binary->vf_frame_info.res.height = vf_out_height; + } + } else { + binary->vf_frame_info.res.width = 0; + binary->vf_frame_info.padded_width = 0; + binary->vf_frame_info.res.height = 0; + } + + if (info->enable.ca_gdc) { + binary->morph_tbl_width = + _ISP_MORPH_TABLE_WIDTH(isp_internal_width); + binary->morph_tbl_aligned_width = + _ISP_MORPH_TABLE_ALIGNED_WIDTH(isp_internal_width); + binary->morph_tbl_height = + _ISP_MORPH_TABLE_HEIGHT(isp_internal_height); + } else { + binary->morph_tbl_width = 0; + binary->morph_tbl_aligned_width = 0; + binary->morph_tbl_height = 0; + } + + sc_3a_dis_width = binary->in_frame_info.res.width; + sc_3a_dis_padded_width = binary->in_frame_info.padded_width; + sc_3a_dis_height = binary->in_frame_info.res.height; + if (bds_out_info != NULL && in_info != NULL && + bds_out_info->res.width != in_info->res.width) { + /* TODO: Next, "internal_frame_info" should be derived from + * bds_out. So this part will change once it is in place! */ + sc_3a_dis_width = bds_out_info->res.width + info->pipeline.left_cropping; + sc_3a_dis_padded_width = isp_internal_width; + sc_3a_dis_height = isp_internal_height; + } + + + s3a_isp_width = _ISP_S3A_ELEMS_ISP_WIDTH(sc_3a_dis_padded_width, + info->pipeline.left_cropping); + if (info->s3a.fixed_s3a_deci_log) { + s3a_log_deci = info->s3a.fixed_s3a_deci_log; + } else { + s3a_log_deci = binary_grid_deci_factor_log2(s3a_isp_width, + sc_3a_dis_height); + } + binary->deci_factor_log2 = s3a_log_deci; + + if (info->enable.s3a) { + binary->s3atbl_width = + _ISP_S3ATBL_WIDTH(sc_3a_dis_width, + s3a_log_deci); + binary->s3atbl_height = + _ISP_S3ATBL_HEIGHT(sc_3a_dis_height, + s3a_log_deci); + binary->s3atbl_isp_width = + _ISP_S3ATBL_ISP_WIDTH(s3a_isp_width, + s3a_log_deci); + binary->s3atbl_isp_height = + _ISP_S3ATBL_ISP_HEIGHT(sc_3a_dis_height, + s3a_log_deci); + } else { + binary->s3atbl_width = 0; + binary->s3atbl_height = 0; + binary->s3atbl_isp_width = 0; + binary->s3atbl_isp_height = 0; + } + + if (info->enable.sc) { + binary->sctbl_width_per_color = +#ifndef ISP2401 + _ISP_SCTBL_WIDTH_PER_COLOR(sc_3a_dis_padded_width, + s3a_log_deci); +#else + _ISP_SCTBL_WIDTH_PER_COLOR(isp_internal_width, s3a_log_deci); +#endif + binary->sctbl_aligned_width_per_color = + SH_CSS_MAX_SCTBL_ALIGNED_WIDTH_PER_COLOR; + binary->sctbl_height = +#ifndef ISP2401 + _ISP_SCTBL_HEIGHT(sc_3a_dis_height, s3a_log_deci); +#else + _ISP_SCTBL_HEIGHT(isp_internal_height, s3a_log_deci); + binary->sctbl_legacy_width_per_color = + _ISP_SCTBL_LEGACY_WIDTH_PER_COLOR(sc_3a_dis_padded_width, s3a_log_deci); + binary->sctbl_legacy_height = + _ISP_SCTBL_LEGACY_HEIGHT(sc_3a_dis_height, s3a_log_deci); +#endif + } else { + binary->sctbl_width_per_color = 0; + binary->sctbl_aligned_width_per_color = 0; + binary->sctbl_height = 0; +#ifdef ISP2401 + binary->sctbl_legacy_width_per_color = 0; + binary->sctbl_legacy_height = 0; +#endif + } + ia_css_sdis_init_info(&binary->dis, + sc_3a_dis_width, + sc_3a_dis_padded_width, + sc_3a_dis_height, + info->pipeline.isp_pipe_version, + info->enable.dis); + if (info->pipeline.left_cropping) + binary->left_padding = 2 * ISP_VEC_NELEMS - info->pipeline.left_cropping; + else + binary->left_padding = 0; + + return IA_CSS_SUCCESS; +} + +enum ia_css_err +ia_css_binary_find(struct ia_css_binary_descr *descr, + struct ia_css_binary *binary) +{ + int mode; + bool online; + bool two_ppc; + enum ia_css_stream_format stream_format; + const struct ia_css_frame_info *req_in_info, + *req_bds_out_info, + *req_out_info[IA_CSS_BINARY_MAX_OUTPUT_PORTS], + *req_bin_out_info = NULL, + *req_vf_info; + + struct ia_css_binary_xinfo *xcandidate; +#ifndef ISP2401 + bool need_ds, need_dz, need_dvs, need_xnr, need_dpc; +#else + bool need_ds, need_dz, need_dvs, need_xnr, need_dpc, need_tnr; +#endif + bool striped; + bool enable_yuv_ds; + bool enable_high_speed; + bool enable_dvs_6axis; + bool enable_reduced_pipe; + bool enable_capture_pp_bli; +#ifdef ISP2401 + bool enable_luma_only; +#endif + enum ia_css_err err = IA_CSS_ERR_INTERNAL_ERROR; + bool continuous; + unsigned int isp_pipe_version; + struct ia_css_resolution dvs_env, internal_res; + unsigned int i; + + assert(descr != NULL); + /* MW: used after an error check, may accept NULL, but doubtfull */ + assert(binary != NULL); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() enter: descr=%p, (mode=%d), binary=%p\n", + descr, descr->mode, + binary); + + mode = descr->mode; + online = descr->online; + two_ppc = descr->two_ppc; + stream_format = descr->stream_format; + req_in_info = descr->in_info; + req_bds_out_info = descr->bds_out_info; + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + req_out_info[i] = descr->out_info[i]; + if (req_out_info[i] && (req_out_info[i]->res.width != 0)) + req_bin_out_info = req_out_info[i]; + } + if (req_bin_out_info == NULL) + return IA_CSS_ERR_INTERNAL_ERROR; +#ifndef ISP2401 + req_vf_info = descr->vf_info; +#else + + if ((descr->vf_info != NULL) && (descr->vf_info->res.width == 0)) + /* width==0 means that there is no vf pin (e.g. in SkyCam preview case) */ + req_vf_info = NULL; + else + req_vf_info = descr->vf_info; +#endif + + need_xnr = descr->enable_xnr; + need_ds = descr->enable_fractional_ds; + need_dz = false; + need_dvs = false; + need_dpc = descr->enable_dpc; +#ifdef ISP2401 + need_tnr = descr->enable_tnr; +#endif + enable_yuv_ds = descr->enable_yuv_ds; + enable_high_speed = descr->enable_high_speed; + enable_dvs_6axis = descr->enable_dvs_6axis; + enable_reduced_pipe = descr->enable_reduced_pipe; + enable_capture_pp_bli = descr->enable_capture_pp_bli; +#ifdef ISP2401 + enable_luma_only = descr->enable_luma_only; +#endif + continuous = descr->continuous; + striped = descr->striped; + isp_pipe_version = descr->isp_pipe_version; + + dvs_env.width = 0; + dvs_env.height = 0; + internal_res.width = 0; + internal_res.height = 0; + + + if (mode == IA_CSS_BINARY_MODE_VIDEO) { + dvs_env = descr->dvs_env; + need_dz = descr->enable_dz; + /* Video is the only mode that has a nodz variant. */ + need_dvs = dvs_env.width || dvs_env.height; + } + + /* print a map of the binary file */ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "BINARY INFO:\n"); + for (i = 0; i < IA_CSS_BINARY_NUM_MODES; i++) { + xcandidate = binary_infos[i]; + if (xcandidate) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%d:\n", i); + while (xcandidate) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, " Name:%s Type:%d Cont:%d\n", + xcandidate->blob->name, xcandidate->type, + xcandidate->sp.enable.continuous); + xcandidate = xcandidate->next; + } + } + } + + /* printf("sh_css_binary_find: pipe version %d\n", isp_pipe_version); */ + for (xcandidate = binary_infos[mode]; xcandidate; + xcandidate = xcandidate->next) { + struct ia_css_binary_info *candidate = &xcandidate->sp; + /* printf("sh_css_binary_find: evaluating candidate: + * %d\n",candidate->id); */ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() candidate = %p, mode = %d ID = %d\n", + candidate, candidate->pipeline.mode, candidate->id); + + /* + * MW: Only a limited set of jointly configured binaries can + * be used in a continuous preview/video mode unless it is + * the copy mode and runs on SP. + */ + if (!candidate->enable.continuous && + continuous && (mode != IA_CSS_BINARY_MODE_COPY)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: !%d && %d && (%d != %d)\n", + __LINE__, candidate->enable.continuous, + continuous, mode, + IA_CSS_BINARY_MODE_COPY); + continue; + } + if (striped && candidate->iterator.num_stripes == 1) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: binary is not striped\n", + __LINE__); + continue; + } + + if (candidate->pipeline.isp_pipe_version != isp_pipe_version && + (mode != IA_CSS_BINARY_MODE_COPY) && + (mode != IA_CSS_BINARY_MODE_CAPTURE_PP) && + (mode != IA_CSS_BINARY_MODE_VF_PP)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: (%d != %d)\n", + __LINE__, + candidate->pipeline.isp_pipe_version, isp_pipe_version); + continue; + } + if (!candidate->enable.reduced_pipe && enable_reduced_pipe) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: !%d && %d\n", + __LINE__, + candidate->enable.reduced_pipe, + enable_reduced_pipe); + continue; + } + if (!candidate->enable.dvs_6axis && enable_dvs_6axis) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: !%d && %d\n", + __LINE__, + candidate->enable.dvs_6axis, + enable_dvs_6axis); + continue; + } + if (candidate->enable.high_speed && !enable_high_speed) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: %d && !%d\n", + __LINE__, + candidate->enable.high_speed, + enable_high_speed); + continue; + } + if (!candidate->enable.xnr && need_xnr) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: %d && !%d\n", + __LINE__, + candidate->enable.xnr, + need_xnr); + continue; + } + if (!(candidate->enable.ds & 2) && enable_yuv_ds) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: !%d && %d\n", + __LINE__, + ((candidate->enable.ds & 2) != 0), + enable_yuv_ds); + continue; + } + if ((candidate->enable.ds & 2) && !enable_yuv_ds) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: %d && !%d\n", + __LINE__, + ((candidate->enable.ds & 2) != 0), + enable_yuv_ds); + continue; + } + + if (mode == IA_CSS_BINARY_MODE_VIDEO && + candidate->enable.ds && need_ds) + need_dz = false; + + /* when we require vf output, we need to have vf_veceven */ + if ((req_vf_info != NULL) && !(candidate->enable.vf_veceven || + /* or variable vf vec even */ + candidate->vf_dec.is_variable || + /* or more than one output pin. */ + xcandidate->num_output_pins > 1)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: (%p != NULL) && !(%d || %d || (%d >%d))\n", + __LINE__, req_vf_info, + candidate->enable.vf_veceven, + candidate->vf_dec.is_variable, + xcandidate->num_output_pins, 1); + continue; + } + if (!candidate->enable.dvs_envelope && need_dvs) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: !%d && %d\n", + __LINE__, + candidate->enable.dvs_envelope, (int)need_dvs); + continue; + } + /* internal_res check considers input, output, and dvs envelope sizes */ + ia_css_binary_internal_res(req_in_info, req_bds_out_info, + req_bin_out_info, &dvs_env, candidate, &internal_res); + if (internal_res.width > candidate->internal.max_width) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: (%d > %d)\n", + __LINE__, internal_res.width, + candidate->internal.max_width); + continue; + } + if (internal_res.height > candidate->internal.max_height) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: (%d > %d)\n", + __LINE__, internal_res.height, + candidate->internal.max_height); + continue; + } + if (!candidate->enable.ds && need_ds & !(xcandidate->num_output_pins > 1)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: !%d && %d\n", + __LINE__, candidate->enable.ds, (int)need_ds); + continue; + } + if (!candidate->enable.uds && !candidate->enable.dvs_6axis && need_dz) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: !%d && !%d && %d\n", + __LINE__, candidate->enable.uds, + candidate->enable.dvs_6axis, (int)need_dz); + continue; + } + if (online && candidate->input.source == IA_CSS_BINARY_INPUT_MEMORY) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: %d && (%d == %d)\n", + __LINE__, online, candidate->input.source, + IA_CSS_BINARY_INPUT_MEMORY); + continue; + } + if (!online && candidate->input.source == IA_CSS_BINARY_INPUT_SENSOR) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: !%d && (%d == %d)\n", + __LINE__, online, candidate->input.source, + IA_CSS_BINARY_INPUT_SENSOR); + continue; + } + if (req_bin_out_info->res.width < candidate->output.min_width || + req_bin_out_info->res.width > candidate->output.max_width) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: (%d > %d) || (%d < %d)\n", + __LINE__, + req_bin_out_info->padded_width, + candidate->output.min_width, + req_bin_out_info->padded_width, + candidate->output.max_width); + continue; + } + if (xcandidate->num_output_pins > 1 && /* in case we have a second output pin, */ + req_vf_info) { /* and we need vf output. */ + if (req_vf_info->res.width > candidate->output.max_width) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: (%d < %d)\n", + __LINE__, + req_vf_info->res.width, + candidate->output.max_width); + continue; + } + } + if (req_in_info->padded_width > candidate->input.max_width) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: (%d > %d)\n", + __LINE__, req_in_info->padded_width, + candidate->input.max_width); + continue; + } + if (!binary_supports_output_format(xcandidate, req_bin_out_info->format)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: !%d\n", + __LINE__, + binary_supports_output_format(xcandidate, req_bin_out_info->format)); + continue; + } +#ifdef ISP2401 + if (!binary_supports_input_format(xcandidate, descr->stream_format)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: !%d\n", + __LINE__, + binary_supports_input_format(xcandidate, req_in_info->format)); + continue; + } +#endif + if (xcandidate->num_output_pins > 1 && /* in case we have a second output pin, */ + req_vf_info && /* and we need vf output. */ + /* check if the required vf format + is supported. */ + !binary_supports_output_format(xcandidate, req_vf_info->format)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: (%d > %d) && (%p != NULL) && !%d\n", + __LINE__, xcandidate->num_output_pins, 1, + req_vf_info, + binary_supports_output_format(xcandidate, req_vf_info->format)); + continue; + } + + /* Check if vf_veceven supports the requested vf format */ + if (xcandidate->num_output_pins == 1 && + req_vf_info && candidate->enable.vf_veceven && + !binary_supports_vf_format(xcandidate, req_vf_info->format)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: (%d == %d) && (%p != NULL) && %d && !%d\n", + __LINE__, xcandidate->num_output_pins, 1, + req_vf_info, candidate->enable.vf_veceven, + binary_supports_vf_format(xcandidate, req_vf_info->format)); + continue; + } + + /* Check if vf_veceven supports the requested vf width */ + if (xcandidate->num_output_pins == 1 && + req_vf_info && candidate->enable.vf_veceven) { /* and we need vf output. */ + if (req_vf_info->res.width > candidate->output.max_width) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: (%d < %d)\n", + __LINE__, + req_vf_info->res.width, + candidate->output.max_width); + continue; + } + } + + if (!supports_bds_factor(candidate->bds.supported_bds_factors, + descr->required_bds_factor)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: 0x%x & 0x%x)\n", + __LINE__, candidate->bds.supported_bds_factors, + descr->required_bds_factor); + continue; + } + + if (!candidate->enable.dpc && need_dpc) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: 0x%x & 0x%x)\n", + __LINE__, candidate->enable.dpc, + descr->enable_dpc); + continue; + } + + if (candidate->uds.use_bci && enable_capture_pp_bli) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: 0x%x & 0x%x)\n", + __LINE__, candidate->uds.use_bci, + descr->enable_capture_pp_bli); + continue; + } + +#ifdef ISP2401 + if (candidate->enable.luma_only != enable_luma_only) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: %d != %d\n", + __LINE__, candidate->enable.luma_only, + descr->enable_luma_only); + continue; + } + + if(!candidate->enable.tnr && need_tnr) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() [%d] continue: !%d && %d\n", + __LINE__, candidate->enable.tnr, + descr->enable_tnr); + continue; + } + +#endif + /* reconfigure any variable properties of the binary */ + err = ia_css_binary_fill_info(xcandidate, online, two_ppc, + stream_format, req_in_info, + req_bds_out_info, + req_out_info, req_vf_info, + binary, &dvs_env, + descr->stream_config_left_padding, + false); + + if (err != IA_CSS_SUCCESS) + break; + binary_init_metrics(&binary->metrics, &binary->info->sp); + break; + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() selected = %p, mode = %d ID = %d\n", + xcandidate, xcandidate ? xcandidate->sp.pipeline.mode : 0, xcandidate ? xcandidate->sp.id : 0); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_binary_find() leave: return_err=%d\n", err); + + return err; +} + +unsigned +ia_css_binary_max_vf_width(void) +{ + /* This is (should be) true for IPU1 and IPU2 */ + /* For IPU3 (SkyCam) this pointer is guarenteed to be NULL simply because such a binary does not exist */ + if (binary_infos[IA_CSS_BINARY_MODE_VF_PP]) + return binary_infos[IA_CSS_BINARY_MODE_VF_PP]->sp.output.max_width; + return 0; +} + +void +ia_css_binary_destroy_isp_parameters(struct ia_css_binary *binary) +{ + if (binary) { + ia_css_isp_param_destroy_isp_parameters(&binary->mem_params, + &binary->css_params); + } +} + +void +ia_css_binary_get_isp_binaries(struct ia_css_binary_xinfo **binaries, + uint32_t *num_isp_binaries) +{ + assert(binaries != NULL); + + if (num_isp_binaries) + *num_isp_binaries = 0; + + *binaries = all_binaries; + if (all_binaries && num_isp_binaries) { + /* -1 to account for sp binary which is not stored in all_binaries */ + if (sh_css_num_binaries > 0) + *num_isp_binaries = sh_css_num_binaries - 1; + } +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/bufq/interface/ia_css_bufq.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/bufq/interface/ia_css_bufq.h new file mode 100644 index 0000000000000000000000000000000000000000..034ec15ec4a15b6302a8fce3a05b4bc1a2f07d36 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/bufq/interface/ia_css_bufq.h @@ -0,0 +1,197 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef _IA_CSS_BUFQ_H +#define _IA_CSS_BUFQ_H + +#include +#include "ia_css_bufq_comm.h" +#include "ia_css_buffer.h" +#include "ia_css_err.h" +#define BUFQ_EVENT_SIZE 4 + + +/** + * @brief Query the internal frame ID. + * + * @param[in] key The query key. + * @param[out] val The query value. + * + * @return + * true, if the query succeeds; + * false, if the query fails. + */ +bool ia_css_query_internal_queue_id( + enum ia_css_buffer_type buf_type, + unsigned int thread_id, + enum sh_css_queue_id *val + ); + + +/** + * @brief Map buffer type to a internal queue id. + * + * @param[in] thread id Thread in which the buffer type has to be mapped or unmapped + * @param[in] buf_type buffer type. + * @param[in] map boolean flag to specify map or unmap + * @return none + */ +void ia_css_queue_map( + unsigned int thread_id, + enum ia_css_buffer_type buf_type, + bool map + ); + + +/** + * @brief Initilize buffer type to a queue id mapping + * @return none + */ +void ia_css_queue_map_init(void); + + +/** + * @brief initializes bufq module + * It create instances of + * -host to SP buffer queue which is a list with predefined size, + * MxN queues where M is the number threads and N is the number queues per thread + *-SP to host buffer queue , is a list with N queues + *-host to SP event communication queue + * -SP to host event communication queue + * -queue for tagger commands + * @return none + */ +void ia_css_bufq_init(void); + + +/** +* @brief Enqueues an item into host to SP buffer queue + * + * @param thread_index[in] Thread in which the item to be enqueued + * + * @param queue_id[in] Index of the queue in the specified thread + * @param item[in] Object to enqueue. + * @return IA_CSS_SUCCESS or error code upon error. + * +*/ +enum ia_css_err ia_css_bufq_enqueue_buffer( + int thread_index, + int queue_id, + uint32_t item); + +/** +* @brief Dequeues an item from SP to host buffer queue. + * + * @param queue_id[in] Specifies the index of the queue in the list where + * the item has to be read. + * @paramitem [out] Object to be dequeued into this item. + * @return IA_CSS_SUCCESS or error code upon error. + * +*/ +enum ia_css_err ia_css_bufq_dequeue_buffer( + int queue_id, + uint32_t *item); + +/** +* @brief Enqueue an event item into host to SP communication event queue. + * + * @param[in] evt_id The event ID. + * @param[in] evt_payload_0 The event payload. + * @param[in] evt_payload_1 The event payload. + * @param[in] evt_payload_2 The event payload. + * @return IA_CSS_SUCCESS or error code upon error. + * +*/ +enum ia_css_err ia_css_bufq_enqueue_psys_event( + uint8_t evt_id, + uint8_t evt_payload_0, + uint8_t evt_payload_1, + uint8_t evt_payload_2 + ); + +/** + * @brief Dequeue an item from SP to host communication event queue. + * + * @param item Object to be dequeued into this item. + * @return IA_CSS_SUCCESS or error code upon error. + * +*/ +enum ia_css_err ia_css_bufq_dequeue_psys_event( + uint8_t item[BUFQ_EVENT_SIZE] + ); + +/** + * @brief Enqueue an event item into host to SP EOF event queue. + * + * @param[in] evt_id The event ID. + * @return IA_CSS_SUCCESS or error code upon error. + * + */ +enum ia_css_err ia_css_bufq_enqueue_isys_event( + uint8_t evt_id); + +/** +* @brief Dequeue an item from SP to host communication EOF event queue. + + * + * @param item Object to be dequeued into this item. + * @return IA_CSS_SUCCESS or error code upon error. + * + */ +enum ia_css_err ia_css_bufq_dequeue_isys_event( + uint8_t item[BUFQ_EVENT_SIZE]); + +/** +* @brief Enqueue a tagger command item into tagger command queue.. + * + * @param item Object to be enqueue. + * @return IA_CSS_SUCCESS or error code upon error. + * +*/ +enum ia_css_err ia_css_bufq_enqueue_tag_cmd( + uint32_t item); + +/** +* @brief Uninitializes bufq module. + * + * @return IA_CSS_SUCCESS or error code upon error. + * +*/ +enum ia_css_err ia_css_bufq_deinit(void); + +/** +* @brief Dump queue states + * + * @return None + * +*/ +void ia_css_bufq_dump_queue_info(void); + +#endif /* _IA_CSS_BUFQ_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/bufq/interface/ia_css_bufq_comm.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/bufq/interface/ia_css_bufq_comm.h new file mode 100644 index 0000000000000000000000000000000000000000..bb77080591b9028fddcdf58ff3899f02fed2b564 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/bufq/interface/ia_css_bufq_comm.h @@ -0,0 +1,66 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef _IA_CSS_BUFQ_COMM_H +#define _IA_CSS_BUFQ_COMM_H + +#include "system_global.h" + +enum sh_css_queue_id { + SH_CSS_INVALID_QUEUE_ID = -1, + SH_CSS_QUEUE_A_ID = 0, + SH_CSS_QUEUE_B_ID, + SH_CSS_QUEUE_C_ID, + SH_CSS_QUEUE_D_ID, + SH_CSS_QUEUE_E_ID, + SH_CSS_QUEUE_F_ID, + SH_CSS_QUEUE_G_ID, +#if defined(HAS_NO_INPUT_SYSTEM) + /* input frame queue for skycam */ + SH_CSS_QUEUE_H_ID, +#endif +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) + SH_CSS_QUEUE_H_ID, /* for metadata */ +#endif + +#if defined(HAS_NO_INPUT_SYSTEM) || defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) +#define SH_CSS_MAX_NUM_QUEUES (SH_CSS_QUEUE_H_ID+1) +#else +#define SH_CSS_MAX_NUM_QUEUES (SH_CSS_QUEUE_G_ID+1) +#endif + +}; + +#define SH_CSS_MAX_DYNAMIC_BUFFERS_PER_THREAD SH_CSS_MAX_NUM_QUEUES +/* for now we staticaly assign queue 0 & 1 to parameter sets */ +#define IA_CSS_PARAMETER_SET_QUEUE_ID SH_CSS_QUEUE_A_ID +#define IA_CSS_PER_FRAME_PARAMETER_SET_QUEUE_ID SH_CSS_QUEUE_B_ID + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/bufq/src/bufq.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/bufq/src/bufq.c new file mode 100644 index 0000000000000000000000000000000000000000..30a329022a2b838570deb75e336b17f2b07bfb52 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/bufq/src/bufq.c @@ -0,0 +1,596 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "assert_support.h" /* assert */ +#include "ia_css_buffer.h" +#include "sp.h" +#include "ia_css_bufq.h" /* Bufq API's */ +#include "ia_css_queue.h" /* ia_css_queue_t */ +#include "sw_event_global.h" /* Event IDs.*/ +#include "ia_css_eventq.h" /* ia_css_eventq_recv()*/ +#include "ia_css_debug.h" /* ia_css_debug_dtrace*/ +#include "sh_css_internal.h" /* sh_css_queue_type */ +#include "sp_local.h" /* sp_address_of */ +#include "ia_css_util.h" /* ia_css_convert_errno()*/ +#include "sh_css_firmware.h" /* sh_css_sp_fw*/ + +#define BUFQ_DUMP_FILE_NAME_PREFIX_SIZE 256 + +static char prefix[BUFQ_DUMP_FILE_NAME_PREFIX_SIZE] = {0}; + +/*********************************************************/ +/* Global Queue objects used by CSS */ +/*********************************************************/ + +#ifndef ISP2401 + +struct sh_css_queues { + /* Host2SP buffer queue */ + ia_css_queue_t host2sp_buffer_queue_handles + [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES]; + /* SP2Host buffer queue */ + ia_css_queue_t sp2host_buffer_queue_handles + [SH_CSS_MAX_NUM_QUEUES]; + + /* Host2SP event queue */ + ia_css_queue_t host2sp_psys_event_queue_handle; + + /* SP2Host event queue */ + ia_css_queue_t sp2host_psys_event_queue_handle; + +#if !defined(HAS_NO_INPUT_SYSTEM) + /* Host2SP ISYS event queue */ + ia_css_queue_t host2sp_isys_event_queue_handle; + + /* SP2Host ISYS event queue */ + ia_css_queue_t sp2host_isys_event_queue_handle; +#endif + /* Tagger command queue */ + ia_css_queue_t host2sp_tag_cmd_queue_handle; +}; + +#else + +struct sh_css_queues { + /* Host2SP buffer queue */ + ia_css_queue_t host2sp_buffer_queue_handles + [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES]; + /* SP2Host buffer queue */ + ia_css_queue_t sp2host_buffer_queue_handles + [SH_CSS_MAX_NUM_QUEUES]; + + /* Host2SP event queue */ + ia_css_queue_t host2sp_psys_event_queue_handle; + + /* SP2Host event queue */ + ia_css_queue_t sp2host_psys_event_queue_handle; + +#if !defined(HAS_NO_INPUT_SYSTEM) + /* Host2SP ISYS event queue */ + ia_css_queue_t host2sp_isys_event_queue_handle; + + /* SP2Host ISYS event queue */ + ia_css_queue_t sp2host_isys_event_queue_handle; + + /* Tagger command queue */ + ia_css_queue_t host2sp_tag_cmd_queue_handle; +#endif +}; + +#endif + +struct sh_css_queues css_queues; + + +/******************************************************* +*** Static variables +********************************************************/ +static int buffer_type_to_queue_id_map[SH_CSS_MAX_SP_THREADS][IA_CSS_NUM_DYNAMIC_BUFFER_TYPE]; +static bool queue_availability[SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES]; + +/******************************************************* +*** Static functions +********************************************************/ +static void map_buffer_type_to_queue_id( + unsigned int thread_id, + enum ia_css_buffer_type buf_type + ); +static void unmap_buffer_type_to_queue_id( + unsigned int thread_id, + enum ia_css_buffer_type buf_type + ); + +static ia_css_queue_t *bufq_get_qhandle( + enum sh_css_queue_type type, + enum sh_css_queue_id id, + int thread + ); + +/******************************************************* +*** Public functions +********************************************************/ +void ia_css_queue_map_init(void) +{ + unsigned int i, j; + + for (i = 0; i < SH_CSS_MAX_SP_THREADS; i++) { + for (j = 0; j < SH_CSS_MAX_NUM_QUEUES; j++) + queue_availability[i][j] = true; + } + + for (i = 0; i < SH_CSS_MAX_SP_THREADS; i++) { + for (j = 0; j < IA_CSS_NUM_DYNAMIC_BUFFER_TYPE; j++) + buffer_type_to_queue_id_map[i][j] = SH_CSS_INVALID_QUEUE_ID; + } +} + +void ia_css_queue_map( + unsigned int thread_id, + enum ia_css_buffer_type buf_type, + bool map) +{ + assert(buf_type < IA_CSS_NUM_DYNAMIC_BUFFER_TYPE); + assert(thread_id < SH_CSS_MAX_SP_THREADS); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_queue_map() enter: buf_type=%d, thread_id=%d\n", buf_type, thread_id); + + if (map) + map_buffer_type_to_queue_id(thread_id, buf_type); + else + unmap_buffer_type_to_queue_id(thread_id, buf_type); +} + +/** + * @brief Query the internal queue ID. + */ +bool ia_css_query_internal_queue_id( + enum ia_css_buffer_type buf_type, + unsigned int thread_id, + enum sh_css_queue_id *val) +{ + IA_CSS_ENTER("buf_type=%d, thread_id=%d, val = %p", buf_type, thread_id, val); + + if ((val == NULL) || (thread_id >= SH_CSS_MAX_SP_THREADS) || (buf_type >= IA_CSS_NUM_DYNAMIC_BUFFER_TYPE)) { + IA_CSS_LEAVE("return_val = false"); + return false; + } + + *val = buffer_type_to_queue_id_map[thread_id][buf_type]; + if ((*val == SH_CSS_INVALID_QUEUE_ID) || (*val >= SH_CSS_MAX_NUM_QUEUES)) { + IA_CSS_LOG("INVALID queue ID MAP = %d\n", *val); + IA_CSS_LEAVE("return_val = false"); + return false; + } + IA_CSS_LEAVE("return_val = true"); + return true; +} + +/******************************************************* +*** Static functions +********************************************************/ +static void map_buffer_type_to_queue_id( + unsigned int thread_id, + enum ia_css_buffer_type buf_type) +{ + unsigned int i; + + assert(thread_id < SH_CSS_MAX_SP_THREADS); + assert(buf_type < IA_CSS_NUM_DYNAMIC_BUFFER_TYPE); + assert(buffer_type_to_queue_id_map[thread_id][buf_type] == SH_CSS_INVALID_QUEUE_ID); + + /* queue 0 is reserved for parameters because it doesn't depend on events */ + if (buf_type == IA_CSS_BUFFER_TYPE_PARAMETER_SET) { + assert(queue_availability[thread_id][IA_CSS_PARAMETER_SET_QUEUE_ID]); + queue_availability[thread_id][IA_CSS_PARAMETER_SET_QUEUE_ID] = false; + buffer_type_to_queue_id_map[thread_id][buf_type] = IA_CSS_PARAMETER_SET_QUEUE_ID; + return; + } + + /* queue 1 is reserved for per frame parameters because it doesn't depend on events */ + if (buf_type == IA_CSS_BUFFER_TYPE_PER_FRAME_PARAMETER_SET) { + assert(queue_availability[thread_id][IA_CSS_PER_FRAME_PARAMETER_SET_QUEUE_ID]); + queue_availability[thread_id][IA_CSS_PER_FRAME_PARAMETER_SET_QUEUE_ID] = false; + buffer_type_to_queue_id_map[thread_id][buf_type] = IA_CSS_PER_FRAME_PARAMETER_SET_QUEUE_ID; + return; + } + + for (i = SH_CSS_QUEUE_C_ID; i < SH_CSS_MAX_NUM_QUEUES; i++) { + if (queue_availability[thread_id][i] == true) { + queue_availability[thread_id][i] = false; + buffer_type_to_queue_id_map[thread_id][buf_type] = i; + break; + } + } + + assert(i != SH_CSS_MAX_NUM_QUEUES); + return; +} + +static void unmap_buffer_type_to_queue_id( + unsigned int thread_id, + enum ia_css_buffer_type buf_type) +{ + int queue_id; + + assert(thread_id < SH_CSS_MAX_SP_THREADS); + assert(buf_type < IA_CSS_NUM_DYNAMIC_BUFFER_TYPE); + assert(buffer_type_to_queue_id_map[thread_id][buf_type] != SH_CSS_INVALID_QUEUE_ID); + + queue_id = buffer_type_to_queue_id_map[thread_id][buf_type]; + buffer_type_to_queue_id_map[thread_id][buf_type] = SH_CSS_INVALID_QUEUE_ID; + queue_availability[thread_id][queue_id] = true; +} + + +static ia_css_queue_t *bufq_get_qhandle( + enum sh_css_queue_type type, + enum sh_css_queue_id id, + int thread) +{ + ia_css_queue_t *q = 0; + + switch (type) { + case sh_css_host2sp_buffer_queue: + if ((thread >= SH_CSS_MAX_SP_THREADS) || (thread < 0) || + (id == SH_CSS_INVALID_QUEUE_ID)) + break; + q = &css_queues.host2sp_buffer_queue_handles[thread][id]; + break; + case sh_css_sp2host_buffer_queue: + if (id == SH_CSS_INVALID_QUEUE_ID) + break; + q = &css_queues.sp2host_buffer_queue_handles[id]; + break; + case sh_css_host2sp_psys_event_queue: + q = &css_queues.host2sp_psys_event_queue_handle; + break; + case sh_css_sp2host_psys_event_queue: + q = &css_queues.sp2host_psys_event_queue_handle; + break; +#if !defined(HAS_NO_INPUT_SYSTEM) + case sh_css_host2sp_isys_event_queue: + q = &css_queues.host2sp_isys_event_queue_handle; + break; + case sh_css_sp2host_isys_event_queue: + q = &css_queues.sp2host_isys_event_queue_handle; + break; +#endif + case sh_css_host2sp_tag_cmd_queue: + q = &css_queues.host2sp_tag_cmd_queue_handle; + break; + default: + break; + } + + return q; +} + +/* Local function to initialize a buffer queue. This reduces + * the chances of copy-paste errors or typos. + */ +STORAGE_CLASS_INLINE void +init_bufq(unsigned int desc_offset, + unsigned int elems_offset, + ia_css_queue_t *handle) +{ + const struct ia_css_fw_info *fw; + unsigned int q_base_addr; + ia_css_queue_remote_t remoteq; + + fw = &sh_css_sp_fw; +#ifdef C_RUN + q_base_addr = (unsigned int)sp_address_of(ia_css_bufq_host_sp_queue); +#else + q_base_addr = fw->info.sp.host_sp_queue; +#endif + + /* Setup queue location as SP and proc id as SP0_ID */ + remoteq.location = IA_CSS_QUEUE_LOC_SP; + remoteq.proc_id = SP0_ID; + remoteq.cb_desc_addr = q_base_addr + desc_offset; + remoteq.cb_elems_addr = q_base_addr + elems_offset; + /* Initialize the queue instance and obtain handle */ + ia_css_queue_remote_init(handle, &remoteq); +} + +void ia_css_bufq_init(void) +{ + int i, j; + + IA_CSS_ENTER_PRIVATE(""); + + /* Setup all the local queue descriptors for Host2SP Buffer Queues */ + for (i = 0; i < SH_CSS_MAX_SP_THREADS; i++) + for (j = 0; j < SH_CSS_MAX_NUM_QUEUES; j++) { + init_bufq((uint32_t)offsetof(struct host_sp_queues, host2sp_buffer_queues_desc[i][j]), + (uint32_t)offsetof(struct host_sp_queues, host2sp_buffer_queues_elems[i][j]), + &css_queues.host2sp_buffer_queue_handles[i][j]); + } + + /* Setup all the local queue descriptors for SP2Host Buffer Queues */ + for (i = 0; i < SH_CSS_MAX_NUM_QUEUES; i++) { + init_bufq(offsetof(struct host_sp_queues, sp2host_buffer_queues_desc[i]), + offsetof(struct host_sp_queues, sp2host_buffer_queues_elems[i]), + &css_queues.sp2host_buffer_queue_handles[i]); + } + + /* Host2SP event queue*/ + init_bufq((uint32_t)offsetof(struct host_sp_queues, host2sp_psys_event_queue_desc), + (uint32_t)offsetof(struct host_sp_queues, host2sp_psys_event_queue_elems), + &css_queues.host2sp_psys_event_queue_handle); + + /* SP2Host event queue */ + init_bufq((uint32_t)offsetof(struct host_sp_queues, sp2host_psys_event_queue_desc), + (uint32_t)offsetof(struct host_sp_queues, sp2host_psys_event_queue_elems), + &css_queues.sp2host_psys_event_queue_handle); + +#if !defined(HAS_NO_INPUT_SYSTEM) + /* Host2SP ISYS event queue */ + init_bufq((uint32_t)offsetof(struct host_sp_queues, host2sp_isys_event_queue_desc), + (uint32_t)offsetof(struct host_sp_queues, host2sp_isys_event_queue_elems), + &css_queues.host2sp_isys_event_queue_handle); + + /* SP2Host ISYS event queue*/ + init_bufq((uint32_t)offsetof(struct host_sp_queues, sp2host_isys_event_queue_desc), + (uint32_t)offsetof(struct host_sp_queues, sp2host_isys_event_queue_elems), + &css_queues.sp2host_isys_event_queue_handle); + + /* Host2SP tagger command queue */ + init_bufq((uint32_t)offsetof(struct host_sp_queues, host2sp_tag_cmd_queue_desc), + (uint32_t)offsetof(struct host_sp_queues, host2sp_tag_cmd_queue_elems), + &css_queues.host2sp_tag_cmd_queue_handle); +#endif + + IA_CSS_LEAVE_PRIVATE(""); +} + +enum ia_css_err ia_css_bufq_enqueue_buffer( + int thread_index, + int queue_id, + uint32_t item) +{ + enum ia_css_err return_err = IA_CSS_SUCCESS; + ia_css_queue_t *q; + int error; + + IA_CSS_ENTER_PRIVATE("queue_id=%d", queue_id); + if ((thread_index >= SH_CSS_MAX_SP_THREADS) || (thread_index < 0) || + (queue_id == SH_CSS_INVALID_QUEUE_ID)) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + /* Get the queue for communication */ + q = bufq_get_qhandle(sh_css_host2sp_buffer_queue, + queue_id, + thread_index); + if (q != NULL) { + error = ia_css_queue_enqueue(q, item); + return_err = ia_css_convert_errno(error); + } else { + IA_CSS_ERROR("queue is not initialized"); + return_err = IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } + + IA_CSS_LEAVE_ERR_PRIVATE(return_err); + return return_err; +} + +enum ia_css_err ia_css_bufq_dequeue_buffer( + int queue_id, + uint32_t *item) +{ + enum ia_css_err return_err; + int error = 0; + ia_css_queue_t *q; + + IA_CSS_ENTER_PRIVATE("queue_id=%d", queue_id); + if ((item == NULL) || + (queue_id <= SH_CSS_INVALID_QUEUE_ID) || + (queue_id >= SH_CSS_MAX_NUM_QUEUES) + ) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + q = bufq_get_qhandle(sh_css_sp2host_buffer_queue, + queue_id, + -1); + if (q != NULL) { + error = ia_css_queue_dequeue(q, item); + return_err = ia_css_convert_errno(error); + } else { + IA_CSS_ERROR("queue is not initialized"); + return_err = IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } + + IA_CSS_LEAVE_ERR_PRIVATE(return_err); + return return_err; +} + +enum ia_css_err ia_css_bufq_enqueue_psys_event( + uint8_t evt_id, + uint8_t evt_payload_0, + uint8_t evt_payload_1, + uint8_t evt_payload_2) +{ + enum ia_css_err return_err; + int error = 0; + ia_css_queue_t *q; + + IA_CSS_ENTER_PRIVATE("evt_id=%d", evt_id); + q = bufq_get_qhandle(sh_css_host2sp_psys_event_queue, -1, -1); + if (NULL == q) { + IA_CSS_ERROR("queue is not initialized"); + return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } + + error = ia_css_eventq_send(q, + evt_id, evt_payload_0, evt_payload_1, evt_payload_2); + + return_err = ia_css_convert_errno(error); + IA_CSS_LEAVE_ERR_PRIVATE(return_err); + return return_err; +} + +enum ia_css_err ia_css_bufq_dequeue_psys_event( + uint8_t item[BUFQ_EVENT_SIZE]) +{ + enum ia_css_err return_err; + int error = 0; + ia_css_queue_t *q; + + /* No ENTER/LEAVE in this function since this is polled + * by some test apps. Enablign logging here floods the log + * files which may cause timeouts. */ + if (item == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + q = bufq_get_qhandle(sh_css_sp2host_psys_event_queue, -1, -1); + if (NULL == q) { + IA_CSS_ERROR("queue is not initialized"); + return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } + error = ia_css_eventq_recv(q, item); + + return_err = ia_css_convert_errno(error); + return return_err; + +} + +enum ia_css_err ia_css_bufq_dequeue_isys_event( + uint8_t item[BUFQ_EVENT_SIZE]) +{ +#if !defined(HAS_NO_INPUT_SYSTEM) + enum ia_css_err return_err; + int error = 0; + ia_css_queue_t *q; + + /* No ENTER/LEAVE in this function since this is polled + * by some test apps. Enablign logging here floods the log + * files which may cause timeouts. */ + if (item == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + q = bufq_get_qhandle(sh_css_sp2host_isys_event_queue, -1, -1); + if (q == NULL) { + IA_CSS_ERROR("queue is not initialized"); + return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } + error = ia_css_eventq_recv(q, item); + return_err = ia_css_convert_errno(error); + return return_err; +#else + (void)item; + return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; +#endif +} + +enum ia_css_err ia_css_bufq_enqueue_isys_event(uint8_t evt_id) +{ +#if !defined(HAS_NO_INPUT_SYSTEM) + enum ia_css_err return_err; + int error = 0; + ia_css_queue_t *q; + + IA_CSS_ENTER_PRIVATE("event_id=%d", evt_id); + q = bufq_get_qhandle(sh_css_host2sp_isys_event_queue, -1, -1); + if (q == NULL) { + IA_CSS_ERROR("queue is not initialized"); + return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } + + error = ia_css_eventq_send(q, evt_id, 0, 0, 0); + return_err = ia_css_convert_errno(error); + IA_CSS_LEAVE_ERR_PRIVATE(return_err); + return return_err; +#else + (void)evt_id; + return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; +#endif +} + +enum ia_css_err ia_css_bufq_enqueue_tag_cmd( + uint32_t item) +{ +#if !defined(HAS_NO_INPUT_SYSTEM) + enum ia_css_err return_err; + int error = 0; + ia_css_queue_t *q; + + IA_CSS_ENTER_PRIVATE("item=%d", item); + q = bufq_get_qhandle(sh_css_host2sp_tag_cmd_queue, -1, -1); + if (NULL == q) { + IA_CSS_ERROR("queue is not initialized"); + return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } + error = ia_css_queue_enqueue(q, item); + + return_err = ia_css_convert_errno(error); + IA_CSS_LEAVE_ERR_PRIVATE(return_err); + return return_err; +#else + (void)item; + return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; +#endif +} + +enum ia_css_err ia_css_bufq_deinit(void) +{ + return IA_CSS_SUCCESS; +} + +static void bufq_dump_queue_info(const char *prefix, ia_css_queue_t *qhandle) +{ + uint32_t free = 0, used = 0; + assert(prefix != NULL && qhandle != NULL); + ia_css_queue_get_used_space(qhandle, &used); + ia_css_queue_get_free_space(qhandle, &free); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s: used=%u free=%u\n", + prefix, used, free); + +} + +void ia_css_bufq_dump_queue_info(void) +{ + int i, j; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "Queue Information:\n"); + + for (i = 0; i < SH_CSS_MAX_SP_THREADS; i++) { + for (j = 0; j < SH_CSS_MAX_NUM_QUEUES; j++) { + snprintf(prefix, BUFQ_DUMP_FILE_NAME_PREFIX_SIZE, + "host2sp_buffer_queue[%u][%u]", i, j); + bufq_dump_queue_info(prefix, + &css_queues.host2sp_buffer_queue_handles[i][j]); + } + } + + for (i = 0; i < SH_CSS_MAX_NUM_QUEUES; i++) { + snprintf(prefix, BUFQ_DUMP_FILE_NAME_PREFIX_SIZE, + "sp2host_buffer_queue[%u]", i); + bufq_dump_queue_info(prefix, + &css_queues.sp2host_buffer_queue_handles[i]); + } + bufq_dump_queue_info("host2sp_psys_event", + &css_queues.host2sp_psys_event_queue_handle); + bufq_dump_queue_info("sp2host_psys_event", + &css_queues.sp2host_psys_event_queue_handle); + +#if !defined(HAS_NO_INPUT_SYSTEM) + bufq_dump_queue_info("host2sp_isys_event", + &css_queues.host2sp_isys_event_queue_handle); + bufq_dump_queue_info("sp2host_isys_event", + &css_queues.sp2host_isys_event_queue_handle); + bufq_dump_queue_info("host2sp_tag_cmd", + &css_queues.host2sp_tag_cmd_queue_handle); +#endif +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/debug/interface/ia_css_debug.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/debug/interface/ia_css_debug.h new file mode 100644 index 0000000000000000000000000000000000000000..be7df3a30c21f67d9ae6b788c788514f45db82df --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/debug/interface/ia_css_debug.h @@ -0,0 +1,508 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _IA_CSS_DEBUG_H_ +#define _IA_CSS_DEBUG_H_ + +/*! \file */ + +#include +#include +#include "ia_css_types.h" +#include "ia_css_binary.h" +#include "ia_css_frame_public.h" +#include "ia_css_pipe_public.h" +#include "ia_css_stream_public.h" +#include "ia_css_metadata.h" +#include "sh_css_internal.h" +#ifdef ISP2401 +#if defined(IS_ISP_2500_SYSTEM) +#include "ia_css_pipe.h" +#endif +#endif + +/* available levels */ +/*! Level for tracing errors */ +#define IA_CSS_DEBUG_ERROR 1 +/*! Level for tracing warnings */ +#define IA_CSS_DEBUG_WARNING 3 +/*! Level for tracing debug messages */ +#define IA_CSS_DEBUG_VERBOSE 5 +/*! Level for tracing trace messages a.o. ia_css public function calls */ +#define IA_CSS_DEBUG_TRACE 6 +/*! Level for tracing trace messages a.o. ia_css private function calls */ +#define IA_CSS_DEBUG_TRACE_PRIVATE 7 +/*! Level for tracing parameter messages e.g. in and out params of functions */ +#define IA_CSS_DEBUG_PARAM 8 +/*! Level for tracing info messages */ +#define IA_CSS_DEBUG_INFO 9 +/* Global variable which controls the verbosity levels of the debug tracing */ +extern unsigned int ia_css_debug_trace_level; + +/*! @brief Enum defining the different isp parameters to dump. + * Values can be combined to dump a combination of sets. + */ +enum ia_css_debug_enable_param_dump { + IA_CSS_DEBUG_DUMP_FPN = 1 << 0, /**< FPN table */ + IA_CSS_DEBUG_DUMP_OB = 1 << 1, /**< OB table */ + IA_CSS_DEBUG_DUMP_SC = 1 << 2, /**< Shading table */ + IA_CSS_DEBUG_DUMP_WB = 1 << 3, /**< White balance */ + IA_CSS_DEBUG_DUMP_DP = 1 << 4, /**< Defect Pixel */ + IA_CSS_DEBUG_DUMP_BNR = 1 << 5, /**< Bayer Noise Reductions */ + IA_CSS_DEBUG_DUMP_S3A = 1 << 6, /**< 3A Statistics */ + IA_CSS_DEBUG_DUMP_DE = 1 << 7, /**< De Mosaicing */ + IA_CSS_DEBUG_DUMP_YNR = 1 << 8, /**< Luma Noise Reduction */ + IA_CSS_DEBUG_DUMP_CSC = 1 << 9, /**< Color Space Conversion */ + IA_CSS_DEBUG_DUMP_GC = 1 << 10, /**< Gamma Correction */ + IA_CSS_DEBUG_DUMP_TNR = 1 << 11, /**< Temporal Noise Reduction */ + IA_CSS_DEBUG_DUMP_ANR = 1 << 12, /**< Advanced Noise Reduction */ + IA_CSS_DEBUG_DUMP_CE = 1 << 13, /**< Chroma Enhancement */ + IA_CSS_DEBUG_DUMP_ALL = 1 << 14 /**< Dump all device parameters */ +}; + +#define IA_CSS_ERROR(fmt, ...) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, \ + "%s() %d: error: " fmt "\n", __func__, __LINE__, ##__VA_ARGS__) + +#define IA_CSS_WARNING(fmt, ...) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_WARNING, \ + "%s() %d: warning: " fmt "\n", __func__, __LINE__, ##__VA_ARGS__) + +/* Logging macros for public functions (API functions) */ +#define IA_CSS_ENTER(fmt, ...) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \ + "%s(): enter: " fmt "\n", __func__, ##__VA_ARGS__) + +/* Use this macro for small functions that do not call other functions. */ +#define IA_CSS_ENTER_LEAVE(fmt, ...) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \ + "%s(): enter: leave: " fmt "\n", __func__, ##__VA_ARGS__) + +#define IA_CSS_LEAVE(fmt, ...) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \ + "%s(): leave: " fmt "\n", __func__, ##__VA_ARGS__) + +/* Shorthand for returning an enum ia_css_err return value */ +#define IA_CSS_LEAVE_ERR(__err) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, \ + "%s() %d: leave: return_err=%d\n", __func__, __LINE__, __err) + +/* Use this macro for logging other than enter/leave. + * Note that this macro always uses the PRIVATE logging level. + */ +#define IA_CSS_LOG(fmt, ...) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, \ + "%s(): " fmt "\n", __func__, ##__VA_ARGS__) + +/* Logging macros for non-API functions. These have a lower trace level */ +#define IA_CSS_ENTER_PRIVATE(fmt, ...) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, \ + "%s(): enter: " fmt "\n", __func__, ##__VA_ARGS__) + +#define IA_CSS_LEAVE_PRIVATE(fmt, ...) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, \ + "%s(): leave: " fmt "\n", __func__, ##__VA_ARGS__) + +/* Shorthand for returning an enum ia_css_err return value */ +#define IA_CSS_LEAVE_ERR_PRIVATE(__err) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, \ + "%s() %d: leave: return_err=%d\n", __func__, __LINE__, __err) + +/* Use this macro for small functions that do not call other functions. */ +#define IA_CSS_ENTER_LEAVE_PRIVATE(fmt, ...) \ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, \ + "%s(): enter: leave: " fmt "\n", __func__, ##__VA_ARGS__) + +/*! @brief Function for tracing to the provided printf function in the + * environment. + * @param[in] level Level of the message. + * @param[in] fmt printf like format string + * @param[in] args arguments for the format string + */ +STORAGE_CLASS_INLINE void +ia_css_debug_vdtrace(unsigned int level, const char *fmt, va_list args) +{ + if (ia_css_debug_trace_level >= level) + sh_css_vprint(fmt, args); +} + +extern void ia_css_debug_dtrace(unsigned int level, const char *fmt, ...); + +/*! @brief Dump sp thread's stack contents + * SP thread's stack contents are set to 0xcafecafe. This function dumps the + * stack to inspect if the stack's boundaries are compromised. + * @return None + */ +void ia_css_debug_dump_sp_stack_info(void); + +/*! @brief Function to set the global dtrace verbosity level. + * @param[in] trace_level Maximum level of the messages to be traced. + * @return None + */ +void ia_css_debug_set_dtrace_level( + const unsigned int trace_level); + +/*! @brief Function to get the global dtrace verbosity level. + * @return global dtrace verbosity level + */ +unsigned int ia_css_debug_get_dtrace_level(void); + +/*! @brief Dump input formatter state. + * Dumps the input formatter state to tracing output. + * @return None + */ +void ia_css_debug_dump_if_state(void); + +/*! @brief Dump isp hardware state. + * Dumps the isp hardware state to tracing output. + * @return None + */ +void ia_css_debug_dump_isp_state(void); + +/*! @brief Dump sp hardware state. + * Dumps the sp hardware state to tracing output. + * @return None + */ +void ia_css_debug_dump_sp_state(void); + +#ifdef ISP2401 +/*! @brief Dump GAC hardware state. + * Dumps the GAC ACB hardware registers. may be useful for + * detecting a GAC which got hang. + * @return None + */ +void ia_css_debug_dump_gac_state(void); + +#endif +/*! @brief Dump dma controller state. + * Dumps the dma controller state to tracing output. + * @return None + */ +void ia_css_debug_dump_dma_state(void); + +/*! @brief Dump internal sp software state. + * Dumps the sp software state to tracing output. + * @return None + */ +void ia_css_debug_dump_sp_sw_debug_info(void); + +/*! @brief Dump all related hardware state to the trace output + * @param[in] context String to identify context in output. + * @return None + */ +void ia_css_debug_dump_debug_info( + const char *context); + +#if SP_DEBUG != SP_DEBUG_NONE +void ia_css_debug_print_sp_debug_state( + const struct sh_css_sp_debug_state *state); +#endif + +/*! @brief Dump all related binary info data + * @param[in] bi Binary info struct. + * @return None + */ +void ia_css_debug_binary_print( + const struct ia_css_binary *bi); + +void ia_css_debug_sp_dump_mipi_fifo_high_water(void); + +/*! @brief Dump isp gdc fifo state to the trace output + * Dumps the isp gdc fifo state to tracing output. + * @return None + */ +void ia_css_debug_dump_isp_gdc_fifo_state(void); + +/*! @brief Dump dma isp fifo state + * Dumps the dma isp fifo state to tracing output. + * @return None + */ +void ia_css_debug_dump_dma_isp_fifo_state(void); + +/*! @brief Dump dma sp fifo state + * Dumps the dma sp fifo state to tracing output. + * @return None + */ +void ia_css_debug_dump_dma_sp_fifo_state(void); + +/*! \brief Dump pif A isp fifo state + * Dumps the primary input formatter state to tracing output. + * @return None + */ +void ia_css_debug_dump_pif_a_isp_fifo_state(void); + +/*! \brief Dump pif B isp fifo state + * Dumps the primary input formatter state to tracing output. + * \return None + */ +void ia_css_debug_dump_pif_b_isp_fifo_state(void); + +/*! @brief Dump stream-to-memory sp fifo state + * Dumps the stream-to-memory block state to tracing output. + * @return None + */ +void ia_css_debug_dump_str2mem_sp_fifo_state(void); + +/*! @brief Dump isp sp fifo state + * Dumps the isp sp fifo state to tracing output. + * @return None + */ +void ia_css_debug_dump_isp_sp_fifo_state(void); + +/*! @brief Dump all fifo state info to the output + * Dumps all fifo state to tracing output. + * @return None + */ +void ia_css_debug_dump_all_fifo_state(void); + +/*! @brief Dump the rx state to the output + * Dumps the rx state to tracing output. + * @return None + */ +void ia_css_debug_dump_rx_state(void); + +/*! @brief Dump the input system state to the output + * Dumps the input system state to tracing output. + * @return None + */ +void ia_css_debug_dump_isys_state(void); + +/*! @brief Dump the frame info to the trace output + * Dumps the frame info to tracing output. + * @param[in] frame pointer to struct ia_css_frame + * @param[in] descr description output along with the frame info + * @return None + */ +void ia_css_debug_frame_print( + const struct ia_css_frame *frame, + const char *descr); + +/*! @brief Function to enable sp sleep mode. + * Function that enables sp sleep mode + * @param[in] mode indicates when to put sp to sleep + * @return None + */ +void ia_css_debug_enable_sp_sleep_mode(enum ia_css_sp_sleep_mode mode); + +/*! @brief Function to wake up sp when in sleep mode. + * After sp has been put to sleep, use this function to let it continue + * to run again. + * @return None + */ +void ia_css_debug_wake_up_sp(void); + +/*! @brief Function to dump isp parameters. + * Dump isp parameters to tracing output + * @param[in] stream pointer to ia_css_stream struct + * @param[in] enable flag indicating which parameters to dump. + * @return None + */ +void ia_css_debug_dump_isp_params(struct ia_css_stream *stream, unsigned int enable); + +/*! @brief Function to dump some sp performance counters. + * Dump sp performance counters, currently input system errors. + * @return None + */ +void ia_css_debug_dump_perf_counters(void); + +#ifdef HAS_WATCHDOG_SP_THREAD_DEBUG +void sh_css_dump_thread_wait_info(void); +void sh_css_dump_pipe_stage_info(void); +void sh_css_dump_pipe_stripe_info(void); +#endif + +void ia_css_debug_dump_isp_binary(void); + +void sh_css_dump_sp_raw_copy_linecount(bool reduced); + +/*! @brief Dump the resolution info to the trace output + * Dumps the resolution info to the trace output. + * @param[in] res pointer to struct ia_css_resolution + * @param[in] label description of resolution output + * @return None + */ +void ia_css_debug_dump_resolution( + const struct ia_css_resolution *res, + const char *label); + +/*! @brief Dump the frame info to the trace output + * Dumps the frame info to the trace output. + * @param[in] info pointer to struct ia_css_frame_info + * @param[in] label description of frame_info output + * @return None + */ +void ia_css_debug_dump_frame_info( + const struct ia_css_frame_info *info, + const char *label); + +/*! @brief Dump the capture config info to the trace output + * Dumps the capture config info to the trace output. + * @param[in] config pointer to struct ia_css_capture_config + * @return None + */ +void ia_css_debug_dump_capture_config( + const struct ia_css_capture_config *config); + +/*! @brief Dump the pipe extra config info to the trace output + * Dumps the pipe extra config info to the trace output. + * @param[in] extra_config pointer to struct ia_css_pipe_extra_config + * @return None + */ +void ia_css_debug_dump_pipe_extra_config( + const struct ia_css_pipe_extra_config *extra_config); + +/*! @brief Dump the pipe config info to the trace output + * Dumps the pipe config info to the trace output. + * @param[in] config pointer to struct ia_css_pipe_config + * @return None + */ +void ia_css_debug_dump_pipe_config( + const struct ia_css_pipe_config *config); + + +/*! @brief Dump the stream config source info to the trace output + * Dumps the stream config source info to the trace output. + * @param[in] config pointer to struct ia_css_stream_config + * @return None + */ +void ia_css_debug_dump_stream_config_source( + const struct ia_css_stream_config *config); + +/*! @brief Dump the mipi buffer config info to the trace output + * Dumps the mipi buffer config info to the trace output. + * @param[in] config pointer to struct ia_css_mipi_buffer_config + * @return None + */ +void ia_css_debug_dump_mipi_buffer_config( + const struct ia_css_mipi_buffer_config *config); + +/*! @brief Dump the metadata config info to the trace output + * Dumps the metadata config info to the trace output. + * @param[in] config pointer to struct ia_css_metadata_config + * @return None + */ +void ia_css_debug_dump_metadata_config( + const struct ia_css_metadata_config *config); + +/*! @brief Dump the stream config info to the trace output + * Dumps the stream config info to the trace output. + * @param[in] config pointer to struct ia_css_stream_config + * @param[in] num_pipes number of pipes for the stream + * @return None + */ +void ia_css_debug_dump_stream_config( + const struct ia_css_stream_config *config, + int num_pipes); + +/*! @brief Dump the state of the SP tagger + * Dumps the internal state of the SP tagger + * @return None + */ +void ia_css_debug_tagger_state(void); + +/** + * @brief Initialize the debug mode. + * + * WARNING: + * This API should be called ONLY once in the debug mode. + * + * @return + * - true, if it is successful. + * - false, otherwise. + */ +bool ia_css_debug_mode_init(void); + +/** + * @brief Disable the DMA channel. + * + * @param[in] dma_ID The ID of the target DMA. + * @param[in] channel_id The ID of the target DMA channel. + * @param[in] request_type The type of the DMA request. + * For example: + * - "0" indicates the writing request. + * - "1" indicates the reading request. + * + * This is part of the DMA API -> dma.h + * + * @return + * - true, if it is successful. + * - false, otherwise. + */ +bool ia_css_debug_mode_disable_dma_channel( + int dma_ID, + int channel_id, + int request_type); +/** + * @brief Enable the DMA channel. + * + * @param[in] dma_ID The ID of the target DMA. + * @param[in] channel_id The ID of the target DMA channel. + * @param[in] request_type The type of the DMA request. + * For example: + * - "0" indicates the writing request. + * - "1" indicates the reading request. + * + * @return + * - true, if it is successful. + * - false, otherwise. + */ +bool ia_css_debug_mode_enable_dma_channel( + int dma_ID, + int channel_id, + int request_type); + +/** + * @brief Dump tracer data. + * [Currently support is only for SKC] + * + * @return + * - none. + */ +void ia_css_debug_dump_trace(void); + +#ifdef ISP2401 +/** + * @brief Program counter dumping (in loop) + * + * @param[in] id The ID of the SP + * @param[in] num_of_dumps The number of dumps + * + * @return + * - none + */ +void ia_css_debug_pc_dump(sp_ID_t id, unsigned int num_of_dumps); + +#if defined(IS_ISP_2500_SYSTEM) +/*! @brief Dump all states for ISP hang case. + * Dumps the ISP previous and current configurations + * GACs status, SP0/1 statuses. + * + * @param[in] pipe The current pipe + * + * @return None + */ +void ia_css_debug_dump_hang_status( + struct ia_css_pipe *pipe); + +/*! @brief External command handler + * External command handler + * + * @return None + */ +void ia_css_debug_ext_command_handler(void); + +#endif +#endif + +#endif /* _IA_CSS_DEBUG_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/debug/interface/ia_css_debug_internal.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/debug/interface/ia_css_debug_internal.h new file mode 100644 index 0000000000000000000000000000000000000000..88d02580720118c5b2bdc5ffbc69bbb521d272d6 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/debug/interface/ia_css_debug_internal.h @@ -0,0 +1,31 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +/* TO DO: Move debug related code from ia_css_internal.h in */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/debug/interface/ia_css_debug_pipe.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/debug/interface/ia_css_debug_pipe.h new file mode 100644 index 0000000000000000000000000000000000000000..72ac0e32ebf7485c12f593538da9e9763c0e7fce --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/debug/interface/ia_css_debug_pipe.h @@ -0,0 +1,84 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef _IA_CSS_DEBUG_PIPE_H_ +#define _IA_CSS_DEBUG_PIPE_H_ + +/*! \file */ + +#include +#include +#include "ia_css_pipeline.h" + +/** + * @brief Internal debug support for constructing a pipe graph. + * + * @return None + */ +extern void ia_css_debug_pipe_graph_dump_prologue(void); + +/** + * @brief Internal debug support for constructing a pipe graph. + * + * @return None + */ +extern void ia_css_debug_pipe_graph_dump_epilogue(void); + +/** + * @brief Internal debug support for constructing a pipe graph. + * @param[in] stage Pipeline stage. + * @param[in] id Pipe id. + * + * @return None + */ +extern void ia_css_debug_pipe_graph_dump_stage( + struct ia_css_pipeline_stage *stage, + enum ia_css_pipe_id id); + +/** + * @brief Internal debug support for constructing a pipe graph. + * @param[in] out_frame Output frame of SP raw copy. + * + * @return None + */ +extern void ia_css_debug_pipe_graph_dump_sp_raw_copy( + struct ia_css_frame *out_frame); + + +/** + * @brief Internal debug support for constructing a pipe graph. + * @param[in] stream_config info about sensor and input formatter. + * + * @return None + */ +extern void ia_css_debug_pipe_graph_dump_stream_config( + const struct ia_css_stream_config *stream_config); + +#endif /* _IA_CSS_DEBUG_PIPE_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/debug/src/ia_css_debug.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/debug/src/ia_css_debug.c new file mode 100644 index 0000000000000000000000000000000000000000..66c969a9c114ae27bf031b1b7fd7440c2d7b5857 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/debug/src/ia_css_debug.c @@ -0,0 +1,3628 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "debug.h" +#include "memory_access.h" + +#ifndef __INLINE_INPUT_SYSTEM__ +#define __INLINE_INPUT_SYSTEM__ +#endif +#ifndef __INLINE_IBUF_CTRL__ +#define __INLINE_IBUF_CTRL__ +#endif +#ifndef __INLINE_CSI_RX__ +#define __INLINE_CSI_RX__ +#endif +#ifndef __INLINE_PIXELGEN__ +#define __INLINE_PIXELGEN__ +#endif +#ifndef __INLINE_STREAM2MMIO__ +#define __INLINE_STREAM2MMIO__ +#endif + +#include "ia_css_debug.h" +#include "ia_css_debug_pipe.h" +#include "ia_css_irq.h" +#include "ia_css_stream.h" +#include "ia_css_pipeline.h" +#include "ia_css_isp_param.h" +#include "sh_css_params.h" +#include "ia_css_bufq.h" +#ifdef ISP2401 +#include "ia_css_queue.h" +#endif + +#include "ia_css_isp_params.h" + +#include "system_local.h" +#include "assert_support.h" +#include "print_support.h" +#include "string_support.h" +#ifdef ISP2401 +#include "ia_css_system_ctrl.h" +#endif + +#include "fifo_monitor.h" + +#if !defined(HAS_NO_INPUT_FORMATTER) +#include "input_formatter.h" +#endif +#include "dma.h" +#include "irq.h" +#include "gp_device.h" +#include "sp.h" +#include "isp.h" +#include "type_support.h" +#include "math_support.h" /* CEIL_DIV */ +#if defined(HAS_INPUT_FORMATTER_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) +#include "input_system.h" /* input_formatter_reg_load */ +#include "gp_device.h" /* gp_device_reg_load */ +#endif +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) +#include "ia_css_tagger_common.h" +#endif + +#include "sh_css_internal.h" +#if !defined(HAS_NO_INPUT_SYSTEM) +#include "ia_css_isys.h" +#endif +#include "sh_css_sp.h" /* sh_css_sp_get_debug_state() */ + +#include "css_trace.h" /* tracer */ + +#include "device_access.h" /* for ia_css_device_load_uint32 */ + +/* Include all kernel host interfaces for ISP1 */ +#include "anr/anr_1.0/ia_css_anr.host.h" +#include "cnr/cnr_1.0/ia_css_cnr.host.h" +#include "csc/csc_1.0/ia_css_csc.host.h" +#include "de/de_1.0/ia_css_de.host.h" +#include "dp/dp_1.0/ia_css_dp.host.h" +#include "bnr/bnr_1.0/ia_css_bnr.host.h" +#include "fpn/fpn_1.0/ia_css_fpn.host.h" +#include "gc/gc_1.0/ia_css_gc.host.h" +#include "ob/ob_1.0/ia_css_ob.host.h" +#include "s3a/s3a_1.0/ia_css_s3a.host.h" +#include "sc/sc_1.0/ia_css_sc.host.h" +#include "tnr/tnr_1.0/ia_css_tnr.host.h" +#include "uds/uds_1.0/ia_css_uds.host.h" +#include "wb/wb_1.0/ia_css_wb.host.h" +#include "ynr/ynr_1.0/ia_css_ynr.host.h" + +/* Include additional kernel host interfaces for ISP2 */ +#include "aa/aa_2/ia_css_aa2.host.h" +#include "anr/anr_2/ia_css_anr2.host.h" +#include "cnr/cnr_2/ia_css_cnr2.host.h" +#include "de/de_2/ia_css_de2.host.h" +#include "gc/gc_2/ia_css_gc2.host.h" +#include "ynr/ynr_2/ia_css_ynr2.host.h" + +/* Global variable to store the dtrace verbosity level */ +unsigned int ia_css_debug_trace_level = IA_CSS_DEBUG_WARNING; + +/* Assumes that IA_CSS_STREAM_FORMAT_BINARY_8 is last */ +#define N_IA_CSS_STREAM_FORMAT (IA_CSS_STREAM_FORMAT_BINARY_8+1) + +#define DPG_START "ia_css_debug_pipe_graph_dump_start " +#define DPG_END " ia_css_debug_pipe_graph_dump_end\n" + +#define ENABLE_LINE_MAX_LENGTH (25) + +#ifdef ISP2401 +#define DBG_EXT_CMD_TRACE_PNTS_DUMP (1 << 8) +#define DBG_EXT_CMD_PUB_CFG_DUMP (1 << 9) +#define DBG_EXT_CMD_GAC_REG_DUMP (1 << 10) +#define DBG_EXT_CMD_GAC_ACB_REG_DUMP (1 << 11) +#define DBG_EXT_CMD_FIFO_DUMP (1 << 12) +#define DBG_EXT_CMD_QUEUE_DUMP (1 << 13) +#define DBG_EXT_CMD_DMA_DUMP (1 << 14) +#define DBG_EXT_CMD_MASK 0xAB0000CD + +#endif +/* + * TODO:SH_CSS_MAX_SP_THREADS is not the max number of sp threads + * future rework should fix this and remove the define MAX_THREAD_NUM + */ +#define MAX_THREAD_NUM (SH_CSS_MAX_SP_THREADS + SH_CSS_MAX_SP_INTERNAL_THREADS) + +static struct pipe_graph_class { + bool do_init; + int height; + int width; + int eff_height; + int eff_width; + enum ia_css_stream_format stream_format; +} pg_inst = {true, 0, 0, 0, 0, N_IA_CSS_STREAM_FORMAT}; + +static const char * const queue_id_to_str[] = { + /* [SH_CSS_QUEUE_A_ID] =*/ "queue_A", + /* [SH_CSS_QUEUE_B_ID] =*/ "queue_B", + /* [SH_CSS_QUEUE_C_ID] =*/ "queue_C", + /* [SH_CSS_QUEUE_D_ID] =*/ "queue_D", + /* [SH_CSS_QUEUE_E_ID] =*/ "queue_E", + /* [SH_CSS_QUEUE_F_ID] =*/ "queue_F", + /* [SH_CSS_QUEUE_G_ID] =*/ "queue_G", + /* [SH_CSS_QUEUE_H_ID] =*/ "queue_H" +}; + +static const char * const pipe_id_to_str[] = { + /* [IA_CSS_PIPE_ID_PREVIEW] =*/ "preview", + /* [IA_CSS_PIPE_ID_COPY] =*/ "copy", + /* [IA_CSS_PIPE_ID_VIDEO] =*/ "video", + /* [IA_CSS_PIPE_ID_CAPTURE] =*/ "capture", + /* [IA_CSS_PIPE_ID_YUVPP] =*/ "yuvpp", + /* [IA_CSS_PIPE_ID_ACC] =*/ "accelerator" +}; + +static char dot_id_input_bin[SH_CSS_MAX_BINARY_NAME+10]; +static char ring_buffer[200]; + +void ia_css_debug_dtrace(unsigned int level, const char *fmt, ...) +{ + va_list ap; + + va_start(ap, fmt); + ia_css_debug_vdtrace(level, fmt, ap); + va_end(ap); +} + +#if !defined(C_RUN) && !defined(HRT_UNSCHED) +static void debug_dump_long_array_formatted( + const sp_ID_t sp_id, + hrt_address stack_sp_addr, + unsigned stack_size) +{ + unsigned int i; + uint32_t val; + uint32_t addr = (uint32_t) stack_sp_addr; + uint32_t stack_size_words = CEIL_DIV(stack_size, sizeof(uint32_t)); + + /* When size is not multiple of four, last word is only relevant for + * remaining bytes */ + for (i = 0; i < stack_size_words; i++) { + val = sp_dmem_load_uint32(sp_id, (hrt_address)addr); + if ((i%8) == 0) + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\n"); + + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "0x%08x ", val); + addr += sizeof(uint32_t); + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\n"); +} + +static void debug_dump_sp_stack_info( + const sp_ID_t sp_id) +{ + const struct ia_css_fw_info *fw; + unsigned int HIVE_ADDR_sp_threads_stack; + unsigned int HIVE_ADDR_sp_threads_stack_size; + uint32_t stack_sizes[MAX_THREAD_NUM]; + uint32_t stack_sp_addr[MAX_THREAD_NUM]; + unsigned int i; + + fw = &sh_css_sp_fw; + + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "sp_id(%u) stack info\n", sp_id); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "from objects stack_addr_offset:0x%x stack_size_offset:0x%x\n", + fw->info.sp.threads_stack, + fw->info.sp.threads_stack_size); + + HIVE_ADDR_sp_threads_stack = fw->info.sp.threads_stack; + HIVE_ADDR_sp_threads_stack_size = fw->info.sp.threads_stack_size; + + if (fw->info.sp.threads_stack == 0 || + fw->info.sp.threads_stack_size == 0) + return; + + (void) HIVE_ADDR_sp_threads_stack; + (void) HIVE_ADDR_sp_threads_stack_size; + + sp_dmem_load(sp_id, + (unsigned int)sp_address_of(sp_threads_stack), + &stack_sp_addr, sizeof(stack_sp_addr)); + sp_dmem_load(sp_id, + (unsigned int)sp_address_of(sp_threads_stack_size), + &stack_sizes, sizeof(stack_sizes)); + + for (i = 0 ; i < MAX_THREAD_NUM; i++) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "thread: %u stack_addr: 0x%08x stack_size: %u\n", + i, stack_sp_addr[i], stack_sizes[i]); + debug_dump_long_array_formatted(sp_id, (hrt_address)stack_sp_addr[i], + stack_sizes[i]); + } +} + +void ia_css_debug_dump_sp_stack_info(void) +{ + debug_dump_sp_stack_info(SP0_ID); +} +#else +/* Empty def for crun */ +void ia_css_debug_dump_sp_stack_info(void) +{ +} +#endif /* #if __HIVECC */ + + +void ia_css_debug_set_dtrace_level(const unsigned int trace_level) +{ + ia_css_debug_trace_level = trace_level; + return; +} + +unsigned int ia_css_debug_get_dtrace_level(void) +{ + return ia_css_debug_trace_level; +} + +static const char *debug_stream_format2str(const enum ia_css_stream_format stream_format) +{ + switch (stream_format) { + case IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY: + return "yuv420-8-legacy"; + case IA_CSS_STREAM_FORMAT_YUV420_8: + return "yuv420-8"; + case IA_CSS_STREAM_FORMAT_YUV420_10: + return "yuv420-10"; + case IA_CSS_STREAM_FORMAT_YUV420_16: + return "yuv420-16"; + case IA_CSS_STREAM_FORMAT_YUV422_8: + return "yuv422-8"; + case IA_CSS_STREAM_FORMAT_YUV422_10: + return "yuv422-10"; + case IA_CSS_STREAM_FORMAT_YUV422_16: + return "yuv422-16"; + case IA_CSS_STREAM_FORMAT_RGB_444: + return "rgb444"; + case IA_CSS_STREAM_FORMAT_RGB_555: + return "rgb555"; + case IA_CSS_STREAM_FORMAT_RGB_565: + return "rgb565"; + case IA_CSS_STREAM_FORMAT_RGB_666: + return "rgb666"; + case IA_CSS_STREAM_FORMAT_RGB_888: + return "rgb888"; + case IA_CSS_STREAM_FORMAT_RAW_6: + return "raw6"; + case IA_CSS_STREAM_FORMAT_RAW_7: + return "raw7"; + case IA_CSS_STREAM_FORMAT_RAW_8: + return "raw8"; + case IA_CSS_STREAM_FORMAT_RAW_10: + return "raw10"; + case IA_CSS_STREAM_FORMAT_RAW_12: + return "raw12"; + case IA_CSS_STREAM_FORMAT_RAW_14: + return "raw14"; + case IA_CSS_STREAM_FORMAT_RAW_16: + return "raw16"; + case IA_CSS_STREAM_FORMAT_BINARY_8: + return "binary8"; + case IA_CSS_STREAM_FORMAT_GENERIC_SHORT1: + return "generic-short1"; + case IA_CSS_STREAM_FORMAT_GENERIC_SHORT2: + return "generic-short2"; + case IA_CSS_STREAM_FORMAT_GENERIC_SHORT3: + return "generic-short3"; + case IA_CSS_STREAM_FORMAT_GENERIC_SHORT4: + return "generic-short4"; + case IA_CSS_STREAM_FORMAT_GENERIC_SHORT5: + return "generic-short5"; + case IA_CSS_STREAM_FORMAT_GENERIC_SHORT6: + return "generic-short6"; + case IA_CSS_STREAM_FORMAT_GENERIC_SHORT7: + return "generic-short7"; + case IA_CSS_STREAM_FORMAT_GENERIC_SHORT8: + return "generic-short8"; + case IA_CSS_STREAM_FORMAT_YUV420_8_SHIFT: + return "yuv420-8-shift"; + case IA_CSS_STREAM_FORMAT_YUV420_10_SHIFT: + return "yuv420-10-shift"; + case IA_CSS_STREAM_FORMAT_EMBEDDED: + return "embedded-8"; + case IA_CSS_STREAM_FORMAT_USER_DEF1: + return "user-def-8-type-1"; + case IA_CSS_STREAM_FORMAT_USER_DEF2: + return "user-def-8-type-2"; + case IA_CSS_STREAM_FORMAT_USER_DEF3: + return "user-def-8-type-3"; + case IA_CSS_STREAM_FORMAT_USER_DEF4: + return "user-def-8-type-4"; + case IA_CSS_STREAM_FORMAT_USER_DEF5: + return "user-def-8-type-5"; + case IA_CSS_STREAM_FORMAT_USER_DEF6: + return "user-def-8-type-6"; + case IA_CSS_STREAM_FORMAT_USER_DEF7: + return "user-def-8-type-7"; + case IA_CSS_STREAM_FORMAT_USER_DEF8: + return "user-def-8-type-8"; + + default: + assert(!"Unknown stream format"); + return "unknown-stream-format"; + } +}; + +static const char *debug_frame_format2str(const enum ia_css_frame_format frame_format) +{ + switch (frame_format) { + + case IA_CSS_FRAME_FORMAT_NV11: + return "NV11"; + case IA_CSS_FRAME_FORMAT_NV12: + return "NV12"; + case IA_CSS_FRAME_FORMAT_NV12_16: + return "NV12_16"; + case IA_CSS_FRAME_FORMAT_NV12_TILEY: + return "NV12_TILEY"; + case IA_CSS_FRAME_FORMAT_NV16: + return "NV16"; + case IA_CSS_FRAME_FORMAT_NV21: + return "NV21"; + case IA_CSS_FRAME_FORMAT_NV61: + return "NV61"; + case IA_CSS_FRAME_FORMAT_YV12: + return "YV12"; + case IA_CSS_FRAME_FORMAT_YV16: + return "YV16"; + case IA_CSS_FRAME_FORMAT_YUV420: + return "YUV420"; + case IA_CSS_FRAME_FORMAT_YUV420_16: + return "YUV420_16"; + case IA_CSS_FRAME_FORMAT_YUV422: + return "YUV422"; + case IA_CSS_FRAME_FORMAT_YUV422_16: + return "YUV422_16"; + case IA_CSS_FRAME_FORMAT_UYVY: + return "UYVY"; + case IA_CSS_FRAME_FORMAT_YUYV: + return "YUYV"; + case IA_CSS_FRAME_FORMAT_YUV444: + return "YUV444"; + case IA_CSS_FRAME_FORMAT_YUV_LINE: + return "YUV_LINE"; + case IA_CSS_FRAME_FORMAT_RAW: + return "RAW"; + case IA_CSS_FRAME_FORMAT_RGB565: + return "RGB565"; + case IA_CSS_FRAME_FORMAT_PLANAR_RGB888: + return "PLANAR_RGB888"; + case IA_CSS_FRAME_FORMAT_RGBA888: + return "RGBA888"; + case IA_CSS_FRAME_FORMAT_QPLANE6: + return "QPLANE6"; + case IA_CSS_FRAME_FORMAT_BINARY_8: + return "BINARY_8"; + case IA_CSS_FRAME_FORMAT_MIPI: + return "MIPI"; + case IA_CSS_FRAME_FORMAT_RAW_PACKED: + return "RAW_PACKED"; + case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8: + return "CSI_MIPI_YUV420_8"; + case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8: + return "CSI_MIPI_LEGACY_YUV420_8"; + case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_10: + return "CSI_MIPI_YUV420_10"; + + default: + assert(!"Unknown frame format"); + return "unknown-frame-format"; + } +} + +static void debug_print_sp_state(const sp_state_t *state, const char *cell) +{ + assert(cell != NULL); + assert(state != NULL); + + ia_css_debug_dtrace(2, "%s state:\n", cell); + ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "PC", state->pc); + ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "Status register", + state->status_register); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is broken", state->is_broken); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is idle", state->is_idle); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is sleeping", + state->is_sleeping); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is stalling", + state->is_stalling); + return; +} + +static void debug_print_isp_state(const isp_state_t *state, const char *cell) +{ + assert(state != NULL); + assert(cell != NULL); + + ia_css_debug_dtrace(2, "%s state:\n", cell); + ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "PC", state->pc); + ia_css_debug_dtrace(2, "\t%-32s: 0x%X\n", "Status register", + state->status_register); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is broken", state->is_broken); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is idle", state->is_idle); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is sleeping", + state->is_sleeping); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "Is stalling", + state->is_stalling); + return; +} + +void ia_css_debug_dump_isp_state(void) +{ + isp_state_t state; + isp_stall_t stall; + + isp_get_state(ISP0_ID, &state, &stall); + + debug_print_isp_state(&state, "ISP"); + + if (state.is_stalling) { +#if !defined(HAS_NO_INPUT_FORMATTER) + ia_css_debug_dtrace(2, "\t%-32s: %d\n", + "[0] if_prim_a_FIFO stalled", stall.fifo0); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", + "[1] if_prim_b_FIFO stalled", stall.fifo1); +#endif + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[2] dma_FIFO stalled", + stall.fifo2); +#if defined(HAS_ISP_2400_MAMOIADA) || defined(HAS_ISP_2401_MAMOIADA) || defined(IS_ISP_2500_SYSTEM) + + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[3] gdc0_FIFO stalled", + stall.fifo3); +#if !defined(IS_ISP_2500_SYSTEM) + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[4] gdc1_FIFO stalled", + stall.fifo4); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[5] gpio_FIFO stalled", + stall.fifo5); +#endif + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "[6] sp_FIFO stalled", + stall.fifo6); +#else +#error "ia_css_debug: ISP cell must be one of {2400_MAMOIADA,, 2401_MAMOIADA, 2500_SKYCAM}" +#endif + ia_css_debug_dtrace(2, "\t%-32s: %d\n", + "status & control stalled", + stall.stat_ctrl); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dmem stalled", + stall.dmem); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vmem stalled", + stall.vmem); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem1 stalled", + stall.vamem1); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem2 stalled", + stall.vamem2); +#if defined(HAS_ISP_2400_MAMOIADA) || defined(HAS_ISP_2401_MAMOIADA) + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "vamem3 stalled", + stall.vamem3); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "hmem stalled", + stall.hmem); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "pmem stalled", + stall.pmem); +#endif + } + return; +} + +void ia_css_debug_dump_sp_state(void) +{ + sp_state_t state; + sp_stall_t stall; + sp_get_state(SP0_ID, &state, &stall); + debug_print_sp_state(&state, "SP"); + if (state.is_stalling) { +#if defined(HAS_SP_2400) || defined(IS_ISP_2500_SYSTEM) +#if !defined(HAS_NO_INPUT_SYSTEM) + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "isys_FIFO stalled", + stall.fifo0); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "if_sec_FIFO stalled", + stall.fifo1); +#endif + ia_css_debug_dtrace(2, "\t%-32s: %d\n", + "str_to_mem_FIFO stalled", stall.fifo2); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dma_FIFO stalled", + stall.fifo3); +#if !defined(HAS_NO_INPUT_FORMATTER) + ia_css_debug_dtrace(2, "\t%-32s: %d\n", + "if_prim_a_FIFO stalled", stall.fifo4); +#endif + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "isp_FIFO stalled", + stall.fifo5); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gp_FIFO stalled", + stall.fifo6); +#if !defined(HAS_NO_INPUT_FORMATTER) + ia_css_debug_dtrace(2, "\t%-32s: %d\n", + "if_prim_b_FIFO stalled", stall.fifo7); +#endif + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gdc0_FIFO stalled", + stall.fifo8); +#if !defined(IS_ISP_2500_SYSTEM) + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "gdc1_FIFO stalled", + stall.fifo9); +#endif + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "irq FIFO stalled", + stall.fifoa); +#else +#error "ia_css_debug: SP cell must be one of {SP2400, SP2500}" +#endif + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "dmem stalled", + stall.dmem); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", + "control master stalled", + stall.control_master); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", + "i-cache master stalled", + stall.icache_master); + } + ia_css_debug_dump_trace(); + return; +} + +static void debug_print_fifo_channel_state(const fifo_channel_state_t *state, + const char *descr) +{ + assert(state != NULL); + assert(descr != NULL); + + ia_css_debug_dtrace(2, "FIFO channel: %s\n", descr); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "source valid", + state->src_valid); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "fifo accept", + state->fifo_accept); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "fifo valid", + state->fifo_valid); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "sink accept", + state->sink_accept); + return; +} + +#if !defined(HAS_NO_INPUT_FORMATTER) && defined(USE_INPUT_SYSTEM_VERSION_2) +void ia_css_debug_dump_pif_a_isp_fifo_state(void) +{ + fifo_channel_state_t pif_to_isp, isp_to_pif; + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_IF0_TO_ISP0, &pif_to_isp); + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_ISP0_TO_IF0, &isp_to_pif); + debug_print_fifo_channel_state(&pif_to_isp, "Primary IF A to ISP"); + debug_print_fifo_channel_state(&isp_to_pif, "ISP to Primary IF A"); +} + +void ia_css_debug_dump_pif_b_isp_fifo_state(void) +{ + fifo_channel_state_t pif_to_isp, isp_to_pif; + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_IF1_TO_ISP0, &pif_to_isp); + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_ISP0_TO_IF1, &isp_to_pif); + debug_print_fifo_channel_state(&pif_to_isp, "Primary IF B to ISP"); + debug_print_fifo_channel_state(&isp_to_pif, "ISP to Primary IF B"); +} + +void ia_css_debug_dump_str2mem_sp_fifo_state(void) +{ + fifo_channel_state_t s2m_to_sp, sp_to_s2m; + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_STREAM2MEM0_TO_SP0, &s2m_to_sp); + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_SP0_TO_STREAM2MEM0, &sp_to_s2m); + debug_print_fifo_channel_state(&s2m_to_sp, "Stream-to-memory to SP"); + debug_print_fifo_channel_state(&sp_to_s2m, "SP to stream-to-memory"); +} + +static void debug_print_if_state(input_formatter_state_t *state, const char *id) +{ + unsigned int val; + +#if defined(HAS_INPUT_FORMATTER_VERSION_1) + const char *st_reset = (state->reset ? "Active" : "Not active"); +#endif + const char *st_vsync_active_low = + (state->vsync_active_low ? "low" : "high"); + const char *st_hsync_active_low = + (state->hsync_active_low ? "low" : "high"); + + const char *fsm_sync_status_str = "unknown"; + const char *fsm_crop_status_str = "unknown"; + const char *fsm_padding_status_str = "unknown"; + + int st_stline = state->start_line; + int st_stcol = state->start_column; + int st_crpht = state->cropped_height; + int st_crpwd = state->cropped_width; + int st_verdcm = state->ver_decimation; + int st_hordcm = state->hor_decimation; + int st_ver_deinterleaving = state->ver_deinterleaving; + int st_hor_deinterleaving = state->hor_deinterleaving; + int st_leftpd = state->left_padding; + int st_eoloff = state->eol_offset; + int st_vmstartaddr = state->vmem_start_address; + int st_vmendaddr = state->vmem_end_address; + int st_vmincr = state->vmem_increment; + int st_yuv420 = state->is_yuv420; + int st_allow_fifo_overflow = state->allow_fifo_overflow; + int st_block_fifo_when_no_req = state->block_fifo_when_no_req; + + assert(state != NULL); + ia_css_debug_dtrace(2, "InputFormatter State (%s):\n", id); + + ia_css_debug_dtrace(2, "\tConfiguration:\n"); + +#if defined(HAS_INPUT_FORMATTER_VERSION_1) + ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "Software reset", st_reset); +#endif + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Start line", st_stline); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Start column", st_stcol); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropped height", st_crpht); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropped width", st_crpwd); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Ver decimation", st_verdcm); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Hor decimation", st_hordcm); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Ver deinterleaving", st_ver_deinterleaving); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Hor deinterleaving", st_hor_deinterleaving); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Left padding", st_leftpd); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "EOL offset (bytes)", st_eoloff); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n", + "VMEM start address", st_vmstartaddr); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n", + "VMEM end address", st_vmendaddr); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%06X\n", + "VMEM increment", st_vmincr); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "YUV 420 format", st_yuv420); + ia_css_debug_dtrace(2, "\t\t%-32s: Active %s\n", + "Vsync", st_vsync_active_low); + ia_css_debug_dtrace(2, "\t\t%-32s: Active %s\n", + "Hsync", st_hsync_active_low); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Allow FIFO overflow", st_allow_fifo_overflow); +/* Flag that tells whether the IF gives backpressure on frames */ +/* + * FYI, this is only on the frame request (indicate), when the IF has + * synch'd on a frame it will always give back pressure + */ + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Block when no request", st_block_fifo_when_no_req); + +#if defined(HAS_INPUT_FORMATTER_VERSION_2) + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "IF_BLOCKED_FIFO_NO_REQ_ADDRESS", + input_formatter_reg_load(INPUT_FORMATTER0_ID, + HIVE_IF_BLOCK_FIFO_NO_REQ_ADDRESS) + ); + + ia_css_debug_dtrace(2, "\t%-32s:\n", "InputSwitch State"); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_input_switch_lut_reg0", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg0)); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_input_switch_lut_reg1", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg1)); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_input_switch_lut_reg2", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg2)); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_input_switch_lut_reg3", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg3)); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_input_switch_lut_reg4", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg4)); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_input_switch_lut_reg5", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg5)); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_input_switch_lut_reg6", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg6)); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_input_switch_lut_reg7", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_lut_reg7)); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_input_switch_fsync_lut", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_input_switch_fsync_lut)); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_srst", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_srst)); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "_REG_GP_IFMT_slv_reg_srst", + gp_device_reg_load(GP_DEVICE0_ID, + _REG_GP_IFMT_slv_reg_srst)); +#endif + + ia_css_debug_dtrace(2, "\tFSM Status:\n"); + + val = state->fsm_sync_status; + + if (val > 7) + fsm_sync_status_str = "ERROR"; + + switch (val & 0x7) { + case 0: + fsm_sync_status_str = "idle"; + break; + case 1: + fsm_sync_status_str = "request frame"; + break; + case 2: + fsm_sync_status_str = "request lines"; + break; + case 3: + fsm_sync_status_str = "request vectors"; + break; + case 4: + fsm_sync_status_str = "send acknowledge"; + break; + default: + fsm_sync_status_str = "unknown"; + break; + } + + ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n", + "FSM Synchronization Status", val, + fsm_sync_status_str); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "FSM Synchronization Counter", + state->fsm_sync_counter); + + val = state->fsm_crop_status; + + if (val > 7) + fsm_crop_status_str = "ERROR"; + + switch (val & 0x7) { + case 0: + fsm_crop_status_str = "idle"; + break; + case 1: + fsm_crop_status_str = "wait line"; + break; + case 2: + fsm_crop_status_str = "crop line"; + break; + case 3: + fsm_crop_status_str = "crop pixel"; + break; + case 4: + fsm_crop_status_str = "pass pixel"; + break; + case 5: + fsm_crop_status_str = "pass line"; + break; + case 6: + fsm_crop_status_str = "lost line"; + break; + default: + fsm_crop_status_str = "unknown"; + break; + } + ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n", + "FSM Crop Status", val, fsm_crop_status_str); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "FSM Crop Line Counter", + state->fsm_crop_line_counter); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "FSM Crop Pixel Counter", + state->fsm_crop_pixel_counter); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "FSM Deinterleaving idx buffer", + state->fsm_deinterleaving_index); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "FSM H decimation counter", + state->fsm_dec_h_counter); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "FSM V decimation counter", + state->fsm_dec_v_counter); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "FSM block V decimation counter", + state->fsm_dec_block_v_counter); + + val = state->fsm_padding_status; + + if (val > 7) + fsm_padding_status_str = "ERROR"; + + switch (val & 0x7) { + case 0: + fsm_padding_status_str = "idle"; + break; + case 1: + fsm_padding_status_str = "left pad"; + break; + case 2: + fsm_padding_status_str = "write"; + break; + case 3: + fsm_padding_status_str = "right pad"; + break; + case 4: + fsm_padding_status_str = "send end of line"; + break; + default: + fsm_padding_status_str = "unknown"; + break; + } + + ia_css_debug_dtrace(2, "\t\t%-32s: (0x%X: %s)\n", "FSM Padding Status", + val, fsm_padding_status_str); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "FSM Padding element idx counter", + state->fsm_padding_elem_counter); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support error", + state->fsm_vector_support_error); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support buf full", + state->fsm_vector_buffer_full); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Vector support", + state->vector_support); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Fifo sensor data lost", + state->sensor_data_lost); + return; +} + +static void debug_print_if_bin_state(input_formatter_bin_state_t *state) +{ + ia_css_debug_dtrace(2, "Stream-to-memory state:\n"); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "reset", state->reset); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "input endianness", + state->input_endianness); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "output endianness", + state->output_endianness); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "bitswap", state->bitswap); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "block_synch", + state->block_synch); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "packet_synch", + state->packet_synch); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "readpostwrite_sync", + state->readpostwrite_synch); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "is_2ppc", state->is_2ppc); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "en_status_update", + state->en_status_update); +} + +void ia_css_debug_dump_if_state(void) +{ + input_formatter_state_t if_state; + input_formatter_bin_state_t if_bin_state; + + input_formatter_get_state(INPUT_FORMATTER0_ID, &if_state); + debug_print_if_state(&if_state, "Primary IF A"); + ia_css_debug_dump_pif_a_isp_fifo_state(); + + input_formatter_get_state(INPUT_FORMATTER1_ID, &if_state); + debug_print_if_state(&if_state, "Primary IF B"); + ia_css_debug_dump_pif_b_isp_fifo_state(); + + input_formatter_bin_get_state(INPUT_FORMATTER3_ID, &if_bin_state); + debug_print_if_bin_state(&if_bin_state); + ia_css_debug_dump_str2mem_sp_fifo_state(); +} +#endif + +void ia_css_debug_dump_dma_state(void) +{ + /* note: the var below is made static as it is quite large; + if it is not static it ends up on the stack which could + cause issues for drivers + */ + static dma_state_t state; + int i, ch_id; + + const char *fsm_cmd_st_lbl = "FSM Command flag state"; + const char *fsm_ctl_st_lbl = "FSM Control flag state"; + const char *fsm_ctl_state = NULL; + const char *fsm_ctl_flag = NULL; + const char *fsm_pack_st = NULL; + const char *fsm_read_st = NULL; + const char *fsm_write_st = NULL; + char last_cmd_str[64]; + + dma_get_state(DMA0_ID, &state); + /* Print header for DMA dump status */ + ia_css_debug_dtrace(2, "DMA dump status:\n"); + + /* Print FSM command flag state */ + if (state.fsm_command_idle) + ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, "IDLE"); + if (state.fsm_command_run) + ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, "RUN"); + if (state.fsm_command_stalling) + ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, + "STALL"); + if (state.fsm_command_error) + ia_css_debug_dtrace(2, "\t%-32s: %s\n", fsm_cmd_st_lbl, + "ERROR"); + + /* Print last command along with the channel */ + ch_id = state.last_command_channel; + + switch (state.last_command) { + case DMA_COMMAND_READ: + snprintf(last_cmd_str, 64, + "Read 2D Block [Channel: %d]", ch_id); + break; + case DMA_COMMAND_WRITE: + snprintf(last_cmd_str, 64, + "Write 2D Block [Channel: %d]", ch_id); + break; + case DMA_COMMAND_SET_CHANNEL: + snprintf(last_cmd_str, 64, "Set Channel [Channel: %d]", ch_id); + break; + case DMA_COMMAND_SET_PARAM: + snprintf(last_cmd_str, 64, + "Set Param: %d [Channel: %d]", + state.last_command_param, ch_id); + break; + case DMA_COMMAND_READ_SPECIFIC: + snprintf(last_cmd_str, 64, + "Read Specific 2D Block [Channel: %d]", ch_id); + break; + case DMA_COMMAND_WRITE_SPECIFIC: + snprintf(last_cmd_str, 64, + "Write Specific 2D Block [Channel: %d]", ch_id); + break; + case DMA_COMMAND_INIT: + snprintf(last_cmd_str, 64, + "Init 2D Block on Device A [Channel: %d]", ch_id); + break; + case DMA_COMMAND_INIT_SPECIFIC: + snprintf(last_cmd_str, 64, + "Init Specific 2D Block [Channel: %d]", ch_id); + break; + case DMA_COMMAND_RST: + snprintf(last_cmd_str, 64, "DMA SW Reset"); + break; + case N_DMA_COMMANDS: + snprintf(last_cmd_str, 64, "UNKNOWN"); + break; + default: + snprintf(last_cmd_str, 64, + "unknown [Channel: %d]", ch_id); + break; + } + ia_css_debug_dtrace(2, "\t%-32s: (0x%X : %s)\n", + "last command received", state.last_command, + last_cmd_str); + + /* Print DMA registers */ + ia_css_debug_dtrace(2, "\t%-32s\n", + "DMA registers, connection group 0"); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Command", + state.current_command); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Address A", + state.current_addr_a); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Cmd Fifo Address B", + state.current_addr_b); + + if (state.fsm_ctrl_idle) + fsm_ctl_flag = "IDLE"; + else if (state.fsm_ctrl_run) + fsm_ctl_flag = "RUN"; + else if (state.fsm_ctrl_stalling) + fsm_ctl_flag = "STAL"; + else if (state.fsm_ctrl_error) + fsm_ctl_flag = "ERROR"; + else + fsm_ctl_flag = "UNKNOWN"; + + switch (state.fsm_ctrl_state) { + case DMA_CTRL_STATE_IDLE: + fsm_ctl_state = "Idle state"; + break; + case DMA_CTRL_STATE_REQ_RCV: + fsm_ctl_state = "Req Rcv state"; + break; + case DMA_CTRL_STATE_RCV: + fsm_ctl_state = "Rcv state"; + break; + case DMA_CTRL_STATE_RCV_REQ: + fsm_ctl_state = "Rcv Req state"; + break; + case DMA_CTRL_STATE_INIT: + fsm_ctl_state = "Init state"; + break; + case N_DMA_CTRL_STATES: + fsm_ctl_state = "Unknown"; + break; + } + + ia_css_debug_dtrace(2, "\t\t%-32s: %s -> %s\n", fsm_ctl_st_lbl, + fsm_ctl_flag, fsm_ctl_state); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source dev", + state.fsm_ctrl_source_dev); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl source addr", + state.fsm_ctrl_source_addr); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl source stride", + state.fsm_ctrl_source_stride); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source width", + state.fsm_ctrl_source_width); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl source height", + state.fsm_ctrl_source_height); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source dev", + state.fsm_ctrl_pack_source_dev); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest dev", + state.fsm_ctrl_pack_dest_dev); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl dest addr", + state.fsm_ctrl_dest_addr); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "FSM Ctrl dest stride", + state.fsm_ctrl_dest_stride); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source width", + state.fsm_ctrl_pack_source_width); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest height", + state.fsm_ctrl_pack_dest_height); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest width", + state.fsm_ctrl_pack_dest_width); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack source elems", + state.fsm_ctrl_pack_source_elems); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack dest elems", + state.fsm_ctrl_pack_dest_elems); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Ctrl pack extension", + state.fsm_ctrl_pack_extension); + + if (state.pack_idle) + fsm_pack_st = "IDLE"; + if (state.pack_run) + fsm_pack_st = "RUN"; + if (state.pack_stalling) + fsm_pack_st = "STALL"; + if (state.pack_error) + fsm_pack_st = "ERROR"; + + ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Pack flag state", + fsm_pack_st); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack cnt height", + state.pack_cnt_height); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack src cnt width", + state.pack_src_cnt_width); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Pack dest cnt width", + state.pack_dest_cnt_width); + + if (state.read_state == DMA_RW_STATE_IDLE) + fsm_read_st = "Idle state"; + if (state.read_state == DMA_RW_STATE_REQ) + fsm_read_st = "Req state"; + if (state.read_state == DMA_RW_STATE_NEXT_LINE) + fsm_read_st = "Next line"; + if (state.read_state == DMA_RW_STATE_UNLOCK_CHANNEL) + fsm_read_st = "Unlock channel"; + + ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Read state", + fsm_read_st); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Read cnt height", + state.read_cnt_height); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Read cnt width", + state.read_cnt_width); + + if (state.write_state == DMA_RW_STATE_IDLE) + fsm_write_st = "Idle state"; + if (state.write_state == DMA_RW_STATE_REQ) + fsm_write_st = "Req state"; + if (state.write_state == DMA_RW_STATE_NEXT_LINE) + fsm_write_st = "Next line"; + if (state.write_state == DMA_RW_STATE_UNLOCK_CHANNEL) + fsm_write_st = "Unlock channel"; + + ia_css_debug_dtrace(2, "\t\t%-32s: %s\n", "FSM Write state", + fsm_write_st); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Write height", + state.write_height); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "FSM Write width", + state.write_width); + + for (i = 0; i < HIVE_ISP_NUM_DMA_CONNS; i++) { + dma_port_state_t *port = &(state.port_states[i]); + ia_css_debug_dtrace(2, "\tDMA device interface %d\n", i); + ia_css_debug_dtrace(2, "\t\tDMA internal side state\n"); + ia_css_debug_dtrace(2, + "\t\t\tCS:%d - We_n:%d - Run:%d - Ack:%d\n", + port->req_cs, port->req_we_n, port->req_run, + port->req_ack); + ia_css_debug_dtrace(2, "\t\tMaster Output side state\n"); + ia_css_debug_dtrace(2, + "\t\t\tCS:%d - We_n:%d - Run:%d - Ack:%d\n", + port->send_cs, port->send_we_n, + port->send_run, port->send_ack); + ia_css_debug_dtrace(2, "\t\tFifo state\n"); + if (port->fifo_state == DMA_FIFO_STATE_WILL_BE_FULL) + ia_css_debug_dtrace(2, "\t\t\tFiFo will be full\n"); + else if (port->fifo_state == DMA_FIFO_STATE_FULL) + ia_css_debug_dtrace(2, "\t\t\tFifo Full\n"); + else if (port->fifo_state == DMA_FIFO_STATE_EMPTY) + ia_css_debug_dtrace(2, "\t\t\tFifo Empty\n"); + else + ia_css_debug_dtrace(2, "\t\t\tFifo state unknown\n"); + + ia_css_debug_dtrace(2, "\t\tFifo counter %d\n\n", + port->fifo_counter); + } + + for (i = 0; i < HIVE_DMA_NUM_CHANNELS; i++) { + dma_channel_state_t *ch = &(state.channel_states[i]); + ia_css_debug_dtrace(2, "\t%-32s: %d\n", "DMA channel register", + i); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Connection", + ch->connection); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Sign extend", + ch->sign_extend); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Stride Dev A", + ch->stride_a); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Elems Dev A", + ch->elems_a); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropping Dev A", + ch->cropping_a); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Width Dev A", + ch->width_a); + ia_css_debug_dtrace(2, "\t\t%-32s: 0x%X\n", "Stride Dev B", + ch->stride_b); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Elems Dev B", + ch->elems_b); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Cropping Dev B", + ch->cropping_b); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Width Dev B", + ch->width_b); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "Height", ch->height); + } + ia_css_debug_dtrace(2, "\n"); + return; +} + +void ia_css_debug_dump_dma_sp_fifo_state(void) +{ + fifo_channel_state_t dma_to_sp, sp_to_dma; + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_DMA0_TO_SP0, &dma_to_sp); + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_SP0_TO_DMA0, &sp_to_dma); + debug_print_fifo_channel_state(&dma_to_sp, "DMA to SP"); + debug_print_fifo_channel_state(&sp_to_dma, "SP to DMA"); + return; +} + +void ia_css_debug_dump_dma_isp_fifo_state(void) +{ + fifo_channel_state_t dma_to_isp, isp_to_dma; + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_DMA0_TO_ISP0, &dma_to_isp); + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_ISP0_TO_DMA0, &isp_to_dma); + debug_print_fifo_channel_state(&dma_to_isp, "DMA to ISP"); + debug_print_fifo_channel_state(&isp_to_dma, "ISP to DMA"); + return; +} + +void ia_css_debug_dump_isp_sp_fifo_state(void) +{ + fifo_channel_state_t sp_to_isp, isp_to_sp; + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_SP0_TO_ISP0, &sp_to_isp); + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_ISP0_TO_SP0, &isp_to_sp); + debug_print_fifo_channel_state(&sp_to_isp, "SP to ISP"); + debug_print_fifo_channel_state(&isp_to_sp, "ISP to SP"); + return; +} + +void ia_css_debug_dump_isp_gdc_fifo_state(void) +{ + fifo_channel_state_t gdc_to_isp, isp_to_gdc; + + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_GDC0_TO_ISP0, &gdc_to_isp); + fifo_channel_get_state(FIFO_MONITOR0_ID, + FIFO_CHANNEL_ISP0_TO_GDC0, &isp_to_gdc); + debug_print_fifo_channel_state(&gdc_to_isp, "GDC to ISP"); + debug_print_fifo_channel_state(&isp_to_gdc, "ISP to GDC"); + return; +} + +void ia_css_debug_dump_all_fifo_state(void) +{ + int i; + fifo_monitor_state_t state; + fifo_monitor_get_state(FIFO_MONITOR0_ID, &state); + + for (i = 0; i < N_FIFO_CHANNEL; i++) + debug_print_fifo_channel_state(&(state.fifo_channels[i]), + "squepfstqkt"); + return; +} + +static void debug_binary_info_print(const struct ia_css_binary_xinfo *info) +{ + assert(info != NULL); + ia_css_debug_dtrace(2, "id = %d\n", info->sp.id); + ia_css_debug_dtrace(2, "mode = %d\n", info->sp.pipeline.mode); + ia_css_debug_dtrace(2, "max_input_width = %d\n", info->sp.input.max_width); + ia_css_debug_dtrace(2, "min_output_width = %d\n", + info->sp.output.min_width); + ia_css_debug_dtrace(2, "max_output_width = %d\n", + info->sp.output.max_width); + ia_css_debug_dtrace(2, "top_cropping = %d\n", info->sp.pipeline.top_cropping); + ia_css_debug_dtrace(2, "left_cropping = %d\n", info->sp.pipeline.left_cropping); + ia_css_debug_dtrace(2, "xmem_addr = %d\n", info->xmem_addr); + ia_css_debug_dtrace(2, "enable_vf_veceven = %d\n", + info->sp.enable.vf_veceven); + ia_css_debug_dtrace(2, "enable_dis = %d\n", info->sp.enable.dis); + ia_css_debug_dtrace(2, "enable_uds = %d\n", info->sp.enable.uds); + ia_css_debug_dtrace(2, "enable ds = %d\n", info->sp.enable.ds); + ia_css_debug_dtrace(2, "s3atbl_use_dmem = %d\n", info->sp.s3a.s3atbl_use_dmem); + return; +} + +void ia_css_debug_binary_print(const struct ia_css_binary *bi) +{ + unsigned int i; + debug_binary_info_print(bi->info); + ia_css_debug_dtrace(2, + "input: %dx%d, format = %d, padded width = %d\n", + bi->in_frame_info.res.width, + bi->in_frame_info.res.height, + bi->in_frame_info.format, + bi->in_frame_info.padded_width); + ia_css_debug_dtrace(2, + "internal :%dx%d, format = %d, padded width = %d\n", + bi->internal_frame_info.res.width, + bi->internal_frame_info.res.height, + bi->internal_frame_info.format, + bi->internal_frame_info.padded_width); + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + if (bi->out_frame_info[i].res.width != 0) { + ia_css_debug_dtrace(2, + "out%d: %dx%d, format = %d, padded width = %d\n", + i, + bi->out_frame_info[i].res.width, + bi->out_frame_info[i].res.height, + bi->out_frame_info[i].format, + bi->out_frame_info[i].padded_width); + } + } + ia_css_debug_dtrace(2, + "vf out: %dx%d, format = %d, padded width = %d\n", + bi->vf_frame_info.res.width, + bi->vf_frame_info.res.height, + bi->vf_frame_info.format, + bi->vf_frame_info.padded_width); + ia_css_debug_dtrace(2, "online = %d\n", bi->online); + ia_css_debug_dtrace(2, "input_buf_vectors = %d\n", + bi->input_buf_vectors); + ia_css_debug_dtrace(2, "deci_factor_log2 = %d\n", bi->deci_factor_log2); + ia_css_debug_dtrace(2, "vf_downscale_log2 = %d\n", + bi->vf_downscale_log2); + ia_css_debug_dtrace(2, "dis_deci_factor_log2 = %d\n", + bi->dis.deci_factor_log2); + ia_css_debug_dtrace(2, "dis hor coef num = %d\n", + bi->dis.coef.pad.width); + ia_css_debug_dtrace(2, "dis ver coef num = %d\n", + bi->dis.coef.pad.height); + ia_css_debug_dtrace(2, "dis hor proj num = %d\n", + bi->dis.proj.pad.height); + ia_css_debug_dtrace(2, "sctbl_width_per_color = %d\n", + bi->sctbl_width_per_color); + ia_css_debug_dtrace(2, "s3atbl_width = %d\n", bi->s3atbl_width); + ia_css_debug_dtrace(2, "s3atbl_height = %d\n", bi->s3atbl_height); + return; +} + +void ia_css_debug_frame_print(const struct ia_css_frame *frame, + const char *descr) +{ + char *data = NULL; + + assert(frame != NULL); + assert(descr != NULL); + + data = (char *)HOST_ADDRESS(frame->data); + ia_css_debug_dtrace(2, "frame %s (%p):\n", descr, frame); + ia_css_debug_dtrace(2, " resolution = %dx%d\n", + frame->info.res.width, frame->info.res.height); + ia_css_debug_dtrace(2, " padded width = %d\n", + frame->info.padded_width); + ia_css_debug_dtrace(2, " format = %d\n", frame->info.format); + ia_css_debug_dtrace(2, " is contiguous = %s\n", + frame->contiguous ? "yes" : "no"); + switch (frame->info.format) { + case IA_CSS_FRAME_FORMAT_NV12: + case IA_CSS_FRAME_FORMAT_NV16: + case IA_CSS_FRAME_FORMAT_NV21: + case IA_CSS_FRAME_FORMAT_NV61: + ia_css_debug_dtrace(2, " Y = %p\n", + data + frame->planes.nv.y.offset); + ia_css_debug_dtrace(2, " UV = %p\n", + data + frame->planes.nv.uv.offset); + break; + case IA_CSS_FRAME_FORMAT_YUYV: + case IA_CSS_FRAME_FORMAT_UYVY: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8: + case IA_CSS_FRAME_FORMAT_YUV_LINE: + ia_css_debug_dtrace(2, " YUYV = %p\n", + data + frame->planes.yuyv.offset); + break; + case IA_CSS_FRAME_FORMAT_YUV420: + case IA_CSS_FRAME_FORMAT_YUV422: + case IA_CSS_FRAME_FORMAT_YUV444: + case IA_CSS_FRAME_FORMAT_YV12: + case IA_CSS_FRAME_FORMAT_YV16: + case IA_CSS_FRAME_FORMAT_YUV420_16: + case IA_CSS_FRAME_FORMAT_YUV422_16: + ia_css_debug_dtrace(2, " Y = %p\n", + data + frame->planes.yuv.y.offset); + ia_css_debug_dtrace(2, " U = %p\n", + data + frame->planes.yuv.u.offset); + ia_css_debug_dtrace(2, " V = %p\n", + data + frame->planes.yuv.v.offset); + break; + case IA_CSS_FRAME_FORMAT_RAW_PACKED: + ia_css_debug_dtrace(2, " RAW PACKED = %p\n", + data + frame->planes.raw.offset); + break; + case IA_CSS_FRAME_FORMAT_RAW: + ia_css_debug_dtrace(2, " RAW = %p\n", + data + frame->planes.raw.offset); + break; + case IA_CSS_FRAME_FORMAT_RGBA888: + case IA_CSS_FRAME_FORMAT_RGB565: + ia_css_debug_dtrace(2, " RGB = %p\n", + data + frame->planes.rgb.offset); + break; + case IA_CSS_FRAME_FORMAT_QPLANE6: + ia_css_debug_dtrace(2, " R = %p\n", + data + frame->planes.plane6.r.offset); + ia_css_debug_dtrace(2, " RatB = %p\n", + data + frame->planes.plane6.r_at_b.offset); + ia_css_debug_dtrace(2, " Gr = %p\n", + data + frame->planes.plane6.gr.offset); + ia_css_debug_dtrace(2, " Gb = %p\n", + data + frame->planes.plane6.gb.offset); + ia_css_debug_dtrace(2, " B = %p\n", + data + frame->planes.plane6.b.offset); + ia_css_debug_dtrace(2, " BatR = %p\n", + data + frame->planes.plane6.b_at_r.offset); + break; + case IA_CSS_FRAME_FORMAT_BINARY_8: + ia_css_debug_dtrace(2, " Binary data = %p\n", + data + frame->planes.binary.data.offset); + break; + default: + ia_css_debug_dtrace(2, " unknown frame type\n"); + break; + } + return; +} + +#if SP_DEBUG != SP_DEBUG_NONE + +void ia_css_debug_print_sp_debug_state(const struct sh_css_sp_debug_state + *state) +{ + +#endif + +#if SP_DEBUG == SP_DEBUG_DUMP + + assert(state != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "current SP software counter: %d\n", + state->debug[0]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty output buffer queue head: 0x%x\n", + state->debug[1]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty output buffer queue tail: 0x%x\n", + state->debug[2]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty s3a buffer queue head: 0x%x\n", + state->debug[3]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty s3a buffer queue tail: 0x%x\n", + state->debug[4]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "full output buffer queue head: 0x%x\n", + state->debug[5]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "full output buffer queue tail: 0x%x\n", + state->debug[6]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "full s3a buffer queue head: 0x%x\n", + state->debug[7]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "full s3a buffer queue tail: 0x%x\n", + state->debug[8]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "event queue head: 0x%x\n", + state->debug[9]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "event queue tail: 0x%x\n", + state->debug[10]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "num of stages of current pipeline: 0x%x\n", + state->debug[11]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "DDR address of stage 1: 0x%x\n", + state->debug[12]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "DDR address of stage 2: 0x%x\n", + state->debug[13]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "current stage out_vf buffer idx: 0x%x\n", + state->debug[14]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "current stage output buffer idx: 0x%x\n", + state->debug[15]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "current stage s3a buffer idx: 0x%x\n", + state->debug[16]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "first char of current stage name: 0x%x\n", + state->debug[17]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "current SP thread id: 0x%x\n", + state->debug[18]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty output buffer address 1: 0x%x\n", + state->debug[19]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty output buffer address 2: 0x%x\n", + state->debug[20]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty out_vf buffer address 1: 0x%x\n", + state->debug[21]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty out_vf buffer address 2: 0x%x\n", + state->debug[22]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty s3a_hi buffer address 1: 0x%x\n", + state->debug[23]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty s3a_hi buffer address 2: 0x%x\n", + state->debug[24]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty s3a_lo buffer address 1: 0x%x\n", + state->debug[25]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty s3a_lo buffer address 2: 0x%x\n", + state->debug[26]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty dis_hor buffer address 1: 0x%x\n", + state->debug[27]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty dis_hor buffer address 2: 0x%x\n", + state->debug[28]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty dis_ver buffer address 1: 0x%x\n", + state->debug[29]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty dis_ver buffer address 2: 0x%x\n", + state->debug[30]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "empty param buffer address: 0x%x\n", + state->debug[31]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "first incorrect frame address: 0x%x\n", + state->debug[32]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "first incorrect frame container address: 0x%x\n", + state->debug[33]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "first incorrect frame container payload: 0x%x\n", + state->debug[34]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "first incorrect s3a_hi address: 0x%x\n", + state->debug[35]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "first incorrect s3a_hi container address: 0x%x\n", + state->debug[36]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "first incorrect s3a_hi container payload: 0x%x\n", + state->debug[37]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "first incorrect s3a_lo address: 0x%x\n", + state->debug[38]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "first incorrect s3a_lo container address: 0x%x\n", + state->debug[39]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "first incorrect s3a_lo container payload: 0x%x\n", + state->debug[40]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "number of calling flash start function: 0x%x\n", + state->debug[41]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "number of calling flash close function: 0x%x\n", + state->debug[42]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "number of flashed frame: 0x%x\n", + state->debug[43]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "flash in use flag: 0x%x\n", + state->debug[44]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "number of update frame flashed flag: 0x%x\n", + state->debug[46]); + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "number of active threads: 0x%x\n", + state->debug[45]); + +#elif SP_DEBUG == SP_DEBUG_COPY + + /* Remember last_index because we only want to print new entries */ + static int last_index; + int sp_index = state->index; + int n; + + assert(state != NULL); + if (sp_index < last_index) { + /* SP has been reset */ + last_index = 0; + } + + if (last_index == 0) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "copy-trace init: sp_dbg_if_start_line=%d, " + "sp_dbg_if_start_column=%d, " + "sp_dbg_if_cropped_height=%d, " + "sp_debg_if_cropped_width=%d\n", + state->if_start_line, + state->if_start_column, + state->if_cropped_height, + state->if_cropped_width); + } + + if ((last_index + SH_CSS_SP_DBG_TRACE_DEPTH) < sp_index) { + /* last index can be multiple rounds behind */ + /* while trace size is only SH_CSS_SP_DBG_TRACE_DEPTH */ + last_index = sp_index - SH_CSS_SP_DBG_TRACE_DEPTH; + } + + for (n = last_index; n < sp_index; n++) { + int i = n % SH_CSS_SP_DBG_TRACE_DEPTH; + if (state->trace[i].frame != 0) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "copy-trace: frame=%d, line=%d, " + "pixel_distance=%d, " + "mipi_used_dword=%d, " + "sp_index=%d\n", + state->trace[i].frame, + state->trace[i].line, + state->trace[i].pixel_distance, + state->trace[i].mipi_used_dword, + state->trace[i].sp_index); + } + } + + last_index = sp_index; + +#elif SP_DEBUG == SP_DEBUG_TRACE + +/** + * This is just an example how TRACE_FILE_ID (see ia_css_debug.sp.h) will + * me mapped on the file name string. + * + * Adjust this to your trace case! + */ + static char const * const id2filename[8] = { + "param_buffer.sp.c | tagger.sp.c | pipe_data.sp.c", + "isp_init.sp.c", + "sp_raw_copy.hive.c", + "dma_configure.sp.c", + "sp.hive.c", + "event_proxy_sp.hive.c", + "circular_buffer.sp.c", + "frame_buffer.sp.c" + }; + +#if 1 + /* Example SH_CSS_SP_DBG_NR_OF_TRACES==1 */ + /* Adjust this to your trace case */ + static char const *trace_name[SH_CSS_SP_DBG_NR_OF_TRACES] = { + "default" + }; +#else + /* Example SH_CSS_SP_DBG_NR_OF_TRACES==4 */ + /* Adjust this to your trace case */ + static char const *trace_name[SH_CSS_SP_DBG_NR_OF_TRACES] = { + "copy", "preview/video", "capture", "acceleration" + }; +#endif + + /* Remember host_index_last because we only want to print new entries */ + static int host_index_last[SH_CSS_SP_DBG_NR_OF_TRACES] = { 0 }; + int t, n; + + assert(state != NULL); + + for (t = 0; t < SH_CSS_SP_DBG_NR_OF_TRACES; t++) { + int sp_index_last = state->index_last[t]; + + if (sp_index_last < host_index_last[t]) { + /* SP has been reset */ + host_index_last[t] = 0; + } + + if ((host_index_last[t] + SH_CSS_SP_DBG_TRACE_DEPTH) < + sp_index_last) { + /* last index can be multiple rounds behind */ + /* while trace size is only SH_CSS_SP_DBG_TRACE_DEPTH */ + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "Warning: trace %s has gap of %d " + "traces\n", + trace_name[t], + (sp_index_last - + (host_index_last[t] + + SH_CSS_SP_DBG_TRACE_DEPTH))); + + host_index_last[t] = + sp_index_last - SH_CSS_SP_DBG_TRACE_DEPTH; + } + + for (n = host_index_last[t]; n < sp_index_last; n++) { + int i = n % SH_CSS_SP_DBG_TRACE_DEPTH; + int l = state->trace[t][i].location & + ((1 << SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS) - 1); + int fid = state->trace[t][i].location >> + SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS; + int ts = state->trace[t][i].time_stamp; + + if (ts) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "%05d trace=%s, file=%s:%d, " + "data=0x%08x\n", + ts, + trace_name[t], + id2filename[fid], l, + state->trace[t][i].data); + } + } + host_index_last[t] = sp_index_last; + } + +#elif SP_DEBUG == SP_DEBUG_MINIMAL + int i; + int base = 0; + int limit = SH_CSS_NUM_SP_DEBUG; + int step = 1; + + assert(state != NULL); + + for (i = base; i < limit; i += step) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "sp_dbg_trace[%d] = %d\n", + i, state->debug[i]); + } +#endif + +#if SP_DEBUG != SP_DEBUG_NONE + + return; +} +#endif + +#if defined(HAS_INPUT_FORMATTER_VERSION_2) && !defined(HAS_NO_INPUT_FORMATTER) +static void debug_print_rx_mipi_port_state(mipi_port_state_t *state) +{ + int i; + unsigned int bits, infos; + + assert(state != NULL); + + bits = state->irq_status; + infos = ia_css_isys_rx_translate_irq_infos(bits); + + ia_css_debug_dtrace(2, "\t\t%-32s: (irq reg = 0x%X)\n", + "receiver errors", bits); + + if (infos & IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN) + ia_css_debug_dtrace(2, "\t\t\tbuffer overrun\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_SOT) + ia_css_debug_dtrace(2, "\t\t\tstart-of-transmission error\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC) + ia_css_debug_dtrace(2, "\t\t\tstart-of-transmission sync error\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_CONTROL) + ia_css_debug_dtrace(2, "\t\t\tcontrol error\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE) + ia_css_debug_dtrace(2, "\t\t\t2 or more ECC errors\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_CRC) + ia_css_debug_dtrace(2, "\t\t\tCRC mismatch\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID) + ia_css_debug_dtrace(2, "\t\t\tunknown error\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC) + ia_css_debug_dtrace(2, "\t\t\tframe sync error\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA) + ia_css_debug_dtrace(2, "\t\t\tframe data error\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT) + ia_css_debug_dtrace(2, "\t\t\tdata timeout\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC) + ia_css_debug_dtrace(2, "\t\t\tunknown escape command entry\n"); + if (infos & IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC) + ia_css_debug_dtrace(2, "\t\t\tline sync error\n"); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "device_ready", state->device_ready); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "irq_status", state->irq_status); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "irq_enable", state->irq_enable); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "timeout_count", state->timeout_count); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "init_count", state->init_count); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw16_18", state->raw16_18); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "sync_count", state->sync_count); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "rx_count", state->rx_count); + + for (i = 0; i < MIPI_4LANE_CFG; i++) { + ia_css_debug_dtrace(2, "\t\t%-32s%d%-32s: %d\n", + "lane_sync_count[", i, "]", + state->lane_sync_count[i]); + } + + for (i = 0; i < MIPI_4LANE_CFG; i++) { + ia_css_debug_dtrace(2, "\t\t%-32s%d%-32s: %d\n", + "lane_rx_count[", i, "]", + state->lane_rx_count[i]); + } + + return; +} + +static void debug_print_rx_channel_state(rx_channel_state_t *state) +{ + int i; + + assert(state != NULL); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "compression_scheme0", state->comp_scheme0); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "compression_scheme1", state->comp_scheme1); + + for (i = 0; i < N_MIPI_FORMAT_CUSTOM; i++) { + ia_css_debug_dtrace(2, "\t\t%-32s%d: %d\n", + "MIPI Predictor ", i, state->pred[i]); + } + + for (i = 0; i < N_MIPI_FORMAT_CUSTOM; i++) { + ia_css_debug_dtrace(2, "\t\t%-32s%d: %d\n", + "MIPI Compressor ", i, state->comp[i]); + } + + return; +} + +static void debug_print_rx_state(receiver_state_t *state) +{ + int i; + + assert(state != NULL); + ia_css_debug_dtrace(2, "CSI Receiver State:\n"); + + ia_css_debug_dtrace(2, "\tConfiguration:\n"); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "fs_to_ls_delay", state->fs_to_ls_delay); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "ls_to_data_delay", state->ls_to_data_delay); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "data_to_le_delay", state->data_to_le_delay); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "le_to_fe_delay", state->le_to_fe_delay); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "fe_to_fs_delay", state->fe_to_fs_delay); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "le_to_fs_delay", state->le_to_fs_delay); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "is_two_ppc", state->is_two_ppc); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "backend_rst", state->backend_rst); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw18", state->raw18); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "force_raw8", state->force_raw8); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "raw16", state->raw16); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_gsp_acc_ovl", state->be_gsp_acc_ovl); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "be_srst", state->be_srst); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_is_two_ppc", state->be_is_two_ppc); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_comp_format0", state->be_comp_format0); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_comp_format1", state->be_comp_format1); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_comp_format2", state->be_comp_format2); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_comp_format3", state->be_comp_format3); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "be_sel", state->be_sel); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_raw16_config", state->be_raw16_config); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_raw18_config", state->be_raw18_config); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_force_raw8", state->be_force_raw8); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_irq_status", state->be_irq_status); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "be_irq_clear", state->be_irq_clear); + + /* mipi port state */ + for (i = 0; i < N_MIPI_PORT_ID; i++) { + ia_css_debug_dtrace(2, "\tMIPI Port %d State:\n", i); + + debug_print_rx_mipi_port_state(&state->mipi_port_state[i]); + } + /* end of mipi port state */ + + /* rx channel state */ + for (i = 0; i < N_RX_CHANNEL_ID; i++) { + ia_css_debug_dtrace(2, "\tRX Channel %d State:\n", i); + + debug_print_rx_channel_state(&state->rx_channel_state[i]); + } + /* end of rx channel state */ + + return; +} +#endif + +#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2) +void ia_css_debug_dump_rx_state(void) +{ +#if defined(HAS_INPUT_FORMATTER_VERSION_2) && !defined(HAS_NO_INPUT_FORMATTER) + receiver_state_t state; + + receiver_get_state(RX0_ID, &state); + debug_print_rx_state(&state); +#endif +} +#endif + +void ia_css_debug_dump_sp_sw_debug_info(void) +{ +#if SP_DEBUG != SP_DEBUG_NONE + struct sh_css_sp_debug_state state; + + sh_css_sp_get_debug_state(&state); + ia_css_debug_print_sp_debug_state(&state); +#endif + ia_css_bufq_dump_queue_info(); + ia_css_pipeline_dump_thread_map_info(); + return; +} + +#if defined(USE_INPUT_SYSTEM_VERSION_2) +static void debug_print_isys_capture_unit_state(capture_unit_state_t *state) +{ + assert(state != NULL); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Packet_Length", state->Packet_Length); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Received_Length", state->Received_Length); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Received_Short_Packets", + state->Received_Short_Packets); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Received_Long_Packets", + state->Received_Long_Packets); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Last_Command", state->Last_Command); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Next_Command", state->Next_Command); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Last_Acknowledge", state->Last_Acknowledge); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Next_Acknowledge", state->Next_Acknowledge); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "FSM_State_Info", state->FSM_State_Info); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "StartMode", state->StartMode); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Start_Addr", state->Start_Addr); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Mem_Region_Size", state->Mem_Region_Size); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Num_Mem_Regions", state->Num_Mem_Regions); + return; +} + +static void debug_print_isys_acquisition_unit_state( + acquisition_unit_state_t *state) +{ + assert(state != NULL); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Received_Short_Packets", + state->Received_Short_Packets); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Received_Long_Packets", + state->Received_Long_Packets); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Last_Command", state->Last_Command); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Next_Command", state->Next_Command); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Last_Acknowledge", state->Last_Acknowledge); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Next_Acknowledge", state->Next_Acknowledge); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "FSM_State_Info", state->FSM_State_Info); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Int_Cntr_Info", state->Int_Cntr_Info); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Start_Addr", state->Start_Addr); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Mem_Region_Size", state->Mem_Region_Size); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "Num_Mem_Regions", state->Num_Mem_Regions); +} + +static void debug_print_isys_ctrl_unit_state(ctrl_unit_state_t *state) +{ + assert(state != NULL); + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "last_cmd", state->last_cmd); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "next_cmd", state->next_cmd); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "last_ack", state->last_ack); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", "next_ack", state->next_ack); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "top_fsm_state", state->top_fsm_state); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captA_fsm_state", state->captA_fsm_state); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captB_fsm_state", state->captB_fsm_state); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captC_fsm_state", state->captC_fsm_state); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "acq_fsm_state", state->acq_fsm_state); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captA_start_addr", state->captA_start_addr); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captB_start_addr", state->captB_start_addr); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captC_start_addr", state->captC_start_addr); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captA_mem_region_size", + state->captA_mem_region_size); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captB_mem_region_size", + state->captB_mem_region_size); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captC_mem_region_size", + state->captC_mem_region_size); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captA_num_mem_regions", + state->captA_num_mem_regions); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captB_num_mem_regions", + state->captB_num_mem_regions); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "captC_num_mem_regions", + state->captC_num_mem_regions); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "acq_start_addr", state->acq_start_addr); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "acq_mem_region_size", state->acq_mem_region_size); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "acq_num_mem_regions", state->acq_num_mem_regions); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "capt_reserve_one_mem_region", + state->capt_reserve_one_mem_region); + + return; +} + +static void debug_print_isys_state(input_system_state_t *state) +{ + int i; + + assert(state != NULL); + ia_css_debug_dtrace(2, "InputSystem State:\n"); + + /* configuration */ + ia_css_debug_dtrace(2, "\tConfiguration:\n"); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "str_multiCastA_sel", state->str_multicastA_sel); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "str_multicastB_sel", state->str_multicastB_sel); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "str_multicastC_sel", state->str_multicastC_sel); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "str_mux_sel", state->str_mux_sel); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "str_mon_status", state->str_mon_status); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "str_mon_irq_cond", state->str_mon_irq_cond); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "str_mon_irq_en", state->str_mon_irq_en); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "isys_srst", state->isys_srst); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "isys_slv_reg_srst", state->isys_slv_reg_srst); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "str_deint_portA_cnt", state->str_deint_portA_cnt); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "str_deint_portB_cnd", state->str_deint_portB_cnt); + /* end of configuration */ + + /* capture unit state */ + for (i = 0; i < N_CAPTURE_UNIT_ID; i++) { + capture_unit_state_t *capture_unit_state; + + ia_css_debug_dtrace(2, "\tCaptureUnit %d State:\n", i); + + capture_unit_state = &state->capture_unit[i]; + debug_print_isys_capture_unit_state(capture_unit_state); + } + /* end of capture unit state */ + + /* acquisition unit state */ + for (i = 0; i < N_ACQUISITION_UNIT_ID; i++) { + acquisition_unit_state_t *acquisition_unit_state; + + ia_css_debug_dtrace(2, "\tAcquisitionUnit %d State:\n", i); + + acquisition_unit_state = &state->acquisition_unit[i]; + debug_print_isys_acquisition_unit_state(acquisition_unit_state); + } + /* end of acquisition unit state */ + + /* control unit state */ + for (i = 0; i < N_CTRL_UNIT_ID; i++) { + ia_css_debug_dtrace(2, "\tControlUnit %d State:\n", i); + + debug_print_isys_ctrl_unit_state(&state->ctrl_unit_state[i]); + } + /* end of control unit state */ +} + +void ia_css_debug_dump_isys_state(void) +{ + input_system_state_t state; + + input_system_get_state(INPUT_SYSTEM0_ID, &state); + debug_print_isys_state(&state); + + return; +} +#endif +#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2401) +void ia_css_debug_dump_isys_state(void) +{ + /* Android compilation fails if made a local variable + stack size on android is limited to 2k and this structure + is around 3.5K, in place of static malloc can be done but + if this call is made too often it will lead to fragment memory + versus a fixed allocation */ + static input_system_state_t state; + + input_system_get_state(INPUT_SYSTEM0_ID, &state); + input_system_dump_state(INPUT_SYSTEM0_ID, &state); +} +#endif + +void ia_css_debug_dump_debug_info(const char *context) +{ + if (context == NULL) + context = "No Context provided"; + + ia_css_debug_dtrace(2, "CSS Debug Info dump [Context = %s]\n", context); +#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2) + ia_css_debug_dump_rx_state(); +#endif +#if !defined(HAS_NO_INPUT_FORMATTER) && defined(USE_INPUT_SYSTEM_VERSION_2) + ia_css_debug_dump_if_state(); +#endif + ia_css_debug_dump_isp_state(); + ia_css_debug_dump_isp_sp_fifo_state(); + ia_css_debug_dump_isp_gdc_fifo_state(); + ia_css_debug_dump_sp_state(); + ia_css_debug_dump_perf_counters(); + +#ifdef HAS_WATCHDOG_SP_THREAD_DEBUG + sh_css_dump_thread_wait_info(); + sh_css_dump_pipe_stage_info(); + sh_css_dump_pipe_stripe_info(); +#endif + ia_css_debug_dump_dma_isp_fifo_state(); + ia_css_debug_dump_dma_sp_fifo_state(); + ia_css_debug_dump_dma_state(); +#if defined(USE_INPUT_SYSTEM_VERSION_2) + ia_css_debug_dump_isys_state(); + + { + irq_controller_state_t state; + irq_controller_get_state(IRQ2_ID, &state); + + ia_css_debug_dtrace(2, "\t%-32s:\n", + "Input System IRQ Controller State"); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "irq_edge", state.irq_edge); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "irq_mask", state.irq_mask); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "irq_status", state.irq_status); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "irq_enable", state.irq_enable); + + ia_css_debug_dtrace(2, "\t\t%-32s: %d\n", + "irq_level_not_pulse", + state.irq_level_not_pulse); + } +#endif +#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2401) + ia_css_debug_dump_isys_state(); +#endif +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) + ia_css_debug_tagger_state(); +#endif + return; +} + +/** this function is for debug use, it can make SP go to sleep + state after each frame, then user can dump the stable SP dmem. + this function can be called after ia_css_start_sp() + and before sh_css_init_buffer_queues() +*/ +void ia_css_debug_enable_sp_sleep_mode(enum ia_css_sp_sleep_mode mode) +{ + const struct ia_css_fw_info *fw; + unsigned int HIVE_ADDR_sp_sleep_mode; + + fw = &sh_css_sp_fw; + HIVE_ADDR_sp_sleep_mode = fw->info.sp.sleep_mode; + + (void)HIVE_ADDR_sp_sleep_mode; /* Suppres warnings in CRUN */ + + sp_dmem_store_uint32(SP0_ID, + (unsigned int)sp_address_of(sp_sleep_mode), + (uint32_t) mode); +} + +void ia_css_debug_wake_up_sp(void) +{ + /*hrt_ctl_start(SP); */ + sp_ctrl_setbit(SP0_ID, SP_SC_REG, SP_START_BIT); +} + +#if !defined(IS_ISP_2500_SYSTEM) +#define FIND_DMEM_PARAMS_TYPE(stream, kernel, type) \ + (struct HRTCAT(HRTCAT(sh_css_isp_, type), _params) *) \ + findf_dmem_params(stream, offsetof(struct ia_css_memory_offsets, dmem.kernel)) + +#define FIND_DMEM_PARAMS(stream, kernel) FIND_DMEM_PARAMS_TYPE(stream, kernel, kernel) + +/* Find a stage that support the kernel and return the parameters for that kernel */ +static char * +findf_dmem_params(struct ia_css_stream *stream, short idx) +{ + int i; + for (i = 0; i < stream->num_pipes; i++) { + struct ia_css_pipe *pipe = stream->pipes[i]; + struct ia_css_pipeline *pipeline = ia_css_pipe_get_pipeline(pipe); + struct ia_css_pipeline_stage *stage; + for (stage = pipeline->stages; stage; stage = stage->next) { + struct ia_css_binary *binary = stage->binary; + short *offsets = (short *)&binary->info->mem_offsets.offsets.param->dmem; + short dmem_offset = offsets[idx]; + const struct ia_css_host_data *isp_data = + ia_css_isp_param_get_mem_init(&binary->mem_params, + IA_CSS_PARAM_CLASS_PARAM, IA_CSS_ISP_DMEM0); + if (dmem_offset < 0) + continue; + return &isp_data->address[dmem_offset]; + } + } + return NULL; +} +#endif + +void ia_css_debug_dump_isp_params(struct ia_css_stream *stream, + unsigned int enable) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "ISP PARAMETERS:\n"); +#if defined(IS_ISP_2500_SYSTEM) + (void)enable; + (void)stream; +#else + + assert(stream != NULL); + if ((enable & IA_CSS_DEBUG_DUMP_FPN) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_fpn_dump(FIND_DMEM_PARAMS(stream, fpn), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_OB) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_ob_dump(FIND_DMEM_PARAMS(stream, ob), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_SC) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_sc_dump(FIND_DMEM_PARAMS(stream, sc), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_WB) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_wb_dump(FIND_DMEM_PARAMS(stream, wb), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_DP) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_dp_dump(FIND_DMEM_PARAMS(stream, dp), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_BNR) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_bnr_dump(FIND_DMEM_PARAMS(stream, bnr), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_S3A) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_s3a_dump(FIND_DMEM_PARAMS(stream, s3a), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_DE) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_de_dump(FIND_DMEM_PARAMS(stream, de), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_YNR) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_nr_dump(FIND_DMEM_PARAMS_TYPE(stream, nr, ynr), IA_CSS_DEBUG_VERBOSE); + ia_css_yee_dump(FIND_DMEM_PARAMS(stream, yee), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_CSC) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_csc_dump(FIND_DMEM_PARAMS(stream, csc), IA_CSS_DEBUG_VERBOSE); + ia_css_yuv2rgb_dump(FIND_DMEM_PARAMS_TYPE(stream, yuv2rgb, csc), IA_CSS_DEBUG_VERBOSE); + ia_css_rgb2yuv_dump(FIND_DMEM_PARAMS_TYPE(stream, rgb2yuv, csc), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_GC) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_gc_dump(FIND_DMEM_PARAMS(stream, gc), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_TNR) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_tnr_dump(FIND_DMEM_PARAMS(stream, tnr), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_ANR) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_anr_dump(FIND_DMEM_PARAMS(stream, anr), IA_CSS_DEBUG_VERBOSE); + } + if ((enable & IA_CSS_DEBUG_DUMP_CE) + || (enable & IA_CSS_DEBUG_DUMP_ALL)) { + ia_css_ce_dump(FIND_DMEM_PARAMS(stream, ce), IA_CSS_DEBUG_VERBOSE); + } +#endif +} + +void sh_css_dump_sp_raw_copy_linecount(bool reduced) +{ + const struct ia_css_fw_info *fw; + unsigned int HIVE_ADDR_raw_copy_line_count; + int32_t raw_copy_line_count; + static int32_t prev_raw_copy_line_count = -1; + + fw = &sh_css_sp_fw; + HIVE_ADDR_raw_copy_line_count = + fw->info.sp.raw_copy_line_count; + + (void)HIVE_ADDR_raw_copy_line_count; + + sp_dmem_load(SP0_ID, + (unsigned int)sp_address_of(raw_copy_line_count), + &raw_copy_line_count, + sizeof(raw_copy_line_count)); + + /* only indicate if copy loop is active */ + if (reduced) + raw_copy_line_count = (raw_copy_line_count < 0)?raw_copy_line_count:1; + /* do the handling */ + if (prev_raw_copy_line_count != raw_copy_line_count) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "sh_css_dump_sp_raw_copy_linecount() " + "line_count=%d\n", + raw_copy_line_count); + prev_raw_copy_line_count = raw_copy_line_count; + } +} + +void ia_css_debug_dump_isp_binary(void) +{ + const struct ia_css_fw_info *fw; + unsigned int HIVE_ADDR_pipeline_sp_curr_binary_id; + uint32_t curr_binary_id; + static uint32_t prev_binary_id = 0xFFFFFFFF; + static uint32_t sample_count; + + fw = &sh_css_sp_fw; + HIVE_ADDR_pipeline_sp_curr_binary_id = fw->info.sp.curr_binary_id; + + (void)HIVE_ADDR_pipeline_sp_curr_binary_id; + + sp_dmem_load(SP0_ID, + (unsigned int)sp_address_of(pipeline_sp_curr_binary_id), + &curr_binary_id, + sizeof(curr_binary_id)); + + /* do the handling */ + sample_count++; + if (prev_binary_id != curr_binary_id) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "sh_css_dump_isp_binary() " + "pipe_id=%d, binary_id=%d, sample_count=%d\n", + (curr_binary_id >> 16), + (curr_binary_id & 0x0ffff), + sample_count); + sample_count = 0; + prev_binary_id = curr_binary_id; + } +} + +void ia_css_debug_dump_perf_counters(void) +{ +#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2) + const struct ia_css_fw_info *fw; + int i; + unsigned int HIVE_ADDR_ia_css_isys_sp_error_cnt; + int32_t ia_css_sp_input_system_error_cnt[N_MIPI_PORT_ID + 1]; /* 3 Capture Units and 1 Acquire Unit. */ + + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "Input System Error Counters:\n"); + + fw = &sh_css_sp_fw; + HIVE_ADDR_ia_css_isys_sp_error_cnt = fw->info.sp.perf_counter_input_system_error; + + (void)HIVE_ADDR_ia_css_isys_sp_error_cnt; + + sp_dmem_load(SP0_ID, + (unsigned int)sp_address_of(ia_css_isys_sp_error_cnt), + &ia_css_sp_input_system_error_cnt, + sizeof(ia_css_sp_input_system_error_cnt)); + + for (i = 0; i < N_MIPI_PORT_ID + 1; i++) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "\tport[%d] = %d\n", + i, ia_css_sp_input_system_error_cnt[i]); + } +#endif +} + +/* + +void sh_css_init_ddr_debug_queue(void) +{ + hrt_vaddress ddr_debug_queue_addr = + mmgr_malloc(sizeof(debug_data_ddr_t)); + const struct ia_css_fw_info *fw; + unsigned int HIVE_ADDR_debug_buffer_ddr_address; + + fw = &sh_css_sp_fw; + HIVE_ADDR_debug_buffer_ddr_address = + fw->info.sp.debug_buffer_ddr_address; + + (void)HIVE_ADDR_debug_buffer_ddr_address; + + debug_buffer_ddr_init(ddr_debug_queue_addr); + + sp_dmem_store_uint32(SP0_ID, + (unsigned int)sp_address_of(debug_buffer_ddr_address), + (uint32_t)(ddr_debug_queue_addr)); +} + +void sh_css_load_ddr_debug_queue(void) +{ + debug_synch_queue_ddr(); +} + +void ia_css_debug_dump_ddr_debug_queue(void) +{ + int i; + sh_css_load_ddr_debug_queue(); + for (i = 0; i < DEBUG_BUF_SIZE; i++) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "ddr_debug_queue[%d] = 0x%x\n", + i, debug_data_ptr->buf[i]); + } +} +*/ + +/** + * @brief Initialize the debug mode. + * Refer to "ia_css_debug.h" for more details. + */ +bool ia_css_debug_mode_init(void) +{ + bool rc; + rc = sh_css_sp_init_dma_sw_reg(0); + return rc; +} + +/** + * @brief Disable the DMA channel. + * Refer to "ia_css_debug.h" for more details. + */ +bool +ia_css_debug_mode_disable_dma_channel(int dma_id, + int channel_id, int request_type) +{ + bool rc; + + rc = sh_css_sp_set_dma_sw_reg(dma_id, channel_id, request_type, false); + + return rc; +} + +/** + * @brief Enable the DMA channel. + * Refer to "ia_css_debug.h" for more details. + */ +bool +ia_css_debug_mode_enable_dma_channel(int dma_id, + int channel_id, int request_type) +{ + bool rc; + + rc = sh_css_sp_set_dma_sw_reg(dma_id, channel_id, request_type, true); + + return rc; +} + +void dtrace_dot(const char *fmt, ...) +{ + va_list ap; +#ifdef HRT_CSIM + va_list ap2; +#endif + + assert(fmt != NULL); + va_start(ap, fmt); +#ifdef HRT_CSIM + va_start(ap2, fmt); +#endif + + ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_START); + ia_css_debug_vdtrace(IA_CSS_DEBUG_INFO, fmt, ap); + ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_END); +#ifdef HRT_CSIM + /* For CSIM we print double because HSS log can mess up this output + * As post processing, we remove incomplete lines and make lines uniq. + * */ + ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_START); + ia_css_debug_vdtrace(IA_CSS_DEBUG_INFO, fmt, ap2); + ia_css_debug_dtrace(IA_CSS_DEBUG_INFO, "%s", DPG_END);\ + + va_end(ap2); +#endif + va_end(ap); +} +#ifdef HAS_WATCHDOG_SP_THREAD_DEBUG +void sh_css_dump_thread_wait_info(void) +{ + const struct ia_css_fw_info *fw; + int i; + unsigned int HIVE_ADDR_sp_thread_wait; + int32_t sp_thread_wait[MAX_THREAD_NUM]; + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "SEM WAITS:\n"); + + fw = &sh_css_sp_fw; + HIVE_ADDR_sp_thread_wait = + fw->info.sp.debug_wait; + + (void)HIVE_ADDR_sp_thread_wait; + + sp_dmem_load(SP0_ID, + (unsigned int)sp_address_of(sp_thread_wait), + &sp_thread_wait, + sizeof(sp_thread_wait)); + for (i = 0; i < MAX_THREAD_NUM; i++) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "\twait[%d] = 0x%X\n", + i, sp_thread_wait[i]); + } + +} + +void sh_css_dump_pipe_stage_info(void) +{ + const struct ia_css_fw_info *fw; + int i; + unsigned int HIVE_ADDR_sp_pipe_stage; + int32_t sp_pipe_stage[MAX_THREAD_NUM]; + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "PIPE STAGE:\n"); + + fw = &sh_css_sp_fw; + HIVE_ADDR_sp_pipe_stage = + fw->info.sp.debug_stage; + + (void)HIVE_ADDR_sp_pipe_stage; + + sp_dmem_load(SP0_ID, + (unsigned int)sp_address_of(sp_pipe_stage), + &sp_pipe_stage, + sizeof(sp_pipe_stage)); + for (i = 0; i < MAX_THREAD_NUM; i++) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "\tstage[%d] = %d\n", + i, sp_pipe_stage[i]); + } + +} + +void sh_css_dump_pipe_stripe_info(void) +{ + const struct ia_css_fw_info *fw; + int i; + unsigned int HIVE_ADDR_sp_pipe_stripe; + int32_t sp_pipe_stripe[MAX_THREAD_NUM]; + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, "PIPE STRIPE:\n"); + + fw = &sh_css_sp_fw; + HIVE_ADDR_sp_pipe_stripe = + fw->info.sp.debug_stripe; + + (void)HIVE_ADDR_sp_pipe_stripe; + + sp_dmem_load(SP0_ID, + (unsigned int)sp_address_of(sp_pipe_stripe), + &sp_pipe_stripe, + sizeof(sp_pipe_stripe)); + for (i = 0; i < MAX_THREAD_NUM; i++) { + ia_css_debug_dtrace(IA_CSS_DEBUG_VERBOSE, + "\tstripe[%d] = %d\n", + i, sp_pipe_stripe[i]); + } + +} +#endif + +static void +ia_css_debug_pipe_graph_dump_frame( + struct ia_css_frame *frame, + enum ia_css_pipe_id id, + char const *blob_name, + char const *frame_name, + bool in_frame) +{ + char bufinfo[100]; + + if (frame->dynamic_queue_id == SH_CSS_INVALID_QUEUE_ID) { + snprintf(bufinfo, sizeof(bufinfo), "Internal"); + } else { + snprintf(bufinfo, sizeof(bufinfo), "Queue: %s %s", + pipe_id_to_str[id], + queue_id_to_str[frame->dynamic_queue_id]); + } + dtrace_dot( + "node [shape = box, " + "fixedsize=true, width=2, height=0.7]; \"0x%08lx\" " + "[label = \"%s\\n%d(%d) x %d, %dbpp\\n%s\"];", + HOST_ADDRESS(frame), + debug_frame_format2str(frame->info.format), + frame->info.res.width, + frame->info.padded_width, + frame->info.res.height, + frame->info.raw_bit_depth, + bufinfo); + + if (in_frame) { + dtrace_dot( + "\"0x%08lx\"->\"%s(pipe%d)\" " + "[label = %s_frame];", + HOST_ADDRESS(frame), + blob_name, id, frame_name); + } else { + dtrace_dot( + "\"%s(pipe%d)\"->\"0x%08lx\" " + "[label = %s_frame];", + blob_name, id, + HOST_ADDRESS(frame), + frame_name); + } +} + +void +ia_css_debug_pipe_graph_dump_prologue(void) +{ + dtrace_dot("digraph sh_css_pipe_graph {"); + dtrace_dot("rankdir=LR;"); + + dtrace_dot("fontsize=9;"); + dtrace_dot("label = \"\\nEnable options: rp=reduced pipe, vfve=vf_veceven, " + "dvse=dvs_envelope, dvs6=dvs_6axis, bo=block_out, " + "fbds=fixed_bayer_ds, bf6=bayer_fir_6db, " + "rawb=raw_binning, cont=continuous, disc=dis_crop\\n" + "dp2a=dp_2adjacent, outp=output, outt=out_table, " + "reff=ref_frame, par=params, gam=gamma, " + "cagdc=ca_gdc, ispa=isp_addresses, inf=in_frame, " + "outf=out_frame, hs=high_speed, inpc=input_chunking\""); +} + +void ia_css_debug_pipe_graph_dump_epilogue(void) +{ + + if (strlen(ring_buffer) > 0) { + dtrace_dot(ring_buffer); + } + + + if (pg_inst.stream_format != N_IA_CSS_STREAM_FORMAT) { + /* An input stream format has been set so assume we have + * an input system and sensor + */ + + + dtrace_dot( + "node [shape = doublecircle, " + "fixedsize=true, width=2.5]; \"input_system\" " + "[label = \"Input system\"];"); + + dtrace_dot( + "\"input_system\"->\"%s\" " + "[label = \"%s\"];", + dot_id_input_bin, debug_stream_format2str(pg_inst.stream_format)); + + dtrace_dot( + "node [shape = doublecircle, " + "fixedsize=true, width=2.5]; \"sensor\" " + "[label = \"Sensor\"];"); + + dtrace_dot( + "\"sensor\"->\"input_system\" " + "[label = \"%s\\n%d x %d\\n(%d x %d)\"];", + debug_stream_format2str(pg_inst.stream_format), + pg_inst.width, pg_inst.height, + pg_inst.eff_width, pg_inst.eff_height); + } + + dtrace_dot("}"); + + /* Reset temp strings */ + memset(dot_id_input_bin, 0, sizeof(dot_id_input_bin)); + memset(ring_buffer, 0, sizeof(ring_buffer)); + + pg_inst.do_init = true; + pg_inst.width = 0; + pg_inst.height = 0; + pg_inst.eff_width = 0; + pg_inst.eff_height = 0; + pg_inst.stream_format = N_IA_CSS_STREAM_FORMAT; +} + +void +ia_css_debug_pipe_graph_dump_stage( + struct ia_css_pipeline_stage *stage, + enum ia_css_pipe_id id) +{ + char blob_name[SH_CSS_MAX_BINARY_NAME+10] = ""; + char const *bin_type = ""; + int i; + + assert(stage != NULL); + if (stage->sp_func != IA_CSS_PIPELINE_NO_FUNC) + return; + + if (pg_inst.do_init) { + ia_css_debug_pipe_graph_dump_prologue(); + pg_inst.do_init = false; + } + + if (stage->binary) { + bin_type = "binary"; + if (stage->binary->info->blob) + snprintf(blob_name, sizeof(blob_name), "%s_stage%d", + stage->binary->info->blob->name, stage->stage_num); + } else if (stage->firmware) { + bin_type = "firmware"; + strncpy_s(blob_name, sizeof(blob_name), IA_CSS_EXT_ISP_PROG_NAME(stage->firmware), sizeof(blob_name)); + } + + /* Guard in case of binaries that don't have any binary_info */ + if (stage->binary_info != NULL) { + char enable_info1[100]; + char enable_info2[100]; + char enable_info3[100]; + char enable_info[200]; + struct ia_css_binary_info *bi = stage->binary_info; + + /* Split it in 2 function-calls to keep the amount of + * parameters per call "reasonable" + */ + snprintf(enable_info1, sizeof(enable_info1), + "%s%s%s%s%s%s%s%s%s%s%s%s%s%s", + bi->enable.reduced_pipe ? "rp," : "", + bi->enable.vf_veceven ? "vfve," : "", + bi->enable.dis ? "dis," : "", + bi->enable.dvs_envelope ? "dvse," : "", + bi->enable.uds ? "uds," : "", + bi->enable.dvs_6axis ? "dvs6," : "", + bi->enable.block_output ? "bo," : "", + bi->enable.ds ? "ds," : "", + bi->enable.bayer_fir_6db ? "bf6," : "", + bi->enable.raw_binning ? "rawb," : "", + bi->enable.continuous ? "cont," : "", + bi->enable.s3a ? "s3a," : "", + bi->enable.fpnr ? "fpnr," : "", + bi->enable.sc ? "sc," : "" + ); + + snprintf(enable_info2, sizeof(enable_info2), + "%s%s%s%s%s%s%s%s%s%s%s", + bi->enable.macc ? "macc," : "", + bi->enable.output ? "outp," : "", + bi->enable.ref_frame ? "reff," : "", + bi->enable.tnr ? "tnr," : "", + bi->enable.xnr ? "xnr," : "", + bi->enable.params ? "par," : "", + bi->enable.ca_gdc ? "cagdc," : "", + bi->enable.isp_addresses ? "ispa," : "", + bi->enable.in_frame ? "inf," : "", + bi->enable.out_frame ? "outf," : "", + bi->enable.high_speed ? "hs," : "" + ); + + /* And merge them into one string */ + snprintf(enable_info, sizeof(enable_info), "%s%s", + enable_info1, enable_info2); + { + int l, p; + char *ei = enable_info; + + l = strlen(ei); + + /* Replace last ',' with \0 if present */ + if (l && enable_info[l-1] == ',') + enable_info[--l] = '\0'; + + if (l <= ENABLE_LINE_MAX_LENGTH) { + /* It fits on one line, copy string and init */ + /* other helper strings with empty string */ + strcpy_s(enable_info, + sizeof(enable_info), + ei); + } else { + /* Too big for one line, find last comma */ + p = ENABLE_LINE_MAX_LENGTH; + while (ei[p] != ',') + p--; + /* Last comma found, copy till that comma */ + strncpy_s(enable_info1, + sizeof(enable_info1), + ei, p); + enable_info1[p] = '\0'; + + ei += p+1; + l = strlen(ei); + + if (l <= ENABLE_LINE_MAX_LENGTH) { + /* The 2nd line fits */ + /* we cannot use ei as argument because + * it is not guarenteed dword aligned + */ + strncpy_s(enable_info2, + sizeof(enable_info2), + ei, l); + enable_info2[l] = '\0'; + snprintf(enable_info, sizeof(enable_info), "%s\\n%s", + enable_info1, enable_info2); + + } else { + /* 2nd line is still too long */ + p = ENABLE_LINE_MAX_LENGTH; + while (ei[p] != ',') + p--; + strncpy_s(enable_info2, + sizeof(enable_info2), + ei, p); + enable_info2[p] = '\0'; + ei += p+1; + l = strlen(ei); + + if (l <= ENABLE_LINE_MAX_LENGTH) { + /* The 3rd line fits */ + /* we cannot use ei as argument because + * it is not guarenteed dword aligned + */ + strcpy_s(enable_info3, + sizeof(enable_info3), ei); + enable_info3[l] = '\0'; + snprintf(enable_info, sizeof(enable_info), + "%s\\n%s\\n%s", + enable_info1, enable_info2, + enable_info3); + } else { + /* 3rd line is still too long */ + p = ENABLE_LINE_MAX_LENGTH; + while (ei[p] != ',') + p--; + strncpy_s(enable_info3, + sizeof(enable_info3), + ei, p); + enable_info3[p] = '\0'; + ei += p+1; + strcpy_s(enable_info3, + sizeof(enable_info3), ei); + snprintf(enable_info, sizeof(enable_info), + "%s\\n%s\\n%s", + enable_info1, enable_info2, + enable_info3); + } + } + } + } + + dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, " + "label=\"%s\\n%s\\n\\n%s\"]; \"%s(pipe%d)\"", + bin_type, blob_name, enable_info, blob_name, id); + + } + else { + dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, " + "label=\"%s\\n%s\\n\"]; \"%s(pipe%d)\"", + bin_type, blob_name, blob_name, id); + } + + if (stage->stage_num == 0) { + /* + * There are some implicite assumptions about which bin is the + * input binary e.g. which one is connected to the input system + * Priority: + * 1) sp_raw_copy bin has highest priority + * 2) First stage==0 binary of preview, video or capture + */ + if (strlen(dot_id_input_bin) == 0) { + snprintf(dot_id_input_bin, sizeof(dot_id_input_bin), + "%s(pipe%d)", blob_name, id); + } + } + + if (stage->args.in_frame) { + ia_css_debug_pipe_graph_dump_frame( + stage->args.in_frame, id, blob_name, + "in", true); + } + +#ifndef ISP2401 + for (i = 0; i < NUM_VIDEO_TNR_FRAMES; i++) { +#else + for (i = 0; i < NUM_TNR_FRAMES; i++) { +#endif + if (stage->args.tnr_frames[i]) { + ia_css_debug_pipe_graph_dump_frame( + stage->args.tnr_frames[i], id, + blob_name, "tnr_frame", true); + } + } + + for (i = 0; i < MAX_NUM_VIDEO_DELAY_FRAMES; i++) { + if (stage->args.delay_frames[i]) { + ia_css_debug_pipe_graph_dump_frame( + stage->args.delay_frames[i], id, + blob_name, "delay_frame", true); + } + } + + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + if (stage->args.out_frame[i]) { + ia_css_debug_pipe_graph_dump_frame( + stage->args.out_frame[i], id, blob_name, + "out", false); + } + } + + if (stage->args.out_vf_frame) { + ia_css_debug_pipe_graph_dump_frame( + stage->args.out_vf_frame, id, blob_name, + "out_vf", false); + } +} + +void +ia_css_debug_pipe_graph_dump_sp_raw_copy( + struct ia_css_frame *out_frame) +{ + assert(out_frame != NULL); + if (pg_inst.do_init) { + ia_css_debug_pipe_graph_dump_prologue(); + pg_inst.do_init = false; + } + + dtrace_dot("node [shape = circle, fixedsize=true, width=2.5, " + "label=\"%s\\n%s\"]; \"%s(pipe%d)\"", + "sp-binary", "sp_raw_copy", "sp_raw_copy", 1); + + snprintf(ring_buffer, sizeof(ring_buffer), + "node [shape = box, " + "fixedsize=true, width=2, height=0.7]; \"0x%08lx\" " + "[label = \"%s\\n%d(%d) x %d\\nRingbuffer\"];", + HOST_ADDRESS(out_frame), + debug_frame_format2str(out_frame->info.format), + out_frame->info.res.width, + out_frame->info.padded_width, + out_frame->info.res.height); + + dtrace_dot(ring_buffer); + + dtrace_dot( + "\"%s(pipe%d)\"->\"0x%08lx\" " + "[label = out_frame];", + "sp_raw_copy", 1, HOST_ADDRESS(out_frame)); + + snprintf(dot_id_input_bin, sizeof(dot_id_input_bin), "%s(pipe%d)", "sp_raw_copy", 1); +} + +void +ia_css_debug_pipe_graph_dump_stream_config( + const struct ia_css_stream_config *stream_config) +{ + pg_inst.width = stream_config->input_config.input_res.width; + pg_inst.height = stream_config->input_config.input_res.height; + pg_inst.eff_width = stream_config->input_config.effective_res.width; + pg_inst.eff_height = stream_config->input_config.effective_res.height; + pg_inst.stream_format = stream_config->input_config.format; +} + +void +ia_css_debug_dump_resolution( + const struct ia_css_resolution *res, + const char *label) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s: =%d x =%d\n", + label, res->width, res->height); +} + +void +ia_css_debug_dump_frame_info( + const struct ia_css_frame_info *info, + const char *label) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", label); + ia_css_debug_dump_resolution(&info->res, "res"); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "padded_width: %d\n", + info->padded_width); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "format: %d\n", info->format); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "raw_bit_depth: %d\n", + info->raw_bit_depth); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "raw_bayer_order: %d\n", + info->raw_bayer_order); +} + +void +ia_css_debug_dump_capture_config( + const struct ia_css_capture_config *config) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", __func__); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_xnr: %d\n", + config->enable_xnr); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_raw_output: %d\n", + config->enable_raw_output); +} + +void +ia_css_debug_dump_pipe_extra_config( + const struct ia_css_pipe_extra_config *extra_config) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s\n", __func__); + if (extra_config) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "enable_raw_binning: %d\n", + extra_config->enable_raw_binning); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_yuv_ds: %d\n", + extra_config->enable_yuv_ds); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "enable_high_speed: %d\n", + extra_config->enable_high_speed); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "enable_dvs_6axis: %d\n", + extra_config->enable_dvs_6axis); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "enable_reduced_pipe: %d\n", + extra_config->enable_reduced_pipe); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "enable_fractional_ds: %d\n", + extra_config->enable_fractional_ds); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "disable_vf_pp: %d\n", + extra_config->disable_vf_pp); + } +} + +void +ia_css_debug_dump_pipe_config( + const struct ia_css_pipe_config *config) +{ + unsigned int i; + + IA_CSS_ENTER_PRIVATE("config = %p", config); + if (!config) { + IA_CSS_ERROR("NULL input parameter"); + IA_CSS_LEAVE_PRIVATE(""); + return; + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "isp_pipe_version: %d\n", + config->isp_pipe_version); + ia_css_debug_dump_resolution(&config->bayer_ds_out_res, + "bayer_ds_out_res"); + ia_css_debug_dump_resolution(&config->capt_pp_in_res, + "capt_pp_in_res"); + ia_css_debug_dump_resolution(&config->vf_pp_in_res, "vf_pp_in_res"); +#ifdef ISP2401 + ia_css_debug_dump_resolution(&config->output_system_in_res, + "output_system_in_res"); +#endif + ia_css_debug_dump_resolution(&config->dvs_crop_out_res, + "dvs_crop_out_res"); + for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + ia_css_debug_dump_frame_info(&config->output_info[i], "output_info"); + ia_css_debug_dump_frame_info(&config->vf_output_info[i], + "vf_output_info"); + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "acc_extension: 0x%x\n", + config->acc_extension); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "num_acc_stages: %d\n", + config->num_acc_stages); + ia_css_debug_dump_capture_config(&config->default_capture_config); + ia_css_debug_dump_resolution(&config->dvs_envelope, "dvs_envelope"); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "dvs_frame_delay: %d\n", + config->dvs_frame_delay); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "acc_num_execs: %d\n", + config->acc_num_execs); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "enable_dz: %d\n", + config->enable_dz); + IA_CSS_LEAVE_PRIVATE(""); +} + +void +ia_css_debug_dump_stream_config_source( + const struct ia_css_stream_config *config) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__); + switch (config->mode) { + case IA_CSS_INPUT_MODE_SENSOR: + case IA_CSS_INPUT_MODE_BUFFERED_SENSOR: + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.port\n"); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "port: %d\n", + config->source.port.port); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "num_lanes: %d\n", + config->source.port.num_lanes); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "timeout: %d\n", + config->source.port.timeout); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "compression: %d\n", + config->source.port.compression); + break; + case IA_CSS_INPUT_MODE_TPG: + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.tpg\n"); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "id: %d\n", + config->source.tpg.id); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", + config->source.tpg.mode); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "x_mask: 0x%x\n", + config->source.tpg.x_mask); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "x_delta: %d\n", + config->source.tpg.x_delta); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "y_mask: 0x%x\n", + config->source.tpg.y_mask); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "y_delta: %d\n", + config->source.tpg.y_delta); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "xy_mask: 0x%x\n", + config->source.tpg.xy_mask); + break; + case IA_CSS_INPUT_MODE_PRBS: + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "source.prbs\n"); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "id: %d\n", + config->source.prbs.id); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "h_blank: %d\n", + config->source.prbs.h_blank); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "v_blank: %d\n", + config->source.prbs.v_blank); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "seed: 0x%x\n", + config->source.prbs.seed); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "seed1: 0x%x\n", + config->source.prbs.seed1); + break; + default: + case IA_CSS_INPUT_MODE_FIFO: + case IA_CSS_INPUT_MODE_MEMORY: + break; + } +} + +void +ia_css_debug_dump_mipi_buffer_config( + const struct ia_css_mipi_buffer_config *config) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "size_mem_words: %d\n", + config->size_mem_words); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "nof_mipi_buffers: %d\n", + config->nof_mipi_buffers); +} + +void +ia_css_debug_dump_metadata_config( + const struct ia_css_metadata_config *config) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "data_type: %d\n", + config->data_type); + ia_css_debug_dump_resolution(&config->resolution, "resolution"); +} + +void +ia_css_debug_dump_stream_config( + const struct ia_css_stream_config *config, + int num_pipes) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%s()\n", __func__); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "num_pipes: %d\n", num_pipes); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "mode: %d\n", config->mode); + ia_css_debug_dump_stream_config_source(config); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "channel_id: %d\n", + config->channel_id); + ia_css_debug_dump_resolution(&config->input_config.input_res, "input_res"); + ia_css_debug_dump_resolution(&config->input_config.effective_res, "effective_res"); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "format: %d\n", + config->input_config.format); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "bayer_order: %d\n", + config->input_config.bayer_order); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sensor_binning_factor: %d\n", + config->sensor_binning_factor); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "pixels_per_clock: %d\n", + config->pixels_per_clock); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "online: %d\n", + config->online); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "init_num_cont_raw_buf: %d\n", + config->init_num_cont_raw_buf); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "target_num_cont_raw_buf: %d\n", + config->target_num_cont_raw_buf); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "pack_raw_pixels: %d\n", + config->pack_raw_pixels); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "continuous: %d\n", + config->continuous); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "flash_gpio_pin: %d\n", + config->flash_gpio_pin); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "left_padding: %d\n", + config->left_padding); + ia_css_debug_dump_mipi_buffer_config(&config->mipi_buffer_config); + ia_css_debug_dump_metadata_config(&config->metadata_config); +} + +/* + Trace support. + + This tracer is using a buffer to trace the flow of the FW and dump misc values (see below for details). + Currently, support is only for SKC. + To enable support for other platforms: + - Allocate a buffer for tracing in DMEM. The longer the better. + - Use the DBG_init routine in sp.hive.c to initiatilize the tracer with the address and size selected. + - Add trace points in the SP code wherever needed. + - Enable the dump below with the required address and required adjustments. + Dump is called at the end of ia_css_debug_dump_sp_state(). +*/ + +/* + dump_trace() : dump the trace points from DMEM2. + for every trace point, the following are printed: index, major:minor and the 16-bit attached value. + The routine looks for the first 0, and then prints from it cyclically. + Data forma in DMEM2: + first 4 DWORDS: header + DWORD 0: data description + byte 0: version + byte 1: number of threads (for future use) + byte 2+3: number ot TPs + DWORD 1: command byte + data (for future use) + byte 0: command + byte 1-3: command signature + DWORD 2-3: additional data (for future use) + Following data is 4-byte oriented: + byte 0: major + byte 1: minor + byte 2-3: data +*/ +#if TRACE_ENABLE_SP0 || TRACE_ENABLE_SP1 || TRACE_ENABLE_ISP +#ifndef ISP2401 +static void debug_dump_one_trace(TRACE_CORE_ID proc_id) +#else +static void debug_dump_one_trace(enum TRACE_CORE_ID proc_id) +#endif +{ +#if defined(HAS_TRACER_V2) + uint32_t start_addr; + uint32_t start_addr_data; + uint32_t item_size; +#ifndef ISP2401 + uint32_t tmp; +#else + uint8_t tid_val; + enum TRACE_DUMP_FORMAT dump_format; +#endif + int i, j, max_trace_points, point_num, limit = -1; + /* using a static buffer here as the driver has issues allocating memory */ + static uint32_t trace_read_buf[TRACE_BUFF_SIZE] = {0}; +#ifdef ISP2401 + static struct trace_header_t header; + uint8_t *header_arr; +#endif + + /* read the header and parse it */ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "~~~ Tracer "); + switch (proc_id) + { + case TRACE_SP0_ID: + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP0"); + start_addr = TRACE_SP0_ADDR; + start_addr_data = TRACE_SP0_DATA_ADDR; + item_size = TRACE_SP0_ITEM_SIZE; + max_trace_points = TRACE_SP0_MAX_POINTS; + break; + case TRACE_SP1_ID: + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP1"); + start_addr = TRACE_SP1_ADDR; + start_addr_data = TRACE_SP1_DATA_ADDR; + item_size = TRACE_SP1_ITEM_SIZE; + max_trace_points = TRACE_SP1_MAX_POINTS; + break; + case TRACE_ISP_ID: + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ISP"); + start_addr = TRACE_ISP_ADDR; + start_addr_data = TRACE_ISP_DATA_ADDR; + item_size = TRACE_ISP_ITEM_SIZE; + max_trace_points = TRACE_ISP_MAX_POINTS; + break; + default: + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\ttraces are not supported for this processor ID - exiting\n"); + return; + } +#ifndef ISP2401 + tmp = ia_css_device_load_uint32(start_addr); + point_num = (tmp >> 16) & 0xFFFF; +#endif + +#ifndef ISP2401 + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, " ver %d %d points\n", tmp & 0xFF, point_num); + if ((tmp & 0xFF) != TRACER_VER) { +#else + /* Loading byte-by-byte as using the master routine had issues */ + header_arr = (uint8_t *)&header; + for (i = 0; i < (int)sizeof(struct trace_header_t); i++) + header_arr[i] = ia_css_device_load_uint8(start_addr + (i)); + + point_num = header.max_tracer_points; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, " ver %d %d points\n", header.version, point_num); + if ((header.version & 0xFF) != TRACER_VER) { +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tUnknown version - exiting\n"); + return; + } + if (point_num > max_trace_points) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tToo many points - exiting\n"); + return; + } + /* copy the TPs and find the first 0 */ + for (i = 0; i < point_num; i++) { + trace_read_buf[i] = ia_css_device_load_uint32(start_addr_data + (i * item_size)); + if ((limit == (-1)) && (trace_read_buf[i] == 0)) + limit = i; + } +#ifdef ISP2401 + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "Status:\n"); + for (i = 0; i < SH_CSS_MAX_SP_THREADS; i++) + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\tT%d: %3d (%02x) %6d (%04x) %10d (%08x)\n", i, + header.thr_status_byte[i], header.thr_status_byte[i], + header.thr_status_word[i], header.thr_status_word[i], + header.thr_status_dword[i], header.thr_status_dword[i]); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "Scratch:\n"); + for (i = 0; i < MAX_SCRATCH_DATA; i++) + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "%10d (%08x) ", + header.scratch_debug[i], header.scratch_debug[i]); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\n"); + +#endif + /* two 0s in the beginning: empty buffer */ + if ((trace_read_buf[0] == 0) && (trace_read_buf[1] == 0)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "\t\tEmpty tracer - exiting\n"); + return; + } + /* no overrun: start from 0 */ + if ((limit == point_num-1) || /* first 0 is at the end - border case */ + (trace_read_buf[limit+1] == 0)) /* did not make a full cycle after the memset */ + limit = 0; + /* overrun: limit is the first non-zero after the first zero */ + else + limit++; + + /* print the TPs */ + for (i = 0; i < point_num; i++) { + j = (limit + i) % point_num; + if (trace_read_buf[j]) + { +#ifndef ISP2401 + TRACE_DUMP_FORMAT dump_format = FIELD_FORMAT_UNPACK(trace_read_buf[j]); +#else + + tid_val = FIELD_TID_UNPACK(trace_read_buf[j]); + dump_format = TRACE_DUMP_FORMAT_POINT; + + /* + * When tid value is 111b, the data will be interpreted differently: + * tid val is ignored, major field contains 2 bits (msb) for format type + */ + if (tid_val == FIELD_TID_SEL_FORMAT_PAT) { + dump_format = FIELD_FORMAT_UNPACK(trace_read_buf[j]); + } +#endif + switch (dump_format) + { + case TRACE_DUMP_FORMAT_POINT: + ia_css_debug_dtrace( +#ifndef ISP2401 + IA_CSS_DEBUG_TRACE, "\t\t%d %d:%d value - %d\n", + j, FIELD_MAJOR_UNPACK(trace_read_buf[j]), +#else + IA_CSS_DEBUG_TRACE, "\t\t%d T%d %d:%d value - %x (%d)\n", + j, + tid_val, + FIELD_MAJOR_UNPACK(trace_read_buf[j]), +#endif + FIELD_MINOR_UNPACK(trace_read_buf[j]), +#ifdef ISP2401 + FIELD_VALUE_UNPACK(trace_read_buf[j]), +#endif + FIELD_VALUE_UNPACK(trace_read_buf[j])); + break; +#ifndef ISP2401 + case TRACE_DUMP_FORMAT_VALUE24_HEX: +#else + case TRACE_DUMP_FORMAT_POINT_NO_TID: +#endif + ia_css_debug_dtrace( +#ifndef ISP2401 + IA_CSS_DEBUG_TRACE, "\t\t%d, %d, 24bit value %x H\n", +#else + IA_CSS_DEBUG_TRACE, "\t\t%d %d:%d value - %x (%d)\n", +#endif + j, +#ifndef ISP2401 + FIELD_MAJOR_UNPACK(trace_read_buf[j]), + FIELD_VALUE_24_UNPACK(trace_read_buf[j])); +#else + FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]), + FIELD_MINOR_UNPACK(trace_read_buf[j]), + FIELD_VALUE_UNPACK(trace_read_buf[j]), + FIELD_VALUE_UNPACK(trace_read_buf[j])); +#endif + break; +#ifndef ISP2401 + case TRACE_DUMP_FORMAT_VALUE24_DEC: +#else + case TRACE_DUMP_FORMAT_VALUE24: +#endif + ia_css_debug_dtrace( +#ifndef ISP2401 + IA_CSS_DEBUG_TRACE, "\t\t%d, %d, 24bit value %d D\n", +#else + IA_CSS_DEBUG_TRACE, "\t\t%d, %d, 24bit value %x (%d)\n", +#endif + j, + FIELD_MAJOR_UNPACK(trace_read_buf[j]), +#ifdef ISP2401 + FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]), + FIELD_VALUE_24_UNPACK(trace_read_buf[j]), +#endif + FIELD_VALUE_24_UNPACK(trace_read_buf[j])); + break; +#ifdef ISP2401 + +#endif + case TRACE_DUMP_FORMAT_VALUE24_TIMING: + ia_css_debug_dtrace( + IA_CSS_DEBUG_TRACE, "\t\t%d, %d, timing %x\n", + j, +#ifndef ISP2401 + FIELD_MAJOR_UNPACK(trace_read_buf[j]), +#else + FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]), +#endif + FIELD_VALUE_24_UNPACK(trace_read_buf[j])); + break; + case TRACE_DUMP_FORMAT_VALUE24_TIMING_DELTA: + ia_css_debug_dtrace( + IA_CSS_DEBUG_TRACE, "\t\t%d, %d, timing delta %x\n", + j, +#ifndef ISP2401 + FIELD_MAJOR_UNPACK(trace_read_buf[j]), +#else + FIELD_MAJOR_W_FMT_UNPACK(trace_read_buf[j]), +#endif + FIELD_VALUE_24_UNPACK(trace_read_buf[j])); + break; + default: + ia_css_debug_dtrace( + IA_CSS_DEBUG_TRACE, + "no such trace dump format %d", +#ifndef ISP2401 + FIELD_FORMAT_UNPACK(trace_read_buf[j])); +#else + dump_format); +#endif + break; + } + } + } +#else + (void)proc_id; +#endif /* HAS_TRACER_V2 */ +} +#endif /* TRACE_ENABLE_SP0 || TRACE_ENABLE_SP1 || TRACE_ENABLE_ISP */ + +void ia_css_debug_dump_trace(void) +{ +#if TRACE_ENABLE_SP0 + debug_dump_one_trace(TRACE_SP0_ID); +#endif +#if TRACE_ENABLE_SP1 + debug_dump_one_trace(TRACE_SP1_ID); +#endif +#if TRACE_ENABLE_ISP + debug_dump_one_trace(TRACE_ISP_ID); +#endif +} + +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) +/* Tagger state dump function. The tagger is only available when the CSS + * contains an input system (2400 or 2401). */ +void ia_css_debug_tagger_state(void) +{ + unsigned int i; + unsigned int HIVE_ADDR_tagger_frames; + ia_css_tagger_buf_sp_elem_t tbuf_frames[MAX_CB_ELEMS_FOR_TAGGER]; + + HIVE_ADDR_tagger_frames = sh_css_sp_fw.info.sp.tagger_frames_addr; + + /* This variable is not used in crun */ + (void)HIVE_ADDR_tagger_frames; + + /* 2400 and 2401 only have 1 SP, so the tagger lives on SP0 */ + sp_dmem_load(SP0_ID, + (unsigned int)sp_address_of(tagger_frames), + tbuf_frames, + sizeof(tbuf_frames)); + + ia_css_debug_dtrace(2, "Tagger Info:\n"); + for (i = 0; i < MAX_CB_ELEMS_FOR_TAGGER; i++) { + ia_css_debug_dtrace(2, "\t tagger frame[%d]: exp_id=%d, marked=%d, locked=%d\n", + i, tbuf_frames[i].exp_id, tbuf_frames[i].mark, tbuf_frames[i].lock); + } + +} +#endif /* defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) */ + +#ifdef ISP2401 +void ia_css_debug_pc_dump(sp_ID_t id, unsigned int num_of_dumps) +{ + unsigned int pc; + unsigned int i; + hrt_data sc = sp_ctrl_load(id, SP_SC_REG); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d Status reg: 0x%X\n", id, sc); + sc = sp_ctrl_load(id, SP_CTRL_SINK_REG); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d Stall reg: 0x%X\n", id, sc); + for (i = 0; i < num_of_dumps; i++) { + pc = sp_ctrl_load(id, SP_PC_REG); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "SP%-1d PC: 0x%X\n", id, pc); + } +} +#endif + +#if defined(HRT_SCHED) || defined(SH_CSS_DEBUG_SPMEM_DUMP_SUPPORT) +#include "spmem_dump.c" +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/event/interface/ia_css_event.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/event/interface/ia_css_event.h new file mode 100644 index 0000000000000000000000000000000000000000..ab1d9bed9fd8877cef979f25b3562ae547008684 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/event/interface/ia_css_event.h @@ -0,0 +1,46 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef _IA_CSS_EVENT_H +#define _IA_CSS_EVENT_H + +#include +#include "sw_event_global.h" /*event macros.TODO : Change File Name..???*/ + +bool ia_css_event_encode( + uint8_t *in, + uint8_t nr, + uint32_t *out); + +void ia_css_event_decode( + uint32_t event, + uint8_t *payload); + +#endif /*_IA_CSS_EVENT_H*/ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/event/src/event.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/event/src/event.c new file mode 100644 index 0000000000000000000000000000000000000000..2698c3e1adb0787fad774fbfa544bfce208c6811 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/event/src/event.c @@ -0,0 +1,126 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#include "sh_css_sp.h" + +#include "dma.h" /* N_DMA_CHANNEL_ID */ + +#include +#include "ia_css_binary.h" +#include "sh_css_hrt.h" +#include "sh_css_defs.h" +#include "sh_css_internal.h" +#include "ia_css_debug.h" +#include "ia_css_debug_internal.h" +#include "sh_css_legacy.h" + +#include "gdc_device.h" /* HRT_GDC_N */ + +/*#include "sp.h"*/ /* host2sp_enqueue_frame_data() */ + +#include "memory_access.h" + +#include "assert_support.h" +#include "platform_support.h" /* hrt_sleep() */ + +#include "ia_css_queue.h" /* host_sp_enqueue_XXX */ +#include "ia_css_event.h" /* ia_css_event_encode */ +/** + * @brief Encode the information into the software-event. + * Refer to "sw_event_public.h" for details. + */ +bool ia_css_event_encode( + uint8_t *in, + uint8_t nr, + uint32_t *out) +{ + bool ret; + uint32_t nr_of_bits; + uint32_t i; + assert(in != NULL); + assert(out != NULL); + OP___assert(nr > 0 && nr <= MAX_NR_OF_PAYLOADS_PER_SW_EVENT); + + /* initialize the output */ + *out = 0; + + /* get the number of bits per information */ + nr_of_bits = sizeof(uint32_t) * 8 / nr; + + /* compress the all inputs into a signle output */ + for (i = 0; i < nr; i++) { + *out <<= nr_of_bits; + *out |= in[i]; + } + + /* get the return value */ + ret = (nr > 0 && nr <= MAX_NR_OF_PAYLOADS_PER_SW_EVENT); + + return ret; +} + +void ia_css_event_decode( + uint32_t event, + uint8_t *payload) +{ + assert(payload[1] == 0); + assert(payload[2] == 0); + assert(payload[3] == 0); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_event_decode() enter:\n"); + + /* First decode according to the common case + * In case of a PORT_EOF event we overwrite with + * the specific values + * This is somewhat ugly but probably somewhat efficient + * (and it avoids some code duplication) + */ + payload[0] = event & 0xff; /*event_code */ + payload[1] = (event >> 8) & 0xff; + payload[2] = (event >> 16) & 0xff; + payload[3] = 0; + + switch (payload[0]) { + case SH_CSS_SP_EVENT_PORT_EOF: + payload[2] = 0; + payload[3] = (event >> 24) & 0xff; + break; + + case SH_CSS_SP_EVENT_ACC_STAGE_COMPLETE: + case SH_CSS_SP_EVENT_TIMER: + case SH_CSS_SP_EVENT_FRAME_TAGGED: + case SH_CSS_SP_EVENT_FW_WARNING: + case SH_CSS_SP_EVENT_FW_ASSERT: + payload[3] = (event >> 24) & 0xff; + break; + default: + break; + } +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/eventq/interface/ia_css_eventq.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/eventq/interface/ia_css_eventq.h new file mode 100644 index 0000000000000000000000000000000000000000..67eb8fdb33c51533792e21b5af68c44bff9cde80 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/eventq/interface/ia_css_eventq.h @@ -0,0 +1,69 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef _IA_CSS_EVENTQ_H +#define _IA_CSS_EVENTQ_H + +#include "ia_css_queue.h" /* queue APIs */ + +/** + * @brief HOST receives event from SP. + * + * @param[in] eventq_handle eventq_handle. + * @param[in] payload The event payload. + * @return 0 - Successfully dequeue. + * @return EINVAL - Invalid argument. + * @return ENODATA - Queue is empty. + */ +int ia_css_eventq_recv( + ia_css_queue_t *eventq_handle, + uint8_t *payload); + +/** + * @brief The Host sends the event to SP. + * The caller of this API will be blocked until the event + * is sent. + * + * @param[in] eventq_handle eventq_handle. + * @param[in] evt_id The event ID. + * @param[in] evt_payload_0 The event payload. + * @param[in] evt_payload_1 The event payload. + * @param[in] evt_payload_2 The event payload. + * @return 0 - Successfully enqueue. + * @return EINVAL - Invalid argument. + * @return ENOBUFS - Queue is full. + */ +int ia_css_eventq_send( + ia_css_queue_t *eventq_handle, + uint8_t evt_id, + uint8_t evt_payload_0, + uint8_t evt_payload_1, + uint8_t evt_payload_2); +#endif /* _IA_CSS_EVENTQ_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/eventq/src/eventq.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/eventq/src/eventq.c new file mode 100644 index 0000000000000000000000000000000000000000..56d6858890ec1dc2d0289947a651c517b39002fa --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/eventq/src/eventq.c @@ -0,0 +1,77 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_types.h" +#include "assert_support.h" +#include "ia_css_queue.h" /* sp2host_dequeue_irq_event() */ +#include "ia_css_eventq.h" +#include "ia_css_event.h" /* ia_css_event_encode() + ia_css_event_decode() + */ +#include "platform_support.h" /* hrt_sleep() */ + +int ia_css_eventq_recv( + ia_css_queue_t *eventq_handle, + uint8_t *payload) +{ + uint32_t sp_event; + int error; + + /* dequeue the IRQ event */ + error = ia_css_queue_dequeue(eventq_handle, &sp_event); + + /* check whether the IRQ event is available or not */ + if (!error) + ia_css_event_decode(sp_event, payload); + return error; +} + +/** + * @brief The Host sends the event to the SP. + * Refer to "sh_css_sp.h" for details. + */ +int ia_css_eventq_send( + ia_css_queue_t *eventq_handle, + uint8_t evt_id, + uint8_t evt_payload_0, + uint8_t evt_payload_1, + uint8_t evt_payload_2) +{ + uint8_t tmp[4]; + uint32_t sw_event; + int error = ENOSYS; + + /* + * Encode the queue type, the thread ID and + * the queue ID into the event. + */ + tmp[0] = evt_id; + tmp[1] = evt_payload_0; + tmp[2] = evt_payload_1; + tmp[3] = evt_payload_2; + ia_css_event_encode(tmp, 4, &sw_event); + + /* queue the software event (busy-waiting) */ + for ( ; ; ) { + error = ia_css_queue_enqueue(eventq_handle, sw_event); + if (ENOBUFS != error) { + /* We were able to successfully send the event + or had a real failure. return the status*/ + break; + } + /* Wait for the queue to be not full and try again*/ + hrt_sleep(); + } + return error; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/frame/interface/ia_css_frame.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/frame/interface/ia_css_frame.h new file mode 100644 index 0000000000000000000000000000000000000000..c7e07b79f4e55be5d91ac0f974ae61685fa9d872 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/frame/interface/ia_css_frame.h @@ -0,0 +1,180 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef __IA_CSS_FRAME_H__ +#define __IA_CSS_FRAME_H__ + +#ifdef ISP2401 +#include +#endif +#include +#include +#include "dma.h" + +/********************************************************************* +**** Frame INFO APIs +**********************************************************************/ +/** @brief Sets the given width and alignment to the frame info + * + * @param + * @param[in] info The info to which parameters would set + * @param[in] width The width to be set to info + * @param[in] aligned The aligned to be set to info + * @return + */ +void ia_css_frame_info_set_width(struct ia_css_frame_info *info, + unsigned int width, + unsigned int min_padded_width); + +/** @brief Sets the given format to the frame info + * + * @param + * @param[in] info The info to which parameters would set + * @param[in] format The format to be set to info + * @return + */ +void ia_css_frame_info_set_format(struct ia_css_frame_info *info, + enum ia_css_frame_format format); + +/** @brief Sets the frame info with the given parameters + * + * @param + * @param[in] info The info to which parameters would set + * @param[in] width The width to be set to info + * @param[in] height The height to be set to info + * @param[in] format The format to be set to info + * @param[in] aligned The aligned to be set to info + * @return + */ +void ia_css_frame_info_init(struct ia_css_frame_info *info, + unsigned int width, + unsigned int height, + enum ia_css_frame_format format, + unsigned int aligned); + +/** @brief Checks whether 2 frame infos has the same resolution + * + * @param + * @param[in] frame_a The first frame to be compared + * @param[in] frame_b The second frame to be compared + * @return Returns true if the frames are equal + */ +bool ia_css_frame_info_is_same_resolution( + const struct ia_css_frame_info *info_a, + const struct ia_css_frame_info *info_b); + +/** @brief Check the frame info is valid + * + * @param + * @param[in] info The frame attributes to be initialized + * @return The error code. + */ +enum ia_css_err ia_css_frame_check_info(const struct ia_css_frame_info *info); + +/********************************************************************* +**** Frame APIs +**********************************************************************/ + +/** @brief Initialize the plane depending on the frame type + * + * @param + * @param[in] frame The frame attributes to be initialized + * @return The error code. + */ +enum ia_css_err ia_css_frame_init_planes(struct ia_css_frame *frame); + +/** @brief Free an array of frames + * + * @param + * @param[in] num_frames The number of frames to be freed in the array + * @param[in] **frames_array The array of frames to be removed + * @return + */ +void ia_css_frame_free_multiple(unsigned int num_frames, + struct ia_css_frame **frames_array); + +/** @brief Allocate a CSS frame structure of given size in bytes.. + * + * @param frame The allocated frame. + * @param[in] size_bytes The frame size in bytes. + * @param[in] contiguous Allocate memory physically contiguously or not. + * @return The error code. + * + * Allocate a frame using the given size in bytes. + * The frame structure is partially null initialized. + */ +enum ia_css_err ia_css_frame_allocate_with_buffer_size( + struct ia_css_frame **frame, + const unsigned int size_bytes, + const bool contiguous); + +/** @brief Check whether 2 frames are same type + * + * @param + * @param[in] frame_a The first frame to be compared + * @param[in] frame_b The second frame to be compared + * @return Returns true if the frames are equal + */ +bool ia_css_frame_is_same_type( + const struct ia_css_frame *frame_a, + const struct ia_css_frame *frame_b); + +/** @brief Configure a dma port from frame info + * + * @param + * @param[in] config The DAM port configuration + * @param[in] info The frame info + * @return + */ +void ia_css_dma_configure_from_info( + struct dma_port_config *config, + const struct ia_css_frame_info *info); + +#ifdef ISP2401 +/** @brief Finds the cropping resolution + * This function finds the maximum cropping resolution in an input image keeping + * the aspect ratio for the given output resolution.Calculates the coordinates + * for cropping from the center and returns the starting pixel location of the + * region in the input image. Also returns the dimension of the cropping + * resolution. + * + * @param + * @param[in] in_res Resolution of input image + * @param[in] out_res Resolution of output image + * @param[out] crop_res Crop resolution of input image + * @return Returns IA_CSS_SUCCESS or IA_CSS_ERR_INVALID_ARGUMENTS on error + */ +enum ia_css_err +ia_css_frame_find_crop_resolution(const struct ia_css_resolution *in_res, + const struct ia_css_resolution *out_res, + struct ia_css_resolution *crop_res); + +#endif +#endif /* __IA_CSS_FRAME_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/frame/interface/ia_css_frame_comm.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/frame/interface/ia_css_frame_comm.h new file mode 100644 index 0000000000000000000000000000000000000000..a469e0afb2b5b5fc1118b53145ff9435cb5467d3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/frame/interface/ia_css_frame_comm.h @@ -0,0 +1,132 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef __IA_CSS_FRAME_COMM_H__ +#define __IA_CSS_FRAME_COMM_H__ + +#include "type_support.h" +#include "platform_support.h" +#include "runtime/bufq/interface/ia_css_bufq_comm.h" +#include /* hrt_vaddress */ + +/* + * These structs are derived from structs defined in ia_css_types.h + * (just take out the "_sp" from the struct name to get the "original") + * All the fields that are not needed by the SP are removed. + */ +struct ia_css_frame_sp_plane { + unsigned int offset; /* offset in bytes to start of frame data */ + /* offset is wrt data in sh_css_sp_sp_frame */ +}; + +struct ia_css_frame_sp_binary_plane { + unsigned int size; + struct ia_css_frame_sp_plane data; +}; + +struct ia_css_frame_sp_yuv_planes { + struct ia_css_frame_sp_plane y; + struct ia_css_frame_sp_plane u; + struct ia_css_frame_sp_plane v; +}; + +struct ia_css_frame_sp_nv_planes { + struct ia_css_frame_sp_plane y; + struct ia_css_frame_sp_plane uv; +}; + +struct ia_css_frame_sp_rgb_planes { + struct ia_css_frame_sp_plane r; + struct ia_css_frame_sp_plane g; + struct ia_css_frame_sp_plane b; +}; + +struct ia_css_frame_sp_plane6 { + struct ia_css_frame_sp_plane r; + struct ia_css_frame_sp_plane r_at_b; + struct ia_css_frame_sp_plane gr; + struct ia_css_frame_sp_plane gb; + struct ia_css_frame_sp_plane b; + struct ia_css_frame_sp_plane b_at_r; +}; + +struct ia_css_sp_resolution { + uint16_t width; /* width of valid data in pixels */ + uint16_t height; /* Height of valid data in lines */ +}; + +/* + * Frame info struct. This describes the contents of an image frame buffer. + */ +struct ia_css_frame_sp_info { + struct ia_css_sp_resolution res; + uint16_t padded_width; /* stride of line in memory + (in pixels) */ + unsigned char format; /* format of the frame data */ + unsigned char raw_bit_depth; /* number of valid bits per pixel, + only valid for RAW bayer frames */ + unsigned char raw_bayer_order; /* bayer order, only valid + for RAW bayer frames */ + unsigned char padding[3]; /* Extend to 32 bit multiple */ +}; + +struct ia_css_buffer_sp { + union { + hrt_vaddress xmem_addr; + enum sh_css_queue_id queue_id; + } buf_src; + enum ia_css_buffer_type buf_type; +}; + +struct ia_css_frame_sp { + struct ia_css_frame_sp_info info; + struct ia_css_buffer_sp buf_attr; + union { + struct ia_css_frame_sp_plane raw; + struct ia_css_frame_sp_plane rgb; + struct ia_css_frame_sp_rgb_planes planar_rgb; + struct ia_css_frame_sp_plane yuyv; + struct ia_css_frame_sp_yuv_planes yuv; + struct ia_css_frame_sp_nv_planes nv; + struct ia_css_frame_sp_plane6 plane6; + struct ia_css_frame_sp_binary_plane binary; + } planes; +}; + +void ia_css_frame_info_to_frame_sp_info( + struct ia_css_frame_sp_info *sp_info, + const struct ia_css_frame_info *info); + +void ia_css_resolution_to_sp_resolution( + struct ia_css_sp_resolution *sp_info, + const struct ia_css_resolution *info); + +#endif /*__IA_CSS_FRAME_COMM_H__*/ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/frame/src/frame.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/frame/src/frame.c new file mode 100644 index 0000000000000000000000000000000000000000..25e9d88dc9300453a5660598c24acd58c162b40b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/frame/src/frame.c @@ -0,0 +1,1027 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#include "ia_css_frame.h" +#include +#include "assert_support.h" +#include "ia_css_debug.h" +#include "isp.h" +#include "sh_css_internal.h" +#include "memory_access.h" + + +#define NV12_TILEY_TILE_WIDTH 128 +#define NV12_TILEY_TILE_HEIGHT 32 + +/************************************************************************** +** Static functions declarations +**************************************************************************/ +static void frame_init_plane(struct ia_css_frame_plane *plane, + unsigned int width, + unsigned int stride, + unsigned int height, + unsigned int offset); + +static void frame_init_single_plane(struct ia_css_frame *frame, + struct ia_css_frame_plane *plane, + unsigned int height, + unsigned int subpixels_per_line, + unsigned int bytes_per_pixel); + +static void frame_init_raw_single_plane( + struct ia_css_frame *frame, + struct ia_css_frame_plane *plane, + unsigned int height, + unsigned int subpixels_per_line, + unsigned int bits_per_pixel); + +static void frame_init_mipi_plane(struct ia_css_frame *frame, + struct ia_css_frame_plane *plane, + unsigned int height, + unsigned int subpixels_per_line, + unsigned int bytes_per_pixel); + +static void frame_init_nv_planes(struct ia_css_frame *frame, + unsigned int horizontal_decimation, + unsigned int vertical_decimation, + unsigned int bytes_per_element); + +static void frame_init_yuv_planes(struct ia_css_frame *frame, + unsigned int horizontal_decimation, + unsigned int vertical_decimation, + bool swap_uv, + unsigned int bytes_per_element); + +static void frame_init_rgb_planes(struct ia_css_frame *frame, + unsigned int bytes_per_element); + +static void frame_init_qplane6_planes(struct ia_css_frame *frame); + +static enum ia_css_err frame_allocate_buffer_data(struct ia_css_frame *frame); + +static enum ia_css_err frame_allocate_with_data(struct ia_css_frame **frame, + unsigned int width, + unsigned int height, + enum ia_css_frame_format format, + unsigned int padded_width, + unsigned int raw_bit_depth, + bool contiguous); + +static struct ia_css_frame *frame_create(unsigned int width, + unsigned int height, + enum ia_css_frame_format format, + unsigned int padded_width, + unsigned int raw_bit_depth, + bool contiguous, + bool valid); + +static unsigned +ia_css_elems_bytes_from_info( + const struct ia_css_frame_info *info); + +/************************************************************************** +** CSS API functions, exposed by ia_css.h +**************************************************************************/ + +void ia_css_frame_zero(struct ia_css_frame *frame) +{ + assert(frame != NULL); + mmgr_clear(frame->data, frame->data_bytes); +} + +enum ia_css_err ia_css_frame_allocate_from_info(struct ia_css_frame **frame, + const struct ia_css_frame_info *info) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + if (frame == NULL || info == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_allocate_from_info() enter:\n"); + err = + ia_css_frame_allocate(frame, info->res.width, info->res.height, + info->format, info->padded_width, + info->raw_bit_depth); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_allocate_from_info() leave:\n"); + return err; +} + +enum ia_css_err ia_css_frame_allocate(struct ia_css_frame **frame, + unsigned int width, + unsigned int height, + enum ia_css_frame_format format, + unsigned int padded_width, + unsigned int raw_bit_depth) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + if (frame == NULL || width == 0 || height == 0) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, +#ifndef ISP2401 + "ia_css_frame_allocate() enter: width=%d, height=%d, format=%d\n", + width, height, format); +#else + "ia_css_frame_allocate() enter: width=%d, height=%d, format=%d, padded_width=%d, raw_bit_depth=%d\n", + width, height, format, padded_width, raw_bit_depth); +#endif + + err = frame_allocate_with_data(frame, width, height, format, + padded_width, raw_bit_depth, false); + +#ifndef ISP2401 + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_allocate() leave: frame=%p\n", + frame ? *frame : (void *)-1); +#else + if ((*frame != NULL) && err == IA_CSS_SUCCESS) + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_allocate() leave: frame=%p, data(DDR address)=0x%x\n", *frame, (*frame)->data); + else + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_allocate() leave: frame=%p, data(DDR address)=0x%x\n", + (void *)-1, (unsigned int)-1); +#endif + + return err; +} + +enum ia_css_err ia_css_frame_map(struct ia_css_frame **frame, + const struct ia_css_frame_info *info, + const void *data, + uint16_t attribute, + void *context) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_frame *me; + assert(frame != NULL); + + /* Create the frame structure */ + err = ia_css_frame_create_from_info(&me, info); + + if (err != IA_CSS_SUCCESS) + return err; + + if (err == IA_CSS_SUCCESS) { + /* use mmgr_mmap to map */ + me->data = (ia_css_ptr) mmgr_mmap(data, + me->data_bytes, + attribute, context); + if (me->data == mmgr_NULL) + err = IA_CSS_ERR_INVALID_ARGUMENTS; + }; + + if (err != IA_CSS_SUCCESS) { + sh_css_free(me); +#ifndef ISP2401 + return err; +#else + me = NULL; +#endif + } + + *frame = me; + + return err; +} + +enum ia_css_err ia_css_frame_create_from_info(struct ia_css_frame **frame, + const struct ia_css_frame_info *info) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_frame *me; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_create_from_info() enter:\n"); + if (frame == NULL || info == NULL) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_create_from_info() leave:" + " invalid arguments\n"); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + me = frame_create(info->res.width, + info->res.height, + info->format, + info->padded_width, + info->raw_bit_depth, + false, + false); + if (me == NULL) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_create_from_info() leave:" + " frame create failed\n"); + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + } + + err = ia_css_frame_init_planes(me); + +#ifndef ISP2401 + if (err == IA_CSS_SUCCESS) + *frame = me; + else +#else + if (err != IA_CSS_SUCCESS) { +#endif + sh_css_free(me); +#ifdef ISP2401 + me = NULL; + } + + *frame = me; +#endif + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_frame_create_from_info() leave:\n"); + + return err; +} + +enum ia_css_err ia_css_frame_set_data(struct ia_css_frame *frame, + const ia_css_ptr mapped_data, + size_t data_bytes) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_set_data() enter:\n"); + if (frame == NULL) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_set_data() leave: NULL frame\n"); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + /* If we are setting a valid data. + * Make sure that there is enough + * room for the expected frame format + */ + if ((mapped_data != mmgr_NULL) && (frame->data_bytes > data_bytes)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_set_data() leave: invalid arguments\n"); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + frame->data = mapped_data; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_frame_set_data() leave:\n"); + + return err; +} + +enum ia_css_err ia_css_frame_allocate_contiguous(struct ia_css_frame **frame, + unsigned int width, + unsigned int height, + enum ia_css_frame_format format, + unsigned int padded_width, + unsigned int raw_bit_depth) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_allocate_contiguous() " +#ifndef ISP2401 + "enter: width=%d, height=%d, format=%d\n", + width, height, format); +#else + "enter: width=%d, height=%d, format=%d, padded_width=%d, raw_bit_depth=%d\n", + width, height, format, padded_width, raw_bit_depth); +#endif + + err = frame_allocate_with_data(frame, width, height, format, + padded_width, raw_bit_depth, true); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_allocate_contiguous() leave: frame=%p\n", + frame ? *frame : (void *)-1); + + return err; +} + +enum ia_css_err ia_css_frame_allocate_contiguous_from_info( + struct ia_css_frame **frame, + const struct ia_css_frame_info *info) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + assert(frame != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_allocate_contiguous_from_info() enter:\n"); + err = ia_css_frame_allocate_contiguous(frame, + info->res.width, + info->res.height, + info->format, + info->padded_width, + info->raw_bit_depth); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_allocate_contiguous_from_info() leave:\n"); + return err; +} + +void ia_css_frame_free(struct ia_css_frame *frame) +{ + IA_CSS_ENTER_PRIVATE("frame = %p", frame); + + if (frame != NULL) { + mmgr_free(frame->data); + sh_css_free(frame); + } + + IA_CSS_LEAVE_PRIVATE("void"); +} + +/************************************************************************** +** Module public functions +**************************************************************************/ + +enum ia_css_err ia_css_frame_check_info(const struct ia_css_frame_info *info) +{ + assert(info != NULL); + if (info->res.width == 0 || info->res.height == 0) + return IA_CSS_ERR_INVALID_ARGUMENTS; + return IA_CSS_SUCCESS; +} + +enum ia_css_err ia_css_frame_init_planes(struct ia_css_frame *frame) +{ + assert(frame != NULL); + + switch (frame->info.format) { + case IA_CSS_FRAME_FORMAT_MIPI: + frame_init_mipi_plane(frame, &frame->planes.raw, + frame->info.res.height, + frame->info.padded_width, + frame->info.raw_bit_depth <= 8 ? 1 : 2); + break; + case IA_CSS_FRAME_FORMAT_RAW_PACKED: + frame_init_raw_single_plane(frame, &frame->planes.raw, + frame->info.res.height, + frame->info.padded_width, + frame->info.raw_bit_depth); + break; + case IA_CSS_FRAME_FORMAT_RAW: + frame_init_single_plane(frame, &frame->planes.raw, + frame->info.res.height, + frame->info.padded_width, + frame->info.raw_bit_depth <= 8 ? 1 : 2); + break; + case IA_CSS_FRAME_FORMAT_RGB565: + frame_init_single_plane(frame, &frame->planes.rgb, + frame->info.res.height, + frame->info.padded_width, 2); + break; + case IA_CSS_FRAME_FORMAT_RGBA888: + frame_init_single_plane(frame, &frame->planes.rgb, + frame->info.res.height, + frame->info.padded_width * 4, 1); + break; + case IA_CSS_FRAME_FORMAT_PLANAR_RGB888: + frame_init_rgb_planes(frame, 1); + break; + /* yuyv and uyvu have the same frame layout, only the data + * positioning differs. + */ + case IA_CSS_FRAME_FORMAT_YUYV: + case IA_CSS_FRAME_FORMAT_UYVY: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8: + frame_init_single_plane(frame, &frame->planes.yuyv, + frame->info.res.height, + frame->info.padded_width * 2, 1); + break; + case IA_CSS_FRAME_FORMAT_YUV_LINE: + /* Needs 3 extra lines to allow vf_pp prefetching */ + frame_init_single_plane(frame, &frame->planes.yuyv, + frame->info.res.height * 3 / 2 + 3, + frame->info.padded_width, 1); + break; + case IA_CSS_FRAME_FORMAT_NV11: + frame_init_nv_planes(frame, 4, 1, 1); + break; + /* nv12 and nv21 have the same frame layout, only the data + * positioning differs. + */ + case IA_CSS_FRAME_FORMAT_NV12: + case IA_CSS_FRAME_FORMAT_NV21: + case IA_CSS_FRAME_FORMAT_NV12_TILEY: + frame_init_nv_planes(frame, 2, 2, 1); + break; + case IA_CSS_FRAME_FORMAT_NV12_16: + frame_init_nv_planes(frame, 2, 2, 2); + break; + /* nv16 and nv61 have the same frame layout, only the data + * positioning differs. + */ + case IA_CSS_FRAME_FORMAT_NV16: + case IA_CSS_FRAME_FORMAT_NV61: + frame_init_nv_planes(frame, 2, 1, 1); + break; + case IA_CSS_FRAME_FORMAT_YUV420: + frame_init_yuv_planes(frame, 2, 2, false, 1); + break; + case IA_CSS_FRAME_FORMAT_YUV422: + frame_init_yuv_planes(frame, 2, 1, false, 1); + break; + case IA_CSS_FRAME_FORMAT_YUV444: + frame_init_yuv_planes(frame, 1, 1, false, 1); + break; + case IA_CSS_FRAME_FORMAT_YUV420_16: + frame_init_yuv_planes(frame, 2, 2, false, 2); + break; + case IA_CSS_FRAME_FORMAT_YUV422_16: + frame_init_yuv_planes(frame, 2, 1, false, 2); + break; + case IA_CSS_FRAME_FORMAT_YV12: + frame_init_yuv_planes(frame, 2, 2, true, 1); + break; + case IA_CSS_FRAME_FORMAT_YV16: + frame_init_yuv_planes(frame, 2, 1, true, 1); + break; + case IA_CSS_FRAME_FORMAT_QPLANE6: + frame_init_qplane6_planes(frame); + break; + case IA_CSS_FRAME_FORMAT_BINARY_8: + frame_init_single_plane(frame, &frame->planes.binary.data, + frame->info.res.height, + frame->info.padded_width, 1); + frame->planes.binary.size = 0; + break; + default: + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + return IA_CSS_SUCCESS; +} + +void ia_css_frame_info_set_width(struct ia_css_frame_info *info, + unsigned int width, + unsigned int min_padded_width) +{ + unsigned int align; + + IA_CSS_ENTER_PRIVATE("info = %p,width = %d, minimum padded width = %d", + info, width, min_padded_width); + if (info == NULL) { + IA_CSS_ERROR("NULL input parameter"); + IA_CSS_LEAVE_PRIVATE(""); + return; + } + if (min_padded_width > width) + align = min_padded_width; + else + align = width; + + info->res.width = width; + /* frames with a U and V plane of 8 bits per pixel need to have + all planes aligned, this means double the alignment for the + Y plane if the horizontal decimation is 2. */ + if (info->format == IA_CSS_FRAME_FORMAT_YUV420 || + info->format == IA_CSS_FRAME_FORMAT_YV12 || + info->format == IA_CSS_FRAME_FORMAT_NV12 || + info->format == IA_CSS_FRAME_FORMAT_NV21 || + info->format == IA_CSS_FRAME_FORMAT_BINARY_8 || + info->format == IA_CSS_FRAME_FORMAT_YUV_LINE) + info->padded_width = + CEIL_MUL(align, 2 * HIVE_ISP_DDR_WORD_BYTES); + else if (info->format == IA_CSS_FRAME_FORMAT_NV12_TILEY) + info->padded_width = CEIL_MUL(align, NV12_TILEY_TILE_WIDTH); + else if (info->format == IA_CSS_FRAME_FORMAT_RAW || + info->format == IA_CSS_FRAME_FORMAT_RAW_PACKED) + info->padded_width = CEIL_MUL(align, 2 * ISP_VEC_NELEMS); + else { + info->padded_width = CEIL_MUL(align, HIVE_ISP_DDR_WORD_BYTES); + } + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_frame_info_set_format(struct ia_css_frame_info *info, + enum ia_css_frame_format format) +{ + assert(info != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_info_set_format() enter:\n"); + info->format = format; +} + +void ia_css_frame_info_init(struct ia_css_frame_info *info, + unsigned int width, + unsigned int height, + enum ia_css_frame_format format, + unsigned int aligned) +{ + IA_CSS_ENTER_PRIVATE("info = %p, width = %d, height = %d, format = %d, aligned = %d", + info, width, height, format, aligned); + if (info == NULL) { + IA_CSS_ERROR("NULL input parameter"); + IA_CSS_LEAVE_PRIVATE(""); + return; + } + info->res.height = height; + info->format = format; + ia_css_frame_info_set_width(info, width, aligned); + IA_CSS_LEAVE_PRIVATE(""); +} + +void ia_css_frame_free_multiple(unsigned int num_frames, + struct ia_css_frame **frames_array) +{ + unsigned int i; + for (i = 0; i < num_frames; i++) { + if (frames_array[i]) { + ia_css_frame_free(frames_array[i]); + frames_array[i] = NULL; + } + } +} + +enum ia_css_err ia_css_frame_allocate_with_buffer_size( + struct ia_css_frame **frame, + const unsigned int buffer_size_bytes, + const bool contiguous) +{ + /* AM: Body coppied from frame_allocate_with_data(). */ + enum ia_css_err err; + struct ia_css_frame *me = frame_create(0, 0, + IA_CSS_FRAME_FORMAT_NUM,/* Not valid format yet */ + 0, 0, contiguous, false); + + if (me == NULL) + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + + /* Get the data size */ + me->data_bytes = buffer_size_bytes; + + err = frame_allocate_buffer_data(me); + + if (err != IA_CSS_SUCCESS) { + sh_css_free(me); +#ifndef ISP2401 + return err; +#else + me = NULL; +#endif + } + + *frame = me; + + return err; +} + +bool ia_css_frame_info_is_same_resolution( + const struct ia_css_frame_info *info_a, + const struct ia_css_frame_info *info_b) +{ + if (!info_a || !info_b) + return false; + return (info_a->res.width == info_b->res.width) && + (info_a->res.height == info_b->res.height); +} + +bool ia_css_frame_is_same_type(const struct ia_css_frame *frame_a, + const struct ia_css_frame *frame_b) +{ + bool is_equal = false; + const struct ia_css_frame_info *info_a = &frame_a->info, + *info_b = &frame_b->info; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_is_same_type() enter:\n"); + + if (!info_a || !info_b) + return false; + if (info_a->format != info_b->format) + return false; + if (info_a->padded_width != info_b->padded_width) + return false; + is_equal = ia_css_frame_info_is_same_resolution(info_a, info_b); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_frame_is_same_type() leave:\n"); + + return is_equal; +} + +void +ia_css_dma_configure_from_info( + struct dma_port_config *config, + const struct ia_css_frame_info *info) +{ + unsigned is_raw_packed = info->format == IA_CSS_FRAME_FORMAT_RAW_PACKED; + unsigned bits_per_pixel = is_raw_packed ? info->raw_bit_depth : ia_css_elems_bytes_from_info(info)*8; + unsigned pix_per_ddrword = HIVE_ISP_DDR_WORD_BITS / bits_per_pixel; + unsigned words_per_line = CEIL_DIV(info->padded_width, pix_per_ddrword); + unsigned elems_b = pix_per_ddrword; + + config->stride = HIVE_ISP_DDR_WORD_BYTES * words_per_line; + config->elems = (uint8_t)elems_b; + config->width = (uint16_t)info->res.width; + config->crop = 0; + assert(config->width <= info->padded_width); +} + +/************************************************************************** +** Static functions +**************************************************************************/ + +static void frame_init_plane(struct ia_css_frame_plane *plane, + unsigned int width, + unsigned int stride, + unsigned int height, + unsigned int offset) +{ + plane->height = height; + plane->width = width; + plane->stride = stride; + plane->offset = offset; +} + +static void frame_init_single_plane(struct ia_css_frame *frame, + struct ia_css_frame_plane *plane, + unsigned int height, + unsigned int subpixels_per_line, + unsigned int bytes_per_pixel) +{ + unsigned int stride; + + stride = subpixels_per_line * bytes_per_pixel; + /* Frame height needs to be even number - needed by hw ISYS2401 + In case of odd number, round up to even. + Images won't be impacted by this round up, + only needed by jpeg/embedded data. + As long as buffer allocation and release are using data_bytes, + there won't be memory leak. */ + frame->data_bytes = stride * CEIL_MUL2(height, 2); + frame_init_plane(plane, subpixels_per_line, stride, height, 0); + return; +} + +static void frame_init_raw_single_plane( + struct ia_css_frame *frame, + struct ia_css_frame_plane *plane, + unsigned int height, + unsigned int subpixels_per_line, + unsigned int bits_per_pixel) +{ + unsigned int stride; + assert(frame != NULL); + + stride = HIVE_ISP_DDR_WORD_BYTES * + CEIL_DIV(subpixels_per_line, + HIVE_ISP_DDR_WORD_BITS / bits_per_pixel); + frame->data_bytes = stride * height; + frame_init_plane(plane, subpixels_per_line, stride, height, 0); + return; +} + +static void frame_init_mipi_plane(struct ia_css_frame *frame, + struct ia_css_frame_plane *plane, + unsigned int height, + unsigned int subpixels_per_line, + unsigned int bytes_per_pixel) +{ + unsigned int stride; + + stride = subpixels_per_line * bytes_per_pixel; + frame->data_bytes = 8388608; /* 8*1024*1024 */ + frame->valid = false; + frame->contiguous = true; + frame_init_plane(plane, subpixels_per_line, stride, height, 0); + return; +} + +static void frame_init_nv_planes(struct ia_css_frame *frame, + unsigned int horizontal_decimation, + unsigned int vertical_decimation, + unsigned int bytes_per_element) +{ + unsigned int y_width = frame->info.padded_width; + unsigned int y_height = frame->info.res.height; + unsigned int uv_width; + unsigned int uv_height; + unsigned int y_bytes; + unsigned int uv_bytes; + unsigned int y_stride; + unsigned int uv_stride; + + assert(horizontal_decimation != 0 && vertical_decimation != 0); + + uv_width = 2 * (y_width / horizontal_decimation); + uv_height = y_height / vertical_decimation; + + if (IA_CSS_FRAME_FORMAT_NV12_TILEY == frame->info.format) { + y_width = CEIL_MUL(y_width, NV12_TILEY_TILE_WIDTH); + uv_width = CEIL_MUL(uv_width, NV12_TILEY_TILE_WIDTH); + y_height = CEIL_MUL(y_height, NV12_TILEY_TILE_HEIGHT); + uv_height = CEIL_MUL(uv_height, NV12_TILEY_TILE_HEIGHT); + } + + y_stride = y_width * bytes_per_element; + uv_stride = uv_width * bytes_per_element; + y_bytes = y_stride * y_height; + uv_bytes = uv_stride * uv_height; + + frame->data_bytes = y_bytes + uv_bytes; + frame_init_plane(&frame->planes.nv.y, y_width, y_stride, y_height, 0); + frame_init_plane(&frame->planes.nv.uv, uv_width, + uv_stride, uv_height, y_bytes); + return; +} + +static void frame_init_yuv_planes(struct ia_css_frame *frame, + unsigned int horizontal_decimation, + unsigned int vertical_decimation, + bool swap_uv, + unsigned int bytes_per_element) +{ + unsigned int y_width = frame->info.padded_width, + y_height = frame->info.res.height, + uv_width = y_width / horizontal_decimation, + uv_height = y_height / vertical_decimation, + y_stride, y_bytes, uv_bytes, uv_stride; + + y_stride = y_width * bytes_per_element; + uv_stride = uv_width * bytes_per_element; + y_bytes = y_stride * y_height; + uv_bytes = uv_stride * uv_height; + + frame->data_bytes = y_bytes + 2 * uv_bytes; + frame_init_plane(&frame->planes.yuv.y, y_width, y_stride, y_height, 0); + if (swap_uv) { + frame_init_plane(&frame->planes.yuv.v, uv_width, uv_stride, + uv_height, y_bytes); + frame_init_plane(&frame->planes.yuv.u, uv_width, uv_stride, + uv_height, y_bytes + uv_bytes); + } else { + frame_init_plane(&frame->planes.yuv.u, uv_width, uv_stride, + uv_height, y_bytes); + frame_init_plane(&frame->planes.yuv.v, uv_width, uv_stride, + uv_height, y_bytes + uv_bytes); + } + return; +} + +static void frame_init_rgb_planes(struct ia_css_frame *frame, + unsigned int bytes_per_element) +{ + unsigned int width = frame->info.res.width, + height = frame->info.res.height, stride, bytes; + + stride = width * bytes_per_element; + bytes = stride * height; + frame->data_bytes = 3 * bytes; + frame_init_plane(&frame->planes.planar_rgb.r, width, stride, height, 0); + frame_init_plane(&frame->planes.planar_rgb.g, + width, stride, height, 1 * bytes); + frame_init_plane(&frame->planes.planar_rgb.b, + width, stride, height, 2 * bytes); + return; +} + +static void frame_init_qplane6_planes(struct ia_css_frame *frame) +{ + unsigned int width = frame->info.padded_width / 2, + height = frame->info.res.height / 2, bytes, stride; + + stride = width * 2; + bytes = stride * height; + + frame->data_bytes = 6 * bytes; + frame_init_plane(&frame->planes.plane6.r, + width, stride, height, 0 * bytes); + frame_init_plane(&frame->planes.plane6.r_at_b, + width, stride, height, 1 * bytes); + frame_init_plane(&frame->planes.plane6.gr, + width, stride, height, 2 * bytes); + frame_init_plane(&frame->planes.plane6.gb, + width, stride, height, 3 * bytes); + frame_init_plane(&frame->planes.plane6.b, + width, stride, height, 4 * bytes); + frame_init_plane(&frame->planes.plane6.b_at_r, + width, stride, height, 5 * bytes); + return; +} + +static enum ia_css_err frame_allocate_buffer_data(struct ia_css_frame *frame) +{ +#ifdef ISP2401 + IA_CSS_ENTER_LEAVE_PRIVATE("frame->data_bytes=%d\n", frame->data_bytes); +#endif + frame->data = mmgr_alloc_attr(frame->data_bytes, + frame->contiguous ? + MMGR_ATTRIBUTE_CONTIGUOUS : + MMGR_ATTRIBUTE_DEFAULT); + + if (frame->data == mmgr_NULL) + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + return IA_CSS_SUCCESS; +} + +static enum ia_css_err frame_allocate_with_data(struct ia_css_frame **frame, + unsigned int width, + unsigned int height, + enum ia_css_frame_format format, + unsigned int padded_width, + unsigned int raw_bit_depth, + bool contiguous) +{ + enum ia_css_err err; + struct ia_css_frame *me = frame_create(width, + height, + format, + padded_width, + raw_bit_depth, + contiguous, + true); + + if (me == NULL) + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + + err = ia_css_frame_init_planes(me); + + if (err == IA_CSS_SUCCESS) + err = frame_allocate_buffer_data(me); + + if (err != IA_CSS_SUCCESS) { + sh_css_free(me); +#ifndef ISP2401 + return err; +#else + me = NULL; +#endif + } + + *frame = me; + + return err; +} + +static struct ia_css_frame *frame_create(unsigned int width, + unsigned int height, + enum ia_css_frame_format format, + unsigned int padded_width, + unsigned int raw_bit_depth, + bool contiguous, + bool valid) +{ + struct ia_css_frame *me = sh_css_malloc(sizeof(*me)); + + if (me == NULL) + return NULL; + + memset(me, 0, sizeof(*me)); + me->info.res.width = width; + me->info.res.height = height; + me->info.format = format; + me->info.padded_width = padded_width; + me->info.raw_bit_depth = raw_bit_depth; + me->contiguous = contiguous; + me->valid = valid; + me->data_bytes = 0; + me->data = mmgr_NULL; + /* To indicate it is not valid frame. */ + me->dynamic_queue_id = (int)SH_CSS_INVALID_QUEUE_ID; + me->buf_type = IA_CSS_BUFFER_TYPE_INVALID; + + return me; +} + +static unsigned +ia_css_elems_bytes_from_info(const struct ia_css_frame_info *info) +{ + if (info->format == IA_CSS_FRAME_FORMAT_RGB565) + return 2; /* bytes per pixel */ + if (info->format == IA_CSS_FRAME_FORMAT_YUV420_16) + return 2; /* bytes per pixel */ + if (info->format == IA_CSS_FRAME_FORMAT_YUV422_16) + return 2; /* bytes per pixel */ + /* Note: Essentially NV12_16 is a 2 bytes per pixel format, this return value is used + * to configure DMA for the output buffer, + * At least in SKC this data is overwriten by isp_output_init.sp.c except for elements(elems), + * which is configured from this return value, + * NV12_16 is implemented by a double buffer of 8 bit elements hence elems should be configured as 8 */ + if (info->format == IA_CSS_FRAME_FORMAT_NV12_16) + return 1; /* bytes per pixel */ + + if (info->format == IA_CSS_FRAME_FORMAT_RAW + || (info->format == IA_CSS_FRAME_FORMAT_RAW_PACKED)) { + if (info->raw_bit_depth) + return CEIL_DIV(info->raw_bit_depth,8); + else + return 2; /* bytes per pixel */ + } + if (info->format == IA_CSS_FRAME_FORMAT_PLANAR_RGB888) + return 3; /* bytes per pixel */ + if (info->format == IA_CSS_FRAME_FORMAT_RGBA888) + return 4; /* bytes per pixel */ + if (info->format == IA_CSS_FRAME_FORMAT_QPLANE6) + return 2; /* bytes per pixel */ + return 1; /* Default is 1 byte per pixel */ +} + +void ia_css_frame_info_to_frame_sp_info( + struct ia_css_frame_sp_info *to, + const struct ia_css_frame_info *from) +{ + ia_css_resolution_to_sp_resolution(&to->res, &from->res); + to->padded_width = (uint16_t)from->padded_width; + to->format = (uint8_t)from->format; + to->raw_bit_depth = (uint8_t)from->raw_bit_depth; + to->raw_bayer_order = from->raw_bayer_order; +} + +void ia_css_resolution_to_sp_resolution( + struct ia_css_sp_resolution *to, + const struct ia_css_resolution *from) +{ + to->width = (uint16_t)from->width; + to->height = (uint16_t)from->height; +} +#ifdef ISP2401 + +enum ia_css_err +ia_css_frame_find_crop_resolution(const struct ia_css_resolution *in_res, + const struct ia_css_resolution *out_res, + struct ia_css_resolution *crop_res) +{ + uint32_t wd_even_ceil, ht_even_ceil; + uint32_t in_ratio, out_ratio; + + if ((in_res == NULL) || (out_res == NULL) || (crop_res == NULL)) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + IA_CSS_ENTER_PRIVATE("in(%ux%u) -> out(%ux%u)", in_res->width, + in_res->height, out_res->width, out_res->height); + + if ((in_res->width == 0) + || (in_res->height == 0) + || (out_res->width == 0) + || (out_res->height == 0)) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + if ((out_res->width > in_res->width) || + (out_res->height > in_res->height)) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + /* If aspect ratio (width/height) of out_res is higher than the aspect + * ratio of the in_res, then we crop vertically, otherwise we crop + * horizontally. + */ + in_ratio = in_res->width * out_res->height; + out_ratio = out_res->width * in_res->height; + + if (in_ratio == out_ratio) { + crop_res->width = in_res->width; + crop_res->height = in_res->height; + } else if (out_ratio > in_ratio) { + crop_res->width = in_res->width; + crop_res->height = ROUND_DIV(out_res->height * crop_res->width, + out_res->width); + } else { + crop_res->height = in_res->height; + crop_res->width = ROUND_DIV(out_res->width * crop_res->height, + out_res->height); + } + + /* Round new (cropped) width and height to an even number. + * binarydesc_calculate_bds_factor is such that we should consider as + * much of the input as possible. This is different only when we end up + * with an odd number in the last step. So, we take the next even number + * if it falls within the input, otherwise take the previous even no. + */ + wd_even_ceil = EVEN_CEIL(crop_res->width); + ht_even_ceil = EVEN_CEIL(crop_res->height); + if ((wd_even_ceil > in_res->width) || (ht_even_ceil > in_res->height)) { + crop_res->width = EVEN_FLOOR(crop_res->width); + crop_res->height = EVEN_FLOOR(crop_res->height); + } else { + crop_res->width = wd_even_ceil; + crop_res->height = ht_even_ceil; + } + + IA_CSS_LEAVE_PRIVATE("in(%ux%u) -> out(%ux%u)", crop_res->width, + crop_res->height, out_res->width, out_res->height); + return IA_CSS_SUCCESS; +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/ifmtr/interface/ia_css_ifmtr.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/ifmtr/interface/ia_css_ifmtr.h new file mode 100644 index 0000000000000000000000000000000000000000..d02bff1bbf46eb90f72b5001c2e947b89e820bb5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/ifmtr/interface/ia_css_ifmtr.h @@ -0,0 +1,49 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef __IA_CSS_IFMTR_H__ +#define __IA_CSS_IFMTR_H__ + +#include +#include +#include + +extern bool ifmtr_set_if_blocking_mode_reset; + +unsigned int ia_css_ifmtr_lines_needed_for_bayer_order( + const struct ia_css_stream_config *config); + +unsigned int ia_css_ifmtr_columns_needed_for_bayer_order( + const struct ia_css_stream_config *config); + +enum ia_css_err ia_css_ifmtr_configure(struct ia_css_stream_config *config, + struct ia_css_binary *binary); + +#endif /* __IA_CSS_IFMTR_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/ifmtr/src/ifmtr.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/ifmtr/src/ifmtr.c new file mode 100644 index 0000000000000000000000000000000000000000..a7c6bba7e09499c9c1aa640cbb8cfc77601a6649 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/ifmtr/src/ifmtr.c @@ -0,0 +1,568 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#include "system_global.h" + +#ifdef USE_INPUT_SYSTEM_VERSION_2 + +#include "ia_css_ifmtr.h" +#include +#include "sh_css_internal.h" +#include "input_formatter.h" +#include "assert_support.h" +#include "sh_css_sp.h" +#include "isp/modes/interface/input_buf.isp.h" + +/************************************************************ + * Static functions declarations + ************************************************************/ +static enum ia_css_err ifmtr_start_column( + const struct ia_css_stream_config *config, + unsigned int bin_in, + unsigned int *start_column); + +static enum ia_css_err ifmtr_input_start_line( + const struct ia_css_stream_config *config, + unsigned int bin_in, + unsigned int *start_line); + +static void ifmtr_set_if_blocking_mode( + const input_formatter_cfg_t * const config_a, + const input_formatter_cfg_t * const config_b); + +/************************************************************ + * Public functions + ************************************************************/ + +/* ISP expects GRBG bayer order, we skip one line and/or one row + * to correct in case the input bayer order is different. + */ +unsigned int ia_css_ifmtr_lines_needed_for_bayer_order( + const struct ia_css_stream_config *config) +{ + assert(config != NULL); + if ((IA_CSS_BAYER_ORDER_BGGR == config->input_config.bayer_order) + || (IA_CSS_BAYER_ORDER_GBRG == config->input_config.bayer_order)) + return 1; + + return 0; +} + +unsigned int ia_css_ifmtr_columns_needed_for_bayer_order( + const struct ia_css_stream_config *config) +{ + assert(config != NULL); + if ((IA_CSS_BAYER_ORDER_RGGB == config->input_config.bayer_order) + || (IA_CSS_BAYER_ORDER_GBRG == config->input_config.bayer_order)) + return 1; + + return 0; +} + +enum ia_css_err ia_css_ifmtr_configure(struct ia_css_stream_config *config, + struct ia_css_binary *binary) +{ + unsigned int start_line, start_column = 0, + cropped_height, + cropped_width, + num_vectors, + buffer_height = 2, + buffer_width, + two_ppc, + vmem_increment = 0, + deinterleaving = 0, + deinterleaving_b = 0, + width_a = 0, + width_b = 0, + bits_per_pixel, + vectors_per_buffer, + vectors_per_line = 0, + buffers_per_line = 0, + buf_offset_a = 0, + buf_offset_b = 0, + line_width = 0, + width_b_factor = 1, start_column_b, + left_padding = 0; + input_formatter_cfg_t if_a_config, if_b_config; + enum ia_css_stream_format input_format; + enum ia_css_err err = IA_CSS_SUCCESS; + uint8_t if_config_index; + + /* Determine which input formatter config set is targeted. */ + /* Index is equal to the CSI-2 port used. */ + enum ia_css_csi2_port port; + + if (binary) { + cropped_height = binary->in_frame_info.res.height; + cropped_width = binary->in_frame_info.res.width; + /* This should correspond to the input buffer definition for + ISP binaries in input_buf.isp.h */ + if (binary->info->sp.enable.continuous && binary->info->sp.pipeline.mode != IA_CSS_BINARY_MODE_COPY) + buffer_width = MAX_VECTORS_PER_INPUT_LINE_CONT * ISP_VEC_NELEMS; + else + buffer_width = binary->info->sp.input.max_width; + input_format = binary->input_format; + } else { + /* sp raw copy pipe (IA_CSS_PIPE_MODE_COPY): binary is NULL */ + cropped_height = config->input_config.input_res.height; + cropped_width = config->input_config.input_res.width; + buffer_width = MAX_VECTORS_PER_INPUT_LINE_CONT * ISP_VEC_NELEMS; + input_format = config->input_config.format; + } + two_ppc = config->pixels_per_clock == 2; + if (config->mode == IA_CSS_INPUT_MODE_SENSOR + || config->mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR) { + port = config->source.port.port; + if_config_index = (uint8_t) (port - IA_CSS_CSI2_PORT0); + } else if (config->mode == IA_CSS_INPUT_MODE_MEMORY) { + if_config_index = SH_CSS_IF_CONFIG_NOT_NEEDED; + } else { + if_config_index = 0; + } + + assert(if_config_index <= SH_CSS_MAX_IF_CONFIGS + || if_config_index == SH_CSS_IF_CONFIG_NOT_NEEDED); + + /* TODO: check to see if input is RAW and if current mode interprets + * RAW data in any particular bayer order. copy binary with output + * format other than raw should not result in dropping lines and/or + * columns. + */ + err = ifmtr_input_start_line(config, cropped_height, &start_line); + if (err != IA_CSS_SUCCESS) + return err; + err = ifmtr_start_column(config, cropped_width, &start_column); + if (err != IA_CSS_SUCCESS) + return err; + + if (config->left_padding == -1) + if (!binary) + /* sp raw copy pipe: set left_padding value */ + left_padding = 0; + else + left_padding = binary->left_padding; + else + left_padding = 2*ISP_VEC_NELEMS - config->left_padding; + + + if (left_padding) { + num_vectors = CEIL_DIV(cropped_width + left_padding, + ISP_VEC_NELEMS); + } else { + num_vectors = CEIL_DIV(cropped_width, ISP_VEC_NELEMS); + num_vectors *= buffer_height; + /* todo: in case of left padding, + num_vectors is vectors per line, + otherwise vectors per line * buffer_height. */ + } + + start_column_b = start_column; + + bits_per_pixel = input_formatter_get_alignment(INPUT_FORMATTER0_ID) + * 8 / ISP_VEC_NELEMS; + switch (input_format) { + case IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY: + if (two_ppc) { + vmem_increment = 1; + deinterleaving = 1; + deinterleaving_b = 1; + /* half lines */ + width_a = cropped_width * deinterleaving / 2; + width_b_factor = 2; + /* full lines */ + width_b = width_a * width_b_factor; + buffer_width *= deinterleaving * 2; + /* Patch from bayer to yuv */ + num_vectors *= deinterleaving; + buf_offset_b = buffer_width / 2 / ISP_VEC_NELEMS; + vectors_per_line = num_vectors / buffer_height; + /* Even lines are half size */ + line_width = vectors_per_line * + input_formatter_get_alignment(INPUT_FORMATTER0_ID) / + 2; + start_column /= 2; + } else { + vmem_increment = 1; + deinterleaving = 3; + width_a = cropped_width * deinterleaving / 2; + buffer_width = buffer_width * deinterleaving / 2; + /* Patch from bayer to yuv */ + num_vectors = num_vectors / 2 * deinterleaving; + start_column = start_column * deinterleaving / 2; + } + break; + case IA_CSS_STREAM_FORMAT_YUV420_8: + case IA_CSS_STREAM_FORMAT_YUV420_10: + case IA_CSS_STREAM_FORMAT_YUV420_16: + if (two_ppc) { + vmem_increment = 1; + deinterleaving = 1; + width_a = width_b = cropped_width * deinterleaving / 2; + buffer_width *= deinterleaving * 2; + num_vectors *= deinterleaving; + buf_offset_b = buffer_width / 2 / ISP_VEC_NELEMS; + vectors_per_line = num_vectors / buffer_height; + /* Even lines are half size */ + line_width = vectors_per_line * + input_formatter_get_alignment(INPUT_FORMATTER0_ID) / + 2; + start_column *= deinterleaving; + start_column /= 2; + start_column_b = start_column; + } else { + vmem_increment = 1; + deinterleaving = 1; + width_a = cropped_width * deinterleaving; + buffer_width *= deinterleaving * 2; + num_vectors *= deinterleaving; + start_column *= deinterleaving; + } + break; + case IA_CSS_STREAM_FORMAT_YUV422_8: + case IA_CSS_STREAM_FORMAT_YUV422_10: + case IA_CSS_STREAM_FORMAT_YUV422_16: + if (two_ppc) { + vmem_increment = 1; + deinterleaving = 1; + width_a = width_b = cropped_width * deinterleaving; + buffer_width *= deinterleaving * 2; + num_vectors *= deinterleaving; + start_column *= deinterleaving; + buf_offset_b = buffer_width / 2 / ISP_VEC_NELEMS; + start_column_b = start_column; + } else { + vmem_increment = 1; + deinterleaving = 2; + width_a = cropped_width * deinterleaving; + buffer_width *= deinterleaving; + num_vectors *= deinterleaving; + start_column *= deinterleaving; + } + break; + case IA_CSS_STREAM_FORMAT_RGB_444: + case IA_CSS_STREAM_FORMAT_RGB_555: + case IA_CSS_STREAM_FORMAT_RGB_565: + case IA_CSS_STREAM_FORMAT_RGB_666: + case IA_CSS_STREAM_FORMAT_RGB_888: + num_vectors *= 2; + if (two_ppc) { + deinterleaving = 2; /* BR in if_a, G in if_b */ + deinterleaving_b = 1; /* BR in if_a, G in if_b */ + buffers_per_line = 4; + start_column_b = start_column; + start_column *= deinterleaving; + start_column_b *= deinterleaving_b; + } else { + deinterleaving = 3; /* BGR */ + buffers_per_line = 3; + start_column *= deinterleaving; + } + vmem_increment = 1; + width_a = cropped_width * deinterleaving; + width_b = cropped_width * deinterleaving_b; + buffer_width *= buffers_per_line; + /* Patch from bayer to rgb */ + num_vectors = num_vectors / 2 * deinterleaving; + buf_offset_b = buffer_width / 2 / ISP_VEC_NELEMS; + break; + case IA_CSS_STREAM_FORMAT_RAW_6: + case IA_CSS_STREAM_FORMAT_RAW_7: + case IA_CSS_STREAM_FORMAT_RAW_8: + case IA_CSS_STREAM_FORMAT_RAW_10: + case IA_CSS_STREAM_FORMAT_RAW_12: + if (two_ppc) { + int crop_col = (start_column % 2) == 1; + vmem_increment = 2; + deinterleaving = 1; + width_a = width_b = cropped_width / 2; + + /* When two_ppc is enabled AND we need to crop one extra + * column, if_a crops by one extra and we swap the + * output offsets to interleave the bayer pattern in + * the correct order. + */ + buf_offset_a = crop_col ? 1 : 0; + buf_offset_b = crop_col ? 0 : 1; + start_column_b = start_column / 2; + start_column = start_column / 2 + crop_col; + } else { + vmem_increment = 1; + deinterleaving = 2; + if ((!binary) || (config->continuous && binary + && binary->info->sp.pipeline.mode == IA_CSS_BINARY_MODE_COPY)) { + /* !binary -> sp raw copy pipe, no deinterleaving */ + deinterleaving = 1; + } + width_a = cropped_width; + /* Must be multiple of deinterleaving */ + num_vectors = CEIL_MUL(num_vectors, deinterleaving); + } + buffer_height *= 2; + if ((!binary) || config->continuous) + /* !binary -> sp raw copy pipe */ + buffer_height *= 2; + vectors_per_line = CEIL_DIV(cropped_width, ISP_VEC_NELEMS); + vectors_per_line = CEIL_MUL(vectors_per_line, deinterleaving); + break; + case IA_CSS_STREAM_FORMAT_RAW_14: + case IA_CSS_STREAM_FORMAT_RAW_16: + if (two_ppc) { + num_vectors *= 2; + vmem_increment = 1; + deinterleaving = 2; + width_a = width_b = cropped_width; + /* B buffer is one line further */ + buf_offset_b = buffer_width / ISP_VEC_NELEMS; + bits_per_pixel *= 2; + } else { + vmem_increment = 1; + deinterleaving = 2; + width_a = cropped_width; + start_column /= deinterleaving; + } + buffer_height *= 2; + break; + case IA_CSS_STREAM_FORMAT_BINARY_8: + case IA_CSS_STREAM_FORMAT_GENERIC_SHORT1: + case IA_CSS_STREAM_FORMAT_GENERIC_SHORT2: + case IA_CSS_STREAM_FORMAT_GENERIC_SHORT3: + case IA_CSS_STREAM_FORMAT_GENERIC_SHORT4: + case IA_CSS_STREAM_FORMAT_GENERIC_SHORT5: + case IA_CSS_STREAM_FORMAT_GENERIC_SHORT6: + case IA_CSS_STREAM_FORMAT_GENERIC_SHORT7: + case IA_CSS_STREAM_FORMAT_GENERIC_SHORT8: + case IA_CSS_STREAM_FORMAT_YUV420_8_SHIFT: + case IA_CSS_STREAM_FORMAT_YUV420_10_SHIFT: + case IA_CSS_STREAM_FORMAT_EMBEDDED: + case IA_CSS_STREAM_FORMAT_USER_DEF1: + case IA_CSS_STREAM_FORMAT_USER_DEF2: + case IA_CSS_STREAM_FORMAT_USER_DEF3: + case IA_CSS_STREAM_FORMAT_USER_DEF4: + case IA_CSS_STREAM_FORMAT_USER_DEF5: + case IA_CSS_STREAM_FORMAT_USER_DEF6: + case IA_CSS_STREAM_FORMAT_USER_DEF7: + case IA_CSS_STREAM_FORMAT_USER_DEF8: + break; + } + if (width_a == 0) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + if (two_ppc) + left_padding /= 2; + + /* Default values */ + if (left_padding) + vectors_per_line = num_vectors; + if (!vectors_per_line) { + vectors_per_line = CEIL_MUL(num_vectors / buffer_height, + deinterleaving); + line_width = 0; + } + if (!line_width) + line_width = vectors_per_line * + input_formatter_get_alignment(INPUT_FORMATTER0_ID); + if (!buffers_per_line) + buffers_per_line = deinterleaving; + line_width = CEIL_MUL(line_width, + input_formatter_get_alignment(INPUT_FORMATTER0_ID) + * vmem_increment); + + vectors_per_buffer = buffer_height * buffer_width / ISP_VEC_NELEMS; + + if (config->mode == IA_CSS_INPUT_MODE_TPG && + ((binary && binary->info->sp.pipeline.mode == IA_CSS_BINARY_MODE_VIDEO) || + (!binary))) { + /* !binary -> sp raw copy pipe */ + /* workaround for TPG in video mode */ + start_line = 0; + start_column = 0; + cropped_height -= start_line; + width_a -= start_column; + } + + if_a_config.start_line = start_line; + if_a_config.start_column = start_column; + if_a_config.left_padding = left_padding / deinterleaving; + if_a_config.cropped_height = cropped_height; + if_a_config.cropped_width = width_a; + if_a_config.deinterleaving = deinterleaving; + if_a_config.buf_vecs = vectors_per_buffer; + if_a_config.buf_start_index = buf_offset_a; + if_a_config.buf_increment = vmem_increment; + if_a_config.buf_eol_offset = + buffer_width * bits_per_pixel / 8 - line_width; + if_a_config.is_yuv420_format = + (input_format == IA_CSS_STREAM_FORMAT_YUV420_8) + || (input_format == IA_CSS_STREAM_FORMAT_YUV420_10) + || (input_format == IA_CSS_STREAM_FORMAT_YUV420_16); + if_a_config.block_no_reqs = (config->mode != IA_CSS_INPUT_MODE_SENSOR); + + if (two_ppc) { + if (deinterleaving_b) { + deinterleaving = deinterleaving_b; + width_b = cropped_width * deinterleaving; + buffer_width *= deinterleaving; + /* Patch from bayer to rgb */ + num_vectors = num_vectors / 2 * + deinterleaving * width_b_factor; + vectors_per_line = num_vectors / buffer_height; + line_width = vectors_per_line * + input_formatter_get_alignment(INPUT_FORMATTER0_ID); + } + if_b_config.start_line = start_line; + if_b_config.start_column = start_column_b; + if_b_config.left_padding = left_padding / deinterleaving; + if_b_config.cropped_height = cropped_height; + if_b_config.cropped_width = width_b; + if_b_config.deinterleaving = deinterleaving; + if_b_config.buf_vecs = vectors_per_buffer; + if_b_config.buf_start_index = buf_offset_b; + if_b_config.buf_increment = vmem_increment; + if_b_config.buf_eol_offset = + buffer_width * bits_per_pixel / 8 - line_width; + if_b_config.is_yuv420_format = + input_format == IA_CSS_STREAM_FORMAT_YUV420_8 + || input_format == IA_CSS_STREAM_FORMAT_YUV420_10 + || input_format == IA_CSS_STREAM_FORMAT_YUV420_16; + if_b_config.block_no_reqs = + (config->mode != IA_CSS_INPUT_MODE_SENSOR); + + if (SH_CSS_IF_CONFIG_NOT_NEEDED != if_config_index) { + assert(if_config_index <= SH_CSS_MAX_IF_CONFIGS); + + ifmtr_set_if_blocking_mode(&if_a_config, &if_b_config); + /* Set the ifconfigs to SP group */ + sh_css_sp_set_if_configs(&if_a_config, &if_b_config, + if_config_index); + } + } else { + if (SH_CSS_IF_CONFIG_NOT_NEEDED != if_config_index) { + assert(if_config_index <= SH_CSS_MAX_IF_CONFIGS); + + ifmtr_set_if_blocking_mode(&if_a_config, NULL); + /* Set the ifconfigs to SP group */ + sh_css_sp_set_if_configs(&if_a_config, NULL, + if_config_index); + } + } + + return IA_CSS_SUCCESS; +} + +bool ifmtr_set_if_blocking_mode_reset = true; + +/************************************************************ + * Static functions + ************************************************************/ +static void ifmtr_set_if_blocking_mode( + const input_formatter_cfg_t * const config_a, + const input_formatter_cfg_t * const config_b) +{ + int i; + bool block[] = { false, false, false, false }; + assert(N_INPUT_FORMATTER_ID <= (sizeof(block) / sizeof(block[0]))); + +#if !defined(IS_ISP_2400_SYSTEM) +#error "ifmtr_set_if_blocking_mode: ISP_SYSTEM must be one of {IS_ISP_2400_SYSTEM}" +#endif + + block[INPUT_FORMATTER0_ID] = (bool)config_a->block_no_reqs; + if (NULL != config_b) + block[INPUT_FORMATTER1_ID] = (bool)config_b->block_no_reqs; + + /* TODO: next could cause issues when streams are started after + * eachother. */ + /*IF should not be reconfigured/reset from host */ + if (ifmtr_set_if_blocking_mode_reset) { + ifmtr_set_if_blocking_mode_reset = false; + for (i = 0; i < N_INPUT_FORMATTER_ID; i++) { + input_formatter_ID_t id = (input_formatter_ID_t) i; + input_formatter_rst(id); + input_formatter_set_fifo_blocking_mode(id, block[id]); + } + } + + return; +} + +static enum ia_css_err ifmtr_start_column( + const struct ia_css_stream_config *config, + unsigned int bin_in, + unsigned int *start_column) +{ + unsigned int in = config->input_config.input_res.width, start, + for_bayer = ia_css_ifmtr_columns_needed_for_bayer_order(config); + + if (bin_in + 2 * for_bayer > in) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + /* On the hardware, we want to use the middle of the input, so we + * divide the start column by 2. */ + start = (in - bin_in) / 2; + /* in case the number of extra columns is 2 or odd, we round the start + * column down */ + start &= ~0x1; + + /* now we add the one column (if needed) to correct for the bayer + * order). + */ + start += for_bayer; + *start_column = start; + return IA_CSS_SUCCESS; +} + +static enum ia_css_err ifmtr_input_start_line( + const struct ia_css_stream_config *config, + unsigned int bin_in, + unsigned int *start_line) +{ + unsigned int in = config->input_config.input_res.height, start, + for_bayer = ia_css_ifmtr_lines_needed_for_bayer_order(config); + + if (bin_in + 2 * for_bayer > in) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + /* On the hardware, we want to use the middle of the input, so we + * divide the start line by 2. On the simulator, we cannot handle extra + * lines at the end of the frame. + */ + start = (in - bin_in) / 2; + /* in case the number of extra lines is 2 or odd, we round the start + * line down. + */ + start &= ~0x1; + + /* now we add the one line (if needed) to correct for the bayer order */ + start += for_bayer; + *start_line = start; + return IA_CSS_SUCCESS; +} + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/inputfifo/interface/ia_css_inputfifo.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/inputfifo/interface/ia_css_inputfifo.h new file mode 100644 index 0000000000000000000000000000000000000000..47d0f7e53f473924eb64619879439c812c5f23e0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/inputfifo/interface/ia_css_inputfifo.h @@ -0,0 +1,69 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef _IA_CSS_INPUTFIFO_H +#define _IA_CSS_INPUTFIFO_H + +#include +#include + +#include "ia_css_stream_format.h" + +/* SP access */ +void ia_css_inputfifo_send_input_frame( + const unsigned short *data, + unsigned int width, + unsigned int height, + unsigned int ch_id, + enum ia_css_stream_format input_format, + bool two_ppc); + +void ia_css_inputfifo_start_frame( + unsigned int ch_id, + enum ia_css_stream_format input_format, + bool two_ppc); + +void ia_css_inputfifo_send_line( + unsigned int ch_id, + const unsigned short *data, + unsigned int width, + const unsigned short *data2, + unsigned int width2); + +void ia_css_inputfifo_send_embedded_line( + unsigned int ch_id, + enum ia_css_stream_format data_type, + const unsigned short *data, + unsigned int width); + +void ia_css_inputfifo_end_frame( + unsigned int ch_id); + +#endif /* _IA_CSS_INPUTFIFO_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/inputfifo/src/inputfifo.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/inputfifo/src/inputfifo.c new file mode 100644 index 0000000000000000000000000000000000000000..cf02970d4f59c38a1ca6afc048a65b198078d437 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/inputfifo/src/inputfifo.c @@ -0,0 +1,613 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#include "platform_support.h" + +#include "ia_css_inputfifo.h" + +#include "device_access.h" + +#define __INLINE_SP__ +#include "sp.h" +#define __INLINE_ISP__ +#include "isp.h" +#define __INLINE_IRQ__ +#include "irq.h" +#define __INLINE_FIFO_MONITOR__ +#include "fifo_monitor.h" + +#define __INLINE_EVENT__ +#include "event_fifo.h" +#define __INLINE_SP__ + +#if !defined(HAS_NO_INPUT_SYSTEM) +#include "input_system.h" /* MIPI_PREDICTOR_NONE,... */ +#endif + +#include "assert_support.h" + +/* System independent */ +#include "sh_css_internal.h" +#if !defined(HAS_NO_INPUT_SYSTEM) +#include "ia_css_isys.h" +#endif + +#define HBLANK_CYCLES (187) +#define MARKER_CYCLES (6) + +#if !defined(HAS_NO_INPUT_SYSTEM) +#include +#endif + +/* The data type is used to send special cases: + * yuv420: odd lines (1, 3 etc) are twice as wide as even + * lines (0, 2, 4 etc). + * rgb: for two pixels per clock, the R and B values are sent + * to output_0 while only G is sent to output_1. This means + * that output_1 only gets half the number of values of output_0. + * WARNING: This type should also be used for Legacy YUV420. + * regular: used for all other data types (RAW, YUV422, etc) + */ +enum inputfifo_mipi_data_type { + inputfifo_mipi_data_type_regular, + inputfifo_mipi_data_type_yuv420, + inputfifo_mipi_data_type_yuv420_legacy, + inputfifo_mipi_data_type_rgb, +}; +#if !defined(HAS_NO_INPUT_SYSTEM) +static unsigned int inputfifo_curr_ch_id, inputfifo_curr_fmt_type; +#endif +struct inputfifo_instance { + unsigned int ch_id; + enum ia_css_stream_format input_format; + bool two_ppc; + bool streaming; + unsigned int hblank_cycles; + unsigned int marker_cycles; + unsigned int fmt_type; + enum inputfifo_mipi_data_type type; +}; +#if !defined(HAS_NO_INPUT_SYSTEM) +/* + * Maintain a basic streaming to Mipi administration with ch_id as index + * ch_id maps on the "Mipi virtual channel ID" and can have value 0..3 + */ +#define INPUTFIFO_NR_OF_S2M_CHANNELS (4) +static struct inputfifo_instance + inputfifo_inst_admin[INPUTFIFO_NR_OF_S2M_CHANNELS]; + +/* Streaming to MIPI */ +static unsigned inputfifo_wrap_marker( +/* STORAGE_CLASS_INLINE unsigned inputfifo_wrap_marker( */ + unsigned marker) +{ + return marker | + (inputfifo_curr_ch_id << HIVE_STR_TO_MIPI_CH_ID_LSB) | + (inputfifo_curr_fmt_type << _HIVE_STR_TO_MIPI_FMT_TYPE_LSB); +} + +STORAGE_CLASS_INLINE void +_sh_css_fifo_snd(unsigned token) +{ + while (!can_event_send_token(STR2MIPI_EVENT_ID)) + hrt_sleep(); + event_send_token(STR2MIPI_EVENT_ID, token); + return; +} + +static void inputfifo_send_data_a( +/* STORAGE_CLASS_INLINE void inputfifo_send_data_a( */ +unsigned int data) +{ + unsigned int token = (1 << HIVE_STR_TO_MIPI_VALID_A_BIT) | + (data << HIVE_STR_TO_MIPI_DATA_A_LSB); + _sh_css_fifo_snd(token); + return; +} + + + +static void inputfifo_send_data_b( +/* STORAGE_CLASS_INLINE void inputfifo_send_data_b( */ + unsigned int data) +{ + unsigned int token = (1 << HIVE_STR_TO_MIPI_VALID_B_BIT) | + (data << _HIVE_STR_TO_MIPI_DATA_B_LSB); + _sh_css_fifo_snd(token); + return; +} + + + +static void inputfifo_send_data( +/* STORAGE_CLASS_INLINE void inputfifo_send_data( */ + unsigned int a, + unsigned int b) +{ + unsigned int token = ((1 << HIVE_STR_TO_MIPI_VALID_A_BIT) | + (1 << HIVE_STR_TO_MIPI_VALID_B_BIT) | + (a << HIVE_STR_TO_MIPI_DATA_A_LSB) | + (b << _HIVE_STR_TO_MIPI_DATA_B_LSB)); + _sh_css_fifo_snd(token); + return; +} + + + +static void inputfifo_send_sol(void) +/* STORAGE_CLASS_INLINE void inputfifo_send_sol(void) */ +{ + hrt_data token = inputfifo_wrap_marker( + 1 << HIVE_STR_TO_MIPI_SOL_BIT); + + _sh_css_fifo_snd(token); + return; +} + + + +static void inputfifo_send_eol(void) +/* STORAGE_CLASS_INLINE void inputfifo_send_eol(void) */ +{ + hrt_data token = inputfifo_wrap_marker( + 1 << HIVE_STR_TO_MIPI_EOL_BIT); + _sh_css_fifo_snd(token); + return; +} + + + +static void inputfifo_send_sof(void) +/* STORAGE_CLASS_INLINE void inputfifo_send_sof(void) */ +{ + hrt_data token = inputfifo_wrap_marker( + 1 << HIVE_STR_TO_MIPI_SOF_BIT); + + _sh_css_fifo_snd(token); + return; +} + + + +static void inputfifo_send_eof(void) +/* STORAGE_CLASS_INLINE void inputfifo_send_eof(void) */ +{ + hrt_data token = inputfifo_wrap_marker( + 1 << HIVE_STR_TO_MIPI_EOF_BIT); + _sh_css_fifo_snd(token); + return; +} + + + +#ifdef __ON__ +static void inputfifo_send_ch_id( +/* STORAGE_CLASS_INLINE void inputfifo_send_ch_id( */ + unsigned int ch_id) +{ + hrt_data token; + inputfifo_curr_ch_id = ch_id & _HIVE_ISP_CH_ID_MASK; + /* we send an zero marker, this will wrap the ch_id and + * fmt_type automatically. + */ + token = inputfifo_wrap_marker(0); + _sh_css_fifo_snd(token); + return; +} + +static void inputfifo_send_fmt_type( +/* STORAGE_CLASS_INLINE void inputfifo_send_fmt_type( */ + unsigned int fmt_type) +{ + hrt_data token; + inputfifo_curr_fmt_type = fmt_type & _HIVE_ISP_FMT_TYPE_MASK; + /* we send an zero marker, this will wrap the ch_id and + * fmt_type automatically. + */ + token = inputfifo_wrap_marker(0); + _sh_css_fifo_snd(token); + return; +} +#endif /* __ON__ */ + + + +static void inputfifo_send_ch_id_and_fmt_type( +/* STORAGE_CLASS_INLINE +void inputfifo_send_ch_id_and_fmt_type( */ + unsigned int ch_id, + unsigned int fmt_type) +{ + hrt_data token; + inputfifo_curr_ch_id = ch_id & _HIVE_ISP_CH_ID_MASK; + inputfifo_curr_fmt_type = fmt_type & _HIVE_ISP_FMT_TYPE_MASK; + /* we send an zero marker, this will wrap the ch_id and + * fmt_type automatically. + */ + token = inputfifo_wrap_marker(0); + _sh_css_fifo_snd(token); + return; +} + + + +static void inputfifo_send_empty_token(void) +/* STORAGE_CLASS_INLINE void inputfifo_send_empty_token(void) */ +{ + hrt_data token = inputfifo_wrap_marker(0); + _sh_css_fifo_snd(token); + return; +} + + + +static void inputfifo_start_frame( +/* STORAGE_CLASS_INLINE void inputfifo_start_frame( */ + unsigned int ch_id, + unsigned int fmt_type) +{ + inputfifo_send_ch_id_and_fmt_type(ch_id, fmt_type); + inputfifo_send_sof(); + return; +} + + + +static void inputfifo_end_frame( + unsigned int marker_cycles) +{ + unsigned int i; + for (i = 0; i < marker_cycles; i++) + inputfifo_send_empty_token(); + inputfifo_send_eof(); + return; +} + + + +static void inputfifo_send_line2( + const unsigned short *data, + unsigned int width, + const unsigned short *data2, + unsigned int width2, + unsigned int hblank_cycles, + unsigned int marker_cycles, + unsigned int two_ppc, + enum inputfifo_mipi_data_type type) +{ + unsigned int i, is_rgb = 0, is_legacy = 0; + + assert(data != NULL); + assert((data2 != NULL) || (width2 == 0)); + if (type == inputfifo_mipi_data_type_rgb) + is_rgb = 1; + + if (type == inputfifo_mipi_data_type_yuv420_legacy) + is_legacy = 1; + + for (i = 0; i < hblank_cycles; i++) + inputfifo_send_empty_token(); + inputfifo_send_sol(); + for (i = 0; i < marker_cycles; i++) + inputfifo_send_empty_token(); + for (i = 0; i < width; i++, data++) { + /* for RGB in two_ppc, we only actually send 2 pixels per + * clock in the even pixels (0, 2 etc). In the other cycles, + * we only send 1 pixel, to data[0]. + */ + unsigned int send_two_pixels = two_ppc; + if ((is_rgb || is_legacy) && (i % 3 == 2)) + send_two_pixels = 0; + if (send_two_pixels) { + if (i + 1 == width) { + /* for jpg (binary) copy, this can occur + * if the file contains an odd number of bytes. + */ + inputfifo_send_data( + data[0], 0); + } else { + inputfifo_send_data( + data[0], data[1]); + } + /* Additional increment because we send 2 pixels */ + data++; + i++; + } else if (two_ppc && is_legacy) { + inputfifo_send_data_b(data[0]); + } else { + inputfifo_send_data_a(data[0]); + } + } + + for (i = 0; i < width2; i++, data2++) { + /* for RGB in two_ppc, we only actually send 2 pixels per + * clock in the even pixels (0, 2 etc). In the other cycles, + * we only send 1 pixel, to data2[0]. + */ + unsigned int send_two_pixels = two_ppc; + if ((is_rgb || is_legacy) && (i % 3 == 2)) + send_two_pixels = 0; + if (send_two_pixels) { + if (i + 1 == width2) { + /* for jpg (binary) copy, this can occur + * if the file contains an odd number of bytes. + */ + inputfifo_send_data( + data2[0], 0); + } else { + inputfifo_send_data( + data2[0], data2[1]); + } + /* Additional increment because we send 2 pixels */ + data2++; + i++; + } else if (two_ppc && is_legacy) { + inputfifo_send_data_b(data2[0]); + } else { + inputfifo_send_data_a(data2[0]); + } + } + for (i = 0; i < hblank_cycles; i++) + inputfifo_send_empty_token(); + inputfifo_send_eol(); + return; +} + + + +static void +inputfifo_send_line(const unsigned short *data, + unsigned int width, + unsigned int hblank_cycles, + unsigned int marker_cycles, + unsigned int two_ppc, + enum inputfifo_mipi_data_type type) +{ + assert(data != NULL); + inputfifo_send_line2(data, width, NULL, 0, + hblank_cycles, + marker_cycles, + two_ppc, + type); +} + + +/* Send a frame of data into the input network via the GP FIFO. + * Parameters: + * - data: array of 16 bit values that contains all data for the frame. + * - width: width of a line in number of subpixels, for yuv420 it is the + * number of Y components per line. + * - height: height of the frame in number of lines. + * - ch_id: channel ID. + * - fmt_type: format type. + * - hblank_cycles: length of horizontal blanking in cycles. + * - marker_cycles: number of empty cycles after start-of-line and before + * end-of-frame. + * - two_ppc: boolean, describes whether to send one or two pixels per clock + * cycle. In this mode, we sent pixels N and N+1 in the same cycle, + * to IF_PRIM_A and IF_PRIM_B respectively. The caller must make + * sure the input data has been formatted correctly for this. + * For example, for RGB formats this means that unused values + * must be inserted. + * - yuv420: boolean, describes whether (non-legacy) yuv420 data is used. In + * this mode, the odd lines (1,3,5 etc) are half as long as the + * even lines (2,4,6 etc). + * Note that the first line is odd (1) and the second line is even + * (2). + * + * This function does not do any reordering of pixels, the caller must make + * sure the data is in the righ format. Please refer to the CSS receiver + * documentation for details on the data formats. + */ + +static void inputfifo_send_frame( + const unsigned short *data, + unsigned int width, + unsigned int height, + unsigned int ch_id, + unsigned int fmt_type, + unsigned int hblank_cycles, + unsigned int marker_cycles, + unsigned int two_ppc, + enum inputfifo_mipi_data_type type) +{ + unsigned int i; + + assert(data != NULL); + inputfifo_start_frame(ch_id, fmt_type); + + for (i = 0; i < height; i++) { + if ((type == inputfifo_mipi_data_type_yuv420) && + (i & 1) == 1) { + inputfifo_send_line(data, 2 * width, + hblank_cycles, + marker_cycles, + two_ppc, type); + data += 2 * width; + } else { + inputfifo_send_line(data, width, + hblank_cycles, + marker_cycles, + two_ppc, type); + data += width; + } + } + inputfifo_end_frame(marker_cycles); + return; +} + + + +static enum inputfifo_mipi_data_type inputfifo_determine_type( + enum ia_css_stream_format input_format) +{ + enum inputfifo_mipi_data_type type; + + type = inputfifo_mipi_data_type_regular; + if (input_format == IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY) { + type = + inputfifo_mipi_data_type_yuv420_legacy; + } else if (input_format == IA_CSS_STREAM_FORMAT_YUV420_8 || + input_format == IA_CSS_STREAM_FORMAT_YUV420_10 || + input_format == IA_CSS_STREAM_FORMAT_YUV420_16) { + type = + inputfifo_mipi_data_type_yuv420; + } else if (input_format >= IA_CSS_STREAM_FORMAT_RGB_444 && + input_format <= IA_CSS_STREAM_FORMAT_RGB_888) { + type = + inputfifo_mipi_data_type_rgb; + } + return type; +} + + + +static struct inputfifo_instance *inputfifo_get_inst( + unsigned int ch_id) +{ + return &inputfifo_inst_admin[ch_id]; +} + +void ia_css_inputfifo_send_input_frame( + const unsigned short *data, + unsigned int width, + unsigned int height, + unsigned int ch_id, + enum ia_css_stream_format input_format, + bool two_ppc) +{ + unsigned int fmt_type, hblank_cycles, marker_cycles; + enum inputfifo_mipi_data_type type; + + assert(data != NULL); + hblank_cycles = HBLANK_CYCLES; + marker_cycles = MARKER_CYCLES; + ia_css_isys_convert_stream_format_to_mipi_format(input_format, + MIPI_PREDICTOR_NONE, + &fmt_type); + + type = inputfifo_determine_type(input_format); + + inputfifo_send_frame(data, width, height, + ch_id, fmt_type, hblank_cycles, marker_cycles, + two_ppc, type); +} + + + +void ia_css_inputfifo_start_frame( + unsigned int ch_id, + enum ia_css_stream_format input_format, + bool two_ppc) +{ + struct inputfifo_instance *s2mi; + s2mi = inputfifo_get_inst(ch_id); + + s2mi->ch_id = ch_id; + ia_css_isys_convert_stream_format_to_mipi_format(input_format, + MIPI_PREDICTOR_NONE, + &s2mi->fmt_type); + s2mi->two_ppc = two_ppc; + s2mi->type = inputfifo_determine_type(input_format); + s2mi->hblank_cycles = HBLANK_CYCLES; + s2mi->marker_cycles = MARKER_CYCLES; + s2mi->streaming = true; + + inputfifo_start_frame(ch_id, s2mi->fmt_type); + return; +} + + + +void ia_css_inputfifo_send_line( + unsigned int ch_id, + const unsigned short *data, + unsigned int width, + const unsigned short *data2, + unsigned int width2) +{ + struct inputfifo_instance *s2mi; + + assert(data != NULL); + assert((data2 != NULL) || (width2 == 0)); + s2mi = inputfifo_get_inst(ch_id); + + + /* Set global variables that indicate channel_id and format_type */ + inputfifo_curr_ch_id = (s2mi->ch_id) & _HIVE_ISP_CH_ID_MASK; + inputfifo_curr_fmt_type = (s2mi->fmt_type) & _HIVE_ISP_FMT_TYPE_MASK; + + inputfifo_send_line2(data, width, data2, width2, + s2mi->hblank_cycles, + s2mi->marker_cycles, + s2mi->two_ppc, + s2mi->type); +} + + +void ia_css_inputfifo_send_embedded_line( + unsigned int ch_id, + enum ia_css_stream_format data_type, + const unsigned short *data, + unsigned int width) +{ + struct inputfifo_instance *s2mi; + unsigned int fmt_type; + + assert(data != NULL); + s2mi = inputfifo_get_inst(ch_id); + ia_css_isys_convert_stream_format_to_mipi_format(data_type, + MIPI_PREDICTOR_NONE, &fmt_type); + + /* Set format_type for metadata line. */ + inputfifo_curr_fmt_type = fmt_type & _HIVE_ISP_FMT_TYPE_MASK; + + inputfifo_send_line(data, width, s2mi->hblank_cycles, s2mi->marker_cycles, + s2mi->two_ppc, inputfifo_mipi_data_type_regular); +} + + +void ia_css_inputfifo_end_frame( + unsigned int ch_id) +{ + struct inputfifo_instance *s2mi; + s2mi = inputfifo_get_inst(ch_id); + + /* Set global variables that indicate channel_id and format_type */ + inputfifo_curr_ch_id = (s2mi->ch_id) & _HIVE_ISP_CH_ID_MASK; + inputfifo_curr_fmt_type = (s2mi->fmt_type) & _HIVE_ISP_FMT_TYPE_MASK; + + /* Call existing HRT function */ + inputfifo_end_frame(s2mi->marker_cycles); + + s2mi->streaming = false; + return; +} +#endif /* #if !defined(HAS_NO_INPUT_SYSTEM) */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isp_param/interface/ia_css_isp_param.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isp_param/interface/ia_css_isp_param.h new file mode 100644 index 0000000000000000000000000000000000000000..285749885105ccf6ce09bacc2b40cd1ff18b44d1 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isp_param/interface/ia_css_isp_param.h @@ -0,0 +1,118 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef _IA_CSS_ISP_PARAM_H_ +#define _IA_CSS_ISP_PARAM_H_ + +#include +#include "ia_css_isp_param_types.h" + +/* Set functions for parameter memory descriptors */ +void +ia_css_isp_param_set_mem_init( + struct ia_css_isp_param_host_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem, + char *address, size_t size); + +void +ia_css_isp_param_set_css_mem_init( + struct ia_css_isp_param_css_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem, + hrt_vaddress address, size_t size); + +void +ia_css_isp_param_set_isp_mem_init( + struct ia_css_isp_param_isp_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem, + uint32_t address, size_t size); + +/* Get functions for parameter memory descriptors */ +const struct ia_css_host_data* +ia_css_isp_param_get_mem_init( + const struct ia_css_isp_param_host_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem); + +const struct ia_css_data* +ia_css_isp_param_get_css_mem_init( + const struct ia_css_isp_param_css_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem); + +const struct ia_css_isp_data* +ia_css_isp_param_get_isp_mem_init( + const struct ia_css_isp_param_isp_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem); + +/* Initialize the memory interface sizes and addresses */ +void +ia_css_init_memory_interface( + struct ia_css_isp_param_css_segments *isp_mem_if, + const struct ia_css_isp_param_host_segments *mem_params, + const struct ia_css_isp_param_css_segments *css_params); + +/* Allocate memory parameters */ +enum ia_css_err +ia_css_isp_param_allocate_isp_parameters( + struct ia_css_isp_param_host_segments *mem_params, + struct ia_css_isp_param_css_segments *css_params, + const struct ia_css_isp_param_isp_segments *mem_initializers); + +/* Destroy memory parameters */ +void +ia_css_isp_param_destroy_isp_parameters( + struct ia_css_isp_param_host_segments *mem_params, + struct ia_css_isp_param_css_segments *css_params); + +/* Load fw parameters */ +void +ia_css_isp_param_load_fw_params( + const char *fw, + union ia_css_all_memory_offsets *mem_offsets, + const struct ia_css_isp_param_memory_offsets *memory_offsets, + bool init); + +/* Copy host parameter images to ddr */ +enum ia_css_err +ia_css_isp_param_copy_isp_mem_if_to_ddr( + struct ia_css_isp_param_css_segments *ddr, + const struct ia_css_isp_param_host_segments *host, + enum ia_css_param_class pclass); + +/* Enable a pipeline by setting the control field in the isp dmem parameters */ +void +ia_css_isp_param_enable_pipeline( + const struct ia_css_isp_param_host_segments *mem_params); + +#endif /* _IA_CSS_ISP_PARAM_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isp_param/interface/ia_css_isp_param_types.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isp_param/interface/ia_css_isp_param_types.h new file mode 100644 index 0000000000000000000000000000000000000000..8e651b80345a0ea47862c78fdfa3ef1359d75bf3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isp_param/interface/ia_css_isp_param_types.h @@ -0,0 +1,107 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef _IA_CSS_ISP_PARAM_TYPES_H_ +#define _IA_CSS_ISP_PARAM_TYPES_H_ + +#include "ia_css_types.h" +#include +#include + +/* Short hands */ +#define IA_CSS_ISP_DMEM IA_CSS_ISP_DMEM0 +#define IA_CSS_ISP_VMEM IA_CSS_ISP_VMEM0 + +/* The driver depends on this, to be removed later. */ +#define IA_CSS_NUM_ISP_MEMORIES IA_CSS_NUM_MEMORIES + +/* Explicit member numbering to avoid fish type checker bug */ +enum ia_css_param_class { + IA_CSS_PARAM_CLASS_PARAM = 0, /* Late binding parameters, like 3A */ + IA_CSS_PARAM_CLASS_CONFIG = 1, /* Pipe config time parameters, like resolution */ + IA_CSS_PARAM_CLASS_STATE = 2, /* State parameters, like tnr buffer index */ +#if 0 /* Not yet implemented */ + IA_CSS_PARAM_CLASS_FRAME = 3, /* Frame time parameters, like output buffer */ +#endif +}; +#define IA_CSS_NUM_PARAM_CLASSES (IA_CSS_PARAM_CLASS_STATE + 1) + +/** ISP parameter descriptor */ +struct ia_css_isp_parameter { + uint32_t offset; /* Offset in isp_)parameters, etc. */ + uint32_t size; /* Disabled if 0 */ +}; + + +/* Address/size of each parameter class in each isp memory, host memory pointers */ +struct ia_css_isp_param_host_segments { + struct ia_css_host_data params[IA_CSS_NUM_PARAM_CLASSES][IA_CSS_NUM_MEMORIES]; +}; + +/* Address/size of each parameter class in each isp memory, css memory pointers */ +struct ia_css_isp_param_css_segments { + struct ia_css_data params[IA_CSS_NUM_PARAM_CLASSES][IA_CSS_NUM_MEMORIES]; +}; + +/* Address/size of each parameter class in each isp memory, isp memory pointers */ +struct ia_css_isp_param_isp_segments { + struct ia_css_isp_data params[IA_CSS_NUM_PARAM_CLASSES][IA_CSS_NUM_MEMORIES]; +}; + +/* Memory offsets in binary info */ +struct ia_css_isp_param_memory_offsets { + uint32_t offsets[IA_CSS_NUM_PARAM_CLASSES]; /**< offset wrt hdr in bytes */ +}; + +/** Offsets for ISP kernel parameters per isp memory. + * Only relevant for standard ISP binaries, not ACC or SP. + */ +union ia_css_all_memory_offsets { + struct { + CSS_ALIGN(struct ia_css_memory_offsets *param, 8); + CSS_ALIGN(struct ia_css_config_memory_offsets *config, 8); + CSS_ALIGN(struct ia_css_state_memory_offsets *state, 8); + } offsets; + struct { + CSS_ALIGN(void *ptr, 8); + } array[IA_CSS_NUM_PARAM_CLASSES]; +}; + +#define IA_CSS_DEFAULT_ISP_MEM_PARAMS \ + { { { { 0, 0 } } } } + +#define IA_CSS_DEFAULT_ISP_CSS_PARAMS \ + { { { { 0, 0 } } } } + +#define IA_CSS_DEFAULT_ISP_ISP_PARAMS \ + { { { { 0, 0 } } } } + +#endif /* _IA_CSS_ISP_PARAM_TYPES_H_ */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isp_param/src/isp_param.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isp_param/src/isp_param.c new file mode 100644 index 0000000000000000000000000000000000000000..6f2935a4b43e7caac07e2d52ee8951edb2ce6139 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isp_param/src/isp_param.c @@ -0,0 +1,227 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#include "memory_access.h" +#include "ia_css_pipeline.h" +#include "ia_css_isp_param.h" + +/* Set functions for parameter memory descriptors */ + +void +ia_css_isp_param_set_mem_init( + struct ia_css_isp_param_host_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem, + char *address, size_t size) +{ + mem_init->params[pclass][mem].address = address; + mem_init->params[pclass][mem].size = (uint32_t)size; +} + +void +ia_css_isp_param_set_css_mem_init( + struct ia_css_isp_param_css_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem, + hrt_vaddress address, size_t size) +{ + mem_init->params[pclass][mem].address = address; + mem_init->params[pclass][mem].size = (uint32_t)size; +} + +void +ia_css_isp_param_set_isp_mem_init( + struct ia_css_isp_param_isp_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem, + uint32_t address, size_t size) +{ + mem_init->params[pclass][mem].address = address; + mem_init->params[pclass][mem].size = (uint32_t)size; +} + +/* Get functions for parameter memory descriptors */ +const struct ia_css_host_data* +ia_css_isp_param_get_mem_init( + const struct ia_css_isp_param_host_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem) +{ + return &mem_init->params[pclass][mem]; +} + +const struct ia_css_data* +ia_css_isp_param_get_css_mem_init( + const struct ia_css_isp_param_css_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem) +{ + return &mem_init->params[pclass][mem]; +} + +const struct ia_css_isp_data* +ia_css_isp_param_get_isp_mem_init( + const struct ia_css_isp_param_isp_segments *mem_init, + enum ia_css_param_class pclass, + enum ia_css_isp_memories mem) +{ + return &mem_init->params[pclass][mem]; +} + +void +ia_css_init_memory_interface( + struct ia_css_isp_param_css_segments *isp_mem_if, + const struct ia_css_isp_param_host_segments *mem_params, + const struct ia_css_isp_param_css_segments *css_params) +{ + unsigned pclass, mem; + for (pclass = 0; pclass < IA_CSS_NUM_PARAM_CLASSES; pclass++) { + memset(isp_mem_if->params[pclass], 0, sizeof(isp_mem_if->params[pclass])); + for (mem = 0; mem < IA_CSS_NUM_MEMORIES; mem++) { + if (!mem_params->params[pclass][mem].address) + continue; + isp_mem_if->params[pclass][mem].size = mem_params->params[pclass][mem].size; + if (pclass != IA_CSS_PARAM_CLASS_PARAM) + isp_mem_if->params[pclass][mem].address = css_params->params[pclass][mem].address; + } + } +} + +enum ia_css_err +ia_css_isp_param_allocate_isp_parameters( + struct ia_css_isp_param_host_segments *mem_params, + struct ia_css_isp_param_css_segments *css_params, + const struct ia_css_isp_param_isp_segments *mem_initializers) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + unsigned mem, pclass; + + pclass = IA_CSS_PARAM_CLASS_PARAM; + for (mem = 0; mem < IA_CSS_NUM_MEMORIES; mem++) { + for (pclass = 0; pclass < IA_CSS_NUM_PARAM_CLASSES; pclass++) { + uint32_t size = 0; + if (mem_initializers) + size = mem_initializers->params[pclass][mem].size; + mem_params->params[pclass][mem].size = size; + mem_params->params[pclass][mem].address = NULL; + css_params->params[pclass][mem].size = size; + css_params->params[pclass][mem].address = 0x0; + if (size) { + mem_params->params[pclass][mem].address = sh_css_calloc(1, size); + if (!mem_params->params[pclass][mem].address) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + goto cleanup; + } + if (pclass != IA_CSS_PARAM_CLASS_PARAM) { + css_params->params[pclass][mem].address = mmgr_malloc(size); + if (!css_params->params[pclass][mem].address) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + goto cleanup; + } + } + } + } + } + return err; +cleanup: + ia_css_isp_param_destroy_isp_parameters(mem_params, css_params); + return err; +} + +void +ia_css_isp_param_destroy_isp_parameters( + struct ia_css_isp_param_host_segments *mem_params, + struct ia_css_isp_param_css_segments *css_params) +{ + unsigned mem, pclass; + + for (mem = 0; mem < IA_CSS_NUM_MEMORIES; mem++) { + for (pclass = 0; pclass < IA_CSS_NUM_PARAM_CLASSES; pclass++) { + if (mem_params->params[pclass][mem].address) + sh_css_free(mem_params->params[pclass][mem].address); + if (css_params->params[pclass][mem].address) + mmgr_free(css_params->params[pclass][mem].address); + mem_params->params[pclass][mem].address = NULL; + css_params->params[pclass][mem].address = 0x0; + } + } +} + +void +ia_css_isp_param_load_fw_params( + const char *fw, + union ia_css_all_memory_offsets *mem_offsets, + const struct ia_css_isp_param_memory_offsets *memory_offsets, + bool init) +{ + unsigned pclass; + for (pclass = 0; pclass < IA_CSS_NUM_PARAM_CLASSES; pclass++) { + mem_offsets->array[pclass].ptr = NULL; + if (init) + mem_offsets->array[pclass].ptr = (void *)(fw + memory_offsets->offsets[pclass]); + } +} + +enum ia_css_err +ia_css_isp_param_copy_isp_mem_if_to_ddr( + struct ia_css_isp_param_css_segments *ddr, + const struct ia_css_isp_param_host_segments *host, + enum ia_css_param_class pclass) +{ + unsigned mem; + + for (mem = 0; mem < N_IA_CSS_ISP_MEMORIES; mem++) { + size_t size = host->params[pclass][mem].size; + hrt_vaddress ddr_mem_ptr = ddr->params[pclass][mem].address; + char *host_mem_ptr = host->params[pclass][mem].address; + if (size != ddr->params[pclass][mem].size) + return IA_CSS_ERR_INTERNAL_ERROR; + if (!size) + continue; + mmgr_store(ddr_mem_ptr, host_mem_ptr, size); + } + return IA_CSS_SUCCESS; +} + +void +ia_css_isp_param_enable_pipeline( + const struct ia_css_isp_param_host_segments *mem_params) +{ + /* By protocol b0 of the mandatory uint32_t first field of the + input parameter is a disable bit*/ + short dmem_offset = 0; + + if (mem_params->params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM0].size == 0) + return; + + *(uint32_t *)&mem_params->params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM0].address[dmem_offset] = 0x0; +} + + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/interface/ia_css_isys.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/interface/ia_css_isys.h new file mode 100644 index 0000000000000000000000000000000000000000..02bf908d94e6c0a25f458ee909ab4fda454f6e71 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/interface/ia_css_isys.h @@ -0,0 +1,201 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef __IA_CSS_ISYS_H__ +#define __IA_CSS_ISYS_H__ + +#include +#include +#include +#include +#include +#include +#include "ia_css_isys_comm.h" + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 +/** + * Virtual Input System. (Input System 2401) + */ +typedef input_system_cfg_t ia_css_isys_descr_t; +/** end of Virtual Input System */ +#endif + +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) +input_system_error_t ia_css_isys_init(void); +void ia_css_isys_uninit(void); +mipi_port_ID_t ia_css_isys_port_to_mipi_port( + enum ia_css_csi2_port api_port); +#endif + +#if defined(USE_INPUT_SYSTEM_VERSION_2401) + +/** + * @brief Register one (virtual) stream. This is used to track when all + * virtual streams are configured inside the input system. The CSI RX is + * only started when all registered streams are configured. + * + * @param[in] port CSI port + * @param[in] isys_stream_id Stream handle generated with ia_css_isys_generate_stream_id() + * Must be lower than SH_CSS_MAX_ISYS_CHANNEL_NODES + * @return IA_CSS_SUCCESS if successful, IA_CSS_ERR_INTERNAL_ERROR if + * there is already a stream registered with the same handle + */ +enum ia_css_err ia_css_isys_csi_rx_register_stream( + enum ia_css_csi2_port port, + uint32_t isys_stream_id); + +/** + * @brief Unregister one (virtual) stream. This is used to track when all + * virtual streams are configured inside the input system. The CSI RX is + * only started when all registered streams are configured. + * + * @param[in] port CSI port + * @param[in] isys_stream_id Stream handle generated with ia_css_isys_generate_stream_id() + * Must be lower than SH_CSS_MAX_ISYS_CHANNEL_NODES + * @return IA_CSS_SUCCESS if successful, IA_CSS_ERR_INTERNAL_ERROR if + * there is no stream registered with that handle + */ +enum ia_css_err ia_css_isys_csi_rx_unregister_stream( + enum ia_css_csi2_port port, + uint32_t isys_stream_id); + +enum ia_css_err ia_css_isys_convert_compressed_format( + struct ia_css_csi2_compression *comp, + struct input_system_cfg_s *cfg); +unsigned int ia_css_csi2_calculate_input_system_alignment( + enum ia_css_stream_format fmt_type); +#endif + +#if !defined(USE_INPUT_SYSTEM_VERSION_2401) +/* CSS Receiver */ +void ia_css_isys_rx_configure( + const rx_cfg_t *config, + const enum ia_css_input_mode input_mode); + +void ia_css_isys_rx_disable(void); + +void ia_css_isys_rx_enable_all_interrupts(mipi_port_ID_t port); + +unsigned int ia_css_isys_rx_get_interrupt_reg(mipi_port_ID_t port); +void ia_css_isys_rx_get_irq_info(mipi_port_ID_t port, + unsigned int *irq_infos); +void ia_css_isys_rx_clear_irq_info(mipi_port_ID_t port, + unsigned int irq_infos); +unsigned int ia_css_isys_rx_translate_irq_infos(unsigned int bits); + +#endif /* #if !defined(USE_INPUT_SYSTEM_VERSION_2401) */ + +/** @brief Translate format and compression to format type. + * + * @param[in] input_format The input format. + * @param[in] compression The compression scheme. + * @param[out] fmt_type Pointer to the resulting format type. + * @return Error code. + * + * Translate an input format and mipi compression pair to the fmt_type. + * This is normally done by the sensor, but when using the input fifo, this + * format type must be sumitted correctly by the application. + */ +enum ia_css_err ia_css_isys_convert_stream_format_to_mipi_format( + enum ia_css_stream_format input_format, + mipi_predictor_t compression, + unsigned int *fmt_type); + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 +/** + * Virtual Input System. (Input System 2401) + */ +extern ia_css_isys_error_t ia_css_isys_stream_create( + ia_css_isys_descr_t *isys_stream_descr, + ia_css_isys_stream_h isys_stream, + uint32_t isys_stream_id); + +extern void ia_css_isys_stream_destroy( + ia_css_isys_stream_h isys_stream); + +extern ia_css_isys_error_t ia_css_isys_stream_calculate_cfg( + ia_css_isys_stream_h isys_stream, + ia_css_isys_descr_t *isys_stream_descr, + ia_css_isys_stream_cfg_t *isys_stream_cfg); + +extern void ia_css_isys_csi_rx_lut_rmgr_init(void); + +extern void ia_css_isys_csi_rx_lut_rmgr_uninit(void); + +extern bool ia_css_isys_csi_rx_lut_rmgr_acquire( + csi_rx_backend_ID_t backend, + csi_mipi_packet_type_t packet_type, + csi_rx_backend_lut_entry_t *entry); + +extern void ia_css_isys_csi_rx_lut_rmgr_release( + csi_rx_backend_ID_t backend, + csi_mipi_packet_type_t packet_type, + csi_rx_backend_lut_entry_t *entry); + + +extern void ia_css_isys_ibuf_rmgr_init(void); + +extern void ia_css_isys_ibuf_rmgr_uninit(void); + +extern bool ia_css_isys_ibuf_rmgr_acquire( + uint32_t size, + uint32_t *start_addr); + +extern void ia_css_isys_ibuf_rmgr_release( + uint32_t *start_addr); + +extern void ia_css_isys_dma_channel_rmgr_init(void); + +extern void ia_css_isys_dma_channel_rmgr_uninit(void); + +extern bool ia_css_isys_dma_channel_rmgr_acquire( + isys2401_dma_ID_t dma_id, + isys2401_dma_channel *channel); + +extern void ia_css_isys_dma_channel_rmgr_release( + isys2401_dma_ID_t dma_id, + isys2401_dma_channel *channel); + +extern void ia_css_isys_stream2mmio_sid_rmgr_init(void); + +extern void ia_css_isys_stream2mmio_sid_rmgr_uninit(void); + +extern bool ia_css_isys_stream2mmio_sid_rmgr_acquire( + stream2mmio_ID_t stream2mmio, + stream2mmio_sid_ID_t *sid); + +extern void ia_css_isys_stream2mmio_sid_rmgr_release( + stream2mmio_ID_t stream2mmio, + stream2mmio_sid_ID_t *sid); + +/** end of Virtual Input System */ +#endif + +#endif /* __IA_CSS_ISYS_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/interface/ia_css_isys_comm.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/interface/ia_css_isys_comm.h new file mode 100644 index 0000000000000000000000000000000000000000..0c3434ad061392b993433c7b4151dc0df59b6032 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/interface/ia_css_isys_comm.h @@ -0,0 +1,69 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef __IA_CSS_ISYS_COMM_H +#define __IA_CSS_ISYS_COMM_H + +#include +#include + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 +#include /* inline */ +#include +#include /* IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH */ + +#define SH_CSS_NODES_PER_THREAD 2 +#define SH_CSS_MAX_ISYS_CHANNEL_NODES (SH_CSS_MAX_SP_THREADS * SH_CSS_NODES_PER_THREAD) + +/* + * a) ia_css_isys_stream_h & ia_css_isys_stream_cfg_t come from host. + * + * b) Here it is better to use actual structures for stream handle + * instead of opaque handles. Otherwise, we need to have another + * communication channel to interpret that opaque handle(this handle is + * maintained by host and needs to be populated to sp for every stream open) + * */ +typedef virtual_input_system_stream_t *ia_css_isys_stream_h; +typedef virtual_input_system_stream_cfg_t ia_css_isys_stream_cfg_t; + +/* + * error check for ISYS APIs. + * */ +typedef bool ia_css_isys_error_t; + +static inline uint32_t ia_css_isys_generate_stream_id( + uint32_t sp_thread_id, + uint32_t stream_id) +{ + return sp_thread_id * IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH + stream_id; +} + +#endif /* USE_INPUT_SYSTEM_VERSION_2401*/ +#endif /*_IA_CSS_ISYS_COMM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/csi_rx_rmgr.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/csi_rx_rmgr.c new file mode 100644 index 0000000000000000000000000000000000000000..d1d4f79c00f19c704dd795999c5ef6acde8d9125 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/csi_rx_rmgr.c @@ -0,0 +1,179 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#include "system_global.h" + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + +#include "assert_support.h" +#include "platform_support.h" +#include "ia_css_isys.h" +#include "bitop_support.h" +#include "ia_css_pipeline.h" /* ia_css_pipeline_get_pipe_io_status() */ +#include "sh_css_internal.h" /* sh_css_sp_pipeline_io_status + * SH_CSS_MAX_SP_THREADS + */ +#include "csi_rx_rmgr.h" + +static isys_csi_rx_rsrc_t isys_csi_rx_rsrc[N_CSI_RX_BACKEND_ID]; + +void ia_css_isys_csi_rx_lut_rmgr_init(void) +{ + memset(isys_csi_rx_rsrc, 0, sizeof(isys_csi_rx_rsrc)); +} + +void ia_css_isys_csi_rx_lut_rmgr_uninit(void) +{ + memset(isys_csi_rx_rsrc, 0, sizeof(isys_csi_rx_rsrc)); +} + +bool ia_css_isys_csi_rx_lut_rmgr_acquire( + csi_rx_backend_ID_t backend, + csi_mipi_packet_type_t packet_type, + csi_rx_backend_lut_entry_t *entry) +{ + bool retval = false; + uint32_t max_num_packets_of_type; + uint32_t num_active_of_type; + isys_csi_rx_rsrc_t *cur_rsrc = NULL; + uint16_t i; + + assert(backend < N_CSI_RX_BACKEND_ID); + assert((packet_type == CSI_MIPI_PACKET_TYPE_LONG) || (packet_type == CSI_MIPI_PACKET_TYPE_SHORT)); + assert(entry != NULL); + + if ((backend < N_CSI_RX_BACKEND_ID) && (entry != NULL)) { + cur_rsrc = &isys_csi_rx_rsrc[backend]; + if (packet_type == CSI_MIPI_PACKET_TYPE_LONG) { + max_num_packets_of_type = N_LONG_PACKET_LUT_ENTRIES[backend]; + num_active_of_type = cur_rsrc->num_long_packets; + } else { + max_num_packets_of_type = N_SHORT_PACKET_LUT_ENTRIES[backend]; + num_active_of_type = cur_rsrc->num_short_packets; + } + + if (num_active_of_type < max_num_packets_of_type) { + for (i = 0; i < max_num_packets_of_type; i++) { + if (bitop_getbit(cur_rsrc->active_table, i) == 0) { + bitop_setbit(cur_rsrc->active_table, i); + + if (packet_type == CSI_MIPI_PACKET_TYPE_LONG) { + entry->long_packet_entry = i; + entry->short_packet_entry = 0; + cur_rsrc->num_long_packets++; + } else { + entry->long_packet_entry = 0; + entry->short_packet_entry = i; + cur_rsrc->num_short_packets++; + } + cur_rsrc->num_active++; + retval = true; + break; + } + } + } + } + return retval; +} + +void ia_css_isys_csi_rx_lut_rmgr_release( + csi_rx_backend_ID_t backend, + csi_mipi_packet_type_t packet_type, + csi_rx_backend_lut_entry_t *entry) +{ + uint32_t max_num_packets; + isys_csi_rx_rsrc_t *cur_rsrc = NULL; + uint32_t packet_entry = 0; + + assert(backend < N_CSI_RX_BACKEND_ID); + assert(entry != NULL); + assert((packet_type >= CSI_MIPI_PACKET_TYPE_LONG) || (packet_type <= CSI_MIPI_PACKET_TYPE_SHORT)); + + if ((backend < N_CSI_RX_BACKEND_ID) && (entry != NULL)) { + if (packet_type == CSI_MIPI_PACKET_TYPE_LONG) { + max_num_packets = N_LONG_PACKET_LUT_ENTRIES[backend]; + packet_entry = entry->long_packet_entry; + } else { + max_num_packets = N_SHORT_PACKET_LUT_ENTRIES[backend]; + packet_entry = entry->short_packet_entry; + } + + cur_rsrc = &isys_csi_rx_rsrc[backend]; + if ((packet_entry < max_num_packets) && (cur_rsrc->num_active > 0)) { + if (bitop_getbit(cur_rsrc->active_table, packet_entry) == 1) { + bitop_clearbit(cur_rsrc->active_table, packet_entry); + + if (packet_type == CSI_MIPI_PACKET_TYPE_LONG) + cur_rsrc->num_long_packets--; + else + cur_rsrc->num_short_packets--; + cur_rsrc->num_active--; + } + } + } +} + +enum ia_css_err ia_css_isys_csi_rx_register_stream( + enum ia_css_csi2_port port, + uint32_t isys_stream_id) +{ + enum ia_css_err retval = IA_CSS_ERR_INTERNAL_ERROR; + + if ((port < N_INPUT_SYSTEM_CSI_PORT) && + (isys_stream_id < SH_CSS_MAX_ISYS_CHANNEL_NODES)) { + struct sh_css_sp_pipeline_io_status *pipe_io_status; + pipe_io_status = ia_css_pipeline_get_pipe_io_status(); + if (bitop_getbit(pipe_io_status->active[port], isys_stream_id) == 0) { + bitop_setbit(pipe_io_status->active[port], isys_stream_id); + pipe_io_status->running[port] = 0; + retval = IA_CSS_SUCCESS; + } + } + return retval; +} + +enum ia_css_err ia_css_isys_csi_rx_unregister_stream( + enum ia_css_csi2_port port, + uint32_t isys_stream_id) +{ + enum ia_css_err retval = IA_CSS_ERR_INTERNAL_ERROR; + + if ((port < N_INPUT_SYSTEM_CSI_PORT) && + (isys_stream_id < SH_CSS_MAX_ISYS_CHANNEL_NODES)) { + struct sh_css_sp_pipeline_io_status *pipe_io_status; + pipe_io_status = ia_css_pipeline_get_pipe_io_status(); + if (bitop_getbit(pipe_io_status->active[port], isys_stream_id) == 1) { + bitop_clearbit(pipe_io_status->active[port], isys_stream_id); + retval = IA_CSS_SUCCESS; + } + } + return retval; +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/csi_rx_rmgr.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/csi_rx_rmgr.h new file mode 100644 index 0000000000000000000000000000000000000000..c27b0ab83c93875f9bb060eb5d1831166b915f34 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/csi_rx_rmgr.h @@ -0,0 +1,43 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef __CSI_RX_RMGR_H_INCLUDED__ +#define __CSI_RX_RMGR_H_INCLUDED__ + +typedef struct isys_csi_rx_rsrc_s isys_csi_rx_rsrc_t; +struct isys_csi_rx_rsrc_s { + uint32_t active_table; + uint32_t num_active; + uint16_t num_long_packets; + uint16_t num_short_packets; +}; + +#endif /* __CSI_RX_RMGR_H_INCLUDED__ */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/ibuf_ctrl_rmgr.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/ibuf_ctrl_rmgr.c new file mode 100644 index 0000000000000000000000000000000000000000..76d9142fd37e5c9c5f264d524a5e0871fb7ee5e8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/ibuf_ctrl_rmgr.c @@ -0,0 +1,141 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#include "system_global.h" + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + +#include "assert_support.h" +#include "platform_support.h" +#include "ia_css_isys.h" +#include "ibuf_ctrl_rmgr.h" + +static ibuf_rsrc_t ibuf_rsrc; + +static ibuf_handle_t *getHandle(uint16_t index) +{ + ibuf_handle_t *handle = NULL; + + if (index < MAX_IBUF_HANDLES) + handle = &ibuf_rsrc.handles[index]; + return handle; +} + +void ia_css_isys_ibuf_rmgr_init(void) +{ + memset(&ibuf_rsrc, 0, sizeof(ibuf_rsrc)); + ibuf_rsrc.free_size = MAX_INPUT_BUFFER_SIZE; +} + +void ia_css_isys_ibuf_rmgr_uninit(void) +{ + memset(&ibuf_rsrc, 0, sizeof(ibuf_rsrc)); + ibuf_rsrc.free_size = MAX_INPUT_BUFFER_SIZE; +} + +bool ia_css_isys_ibuf_rmgr_acquire( + uint32_t size, + uint32_t *start_addr) +{ + bool retval = false; + bool input_buffer_found = false; + uint32_t aligned_size; + ibuf_handle_t *handle = NULL; + uint16_t i; + + assert(start_addr != NULL); + assert(size > 0); + + aligned_size = (size + (IBUF_ALIGN - 1)) & ~(IBUF_ALIGN - 1); + + /* Check if there is an available un-used handle with the size + * that will fulfill the request. + */ + if (ibuf_rsrc.num_active < ibuf_rsrc.num_allocated) { + for (i = 0; i < ibuf_rsrc.num_allocated; i++) { + handle = getHandle(i); + if (!handle->active) { + if (handle->size >= aligned_size) { + handle->active = true; + input_buffer_found = true; + ibuf_rsrc.num_active++; + break; + } + } + } + } + + if (!input_buffer_found) { + /* There were no available handles that fulfilled the + * request. Allocate a new handle with the requested size. + */ + if ((ibuf_rsrc.num_allocated < MAX_IBUF_HANDLES) && + (ibuf_rsrc.free_size >= aligned_size)) { + handle = getHandle(ibuf_rsrc.num_allocated); + handle->start_addr = ibuf_rsrc.free_start_addr; + handle->size = aligned_size; + handle->active = true; + + ibuf_rsrc.free_start_addr += aligned_size; + ibuf_rsrc.free_size -= aligned_size; + ibuf_rsrc.num_active++; + ibuf_rsrc.num_allocated++; + + input_buffer_found = true; + } + } + + if (input_buffer_found && handle) { + *start_addr = handle->start_addr; + retval = true; + } + + return retval; +} + +void ia_css_isys_ibuf_rmgr_release( + uint32_t *start_addr) +{ + uint16_t i; + ibuf_handle_t *handle = NULL; + + assert(start_addr != NULL); + + for (i = 0; i < ibuf_rsrc.num_allocated; i++) { + handle = getHandle(i); + if ((handle->start_addr == *start_addr) + && ( true == handle->active)) { + handle->active = false; + ibuf_rsrc.num_active--; + break; + } + } +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/ibuf_ctrl_rmgr.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/ibuf_ctrl_rmgr.h new file mode 100644 index 0000000000000000000000000000000000000000..424cfe9f3b2a286d17038bc85e00370b895ecc54 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/ibuf_ctrl_rmgr.h @@ -0,0 +1,55 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef __IBUF_CTRL_RMGR_H_INCLUDED__ +#define __IBUF_CTRL_RMGR_H_INCLUDED__ + +#define MAX_IBUF_HANDLES 24 +#define MAX_INPUT_BUFFER_SIZE (64 * 1024) +#define IBUF_ALIGN 8 + +typedef struct ibuf_handle_s ibuf_handle_t; +struct ibuf_handle_s { + uint32_t start_addr; + uint32_t size; + bool active; +}; + +typedef struct ibuf_rsrc_s ibuf_rsrc_t; +struct ibuf_rsrc_s { + uint32_t free_start_addr; + uint32_t free_size; + uint16_t num_active; + uint16_t num_allocated; + ibuf_handle_t handles[MAX_IBUF_HANDLES]; +}; + +#endif /* __IBUF_CTRL_RMGR_H_INCLUDED */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_dma_rmgr.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_dma_rmgr.c new file mode 100644 index 0000000000000000000000000000000000000000..d99150a4aaf4ebea024770da98d19848a74892ad --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_dma_rmgr.c @@ -0,0 +1,103 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#include "system_global.h" + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + +#include "assert_support.h" +#include "platform_support.h" +#include "ia_css_isys.h" +#include "bitop_support.h" +#include "isys_dma_rmgr.h" + +static isys_dma_rsrc_t isys_dma_rsrc[N_ISYS2401_DMA_ID]; + +void ia_css_isys_dma_channel_rmgr_init(void) +{ + memset(&isys_dma_rsrc, 0, sizeof(isys_dma_rsrc_t)); +} + +void ia_css_isys_dma_channel_rmgr_uninit(void) +{ + memset(&isys_dma_rsrc, 0, sizeof(isys_dma_rsrc_t)); +} + +bool ia_css_isys_dma_channel_rmgr_acquire( + isys2401_dma_ID_t dma_id, + isys2401_dma_channel *channel) +{ + bool retval = false; + isys2401_dma_channel i; + isys2401_dma_channel max_dma_channel; + isys_dma_rsrc_t *cur_rsrc = NULL; + + assert(dma_id < N_ISYS2401_DMA_ID); + assert(channel != NULL); + + max_dma_channel = N_ISYS2401_DMA_CHANNEL_PROCS[dma_id]; + cur_rsrc = &isys_dma_rsrc[dma_id]; + + if (cur_rsrc->num_active < max_dma_channel) { + for (i = ISYS2401_DMA_CHANNEL_0; i < N_ISYS2401_DMA_CHANNEL; i++) { + if (bitop_getbit(cur_rsrc->active_table, i) == 0) { + bitop_setbit(cur_rsrc->active_table, i); + *channel = (isys2401_dma_channel)i; + cur_rsrc->num_active++; + retval = true; + break; + } + } + } + + return retval; +} + +void ia_css_isys_dma_channel_rmgr_release( + isys2401_dma_ID_t dma_id, + isys2401_dma_channel *channel) +{ + isys2401_dma_channel max_dma_channel; + isys_dma_rsrc_t *cur_rsrc = NULL; + + assert(dma_id < N_ISYS2401_DMA_ID); + assert(channel != NULL); + + max_dma_channel = N_ISYS2401_DMA_CHANNEL_PROCS[dma_id]; + cur_rsrc = &isys_dma_rsrc[dma_id]; + + if ((*channel < max_dma_channel) && (cur_rsrc->num_active > 0)) { + if (bitop_getbit(cur_rsrc->active_table, *channel) == 1) { + bitop_clearbit(cur_rsrc->active_table, *channel); + cur_rsrc->num_active--; + } + } +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_dma_rmgr.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_dma_rmgr.h new file mode 100644 index 0000000000000000000000000000000000000000..b2c286537774f9cec06e5677d7be571631bba87a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_dma_rmgr.h @@ -0,0 +1,41 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef __ISYS_DMA_RMGR_H_INCLUDED__ +#define __ISYS_DMA_RMGR_H_INCLUDED__ + +typedef struct isys_dma_rsrc_s isys_dma_rsrc_t; +struct isys_dma_rsrc_s { + uint32_t active_table; + uint16_t num_active; +}; + +#endif /* __ISYS_DMA_RMGR_H_INCLUDED__ */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_init.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_init.c new file mode 100644 index 0000000000000000000000000000000000000000..239ef310bdeb6f653eb345ed06513eaae0e88e05 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_init.c @@ -0,0 +1,141 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#include "input_system.h" + +#ifdef HAS_INPUT_SYSTEM_VERSION_2 +#include "ia_css_isys.h" +#include "platform_support.h" + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 +#include "isys_dma.h" /* isys2401_dma_set_max_burst_size() */ +#include "isys_irq.h" +#endif + +#if defined(USE_INPUT_SYSTEM_VERSION_2) +input_system_error_t ia_css_isys_init(void) +{ + backend_channel_cfg_t backend_ch0; + backend_channel_cfg_t backend_ch1; + target_cfg2400_t targetB; + target_cfg2400_t targetC; + uint32_t acq_mem_region_size = 24; + uint32_t acq_nof_mem_regions = 2; + input_system_error_t error = INPUT_SYSTEM_ERR_NO_ERROR; + + memset(&backend_ch0, 0, sizeof(backend_channel_cfg_t)); + memset(&backend_ch1, 0, sizeof(backend_channel_cfg_t)); + memset(&targetB, 0, sizeof(targetB)); + memset(&targetC, 0, sizeof(targetC)); + + error = input_system_configuration_reset(); + if (error != INPUT_SYSTEM_ERR_NO_ERROR) + return error; + + error = input_system_csi_xmem_channel_cfg( + 0, /*ch_id */ + INPUT_SYSTEM_PORT_A, /*port */ + backend_ch0, /*backend_ch */ + 32, /*mem_region_size */ + 6, /*nof_mem_regions */ + acq_mem_region_size, /*acq_mem_region_size */ + acq_nof_mem_regions, /*acq_nof_mem_regions */ + targetB, /*target */ + 3); /*nof_xmem_buffers */ + if (error != INPUT_SYSTEM_ERR_NO_ERROR) + return error; + + error = input_system_csi_xmem_channel_cfg( + 1, /*ch_id */ + INPUT_SYSTEM_PORT_B, /*port */ + backend_ch0, /*backend_ch */ + 16, /*mem_region_size */ + 3, /*nof_mem_regions */ + acq_mem_region_size, /*acq_mem_region_size */ + acq_nof_mem_regions, /*acq_nof_mem_regions */ + targetB, /*target */ + 3); /*nof_xmem_buffers */ + if (error != INPUT_SYSTEM_ERR_NO_ERROR) + return error; + + error = input_system_csi_xmem_channel_cfg( + 2, /*ch_id */ + INPUT_SYSTEM_PORT_C, /*port */ + backend_ch1, /*backend_ch */ + 32, /*mem_region_size */ + 3, /*nof_mem_regions */ + acq_mem_region_size, /*acq_mem_region_size */ + acq_nof_mem_regions, /*acq_nof_mem_regions */ + targetC, /*target */ + 2); /*nof_xmem_buffers */ + if (error != INPUT_SYSTEM_ERR_NO_ERROR) + return error; + + error = input_system_configuration_commit(); + + return error; +} +#elif defined(USE_INPUT_SYSTEM_VERSION_2401) +input_system_error_t ia_css_isys_init(void) +{ + input_system_error_t error = INPUT_SYSTEM_ERR_NO_ERROR; + + ia_css_isys_csi_rx_lut_rmgr_init(); + ia_css_isys_ibuf_rmgr_init(); + ia_css_isys_dma_channel_rmgr_init(); + ia_css_isys_stream2mmio_sid_rmgr_init(); + + isys2401_dma_set_max_burst_size(ISYS2401_DMA0_ID, + 1 /* Non Burst DMA transactions */); + + /* Enable 2401 input system IRQ status for driver to retrieve */ + isys_irqc_status_enable(ISYS_IRQ0_ID); + isys_irqc_status_enable(ISYS_IRQ1_ID); + isys_irqc_status_enable(ISYS_IRQ2_ID); + + return error; +} +#endif + +#if defined(USE_INPUT_SYSTEM_VERSION_2) +void ia_css_isys_uninit(void) +{ +} +#elif defined(USE_INPUT_SYSTEM_VERSION_2401) +void ia_css_isys_uninit(void) +{ + ia_css_isys_csi_rx_lut_rmgr_uninit(); + ia_css_isys_ibuf_rmgr_uninit(); + ia_css_isys_dma_channel_rmgr_uninit(); + ia_css_isys_stream2mmio_sid_rmgr_uninit(); +} +#endif + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_stream2mmio_rmgr.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_stream2mmio_rmgr.c new file mode 100644 index 0000000000000000000000000000000000000000..a93c7f44ff1283e18ba1c26821a9cbdbfb0dace5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_stream2mmio_rmgr.c @@ -0,0 +1,105 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#include "system_global.h" + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + +#include "assert_support.h" +#include "platform_support.h" +#include "ia_css_isys.h" +#include "bitop_support.h" +#include "isys_stream2mmio_rmgr.h" + +static isys_stream2mmio_rsrc_t isys_stream2mmio_rsrc[N_STREAM2MMIO_ID]; + +void ia_css_isys_stream2mmio_sid_rmgr_init(void) +{ + memset(isys_stream2mmio_rsrc, 0, sizeof(isys_stream2mmio_rsrc)); +} + +void ia_css_isys_stream2mmio_sid_rmgr_uninit(void) +{ + memset(isys_stream2mmio_rsrc, 0, sizeof(isys_stream2mmio_rsrc)); +} + +bool ia_css_isys_stream2mmio_sid_rmgr_acquire( + stream2mmio_ID_t stream2mmio, + stream2mmio_sid_ID_t *sid) +{ + bool retval = false; + stream2mmio_sid_ID_t max_sid; + isys_stream2mmio_rsrc_t *cur_rsrc = NULL; + stream2mmio_sid_ID_t i; + + assert(stream2mmio < N_STREAM2MMIO_ID); + assert(sid != NULL); + + if ((stream2mmio < N_STREAM2MMIO_ID) && (sid != NULL)) { + max_sid = N_STREAM2MMIO_SID_PROCS[stream2mmio]; + cur_rsrc = &isys_stream2mmio_rsrc[stream2mmio]; + + if (cur_rsrc->num_active < max_sid) { + for (i = STREAM2MMIO_SID0_ID; i < max_sid; i++) { + if (bitop_getbit(cur_rsrc->active_table, i) == 0) { + bitop_setbit(cur_rsrc->active_table, i); + *sid = i; + cur_rsrc->num_active++; + retval = true; + break; + } + } + } + } + return retval; +} + +void ia_css_isys_stream2mmio_sid_rmgr_release( + stream2mmio_ID_t stream2mmio, + stream2mmio_sid_ID_t *sid) +{ + stream2mmio_sid_ID_t max_sid; + isys_stream2mmio_rsrc_t *cur_rsrc = NULL; + + assert(stream2mmio < N_STREAM2MMIO_ID); + assert(sid != NULL); + + if ((stream2mmio < N_STREAM2MMIO_ID) && (sid != NULL)) { + max_sid = N_STREAM2MMIO_SID_PROCS[stream2mmio]; + cur_rsrc = &isys_stream2mmio_rsrc[stream2mmio]; + if ((*sid < max_sid) && (cur_rsrc->num_active > 0)) { + if (bitop_getbit(cur_rsrc->active_table, *sid) == 1) { + bitop_clearbit(cur_rsrc->active_table, *sid); + cur_rsrc->num_active--; + } + } + } +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_stream2mmio_rmgr.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_stream2mmio_rmgr.h new file mode 100644 index 0000000000000000000000000000000000000000..4f63005b1071b815e85335346e1ee8b8aba7cecf --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/isys_stream2mmio_rmgr.h @@ -0,0 +1,41 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef __ISYS_STREAM2MMIO_RMGR_H_INCLUDED__ +#define __ISYS_STREAM2MMIO_RMGR_H_INCLUDED__ + +typedef struct isys_stream2mmio_rsrc_s isys_stream2mmio_rsrc_t; +struct isys_stream2mmio_rsrc_s { + uint32_t active_table; + uint16_t num_active; +}; + +#endif /* __ISYS_STREAM2MMIO_RMGR_H_INCLUDED__ */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/rx.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/rx.c new file mode 100644 index 0000000000000000000000000000000000000000..46a157f64343c21e176efc976fcea11140b0efbc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/rx.c @@ -0,0 +1,607 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#define __INLINE_INPUT_SYSTEM__ +#include "input_system.h" +#include "assert_support.h" +#include "ia_css_isys.h" +#include "ia_css_irq.h" +#include "sh_css_internal.h" + +#if !defined(USE_INPUT_SYSTEM_VERSION_2401) +void ia_css_isys_rx_enable_all_interrupts(mipi_port_ID_t port) +{ + hrt_data bits = receiver_port_reg_load(RX0_ID, + port, + _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX); + + bits |= (1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT) | +#if defined(HAS_RX_VERSION_2) + (1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT) | +#endif + (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT) | + /*(1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_NO_CORRECTION_BIT) | */ + (1U << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT) | + (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT); + /*(1U << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT); */ + + receiver_port_reg_store(RX0_ID, + port, + _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX, bits); + + /* + * The CSI is nested into the Iunit IRQ's + */ + ia_css_irq_enable(IA_CSS_IRQ_INFO_CSS_RECEIVER_ERROR, true); + + return; +} + +/* This function converts between the enum used on the CSS API and the + * internal DLI enum type. + * We do not use an array for this since we cannot use named array + * initializers in Windows. Without that there is no easy way to guarantee + * that the array values would be in the correct order. + * */ +mipi_port_ID_t ia_css_isys_port_to_mipi_port(enum ia_css_csi2_port api_port) +{ + /* In this module the validity of the inptu variable should + * have been checked already, so we do not check for erroneous + * values. */ + mipi_port_ID_t port = MIPI_PORT0_ID; + + if (api_port == IA_CSS_CSI2_PORT1) + port = MIPI_PORT1_ID; + else if (api_port == IA_CSS_CSI2_PORT2) + port = MIPI_PORT2_ID; + + return port; +} + +unsigned int ia_css_isys_rx_get_interrupt_reg(mipi_port_ID_t port) +{ + return receiver_port_reg_load(RX0_ID, + port, + _HRT_CSS_RECEIVER_IRQ_STATUS_REG_IDX); +} + +void ia_css_rx_get_irq_info(unsigned int *irq_infos) +{ + ia_css_rx_port_get_irq_info(IA_CSS_CSI2_PORT1, irq_infos); +} + +void ia_css_rx_port_get_irq_info(enum ia_css_csi2_port api_port, + unsigned int *irq_infos) +{ + mipi_port_ID_t port = ia_css_isys_port_to_mipi_port(api_port); + ia_css_isys_rx_get_irq_info(port, irq_infos); +} + +void ia_css_isys_rx_get_irq_info(mipi_port_ID_t port, + unsigned int *irq_infos) +{ + unsigned int bits; + + assert(irq_infos != NULL); + bits = ia_css_isys_rx_get_interrupt_reg(port); + *irq_infos = ia_css_isys_rx_translate_irq_infos(bits); +} + +/* Translate register bits to CSS API enum mask */ +unsigned int ia_css_isys_rx_translate_irq_infos(unsigned int bits) +{ + unsigned int infos = 0; + + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN; +#if defined(HAS_RX_VERSION_2) + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_INIT_TIMEOUT; +#endif + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ECC_CORRECTED; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_SOT; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_CONTROL; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_CRC; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC; + if (bits & (1U << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT)) + infos |= IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC; + + return infos; +} + +void ia_css_rx_clear_irq_info(unsigned int irq_infos) +{ + ia_css_rx_port_clear_irq_info(IA_CSS_CSI2_PORT1, irq_infos); +} + +void ia_css_rx_port_clear_irq_info(enum ia_css_csi2_port api_port, unsigned int irq_infos) +{ + mipi_port_ID_t port = ia_css_isys_port_to_mipi_port(api_port); + ia_css_isys_rx_clear_irq_info(port, irq_infos); +} + +void ia_css_isys_rx_clear_irq_info(mipi_port_ID_t port, unsigned int irq_infos) +{ + hrt_data bits = receiver_port_reg_load(RX0_ID, + port, + _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX); + + /* MW: Why do we remap the receiver bitmap */ + if (irq_infos & IA_CSS_RX_IRQ_INFO_BUFFER_OVERRUN) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_OVERRUN_BIT; +#if defined(HAS_RX_VERSION_2) + if (irq_infos & IA_CSS_RX_IRQ_INFO_INIT_TIMEOUT) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_INIT_TIMEOUT_BIT; +#endif + if (irq_infos & IA_CSS_RX_IRQ_INFO_ENTER_SLEEP_MODE) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_ENTRY_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_EXIT_SLEEP_MODE) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_SLEEP_MODE_EXIT_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ECC_CORRECTED) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_CORRECTED_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_SOT) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_HS_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_SOT_SYNC) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_SOT_SYNC_HS_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_CONTROL) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_CONTROL_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_ECC_DOUBLE) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ECC_DOUBLE_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_CRC) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_CRC_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ID) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ID_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_SYNC) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_SYNC_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_FRAME_DATA) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_FRAME_DATA_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_DATA_TIMEOUT) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_DATA_TIMEOUT_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_UNKNOWN_ESC) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_ESCAPE_BIT; + if (irq_infos & IA_CSS_RX_IRQ_INFO_ERR_LINE_SYNC) + bits |= 1U << _HRT_CSS_RECEIVER_IRQ_ERR_LINE_SYNC_BIT; + + receiver_port_reg_store(RX0_ID, + port, + _HRT_CSS_RECEIVER_IRQ_ENABLE_REG_IDX, bits); + + return; +} +#endif /* #if !defined(USE_INPUT_SYSTEM_VERSION_2401) */ + +enum ia_css_err ia_css_isys_convert_stream_format_to_mipi_format( + enum ia_css_stream_format input_format, + mipi_predictor_t compression, + unsigned int *fmt_type) +{ + assert(fmt_type != NULL); + /* + * Custom (user defined) modes. Used for compressed + * MIPI transfers + * + * Checkpatch thinks the indent before "if" is suspect + * I think the only suspect part is the missing "else" + * because of the return. + */ + if (compression != MIPI_PREDICTOR_NONE) { + switch (input_format) { + case IA_CSS_STREAM_FORMAT_RAW_6: + *fmt_type = 6; + break; + case IA_CSS_STREAM_FORMAT_RAW_7: + *fmt_type = 7; + break; + case IA_CSS_STREAM_FORMAT_RAW_8: + *fmt_type = 8; + break; + case IA_CSS_STREAM_FORMAT_RAW_10: + *fmt_type = 10; + break; + case IA_CSS_STREAM_FORMAT_RAW_12: + *fmt_type = 12; + break; + case IA_CSS_STREAM_FORMAT_RAW_14: + *fmt_type = 14; + break; + case IA_CSS_STREAM_FORMAT_RAW_16: + *fmt_type = 16; + break; + default: + return IA_CSS_ERR_INTERNAL_ERROR; + } + return IA_CSS_SUCCESS; + } + /* + * This mapping comes from the Arasan CSS function spec + * (CSS_func_spec1.08_ahb_sep29_08.pdf). + * + * MW: For some reason the mapping is not 1-to-1 + */ + switch (input_format) { + case IA_CSS_STREAM_FORMAT_RGB_888: + *fmt_type = MIPI_FORMAT_RGB888; + break; + case IA_CSS_STREAM_FORMAT_RGB_555: + *fmt_type = MIPI_FORMAT_RGB555; + break; + case IA_CSS_STREAM_FORMAT_RGB_444: + *fmt_type = MIPI_FORMAT_RGB444; + break; + case IA_CSS_STREAM_FORMAT_RGB_565: + *fmt_type = MIPI_FORMAT_RGB565; + break; + case IA_CSS_STREAM_FORMAT_RGB_666: + *fmt_type = MIPI_FORMAT_RGB666; + break; + case IA_CSS_STREAM_FORMAT_RAW_8: + *fmt_type = MIPI_FORMAT_RAW8; + break; + case IA_CSS_STREAM_FORMAT_RAW_10: + *fmt_type = MIPI_FORMAT_RAW10; + break; + case IA_CSS_STREAM_FORMAT_RAW_6: + *fmt_type = MIPI_FORMAT_RAW6; + break; + case IA_CSS_STREAM_FORMAT_RAW_7: + *fmt_type = MIPI_FORMAT_RAW7; + break; + case IA_CSS_STREAM_FORMAT_RAW_12: + *fmt_type = MIPI_FORMAT_RAW12; + break; + case IA_CSS_STREAM_FORMAT_RAW_14: + *fmt_type = MIPI_FORMAT_RAW14; + break; + case IA_CSS_STREAM_FORMAT_YUV420_8: + *fmt_type = MIPI_FORMAT_YUV420_8; + break; + case IA_CSS_STREAM_FORMAT_YUV420_10: + *fmt_type = MIPI_FORMAT_YUV420_10; + break; + case IA_CSS_STREAM_FORMAT_YUV422_8: + *fmt_type = MIPI_FORMAT_YUV422_8; + break; + case IA_CSS_STREAM_FORMAT_YUV422_10: + *fmt_type = MIPI_FORMAT_YUV422_10; + break; + case IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY: + *fmt_type = MIPI_FORMAT_YUV420_8_LEGACY; + break; + case IA_CSS_STREAM_FORMAT_EMBEDDED: + *fmt_type = MIPI_FORMAT_EMBEDDED; + break; +#ifndef USE_INPUT_SYSTEM_VERSION_2401 + case IA_CSS_STREAM_FORMAT_RAW_16: + /* This is not specified by Arasan, so we use + * 17 for now. + */ + *fmt_type = MIPI_FORMAT_RAW16; + break; + case IA_CSS_STREAM_FORMAT_BINARY_8: + *fmt_type = MIPI_FORMAT_BINARY_8; + break; +#else + case IA_CSS_STREAM_FORMAT_USER_DEF1: + *fmt_type = MIPI_FORMAT_CUSTOM0; + break; + case IA_CSS_STREAM_FORMAT_USER_DEF2: + *fmt_type = MIPI_FORMAT_CUSTOM1; + break; + case IA_CSS_STREAM_FORMAT_USER_DEF3: + *fmt_type = MIPI_FORMAT_CUSTOM2; + break; + case IA_CSS_STREAM_FORMAT_USER_DEF4: + *fmt_type = MIPI_FORMAT_CUSTOM3; + break; + case IA_CSS_STREAM_FORMAT_USER_DEF5: + *fmt_type = MIPI_FORMAT_CUSTOM4; + break; + case IA_CSS_STREAM_FORMAT_USER_DEF6: + *fmt_type = MIPI_FORMAT_CUSTOM5; + break; + case IA_CSS_STREAM_FORMAT_USER_DEF7: + *fmt_type = MIPI_FORMAT_CUSTOM6; + break; + case IA_CSS_STREAM_FORMAT_USER_DEF8: + *fmt_type = MIPI_FORMAT_CUSTOM7; + break; +#endif + + case IA_CSS_STREAM_FORMAT_YUV420_16: + case IA_CSS_STREAM_FORMAT_YUV422_16: + default: + return IA_CSS_ERR_INTERNAL_ERROR; + } + return IA_CSS_SUCCESS; +} +#if defined(USE_INPUT_SYSTEM_VERSION_2401) +static mipi_predictor_t sh_css_csi2_compression_type_2_mipi_predictor(enum ia_css_csi2_compression_type type) +{ + mipi_predictor_t predictor = MIPI_PREDICTOR_NONE; + + switch (type) { + case IA_CSS_CSI2_COMPRESSION_TYPE_1: + predictor = MIPI_PREDICTOR_TYPE1-1; + break; + case IA_CSS_CSI2_COMPRESSION_TYPE_2: + predictor = MIPI_PREDICTOR_TYPE2-1; + default: + break; + } + return predictor; +} +enum ia_css_err ia_css_isys_convert_compressed_format( + struct ia_css_csi2_compression *comp, + struct input_system_cfg_s *cfg) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + assert(comp != NULL); + assert(cfg != NULL); + + if (comp->type != IA_CSS_CSI2_COMPRESSION_TYPE_NONE) { + /* compression register bit slicing + 4 bit for each user defined data type + 3 bit indicate compression scheme + 000 No compression + 001 10-6-10 + 010 10-7-10 + 011 10-8-10 + 100 12-6-12 + 101 12-6-12 + 100 12-7-12 + 110 12-8-12 + 1 bit indicate predictor + */ + if (comp->uncompressed_bits_per_pixel == UNCOMPRESSED_BITS_PER_PIXEL_10) { + switch (comp->compressed_bits_per_pixel) { + case COMPRESSED_BITS_PER_PIXEL_6: + cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_10_6_10; + break; + case COMPRESSED_BITS_PER_PIXEL_7: + cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_10_7_10; + break; + case COMPRESSED_BITS_PER_PIXEL_8: + cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_10_8_10; + break; + default: + err = IA_CSS_ERR_INVALID_ARGUMENTS; + } + } else if (comp->uncompressed_bits_per_pixel == UNCOMPRESSED_BITS_PER_PIXEL_12) { + switch (comp->compressed_bits_per_pixel) { + case COMPRESSED_BITS_PER_PIXEL_6: + cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_12_6_12; + break; + case COMPRESSED_BITS_PER_PIXEL_7: + cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_12_7_12; + break; + case COMPRESSED_BITS_PER_PIXEL_8: + cfg->csi_port_attr.comp_scheme = MIPI_COMPRESSOR_12_8_12; + break; + default: + err = IA_CSS_ERR_INVALID_ARGUMENTS; + } + } else + err = IA_CSS_ERR_INVALID_ARGUMENTS; + cfg->csi_port_attr.comp_predictor = sh_css_csi2_compression_type_2_mipi_predictor(comp->type); + cfg->csi_port_attr.comp_enable = true; + } else /* No compression */ + cfg->csi_port_attr.comp_enable = false; + return err; +} + +unsigned int ia_css_csi2_calculate_input_system_alignment( + enum ia_css_stream_format fmt_type) +{ + unsigned int memory_alignment_in_bytes = HIVE_ISP_DDR_WORD_BYTES; + + switch (fmt_type) { + case IA_CSS_STREAM_FORMAT_RAW_6: + case IA_CSS_STREAM_FORMAT_RAW_7: + case IA_CSS_STREAM_FORMAT_RAW_8: + case IA_CSS_STREAM_FORMAT_RAW_10: + case IA_CSS_STREAM_FORMAT_RAW_12: + case IA_CSS_STREAM_FORMAT_RAW_14: + memory_alignment_in_bytes = 2 * ISP_VEC_NELEMS; + break; + case IA_CSS_STREAM_FORMAT_YUV420_8: + case IA_CSS_STREAM_FORMAT_YUV422_8: + case IA_CSS_STREAM_FORMAT_USER_DEF1: + case IA_CSS_STREAM_FORMAT_USER_DEF2: + case IA_CSS_STREAM_FORMAT_USER_DEF3: + case IA_CSS_STREAM_FORMAT_USER_DEF4: + case IA_CSS_STREAM_FORMAT_USER_DEF5: + case IA_CSS_STREAM_FORMAT_USER_DEF6: + case IA_CSS_STREAM_FORMAT_USER_DEF7: + case IA_CSS_STREAM_FORMAT_USER_DEF8: + /* Planar YUV formats need to have all planes aligned, this means + * double the alignment for the Y plane if the horizontal decimation is 2. */ + memory_alignment_in_bytes = 2 * HIVE_ISP_DDR_WORD_BYTES; + break; + case IA_CSS_STREAM_FORMAT_EMBEDDED: + default: + memory_alignment_in_bytes = HIVE_ISP_DDR_WORD_BYTES; + break; + } + return memory_alignment_in_bytes; +} + +#endif + +#if !defined(USE_INPUT_SYSTEM_VERSION_2401) +void ia_css_isys_rx_configure(const rx_cfg_t *config, + const enum ia_css_input_mode input_mode) +{ +#if defined(HAS_RX_VERSION_2) + bool port_enabled[N_MIPI_PORT_ID]; + bool any_port_enabled = false; + mipi_port_ID_t port; + + if ((config == NULL) + || (config->mode >= N_RX_MODE) + || (config->port >= N_MIPI_PORT_ID)) { + assert(0); + return; + } + for (port = (mipi_port_ID_t) 0; port < N_MIPI_PORT_ID; port++) { + if (is_receiver_port_enabled(RX0_ID, port)) + any_port_enabled = true; + } + /* AM: Check whether this is a problem with multiple + * streams. MS: This is the case. */ + + port = config->port; + receiver_port_enable(RX0_ID, port, false); + + port = config->port; + + /* AM: Check whether this is a problem with multiple streams. */ + if (MIPI_PORT_LANES[config->mode][port] != MIPI_0LANE_CFG) { + receiver_port_reg_store(RX0_ID, port, + _HRT_CSS_RECEIVER_FUNC_PROG_REG_IDX, + config->timeout); + receiver_port_reg_store(RX0_ID, port, + _HRT_CSS_RECEIVER_2400_INIT_COUNT_REG_IDX, + config->initcount); + receiver_port_reg_store(RX0_ID, port, + _HRT_CSS_RECEIVER_2400_SYNC_COUNT_REG_IDX, + config->synccount); + receiver_port_reg_store(RX0_ID, port, + _HRT_CSS_RECEIVER_2400_RX_COUNT_REG_IDX, + config->rxcount); + + port_enabled[port] = true; + + if (input_mode != IA_CSS_INPUT_MODE_BUFFERED_SENSOR) { + + /* MW: A bit of a hack, straight wiring of the capture + * units,assuming they are linearly enumerated. */ + input_system_sub_system_reg_store(INPUT_SYSTEM0_ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_A_IDX + + (unsigned int)port, + INPUT_SYSTEM_CSI_BACKEND); + /* MW: Like the integration test example we overwite, + * the GPREG_MUX register */ + input_system_sub_system_reg_store(INPUT_SYSTEM0_ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MUX_IDX, + (input_system_multiplex_t) port); + } else { + /* + * AM: A bit of a hack, wiring the input system. + */ + input_system_sub_system_reg_store(INPUT_SYSTEM0_ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MULTICAST_A_IDX + + (unsigned int)port, + INPUT_SYSTEM_INPUT_BUFFER); + input_system_sub_system_reg_store(INPUT_SYSTEM0_ID, + GPREGS_UNIT0_ID, + HIVE_ISYS_GPREG_MUX_IDX, + INPUT_SYSTEM_ACQUISITION_UNIT); + } + } + /* + * The 2ppc is shared for all ports, so we cannot + * disable->configure->enable individual ports + */ + /* AM: Check whether this is a problem with multiple streams. */ + /* MS: 2ppc should be a property per binary and should be + * enabled/disabled per binary. + * Currently it is implemented as a system wide setting due + * to effort and risks. */ + if (!any_port_enabled) { + receiver_reg_store(RX0_ID, + _HRT_CSS_RECEIVER_TWO_PIXEL_EN_REG_IDX, + config->is_two_ppc); + receiver_reg_store(RX0_ID, _HRT_CSS_RECEIVER_BE_TWO_PPC_REG_IDX, + config->is_two_ppc); + } + receiver_port_enable(RX0_ID, port, true); + /* TODO: JB: need to add the beneath used define to mizuchi */ + /* sh_css_sw_hive_isp_css_2400_system_20121224_0125\css + * \hrt\input_system_defs.h + * #define INPUT_SYSTEM_CSI_RECEIVER_SELECT_BACKENG 0X207 + */ + /* TODO: need better name for define + * input_system_reg_store(INPUT_SYSTEM0_ID, + * INPUT_SYSTEM_CSI_RECEIVER_SELECT_BACKENG, 1); + */ + input_system_reg_store(INPUT_SYSTEM0_ID, 0x207, 1); +#else +#error "rx.c: RX version must be one of {RX_VERSION_2}" +#endif + + return; +} + +void ia_css_isys_rx_disable(void) +{ + mipi_port_ID_t port; + for (port = (mipi_port_ID_t) 0; port < N_MIPI_PORT_ID; port++) { + receiver_port_reg_store(RX0_ID, port, + _HRT_CSS_RECEIVER_DEVICE_READY_REG_IDX, + false); + } + return; +} +#endif /* if !defined(USE_INPUT_SYSTEM_VERSION_2401) */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/virtual_isys.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/virtual_isys.c new file mode 100644 index 0000000000000000000000000000000000000000..0f1e8a2f6b104a45e682e5126161376b213b1471 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/virtual_isys.c @@ -0,0 +1,898 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#include "system_global.h" + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + +#include "ia_css_isys.h" +#include "ia_css_debug.h" +#include "math_support.h" +#include "string_support.h" +#include "virtual_isys.h" +#include "isp.h" +#include "sh_css_defs.h" + +/************************************************* + * + * Forwarded Declaration + * + *************************************************/ +#ifndef ISP2401 + +#endif +static bool create_input_system_channel( + input_system_cfg_t *cfg, + bool metadata, + input_system_channel_t *channel); + +static void destroy_input_system_channel( + input_system_channel_t *channel); + +static bool create_input_system_input_port( + input_system_cfg_t *cfg, + input_system_input_port_t *input_port); + +static void destroy_input_system_input_port( + input_system_input_port_t *input_port); + +static bool calculate_input_system_channel_cfg( + input_system_channel_t *channel, + input_system_input_port_t *input_port, + input_system_cfg_t *isys_cfg, + input_system_channel_cfg_t *channel_cfg, + bool metadata); + +static bool calculate_input_system_input_port_cfg( + input_system_channel_t *channel, + input_system_input_port_t *input_port, + input_system_cfg_t *isys_cfg, + input_system_input_port_cfg_t *input_port_cfg); + +static bool acquire_sid( + stream2mmio_ID_t stream2mmio, + stream2mmio_sid_ID_t *sid); + +static void release_sid( + stream2mmio_ID_t stream2mmio, + stream2mmio_sid_ID_t *sid); + +static bool acquire_ib_buffer( + int32_t bits_per_pixel, + int32_t pixels_per_line, + int32_t lines_per_frame, + int32_t align_in_bytes, + bool online, + ib_buffer_t *buf); + +static void release_ib_buffer( + ib_buffer_t *buf); + +static bool acquire_dma_channel( + isys2401_dma_ID_t dma_id, + isys2401_dma_channel *channel); + +static void release_dma_channel( + isys2401_dma_ID_t dma_id, + isys2401_dma_channel *channel); + +static bool acquire_be_lut_entry( + csi_rx_backend_ID_t backend, + csi_mipi_packet_type_t packet_type, + csi_rx_backend_lut_entry_t *entry); + +static void release_be_lut_entry( + csi_rx_backend_ID_t backend, + csi_mipi_packet_type_t packet_type, + csi_rx_backend_lut_entry_t *entry); + +static bool calculate_tpg_cfg( + input_system_channel_t *channel, + input_system_input_port_t *input_port, + input_system_cfg_t *isys_cfg, + pixelgen_tpg_cfg_t *cfg); + +static bool calculate_prbs_cfg( + input_system_channel_t *channel, + input_system_input_port_t *input_port, + input_system_cfg_t *isys_cfg, + pixelgen_prbs_cfg_t *cfg); + +static bool calculate_fe_cfg( + const input_system_cfg_t *isys_cfg, + csi_rx_frontend_cfg_t *cfg); + +static bool calculate_be_cfg( + const input_system_input_port_t *input_port, + const input_system_cfg_t *isys_cfg, + bool metadata, + csi_rx_backend_cfg_t *cfg); + +static bool calculate_stream2mmio_cfg( + const input_system_cfg_t *isys_cfg, + bool metadata, + stream2mmio_cfg_t *cfg); + +static bool calculate_ibuf_ctrl_cfg( + const input_system_channel_t *channel, + const input_system_input_port_t *input_port, + const input_system_cfg_t *isys_cfg, + ibuf_ctrl_cfg_t *cfg); + +static bool calculate_isys2401_dma_cfg( + const input_system_channel_t *channel, + const input_system_cfg_t *isys_cfg, + isys2401_dma_cfg_t *cfg); + +static bool calculate_isys2401_dma_port_cfg( + const input_system_cfg_t *isys_cfg, + bool raw_packed, + bool metadata, + isys2401_dma_port_cfg_t *cfg); + +static csi_mipi_packet_type_t get_csi_mipi_packet_type( + int32_t data_type); + +static int32_t calculate_stride( + int32_t bits_per_pixel, + int32_t pixels_per_line, + bool raw_packed, + int32_t align_in_bytes); + +/** end of Forwarded Declaration */ + +/************************************************** + * + * Public Methods + * + **************************************************/ +ia_css_isys_error_t ia_css_isys_stream_create( + ia_css_isys_descr_t *isys_stream_descr, + ia_css_isys_stream_h isys_stream, + uint32_t isys_stream_id) +{ + ia_css_isys_error_t rc; + + if (isys_stream_descr == NULL || isys_stream == NULL || + isys_stream_id >= SH_CSS_MAX_ISYS_CHANNEL_NODES) + return false; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_isys_stream_create() enter:\n"); + + /*Reset isys_stream to 0*/ + memset(isys_stream, 0, sizeof(*isys_stream)); + isys_stream->enable_metadata = isys_stream_descr->metadata.enable; + isys_stream->id = isys_stream_id; + + isys_stream->linked_isys_stream_id = isys_stream_descr->linked_isys_stream_id; + rc = create_input_system_input_port(isys_stream_descr, &(isys_stream->input_port)); + if (rc == false) + return false; + + rc = create_input_system_channel(isys_stream_descr, false, &(isys_stream->channel)); + if (rc == false) { + destroy_input_system_input_port(&isys_stream->input_port); + return false; + } + +#ifdef ISP2401 + /* + * Early polling is required for timestamp accuracy in certain cause. + * The ISYS HW polling is started on + * ia_css_isys_stream_capture_indication() instead of + * ia_css_pipeline_sp_wait_for_isys_stream_N() as isp processing of + * capture takes longer than getting an ISYS frame + */ + isys_stream->polling_mode = isys_stream_descr->polling_mode; + +#endif + /* create metadata channel */ + if (isys_stream_descr->metadata.enable) { + rc = create_input_system_channel(isys_stream_descr, true, &isys_stream->md_channel); + if (rc == false) { + destroy_input_system_input_port(&isys_stream->input_port); + destroy_input_system_channel(&isys_stream->channel); + return false; + } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_isys_stream_create() leave:\n"); + + return true; +} + +void ia_css_isys_stream_destroy( + ia_css_isys_stream_h isys_stream) +{ + destroy_input_system_input_port(&isys_stream->input_port); + destroy_input_system_channel(&(isys_stream->channel)); + if (isys_stream->enable_metadata) { + /* Destroy metadata channel only if its allocated*/ + destroy_input_system_channel(&isys_stream->md_channel); + } +} + +ia_css_isys_error_t ia_css_isys_stream_calculate_cfg( + ia_css_isys_stream_h isys_stream, + ia_css_isys_descr_t *isys_stream_descr, + ia_css_isys_stream_cfg_t *isys_stream_cfg) +{ + ia_css_isys_error_t rc; + + if (isys_stream_cfg == NULL || + isys_stream_descr == NULL || + isys_stream == NULL) + return false; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_isys_stream_calculate_cfg() enter:\n"); + + rc = calculate_input_system_channel_cfg( + &(isys_stream->channel), + &(isys_stream->input_port), + isys_stream_descr, + &(isys_stream_cfg->channel_cfg), + false); + if (rc == false) + return false; + + /* configure metadata channel */ + if (isys_stream_descr->metadata.enable) { + isys_stream_cfg->enable_metadata = true; + rc = calculate_input_system_channel_cfg( + &isys_stream->md_channel, + &isys_stream->input_port, + isys_stream_descr, + &isys_stream_cfg->md_channel_cfg, + true); + if (rc == false) + return false; + } + + rc = calculate_input_system_input_port_cfg( + &(isys_stream->channel), + &(isys_stream->input_port), + isys_stream_descr, + &(isys_stream_cfg->input_port_cfg)); + if (rc == false) + return false; + + isys_stream->valid = 1; + isys_stream_cfg->valid = 1; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_isys_stream_calculate_cfg() leave:\n"); + return rc; +} + +/** end of Public Methods */ + +/************************************************** + * + * Private Methods + * + **************************************************/ +static bool create_input_system_channel( + input_system_cfg_t *cfg, + bool metadata, + input_system_channel_t *me) +{ + bool rc = true; + + me->dma_id = ISYS2401_DMA0_ID; + + switch (cfg->input_port_id) { + case INPUT_SYSTEM_CSI_PORT0_ID: + case INPUT_SYSTEM_PIXELGEN_PORT0_ID: + me->stream2mmio_id = STREAM2MMIO0_ID; + me->ibuf_ctrl_id = IBUF_CTRL0_ID; + break; + + case INPUT_SYSTEM_CSI_PORT1_ID: + case INPUT_SYSTEM_PIXELGEN_PORT1_ID: + me->stream2mmio_id = STREAM2MMIO1_ID; + me->ibuf_ctrl_id = IBUF_CTRL1_ID; + break; + + case INPUT_SYSTEM_CSI_PORT2_ID: + case INPUT_SYSTEM_PIXELGEN_PORT2_ID: + me->stream2mmio_id = STREAM2MMIO2_ID; + me->ibuf_ctrl_id = IBUF_CTRL2_ID; + break; + default: + rc = false; + break; + } + + if (rc == false) + return false; + + if (!acquire_sid(me->stream2mmio_id, &(me->stream2mmio_sid_id))) { + return false; + } + + if (!acquire_ib_buffer( + metadata ? cfg->metadata.bits_per_pixel : cfg->input_port_resolution.bits_per_pixel, + metadata ? cfg->metadata.pixels_per_line : cfg->input_port_resolution.pixels_per_line, + metadata ? cfg->metadata.lines_per_frame : cfg->input_port_resolution.lines_per_frame, + metadata ? cfg->metadata.align_req_in_bytes : cfg->input_port_resolution.align_req_in_bytes, + cfg->online, + &(me->ib_buffer))) { + release_sid(me->stream2mmio_id, &(me->stream2mmio_sid_id)); + return false; + } + + if (!acquire_dma_channel(me->dma_id, &(me->dma_channel))) { + release_sid(me->stream2mmio_id, &(me->stream2mmio_sid_id)); + release_ib_buffer(&(me->ib_buffer)); + return false; + } + + return true; +} + +static void destroy_input_system_channel( + input_system_channel_t *me) +{ + release_sid(me->stream2mmio_id, + &(me->stream2mmio_sid_id)); + + release_ib_buffer(&(me->ib_buffer)); + + release_dma_channel(me->dma_id, &(me->dma_channel)); +} + +static bool create_input_system_input_port( + input_system_cfg_t *cfg, + input_system_input_port_t *me) +{ + csi_mipi_packet_type_t packet_type; + bool rc = true; + + switch (cfg->input_port_id) { + case INPUT_SYSTEM_CSI_PORT0_ID: + me->csi_rx.frontend_id = CSI_RX_FRONTEND0_ID; + me->csi_rx.backend_id = CSI_RX_BACKEND0_ID; + + packet_type = get_csi_mipi_packet_type(cfg->csi_port_attr.fmt_type); + me->csi_rx.packet_type = packet_type; + + rc = acquire_be_lut_entry( + me->csi_rx.backend_id, + packet_type, + &(me->csi_rx.backend_lut_entry)); + break; + case INPUT_SYSTEM_PIXELGEN_PORT0_ID: + me->pixelgen.pixelgen_id = PIXELGEN0_ID; + break; + case INPUT_SYSTEM_CSI_PORT1_ID: + me->csi_rx.frontend_id = CSI_RX_FRONTEND1_ID; + me->csi_rx.backend_id = CSI_RX_BACKEND1_ID; + + packet_type = get_csi_mipi_packet_type(cfg->csi_port_attr.fmt_type); + me->csi_rx.packet_type = packet_type; + + rc = acquire_be_lut_entry( + me->csi_rx.backend_id, + packet_type, + &(me->csi_rx.backend_lut_entry)); + break; + case INPUT_SYSTEM_PIXELGEN_PORT1_ID: + me->pixelgen.pixelgen_id = PIXELGEN1_ID; + + break; + case INPUT_SYSTEM_CSI_PORT2_ID: + me->csi_rx.frontend_id = CSI_RX_FRONTEND2_ID; + me->csi_rx.backend_id = CSI_RX_BACKEND2_ID; + + packet_type = get_csi_mipi_packet_type(cfg->csi_port_attr.fmt_type); + me->csi_rx.packet_type = packet_type; + + rc = acquire_be_lut_entry( + me->csi_rx.backend_id, + packet_type, + &(me->csi_rx.backend_lut_entry)); + break; + case INPUT_SYSTEM_PIXELGEN_PORT2_ID: + me->pixelgen.pixelgen_id = PIXELGEN2_ID; + break; + default: + rc = false; + break; + } + + me->source_type = cfg->mode; + + /* for metadata */ + me->metadata.packet_type = CSI_MIPI_PACKET_TYPE_UNDEFINED; + if (rc && cfg->metadata.enable) { + me->metadata.packet_type = get_csi_mipi_packet_type( + cfg->metadata.fmt_type); + rc = acquire_be_lut_entry( + me->csi_rx.backend_id, + me->metadata.packet_type, + &me->metadata.backend_lut_entry); + } + + return rc; +} + +static void destroy_input_system_input_port( + input_system_input_port_t *me) +{ + if (me->source_type == INPUT_SYSTEM_SOURCE_TYPE_SENSOR) { + release_be_lut_entry( + me->csi_rx.backend_id, + me->csi_rx.packet_type, + &me->csi_rx.backend_lut_entry); + } + + if (me->metadata.packet_type != CSI_MIPI_PACKET_TYPE_UNDEFINED) { + /*Free the backend lut allocated for metadata*/ + release_be_lut_entry( + me->csi_rx.backend_id, + me->metadata.packet_type, + &me->metadata.backend_lut_entry); + } +} + +static bool calculate_input_system_channel_cfg( + input_system_channel_t *channel, + input_system_input_port_t *input_port, + input_system_cfg_t *isys_cfg, + input_system_channel_cfg_t *channel_cfg, + bool metadata) +{ + bool rc; + + rc = calculate_stream2mmio_cfg(isys_cfg, metadata, + &(channel_cfg->stream2mmio_cfg)); + if (rc == false) + return false; + + rc = calculate_ibuf_ctrl_cfg( + channel, + input_port, + isys_cfg, + &(channel_cfg->ibuf_ctrl_cfg)); + if (rc == false) + return false; + if (metadata) + channel_cfg->ibuf_ctrl_cfg.stores_per_frame = isys_cfg->metadata.lines_per_frame; + + rc = calculate_isys2401_dma_cfg( + channel, + isys_cfg, + &(channel_cfg->dma_cfg)); + if (rc == false) + return false; + + rc = calculate_isys2401_dma_port_cfg( + isys_cfg, + false, + metadata, + &(channel_cfg->dma_src_port_cfg)); + if (rc == false) + return false; + + rc = calculate_isys2401_dma_port_cfg( + isys_cfg, + isys_cfg->raw_packed, + metadata, + &(channel_cfg->dma_dest_port_cfg)); + if (rc == false) + return false; + + return true; +} + +static bool calculate_input_system_input_port_cfg( + input_system_channel_t *channel, + input_system_input_port_t *input_port, + input_system_cfg_t *isys_cfg, + input_system_input_port_cfg_t *input_port_cfg) +{ + bool rc; + + switch (input_port->source_type) { + case INPUT_SYSTEM_SOURCE_TYPE_SENSOR: + rc = calculate_fe_cfg( + isys_cfg, + &(input_port_cfg->csi_rx_cfg.frontend_cfg)); + + rc &= calculate_be_cfg( + input_port, + isys_cfg, + false, + &(input_port_cfg->csi_rx_cfg.backend_cfg)); + + if (rc && isys_cfg->metadata.enable) + rc &= calculate_be_cfg(input_port, isys_cfg, true, + &input_port_cfg->csi_rx_cfg.md_backend_cfg); + break; + case INPUT_SYSTEM_SOURCE_TYPE_TPG: + rc = calculate_tpg_cfg( + channel, + input_port, + isys_cfg, + &(input_port_cfg->pixelgen_cfg.tpg_cfg)); + break; + case INPUT_SYSTEM_SOURCE_TYPE_PRBS: + rc = calculate_prbs_cfg( + channel, + input_port, + isys_cfg, + &(input_port_cfg->pixelgen_cfg.prbs_cfg)); + break; + default: + rc = false; + break; + } + + return rc; +} + +static bool acquire_sid( + stream2mmio_ID_t stream2mmio, + stream2mmio_sid_ID_t *sid) +{ + return ia_css_isys_stream2mmio_sid_rmgr_acquire(stream2mmio, sid); +} + +static void release_sid( + stream2mmio_ID_t stream2mmio, + stream2mmio_sid_ID_t *sid) +{ + ia_css_isys_stream2mmio_sid_rmgr_release(stream2mmio, sid); +} + +/* See also: ia_css_dma_configure_from_info() */ +static int32_t calculate_stride( + int32_t bits_per_pixel, + int32_t pixels_per_line, + bool raw_packed, + int32_t align_in_bytes) +{ + int32_t bytes_per_line; + int32_t pixels_per_word; + int32_t words_per_line; + int32_t pixels_per_line_padded; + + pixels_per_line_padded = CEIL_MUL(pixels_per_line, align_in_bytes); + + if (!raw_packed) + bits_per_pixel = CEIL_MUL(bits_per_pixel, 8); + + pixels_per_word = HIVE_ISP_DDR_WORD_BITS / bits_per_pixel; + words_per_line = ceil_div(pixels_per_line_padded, pixels_per_word); + bytes_per_line = HIVE_ISP_DDR_WORD_BYTES * words_per_line; + + return bytes_per_line; +} + +static bool acquire_ib_buffer( + int32_t bits_per_pixel, + int32_t pixels_per_line, + int32_t lines_per_frame, + int32_t align_in_bytes, + bool online, + ib_buffer_t *buf) +{ + buf->stride = calculate_stride(bits_per_pixel, pixels_per_line, false, align_in_bytes); + if (online) + buf->lines = 4; /* use double buffering for online usecases */ + else + buf->lines = 2; + + (void)(lines_per_frame); + return ia_css_isys_ibuf_rmgr_acquire(buf->stride * buf->lines, &buf->start_addr); +} + +static void release_ib_buffer( + ib_buffer_t *buf) +{ + ia_css_isys_ibuf_rmgr_release(&buf->start_addr); +} + +static bool acquire_dma_channel( + isys2401_dma_ID_t dma_id, + isys2401_dma_channel *channel) +{ + return ia_css_isys_dma_channel_rmgr_acquire(dma_id, channel); +} + +static void release_dma_channel( + isys2401_dma_ID_t dma_id, + isys2401_dma_channel *channel) +{ + ia_css_isys_dma_channel_rmgr_release(dma_id, channel); +} + +static bool acquire_be_lut_entry( + csi_rx_backend_ID_t backend, + csi_mipi_packet_type_t packet_type, + csi_rx_backend_lut_entry_t *entry) +{ + return ia_css_isys_csi_rx_lut_rmgr_acquire(backend, packet_type, entry); +} + +static void release_be_lut_entry( + csi_rx_backend_ID_t backend, + csi_mipi_packet_type_t packet_type, + csi_rx_backend_lut_entry_t *entry) +{ + ia_css_isys_csi_rx_lut_rmgr_release(backend, packet_type, entry); +} + +static bool calculate_tpg_cfg( + input_system_channel_t *channel, + input_system_input_port_t *input_port, + input_system_cfg_t *isys_cfg, + pixelgen_tpg_cfg_t *cfg) +{ + (void)channel; + (void)input_port; + + memcpy_s( + (void *)cfg, + sizeof(pixelgen_tpg_cfg_t), + (void *)(&(isys_cfg->tpg_port_attr)), + sizeof(pixelgen_tpg_cfg_t)); + return true; +} + +static bool calculate_prbs_cfg( + input_system_channel_t *channel, + input_system_input_port_t *input_port, + input_system_cfg_t *isys_cfg, + pixelgen_prbs_cfg_t *cfg) +{ + (void)channel; + (void)input_port; + + memcpy_s( + (void *)cfg, + sizeof(pixelgen_prbs_cfg_t), + (void *)(&(isys_cfg->prbs_port_attr)), + sizeof(pixelgen_prbs_cfg_t)); + return true; +} + +static bool calculate_fe_cfg( + const input_system_cfg_t *isys_cfg, + csi_rx_frontend_cfg_t *cfg) +{ + cfg->active_lanes = isys_cfg->csi_port_attr.active_lanes; + return true; +} + +static bool calculate_be_cfg( + const input_system_input_port_t *input_port, + const input_system_cfg_t *isys_cfg, + bool metadata, + csi_rx_backend_cfg_t *cfg) +{ + + memcpy_s( + (void *)(&cfg->lut_entry), + sizeof(csi_rx_backend_lut_entry_t), + metadata ? (void *)(&input_port->metadata.backend_lut_entry) : + (void *)(&input_port->csi_rx.backend_lut_entry), + sizeof(csi_rx_backend_lut_entry_t)); + + cfg->csi_mipi_cfg.virtual_channel = isys_cfg->csi_port_attr.ch_id; + if (metadata) { + cfg->csi_mipi_packet_type = get_csi_mipi_packet_type(isys_cfg->metadata.fmt_type); + cfg->csi_mipi_cfg.comp_enable = false; + cfg->csi_mipi_cfg.data_type = isys_cfg->metadata.fmt_type; + } + else { + cfg->csi_mipi_packet_type = get_csi_mipi_packet_type(isys_cfg->csi_port_attr.fmt_type); + cfg->csi_mipi_cfg.data_type = isys_cfg->csi_port_attr.fmt_type; + cfg->csi_mipi_cfg.comp_enable = isys_cfg->csi_port_attr.comp_enable; + cfg->csi_mipi_cfg.comp_scheme = isys_cfg->csi_port_attr.comp_scheme; + cfg->csi_mipi_cfg.comp_predictor = isys_cfg->csi_port_attr.comp_predictor; + cfg->csi_mipi_cfg.comp_bit_idx = cfg->csi_mipi_cfg.data_type - MIPI_FORMAT_CUSTOM0; + } + + return true; +} + +static bool calculate_stream2mmio_cfg( + const input_system_cfg_t *isys_cfg, + bool metadata, + stream2mmio_cfg_t *cfg +) +{ + cfg->bits_per_pixel = metadata ? isys_cfg->metadata.bits_per_pixel : + isys_cfg->input_port_resolution.bits_per_pixel; + + cfg->enable_blocking = + ((isys_cfg->mode == INPUT_SYSTEM_SOURCE_TYPE_TPG) || + (isys_cfg->mode == INPUT_SYSTEM_SOURCE_TYPE_PRBS)); + + return true; +} + +static bool calculate_ibuf_ctrl_cfg( + const input_system_channel_t *channel, + const input_system_input_port_t *input_port, + const input_system_cfg_t *isys_cfg, + ibuf_ctrl_cfg_t *cfg) +{ + const int32_t bits_per_byte = 8; + int32_t bits_per_pixel; + int32_t bytes_per_pixel; + int32_t left_padding; + + (void)input_port; + + bits_per_pixel = isys_cfg->input_port_resolution.bits_per_pixel; + bytes_per_pixel = ceil_div(bits_per_pixel, bits_per_byte); + + left_padding = CEIL_MUL(isys_cfg->output_port_attr.left_padding, ISP_VEC_NELEMS) + * bytes_per_pixel; + + cfg->online = isys_cfg->online; + + cfg->dma_cfg.channel = channel->dma_channel; + cfg->dma_cfg.cmd = _DMA_V2_MOVE_A2B_NO_SYNC_CHK_COMMAND; + + cfg->dma_cfg.shift_returned_items = 0; + cfg->dma_cfg.elems_per_word_in_ibuf = 0; + cfg->dma_cfg.elems_per_word_in_dest = 0; + + cfg->ib_buffer.start_addr = channel->ib_buffer.start_addr; + cfg->ib_buffer.stride = channel->ib_buffer.stride; + cfg->ib_buffer.lines = channel->ib_buffer.lines; + + /* +#ifndef ISP2401 + * zhengjie.lu@intel.com: +#endif + * "dest_buf_cfg" should be part of the input system output + * port configuration. + * + * TODO: move "dest_buf_cfg" to the input system output + * port configuration. + */ + + /* input_buf addr only available in sched mode; + this buffer is allocated in isp, crun mode addr + can be passed by after ISP allocation */ + if (cfg->online) { + cfg->dest_buf_cfg.start_addr = ISP_INPUT_BUF_START_ADDR + left_padding; + cfg->dest_buf_cfg.stride = bytes_per_pixel + * isys_cfg->output_port_attr.max_isp_input_width; + cfg->dest_buf_cfg.lines = LINES_OF_ISP_INPUT_BUF; + } else if (isys_cfg->raw_packed) { + cfg->dest_buf_cfg.stride = calculate_stride(bits_per_pixel, + isys_cfg->input_port_resolution.pixels_per_line, + isys_cfg->raw_packed, + isys_cfg->input_port_resolution.align_req_in_bytes); + } else { + cfg->dest_buf_cfg.stride = channel->ib_buffer.stride; + } + + /* +#ifndef ISP2401 + * zhengjie.lu@intel.com: +#endif + * "items_per_store" is hard coded as "1", which is ONLY valid + * when the CSI-MIPI long packet is transferred. + * + * TODO: After the 1st stage of MERR+, make the proper solution to + * configure "items_per_store" so that it can also handle the CSI-MIPI + * short packet. + */ + cfg->items_per_store = 1; + + cfg->stores_per_frame = isys_cfg->input_port_resolution.lines_per_frame; + + + cfg->stream2mmio_cfg.sync_cmd = _STREAM2MMIO_CMD_TOKEN_SYNC_FRAME; + + /* TODO: Define conditions as when to use store words vs store packets */ + cfg->stream2mmio_cfg.store_cmd = _STREAM2MMIO_CMD_TOKEN_STORE_PACKETS; + + return true; +} + +static bool calculate_isys2401_dma_cfg( + const input_system_channel_t *channel, + const input_system_cfg_t *isys_cfg, + isys2401_dma_cfg_t *cfg) +{ + cfg->channel = channel->dma_channel; + + /* only online/sensor mode goto vmem + offline/buffered_sensor, tpg and prbs will go to ddr */ + if (isys_cfg->online) + cfg->connection = isys2401_dma_ibuf_to_vmem_connection; + else + cfg->connection = isys2401_dma_ibuf_to_ddr_connection; + + cfg->extension = isys2401_dma_zero_extension; + cfg->height = 1; + + return true; +} + +/* See also: ia_css_dma_configure_from_info() */ +static bool calculate_isys2401_dma_port_cfg( + const input_system_cfg_t *isys_cfg, + bool raw_packed, + bool metadata, + isys2401_dma_port_cfg_t *cfg) +{ + int32_t bits_per_pixel; + int32_t pixels_per_line; + int32_t align_req_in_bytes; + + /* TODO: Move metadata away from isys_cfg to application layer */ + if (metadata) { + bits_per_pixel = isys_cfg->metadata.bits_per_pixel; + pixels_per_line = isys_cfg->metadata.pixels_per_line; + align_req_in_bytes = isys_cfg->metadata.align_req_in_bytes; + } else { + bits_per_pixel = isys_cfg->input_port_resolution.bits_per_pixel; + pixels_per_line = isys_cfg->input_port_resolution.pixels_per_line; + align_req_in_bytes = isys_cfg->input_port_resolution.align_req_in_bytes; + } + + cfg->stride = calculate_stride(bits_per_pixel, pixels_per_line, raw_packed, align_req_in_bytes); + + if (!raw_packed) + bits_per_pixel = CEIL_MUL(bits_per_pixel, 8); + + cfg->elements = HIVE_ISP_DDR_WORD_BITS / bits_per_pixel; + cfg->cropping = 0; + cfg->width = CEIL_DIV(cfg->stride, HIVE_ISP_DDR_WORD_BYTES); + + return true; +} + +static csi_mipi_packet_type_t get_csi_mipi_packet_type( + int32_t data_type) +{ + csi_mipi_packet_type_t packet_type; + + packet_type = CSI_MIPI_PACKET_TYPE_RESERVED; + + if (data_type >= 0 && data_type <= MIPI_FORMAT_SHORT8) + packet_type = CSI_MIPI_PACKET_TYPE_SHORT; + + if (data_type > MIPI_FORMAT_SHORT8 && data_type <= N_MIPI_FORMAT) + packet_type = CSI_MIPI_PACKET_TYPE_LONG; + + return packet_type; +} +/** end of Private Methods */ +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/virtual_isys.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/virtual_isys.h new file mode 100644 index 0000000000000000000000000000000000000000..66c7293c0a93ed6ec5324a235a83c653befe8cc9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/isys/src/virtual_isys.h @@ -0,0 +1,41 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef __VIRTUAL_ISYS_H_INCLUDED__ +#define __VIRTUAL_ISYS_H_INCLUDED__ + +/* cmd for storing a number of packets indicated by reg _STREAM2MMIO_NUM_ITEMS*/ +#define _STREAM2MMIO_CMD_TOKEN_STORE_PACKETS 1 + +/* command for waiting for a frame start */ +#define _STREAM2MMIO_CMD_TOKEN_SYNC_FRAME 2 + +#endif /* __VIRTUAL_ISYS_H_INCLUDED__ */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/pipeline/interface/ia_css_pipeline.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/pipeline/interface/ia_css_pipeline.h new file mode 100644 index 0000000000000000000000000000000000000000..90646f5f888568299a6c55b5218828fc4bd08ded --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/pipeline/interface/ia_css_pipeline.h @@ -0,0 +1,308 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef __IA_CSS_PIPELINE_H__ +#define __IA_CSS_PIPELINE_H__ + +#include "sh_css_internal.h" +#include "ia_css_pipe_public.h" +#include "ia_css_pipeline_common.h" + +#define IA_CSS_PIPELINE_NUM_MAX (20) + + +/* Pipeline stage to be executed on SP/ISP */ +struct ia_css_pipeline_stage { + unsigned int stage_num; + struct ia_css_binary *binary; /* built-in binary */ + struct ia_css_binary_info *binary_info; + const struct ia_css_fw_info *firmware; /* acceleration binary */ + /* SP function for SP stage */ + enum ia_css_pipeline_stage_sp_func sp_func; + unsigned max_input_width; /* For SP raw copy */ + struct sh_css_binary_args args; + int mode; + bool out_frame_allocated[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + bool vf_frame_allocated; + struct ia_css_pipeline_stage *next; + bool enable_zoom; +}; + +/* Pipeline of n stages to be executed on SP/ISP per stage */ +struct ia_css_pipeline { + enum ia_css_pipe_id pipe_id; + uint8_t pipe_num; + bool stop_requested; + struct ia_css_pipeline_stage *stages; + struct ia_css_pipeline_stage *current_stage; + unsigned num_stages; + struct ia_css_frame in_frame; + struct ia_css_frame out_frame[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + struct ia_css_frame vf_frame[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + unsigned int dvs_frame_delay; + unsigned inout_port_config; + int num_execs; + bool acquire_isp_each_stage; + uint32_t pipe_qos_config; +}; + +#define DEFAULT_PIPELINE \ +{ \ + IA_CSS_PIPE_ID_PREVIEW, /* pipe_id */ \ + 0, /* pipe_num */ \ + false, /* stop_requested */ \ + NULL, /* stages */ \ + NULL, /* current_stage */ \ + 0, /* num_stages */ \ + DEFAULT_FRAME, /* in_frame */ \ + {DEFAULT_FRAME}, /* out_frame */ \ + {DEFAULT_FRAME}, /* vf_frame */ \ + IA_CSS_FRAME_DELAY_1, /* frame_delay */ \ + 0, /* inout_port_config */ \ + -1, /* num_execs */ \ + true, /* acquire_isp_each_stage */\ + QOS_INVALID /* pipe_qos_config */\ +} + +/* Stage descriptor used to create a new stage in the pipeline */ +struct ia_css_pipeline_stage_desc { + struct ia_css_binary *binary; + const struct ia_css_fw_info *firmware; + enum ia_css_pipeline_stage_sp_func sp_func; + unsigned max_input_width; + unsigned int mode; + struct ia_css_frame *in_frame; + struct ia_css_frame *out_frame[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_frame *vf_frame; +}; + +/** @brief initialize the pipeline module + * + * @return None + * + * Initializes the pipeline module. This API has to be called + * before any operation on the pipeline module is done + */ +void ia_css_pipeline_init(void); + +/** @brief initialize the pipeline structure with default values + * + * @param[out] pipeline structure to be initialized with defaults + * @param[in] pipe_id + * @param[in] pipe_num Number that uniquely identifies a pipeline. + * @return IA_CSS_SUCCESS or error code upon error. + * + * Initializes the pipeline structure with a set of default values. + * This API is expected to be used when a pipeline structure is allocated + * externally and needs sane defaults + */ +enum ia_css_err ia_css_pipeline_create( + struct ia_css_pipeline *pipeline, + enum ia_css_pipe_id pipe_id, + unsigned int pipe_num, + unsigned int dvs_frame_delay); + +/** @brief destroy a pipeline + * + * @param[in] pipeline + * @return None + * + */ +void ia_css_pipeline_destroy(struct ia_css_pipeline *pipeline); + + +/** @brief Starts a pipeline + * + * @param[in] pipe_id + * @param[in] pipeline + * @return None + * + */ +void ia_css_pipeline_start(enum ia_css_pipe_id pipe_id, + struct ia_css_pipeline *pipeline); + +/** @brief Request to stop a pipeline + * + * @param[in] pipeline + * @return IA_CSS_SUCCESS or error code upon error. + * + */ +enum ia_css_err ia_css_pipeline_request_stop(struct ia_css_pipeline *pipeline); + +/** @brief Check whether pipeline has stopped + * + * @param[in] pipeline + * @return true if the pipeline has stopped + * + */ +bool ia_css_pipeline_has_stopped(struct ia_css_pipeline *pipe); + +/** @brief clean all the stages pipeline and make it as new + * + * @param[in] pipeline + * @return None + * + */ +void ia_css_pipeline_clean(struct ia_css_pipeline *pipeline); + +/** @brief Add a stage to pipeline. + * + * @param pipeline Pointer to the pipeline to be added to. + * @param[in] stage_desc The description of the stage + * @param[out] stage The successor of the stage. + * @return IA_CSS_SUCCESS or error code upon error. + * + * Add a new stage to a non-NULL pipeline. + * The stage consists of an ISP binary or firmware and input and output + * arguments. +*/ +enum ia_css_err ia_css_pipeline_create_and_add_stage( + struct ia_css_pipeline *pipeline, + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_pipeline_stage **stage); + +/** @brief Finalize the stages in a pipeline + * + * @param pipeline Pointer to the pipeline to be added to. + * @return None + * + * This API is expected to be called after adding all stages +*/ +void ia_css_pipeline_finalize_stages(struct ia_css_pipeline *pipeline, + bool continuous); + +/** @brief gets a stage from the pipeline + * + * @param[in] pipeline + * @return IA_CSS_SUCCESS or error code upon error. + * + */ +enum ia_css_err ia_css_pipeline_get_stage(struct ia_css_pipeline *pipeline, + int mode, + struct ia_css_pipeline_stage **stage); + +/** @brief Gets a pipeline stage corresponding Firmware handle from the pipeline + * + * @param[in] pipeline + * @param[in] fw_handle + * @param[out] stage Pointer to Stage + * + * @return IA_CSS_SUCCESS or error code upon error. + * + */ +enum ia_css_err ia_css_pipeline_get_stage_from_fw(struct ia_css_pipeline *pipeline, + uint32_t fw_handle, + struct ia_css_pipeline_stage **stage); + +/** @brief Gets the Firmware handle correponding the stage num from the pipeline + * + * @param[in] pipeline + * @param[in] stage_num + * @param[out] fw_handle + * + * @return IA_CSS_SUCCESS or error code upon error. + * + */ +enum ia_css_err ia_css_pipeline_get_fw_from_stage(struct ia_css_pipeline *pipeline, + uint32_t stage_num, + uint32_t *fw_handle); + +/** @brief gets the output stage from the pipeline + * + * @param[in] pipeline + * @return IA_CSS_SUCCESS or error code upon error. + * + */ +enum ia_css_err ia_css_pipeline_get_output_stage( + struct ia_css_pipeline *pipeline, + int mode, + struct ia_css_pipeline_stage **stage); + +/** @brief Checks whether the pipeline uses params + * + * @param[in] pipeline + * @return true if the pipeline uses params + * + */ +bool ia_css_pipeline_uses_params(struct ia_css_pipeline *pipeline); + +/** + * @brief get the SP thread ID. + * + * @param[in] key The query key, typical use is pipe_num. + * @param[out] val The query value. + * + * @return + * true, if the query succeeds; + * false, if the query fails. + */ +bool ia_css_pipeline_get_sp_thread_id(unsigned int key, unsigned int *val); + +#if defined(USE_INPUT_SYSTEM_VERSION_2401) +/** + * @brief Get the pipeline io status + * + * @param[in] None + * @return + * Pointer to pipe_io_status + */ +struct sh_css_sp_pipeline_io_status *ia_css_pipeline_get_pipe_io_status(void); +#endif + +/** + * @brief Map an SP thread to this pipeline + * + * @param[in] pipe_num + * @param[in] map true for mapping and false for unmapping sp threads. + * + */ +void ia_css_pipeline_map(unsigned int pipe_num, bool map); + +/** + * @brief Checks whether the pipeline is mapped to SP threads + * + * @param[in] Query key, typical use is pipe_num + * + * return + * true, pipeline is mapped to SP threads + * false, pipeline is not mapped to SP threads + */ +bool ia_css_pipeline_is_mapped(unsigned int key); + +/** + * @brief Print pipeline thread mapping + * + * @param[in] none + * + * return none + */ +void ia_css_pipeline_dump_thread_map_info(void); + +#endif /*__IA_CSS_PIPELINE_H__*/ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/pipeline/interface/ia_css_pipeline_common.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/pipeline/interface/ia_css_pipeline_common.h new file mode 100644 index 0000000000000000000000000000000000000000..a7e6edf41cdbd0449458eb9ff845dda816e270c5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/pipeline/interface/ia_css_pipeline_common.h @@ -0,0 +1,42 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef __IA_CSS_PIPELINE_COMMON_H__ +#define __IA_CSS_PIPELINE_COMMON_H__ + +enum ia_css_pipeline_stage_sp_func { + IA_CSS_PIPELINE_RAW_COPY = 0, + IA_CSS_PIPELINE_BIN_COPY = 1, + IA_CSS_PIPELINE_ISYS_COPY = 2, + IA_CSS_PIPELINE_NO_FUNC = 3, +}; +#define IA_CSS_PIPELINE_NUM_STAGE_FUNCS 3 + +#endif /*__IA_CSS_PIPELINE_COMMON_H__*/ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/pipeline/src/pipeline.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/pipeline/src/pipeline.c new file mode 100644 index 0000000000000000000000000000000000000000..95542fc8221710032b8673d67551e46fa0a87dda --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/pipeline/src/pipeline.c @@ -0,0 +1,806 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#include "ia_css_debug.h" +#include "sw_event_global.h" /* encode_sw_event */ +#include "sp.h" /* cnd_sp_irq_enable() */ +#include "assert_support.h" +#include "memory_access.h" +#include "sh_css_sp.h" +#include "ia_css_pipeline.h" +#include "ia_css_isp_param.h" +#include "ia_css_bufq.h" + +#define PIPELINE_NUM_UNMAPPED (~0U) +#define PIPELINE_SP_THREAD_EMPTY_TOKEN (0x0) +#define PIPELINE_SP_THREAD_RESERVED_TOKEN (0x1) + + +/******************************************************* +*** Static variables +********************************************************/ +static unsigned int pipeline_num_to_sp_thread_map[IA_CSS_PIPELINE_NUM_MAX]; +static unsigned int pipeline_sp_thread_list[SH_CSS_MAX_SP_THREADS]; + +/******************************************************* +*** Static functions +********************************************************/ +static void pipeline_init_sp_thread_map(void); +static void pipeline_map_num_to_sp_thread(unsigned int pipe_num); +static void pipeline_unmap_num_to_sp_thread(unsigned int pipe_num); +static void pipeline_init_defaults( + struct ia_css_pipeline *pipeline, + enum ia_css_pipe_id pipe_id, + unsigned int pipe_num, + unsigned int dvs_frame_delay); + +static void pipeline_stage_destroy(struct ia_css_pipeline_stage *stage); +static enum ia_css_err pipeline_stage_create( + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_pipeline_stage **new_stage); +static void ia_css_pipeline_set_zoom_stage(struct ia_css_pipeline *pipeline); +static void ia_css_pipeline_configure_inout_port(struct ia_css_pipeline *me, + bool continuous); + +/******************************************************* +*** Public functions +********************************************************/ +void ia_css_pipeline_init(void) +{ + pipeline_init_sp_thread_map(); +} + +enum ia_css_err ia_css_pipeline_create( + struct ia_css_pipeline *pipeline, + enum ia_css_pipe_id pipe_id, + unsigned int pipe_num, + unsigned int dvs_frame_delay) +{ + assert(pipeline != NULL); + IA_CSS_ENTER_PRIVATE("pipeline = %p, pipe_id = %d, pipe_num = %d, dvs_frame_delay = %d", + pipeline, pipe_id, pipe_num, dvs_frame_delay); + if (pipeline == NULL) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + pipeline_init_defaults(pipeline, pipe_id, pipe_num, dvs_frame_delay); + + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + return IA_CSS_SUCCESS; +} + +void ia_css_pipeline_map(unsigned int pipe_num, bool map) +{ + assert(pipe_num < IA_CSS_PIPELINE_NUM_MAX); + IA_CSS_ENTER_PRIVATE("pipe_num = %d, map = %d", pipe_num, map); + + if (pipe_num >= IA_CSS_PIPELINE_NUM_MAX) { + IA_CSS_ERROR("Invalid pipe number"); + IA_CSS_LEAVE_PRIVATE("void"); + return; + } + if (map) + pipeline_map_num_to_sp_thread(pipe_num); + else + pipeline_unmap_num_to_sp_thread(pipe_num); + IA_CSS_LEAVE_PRIVATE("void"); +} + +/** @brief destroy a pipeline + * + * @param[in] pipeline + * @return None + * + */ +void ia_css_pipeline_destroy(struct ia_css_pipeline *pipeline) +{ + assert(pipeline != NULL); + IA_CSS_ENTER_PRIVATE("pipeline = %p", pipeline); + + if (pipeline == NULL) { + IA_CSS_ERROR("NULL input parameter"); + IA_CSS_LEAVE_PRIVATE("void"); + return; + } + + IA_CSS_LOG("pipe_num = %d", pipeline->pipe_num); + + /* Free the pipeline number */ + ia_css_pipeline_clean(pipeline); + + IA_CSS_LEAVE_PRIVATE("void"); +} + +/* Run a pipeline and wait till it completes. */ +void ia_css_pipeline_start(enum ia_css_pipe_id pipe_id, + struct ia_css_pipeline *pipeline) +{ + uint8_t pipe_num = 0; + unsigned int thread_id; + + assert(pipeline != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_start() enter: pipe_id=%d, pipeline=%p\n", + pipe_id, pipeline); + pipeline->pipe_id = pipe_id; + sh_css_sp_init_pipeline(pipeline, pipe_id, pipe_num, + false, false, false, true, SH_CSS_BDS_FACTOR_1_00, + SH_CSS_PIPE_CONFIG_OVRD_NO_OVRD, +#ifndef ISP2401 + IA_CSS_INPUT_MODE_MEMORY, NULL, NULL +#else + IA_CSS_INPUT_MODE_MEMORY, NULL, NULL, +#endif +#if !defined(HAS_NO_INPUT_SYSTEM) +#ifndef ISP2401 + , (mipi_port_ID_t) 0 +#else + (mipi_port_ID_t) 0, +#endif +#endif +#ifndef ISP2401 + ); +#else + NULL, NULL); +#endif + ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id); + if (!sh_css_sp_is_running()) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_start() error,leaving\n"); + /* queues are invalid*/ + return; + } + ia_css_bufq_enqueue_psys_event(IA_CSS_PSYS_SW_EVENT_START_STREAM, + (uint8_t)thread_id, + 0, + 0); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_start() leave: return_void\n"); +} + +/** + * @brief Query the SP thread ID. + * Refer to "sh_css_internal.h" for details. + */ +bool ia_css_pipeline_get_sp_thread_id(unsigned int key, unsigned int *val) +{ + + IA_CSS_ENTER("key=%d, val=%p", key, val); + + if ((val == NULL) || (key >= IA_CSS_PIPELINE_NUM_MAX) || (key >= IA_CSS_PIPE_ID_NUM)) { + IA_CSS_LEAVE("return value = false"); + return false; + } + + *val = pipeline_num_to_sp_thread_map[key]; + + if (*val == (unsigned)PIPELINE_NUM_UNMAPPED) { + IA_CSS_LOG("unmapped pipeline number"); + IA_CSS_LEAVE("return value = false"); + return false; + } + IA_CSS_LEAVE("return value = true"); + return true; +} + +void ia_css_pipeline_dump_thread_map_info(void) +{ + unsigned int i; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "pipeline_num_to_sp_thread_map:\n"); + for (i = 0; i < IA_CSS_PIPELINE_NUM_MAX; i++) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "pipe_num: %u, tid: 0x%x\n", i, pipeline_num_to_sp_thread_map[i]); + } +} + +enum ia_css_err ia_css_pipeline_request_stop(struct ia_css_pipeline *pipeline) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + unsigned int thread_id; + + assert(pipeline != NULL); + + if (pipeline == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_request_stop() enter: pipeline=%p\n", + pipeline); + pipeline->stop_requested = true; + + /* Send stop event to the sp*/ + /* This needs improvement, stop on all the pipes available + * in the stream*/ + ia_css_pipeline_get_sp_thread_id(pipeline->pipe_num, &thread_id); + if (!sh_css_sp_is_running()) + { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_request_stop() leaving\n"); + /* queues are invalid */ + return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } + ia_css_bufq_enqueue_psys_event(IA_CSS_PSYS_SW_EVENT_STOP_STREAM, + (uint8_t)thread_id, + 0, + 0); + sh_css_sp_uninit_pipeline(pipeline->pipe_num); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_request_stop() leave: return_err=%d\n", + err); + return err; +} + +void ia_css_pipeline_clean(struct ia_css_pipeline *pipeline) +{ + struct ia_css_pipeline_stage *s; + + assert(pipeline != NULL); + IA_CSS_ENTER_PRIVATE("pipeline = %p", pipeline); + + if (pipeline == NULL) { + IA_CSS_ERROR("NULL input parameter"); + IA_CSS_LEAVE_PRIVATE("void"); + return; + } + s = pipeline->stages; + + while (s) { + struct ia_css_pipeline_stage *next = s->next; + pipeline_stage_destroy(s); + s = next; + } + pipeline_init_defaults(pipeline, pipeline->pipe_id, pipeline->pipe_num, pipeline->dvs_frame_delay); + + IA_CSS_LEAVE_PRIVATE("void"); +} + +/** @brief Add a stage to pipeline. + * + * @param pipeline Pointer to the pipeline to be added to. + * @param[in] stage_desc The description of the stage + * @param[out] stage The successor of the stage. + * @return IA_CSS_SUCCESS or error code upon error. + * + * Add a new stage to a non-NULL pipeline. + * The stage consists of an ISP binary or firmware and input and + * output arguments. +*/ +enum ia_css_err ia_css_pipeline_create_and_add_stage( + struct ia_css_pipeline *pipeline, + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_pipeline_stage **stage) +{ + struct ia_css_pipeline_stage *last, *new_stage = NULL; + enum ia_css_err err; + + /* other arguments can be NULL */ + assert(pipeline != NULL); + assert(stage_desc != NULL); + last = pipeline->stages; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_create_and_add_stage() enter:\n"); + if (!stage_desc->binary && !stage_desc->firmware + && (stage_desc->sp_func == IA_CSS_PIPELINE_NO_FUNC)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_create_and_add_stage() done:" + " Invalid args\n"); + + return IA_CSS_ERR_INTERNAL_ERROR; + } + + /* Find the last stage */ + while (last && last->next) + last = last->next; + + /* if in_frame is not set, we use the out_frame from the previous + * stage, if no previous stage, it's an error. + */ + if ((stage_desc->sp_func == IA_CSS_PIPELINE_NO_FUNC) + && (!stage_desc->in_frame) + && (!stage_desc->firmware) + && (!stage_desc->binary->online)) { + + /* Do this only for ISP stages*/ + if (last && last->args.out_frame[0]) + stage_desc->in_frame = last->args.out_frame[0]; + + if (!stage_desc->in_frame) + return IA_CSS_ERR_INTERNAL_ERROR; + } + + /* Create the new stage */ + err = pipeline_stage_create(stage_desc, &new_stage); + if (err != IA_CSS_SUCCESS) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_create_and_add_stage() done:" + " stage_create_failed\n"); + return err; + } + + if (last) + last->next = new_stage; + else + pipeline->stages = new_stage; + + /* Output the new stage */ + if (stage) + *stage = new_stage; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_create_and_add_stage() done:\n"); + return IA_CSS_SUCCESS; +} + +void ia_css_pipeline_finalize_stages(struct ia_css_pipeline *pipeline, + bool continuous) +{ + unsigned i = 0; + struct ia_css_pipeline_stage *stage; + + assert(pipeline != NULL); + for (stage = pipeline->stages; stage; stage = stage->next) { + stage->stage_num = i; + i++; + } + pipeline->num_stages = i; + + ia_css_pipeline_set_zoom_stage(pipeline); + ia_css_pipeline_configure_inout_port(pipeline, continuous); +} + +enum ia_css_err ia_css_pipeline_get_stage(struct ia_css_pipeline *pipeline, + int mode, + struct ia_css_pipeline_stage **stage) +{ + struct ia_css_pipeline_stage *s; + assert(pipeline != NULL); + assert(stage != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_get_stage() enter:\n"); + for (s = pipeline->stages; s; s = s->next) { + if (s->mode == mode) { + *stage = s; + return IA_CSS_SUCCESS; + } + } + return IA_CSS_ERR_INTERNAL_ERROR; +} + +enum ia_css_err ia_css_pipeline_get_stage_from_fw(struct ia_css_pipeline *pipeline, + uint32_t fw_handle, + struct ia_css_pipeline_stage **stage) +{ + struct ia_css_pipeline_stage *s; + assert(pipeline != NULL); + assert(stage != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,"%s() \n",__func__); + for (s = pipeline->stages; s; s = s->next) { + if ((s->firmware) && (s->firmware->handle == fw_handle)) { + *stage = s; + return IA_CSS_SUCCESS; + } + } + return IA_CSS_ERR_INTERNAL_ERROR; +} + +enum ia_css_err ia_css_pipeline_get_fw_from_stage(struct ia_css_pipeline *pipeline, + uint32_t stage_num, + uint32_t *fw_handle) +{ + struct ia_css_pipeline_stage *s; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE,"%s() \n",__func__); + if ((pipeline == NULL) || (fw_handle == NULL)) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + for (s = pipeline->stages; s; s = s->next) { + if((s->stage_num == stage_num) && (s->firmware)) { + *fw_handle = s->firmware->handle; + return IA_CSS_SUCCESS; + } + } + return IA_CSS_ERR_INTERNAL_ERROR; +} + +enum ia_css_err ia_css_pipeline_get_output_stage( + struct ia_css_pipeline *pipeline, + int mode, + struct ia_css_pipeline_stage **stage) +{ + struct ia_css_pipeline_stage *s; + assert(pipeline != NULL); + assert(stage != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_get_output_stage() enter:\n"); + + *stage = NULL; + /* First find acceleration firmware at end of pipe */ + for (s = pipeline->stages; s; s = s->next) { + if (s->firmware && s->mode == mode && + s->firmware->info.isp.sp.enable.output) + *stage = s; + } + if (*stage) + return IA_CSS_SUCCESS; + /* If no firmware, find binary in pipe */ + return ia_css_pipeline_get_stage(pipeline, mode, stage); +} + +bool ia_css_pipeline_has_stopped(struct ia_css_pipeline *pipeline) +{ + /* Android compilation files if made an local variable + stack size on android is limited to 2k and this structure + is around 2.5K, in place of static malloc can be done but + if this call is made too often it will lead to fragment memory + versus a fixed allocation */ + static struct sh_css_sp_group sp_group; + unsigned int thread_id; + const struct ia_css_fw_info *fw; + unsigned int HIVE_ADDR_sp_group; + + fw = &sh_css_sp_fw; + HIVE_ADDR_sp_group = fw->info.sp.group; + + ia_css_pipeline_get_sp_thread_id(pipeline->pipe_num, &thread_id); + sp_dmem_load(SP0_ID, + (unsigned int)sp_address_of(sp_group), + &sp_group, sizeof(struct sh_css_sp_group)); + return sp_group.pipe[thread_id].num_stages == 0; +} + +#if defined(USE_INPUT_SYSTEM_VERSION_2401) +struct sh_css_sp_pipeline_io_status *ia_css_pipeline_get_pipe_io_status(void) +{ + return(&sh_css_sp_group.pipe_io_status); +} +#endif + +bool ia_css_pipeline_is_mapped(unsigned int key) +{ + bool ret = false; + + IA_CSS_ENTER_PRIVATE("key = %d", key); + + if ((key >= IA_CSS_PIPELINE_NUM_MAX) || (key >= IA_CSS_PIPE_ID_NUM)) { + IA_CSS_ERROR("Invalid key!!"); + IA_CSS_LEAVE_PRIVATE("return = %d", false); + return false; + } + + ret = (bool)(pipeline_num_to_sp_thread_map[key] != (unsigned)PIPELINE_NUM_UNMAPPED); + + IA_CSS_LEAVE_PRIVATE("return = %d", ret); + return ret; +} + +/******************************************************* +*** Static functions +********************************************************/ + +/* Pipeline: + * To organize the several different binaries for each type of mode, + * we use a pipeline. A pipeline contains a number of stages, each with + * their own binary and frame pointers. + * When stages are added to a pipeline, output frames that are not passed + * from outside are automatically allocated. + * When input frames are not passed from outside, each stage will use the + * output frame of the previous stage as input (the full resolution output, + * not the viewfinder output). + * Pipelines must be cleaned and re-created when settings of the binaries + * change. + */ +static void pipeline_stage_destroy(struct ia_css_pipeline_stage *stage) +{ + unsigned int i; + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + if (stage->out_frame_allocated[i]) { + ia_css_frame_free(stage->args.out_frame[i]); + stage->args.out_frame[i] = NULL; + } + } + if (stage->vf_frame_allocated) { + ia_css_frame_free(stage->args.out_vf_frame); + stage->args.out_vf_frame = NULL; + } + sh_css_free(stage); +} + +static void pipeline_init_sp_thread_map(void) +{ + unsigned int i; + + for (i = 1; i < SH_CSS_MAX_SP_THREADS; i++) + pipeline_sp_thread_list[i] = PIPELINE_SP_THREAD_EMPTY_TOKEN; + + for (i = 0; i < IA_CSS_PIPELINE_NUM_MAX; i++) + pipeline_num_to_sp_thread_map[i] = PIPELINE_NUM_UNMAPPED; +} + +static void pipeline_map_num_to_sp_thread(unsigned int pipe_num) +{ + unsigned int i; + bool found_sp_thread = false; + + /* pipe is not mapped to any thread */ + assert(pipeline_num_to_sp_thread_map[pipe_num] + == (unsigned)PIPELINE_NUM_UNMAPPED); + + for (i = 0; i < SH_CSS_MAX_SP_THREADS; i++) { + if (pipeline_sp_thread_list[i] == + PIPELINE_SP_THREAD_EMPTY_TOKEN) { + pipeline_sp_thread_list[i] = + PIPELINE_SP_THREAD_RESERVED_TOKEN; + pipeline_num_to_sp_thread_map[pipe_num] = i; + found_sp_thread = true; + break; + } + } + + /* Make sure a mapping is found */ + /* I could do: + assert(i < SH_CSS_MAX_SP_THREADS); + + But the below is more descriptive. + */ + assert(found_sp_thread != false); +} + +static void pipeline_unmap_num_to_sp_thread(unsigned int pipe_num) +{ + unsigned int thread_id; + assert(pipeline_num_to_sp_thread_map[pipe_num] + != (unsigned)PIPELINE_NUM_UNMAPPED); + + thread_id = pipeline_num_to_sp_thread_map[pipe_num]; + pipeline_num_to_sp_thread_map[pipe_num] = PIPELINE_NUM_UNMAPPED; + pipeline_sp_thread_list[thread_id] = PIPELINE_SP_THREAD_EMPTY_TOKEN; +} + +static enum ia_css_err pipeline_stage_create( + struct ia_css_pipeline_stage_desc *stage_desc, + struct ia_css_pipeline_stage **new_stage) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_pipeline_stage *stage = NULL; + struct ia_css_binary *binary; + struct ia_css_frame *vf_frame; + struct ia_css_frame *out_frame[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + const struct ia_css_fw_info *firmware; + unsigned int i; + + /* Verify input parameters*/ + if (!(stage_desc->in_frame) && !(stage_desc->firmware) + && (stage_desc->binary) && !(stage_desc->binary->online)) { + err = IA_CSS_ERR_INTERNAL_ERROR; + goto ERR; + } + + binary = stage_desc->binary; + firmware = stage_desc->firmware; + vf_frame = stage_desc->vf_frame; + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + out_frame[i] = stage_desc->out_frame[i]; + } + + stage = sh_css_malloc(sizeof(*stage)); + if (stage == NULL) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + goto ERR; + } + memset(stage, 0, sizeof(*stage)); + + if (firmware) { + stage->binary = NULL; + stage->binary_info = + (struct ia_css_binary_info *)&firmware->info.isp; + } else { + stage->binary = binary; + if (binary) + stage->binary_info = + (struct ia_css_binary_info *)binary->info; + else + stage->binary_info = NULL; + } + + stage->firmware = firmware; + stage->sp_func = stage_desc->sp_func; + stage->max_input_width = stage_desc->max_input_width; + stage->mode = stage_desc->mode; + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + stage->out_frame_allocated[i] = false; + stage->vf_frame_allocated = false; + stage->next = NULL; + sh_css_binary_args_reset(&stage->args); + + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + if (!(out_frame[i]) && (binary) + && (binary->out_frame_info[i].res.width)) { + err = ia_css_frame_allocate_from_info(&out_frame[i], + &binary->out_frame_info[i]); + if (err != IA_CSS_SUCCESS) + goto ERR; + stage->out_frame_allocated[i] = true; + } + } + /* VF frame is not needed in case of need_pp + However, the capture binary needs a vf frame to write to. + */ + if (!vf_frame) { + if ((binary && binary->vf_frame_info.res.width) || + (firmware && firmware->info.isp.sp.enable.vf_veceven) + ) { + err = ia_css_frame_allocate_from_info(&vf_frame, + &binary->vf_frame_info); + if (err != IA_CSS_SUCCESS) + goto ERR; + stage->vf_frame_allocated = true; + } + } else if (vf_frame && binary && binary->vf_frame_info.res.width + && !firmware) { + /* only mark as allocated if buffer pointer available */ + if (vf_frame->data != mmgr_NULL) + stage->vf_frame_allocated = true; + } + + stage->args.in_frame = stage_desc->in_frame; + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + stage->args.out_frame[i] = out_frame[i]; + stage->args.out_vf_frame = vf_frame; + *new_stage = stage; + return err; +ERR: + if (stage != NULL) + pipeline_stage_destroy(stage); + return err; +} + +static void pipeline_init_defaults( + struct ia_css_pipeline *pipeline, + enum ia_css_pipe_id pipe_id, + unsigned int pipe_num, + unsigned int dvs_frame_delay) +{ + struct ia_css_frame init_frame = DEFAULT_FRAME; + unsigned int i; + + pipeline->pipe_id = pipe_id; + pipeline->stages = NULL; + pipeline->stop_requested = false; + pipeline->current_stage = NULL; + pipeline->in_frame = init_frame; + for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + pipeline->out_frame[i] = init_frame; + pipeline->vf_frame[i] = init_frame; + } + pipeline->num_execs = -1; + pipeline->acquire_isp_each_stage = true; + pipeline->pipe_num = (uint8_t)pipe_num; + pipeline->dvs_frame_delay = dvs_frame_delay; +} + +static void ia_css_pipeline_set_zoom_stage(struct ia_css_pipeline *pipeline) +{ + struct ia_css_pipeline_stage *stage = NULL; + enum ia_css_err err = IA_CSS_SUCCESS; + + assert(pipeline != NULL); + if (pipeline->pipe_id == IA_CSS_PIPE_ID_PREVIEW) { + /* in preview pipeline, vf_pp stage should do zoom */ + err = ia_css_pipeline_get_stage(pipeline, IA_CSS_BINARY_MODE_VF_PP, &stage); + if (err == IA_CSS_SUCCESS) + stage->enable_zoom = true; + } else if (pipeline->pipe_id == IA_CSS_PIPE_ID_CAPTURE) { + /* in capture pipeline, capture_pp stage should do zoom */ + err = ia_css_pipeline_get_stage(pipeline, IA_CSS_BINARY_MODE_CAPTURE_PP, &stage); + if (err == IA_CSS_SUCCESS) + stage->enable_zoom = true; + } else if (pipeline->pipe_id == IA_CSS_PIPE_ID_VIDEO) { + /* in video pipeline, video stage should do zoom */ + err = ia_css_pipeline_get_stage(pipeline, IA_CSS_BINARY_MODE_VIDEO, &stage); + if (err == IA_CSS_SUCCESS) + stage->enable_zoom = true; + } else if (pipeline->pipe_id == IA_CSS_PIPE_ID_YUVPP) { + /* in yuvpp pipeline, first yuv_scaler stage should do zoom */ + err = ia_css_pipeline_get_stage(pipeline, IA_CSS_BINARY_MODE_CAPTURE_PP, &stage); + if (err == IA_CSS_SUCCESS) + stage->enable_zoom = true; + } +} + +static void +ia_css_pipeline_configure_inout_port(struct ia_css_pipeline *me, bool continuous) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_pipeline_configure_inout_port() enter: pipe_id(%d) continuous(%d)\n", + me->pipe_id, continuous); + switch (me->pipe_id) { + case IA_CSS_PIPE_ID_PREVIEW: + case IA_CSS_PIPE_ID_VIDEO: + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_INPUT, + (uint8_t)(continuous ? SH_CSS_COPYSINK_TYPE : SH_CSS_HOST_TYPE), 1); + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_OUTPUT, + (uint8_t)SH_CSS_HOST_TYPE, 1); + break; + case IA_CSS_PIPE_ID_COPY: /*Copy pipe ports configured to "offline" mode*/ + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_INPUT, + (uint8_t)SH_CSS_HOST_TYPE, 1); + if (continuous) { + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_OUTPUT, + (uint8_t)SH_CSS_COPYSINK_TYPE, 1); + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_OUTPUT, + (uint8_t)SH_CSS_TAGGERSINK_TYPE, 1); + } else { + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_OUTPUT, + (uint8_t)SH_CSS_HOST_TYPE, 1); + } + break; + case IA_CSS_PIPE_ID_CAPTURE: + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_INPUT, + (uint8_t)(continuous ? SH_CSS_TAGGERSINK_TYPE : SH_CSS_HOST_TYPE), + 1); + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_OUTPUT, + (uint8_t)SH_CSS_HOST_TYPE, 1); + break; + case IA_CSS_PIPE_ID_YUVPP: + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_INPUT, + (uint8_t)(SH_CSS_HOST_TYPE), 1); + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_OUTPUT, + (uint8_t)SH_CSS_HOST_TYPE, 1); + break; + case IA_CSS_PIPE_ID_ACC: + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_INPUT, + (uint8_t)SH_CSS_HOST_TYPE, 1); + SH_CSS_PIPE_PORT_CONFIG_SET(me->inout_port_config, + (uint8_t)SH_CSS_PORT_OUTPUT, + (uint8_t)SH_CSS_HOST_TYPE, 1); + break; + default: + break; + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "ia_css_pipeline_configure_inout_port() leave: inout_port_config(%x)\n", + me->inout_port_config); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/interface/ia_css_queue.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/interface/ia_css_queue.h new file mode 100644 index 0000000000000000000000000000000000000000..e50a0f8137530bbbd60bb230c4e6a2b771cbe77c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/interface/ia_css_queue.h @@ -0,0 +1,192 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef __IA_CSS_QUEUE_H +#define __IA_CSS_QUEUE_H + +#include +#include + +#include "ia_css_queue_comm.h" +#include "../src/queue_access.h" + +/* Local Queue object descriptor */ +struct ia_css_queue_local { + ia_css_circbuf_desc_t *cb_desc; /*Circbuf desc for local queues*/ + ia_css_circbuf_elem_t *cb_elems; /*Circbuf elements*/ +}; +typedef struct ia_css_queue_local ia_css_queue_local_t; + +/* Handle for queue object*/ +typedef struct ia_css_queue ia_css_queue_t; + + +/***************************************************************************** + * Queue Public APIs + *****************************************************************************/ +/** @brief Initialize a local queue instance. + * + * @param[out] qhandle. Handle to queue instance for use with API + * @param[in] desc. Descriptor with queue properties filled-in + * @return 0 - Successful init of local queue instance. + * @return EINVAL - Invalid argument. + * + */ +extern int ia_css_queue_local_init( + ia_css_queue_t *qhandle, + ia_css_queue_local_t *desc); + +/** @brief Initialize a remote queue instance + * + * @param[out] qhandle. Handle to queue instance for use with API + * @param[in] desc. Descriptor with queue properties filled-in + * @return 0 - Successful init of remote queue instance. + * @return EINVAL - Invalid argument. + */ +extern int ia_css_queue_remote_init( + ia_css_queue_t *qhandle, + ia_css_queue_remote_t *desc); + +/** @brief Uninitialize a queue instance + * + * @param[in] qhandle. Handle to queue instance + * @return 0 - Successful uninit. + * + */ +extern int ia_css_queue_uninit( + ia_css_queue_t *qhandle); + +/** @brief Enqueue an item in the queue instance + * + * @param[in] qhandle. Handle to queue instance + * @param[in] item. Object to be enqueued. + * @return 0 - Successful enqueue. + * @return EINVAL - Invalid argument. + * @return ENOBUFS - Queue is full. + * + */ +extern int ia_css_queue_enqueue( + ia_css_queue_t *qhandle, + uint32_t item); + +/** @brief Dequeue an item from the queue instance + * + * @param[in] qhandle. Handle to queue instance + * @param[out] item. Object to be dequeued into this item. + + * @return 0 - Successful dequeue. + * @return EINVAL - Invalid argument. + * @return ENODATA - Queue is empty. + * + */ +extern int ia_css_queue_dequeue( + ia_css_queue_t *qhandle, + uint32_t *item); + +/** @brief Check if the queue is empty + * + * @param[in] qhandle. Handle to queue instance + * @param[in] is_empty True if empty, False if not. + * @return 0 - Successful access state. + * @return EINVAL - Invalid argument. + * @return ENOSYS - Function not implemented. + * + */ +extern int ia_css_queue_is_empty( + ia_css_queue_t *qhandle, + bool *is_empty); + +/** @brief Check if the queue is full + * + * @param[in] qhandle. Handle to queue instance + * @param[in] is_full True if Full, False if not. + * @return 0 - Successfully access state. + * @return EINVAL - Invalid argument. + * @return ENOSYS - Function not implemented. + * + */ +extern int ia_css_queue_is_full( + ia_css_queue_t *qhandle, + bool *is_full); + +/** @brief Get used space in the queue + * + * @param[in] qhandle. Handle to queue instance + * @param[in] size Number of available elements in the queue + * @return 0 - Successfully access state. + * @return EINVAL - Invalid argument. + * + */ +extern int ia_css_queue_get_used_space( + ia_css_queue_t *qhandle, + uint32_t *size); + +/** @brief Get free space in the queue + * + * @param[in] qhandle. Handle to queue instance + * @param[in] size Number of free elements in the queue + * @return 0 - Successfully access state. + * @return EINVAL - Invalid argument. + * + */ +extern int ia_css_queue_get_free_space( + ia_css_queue_t *qhandle, + uint32_t *size); + +/** @brief Peek at an element in the queue + * + * @param[in] qhandle. Handle to queue instance + * @param[in] offset Offset of element to peek, + * starting from head of queue + * @param[in] element Value of element returned + * @return 0 - Successfully access state. + * @return EINVAL - Invalid argument. + * + */ +extern int ia_css_queue_peek( + ia_css_queue_t *qhandle, + uint32_t offset, + uint32_t *element); + +/** @brief Get the usable size for the queue + * + * @param[in] qhandle. Handle to queue instance + * @param[out] size Size value to be returned here. + * @return 0 - Successful get size. + * @return EINVAL - Invalid argument. + * @return ENOSYS - Function not implemented. + * + */ +extern int ia_css_queue_get_size( + ia_css_queue_t *qhandle, + uint32_t *size); + +#endif /* __IA_CSS_QUEUE_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/interface/ia_css_queue_comm.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/interface/ia_css_queue_comm.h new file mode 100644 index 0000000000000000000000000000000000000000..4ebaeb0c18470f86079cb9b97a2cae6ea4f5290b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/interface/ia_css_queue_comm.h @@ -0,0 +1,69 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef __IA_CSS_QUEUE_COMM_H +#define __IA_CSS_QUEUE_COMM_H + +#include "type_support.h" +#include "ia_css_circbuf.h" +/***************************************************************************** + * Queue Public Data Structures + *****************************************************************************/ + +/* Queue location specifier */ +/* Avoiding enums to save space */ +#define IA_CSS_QUEUE_LOC_HOST 0 +#define IA_CSS_QUEUE_LOC_SP 1 +#define IA_CSS_QUEUE_LOC_ISP 2 + +/* Queue type specifier */ +/* Avoiding enums to save space */ +#define IA_CSS_QUEUE_TYPE_LOCAL 0 +#define IA_CSS_QUEUE_TYPE_REMOTE 1 + +/* for DDR Allocated queues, +allocate minimum these many elements. +DDR->SP' DMEM DMA transfer needs 32byte aligned address. +Since each element size is 4 bytes, 8 elements need to be +DMAed to access single element.*/ +#define IA_CSS_MIN_ELEM_COUNT 8 +#define IA_CSS_DMA_XFER_MASK (IA_CSS_MIN_ELEM_COUNT - 1) + +/* Remote Queue object descriptor */ +struct ia_css_queue_remote { + uint32_t cb_desc_addr; /*Circbuf desc address for remote queues*/ + uint32_t cb_elems_addr; /*Circbuf elements addr for remote queue*/ + uint8_t location; /* Cell location for queue */ + uint8_t proc_id; /* Processor id for queue access */ +}; +typedef struct ia_css_queue_remote ia_css_queue_remote_t; + + +#endif /* __IA_CSS_QUEUE_COMM_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/src/queue.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/src/queue.c new file mode 100644 index 0000000000000000000000000000000000000000..06667bdbb0eb0e5f96c2033df2cd7f886f31bf5e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/src/queue.c @@ -0,0 +1,412 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_queue.h" +#include +#include +#include +#include "queue_access.h" + +/***************************************************************************** + * Queue Public APIs + *****************************************************************************/ +int ia_css_queue_local_init( + ia_css_queue_t *qhandle, + ia_css_queue_local_t *desc) +{ + if (NULL == qhandle || NULL == desc + || NULL == desc->cb_elems || NULL == desc->cb_desc) { + /* Invalid parameters, return error*/ + return EINVAL; + } + + /* Mark the queue as Local */ + qhandle->type = IA_CSS_QUEUE_TYPE_LOCAL; + + /* Create a local circular buffer queue*/ + ia_css_circbuf_create(&qhandle->desc.cb_local, + desc->cb_elems, + desc->cb_desc); + + return 0; +} + +int ia_css_queue_remote_init( + ia_css_queue_t *qhandle, + ia_css_queue_remote_t *desc) +{ + if (NULL == qhandle || NULL == desc) { + /* Invalid parameters, return error*/ + return EINVAL; + } + + /* Mark the queue as remote*/ + qhandle->type = IA_CSS_QUEUE_TYPE_REMOTE; + + /* Copy over the local queue descriptor*/ + qhandle->location = desc->location; + qhandle->proc_id = desc->proc_id; + qhandle->desc.remote.cb_desc_addr = desc->cb_desc_addr; + qhandle->desc.remote.cb_elems_addr = desc->cb_elems_addr; + + /* If queue is remote, we let the local processor + * do its init, before using it. This is just to get us + * started, we can remove this restriction as we go ahead + */ + + return 0; +} + +int ia_css_queue_uninit( + ia_css_queue_t *qhandle) +{ + if (!qhandle) + return EINVAL; + + /* Load the required queue object */ + if (qhandle->type == IA_CSS_QUEUE_TYPE_LOCAL) { + /* Local queues are created. Destroy it*/ + ia_css_circbuf_destroy(&qhandle->desc.cb_local); + } + + return 0; +} + +int ia_css_queue_enqueue( + ia_css_queue_t *qhandle, + uint32_t item) +{ + int error = 0; + if (0 == qhandle) + return EINVAL; + + /* 1. Load the required queue object */ + if (qhandle->type == IA_CSS_QUEUE_TYPE_LOCAL) { + /* Directly de-ref the object and + * operate on the queue + */ + if (ia_css_circbuf_is_full(&qhandle->desc.cb_local)) { + /* Cannot push the element. Return*/ + return ENOBUFS; + } + + /* Push the element*/ + ia_css_circbuf_push(&qhandle->desc.cb_local, item); + } else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) { + ia_css_circbuf_desc_t cb_desc; + ia_css_circbuf_elem_t cb_elem; + uint32_t ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG; + + /* a. Load the queue cb_desc from remote */ + QUEUE_CB_DESC_INIT(&cb_desc); + error = ia_css_queue_load(qhandle, &cb_desc, ignore_desc_flags); + if (error != 0) + return error; + + /* b. Operate on the queue */ + if (ia_css_circbuf_desc_is_full(&cb_desc)) + return ENOBUFS; + + cb_elem.val = item; + + error = ia_css_queue_item_store(qhandle, cb_desc.end, &cb_elem); + if (error != 0) + return error; + + cb_desc.end = (cb_desc.end + 1) % cb_desc.size; + + /* c. Store the queue object */ + /* Set only fields requiring update with + * valid value. Avoids uncessary calls + * to load/store functions + */ + ignore_desc_flags = QUEUE_IGNORE_SIZE_START_STEP_FLAGS; + + error = ia_css_queue_store(qhandle, &cb_desc, ignore_desc_flags); + if (error != 0) + return error; + } + + return 0; +} + +int ia_css_queue_dequeue( + ia_css_queue_t *qhandle, + uint32_t *item) +{ + int error = 0; + if (qhandle == 0 || NULL == item) + return EINVAL; + + /* 1. Load the required queue object */ + if (qhandle->type == IA_CSS_QUEUE_TYPE_LOCAL) { + /* Directly de-ref the object and + * operate on the queue + */ + if (ia_css_circbuf_is_empty(&qhandle->desc.cb_local)) { + /* Nothing to pop. Return empty queue*/ + return ENODATA; + } + + *item = ia_css_circbuf_pop(&qhandle->desc.cb_local); + } else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) { + /* a. Load the queue from remote */ + ia_css_circbuf_desc_t cb_desc; + ia_css_circbuf_elem_t cb_elem; + uint32_t ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG; + + QUEUE_CB_DESC_INIT(&cb_desc); + + error = ia_css_queue_load(qhandle, &cb_desc, ignore_desc_flags); + if (error != 0) + return error; + + /* b. Operate on the queue */ + if (ia_css_circbuf_desc_is_empty(&cb_desc)) + return ENODATA; + + error = ia_css_queue_item_load(qhandle, cb_desc.start, &cb_elem); + if (error != 0) + return error; + + *item = cb_elem.val; + + cb_desc.start = OP_std_modadd(cb_desc.start, 1, cb_desc.size); + + /* c. Store the queue object */ + /* Set only fields requiring update with + * valid value. Avoids uncessary calls + * to load/store functions + */ + ignore_desc_flags = QUEUE_IGNORE_SIZE_END_STEP_FLAGS; + error = ia_css_queue_store(qhandle, &cb_desc, ignore_desc_flags); + if (error != 0) + return error; + } + return 0; +} + +int ia_css_queue_is_full( + ia_css_queue_t *qhandle, + bool *is_full) +{ + int error = 0; + if ((qhandle == NULL) || (is_full == NULL)) + return EINVAL; + + /* 1. Load the required queue object */ + if (qhandle->type == IA_CSS_QUEUE_TYPE_LOCAL) { + /* Directly de-ref the object and + * operate on the queue + */ + *is_full = ia_css_circbuf_is_full(&qhandle->desc.cb_local); + return 0; + } else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) { + /* a. Load the queue from remote */ + ia_css_circbuf_desc_t cb_desc; + uint32_t ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG; + QUEUE_CB_DESC_INIT(&cb_desc); + error = ia_css_queue_load(qhandle, &cb_desc, ignore_desc_flags); + if (error != 0) + return error; + + /* b. Operate on the queue */ + *is_full = ia_css_circbuf_desc_is_full(&cb_desc); + return 0; + } + + return EINVAL; +} + +int ia_css_queue_get_free_space( + ia_css_queue_t *qhandle, + uint32_t *size) +{ + int error = 0; + if ((qhandle == NULL) || (size == NULL)) + return EINVAL; + + /* 1. Load the required queue object */ + if (qhandle->type == IA_CSS_QUEUE_TYPE_LOCAL) { + /* Directly de-ref the object and + * operate on the queue + */ + *size = ia_css_circbuf_get_free_elems(&qhandle->desc.cb_local); + return 0; + } else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) { + /* a. Load the queue from remote */ + ia_css_circbuf_desc_t cb_desc; + uint32_t ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG; + QUEUE_CB_DESC_INIT(&cb_desc); + error = ia_css_queue_load(qhandle, &cb_desc, ignore_desc_flags); + if (error != 0) + return error; + + /* b. Operate on the queue */ + *size = ia_css_circbuf_desc_get_free_elems(&cb_desc); + return 0; + } + + return EINVAL; +} + +int ia_css_queue_get_used_space( + ia_css_queue_t *qhandle, + uint32_t *size) +{ + int error = 0; + if ((qhandle == NULL) || (size == NULL)) + return EINVAL; + + /* 1. Load the required queue object */ + if (qhandle->type == IA_CSS_QUEUE_TYPE_LOCAL) { + /* Directly de-ref the object and + * operate on the queue + */ + *size = ia_css_circbuf_get_num_elems(&qhandle->desc.cb_local); + return 0; + } else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) { + /* a. Load the queue from remote */ + ia_css_circbuf_desc_t cb_desc; + uint32_t ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG; + QUEUE_CB_DESC_INIT(&cb_desc); + error = ia_css_queue_load(qhandle, &cb_desc, ignore_desc_flags); + if (error != 0) + return error; + + /* b. Operate on the queue */ + *size = ia_css_circbuf_desc_get_num_elems(&cb_desc); + return 0; + } + + return EINVAL; +} + +int ia_css_queue_peek( + ia_css_queue_t *qhandle, + uint32_t offset, + uint32_t *element) +{ + uint32_t num_elems = 0; + int error = 0; + + if ((qhandle == NULL) || (element == NULL)) + return EINVAL; + + /* 1. Load the required queue object */ + if (qhandle->type == IA_CSS_QUEUE_TYPE_LOCAL) { + /* Directly de-ref the object and + * operate on the queue + */ + /* Check if offset is valid */ + num_elems = ia_css_circbuf_get_num_elems(&qhandle->desc.cb_local); + if (offset > num_elems) + return EINVAL; + + *element = ia_css_circbuf_peek_from_start(&qhandle->desc.cb_local, (int) offset); + return 0; + } else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) { + /* a. Load the queue from remote */ + ia_css_circbuf_desc_t cb_desc; + ia_css_circbuf_elem_t cb_elem; + uint32_t ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG; + + QUEUE_CB_DESC_INIT(&cb_desc); + + error = ia_css_queue_load(qhandle, &cb_desc, ignore_desc_flags); + if (error != 0) + return error; + + /* Check if offset is valid */ + num_elems = ia_css_circbuf_desc_get_num_elems(&cb_desc); + if (offset > num_elems) + return EINVAL; + + offset = OP_std_modadd(cb_desc.start, offset, cb_desc.size); + error = ia_css_queue_item_load(qhandle, (uint8_t)offset, &cb_elem); + if (error != 0) + return error; + + *element = cb_elem.val; + return 0; + } + + return EINVAL; +} + +int ia_css_queue_is_empty( + ia_css_queue_t *qhandle, + bool *is_empty) +{ + int error = 0; + if ((qhandle == NULL) || (is_empty == NULL)) + return EINVAL; + + /* 1. Load the required queue object */ + if (qhandle->type == IA_CSS_QUEUE_TYPE_LOCAL) { + /* Directly de-ref the object and + * operate on the queue + */ + *is_empty = ia_css_circbuf_is_empty(&qhandle->desc.cb_local); + return 0; + } else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) { + /* a. Load the queue from remote */ + ia_css_circbuf_desc_t cb_desc; + uint32_t ignore_desc_flags = QUEUE_IGNORE_STEP_FLAG; + + QUEUE_CB_DESC_INIT(&cb_desc); + error = ia_css_queue_load(qhandle, &cb_desc, ignore_desc_flags); + if (error != 0) + return error; + + /* b. Operate on the queue */ + *is_empty = ia_css_circbuf_desc_is_empty(&cb_desc); + return 0; + } + + return EINVAL; +} + +int ia_css_queue_get_size( + ia_css_queue_t *qhandle, + uint32_t *size) +{ + int error = 0; + if ((qhandle == 0) || (size == NULL)) + return EINVAL; + + /* 1. Load the required queue object */ + if (qhandle->type == IA_CSS_QUEUE_TYPE_LOCAL) { + /* Directly de-ref the object and + * operate on the queue + */ + /* Return maximum usable capacity */ + *size = ia_css_circbuf_get_size(&qhandle->desc.cb_local); + } else if (qhandle->type == IA_CSS_QUEUE_TYPE_REMOTE) { + /* a. Load the queue from remote */ + ia_css_circbuf_desc_t cb_desc; + uint32_t ignore_desc_flags = QUEUE_IGNORE_START_END_STEP_FLAGS; + + QUEUE_CB_DESC_INIT(&cb_desc); + + error = ia_css_queue_load(qhandle, &cb_desc, ignore_desc_flags); + if (error != 0) + return error; + + /* Return maximum usable capacity */ + *size = cb_desc.size; + } + + return 0; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/src/queue_access.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/src/queue_access.c new file mode 100644 index 0000000000000000000000000000000000000000..946d4f2d21080099daa2aa76589cda6a8ba0cd37 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/src/queue_access.c @@ -0,0 +1,192 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#include "type_support.h" +#include "queue_access.h" +#include "ia_css_circbuf.h" +#include "sp.h" +#include "memory_access.h" +#include "assert_support.h" + +int ia_css_queue_load( + struct ia_css_queue *rdesc, + ia_css_circbuf_desc_t *cb_desc, + uint32_t ignore_desc_flags) +{ + if (rdesc == NULL || cb_desc == NULL) + return EINVAL; + + if (rdesc->location == IA_CSS_QUEUE_LOC_SP) { + assert(ignore_desc_flags <= QUEUE_IGNORE_DESC_FLAGS_MAX); + + if (0 == (ignore_desc_flags & QUEUE_IGNORE_SIZE_FLAG)) { + cb_desc->size = sp_dmem_load_uint8(rdesc->proc_id, + rdesc->desc.remote.cb_desc_addr + + offsetof(ia_css_circbuf_desc_t, size)); + + if (0 == cb_desc->size) { + /* Adding back the workaround which was removed + while refactoring queues. When reading size + through sp_dmem_load_*, sometimes we get back + the value as zero. This causes division by 0 + exception as the size is used in a modular + division operation. */ + return EDOM; + } + } + + if (0 == (ignore_desc_flags & QUEUE_IGNORE_START_FLAG)) + cb_desc->start = sp_dmem_load_uint8(rdesc->proc_id, + rdesc->desc.remote.cb_desc_addr + + offsetof(ia_css_circbuf_desc_t, start)); + + if (0 == (ignore_desc_flags & QUEUE_IGNORE_END_FLAG)) + cb_desc->end = sp_dmem_load_uint8(rdesc->proc_id, + rdesc->desc.remote.cb_desc_addr + + offsetof(ia_css_circbuf_desc_t, end)); + + if (0 == (ignore_desc_flags & QUEUE_IGNORE_STEP_FLAG)) + cb_desc->step = sp_dmem_load_uint8(rdesc->proc_id, + rdesc->desc.remote.cb_desc_addr + + offsetof(ia_css_circbuf_desc_t, step)); + + } else if (rdesc->location == IA_CSS_QUEUE_LOC_HOST) { + /* doing DMA transfer of entire structure */ + mmgr_load(rdesc->desc.remote.cb_desc_addr, + (void *)cb_desc, + sizeof(ia_css_circbuf_desc_t)); + } else if (rdesc->location == IA_CSS_QUEUE_LOC_ISP) { + /* Not supported yet */ + return ENOTSUP; + } + + return 0; +} + +int ia_css_queue_store( + struct ia_css_queue *rdesc, + ia_css_circbuf_desc_t *cb_desc, + uint32_t ignore_desc_flags) +{ + if (rdesc == NULL || cb_desc == NULL) + return EINVAL; + + if (rdesc->location == IA_CSS_QUEUE_LOC_SP) { + assert(ignore_desc_flags <= QUEUE_IGNORE_DESC_FLAGS_MAX); + + if (0 == (ignore_desc_flags & QUEUE_IGNORE_SIZE_FLAG)) + sp_dmem_store_uint8(rdesc->proc_id, + rdesc->desc.remote.cb_desc_addr + + offsetof(ia_css_circbuf_desc_t, size), + cb_desc->size); + + if (0 == (ignore_desc_flags & QUEUE_IGNORE_START_FLAG)) + sp_dmem_store_uint8(rdesc->proc_id, + rdesc->desc.remote.cb_desc_addr + + offsetof(ia_css_circbuf_desc_t, start), + cb_desc->start); + + if (0 == (ignore_desc_flags & QUEUE_IGNORE_END_FLAG)) + sp_dmem_store_uint8(rdesc->proc_id, + rdesc->desc.remote.cb_desc_addr + + offsetof(ia_css_circbuf_desc_t, end), + cb_desc->end); + + if (0 == (ignore_desc_flags & QUEUE_IGNORE_STEP_FLAG)) + sp_dmem_store_uint8(rdesc->proc_id, + rdesc->desc.remote.cb_desc_addr + + offsetof(ia_css_circbuf_desc_t, step), + cb_desc->step); + } else if (rdesc->location == IA_CSS_QUEUE_LOC_HOST) { + /* doing DMA transfer of entire structure */ + mmgr_store(rdesc->desc.remote.cb_desc_addr, + (void *)cb_desc, + sizeof(ia_css_circbuf_desc_t)); + } else if (rdesc->location == IA_CSS_QUEUE_LOC_ISP) { + /* Not supported yet */ + return ENOTSUP; + } + + return 0; +} + +int ia_css_queue_item_load( + struct ia_css_queue *rdesc, + uint8_t position, + ia_css_circbuf_elem_t *item) +{ + if (rdesc == NULL || item == NULL) + return EINVAL; + + if (rdesc->location == IA_CSS_QUEUE_LOC_SP) { + sp_dmem_load(rdesc->proc_id, + rdesc->desc.remote.cb_elems_addr + + position * sizeof(ia_css_circbuf_elem_t), + item, + sizeof(ia_css_circbuf_elem_t)); + } else if (rdesc->location == IA_CSS_QUEUE_LOC_HOST) { + mmgr_load(rdesc->desc.remote.cb_elems_addr + + position * sizeof(ia_css_circbuf_elem_t), + (void *)item, + sizeof(ia_css_circbuf_elem_t)); + } else if (rdesc->location == IA_CSS_QUEUE_LOC_ISP) { + /* Not supported yet */ + return ENOTSUP; + } + + return 0; +} + +int ia_css_queue_item_store( + struct ia_css_queue *rdesc, + uint8_t position, + ia_css_circbuf_elem_t *item) +{ + if (rdesc == NULL || item == NULL) + return EINVAL; + + if (rdesc->location == IA_CSS_QUEUE_LOC_SP) { + sp_dmem_store(rdesc->proc_id, + rdesc->desc.remote.cb_elems_addr + + position * sizeof(ia_css_circbuf_elem_t), + item, + sizeof(ia_css_circbuf_elem_t)); + } else if (rdesc->location == IA_CSS_QUEUE_LOC_HOST) { + mmgr_store(rdesc->desc.remote.cb_elems_addr + + position * sizeof(ia_css_circbuf_elem_t), + (void *)item, + sizeof(ia_css_circbuf_elem_t)); + } else if (rdesc->location == IA_CSS_QUEUE_LOC_ISP) { + /* Not supported yet */ + return ENOTSUP; + } + + return 0; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/src/queue_access.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/src/queue_access.h new file mode 100644 index 0000000000000000000000000000000000000000..4775513f54cf19f516cf39f512d5f19b42effd95 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/queue/src/queue_access.h @@ -0,0 +1,101 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef __QUEUE_ACCESS_H +#define __QUEUE_ACCESS_H + +#include +#include +#include +#include + +#define QUEUE_IGNORE_START_FLAG 0x0001 +#define QUEUE_IGNORE_END_FLAG 0x0002 +#define QUEUE_IGNORE_SIZE_FLAG 0x0004 +#define QUEUE_IGNORE_STEP_FLAG 0x0008 +#define QUEUE_IGNORE_DESC_FLAGS_MAX 0x000f + +#define QUEUE_IGNORE_SIZE_START_STEP_FLAGS \ + (QUEUE_IGNORE_SIZE_FLAG | \ + QUEUE_IGNORE_START_FLAG | \ + QUEUE_IGNORE_STEP_FLAG) + +#define QUEUE_IGNORE_SIZE_END_STEP_FLAGS \ + (QUEUE_IGNORE_SIZE_FLAG | \ + QUEUE_IGNORE_END_FLAG | \ + QUEUE_IGNORE_STEP_FLAG) + +#define QUEUE_IGNORE_START_END_STEP_FLAGS \ + (QUEUE_IGNORE_START_FLAG | \ + QUEUE_IGNORE_END_FLAG | \ + QUEUE_IGNORE_STEP_FLAG) + +#define QUEUE_CB_DESC_INIT(cb_desc) \ + do { \ + (cb_desc)->size = 0; \ + (cb_desc)->step = 0; \ + (cb_desc)->start = 0; \ + (cb_desc)->end = 0; \ + } while(0) + +struct ia_css_queue { + uint8_t type; /* Specify remote/local type of access */ + uint8_t location; /* Cell location for queue */ + uint8_t proc_id; /* Processor id for queue access */ + union { + ia_css_circbuf_t cb_local; + struct { + uint32_t cb_desc_addr; /*Circbuf desc address for remote queues*/ + uint32_t cb_elems_addr; /*Circbuf elements addr for remote queue*/ + } remote; + } desc; +}; + +extern int ia_css_queue_load( + struct ia_css_queue *rdesc, + ia_css_circbuf_desc_t *cb_desc, + uint32_t ignore_desc_flags); + +extern int ia_css_queue_store( + struct ia_css_queue *rdesc, + ia_css_circbuf_desc_t *cb_desc, + uint32_t ignore_desc_flags); + +extern int ia_css_queue_item_load( + struct ia_css_queue *rdesc, + uint8_t position, + ia_css_circbuf_elem_t *item); + +extern int ia_css_queue_item_store( + struct ia_css_queue *rdesc, + uint8_t position, + ia_css_circbuf_elem_t *item); + +#endif /* __QUEUE_ACCESS_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/interface/ia_css_rmgr.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/interface/ia_css_rmgr.h new file mode 100644 index 0000000000000000000000000000000000000000..a0bb9f663ce6aa3636c5122644fa90a30126cc73 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/interface/ia_css_rmgr.h @@ -0,0 +1,89 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef _IA_CSS_RMGR_H +#define _IA_CSS_RMGR_H + +#include "storage_class.h" +#include + +#ifndef __INLINE_RMGR__ +#define STORAGE_CLASS_RMGR_H STORAGE_CLASS_EXTERN +#define STORAGE_CLASS_RMGR_C +#else /* __INLINE_RMGR__ */ +#define STORAGE_CLASS_RMGR_H STORAGE_CLASS_INLINE +#define STORAGE_CLASS_RMGR_C STORAGE_CLASS_INLINE +#endif /* __INLINE_RMGR__ */ + +/** + * @brief Initialize resource manager (host/common) + */ +enum ia_css_err ia_css_rmgr_init(void); + +/** + * @brief Uninitialize resource manager (host/common) + */ +void ia_css_rmgr_uninit(void); + +/***************************************************************** + * Interface definition - resource type (host/common) + ***************************************************************** + * + * struct ia_css_rmgr__pool; + * struct ia_css_rmgr__handle; + * + * STORAGE_CLASS_RMGR_H void ia_css_rmgr_init_( + * struct ia_css_rmgr__pool *pool); + * + * STORAGE_CLASS_RMGR_H void ia_css_rmgr_uninit_( + * struct ia_css_rmgr__pool *pool); + * + * STORAGE_CLASS_RMGR_H void ia_css_rmgr_acq_( + * struct ia_css_rmgr__pool *pool, + * struct ia_css_rmgr__handle **handle); + * + * STORAGE_CLASS_RMGR_H void ia_css_rmgr_rel_( + * struct ia_css_rmgr__pool *pool, + * struct ia_css_rmgr__handle **handle); + * + ***************************************************************** + * Interface definition - refcounting (host/common) + ***************************************************************** + * + * void ia_css_rmgr_refcount_retain_( + * struct ia_css_rmgr__handle **handle); + * + * void ia_css_rmgr_refcount_release_( + * struct ia_css_rmgr__handle **handle); + */ + +#include "ia_css_rmgr_vbuf.h" + +#endif /* _IA_CSS_RMGR_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/interface/ia_css_rmgr_vbuf.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/interface/ia_css_rmgr_vbuf.h new file mode 100644 index 0000000000000000000000000000000000000000..90ac27cf02cffb6c49584d15e85112001a78ebe0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/interface/ia_css_rmgr_vbuf.h @@ -0,0 +1,115 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef _IA_CSS_RMGR_VBUF_H +#define _IA_CSS_RMGR_VBUF_H + +#include "ia_css_rmgr.h" +#include +#include + +/** + * @brief Data structure for the resource handle (host, vbuf) + */ +struct ia_css_rmgr_vbuf_handle { + hrt_vaddress vptr; + uint8_t count; + uint32_t size; +}; + +/** + * @brief Data structure for the resource pool (host, vbuf) + */ +struct ia_css_rmgr_vbuf_pool { + uint8_t copy_on_write; + uint8_t recycle; + uint32_t size; + uint32_t index; + struct ia_css_rmgr_vbuf_handle **handles; +}; + +/** + * @brief VBUF resource pools + */ +extern struct ia_css_rmgr_vbuf_pool *vbuf_ref; +extern struct ia_css_rmgr_vbuf_pool *vbuf_write; +extern struct ia_css_rmgr_vbuf_pool *hmm_buffer_pool; + +/** + * @brief Initialize the resource pool (host, vbuf) + * + * @param pool The pointer to the pool + */ +STORAGE_CLASS_RMGR_H enum ia_css_err ia_css_rmgr_init_vbuf( + struct ia_css_rmgr_vbuf_pool *pool); + +/** + * @brief Uninitialize the resource pool (host, vbuf) + * + * @param pool The pointer to the pool + */ +STORAGE_CLASS_RMGR_H void ia_css_rmgr_uninit_vbuf( + struct ia_css_rmgr_vbuf_pool *pool); + +/** + * @brief Acquire a handle from the pool (host, vbuf) + * + * @param pool The pointer to the pool + * @param handle The pointer to the handle + */ +STORAGE_CLASS_RMGR_H void ia_css_rmgr_acq_vbuf( + struct ia_css_rmgr_vbuf_pool *pool, + struct ia_css_rmgr_vbuf_handle **handle); + +/** + * @brief Release a handle to the pool (host, vbuf) + * + * @param pool The pointer to the pool + * @param handle The pointer to the handle + */ +STORAGE_CLASS_RMGR_H void ia_css_rmgr_rel_vbuf( + struct ia_css_rmgr_vbuf_pool *pool, + struct ia_css_rmgr_vbuf_handle **handle); + +/** + * @brief Retain the reference count for a handle (host, vbuf) + * + * @param handle The pointer to the handle + */ +void ia_css_rmgr_refcount_retain_vbuf(struct ia_css_rmgr_vbuf_handle **handle); + +/** + * @brief Release the reference count for a handle (host, vbuf) + * + * @param handle The pointer to the handle + */ +void ia_css_rmgr_refcount_release_vbuf(struct ia_css_rmgr_vbuf_handle **handle); + +#endif /* _IA_CSS_RMGR_VBUF_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/src/rmgr.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/src/rmgr.c new file mode 100644 index 0000000000000000000000000000000000000000..efa9c140484f6a2dc9a4f9b9fc1f4a811cfcbf33 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/src/rmgr.c @@ -0,0 +1,55 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#include "ia_css_rmgr.h" + +enum ia_css_err ia_css_rmgr_init(void) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + err = ia_css_rmgr_init_vbuf(vbuf_ref); + if (err == IA_CSS_SUCCESS) + err = ia_css_rmgr_init_vbuf(vbuf_write); + if (err == IA_CSS_SUCCESS) + err = ia_css_rmgr_init_vbuf(hmm_buffer_pool); + if (err != IA_CSS_SUCCESS) + ia_css_rmgr_uninit(); + return err; +} + +/** + * @brief Uninitialize resource pool (host) + */ +void ia_css_rmgr_uninit(void) +{ + ia_css_rmgr_uninit_vbuf(hmm_buffer_pool); + ia_css_rmgr_uninit_vbuf(vbuf_write); + ia_css_rmgr_uninit_vbuf(vbuf_ref); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/src/rmgr_vbuf.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/src/rmgr_vbuf.c new file mode 100644 index 0000000000000000000000000000000000000000..dc30e7caa9400640339e9f38725e44b8f90fb0d4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/rmgr/src/rmgr_vbuf.c @@ -0,0 +1,360 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#include "ia_css_rmgr.h" + +#include +#include +#include /* memset */ +#include /* mmmgr_malloc, mmmgr_free */ +#include + +/** + * @brief VBUF resource handles + */ +#define NUM_HANDLES 1000 +struct ia_css_rmgr_vbuf_handle handle_table[NUM_HANDLES]; + +/** + * @brief VBUF resource pool - refpool + */ +struct ia_css_rmgr_vbuf_pool refpool = { + false, /* copy_on_write */ + false, /* recycle */ + 0, /* size */ + 0, /* index */ + NULL, /* handles */ +}; + +/** + * @brief VBUF resource pool - writepool + */ +struct ia_css_rmgr_vbuf_pool writepool = { + true, /* copy_on_write */ + false, /* recycle */ + 0, /* size */ + 0, /* index */ + NULL, /* handles */ +}; + +/** + * @brief VBUF resource pool - hmmbufferpool + */ +struct ia_css_rmgr_vbuf_pool hmmbufferpool = { + true, /* copy_on_write */ + true, /* recycle */ + 32, /* size */ + 0, /* index */ + NULL, /* handles */ +}; + +struct ia_css_rmgr_vbuf_pool *vbuf_ref = &refpool; +struct ia_css_rmgr_vbuf_pool *vbuf_write = &writepool; +struct ia_css_rmgr_vbuf_pool *hmm_buffer_pool = &hmmbufferpool; + +/** + * @brief Initialize the reference count (host, vbuf) + */ +static void rmgr_refcount_init_vbuf(void) +{ + /* initialize the refcount table */ + memset(&handle_table, 0, sizeof(handle_table)); +} + +/** + * @brief Retain the reference count for a handle (host, vbuf) + * + * @param handle The pointer to the handle + */ +void ia_css_rmgr_refcount_retain_vbuf(struct ia_css_rmgr_vbuf_handle **handle) +{ + int i; + struct ia_css_rmgr_vbuf_handle *h; + if ((handle == NULL) || (*handle == NULL)) { + IA_CSS_LOG("Invalid inputs"); + return; + } + /* new vbuf to count on */ + if ((*handle)->count == 0) { + h = *handle; + *handle = NULL; + for (i = 0; i < NUM_HANDLES; i++) { + if (handle_table[i].count == 0) { + *handle = &handle_table[i]; + break; + } + } + /* if the loop dus not break and *handle == NULL + this is an error handle and report it. + */ + if (*handle == NULL) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "ia_css_i_host_refcount_retain_vbuf() failed to find empty slot!\n"); + return; + } + (*handle)->vptr = h->vptr; + (*handle)->size = h->size; + } + (*handle)->count++; +} + +/** + * @brief Release the reference count for a handle (host, vbuf) + * + * @param handle The pointer to the handle + */ +void ia_css_rmgr_refcount_release_vbuf(struct ia_css_rmgr_vbuf_handle **handle) +{ + if ((handle == NULL) || ((*handle) == NULL) || (((*handle)->count) == 0)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "ia_css_rmgr_refcount_release_vbuf() invalid arguments!\n"); + return; + } + /* decrease reference count */ + (*handle)->count--; + /* remove from admin */ + if ((*handle)->count == 0) { + (*handle)->vptr = 0x0; + (*handle)->size = 0; + *handle = NULL; + } +} + +/** + * @brief Initialize the resource pool (host, vbuf) + * + * @param pool The pointer to the pool + */ +enum ia_css_err ia_css_rmgr_init_vbuf(struct ia_css_rmgr_vbuf_pool *pool) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + size_t bytes_needed; + rmgr_refcount_init_vbuf(); + assert(pool != NULL); + if (pool == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + /* initialize the recycle pool if used */ + if (pool->recycle && pool->size) { + /* allocate memory for storing the handles */ + bytes_needed = + sizeof(void *) * + pool->size; + pool->handles = sh_css_malloc(bytes_needed); + if (pool->handles != NULL) + memset(pool->handles, 0, bytes_needed); + else + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + } else { + /* just in case, set the size to 0 */ + pool->size = 0; + pool->handles = NULL; + } + return err; +} + +/** + * @brief Uninitialize the resource pool (host, vbuf) + * + * @param pool The pointer to the pool + */ +void ia_css_rmgr_uninit_vbuf(struct ia_css_rmgr_vbuf_pool *pool) +{ + uint32_t i; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_rmgr_uninit_vbuf()\n"); + if (pool == NULL) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, "ia_css_rmgr_uninit_vbuf(): NULL argument\n"); + return; + } + if (pool->handles != NULL) { + /* free the hmm buffers */ + for (i = 0; i < pool->size; i++) { + if (pool->handles[i] != NULL) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + " freeing/releasing %x (count=%d)\n", + pool->handles[i]->vptr, + pool->handles[i]->count); + /* free memory */ + mmgr_free(pool->handles[i]->vptr); + /* remove from refcount admin */ + ia_css_rmgr_refcount_release_vbuf( + &pool->handles[i]); + } + } + /* now free the pool handles list */ + sh_css_free(pool->handles); + pool->handles = NULL; + } +} + +/** + * @brief Push a handle to the pool + * + * @param pool The pointer to the pool + * @param handle The pointer to the handle + */ +static +void rmgr_push_handle(struct ia_css_rmgr_vbuf_pool *pool, + struct ia_css_rmgr_vbuf_handle **handle) +{ + uint32_t i; + bool succes = false; + assert(pool != NULL); + assert(pool->recycle); + assert(pool->handles != NULL); + assert(handle != NULL); + for (i = 0; i < pool->size; i++) { + if (pool->handles[i] == NULL) { + ia_css_rmgr_refcount_retain_vbuf(handle); + pool->handles[i] = *handle; + succes = true; + break; + } + } + assert(succes); +} + +/** + * @brief Pop a handle from the pool + * + * @param pool The pointer to the pool + * @param handle The pointer to the handle + */ +static +void rmgr_pop_handle(struct ia_css_rmgr_vbuf_pool *pool, + struct ia_css_rmgr_vbuf_handle **handle) +{ + uint32_t i; + bool succes = false; + assert(pool != NULL); + assert(pool->recycle); + assert(pool->handles != NULL); + assert(handle != NULL); + assert(*handle != NULL); + for (i = 0; i < pool->size; i++) { + if ((pool->handles[i] != NULL) && + (pool->handles[i]->size == (*handle)->size)) { + *handle = pool->handles[i]; + pool->handles[i] = NULL; + /* dont release, we are returning it... + ia_css_rmgr_refcount_release_vbuf(handle); */ + succes = true; + break; + } + } +} + +/** + * @brief Acquire a handle from the pool (host, vbuf) + * + * @param pool The pointer to the pool + * @param handle The pointer to the handle + */ +void ia_css_rmgr_acq_vbuf(struct ia_css_rmgr_vbuf_pool *pool, + struct ia_css_rmgr_vbuf_handle **handle) +{ +#ifdef __KLOCWORK__ + /* KW sees the *handle = h; assignment about 20 lines down + and thinks that we are assigning a local to a global. + What it does not see is that in ia_css_i_host_rmgr_pop_handle + a new value is assigned to handle. + So this is a false positive KW issue. + To fix that we make the struct static for KW so it will + think that h remains alive; we do not want this in our + production code though as it breaks reentrancy of the code + */ + + static struct ia_css_rmgr_vbuf_handle h; +#else /* __KLOCWORK__ */ + struct ia_css_rmgr_vbuf_handle h; +#endif /* __KLOCWORK__ */ + + if ((pool == NULL) || (handle == NULL) || (*handle == NULL)) { + IA_CSS_LOG("Invalid inputs"); + return; + } + + if (pool->copy_on_write) { + /* only one reference, reuse (no new retain) */ + if ((*handle)->count == 1) + return; + /* more than one reference, release current buffer */ + if ((*handle)->count > 1) { + /* store current values */ + h.vptr = 0x0; + h.size = (*handle)->size; + /* release ref to current buffer */ + ia_css_rmgr_refcount_release_vbuf(handle); + *handle = &h; + } + /* get new buffer for needed size */ + if ((*handle)->vptr == 0x0) { + if (pool->recycle) { + /* try and pop from pool */ + rmgr_pop_handle(pool, handle); + } + if ((*handle)->vptr == 0x0) { + /* we need to allocate */ + (*handle)->vptr = mmgr_malloc((*handle)->size); + } else { + /* we popped a buffer */ + return; + } + } + } + /* Note that handle will change to an internally maintained one */ + ia_css_rmgr_refcount_retain_vbuf(handle); +} + +/** + * @brief Release a handle to the pool (host, vbuf) + * + * @param pool The pointer to the pool + * @param handle The pointer to the handle + */ +void ia_css_rmgr_rel_vbuf(struct ia_css_rmgr_vbuf_pool *pool, + struct ia_css_rmgr_vbuf_handle **handle) +{ + if ((pool == NULL) || (handle == NULL) || (*handle == NULL)) { + IA_CSS_LOG("Invalid inputs"); + return; + } + /* release the handle */ + if ((*handle)->count == 1) { + if (!pool->recycle) { + /* non recycling pool, free mem */ + mmgr_free((*handle)->vptr); + } else { + /* recycle to pool */ + rmgr_push_handle(pool, handle); + } + } + ia_css_rmgr_refcount_release_vbuf(handle); + *handle = NULL; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/spctrl/interface/ia_css_spctrl.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/spctrl/interface/ia_css_spctrl.h new file mode 100644 index 0000000000000000000000000000000000000000..27e9eb1e2102b3f29bd4b8403587c5c9f10cf9d2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/spctrl/interface/ia_css_spctrl.h @@ -0,0 +1,87 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef __IA_CSS_SPCTRL_H__ +#define __IA_CSS_SPCTRL_H__ + +#include +#include +#include "ia_css_spctrl_comm.h" + + +typedef struct { + uint32_t ddr_data_offset; /**< posistion of data in DDR */ + uint32_t dmem_data_addr; /**< data segment address in dmem */ + uint32_t dmem_bss_addr; /**< bss segment address in dmem */ + uint32_t data_size; /**< data segment size */ + uint32_t bss_size; /**< bss segment size */ + uint32_t spctrl_config_dmem_addr; /** + +/* state of SP */ +typedef enum { + IA_CSS_SP_SW_TERMINATED = 0, + IA_CSS_SP_SW_INITIALIZED, + IA_CSS_SP_SW_CONNECTED, + IA_CSS_SP_SW_RUNNING +} ia_css_spctrl_sp_sw_state; + +/** Structure to encapsulate required arguments for + * initialization of SP DMEM using the SP itself + */ +struct ia_css_sp_init_dmem_cfg { + ia_css_ptr ddr_data_addr; /**< data segment address in ddr */ + uint32_t dmem_data_addr; /**< data segment address in dmem */ + uint32_t dmem_bss_addr; /**< bss segment address in dmem */ + uint32_t data_size; /**< data segment size */ + uint32_t bss_size; /**< bss segment size */ + sp_ID_t sp_id; /** +#endif + +#include "memory_access.h" +#include "assert_support.h" +#include "ia_css_spctrl.h" +#include "ia_css_debug.h" + +typedef struct { + struct ia_css_sp_init_dmem_cfg dmem_config; + uint32_t spctrl_config_dmem_addr; /** location of dmem_cfg in SP dmem */ + uint32_t spctrl_state_dmem_addr; + unsigned int sp_entry; /* entry function ptr on SP */ + hrt_vaddress code_addr; /* sp firmware location in host mem-DDR*/ + uint32_t code_size; + char *program_name; /* used in case of PLATFORM_SIM */ +} spctrl_context_info; + +static spctrl_context_info spctrl_cofig_info[N_SP_ID]; +static bool spctrl_loaded[N_SP_ID] = {0}; + +/* Load firmware */ +enum ia_css_err ia_css_spctrl_load_fw(sp_ID_t sp_id, + ia_css_spctrl_cfg *spctrl_cfg) +{ + hrt_vaddress code_addr = mmgr_NULL; + struct ia_css_sp_init_dmem_cfg *init_dmem_cfg; + + if ((sp_id >= N_SP_ID) || (spctrl_cfg == 0)) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + spctrl_cofig_info[sp_id].code_addr = mmgr_NULL; + +#if defined(C_RUN) || defined(HRT_UNSCHED) + (void)init_dmem_cfg; + code_addr = mmgr_malloc(1); + if (code_addr == mmgr_NULL) + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; +#else + init_dmem_cfg = &spctrl_cofig_info[sp_id].dmem_config; + init_dmem_cfg->dmem_data_addr = spctrl_cfg->dmem_data_addr; + init_dmem_cfg->dmem_bss_addr = spctrl_cfg->dmem_bss_addr; + init_dmem_cfg->data_size = spctrl_cfg->data_size; + init_dmem_cfg->bss_size = spctrl_cfg->bss_size; + init_dmem_cfg->sp_id = sp_id; + + spctrl_cofig_info[sp_id].spctrl_config_dmem_addr = spctrl_cfg->spctrl_config_dmem_addr; + spctrl_cofig_info[sp_id].spctrl_state_dmem_addr = spctrl_cfg->spctrl_state_dmem_addr; + + /* store code (text + icache) and data to DDR + * + * Data used to be stored separately, because of access alignment constraints, + * fix the FW generation instead + */ + code_addr = mmgr_malloc(spctrl_cfg->code_size); + if (code_addr == mmgr_NULL) + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + mmgr_store(code_addr, spctrl_cfg->code, spctrl_cfg->code_size); + + if (sizeof(hrt_vaddress) > sizeof(hrt_data)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "size of hrt_vaddress can not be greater than hrt_data\n"); + mmgr_free(code_addr); + code_addr = mmgr_NULL; + return IA_CSS_ERR_INTERNAL_ERROR; + } + + init_dmem_cfg->ddr_data_addr = code_addr + spctrl_cfg->ddr_data_offset; + if ((init_dmem_cfg->ddr_data_addr % HIVE_ISP_DDR_WORD_BYTES) != 0) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "DDR address pointer is not properly aligned for DMA transfer\n"); + mmgr_free(code_addr); + code_addr = mmgr_NULL; + return IA_CSS_ERR_INTERNAL_ERROR; + } +#endif + spctrl_cofig_info[sp_id].sp_entry = spctrl_cfg->sp_entry; + spctrl_cofig_info[sp_id].code_addr = code_addr; + spctrl_cofig_info[sp_id].program_name = spctrl_cfg->program_name; + +#ifdef HRT_CSIM + /* Secondary SP is named as SP2 in SDK, however we are using secondary + SP as SP1 in the HSS and secondary SP Firmware */ + if (sp_id == SP0_ID) { + hrt_cell_set_icache_base_address(SP, spctrl_cofig_info[sp_id].code_addr); + hrt_cell_invalidate_icache(SP); + hrt_cell_load_program(SP, spctrl_cofig_info[sp_id].program_name); + } +#if defined(HAS_SEC_SP) + else { + hrt_cell_set_icache_base_address(SP2, spctrl_cofig_info[sp_id].code_addr); + hrt_cell_invalidate_icache(SP2); + hrt_cell_load_program(SP2, spctrl_cofig_info[sp_id].program_name); + } +#endif /* HAS_SEC_SP */ +#else + /* now we program the base address into the icache and + * invalidate the cache. + */ + sp_ctrl_store(sp_id, SP_ICACHE_ADDR_REG, (hrt_data)spctrl_cofig_info[sp_id].code_addr); + sp_ctrl_setbit(sp_id, SP_ICACHE_INV_REG, SP_ICACHE_INV_BIT); +#endif + spctrl_loaded[sp_id] = true; + return IA_CSS_SUCCESS; +} + +#ifdef ISP2401 +/* reload pre-loaded FW */ +void sh_css_spctrl_reload_fw(sp_ID_t sp_id) +{ +#ifdef HRT_CSIM + /* Secondary SP is named as SP2 in SDK, however we are using secondary + SP as SP1 in the HSS and secondary SP Firmware */ + if (sp_id == SP0_ID) { + hrt_cell_set_icache_base_address(SP, spctrl_cofig_info[sp_id].code_addr); + hrt_cell_invalidate_icache(SP); + hrt_cell_load_program(SP, spctrl_cofig_info[sp_id].program_name); + } +#if defined(HAS_SEC_SP) + else { + hrt_cell_set_icache_base_address(SP2, spctrl_cofig_info[sp_id].code_addr); + hrt_cell_invalidate_icache(SP2); + hrt_cell_load_program(SP2, spctrl_cofig_info[sp_id].program_name); + } +#endif /* HAS_SEC_SP */ +#else + /* now we program the base address into the icache and + * invalidate the cache. + */ + sp_ctrl_store(sp_id, SP_ICACHE_ADDR_REG, (hrt_data)spctrl_cofig_info[sp_id].code_addr); + sp_ctrl_setbit(sp_id, SP_ICACHE_INV_REG, SP_ICACHE_INV_BIT); +#endif + spctrl_loaded[sp_id] = true; +} + +#endif +hrt_vaddress get_sp_code_addr(sp_ID_t sp_id) +{ + return spctrl_cofig_info[sp_id].code_addr; +} + +enum ia_css_err ia_css_spctrl_unload_fw(sp_ID_t sp_id) +{ + if ((sp_id >= N_SP_ID) || ((sp_id < N_SP_ID) && (!spctrl_loaded[sp_id]))) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + /* freeup the resource */ + if (spctrl_cofig_info[sp_id].code_addr) + mmgr_free(spctrl_cofig_info[sp_id].code_addr); + spctrl_loaded[sp_id] = false; + return IA_CSS_SUCCESS; +} + +#ifdef HRT_CSIM +enum ia_css_err ia_css_spctrl_start(sp_ID_t sp_id) +{ + unsigned int HIVE_ADDR_sp_start_isp_entry; +#if defined(HAS_SEC_SP) + unsigned int HIVE_ADDR_sp1_start_entry; +#endif /* HAS_SEC_SP */ + if ((sp_id >= N_SP_ID) || ((sp_id < N_SP_ID) && (!spctrl_loaded[sp_id]))) + return IA_CSS_ERR_INVALID_ARGUMENTS; +if (sp_id == SP0_ID) + HIVE_ADDR_sp_start_isp_entry = spctrl_cofig_info[sp_id].sp_entry; +#if defined(HAS_SEC_SP) +else + HIVE_ADDR_sp1_start_entry = spctrl_cofig_info[sp_id].sp_entry; +#endif /* HAS_SEC_SP */ + +#if !defined(C_RUN) && !defined(HRT_UNSCHED) + sp_dmem_store(sp_id, + spctrl_cofig_info[sp_id].spctrl_config_dmem_addr, + &spctrl_cofig_info[sp_id].dmem_config, + sizeof(spctrl_cofig_info[sp_id].dmem_config)); +#endif + if (sp_id == SP0_ID) + hrt_cell_start_function(SP, sp_start_isp); +#if defined(HAS_SEC_SP) + else + /* Secondary SP is named as sp1 in the firmware however in + SDK secondary SP is named as SP2 */ + hrt_cell_start_function(SP2, sp1_start); +#endif /* HAS_SEC_SP */ + + return IA_CSS_SUCCESS; +} +#else +/* Initialize dmem_cfg in SP dmem and start SP program*/ +enum ia_css_err ia_css_spctrl_start(sp_ID_t sp_id) +{ + if ((sp_id >= N_SP_ID) || ((sp_id < N_SP_ID) && (!spctrl_loaded[sp_id]))) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + /* Set descr in the SP to initialize the SP DMEM */ + /* + * The FW stores user-space pointers to the FW, the ISP pointer + * is only available here + * + */ + assert(sizeof(unsigned int) <= sizeof(hrt_data)); + + sp_dmem_store(sp_id, + spctrl_cofig_info[sp_id].spctrl_config_dmem_addr, + &spctrl_cofig_info[sp_id].dmem_config, + sizeof(spctrl_cofig_info[sp_id].dmem_config)); + /* set the start address */ + sp_ctrl_store(sp_id, SP_START_ADDR_REG, (hrt_data)spctrl_cofig_info[sp_id].sp_entry); + sp_ctrl_setbit(sp_id, SP_SC_REG, SP_RUN_BIT); + sp_ctrl_setbit(sp_id, SP_SC_REG, SP_START_BIT); + return IA_CSS_SUCCESS; +} +#endif +/* Query the state of SP1 */ +ia_css_spctrl_sp_sw_state ia_css_spctrl_get_state(sp_ID_t sp_id) +{ + ia_css_spctrl_sp_sw_state state = 0; + unsigned int HIVE_ADDR_sp_sw_state; + if (sp_id >= N_SP_ID) + return IA_CSS_SP_SW_TERMINATED; + + HIVE_ADDR_sp_sw_state = spctrl_cofig_info[sp_id].spctrl_state_dmem_addr; + (void)HIVE_ADDR_sp_sw_state; /* Suppres warnings in CRUN */ + if (sp_id == SP0_ID) + state = sp_dmem_load_uint32(sp_id, (unsigned)sp_address_of(sp_sw_state)); +#if defined(HAS_SEC_SP) + else + state = sp_dmem_load_uint32(sp_id, (unsigned)sp1_address_of(sp_sw_state)); +#endif /* HAS_SEC_SP */ + + return state; +} + +int ia_css_spctrl_is_idle(sp_ID_t sp_id) +{ + int state = 0; + assert (sp_id < N_SP_ID); + +#ifdef HRT_CSIM + if (sp_id == SP0_ID) + state = (int)hrt_ctl_is_ready(SP); +#if defined(HAS_SEC_SP) + else + state = (int)hrt_ctl_is_ready(SP2); +#endif /* HAS_SEC_SP */ +#else /* HRT_CSIM */ + state = sp_ctrl_getbit(sp_id, SP_SC_REG, SP_IDLE_BIT); +#endif /* HRT_CSIM */ + return state; +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/tagger/interface/ia_css_tagger_common.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/tagger/interface/ia_css_tagger_common.h new file mode 100644 index 0000000000000000000000000000000000000000..d0d74957358be0ec108299cc9323d8091b67ebe2 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/tagger/interface/ia_css_tagger_common.h @@ -0,0 +1,59 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#ifndef __IA_CSS_TAGGER_COMMON_H__ +#define __IA_CSS_TAGGER_COMMON_H__ + +#include +#include + +/** + * @brief The tagger's circular buffer. + * + * Should be one less than NUM_CONTINUOUS_FRAMES in sh_css_internal.h + */ +#if defined(HAS_SP_2400) +#define MAX_CB_ELEMS_FOR_TAGGER 14 +#else +#define MAX_CB_ELEMS_FOR_TAGGER 9 +#endif + +/** + * @brief Data structure for the tagger buffer element. + */ +typedef struct { + uint32_t frame; /* the frame value stored in the element */ + uint32_t param; /* the param value stored in the element */ + uint8_t mark; /* the mark on the element */ + uint8_t lock; /* the lock on the element */ + uint8_t exp_id; /* exp_id of frame, for debugging only */ +} ia_css_tagger_buf_sp_elem_t; + +#endif /* __IA_CSS_TAGGER_COMMON_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/timer/src/timer.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/timer/src/timer.c new file mode 100644 index 0000000000000000000000000000000000000000..49c69e60ca5c5ed748bbab5c4bfad41a70c47d1b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/runtime/timer/src/timer.c @@ -0,0 +1,48 @@ +#ifndef ISP2401 +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ +#else +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ +#endif + +#include /* for uint32_t */ +#include "ia_css_timer.h" /*struct ia_css_clock_tick */ +#include "sh_css_legacy.h" /* IA_CSS_PIPE_ID_NUM*/ +#include "gp_timer.h" /*gp_timer_read()*/ +#include "assert_support.h" + +enum ia_css_err +ia_css_timer_get_current_tick( + struct ia_css_clock_tick *curr_ts) { + + assert(curr_ts != NULL); + if (curr_ts == NULL) { + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + curr_ts->ticks = (clock_value_t)gp_timer_read(GP_TIMER_SEL); + return IA_CSS_SUCCESS; +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css.c new file mode 100644 index 0000000000000000000000000000000000000000..f39d6f53e88d8d1208c8886a221fc8573c690bf3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css.c @@ -0,0 +1,11529 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/*! \file */ +#include "ia_css.h" +#include "sh_css_hrt.h" /* only for file 2 MIPI */ +#include "ia_css_buffer.h" +#include "ia_css_binary.h" +#include "sh_css_internal.h" +#include "sh_css_mipi.h" +#include "sh_css_sp.h" /* sh_css_sp_group */ +#if !defined(HAS_NO_INPUT_SYSTEM) +#include "ia_css_isys.h" +#endif +#include "ia_css_frame.h" +#include "sh_css_defs.h" +#include "sh_css_firmware.h" +#include "sh_css_params.h" +#include "sh_css_params_internal.h" +#include "sh_css_param_shading.h" +#include "ia_css_refcount.h" +#include "ia_css_rmgr.h" +#include "ia_css_debug.h" +#include "ia_css_debug_pipe.h" +#include "ia_css_memory_access.h" +#include "ia_css_device_access.h" +#include "device_access.h" +#include "sh_css_legacy.h" +#include "ia_css_pipeline.h" +#include "ia_css_stream.h" +#include "sh_css_stream_format.h" +#include "ia_css_pipe.h" +#include "ia_css_util.h" +#include "ia_css_pipe_util.h" +#include "ia_css_pipe_binarydesc.h" +#include "ia_css_pipe_stagedesc.h" +#ifdef USE_INPUT_SYSTEM_VERSION_2 +#include "ia_css_isys.h" +#endif + +#include "memory_access.h" +#include "tag.h" +#include "assert_support.h" +#include "math_support.h" +#include "sw_event_global.h" /* Event IDs.*/ +#if !defined(HAS_NO_INPUT_FORMATTER) +#include "ia_css_ifmtr.h" +#endif +#if !defined(HAS_NO_INPUT_SYSTEM) +#include "input_system.h" +#endif +#include "mmu_device.h" /* mmu_set_page_table_base_index(), ... */ +//#include "ia_css_mmu_private.h" /* sh_css_mmu_set_page_table_base_index() */ +#include "gdc_device.h" /* HRT_GDC_N */ +#include "dma.h" /* dma_set_max_burst_size() */ +#include "irq.h" /* virq */ +#include "sp.h" /* cnd_sp_irq_enable() */ +#include "isp.h" /* cnd_isp_irq_enable, ISP_VEC_NELEMS */ +#include "gp_device.h" /* gp_device_reg_store() */ +#define __INLINE_GPIO__ +#include "gpio.h" +#include "timed_ctrl.h" +#include "platform_support.h" /* hrt_sleep(), inline */ +#include "ia_css_inputfifo.h" +#define WITH_PC_MONITORING 0 + +#define SH_CSS_VIDEO_BUFFER_ALIGNMENT 0 + +#if WITH_PC_MONITORING +#define MULTIPLE_SAMPLES 1 +#define NOF_SAMPLES 60 +#include "linux/kthread.h" +#include "linux/sched.h" +#include "linux/delay.h" +#include "sh_css_metrics.h" +static int thread_alive; +#endif /* WITH_PC_MONITORING */ + +#include "ia_css_spctrl.h" +#include "ia_css_version_data.h" +#include "sh_css_struct.h" +#include "ia_css_bufq.h" +#include "ia_css_timer.h" /* clock_value_t */ + +#include "isp/modes/interface/input_buf.isp.h" + +#if defined(HAS_BL) +#include "support/bootloader/interface/ia_css_blctrl.h" +#endif +#if defined(HAS_RES_MGR) +#include "components/acc_cluster/gen/host/acc_cluster.host.h" +#endif + +/* Name of the sp program: should not be built-in */ +#define SP_PROG_NAME "sp" +#if defined(HAS_SEC_SP) +#define SP1_PROG_NAME "sp1" +#endif /* HAS_SEC_SP */ +#if defined(HAS_BL) +#define BL_PROG_NAME "bootloader" +#endif +/* Size of Refcount List */ +#define REFCOUNT_SIZE 1000 + +/* for JPEG, we don't know the length of the image upfront, + * but since we support sensor upto 16MP, we take this as + * upper limit. + */ +#define JPEG_BYTES (16 * 1024 * 1024) + +#define STATS_ENABLED(stage) (stage && stage->binary && stage->binary->info && \ + (stage->binary->info->sp.enable.s3a || stage->binary->info->sp.enable.dis)) + +#define DEFAULT_PLANES { {0, 0, 0, 0} } + +struct sh_css my_css; + +int (*sh_css_printf) (const char *fmt, va_list args) = NULL; + +/* modes of work: stream_create and stream_destroy will update the save/restore data + only when in working mode, not suspend/resume +*/ +enum ia_sh_css_modes { + sh_css_mode_none = 0, + sh_css_mode_working, + sh_css_mode_suspend, + sh_css_mode_resume +}; + +/* a stream seed, to save and restore the stream data. + the stream seed contains all the data required to "grow" the seed again after it was closed. +*/ +struct sh_css_stream_seed { + struct ia_css_stream **orig_stream; /* pointer to restore the original handle */ + struct ia_css_stream *stream; /* handle, used as ID too.*/ + struct ia_css_stream_config stream_config; /* stream config struct */ + int num_pipes; + struct ia_css_pipe *pipes[IA_CSS_PIPE_ID_NUM]; /* pipe handles */ + struct ia_css_pipe **orig_pipes[IA_CSS_PIPE_ID_NUM]; /* pointer to restore original handle */ + struct ia_css_pipe_config pipe_config[IA_CSS_PIPE_ID_NUM]; /* pipe config structs */ +}; + +#define MAX_ACTIVE_STREAMS 5 +/* A global struct for save/restore to hold all the data that should sustain power-down: + MMU base, IRQ type, env for routines, binary loaded FW and the stream seeds. +*/ +struct sh_css_save { + enum ia_sh_css_modes mode; + uint32_t mmu_base; /* the last mmu_base */ + enum ia_css_irq_type irq_type; + struct sh_css_stream_seed stream_seeds[MAX_ACTIVE_STREAMS]; + struct ia_css_fw *loaded_fw; /* fw struct previously loaded */ + struct ia_css_env driver_env; /* driver-supplied env copy */ +}; + +static bool my_css_save_initialized; /* if my_css_save was initialized */ +static struct sh_css_save my_css_save; + +/* pqiao NOTICE: this is for css internal buffer recycling when stopping pipeline, + this array is temporary and will be replaced by resource manager*/ +/* Taking the biggest Size for number of Elements */ +#define MAX_HMM_BUFFER_NUM \ + (SH_CSS_MAX_NUM_QUEUES * (IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE + 2)) + +struct sh_css_hmm_buffer_record { + bool in_use; + enum ia_css_buffer_type type; + struct ia_css_rmgr_vbuf_handle *h_vbuf; + hrt_address kernel_ptr; +}; + +static struct sh_css_hmm_buffer_record hmm_buffer_record[MAX_HMM_BUFFER_NUM]; + +#define GPIO_FLASH_PIN_MASK (1 << HIVE_GPIO_STROBE_TRIGGER_PIN) + +static bool fw_explicitly_loaded = false; + +/** + * Local prototypes + */ + +static enum ia_css_err +allocate_delay_frames(struct ia_css_pipe *pipe); + +static enum ia_css_err +sh_css_pipe_start(struct ia_css_stream *stream); + +#ifdef ISP2401 +/** + * @brief Stop all "ia_css_pipe" instances in the target + * "ia_css_stream" instance. + * + * @param[in] stream Point to the target "ia_css_stream" instance. + * + * @return + * - IA_CSS_SUCCESS, if the "stop" requests have been sucessfully sent out. + * - CSS error code, otherwise. + * + * + * NOTE + * This API sends the "stop" requests to the "ia_css_pipe" + * instances in the same "ia_css_stream" instance. It will + * return without waiting for all "ia_css_pipe" instatnces + * being stopped. + */ +static enum ia_css_err +sh_css_pipes_stop(struct ia_css_stream *stream); + +/** + * @brief Check if all "ia_css_pipe" instances in the target + * "ia_css_stream" instance have stopped. + * + * @param[in] stream Point to the target "ia_css_stream" instance. + * + * @return + * - true, if all "ia_css_pipe" instances in the target "ia_css_stream" + * instance have ben stopped. + * - false, otherwise. + */ +static bool +sh_css_pipes_have_stopped(struct ia_css_stream *stream); + +static enum ia_css_err +ia_css_pipe_check_format(struct ia_css_pipe *pipe, enum ia_css_frame_format format); + +static enum ia_css_err +check_pipe_resolutions(const struct ia_css_pipe *pipe); + +#endif + +static enum ia_css_err +ia_css_pipe_load_extension(struct ia_css_pipe *pipe, + struct ia_css_fw_info *firmware); + +static void +ia_css_pipe_unload_extension(struct ia_css_pipe *pipe, + struct ia_css_fw_info *firmware); +static void +ia_css_reset_defaults(struct sh_css* css); + +static void +sh_css_init_host_sp_control_vars(void); + +#ifndef ISP2401 +static void +sh_css_mmu_set_page_table_base_index(hrt_data base_index); + +#endif +static enum ia_css_err set_num_primary_stages(unsigned int *num, enum ia_css_pipe_version version); + +static bool +need_capture_pp(const struct ia_css_pipe *pipe); + +static bool +need_yuv_scaler_stage(const struct ia_css_pipe *pipe); + +static enum ia_css_err ia_css_pipe_create_cas_scaler_desc_single_output( + struct ia_css_frame_info *cas_scaler_in_info, + struct ia_css_frame_info *cas_scaler_out_info, + struct ia_css_frame_info *cas_scaler_vf_info, + struct ia_css_cas_binary_descr *descr); + +static void ia_css_pipe_destroy_cas_scaler_desc(struct ia_css_cas_binary_descr *descr); + +static bool +need_downscaling(const struct ia_css_resolution in_res, + const struct ia_css_resolution out_res); + +static bool need_capt_ldc(const struct ia_css_pipe *pipe); + +static enum ia_css_err +sh_css_pipe_load_binaries(struct ia_css_pipe *pipe); + +static +enum ia_css_err sh_css_pipe_get_viewfinder_frame_info( + struct ia_css_pipe *pipe, + struct ia_css_frame_info *info, + unsigned int idx); + +static enum ia_css_err +sh_css_pipe_get_output_frame_info(struct ia_css_pipe *pipe, + struct ia_css_frame_info *info, + unsigned int idx); + +static enum ia_css_err +capture_start(struct ia_css_pipe *pipe); + +static enum ia_css_err +video_start(struct ia_css_pipe *pipe); + +static enum ia_css_err +preview_start(struct ia_css_pipe *pipe); + +static enum ia_css_err +yuvpp_start(struct ia_css_pipe *pipe); + +static bool copy_on_sp(struct ia_css_pipe *pipe); + +static enum ia_css_err +init_vf_frameinfo_defaults(struct ia_css_pipe *pipe, + struct ia_css_frame *vf_frame, unsigned int idx); + +static enum ia_css_err +init_in_frameinfo_memory_defaults(struct ia_css_pipe *pipe, + struct ia_css_frame *frame, enum ia_css_frame_format format); + +static enum ia_css_err +init_out_frameinfo_defaults(struct ia_css_pipe *pipe, + struct ia_css_frame *out_frame, unsigned int idx); + +static enum ia_css_err +sh_css_pipeline_add_acc_stage(struct ia_css_pipeline *pipeline, + const void *acc_fw); + +static enum ia_css_err +alloc_continuous_frames( + struct ia_css_pipe *pipe, bool init_time); + +static void +pipe_global_init(void); + +static enum ia_css_err +pipe_generate_pipe_num(const struct ia_css_pipe *pipe, unsigned int *pipe_number); + +static void +pipe_release_pipe_num(unsigned int pipe_num); + +static enum ia_css_err +create_host_pipeline_structure(struct ia_css_stream *stream); + +static enum ia_css_err +create_host_pipeline(struct ia_css_stream *stream); + +static enum ia_css_err +create_host_preview_pipeline(struct ia_css_pipe *pipe); + +static enum ia_css_err +create_host_video_pipeline(struct ia_css_pipe *pipe); + +static enum ia_css_err +create_host_copy_pipeline(struct ia_css_pipe *pipe, + unsigned max_input_width, + struct ia_css_frame *out_frame); + +static enum ia_css_err +create_host_isyscopy_capture_pipeline(struct ia_css_pipe *pipe); + +static enum ia_css_err +create_host_capture_pipeline(struct ia_css_pipe *pipe); + +static enum ia_css_err +create_host_yuvpp_pipeline(struct ia_css_pipe *pipe); + +static enum ia_css_err +create_host_acc_pipeline(struct ia_css_pipe *pipe); + +static unsigned int +sh_css_get_sw_interrupt_value(unsigned int irq); + +static struct ia_css_binary *ia_css_pipe_get_shading_correction_binary(const struct ia_css_pipe *pipe); + +static struct ia_css_binary * +ia_css_pipe_get_s3a_binary(const struct ia_css_pipe *pipe); + +static struct ia_css_binary * +ia_css_pipe_get_sdis_binary(const struct ia_css_pipe *pipe); + +static void +sh_css_hmm_buffer_record_init(void); + +static void +sh_css_hmm_buffer_record_uninit(void); + +static void +sh_css_hmm_buffer_record_reset(struct sh_css_hmm_buffer_record *buffer_record); + +#ifndef ISP2401 +static bool +sh_css_hmm_buffer_record_acquire(struct ia_css_rmgr_vbuf_handle *h_vbuf, +#else +static struct sh_css_hmm_buffer_record +*sh_css_hmm_buffer_record_acquire(struct ia_css_rmgr_vbuf_handle *h_vbuf, +#endif + enum ia_css_buffer_type type, + hrt_address kernel_ptr); + +static struct sh_css_hmm_buffer_record +*sh_css_hmm_buffer_record_validate(hrt_vaddress ddr_buffer_addr, + enum ia_css_buffer_type type); + +void +ia_css_get_acc_configs( + struct ia_css_pipe *pipe, + struct ia_css_isp_config *config); + + +#if CONFIG_ON_FRAME_ENQUEUE() +static enum ia_css_err set_config_on_frame_enqueue(struct ia_css_frame_info *info, struct frame_data_wrapper *frame); +#endif + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 +static unsigned int get_crop_lines_for_bayer_order(const struct ia_css_stream_config *config); +static unsigned int get_crop_columns_for_bayer_order(const struct ia_css_stream_config *config); +static void get_pipe_extra_pixel(struct ia_css_pipe *pipe, + unsigned int *extra_row, unsigned int *extra_column); +#endif + +#if defined(HAS_SEC_SP) +static enum ia_css_err +sh_css_start_sp1(void); + +static enum ia_css_err +sh_css_stop_sp1(void); +#endif + +#ifdef ISP2401 +#ifdef USE_INPUT_SYSTEM_VERSION_2401 +static enum ia_css_err +aspect_ratio_crop_init(struct ia_css_stream *curr_stream, + struct ia_css_pipe *pipes[], + bool *do_crop_status); + +static bool +aspect_ratio_crop_check(bool enabled, struct ia_css_pipe *curr_pipe); + +static enum ia_css_err +aspect_ratio_crop(struct ia_css_pipe *curr_pipe, + struct ia_css_resolution *effective_res); +#endif + +#endif +static void +sh_css_pipe_free_shading_table(struct ia_css_pipe *pipe) +{ + assert(pipe != NULL); + if (pipe == NULL) { + IA_CSS_ERROR("NULL input parameter"); + return; + } + + if (pipe->shading_table) + ia_css_shading_table_free(pipe->shading_table); + pipe->shading_table = NULL; +} + +static enum ia_css_frame_format yuv420_copy_formats[] = { + IA_CSS_FRAME_FORMAT_NV12, + IA_CSS_FRAME_FORMAT_NV21, + IA_CSS_FRAME_FORMAT_YV12, + IA_CSS_FRAME_FORMAT_YUV420, + IA_CSS_FRAME_FORMAT_YUV420_16, + IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8, + IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8 +}; + +static enum ia_css_frame_format yuv422_copy_formats[] = { + IA_CSS_FRAME_FORMAT_NV12, + IA_CSS_FRAME_FORMAT_NV16, + IA_CSS_FRAME_FORMAT_NV21, + IA_CSS_FRAME_FORMAT_NV61, + IA_CSS_FRAME_FORMAT_YV12, + IA_CSS_FRAME_FORMAT_YV16, + IA_CSS_FRAME_FORMAT_YUV420, + IA_CSS_FRAME_FORMAT_YUV420_16, + IA_CSS_FRAME_FORMAT_YUV422, + IA_CSS_FRAME_FORMAT_YUV422_16, + IA_CSS_FRAME_FORMAT_UYVY, + IA_CSS_FRAME_FORMAT_YUYV +}; + +#define array_length(array) (sizeof(array)/sizeof(array[0])) + +/* Verify whether the selected output format is can be produced + * by the copy binary given the stream format. + * */ +static enum ia_css_err +verify_copy_out_frame_format(struct ia_css_pipe *pipe) +{ + enum ia_css_frame_format out_fmt = pipe->output_info[0].format; + unsigned int i, found = 0; + + assert(pipe != NULL); + assert(pipe->stream != NULL); + + switch (pipe->stream->config.input_config.format) { + case IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY: + case IA_CSS_STREAM_FORMAT_YUV420_8: + for (i=0; iconfig.input_config.format, + stream->config.pixels_per_clock == 2); + + return bpp; +} + +#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2) +static enum ia_css_err +sh_css_config_input_network(struct ia_css_stream *stream) +{ + unsigned int fmt_type; + struct ia_css_pipe *pipe = stream->last_pipe; + struct ia_css_binary *binary = NULL; + enum ia_css_err err = IA_CSS_SUCCESS; + + assert(stream != NULL); + assert(pipe != NULL); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_config_input_network() enter:\n"); + + if (pipe->pipeline.stages) + binary = pipe->pipeline.stages->binary; + + err = ia_css_isys_convert_stream_format_to_mipi_format( + stream->config.input_config.format, + stream->csi_rx_config.comp, + &fmt_type); + if (err != IA_CSS_SUCCESS) + return err; + sh_css_sp_program_input_circuit(fmt_type, + stream->config.channel_id, + stream->config.mode); + + if ((binary && (binary->online || stream->config.continuous)) || + pipe->config.mode == IA_CSS_PIPE_MODE_COPY) { + err = ia_css_ifmtr_configure(&stream->config, + binary); + if (err != IA_CSS_SUCCESS) + return err; + } + + if (stream->config.mode == IA_CSS_INPUT_MODE_TPG || + stream->config.mode == IA_CSS_INPUT_MODE_PRBS) { + unsigned int hblank_cycles = 100, + vblank_lines = 6, + width, + height, + vblank_cycles; + width = (stream->config.input_config.input_res.width) / (1 + (stream->config.pixels_per_clock == 2)); + height = stream->config.input_config.input_res.height; + vblank_cycles = vblank_lines * (width + hblank_cycles); + sh_css_sp_configure_sync_gen(width, height, hblank_cycles, + vblank_cycles); +#if defined(IS_ISP_2400_SYSTEM) + if (pipe->stream->config.mode == IA_CSS_INPUT_MODE_TPG) { + /* TODO: move define to proper file in tools */ + #define GP_ISEL_TPG_MODE 0x90058 + ia_css_device_store_uint32(GP_ISEL_TPG_MODE, 0); + } +#endif + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_config_input_network() leave:\n"); + return IA_CSS_SUCCESS; +} +#elif !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2401) +static unsigned int csi2_protocol_calculate_max_subpixels_per_line( + enum ia_css_stream_format format, + unsigned int pixels_per_line) +{ + unsigned int rval; + + switch (format) { + case IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY: + /* + * The frame format layout is shown below. + * + * Line 0: UYY0 UYY0 ... UYY0 + * Line 1: VYY0 VYY0 ... VYY0 + * Line 2: UYY0 UYY0 ... UYY0 + * Line 3: VYY0 VYY0 ... VYY0 + * ... + * Line (n-2): UYY0 UYY0 ... UYY0 + * Line (n-1): VYY0 VYY0 ... VYY0 + * + * In this frame format, the even-line is + * as wide as the odd-line. + * The 0 is introduced by the input system + * (mipi backend). + */ + rval = pixels_per_line * 2; + break; + case IA_CSS_STREAM_FORMAT_YUV420_8: + case IA_CSS_STREAM_FORMAT_YUV420_10: + case IA_CSS_STREAM_FORMAT_YUV420_16: + /* + * The frame format layout is shown below. + * + * Line 0: YYYY YYYY ... YYYY + * Line 1: UYVY UYVY ... UYVY UYVY + * Line 2: YYYY YYYY ... YYYY + * Line 3: UYVY UYVY ... UYVY UYVY + * ... + * Line (n-2): YYYY YYYY ... YYYY + * Line (n-1): UYVY UYVY ... UYVY UYVY + * + * In this frame format, the odd-line is twice + * wider than the even-line. + */ + rval = pixels_per_line * 2; + break; + case IA_CSS_STREAM_FORMAT_YUV422_8: + case IA_CSS_STREAM_FORMAT_YUV422_10: + case IA_CSS_STREAM_FORMAT_YUV422_16: + /* + * The frame format layout is shown below. + * + * Line 0: UYVY UYVY ... UYVY + * Line 1: UYVY UYVY ... UYVY + * Line 2: UYVY UYVY ... UYVY + * Line 3: UYVY UYVY ... UYVY + * ... + * Line (n-2): UYVY UYVY ... UYVY + * Line (n-1): UYVY UYVY ... UYVY + * + * In this frame format, the even-line is + * as wide as the odd-line. + */ + rval = pixels_per_line * 2; + break; + case IA_CSS_STREAM_FORMAT_RGB_444: + case IA_CSS_STREAM_FORMAT_RGB_555: + case IA_CSS_STREAM_FORMAT_RGB_565: + case IA_CSS_STREAM_FORMAT_RGB_666: + case IA_CSS_STREAM_FORMAT_RGB_888: + /* + * The frame format layout is shown below. + * + * Line 0: ABGR ABGR ... ABGR + * Line 1: ABGR ABGR ... ABGR + * Line 2: ABGR ABGR ... ABGR + * Line 3: ABGR ABGR ... ABGR + * ... + * Line (n-2): ABGR ABGR ... ABGR + * Line (n-1): ABGR ABGR ... ABGR + * + * In this frame format, the even-line is + * as wide as the odd-line. + */ + rval = pixels_per_line * 4; + break; + case IA_CSS_STREAM_FORMAT_RAW_6: + case IA_CSS_STREAM_FORMAT_RAW_7: + case IA_CSS_STREAM_FORMAT_RAW_8: + case IA_CSS_STREAM_FORMAT_RAW_10: + case IA_CSS_STREAM_FORMAT_RAW_12: + case IA_CSS_STREAM_FORMAT_RAW_14: + case IA_CSS_STREAM_FORMAT_RAW_16: + case IA_CSS_STREAM_FORMAT_BINARY_8: + case IA_CSS_STREAM_FORMAT_USER_DEF1: + case IA_CSS_STREAM_FORMAT_USER_DEF2: + case IA_CSS_STREAM_FORMAT_USER_DEF3: + case IA_CSS_STREAM_FORMAT_USER_DEF4: + case IA_CSS_STREAM_FORMAT_USER_DEF5: + case IA_CSS_STREAM_FORMAT_USER_DEF6: + case IA_CSS_STREAM_FORMAT_USER_DEF7: + case IA_CSS_STREAM_FORMAT_USER_DEF8: + /* + * The frame format layout is shown below. + * + * Line 0: Pixel Pixel ... Pixel + * Line 1: Pixel Pixel ... Pixel + * Line 2: Pixel Pixel ... Pixel + * Line 3: Pixel Pixel ... Pixel + * ... + * Line (n-2): Pixel Pixel ... Pixel + * Line (n-1): Pixel Pixel ... Pixel + * + * In this frame format, the even-line is + * as wide as the odd-line. + */ + rval = pixels_per_line; + break; + default: + rval = 0; + break; + } + + return rval; +} + +static bool sh_css_translate_stream_cfg_to_input_system_input_port_id( + struct ia_css_stream_config *stream_cfg, + ia_css_isys_descr_t *isys_stream_descr) +{ + bool rc; + + rc = true; + switch (stream_cfg->mode) { + case IA_CSS_INPUT_MODE_TPG: + + if (stream_cfg->source.tpg.id == IA_CSS_TPG_ID0) { + isys_stream_descr->input_port_id = INPUT_SYSTEM_PIXELGEN_PORT0_ID; + } else if (stream_cfg->source.tpg.id == IA_CSS_TPG_ID1) { + isys_stream_descr->input_port_id = INPUT_SYSTEM_PIXELGEN_PORT1_ID; + } else if (stream_cfg->source.tpg.id == IA_CSS_TPG_ID2) { + isys_stream_descr->input_port_id = INPUT_SYSTEM_PIXELGEN_PORT2_ID; + } + + break; + case IA_CSS_INPUT_MODE_PRBS: + + if (stream_cfg->source.prbs.id == IA_CSS_PRBS_ID0) { + isys_stream_descr->input_port_id = INPUT_SYSTEM_PIXELGEN_PORT0_ID; + } else if (stream_cfg->source.prbs.id == IA_CSS_PRBS_ID1) { + isys_stream_descr->input_port_id = INPUT_SYSTEM_PIXELGEN_PORT1_ID; + } else if (stream_cfg->source.prbs.id == IA_CSS_PRBS_ID2) { + isys_stream_descr->input_port_id = INPUT_SYSTEM_PIXELGEN_PORT2_ID; + } + + break; + case IA_CSS_INPUT_MODE_BUFFERED_SENSOR: + + if (stream_cfg->source.port.port == IA_CSS_CSI2_PORT0) { + isys_stream_descr->input_port_id = INPUT_SYSTEM_CSI_PORT0_ID; + } else if (stream_cfg->source.port.port == IA_CSS_CSI2_PORT1) { + isys_stream_descr->input_port_id = INPUT_SYSTEM_CSI_PORT1_ID; + } else if (stream_cfg->source.port.port == IA_CSS_CSI2_PORT2) { + isys_stream_descr->input_port_id = INPUT_SYSTEM_CSI_PORT2_ID; + } + + break; + default: + rc = false; + break; + } + + return rc; +} + +static bool sh_css_translate_stream_cfg_to_input_system_input_port_type( + struct ia_css_stream_config *stream_cfg, + ia_css_isys_descr_t *isys_stream_descr) +{ + bool rc; + + rc = true; + switch (stream_cfg->mode) { + case IA_CSS_INPUT_MODE_TPG: + + isys_stream_descr->mode = INPUT_SYSTEM_SOURCE_TYPE_TPG; + + break; + case IA_CSS_INPUT_MODE_PRBS: + + isys_stream_descr->mode = INPUT_SYSTEM_SOURCE_TYPE_PRBS; + + break; + case IA_CSS_INPUT_MODE_SENSOR: + case IA_CSS_INPUT_MODE_BUFFERED_SENSOR: + + isys_stream_descr->mode = INPUT_SYSTEM_SOURCE_TYPE_SENSOR; + break; + + default: + rc = false; + break; + } + + return rc; +} + +static bool sh_css_translate_stream_cfg_to_input_system_input_port_attr( + struct ia_css_stream_config *stream_cfg, + ia_css_isys_descr_t *isys_stream_descr, + int isys_stream_idx) +{ + bool rc; + + rc = true; + switch (stream_cfg->mode) { + case IA_CSS_INPUT_MODE_TPG: + if (stream_cfg->source.tpg.mode == IA_CSS_TPG_MODE_RAMP) { + isys_stream_descr->tpg_port_attr.mode = PIXELGEN_TPG_MODE_RAMP; + } else if (stream_cfg->source.tpg.mode == IA_CSS_TPG_MODE_CHECKERBOARD) { + isys_stream_descr->tpg_port_attr.mode = PIXELGEN_TPG_MODE_CHBO; + } else if (stream_cfg->source.tpg.mode == IA_CSS_TPG_MODE_MONO) { + isys_stream_descr->tpg_port_attr.mode = PIXELGEN_TPG_MODE_MONO; + } else { + rc = false; + } + + /* + * TODO + * - Make "color_cfg" as part of "ia_css_tpg_config". + */ + isys_stream_descr->tpg_port_attr.color_cfg.R1 = 51; + isys_stream_descr->tpg_port_attr.color_cfg.G1 = 102; + isys_stream_descr->tpg_port_attr.color_cfg.B1 = 255; + isys_stream_descr->tpg_port_attr.color_cfg.R2 = 0; + isys_stream_descr->tpg_port_attr.color_cfg.G2 = 100; + isys_stream_descr->tpg_port_attr.color_cfg.B2 = 160; + + isys_stream_descr->tpg_port_attr.mask_cfg.h_mask = stream_cfg->source.tpg.x_mask; + isys_stream_descr->tpg_port_attr.mask_cfg.v_mask = stream_cfg->source.tpg.y_mask; + isys_stream_descr->tpg_port_attr.mask_cfg.hv_mask = stream_cfg->source.tpg.xy_mask; + + isys_stream_descr->tpg_port_attr.delta_cfg.h_delta = stream_cfg->source.tpg.x_delta; + isys_stream_descr->tpg_port_attr.delta_cfg.v_delta = stream_cfg->source.tpg.y_delta; + + /* + * TODO + * - Make "sync_gen_cfg" as part of "ia_css_tpg_config". + */ + isys_stream_descr->tpg_port_attr.sync_gen_cfg.hblank_cycles = 100; + isys_stream_descr->tpg_port_attr.sync_gen_cfg.vblank_cycles = 100; + isys_stream_descr->tpg_port_attr.sync_gen_cfg.pixels_per_clock = stream_cfg->pixels_per_clock; + isys_stream_descr->tpg_port_attr.sync_gen_cfg.nr_of_frames = (uint32_t) ~(0x0); + isys_stream_descr->tpg_port_attr.sync_gen_cfg.pixels_per_line = stream_cfg->isys_config[IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX].input_res.width; + isys_stream_descr->tpg_port_attr.sync_gen_cfg.lines_per_frame = stream_cfg->isys_config[IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX].input_res.height; + + break; + case IA_CSS_INPUT_MODE_PRBS: + + isys_stream_descr->prbs_port_attr.seed0 = stream_cfg->source.prbs.seed; + isys_stream_descr->prbs_port_attr.seed1 = stream_cfg->source.prbs.seed1; + + /* + * TODO + * - Make "sync_gen_cfg" as part of "ia_css_prbs_config". + */ + isys_stream_descr->prbs_port_attr.sync_gen_cfg.hblank_cycles = 100; + isys_stream_descr->prbs_port_attr.sync_gen_cfg.vblank_cycles = 100; + isys_stream_descr->prbs_port_attr.sync_gen_cfg.pixels_per_clock = stream_cfg->pixels_per_clock; + isys_stream_descr->prbs_port_attr.sync_gen_cfg.nr_of_frames = (uint32_t) ~(0x0); + isys_stream_descr->prbs_port_attr.sync_gen_cfg.pixels_per_line = stream_cfg->isys_config[IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX].input_res.width; + isys_stream_descr->prbs_port_attr.sync_gen_cfg.lines_per_frame = stream_cfg->isys_config[IA_CSS_STREAM_DEFAULT_ISYS_STREAM_IDX].input_res.height; + + break; + case IA_CSS_INPUT_MODE_BUFFERED_SENSOR: + { + enum ia_css_err err; + unsigned int fmt_type; + + err = ia_css_isys_convert_stream_format_to_mipi_format( + stream_cfg->isys_config[isys_stream_idx].format, + MIPI_PREDICTOR_NONE, + &fmt_type); + if (err != IA_CSS_SUCCESS) + rc = false; + + isys_stream_descr->csi_port_attr.active_lanes = stream_cfg->source.port.num_lanes; + isys_stream_descr->csi_port_attr.fmt_type = fmt_type; + isys_stream_descr->csi_port_attr.ch_id = stream_cfg->channel_id; +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + isys_stream_descr->online = stream_cfg->online; +#endif + err |= ia_css_isys_convert_compressed_format( + &stream_cfg->source.port.compression, + isys_stream_descr); + if (err != IA_CSS_SUCCESS) + rc = false; + + /* metadata */ + isys_stream_descr->metadata.enable = false; + if (stream_cfg->metadata_config.resolution.height > 0) { + err = ia_css_isys_convert_stream_format_to_mipi_format( + stream_cfg->metadata_config.data_type, + MIPI_PREDICTOR_NONE, + &fmt_type); + if (err != IA_CSS_SUCCESS) + rc = false; + isys_stream_descr->metadata.fmt_type = fmt_type; + isys_stream_descr->metadata.bits_per_pixel = + ia_css_util_input_format_bpp(stream_cfg->metadata_config.data_type, true); + isys_stream_descr->metadata.pixels_per_line = stream_cfg->metadata_config.resolution.width; + isys_stream_descr->metadata.lines_per_frame = stream_cfg->metadata_config.resolution.height; +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + /* For new input system, number of str2mmio requests must be even. + * So we round up number of metadata lines to be even. */ + if (isys_stream_descr->metadata.lines_per_frame > 0) + isys_stream_descr->metadata.lines_per_frame += + (isys_stream_descr->metadata.lines_per_frame & 1); +#endif + isys_stream_descr->metadata.align_req_in_bytes = + ia_css_csi2_calculate_input_system_alignment(stream_cfg->metadata_config.data_type); + isys_stream_descr->metadata.enable = true; + } + + break; + } + default: + rc = false; + break; + } + + return rc; +} + +static bool sh_css_translate_stream_cfg_to_input_system_input_port_resolution( + struct ia_css_stream_config *stream_cfg, + ia_css_isys_descr_t *isys_stream_descr, + int isys_stream_idx) +{ + unsigned int bits_per_subpixel; + unsigned int max_subpixels_per_line; + unsigned int lines_per_frame; + unsigned int align_req_in_bytes; + enum ia_css_stream_format fmt_type; + + fmt_type = stream_cfg->isys_config[isys_stream_idx].format; + if ((stream_cfg->mode == IA_CSS_INPUT_MODE_SENSOR || + stream_cfg->mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR) && + stream_cfg->source.port.compression.type != IA_CSS_CSI2_COMPRESSION_TYPE_NONE) { + + if (stream_cfg->source.port.compression.uncompressed_bits_per_pixel == + UNCOMPRESSED_BITS_PER_PIXEL_10) { + fmt_type = IA_CSS_STREAM_FORMAT_RAW_10; + } + else if (stream_cfg->source.port.compression.uncompressed_bits_per_pixel == + UNCOMPRESSED_BITS_PER_PIXEL_12) { + fmt_type = IA_CSS_STREAM_FORMAT_RAW_12; + } + else + return false; + } + + bits_per_subpixel = + sh_css_stream_format_2_bits_per_subpixel(fmt_type); + if (bits_per_subpixel == 0) + return false; + + max_subpixels_per_line = + csi2_protocol_calculate_max_subpixels_per_line(fmt_type, + stream_cfg->isys_config[isys_stream_idx].input_res.width); + if (max_subpixels_per_line == 0) + return false; + + lines_per_frame = stream_cfg->isys_config[isys_stream_idx].input_res.height; + if (lines_per_frame == 0) + return false; + + align_req_in_bytes = ia_css_csi2_calculate_input_system_alignment(fmt_type); + + /* HW needs subpixel info for their settings */ + isys_stream_descr->input_port_resolution.bits_per_pixel = bits_per_subpixel; + isys_stream_descr->input_port_resolution.pixels_per_line = max_subpixels_per_line; + isys_stream_descr->input_port_resolution.lines_per_frame = lines_per_frame; + isys_stream_descr->input_port_resolution.align_req_in_bytes = align_req_in_bytes; + + return true; +} + +static bool sh_css_translate_stream_cfg_to_isys_stream_descr( + struct ia_css_stream_config *stream_cfg, + bool early_polling, + ia_css_isys_descr_t *isys_stream_descr, + int isys_stream_idx) +{ + bool rc; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_translate_stream_cfg_to_isys_stream_descr() enter:\n"); + rc = sh_css_translate_stream_cfg_to_input_system_input_port_id(stream_cfg, isys_stream_descr); + rc &= sh_css_translate_stream_cfg_to_input_system_input_port_type(stream_cfg, isys_stream_descr); + rc &= sh_css_translate_stream_cfg_to_input_system_input_port_attr(stream_cfg, isys_stream_descr, isys_stream_idx); + rc &= sh_css_translate_stream_cfg_to_input_system_input_port_resolution(stream_cfg, isys_stream_descr, isys_stream_idx); + + isys_stream_descr->raw_packed = stream_cfg->pack_raw_pixels; + isys_stream_descr->linked_isys_stream_id = (int8_t) stream_cfg->isys_config[isys_stream_idx].linked_isys_stream_id; + /* + * Early polling is required for timestamp accuracy in certain case. + * The ISYS HW polling is started on + * ia_css_isys_stream_capture_indication() instead of + * ia_css_pipeline_sp_wait_for_isys_stream_N() as isp processing of + * capture takes longer than getting an ISYS frame + * + * Only 2401 relevant ?? + */ + isys_stream_descr->polling_mode + = early_polling ? INPUT_SYSTEM_POLL_ON_CAPTURE_REQUEST + : INPUT_SYSTEM_POLL_ON_WAIT_FOR_FRAME; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_translate_stream_cfg_to_isys_stream_descr() leave:\n"); + + return rc; +} + +static bool sh_css_translate_binary_info_to_input_system_output_port_attr( + struct ia_css_binary *binary, + ia_css_isys_descr_t *isys_stream_descr) +{ + if (!binary) + return false; + + isys_stream_descr->output_port_attr.left_padding = binary->left_padding; + isys_stream_descr->output_port_attr.max_isp_input_width = binary->info->sp.input.max_width; + + return true; +} + +static enum ia_css_err +sh_css_config_input_network(struct ia_css_stream *stream) +{ + bool rc; + ia_css_isys_descr_t isys_stream_descr; + unsigned int sp_thread_id; + struct sh_css_sp_pipeline_terminal *sp_pipeline_input_terminal; + struct ia_css_pipe *pipe = NULL; + struct ia_css_binary *binary = NULL; + int i; + uint32_t isys_stream_id; + bool early_polling = false; + + assert(stream != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_config_input_network() enter 0x%p:\n", stream); + + if (stream->config.continuous == true) { + if (stream->last_pipe->config.mode == IA_CSS_PIPE_MODE_CAPTURE) { + pipe = stream->last_pipe; + } else if (stream->last_pipe->config.mode == IA_CSS_PIPE_MODE_YUVPP) { + pipe = stream->last_pipe; + } else if (stream->last_pipe->config.mode == IA_CSS_PIPE_MODE_PREVIEW) { + pipe = stream->last_pipe->pipe_settings.preview.copy_pipe; + } else if (stream->last_pipe->config.mode == IA_CSS_PIPE_MODE_VIDEO) { + pipe = stream->last_pipe->pipe_settings.video.copy_pipe; + } + } else { + pipe = stream->last_pipe; + if (stream->last_pipe->config.mode == IA_CSS_PIPE_MODE_CAPTURE) { + /* + * We need to poll the ISYS HW in capture_indication itself + * for "non-continous" capture usecase for getting accurate + * isys frame capture timestamps. + * This is because the capturepipe propcessing takes longer + * to execute than the input system frame capture. + * 2401 specific + */ + early_polling = true; + } + } + + assert(pipe != NULL); + if (pipe == NULL) + return IA_CSS_ERR_INTERNAL_ERROR; + + if (pipe->pipeline.stages != NULL) + if (pipe->pipeline.stages->binary != NULL) + binary = pipe->pipeline.stages->binary; + + + + if (binary) { + /* this was being done in ifmtr in 2400. + * online and cont bypass the init_in_frameinfo_memory_defaults + * so need to do it here + */ + ia_css_get_crop_offsets(pipe, &binary->in_frame_info); + } + + /* get the SP thread id */ + rc = ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &sp_thread_id); + if (rc != true) + return IA_CSS_ERR_INTERNAL_ERROR; + /* get the target input terminal */ + sp_pipeline_input_terminal = &(sh_css_sp_group.pipe_io[sp_thread_id].input); + + for (i = 0; i < IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH; i++) { + /* initialization */ + memset((void*)(&isys_stream_descr), 0, sizeof(ia_css_isys_descr_t)); + sp_pipeline_input_terminal->context.virtual_input_system_stream[i].valid = 0; + sp_pipeline_input_terminal->ctrl.virtual_input_system_stream_cfg[i].valid = 0; + + if (!stream->config.isys_config[i].valid) + continue; + + /* translate the stream configuration to the Input System (2401) configuration */ + rc = sh_css_translate_stream_cfg_to_isys_stream_descr( + &(stream->config), + early_polling, + &(isys_stream_descr), i); + + if (stream->config.online) { + rc &= sh_css_translate_binary_info_to_input_system_output_port_attr( + binary, + &(isys_stream_descr)); + } + + if (rc != true) + return IA_CSS_ERR_INTERNAL_ERROR; + + isys_stream_id = ia_css_isys_generate_stream_id(sp_thread_id, i); + + /* create the virtual Input System (2401) */ + rc = ia_css_isys_stream_create( + &(isys_stream_descr), + &(sp_pipeline_input_terminal->context.virtual_input_system_stream[i]), + isys_stream_id); + if (rc != true) + return IA_CSS_ERR_INTERNAL_ERROR; + + /* calculate the configuration of the virtual Input System (2401) */ + rc = ia_css_isys_stream_calculate_cfg( + &(sp_pipeline_input_terminal->context.virtual_input_system_stream[i]), + &(isys_stream_descr), + &(sp_pipeline_input_terminal->ctrl.virtual_input_system_stream_cfg[i])); + if (rc != true) { + ia_css_isys_stream_destroy(&(sp_pipeline_input_terminal->context.virtual_input_system_stream[i])); + return IA_CSS_ERR_INTERNAL_ERROR; + } + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_config_input_network() leave:\n"); + + return IA_CSS_SUCCESS; +} + +static inline struct ia_css_pipe *stream_get_last_pipe( + struct ia_css_stream *stream) +{ + struct ia_css_pipe *last_pipe = NULL; + if (stream != NULL) + last_pipe = stream->last_pipe; + + return last_pipe; +} + +static inline struct ia_css_pipe *stream_get_copy_pipe( + struct ia_css_stream *stream) +{ + struct ia_css_pipe *copy_pipe = NULL; + struct ia_css_pipe *last_pipe = NULL; + enum ia_css_pipe_id pipe_id; + + last_pipe = stream_get_last_pipe(stream); + + if ((stream != NULL) && + (last_pipe != NULL) && + (stream->config.continuous)) { + + pipe_id = last_pipe->mode; + switch (pipe_id) { + case IA_CSS_PIPE_ID_PREVIEW: + copy_pipe = last_pipe->pipe_settings.preview.copy_pipe; + break; + case IA_CSS_PIPE_ID_VIDEO: + copy_pipe = last_pipe->pipe_settings.video.copy_pipe; + break; + default: + copy_pipe = NULL; + break; + } + } + + return copy_pipe; +} + +static inline struct ia_css_pipe *stream_get_target_pipe( + struct ia_css_stream *stream) +{ + struct ia_css_pipe *target_pipe; + + /* get the pipe that consumes the stream */ + if (stream->config.continuous) { + target_pipe = stream_get_copy_pipe(stream); + } else { + target_pipe = stream_get_last_pipe(stream); + } + + return target_pipe; +} + +static enum ia_css_err stream_csi_rx_helper( + struct ia_css_stream *stream, + enum ia_css_err (*func)(enum ia_css_csi2_port, uint32_t)) +{ + enum ia_css_err retval = IA_CSS_ERR_INTERNAL_ERROR; + uint32_t sp_thread_id, stream_id; + bool rc; + struct ia_css_pipe *target_pipe = NULL; + + if ((stream == NULL) || (stream->config.mode != IA_CSS_INPUT_MODE_BUFFERED_SENSOR)) + goto exit; + + target_pipe = stream_get_target_pipe(stream); + + if (target_pipe == NULL) + goto exit; + + rc = ia_css_pipeline_get_sp_thread_id( + ia_css_pipe_get_pipe_num(target_pipe), + &sp_thread_id); + + if (!rc) + goto exit; + + /* (un)register all valid "virtual isys streams" within the ia_css_stream */ + stream_id = 0; + do { + if (stream->config.isys_config[stream_id].valid) { + uint32_t isys_stream_id = ia_css_isys_generate_stream_id(sp_thread_id, stream_id); + retval = func(stream->config.source.port.port, isys_stream_id); + } + stream_id++; + } while ((retval == IA_CSS_SUCCESS) && + (stream_id < IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH)); + +exit: + return retval; +} + +static inline enum ia_css_err stream_register_with_csi_rx( + struct ia_css_stream *stream) +{ + return stream_csi_rx_helper(stream, ia_css_isys_csi_rx_register_stream); +} + +static inline enum ia_css_err stream_unregister_with_csi_rx( + struct ia_css_stream *stream) +{ + return stream_csi_rx_helper(stream, ia_css_isys_csi_rx_unregister_stream); +} +#endif + +#if WITH_PC_MONITORING +static struct task_struct *my_kthread; /* Handle for the monitoring thread */ +static int sh_binary_running; /* Enable sampling in the thread */ + +static void print_pc_histo(char *core_name, struct sh_css_pc_histogram *hist) +{ + unsigned i; + unsigned cnt_run = 0; + unsigned cnt_stall = 0; + + if (hist == NULL) + return; + + sh_css_print("%s histogram length = %d\n", core_name, hist->length); + sh_css_print("%s PC\trun\tstall\n", core_name); + + for (i = 0; i < hist->length; i++) { + if ((hist->run[i] == 0) && (hist->run[i] == hist->stall[i])) + continue; + sh_css_print("%s %d\t%d\t%d\n", + core_name, i, hist->run[i], hist->stall[i]); + cnt_run += hist->run[i]; + cnt_stall += hist->stall[i]; + } + + sh_css_print(" Statistics for %s, cnt_run = %d, cnt_stall = %d, " + "hist->length = %d\n", + core_name, cnt_run, cnt_stall, hist->length); +} + +static void print_pc_histogram(void) +{ + struct ia_css_binary_metrics *metrics; + + for (metrics = sh_css_metrics.binary_metrics; + metrics; + metrics = metrics->next) { + if (metrics->mode == IA_CSS_BINARY_MODE_PREVIEW || + metrics->mode == IA_CSS_BINARY_MODE_VF_PP) { + sh_css_print("pc_histogram for binary %d is SKIPPED\n", + metrics->id); + continue; + } + + sh_css_print(" pc_histogram for binary %d\n", metrics->id); + print_pc_histo(" ISP", &metrics->isp_histogram); + print_pc_histo(" SP", &metrics->sp_histogram); + sh_css_print("print_pc_histogram() done for binay->id = %d, " + "done.\n", metrics->id); + } + + sh_css_print("PC_MONITORING:print_pc_histogram() -- DONE\n"); +} + +static int pc_monitoring(void *data) +{ + int i = 0; + + (void)data; + while (true) { + if (sh_binary_running) { + sh_css_metrics_sample_pcs(); +#if MULTIPLE_SAMPLES + for (i = 0; i < NOF_SAMPLES; i++) + sh_css_metrics_sample_pcs(); +#endif + } + usleep_range(10, 50); + } + return 0; +} + +static void spying_thread_create(void) +{ + my_kthread = kthread_run(pc_monitoring, NULL, "sh_pc_monitor"); + sh_css_metrics_enable_pc_histogram(1); +} + +static void input_frame_info(struct ia_css_frame_info frame_info) +{ + sh_css_print("SH_CSS:input_frame_info() -- frame->info.res.width = %d, " + "frame->info.res.height = %d, format = %d\n", + frame_info.res.width, frame_info.res.height, frame_info.format); +} +#endif /* WITH_PC_MONITORING */ + +static void +start_binary(struct ia_css_pipe *pipe, + struct ia_css_binary *binary) +{ + struct ia_css_stream *stream; + + assert(pipe != NULL); + /* Acceleration uses firmware, the binary thus can be NULL */ + /* assert(binary != NULL); */ + + (void)binary; + +#if !defined(HAS_NO_INPUT_SYSTEM) + stream = pipe->stream; +#else + (void)pipe; + (void)stream; +#endif + + if (binary) + sh_css_metrics_start_binary(&binary->metrics); + +#if WITH_PC_MONITORING + sh_css_print("PC_MONITORING: %s() -- binary id = %d , " + "enable_dvs_envelope = %d\n", + __func__, binary->info->sp.id, + binary->info->sp.enable.dvs_envelope); + input_frame_info(binary->in_frame_info); + + if (binary && binary->info->sp.pipeline.mode == IA_CSS_BINARY_MODE_VIDEO) + sh_binary_running = true; +#endif + +#if !defined(HAS_NO_INPUT_SYSTEM) && !defined(USE_INPUT_SYSTEM_VERSION_2401) + if (stream->reconfigure_css_rx) { + ia_css_isys_rx_configure(&pipe->stream->csi_rx_config, + pipe->stream->config.mode); + stream->reconfigure_css_rx = false; + } +#endif +} + +/* start the copy function on the SP */ +static enum ia_css_err +start_copy_on_sp(struct ia_css_pipe *pipe, + struct ia_css_frame *out_frame) +{ + + (void)out_frame; + assert(pipe != NULL); + assert(pipe->stream != NULL); + + if ((pipe == NULL) || (pipe->stream == NULL)) + return IA_CSS_ERR_INVALID_ARGUMENTS; + +#if !defined(HAS_NO_INPUT_SYSTEM) && !defined(USE_INPUT_SYSTEM_VERSION_2401) + if (pipe->stream->reconfigure_css_rx) + ia_css_isys_rx_disable(); +#endif + + if (pipe->stream->config.input_config.format != IA_CSS_STREAM_FORMAT_BINARY_8) + return IA_CSS_ERR_INTERNAL_ERROR; + sh_css_sp_start_binary_copy(ia_css_pipe_get_pipe_num(pipe), out_frame, pipe->stream->config.pixels_per_clock == 2); + +#if !defined(HAS_NO_INPUT_SYSTEM) && !defined(USE_INPUT_SYSTEM_VERSION_2401) + if (pipe->stream->reconfigure_css_rx) { + ia_css_isys_rx_configure(&pipe->stream->csi_rx_config, pipe->stream->config.mode); + pipe->stream->reconfigure_css_rx = false; + } +#endif + + return IA_CSS_SUCCESS; +} + +void sh_css_binary_args_reset(struct sh_css_binary_args *args) +{ + unsigned int i; + +#ifndef ISP2401 + for (i = 0; i < NUM_VIDEO_TNR_FRAMES; i++) +#else + for (i = 0; i < NUM_TNR_FRAMES; i++) +#endif + args->tnr_frames[i] = NULL; + for (i = 0; i < MAX_NUM_VIDEO_DELAY_FRAMES; i++) + args->delay_frames[i] = NULL; + args->in_frame = NULL; + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) + args->out_frame[i] = NULL; + args->out_vf_frame = NULL; + args->copy_vf = false; + args->copy_output = true; + args->vf_downscale_log2 = 0; +} + +static void start_pipe( + struct ia_css_pipe *me, + enum sh_css_pipe_config_override copy_ovrd, + enum ia_css_input_mode input_mode) +{ +#if defined(HAS_NO_INPUT_SYSTEM) + (void)input_mode; +#endif + + IA_CSS_ENTER_PRIVATE("me = %p, copy_ovrd = %d, input_mode = %d", + me, copy_ovrd, input_mode); + + assert(me != NULL); /* all callers are in this file and call with non null argument */ + + sh_css_sp_init_pipeline(&me->pipeline, + me->mode, + (uint8_t)ia_css_pipe_get_pipe_num(me), + me->config.default_capture_config.enable_xnr != 0, + me->stream->config.pixels_per_clock == 2, + me->stream->config.continuous, + false, + me->required_bds_factor, + copy_ovrd, + input_mode, + &me->stream->config.metadata_config, +#ifndef ISP2401 + &me->stream->info.metadata_info +#else + &me->stream->info.metadata_info, +#endif +#if !defined(HAS_NO_INPUT_SYSTEM) +#ifndef ISP2401 + , (input_mode==IA_CSS_INPUT_MODE_MEMORY)? +#else + (input_mode == IA_CSS_INPUT_MODE_MEMORY) ? +#endif + (mipi_port_ID_t)0 : +#ifndef ISP2401 + me->stream->config.source.port.port +#else + me->stream->config.source.port.port, +#endif +#endif +#ifndef ISP2401 + ); +#else + &me->config.internal_frame_origin_bqs_on_sctbl, + me->stream->isp_params_configs); +#endif + + if (me->config.mode != IA_CSS_PIPE_MODE_COPY) { + struct ia_css_pipeline_stage *stage; + stage = me->pipeline.stages; + if (stage) { + me->pipeline.current_stage = stage; + start_binary(me, stage->binary); + } + } + IA_CSS_LEAVE_PRIVATE("void"); +} + +void +sh_css_invalidate_shading_tables(struct ia_css_stream *stream) +{ + int i; + assert(stream != NULL); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "sh_css_invalidate_shading_tables() enter:\n"); + + for (i=0; inum_pipes; i++) { + assert(stream->pipes[i] != NULL); + sh_css_pipe_free_shading_table(stream->pipes[i]); + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "sh_css_invalidate_shading_tables() leave: return_void\n"); +} + +#ifndef ISP2401 +static void +enable_interrupts(enum ia_css_irq_type irq_type) +{ +#ifdef USE_INPUT_SYSTEM_VERSION_2 + mipi_port_ID_t port; +#endif + bool enable_pulse = irq_type != IA_CSS_IRQ_TYPE_EDGE; + IA_CSS_ENTER_PRIVATE(""); + /* Enable IRQ on the SP which signals that SP goes to idle + * (aka ready state) */ + cnd_sp_irq_enable(SP0_ID, true); + /* Set the IRQ device 0 to either level or pulse */ + irq_enable_pulse(IRQ0_ID, enable_pulse); + + cnd_virq_enable_channel(virq_sp, true); + + /* Enable SW interrupt 0, this is used to signal ISYS events */ + cnd_virq_enable_channel( + (virq_id_t)(IRQ_SW_CHANNEL0_ID + IRQ_SW_CHANNEL_OFFSET), + true); + /* Enable SW interrupt 1, this is used to signal PSYS events */ + cnd_virq_enable_channel( + (virq_id_t)(IRQ_SW_CHANNEL1_ID + IRQ_SW_CHANNEL_OFFSET), + true); +#if !defined(HAS_IRQ_MAP_VERSION_2) + /* IRQ_SW_CHANNEL2_ID does not exist on 240x systems */ + cnd_virq_enable_channel( + (virq_id_t)(IRQ_SW_CHANNEL2_ID + IRQ_SW_CHANNEL_OFFSET), + true); + virq_clear_all(); +#endif + +#ifdef USE_INPUT_SYSTEM_VERSION_2 + for (port = 0; port < N_MIPI_PORT_ID; port++) + ia_css_isys_rx_enable_all_interrupts(port); +#endif + +#if defined(HRT_CSIM) + /* + * Enable IRQ on the SP which signals that SP goes to idle + * to get statistics for each binary + */ + cnd_isp_irq_enable(ISP0_ID, true); + cnd_virq_enable_channel(virq_isp, true); +#endif + IA_CSS_LEAVE_PRIVATE(""); +} + +#endif +#if defined(HAS_BL) +static bool sh_css_setup_blctrl_config(const struct ia_css_fw_info *fw, + const char *program, + ia_css_blctrl_cfg *blctrl_cfg) +{ + if((fw == NULL)||(blctrl_cfg == NULL)) + return false; + blctrl_cfg->bl_entry = 0; + blctrl_cfg->program_name = (char *)(program); + +#if !defined(C_RUN) && !defined(HRT_UNSCHED) + blctrl_cfg->ddr_data_offset = fw->blob.data_source; + blctrl_cfg->dmem_data_addr = fw->blob.data_target; + blctrl_cfg->dmem_bss_addr = fw->blob.bss_target; + blctrl_cfg->data_size = fw->blob.data_size ; + blctrl_cfg->bss_size = fw->blob.bss_size; + + blctrl_cfg->blctrl_state_dmem_addr = fw->info.bl.sw_state; + blctrl_cfg->blctrl_dma_cmd_list = fw->info.bl.dma_cmd_list; + blctrl_cfg->blctrl_nr_of_dma_cmds = fw->info.bl.num_dma_cmds; + + blctrl_cfg->code_size = fw->blob.size; + blctrl_cfg->code = fw->blob.code; + blctrl_cfg->bl_entry = fw->info.bl.bl_entry; /* entry function ptr on Bootloader */ +#endif + return true; +} +#endif +static bool sh_css_setup_spctrl_config(const struct ia_css_fw_info *fw, + const char * program, + ia_css_spctrl_cfg *spctrl_cfg) +{ + if((fw == NULL)||(spctrl_cfg == NULL)) + return false; + spctrl_cfg->sp_entry = 0; + spctrl_cfg->program_name = (char *)(program); + +#if !defined(C_RUN) && !defined(HRT_UNSCHED) + spctrl_cfg->ddr_data_offset = fw->blob.data_source; + spctrl_cfg->dmem_data_addr = fw->blob.data_target; + spctrl_cfg->dmem_bss_addr = fw->blob.bss_target; + spctrl_cfg->data_size = fw->blob.data_size ; + spctrl_cfg->bss_size = fw->blob.bss_size; + + spctrl_cfg->spctrl_config_dmem_addr = fw->info.sp.init_dmem_data; + spctrl_cfg->spctrl_state_dmem_addr = fw->info.sp.sw_state; + + spctrl_cfg->code_size = fw->blob.size; + spctrl_cfg->code = fw->blob.code; + spctrl_cfg->sp_entry = fw->info.sp.sp_entry; /* entry function ptr on SP */ +#endif + return true; +} +void +ia_css_unload_firmware(void) +{ + if (sh_css_num_binaries) + { + /* we have already loaded before so get rid of the old stuff */ + ia_css_binary_uninit(); + sh_css_unload_firmware(); + } + fw_explicitly_loaded = false; +} + +static void +ia_css_reset_defaults(struct sh_css* css) +{ + struct sh_css default_css; + + /* Reset everything to zero */ + memset(&default_css, 0, sizeof(default_css)); + + /* Initialize the non zero values*/ + default_css.check_system_idle = true; + default_css.num_cont_raw_frames = NUM_CONTINUOUS_FRAMES; + + /* All should be 0: but memset does it already. + * default_css.num_mipi_frames[N_CSI_PORTS] = 0; + */ + + default_css.irq_type = IA_CSS_IRQ_TYPE_EDGE; + + /*Set the defaults to the output */ + *css = default_css; +} + +bool +ia_css_check_firmware_version(const struct ia_css_fw *fw) +{ + bool retval = false; + + if (fw != NULL) { + retval = sh_css_check_firmware_version(fw->data); + } + return retval; +} + +enum ia_css_err +ia_css_load_firmware(const struct ia_css_env *env, + const struct ia_css_fw *fw) +{ + enum ia_css_err err; + + if (env == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + if (fw == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_load_firmware() enter\n"); + + ia_css_memory_access_init(&env->css_mem_env); + + /* make sure we initialize my_css */ + if ((my_css.malloc != env->cpu_mem_env.alloc) || + (my_css.free != env->cpu_mem_env.free) || + (my_css.flush != env->cpu_mem_env.flush) + ) + { + ia_css_reset_defaults(&my_css); + + my_css.malloc = env->cpu_mem_env.alloc; + my_css.free = env->cpu_mem_env.free; + my_css.flush = env->cpu_mem_env.flush; + } + + ia_css_unload_firmware(); /* in case we are called twice */ + err = sh_css_load_firmware(fw->data, fw->bytes); + if (err == IA_CSS_SUCCESS) { + err = ia_css_binary_init_infos(); + if (err == IA_CSS_SUCCESS) + fw_explicitly_loaded = true; + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_load_firmware() leave \n"); + return err; +} + +enum ia_css_err +ia_css_init(const struct ia_css_env *env, + const struct ia_css_fw *fw, + uint32_t mmu_l1_base, + enum ia_css_irq_type irq_type) +{ + enum ia_css_err err; + ia_css_spctrl_cfg spctrl_cfg; +#if defined(HAS_BL) + ia_css_blctrl_cfg blctrl_cfg; +#endif +#if defined(HAS_SEC_SP) + ia_css_spctrl_cfg sp1ctrl_cfg; +#endif /* HAS_SEC_SP */ + + void *(*malloc_func)(size_t size, bool zero_mem); + void (*free_func)(void *ptr); + void (*flush_func)(struct ia_css_acc_fw *fw); + hrt_data select, enable; + + /** + * The C99 standard does not specify the exact object representation of structs; + * the representation is compiler dependent. + * + * The structs that are communicated between host and SP/ISP should have the + * exact same object representation. The compiler that is used to compile the + * firmware is hivecc. + * + * To check if a different compiler, used to compile a host application, uses + * another object representation, macros are defined specifying the size of + * the structs as expected by the firmware. + * + * A host application shall verify that a sizeof( ) of the struct is equal to + * the SIZE_OF_XXX macro of the corresponding struct. If they are not + * equal, functionality will break. + */ + /* Check struct sh_css_ddr_address_map */ + COMPILATION_ERROR_IF( sizeof(struct sh_css_ddr_address_map) != SIZE_OF_SH_CSS_DDR_ADDRESS_MAP_STRUCT ); + /* Check struct host_sp_queues */ + COMPILATION_ERROR_IF( sizeof(struct host_sp_queues) != SIZE_OF_HOST_SP_QUEUES_STRUCT ); + COMPILATION_ERROR_IF( sizeof(struct ia_css_circbuf_desc_s) != SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT ); + COMPILATION_ERROR_IF( sizeof(struct ia_css_circbuf_elem_s) != SIZE_OF_IA_CSS_CIRCBUF_ELEM_S_STRUCT ); + + /* Check struct host_sp_communication */ + COMPILATION_ERROR_IF( sizeof(struct host_sp_communication) != SIZE_OF_HOST_SP_COMMUNICATION_STRUCT ); + COMPILATION_ERROR_IF( sizeof(struct sh_css_event_irq_mask) != SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT ); + + /* Check struct sh_css_hmm_buffer */ + COMPILATION_ERROR_IF( sizeof(struct sh_css_hmm_buffer) != SIZE_OF_SH_CSS_HMM_BUFFER_STRUCT ); + COMPILATION_ERROR_IF( sizeof(struct ia_css_isp_3a_statistics) != SIZE_OF_IA_CSS_ISP_3A_STATISTICS_STRUCT ); + COMPILATION_ERROR_IF( sizeof(struct ia_css_isp_dvs_statistics) != SIZE_OF_IA_CSS_ISP_DVS_STATISTICS_STRUCT ); + COMPILATION_ERROR_IF( sizeof(struct ia_css_metadata) != SIZE_OF_IA_CSS_METADATA_STRUCT ); + + /* Check struct ia_css_init_dmem_cfg */ + COMPILATION_ERROR_IF( sizeof(struct ia_css_sp_init_dmem_cfg) != SIZE_OF_IA_CSS_SP_INIT_DMEM_CFG_STRUCT ); + + if (fw == NULL && !fw_explicitly_loaded) + return IA_CSS_ERR_INVALID_ARGUMENTS; + if (env == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + sh_css_printf = env->print_env.debug_print; + + IA_CSS_ENTER("void"); + + malloc_func = env->cpu_mem_env.alloc; + free_func = env->cpu_mem_env.free; + flush_func = env->cpu_mem_env.flush; + + pipe_global_init(); + ia_css_pipeline_init(); + ia_css_queue_map_init(); + + ia_css_device_access_init(&env->hw_access_env); + ia_css_memory_access_init(&env->css_mem_env); + + select = gpio_reg_load(GPIO0_ID, _gpio_block_reg_do_select) + & (~GPIO_FLASH_PIN_MASK); + enable = gpio_reg_load(GPIO0_ID, _gpio_block_reg_do_e) + | GPIO_FLASH_PIN_MASK; + sh_css_mmu_set_page_table_base_index(mmu_l1_base); +#ifndef ISP2401 + my_css_save.mmu_base = mmu_l1_base; +#else + ia_css_save_mmu_base_addr(mmu_l1_base); +#endif + + if (malloc_func == NULL || free_func == NULL) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + ia_css_reset_defaults(&my_css); + + my_css_save.driver_env = *env; + my_css.malloc = malloc_func; + my_css.free = free_func; + my_css.flush = flush_func; + + err = ia_css_rmgr_init(); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR(err); + return err; + } + +#ifndef ISP2401 + IA_CSS_LOG("init: %d", my_css_save_initialized); +#else + ia_css_save_restore_data_init(); +#endif + +#ifndef ISP2401 + if (!my_css_save_initialized) + { + my_css_save_initialized = true; + my_css_save.mode = sh_css_mode_working; + memset(my_css_save.stream_seeds, 0, sizeof(struct sh_css_stream_seed) * MAX_ACTIVE_STREAMS); + IA_CSS_LOG("init: %d mode=%d", my_css_save_initialized, my_css_save.mode); + } +#endif + mipi_init(); + +#ifndef ISP2401 + /* In case this has been programmed already, update internal + data structure ... DEPRECATED */ + my_css.page_table_base_index = mmu_get_page_table_base_index(MMU0_ID); + +#endif + my_css.irq_type = irq_type; +#ifndef ISP2401 + my_css_save.irq_type = irq_type; +#else + ia_css_save_irq_type(irq_type); +#endif + enable_interrupts(my_css.irq_type); + + /* configure GPIO to output mode */ + gpio_reg_store(GPIO0_ID, _gpio_block_reg_do_select, select); + gpio_reg_store(GPIO0_ID, _gpio_block_reg_do_e, enable); + gpio_reg_store(GPIO0_ID, _gpio_block_reg_do_0, 0); + + err = ia_css_refcount_init(REFCOUNT_SIZE); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR(err); + return err; + } + err = sh_css_params_init(); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR(err); + return err; + } + if (fw) + { + ia_css_unload_firmware(); /* in case we already had firmware loaded */ + err = sh_css_load_firmware(fw->data, fw->bytes); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR(err); + return err; + } + err = ia_css_binary_init_infos(); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR(err); + return err; + } + fw_explicitly_loaded = false; +#ifndef ISP2401 + my_css_save.loaded_fw = (struct ia_css_fw *)fw; +#endif + } + if(!sh_css_setup_spctrl_config(&sh_css_sp_fw,SP_PROG_NAME,&spctrl_cfg)) + return IA_CSS_ERR_INTERNAL_ERROR; + + err = ia_css_spctrl_load_fw(SP0_ID, &spctrl_cfg); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR(err); + return err; + } +#if defined(HAS_SEC_SP) + if(!sh_css_setup_spctrl_config(&sh_css_sp1_fw,SP1_PROG_NAME,&sp1ctrl_cfg)) + return IA_CSS_ERR_INTERNAL_ERROR; + err = ia_css_spctrl_load_fw(SP1_ID, &sp1ctrl_cfg); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR(err); + return err; + } +#endif /* HAS_SEC_SP */ + +#if defined(HAS_BL) + if (!sh_css_setup_blctrl_config(&sh_css_bl_fw, BL_PROG_NAME, &blctrl_cfg)) + return IA_CSS_ERR_INTERNAL_ERROR; + err = ia_css_blctrl_load_fw(&blctrl_cfg); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR(err); + return err; + } +#if defined(HAS_SEC_SP) + err = ia_css_blctrl_add_target_fw_info(&sh_css_sp1_fw, IA_CSS_SP1, + get_sp_code_addr(SP1_ID)); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR(err); + return err; + } +#endif +#ifdef ISP2401 + err = ia_css_blctrl_add_target_fw_info(&sh_css_sp_fw, IA_CSS_SP0, + get_sp_code_addr(SP0_ID)); + +#endif + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR(err); + return err; + } +#endif /* HAS_BL */ + +#if defined(HRT_CSIM) + /** + * In compiled simulator context include debug support by default. + * In all other cases (e.g. Android phone), the user (e.g. driver) + * must explicitly enable debug support by calling this function. + */ + if (!ia_css_debug_mode_init()) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INTERNAL_ERROR); + return IA_CSS_ERR_INTERNAL_ERROR; + } +#endif + +#if WITH_PC_MONITORING + if (!thread_alive) { + thread_alive++; + sh_css_print("PC_MONITORING: %s() -- create thread DISABLED\n", + __func__); + spying_thread_create(); + } +#endif + if (!sh_css_hrt_system_is_idle()) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_SYSTEM_NOT_IDLE); + return IA_CSS_ERR_SYSTEM_NOT_IDLE; + } + /* can be called here, queuing works, but: + - when sp is started later, it will wipe queued items + so for now we leave it for later and make sure + updates are not called to frequently. + sh_css_init_buffer_queues(); + */ + +#if defined(HAS_INPUT_SYSTEM_VERSION_2) && defined(HAS_INPUT_SYSTEM_VERSION_2401) +#if defined(USE_INPUT_SYSTEM_VERSION_2) + gp_device_reg_store(GP_DEVICE0_ID, _REG_GP_SWITCH_ISYS2401_ADDR, 0); +#elif defined (USE_INPUT_SYSTEM_VERSION_2401) + gp_device_reg_store(GP_DEVICE0_ID, _REG_GP_SWITCH_ISYS2401_ADDR, 1); +#endif +#endif + +#if !defined(HAS_NO_INPUT_SYSTEM) + dma_set_max_burst_size(DMA0_ID, HIVE_DMA_BUS_DDR_CONN, + ISP_DMA_MAX_BURST_LENGTH); + + if(ia_css_isys_init() != INPUT_SYSTEM_ERR_NO_ERROR) + err = IA_CSS_ERR_INVALID_ARGUMENTS; +#endif + + sh_css_params_map_and_store_default_gdc_lut(); + + IA_CSS_LEAVE_ERR(err); + return err; +} + +enum ia_css_err ia_css_suspend(void) +{ + int i; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_suspend() enter\n"); + my_css_save.mode = sh_css_mode_suspend; + for(i=0;i unloading seed %d (%p)\n", i, my_css_save.stream_seeds[i].stream); + ia_css_stream_unload(my_css_save.stream_seeds[i].stream); + } + my_css_save.mode = sh_css_mode_working; + ia_css_stop_sp(); + ia_css_uninit(); + for(i=0;i after 1: seed %d (%p)\n", i, my_css_save.stream_seeds[i].stream); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_suspend() leave\n"); + return(IA_CSS_SUCCESS); +} + +enum ia_css_err +ia_css_resume(void) +{ + int i, j; + enum ia_css_err err; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_resume() enter: void\n"); + + err = ia_css_init(&(my_css_save.driver_env), my_css_save.loaded_fw, my_css_save.mmu_base, my_css_save.irq_type); + if (err != IA_CSS_SUCCESS) + return(err); + err = ia_css_start_sp(); + if (err != IA_CSS_SUCCESS) + return(err); + my_css_save.mode = sh_css_mode_resume; + for(i=0;i seed stream %p\n", my_css_save.stream_seeds[i].stream); + if (my_css_save.stream_seeds[i].stream != NULL) + { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "==*> loading seed %d\n", i); + err = ia_css_stream_load(my_css_save.stream_seeds[i].stream); + if (err != IA_CSS_SUCCESS) + { + if (i) + for(j=0;j 0 && my_css.malloc) + return my_css.malloc(size, false); + return NULL; +} + +void * +sh_css_calloc_ex(size_t N, size_t size, const char *caller_func, int caller_line) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sh_css_calloc() enter: N=%d, size=%d\n",N,size); + (void)caller_func; + (void)caller_line; + if (size > 0 && my_css.malloc) + return my_css.malloc(N*size, true); + return NULL; +} + +void +sh_css_free_ex(void *ptr, const char *caller_func, int caller_line) +{ + IA_CSS_ENTER_PRIVATE("ptr = %p", ptr); + (void)caller_func; + (void)caller_line; + if (ptr && my_css.free) + my_css.free(ptr); + IA_CSS_LEAVE_PRIVATE("void"); +} + +/* For Acceleration API: Flush FW (shared buffer pointer) arguments */ +void +sh_css_flush(struct ia_css_acc_fw *fw) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sh_css_flush() enter:\n"); + if ((fw != NULL) && (my_css.flush != NULL)) + my_css.flush(fw); +} + +/* Mapping sp threads. Currently, this is done when a stream is created and + * pipelines are ready to be converted to sp pipelines. Be careful if you are + * doing it from stream_create since we could run out of sp threads due to + * allocation on inactive pipelines. */ +static enum ia_css_err +map_sp_threads(struct ia_css_stream *stream, bool map) +{ + struct ia_css_pipe *main_pipe = NULL; + struct ia_css_pipe *copy_pipe = NULL; + struct ia_css_pipe *capture_pipe = NULL; + struct ia_css_pipe *acc_pipe = NULL; + enum ia_css_err err = IA_CSS_SUCCESS; + enum ia_css_pipe_id pipe_id; + + assert(stream != NULL); + IA_CSS_ENTER_PRIVATE("stream = %p, map = %p", stream, map); + + if (stream == NULL) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + main_pipe = stream->last_pipe; + pipe_id = main_pipe->mode; + + ia_css_pipeline_map(main_pipe->pipe_num, map); + + switch (pipe_id) { + case IA_CSS_PIPE_ID_PREVIEW: + copy_pipe = main_pipe->pipe_settings.preview.copy_pipe; + capture_pipe = main_pipe->pipe_settings.preview.capture_pipe; + acc_pipe = main_pipe->pipe_settings.preview.acc_pipe; + break; + + case IA_CSS_PIPE_ID_VIDEO: + copy_pipe = main_pipe->pipe_settings.video.copy_pipe; + capture_pipe = main_pipe->pipe_settings.video.capture_pipe; + break; + + case IA_CSS_PIPE_ID_CAPTURE: + case IA_CSS_PIPE_ID_ACC: + default: + break; + } + + if (acc_pipe) { + ia_css_pipeline_map(acc_pipe->pipe_num, map); + } + + if(capture_pipe) { + ia_css_pipeline_map(capture_pipe->pipe_num, map); + } + + /* Firmware expects copy pipe to be the last pipe mapped. (if needed) */ + if(copy_pipe) { + ia_css_pipeline_map(copy_pipe->pipe_num, map); + } + /* DH regular multi pipe - not continuous mode: map the next pipes too */ + if (!stream->config.continuous) { + int i; + for (i = 1; i < stream->num_pipes; i++) + ia_css_pipeline_map(stream->pipes[i]->pipe_num, map); + } + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +/* creates a host pipeline skeleton for all pipes in a stream. Called during + * stream_create. */ +static enum ia_css_err +create_host_pipeline_structure(struct ia_css_stream *stream) +{ + struct ia_css_pipe *copy_pipe = NULL, *capture_pipe = NULL; + struct ia_css_pipe *acc_pipe = NULL; + enum ia_css_pipe_id pipe_id; + struct ia_css_pipe *main_pipe = NULL; + enum ia_css_err err = IA_CSS_SUCCESS; + unsigned int copy_pipe_delay = 0, + capture_pipe_delay = 0; + + assert(stream != NULL); + IA_CSS_ENTER_PRIVATE("stream = %p", stream); + + if (stream == NULL) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + main_pipe = stream->last_pipe; + assert(main_pipe != NULL); + if (main_pipe == NULL) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + pipe_id = main_pipe->mode; + + switch (pipe_id) { + case IA_CSS_PIPE_ID_PREVIEW: + copy_pipe = main_pipe->pipe_settings.preview.copy_pipe; + copy_pipe_delay = main_pipe->dvs_frame_delay; + capture_pipe = main_pipe->pipe_settings.preview.capture_pipe; + capture_pipe_delay = IA_CSS_FRAME_DELAY_0; + acc_pipe = main_pipe->pipe_settings.preview.acc_pipe; + err = ia_css_pipeline_create(&main_pipe->pipeline, main_pipe->mode, main_pipe->pipe_num, main_pipe->dvs_frame_delay); + break; + + case IA_CSS_PIPE_ID_VIDEO: + copy_pipe = main_pipe->pipe_settings.video.copy_pipe; + copy_pipe_delay = main_pipe->dvs_frame_delay; + capture_pipe = main_pipe->pipe_settings.video.capture_pipe; + capture_pipe_delay = IA_CSS_FRAME_DELAY_0; + err = ia_css_pipeline_create(&main_pipe->pipeline, main_pipe->mode, main_pipe->pipe_num, main_pipe->dvs_frame_delay); + break; + + case IA_CSS_PIPE_ID_CAPTURE: + capture_pipe = main_pipe; + capture_pipe_delay = main_pipe->dvs_frame_delay; + break; + + case IA_CSS_PIPE_ID_YUVPP: + err = ia_css_pipeline_create(&main_pipe->pipeline, main_pipe->mode, + main_pipe->pipe_num, main_pipe->dvs_frame_delay); + break; + + case IA_CSS_PIPE_ID_ACC: + err = ia_css_pipeline_create(&main_pipe->pipeline, main_pipe->mode, main_pipe->pipe_num, main_pipe->dvs_frame_delay); + break; + + default: + err = IA_CSS_ERR_INVALID_ARGUMENTS; + } + + if ((IA_CSS_SUCCESS == err) && copy_pipe) { + err = ia_css_pipeline_create(©_pipe->pipeline, + copy_pipe->mode, + copy_pipe->pipe_num, + copy_pipe_delay); + } + + if ((IA_CSS_SUCCESS == err) && capture_pipe) { + err = ia_css_pipeline_create(&capture_pipe->pipeline, + capture_pipe->mode, + capture_pipe->pipe_num, + capture_pipe_delay); + } + + if ((IA_CSS_SUCCESS == err) && acc_pipe) { + err = ia_css_pipeline_create(&acc_pipe->pipeline, acc_pipe->mode, acc_pipe->pipe_num, main_pipe->dvs_frame_delay); + } + + /* DH regular multi pipe - not continuous mode: create the next pipelines too */ + if (!stream->config.continuous) { + int i; + for (i = 1; i < stream->num_pipes && IA_CSS_SUCCESS == err; i++) { + main_pipe = stream->pipes[i]; + err = ia_css_pipeline_create(&main_pipe->pipeline, + main_pipe->mode, + main_pipe->pipe_num, + main_pipe->dvs_frame_delay); + } + } + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +/* creates a host pipeline for all pipes in a stream. Called during + * stream_start. */ +static enum ia_css_err +create_host_pipeline(struct ia_css_stream *stream) +{ + struct ia_css_pipe *copy_pipe = NULL, *capture_pipe = NULL; + struct ia_css_pipe *acc_pipe = NULL; + enum ia_css_pipe_id pipe_id; + struct ia_css_pipe *main_pipe = NULL; + enum ia_css_err err = IA_CSS_SUCCESS; + unsigned max_input_width = 0; + + IA_CSS_ENTER_PRIVATE("stream = %p", stream); + if (stream == NULL) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + main_pipe = stream->last_pipe; + pipe_id = main_pipe->mode; + + /* No continuous frame allocation for capture pipe. It uses the + * "main" pipe's frames. */ + if ((pipe_id == IA_CSS_PIPE_ID_PREVIEW) || + (pipe_id == IA_CSS_PIPE_ID_VIDEO)) { + /* About pipe_id == IA_CSS_PIPE_ID_PREVIEW && stream->config.mode != IA_CSS_INPUT_MODE_MEMORY: + * The original condition pipe_id == IA_CSS_PIPE_ID_PREVIEW is too strong. E.g. in SkyCam (with memory + * based input frames) there is no continuous mode and thus no need for allocated continuous frames + * This is not only for SkyCam but for all preview cases that use DDR based input frames. For this + * reason the stream->config.mode != IA_CSS_INPUT_MODE_MEMORY has beed added. + */ + if (stream->config.continuous || + (pipe_id == IA_CSS_PIPE_ID_PREVIEW && stream->config.mode != IA_CSS_INPUT_MODE_MEMORY)) { + err = alloc_continuous_frames(main_pipe, true); + if (err != IA_CSS_SUCCESS) + goto ERR; + } + +#ifdef HRT_CSIM + if(main_pipe->continuous_frames[0]) + ia_css_frame_zero(main_pipe->continuous_frames[0]); +#endif + } + +#if defined(USE_INPUT_SYSTEM_VERSION_2) + /* old isys: need to allocate_mipi_frames() even in IA_CSS_PIPE_MODE_COPY */ + if (pipe_id != IA_CSS_PIPE_ID_ACC) { + err = allocate_mipi_frames(main_pipe, &stream->info); + if (err != IA_CSS_SUCCESS) + goto ERR; + } +#elif defined(USE_INPUT_SYSTEM_VERSION_2401) + if ((pipe_id != IA_CSS_PIPE_ID_ACC) && + (main_pipe->config.mode != IA_CSS_PIPE_MODE_COPY)) { + err = allocate_mipi_frames(main_pipe, &stream->info); + if (err != IA_CSS_SUCCESS) + goto ERR; + } +#endif + + switch (pipe_id) { + case IA_CSS_PIPE_ID_PREVIEW: + copy_pipe = main_pipe->pipe_settings.preview.copy_pipe; + capture_pipe = main_pipe->pipe_settings.preview.capture_pipe; + acc_pipe = main_pipe->pipe_settings.preview.acc_pipe; + max_input_width = + main_pipe->pipe_settings.preview.preview_binary.info->sp.input.max_width; + + err = create_host_preview_pipeline(main_pipe); + if (err != IA_CSS_SUCCESS) + goto ERR; + + break; + + case IA_CSS_PIPE_ID_VIDEO: + copy_pipe = main_pipe->pipe_settings.video.copy_pipe; + capture_pipe = main_pipe->pipe_settings.video.capture_pipe; + max_input_width = + main_pipe->pipe_settings.video.video_binary.info->sp.input.max_width; + + err = create_host_video_pipeline(main_pipe); + if (err != IA_CSS_SUCCESS) + goto ERR; + + break; + + case IA_CSS_PIPE_ID_CAPTURE: + capture_pipe = main_pipe; + + break; + + case IA_CSS_PIPE_ID_YUVPP: + err = create_host_yuvpp_pipeline(main_pipe); + if (err != IA_CSS_SUCCESS) + goto ERR; + + break; + + case IA_CSS_PIPE_ID_ACC: + err = create_host_acc_pipeline(main_pipe); + if (err != IA_CSS_SUCCESS) + goto ERR; + + break; + default: + err = IA_CSS_ERR_INVALID_ARGUMENTS; + } + if (err != IA_CSS_SUCCESS) + goto ERR; + + if(copy_pipe) { + err = create_host_copy_pipeline(copy_pipe, max_input_width, + main_pipe->continuous_frames[0]); + if (err != IA_CSS_SUCCESS) + goto ERR; + } + + if(capture_pipe) { + err = create_host_capture_pipeline(capture_pipe); + if (err != IA_CSS_SUCCESS) + goto ERR; + } + + if (acc_pipe) { + err = create_host_acc_pipeline(acc_pipe); + if (err != IA_CSS_SUCCESS) + goto ERR; + } + + /* DH regular multi pipe - not continuous mode: create the next pipelines too */ + if (!stream->config.continuous) { + int i; + for (i = 1; i < stream->num_pipes && IA_CSS_SUCCESS == err; i++) { + switch (stream->pipes[i]->mode) { + case IA_CSS_PIPE_ID_PREVIEW: + err = create_host_preview_pipeline(stream->pipes[i]); + break; + case IA_CSS_PIPE_ID_VIDEO: + err = create_host_video_pipeline(stream->pipes[i]); + break; + case IA_CSS_PIPE_ID_CAPTURE: + err = create_host_capture_pipeline(stream->pipes[i]); + break; + case IA_CSS_PIPE_ID_YUVPP: + err = create_host_yuvpp_pipeline(stream->pipes[i]); + break; + case IA_CSS_PIPE_ID_ACC: + err = create_host_acc_pipeline(stream->pipes[i]); + break; + default: + err = IA_CSS_ERR_INVALID_ARGUMENTS; + } + if (err != IA_CSS_SUCCESS) + goto ERR; + } + } + +ERR: + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static enum ia_css_err +init_pipe_defaults(enum ia_css_pipe_mode mode, + struct ia_css_pipe *pipe, + bool copy_pipe) +{ + static struct ia_css_pipe default_pipe = IA_CSS_DEFAULT_PIPE; + static struct ia_css_preview_settings prev = IA_CSS_DEFAULT_PREVIEW_SETTINGS; + static struct ia_css_capture_settings capt = IA_CSS_DEFAULT_CAPTURE_SETTINGS; + static struct ia_css_video_settings video = IA_CSS_DEFAULT_VIDEO_SETTINGS; + static struct ia_css_yuvpp_settings yuvpp = IA_CSS_DEFAULT_YUVPP_SETTINGS; + + if (pipe == NULL) { + IA_CSS_ERROR("NULL pipe parameter"); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + /* Initialize pipe to pre-defined defaults */ + *pipe = default_pipe; + + /* TODO: JB should not be needed, but temporary backward reference */ + switch (mode) { + case IA_CSS_PIPE_MODE_PREVIEW: + pipe->mode = IA_CSS_PIPE_ID_PREVIEW; + pipe->pipe_settings.preview = prev; + break; + case IA_CSS_PIPE_MODE_CAPTURE: + if (copy_pipe) { + pipe->mode = IA_CSS_PIPE_ID_COPY; + } else { + pipe->mode = IA_CSS_PIPE_ID_CAPTURE; + } + pipe->pipe_settings.capture = capt; + break; + case IA_CSS_PIPE_MODE_VIDEO: + pipe->mode = IA_CSS_PIPE_ID_VIDEO; + pipe->pipe_settings.video = video; + break; + case IA_CSS_PIPE_MODE_ACC: + pipe->mode = IA_CSS_PIPE_ID_ACC; + break; + case IA_CSS_PIPE_MODE_COPY: + pipe->mode = IA_CSS_PIPE_ID_CAPTURE; + break; + case IA_CSS_PIPE_MODE_YUVPP: + pipe->mode = IA_CSS_PIPE_ID_YUVPP; + pipe->pipe_settings.yuvpp = yuvpp; + break; + default: + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + return IA_CSS_SUCCESS; +} + +static void +pipe_global_init(void) +{ + uint8_t i; + + my_css.pipe_counter = 0; + for (i = 0; i < IA_CSS_PIPELINE_NUM_MAX; i++) { + my_css.all_pipes[i] = NULL; + } +} + +static enum ia_css_err +pipe_generate_pipe_num(const struct ia_css_pipe *pipe, unsigned int *pipe_number) +{ + const uint8_t INVALID_PIPE_NUM = (uint8_t)~(0); + uint8_t pipe_num = INVALID_PIPE_NUM; + uint8_t i; + + if (pipe == NULL) { + IA_CSS_ERROR("NULL pipe parameter"); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + /* Assign a new pipe_num .... search for empty place */ + for (i = 0; i < IA_CSS_PIPELINE_NUM_MAX; i++) { + if (my_css.all_pipes[i] == NULL) { + /*position is reserved */ + my_css.all_pipes[i] = (struct ia_css_pipe *)pipe; + pipe_num = i; + break; + } + } + if (pipe_num == INVALID_PIPE_NUM) { + /* Max number of pipes already allocated */ + IA_CSS_ERROR("Max number of pipes already created"); + return IA_CSS_ERR_RESOURCE_EXHAUSTED; + } + + my_css.pipe_counter++; + + IA_CSS_LOG("pipe_num (%d)", pipe_num); + + *pipe_number = pipe_num; + return IA_CSS_SUCCESS; +} + +static void +pipe_release_pipe_num(unsigned int pipe_num) +{ + my_css.all_pipes[pipe_num] = NULL; + my_css.pipe_counter--; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "pipe_release_pipe_num (%d)\n", pipe_num); +} + +static enum ia_css_err +create_pipe(enum ia_css_pipe_mode mode, + struct ia_css_pipe **pipe, + bool copy_pipe) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_pipe *me; + + if (pipe == NULL) { + IA_CSS_ERROR("NULL pipe parameter"); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + me = sh_css_malloc(sizeof(*me)); + if (!me) + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + + err = init_pipe_defaults(mode, me, copy_pipe); + if (err != IA_CSS_SUCCESS) { + sh_css_free(me); + return err; + } + + err = pipe_generate_pipe_num(me, &(me->pipe_num)); + if (err != IA_CSS_SUCCESS) { + sh_css_free(me); + return err; + } + + *pipe = me; + return IA_CSS_SUCCESS; +} + +struct ia_css_pipe * +find_pipe_by_num(uint32_t pipe_num) +{ + unsigned int i; + for (i = 0; i < IA_CSS_PIPELINE_NUM_MAX; i++){ + if (my_css.all_pipes[i] && + ia_css_pipe_get_pipe_num(my_css.all_pipes[i]) == pipe_num) { + return my_css.all_pipes[i]; + } + } + return NULL; +} + +static void sh_css_pipe_free_acc_binaries ( + struct ia_css_pipe *pipe) +{ + struct ia_css_pipeline *pipeline; + struct ia_css_pipeline_stage *stage; + + assert(pipe != NULL); + if (pipe == NULL) { + IA_CSS_ERROR("NULL input pointer"); + return; + } + pipeline = &pipe->pipeline; + + /* loop through the stages and unload them */ + for (stage = pipeline->stages; stage; stage = stage->next) { + struct ia_css_fw_info *firmware = (struct ia_css_fw_info *) + stage->firmware; + if (firmware) + ia_css_pipe_unload_extension(pipe, firmware); + } +} + +enum ia_css_err +ia_css_pipe_destroy(struct ia_css_pipe *pipe) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + IA_CSS_ENTER("pipe = %p", pipe); + + if (pipe == NULL) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + if (pipe->stream != NULL) { + IA_CSS_LOG("ia_css_stream_destroy not called!"); + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + switch (pipe->config.mode) { + case IA_CSS_PIPE_MODE_PREVIEW: + /* need to take into account that this function is also called + on the internal copy pipe */ + if (pipe->mode == IA_CSS_PIPE_ID_PREVIEW) { + ia_css_frame_free_multiple(NUM_CONTINUOUS_FRAMES, + pipe->continuous_frames); + ia_css_metadata_free_multiple(NUM_CONTINUOUS_FRAMES, + pipe->cont_md_buffers); + if (pipe->pipe_settings.preview.copy_pipe) { + err = ia_css_pipe_destroy(pipe->pipe_settings.preview.copy_pipe); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_pipe_destroy(): " + "destroyed internal copy pipe err=%d\n", err); + } + } + break; + case IA_CSS_PIPE_MODE_VIDEO: + if (pipe->mode == IA_CSS_PIPE_ID_VIDEO) { + ia_css_frame_free_multiple(NUM_CONTINUOUS_FRAMES, + pipe->continuous_frames); + ia_css_metadata_free_multiple(NUM_CONTINUOUS_FRAMES, + pipe->cont_md_buffers); + if (pipe->pipe_settings.video.copy_pipe) { + err = ia_css_pipe_destroy(pipe->pipe_settings.video.copy_pipe); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_pipe_destroy(): " + "destroyed internal copy pipe err=%d\n", err); + } + } +#ifndef ISP2401 + ia_css_frame_free_multiple(NUM_VIDEO_TNR_FRAMES, pipe->pipe_settings.video.tnr_frames); +#else + ia_css_frame_free_multiple(NUM_TNR_FRAMES, pipe->pipe_settings.video.tnr_frames); +#endif + ia_css_frame_free_multiple(MAX_NUM_VIDEO_DELAY_FRAMES, pipe->pipe_settings.video.delay_frames); + break; + case IA_CSS_PIPE_MODE_CAPTURE: + ia_css_frame_free_multiple(MAX_NUM_VIDEO_DELAY_FRAMES, pipe->pipe_settings.capture.delay_frames); + break; + case IA_CSS_PIPE_MODE_ACC: + sh_css_pipe_free_acc_binaries(pipe); + break; + case IA_CSS_PIPE_MODE_COPY: + break; + case IA_CSS_PIPE_MODE_YUVPP: + break; + } + +#ifndef ISP2401 + if (pipe->scaler_pp_lut != mmgr_NULL) { + mmgr_free(pipe->scaler_pp_lut); + pipe->scaler_pp_lut = mmgr_NULL; + } +#else + sh_css_params_free_gdc_lut(pipe->scaler_pp_lut); + pipe->scaler_pp_lut = mmgr_NULL; +#endif + + my_css.active_pipes[ia_css_pipe_get_pipe_num(pipe)] = NULL; + sh_css_pipe_free_shading_table(pipe); + + ia_css_pipeline_destroy(&pipe->pipeline); + pipe_release_pipe_num(ia_css_pipe_get_pipe_num(pipe)); + + /* Temporarily, not every sh_css_pipe has an acc_extension. */ + if (pipe->config.acc_extension) { + ia_css_pipe_unload_extension(pipe, pipe->config.acc_extension); + } + sh_css_free(pipe); + IA_CSS_LEAVE("err = %d", err); + return err; +} + +void +ia_css_uninit(void) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_uninit() enter: void\n"); +#if WITH_PC_MONITORING + sh_css_print("PC_MONITORING: %s() -- started\n", __func__); + print_pc_histogram(); +#endif + + sh_css_params_free_default_gdc_lut(); + + + /* TODO: JB: implement decent check and handling of freeing mipi frames */ + //assert(ref_count_mipi_allocation == 0); //mipi frames are not freed + /* cleanup generic data */ + sh_css_params_uninit(); + ia_css_refcount_uninit(); + + ia_css_rmgr_uninit(); + +#if !defined(HAS_NO_INPUT_FORMATTER) + /* needed for reprogramming the inputformatter after power cycle of css */ + ifmtr_set_if_blocking_mode_reset = true; +#endif + + if (fw_explicitly_loaded == false) { + ia_css_unload_firmware(); + } + ia_css_spctrl_unload_fw(SP0_ID); + sh_css_sp_set_sp_running(false); +#if defined(HAS_SEC_SP) + ia_css_spctrl_unload_fw(SP1_ID); + sh_css_sp1_set_sp1_running(false); +#endif /* HAS_SEC_SP */ + +#if defined(HAS_BL) + ia_css_blctrl_unload_fw(); +#endif +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) + /* check and free any remaining mipi frames */ + free_mipi_frames(NULL); +#endif + + sh_css_sp_reset_global_vars(); + +#if !defined(HAS_NO_INPUT_SYSTEM) + ia_css_isys_uninit(); +#endif + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_uninit() leave: return_void\n"); +} + +#ifndef ISP2401 +/* Deprecated, this is an HRT backend function (memory_access.h) */ +static void +sh_css_mmu_set_page_table_base_index(hrt_data base_index) +{ + int i; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "sh_css_mmu_set_page_table_base_index() enter: base_index=0x%08x\n",base_index); + my_css.page_table_base_index = base_index; + for (i = 0; i < (int)N_MMU_ID; i++) { + mmu_ID_t mmu_id = (mmu_ID_t)i; + mmu_set_page_table_base_index(mmu_id, base_index); + mmu_invalidate_cache(mmu_id); + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "sh_css_mmu_set_page_table_base_index() leave: return_void\n"); +} + +#endif +#if defined(HAS_IRQ_MAP_VERSION_2) +enum ia_css_err ia_css_irq_translate( + unsigned int *irq_infos) +{ + virq_id_t irq; + enum hrt_isp_css_irq_status status = hrt_isp_css_irq_status_more_irqs; + unsigned int infos = 0; + +/* irq_infos can be NULL, but that would make the function useless */ +/* assert(irq_infos != NULL); */ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_irq_translate() enter: irq_infos=%p\n",irq_infos); + + while (status == hrt_isp_css_irq_status_more_irqs) { + status = virq_get_channel_id(&irq); + if (status == hrt_isp_css_irq_status_error) + return IA_CSS_ERR_INTERNAL_ERROR; + +#if WITH_PC_MONITORING + sh_css_print("PC_MONITORING: %s() irq = %d, " + "sh_binary_running set to 0\n", __func__, irq); + sh_binary_running = 0 ; +#endif + + switch (irq) { + case virq_sp: + /* When SP goes to idle, info is available in the + * event queue. */ + infos |= IA_CSS_IRQ_INFO_EVENTS_READY; + break; + case virq_isp: +#ifdef HRT_CSIM + /* Enable IRQ which signals that ISP goes to idle + * to get statistics for each binary */ + infos |= IA_CSS_IRQ_INFO_ISP_BINARY_STATISTICS_READY; +#endif + break; +#if !defined(HAS_NO_INPUT_SYSTEM) + case virq_isys_sof: + infos |= IA_CSS_IRQ_INFO_CSS_RECEIVER_SOF; + break; + case virq_isys_eof: + infos |= IA_CSS_IRQ_INFO_CSS_RECEIVER_EOF; + break; + case virq_isys_csi: + infos |= IA_CSS_IRQ_INFO_INPUT_SYSTEM_ERROR; + break; +#endif +#if !defined(HAS_NO_INPUT_FORMATTER) + case virq_ifmt0_id: + infos |= IA_CSS_IRQ_INFO_IF_ERROR; + break; +#endif + case virq_dma: + infos |= IA_CSS_IRQ_INFO_DMA_ERROR; + break; + case virq_sw_pin_0: + infos |= sh_css_get_sw_interrupt_value(0); + break; + case virq_sw_pin_1: + infos |= sh_css_get_sw_interrupt_value(1); + /* pqiao TODO: also assumption here */ + break; + default: + break; + } + } + + if (irq_infos) + *irq_infos = infos; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_irq_translate() " + "leave: irq_infos=%p\n", infos); + + return IA_CSS_SUCCESS; +} + +enum ia_css_err ia_css_irq_enable( + enum ia_css_irq_info info, + bool enable) +{ + virq_id_t irq = N_virq_id; + IA_CSS_ENTER("info=%d, enable=%d", info, enable); + + switch (info) { +#if !defined(HAS_NO_INPUT_FORMATTER) + case IA_CSS_IRQ_INFO_CSS_RECEIVER_SOF: + irq = virq_isys_sof; + break; + case IA_CSS_IRQ_INFO_CSS_RECEIVER_EOF: + irq = virq_isys_eof; + break; + case IA_CSS_IRQ_INFO_INPUT_SYSTEM_ERROR: + irq = virq_isys_csi; + break; +#endif +#if !defined(HAS_NO_INPUT_FORMATTER) + case IA_CSS_IRQ_INFO_IF_ERROR: + irq = virq_ifmt0_id; + break; +#endif + case IA_CSS_IRQ_INFO_DMA_ERROR: + irq = virq_dma; + break; + case IA_CSS_IRQ_INFO_SW_0: + irq = virq_sw_pin_0; + break; + case IA_CSS_IRQ_INFO_SW_1: + irq = virq_sw_pin_1; + break; + default: + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + cnd_virq_enable_channel(irq, enable); + + IA_CSS_LEAVE_ERR(IA_CSS_SUCCESS); + return IA_CSS_SUCCESS; +} + +#else +#error "sh_css.c: IRQ MAP must be one of \ + {IRQ_MAP_VERSION_2}" +#endif + +static unsigned int +sh_css_get_sw_interrupt_value(unsigned int irq) +{ + unsigned int irq_value; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sh_css_get_sw_interrupt_value() enter: irq=%d\n",irq); + irq_value = sh_css_sp_get_sw_interrupt_value(irq); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sh_css_get_sw_interrupt_value() leave: irq_value=%d\n",irq_value); + return irq_value; +} + +/* configure and load the copy binary, the next binary is used to + determine whether the copy binary needs to do left padding. */ +static enum ia_css_err load_copy_binary( + struct ia_css_pipe *pipe, + struct ia_css_binary *copy_binary, + struct ia_css_binary *next_binary) +{ + struct ia_css_frame_info copy_out_info, copy_in_info, copy_vf_info; + unsigned int left_padding; + enum ia_css_err err; + struct ia_css_binary_descr copy_descr; + + /* next_binary can be NULL */ + assert(pipe != NULL); + assert(copy_binary != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "load_copy_binary() enter:\n"); + + if (next_binary != NULL) { + copy_out_info = next_binary->in_frame_info; + left_padding = next_binary->left_padding; + } else { + copy_out_info = pipe->output_info[0]; + copy_vf_info = pipe->vf_output_info[0]; + ia_css_frame_info_set_format(©_vf_info, IA_CSS_FRAME_FORMAT_YUV_LINE); + left_padding = 0; + } + + ia_css_pipe_get_copy_binarydesc(pipe, ©_descr, + ©_in_info, ©_out_info, (next_binary != NULL) ? NULL : NULL/*TODO: ©_vf_info*/); + err = ia_css_binary_find(©_descr, copy_binary); + if (err != IA_CSS_SUCCESS) + return err; + copy_binary->left_padding = left_padding; + return IA_CSS_SUCCESS; +} + +static enum ia_css_err +alloc_continuous_frames( + struct ia_css_pipe *pipe, bool init_time) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_frame_info ref_info; + enum ia_css_pipe_id pipe_id; + bool continuous; + unsigned int i, idx; + unsigned int num_frames; + struct ia_css_pipe *capture_pipe = NULL; + + IA_CSS_ENTER_PRIVATE("pipe = %p, init_time = %d", pipe, init_time); + + if ((pipe == NULL) || (pipe->stream == NULL)) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + pipe_id = pipe->mode; + continuous = pipe->stream->config.continuous; + + if (continuous) { + if (init_time) { + num_frames = pipe->stream->config.init_num_cont_raw_buf; + pipe->stream->continuous_pipe = pipe; + } else + num_frames = pipe->stream->config.target_num_cont_raw_buf; + } else { + num_frames = NUM_ONLINE_INIT_CONTINUOUS_FRAMES; + } + + if (pipe_id == IA_CSS_PIPE_ID_PREVIEW) { + ref_info = pipe->pipe_settings.preview.preview_binary.in_frame_info; + } else if (pipe_id == IA_CSS_PIPE_ID_VIDEO) { + ref_info = pipe->pipe_settings.video.video_binary.in_frame_info; + } + else { + /* should not happen */ + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INTERNAL_ERROR); + return IA_CSS_ERR_INTERNAL_ERROR; + } + +#if defined(USE_INPUT_SYSTEM_VERSION_2401) + /* For CSI2+, the continuous frame will hold the full input frame */ + ref_info.res.width = pipe->stream->config.input_config.input_res.width; + ref_info.res.height = pipe->stream->config.input_config.input_res.height; + + /* Ensure padded width is aligned for 2401 */ + ref_info.padded_width = CEIL_MUL(ref_info.res.width, 2 * ISP_VEC_NELEMS); +#endif + +#if !defined(HAS_NO_PACKED_RAW_PIXELS) + if (pipe->stream->config.pack_raw_pixels) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "alloc_continuous_frames() IA_CSS_FRAME_FORMAT_RAW_PACKED\n"); + ref_info.format = IA_CSS_FRAME_FORMAT_RAW_PACKED; + } else +#endif + { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "alloc_continuous_frames() IA_CSS_FRAME_FORMAT_RAW\n"); + ref_info.format = IA_CSS_FRAME_FORMAT_RAW; + } + + /* Write format back to binary */ + if (pipe_id == IA_CSS_PIPE_ID_PREVIEW) { + pipe->pipe_settings.preview.preview_binary.in_frame_info.format = ref_info.format; + capture_pipe = pipe->pipe_settings.preview.capture_pipe; + } else if (pipe_id == IA_CSS_PIPE_ID_VIDEO) { + pipe->pipe_settings.video.video_binary.in_frame_info.format = ref_info.format; + capture_pipe = pipe->pipe_settings.video.capture_pipe; + } else { + /* should not happen */ + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INTERNAL_ERROR); + return IA_CSS_ERR_INTERNAL_ERROR; + } + + if (init_time) + idx = 0; + else + idx = pipe->stream->config.init_num_cont_raw_buf; + + for (i = idx; i < NUM_CONTINUOUS_FRAMES; i++) { + /* free previous frame */ + if (pipe->continuous_frames[i]) { + ia_css_frame_free(pipe->continuous_frames[i]); + pipe->continuous_frames[i] = NULL; + } + /* free previous metadata buffer */ + ia_css_metadata_free(pipe->cont_md_buffers[i]); + pipe->cont_md_buffers[i] = NULL; + + /* check if new frame needed */ + if (i < num_frames) { + /* allocate new frame */ + err = ia_css_frame_allocate_from_info( + &pipe->continuous_frames[i], + &ref_info); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + /* allocate metadata buffer */ + pipe->cont_md_buffers[i] = ia_css_metadata_allocate( + &pipe->stream->info.metadata_info); + } + } + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + return IA_CSS_SUCCESS; +} + +enum ia_css_err +ia_css_alloc_continuous_frame_remain(struct ia_css_stream *stream) +{ + if (stream == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + return alloc_continuous_frames(stream->continuous_pipe, false); +} + +static enum ia_css_err +load_preview_binaries(struct ia_css_pipe *pipe) +{ + struct ia_css_frame_info prev_in_info, + prev_bds_out_info, + prev_out_info, + prev_vf_info; + struct ia_css_binary_descr preview_descr; + bool online; + enum ia_css_err err = IA_CSS_SUCCESS; + bool continuous, need_vf_pp = false; + bool need_isp_copy_binary = false; +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + bool sensor = false; +#endif + /* preview only have 1 output pin now */ + struct ia_css_frame_info *pipe_out_info = &pipe->output_info[0]; +#ifdef ISP2401 + struct ia_css_preview_settings *mycs = &pipe->pipe_settings.preview; + +#endif + + IA_CSS_ENTER_PRIVATE(""); + assert(pipe != NULL); + assert(pipe->stream != NULL); + assert(pipe->mode == IA_CSS_PIPE_ID_PREVIEW); + + online = pipe->stream->config.online; + continuous = pipe->stream->config.continuous; +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + sensor = pipe->stream->config.mode == IA_CSS_INPUT_MODE_SENSOR; +#endif + +#ifndef ISP2401 + if (pipe->pipe_settings.preview.preview_binary.info) +#else + if (mycs->preview_binary.info) +#endif + return IA_CSS_SUCCESS; + + err = ia_css_util_check_input(&pipe->stream->config, false, false); + if (err != IA_CSS_SUCCESS) + return err; + err = ia_css_frame_check_info(pipe_out_info); + if (err != IA_CSS_SUCCESS) + return err; + + /* Note: the current selection of vf_pp binary and + * parameterization of the preview binary contains a few pieces + * of hardcoded knowledge. This needs to be cleaned up such that + * the binary selection becomes more generic. + * The vf_pp binary is needed if one or more of the following features + * are required: + * 1. YUV downscaling. + * 2. Digital zoom. + * 3. An output format that is not supported by the preview binary. + * In practice this means something other than yuv_line or nv12. + * The decision if the vf_pp binary is needed for YUV downscaling is + * made after the preview binary selection, since some preview binaries + * can perform the requested YUV downscaling. + * */ + need_vf_pp = pipe->config.enable_dz; + need_vf_pp |= pipe_out_info->format != IA_CSS_FRAME_FORMAT_YUV_LINE && + !(pipe_out_info->format == IA_CSS_FRAME_FORMAT_NV12 || + pipe_out_info->format == IA_CSS_FRAME_FORMAT_NV12_16 || + pipe_out_info->format == IA_CSS_FRAME_FORMAT_NV12_TILEY); + + /* Preview step 1 */ + if (pipe->vf_yuv_ds_input_info.res.width) + prev_vf_info = pipe->vf_yuv_ds_input_info; + else + prev_vf_info = *pipe_out_info; + /* If vf_pp is needed, then preview must output yuv_line. + * The exception is when vf_pp is manually disabled, that is only + * used in combination with a pipeline extension that requires + * yuv_line as input. + * */ + if (need_vf_pp) + ia_css_frame_info_set_format(&prev_vf_info, + IA_CSS_FRAME_FORMAT_YUV_LINE); + + err = ia_css_pipe_get_preview_binarydesc( + pipe, + &preview_descr, + &prev_in_info, + &prev_bds_out_info, + &prev_out_info, + &prev_vf_info); + if (err != IA_CSS_SUCCESS) + return err; + err = ia_css_binary_find(&preview_descr, +#ifndef ISP2401 + &pipe->pipe_settings.preview.preview_binary); +#else + &mycs->preview_binary); +#endif + if (err != IA_CSS_SUCCESS) + return err; + +#ifdef ISP2401 + /* The delay latency determines the number of invalid frames after + * a stream is started. */ + pipe->num_invalid_frames = pipe->dvs_frame_delay; + pipe->info.num_invalid_frames = pipe->num_invalid_frames; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "load_preview_binaries() num_invalid_frames=%d dvs_frame_delay=%d\n", + pipe->num_invalid_frames, pipe->dvs_frame_delay); + +#endif + /* The vf_pp binary is needed when (further) YUV downscaling is required */ +#ifndef ISP2401 + need_vf_pp |= pipe->pipe_settings.preview.preview_binary.out_frame_info[0].res.width != pipe_out_info->res.width; + need_vf_pp |= pipe->pipe_settings.preview.preview_binary.out_frame_info[0].res.height != pipe_out_info->res.height; +#else + need_vf_pp |= mycs->preview_binary.out_frame_info[0].res.width != pipe_out_info->res.width; + need_vf_pp |= mycs->preview_binary.out_frame_info[0].res.height != pipe_out_info->res.height; +#endif + + /* When vf_pp is needed, then the output format of the selected + * preview binary must be yuv_line. If this is not the case, + * then the preview binary selection is done again. + */ + if (need_vf_pp && +#ifndef ISP2401 + (pipe->pipe_settings.preview.preview_binary.out_frame_info[0].format != IA_CSS_FRAME_FORMAT_YUV_LINE)) { +#else + (mycs->preview_binary.out_frame_info[0].format != IA_CSS_FRAME_FORMAT_YUV_LINE)) { +#endif + + /* Preview step 2 */ + if (pipe->vf_yuv_ds_input_info.res.width) + prev_vf_info = pipe->vf_yuv_ds_input_info; + else + prev_vf_info = *pipe_out_info; + + ia_css_frame_info_set_format(&prev_vf_info, + IA_CSS_FRAME_FORMAT_YUV_LINE); + + err = ia_css_pipe_get_preview_binarydesc( + pipe, + &preview_descr, + &prev_in_info, + &prev_bds_out_info, + &prev_out_info, + &prev_vf_info); + if (err != IA_CSS_SUCCESS) + return err; + err = ia_css_binary_find(&preview_descr, +#ifndef ISP2401 + &pipe->pipe_settings.preview.preview_binary); +#else + &mycs->preview_binary); +#endif + if (err != IA_CSS_SUCCESS) + return err; + } + + if (need_vf_pp) { + struct ia_css_binary_descr vf_pp_descr; + + /* Viewfinder post-processing */ + ia_css_pipe_get_vfpp_binarydesc(pipe, &vf_pp_descr, +#ifndef ISP2401 + &pipe->pipe_settings.preview.preview_binary.out_frame_info[0], +#else + &mycs->preview_binary.out_frame_info[0], +#endif + pipe_out_info); + err = ia_css_binary_find(&vf_pp_descr, +#ifndef ISP2401 + &pipe->pipe_settings.preview.vf_pp_binary); +#else + &mycs->vf_pp_binary); +#endif + if (err != IA_CSS_SUCCESS) + return err; + } + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + /* When the input system is 2401, only the Direct Sensor Mode + * Offline Preview uses the ISP copy binary. + */ + need_isp_copy_binary = !online && sensor; +#else +#ifndef ISP2401 + need_isp_copy_binary = !online && !continuous; +#else + /* About pipe->stream->config.mode == IA_CSS_INPUT_MODE_MEMORY: + * This is typical the case with SkyCam (which has no input system) but it also applies to all cases + * where the driver chooses for memory based input frames. In these cases, a copy binary (which typical + * copies sensor data to DDR) does not have much use. + */ + need_isp_copy_binary = !online && !continuous && !(pipe->stream->config.mode == IA_CSS_INPUT_MODE_MEMORY); +#endif +#endif + + /* Copy */ + if (need_isp_copy_binary) { + err = load_copy_binary(pipe, +#ifndef ISP2401 + &pipe->pipe_settings.preview.copy_binary, + &pipe->pipe_settings.preview.preview_binary); +#else + &mycs->copy_binary, + &mycs->preview_binary); +#endif + if (err != IA_CSS_SUCCESS) + return err; + } + + if (pipe->shading_table) { + ia_css_shading_table_free(pipe->shading_table); + pipe->shading_table = NULL; + } + + return IA_CSS_SUCCESS; +} + +static void +ia_css_binary_unload(struct ia_css_binary *binary) +{ + ia_css_binary_destroy_isp_parameters(binary); +} + +static enum ia_css_err +unload_preview_binaries(struct ia_css_pipe *pipe) +{ + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + + if ((pipe == NULL) || (pipe->mode != IA_CSS_PIPE_ID_PREVIEW)) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + ia_css_binary_unload(&pipe->pipe_settings.preview.copy_binary); + ia_css_binary_unload(&pipe->pipe_settings.preview.preview_binary); + ia_css_binary_unload(&pipe->pipe_settings.preview.vf_pp_binary); + + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + return IA_CSS_SUCCESS; +} + +static const struct ia_css_fw_info *last_output_firmware( + const struct ia_css_fw_info *fw) +{ + const struct ia_css_fw_info *last_fw = NULL; +/* fw can be NULL */ + IA_CSS_ENTER_LEAVE_PRIVATE(""); + + for (; fw; fw = fw->next) { + const struct ia_css_fw_info *info = fw; + if (info->info.isp.sp.enable.output) + last_fw = fw; + } + return last_fw; +} + +static enum ia_css_err add_firmwares( + struct ia_css_pipeline *me, + struct ia_css_binary *binary, + const struct ia_css_fw_info *fw, + const struct ia_css_fw_info *last_fw, + unsigned int binary_mode, + struct ia_css_frame *in_frame, + struct ia_css_frame *out_frame, + struct ia_css_frame *vf_frame, + struct ia_css_pipeline_stage **my_stage, + struct ia_css_pipeline_stage **vf_stage) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_pipeline_stage *extra_stage = NULL; + struct ia_css_pipeline_stage_desc stage_desc; + +/* all args can be NULL ??? */ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "add_firmwares() enter:\n"); + + for (; fw; fw = fw->next) { + struct ia_css_frame *out[IA_CSS_BINARY_MAX_OUTPUT_PORTS] = {NULL}; + struct ia_css_frame *in = NULL; + struct ia_css_frame *vf = NULL; + if ((fw == last_fw) && (fw->info.isp.sp.enable.out_frame != 0)) { + out[0] = out_frame; + } + if (fw->info.isp.sp.enable.in_frame != 0) { + in = in_frame; + } + if (fw->info.isp.sp.enable.out_frame != 0) { + vf = vf_frame; + } + ia_css_pipe_get_firmwares_stage_desc(&stage_desc, binary, + out, in, vf, fw, binary_mode); + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, + &extra_stage); + if (err != IA_CSS_SUCCESS) + return err; + if (fw->info.isp.sp.enable.output != 0) + in_frame = extra_stage->args.out_frame[0]; + if (my_stage && !*my_stage && extra_stage) + *my_stage = extra_stage; + if (vf_stage && !*vf_stage && extra_stage && + fw->info.isp.sp.enable.vf_veceven) + *vf_stage = extra_stage; + } + return err; +} + +static enum ia_css_err add_vf_pp_stage( + struct ia_css_pipe *pipe, + struct ia_css_frame *in_frame, + struct ia_css_frame *out_frame, + struct ia_css_binary *vf_pp_binary, + struct ia_css_pipeline_stage **vf_pp_stage) +{ + + struct ia_css_pipeline *me = NULL; + const struct ia_css_fw_info *last_fw = NULL; + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_frame *out_frames[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_pipeline_stage_desc stage_desc; + +/* out_frame can be NULL ??? */ + + if (pipe == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + if (in_frame == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + if (vf_pp_binary == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + if (vf_pp_stage == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + ia_css_pipe_util_create_output_frames(out_frames); + me = &pipe->pipeline; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "add_vf_pp_stage() enter:\n"); + + *vf_pp_stage = NULL; + + last_fw = last_output_firmware(pipe->vf_stage); + if (!pipe->extra_config.disable_vf_pp) { + if (last_fw) { + ia_css_pipe_util_set_output_frames(out_frames, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, vf_pp_binary, + out_frames, in_frame, NULL); + } else{ + ia_css_pipe_util_set_output_frames(out_frames, 0, out_frame); + ia_css_pipe_get_generic_stage_desc(&stage_desc, vf_pp_binary, + out_frames, in_frame, NULL); + } + err = ia_css_pipeline_create_and_add_stage(me, &stage_desc, vf_pp_stage); + if (err != IA_CSS_SUCCESS) + return err; + in_frame = (*vf_pp_stage)->args.out_frame[0]; + } + err = add_firmwares(me, vf_pp_binary, pipe->vf_stage, last_fw, + IA_CSS_BINARY_MODE_VF_PP, + in_frame, out_frame, NULL, + vf_pp_stage, NULL); + return err; +} + +static enum ia_css_err add_yuv_scaler_stage( + struct ia_css_pipe *pipe, + struct ia_css_pipeline *me, + struct ia_css_frame *in_frame, + struct ia_css_frame *out_frame, + struct ia_css_frame *internal_out_frame, + struct ia_css_binary *yuv_scaler_binary, + struct ia_css_pipeline_stage **pre_vf_pp_stage) +{ + const struct ia_css_fw_info *last_fw; + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_frame *vf_frame = NULL; + struct ia_css_frame *out_frames[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_pipeline_stage_desc stage_desc; + + /* out_frame can be NULL ??? */ + assert(in_frame != NULL); + assert(pipe != NULL); + assert(me != NULL); + assert(yuv_scaler_binary != NULL); + assert(pre_vf_pp_stage != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "add_yuv_scaler_stage() enter:\n"); + + *pre_vf_pp_stage = NULL; + ia_css_pipe_util_create_output_frames(out_frames); + + last_fw = last_output_firmware(pipe->output_stage); + + if(last_fw) { + ia_css_pipe_util_set_output_frames(out_frames, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, + yuv_scaler_binary, out_frames, in_frame, vf_frame); + } else { + ia_css_pipe_util_set_output_frames(out_frames, 0, out_frame); + ia_css_pipe_util_set_output_frames(out_frames, 1, internal_out_frame); + ia_css_pipe_get_generic_stage_desc(&stage_desc, + yuv_scaler_binary, out_frames, in_frame, vf_frame); + } + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, + pre_vf_pp_stage); + if (err != IA_CSS_SUCCESS) + return err; + in_frame = (*pre_vf_pp_stage)->args.out_frame[0]; + + err = add_firmwares(me, yuv_scaler_binary, pipe->output_stage, last_fw, + IA_CSS_BINARY_MODE_CAPTURE_PP, + in_frame, out_frame, vf_frame, + NULL, pre_vf_pp_stage); + /* If a firmware produce vf_pp output, we set that as vf_pp input */ + (*pre_vf_pp_stage)->args.vf_downscale_log2 = yuv_scaler_binary->vf_downscale_log2; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "add_yuv_scaler_stage() leave:\n"); + return err; +} + +static enum ia_css_err add_capture_pp_stage( + struct ia_css_pipe *pipe, + struct ia_css_pipeline *me, + struct ia_css_frame *in_frame, + struct ia_css_frame *out_frame, + struct ia_css_binary *capture_pp_binary, + struct ia_css_pipeline_stage **capture_pp_stage) +{ + const struct ia_css_fw_info *last_fw = NULL; + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_frame *vf_frame = NULL; + struct ia_css_frame *out_frames[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_pipeline_stage_desc stage_desc; + + /* out_frame can be NULL ??? */ + assert(in_frame != NULL); + assert(pipe != NULL); + assert(me != NULL); + assert(capture_pp_binary != NULL); + assert(capture_pp_stage != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "add_capture_pp_stage() enter:\n"); + + *capture_pp_stage = NULL; + ia_css_pipe_util_create_output_frames(out_frames); + + last_fw = last_output_firmware(pipe->output_stage); + err = ia_css_frame_allocate_from_info(&vf_frame, + &capture_pp_binary->vf_frame_info); + if (err != IA_CSS_SUCCESS) + return err; + if(last_fw) { + ia_css_pipe_util_set_output_frames(out_frames, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, + capture_pp_binary, out_frames, NULL, vf_frame); + } else { + ia_css_pipe_util_set_output_frames(out_frames, 0, out_frame); + ia_css_pipe_get_generic_stage_desc(&stage_desc, + capture_pp_binary, out_frames, NULL, vf_frame); + } + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, + capture_pp_stage); + if (err != IA_CSS_SUCCESS) + return err; + err = add_firmwares(me, capture_pp_binary, pipe->output_stage, last_fw, + IA_CSS_BINARY_MODE_CAPTURE_PP, + in_frame, out_frame, vf_frame, + NULL, capture_pp_stage); + /* If a firmware produce vf_pp output, we set that as vf_pp input */ + if (*capture_pp_stage) { + (*capture_pp_stage)->args.vf_downscale_log2 = + capture_pp_binary->vf_downscale_log2; + } + return err; +} + +static void sh_css_setup_queues(void) +{ + const struct ia_css_fw_info *fw; + unsigned int HIVE_ADDR_host_sp_queues_initialized; + + sh_css_hmm_buffer_record_init(); + + sh_css_event_init_irq_mask(); + + fw = &sh_css_sp_fw; + HIVE_ADDR_host_sp_queues_initialized = + fw->info.sp.host_sp_queues_initialized; + + ia_css_bufq_init(); + + /* set "host_sp_queues_initialized" to "true" */ + sp_dmem_store_uint32(SP0_ID, + (unsigned int)sp_address_of(host_sp_queues_initialized), + (uint32_t)(1)); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sh_css_setup_queues() leave:\n"); +} + +static enum ia_css_err +init_vf_frameinfo_defaults(struct ia_css_pipe *pipe, + struct ia_css_frame *vf_frame, unsigned int idx) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + unsigned int thread_id; + enum sh_css_queue_id queue_id; + + assert(vf_frame != NULL); + + sh_css_pipe_get_viewfinder_frame_info(pipe, &vf_frame->info, idx); + vf_frame->contiguous = false; + vf_frame->flash_state = IA_CSS_FRAME_FLASH_STATE_NONE; + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME + idx, thread_id, &queue_id); + vf_frame->dynamic_queue_id = queue_id; + vf_frame->buf_type = IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME + idx; + + err = ia_css_frame_init_planes(vf_frame); + return err; +} + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 +static unsigned int +get_crop_lines_for_bayer_order ( + const struct ia_css_stream_config *config) +{ + assert(config != NULL); + if ((IA_CSS_BAYER_ORDER_BGGR == config->input_config.bayer_order) + || (IA_CSS_BAYER_ORDER_GBRG == config->input_config.bayer_order)) + return 1; + + return 0; +} + +static unsigned int +get_crop_columns_for_bayer_order ( + const struct ia_css_stream_config *config) +{ + assert(config != NULL); + if ((IA_CSS_BAYER_ORDER_RGGB == config->input_config.bayer_order) + || (IA_CSS_BAYER_ORDER_GBRG == config->input_config.bayer_order)) + return 1; + + return 0; +} + +/* This function is to get the sum of all extra pixels in addition to the effective + * input, it includes dvs envelop and filter run-in */ +static void get_pipe_extra_pixel(struct ia_css_pipe *pipe, + unsigned int *extra_row, unsigned int *extra_column) +{ + enum ia_css_pipe_id pipe_id = pipe->mode; + unsigned int left_cropping = 0, top_cropping = 0; + unsigned int i; + struct ia_css_resolution dvs_env = pipe->config.dvs_envelope; + + /* The dvs envelope info may not be correctly sent down via pipe config + * The check is made and the correct value is populated in the binary info + * Use this value when computing crop, else excess lines may get trimmed + */ + switch (pipe_id) { + case IA_CSS_PIPE_ID_PREVIEW: + if (pipe->pipe_settings.preview.preview_binary.info) { + left_cropping = pipe->pipe_settings.preview.preview_binary.info->sp.pipeline.left_cropping; + top_cropping = pipe->pipe_settings.preview.preview_binary.info->sp.pipeline.top_cropping; + } + dvs_env = pipe->pipe_settings.preview.preview_binary.dvs_envelope; + break; + case IA_CSS_PIPE_ID_VIDEO: + if (pipe->pipe_settings.video.video_binary.info) { + left_cropping = pipe->pipe_settings.video.video_binary.info->sp.pipeline.left_cropping; + top_cropping = pipe->pipe_settings.video.video_binary.info->sp.pipeline.top_cropping; + } + dvs_env = pipe->pipe_settings.video.video_binary.dvs_envelope; + break; + case IA_CSS_PIPE_ID_CAPTURE: + for (i = 0; i < pipe->pipe_settings.capture.num_primary_stage; i++) { + if (pipe->pipe_settings.capture.primary_binary[i].info) { + left_cropping += pipe->pipe_settings.capture.primary_binary[i].info->sp.pipeline.left_cropping; + top_cropping += pipe->pipe_settings.capture.primary_binary[i].info->sp.pipeline.top_cropping; + } + dvs_env.width += pipe->pipe_settings.capture.primary_binary[i].dvs_envelope.width; + dvs_env.height += pipe->pipe_settings.capture.primary_binary[i].dvs_envelope.height; + } + break; + default: + break; + } + + *extra_row = top_cropping + dvs_env.height; + *extra_column = left_cropping + dvs_env.width; +} + +void +ia_css_get_crop_offsets ( + struct ia_css_pipe *pipe, + struct ia_css_frame_info *in_frame) +{ + unsigned int row = 0; + unsigned int column = 0; + struct ia_css_resolution *input_res; + struct ia_css_resolution *effective_res; + unsigned int extra_row = 0, extra_col = 0; + unsigned int min_reqd_height, min_reqd_width; + + assert(pipe != NULL); + assert(pipe->stream != NULL); + assert(in_frame != NULL); + + IA_CSS_ENTER_PRIVATE("pipe = %p effective_wd = %u effective_ht = %u", + pipe, pipe->config.input_effective_res.width, + pipe->config.input_effective_res.height); + + input_res = &pipe->stream->config.input_config.input_res; +#ifndef ISP2401 + effective_res = &pipe->stream->config.input_config.effective_res; +#else + effective_res = &pipe->config.input_effective_res; +#endif + + get_pipe_extra_pixel(pipe, &extra_row, &extra_col); + + in_frame->raw_bayer_order = pipe->stream->config.input_config.bayer_order; + + min_reqd_height = effective_res->height + extra_row; + min_reqd_width = effective_res->width + extra_col; + + if (input_res->height > min_reqd_height) { + row = (input_res->height - min_reqd_height) / 2; + row &= ~0x1; + } + if (input_res->width > min_reqd_width) { + column = (input_res->width - min_reqd_width) / 2; + column &= ~0x1; + } + + /* + * TODO: + * 1. Require the special support for RAW10 packed mode. + * 2. Require the special support for the online use cases. + */ + + /* ISP expects GRBG bayer order, we skip one line and/or one row + * to correct in case the input bayer order is different. + */ + column += get_crop_columns_for_bayer_order(&pipe->stream->config); + row += get_crop_lines_for_bayer_order(&pipe->stream->config); + + in_frame->crop_info.start_column = column; + in_frame->crop_info.start_line = row; + + IA_CSS_LEAVE_PRIVATE("void start_col: %u start_row: %u", column, row); + + return; +} +#endif + +static enum ia_css_err +init_in_frameinfo_memory_defaults(struct ia_css_pipe *pipe, + struct ia_css_frame *frame, enum ia_css_frame_format format) +{ + struct ia_css_frame *in_frame; + enum ia_css_err err = IA_CSS_SUCCESS; + unsigned int thread_id; + enum sh_css_queue_id queue_id; + + assert(frame != NULL); + in_frame = frame; + + in_frame->info.format = format; + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + if (format == IA_CSS_FRAME_FORMAT_RAW) + in_frame->info.format = (pipe->stream->config.pack_raw_pixels) ? + IA_CSS_FRAME_FORMAT_RAW_PACKED : IA_CSS_FRAME_FORMAT_RAW; +#endif + + + in_frame->info.res.width = pipe->stream->config.input_config.input_res.width; + in_frame->info.res.height = pipe->stream->config.input_config.input_res.height; + in_frame->info.raw_bit_depth = + ia_css_pipe_util_pipe_input_format_bpp(pipe); + ia_css_frame_info_set_width(&in_frame->info, pipe->stream->config.input_config.input_res.width, 0); + in_frame->contiguous = false; + in_frame->flash_state = IA_CSS_FRAME_FLASH_STATE_NONE; + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_INPUT_FRAME, thread_id, &queue_id); + in_frame->dynamic_queue_id = queue_id; + in_frame->buf_type = IA_CSS_BUFFER_TYPE_INPUT_FRAME; +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + ia_css_get_crop_offsets(pipe, &in_frame->info); +#endif + err = ia_css_frame_init_planes(in_frame); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "init_in_frameinfo_memory_defaults() bayer_order = %d:\n", in_frame->info.raw_bayer_order); + + return err; +} + +static enum ia_css_err +init_out_frameinfo_defaults(struct ia_css_pipe *pipe, + struct ia_css_frame *out_frame, unsigned int idx) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + unsigned int thread_id; + enum sh_css_queue_id queue_id; + + assert(out_frame != NULL); + + sh_css_pipe_get_output_frame_info(pipe, &out_frame->info, idx); + out_frame->contiguous = false; + out_frame->flash_state = IA_CSS_FRAME_FLASH_STATE_NONE; + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_OUTPUT_FRAME + idx, thread_id, &queue_id); + out_frame->dynamic_queue_id = queue_id; + out_frame->buf_type = IA_CSS_BUFFER_TYPE_OUTPUT_FRAME + idx; + err = ia_css_frame_init_planes(out_frame); + + return err; +} + +/* Create stages for video pipe */ +static enum ia_css_err create_host_video_pipeline(struct ia_css_pipe *pipe) +{ + struct ia_css_pipeline_stage_desc stage_desc; + struct ia_css_binary *copy_binary, *video_binary, + *yuv_scaler_binary, *vf_pp_binary; + struct ia_css_pipeline_stage *copy_stage = NULL; + struct ia_css_pipeline_stage *video_stage = NULL; + struct ia_css_pipeline_stage *yuv_scaler_stage = NULL; + struct ia_css_pipeline_stage *vf_pp_stage = NULL; + struct ia_css_pipeline *me; + struct ia_css_frame *in_frame = NULL; + struct ia_css_frame *out_frame; + struct ia_css_frame *out_frames[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_frame *vf_frame = NULL; + enum ia_css_err err = IA_CSS_SUCCESS; + bool need_copy = false; + bool need_vf_pp = false; + bool need_yuv_pp = false; + unsigned num_output_pins; + bool need_in_frameinfo_memory = false; + + unsigned int i, num_yuv_scaler; + bool *is_output_stage = NULL; + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + if ((pipe == NULL) || (pipe->stream == NULL) || (pipe->mode != IA_CSS_PIPE_ID_VIDEO)) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + ia_css_pipe_util_create_output_frames(out_frames); + out_frame = &pipe->out_frame_struct; + + /* pipeline already created as part of create_host_pipeline_structure */ + me = &pipe->pipeline; + ia_css_pipeline_clean(me); + + me->dvs_frame_delay = pipe->dvs_frame_delay; + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + /* When the input system is 2401, always enable 'in_frameinfo_memory' + * except for the following: online or continuous + */ + need_in_frameinfo_memory = !(pipe->stream->config.online || pipe->stream->config.continuous); +#else + /* Construct in_frame info (only in case we have dynamic input */ + need_in_frameinfo_memory = pipe->stream->config.mode == IA_CSS_INPUT_MODE_MEMORY; +#endif + + /* Construct in_frame info (only in case we have dynamic input */ + if (need_in_frameinfo_memory) { + in_frame = &pipe->in_frame_struct; + err = init_in_frameinfo_memory_defaults(pipe, in_frame, IA_CSS_FRAME_FORMAT_RAW); + if (err != IA_CSS_SUCCESS) + goto ERR; + } + + out_frame->data = 0; + err = init_out_frameinfo_defaults(pipe, out_frame, 0); + if (err != IA_CSS_SUCCESS) + goto ERR; + + if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0]) { + vf_frame = &pipe->vf_frame_struct; + vf_frame->data = 0; + err = init_vf_frameinfo_defaults(pipe, vf_frame, 0); + if (err != IA_CSS_SUCCESS) + goto ERR; + } + + copy_binary = &pipe->pipe_settings.video.copy_binary; + video_binary = &pipe->pipe_settings.video.video_binary; + vf_pp_binary = &pipe->pipe_settings.video.vf_pp_binary; + num_output_pins = video_binary->info->num_output_pins; + + yuv_scaler_binary = pipe->pipe_settings.video.yuv_scaler_binary; + num_yuv_scaler = pipe->pipe_settings.video.num_yuv_scaler; + is_output_stage = pipe->pipe_settings.video.is_output_stage; + + need_copy = (copy_binary != NULL && copy_binary->info != NULL); + need_vf_pp = (vf_pp_binary != NULL && vf_pp_binary->info != NULL); + need_yuv_pp = (yuv_scaler_binary != NULL && yuv_scaler_binary->info != NULL); + + if (need_copy) { + ia_css_pipe_util_set_output_frames(out_frames, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, copy_binary, + out_frames, NULL, NULL); + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, + ©_stage); + if (err != IA_CSS_SUCCESS) + goto ERR; + in_frame = me->stages->args.out_frame[0]; + } else if (pipe->stream->config.continuous) { +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + /* When continous is enabled, configure in_frame with the + * last pipe, which is the copy pipe. + */ + in_frame = pipe->stream->last_pipe->continuous_frames[0]; +#else + in_frame = pipe->continuous_frames[0]; +#endif + } + + ia_css_pipe_util_set_output_frames(out_frames, 0, need_yuv_pp ? NULL : out_frame); + + /* when the video binary supports a second output pin, + it can directly produce the vf_frame. */ + if(need_vf_pp) { + ia_css_pipe_get_generic_stage_desc(&stage_desc, video_binary, + out_frames, in_frame, NULL); + } else { + ia_css_pipe_get_generic_stage_desc(&stage_desc, video_binary, + out_frames, in_frame, vf_frame); + } + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, + &video_stage); + if (err != IA_CSS_SUCCESS) + goto ERR; + + /* If we use copy iso video, the input must be yuv iso raw */ + if(video_stage) { + video_stage->args.copy_vf = + video_binary->info->sp.pipeline.mode == IA_CSS_BINARY_MODE_COPY; + video_stage->args.copy_output = video_stage->args.copy_vf; + } + + /* when the video binary supports only 1 output pin, vf_pp is needed to + produce the vf_frame.*/ + if (need_vf_pp && video_stage) { + in_frame = video_stage->args.out_vf_frame; + err = add_vf_pp_stage(pipe, in_frame, vf_frame, vf_pp_binary, + &vf_pp_stage); + if (err != IA_CSS_SUCCESS) + goto ERR; + } + if (video_stage) { + int frm; +#ifndef ISP2401 + for (frm = 0; frm < NUM_VIDEO_TNR_FRAMES; frm++) { +#else + for (frm = 0; frm < NUM_TNR_FRAMES; frm++) { +#endif + video_stage->args.tnr_frames[frm] = + pipe->pipe_settings.video.tnr_frames[frm]; + } + for (frm = 0; frm < MAX_NUM_VIDEO_DELAY_FRAMES; frm++) { + video_stage->args.delay_frames[frm] = + pipe->pipe_settings.video.delay_frames[frm]; + } + } + + /* Append Extension on Video out, if enabled */ + if (!need_vf_pp && video_stage && pipe->config.acc_extension && + (pipe->config.acc_extension->info.isp.type == IA_CSS_ACC_OUTPUT)) + { + struct ia_css_frame *out = NULL; + struct ia_css_frame *in = NULL; + + if ((pipe->config.acc_extension->info.isp.sp.enable.output) && + (pipe->config.acc_extension->info.isp.sp.enable.in_frame) && + (pipe->config.acc_extension->info.isp.sp.enable.out_frame)) { + + /* In/Out Frame mapping to support output frame extension.*/ + out = video_stage->args.out_frame[0]; + err = ia_css_frame_allocate_from_info(&in, &(pipe->output_info[0])); + if (err != IA_CSS_SUCCESS) + goto ERR; + video_stage->args.out_frame[0] = in; + } + + err = add_firmwares( me, video_binary, pipe->output_stage, + last_output_firmware(pipe->output_stage), + IA_CSS_BINARY_MODE_VIDEO, + in, out, NULL, &video_stage, NULL); + if (err != IA_CSS_SUCCESS) + goto ERR; + } + + if (need_yuv_pp && video_stage) { + struct ia_css_frame *tmp_in_frame = video_stage->args.out_frame[0]; + struct ia_css_frame *tmp_out_frame = NULL; + + for (i = 0; i < num_yuv_scaler; i++) { + if (is_output_stage[i] == true) { + tmp_out_frame = out_frame; + } else { + tmp_out_frame = NULL; + } + err = add_yuv_scaler_stage(pipe, me, tmp_in_frame, tmp_out_frame, + NULL, + &yuv_scaler_binary[i], + &yuv_scaler_stage); + + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + /* we use output port 1 as internal output port */ + if (yuv_scaler_stage) + tmp_in_frame = yuv_scaler_stage->args.out_frame[1]; + } + } + + pipe->pipeline.acquire_isp_each_stage = false; + ia_css_pipeline_finalize_stages(&pipe->pipeline, pipe->stream->config.continuous); + +ERR: + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static enum ia_css_err +create_host_acc_pipeline(struct ia_css_pipe *pipe) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + unsigned int i; + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + if ((pipe == NULL) || (pipe->stream == NULL)) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + pipe->pipeline.num_execs = pipe->config.acc_num_execs; + /* Reset pipe_qos_config to default disable all QOS extension stages */ + if (pipe->config.acc_extension) + pipe->pipeline.pipe_qos_config = 0; + +{ + const struct ia_css_fw_info *fw = pipe->vf_stage; + for (i = 0; fw; fw = fw->next){ + err = sh_css_pipeline_add_acc_stage(&pipe->pipeline, fw); + if (err != IA_CSS_SUCCESS) + goto ERR; + } +} + + for (i=0; iconfig.num_acc_stages; i++) { + struct ia_css_fw_info *fw = pipe->config.acc_stages[i]; + err = sh_css_pipeline_add_acc_stage(&pipe->pipeline, fw); + if (err != IA_CSS_SUCCESS) + goto ERR; + } + + ia_css_pipeline_finalize_stages(&pipe->pipeline, pipe->stream->config.continuous); + +ERR: + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +/* Create stages for preview */ +static enum ia_css_err +create_host_preview_pipeline(struct ia_css_pipe *pipe) +{ + struct ia_css_pipeline_stage *copy_stage = NULL; + struct ia_css_pipeline_stage *preview_stage = NULL; + struct ia_css_pipeline_stage *vf_pp_stage = NULL; + struct ia_css_pipeline_stage_desc stage_desc; + struct ia_css_pipeline *me = NULL; + struct ia_css_binary *copy_binary, *preview_binary, *vf_pp_binary = NULL; + struct ia_css_frame *in_frame = NULL; + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_frame *out_frame; + struct ia_css_frame *out_frames[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + bool need_in_frameinfo_memory = false; +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + bool sensor = false; + bool buffered_sensor = false; + bool online = false; + bool continuous = false; +#endif + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + if ((pipe == NULL) || (pipe->stream == NULL) || (pipe->mode != IA_CSS_PIPE_ID_PREVIEW)) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + + ia_css_pipe_util_create_output_frames(out_frames); + /* pipeline already created as part of create_host_pipeline_structure */ + me = &pipe->pipeline; + ia_css_pipeline_clean(me); + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + /* When the input system is 2401, always enable 'in_frameinfo_memory' + * except for the following: + * - Direct Sensor Mode Online Preview + * - Buffered Sensor Mode Online Preview + * - Direct Sensor Mode Continuous Preview + * - Buffered Sensor Mode Continous Preview + */ + sensor = (pipe->stream->config.mode == IA_CSS_INPUT_MODE_SENSOR); + buffered_sensor = (pipe->stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR); + online = pipe->stream->config.online; + continuous = pipe->stream->config.continuous; + need_in_frameinfo_memory = + !((sensor && (online || continuous)) || (buffered_sensor && (online || continuous))); +#else + /* Construct in_frame info (only in case we have dynamic input */ + need_in_frameinfo_memory = pipe->stream->config.mode == IA_CSS_INPUT_MODE_MEMORY; +#endif + if (need_in_frameinfo_memory) { + err = init_in_frameinfo_memory_defaults(pipe, &me->in_frame, IA_CSS_FRAME_FORMAT_RAW); + if (err != IA_CSS_SUCCESS) + goto ERR; + + in_frame = &me->in_frame; + } else { + in_frame = NULL; + } + + err = init_out_frameinfo_defaults(pipe, &me->out_frame[0], 0); + if (err != IA_CSS_SUCCESS) + goto ERR; + out_frame = &me->out_frame[0]; + + copy_binary = &pipe->pipe_settings.preview.copy_binary; + preview_binary = &pipe->pipe_settings.preview.preview_binary; + if (pipe->pipe_settings.preview.vf_pp_binary.info) + vf_pp_binary = &pipe->pipe_settings.preview.vf_pp_binary; + + if (pipe->pipe_settings.preview.copy_binary.info) { + ia_css_pipe_util_set_output_frames(out_frames, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, copy_binary, + out_frames, NULL, NULL); + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, + ©_stage); + if (err != IA_CSS_SUCCESS) + goto ERR; + in_frame = me->stages->args.out_frame[0]; +#ifndef ISP2401 + } else { +#else + } else if (pipe->stream->config.continuous) { +#endif +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + /* When continuous is enabled, configure in_frame with the + * last pipe, which is the copy pipe. + */ + if (continuous || !online){ + in_frame = pipe->stream->last_pipe->continuous_frames[0]; + } +#else + in_frame = pipe->continuous_frames[0]; +#endif + } + + if (vf_pp_binary) { + ia_css_pipe_util_set_output_frames(out_frames, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, preview_binary, + out_frames, in_frame, NULL); + } else { + ia_css_pipe_util_set_output_frames(out_frames, 0, out_frame); + ia_css_pipe_get_generic_stage_desc(&stage_desc, preview_binary, + out_frames, in_frame, NULL); + } + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, + &preview_stage); + if (err != IA_CSS_SUCCESS) + goto ERR; + /* If we use copy iso preview, the input must be yuv iso raw */ + preview_stage->args.copy_vf = + preview_binary->info->sp.pipeline.mode == IA_CSS_BINARY_MODE_COPY; + preview_stage->args.copy_output = !preview_stage->args.copy_vf; + if (preview_stage->args.copy_vf && !preview_stage->args.out_vf_frame) { + /* in case of copy, use the vf frame as output frame */ + preview_stage->args.out_vf_frame = + preview_stage->args.out_frame[0]; + } + if (vf_pp_binary) { + if (preview_binary->info->sp.pipeline.mode == IA_CSS_BINARY_MODE_COPY) + in_frame = preview_stage->args.out_vf_frame; + else + in_frame = preview_stage->args.out_frame[0]; + err = add_vf_pp_stage(pipe, in_frame, out_frame, vf_pp_binary, + &vf_pp_stage); + if (err != IA_CSS_SUCCESS) + goto ERR; + } + + pipe->pipeline.acquire_isp_each_stage = false; + ia_css_pipeline_finalize_stages(&pipe->pipeline, pipe->stream->config.continuous); + +ERR: + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static void send_raw_frames(struct ia_css_pipe *pipe) +{ + if (pipe->stream->config.continuous) { + unsigned int i; + + sh_css_update_host2sp_cont_num_raw_frames + (pipe->stream->config.init_num_cont_raw_buf, true); + sh_css_update_host2sp_cont_num_raw_frames + (pipe->stream->config.target_num_cont_raw_buf, false); + + /* Hand-over all the SP-internal buffers */ + for (i = 0; i < pipe->stream->config.init_num_cont_raw_buf; i++) { + sh_css_update_host2sp_offline_frame(i, + pipe->continuous_frames[i], pipe->cont_md_buffers[i]); + } + } + + return; +} + +static enum ia_css_err +preview_start(struct ia_css_pipe *pipe) +{ + struct ia_css_pipeline *me ; + struct ia_css_binary *copy_binary, *preview_binary, *vf_pp_binary = NULL; + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_pipe *copy_pipe, *capture_pipe; + struct ia_css_pipe *acc_pipe; + enum sh_css_pipe_config_override copy_ovrd; + enum ia_css_input_mode preview_pipe_input_mode; + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + if ((pipe == NULL) || (pipe->stream == NULL) || (pipe->mode != IA_CSS_PIPE_ID_PREVIEW)) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + me = &pipe->pipeline; + + preview_pipe_input_mode = pipe->stream->config.mode; + + copy_pipe = pipe->pipe_settings.preview.copy_pipe; + capture_pipe = pipe->pipe_settings.preview.capture_pipe; + acc_pipe = pipe->pipe_settings.preview.acc_pipe; + + copy_binary = &pipe->pipe_settings.preview.copy_binary; + preview_binary = &pipe->pipe_settings.preview.preview_binary; + if (pipe->pipe_settings.preview.vf_pp_binary.info) + vf_pp_binary = &pipe->pipe_settings.preview.vf_pp_binary; + + sh_css_metrics_start_frame(); + +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) + /* multi stream video needs mipi buffers */ + err = send_mipi_frames(pipe); + if (err != IA_CSS_SUCCESS) + goto ERR; +#endif + send_raw_frames(pipe); + + { + unsigned int thread_id; + + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + copy_ovrd = 1 << thread_id; + + if (pipe->stream->cont_capt) { + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(capture_pipe), &thread_id); + copy_ovrd |= 1 << thread_id; + } + } + + /* Construct and load the copy pipe */ + if (pipe->stream->config.continuous) { + sh_css_sp_init_pipeline(©_pipe->pipeline, + IA_CSS_PIPE_ID_COPY, + (uint8_t)ia_css_pipe_get_pipe_num(copy_pipe), + false, + pipe->stream->config.pixels_per_clock == 2, false, + false, pipe->required_bds_factor, + copy_ovrd, + pipe->stream->config.mode, + &pipe->stream->config.metadata_config, +#ifndef ISP2401 + &pipe->stream->info.metadata_info +#else + &pipe->stream->info.metadata_info, +#endif +#if !defined(HAS_NO_INPUT_SYSTEM) +#ifndef ISP2401 + , pipe->stream->config.source.port.port +#else + pipe->stream->config.source.port.port, +#endif +#endif +#ifndef ISP2401 + ); +#else + &pipe->config.internal_frame_origin_bqs_on_sctbl, + pipe->stream->isp_params_configs); +#endif + + /* make the preview pipe start with mem mode input, copy handles + the actual mode */ + preview_pipe_input_mode = IA_CSS_INPUT_MODE_MEMORY; + } + + /* Construct and load the capture pipe */ + if (pipe->stream->cont_capt) { + sh_css_sp_init_pipeline(&capture_pipe->pipeline, + IA_CSS_PIPE_ID_CAPTURE, + (uint8_t)ia_css_pipe_get_pipe_num(capture_pipe), + capture_pipe->config.default_capture_config.enable_xnr != 0, + capture_pipe->stream->config.pixels_per_clock == 2, + true, /* continuous */ + false, /* offline */ + capture_pipe->required_bds_factor, + 0, + IA_CSS_INPUT_MODE_MEMORY, + &pipe->stream->config.metadata_config, +#ifndef ISP2401 + &pipe->stream->info.metadata_info +#else + &pipe->stream->info.metadata_info, +#endif +#if !defined(HAS_NO_INPUT_SYSTEM) +#ifndef ISP2401 + , (mipi_port_ID_t)0 +#else + (mipi_port_ID_t)0, +#endif +#endif +#ifndef ISP2401 + ); +#else + &capture_pipe->config.internal_frame_origin_bqs_on_sctbl, + capture_pipe->stream->isp_params_configs); +#endif + } + + if (acc_pipe) { + sh_css_sp_init_pipeline(&acc_pipe->pipeline, + IA_CSS_PIPE_ID_ACC, + (uint8_t) ia_css_pipe_get_pipe_num(acc_pipe), + false, + pipe->stream->config.pixels_per_clock == 2, + false, /* continuous */ + false, /* offline */ + pipe->required_bds_factor, + 0, + IA_CSS_INPUT_MODE_MEMORY, + NULL, +#ifndef ISP2401 + NULL +#else + NULL, +#endif +#if !defined(HAS_NO_INPUT_SYSTEM) +#ifndef ISP2401 + , (mipi_port_ID_t) 0 +#else + (mipi_port_ID_t) 0, +#endif +#endif +#ifndef ISP2401 + ); +#else + &pipe->config.internal_frame_origin_bqs_on_sctbl, + pipe->stream->isp_params_configs); +#endif + } + + start_pipe(pipe, copy_ovrd, preview_pipe_input_mode); + +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) +ERR: +#endif + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +enum ia_css_err +ia_css_pipe_enqueue_buffer(struct ia_css_pipe *pipe, + const struct ia_css_buffer *buffer) +{ + enum ia_css_err return_err = IA_CSS_SUCCESS; + unsigned int thread_id; + enum sh_css_queue_id queue_id; + struct ia_css_pipeline *pipeline; + struct ia_css_pipeline_stage *stage; + struct ia_css_rmgr_vbuf_handle p_vbuf; + struct ia_css_rmgr_vbuf_handle *h_vbuf; + struct sh_css_hmm_buffer ddr_buffer; + enum ia_css_buffer_type buf_type; + enum ia_css_pipe_id pipe_id; + bool ret_err; + + IA_CSS_ENTER("pipe=%p, buffer=%p", pipe, buffer); + + if ((pipe == NULL) || (buffer == NULL)) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + buf_type = buffer->type; + /* following code will be enabled when IA_CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME + is removed */ +#if 0 + if (buf_type == IA_CSS_BUFFER_TYPE_OUTPUT_FRAME) { + bool found_pipe = false; + for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + if ((buffer->data.frame->info.res.width == pipe->output_info[i].res.width) && + (buffer->data.frame->info.res.height == pipe->output_info[i].res.height)) { + buf_type += i; + found_pipe = true; + break; + } + } + if (!found_pipe) + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + if (buf_type == IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME) { + bool found_pipe = false; + for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + if ((buffer->data.frame->info.res.width == pipe->vf_output_info[i].res.width) && + (buffer->data.frame->info.res.height == pipe->vf_output_info[i].res.height)) { + buf_type += i; + found_pipe = true; + break; + } + } + if (!found_pipe) + return IA_CSS_ERR_INVALID_ARGUMENTS; + } +#endif + pipe_id = pipe->mode; + + IA_CSS_LOG("pipe_id=%d, buf_type=%d", pipe_id, buf_type); + + + assert(pipe_id < IA_CSS_PIPE_ID_NUM); + assert(buf_type < IA_CSS_NUM_DYNAMIC_BUFFER_TYPE); + if ((buf_type == IA_CSS_BUFFER_TYPE_INVALID) || + (buf_type >= IA_CSS_NUM_DYNAMIC_BUFFER_TYPE) || + (pipe_id >= IA_CSS_PIPE_ID_NUM)) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INTERNAL_ERROR); + return IA_CSS_ERR_INTERNAL_ERROR; + } + + ret_err = ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + if (!ret_err) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + ret_err = ia_css_query_internal_queue_id(buf_type, thread_id, &queue_id); + if (!ret_err) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + if ((queue_id <= SH_CSS_INVALID_QUEUE_ID) || (queue_id >= SH_CSS_MAX_NUM_QUEUES)) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + if (!sh_css_sp_is_running()) { + IA_CSS_LOG("SP is not running!"); + IA_CSS_LEAVE_ERR(IA_CSS_ERR_RESOURCE_NOT_AVAILABLE); + /* SP is not running. The queues are not valid */ + return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } + + + pipeline = &pipe->pipeline; + + assert(pipeline != NULL || + pipe_id == IA_CSS_PIPE_ID_COPY || + pipe_id == IA_CSS_PIPE_ID_ACC); + + assert(sizeof(NULL) <= sizeof(ddr_buffer.kernel_ptr)); + ddr_buffer.kernel_ptr = HOST_ADDRESS(NULL); + ddr_buffer.cookie_ptr = buffer->driver_cookie; + ddr_buffer.timing_data = buffer->timing_data; + + if (buf_type == IA_CSS_BUFFER_TYPE_3A_STATISTICS) { + if (buffer->data.stats_3a == NULL) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + ddr_buffer.kernel_ptr = HOST_ADDRESS(buffer->data.stats_3a); + ddr_buffer.payload.s3a = *buffer->data.stats_3a; + } else if (buf_type == IA_CSS_BUFFER_TYPE_DIS_STATISTICS) { + if (buffer->data.stats_dvs == NULL) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + ddr_buffer.kernel_ptr = HOST_ADDRESS(buffer->data.stats_dvs); + ddr_buffer.payload.dis = *buffer->data.stats_dvs; + } else if (buf_type == IA_CSS_BUFFER_TYPE_METADATA) { + if (buffer->data.metadata == NULL) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + ddr_buffer.kernel_ptr = HOST_ADDRESS(buffer->data.metadata); + ddr_buffer.payload.metadata = *buffer->data.metadata; + } else if ((buf_type == IA_CSS_BUFFER_TYPE_INPUT_FRAME) + || (buf_type == IA_CSS_BUFFER_TYPE_OUTPUT_FRAME) + || (buf_type == IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME) + || (buf_type == IA_CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME) + || (buf_type == IA_CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME)) { + if (buffer->data.frame == NULL) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + ddr_buffer.kernel_ptr = HOST_ADDRESS(buffer->data.frame); + ddr_buffer.payload.frame.frame_data = buffer->data.frame->data; + ddr_buffer.payload.frame.flashed = 0; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipe_enqueue_buffer() buf_type=%d, data(DDR address)=0x%x\n", + buf_type, buffer->data.frame->data); + + +#if CONFIG_ON_FRAME_ENQUEUE() + return_err = set_config_on_frame_enqueue( + &buffer->data.frame->info, + &ddr_buffer.payload.frame); + if (IA_CSS_SUCCESS != return_err) { + IA_CSS_LEAVE_ERR(return_err); + return return_err; + } +#endif + } + + /* start of test for using rmgr for acq/rel memory */ + p_vbuf.vptr = 0; + p_vbuf.count = 0; + p_vbuf.size = sizeof(struct sh_css_hmm_buffer); + h_vbuf = &p_vbuf; + /* TODO: change next to correct pool for optimization */ + ia_css_rmgr_acq_vbuf(hmm_buffer_pool, &h_vbuf); + + assert(h_vbuf != NULL); + assert(h_vbuf->vptr != 0x0); + + if ((h_vbuf == NULL) || (h_vbuf->vptr == 0x0)) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INTERNAL_ERROR); + return IA_CSS_ERR_INTERNAL_ERROR; + } + + mmgr_store(h_vbuf->vptr, + (void *)(&ddr_buffer), + sizeof(struct sh_css_hmm_buffer)); + if ((buf_type == IA_CSS_BUFFER_TYPE_3A_STATISTICS) + || (buf_type == IA_CSS_BUFFER_TYPE_DIS_STATISTICS) + || (buf_type == IA_CSS_BUFFER_TYPE_LACE_STATISTICS)) { + if (pipeline == NULL) { + ia_css_rmgr_rel_vbuf(hmm_buffer_pool, &h_vbuf); + IA_CSS_LOG("pipeline is empty!"); + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INTERNAL_ERROR); + return IA_CSS_ERR_INTERNAL_ERROR; + } + + for (stage = pipeline->stages; stage; stage = stage->next) { + /* The SP will read the params + after it got empty 3a and dis */ + if (STATS_ENABLED(stage)) { + /* there is a stage that needs it */ + return_err = ia_css_bufq_enqueue_buffer(thread_id, + queue_id, + (uint32_t)h_vbuf->vptr); + } + } + } else if ((buf_type == IA_CSS_BUFFER_TYPE_INPUT_FRAME) + || (buf_type == IA_CSS_BUFFER_TYPE_OUTPUT_FRAME) + || (buf_type == IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME) + || (buf_type == IA_CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME) + || (buf_type == IA_CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME) + || (buf_type == IA_CSS_BUFFER_TYPE_METADATA)) { + return_err = ia_css_bufq_enqueue_buffer(thread_id, + queue_id, + (uint32_t)h_vbuf->vptr); +#if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS) + if ((return_err == IA_CSS_SUCCESS) && (IA_CSS_BUFFER_TYPE_OUTPUT_FRAME == buf_type)) { + IA_CSS_LOG("pfp: enqueued OF %d to q %d thread %d", + ddr_buffer.payload.frame.frame_data, + queue_id, thread_id); + } +#endif + + } + + if (return_err == IA_CSS_SUCCESS) { +#ifndef ISP2401 + bool found_record = false; + found_record = sh_css_hmm_buffer_record_acquire( +#else + struct sh_css_hmm_buffer_record *hmm_buffer_record = NULL; + + hmm_buffer_record = sh_css_hmm_buffer_record_acquire( +#endif + h_vbuf, buf_type, + HOST_ADDRESS(ddr_buffer.kernel_ptr)); +#ifndef ISP2401 + if (found_record == true) { +#else + if (hmm_buffer_record) { +#endif + IA_CSS_LOG("send vbuf=0x%x", h_vbuf); + } else { + return_err = IA_CSS_ERR_INTERNAL_ERROR; + IA_CSS_ERROR("hmm_buffer_record[]: no available slots\n"); + } + } + + /* + * Tell the SP which queues are not empty, + * by sending the software event. + */ + if (return_err == IA_CSS_SUCCESS) { + if (!sh_css_sp_is_running()) { + /* SP is not running. The queues are not valid */ + IA_CSS_LOG("SP is not running!"); + IA_CSS_LEAVE_ERR(IA_CSS_ERR_RESOURCE_NOT_AVAILABLE); + return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } + return_err = ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_BUFFER_ENQUEUED, + (uint8_t)thread_id, + queue_id, + 0); + } else { + ia_css_rmgr_rel_vbuf(hmm_buffer_pool, &h_vbuf); + IA_CSS_ERROR("buffer not enqueued"); + } + + IA_CSS_LEAVE("return value = %d", return_err); + + return return_err; +} + +/* + * TODO: Free up the hmm memory space. + */ +enum ia_css_err +ia_css_pipe_dequeue_buffer(struct ia_css_pipe *pipe, + struct ia_css_buffer *buffer) +{ + enum ia_css_err return_err; + enum sh_css_queue_id queue_id; + hrt_vaddress ddr_buffer_addr = (hrt_vaddress)0; + struct sh_css_hmm_buffer ddr_buffer; + enum ia_css_buffer_type buf_type; + enum ia_css_pipe_id pipe_id; + unsigned int thread_id; + hrt_address kernel_ptr = 0; + bool ret_err; + + IA_CSS_ENTER("pipe=%p, buffer=%p", pipe, buffer); + + if ((pipe == NULL) || (buffer == NULL)) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + pipe_id = pipe->mode; + + buf_type = buffer->type; + + IA_CSS_LOG("pipe_id=%d, buf_type=%d", pipe_id, buf_type); + + ddr_buffer.kernel_ptr = 0; + + ret_err = ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + if (!ret_err) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + ret_err = ia_css_query_internal_queue_id(buf_type, thread_id, &queue_id); + if (!ret_err) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + if ((queue_id <= SH_CSS_INVALID_QUEUE_ID) || (queue_id >= SH_CSS_MAX_NUM_QUEUES)) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + if (!sh_css_sp_is_running()) { + IA_CSS_LOG("SP is not running!"); + IA_CSS_LEAVE_ERR(IA_CSS_ERR_RESOURCE_NOT_AVAILABLE); + /* SP is not running. The queues are not valid */ + return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } + + return_err = ia_css_bufq_dequeue_buffer(queue_id, + (uint32_t *)&ddr_buffer_addr); + + if (return_err == IA_CSS_SUCCESS) { + struct ia_css_frame *frame; + struct sh_css_hmm_buffer_record *hmm_buffer_record = NULL; + + IA_CSS_LOG("receive vbuf=%x", (int)ddr_buffer_addr); + + /* Validate the ddr_buffer_addr and buf_type */ + hmm_buffer_record = sh_css_hmm_buffer_record_validate( + ddr_buffer_addr, buf_type); + if (hmm_buffer_record != NULL) { + /* valid hmm_buffer_record found. Save the kernel_ptr + * for validation after performing mmgr_load. The + * vbuf handle and buffer_record can be released. + */ + kernel_ptr = hmm_buffer_record->kernel_ptr; + ia_css_rmgr_rel_vbuf(hmm_buffer_pool, &hmm_buffer_record->h_vbuf); + sh_css_hmm_buffer_record_reset(hmm_buffer_record); + } else { + IA_CSS_ERROR("hmm_buffer_record not found (0x%p) buf_type(%d)", + ddr_buffer_addr, buf_type); + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INTERNAL_ERROR); + return IA_CSS_ERR_INTERNAL_ERROR; + } + + mmgr_load(ddr_buffer_addr, + &ddr_buffer, + sizeof(struct sh_css_hmm_buffer)); + + /* if the kernel_ptr is 0 or an invalid, return an error. + * do not access the buffer via the kernal_ptr. + */ + if ((ddr_buffer.kernel_ptr == 0) || + (kernel_ptr != HOST_ADDRESS(ddr_buffer.kernel_ptr))) { + IA_CSS_ERROR("kernel_ptr invalid"); + IA_CSS_ERROR("expected: (0x%p)", kernel_ptr); + IA_CSS_ERROR("actual: (0x%p)", HOST_ADDRESS(ddr_buffer.kernel_ptr)); + IA_CSS_ERROR("buf_type: %d\n", buf_type); + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INTERNAL_ERROR); + return IA_CSS_ERR_INTERNAL_ERROR; + } + + if (ddr_buffer.kernel_ptr != 0) { + /* buffer->exp_id : all instances to be removed later once the driver change + * is completed. See patch #5758 for reference */ + buffer->exp_id = 0; + buffer->driver_cookie = ddr_buffer.cookie_ptr; + buffer->timing_data = ddr_buffer.timing_data; + + if ((buf_type == IA_CSS_BUFFER_TYPE_OUTPUT_FRAME) || + (buf_type == IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME)) { + buffer->isys_eof_clock_tick.ticks = ddr_buffer.isys_eof_clock_tick; + } + + switch (buf_type) { + case IA_CSS_BUFFER_TYPE_INPUT_FRAME: + case IA_CSS_BUFFER_TYPE_OUTPUT_FRAME: + case IA_CSS_BUFFER_TYPE_SEC_OUTPUT_FRAME: + if ((pipe) && (pipe->stop_requested == true)) + { + +#if defined(USE_INPUT_SYSTEM_VERSION_2) + /* free mipi frames only for old input system + * for 2401 it is done in ia_css_stream_destroy call + */ + return_err = free_mipi_frames(pipe); + if (return_err != IA_CSS_SUCCESS) { + IA_CSS_LOG("free_mipi_frames() failed"); + IA_CSS_LEAVE_ERR(return_err); + return return_err; + } +#endif + pipe->stop_requested = false; + } + case IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME: + case IA_CSS_BUFFER_TYPE_SEC_VF_OUTPUT_FRAME: + frame = (struct ia_css_frame*)HOST_ADDRESS(ddr_buffer.kernel_ptr); + buffer->data.frame = frame; + buffer->exp_id = ddr_buffer.payload.frame.exp_id; + frame->exp_id = ddr_buffer.payload.frame.exp_id; + frame->isp_config_id = ddr_buffer.payload.frame.isp_parameters_id; + if (ddr_buffer.payload.frame.flashed == 1) + frame->flash_state = + IA_CSS_FRAME_FLASH_STATE_PARTIAL; + if (ddr_buffer.payload.frame.flashed == 2) + frame->flash_state = + IA_CSS_FRAME_FLASH_STATE_FULL; + frame->valid = pipe->num_invalid_frames == 0; + if (!frame->valid) + pipe->num_invalid_frames--; + + if (frame->info.format == IA_CSS_FRAME_FORMAT_BINARY_8) { +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + frame->planes.binary.size = frame->data_bytes; +#else + frame->planes.binary.size = + sh_css_sp_get_binary_copy_size(); +#endif + } +#if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS) + if (IA_CSS_BUFFER_TYPE_OUTPUT_FRAME == buf_type) { + IA_CSS_LOG("pfp: dequeued OF %d with config id %d thread %d", + frame->data, frame->isp_config_id, thread_id); + } +#endif + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipe_dequeue_buffer() buf_type=%d, data(DDR address)=0x%x\n", + buf_type, buffer->data.frame->data); + + break; + case IA_CSS_BUFFER_TYPE_3A_STATISTICS: + buffer->data.stats_3a = + (struct ia_css_isp_3a_statistics*)HOST_ADDRESS(ddr_buffer.kernel_ptr); + buffer->exp_id = ddr_buffer.payload.s3a.exp_id; + buffer->data.stats_3a->exp_id = ddr_buffer.payload.s3a.exp_id; + buffer->data.stats_3a->isp_config_id = ddr_buffer.payload.s3a.isp_config_id; + break; + case IA_CSS_BUFFER_TYPE_DIS_STATISTICS: + buffer->data.stats_dvs = + (struct ia_css_isp_dvs_statistics*) + HOST_ADDRESS(ddr_buffer.kernel_ptr); + buffer->exp_id = ddr_buffer.payload.dis.exp_id; + buffer->data.stats_dvs->exp_id = ddr_buffer.payload.dis.exp_id; + break; + case IA_CSS_BUFFER_TYPE_LACE_STATISTICS: + break; + case IA_CSS_BUFFER_TYPE_METADATA: + buffer->data.metadata = + (struct ia_css_metadata*)HOST_ADDRESS(ddr_buffer.kernel_ptr); + buffer->exp_id = ddr_buffer.payload.metadata.exp_id; + buffer->data.metadata->exp_id = ddr_buffer.payload.metadata.exp_id; + break; + default: + return_err = IA_CSS_ERR_INTERNAL_ERROR; + break; + } + } + } + + /* + * Tell the SP which queues are not full, + * by sending the software event. + */ + if (return_err == IA_CSS_SUCCESS){ + if (!sh_css_sp_is_running()) { + IA_CSS_LOG("SP is not running!"); + IA_CSS_LEAVE_ERR(IA_CSS_ERR_RESOURCE_NOT_AVAILABLE); + /* SP is not running. The queues are not valid */ + return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } + ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_BUFFER_DEQUEUED, + 0, + queue_id, + 0); + } + IA_CSS_LEAVE("buffer=%p", buffer); + + return return_err; +} + +/* + * Cannot Move this to event module as it is of ia_css_event_type which is declared in ia_css.h + * TODO: modify and move it if possible. + * + * !!!IMPORTANT!!! KEEP THE FOLLOWING IN SYNC: + * 1) "enum ia_css_event_type" (ia_css_event_public.h) + * 2) "enum sh_css_sp_event_type" (sh_css_internal.h) + * 3) "enum ia_css_event_type event_id_2_event_mask" (event_handler.sp.c) + * 4) "enum ia_css_event_type convert_event_sp_to_host_domain" (sh_css.c) + */ +static enum ia_css_event_type convert_event_sp_to_host_domain[] = { + IA_CSS_EVENT_TYPE_OUTPUT_FRAME_DONE, /**< Output frame ready. */ + IA_CSS_EVENT_TYPE_SECOND_OUTPUT_FRAME_DONE, /**< Second output frame ready. */ + IA_CSS_EVENT_TYPE_VF_OUTPUT_FRAME_DONE, /**< Viewfinder Output frame ready. */ + IA_CSS_EVENT_TYPE_SECOND_VF_OUTPUT_FRAME_DONE, /**< Second viewfinder Output frame ready. */ + IA_CSS_EVENT_TYPE_3A_STATISTICS_DONE, /**< Indication that 3A statistics are available. */ + IA_CSS_EVENT_TYPE_DIS_STATISTICS_DONE, /**< Indication that DIS statistics are available. */ + IA_CSS_EVENT_TYPE_PIPELINE_DONE, /**< Pipeline Done event, sent after last pipeline stage. */ + IA_CSS_EVENT_TYPE_FRAME_TAGGED, /**< Frame tagged. */ + IA_CSS_EVENT_TYPE_INPUT_FRAME_DONE, /**< Input frame ready. */ + IA_CSS_EVENT_TYPE_METADATA_DONE, /**< Metadata ready. */ + IA_CSS_EVENT_TYPE_LACE_STATISTICS_DONE, /**< Indication that LACE statistics are available. */ + IA_CSS_EVENT_TYPE_ACC_STAGE_COMPLETE, /**< Extension stage executed. */ + IA_CSS_EVENT_TYPE_TIMER, /**< Timing measurement data. */ + IA_CSS_EVENT_TYPE_PORT_EOF, /**< End Of Frame event, sent when in buffered sensor mode. */ + IA_CSS_EVENT_TYPE_FW_WARNING, /**< Performance warning encountered by FW */ + IA_CSS_EVENT_TYPE_FW_ASSERT, /**< Assertion hit by FW */ + 0, /** error if sp passes SH_CSS_SP_EVENT_NR_OF_TYPES as a valid event. */ +}; + +enum ia_css_err +ia_css_dequeue_event(struct ia_css_event *event) +{ + return ia_css_dequeue_psys_event(event); +} + +enum ia_css_err +ia_css_dequeue_psys_event(struct ia_css_event *event) +{ + enum ia_css_pipe_id pipe_id = 0; + uint8_t payload[4] = {0,0,0,0}; + enum ia_css_err ret_err; + + /*TODO: + * a) use generic decoding function , same as the one used by sp. + * b) group decode and dequeue into eventQueue module + * + * We skip the IA_CSS_ENTER logging call + * to avoid flooding the logs when the host application + * uses polling. */ + if (event == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + if (!sh_css_sp_is_running()) { + /* SP is not running. The queues are not valid */ + return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } + + /* dequeue the event (if any) from the psys event queue */ + ret_err = ia_css_bufq_dequeue_psys_event(payload); + if (ret_err != IA_CSS_SUCCESS) + return ret_err; + + IA_CSS_LOG("event dequeued from psys event queue"); + + /* Tell the SP that we dequeued an event from the event queue. */ + ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_EVENT_DEQUEUED, 0, 0, 0); + + /* Events are decoded into 4 bytes of payload, the first byte + * contains the sp event type. This is converted to a host enum. + * TODO: can this enum conversion be eliminated */ + event->type = convert_event_sp_to_host_domain[payload[0]]; + /* Some sane default values since not all events use all fields. */ + event->pipe = NULL; + event->port = IA_CSS_CSI2_PORT0; + event->exp_id = 0; + event->fw_warning = IA_CSS_FW_WARNING_NONE; + event->fw_handle = 0; + event->timer_data = 0; + event->timer_code = 0; + event->timer_subcode = 0; + + if (event->type == IA_CSS_EVENT_TYPE_TIMER) { + /* timer event ??? get the 2nd event and decode the data into the event struct */ + uint32_t tmp_data; + /* 1st event: LSB 16-bit timer data and code */ + event->timer_data = ((payload[1] & 0xFF) | ((payload[3] & 0xFF) << 8)); + event->timer_code = payload[2]; + payload[0] = payload[1] = payload[2] = payload[3] = 0; + ret_err = ia_css_bufq_dequeue_psys_event(payload); + if (ret_err != IA_CSS_SUCCESS) { + /* no 2nd event ??? an error */ + /* Putting IA_CSS_ERROR is resulting in failures in + * Merrifield smoke testing */ + IA_CSS_WARNING("Timer: Error de-queuing the 2nd TIMER event!!!\n"); + return ret_err; + } + ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_EVENT_DEQUEUED, 0, 0, 0); + event->type = convert_event_sp_to_host_domain[payload[0]]; + /* It's a timer */ + if (event->type == IA_CSS_EVENT_TYPE_TIMER) { + /* 2nd event data: MSB 16-bit timer and subcode */ + tmp_data = ((payload[1] & 0xFF) | ((payload[3] & 0xFF) << 8)); + event->timer_data |= (tmp_data << 16); + event->timer_subcode = payload[2]; + } + /* It's a non timer event. So clear first half of the timer event data. + * If the second part of the TIMER event is not recieved, we discard + * the first half of the timer data and process the non timer event without + * affecting the flow. So the non timer event falls through + * the code. */ + else { + event->timer_data = 0; + event->timer_code = 0; + event->timer_subcode = 0; + IA_CSS_ERROR("Missing 2nd timer event. Timer event discarded"); + } + } + if (event->type == IA_CSS_EVENT_TYPE_PORT_EOF) { + event->port = (enum ia_css_csi2_port)payload[1]; + event->exp_id = payload[3]; + } else if (event->type == IA_CSS_EVENT_TYPE_FW_WARNING) { + event->fw_warning = (enum ia_css_fw_warning)payload[1]; + /* exp_id is only available in these warning types */ + if (event->fw_warning == IA_CSS_FW_WARNING_EXP_ID_LOCKED || + event->fw_warning == IA_CSS_FW_WARNING_TAG_EXP_ID_FAILED) + event->exp_id = payload[3]; + } else if (event->type == IA_CSS_EVENT_TYPE_FW_ASSERT) { + event->fw_assert_module_id = payload[1]; /* module */ + event->fw_assert_line_no = (payload[2] << 8) + payload[3]; + /* payload[2] is line_no>>8, payload[3] is line_no&0xff */ + } else if (event->type != IA_CSS_EVENT_TYPE_TIMER) { + /* pipe related events. + * payload[1] contains the pipe_num, + * payload[2] contains the pipe_id. These are different. */ + event->pipe = find_pipe_by_num(payload[1]); + pipe_id = (enum ia_css_pipe_id)payload[2]; + /* Check to see if pipe still exists */ + if (!event->pipe) + return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + + if (event->type == IA_CSS_EVENT_TYPE_FRAME_TAGGED) { + /* find the capture pipe that goes with this */ + int i, n; + n = event->pipe->stream->num_pipes; + for (i = 0; i < n; i++) { + struct ia_css_pipe *p = + event->pipe->stream->pipes[i]; + if (p->config.mode == IA_CSS_PIPE_MODE_CAPTURE) { + event->pipe = p; + break; + } + } + event->exp_id = payload[3]; + } + if (event->type == IA_CSS_EVENT_TYPE_ACC_STAGE_COMPLETE) { + /* payload[3] contains the acc fw handle. */ + uint32_t stage_num = (uint32_t)payload[3]; + ret_err = ia_css_pipeline_get_fw_from_stage( + &(event->pipe->pipeline), + stage_num, + &(event->fw_handle)); + if (ret_err != IA_CSS_SUCCESS) { + IA_CSS_ERROR("Invalid stage num received for ACC event. stage_num:%u", + stage_num); + return ret_err; + } + } + } + + if (event->pipe) + IA_CSS_LEAVE("event_id=%d, pipe_id=%d", event->type, pipe_id); + else + IA_CSS_LEAVE("event_id=%d", event->type); + + return IA_CSS_SUCCESS; +} + +enum ia_css_err +ia_css_dequeue_isys_event(struct ia_css_event *event) +{ + uint8_t payload[4] = {0, 0, 0, 0}; + enum ia_css_err err = IA_CSS_SUCCESS; + + /* We skip the IA_CSS_ENTER logging call + * to avoid flooding the logs when the host application + * uses polling. */ + if (event == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + if (!sh_css_sp_is_running()) { + /* SP is not running. The queues are not valid */ + return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } + + err = ia_css_bufq_dequeue_isys_event(payload); + if (err != IA_CSS_SUCCESS) + return err; + + IA_CSS_LOG("event dequeued from isys event queue"); + + /* Update SP state to indicate that element was dequeued. */ + ia_css_bufq_enqueue_isys_event(IA_CSS_ISYS_SW_EVENT_EVENT_DEQUEUED); + + /* Fill return struct with appropriate info */ + event->type = IA_CSS_EVENT_TYPE_PORT_EOF; + /* EOF events are associated with a CSI port, not with a pipe */ + event->pipe = NULL; + event->port = payload[1]; + event->exp_id = payload[3]; + + IA_CSS_LEAVE_ERR(err); + return err; +} + +static void +acc_start(struct ia_css_pipe *pipe) +{ + assert(pipe != NULL); + assert(pipe->stream != NULL); + + start_pipe(pipe, SH_CSS_PIPE_CONFIG_OVRD_NO_OVRD, + pipe->stream->config.mode); +} + +static enum ia_css_err +sh_css_pipe_start(struct ia_css_stream *stream) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + struct ia_css_pipe *pipe; + enum ia_css_pipe_id pipe_id; + unsigned int thread_id; + + IA_CSS_ENTER_PRIVATE("stream = %p", stream); + + if (stream == NULL) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + pipe = stream->last_pipe; + if (pipe == NULL) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + pipe_id = pipe->mode; + + if(stream->started == true) { + IA_CSS_WARNING("Cannot start stream that is already started"); + IA_CSS_LEAVE_ERR(err); + return err; + } + + pipe->stop_requested = false; + + switch (pipe_id) { + case IA_CSS_PIPE_ID_PREVIEW: + err = preview_start(pipe); + break; + case IA_CSS_PIPE_ID_VIDEO: + err = video_start(pipe); + break; + case IA_CSS_PIPE_ID_CAPTURE: + err = capture_start(pipe); + break; + case IA_CSS_PIPE_ID_YUVPP: + err = yuvpp_start(pipe); + break; + case IA_CSS_PIPE_ID_ACC: + acc_start(pipe); + break; + default: + err = IA_CSS_ERR_INVALID_ARGUMENTS; + } + /* DH regular multi pipe - not continuous mode: start the next pipes too */ + if (!stream->config.continuous) { + int i; + for (i = 1; i < stream->num_pipes && IA_CSS_SUCCESS == err ; i++) { + switch (stream->pipes[i]->mode) { + case IA_CSS_PIPE_ID_PREVIEW: + stream->pipes[i]->stop_requested = false; + err = preview_start(stream->pipes[i]); + break; + case IA_CSS_PIPE_ID_VIDEO: + stream->pipes[i]->stop_requested = false; + err = video_start(stream->pipes[i]); + break; + case IA_CSS_PIPE_ID_CAPTURE: + stream->pipes[i]->stop_requested = false; + err = capture_start(stream->pipes[i]); + break; + case IA_CSS_PIPE_ID_YUVPP: + stream->pipes[i]->stop_requested = false; + err = yuvpp_start(stream->pipes[i]); + break; + case IA_CSS_PIPE_ID_ACC: + stream->pipes[i]->stop_requested = false; + acc_start(stream->pipes[i]); + break; + default: + err = IA_CSS_ERR_INVALID_ARGUMENTS; + } + } + } + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + /* Force ISP parameter calculation after a mode change + * Acceleration API examples pass NULL for stream but they + * don't use ISP parameters anyway. So this should be okay. + * The SP binary (jpeg) copy does not use any parameters. + */ + if (!copy_on_sp(pipe)) { + sh_css_invalidate_params(stream); + err = sh_css_param_update_isp_params(pipe, + stream->isp_params_configs, true, NULL); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + + ia_css_debug_pipe_graph_dump_epilogue(); + + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + + if (!sh_css_sp_is_running()) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_RESOURCE_NOT_AVAILABLE); + /* SP is not running. The queues are not valid */ + return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } + ia_css_bufq_enqueue_psys_event(IA_CSS_PSYS_SW_EVENT_START_STREAM, + (uint8_t)thread_id, 0, 0); + + /* DH regular multi pipe - not continuous mode: enqueue event to the next pipes too */ + if (!stream->config.continuous) { + int i; + for (i = 1; i < stream->num_pipes; i++) { + ia_css_pipeline_get_sp_thread_id( + ia_css_pipe_get_pipe_num(stream->pipes[i]), + &thread_id); + ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_START_STREAM, + (uint8_t)thread_id, 0, 0); + } + } + + /* in case of continuous capture mode, we also start capture thread and copy thread*/ + if (pipe->stream->config.continuous) { + struct ia_css_pipe *copy_pipe = NULL; + + if (pipe_id == IA_CSS_PIPE_ID_PREVIEW) + copy_pipe = pipe->pipe_settings.preview.copy_pipe; + else if (pipe_id == IA_CSS_PIPE_ID_VIDEO) + copy_pipe = pipe->pipe_settings.video.copy_pipe; + + if (copy_pipe == NULL) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INTERNAL_ERROR); + return IA_CSS_ERR_INTERNAL_ERROR; + } + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(copy_pipe), &thread_id); + /* by the time we reach here q is initialized and handle is available.*/ + ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_START_STREAM, + (uint8_t)thread_id, 0, 0); + } + if (pipe->stream->cont_capt) { + struct ia_css_pipe *capture_pipe = NULL; + if (pipe_id == IA_CSS_PIPE_ID_PREVIEW) + capture_pipe = pipe->pipe_settings.preview.capture_pipe; + else if (pipe_id == IA_CSS_PIPE_ID_VIDEO) + capture_pipe = pipe->pipe_settings.video.capture_pipe; + + if (capture_pipe == NULL) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INTERNAL_ERROR); + return IA_CSS_ERR_INTERNAL_ERROR; + } + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(capture_pipe), &thread_id); + /* by the time we reach here q is initialized and handle is available.*/ + ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_START_STREAM, + (uint8_t)thread_id, 0, 0); + } + + /* in case of PREVIEW mode, check whether QOS acc_pipe is available, then start the qos pipe */ + if (pipe_id == IA_CSS_PIPE_ID_PREVIEW) { + struct ia_css_pipe *acc_pipe = NULL; + acc_pipe = pipe->pipe_settings.preview.acc_pipe; + + if (acc_pipe){ + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(acc_pipe), &thread_id); + /* by the time we reach here q is initialized and handle is available.*/ + ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_START_STREAM, + (uint8_t) thread_id, 0, 0); + } + } + + stream->started = true; + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +#ifndef ISP2401 +void +sh_css_enable_cont_capt(bool enable, bool stop_copy_preview) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "sh_css_enable_cont_capt() enter: enable=%d\n", enable); +//my_css.cont_capt = enable; + my_css.stop_copy_preview = stop_copy_preview; +} + +bool +sh_css_continuous_is_enabled(uint8_t pipe_num) +#else +/** + * @brief Stop all "ia_css_pipe" instances in the target + * "ia_css_stream" instance. + * + * Refer to "Local prototypes" for more info. + */ +static enum ia_css_err +sh_css_pipes_stop(struct ia_css_stream *stream) +#endif +{ +#ifndef ISP2401 + struct ia_css_pipe *pipe; + bool continuous; +#else + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_pipe *main_pipe; + enum ia_css_pipe_id main_pipe_id; + int i; +#endif + +#ifndef ISP2401 + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sh_css_continuous_is_enabled() enter: pipe_num=%d\n", pipe_num); +#else + assert(stream != NULL); + if (stream == NULL) { + IA_CSS_LOG("stream does NOT exist!"); + err = IA_CSS_ERR_INTERNAL_ERROR; + goto ERR; + } +#endif + +#ifndef ISP2401 + pipe = find_pipe_by_num(pipe_num); + continuous = pipe && pipe->stream->config.continuous; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "sh_css_continuous_is_enabled() leave: enable=%d\n", + continuous); + return continuous; +} +#else + main_pipe = stream->last_pipe; + assert(main_pipe != NULL); + if (main_pipe == NULL) { + IA_CSS_LOG("main_pipe does NOT exist!"); + err = IA_CSS_ERR_INTERNAL_ERROR; + goto ERR; + } +#endif + +#ifndef ISP2401 +enum ia_css_err +ia_css_stream_get_max_buffer_depth(struct ia_css_stream *stream, int *buffer_depth) +{ + if (buffer_depth == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_get_max_buffer_depth() enter: void\n"); + (void)stream; + *buffer_depth = NUM_CONTINUOUS_FRAMES; + return IA_CSS_SUCCESS; +} +#else + main_pipe_id = main_pipe->mode; + IA_CSS_ENTER_PRIVATE("main_pipe_id=%d", main_pipe_id); +#endif + +#ifndef ISP2401 +enum ia_css_err +ia_css_stream_set_buffer_depth(struct ia_css_stream *stream, int buffer_depth) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_set_buffer_depth() enter: num_frames=%d\n",buffer_depth); + (void)stream; + if (buffer_depth > NUM_CONTINUOUS_FRAMES || buffer_depth < 1) + return IA_CSS_ERR_INVALID_ARGUMENTS; + /* ok, value allowed */ + stream->config.target_num_cont_raw_buf = buffer_depth; + /* TODO: check what to regarding initialization */ + return IA_CSS_SUCCESS; +} +#else + /** + * Stop all "ia_css_pipe" instances in this target + * "ia_css_stream" instance. + */ + for (i = 0; i < stream->num_pipes; i++) { + /* send the "stop" request to the "ia_css_pipe" instance */ + IA_CSS_LOG("Send the stop-request to the pipe: pipe_id=%d", + stream->pipes[i]->pipeline.pipe_id); + err = ia_css_pipeline_request_stop(&stream->pipes[i]->pipeline); +#endif + +#ifndef ISP2401 +enum ia_css_err +ia_css_stream_get_buffer_depth(struct ia_css_stream *stream, int *buffer_depth) +{ + if (buffer_depth == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_get_buffer_depth() enter: void\n"); +#else + /* + * Exit this loop if "ia_css_pipeline_request_stop()" + * returns the error code. + * + * The error code would be generated in the following + * two cases: + * (1) The Scalar Processor has already been stopped. + * (2) The "Host->SP" event queue is full. + * + * As the convention of using CSS API 2.0/2.1, such CSS + * error code would be propogated from the CSS-internal + * API returned value to the CSS API returned value. Then + * the CSS driver should capture these error code and + * handle it in the driver exception handling mechanism. + */ + if (err != IA_CSS_SUCCESS) { + goto ERR; + } + } + + /** + * In the CSS firmware use scenario "Continuous Preview" + * as well as "Continuous Video", the "ia_css_pipe" instance + * "Copy Pipe" is activated. This "Copy Pipe" is private to + * the CSS firmware so that it is not listed in the target + * "ia_css_stream" instance. + * + * We need to stop this "Copy Pipe", as well. + */ + if (main_pipe->stream->config.continuous) { + struct ia_css_pipe *copy_pipe = NULL; + + /* get the reference to "Copy Pipe" */ + if (main_pipe_id == IA_CSS_PIPE_ID_PREVIEW) + copy_pipe = main_pipe->pipe_settings.preview.copy_pipe; + else if (main_pipe_id == IA_CSS_PIPE_ID_VIDEO) + copy_pipe = main_pipe->pipe_settings.video.copy_pipe; + + /* return the error code if "Copy Pipe" does NOT exist */ + assert(copy_pipe != NULL); + if (copy_pipe == NULL) { + IA_CSS_LOG("Copy Pipe does NOT exist!"); + err = IA_CSS_ERR_INTERNAL_ERROR; + goto ERR; + } + + /* send the "stop" request to "Copy Pipe" */ + IA_CSS_LOG("Send the stop-request to the pipe: pipe_id=%d", + copy_pipe->pipeline.pipe_id); + err = ia_css_pipeline_request_stop(©_pipe->pipeline); + } + +ERR: + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +/** + * @brief Check if all "ia_css_pipe" instances in the target + * "ia_css_stream" instance have stopped. + * + * Refer to "Local prototypes" for more info. + */ +static bool +sh_css_pipes_have_stopped(struct ia_css_stream *stream) +{ + bool rval = true; + + struct ia_css_pipe *main_pipe; + enum ia_css_pipe_id main_pipe_id; + + int i; + + assert(stream != NULL); + if (stream == NULL) { + IA_CSS_LOG("stream does NOT exist!"); + rval = false; + goto RET; + } + + main_pipe = stream->last_pipe; + assert(main_pipe != NULL); + + if (main_pipe == NULL) { + IA_CSS_LOG("main_pipe does NOT exist!"); + rval = false; + goto RET; + } + + main_pipe_id = main_pipe->mode; + IA_CSS_ENTER_PRIVATE("main_pipe_id=%d", main_pipe_id); + + /** + * Check if every "ia_css_pipe" instance in this target + * "ia_css_stream" instance has stopped. + */ + for (i = 0; i < stream->num_pipes; i++) { + rval = rval && ia_css_pipeline_has_stopped(&stream->pipes[i]->pipeline); + IA_CSS_LOG("Pipe has stopped: pipe_id=%d, stopped=%d", + stream->pipes[i]->pipeline.pipe_id, + rval); + } + + /** + * In the CSS firmware use scenario "Continuous Preview" + * as well as "Continuous Video", the "ia_css_pipe" instance + * "Copy Pipe" is activated. This "Copy Pipe" is private to + * the CSS firmware so that it is not listed in the target + * "ia_css_stream" instance. + * + * We need to check if this "Copy Pipe" has stopped, as well. + */ + if (main_pipe->stream->config.continuous) { + struct ia_css_pipe *copy_pipe = NULL; + + /* get the reference to "Copy Pipe" */ + if (main_pipe_id == IA_CSS_PIPE_ID_PREVIEW) + copy_pipe = main_pipe->pipe_settings.preview.copy_pipe; + else if (main_pipe_id == IA_CSS_PIPE_ID_VIDEO) + copy_pipe = main_pipe->pipe_settings.video.copy_pipe; + + /* return if "Copy Pipe" does NOT exist */ + assert(copy_pipe != NULL); + if (copy_pipe == NULL) { + IA_CSS_LOG("Copy Pipe does NOT exist!"); + + rval = false; + goto RET; + } + + /* check if "Copy Pipe" has stopped or not */ + rval = rval && ia_css_pipeline_has_stopped(©_pipe->pipeline); + IA_CSS_LOG("Pipe has stopped: pipe_id=%d, stopped=%d", + copy_pipe->pipeline.pipe_id, + rval); + } + +RET: + IA_CSS_LEAVE_PRIVATE("rval=%d", rval); + return rval; +} + +bool +sh_css_continuous_is_enabled(uint8_t pipe_num) +{ + struct ia_css_pipe *pipe; + bool continuous; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "sh_css_continuous_is_enabled() enter: pipe_num=%d\n", pipe_num); + + pipe = find_pipe_by_num(pipe_num); + continuous = pipe && pipe->stream->config.continuous; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "sh_css_continuous_is_enabled() leave: enable=%d\n", + continuous); + return continuous; +} + +enum ia_css_err +ia_css_stream_get_max_buffer_depth(struct ia_css_stream *stream, int *buffer_depth) +{ + if (buffer_depth == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_get_max_buffer_depth() enter: void\n"); + (void)stream; + *buffer_depth = NUM_CONTINUOUS_FRAMES; + return IA_CSS_SUCCESS; +} + +enum ia_css_err +ia_css_stream_set_buffer_depth(struct ia_css_stream *stream, int buffer_depth) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_set_buffer_depth() enter: num_frames=%d\n",buffer_depth); + (void)stream; + if (buffer_depth > NUM_CONTINUOUS_FRAMES || buffer_depth < 1) + return IA_CSS_ERR_INVALID_ARGUMENTS; + /* ok, value allowed */ + stream->config.target_num_cont_raw_buf = buffer_depth; + /* TODO: check what to regarding initialization */ + return IA_CSS_SUCCESS; +} + +enum ia_css_err +ia_css_stream_get_buffer_depth(struct ia_css_stream *stream, int *buffer_depth) +{ + if (buffer_depth == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_get_buffer_depth() enter: void\n"); +#endif + (void)stream; + *buffer_depth = stream->config.target_num_cont_raw_buf; + return IA_CSS_SUCCESS; +} + +#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2) +unsigned int +sh_css_get_mipi_sizes_for_check(const unsigned int port, const unsigned int idx) +{ + OP___assert(port < N_CSI_PORTS); + OP___assert(idx < IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "sh_css_get_mipi_sizes_for_check(port %d, idx %d): %d\n", + port, idx, my_css.mipi_sizes_for_check[port][idx]); + return my_css.mipi_sizes_for_check[port][idx]; +} +#endif + +static enum ia_css_err sh_css_pipe_configure_output( + struct ia_css_pipe *pipe, + unsigned int width, + unsigned int height, + unsigned int padded_width, + enum ia_css_frame_format format, + unsigned int idx) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + IA_CSS_ENTER_PRIVATE("pipe = %p, width = %d, height = %d, paddaed width = %d, format = %d, idx = %d", + pipe, width, height, padded_width, format, idx); + if (pipe == NULL) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + err = ia_css_util_check_res(width, height); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + if (pipe->output_info[idx].res.width != width || + pipe->output_info[idx].res.height != height || + pipe->output_info[idx].format != format) + { + ia_css_frame_info_init( + &pipe->output_info[idx], + width, + height, + format, + padded_width); + } + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + return IA_CSS_SUCCESS; +} + +static enum ia_css_err +sh_css_pipe_get_shading_info(struct ia_css_pipe *pipe, +#ifndef ISP2401 + struct ia_css_shading_info *info) +#else + struct ia_css_shading_info *shading_info, + struct ia_css_pipe_config *pipe_config) +#endif +{ + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_binary *binary = NULL; + + assert(pipe != NULL); +#ifndef ISP2401 + assert(info != NULL); +#else + assert(shading_info != NULL); + assert(pipe_config != NULL); +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_pipe_get_shading_info() enter:\n"); + + binary = ia_css_pipe_get_shading_correction_binary(pipe); + + if (binary) { + err = ia_css_binary_get_shading_info(binary, + IA_CSS_SHADING_CORRECTION_TYPE_1, + pipe->required_bds_factor, + (const struct ia_css_stream_config *)&pipe->stream->config, +#ifndef ISP2401 + info); +#else + shading_info, pipe_config); +#endif + /* Other function calls can be added here when other shading correction types will be added + * in the future. + */ + } else { + /* When the pipe does not have a binary which has the shading + * correction, this function does not need to fill the shading + * information. It is not a error case, and then + * this function should return IA_CSS_SUCCESS. + */ +#ifndef ISP2401 + memset(info, 0, sizeof(*info)); +#else + memset(shading_info, 0, sizeof(*shading_info)); +#endif + } + return err; +} + +static enum ia_css_err +sh_css_pipe_get_grid_info(struct ia_css_pipe *pipe, + struct ia_css_grid_info *info) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_binary *binary = NULL; + + assert(pipe != NULL); + assert(info != NULL); + + IA_CSS_ENTER_PRIVATE(""); + + binary = ia_css_pipe_get_s3a_binary(pipe); + + if (binary) { + err = ia_css_binary_3a_grid_info(binary, info, pipe); + if (err != IA_CSS_SUCCESS) + goto ERR; + } else + memset(&info->s3a_grid, 0, sizeof(info->s3a_grid)); + + binary = ia_css_pipe_get_sdis_binary(pipe); + + if (binary) { + ia_css_binary_dvs_grid_info(binary, info, pipe); + ia_css_binary_dvs_stat_grid_info(binary, info, pipe); + } else { + memset(&info->dvs_grid.dvs_grid_info, 0, + sizeof(info->dvs_grid.dvs_grid_info)); + memset(&info->dvs_grid.dvs_stat_grid_info, 0, + sizeof(info->dvs_grid.dvs_stat_grid_info)); + } + + if (binary != NULL) { + /* copy pipe does not have ISP binary*/ + info->isp_in_width = binary->internal_frame_info.res.width; + info->isp_in_height = binary->internal_frame_info.res.height; + } + +#if defined(HAS_VAMEM_VERSION_2) + info->vamem_type = IA_CSS_VAMEM_TYPE_2; +#elif defined(HAS_VAMEM_VERSION_1) + info->vamem_type = IA_CSS_VAMEM_TYPE_1; +#else +#error "Unknown VAMEM version" +#endif + +ERR: + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +#ifdef ISP2401 +/** + * @brief Check if a format is supported by the pipe. + * + */ +static enum ia_css_err +ia_css_pipe_check_format(struct ia_css_pipe *pipe, enum ia_css_frame_format format) +{ + const enum ia_css_frame_format *supported_formats; + int number_of_formats; + int found = 0; + int i; + + IA_CSS_ENTER_PRIVATE(""); + + if (NULL == pipe || NULL == pipe->pipe_settings.video.video_binary.info) { + IA_CSS_ERROR("Pipe or binary info is not set"); + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + supported_formats = pipe->pipe_settings.video.video_binary.info->output_formats; + number_of_formats = sizeof(pipe->pipe_settings.video.video_binary.info->output_formats)/sizeof(enum ia_css_frame_format); + + for (i = 0; i < number_of_formats && !found; i++) { + if (supported_formats[i] == format) { + found = 1; + break; + } + } + if (!found) { + IA_CSS_ERROR("Requested format is not supported by binary"); + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } else { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + return IA_CSS_SUCCESS; + } +} +#endif + +static enum ia_css_err load_video_binaries(struct ia_css_pipe *pipe) +{ + struct ia_css_frame_info video_in_info, tnr_info, + *video_vf_info, video_bds_out_info, *pipe_out_info, *pipe_vf_out_info; + bool online; + enum ia_css_err err = IA_CSS_SUCCESS; + bool continuous = pipe->stream->config.continuous; + unsigned int i; + unsigned num_output_pins; + struct ia_css_frame_info video_bin_out_info; + bool need_scaler = false; + bool vf_res_different_than_output = false; + bool need_vf_pp = false; + int vf_ds_log2; + struct ia_css_video_settings *mycs = &pipe->pipe_settings.video; + + IA_CSS_ENTER_PRIVATE(""); + assert(pipe != NULL); + assert(pipe->mode == IA_CSS_PIPE_ID_VIDEO); + /* we only test the video_binary because offline video doesn't need a + * vf_pp binary and online does not (always use) the copy_binary. + * All are always reset at the same time anyway. + */ + if (mycs->video_binary.info) + return IA_CSS_SUCCESS; + + online = pipe->stream->config.online; + pipe_out_info = &pipe->output_info[0]; + pipe_vf_out_info = &pipe->vf_output_info[0]; + + assert(pipe_out_info != NULL); + + /* + * There is no explicit input format requirement for raw or yuv + * What matters is that there is a binary that supports the stream format. + * This is checked in the binary_find(), so no need to check it here + */ + err = ia_css_util_check_input(&pipe->stream->config, false, false); + if (err != IA_CSS_SUCCESS) + return err; + /* cannot have online video and input_mode memory */ + if (online && pipe->stream->config.mode == IA_CSS_INPUT_MODE_MEMORY) + return IA_CSS_ERR_INVALID_ARGUMENTS; + if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0]) { + err = ia_css_util_check_vf_out_info(pipe_out_info, + pipe_vf_out_info); + if (err != IA_CSS_SUCCESS) + return err; + } else { + err = ia_css_frame_check_info(pipe_out_info); + if (err != IA_CSS_SUCCESS) + return err; + } + + if (pipe->out_yuv_ds_input_info.res.width) + video_bin_out_info = pipe->out_yuv_ds_input_info; + else + video_bin_out_info = *pipe_out_info; + + /* Video */ + if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0]){ + video_vf_info = pipe_vf_out_info; + vf_res_different_than_output = (video_vf_info->res.width != video_bin_out_info.res.width) || + (video_vf_info->res.height != video_bin_out_info.res.height); + } + else { + video_vf_info = NULL; + } + + need_scaler = need_downscaling(video_bin_out_info.res, pipe_out_info->res); + + /* we build up the pipeline starting at the end */ + /* YUV post-processing if needed */ + if (need_scaler) { + struct ia_css_cas_binary_descr cas_scaler_descr + = IA_CSS_DEFAULT_CAS_BINARY_DESCR; + + /* NV12 is the common format that is supported by both */ + /* yuv_scaler and the video_xx_isp2_min binaries. */ + video_bin_out_info.format = IA_CSS_FRAME_FORMAT_NV12; + + err = ia_css_pipe_create_cas_scaler_desc_single_output( + &video_bin_out_info, + pipe_out_info, + NULL, + &cas_scaler_descr); + if (err != IA_CSS_SUCCESS) + return err; + mycs->num_yuv_scaler = cas_scaler_descr.num_stage; + mycs->yuv_scaler_binary = sh_css_calloc(cas_scaler_descr.num_stage, + sizeof(struct ia_css_binary)); + if (mycs->yuv_scaler_binary == NULL) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + return err; + } + mycs->is_output_stage = sh_css_calloc(cas_scaler_descr.num_stage, + sizeof(bool)); + if (mycs->is_output_stage == NULL) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + return err; + } + for (i = 0; i < cas_scaler_descr.num_stage; i++) { + struct ia_css_binary_descr yuv_scaler_descr; + mycs->is_output_stage[i] = cas_scaler_descr.is_output_stage[i]; + ia_css_pipe_get_yuvscaler_binarydesc(pipe, + &yuv_scaler_descr, &cas_scaler_descr.in_info[i], + &cas_scaler_descr.out_info[i], + &cas_scaler_descr.internal_out_info[i], + &cas_scaler_descr.vf_info[i]); + err = ia_css_binary_find(&yuv_scaler_descr, + &mycs->yuv_scaler_binary[i]); + if (err != IA_CSS_SUCCESS) { + sh_css_free(mycs->is_output_stage); + mycs->is_output_stage = NULL; + return err; + } + } + ia_css_pipe_destroy_cas_scaler_desc(&cas_scaler_descr); + } + + + { + struct ia_css_binary_descr video_descr; + enum ia_css_frame_format vf_info_format; + + err = ia_css_pipe_get_video_binarydesc(pipe, + &video_descr, &video_in_info, &video_bds_out_info, &video_bin_out_info, video_vf_info, + pipe->stream->config.left_padding); + if (err != IA_CSS_SUCCESS) + return err; + + /* In the case where video_vf_info is not NULL, this allows + * us to find a potential video library with desired vf format. + * If success, no vf_pp binary is needed. + * If failed, we will look up video binary with YUV_LINE vf format + */ + err = ia_css_binary_find(&video_descr, + &mycs->video_binary); + + if (err != IA_CSS_SUCCESS) { + if (video_vf_info) { + /* This will do another video binary lookup later for YUV_LINE format*/ + need_vf_pp = true; + } else + return err; + } else if (video_vf_info) { + /* The first video binary lookup is successful, but we may + * still need vf_pp binary based on additiona check */ + num_output_pins = mycs->video_binary.info->num_output_pins; + vf_ds_log2 = mycs->video_binary.vf_downscale_log2; + + /* If the binary has dual output pins, we need vf_pp if the resolution + * is different. */ + need_vf_pp |= ((num_output_pins == 2) && vf_res_different_than_output); + + /* If the binary has single output pin, we need vf_pp if additional + * scaling is needed for vf */ + need_vf_pp |= ((num_output_pins == 1) && + ((video_vf_info->res.width << vf_ds_log2 != pipe_out_info->res.width) || + (video_vf_info->res.height << vf_ds_log2 != pipe_out_info->res.height))); + } + + if (need_vf_pp) { + /* save the current vf_info format for restoration later */ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "load_video_binaries() need_vf_pp; find video binary with YUV_LINE again\n"); + + vf_info_format = video_vf_info->format; + + if (!pipe->config.enable_vfpp_bci) + ia_css_frame_info_set_format(video_vf_info, + IA_CSS_FRAME_FORMAT_YUV_LINE); + + ia_css_binary_destroy_isp_parameters(&mycs->video_binary); + + err = ia_css_binary_find(&video_descr, + &mycs->video_binary); + + /* restore original vf_info format */ + ia_css_frame_info_set_format(video_vf_info, + vf_info_format); + if (err != IA_CSS_SUCCESS) + return err; + } + } + + /* If a video binary does not use a ref_frame, we set the frame delay + * to 0. This is the case for the 1-stage low-power video binary. */ + if (!mycs->video_binary.info->sp.enable.ref_frame) + pipe->dvs_frame_delay = 0; + + /* The delay latency determines the number of invalid frames after + * a stream is started. */ + pipe->num_invalid_frames = pipe->dvs_frame_delay; + pipe->info.num_invalid_frames = pipe->num_invalid_frames; + + /* Viewfinder frames also decrement num_invalid_frames. If the pipe + * outputs a viewfinder output, then we need double the number of + * invalid frames */ + if (video_vf_info) + pipe->num_invalid_frames *= 2; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "load_video_binaries() num_invalid_frames=%d dvs_frame_delay=%d\n", + pipe->num_invalid_frames, pipe->dvs_frame_delay); + +/* pqiao TODO: temp hack for PO, should be removed after offline YUVPP is enabled */ +#if !defined(USE_INPUT_SYSTEM_VERSION_2401) + /* Copy */ + if (!online && !continuous) { + /* TODO: what exactly needs doing, prepend the copy binary to + * video base this only on !online? + */ + err = load_copy_binary(pipe, + &mycs->copy_binary, + &mycs->video_binary); + if (err != IA_CSS_SUCCESS) + return err; + } +#else + (void)continuous; +#endif + +#if !defined(HAS_OUTPUT_SYSTEM) + if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0] && need_vf_pp) { + struct ia_css_binary_descr vf_pp_descr; + + if (mycs->video_binary.vf_frame_info.format + == IA_CSS_FRAME_FORMAT_YUV_LINE) { + ia_css_pipe_get_vfpp_binarydesc(pipe, &vf_pp_descr, + &mycs->video_binary.vf_frame_info, + pipe_vf_out_info); + } else { + /* output from main binary is not yuv line. currently this is + * possible only when bci is enabled on vfpp output */ + assert(pipe->config.enable_vfpp_bci == true); + ia_css_pipe_get_yuvscaler_binarydesc(pipe, &vf_pp_descr, + &mycs->video_binary.vf_frame_info, + pipe_vf_out_info, NULL, NULL); + } + + err = ia_css_binary_find(&vf_pp_descr, + &mycs->vf_pp_binary); + if (err != IA_CSS_SUCCESS) + return err; + } +#endif + + err = allocate_delay_frames(pipe); + + if (err != IA_CSS_SUCCESS) + return err; + + if (mycs->video_binary.info->sp.enable.block_output) { +#ifdef ISP2401 + unsigned int tnr_width; + unsigned int tnr_height; +#endif + tnr_info = mycs->video_binary.out_frame_info[0]; +#ifdef ISP2401 + + /* Select resolution for TNR. If + * output_system_in_resolution(GDC_out_resolution) is + * being used, then select that as it will also be in resolution for + * TNR. At present, it only make sense for Skycam */ + if (pipe->config.output_system_in_res.width && pipe->config.output_system_in_res.height) { + tnr_width = pipe->config.output_system_in_res.width; + tnr_height = pipe->config.output_system_in_res.height; + } else { + tnr_width = tnr_info.res.width; + tnr_height = tnr_info.res.height; + } + + /* Make tnr reference buffers output block width(in pix) align */ + tnr_info.res.width = + CEIL_MUL(tnr_width, + (mycs->video_binary.info->sp.block.block_width * ISP_NWAY)); + tnr_info.padded_width = tnr_info.res.width; + +#endif + /* Make tnr reference buffers output block height align */ + tnr_info.res.height = +#ifndef ISP2401 + CEIL_MUL(tnr_info.res.height, +#else + CEIL_MUL(tnr_height, +#endif + mycs->video_binary.info->sp.block.output_block_height); + } else { + tnr_info = mycs->video_binary.internal_frame_info; + } + tnr_info.format = IA_CSS_FRAME_FORMAT_YUV_LINE; + tnr_info.raw_bit_depth = SH_CSS_TNR_BIT_DEPTH; + +#ifndef ISP2401 + for (i = 0; i < NUM_VIDEO_TNR_FRAMES; i++) { +#else + for (i = 0; i < NUM_TNR_FRAMES; i++) { +#endif + if (mycs->tnr_frames[i]) { + ia_css_frame_free(mycs->tnr_frames[i]); + mycs->tnr_frames[i] = NULL; + } + err = ia_css_frame_allocate_from_info( + &mycs->tnr_frames[i], + &tnr_info); +#ifdef HRT_CSIM + ia_css_frame_zero(mycs->tnr_frames[i]); +#endif + if (err != IA_CSS_SUCCESS) + return err; + } + IA_CSS_LEAVE_PRIVATE(""); + return IA_CSS_SUCCESS; +} + +static enum ia_css_err +unload_video_binaries(struct ia_css_pipe *pipe) +{ + unsigned int i; + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + + if ((pipe == NULL) || (pipe->mode != IA_CSS_PIPE_ID_VIDEO)) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + ia_css_binary_unload(&pipe->pipe_settings.video.copy_binary); + ia_css_binary_unload(&pipe->pipe_settings.video.video_binary); + ia_css_binary_unload(&pipe->pipe_settings.video.vf_pp_binary); +#ifndef ISP2401 + ia_css_binary_unload(&pipe->pipe_settings.video.vf_pp_binary); +#endif + + for (i = 0; i < pipe->pipe_settings.video.num_yuv_scaler; i++) + ia_css_binary_unload(&pipe->pipe_settings.video.yuv_scaler_binary[i]); + + sh_css_free(pipe->pipe_settings.video.is_output_stage); + pipe->pipe_settings.video.is_output_stage = NULL; + sh_css_free(pipe->pipe_settings.video.yuv_scaler_binary); + pipe->pipe_settings.video.yuv_scaler_binary = NULL; + + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + return IA_CSS_SUCCESS; +} + +static enum ia_css_err video_start(struct ia_css_pipe *pipe) +{ + struct ia_css_binary *copy_binary; + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_pipe *copy_pipe, *capture_pipe; + enum sh_css_pipe_config_override copy_ovrd; + enum ia_css_input_mode video_pipe_input_mode; + + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + if ((pipe == NULL) || (pipe->mode != IA_CSS_PIPE_ID_VIDEO)) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + video_pipe_input_mode = pipe->stream->config.mode; + + copy_pipe = pipe->pipe_settings.video.copy_pipe; + capture_pipe = pipe->pipe_settings.video.capture_pipe; + + copy_binary = &pipe->pipe_settings.video.copy_binary; + + sh_css_metrics_start_frame(); + + /* multi stream video needs mipi buffers */ + +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) + err = send_mipi_frames(pipe); + if (err != IA_CSS_SUCCESS) + return err; +#endif + + send_raw_frames(pipe); + { + unsigned int thread_id; + + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + copy_ovrd = 1 << thread_id; + + if (pipe->stream->cont_capt) { + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(capture_pipe), &thread_id); + copy_ovrd |= 1 << thread_id; + } + } + + /* Construct and load the copy pipe */ + if (pipe->stream->config.continuous) { + sh_css_sp_init_pipeline(©_pipe->pipeline, + IA_CSS_PIPE_ID_COPY, + (uint8_t)ia_css_pipe_get_pipe_num(copy_pipe), + false, + pipe->stream->config.pixels_per_clock == 2, false, + false, pipe->required_bds_factor, + copy_ovrd, + pipe->stream->config.mode, + &pipe->stream->config.metadata_config, +#ifndef ISP2401 + &pipe->stream->info.metadata_info +#else + &pipe->stream->info.metadata_info, +#endif +#if !defined(HAS_NO_INPUT_SYSTEM) +#ifndef ISP2401 + , pipe->stream->config.source.port.port +#else + pipe->stream->config.source.port.port, +#endif +#endif +#ifndef ISP2401 + ); +#else + ©_pipe->config.internal_frame_origin_bqs_on_sctbl, + copy_pipe->stream->isp_params_configs); +#endif + + /* make the video pipe start with mem mode input, copy handles + the actual mode */ + video_pipe_input_mode = IA_CSS_INPUT_MODE_MEMORY; + } + + /* Construct and load the capture pipe */ + if (pipe->stream->cont_capt) { + sh_css_sp_init_pipeline(&capture_pipe->pipeline, + IA_CSS_PIPE_ID_CAPTURE, + (uint8_t)ia_css_pipe_get_pipe_num(capture_pipe), + capture_pipe->config.default_capture_config.enable_xnr != 0, + capture_pipe->stream->config.pixels_per_clock == 2, + true, /* continuous */ + false, /* offline */ + capture_pipe->required_bds_factor, + 0, + IA_CSS_INPUT_MODE_MEMORY, + &pipe->stream->config.metadata_config, +#ifndef ISP2401 + &pipe->stream->info.metadata_info +#else + &pipe->stream->info.metadata_info, +#endif +#if !defined(HAS_NO_INPUT_SYSTEM) +#ifndef ISP2401 + , (mipi_port_ID_t)0 +#else + (mipi_port_ID_t)0, +#endif +#endif +#ifndef ISP2401 + ); +#else + &capture_pipe->config.internal_frame_origin_bqs_on_sctbl, + capture_pipe->stream->isp_params_configs); +#endif + } + + start_pipe(pipe, copy_ovrd, video_pipe_input_mode); + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static +enum ia_css_err sh_css_pipe_get_viewfinder_frame_info( + struct ia_css_pipe *pipe, + struct ia_css_frame_info *info, + unsigned int idx) +{ + assert(pipe != NULL); + assert(info != NULL); + +/* We could print the pointer as input arg, and the values as output */ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "sh_css_pipe_get_viewfinder_frame_info() enter: void\n"); + + if ( pipe->mode == IA_CSS_PIPE_ID_CAPTURE && + (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_RAW || + pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_BAYER)) + return IA_CSS_ERR_MODE_HAS_NO_VIEWFINDER; + /* offline video does not generate viewfinder output */ + *info = pipe->vf_output_info[idx]; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_pipe_get_viewfinder_frame_info() leave: \ + info.res.width=%d, info.res.height=%d, \ + info.padded_width=%d, info.format=%d, \ + info.raw_bit_depth=%d, info.raw_bayer_order=%d\n", + info->res.width,info->res.height, + info->padded_width,info->format, + info->raw_bit_depth,info->raw_bayer_order); + + return IA_CSS_SUCCESS; +} + +static enum ia_css_err +sh_css_pipe_configure_viewfinder(struct ia_css_pipe *pipe, unsigned int width, + unsigned int height, unsigned int min_width, + enum ia_css_frame_format format, + unsigned int idx) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + IA_CSS_ENTER_PRIVATE("pipe = %p, width = %d, height = %d, min_width = %d, format = %d, idx = %d\n", + pipe, width, height, min_width, format, idx); + + if (pipe == NULL) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + + err = ia_css_util_check_res(width, height); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + if (pipe->vf_output_info[idx].res.width != width || + pipe->vf_output_info[idx].res.height != height || + pipe->vf_output_info[idx].format != format) { + ia_css_frame_info_init(&pipe->vf_output_info[idx], width, height, + format, min_width); + } + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + return IA_CSS_SUCCESS; +} + +static enum ia_css_err load_copy_binaries(struct ia_css_pipe *pipe) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + assert(pipe != NULL); + IA_CSS_ENTER_PRIVATE(""); + + assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || pipe->mode == IA_CSS_PIPE_ID_COPY); + if (pipe->pipe_settings.capture.copy_binary.info) + return IA_CSS_SUCCESS; + + err = ia_css_frame_check_info(&pipe->output_info[0]); + if (err != IA_CSS_SUCCESS) + goto ERR; + + err = verify_copy_out_frame_format(pipe); + if (err != IA_CSS_SUCCESS) + goto ERR; + + err = load_copy_binary(pipe, + &pipe->pipe_settings.capture.copy_binary, + NULL); + +ERR: + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static bool need_capture_pp( + const struct ia_css_pipe *pipe) +{ + const struct ia_css_frame_info *out_info = &pipe->output_info[0]; + IA_CSS_ENTER_LEAVE_PRIVATE(""); + assert(pipe != NULL); + assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE); +#ifdef ISP2401 + + /* ldc and capture_pp are not supported in the same pipeline */ + if (need_capt_ldc(pipe) == true) + return false; +#endif + /* determine whether we need to use the capture_pp binary. + * This is needed for: + * 1. XNR or + * 2. Digital Zoom or + * 3. YUV downscaling + */ + if (pipe->out_yuv_ds_input_info.res.width && + ((pipe->out_yuv_ds_input_info.res.width != out_info->res.width) || + (pipe->out_yuv_ds_input_info.res.height != out_info->res.height))) + return true; + + if (pipe->config.default_capture_config.enable_xnr != 0) + return true; + + if ((pipe->stream->isp_params_configs->dz_config.dx < HRT_GDC_N) || + (pipe->stream->isp_params_configs->dz_config.dy < HRT_GDC_N) || + pipe->config.enable_dz) + return true; + + return false; +} + +static bool need_capt_ldc( + const struct ia_css_pipe *pipe) +{ + IA_CSS_ENTER_LEAVE_PRIVATE(""); + assert(pipe != NULL); + assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE); + return (pipe->extra_config.enable_dvs_6axis) ? true:false; +} + +static enum ia_css_err set_num_primary_stages(unsigned int *num, enum ia_css_pipe_version version) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + if (num == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + switch (version) { + case IA_CSS_PIPE_VERSION_2_6_1: + *num = NUM_PRIMARY_HQ_STAGES; + break; + case IA_CSS_PIPE_VERSION_2_2: + case IA_CSS_PIPE_VERSION_1: + *num = NUM_PRIMARY_STAGES; + break; + default: + err = IA_CSS_ERR_INVALID_ARGUMENTS; + break; + } + + return err; +} + +static enum ia_css_err load_primary_binaries( + struct ia_css_pipe *pipe) +{ + bool online = false; + bool memory = false; + bool continuous = false; + bool need_pp = false; + bool need_isp_copy_binary = false; + bool need_ldc = false; +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + bool sensor = false; +#endif + struct ia_css_frame_info prim_in_info, + prim_out_info, + capt_pp_out_info, vf_info, + *vf_pp_in_info, *pipe_out_info, +#ifndef ISP2401 + *pipe_vf_out_info, *capt_pp_in_info, + capt_ldc_out_info; +#else + *pipe_vf_out_info; +#endif +#if defined(HAS_RES_MGR) + struct ia_css_frame_info bds_out_info; +#endif + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_capture_settings *mycs; + unsigned int i; + bool need_extra_yuv_scaler = false; + + IA_CSS_ENTER_PRIVATE(""); + assert(pipe != NULL); + assert(pipe->stream != NULL); + assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || pipe->mode == IA_CSS_PIPE_ID_COPY); + + online = pipe->stream->config.online; + memory = pipe->stream->config.mode == IA_CSS_INPUT_MODE_MEMORY; + continuous = pipe->stream->config.continuous; +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + sensor = (pipe->stream->config.mode == IA_CSS_INPUT_MODE_SENSOR); +#endif + + mycs = &pipe->pipe_settings.capture; + pipe_out_info = &pipe->output_info[0]; + pipe_vf_out_info = &pipe->vf_output_info[0]; + + if (mycs->primary_binary[0].info) + return IA_CSS_SUCCESS; + + err = set_num_primary_stages(&mycs->num_primary_stage, pipe->config.isp_pipe_version); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0]) { + err = ia_css_util_check_vf_out_info(pipe_out_info, pipe_vf_out_info); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + else{ + err = ia_css_frame_check_info(pipe_out_info); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + need_pp = need_capture_pp(pipe); + + /* we use the vf output info to get the primary/capture_pp binary + configured for vf_veceven. It will select the closest downscaling + factor. */ + vf_info = *pipe_vf_out_info; + +/* + * WARNING: The #if def flag has been added below as a + * temporary solution to solve the problem of enabling the + * view finder in a single binary in a capture flow. The + * vf-pp stage has been removed for Skycam in the solution + * provided. The vf-pp stage should be re-introduced when + * required. This should not be considered as a clean solution. + * Proper investigation should be done to come up with the clean + * solution. + * */ + ia_css_frame_info_set_format(&vf_info, IA_CSS_FRAME_FORMAT_YUV_LINE); + + /* TODO: All this yuv_scaler and capturepp calculation logic + * can be shared later. Capture_pp is also a yuv_scale binary + * with extra XNR funcionality. Therefore, it can be made as the + * first step of the cascade. */ + capt_pp_out_info = pipe->out_yuv_ds_input_info; + capt_pp_out_info.format = IA_CSS_FRAME_FORMAT_YUV420; + capt_pp_out_info.res.width /= MAX_PREFERRED_YUV_DS_PER_STEP; + capt_pp_out_info.res.height /= MAX_PREFERRED_YUV_DS_PER_STEP; + ia_css_frame_info_set_width(&capt_pp_out_info, capt_pp_out_info.res.width, 0); + +/* + * WARNING: The #if def flag has been added below as a + * temporary solution to solve the problem of enabling the + * view finder in a single binary in a capture flow. The + * vf-pp stage has been removed for Skycam in the solution + * provided. The vf-pp stage should be re-introduced when + * required. This should not be considered as a clean solution. + * Proper investigation should be done to come up with the clean + * solution. + * */ + need_extra_yuv_scaler = need_downscaling(capt_pp_out_info.res, + pipe_out_info->res); + + if (need_extra_yuv_scaler) { + struct ia_css_cas_binary_descr cas_scaler_descr + = IA_CSS_DEFAULT_CAS_BINARY_DESCR; + err = ia_css_pipe_create_cas_scaler_desc_single_output( + &capt_pp_out_info, + pipe_out_info, + NULL, + &cas_scaler_descr); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + mycs->num_yuv_scaler = cas_scaler_descr.num_stage; + mycs->yuv_scaler_binary = sh_css_calloc(cas_scaler_descr.num_stage, + sizeof(struct ia_css_binary)); + if (mycs->yuv_scaler_binary == NULL) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + mycs->is_output_stage = sh_css_calloc(cas_scaler_descr.num_stage, + sizeof(bool)); + if (mycs->is_output_stage == NULL) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + for (i = 0; i < cas_scaler_descr.num_stage; i++) { + struct ia_css_binary_descr yuv_scaler_descr; + mycs->is_output_stage[i] = cas_scaler_descr.is_output_stage[i]; + ia_css_pipe_get_yuvscaler_binarydesc(pipe, + &yuv_scaler_descr, &cas_scaler_descr.in_info[i], + &cas_scaler_descr.out_info[i], + &cas_scaler_descr.internal_out_info[i], + &cas_scaler_descr.vf_info[i]); +#if defined(HAS_RES_MGR) + bds_out_info.res = pipe->config.bayer_ds_out_res; + yuv_scaler_descr.bds_out_info = &bds_out_info; +#endif + err = ia_css_binary_find(&yuv_scaler_descr, + &mycs->yuv_scaler_binary[i]); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + ia_css_pipe_destroy_cas_scaler_desc(&cas_scaler_descr); + + } else { + capt_pp_out_info = pipe->output_info[0]; + } + + /* TODO Do we disable ldc for skycam */ + need_ldc = need_capt_ldc(pipe); +#ifdef ISP2401 + /* ldc and capt_pp are not supported in the same pipeline */ + if (need_ldc) { + struct ia_css_binary_descr capt_ldc_descr; + ia_css_pipe_get_ldc_binarydesc(pipe, + &capt_ldc_descr, &prim_out_info, + &capt_pp_out_info); +#endif + +#ifdef ISP2401 + err = ia_css_binary_find(&capt_ldc_descr, + &mycs->capture_ldc_binary); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } else if (need_pp) { +#endif + /* we build up the pipeline starting at the end */ + /* Capture post-processing */ +#ifndef ISP2401 + if (need_pp) { +#endif + struct ia_css_binary_descr capture_pp_descr; +#ifndef ISP2401 + capt_pp_in_info = need_ldc ? &capt_ldc_out_info : &prim_out_info; +#endif + + ia_css_pipe_get_capturepp_binarydesc(pipe, +#ifndef ISP2401 + &capture_pp_descr, capt_pp_in_info, +#else + &capture_pp_descr, &prim_out_info, +#endif + &capt_pp_out_info, &vf_info); +#if defined(HAS_RES_MGR) + bds_out_info.res = pipe->config.bayer_ds_out_res; + capture_pp_descr.bds_out_info = &bds_out_info; +#endif + err = ia_css_binary_find(&capture_pp_descr, + &mycs->capture_pp_binary); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } +#ifndef ISP2401 + + if(need_ldc) { + struct ia_css_binary_descr capt_ldc_descr; + ia_css_pipe_get_ldc_binarydesc(pipe, + &capt_ldc_descr, &prim_out_info, + &capt_ldc_out_info); + + err = ia_css_binary_find(&capt_ldc_descr, + &mycs->capture_ldc_binary); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } +#endif + } else { + prim_out_info = *pipe_out_info; + } + + /* Primary */ + { + struct ia_css_binary_descr prim_descr[MAX_NUM_PRIMARY_STAGES]; + + for (i = 0; i < mycs->num_primary_stage; i++) { + struct ia_css_frame_info *local_vf_info = NULL; + if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0] && (i == mycs->num_primary_stage - 1)) + local_vf_info = &vf_info; + ia_css_pipe_get_primary_binarydesc(pipe, &prim_descr[i], &prim_in_info, &prim_out_info, local_vf_info, i); +#if defined(HAS_RES_MGR) + bds_out_info.res = pipe->config.bayer_ds_out_res; + prim_descr[i].bds_out_info = &bds_out_info; +#endif + err = ia_css_binary_find(&prim_descr[i], &mycs->primary_binary[i]); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + } + + /* Viewfinder post-processing */ + if (need_pp) { + vf_pp_in_info = + &mycs->capture_pp_binary.vf_frame_info; + } else { + vf_pp_in_info = + &mycs->primary_binary[mycs->num_primary_stage - 1].vf_frame_info; + } + +/* + * WARNING: The #if def flag has been added below as a + * temporary solution to solve the problem of enabling the + * view finder in a single binary in a capture flow. The + * vf-pp stage has been removed for Skycam in the solution + * provided. The vf-pp stage should be re-introduced when + * required. Thisshould not be considered as a clean solution. + * Proper * investigation should be done to come up with the clean + * solution. + * */ + if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0]) + { + struct ia_css_binary_descr vf_pp_descr; + + ia_css_pipe_get_vfpp_binarydesc(pipe, + &vf_pp_descr, vf_pp_in_info, pipe_vf_out_info); +#if defined(HAS_RES_MGR) + bds_out_info.res = pipe->config.bayer_ds_out_res; + vf_pp_descr.bds_out_info = &bds_out_info; +#endif + err = ia_css_binary_find(&vf_pp_descr, &mycs->vf_pp_binary); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + err = allocate_delay_frames(pipe); + + if (err != IA_CSS_SUCCESS) + return err; + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + /* When the input system is 2401, only the Direct Sensor Mode + * Offline Capture uses the ISP copy binary. + */ + need_isp_copy_binary = !online && sensor; +#else + need_isp_copy_binary = !online && !continuous && !memory; +#endif + + /* ISP Copy */ + if (need_isp_copy_binary) { + err = load_copy_binary(pipe, + &mycs->copy_binary, + &mycs->primary_binary[0]); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + + return IA_CSS_SUCCESS; +} + +static enum ia_css_err +allocate_delay_frames(struct ia_css_pipe *pipe) +{ + unsigned int num_delay_frames = 0, i = 0; + unsigned int dvs_frame_delay = 0; + struct ia_css_frame_info ref_info; + enum ia_css_err err = IA_CSS_SUCCESS; + enum ia_css_pipe_id mode = IA_CSS_PIPE_ID_VIDEO; + struct ia_css_frame **delay_frames = NULL; + + IA_CSS_ENTER_PRIVATE(""); + + if (pipe == NULL) { + IA_CSS_ERROR("Invalid args - pipe %x", pipe); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + mode = pipe->mode; + dvs_frame_delay = pipe->dvs_frame_delay; + + if (dvs_frame_delay > 0) + num_delay_frames = dvs_frame_delay + 1; + + switch (mode) { + case IA_CSS_PIPE_ID_CAPTURE: + { + struct ia_css_capture_settings *mycs_capture = &pipe->pipe_settings.capture; + (void)mycs_capture; + return err; + } + break; + case IA_CSS_PIPE_ID_VIDEO: + { + struct ia_css_video_settings *mycs_video = &pipe->pipe_settings.video; + ref_info = mycs_video->video_binary.internal_frame_info; + /*The ref frame expects + * 1. Y plane + * 2. UV plane with line interleaving, like below + * UUUUUU(width/2 times) VVVVVVVV..(width/2 times) + * + * This format is not YUV420(which has Y, U and V planes). + * Its closer to NV12, except that the UV plane has UV + * interleaving, like UVUVUVUVUVUVUVUVU... + * + * TODO: make this ref_frame format as a separate frame format + */ + ref_info.format = IA_CSS_FRAME_FORMAT_NV12; + delay_frames = mycs_video->delay_frames; + } + break; + case IA_CSS_PIPE_ID_PREVIEW: + { + struct ia_css_preview_settings *mycs_preview = &pipe->pipe_settings.preview; + ref_info = mycs_preview->preview_binary.internal_frame_info; + /*The ref frame expects + * 1. Y plane + * 2. UV plane with line interleaving, like below + * UUUUUU(width/2 times) VVVVVVVV..(width/2 times) + * + * This format is not YUV420(which has Y, U and V planes). + * Its closer to NV12, except that the UV plane has UV + * interleaving, like UVUVUVUVUVUVUVUVU... + * + * TODO: make this ref_frame format as a separate frame format + */ + ref_info.format = IA_CSS_FRAME_FORMAT_NV12; + delay_frames = mycs_preview->delay_frames; + } + break; + default: + return IA_CSS_ERR_INVALID_ARGUMENTS; + + } + + ref_info.raw_bit_depth = SH_CSS_REF_BIT_DEPTH; + + assert(num_delay_frames <= MAX_NUM_VIDEO_DELAY_FRAMES); + for (i = 0; i < num_delay_frames; i++) { + err = ia_css_frame_allocate_from_info(&delay_frames[i], &ref_info); + if (err != IA_CSS_SUCCESS) + return err; +#if defined(HRT_CSIM) || defined(__SVOS__) + ia_css_frame_zero(delay_frames[i]); +#endif + } + IA_CSS_LEAVE_PRIVATE(""); + return IA_CSS_SUCCESS; +} + +static enum ia_css_err load_advanced_binaries( + struct ia_css_pipe *pipe) +{ + struct ia_css_frame_info pre_in_info, gdc_in_info, + post_in_info, post_out_info, + vf_info, *vf_pp_in_info, *pipe_out_info, + *pipe_vf_out_info; + bool need_pp; + bool need_isp_copy = true; + enum ia_css_err err = IA_CSS_SUCCESS; + + IA_CSS_ENTER_PRIVATE(""); + + assert(pipe != NULL); + assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || pipe->mode == IA_CSS_PIPE_ID_COPY); + if (pipe->pipe_settings.capture.pre_isp_binary.info) + return IA_CSS_SUCCESS; + pipe_out_info = &pipe->output_info[0]; + pipe_vf_out_info = &pipe->vf_output_info[0]; + + vf_info = *pipe_vf_out_info; + err = ia_css_util_check_vf_out_info(pipe_out_info, &vf_info); + if (err != IA_CSS_SUCCESS) + return err; + need_pp = need_capture_pp(pipe); + + ia_css_frame_info_set_format(&vf_info, + IA_CSS_FRAME_FORMAT_YUV_LINE); + + /* we build up the pipeline starting at the end */ + /* Capture post-processing */ + if (need_pp) { + struct ia_css_binary_descr capture_pp_descr; + + ia_css_pipe_get_capturepp_binarydesc(pipe, + &capture_pp_descr, &post_out_info, pipe_out_info, &vf_info); + err = ia_css_binary_find(&capture_pp_descr, + &pipe->pipe_settings.capture.capture_pp_binary); + if (err != IA_CSS_SUCCESS) + return err; + } else { + post_out_info = *pipe_out_info; + } + + /* Post-gdc */ + { + struct ia_css_binary_descr post_gdc_descr; + + ia_css_pipe_get_post_gdc_binarydesc(pipe, + &post_gdc_descr, &post_in_info, &post_out_info, &vf_info); + err = ia_css_binary_find(&post_gdc_descr, + &pipe->pipe_settings.capture.post_isp_binary); + if (err != IA_CSS_SUCCESS) + return err; + } + + /* Gdc */ + { + struct ia_css_binary_descr gdc_descr; + + ia_css_pipe_get_gdc_binarydesc(pipe, &gdc_descr, &gdc_in_info, + &pipe->pipe_settings.capture.post_isp_binary.in_frame_info); + err = ia_css_binary_find(&gdc_descr, + &pipe->pipe_settings.capture.anr_gdc_binary); + if (err != IA_CSS_SUCCESS) + return err; + } + pipe->pipe_settings.capture.anr_gdc_binary.left_padding = + pipe->pipe_settings.capture.post_isp_binary.left_padding; + + /* Pre-gdc */ + { + struct ia_css_binary_descr pre_gdc_descr; + + ia_css_pipe_get_pre_gdc_binarydesc(pipe, &pre_gdc_descr, &pre_in_info, + &pipe->pipe_settings.capture.anr_gdc_binary.in_frame_info); + err = ia_css_binary_find(&pre_gdc_descr, + &pipe->pipe_settings.capture.pre_isp_binary); + if (err != IA_CSS_SUCCESS) + return err; + } + pipe->pipe_settings.capture.pre_isp_binary.left_padding = + pipe->pipe_settings.capture.anr_gdc_binary.left_padding; + + /* Viewfinder post-processing */ + if (need_pp) { + vf_pp_in_info = + &pipe->pipe_settings.capture.capture_pp_binary.vf_frame_info; + } else { + vf_pp_in_info = + &pipe->pipe_settings.capture.post_isp_binary.vf_frame_info; + } + + { + struct ia_css_binary_descr vf_pp_descr; + + ia_css_pipe_get_vfpp_binarydesc(pipe, + &vf_pp_descr, vf_pp_in_info, pipe_vf_out_info); + err = ia_css_binary_find(&vf_pp_descr, + &pipe->pipe_settings.capture.vf_pp_binary); + if (err != IA_CSS_SUCCESS) + return err; + } + + /* Copy */ +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + /* For CSI2+, only the direct sensor mode/online requires ISP copy */ + need_isp_copy = pipe->stream->config.mode == IA_CSS_INPUT_MODE_SENSOR; +#endif + if (need_isp_copy) + load_copy_binary(pipe, + &pipe->pipe_settings.capture.copy_binary, + &pipe->pipe_settings.capture.pre_isp_binary); + + return err; +} + +static enum ia_css_err load_bayer_isp_binaries( + struct ia_css_pipe *pipe) +{ + struct ia_css_frame_info pre_isp_in_info, *pipe_out_info; + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_binary_descr pre_de_descr; + + IA_CSS_ENTER_PRIVATE(""); + assert(pipe != NULL); + assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || pipe->mode == IA_CSS_PIPE_ID_COPY); + pipe_out_info = &pipe->output_info[0]; + + if (pipe->pipe_settings.capture.pre_isp_binary.info) + return IA_CSS_SUCCESS; + + err = ia_css_frame_check_info(pipe_out_info); + if (err != IA_CSS_SUCCESS) + return err; + + ia_css_pipe_get_pre_de_binarydesc(pipe, &pre_de_descr, + &pre_isp_in_info, + pipe_out_info); + + err = ia_css_binary_find(&pre_de_descr, + &pipe->pipe_settings.capture.pre_isp_binary); + + return err; +} + +static enum ia_css_err load_low_light_binaries( + struct ia_css_pipe *pipe) +{ + struct ia_css_frame_info pre_in_info, anr_in_info, + post_in_info, post_out_info, + vf_info, *pipe_vf_out_info, *pipe_out_info, + *vf_pp_in_info; + bool need_pp; + bool need_isp_copy = true; + enum ia_css_err err = IA_CSS_SUCCESS; + + IA_CSS_ENTER_PRIVATE(""); + assert(pipe != NULL); + assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || pipe->mode == IA_CSS_PIPE_ID_COPY); + + if (pipe->pipe_settings.capture.pre_isp_binary.info) + return IA_CSS_SUCCESS; + pipe_vf_out_info = &pipe->vf_output_info[0]; + pipe_out_info = &pipe->output_info[0]; + + vf_info = *pipe_vf_out_info; + err = ia_css_util_check_vf_out_info(pipe_out_info, + &vf_info); + if (err != IA_CSS_SUCCESS) + return err; + need_pp = need_capture_pp(pipe); + + ia_css_frame_info_set_format(&vf_info, + IA_CSS_FRAME_FORMAT_YUV_LINE); + + /* we build up the pipeline starting at the end */ + /* Capture post-processing */ + if (need_pp) { + struct ia_css_binary_descr capture_pp_descr; + + ia_css_pipe_get_capturepp_binarydesc(pipe, + &capture_pp_descr, &post_out_info, pipe_out_info, &vf_info); + err = ia_css_binary_find(&capture_pp_descr, + &pipe->pipe_settings.capture.capture_pp_binary); + if (err != IA_CSS_SUCCESS) + return err; + } else { + post_out_info = *pipe_out_info; + } + + /* Post-anr */ + { + struct ia_css_binary_descr post_anr_descr; + + ia_css_pipe_get_post_anr_binarydesc(pipe, + &post_anr_descr, &post_in_info, &post_out_info, &vf_info); + err = ia_css_binary_find(&post_anr_descr, + &pipe->pipe_settings.capture.post_isp_binary); + if (err != IA_CSS_SUCCESS) + return err; + } + + /* Anr */ + { + struct ia_css_binary_descr anr_descr; + + ia_css_pipe_get_anr_binarydesc(pipe, &anr_descr, &anr_in_info, + &pipe->pipe_settings.capture.post_isp_binary.in_frame_info); + err = ia_css_binary_find(&anr_descr, + &pipe->pipe_settings.capture.anr_gdc_binary); + if (err != IA_CSS_SUCCESS) + return err; + } + pipe->pipe_settings.capture.anr_gdc_binary.left_padding = + pipe->pipe_settings.capture.post_isp_binary.left_padding; + + /* Pre-anr */ + { + struct ia_css_binary_descr pre_anr_descr; + + ia_css_pipe_get_pre_anr_binarydesc(pipe, &pre_anr_descr, &pre_in_info, + &pipe->pipe_settings.capture.anr_gdc_binary.in_frame_info); + err = ia_css_binary_find(&pre_anr_descr, + &pipe->pipe_settings.capture.pre_isp_binary); + if (err != IA_CSS_SUCCESS) + return err; + } + pipe->pipe_settings.capture.pre_isp_binary.left_padding = + pipe->pipe_settings.capture.anr_gdc_binary.left_padding; + + /* Viewfinder post-processing */ + if (need_pp) { + vf_pp_in_info = + &pipe->pipe_settings.capture.capture_pp_binary.vf_frame_info; + } else { + vf_pp_in_info = + &pipe->pipe_settings.capture.post_isp_binary.vf_frame_info; + } + + { + struct ia_css_binary_descr vf_pp_descr; + + ia_css_pipe_get_vfpp_binarydesc(pipe, + &vf_pp_descr, vf_pp_in_info, pipe_vf_out_info); + err = ia_css_binary_find(&vf_pp_descr, + &pipe->pipe_settings.capture.vf_pp_binary); + if (err != IA_CSS_SUCCESS) + return err; + } + + /* Copy */ +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + /* For CSI2+, only the direct sensor mode/online requires ISP copy */ + need_isp_copy = pipe->stream->config.mode == IA_CSS_INPUT_MODE_SENSOR; +#endif + if (need_isp_copy) + err = load_copy_binary(pipe, + &pipe->pipe_settings.capture.copy_binary, + &pipe->pipe_settings.capture.pre_isp_binary); + + return err; +} + +static bool copy_on_sp(struct ia_css_pipe *pipe) +{ + bool rval; + + assert(pipe != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "copy_on_sp() enter:\n"); + + rval = true; + + rval &= (pipe->mode == IA_CSS_PIPE_ID_CAPTURE); + + rval &= (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_RAW); + + rval &= ((pipe->stream->config.input_config.format == IA_CSS_STREAM_FORMAT_BINARY_8) || + (pipe->config.mode == IA_CSS_PIPE_MODE_COPY)); + + return rval; +} + +static enum ia_css_err load_capture_binaries( + struct ia_css_pipe *pipe) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + bool must_be_raw; + + IA_CSS_ENTER_PRIVATE(""); + assert(pipe != NULL); + assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || pipe->mode == IA_CSS_PIPE_ID_COPY); + + if (pipe->pipe_settings.capture.primary_binary[0].info) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + return IA_CSS_SUCCESS; + } + + /* in primary, advanced,low light or bayer, + the input format must be raw */ + must_be_raw = + pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_ADVANCED || + pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_BAYER || + pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_LOW_LIGHT; + err = ia_css_util_check_input(&pipe->stream->config, must_be_raw, false); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + if (copy_on_sp(pipe) && + pipe->stream->config.input_config.format == IA_CSS_STREAM_FORMAT_BINARY_8) { + ia_css_frame_info_init( + &pipe->output_info[0], + JPEG_BYTES, + 1, + IA_CSS_FRAME_FORMAT_BINARY_8, + 0); + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + return IA_CSS_SUCCESS; + } + + switch (pipe->config.default_capture_config.mode) { + case IA_CSS_CAPTURE_MODE_RAW: + err = load_copy_binaries(pipe); +#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2401) + if (err == IA_CSS_SUCCESS) + pipe->pipe_settings.capture.copy_binary.online = pipe->stream->config.online; +#endif + break; + case IA_CSS_CAPTURE_MODE_BAYER: + err = load_bayer_isp_binaries(pipe); + break; + case IA_CSS_CAPTURE_MODE_PRIMARY: + err = load_primary_binaries(pipe); + break; + case IA_CSS_CAPTURE_MODE_ADVANCED: + err = load_advanced_binaries(pipe); + break; + case IA_CSS_CAPTURE_MODE_LOW_LIGHT: + err = load_low_light_binaries(pipe); + break; + } + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static enum ia_css_err +unload_capture_binaries(struct ia_css_pipe *pipe) +{ + unsigned int i; + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + + if ((pipe == NULL) || ((pipe->mode != IA_CSS_PIPE_ID_CAPTURE) && (pipe->mode != IA_CSS_PIPE_ID_COPY))) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + ia_css_binary_unload(&pipe->pipe_settings.capture.copy_binary); + for (i = 0; i < MAX_NUM_PRIMARY_STAGES; i++) + ia_css_binary_unload(&pipe->pipe_settings.capture.primary_binary[i]); + ia_css_binary_unload(&pipe->pipe_settings.capture.pre_isp_binary); + ia_css_binary_unload(&pipe->pipe_settings.capture.anr_gdc_binary); + ia_css_binary_unload(&pipe->pipe_settings.capture.post_isp_binary); + ia_css_binary_unload(&pipe->pipe_settings.capture.capture_pp_binary); + ia_css_binary_unload(&pipe->pipe_settings.capture.capture_ldc_binary); + ia_css_binary_unload(&pipe->pipe_settings.capture.vf_pp_binary); + + for (i = 0; i < pipe->pipe_settings.capture.num_yuv_scaler; i++) + ia_css_binary_unload(&pipe->pipe_settings.capture.yuv_scaler_binary[i]); + + sh_css_free(pipe->pipe_settings.capture.is_output_stage); + pipe->pipe_settings.capture.is_output_stage = NULL; + sh_css_free(pipe->pipe_settings.capture.yuv_scaler_binary); + pipe->pipe_settings.capture.yuv_scaler_binary = NULL; + + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + return IA_CSS_SUCCESS; +} + +static bool +need_downscaling(const struct ia_css_resolution in_res, + const struct ia_css_resolution out_res) +{ + + if (in_res.width > out_res.width || in_res.height > out_res.height) + return true; + + return false; +} + +static bool +need_yuv_scaler_stage(const struct ia_css_pipe *pipe) +{ + unsigned int i; + struct ia_css_resolution in_res, out_res; + + bool need_format_conversion = false; + + IA_CSS_ENTER_PRIVATE(""); + assert(pipe != NULL); + assert(pipe->mode == IA_CSS_PIPE_ID_YUVPP); + + /* TODO: make generic function */ + need_format_conversion = + ((pipe->stream->config.input_config.format == IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY) && + (pipe->output_info[0].format != IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8)); + + in_res = pipe->config.input_effective_res; + + if (pipe->config.enable_dz) + return true; + + if ((pipe->output_info[0].res.width != 0) && need_format_conversion) + return true; + + for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + out_res = pipe->output_info[i].res; + + /* A non-zero width means it is a valid output port */ + if ((out_res.width != 0) && need_downscaling(in_res, out_res)) + return true; + } + + return false; +} + +/* TODO: it is temporarily created from ia_css_pipe_create_cas_scaler_desc */ +/* which has some hard-coded knowledge which prevents reuse of the function. */ +/* Later, merge this with ia_css_pipe_create_cas_scaler_desc */ +static enum ia_css_err ia_css_pipe_create_cas_scaler_desc_single_output( + struct ia_css_frame_info *cas_scaler_in_info, + struct ia_css_frame_info *cas_scaler_out_info, + struct ia_css_frame_info *cas_scaler_vf_info, + struct ia_css_cas_binary_descr *descr) +{ + unsigned int i; + unsigned int hor_ds_factor = 0, ver_ds_factor = 0; + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_frame_info tmp_in_info = IA_CSS_BINARY_DEFAULT_FRAME_INFO; + + unsigned max_scale_factor_per_stage = MAX_PREFERRED_YUV_DS_PER_STEP; + + assert(cas_scaler_in_info != NULL); + assert(cas_scaler_out_info != NULL); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_pipe_create_cas_scaler_desc() enter:\n"); + + /* We assume that this function is used only for single output port case. */ + descr->num_output_stage = 1; + + hor_ds_factor = CEIL_DIV(cas_scaler_in_info->res.width , cas_scaler_out_info->res.width); + ver_ds_factor = CEIL_DIV(cas_scaler_in_info->res.height, cas_scaler_out_info->res.height); + /* use the same horizontal and vertical downscaling factor for simplicity */ + assert(hor_ds_factor == ver_ds_factor); + + i = 1; + while (i < hor_ds_factor) { + descr->num_stage++; + i *= max_scale_factor_per_stage; + } + + descr->in_info = sh_css_malloc(descr->num_stage * sizeof(struct ia_css_frame_info)); + if (descr->in_info == NULL) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + goto ERR; + } + descr->internal_out_info = sh_css_malloc(descr->num_stage * sizeof(struct ia_css_frame_info)); + if (descr->internal_out_info == NULL) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + goto ERR; + } + descr->out_info = sh_css_malloc(descr->num_stage * sizeof(struct ia_css_frame_info)); + if (descr->out_info == NULL) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + goto ERR; + } + descr->vf_info = sh_css_malloc(descr->num_stage * sizeof(struct ia_css_frame_info)); + if (descr->vf_info == NULL) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + goto ERR; + } + descr->is_output_stage = sh_css_malloc(descr->num_stage * sizeof(bool)); + if (descr->is_output_stage == NULL) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + goto ERR; + } + + tmp_in_info = *cas_scaler_in_info; + for (i = 0; i < descr->num_stage; i++) { + + descr->in_info[i] = tmp_in_info; + if ((tmp_in_info.res.width / max_scale_factor_per_stage) <= cas_scaler_out_info->res.width) { + descr->is_output_stage[i] = true; + if ((descr->num_output_stage > 1) && (i != (descr->num_stage - 1))) { + descr->internal_out_info[i].res.width = cas_scaler_out_info->res.width; + descr->internal_out_info[i].res.height = cas_scaler_out_info->res.height; + descr->internal_out_info[i].padded_width = cas_scaler_out_info->padded_width; + descr->internal_out_info[i].format = IA_CSS_FRAME_FORMAT_YUV420; + } else { + assert(i == (descr->num_stage - 1)); + descr->internal_out_info[i].res.width = 0; + descr->internal_out_info[i].res.height = 0; + } + descr->out_info[i].res.width = cas_scaler_out_info->res.width; + descr->out_info[i].res.height = cas_scaler_out_info->res.height; + descr->out_info[i].padded_width = cas_scaler_out_info->padded_width; + descr->out_info[i].format = cas_scaler_out_info->format; + if (cas_scaler_vf_info != NULL) { + descr->vf_info[i].res.width = cas_scaler_vf_info->res.width; + descr->vf_info[i].res.height = cas_scaler_vf_info->res.height; + descr->vf_info[i].padded_width = cas_scaler_vf_info->padded_width; + ia_css_frame_info_set_format(&descr->vf_info[i], IA_CSS_FRAME_FORMAT_YUV_LINE); + } else { + descr->vf_info[i].res.width = 0; + descr->vf_info[i].res.height = 0; + descr->vf_info[i].padded_width = 0; + } + } else { + descr->is_output_stage[i] = false; + descr->internal_out_info[i].res.width = tmp_in_info.res.width / max_scale_factor_per_stage; + descr->internal_out_info[i].res.height = tmp_in_info.res.height / max_scale_factor_per_stage; + descr->internal_out_info[i].format = IA_CSS_FRAME_FORMAT_YUV420; + ia_css_frame_info_init(&descr->internal_out_info[i], + tmp_in_info.res.width / max_scale_factor_per_stage, + tmp_in_info.res.height / max_scale_factor_per_stage, + IA_CSS_FRAME_FORMAT_YUV420, 0); + descr->out_info[i].res.width = 0; + descr->out_info[i].res.height = 0; + descr->vf_info[i].res.width = 0; + descr->vf_info[i].res.height = 0; + } + tmp_in_info = descr->internal_out_info[i]; + } +ERR: + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_pipe_create_cas_scaler_desc() leave, err=%d\n", + err); + return err; +} + +static enum ia_css_err ia_css_pipe_create_cas_scaler_desc(struct ia_css_pipe *pipe, + struct ia_css_cas_binary_descr *descr) +{ + struct ia_css_frame_info in_info = IA_CSS_BINARY_DEFAULT_FRAME_INFO; + struct ia_css_frame_info *out_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + struct ia_css_frame_info *vf_out_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + struct ia_css_frame_info tmp_in_info = IA_CSS_BINARY_DEFAULT_FRAME_INFO; + unsigned int i, j; + unsigned int hor_scale_factor[IA_CSS_PIPE_MAX_OUTPUT_STAGE], + ver_scale_factor[IA_CSS_PIPE_MAX_OUTPUT_STAGE], + scale_factor = 0; + unsigned int num_stages = 0; + enum ia_css_err err = IA_CSS_SUCCESS; + + unsigned max_scale_factor_per_stage = MAX_PREFERRED_YUV_DS_PER_STEP; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_pipe_create_cas_scaler_desc() enter:\n"); + + for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + out_info[i] = NULL; + vf_out_info[i] = NULL; + hor_scale_factor[i] = 0; + ver_scale_factor[i] = 0; + } + + in_info.res = pipe->config.input_effective_res; + in_info.padded_width = in_info.res.width; + descr->num_output_stage = 0; + /* Find out how much scaling we need for each output */ + for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + if (pipe->output_info[i].res.width != 0) { + out_info[i] = &pipe->output_info[i]; + if (pipe->vf_output_info[i].res.width != 0) + vf_out_info[i] = &pipe->vf_output_info[i]; + descr->num_output_stage += 1; + } + + if (out_info[i] != NULL) { + hor_scale_factor[i] = CEIL_DIV(in_info.res.width, out_info[i]->res.width); + ver_scale_factor[i] = CEIL_DIV(in_info.res.height, out_info[i]->res.height); + /* use the same horizontal and vertical scaling factor for simplicity */ + assert(hor_scale_factor[i] == ver_scale_factor[i]); + scale_factor = 1; + do { + num_stages++; + scale_factor *= max_scale_factor_per_stage; + } while (scale_factor < hor_scale_factor[i]); + + in_info.res = out_info[i]->res; + } + } + + if (need_yuv_scaler_stage(pipe) && (num_stages == 0)) + num_stages = 1; + + descr->num_stage = num_stages; + + descr->in_info = sh_css_malloc(descr->num_stage * sizeof(struct ia_css_frame_info)); + if (descr->in_info == NULL) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + goto ERR; + } + descr->internal_out_info = sh_css_malloc(descr->num_stage * sizeof(struct ia_css_frame_info)); + if (descr->internal_out_info == NULL) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + goto ERR; + } + descr->out_info = sh_css_malloc(descr->num_stage * sizeof(struct ia_css_frame_info)); + if (descr->out_info == NULL) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + goto ERR; + } + descr->vf_info = sh_css_malloc(descr->num_stage * sizeof(struct ia_css_frame_info)); + if (descr->vf_info == NULL) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + goto ERR; + } + descr->is_output_stage = sh_css_malloc(descr->num_stage * sizeof(bool)); + if (descr->is_output_stage == NULL) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + goto ERR; + } + + for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + if (out_info[i]) { + if (i > 0) { + assert((out_info[i-1]->res.width >= out_info[i]->res.width) && + (out_info[i-1]->res.height >= out_info[i]->res.height)); + } + } + } + + tmp_in_info.res = pipe->config.input_effective_res; + tmp_in_info.format = IA_CSS_FRAME_FORMAT_YUV420; + for (i = 0, j = 0; i < descr->num_stage; i++) { + assert(j < 2); + assert(out_info[j] != NULL); + + descr->in_info[i] = tmp_in_info; + if ((tmp_in_info.res.width / max_scale_factor_per_stage) <= out_info[j]->res.width) { + descr->is_output_stage[i] = true; + if ((descr->num_output_stage > 1) && (i != (descr->num_stage - 1))) { + descr->internal_out_info[i].res.width = out_info[j]->res.width; + descr->internal_out_info[i].res.height = out_info[j]->res.height; + descr->internal_out_info[i].padded_width = out_info[j]->padded_width; + descr->internal_out_info[i].format = IA_CSS_FRAME_FORMAT_YUV420; + } else { + assert(i == (descr->num_stage - 1)); + descr->internal_out_info[i].res.width = 0; + descr->internal_out_info[i].res.height = 0; + } + descr->out_info[i].res.width = out_info[j]->res.width; + descr->out_info[i].res.height = out_info[j]->res.height; + descr->out_info[i].padded_width = out_info[j]->padded_width; + descr->out_info[i].format = out_info[j]->format; + if (vf_out_info[j] != NULL) { + descr->vf_info[i].res.width = vf_out_info[j]->res.width; + descr->vf_info[i].res.height = vf_out_info[j]->res.height; + descr->vf_info[i].padded_width = vf_out_info[j]->padded_width; + ia_css_frame_info_set_format(&descr->vf_info[i], IA_CSS_FRAME_FORMAT_YUV_LINE); + } else { + descr->vf_info[i].res.width = 0; + descr->vf_info[i].res.height = 0; + descr->vf_info[i].padded_width = 0; + } + j++; + } else { + descr->is_output_stage[i] = false; + descr->internal_out_info[i].res.width = tmp_in_info.res.width / max_scale_factor_per_stage; + descr->internal_out_info[i].res.height = tmp_in_info.res.height / max_scale_factor_per_stage; + descr->internal_out_info[i].format = IA_CSS_FRAME_FORMAT_YUV420; + ia_css_frame_info_init(&descr->internal_out_info[i], + tmp_in_info.res.width / max_scale_factor_per_stage, + tmp_in_info.res.height / max_scale_factor_per_stage, + IA_CSS_FRAME_FORMAT_YUV420, 0); + descr->out_info[i].res.width = 0; + descr->out_info[i].res.height = 0; + descr->vf_info[i].res.width = 0; + descr->vf_info[i].res.height = 0; + } + tmp_in_info = descr->internal_out_info[i]; + } +ERR: + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_pipe_create_cas_scaler_desc() leave, err=%d\n", + err); + return err; +} + +static void ia_css_pipe_destroy_cas_scaler_desc(struct ia_css_cas_binary_descr *descr) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_pipe_destroy_cas_scaler_desc() enter:\n"); + sh_css_free(descr->in_info); + descr->in_info = NULL; + sh_css_free(descr->internal_out_info); + descr->internal_out_info = NULL; + sh_css_free(descr->out_info); + descr->out_info = NULL; + sh_css_free(descr->vf_info); + descr->vf_info = NULL; + sh_css_free(descr->is_output_stage); + descr->is_output_stage = NULL; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "ia_css_pipe_destroy_cas_scaler_desc() leave\n"); +} + +static enum ia_css_err +load_yuvpp_binaries(struct ia_css_pipe *pipe) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + bool need_scaler = false; + struct ia_css_frame_info *vf_pp_in_info[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + struct ia_css_yuvpp_settings *mycs; + struct ia_css_binary *next_binary; + struct ia_css_cas_binary_descr cas_scaler_descr = IA_CSS_DEFAULT_CAS_BINARY_DESCR; + unsigned int i, j; + bool need_isp_copy_binary = false; + + IA_CSS_ENTER_PRIVATE(""); + assert(pipe != NULL); + assert(pipe->stream != NULL); + assert(pipe->mode == IA_CSS_PIPE_ID_YUVPP); + + if (pipe->pipe_settings.yuvpp.copy_binary.info) + goto ERR; + + /* Set both must_be_raw and must_be_yuv to false then yuvpp can take rgb inputs */ + err = ia_css_util_check_input(&pipe->stream->config, false, false); + if (err != IA_CSS_SUCCESS) + goto ERR; + + mycs = &pipe->pipe_settings.yuvpp; + + for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + if (pipe->vf_output_info[i].res.width != 0) { + err = ia_css_util_check_vf_out_info(&pipe->output_info[i], + &pipe->vf_output_info[i]); + if (err != IA_CSS_SUCCESS) + goto ERR; + } + vf_pp_in_info[i] = NULL; + } + + need_scaler = need_yuv_scaler_stage(pipe); + + /* we build up the pipeline starting at the end */ + /* Capture post-processing */ + if (need_scaler) { + struct ia_css_binary_descr yuv_scaler_descr; + + err = ia_css_pipe_create_cas_scaler_desc(pipe, + &cas_scaler_descr); + if (err != IA_CSS_SUCCESS) + goto ERR; + mycs->num_output = cas_scaler_descr.num_output_stage; + mycs->num_yuv_scaler = cas_scaler_descr.num_stage; + mycs->yuv_scaler_binary = sh_css_calloc(cas_scaler_descr.num_stage, + sizeof(struct ia_css_binary)); + if (mycs->yuv_scaler_binary == NULL) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + goto ERR; + } + mycs->is_output_stage = sh_css_calloc(cas_scaler_descr.num_stage, + sizeof(bool)); + if (mycs->is_output_stage == NULL) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + goto ERR; + } + for (i = 0; i < cas_scaler_descr.num_stage; i++) { + mycs->is_output_stage[i] = cas_scaler_descr.is_output_stage[i]; + ia_css_pipe_get_yuvscaler_binarydesc(pipe, + &yuv_scaler_descr, &cas_scaler_descr.in_info[i], + &cas_scaler_descr.out_info[i], + &cas_scaler_descr.internal_out_info[i], + &cas_scaler_descr.vf_info[i]); + err = ia_css_binary_find(&yuv_scaler_descr, + &mycs->yuv_scaler_binary[i]); + if (err != IA_CSS_SUCCESS) + goto ERR; + } + ia_css_pipe_destroy_cas_scaler_desc(&cas_scaler_descr); + } else { + mycs->num_output = 1; + } + + if (need_scaler) { + next_binary = &mycs->yuv_scaler_binary[0]; + } else { + next_binary = NULL; + } + +#if defined(USE_INPUT_SYSTEM_VERSION_2401) + /* + * NOTES + * - Why does the "yuvpp" pipe needs "isp_copy_binary" (i.e. ISP Copy) when + * its input is "IA_CSS_STREAM_FORMAT_YUV422_8"? + * + * In most use cases, the first stage in the "yuvpp" pipe is the "yuv_scale_ + * binary". However, the "yuv_scale_binary" does NOT support the input-frame + * format as "IA_CSS_STREAM _FORMAT_YUV422_8". + * + * Hence, the "isp_copy_binary" is required to be present in front of the "yuv + * _scale_binary". It would translate the input-frame to the frame formats that + * are supported by the "yuv_scale_binary". + * + * Please refer to "FrameWork/css/isp/pipes/capture_pp/capture_pp_1.0/capture_ + * pp_defs.h" for the list of input-frame formats that are supported by the + * "yuv_scale_binary". + */ + need_isp_copy_binary = + (pipe->stream->config.input_config.format == IA_CSS_STREAM_FORMAT_YUV422_8); +#else /* !USE_INPUT_SYSTEM_VERSION_2401 */ + need_isp_copy_binary = true; +#endif /* USE_INPUT_SYSTEM_VERSION_2401 */ + + if (need_isp_copy_binary) { + err = load_copy_binary(pipe, + &mycs->copy_binary, + next_binary); + + if (err != IA_CSS_SUCCESS) + goto ERR; + + /* + * NOTES + * - Why is "pipe->pipe_settings.capture.copy_binary.online" specified? + * + * In some use cases, the first stage in the "yuvpp" pipe is the + * "isp_copy_binary". The "isp_copy_binary" is designed to process + * the input from either the system DDR or from the IPU internal VMEM. + * So it provides the flag "online" to specify where its input is from, + * i.e.: + * + * (1) "online <= true", the input is from the IPU internal VMEM. + * (2) "online <= false", the input is from the system DDR. + * + * In other use cases, the first stage in the "yuvpp" pipe is the + * "yuv_scale_binary". "The "yuv_scale_binary" is designed to process the + * input ONLY from the system DDR. So it does not provide the flag "online" + * to specify where its input is from. + */ + pipe->pipe_settings.capture.copy_binary.online = pipe->stream->config.online; + } + + /* Viewfinder post-processing */ + if (need_scaler) { + for (i = 0, j = 0; i < mycs->num_yuv_scaler; i++) { + if (mycs->is_output_stage[i]) { + assert(j < 2); + vf_pp_in_info[j] = + &mycs->yuv_scaler_binary[i].vf_frame_info; + j++; + } + } + mycs->num_vf_pp = j; + } else { + vf_pp_in_info[0] = + &mycs->copy_binary.vf_frame_info; + for (i = 1; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + vf_pp_in_info[i] = NULL; + } + mycs->num_vf_pp = 1; + } + mycs->vf_pp_binary = sh_css_calloc(mycs->num_vf_pp, sizeof(struct ia_css_binary)); + if (mycs->vf_pp_binary == NULL) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + goto ERR; + } + + { + struct ia_css_binary_descr vf_pp_descr; + + for (i = 0; i < mycs->num_vf_pp; i++) { + if (pipe->vf_output_info[i].res.width != 0) { + ia_css_pipe_get_vfpp_binarydesc(pipe, + &vf_pp_descr, vf_pp_in_info[i], &pipe->vf_output_info[i]); + err = ia_css_binary_find(&vf_pp_descr, &mycs->vf_pp_binary[i]); + if (err != IA_CSS_SUCCESS) + goto ERR; + } + } + } + + if (err != IA_CSS_SUCCESS) + goto ERR; + +ERR: + if (need_scaler) { + ia_css_pipe_destroy_cas_scaler_desc(&cas_scaler_descr); + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "load_yuvpp_binaries() leave, err=%d\n", + err); + return err; +} + +static enum ia_css_err +unload_yuvpp_binaries(struct ia_css_pipe *pipe) +{ + unsigned int i; + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + + if ((pipe == NULL) || (pipe->mode != IA_CSS_PIPE_ID_YUVPP)) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + ia_css_binary_unload(&pipe->pipe_settings.yuvpp.copy_binary); + for (i = 0; i < pipe->pipe_settings.yuvpp.num_yuv_scaler; i++) { + ia_css_binary_unload(&pipe->pipe_settings.yuvpp.yuv_scaler_binary[i]); + } + for (i = 0; i < pipe->pipe_settings.yuvpp.num_vf_pp; i++) { + ia_css_binary_unload(&pipe->pipe_settings.yuvpp.vf_pp_binary[i]); + } + sh_css_free(pipe->pipe_settings.yuvpp.is_output_stage); + pipe->pipe_settings.yuvpp.is_output_stage = NULL; + sh_css_free(pipe->pipe_settings.yuvpp.yuv_scaler_binary); + pipe->pipe_settings.yuvpp.yuv_scaler_binary = NULL; + sh_css_free(pipe->pipe_settings.yuvpp.vf_pp_binary); + pipe->pipe_settings.yuvpp.vf_pp_binary = NULL; + + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + return IA_CSS_SUCCESS; +} + +static enum ia_css_err yuvpp_start(struct ia_css_pipe *pipe) +{ + struct ia_css_binary *copy_binary; + enum ia_css_err err = IA_CSS_SUCCESS; + enum sh_css_pipe_config_override copy_ovrd; + enum ia_css_input_mode yuvpp_pipe_input_mode; + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + if ((pipe == NULL) || (pipe->mode != IA_CSS_PIPE_ID_YUVPP)) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + yuvpp_pipe_input_mode = pipe->stream->config.mode; + + copy_binary = &pipe->pipe_settings.yuvpp.copy_binary; + + sh_css_metrics_start_frame(); + + /* multi stream video needs mipi buffers */ + +#if !defined(HAS_NO_INPUT_SYSTEM) && ( defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) ) + err = send_mipi_frames(pipe); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } +#endif + + { + unsigned int thread_id; + + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + copy_ovrd = 1 << thread_id; + } + + start_pipe(pipe, copy_ovrd, yuvpp_pipe_input_mode); + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static enum ia_css_err +sh_css_pipe_unload_binaries(struct ia_css_pipe *pipe) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + + if (pipe == NULL) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + /* PIPE_MODE_COPY has no binaries, but has output frames to outside*/ + if (pipe->config.mode == IA_CSS_PIPE_MODE_COPY) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + return IA_CSS_SUCCESS; + } + + switch (pipe->mode) { + case IA_CSS_PIPE_ID_PREVIEW: + err = unload_preview_binaries(pipe); + break; + case IA_CSS_PIPE_ID_VIDEO: + err = unload_video_binaries(pipe); + break; + case IA_CSS_PIPE_ID_CAPTURE: + err = unload_capture_binaries(pipe); + break; + case IA_CSS_PIPE_ID_YUVPP: + err = unload_yuvpp_binaries(pipe); + break; + default: + break; + } + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static enum ia_css_err +sh_css_pipe_load_binaries(struct ia_css_pipe *pipe) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + assert(pipe != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "sh_css_pipe_load_binaries() enter:\n"); + + /* PIPE_MODE_COPY has no binaries, but has output frames to outside*/ + if (pipe->config.mode == IA_CSS_PIPE_MODE_COPY) + return err; + + switch (pipe->mode) { + case IA_CSS_PIPE_ID_PREVIEW: + err = load_preview_binaries(pipe); + break; + case IA_CSS_PIPE_ID_VIDEO: + err = load_video_binaries(pipe); + break; + case IA_CSS_PIPE_ID_CAPTURE: + err = load_capture_binaries(pipe); + break; + case IA_CSS_PIPE_ID_YUVPP: + err = load_yuvpp_binaries(pipe); + break; + case IA_CSS_PIPE_ID_ACC: + break; + default: + err = IA_CSS_ERR_INTERNAL_ERROR; + break; + } + if (err != IA_CSS_SUCCESS) { + if (sh_css_pipe_unload_binaries(pipe) != IA_CSS_SUCCESS) { + /* currently css does not support multiple error returns in a single function, + * using IA_CSS_ERR_INTERNAL_ERROR in this case */ + err = IA_CSS_ERR_INTERNAL_ERROR; + } + } + return err; +} + +static enum ia_css_err +create_host_yuvpp_pipeline(struct ia_css_pipe *pipe) +{ + struct ia_css_pipeline *me; + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_pipeline_stage *vf_pp_stage = NULL, + *copy_stage = NULL, + *yuv_scaler_stage = NULL; + struct ia_css_binary *copy_binary, + *vf_pp_binary, + *yuv_scaler_binary; + bool need_scaler = false; + unsigned int num_stage, num_vf_pp_stage, num_output_stage; + unsigned int i, j; + + struct ia_css_frame *in_frame = NULL; + struct ia_css_frame *out_frame[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + struct ia_css_frame *bin_out_frame[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_frame *vf_frame[IA_CSS_PIPE_MAX_OUTPUT_STAGE]; + struct ia_css_pipeline_stage_desc stage_desc; + bool need_in_frameinfo_memory = false; +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + bool sensor = false; + bool buffered_sensor = false; + bool online = false; + bool continuous = false; +#endif + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + if ((pipe == NULL) || (pipe->stream == NULL) || (pipe->mode != IA_CSS_PIPE_ID_YUVPP)) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + me = &pipe->pipeline; + ia_css_pipeline_clean(me); + for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + out_frame[i] = NULL; + vf_frame[i] = NULL; + } + ia_css_pipe_util_create_output_frames(bin_out_frame); + num_stage = pipe->pipe_settings.yuvpp.num_yuv_scaler; + num_vf_pp_stage = pipe->pipe_settings.yuvpp.num_vf_pp; + num_output_stage = pipe->pipe_settings.yuvpp.num_output; + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + /* When the input system is 2401, always enable 'in_frameinfo_memory' + * except for the following: + * - Direct Sensor Mode Online Capture + * - Direct Sensor Mode Continuous Capture + * - Buffered Sensor Mode Continous Capture + */ + sensor = pipe->stream->config.mode == IA_CSS_INPUT_MODE_SENSOR; + buffered_sensor = pipe->stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR; + online = pipe->stream->config.online; + continuous = pipe->stream->config.continuous; + need_in_frameinfo_memory = + !((sensor && (online || continuous)) || (buffered_sensor && continuous)); +#else + /* Construct in_frame info (only in case we have dynamic input */ + need_in_frameinfo_memory = pipe->stream->config.mode == IA_CSS_INPUT_MODE_MEMORY; +#endif + /* the input frame can come from: + * a) memory: connect yuvscaler to me->in_frame + * b) sensor, via copy binary: connect yuvscaler to copy binary later on */ + if (need_in_frameinfo_memory) { + /* TODO: improve for different input formats. */ + + /* + * "pipe->stream->config.input_config.format" represents the sensor output + * frame format, e.g. YUV422 8-bit. + * + * "in_frame_format" represents the imaging pipe's input frame format, e.g. + * Bayer-Quad RAW. + */ + int in_frame_format; + if (pipe->stream->config.input_config.format == IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY) { + in_frame_format = IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8; + } else if (pipe->stream->config.input_config.format == IA_CSS_STREAM_FORMAT_YUV422_8) { + /* + * When the sensor output frame format is "IA_CSS_STREAM_FORMAT_YUV422_8", + * the "isp_copy_var" binary is selected as the first stage in the yuvpp + * pipe. + * + * For the "isp_copy_var" binary, it reads the YUV422-8 pixels from + * the frame buffer (at DDR) to the frame-line buffer (at VMEM). + * + * By now, the "isp_copy_var" binary does NOT provide a separated + * frame-line buffer to store the YUV422-8 pixels. Instead, it stores + * the YUV422-8 pixels in the frame-line buffer which is designed to + * store the Bayer-Quad RAW pixels. + * + * To direct the "isp_copy_var" binary reading from the RAW frame-line + * buffer, its input frame format must be specified as "IA_CSS_FRAME_ + * FORMAT_RAW". + */ + in_frame_format = IA_CSS_FRAME_FORMAT_RAW; + } else { + in_frame_format = IA_CSS_FRAME_FORMAT_NV12; + } + + err = init_in_frameinfo_memory_defaults(pipe, + &me->in_frame, + in_frame_format); + + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + in_frame = &me->in_frame; + } else { + in_frame = NULL; + } + + for (i = 0; i < num_output_stage; i++) { + assert(i < IA_CSS_PIPE_MAX_OUTPUT_STAGE); + if (pipe->output_info[i].res.width != 0) { + err = init_out_frameinfo_defaults(pipe, &me->out_frame[i], i); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + out_frame[i] = &me->out_frame[i]; + } + + /* Construct vf_frame info (only in case we have VF) */ + if (pipe->vf_output_info[i].res.width != 0) { + err = init_vf_frameinfo_defaults(pipe, &me->vf_frame[i], i); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + vf_frame[i] = &me->vf_frame[i]; + } + } + + copy_binary = &pipe->pipe_settings.yuvpp.copy_binary; + vf_pp_binary = pipe->pipe_settings.yuvpp.vf_pp_binary; + yuv_scaler_binary = pipe->pipe_settings.yuvpp.yuv_scaler_binary; + need_scaler = need_yuv_scaler_stage(pipe); + + if (pipe->pipe_settings.yuvpp.copy_binary.info) { + + struct ia_css_frame *in_frame_local = NULL; + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + /* After isp copy is enabled in_frame needs to be passed. */ + if (!online) + in_frame_local = in_frame; +#endif + + if (need_scaler) { + ia_css_pipe_util_set_output_frames(bin_out_frame, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, copy_binary, + bin_out_frame, in_frame_local, NULL); + } else { + ia_css_pipe_util_set_output_frames(bin_out_frame, 0, out_frame[0]); + ia_css_pipe_get_generic_stage_desc(&stage_desc, copy_binary, + bin_out_frame, in_frame_local, NULL); + } + + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, + ©_stage); + + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + if (copy_stage) { + /* if we use yuv scaler binary, vf output should be from there */ + copy_stage->args.copy_vf = !need_scaler; + /* for yuvpp pipe, it should always be enabled */ + copy_stage->args.copy_output = true; + /* connect output of copy binary to input of yuv scaler */ + in_frame = copy_stage->args.out_frame[0]; + } + } + + if (need_scaler) { + struct ia_css_frame *tmp_out_frame = NULL; + struct ia_css_frame *tmp_vf_frame = NULL; + struct ia_css_frame *tmp_in_frame = in_frame; + + for (i = 0, j = 0; i < num_stage; i++) { + assert(j < num_output_stage); + if (pipe->pipe_settings.yuvpp.is_output_stage[i] == true) { + tmp_out_frame = out_frame[j]; + tmp_vf_frame = vf_frame[j]; + } else { + tmp_out_frame = NULL; + tmp_vf_frame = NULL; + } + + err = add_yuv_scaler_stage(pipe, me, tmp_in_frame, tmp_out_frame, + NULL, + &yuv_scaler_binary[i], + &yuv_scaler_stage); + + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + /* we use output port 1 as internal output port */ + tmp_in_frame = yuv_scaler_stage->args.out_frame[1]; + if (pipe->pipe_settings.yuvpp.is_output_stage[i] == true) { + if (tmp_vf_frame && (tmp_vf_frame->info.res.width != 0)) { + in_frame = yuv_scaler_stage->args.out_vf_frame; + err = add_vf_pp_stage(pipe, in_frame, tmp_vf_frame, &vf_pp_binary[j], + &vf_pp_stage); + + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + j++; + } + } + } else if (copy_stage != NULL) { + if (vf_frame[0] != NULL && vf_frame[0]->info.res.width != 0) { + in_frame = copy_stage->args.out_vf_frame; + err = add_vf_pp_stage(pipe, in_frame, vf_frame[0], &vf_pp_binary[0], + &vf_pp_stage); + } + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + + ia_css_pipeline_finalize_stages(&pipe->pipeline, pipe->stream->config.continuous); + + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + + return IA_CSS_SUCCESS; +} + +static enum ia_css_err +create_host_copy_pipeline(struct ia_css_pipe *pipe, + unsigned max_input_width, + struct ia_css_frame *out_frame) +{ + struct ia_css_pipeline *me; + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_pipeline_stage_desc stage_desc; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "create_host_copy_pipeline() enter:\n"); + + /* pipeline already created as part of create_host_pipeline_structure */ + me = &pipe->pipeline; + ia_css_pipeline_clean(me); + + /* Construct out_frame info */ + out_frame->contiguous = false; + out_frame->flash_state = IA_CSS_FRAME_FLASH_STATE_NONE; + + if (copy_on_sp(pipe) && + pipe->stream->config.input_config.format == IA_CSS_STREAM_FORMAT_BINARY_8) { + ia_css_frame_info_init( + &out_frame->info, + JPEG_BYTES, + 1, + IA_CSS_FRAME_FORMAT_BINARY_8, + 0); + } else if (out_frame->info.format == IA_CSS_FRAME_FORMAT_RAW) { + out_frame->info.raw_bit_depth = + ia_css_pipe_util_pipe_input_format_bpp(pipe); + } + + me->num_stages = 1; + me->pipe_id = IA_CSS_PIPE_ID_COPY; + pipe->mode = IA_CSS_PIPE_ID_COPY; + + ia_css_pipe_get_sp_func_stage_desc(&stage_desc, out_frame, + IA_CSS_PIPELINE_RAW_COPY, max_input_width); + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, + NULL); + + ia_css_pipeline_finalize_stages(&pipe->pipeline, pipe->stream->config.continuous); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "create_host_copy_pipeline() leave:\n"); + + return err; +} + +static enum ia_css_err +create_host_isyscopy_capture_pipeline(struct ia_css_pipe *pipe) +{ + struct ia_css_pipeline *me = &pipe->pipeline; + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_pipeline_stage_desc stage_desc; + struct ia_css_frame *out_frame = &me->out_frame[0]; + struct ia_css_pipeline_stage *out_stage = NULL; + unsigned int thread_id; + enum sh_css_queue_id queue_id; + unsigned int max_input_width = MAX_VECTORS_PER_INPUT_LINE_CONT * ISP_VEC_NELEMS; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "create_host_isyscopy_capture_pipeline() enter:\n"); + ia_css_pipeline_clean(me); + + /* Construct out_frame info */ + err = sh_css_pipe_get_output_frame_info(pipe, &out_frame->info, 0); + if (err != IA_CSS_SUCCESS) + return err; + out_frame->contiguous = false; + out_frame->flash_state = IA_CSS_FRAME_FLASH_STATE_NONE; + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_OUTPUT_FRAME, thread_id, &queue_id); + out_frame->dynamic_queue_id = queue_id; + out_frame->buf_type = IA_CSS_BUFFER_TYPE_OUTPUT_FRAME; + + me->num_stages = 1; + me->pipe_id = IA_CSS_PIPE_ID_CAPTURE; + pipe->mode = IA_CSS_PIPE_ID_CAPTURE; + ia_css_pipe_get_sp_func_stage_desc(&stage_desc, out_frame, + IA_CSS_PIPELINE_ISYS_COPY, max_input_width); + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, &out_stage); + if(err != IA_CSS_SUCCESS) + return err; + + ia_css_pipeline_finalize_stages(me, pipe->stream->config.continuous); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "create_host_isyscopy_capture_pipeline() leave:\n"); + + return err; +} + +static enum ia_css_err +create_host_regular_capture_pipeline(struct ia_css_pipe *pipe) +{ + struct ia_css_pipeline *me; + enum ia_css_err err = IA_CSS_SUCCESS; + enum ia_css_capture_mode mode; + struct ia_css_pipeline_stage *current_stage = NULL; + struct ia_css_pipeline_stage *yuv_scaler_stage = NULL; + struct ia_css_binary *copy_binary, + *primary_binary[MAX_NUM_PRIMARY_STAGES], + *vf_pp_binary, + *pre_isp_binary, + *anr_gdc_binary, + *post_isp_binary, + *yuv_scaler_binary, + *capture_pp_binary, + *capture_ldc_binary; + bool need_pp = false; + bool raw; + + struct ia_css_frame *in_frame; + struct ia_css_frame *out_frame; + struct ia_css_frame *out_frames[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_frame *vf_frame; + struct ia_css_pipeline_stage_desc stage_desc; + bool need_in_frameinfo_memory = false; +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + bool sensor = false; + bool buffered_sensor = false; + bool online = false; + bool continuous = false; +#endif + unsigned int i, num_yuv_scaler, num_primary_stage; + bool need_yuv_pp = false; + bool *is_output_stage = NULL; + bool need_ldc = false; + + IA_CSS_ENTER_PRIVATE(""); + assert(pipe != NULL); + assert(pipe->stream != NULL); + assert(pipe->mode == IA_CSS_PIPE_ID_CAPTURE || pipe->mode == IA_CSS_PIPE_ID_COPY); + + me = &pipe->pipeline; + mode = pipe->config.default_capture_config.mode; + raw = (mode == IA_CSS_CAPTURE_MODE_RAW); + ia_css_pipeline_clean(me); + ia_css_pipe_util_create_output_frames(out_frames); + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + /* When the input system is 2401, always enable 'in_frameinfo_memory' + * except for the following: + * - Direct Sensor Mode Online Capture + * - Direct Sensor Mode Online Capture + * - Direct Sensor Mode Continuous Capture + * - Buffered Sensor Mode Continous Capture + */ + sensor = (pipe->stream->config.mode == IA_CSS_INPUT_MODE_SENSOR); + buffered_sensor = (pipe->stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR); + online = pipe->stream->config.online; + continuous = pipe->stream->config.continuous; + need_in_frameinfo_memory = + !((sensor && (online || continuous)) || (buffered_sensor && (online || continuous))); +#else + /* Construct in_frame info (only in case we have dynamic input */ + need_in_frameinfo_memory = pipe->stream->config.mode == IA_CSS_INPUT_MODE_MEMORY; +#endif + if (need_in_frameinfo_memory) { + err = init_in_frameinfo_memory_defaults(pipe, &me->in_frame, IA_CSS_FRAME_FORMAT_RAW); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + in_frame = &me->in_frame; + } else { + in_frame = NULL; + } + + err = init_out_frameinfo_defaults(pipe, &me->out_frame[0], 0); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + out_frame = &me->out_frame[0]; + + /* Construct vf_frame info (only in case we have VF) */ + if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0]) { + if (mode == IA_CSS_CAPTURE_MODE_RAW || mode == IA_CSS_CAPTURE_MODE_BAYER) { + /* These modes don't support viewfinder output */ + vf_frame = NULL; + } else { + init_vf_frameinfo_defaults(pipe, &me->vf_frame[0], 0); + vf_frame = &me->vf_frame[0]; + } + } else { + vf_frame = NULL; + } + + copy_binary = &pipe->pipe_settings.capture.copy_binary; + num_primary_stage = pipe->pipe_settings.capture.num_primary_stage; + if ((num_primary_stage == 0) && (mode == IA_CSS_CAPTURE_MODE_PRIMARY)) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INTERNAL_ERROR); + return IA_CSS_ERR_INTERNAL_ERROR; + } + for (i = 0; i < num_primary_stage; i++) { + primary_binary[i] = &pipe->pipe_settings.capture.primary_binary[i]; + } + vf_pp_binary = &pipe->pipe_settings.capture.vf_pp_binary; + pre_isp_binary = &pipe->pipe_settings.capture.pre_isp_binary; + anr_gdc_binary = &pipe->pipe_settings.capture.anr_gdc_binary; + post_isp_binary = &pipe->pipe_settings.capture.post_isp_binary; + capture_pp_binary = &pipe->pipe_settings.capture.capture_pp_binary; + yuv_scaler_binary = pipe->pipe_settings.capture.yuv_scaler_binary; + num_yuv_scaler = pipe->pipe_settings.capture.num_yuv_scaler; + is_output_stage = pipe->pipe_settings.capture.is_output_stage; + capture_ldc_binary = &pipe->pipe_settings.capture.capture_ldc_binary; + + need_pp = (need_capture_pp(pipe) || pipe->output_stage) && + mode != IA_CSS_CAPTURE_MODE_RAW && + mode != IA_CSS_CAPTURE_MODE_BAYER; + need_yuv_pp = (yuv_scaler_binary != NULL && yuv_scaler_binary->info != NULL); + need_ldc = (capture_ldc_binary != NULL && capture_ldc_binary->info != NULL); + + if (pipe->pipe_settings.capture.copy_binary.info) { + if (raw) { + ia_css_pipe_util_set_output_frames(out_frames, 0, out_frame); +#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2401) + if (!continuous) { + ia_css_pipe_get_generic_stage_desc(&stage_desc, copy_binary, + out_frames, in_frame, NULL); + } else { + in_frame = pipe->stream->last_pipe->continuous_frames[0]; + ia_css_pipe_get_generic_stage_desc(&stage_desc, copy_binary, + out_frames, in_frame, NULL); + } +#else + ia_css_pipe_get_generic_stage_desc(&stage_desc, copy_binary, + out_frames, NULL, NULL); +#endif + } else { + ia_css_pipe_util_set_output_frames(out_frames, 0, in_frame); + ia_css_pipe_get_generic_stage_desc(&stage_desc, copy_binary, + out_frames, NULL, NULL); + } + + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, + ¤t_stage); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } else if (pipe->stream->config.continuous) { + in_frame = pipe->stream->last_pipe->continuous_frames[0]; + } + + if (mode == IA_CSS_CAPTURE_MODE_PRIMARY) { + unsigned int frm; + struct ia_css_frame *local_in_frame = NULL; + struct ia_css_frame *local_out_frame = NULL; + + for (i = 0; i < num_primary_stage; i++) { + if (i == 0) + local_in_frame = in_frame; + else + local_in_frame = NULL; +#ifndef ISP2401 + if (!need_pp && (i == num_primary_stage - 1)) +#else + if (!need_pp && (i == num_primary_stage - 1) && !need_ldc) +#endif + local_out_frame = out_frame; + else + local_out_frame = NULL; + ia_css_pipe_util_set_output_frames(out_frames, 0, local_out_frame); +/* + * WARNING: The #if def flag has been added below as a + * temporary solution to solve the problem of enabling the + * view finder in a single binary in a capture flow. The + * vf-pp stage has been removed from Skycam in the solution + * provided. The vf-pp stage should be re-introduced when + * required. This * should not be considered as a clean solution. + * Proper investigation should be done to come up with the clean + * solution. + * */ + ia_css_pipe_get_generic_stage_desc(&stage_desc, primary_binary[i], + out_frames, local_in_frame, NULL); + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, + ¤t_stage); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + (void)frm; + /* If we use copy iso primary, + the input must be yuv iso raw */ + current_stage->args.copy_vf = + primary_binary[0]->info->sp.pipeline.mode == + IA_CSS_BINARY_MODE_COPY; + current_stage->args.copy_output = current_stage->args.copy_vf; + } else if (mode == IA_CSS_CAPTURE_MODE_ADVANCED || + mode == IA_CSS_CAPTURE_MODE_LOW_LIGHT) { + ia_css_pipe_util_set_output_frames(out_frames, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, pre_isp_binary, + out_frames, in_frame, NULL); + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, NULL); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + ia_css_pipe_util_set_output_frames(out_frames, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, anr_gdc_binary, + out_frames, NULL, NULL); + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, NULL); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + if(need_pp) { + ia_css_pipe_util_set_output_frames(out_frames, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, post_isp_binary, + out_frames, NULL, NULL); + } else { + ia_css_pipe_util_set_output_frames(out_frames, 0, out_frame); + ia_css_pipe_get_generic_stage_desc(&stage_desc, post_isp_binary, + out_frames, NULL, NULL); + } + + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, ¤t_stage); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } else if (mode == IA_CSS_CAPTURE_MODE_BAYER) { + ia_css_pipe_util_set_output_frames(out_frames, 0, out_frame); + ia_css_pipe_get_generic_stage_desc(&stage_desc, pre_isp_binary, + out_frames, in_frame, NULL); + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, + NULL); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + +#ifndef ISP2401 + if (need_pp && current_stage) { + struct ia_css_frame *local_in_frame = NULL; + local_in_frame = current_stage->args.out_frame[0]; + + if(need_ldc) { + ia_css_pipe_util_set_output_frames(out_frames, 0, NULL); + ia_css_pipe_get_generic_stage_desc(&stage_desc, capture_ldc_binary, + out_frames, local_in_frame, NULL); + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, + ¤t_stage); + local_in_frame = current_stage->args.out_frame[0]; + } + err = add_capture_pp_stage(pipe, me, local_in_frame, need_yuv_pp ? NULL : out_frame, +#else + /* ldc and capture_pp not supported in same pipeline */ + if (need_ldc && current_stage) { + in_frame = current_stage->args.out_frame[0]; + ia_css_pipe_util_set_output_frames(out_frames, 0, out_frame); + ia_css_pipe_get_generic_stage_desc(&stage_desc, capture_ldc_binary, + out_frames, in_frame, NULL); + err = ia_css_pipeline_create_and_add_stage(me, + &stage_desc, + NULL); + } else if (need_pp && current_stage) { + in_frame = current_stage->args.out_frame[0]; + err = add_capture_pp_stage(pipe, me, in_frame, need_yuv_pp ? NULL : out_frame, +#endif + capture_pp_binary, + ¤t_stage); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + + if (need_yuv_pp && current_stage) { + struct ia_css_frame *tmp_in_frame = current_stage->args.out_frame[0]; + struct ia_css_frame *tmp_out_frame = NULL; + + for (i = 0; i < num_yuv_scaler; i++) { + if (is_output_stage[i] == true) + tmp_out_frame = out_frame; + else + tmp_out_frame = NULL; + + err = add_yuv_scaler_stage(pipe, me, tmp_in_frame, tmp_out_frame, + NULL, + &yuv_scaler_binary[i], + &yuv_scaler_stage); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + /* we use output port 1 as internal output port */ + tmp_in_frame = yuv_scaler_stage->args.out_frame[1]; + } + } + +/* + * WARNING: The #if def flag has been added below as a + * temporary solution to solve the problem of enabling the + * view finder in a single binary in a capture flow. The vf-pp + * stage has been removed from Skycam in the solution provided. + * The vf-pp stage should be re-introduced when required. This + * should not be considered as a clean solution. Proper + * investigation should be done to come up with the clean solution. + * */ + if (mode != IA_CSS_CAPTURE_MODE_RAW && mode != IA_CSS_CAPTURE_MODE_BAYER && current_stage && vf_frame) { + in_frame = current_stage->args.out_vf_frame; + err = add_vf_pp_stage(pipe, in_frame, vf_frame, vf_pp_binary, + ¤t_stage); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + ia_css_pipeline_finalize_stages(&pipe->pipeline, pipe->stream->config.continuous); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "create_host_regular_capture_pipeline() leave:\n"); + + return IA_CSS_SUCCESS; +} + +static enum ia_css_err +create_host_capture_pipeline(struct ia_css_pipe *pipe) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + + if (pipe->config.mode == IA_CSS_PIPE_MODE_COPY) + err = create_host_isyscopy_capture_pipeline(pipe); + else + err = create_host_regular_capture_pipeline(pipe); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + IA_CSS_LEAVE_ERR_PRIVATE(err); + + return err; +} + +static enum ia_css_err capture_start( + struct ia_css_pipe *pipe) +{ + struct ia_css_pipeline *me; + + enum ia_css_err err = IA_CSS_SUCCESS; + enum sh_css_pipe_config_override copy_ovrd; + + IA_CSS_ENTER_PRIVATE("pipe = %p", pipe); + if (pipe == NULL) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + me = &pipe->pipeline; + + if ((pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_RAW || + pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_BAYER ) && + (pipe->config.mode != IA_CSS_PIPE_MODE_COPY)) { + if (copy_on_sp(pipe)) { + err = start_copy_on_sp(pipe, &me->out_frame[0]); + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + +#if defined(USE_INPUT_SYSTEM_VERSION_2) + /* old isys: need to send_mipi_frames() in all pipe modes */ + err = send_mipi_frames(pipe); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } +#elif defined(USE_INPUT_SYSTEM_VERSION_2401) + if (pipe->config.mode != IA_CSS_PIPE_MODE_COPY) { + err = send_mipi_frames(pipe); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + +#endif + + { + unsigned int thread_id; + + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + copy_ovrd = 1 << thread_id; + + } + start_pipe(pipe, copy_ovrd, pipe->stream->config.mode); + +#if !defined(HAS_NO_INPUT_SYSTEM) && !defined(USE_INPUT_SYSTEM_VERSION_2401) + /* + * old isys: for IA_CSS_PIPE_MODE_COPY pipe, isys rx has to be configured, + * which is currently done in start_binary(); but COPY pipe contains no binary, + * and does not call start_binary(); so we need to configure the rx here. + */ + if (pipe->config.mode == IA_CSS_PIPE_MODE_COPY && pipe->stream->reconfigure_css_rx) { + ia_css_isys_rx_configure(&pipe->stream->csi_rx_config, pipe->stream->config.mode); + pipe->stream->reconfigure_css_rx = false; + } +#endif + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + +} + +static enum ia_css_err +sh_css_pipe_get_output_frame_info(struct ia_css_pipe *pipe, + struct ia_css_frame_info *info, + unsigned int idx) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + assert(pipe != NULL); + assert(info != NULL); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_pipe_get_output_frame_info() enter:\n"); + + *info = pipe->output_info[idx]; + if (copy_on_sp(pipe) && + pipe->stream->config.input_config.format == IA_CSS_STREAM_FORMAT_BINARY_8) { + ia_css_frame_info_init( + info, + JPEG_BYTES, + 1, + IA_CSS_FRAME_FORMAT_BINARY_8, + 0); + } else if (info->format == IA_CSS_FRAME_FORMAT_RAW || + info->format == IA_CSS_FRAME_FORMAT_RAW_PACKED) { + info->raw_bit_depth = + ia_css_pipe_util_pipe_input_format_bpp(pipe); + + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_pipe_get_output_frame_info() leave:\n"); + return err; +} + +#if !defined(HAS_NO_INPUT_SYSTEM) +void +ia_css_stream_send_input_frame(const struct ia_css_stream *stream, + const unsigned short *data, + unsigned int width, + unsigned int height) +{ + assert(stream != NULL); + + ia_css_inputfifo_send_input_frame( + data, width, height, + stream->config.channel_id, + stream->config.input_config.format, + stream->config.pixels_per_clock == 2); +} + +void +ia_css_stream_start_input_frame(const struct ia_css_stream *stream) +{ + assert(stream != NULL); + + ia_css_inputfifo_start_frame( + stream->config.channel_id, + stream->config.input_config.format, + stream->config.pixels_per_clock == 2); +} + +void +ia_css_stream_send_input_line(const struct ia_css_stream *stream, + const unsigned short *data, + unsigned int width, + const unsigned short *data2, + unsigned int width2) +{ + assert(stream != NULL); + + ia_css_inputfifo_send_line(stream->config.channel_id, + data, width, data2, width2); +} + +void +ia_css_stream_send_input_embedded_line(const struct ia_css_stream *stream, + enum ia_css_stream_format format, + const unsigned short *data, + unsigned int width) +{ + assert(stream != NULL); + if (data == NULL || width == 0) + return; + ia_css_inputfifo_send_embedded_line(stream->config.channel_id, + format, data, width); +} + +void +ia_css_stream_end_input_frame(const struct ia_css_stream *stream) +{ + assert(stream != NULL); + + ia_css_inputfifo_end_frame(stream->config.channel_id); +} +#endif + +static void +append_firmware(struct ia_css_fw_info **l, struct ia_css_fw_info *firmware) +{ + IA_CSS_ENTER_PRIVATE("l = %p, firmware = %p", l , firmware); + if (l == NULL) { + IA_CSS_ERROR("NULL fw_info"); + IA_CSS_LEAVE_PRIVATE(""); + return; + } + while (*l) + l = &(*l)->next; + *l = firmware; + /*firmware->next = NULL;*/ /* when multiple acc extensions are loaded, 'next' can be not NULL */ + IA_CSS_LEAVE_PRIVATE(""); +} + +static void +remove_firmware(struct ia_css_fw_info **l, struct ia_css_fw_info *firmware) +{ + assert(*l); + assert(firmware); + (void)l; + (void)firmware; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "remove_firmware() enter:\n"); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, "remove_firmware() leave:\n"); + return; /* removing single and multiple firmware is handled in acc_unload_extension() */ +} + +#if !defined(C_RUN) && !defined(HRT_UNSCHED) +static enum ia_css_err +upload_isp_code(struct ia_css_fw_info *firmware) +{ + hrt_vaddress binary; + + if (firmware == NULL) { + IA_CSS_ERROR("NULL input parameter"); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + binary = firmware->info.isp.xmem_addr; + + if (!binary) { + unsigned size = firmware->blob.size; + const unsigned char *blob; + const unsigned char *binary_name; + binary_name = + (const unsigned char *)(IA_CSS_EXT_ISP_PROG_NAME( + firmware)); + blob = binary_name + + strlen((const char *)binary_name) + + 1; + binary = sh_css_load_blob(blob, size); + firmware->info.isp.xmem_addr = binary; + } + + if (!binary) + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + return IA_CSS_SUCCESS; +} +#endif + +static enum ia_css_err +acc_load_extension(struct ia_css_fw_info *firmware) +{ +#if !defined(C_RUN) && !defined(HRT_UNSCHED) + enum ia_css_err err; + struct ia_css_fw_info *hd = firmware; + while (hd){ + err = upload_isp_code(hd); + if (err != IA_CSS_SUCCESS) + return err; + hd = hd->next; + } +#endif + + if (firmware == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + firmware->loaded = true; + return IA_CSS_SUCCESS; +} + +static void +acc_unload_extension(struct ia_css_fw_info *firmware) +{ + struct ia_css_fw_info *hd = firmware; + struct ia_css_fw_info *hdn = NULL; + + if (firmware == NULL) /* should not happen */ + return; + /* unload and remove multiple firmwares */ + while (hd){ + hdn = (hd->next) ? &(*hd->next) : NULL; + if (hd->info.isp.xmem_addr) { + mmgr_free(hd->info.isp.xmem_addr); + hd->info.isp.xmem_addr = mmgr_NULL; + } + hd->isp_code = NULL; + hd->next = NULL; + hd = hdn; + } + + firmware->loaded = false; +} +/* Load firmware for extension */ +static enum ia_css_err +ia_css_pipe_load_extension(struct ia_css_pipe *pipe, + struct ia_css_fw_info *firmware) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + IA_CSS_ENTER_PRIVATE("fw = %p pipe = %p", firmware, pipe); + + if ((firmware == NULL) || (pipe == NULL)) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + if (firmware->info.isp.type == IA_CSS_ACC_OUTPUT) { + if (&pipe->output_stage != NULL) + append_firmware(&pipe->output_stage, firmware); + else { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INTERNAL_ERROR); + return IA_CSS_ERR_INTERNAL_ERROR; + } + } + else if (firmware->info.isp.type == IA_CSS_ACC_VIEWFINDER) { + if (&pipe->vf_stage != NULL) + append_firmware(&pipe->vf_stage, firmware); + else { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INTERNAL_ERROR); + return IA_CSS_ERR_INTERNAL_ERROR; + } + } + err = acc_load_extension(firmware); + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +/* Unload firmware for extension */ +static void +ia_css_pipe_unload_extension(struct ia_css_pipe *pipe, + struct ia_css_fw_info *firmware) +{ + IA_CSS_ENTER_PRIVATE("fw = %p pipe = %p", firmware, pipe); + + if ((firmware == NULL) || (pipe == NULL)) { + IA_CSS_ERROR("NULL input parameters"); + IA_CSS_LEAVE_PRIVATE(""); + return; + } + + if (firmware->info.isp.type == IA_CSS_ACC_OUTPUT) + remove_firmware(&pipe->output_stage, firmware); + else if (firmware->info.isp.type == IA_CSS_ACC_VIEWFINDER) + remove_firmware(&pipe->vf_stage, firmware); + acc_unload_extension(firmware); + + IA_CSS_LEAVE_PRIVATE(""); +} + +bool +ia_css_pipeline_uses_params(struct ia_css_pipeline *me) +{ + struct ia_css_pipeline_stage *stage; + + assert(me != NULL); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_uses_params() enter: me=%p\n", me); + + for (stage = me->stages; stage; stage = stage->next) + if (stage->binary_info && stage->binary_info->enable.params) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_uses_params() leave: " + "return_bool=true\n"); + return true; + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipeline_uses_params() leave: return_bool=false\n"); + return false; +} + +static enum ia_css_err +sh_css_pipeline_add_acc_stage(struct ia_css_pipeline *pipeline, + const void *acc_fw) +{ + struct ia_css_fw_info *fw = (struct ia_css_fw_info *)acc_fw; + /* In QoS case, load_extension already called, so skipping */ + enum ia_css_err err = IA_CSS_SUCCESS; + if (fw->loaded == false) + err = acc_load_extension(fw); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "sh_css_pipeline_add_acc_stage() enter: pipeline=%p," + " acc_fw=%p\n", pipeline, acc_fw); + + if (err == IA_CSS_SUCCESS) { + struct ia_css_pipeline_stage_desc stage_desc; + ia_css_pipe_get_acc_stage_desc(&stage_desc, NULL, fw); + err = ia_css_pipeline_create_and_add_stage(pipeline, + &stage_desc, + NULL); + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "sh_css_pipeline_add_acc_stage() leave: return_err=%d\n",err); + return err; +} + +/** + * @brief Tag a specific frame in continuous capture. + * Refer to "sh_css_internal.h" for details. + */ +enum ia_css_err ia_css_stream_capture_frame(struct ia_css_stream *stream, + unsigned int exp_id) +{ + struct sh_css_tag_descr tag_descr; + uint32_t encoded_tag_descr; + enum ia_css_err err; + + assert(stream != NULL); + IA_CSS_ENTER("exp_id=%d", exp_id); + + /* Only continuous streams have a tagger */ + if (exp_id == 0 || !stream->config.continuous) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + if (!sh_css_sp_is_running()) { + /* SP is not running. The queues are not valid */ + IA_CSS_LEAVE_ERR(IA_CSS_ERR_RESOURCE_NOT_AVAILABLE); + return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } + + /* Create the tag descriptor from the parameters */ + sh_css_create_tag_descr(0, 0, 0, exp_id, &tag_descr); + /* Encode the tag descriptor into a 32-bit value */ + encoded_tag_descr = sh_css_encode_tag_descr(&tag_descr); + /* Enqueue the encoded tag to the host2sp queue. + * Note: The pipe and stage IDs for tag_cmd queue are hard-coded to 0 + * on both host and the SP side. + * It is mainly because it is enough to have only one tag_cmd queue */ + err= ia_css_bufq_enqueue_tag_cmd(encoded_tag_descr); + + IA_CSS_LEAVE_ERR(err); + return err; +} + +/** + * @brief Configure the continuous capture. + * Refer to "sh_css_internal.h" for details. + */ +enum ia_css_err ia_css_stream_capture( + struct ia_css_stream *stream, + int num_captures, + unsigned int skip, + int offset) +{ + struct sh_css_tag_descr tag_descr; + unsigned int encoded_tag_descr; + enum ia_css_err return_err; + + if (stream == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_stream_capture() enter: num_captures=%d," + " skip=%d, offset=%d\n", num_captures, skip,offset); + + /* Check if the tag descriptor is valid */ + if (num_captures < SH_CSS_MINIMUM_TAG_ID) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_stream_capture() leave: return_err=%d\n", + IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + /* Create the tag descriptor from the parameters */ + sh_css_create_tag_descr(num_captures, skip, offset, 0, &tag_descr); + + + /* Encode the tag descriptor into a 32-bit value */ + encoded_tag_descr = sh_css_encode_tag_descr(&tag_descr); + + if (!sh_css_sp_is_running()) { + /* SP is not running. The queues are not valid */ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_stream_capture() leaving:" + "queues unavailable\n"); + return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } + + /* Enqueue the encoded tag to the host2sp queue. + * Note: The pipe and stage IDs for tag_cmd queue are hard-coded to 0 + * on both host and the SP side. + * It is mainly because it is enough to have only one tag_cmd queue */ + return_err = ia_css_bufq_enqueue_tag_cmd((uint32_t)encoded_tag_descr); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_stream_capture() leave: return_err=%d\n", + return_err); + + return return_err; +} + +void ia_css_stream_request_flash(struct ia_css_stream *stream) +{ + (void)stream; + + assert(stream != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_request_flash() enter: void\n"); + +#ifndef ISP2401 + sh_css_write_host2sp_command(host2sp_cmd_start_flash); +#else + if (sh_css_sp_is_running()) { + if (!sh_css_write_host2sp_command(host2sp_cmd_start_flash)) { + IA_CSS_ERROR("Call to 'sh-css_write_host2sp_command()' failed"); + ia_css_debug_dump_sp_sw_debug_info(); + ia_css_debug_dump_debug_info(NULL); + } + } else + IA_CSS_LOG("SP is not running!"); + +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_stream_request_flash() leave: return_void\n"); +} + +static void +sh_css_init_host_sp_control_vars(void) +{ + const struct ia_css_fw_info *fw; + unsigned int HIVE_ADDR_ia_css_ispctrl_sp_isp_started; + + unsigned int HIVE_ADDR_host_sp_queues_initialized; + unsigned int HIVE_ADDR_sp_sleep_mode; + unsigned int HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb; +#ifndef ISP2401 + unsigned int HIVE_ADDR_sp_stop_copy_preview; +#endif + unsigned int HIVE_ADDR_host_sp_com; + unsigned int o = offsetof(struct host_sp_communication, host2sp_command) + / sizeof(int); + +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) + unsigned int i; +#endif + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_init_host_sp_control_vars() enter: void\n"); + + fw = &sh_css_sp_fw; + HIVE_ADDR_ia_css_ispctrl_sp_isp_started = fw->info.sp.isp_started; + + HIVE_ADDR_host_sp_queues_initialized = + fw->info.sp.host_sp_queues_initialized; + HIVE_ADDR_sp_sleep_mode = fw->info.sp.sleep_mode; + HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb = fw->info.sp.invalidate_tlb; +#ifndef ISP2401 + HIVE_ADDR_sp_stop_copy_preview = fw->info.sp.stop_copy_preview; +#endif + HIVE_ADDR_host_sp_com = fw->info.sp.host_sp_com; + + (void)HIVE_ADDR_ia_css_ispctrl_sp_isp_started; /* Suppres warnings in CRUN */ + + (void)HIVE_ADDR_sp_sleep_mode; + (void)HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb; +#ifndef ISP2401 + (void)HIVE_ADDR_sp_stop_copy_preview; +#endif + (void)HIVE_ADDR_host_sp_com; + + sp_dmem_store_uint32(SP0_ID, + (unsigned int)sp_address_of(ia_css_ispctrl_sp_isp_started), + (uint32_t)(0)); + + sp_dmem_store_uint32(SP0_ID, + (unsigned int)sp_address_of(host_sp_queues_initialized), + (uint32_t)(0)); + sp_dmem_store_uint32(SP0_ID, + (unsigned int)sp_address_of(sp_sleep_mode), + (uint32_t)(0)); + sp_dmem_store_uint32(SP0_ID, + (unsigned int)sp_address_of(ia_css_dmaproxy_sp_invalidate_tlb), + (uint32_t)(false)); +#ifndef ISP2401 + sp_dmem_store_uint32(SP0_ID, + (unsigned int)sp_address_of(sp_stop_copy_preview), + my_css.stop_copy_preview?(uint32_t)(1):(uint32_t)(0)); +#endif + store_sp_array_uint(host_sp_com, o, host2sp_cmd_ready); + +#if !defined(HAS_NO_INPUT_SYSTEM) + for (i = 0; i < N_CSI_PORTS; i++) { + sh_css_update_host2sp_num_mipi_frames + (my_css.num_mipi_frames[i]); + } +#endif + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_init_host_sp_control_vars() leave: return_void\n"); +} + +/** + * create the internal structures and fill in the configuration data + */ +void ia_css_pipe_config_defaults(struct ia_css_pipe_config *pipe_config) +{ + struct ia_css_pipe_config def_config = DEFAULT_PIPE_CONFIG; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_pipe_config_defaults()\n"); + *pipe_config = def_config; +} + +void +ia_css_pipe_extra_config_defaults(struct ia_css_pipe_extra_config *extra_config) +{ + if (extra_config == NULL) { + IA_CSS_ERROR("NULL input parameter"); + return; + } + + extra_config->enable_raw_binning = false; + extra_config->enable_yuv_ds = false; + extra_config->enable_high_speed = false; + extra_config->enable_dvs_6axis = false; + extra_config->enable_reduced_pipe = false; + extra_config->disable_vf_pp = false; + extra_config->enable_fractional_ds = false; +} + +void ia_css_stream_config_defaults(struct ia_css_stream_config *stream_config) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_config_defaults()\n"); + assert(stream_config != NULL); + memset(stream_config, 0, sizeof(*stream_config)); + stream_config->online = true; + stream_config->left_padding = -1; + stream_config->pixels_per_clock = 1; + /* temporary default value for backwards compatibility. + * This field used to be hardcoded within CSS but this has now + * been moved to the stream_config struct. */ + stream_config->source.port.rxcount = 0x04040404; +} + +static enum ia_css_err +ia_css_acc_pipe_create(struct ia_css_pipe *pipe) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + if (pipe == NULL) { + IA_CSS_ERROR("NULL input parameter"); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + /* There is not meaning for num_execs = 0 semantically. Run atleast once. */ + if (pipe->config.acc_num_execs == 0) + pipe->config.acc_num_execs = 1; + + if (pipe->config.acc_extension) { + err = ia_css_pipe_load_extension(pipe, pipe->config.acc_extension); + } + + return err; +} + +enum ia_css_err +ia_css_pipe_create(const struct ia_css_pipe_config *config, + struct ia_css_pipe **pipe) +{ +#ifndef ISP2401 + if (config == NULL) +#else + enum ia_css_err err = IA_CSS_SUCCESS; + IA_CSS_ENTER_PRIVATE("config = %p, pipe = %p", config, pipe); + + if (config == NULL) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); +#endif + return IA_CSS_ERR_INVALID_ARGUMENTS; +#ifndef ISP2401 + if (pipe == NULL) +#else + } + if (pipe == NULL) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); +#endif + return IA_CSS_ERR_INVALID_ARGUMENTS; +#ifndef ISP2401 + return ia_css_pipe_create_extra(config, NULL, pipe); +#else + } + + err = ia_css_pipe_create_extra(config, NULL, pipe); + + if(err == IA_CSS_SUCCESS) { + IA_CSS_LOG("pipe created successfuly = %p", *pipe); + } + + IA_CSS_LEAVE_ERR_PRIVATE(err); + + return err; +#endif +} + +enum ia_css_err +ia_css_pipe_create_extra(const struct ia_css_pipe_config *config, + const struct ia_css_pipe_extra_config *extra_config, + struct ia_css_pipe **pipe) +{ + enum ia_css_err err = IA_CSS_ERR_INTERNAL_ERROR; + struct ia_css_pipe *internal_pipe = NULL; + unsigned int i; + + IA_CSS_ENTER_PRIVATE("config = %p, extra_config = %p and pipe = %p", config, extra_config, pipe); + + /* do not allow to create more than the maximum limit */ + if (my_css.pipe_counter >= IA_CSS_PIPELINE_NUM_MAX) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_RESOURCE_EXHAUSTED); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + if ((pipe == NULL) || (config == NULL)) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + ia_css_debug_dump_pipe_config(config); + ia_css_debug_dump_pipe_extra_config(extra_config); + + err = create_pipe(config->mode, &internal_pipe, false); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + /* now we have a pipe structure to fill */ + internal_pipe->config = *config; + if (extra_config) + internal_pipe->extra_config = *extra_config; + else + ia_css_pipe_extra_config_defaults(&internal_pipe->extra_config); + + if (config->mode == IA_CSS_PIPE_MODE_ACC) { + /* Temporary hack to migrate acceleration to CSS 2.0. + * In the future the code for all pipe types should be + * unified. */ + *pipe = internal_pipe; + if (!internal_pipe->config.acc_extension && + internal_pipe->config.num_acc_stages == 0){ /* if no acc binary and no standalone stage */ + *pipe = NULL; + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + return IA_CSS_SUCCESS; + } + return ia_css_acc_pipe_create(internal_pipe); + } + + /* Use config value when dvs_frame_delay setting equal to 2, otherwise always 1 by default */ + if (internal_pipe->config.dvs_frame_delay == IA_CSS_FRAME_DELAY_2) + internal_pipe->dvs_frame_delay = 2; + else + internal_pipe->dvs_frame_delay = 1; + + + /* we still keep enable_raw_binning for backward compatibility, for any new + fractional bayer downscaling, we should use bayer_ds_out_res. if both are + specified, bayer_ds_out_res will take precedence.if none is specified, we + set bayer_ds_out_res equal to IF output resolution(IF may do cropping on + sensor output) or use default decimation factor 1. */ + if (internal_pipe->extra_config.enable_raw_binning && + internal_pipe->config.bayer_ds_out_res.width) { + /* fill some code here, if no code is needed, please remove it during integration */ + } + + /* YUV downscaling */ + if ((internal_pipe->config.vf_pp_in_res.width || + internal_pipe->config.capt_pp_in_res.width)) { + enum ia_css_frame_format format; + if (internal_pipe->config.vf_pp_in_res.width) { + format = IA_CSS_FRAME_FORMAT_YUV_LINE; + ia_css_frame_info_init( + &internal_pipe->vf_yuv_ds_input_info, + internal_pipe->config.vf_pp_in_res.width, + internal_pipe->config.vf_pp_in_res.height, + format, 0); + } + if (internal_pipe->config.capt_pp_in_res.width) { + format = IA_CSS_FRAME_FORMAT_YUV420; + ia_css_frame_info_init( + &internal_pipe->out_yuv_ds_input_info, + internal_pipe->config.capt_pp_in_res.width, + internal_pipe->config.capt_pp_in_res.height, + format, 0); + } + } + if (internal_pipe->config.vf_pp_in_res.width && + internal_pipe->config.mode == IA_CSS_PIPE_MODE_PREVIEW) { + ia_css_frame_info_init( + &internal_pipe->vf_yuv_ds_input_info, + internal_pipe->config.vf_pp_in_res.width, + internal_pipe->config.vf_pp_in_res.height, + IA_CSS_FRAME_FORMAT_YUV_LINE, 0); + } + /* handle bayer downscaling output info */ + if (internal_pipe->config.bayer_ds_out_res.width) { + ia_css_frame_info_init( + &internal_pipe->bds_output_info, + internal_pipe->config.bayer_ds_out_res.width, + internal_pipe->config.bayer_ds_out_res.height, + IA_CSS_FRAME_FORMAT_RAW, 0); + } + + /* handle output info, assume always needed */ + for (i = 0; i < IA_CSS_PIPE_MAX_OUTPUT_STAGE; i++) { + if (internal_pipe->config.output_info[i].res.width) { + err = sh_css_pipe_configure_output( + internal_pipe, + internal_pipe->config.output_info[i].res.width, + internal_pipe->config.output_info[i].res.height, + internal_pipe->config.output_info[i].padded_width, + internal_pipe->config.output_info[i].format, + i); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + sh_css_free(internal_pipe); + internal_pipe = NULL; + return err; + } + } + + /* handle vf output info, when configured */ + internal_pipe->enable_viewfinder[i] = (internal_pipe->config.vf_output_info[i].res.width != 0); + if (internal_pipe->config.vf_output_info[i].res.width) { + err = sh_css_pipe_configure_viewfinder( + internal_pipe, + internal_pipe->config.vf_output_info[i].res.width, + internal_pipe->config.vf_output_info[i].res.height, + internal_pipe->config.vf_output_info[i].padded_width, + internal_pipe->config.vf_output_info[i].format, + i); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + sh_css_free(internal_pipe); + internal_pipe = NULL; + return err; + } + } + } + if (internal_pipe->config.acc_extension) { + err = ia_css_pipe_load_extension(internal_pipe, + internal_pipe->config.acc_extension); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + sh_css_free(internal_pipe); + return err; + } + } + /* set all info to zeroes first */ + memset(&internal_pipe->info, 0, sizeof(internal_pipe->info)); + + /* all went well, return the pipe */ + *pipe = internal_pipe; + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + return IA_CSS_SUCCESS; +} + + +enum ia_css_err +ia_css_pipe_get_info(const struct ia_css_pipe *pipe, + struct ia_css_pipe_info *pipe_info) +{ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_pipe_get_info()\n"); + assert(pipe_info != NULL); + if (pipe_info == NULL) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "ia_css_pipe_get_info: pipe_info cannot be NULL\n"); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + if (pipe == NULL || pipe->stream == NULL) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "ia_css_pipe_get_info: ia_css_stream_create needs to" + " be called before ia_css_[stream/pipe]_get_info\n"); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + /* we succeeded return the info */ + *pipe_info = pipe->info; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_pipe_get_info() leave\n"); + return IA_CSS_SUCCESS; +} + +bool ia_css_pipe_has_dvs_stats(struct ia_css_pipe_info *pipe_info) +{ + unsigned int i; + + if (pipe_info != NULL) { + for (i = 0; i < IA_CSS_DVS_STAT_NUM_OF_LEVELS; i++) { + if (pipe_info->grid_info.dvs_grid.dvs_stat_grid_info.grd_cfg[i].grd_start.enable) + return true; + } + } + + return false; +} + +#ifdef ISP2401 +enum ia_css_err +ia_css_pipe_override_frame_format(struct ia_css_pipe *pipe, + int pin_index, + enum ia_css_frame_format new_format) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + IA_CSS_ENTER_PRIVATE("pipe = %p, pin_index = %d, new_formats = %d", pipe, pin_index, new_format); + + if (NULL == pipe) { + IA_CSS_ERROR("pipe is not set"); + err = IA_CSS_ERR_INVALID_ARGUMENTS; + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + if (0 != pin_index && 1 != pin_index) { + IA_CSS_ERROR("pin index is not valid"); + err = IA_CSS_ERR_INVALID_ARGUMENTS; + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + if (IA_CSS_FRAME_FORMAT_NV12_TILEY != new_format) { + IA_CSS_ERROR("new format is not valid"); + err = IA_CSS_ERR_INVALID_ARGUMENTS; + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } else { + err = ia_css_pipe_check_format(pipe, new_format); + if (IA_CSS_SUCCESS == err) { + if (pin_index == 0) { + pipe->output_info[0].format = new_format; + } else { + pipe->vf_output_info[0].format = new_format; + } + } + } + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +#endif +#if defined(USE_INPUT_SYSTEM_VERSION_2) +/* Configuration of INPUT_SYSTEM_VERSION_2401 is done on SP */ +static enum ia_css_err +ia_css_stream_configure_rx(struct ia_css_stream *stream) +{ + struct ia_css_input_port *config; + assert(stream != NULL); + + config = &stream->config.source.port; +/* AM: this code is not reliable, especially for 2400 */ + if (config->num_lanes == 1) + stream->csi_rx_config.mode = MONO_1L_1L_0L; + else if (config->num_lanes == 2) + stream->csi_rx_config.mode = MONO_2L_1L_0L; + else if (config->num_lanes == 3) + stream->csi_rx_config.mode = MONO_3L_1L_0L; + else if (config->num_lanes == 4) + stream->csi_rx_config.mode = MONO_4L_1L_0L; + else if (config->num_lanes != 0) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + if (config->port > IA_CSS_CSI2_PORT2) + return IA_CSS_ERR_INVALID_ARGUMENTS; + stream->csi_rx_config.port = + ia_css_isys_port_to_mipi_port(config->port); + stream->csi_rx_config.timeout = config->timeout; + stream->csi_rx_config.initcount = 0; + stream->csi_rx_config.synccount = 0x28282828; + stream->csi_rx_config.rxcount = config->rxcount; + if (config->compression.type == IA_CSS_CSI2_COMPRESSION_TYPE_NONE) + stream->csi_rx_config.comp = MIPI_PREDICTOR_NONE; + else { + /* not implemented yet, requires extension of the rx_cfg_t + * struct */ + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + stream->csi_rx_config.is_two_ppc = (stream->config.pixels_per_clock == 2); + stream->reconfigure_css_rx = true; + return IA_CSS_SUCCESS; +} +#endif + +static struct ia_css_pipe * +find_pipe(struct ia_css_pipe *pipes[], + unsigned int num_pipes, + enum ia_css_pipe_mode mode, + bool copy_pipe) +{ + unsigned i; + assert(pipes != NULL); + for (i = 0; i < num_pipes; i++) { + assert(pipes[i] != NULL); + if (pipes[i]->config.mode != mode) + continue; + if (copy_pipe && pipes[i]->mode != IA_CSS_PIPE_ID_COPY) + continue; + return pipes[i]; + } + return NULL; +} + +static enum ia_css_err +ia_css_acc_stream_create(struct ia_css_stream *stream) +{ + int i; + enum ia_css_err err = IA_CSS_SUCCESS; + + assert(stream != NULL); + IA_CSS_ENTER_PRIVATE("stream = %p", stream); + + if (stream == NULL) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + for (i = 0; i < stream->num_pipes; i++) { + struct ia_css_pipe *pipe = stream->pipes[i]; + assert(pipe != NULL); + if (pipe == NULL) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + pipe->stream = stream; + } + + /* Map SP threads before doing anything. */ + err = map_sp_threads(stream, true); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + for (i = 0; i < stream->num_pipes; i++) { + struct ia_css_pipe *pipe = stream->pipes[i]; + assert(pipe != NULL); + ia_css_pipe_map_queue(pipe, true); + } + + err = create_host_pipeline_structure(stream); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + stream->started = false; + + + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + + return IA_CSS_SUCCESS; +} + +static enum ia_css_err +metadata_info_init(const struct ia_css_metadata_config *mdc, + struct ia_css_metadata_info *md) +{ + /* Either both width and height should be set or neither */ + if ((mdc->resolution.height > 0) ^ (mdc->resolution.width > 0)) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + md->resolution = mdc->resolution; + /* We round up the stride to a multiple of the width + * of the port going to DDR, this is a HW requirements (DMA). */ + md->stride = CEIL_MUL(mdc->resolution.width, HIVE_ISP_DDR_WORD_BYTES); + md->size = mdc->resolution.height * md->stride; + return IA_CSS_SUCCESS; +} + +#ifdef ISP2401 +static enum ia_css_err check_pipe_resolutions(const struct ia_css_pipe *pipe) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + IA_CSS_ENTER_PRIVATE(""); + + if (!pipe || !pipe->stream) { + IA_CSS_ERROR("null arguments"); + err = IA_CSS_ERR_INTERNAL_ERROR; + goto EXIT; + } + + if (ia_css_util_check_res(pipe->config.input_effective_res.width, + pipe->config.input_effective_res.height) != IA_CSS_SUCCESS) { + IA_CSS_ERROR("effective resolution not supported"); + err = IA_CSS_ERR_INVALID_ARGUMENTS; + goto EXIT; + } + if (!ia_css_util_resolution_is_zero(pipe->stream->config.input_config.input_res)) { + if (!ia_css_util_res_leq(pipe->config.input_effective_res, + pipe->stream->config.input_config.input_res)) { + IA_CSS_ERROR("effective resolution is larger than input resolution"); + err = IA_CSS_ERR_INVALID_ARGUMENTS; + goto EXIT; + } + } + if (!ia_css_util_resolution_is_even(pipe->config.output_info[0].res)) { + IA_CSS_ERROR("output resolution must be even"); + err = IA_CSS_ERR_INVALID_ARGUMENTS; + goto EXIT; + } + if (!ia_css_util_resolution_is_even(pipe->config.vf_output_info[0].res)) { + IA_CSS_ERROR("VF resolution must be even"); + err = IA_CSS_ERR_INVALID_ARGUMENTS; + goto EXIT; + } +EXIT: + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +#endif + +enum ia_css_err +ia_css_stream_create(const struct ia_css_stream_config *stream_config, + int num_pipes, + struct ia_css_pipe *pipes[], + struct ia_css_stream **stream) +{ + struct ia_css_pipe *curr_pipe; + struct ia_css_stream *curr_stream = NULL; + bool spcopyonly; + bool sensor_binning_changed; + int i, j; + enum ia_css_err err = IA_CSS_ERR_INTERNAL_ERROR; + struct ia_css_metadata_info md_info; +#ifndef ISP2401 + struct ia_css_resolution effective_res; +#else +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + bool aspect_ratio_crop_enabled = false; +#endif +#endif + + IA_CSS_ENTER("num_pipes=%d", num_pipes); + ia_css_debug_dump_stream_config(stream_config, num_pipes); + + /* some checks */ + if (num_pipes == 0 || + stream == NULL || + pipes == NULL) { + err = IA_CSS_ERR_INVALID_ARGUMENTS; + IA_CSS_LEAVE_ERR(err); + return err; + } + +#if defined(USE_INPUT_SYSTEM_VERSION_2) + /* We don't support metadata for JPEG stream, since they both use str2mem */ + if (stream_config->input_config.format == IA_CSS_STREAM_FORMAT_BINARY_8 && + stream_config->metadata_config.resolution.height > 0) { + err = IA_CSS_ERR_INVALID_ARGUMENTS; + IA_CSS_LEAVE_ERR(err); + return err; + } +#endif + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + if (stream_config->online && stream_config->pack_raw_pixels) { + IA_CSS_LOG("online and pack raw is invalid on input system 2401"); + err = IA_CSS_ERR_INVALID_ARGUMENTS; + IA_CSS_LEAVE_ERR(err); + return err; + } +#endif + +#if !defined(HAS_NO_INPUT_SYSTEM) + ia_css_debug_pipe_graph_dump_stream_config(stream_config); + + /* check if mipi size specified */ + if (stream_config->mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR) +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + if (!stream_config->online) +#endif + { + unsigned int port = (unsigned int) stream_config->source.port.port; + if (port >= N_MIPI_PORT_ID) { + err = IA_CSS_ERR_INVALID_ARGUMENTS; + IA_CSS_LEAVE_ERR(err); + return err; + } + + if (my_css.size_mem_words != 0){ + my_css.mipi_frame_size[port] = my_css.size_mem_words; + } else if (stream_config->mipi_buffer_config.size_mem_words != 0) { + my_css.mipi_frame_size[port] = stream_config->mipi_buffer_config.size_mem_words; + } else { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_stream_create() exit: error, need to set mipi frame size.\n"); + assert(stream_config->mipi_buffer_config.size_mem_words != 0); + err = IA_CSS_ERR_INTERNAL_ERROR; + IA_CSS_LEAVE_ERR(err); + return err; + } + + if (my_css.size_mem_words != 0) { + my_css.num_mipi_frames[port] = 2; /* Temp change: Default for backwards compatibility. */ + } else if (stream_config->mipi_buffer_config.nof_mipi_buffers != 0) { + my_css.num_mipi_frames[port] = stream_config->mipi_buffer_config.nof_mipi_buffers; + } else { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "ia_css_stream_create() exit: error, need to set number of mipi frames.\n"); + assert(stream_config->mipi_buffer_config.nof_mipi_buffers != 0); + err = IA_CSS_ERR_INTERNAL_ERROR; + IA_CSS_LEAVE_ERR(err); + return err; + } + + } +#endif + + /* Currently we only supported metadata up to a certain size. */ + err = metadata_info_init(&stream_config->metadata_config, &md_info); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR(err); + return err; + } + + /* allocate the stream instance */ + curr_stream = sh_css_malloc(sizeof(struct ia_css_stream)); + if (curr_stream == NULL) { + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + IA_CSS_LEAVE_ERR(err); + return err; + } + /* default all to 0 */ + memset(curr_stream, 0, sizeof(struct ia_css_stream)); + curr_stream->info.metadata_info = md_info; + + /* allocate pipes */ + curr_stream->num_pipes = num_pipes; + curr_stream->pipes = sh_css_malloc(num_pipes * sizeof(struct ia_css_pipe *)); + if (curr_stream->pipes == NULL) { + curr_stream->num_pipes = 0; + sh_css_free(curr_stream); + curr_stream = NULL; + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + IA_CSS_LEAVE_ERR(err); + return err; + } + /* store pipes */ + spcopyonly = (num_pipes == 1) && (pipes[0]->config.mode == IA_CSS_PIPE_MODE_COPY); + for (i = 0; i < num_pipes; i++) + curr_stream->pipes [i] = pipes[i]; + curr_stream->last_pipe = curr_stream->pipes[0]; + /* take over stream config */ + curr_stream->config = *stream_config; + +#if defined(USE_INPUT_SYSTEM_VERSION_2401) && defined(CSI2P_DISABLE_ISYS2401_ONLINE_MODE) + if (stream_config->mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR && + stream_config->online) + curr_stream->config.online = false; +#endif + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + if (curr_stream->config.online) { + curr_stream->config.source.port.num_lanes = stream_config->source.port.num_lanes; + curr_stream->config.mode = IA_CSS_INPUT_MODE_BUFFERED_SENSOR; + } +#endif + /* in case driver doesn't configure init number of raw buffers, configure it here */ + if (curr_stream->config.target_num_cont_raw_buf == 0) + curr_stream->config.target_num_cont_raw_buf = NUM_CONTINUOUS_FRAMES; + if (curr_stream->config.init_num_cont_raw_buf == 0) + curr_stream->config.init_num_cont_raw_buf = curr_stream->config.target_num_cont_raw_buf; + + /* Enable locking & unlocking of buffers in RAW buffer pool */ + if (curr_stream->config.ia_css_enable_raw_buffer_locking) + sh_css_sp_configure_enable_raw_pool_locking( + curr_stream->config.lock_all); + + /* copy mode specific stuff */ + switch (curr_stream->config.mode) { + case IA_CSS_INPUT_MODE_SENSOR: + case IA_CSS_INPUT_MODE_BUFFERED_SENSOR: +#if defined(USE_INPUT_SYSTEM_VERSION_2) + ia_css_stream_configure_rx(curr_stream); +#endif + break; + case IA_CSS_INPUT_MODE_TPG: +#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2) + IA_CSS_LOG("tpg_configuration: x_mask=%d, y_mask=%d, x_delta=%d, y_delta=%d, xy_mask=%d", + curr_stream->config.source.tpg.x_mask, + curr_stream->config.source.tpg.y_mask, + curr_stream->config.source.tpg.x_delta, + curr_stream->config.source.tpg.y_delta, + curr_stream->config.source.tpg.xy_mask); + + sh_css_sp_configure_tpg( + curr_stream->config.source.tpg.x_mask, + curr_stream->config.source.tpg.y_mask, + curr_stream->config.source.tpg.x_delta, + curr_stream->config.source.tpg.y_delta, + curr_stream->config.source.tpg.xy_mask); +#endif + break; + case IA_CSS_INPUT_MODE_PRBS: +#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2) + IA_CSS_LOG("mode prbs"); + sh_css_sp_configure_prbs(curr_stream->config.source.prbs.seed); +#endif + break; + case IA_CSS_INPUT_MODE_MEMORY: + IA_CSS_LOG("mode memory"); + curr_stream->reconfigure_css_rx = false; + break; + default: + IA_CSS_LOG("mode sensor/default"); + } + +#ifdef ISP2401 +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + err = aspect_ratio_crop_init(curr_stream, + pipes, + &aspect_ratio_crop_enabled); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR(err); + return err; + } +#endif + +#endif + for (i = 0; i < num_pipes; i++) { +#ifdef ISP2401 + struct ia_css_resolution effective_res; +#endif + curr_pipe = pipes[i]; + /* set current stream */ + curr_pipe->stream = curr_stream; + /* take over effective info */ + + effective_res = curr_pipe->config.input_effective_res; + if (effective_res.height == 0 || effective_res.width == 0) { + effective_res = curr_pipe->stream->config.input_config.effective_res; +#ifdef ISP2401 + +#if defined(USE_INPUT_SYSTEM_VERSION_2401) + /* The aspect ratio cropping is currently only + * supported on the new input system. */ + if (aspect_ratio_crop_check(aspect_ratio_crop_enabled, curr_pipe)) { + + struct ia_css_resolution crop_res; + + err = aspect_ratio_crop(curr_pipe, &crop_res); + if (err == IA_CSS_SUCCESS) { + effective_res = crop_res; + } else { + /* in case of error fallback to default + * effective resolution from driver. */ + IA_CSS_LOG("aspect_ratio_crop() failed with err(%d)", err); + } + } +#endif +#endif + curr_pipe->config.input_effective_res = effective_res; + } + IA_CSS_LOG("effective_res=%dx%d", + effective_res.width, + effective_res.height); + } + +#ifdef ISP2401 + for (i = 0; i < num_pipes; i++) { + if (pipes[i]->config.mode != IA_CSS_PIPE_MODE_ACC && + pipes[i]->config.mode != IA_CSS_PIPE_MODE_COPY) { + err = check_pipe_resolutions(pipes[i]); + if (err != IA_CSS_SUCCESS) { + goto ERR; + } + } + } + +#endif + err = ia_css_stream_isp_parameters_init(curr_stream); + if (err != IA_CSS_SUCCESS) + goto ERR; + IA_CSS_LOG("isp_params_configs: %p", curr_stream->isp_params_configs); + + if (num_pipes == 1 && pipes[0]->config.mode == IA_CSS_PIPE_MODE_ACC) { + *stream = curr_stream; + err = ia_css_acc_stream_create(curr_stream); + goto ERR; + } + /* sensor binning */ + if (!spcopyonly){ + sensor_binning_changed = + sh_css_params_set_binning_factor(curr_stream, curr_stream->config.sensor_binning_factor); + } else { + sensor_binning_changed = false; + } + + IA_CSS_LOG("sensor_binning=%d, changed=%d", + curr_stream->config.sensor_binning_factor, sensor_binning_changed); + /* loop over pipes */ + IA_CSS_LOG("num_pipes=%d", num_pipes); + curr_stream->cont_capt = false; + /* Temporary hack: we give the preview pipe a reference to the capture + * pipe in continuous capture mode. */ + if (curr_stream->config.continuous) { + /* Search for the preview pipe and create the copy pipe */ + struct ia_css_pipe *preview_pipe; + struct ia_css_pipe *video_pipe; + struct ia_css_pipe *acc_pipe; + struct ia_css_pipe *capture_pipe = NULL; + struct ia_css_pipe *copy_pipe = NULL; + + if (num_pipes >= 2) { + curr_stream->cont_capt = true; + curr_stream->disable_cont_vf = curr_stream->config.disable_cont_viewfinder; +#ifndef ISP2401 + curr_stream->stop_copy_preview = my_css.stop_copy_preview; +#endif + } + + /* Create copy pipe here, since it may not be exposed to the driver */ + preview_pipe = find_pipe(pipes, num_pipes, + IA_CSS_PIPE_MODE_PREVIEW, false); + video_pipe = find_pipe(pipes, num_pipes, + IA_CSS_PIPE_MODE_VIDEO, false); + acc_pipe = find_pipe(pipes, num_pipes, + IA_CSS_PIPE_MODE_ACC, false); + if (acc_pipe && num_pipes == 2 && curr_stream->cont_capt == true) + curr_stream->cont_capt = false; /* preview + QoS case will not need cont_capt switch */ + if (curr_stream->cont_capt == true) { + capture_pipe = find_pipe(pipes, num_pipes, + IA_CSS_PIPE_MODE_CAPTURE, false); + if (capture_pipe == NULL) { + err = IA_CSS_ERR_INTERNAL_ERROR; + goto ERR; + } + } + /* We do not support preview and video pipe at the same time */ + if (preview_pipe && video_pipe) { + err = IA_CSS_ERR_INVALID_ARGUMENTS; + goto ERR; + } + + if (preview_pipe && !preview_pipe->pipe_settings.preview.copy_pipe) { + err = create_pipe(IA_CSS_PIPE_MODE_CAPTURE, ©_pipe, true); + if (err != IA_CSS_SUCCESS) + goto ERR; + ia_css_pipe_config_defaults(©_pipe->config); + preview_pipe->pipe_settings.preview.copy_pipe = copy_pipe; + copy_pipe->stream = curr_stream; + } + if (preview_pipe && (curr_stream->cont_capt == true)) { + preview_pipe->pipe_settings.preview.capture_pipe = capture_pipe; + } + if (video_pipe && !video_pipe->pipe_settings.video.copy_pipe) { + err = create_pipe(IA_CSS_PIPE_MODE_CAPTURE, ©_pipe, true); + if (err != IA_CSS_SUCCESS) + goto ERR; + ia_css_pipe_config_defaults(©_pipe->config); + video_pipe->pipe_settings.video.copy_pipe = copy_pipe; + copy_pipe->stream = curr_stream; + } + if (video_pipe && (curr_stream->cont_capt == true)) { + video_pipe->pipe_settings.video.capture_pipe = capture_pipe; + } + if (preview_pipe && acc_pipe) { + preview_pipe->pipe_settings.preview.acc_pipe = acc_pipe; + } + } + for (i = 0; i < num_pipes; i++) { + curr_pipe = pipes[i]; + /* set current stream */ + curr_pipe->stream = curr_stream; +#ifndef ISP2401 + /* take over effective info */ + + effective_res = curr_pipe->config.input_effective_res; +#endif + +#ifndef ISP2401 + err = ia_css_util_check_res( + effective_res.width, + effective_res.height); + if (err != IA_CSS_SUCCESS) + goto ERR; +#endif + /* sensor binning per pipe */ + if (sensor_binning_changed) + sh_css_pipe_free_shading_table(curr_pipe); + } + + /* now pipes have been configured, info should be available */ + for (i = 0; i < num_pipes; i++) { + struct ia_css_pipe_info *pipe_info = NULL; + curr_pipe = pipes[i]; + + err = sh_css_pipe_load_binaries(curr_pipe); + if (err != IA_CSS_SUCCESS) + goto ERR; + +#if defined(HAS_RES_MGR) + /* update acc configuration - striping info is ready */ + err = ia_css_update_cfg_stripe_info(curr_pipe); + if (err != IA_CSS_SUCCESS) + goto ERR; +#endif + + /* handle each pipe */ + pipe_info = &curr_pipe->info; + for (j = 0; j < IA_CSS_PIPE_MAX_OUTPUT_STAGE; j++) { + err = sh_css_pipe_get_output_frame_info(curr_pipe, + &pipe_info->output_info[j], j); + if (err != IA_CSS_SUCCESS) + goto ERR; + } +#ifdef ISP2401 + pipe_info->output_system_in_res_info = curr_pipe->config.output_system_in_res; +#endif + if (!spcopyonly){ + err = sh_css_pipe_get_shading_info(curr_pipe, +#ifndef ISP2401 + &pipe_info->shading_info); +#else + &pipe_info->shading_info, &curr_pipe->config); +#endif + if (err != IA_CSS_SUCCESS) + goto ERR; + err = sh_css_pipe_get_grid_info(curr_pipe, + &pipe_info->grid_info); + if (err != IA_CSS_SUCCESS) + goto ERR; + for (j = 0; j < IA_CSS_PIPE_MAX_OUTPUT_STAGE; j++) { + sh_css_pipe_get_viewfinder_frame_info(curr_pipe, + &pipe_info->vf_output_info[j], j); + if (err != IA_CSS_SUCCESS) + goto ERR; + } + } + + my_css.active_pipes[ia_css_pipe_get_pipe_num(curr_pipe)] = curr_pipe; + } + + curr_stream->started = false; + + /* Map SP threads before doing anything. */ + err = map_sp_threads(curr_stream, true); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LOG("map_sp_threads: return_err=%d", err); + goto ERR; + } + + for (i = 0; i < num_pipes; i++) { + curr_pipe = pipes[i]; + ia_css_pipe_map_queue(curr_pipe, true); + } + + /* Create host side pipeline objects without stages */ + err = create_host_pipeline_structure(curr_stream); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LOG("create_host_pipeline_structure: return_err=%d", err); + goto ERR; + } + + /* assign curr_stream */ + *stream = curr_stream; + +ERR: +#ifndef ISP2401 + if (err == IA_CSS_SUCCESS) + { + /* working mode: enter into the seed list */ + if (my_css_save.mode == sh_css_mode_working) + for(i = 0; i < MAX_ACTIVE_STREAMS; i++) + if (my_css_save.stream_seeds[i].stream == NULL) + { + IA_CSS_LOG("entered stream into loc=%d", i); + my_css_save.stream_seeds[i].orig_stream = stream; + my_css_save.stream_seeds[i].stream = curr_stream; + my_css_save.stream_seeds[i].num_pipes = num_pipes; + my_css_save.stream_seeds[i].stream_config = *stream_config; + for(j = 0; j < num_pipes; j++) + { + my_css_save.stream_seeds[i].pipe_config[j] = pipes[j]->config; + my_css_save.stream_seeds[i].pipes[j] = pipes[j]; + my_css_save.stream_seeds[i].orig_pipes[j] = &pipes[j]; + } + break; + } +#else + if (err == IA_CSS_SUCCESS) { + err = ia_css_save_stream(curr_stream); +#endif + } else { + ia_css_stream_destroy(curr_stream); + } +#ifndef ISP2401 + IA_CSS_LEAVE("return_err=%d mode=%d", err, my_css_save.mode); +#else + IA_CSS_LEAVE("return_err=%d", err); +#endif + return err; +} + +enum ia_css_err +ia_css_stream_destroy(struct ia_css_stream *stream) +{ + int i; + enum ia_css_err err = IA_CSS_SUCCESS; +#ifdef ISP2401 + enum ia_css_err err1 = IA_CSS_SUCCESS; + enum ia_css_err err2 = IA_CSS_SUCCESS; +#endif + + IA_CSS_ENTER_PRIVATE("stream = %p", stream); + if (stream == NULL) { + err = IA_CSS_ERR_INVALID_ARGUMENTS; + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + ia_css_stream_isp_parameters_uninit(stream); + + if ((stream->last_pipe != NULL) && + ia_css_pipeline_is_mapped(stream->last_pipe->pipe_num)) { +#if defined(USE_INPUT_SYSTEM_VERSION_2401) + for (i = 0; i < stream->num_pipes; i++) { + struct ia_css_pipe *entry = stream->pipes[i]; + unsigned int sp_thread_id; + struct sh_css_sp_pipeline_terminal *sp_pipeline_input_terminal; + + assert(entry != NULL); + if (entry != NULL) { + /* get the SP thread id */ + if (ia_css_pipeline_get_sp_thread_id( + ia_css_pipe_get_pipe_num(entry), &sp_thread_id) != true) + return IA_CSS_ERR_INTERNAL_ERROR; + /* get the target input terminal */ + sp_pipeline_input_terminal = + &(sh_css_sp_group.pipe_io[sp_thread_id].input); + + for (i = 0; i < IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH; i++) { + ia_css_isys_stream_h isys_stream = + &(sp_pipeline_input_terminal->context.virtual_input_system_stream[i]); + if (stream->config.isys_config[i].valid && isys_stream->valid) + ia_css_isys_stream_destroy(isys_stream); + } + } + } +#ifndef ISP2401 + if (stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR) { +#else + if (stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR || + stream->config.mode == IA_CSS_INPUT_MODE_TPG || + stream->config.mode == IA_CSS_INPUT_MODE_PRBS) { +#endif + for (i = 0; i < stream->num_pipes; i++) { + struct ia_css_pipe *entry = stream->pipes[i]; + /* free any mipi frames that are remaining: + * some test stream create-destroy cycles do not generate output frames + * and the mipi buffer is not freed in the deque function + */ + if (entry != NULL) + free_mipi_frames(entry); + } + } + stream_unregister_with_csi_rx(stream); +#endif + + for (i = 0; i < stream->num_pipes; i++) { + struct ia_css_pipe *curr_pipe = stream->pipes[i]; + assert(curr_pipe != NULL); + ia_css_pipe_map_queue(curr_pipe, false); + } + + err = map_sp_threads(stream, false); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + + /* remove references from pipes to stream */ + for (i = 0; i < stream->num_pipes; i++) { + struct ia_css_pipe *entry = stream->pipes[i]; + assert(entry != NULL); + if (entry != NULL) { + /* clear reference to stream */ + entry->stream = NULL; + /* check internal copy pipe */ + if (entry->mode == IA_CSS_PIPE_ID_PREVIEW && + entry->pipe_settings.preview.copy_pipe) { + IA_CSS_LOG("clearing stream on internal preview copy pipe"); + entry->pipe_settings.preview.copy_pipe->stream = NULL; + } + if (entry->mode == IA_CSS_PIPE_ID_VIDEO && + entry->pipe_settings.video.copy_pipe) { + IA_CSS_LOG("clearing stream on internal video copy pipe"); + entry->pipe_settings.video.copy_pipe->stream = NULL; + } + err = sh_css_pipe_unload_binaries(entry); + } + } + /* free associated memory of stream struct */ + sh_css_free(stream->pipes); + stream->pipes = NULL; + stream->num_pipes = 0; +#ifndef ISP2401 + /* working mode: take out of the seed list */ + if (my_css_save.mode == sh_css_mode_working) + for(i=0;iinfo; + return IA_CSS_SUCCESS; +} + +/* + * Rebuild a stream, including allocating structs, setting configuration and + * building the required pipes. + * The data is taken from the css_save struct updated upon stream creation. + * The stream handle is used to identify the correct entry in the css_save struct + */ +enum ia_css_err +ia_css_stream_load(struct ia_css_stream *stream) +{ +#ifndef ISP2401 + int i; + enum ia_css_err err; + assert(stream != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_load() enter, \n"); + for(i=0;ilast_pipe == NULL)) { + IA_CSS_LEAVE_ERR(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + IA_CSS_LOG("starting %d", stream->last_pipe->mode); + + sh_css_sp_set_disable_continuous_viewfinder(stream->disable_cont_vf); + + /* Create host side pipeline. */ + err = create_host_pipeline(stream); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR(err); + return err; + } + +#if !defined(HAS_NO_INPUT_SYSTEM) +#if defined(USE_INPUT_SYSTEM_VERSION_2401) + if((stream->config.mode == IA_CSS_INPUT_MODE_SENSOR) || + (stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR)) + stream_register_with_csi_rx(stream); +#endif +#endif + +#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2) + /* Initialize mipi size checks */ + if (stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR) + { + unsigned int idx; + unsigned int port = (unsigned int) (stream->config.source.port.port) ; + + for (idx = 0; idx < IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT; idx++) { + sh_css_sp_group.config.mipi_sizes_for_check[port][idx] = sh_css_get_mipi_sizes_for_check(port, idx); + } + } +#endif + +#if !defined(HAS_NO_INPUT_SYSTEM) + if (stream->config.mode != IA_CSS_INPUT_MODE_MEMORY) { + err = sh_css_config_input_network(stream); + if (err != IA_CSS_SUCCESS) + return err; + } +#endif /* !HAS_NO_INPUT_SYSTEM */ + + err = sh_css_pipe_start(stream); + IA_CSS_LEAVE_ERR(err); + return err; +} + +enum ia_css_err +ia_css_stream_stop(struct ia_css_stream *stream) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_stop() enter/exit\n"); + assert(stream != NULL); + assert(stream->last_pipe != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_stop: stopping %d\n", + stream->last_pipe->mode); + +#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2) + /* De-initialize mipi size checks */ + if (stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR) + { + unsigned int idx; + unsigned int port = (unsigned int) (stream->config.source.port.port) ; + + for (idx = 0; idx < IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT; idx++) { + sh_css_sp_group.config.mipi_sizes_for_check[port][idx] = 0; + } + } +#endif +#ifndef ISP2401 + err = ia_css_pipeline_request_stop(&stream->last_pipe->pipeline); +#else + + err = sh_css_pipes_stop(stream); +#endif + if (err != IA_CSS_SUCCESS) + return err; + + /* Ideally, unmapping should happen after pipeline_stop, but current + * semantics do not allow that. */ + /* err = map_sp_threads(stream, false); */ + + return err; +} + +bool +ia_css_stream_has_stopped(struct ia_css_stream *stream) +{ + bool stopped; + assert(stream != NULL); + +#ifndef ISP2401 + stopped = ia_css_pipeline_has_stopped(&stream->last_pipe->pipeline); +#else + stopped = sh_css_pipes_have_stopped(stream); +#endif + + return stopped; +} + +#ifndef ISP2401 +/* + * Destroy the stream and all the pipes related to it. + * The stream handle is used to identify the correct entry in the css_save struct + */ +enum ia_css_err +ia_css_stream_unload(struct ia_css_stream *stream) +{ + int i; + assert(stream != NULL); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_stream_unload() enter, \n"); + /* some checks */ + assert (stream != NULL); + for(i=0;imode; + else + *pipe_id = IA_CSS_PIPE_ID_COPY; + + return IA_CSS_SUCCESS; +} + +enum ia_css_stream_format +ia_css_stream_get_format(const struct ia_css_stream *stream) +{ + return stream->config.input_config.format; +} + +bool +ia_css_stream_get_two_pixels_per_clock(const struct ia_css_stream *stream) +{ + return (stream->config.pixels_per_clock == 2); +} + +struct ia_css_binary * +ia_css_stream_get_shading_correction_binary(const struct ia_css_stream *stream) +{ + struct ia_css_pipe *pipe; + + assert(stream != NULL); + + pipe = stream->pipes[0]; + + if (stream->num_pipes == 2) { + assert(stream->pipes[1] != NULL); + if (stream->pipes[1]->config.mode == IA_CSS_PIPE_MODE_VIDEO || + stream->pipes[1]->config.mode == IA_CSS_PIPE_MODE_PREVIEW) + pipe = stream->pipes[1]; + } + + return ia_css_pipe_get_shading_correction_binary(pipe); +} + +struct ia_css_binary * +ia_css_stream_get_dvs_binary(const struct ia_css_stream *stream) +{ + int i; + struct ia_css_pipe *video_pipe = NULL; + + /* First we find the video pipe */ + for (i=0; inum_pipes; i++) { + struct ia_css_pipe *pipe = stream->pipes[i]; + if (pipe->config.mode == IA_CSS_PIPE_MODE_VIDEO) { + video_pipe = pipe; + break; + } + } + if (video_pipe) + return &video_pipe->pipe_settings.video.video_binary; + return NULL; +} + +struct ia_css_binary * +ia_css_stream_get_3a_binary(const struct ia_css_stream *stream) +{ + struct ia_css_pipe *pipe; + struct ia_css_binary *s3a_binary = NULL; + + assert(stream != NULL); + + pipe = stream->pipes[0]; + + if (stream->num_pipes == 2) { + assert(stream->pipes[1] != NULL); + if (stream->pipes[1]->config.mode == IA_CSS_PIPE_MODE_VIDEO || + stream->pipes[1]->config.mode == IA_CSS_PIPE_MODE_PREVIEW) + pipe = stream->pipes[1]; + } + + s3a_binary = ia_css_pipe_get_s3a_binary(pipe); + + return s3a_binary; +} + + +enum ia_css_err +ia_css_stream_set_output_padded_width(struct ia_css_stream *stream, unsigned int output_padded_width) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + struct ia_css_pipe *pipe; + + assert(stream != NULL); + + pipe = stream->last_pipe; + + assert(pipe != NULL); + + /* set the config also just in case (redundant info? why do we save config in pipe?) */ + pipe->config.output_info[IA_CSS_PIPE_OUTPUT_STAGE_0].padded_width = output_padded_width; + pipe->output_info[IA_CSS_PIPE_OUTPUT_STAGE_0].padded_width = output_padded_width; + + return err; +} + +static struct ia_css_binary * +ia_css_pipe_get_shading_correction_binary(const struct ia_css_pipe *pipe) +{ + struct ia_css_binary *binary = NULL; + + assert(pipe != NULL); + + switch (pipe->config.mode) { + case IA_CSS_PIPE_MODE_PREVIEW: + binary = (struct ia_css_binary *)&pipe->pipe_settings.preview.preview_binary; + break; + case IA_CSS_PIPE_MODE_VIDEO: + binary = (struct ia_css_binary *)&pipe->pipe_settings.video.video_binary; + break; + case IA_CSS_PIPE_MODE_CAPTURE: + if (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_PRIMARY) { + unsigned int i; + + for (i = 0; i < pipe->pipe_settings.capture.num_primary_stage; i++) { + if (pipe->pipe_settings.capture.primary_binary[i].info->sp.enable.sc) { + binary = (struct ia_css_binary *)&pipe->pipe_settings.capture.primary_binary[i]; + break; + } + } + } + else if (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_BAYER) + binary = (struct ia_css_binary *)&pipe->pipe_settings.capture.pre_isp_binary; + else if (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_ADVANCED || + pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_LOW_LIGHT) { + if (pipe->config.isp_pipe_version == IA_CSS_PIPE_VERSION_1) + binary = (struct ia_css_binary *)&pipe->pipe_settings.capture.pre_isp_binary; + else if (pipe->config.isp_pipe_version == IA_CSS_PIPE_VERSION_2_2) + binary = (struct ia_css_binary *)&pipe->pipe_settings.capture.post_isp_binary; + } + break; + default: + break; + } + + if (binary && binary->info->sp.enable.sc) + return binary; + + return NULL; +} + +static struct ia_css_binary * +ia_css_pipe_get_s3a_binary(const struct ia_css_pipe *pipe) +{ + struct ia_css_binary *binary = NULL; + + assert(pipe != NULL); + + switch (pipe->config.mode) { + case IA_CSS_PIPE_MODE_PREVIEW: + binary = (struct ia_css_binary*)&pipe->pipe_settings.preview.preview_binary; + break; + case IA_CSS_PIPE_MODE_VIDEO: + binary = (struct ia_css_binary*)&pipe->pipe_settings.video.video_binary; + break; + case IA_CSS_PIPE_MODE_CAPTURE: + if (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_PRIMARY) { + unsigned int i; + for (i = 0; i < pipe->pipe_settings.capture.num_primary_stage; i++) { + if (pipe->pipe_settings.capture.primary_binary[i].info->sp.enable.s3a) { + binary = (struct ia_css_binary *)&pipe->pipe_settings.capture.primary_binary[i]; + break; + } + } + } + else if (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_BAYER) + binary = (struct ia_css_binary *)&pipe->pipe_settings.capture.pre_isp_binary; + else if (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_ADVANCED || + pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_LOW_LIGHT) { + if (pipe->config.isp_pipe_version == IA_CSS_PIPE_VERSION_1) + binary = (struct ia_css_binary *)&pipe->pipe_settings.capture.pre_isp_binary; + else if (pipe->config.isp_pipe_version == IA_CSS_PIPE_VERSION_2_2) + binary = (struct ia_css_binary *)&pipe->pipe_settings.capture.post_isp_binary; + else + assert(0); + } + break; + default: + break; + } + + if (binary && !binary->info->sp.enable.s3a) + binary = NULL; + + return binary; +} + +static struct ia_css_binary * +ia_css_pipe_get_sdis_binary(const struct ia_css_pipe *pipe) +{ + struct ia_css_binary *binary = NULL; + + assert(pipe != NULL); + + switch (pipe->config.mode) { + case IA_CSS_PIPE_MODE_VIDEO: + binary = (struct ia_css_binary*)&pipe->pipe_settings.video.video_binary; + break; + default: + break; + } + + if (binary && !binary->info->sp.enable.dis) + binary = NULL; + + return binary; +} + +struct ia_css_pipeline * +ia_css_pipe_get_pipeline(const struct ia_css_pipe *pipe) +{ + assert(pipe != NULL); + + return (struct ia_css_pipeline*)&pipe->pipeline; +} + +unsigned int +ia_css_pipe_get_pipe_num(const struct ia_css_pipe *pipe) +{ + assert(pipe != NULL); + + /* KW was not sure this function was not returning a value + that was out of range; so added an assert, and, for the + case when asserts are not enabled, clip to the largest + value; pipe_num is unsigned so the value cannot be too small + */ + assert(pipe->pipe_num < IA_CSS_PIPELINE_NUM_MAX); + + if (pipe->pipe_num >= IA_CSS_PIPELINE_NUM_MAX) + return (IA_CSS_PIPELINE_NUM_MAX - 1); + + return pipe->pipe_num; +} + + +unsigned int +ia_css_pipe_get_isp_pipe_version(const struct ia_css_pipe *pipe) +{ + assert(pipe != NULL); + + return (unsigned int)pipe->config.isp_pipe_version; +} + +#if defined(HAS_BL) +#define BL_START_TIMEOUT_US 30000000 +static enum ia_css_err +ia_css_start_bl(void) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + unsigned long timeout; + + IA_CSS_ENTER(""); + sh_css_start_bl(); + /* waiting for the Bootloader to complete execution */ + timeout = BL_START_TIMEOUT_US; + while((ia_css_blctrl_get_state() == BOOTLOADER_BUSY) && timeout) { + timeout--; + hrt_sleep(); + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, + "Bootloader state %d\n", ia_css_blctrl_get_state()); + if (timeout == 0) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "Bootloader Execution Timeout\n"); + err = IA_CSS_ERR_INTERNAL_ERROR; + } + if (ia_css_blctrl_get_state() != BOOTLOADER_OK) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "Bootloader Execution Failed\n"); + err = IA_CSS_ERR_INTERNAL_ERROR; + } + IA_CSS_LEAVE_ERR(err); + return err; +} +#endif + +#define SP_START_TIMEOUT_US 30000000 + +#if defined(HAS_SEC_SP) + +static enum ia_css_err +sh_css_start_sp1(void) +{ + + unsigned long timeout; + + IA_CSS_ENTER_PRIVATE("void"); + sh_css_sp1_start(); + /* waiting for the SP is completely started */ + timeout = SP_START_TIMEOUT_US; + while((ia_css_spctrl_get_state(SP1_ID) != IA_CSS_SP_SW_INITIALIZED) && timeout) { + timeout--; + hrt_sleep(); + } + if (timeout == 0) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INTERNAL_ERROR); + return IA_CSS_ERR_INTERNAL_ERROR; + } + sh_css_write_host2sp1_command(host2sp_cmd_ready); + + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + return IA_CSS_SUCCESS; +} +#endif + +enum ia_css_err +ia_css_start_sp(void) +{ + unsigned long timeout; + enum ia_css_err err = IA_CSS_SUCCESS; + + IA_CSS_ENTER(""); +#if defined(HAS_BL) + /* Starting bootloader before Sp0 and Sp1 + * and not exposing CSS API */ + err = ia_css_start_bl(); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE("Bootloader fails"); + return err; + } +#endif + sh_css_sp_start_isp(); + + /* waiting for the SP is completely started */ + timeout = SP_START_TIMEOUT_US; + while((ia_css_spctrl_get_state(SP0_ID) != IA_CSS_SP_SW_INITIALIZED) && timeout) { + timeout--; + hrt_sleep(); + } + if (timeout == 0) { + IA_CSS_ERROR("timeout during SP initialization"); + return IA_CSS_ERR_INTERNAL_ERROR; + } + + /* Workaround, in order to run two streams in parallel. See TASK 4271*/ + /* TODO: Fix this. */ + + sh_css_init_host_sp_control_vars(); + + /* buffers should be initialized only when sp is started */ + /* AM: At the moment it will be done only when there is no stream active. */ + + sh_css_setup_queues(); + ia_css_bufq_dump_queue_info(); + +#if defined(HAS_SEC_SP) + /* Start the SP1 Core */ + err = sh_css_start_sp1(); +#endif /* HAS_SEC_SP */ + +#ifdef ISP2401 + if (ia_css_is_system_mode_suspend_or_resume() == false) { /* skip in suspend/resume flow */ + ia_css_set_system_mode(IA_CSS_SYS_MODE_WORKING); + } +#endif + IA_CSS_LEAVE_ERR(err); + return err; +} + +/** + * Time to wait SP for termincate. Only condition when this can happen + * is a fatal hw failure, but we must be able to detect this and emit + * a proper error trace. + */ +#define SP_SHUTDOWN_TIMEOUT_US 200000 + +#if defined(HAS_SEC_SP) + +static enum ia_css_err +sh_css_stop_sp1(void) +{ + unsigned long timeout; + + IA_CSS_ENTER_PRIVATE("void"); + + /* For now, stop whole SP1 */ + sh_css_write_host2sp1_command(host2sp_cmd_terminate); + sh_css_sp1_set_sp1_running(false); + + timeout = SP_SHUTDOWN_TIMEOUT_US; + while ((ia_css_spctrl_get_state(SP1_ID)!= IA_CSS_SP_SW_TERMINATED) && timeout) { + timeout--; + hrt_sleep(); + } + if (timeout == 0) { + IA_CSS_WARNING("SP1 is not terminated"); + } else { + timeout = SP_SHUTDOWN_TIMEOUT_US; + while (!ia_css_spctrl_is_idle(SP1_ID) && 0 != timeout) { + timeout--; + hrt_sleep(); + } + if (0 == timeout) { + IA_CSS_WARNING("SP1 is not idle"); + } + } + + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + return IA_CSS_SUCCESS; +} +#endif + +enum ia_css_err +ia_css_stop_sp(void) +{ + unsigned long timeout; + enum ia_css_err err = IA_CSS_SUCCESS; + + IA_CSS_ENTER("void"); + + if (!sh_css_sp_is_running()) { + err = IA_CSS_ERR_INVALID_ARGUMENTS; + IA_CSS_LEAVE("SP already stopped : return_err=%d", err); + + /* Return an error - stop SP should not have been called by driver */ + return err; + } + + /* For now, stop whole SP */ +#ifndef ISP2401 + sh_css_write_host2sp_command(host2sp_cmd_terminate); +#else + if (!sh_css_write_host2sp_command(host2sp_cmd_terminate)) { + IA_CSS_ERROR("Call to 'sh-css_write_host2sp_command()' failed"); + ia_css_debug_dump_sp_sw_debug_info(); + ia_css_debug_dump_debug_info(NULL); + } +#endif + sh_css_sp_set_sp_running(false); + + timeout = SP_SHUTDOWN_TIMEOUT_US; + while (!ia_css_spctrl_is_idle(SP0_ID) && timeout) { + timeout--; + hrt_sleep(); + } + if ((ia_css_spctrl_get_state(SP0_ID) != IA_CSS_SP_SW_TERMINATED)) + IA_CSS_WARNING("SP has not terminated (SW)"); + + if (timeout == 0) { + IA_CSS_WARNING("SP is not idle"); + ia_css_debug_dump_sp_sw_debug_info(); + } + timeout = SP_SHUTDOWN_TIMEOUT_US; + while (!isp_ctrl_getbit(ISP0_ID, ISP_SC_REG, ISP_IDLE_BIT) && timeout) { + timeout--; + hrt_sleep(); + } + if (timeout == 0) { + IA_CSS_WARNING("ISP is not idle"); + ia_css_debug_dump_sp_sw_debug_info(); + } + + sh_css_hmm_buffer_record_uninit(); + +#ifndef ISP2401 + /* clear pending param sets from refcount */ + sh_css_param_clear_param_sets(); +#else + if (ia_css_is_system_mode_suspend_or_resume() == false) { /* skip in suspend/resume flow */ + /* clear pending param sets from refcount */ + sh_css_param_clear_param_sets(); + ia_css_set_system_mode(IA_CSS_SYS_MODE_INIT); /* System is initialized but not 'running' */ + } +#endif + +#if defined(HAS_SEC_SP) + /* Stop SP1 Core */ + sh_css_stop_sp1(); +#endif /* HAS_SEC_SP */ + + IA_CSS_LEAVE_ERR(err); + return err; +} + +enum ia_css_err +ia_css_update_continuous_frames(struct ia_css_stream *stream) +{ + struct ia_css_pipe *pipe; + unsigned int i; + + ia_css_debug_dtrace( + IA_CSS_DEBUG_TRACE, + "sh_css_update_continuous_frames() enter:\n"); + + if (stream == NULL) { + ia_css_debug_dtrace( + IA_CSS_DEBUG_TRACE, + "sh_css_update_continuous_frames() leave: invalid stream, return_void\n"); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + pipe = stream->continuous_pipe; + + for (i = stream->config.init_num_cont_raw_buf; + i < stream->config.target_num_cont_raw_buf; i++) { + sh_css_update_host2sp_offline_frame(i, + pipe->continuous_frames[i], pipe->cont_md_buffers[i]); + } + sh_css_update_host2sp_cont_num_raw_frames + (stream->config.target_num_cont_raw_buf, true); + ia_css_debug_dtrace( + IA_CSS_DEBUG_TRACE, + "sh_css_update_continuous_frames() leave: return_void\n"); + + return IA_CSS_SUCCESS; +} + +void ia_css_pipe_map_queue(struct ia_css_pipe *pipe, bool map) +{ + unsigned int thread_id; + enum ia_css_pipe_id pipe_id; + unsigned int pipe_num; + bool need_input_queue; + + IA_CSS_ENTER(""); + assert(pipe != NULL); + + pipe_id = pipe->mode; + pipe_num = pipe->pipe_num; + + ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id); + +#if defined(HAS_NO_INPUT_SYSTEM) || defined(USE_INPUT_SYSTEM_VERSION_2401) + need_input_queue = true; +#else + need_input_queue = pipe->stream->config.mode == IA_CSS_INPUT_MODE_MEMORY; +#endif + + /* map required buffer queues to resources */ + /* TODO: to be improved */ + if (pipe->mode == IA_CSS_PIPE_ID_PREVIEW) { + if (need_input_queue) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_INPUT_FRAME, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_OUTPUT_FRAME, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_PARAMETER_SET, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_PER_FRAME_PARAMETER_SET, map); +#if defined SH_CSS_ENABLE_METADATA + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_METADATA, map); +#endif + if (pipe->pipe_settings.preview.preview_binary.info && + pipe->pipe_settings.preview.preview_binary.info->sp.enable.s3a) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_3A_STATISTICS, map); + } else if (pipe->mode == IA_CSS_PIPE_ID_CAPTURE) { + unsigned int i; + + if (need_input_queue) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_INPUT_FRAME, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_OUTPUT_FRAME, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_PARAMETER_SET, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_PER_FRAME_PARAMETER_SET, map); +#if defined SH_CSS_ENABLE_METADATA + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_METADATA, map); +#endif + if (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_PRIMARY) { + for (i = 0; i < pipe->pipe_settings.capture.num_primary_stage; i++) { + if (pipe->pipe_settings.capture.primary_binary[i].info && + pipe->pipe_settings.capture.primary_binary[i].info->sp.enable.s3a) { + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_3A_STATISTICS, map); + break; + } + } + } else if (pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_ADVANCED || + pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_LOW_LIGHT || + pipe->config.default_capture_config.mode == IA_CSS_CAPTURE_MODE_BAYER) { + if (pipe->pipe_settings.capture.pre_isp_binary.info && + pipe->pipe_settings.capture.pre_isp_binary.info->sp.enable.s3a) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_3A_STATISTICS, map); + } + } else if (pipe->mode == IA_CSS_PIPE_ID_VIDEO) { + if (need_input_queue) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_INPUT_FRAME, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_OUTPUT_FRAME, map); + if (pipe->enable_viewfinder[IA_CSS_PIPE_OUTPUT_STAGE_0]) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_PARAMETER_SET, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_PER_FRAME_PARAMETER_SET, map); +#if defined SH_CSS_ENABLE_METADATA + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_METADATA, map); +#endif + if (pipe->pipe_settings.video.video_binary.info && + pipe->pipe_settings.video.video_binary.info->sp.enable.s3a) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_3A_STATISTICS, map); + if (pipe->pipe_settings.video.video_binary.info && + (pipe->pipe_settings.video.video_binary.info->sp.enable.dis + )) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_DIS_STATISTICS, map); + } else if (pipe->mode == IA_CSS_PIPE_ID_COPY) { + if (need_input_queue) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_INPUT_FRAME, map); + if (!pipe->stream->config.continuous) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_OUTPUT_FRAME, map); +#if defined SH_CSS_ENABLE_METADATA + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_METADATA, map); +#endif + } else if (pipe->mode == IA_CSS_PIPE_ID_ACC) { + if (need_input_queue) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_INPUT_FRAME, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_OUTPUT_FRAME, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_PARAMETER_SET, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_PER_FRAME_PARAMETER_SET, map); +#if defined SH_CSS_ENABLE_METADATA + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_METADATA, map); +#endif + } else if (pipe->mode == IA_CSS_PIPE_ID_YUVPP) { + unsigned int idx; + for (idx = 0; idx < IA_CSS_PIPE_MAX_OUTPUT_STAGE; idx++) { + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_OUTPUT_FRAME + idx, map); + if (pipe->enable_viewfinder[idx]) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_VF_OUTPUT_FRAME + idx, map); + } + if (need_input_queue) + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_INPUT_FRAME, map); + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_PARAMETER_SET, map); +#if defined SH_CSS_ENABLE_METADATA + ia_css_queue_map(thread_id, IA_CSS_BUFFER_TYPE_METADATA, map); +#endif + } + IA_CSS_LEAVE(""); +} + +#if CONFIG_ON_FRAME_ENQUEUE() +static enum ia_css_err set_config_on_frame_enqueue(struct ia_css_frame_info *info, struct frame_data_wrapper *frame) +{ + frame->config_on_frame_enqueue.padded_width = 0; + + /* currently we support configuration on frame enqueue only on YUV formats */ + /* on other formats the padded_width is zeroed for no configuration override */ + switch (info->format) { + case IA_CSS_FRAME_FORMAT_YUV420: + case IA_CSS_FRAME_FORMAT_NV12: + if (info->padded_width > info->res.width) + { + frame->config_on_frame_enqueue.padded_width = info->padded_width; + } + else if ((info->padded_width < info->res.width) && (info->padded_width > 0)) + { + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + /* nothing to do if width == padded width or padded width is zeroed (the same) */ + break; + default: + break; + } + + return IA_CSS_SUCCESS; +} +#endif + +enum ia_css_err +ia_css_unlock_raw_frame(struct ia_css_stream *stream, uint32_t exp_id) +{ + enum ia_css_err ret; + + IA_CSS_ENTER(""); + + /* Only continuous streams have a tagger to which we can send the + * unlock message. */ + if (stream == NULL || !stream->config.continuous) { + IA_CSS_ERROR("invalid stream pointer"); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + if (exp_id > IA_CSS_ISYS_MAX_EXPOSURE_ID || + exp_id < IA_CSS_ISYS_MIN_EXPOSURE_ID) { + IA_CSS_ERROR("invalid expsure ID: %d\n", exp_id); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + /* Send the event. Since we verified that the exp_id is valid, + * we can safely assign it to an 8-bit argument here. */ + ret = ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_UNLOCK_RAW_BUFFER, exp_id, 0, 0); + + IA_CSS_LEAVE_ERR(ret); + return ret; +} + +/** @brief Set the state (Enable or Disable) of the Extension stage in the + * given pipe. + */ +enum ia_css_err +ia_css_pipe_set_qos_ext_state(struct ia_css_pipe *pipe, uint32_t fw_handle, bool enable) +{ + unsigned int thread_id; + struct ia_css_pipeline_stage *stage; + enum ia_css_err err = IA_CSS_SUCCESS; + + IA_CSS_ENTER(""); + + /* Parameter Check */ + if (pipe == NULL || pipe->stream == NULL) { + IA_CSS_ERROR("Invalid Pipe."); + err = IA_CSS_ERR_INVALID_ARGUMENTS; + } else if (!(pipe->config.acc_extension)) { + IA_CSS_ERROR("Invalid Pipe(No Extension Firmware)"); + err = IA_CSS_ERR_INVALID_ARGUMENTS; + } else if (!sh_css_sp_is_running()) { + IA_CSS_ERROR("Leaving: queue unavailable."); + err = IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } else { + /* Query the threadid and stage_num for the Extension firmware*/ + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + err = ia_css_pipeline_get_stage_from_fw(&(pipe->pipeline), fw_handle, &stage); + if (err == IA_CSS_SUCCESS) { + /* Set the Extension State;. TODO: Add check for stage firmware.type (QOS)*/ + err = ia_css_bufq_enqueue_psys_event( + (uint8_t) IA_CSS_PSYS_SW_EVENT_STAGE_ENABLE_DISABLE, + (uint8_t) thread_id, + (uint8_t) stage->stage_num, + (enable == true) ? 1 : 0); + if (err == IA_CSS_SUCCESS) { + if(enable) + SH_CSS_QOS_STAGE_ENABLE(&(sh_css_sp_group.pipe[thread_id]),stage->stage_num); + else + SH_CSS_QOS_STAGE_DISABLE(&(sh_css_sp_group.pipe[thread_id]),stage->stage_num); + } + } + } + IA_CSS_LEAVE("err:%d handle:%u enable:%d", err, fw_handle, enable); + return err; +} + +/** @brief Get the state (Enable or Disable) of the Extension stage in the + * given pipe. + */ +enum ia_css_err +ia_css_pipe_get_qos_ext_state(struct ia_css_pipe *pipe, uint32_t fw_handle, bool *enable) +{ + struct ia_css_pipeline_stage *stage; + unsigned int thread_id; + enum ia_css_err err = IA_CSS_SUCCESS; + + IA_CSS_ENTER(""); + + /* Parameter Check */ + if (pipe == NULL || pipe->stream == NULL) { + IA_CSS_ERROR("Invalid Pipe."); + err = IA_CSS_ERR_INVALID_ARGUMENTS; + } else if (!(pipe->config.acc_extension)) { + IA_CSS_ERROR("Invalid Pipe (No Extension Firmware)."); + err = IA_CSS_ERR_INVALID_ARGUMENTS; + } else if (!sh_css_sp_is_running()) { + IA_CSS_ERROR("Leaving: queue unavailable."); + err = IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } else { + /* Query the threadid and stage_num corresponding to the Extension firmware*/ + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + err = ia_css_pipeline_get_stage_from_fw(&pipe->pipeline, fw_handle, &stage); + + if (err == IA_CSS_SUCCESS) { + /* Get the Extension State */ + *enable = (SH_CSS_QOS_STAGE_IS_ENABLED(&(sh_css_sp_group.pipe[thread_id]),stage->stage_num)) ? true : false; + } + } + IA_CSS_LEAVE("err:%d handle:%u enable:%d", err, fw_handle, *enable); + return err; +} + +#ifdef ISP2401 +enum ia_css_err +ia_css_pipe_update_qos_ext_mapped_arg(struct ia_css_pipe *pipe, uint32_t fw_handle, + struct ia_css_isp_param_css_segments *css_seg, struct ia_css_isp_param_isp_segments *isp_seg) +{ +#ifndef HRT_CSIM + unsigned int HIVE_ADDR_sp_group; + static struct sh_css_sp_group sp_group; +#endif + static struct sh_css_sp_stage sp_stage; + static struct sh_css_isp_stage isp_stage; + const struct ia_css_fw_info *fw; + unsigned int thread_id; + struct ia_css_pipeline_stage *stage; + enum ia_css_err err = IA_CSS_SUCCESS; + int stage_num = 0; + enum ia_css_isp_memories mem; + bool enabled; + + IA_CSS_ENTER(""); + + fw = &sh_css_sp_fw; + + /* Parameter Check */ + if (pipe == NULL || pipe->stream == NULL) { + IA_CSS_ERROR("Invalid Pipe."); + err = IA_CSS_ERR_INVALID_ARGUMENTS; + } else if (!(pipe->config.acc_extension)) { + IA_CSS_ERROR("Invalid Pipe (No Extension Firmware)."); + err = IA_CSS_ERR_INVALID_ARGUMENTS; + } else if (!sh_css_sp_is_running()) { + IA_CSS_ERROR("Leaving: queue unavailable."); + err = IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } else { + /* Query the thread_id and stage_num corresponding to the Extension firmware */ + ia_css_pipeline_get_sp_thread_id(ia_css_pipe_get_pipe_num(pipe), &thread_id); + err = ia_css_pipeline_get_stage_from_fw(&(pipe->pipeline), fw_handle, &stage); + if (err == IA_CSS_SUCCESS) { + /* Get the Extension State */ + enabled = (SH_CSS_QOS_STAGE_IS_ENABLED(&(sh_css_sp_group.pipe[thread_id]), stage->stage_num)) ? true : false; + /* Update mapped arg only when extension stage is not enabled */ + if (enabled) { + IA_CSS_ERROR("Leaving: cannot update when stage is enabled."); + err = IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } else { + stage_num = stage->stage_num; + +#ifndef HRT_CSIM + HIVE_ADDR_sp_group = fw->info.sp.group; + sp_dmem_load(SP0_ID, + (unsigned int)sp_address_of(sp_group), + &sp_group, sizeof(struct sh_css_sp_group)); + mmgr_load(sp_group.pipe[thread_id].sp_stage_addr[stage_num], + &sp_stage, sizeof(struct sh_css_sp_stage)); +#else + mmgr_load(sh_css_sp_group.pipe[thread_id].sp_stage_addr[stage_num], + &sp_stage, sizeof(struct sh_css_sp_stage)); +#endif + + mmgr_load(sp_stage.isp_stage_addr, + &isp_stage, sizeof(struct sh_css_isp_stage)); + + for (mem = 0; mem < N_IA_CSS_ISP_MEMORIES; mem++) { + isp_stage.mem_initializers.params[IA_CSS_PARAM_CLASS_PARAM][mem].address = + css_seg->params[IA_CSS_PARAM_CLASS_PARAM][mem].address; + isp_stage.mem_initializers.params[IA_CSS_PARAM_CLASS_PARAM][mem].size = + css_seg->params[IA_CSS_PARAM_CLASS_PARAM][mem].size; + isp_stage.binary_info.mem_initializers.params[IA_CSS_PARAM_CLASS_PARAM][mem].address = + isp_seg->params[IA_CSS_PARAM_CLASS_PARAM][mem].address; + isp_stage.binary_info.mem_initializers.params[IA_CSS_PARAM_CLASS_PARAM][mem].size = + isp_seg->params[IA_CSS_PARAM_CLASS_PARAM][mem].size; + } + + mmgr_store(sp_stage.isp_stage_addr, + &isp_stage, sizeof(struct sh_css_isp_stage)); + } + } + } + IA_CSS_LEAVE("err:%d handle:%u", err, fw_handle); + return err; +} + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 +static enum ia_css_err +aspect_ratio_crop_init(struct ia_css_stream *curr_stream, + struct ia_css_pipe *pipes[], + bool *do_crop_status) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + int i; + struct ia_css_pipe *curr_pipe; + uint32_t pipe_mask = 0; + + if ((curr_stream == NULL) || + (curr_stream->num_pipes == 0) || + (pipes == NULL) || + (do_crop_status == NULL)) { + err = IA_CSS_ERR_INVALID_ARGUMENTS; + IA_CSS_LEAVE_ERR(err); + return err; + } + + for (i = 0; i < curr_stream->num_pipes; i++) { + curr_pipe = pipes[i]; + pipe_mask |= (1 << curr_pipe->config.mode); + } + + *do_crop_status = + (((pipe_mask & (1 << IA_CSS_PIPE_MODE_PREVIEW)) || + (pipe_mask & (1 << IA_CSS_PIPE_MODE_VIDEO))) && + (pipe_mask & (1 << IA_CSS_PIPE_MODE_CAPTURE)) && + curr_stream->config.continuous); + return IA_CSS_SUCCESS; +} + +static bool +aspect_ratio_crop_check(bool enabled, struct ia_css_pipe *curr_pipe) +{ + bool status = false; + + if ((curr_pipe != NULL) && enabled) { + if ((curr_pipe->config.mode == IA_CSS_PIPE_MODE_PREVIEW) || + (curr_pipe->config.mode == IA_CSS_PIPE_MODE_VIDEO) || + (curr_pipe->config.mode == IA_CSS_PIPE_MODE_CAPTURE)) + status = true; + } + + return status; +} + +static enum ia_css_err +aspect_ratio_crop(struct ia_css_pipe *curr_pipe, + struct ia_css_resolution *effective_res) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_resolution crop_res; + struct ia_css_resolution *in_res = NULL; + struct ia_css_resolution *out_res = NULL; + bool use_bds_output_info = false; + bool use_vf_pp_in_res = false; + bool use_capt_pp_in_res = false; + + if ((curr_pipe == NULL) || + (effective_res == NULL)) { + err = IA_CSS_ERR_INVALID_ARGUMENTS; + IA_CSS_LEAVE_ERR(err); + return err; + } + + if ((curr_pipe->config.mode != IA_CSS_PIPE_MODE_PREVIEW) && + (curr_pipe->config.mode != IA_CSS_PIPE_MODE_VIDEO) && + (curr_pipe->config.mode != IA_CSS_PIPE_MODE_CAPTURE)) { + err = IA_CSS_ERR_INVALID_ARGUMENTS; + IA_CSS_LEAVE_ERR(err); + return err; + } + + use_bds_output_info = + ((curr_pipe->bds_output_info.res.width != 0) && + (curr_pipe->bds_output_info.res.height != 0)); + + use_vf_pp_in_res = + ((curr_pipe->config.vf_pp_in_res.width != 0) && + (curr_pipe->config.vf_pp_in_res.height != 0)); + + use_capt_pp_in_res = + ((curr_pipe->config.capt_pp_in_res.width != 0) && + (curr_pipe->config.capt_pp_in_res.height != 0)); + + in_res = &curr_pipe->stream->config.input_config.effective_res; + out_res = &curr_pipe->output_info[0].res; + + switch (curr_pipe->config.mode) { + case IA_CSS_PIPE_MODE_PREVIEW: + if (use_bds_output_info) + out_res = &curr_pipe->bds_output_info.res; + else if (use_vf_pp_in_res) + out_res = &curr_pipe->config.vf_pp_in_res; + break; + case IA_CSS_PIPE_MODE_VIDEO: + if (use_bds_output_info) + out_res = &curr_pipe->bds_output_info.res; + break; + case IA_CSS_PIPE_MODE_CAPTURE: + if (use_capt_pp_in_res) + out_res = &curr_pipe->config.capt_pp_in_res; + break; + case IA_CSS_PIPE_MODE_ACC: + case IA_CSS_PIPE_MODE_COPY: + case IA_CSS_PIPE_MODE_YUVPP: + default: + IA_CSS_ERROR("aspect ratio cropping invalid args: mode[%d]\n", + curr_pipe->config.mode); + assert(0); + break; + } + + err = ia_css_frame_find_crop_resolution(in_res, out_res, &crop_res); + if (err == IA_CSS_SUCCESS) { + *effective_res = crop_res; + } else { + /* in case of error fallback to default + * effective resolution from driver. */ + IA_CSS_LOG("ia_css_frame_find_crop_resolution() failed with err(%d)", err); + } + return err; +} +#endif + +#endif +static void +sh_css_hmm_buffer_record_init(void) +{ + int i; + +#ifndef ISP2401 + for (i = 0; i < MAX_HMM_BUFFER_NUM; i++) { + sh_css_hmm_buffer_record_reset(&hmm_buffer_record[i]); +#else + if (ia_css_is_system_mode_suspend_or_resume() == false) { /* skip in suspend/resume flow */ + for (i = 0; i < MAX_HMM_BUFFER_NUM; i++) { + sh_css_hmm_buffer_record_reset(&hmm_buffer_record[i]); + } +#endif + } +} + +static void +sh_css_hmm_buffer_record_uninit(void) +{ + int i; + struct sh_css_hmm_buffer_record *buffer_record = NULL; + +#ifndef ISP2401 + buffer_record = &hmm_buffer_record[0]; + for (i = 0; i < MAX_HMM_BUFFER_NUM; i++) { + if (buffer_record->in_use) { + if (buffer_record->h_vbuf != NULL) + ia_css_rmgr_rel_vbuf(hmm_buffer_pool, &buffer_record->h_vbuf); + sh_css_hmm_buffer_record_reset(buffer_record); +#else + if (ia_css_is_system_mode_suspend_or_resume() == false) { /* skip in suspend/resume flow */ + buffer_record = &hmm_buffer_record[0]; + for (i = 0; i < MAX_HMM_BUFFER_NUM; i++) { + if (buffer_record->in_use) { + if (buffer_record->h_vbuf != NULL) + ia_css_rmgr_rel_vbuf(hmm_buffer_pool, &buffer_record->h_vbuf); + sh_css_hmm_buffer_record_reset(buffer_record); + } + buffer_record++; +#endif + } +#ifndef ISP2401 + buffer_record++; +#endif + } +} + +static void +sh_css_hmm_buffer_record_reset(struct sh_css_hmm_buffer_record *buffer_record) +{ + assert(buffer_record != NULL); + buffer_record->in_use = false; + buffer_record->type = IA_CSS_BUFFER_TYPE_INVALID; + buffer_record->h_vbuf = NULL; + buffer_record->kernel_ptr = 0; +} + +#ifndef ISP2401 +static bool +sh_css_hmm_buffer_record_acquire(struct ia_css_rmgr_vbuf_handle *h_vbuf, +#else +static struct sh_css_hmm_buffer_record +*sh_css_hmm_buffer_record_acquire(struct ia_css_rmgr_vbuf_handle *h_vbuf, +#endif + enum ia_css_buffer_type type, + hrt_address kernel_ptr) +{ + int i; + struct sh_css_hmm_buffer_record *buffer_record = NULL; +#ifndef ISP2401 + bool found_record = false; +#else + struct sh_css_hmm_buffer_record *out_buffer_record = NULL; +#endif + + assert(h_vbuf != NULL); + assert((type > IA_CSS_BUFFER_TYPE_INVALID) && (type < IA_CSS_NUM_DYNAMIC_BUFFER_TYPE)); + assert(kernel_ptr != 0); + + buffer_record = &hmm_buffer_record[0]; + for (i = 0; i < MAX_HMM_BUFFER_NUM; i++) { + if (buffer_record->in_use == false) { + buffer_record->in_use = true; + buffer_record->type = type; + buffer_record->h_vbuf = h_vbuf; + buffer_record->kernel_ptr = kernel_ptr; +#ifndef ISP2401 + found_record = true; +#else + out_buffer_record = buffer_record; +#endif + break; + } + buffer_record++; + } + +#ifndef ISP2401 + return found_record; +#else + return out_buffer_record; +#endif +} + +static struct sh_css_hmm_buffer_record +*sh_css_hmm_buffer_record_validate(hrt_vaddress ddr_buffer_addr, + enum ia_css_buffer_type type) +{ + int i; + struct sh_css_hmm_buffer_record *buffer_record = NULL; + bool found_record = false; + + buffer_record = &hmm_buffer_record[0]; + for (i = 0; i < MAX_HMM_BUFFER_NUM; i++) { + if ((buffer_record->in_use == true) && + (buffer_record->type == type) && + (buffer_record->h_vbuf != NULL) && + (buffer_record->h_vbuf->vptr == ddr_buffer_addr)) { + found_record = true; + break; + } + buffer_record++; + } + + if (found_record == true) + return buffer_record; + else + return NULL; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_defs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_defs.h new file mode 100644 index 0000000000000000000000000000000000000000..b24c404c9eed1b5e6ca364fdd4fe9c2a09d827c7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_defs.h @@ -0,0 +1,413 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_DEFS_H_ +#define _SH_CSS_DEFS_H_ + +#if !defined(__SP1) +#include "isp.h" +#else +#include "system_local.h" /* to get IS_ISP_2500_SYSTEM for SP1*/ +#endif +/*#include "vamem.h"*/ /* Cannot include for VAMEM properties this file is visible on ISP -> pipeline generator */ + +#include "math_support.h" /* max(), min, etc etc */ + +/* ID's for refcount */ +#define IA_CSS_REFCOUNT_PARAM_SET_POOL 0xCAFE0001 +#define IA_CSS_REFCOUNT_PARAM_BUFFER 0xCAFE0002 + +/* Digital Image Stabilization */ +#define SH_CSS_DIS_DECI_FACTOR_LOG2 6 + +/* UV offset: 1:uv=-128...127, 0:uv=0...255 */ +#define SH_CSS_UV_OFFSET_IS_0 0 + +/* Bits of bayer is adjusted as 13 in ISP */ +#define SH_CSS_BAYER_BITS 13 + +/* Max value of bayer data (unsigned 13bit in ISP) */ +#define SH_CSS_BAYER_MAXVAL ((1U << SH_CSS_BAYER_BITS) - 1) + +/* Bits of yuv in ISP */ +#define SH_CSS_ISP_YUV_BITS 8 + +#define SH_CSS_DP_GAIN_SHIFT 5 +#define SH_CSS_BNR_GAIN_SHIFT 13 +#define SH_CSS_YNR_GAIN_SHIFT 13 +#define SH_CSS_AE_YCOEF_SHIFT 13 +#define SH_CSS_AF_FIR_SHIFT 13 +#define SH_CSS_YEE_DETAIL_GAIN_SHIFT 8 /* [u5.8] */ +#define SH_CSS_YEE_SCALE_SHIFT 8 +#define SH_CSS_TNR_COEF_SHIFT 13 +#define SH_CSS_MACC_COEF_SHIFT 11 /* [s2.11] for ISP1 */ +#define SH_CSS_MACC2_COEF_SHIFT 13 /* [s[exp].[13-exp]] for ISP2 */ +#define SH_CSS_DIS_COEF_SHIFT 13 + +/* enumeration of the bayer downscale factors. When a binary supports multiple + * factors, the OR of these defines is used to build the mask of supported + * factors. The BDS factor is used in pre-processor expressions so we cannot + * use an enum here. */ +#define SH_CSS_BDS_FACTOR_1_00 (0) +#define SH_CSS_BDS_FACTOR_1_25 (1) +#define SH_CSS_BDS_FACTOR_1_50 (2) +#define SH_CSS_BDS_FACTOR_2_00 (3) +#define SH_CSS_BDS_FACTOR_2_25 (4) +#define SH_CSS_BDS_FACTOR_2_50 (5) +#define SH_CSS_BDS_FACTOR_3_00 (6) +#define SH_CSS_BDS_FACTOR_4_00 (7) +#define SH_CSS_BDS_FACTOR_4_50 (8) +#define SH_CSS_BDS_FACTOR_5_00 (9) +#define SH_CSS_BDS_FACTOR_6_00 (10) +#define SH_CSS_BDS_FACTOR_8_00 (11) +#define NUM_BDS_FACTORS (12) + +#define PACK_BDS_FACTOR(factor) (1<<(factor)) + +/* Following macros should match with the type enum ia_css_pipe_version in + * ia_css_pipe_public.h. The reason to add these macros is that enum type + * will be evaluted to 0 in preprocessing time. */ +#define SH_CSS_ISP_PIPE_VERSION_1 1 +#define SH_CSS_ISP_PIPE_VERSION_2_2 2 +#define SH_CSS_ISP_PIPE_VERSION_2_6_1 3 +#define SH_CSS_ISP_PIPE_VERSION_2_7 4 + +/*--------------- sRGB Gamma ----------------- +CCM : YCgCo[0,8191] -> RGB[0,4095] +sRGB Gamma : RGB [0,4095] -> RGB[0,8191] +CSC : RGB [0,8191] -> YUV[0,8191] + +CCM: +Y[0,8191],CgCo[-4096,4095],coef[-8192,8191] -> RGB[0,4095] + +sRGB Gamma: +RGB[0,4095] -(interpolation step16)-> RGB[0,255] -(LUT 12bit)-> RGB[0,4095] -> RGB[0,8191] + +CSC: +RGB[0,8191],coef[-8192,8191] -> RGB[0,8191] +--------------------------------------------*/ +/* Bits of input/output of sRGB Gamma */ +#define SH_CSS_RGB_GAMMA_INPUT_BITS 12 /* [0,4095] */ +#define SH_CSS_RGB_GAMMA_OUTPUT_BITS 13 /* [0,8191] */ + +/* Bits of fractional part of interpolation in vamem, [0,4095]->[0,255] */ +#define SH_CSS_RGB_GAMMA_FRAC_BITS \ + (SH_CSS_RGB_GAMMA_INPUT_BITS - SH_CSS_ISP_RGB_GAMMA_TABLE_SIZE_LOG2) +#define SH_CSS_RGB_GAMMA_ONE (1 << SH_CSS_RGB_GAMMA_FRAC_BITS) + +/* Bits of input of CCM, = 13, Y[0,8191],CgCo[-4096,4095] */ +#define SH_CSS_YUV2RGB_CCM_INPUT_BITS SH_CSS_BAYER_BITS + +/* Bits of output of CCM, = 12, RGB[0,4095] */ +#define SH_CSS_YUV2RGB_CCM_OUTPUT_BITS SH_CSS_RGB_GAMMA_INPUT_BITS + +/* Maximum value of output of CCM */ +#define SH_CSS_YUV2RGB_CCM_MAX_OUTPUT \ + ((1 << SH_CSS_YUV2RGB_CCM_OUTPUT_BITS) - 1) + +#define SH_CSS_NUM_INPUT_BUF_LINES 4 + +/* Left cropping only applicable for sufficiently large nway */ +#if ISP_VEC_NELEMS == 16 +#define SH_CSS_MAX_LEFT_CROPPING 0 +#define SH_CSS_MAX_TOP_CROPPING 0 +#else +#define SH_CSS_MAX_LEFT_CROPPING 12 +#define SH_CSS_MAX_TOP_CROPPING 12 +#endif + +#define SH_CSS_SP_MAX_WIDTH 1280 + +/* This is the maximum grid we can handle in the ISP binaries. + * The host code makes sure no bigger grid is ever selected. */ +#define SH_CSS_MAX_BQ_GRID_WIDTH 80 +#define SH_CSS_MAX_BQ_GRID_HEIGHT 60 + +/* The minimum dvs envelope is 12x12(for IPU2) to make sure the + * invalid rows/columns that result from filter initialization are skipped. */ +#define SH_CSS_MIN_DVS_ENVELOPE 12U + +/* The FPGA system (vec_nelems == 16) only supports upto 5MP */ +#if ISP_VEC_NELEMS == 16 +#define SH_CSS_MAX_SENSOR_WIDTH 2560 +#define SH_CSS_MAX_SENSOR_HEIGHT 1920 +#else +#define SH_CSS_MAX_SENSOR_WIDTH 4608 +#define SH_CSS_MAX_SENSOR_HEIGHT 3450 +#endif + +/* Limited to reduce vmem pressure */ +#if ISP_VMEM_DEPTH >= 3072 +#define SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH SH_CSS_MAX_SENSOR_WIDTH +#define SH_CSS_MAX_CONTINUOUS_SENSOR_HEIGHT SH_CSS_MAX_SENSOR_HEIGHT +#else +#define SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH 3264 +#define SH_CSS_MAX_CONTINUOUS_SENSOR_HEIGHT 2448 +#endif +/* When using bayer decimation */ +/* +#define SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH_DEC 4224 +#define SH_CSS_MAX_CONTINUOUS_SENSOR_HEIGHT_DEC 3168 +*/ +#define SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH_DEC SH_CSS_MAX_SENSOR_WIDTH +#define SH_CSS_MAX_CONTINUOUS_SENSOR_HEIGHT_DEC SH_CSS_MAX_SENSOR_HEIGHT + +#define SH_CSS_MIN_SENSOR_WIDTH 2 +#define SH_CSS_MIN_SENSOR_HEIGHT 2 + +#if defined(IS_ISP_2400_SYSTEM) +/* MAX width and height set to the same to allow for rotated + * resolutions. */ +#define SH_CSS_MAX_VF_WIDTH 1920 +#define SH_CSS_MAX_VF_HEIGHT 1920 +#else +#define SH_CSS_MAX_VF_WIDTH 1280 +#define SH_CSS_MAX_VF_HEIGHT 960 +#endif +/* +#define SH_CSS_MAX_VF_WIDTH_DEC 1920 +#define SH_CSS_MAX_VF_HEIGHT_DEC 1080 +*/ +#define SH_CSS_MAX_VF_WIDTH_DEC SH_CSS_MAX_VF_WIDTH +#define SH_CSS_MAX_VF_HEIGHT_DEC SH_CSS_MAX_VF_HEIGHT + +/* We use 16 bits per coordinate component, including integer + and fractional bits */ +#define SH_CSS_MORPH_TABLE_GRID ISP_VEC_NELEMS +#define SH_CSS_MORPH_TABLE_ELEM_BYTES 2 +#define SH_CSS_MORPH_TABLE_ELEMS_PER_DDR_WORD \ + (HIVE_ISP_DDR_WORD_BYTES/SH_CSS_MORPH_TABLE_ELEM_BYTES) + +#ifndef ISP2401 +#define SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR (SH_CSS_MAX_BQ_GRID_WIDTH + 1) +#define SH_CSS_MAX_SCTBL_HEIGHT_PER_COLOR (SH_CSS_MAX_BQ_GRID_HEIGHT + 1) +#else +/* TODO: I will move macros of "*_SCTBL_*" to SC kernel. + "+ 2" should be "+ SH_CSS_SCTBL_CENTERING_MARGIN + SH_CSS_SCTBL_LAST_GRID_COUNT". (michie, Sep/23/2014) */ +#define SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR (SH_CSS_MAX_BQ_GRID_WIDTH + 2) +#define SH_CSS_MAX_SCTBL_HEIGHT_PER_COLOR (SH_CSS_MAX_BQ_GRID_HEIGHT + 2) +#endif +#define SH_CSS_MAX_SCTBL_ALIGNED_WIDTH_PER_COLOR \ + CEIL_MUL(SH_CSS_MAX_SCTBL_WIDTH_PER_COLOR, ISP_VEC_NELEMS) + +/* Each line of this table is aligned to the maximum line width. */ +#define SH_CSS_MAX_S3ATBL_WIDTH SH_CSS_MAX_BQ_GRID_WIDTH + +#ifndef ISP2401 +/* The video binary supports a delay of 1 or 2 */ +#define MAX_DVS_FRAME_DELAY 2 +/* We always need one additional frame because the video binary + * reads the previous and writes the current frame concurrently */ +#define MAX_NUM_VIDEO_DELAY_FRAMES (MAX_DVS_FRAME_DELAY + 1) +#define NUM_VIDEO_TNR_FRAMES 2 + +#define NUM_TNR_FRAMES 2 /* FIXME */ + + +#define MAX_NUM_DELAY_FRAMES MAX_NUM_VIDEO_DELAY_FRAMES + +#else +/* Video mode specific DVS define */ +/* The video binary supports a delay of 1 or 2 frames */ +#define VIDEO_FRAME_DELAY 2 +/* +1 because DVS reads the previous and writes the current frame concurrently */ +#define MAX_NUM_VIDEO_DELAY_FRAMES (VIDEO_FRAME_DELAY + 1) + +/* Preview mode specific DVS define. */ +/* In preview we only need GDC functionality (and not the DVS functionality) */ +/* The minimum number of DVS frames you need is 2, one were GDC reads from and another where GDC writes into */ +#define NUM_PREVIEW_DVS_FRAMES (2) + +/* TNR is no longer exclusive to video, SkyCam preview has TNR too (same kernel as video). + * All uses the generic define NUM_TNR_FRAMES. The define NUM_VIDEO_TNR_FRAMES has been deprecated. + * + * Notes + * 1) The value depends on the used TNR kernel and is not something that depends on the mode + * and it is not something you just could choice. + * 2) For the luma only pipeline a version that supports two different sets of TNR reference frames + * is being used. + *. + */ +#define NUM_VALID_TNR_REF_FRAMES (1) /* At least one valid TNR reference frame is required */ +#define NUM_TNR_FRAMES_PER_REF_BUF_SET (2) + +/* In luma-only mode alternate illuminated frames are supported, that requires two double buffers */ +#ifdef ENABLE_LUMA_ONLY +#define NUM_TNR_REF_BUF_SETS (2) +#else +#define NUM_TNR_REF_BUF_SETS (1) +#endif + +#define NUM_TNR_FRAMES (NUM_TNR_FRAMES_PER_REF_BUF_SET * NUM_TNR_REF_BUF_SETS) + +#define MAX_NUM_DELAY_FRAMES MAX(MAX_NUM_VIDEO_DELAY_FRAMES, NUM_PREVIEW_DVS_FRAMES) + +#endif + +/* Note that this is the define used to configure all data structures common for all modes */ +/* It should be equal or bigger to the max number of DVS frames for all possible modes */ +/* Rules: these implement logic shared between the host code and ISP firmware. + The ISP firmware needs these rules to be applied at pre-processor time, + that's why these are macros, not functions. */ +#define _ISP_BQS(num) ((num)/2) +#define _ISP_VECS(width) CEIL_DIV(width, ISP_VEC_NELEMS) + +#define ISP_BQ_GRID_WIDTH(elements_per_line, deci_factor_log2) \ + CEIL_SHIFT(elements_per_line/2, deci_factor_log2) +#define ISP_BQ_GRID_HEIGHT(lines_per_frame, deci_factor_log2) \ + CEIL_SHIFT(lines_per_frame/2, deci_factor_log2) +#define ISP_C_VECTORS_PER_LINE(elements_per_line) \ + _ISP_VECS(elements_per_line/2) + +/* The morphing table is similar to the shading table in the sense that we + have 1 more value than we have cells in the grid. */ +#define _ISP_MORPH_TABLE_WIDTH(int_width) \ + (CEIL_DIV(int_width, SH_CSS_MORPH_TABLE_GRID) + 1) +#define _ISP_MORPH_TABLE_HEIGHT(int_height) \ + (CEIL_DIV(int_height, SH_CSS_MORPH_TABLE_GRID) + 1) +#define _ISP_MORPH_TABLE_ALIGNED_WIDTH(width) \ + CEIL_MUL(_ISP_MORPH_TABLE_WIDTH(width), \ + SH_CSS_MORPH_TABLE_ELEMS_PER_DDR_WORD) + +#ifndef ISP2401 +#define _ISP_SCTBL_WIDTH_PER_COLOR(input_width, deci_factor_log2) \ + (ISP_BQ_GRID_WIDTH(input_width, deci_factor_log2) + 1) +#define _ISP_SCTBL_HEIGHT(input_height, deci_factor_log2) \ + (ISP_BQ_GRID_HEIGHT(input_height, deci_factor_log2) + 1) +#define _ISP_SCTBL_ALIGNED_WIDTH_PER_COLOR(input_width, deci_factor_log2) \ + CEIL_MUL(_ISP_SCTBL_WIDTH_PER_COLOR(input_width, deci_factor_log2), \ + ISP_VEC_NELEMS) + +#endif +/* ***************************************************************** + * Statistics for 3A (Auto Focus, Auto White Balance, Auto Exposure) + * *****************************************************************/ +/* if left cropping is used, 3A statistics are also cropped by 2 vectors. */ +#define _ISP_S3ATBL_WIDTH(in_width, deci_factor_log2) \ + (_ISP_BQS(in_width) >> deci_factor_log2) +#define _ISP_S3ATBL_HEIGHT(in_height, deci_factor_log2) \ + (_ISP_BQS(in_height) >> deci_factor_log2) +#define _ISP_S3A_ELEMS_ISP_WIDTH(width, left_crop) \ + (width - ((left_crop) ? 2 * ISP_VEC_NELEMS : 0)) + +#define _ISP_S3ATBL_ISP_WIDTH(in_width, deci_factor_log2) \ + CEIL_SHIFT(_ISP_BQS(in_width), deci_factor_log2) +#define _ISP_S3ATBL_ISP_HEIGHT(in_height, deci_factor_log2) \ + CEIL_SHIFT(_ISP_BQS(in_height), deci_factor_log2) +#define ISP_S3ATBL_VECTORS \ + _ISP_VECS(SH_CSS_MAX_S3ATBL_WIDTH * \ + (sizeof(struct ia_css_3a_output)/sizeof(int32_t))) +#define ISP_S3ATBL_HI_LO_STRIDE \ + (ISP_S3ATBL_VECTORS * ISP_VEC_NELEMS) +#define ISP_S3ATBL_HI_LO_STRIDE_BYTES \ + (sizeof(unsigned short) * ISP_S3ATBL_HI_LO_STRIDE) + +/* Viewfinder support */ +#define __ISP_MAX_VF_OUTPUT_WIDTH(width, left_crop) \ + (width - 2*ISP_VEC_NELEMS + ((left_crop) ? 2 * ISP_VEC_NELEMS : 0)) + +#define __ISP_VF_OUTPUT_WIDTH_VECS(out_width, vf_log_downscale) \ + (_ISP_VECS((out_width) >> (vf_log_downscale))) + +#define _ISP_VF_OUTPUT_WIDTH(vf_out_vecs) ((vf_out_vecs) * ISP_VEC_NELEMS) +#define _ISP_VF_OUTPUT_HEIGHT(out_height, vf_log_ds) \ + ((out_height) >> (vf_log_ds)) + +#define _ISP_LOG_VECTOR_STEP(mode) \ + ((mode) == IA_CSS_BINARY_MODE_CAPTURE_PP ? 2 : 1) + +/* It is preferred to have not more than 2x scaling at one step + * in GDC (assumption is for capture_pp and yuv_scale stages) */ +#define MAX_PREFERRED_YUV_DS_PER_STEP 2 + +/* Rules for computing the internal width. This is extremely complicated + * and definitely needs to be commented and explained. */ +#define _ISP_LEFT_CROP_EXTRA(left_crop) ((left_crop) > 0 ? 2*ISP_VEC_NELEMS : 0) + +#define __ISP_MIN_INTERNAL_WIDTH(num_chunks, pipelining, mode) \ + ((num_chunks) * (pipelining) * (1<<_ISP_LOG_VECTOR_STEP(mode)) * \ + ISP_VEC_NELEMS) + +#define __ISP_PADDED_OUTPUT_WIDTH(out_width, dvs_env_width, left_crop) \ + ((out_width) + MAX(dvs_env_width, _ISP_LEFT_CROP_EXTRA(left_crop))) + +#define __ISP_CHUNK_STRIDE_ISP(mode) \ + ((1<<_ISP_LOG_VECTOR_STEP(mode)) * ISP_VEC_NELEMS) + +#define __ISP_CHUNK_STRIDE_DDR(c_subsampling, num_chunks) \ + ((c_subsampling) * (num_chunks) * HIVE_ISP_DDR_WORD_BYTES) +#define __ISP_INTERNAL_WIDTH(out_width, \ + dvs_env_width, \ + left_crop, \ + mode, \ + c_subsampling, \ + num_chunks, \ + pipelining) \ + CEIL_MUL2(CEIL_MUL2(MAX(__ISP_PADDED_OUTPUT_WIDTH(out_width, \ + dvs_env_width, \ + left_crop), \ + __ISP_MIN_INTERNAL_WIDTH(num_chunks, \ + pipelining, \ + mode) \ + ), \ + __ISP_CHUNK_STRIDE_ISP(mode) \ + ), \ + __ISP_CHUNK_STRIDE_DDR(c_subsampling, num_chunks) \ + ) + +#define __ISP_INTERNAL_HEIGHT(out_height, dvs_env_height, top_crop) \ + ((out_height) + (dvs_env_height) + top_crop) + +/* @GC: Input can be up to sensor resolution when either bayer downscaling + * or raw binning is enabled. + * Also, during continuous mode, we need to align to 4*NWAY since input + * should support binning */ +#define _ISP_MAX_INPUT_WIDTH(max_internal_width, enable_ds, enable_fixed_bayer_ds, enable_raw_bin, \ + enable_continuous) \ + ((enable_ds) ? \ + SH_CSS_MAX_SENSOR_WIDTH :\ + (enable_fixed_bayer_ds) ? \ + CEIL_MUL(SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH_DEC, 4*ISP_VEC_NELEMS) : \ + (enable_raw_bin) ? \ + CEIL_MUL(SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH, 4*ISP_VEC_NELEMS) : \ + (enable_continuous) ? \ + SH_CSS_MAX_CONTINUOUS_SENSOR_WIDTH \ + : max_internal_width) + +#define _ISP_INPUT_WIDTH(internal_width, ds_input_width, enable_ds) \ + ((enable_ds) ? (ds_input_width) : (internal_width)) + +#define _ISP_MAX_INPUT_HEIGHT(max_internal_height, enable_ds, enable_fixed_bayer_ds, enable_raw_bin, \ + enable_continuous) \ + ((enable_ds) ? \ + SH_CSS_MAX_SENSOR_HEIGHT :\ + (enable_fixed_bayer_ds) ? \ + SH_CSS_MAX_CONTINUOUS_SENSOR_HEIGHT_DEC : \ + (enable_raw_bin || enable_continuous) ? \ + SH_CSS_MAX_CONTINUOUS_SENSOR_HEIGHT \ + : max_internal_height) + +#define _ISP_INPUT_HEIGHT(internal_height, ds_input_height, enable_ds) \ + ((enable_ds) ? (ds_input_height) : (internal_height)) + +#define SH_CSS_MAX_STAGES 8 /* primary_stage[1-6], capture_pp, vf_pp */ + +/* For CSI2+ input system, it requires extra paddinga from vmem */ +#ifdef CONFIG_CSI2_PLUS +#define _ISP_EXTRA_PADDING_VECS 2 +#else +#define _ISP_EXTRA_PADDING_VECS 0 +#endif /* CONFIG_CSI2_PLUS */ + +#endif /* _SH_CSS_DEFS_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_dvs_info.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_dvs_info.h new file mode 100644 index 0000000000000000000000000000000000000000..23044aad654fe116f7b83421fbb2a15d48ca3dc9 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_dvs_info.h @@ -0,0 +1,36 @@ +/** +Support for Intel Camera Imaging ISP subsystem. +Copyright (c) 2010 - 2015, Intel Corporation. + +This program is free software; you can redistribute it and/or modify it +under the terms and conditions of the GNU General Public License, +version 2, as published by the Free Software Foundation. + +This program is distributed in the hope it will be useful, but WITHOUT +ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or +FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for +more details. +*/ + +#ifndef __SH_CSS_DVS_INFO_H__ +#define __SH_CSS_DVS_INFO_H__ + +#include + +/* horizontal 64x64 blocks round up to DVS_BLOCKDIM_X, make even */ +#define DVS_NUM_BLOCKS_X(X) (CEIL_MUL(CEIL_DIV((X), DVS_BLOCKDIM_X), 2)) + +/* vertical 64x64 blocks round up to DVS_BLOCKDIM_Y */ +#define DVS_NUM_BLOCKS_Y(X) (CEIL_DIV((X), DVS_BLOCKDIM_Y_LUMA)) + +/* Bilinear interpolation (HRT_GDC_BLI_MODE) is the supported method currently. + * Bicubic interpolation (HRT_GDC_BCI_MODE) is not supported yet */ +#define DVS_GDC_INTERP_METHOD HRT_GDC_BLI_MODE + +#define DVS_INPUT_BYTES_PER_PIXEL (1) + +#define DVS_NUM_BLOCKS_X_CHROMA(X) (CEIL_DIV((X), DVS_BLOCKDIM_X)) + +#define DVS_NUM_BLOCKS_Y_CHROMA(X) (CEIL_DIV((X), DVS_BLOCKDIM_Y_CHROMA)) + +#endif /* __SH_CSS_DVS_INFO_H__ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_firmware.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_firmware.c new file mode 100644 index 0000000000000000000000000000000000000000..b7db3de691acfdafeeee56ebb1ff480aa096fe1b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_firmware.c @@ -0,0 +1,363 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include "platform_support.h" +#include "sh_css_firmware.h" + +#include "sh_css_defs.h" +#include "ia_css_debug.h" +#include "sh_css_internal.h" +#include "ia_css_isp_param.h" + +#include "memory_access.h" +#include "assert_support.h" +#include "string_support.h" + +#include "isp.h" /* PMEM_WIDTH_LOG2 */ + +#include "ia_css_isp_params.h" +#include "ia_css_isp_configs.h" +#include "ia_css_isp_states.h" + +#define _STR(x) #x +#define STR(x) _STR(x) + +struct firmware_header { + struct sh_css_fw_bi_file_h file_header; + struct ia_css_fw_info binary_header; +}; + +struct fw_param { + const char *name; + const void *buffer; +}; + +/* Warning: same order as SH_CSS_BINARY_ID_* */ +static struct firmware_header *firmware_header; + +/* The string STR is a place holder + * which will be replaced with the actual RELEASE_VERSION + * during package generation. Please do not modify */ +#ifndef ISP2401 +static const char *release_version = STR(irci_stable_candrpv_0415_20150521_0458); +#else +static const char *release_version = STR(irci_ecr-master_20150911_0724); +#endif + +#define MAX_FW_REL_VER_NAME 300 +static char FW_rel_ver_name[MAX_FW_REL_VER_NAME] = "---"; + +struct ia_css_fw_info sh_css_sp_fw; +#if defined(HAS_SEC_SP) +struct ia_css_fw_info sh_css_sp1_fw; +#endif /* HAS_SEC_SP */ +#if defined(HAS_BL) +struct ia_css_fw_info sh_css_bl_fw; +#endif /* HAS_BL */ +struct ia_css_blob_descr *sh_css_blob_info; /* Only ISP blob info (no SP) */ +unsigned sh_css_num_binaries; /* This includes 1 SP binary */ + +static struct fw_param *fw_minibuffer; + + +char *sh_css_get_fw_version(void) +{ + return(FW_rel_ver_name); +} + + +/* + * Split the loaded firmware into blobs + */ + +/* Setup sp/sp1 binary */ +static enum ia_css_err +setup_binary(struct ia_css_fw_info *fw, const char *fw_data, struct ia_css_fw_info *sh_css_fw, unsigned binary_id) +{ + const char *blob_data; + + if ((fw == NULL) || (fw_data == NULL)) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + blob_data = fw_data + fw->blob.offset; + + *sh_css_fw = *fw; + +#if defined(C_RUN) || defined(HRT_UNSCHED) + sh_css_fw->blob.code = sh_css_malloc(1); +#else + sh_css_fw->blob.code = sh_css_malloc(fw->blob.size); +#endif + + if (sh_css_fw->blob.code == NULL) + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + + memcpy((void *)sh_css_fw->blob.code, blob_data, fw->blob.size); + sh_css_fw->blob.data = (char *)sh_css_fw->blob.code + fw->blob.data_source; + fw_minibuffer[binary_id].buffer = sh_css_fw->blob.code; + + return IA_CSS_SUCCESS; +} +enum ia_css_err +sh_css_load_blob_info(const char *fw, const struct ia_css_fw_info *bi, struct ia_css_blob_descr *bd, unsigned index) +{ + const char *name; + const unsigned char *blob; + + if ((fw == NULL) || (bd == NULL)) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + /* Special case: only one binary in fw */ + if (bi == NULL) bi = (const struct ia_css_fw_info *)fw; + + name = (const char *)fw + bi->blob.prog_name_offset; + blob = (const unsigned char *)fw + bi->blob.offset; + + /* sanity check */ + if (bi->blob.size != bi->blob.text_size + bi->blob.icache_size + bi->blob.data_size + bi->blob.padding_size) { + /* sanity check, note the padding bytes added for section to DDR alignment */ + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + if ((bi->blob.offset % (1UL<<(ISP_PMEM_WIDTH_LOG2-3))) != 0) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + bd->blob = blob; + bd->header = *bi; + + if ((bi->type == ia_css_isp_firmware) || (bi->type == ia_css_sp_firmware) +#if defined(HAS_SEC_SP) + || (bi->type == ia_css_sp1_firmware) +#endif /* HAS_SEC_SP */ +#if defined(HAS_BL) + || (bi->type == ia_css_bootloader_firmware) +#endif /* HAS_BL */ + ) + { + char *namebuffer; + int namelength = (int)strlen(name); + + namebuffer = (char *) sh_css_malloc(namelength+1); + if (namebuffer == NULL) + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + + memcpy(namebuffer, name, namelength+1); + + bd->name = fw_minibuffer[index].name = namebuffer; + } else { + bd->name = name; + } + + if (bi->type == ia_css_isp_firmware) { + size_t paramstruct_size = sizeof(struct ia_css_memory_offsets); + size_t configstruct_size = sizeof(struct ia_css_config_memory_offsets); + size_t statestruct_size = sizeof(struct ia_css_state_memory_offsets); + + char *parambuf = (char *) sh_css_malloc(paramstruct_size + configstruct_size + statestruct_size); + if (parambuf == NULL) + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + + bd->mem_offsets.array[IA_CSS_PARAM_CLASS_PARAM].ptr = NULL; + bd->mem_offsets.array[IA_CSS_PARAM_CLASS_CONFIG].ptr = NULL; + bd->mem_offsets.array[IA_CSS_PARAM_CLASS_STATE].ptr = NULL; + + fw_minibuffer[index].buffer = parambuf; + + /* copy ia_css_memory_offsets */ + memcpy(parambuf, (void *)(fw + bi->blob.memory_offsets.offsets[IA_CSS_PARAM_CLASS_PARAM]), + paramstruct_size); + bd->mem_offsets.array[IA_CSS_PARAM_CLASS_PARAM].ptr = parambuf; + + /* copy ia_css_config_memory_offsets */ + memcpy(parambuf + paramstruct_size, + (void *)(fw + bi->blob.memory_offsets.offsets[IA_CSS_PARAM_CLASS_CONFIG]), + configstruct_size); + bd->mem_offsets.array[IA_CSS_PARAM_CLASS_CONFIG].ptr = parambuf + paramstruct_size; + + /* copy ia_css_state_memory_offsets */ + memcpy(parambuf + paramstruct_size + configstruct_size, + (void *)(fw + bi->blob.memory_offsets.offsets[IA_CSS_PARAM_CLASS_STATE]), + statestruct_size); + bd->mem_offsets.array[IA_CSS_PARAM_CLASS_STATE].ptr = parambuf + paramstruct_size + configstruct_size; + } + return IA_CSS_SUCCESS; +} + +bool +sh_css_check_firmware_version(const char *fw_data) +{ + struct sh_css_fw_bi_file_h *file_header; + + firmware_header = (struct firmware_header *)fw_data; + file_header = (struct sh_css_fw_bi_file_h *)&firmware_header->file_header; + + if (strcmp(file_header->version, release_version) != 0) { + return false; + } else { + /* firmware version matches */ + return true; + } +} + +enum ia_css_err +sh_css_load_firmware(const char *fw_data, + unsigned int fw_size) +{ + unsigned i; + struct ia_css_fw_info *binaries; + struct sh_css_fw_bi_file_h *file_header; + bool valid_firmware = false; + + firmware_header = (struct firmware_header *)fw_data; + file_header = (struct sh_css_fw_bi_file_h *)&firmware_header->file_header; + binaries = (struct ia_css_fw_info *)&firmware_header->binary_header; + strncpy(FW_rel_ver_name, file_header->version, min(sizeof(FW_rel_ver_name), sizeof(file_header->version)) - 1); + valid_firmware = sh_css_check_firmware_version(fw_data); + if (!valid_firmware) { +#if (!defined HRT_CSIM && !defined HRT_RTL) + IA_CSS_ERROR("CSS code version (%s) and firmware version (%s) mismatch!", + file_header->version, release_version); + return IA_CSS_ERR_VERSION_MISMATCH; +#endif + } else { + IA_CSS_LOG("successfully load firmware version %s", release_version); + } + + /* some sanity checks */ + if (!fw_data || fw_size < sizeof(struct sh_css_fw_bi_file_h)) + return IA_CSS_ERR_INTERNAL_ERROR; + + if (file_header->h_size != sizeof(struct sh_css_fw_bi_file_h)) + return IA_CSS_ERR_INTERNAL_ERROR; + + sh_css_num_binaries = file_header->binary_nr; + /* Only allocate memory for ISP blob info */ + if (sh_css_num_binaries > (NUM_OF_SPS + NUM_OF_BLS)) { + sh_css_blob_info = sh_css_malloc( + (sh_css_num_binaries - (NUM_OF_SPS + NUM_OF_BLS)) * + sizeof(*sh_css_blob_info)); + if (sh_css_blob_info == NULL) + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + } else { + sh_css_blob_info = NULL; + } + + fw_minibuffer = sh_css_malloc(sh_css_num_binaries * sizeof(struct fw_param)); + if (fw_minibuffer == NULL) + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + memset(fw_minibuffer, 0, sh_css_num_binaries * sizeof(struct fw_param)); + + for (i = 0; i < sh_css_num_binaries; i++) { + struct ia_css_fw_info *bi = &binaries[i]; + /* note: the var below is made static as it is quite large; + if it is not static it ends up on the stack which could + cause issues for drivers + */ + static struct ia_css_blob_descr bd; + enum ia_css_err err; + + err = sh_css_load_blob_info(fw_data, bi, &bd, i); + + if (err != IA_CSS_SUCCESS) + return IA_CSS_ERR_INTERNAL_ERROR; + + if (bi->blob.offset + bi->blob.size > fw_size) + return IA_CSS_ERR_INTERNAL_ERROR; + + if (bi->type == ia_css_sp_firmware) { + if (i != SP_FIRMWARE) + return IA_CSS_ERR_INTERNAL_ERROR; + err = setup_binary(bi, fw_data, &sh_css_sp_fw, i); + if (err != IA_CSS_SUCCESS) + return err; +#if defined(HAS_SEC_SP) + } else if (bi->type == ia_css_sp1_firmware) { + if (i != SP1_FIRMWARE) + return IA_CSS_ERR_INTERNAL_ERROR; + err = setup_binary(bi, fw_data, &sh_css_sp1_fw, i); + if (err != IA_CSS_SUCCESS) + return err; +#endif /* HAS_SEC_SP */ +#if defined(HAS_BL) + } else if (bi->type == ia_css_bootloader_firmware) { + if (i != BOOTLOADER_FIRMWARE) + return IA_CSS_ERR_INTERNAL_ERROR; + err = setup_binary(bi, fw_data, &sh_css_bl_fw, i); + if (err != IA_CSS_SUCCESS) + return err; + IA_CSS_LOG("Bootloader binary recognized\n"); +#endif + } else { + /* All subsequent binaries (including bootloaders) (i>NUM_OF_SPS+NUM_OF_BLS) are ISP firmware */ + if (i < (NUM_OF_SPS + NUM_OF_BLS)) + return IA_CSS_ERR_INTERNAL_ERROR; + + if (bi->type != ia_css_isp_firmware) + return IA_CSS_ERR_INTERNAL_ERROR; + if (sh_css_blob_info == NULL) /* cannot happen but KW does not see this */ + return IA_CSS_ERR_INTERNAL_ERROR; + sh_css_blob_info[i-(NUM_OF_SPS + NUM_OF_BLS)] = bd; + } + } + + return IA_CSS_SUCCESS; +} + +void sh_css_unload_firmware(void) +{ + + /* release firmware minibuffer */ + if (fw_minibuffer) { + unsigned int i = 0; + for (i = 0; i < sh_css_num_binaries; i++) { + if (fw_minibuffer[i].name) + sh_css_free((void *)fw_minibuffer[i].name); + if (fw_minibuffer[i].buffer) + sh_css_free((void *)fw_minibuffer[i].buffer); + } + sh_css_free(fw_minibuffer); + fw_minibuffer = NULL; + } + + memset(&sh_css_sp_fw, 0, sizeof(sh_css_sp_fw)); +#if defined(HAS_SEC_SP) + memset(&sh_css_sp1_fw, 0, sizeof(sh_css_sp1_fw)); +#endif /* HAS_SEC_SP */ + if (sh_css_blob_info) { + sh_css_free(sh_css_blob_info); + sh_css_blob_info = NULL; + } + sh_css_num_binaries = 0; +} + +hrt_vaddress +sh_css_load_blob(const unsigned char *blob, unsigned size) +{ + hrt_vaddress target_addr = mmgr_malloc(size); + /* this will allocate memory aligned to a DDR word boundary which + is required for the CSS DMA to read the instructions. */ + + assert(blob != NULL); + if (target_addr) { + mmgr_store(target_addr, blob, size); +#ifdef HRT_CSIM + { + unsigned padded_size = CEIL_MUL(size, HIVE_ISP_DDR_WORD_BYTES); + mmgr_clear(target_addr + size, padded_size - size); + } +#endif + } + return target_addr; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_firmware.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_firmware.h new file mode 100644 index 0000000000000000000000000000000000000000..97bdf2e43db9a472737006ac425d01d302523c76 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_firmware.h @@ -0,0 +1,57 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_FIRMWARE_H_ +#define _SH_CSS_FIRMWARE_H_ + +#include + +#include +#include + +/* This is for the firmware loaded from user space */ +struct sh_css_fw_bi_file_h { + char version[64]; /* branch tag + week day + time */ + int binary_nr; /* Number of binaries */ + unsigned int h_size; /* sizeof(struct sh_css_fw_bi_file_h) */ +}; + +extern struct ia_css_fw_info sh_css_sp_fw; +#if defined(HAS_SEC_SP) +extern struct ia_css_fw_info sh_css_sp1_fw; +#endif /* HAS_SEC_SP */ +#if defined(HAS_BL) +extern struct ia_css_fw_info sh_css_bl_fw; +#endif /* HAS_BL */ +extern struct ia_css_blob_descr *sh_css_blob_info; +extern unsigned sh_css_num_binaries; + +char +*sh_css_get_fw_version(void); + +bool +sh_css_check_firmware_version(const char *fw_data); + +enum ia_css_err +sh_css_load_firmware(const char *fw_data, + unsigned int fw_size); + +void sh_css_unload_firmware(void); + +hrt_vaddress sh_css_load_blob(const unsigned char *blob, unsigned size); + +enum ia_css_err +sh_css_load_blob_info(const char *fw, const struct ia_css_fw_info *bi, struct ia_css_blob_descr *bd, unsigned int i); + +#endif /* _SH_CSS_FIRMWARE_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_frac.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_frac.h new file mode 100644 index 0000000000000000000000000000000000000000..1d1771d71f3c6e03d64f55187fce54c1da0442ab --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_frac.h @@ -0,0 +1,40 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SH_CSS_FRAC_H +#define __SH_CSS_FRAC_H + +#include + +#define sISP_REG_BIT ISP_VEC_ELEMBITS +#define uISP_REG_BIT ((unsigned)(sISP_REG_BIT-1)) +#define sSHIFT (16-sISP_REG_BIT) +#define uSHIFT ((unsigned)(16-uISP_REG_BIT)) +#define sFRACTION_BITS_FITTING(a) (a-sSHIFT) +#define uFRACTION_BITS_FITTING(a) ((unsigned)(a-uSHIFT)) +#define sISP_VAL_MIN (-(1<>sSHIFT) >> max(sFRACTION_BITS_FITTING(a)-(b), 0)), \ + sISP_VAL_MIN), sISP_VAL_MAX) +#define uDIGIT_FITTING(v, a, b) \ + min((unsigned)max((unsigned)(((v)>>uSHIFT) \ + >> max((int)(uFRACTION_BITS_FITTING(a)-(b)), 0)), \ + uISP_VAL_MIN), uISP_VAL_MAX) + +#endif /* __SH_CSS_FRAC_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_host_data.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_host_data.c new file mode 100644 index 0000000000000000000000000000000000000000..19194972a74cd5d30149e96c97ee29dc3d830c38 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_host_data.c @@ -0,0 +1,42 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include +#include + +struct ia_css_host_data *ia_css_host_data_allocate(size_t size) +{ + struct ia_css_host_data *me; + + me = sh_css_malloc(sizeof(struct ia_css_host_data)); + if (!me) + return NULL; + me->size = (uint32_t)size; + me->address = sh_css_malloc(size); + if (!me->address) { + sh_css_free(me); + return NULL; + } + return me; +} + +void ia_css_host_data_free(struct ia_css_host_data *me) +{ + if (me) { + sh_css_free(me->address); + me->address = NULL; + sh_css_free(me); + } +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_hrt.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_hrt.c new file mode 100644 index 0000000000000000000000000000000000000000..0bfebced63afbe3cd4864f046f9ad8c19a0da17c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_hrt.c @@ -0,0 +1,84 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "platform_support.h" + +#include "sh_css_hrt.h" +#include "ia_css_debug.h" + +#include "device_access.h" + +#define __INLINE_EVENT__ +#include "event_fifo.h" +#define __INLINE_SP__ +#include "sp.h" +#define __INLINE_ISP__ +#include "isp.h" +#define __INLINE_IRQ__ +#include "irq.h" +#define __INLINE_FIFO_MONITOR__ +#include "fifo_monitor.h" + +/* System independent */ +#include "sh_css_internal.h" + +bool sh_css_hrt_system_is_idle(void) +{ + bool not_idle = false, idle; + fifo_channel_t ch; + + idle = sp_ctrl_getbit(SP0_ID, SP_SC_REG, SP_IDLE_BIT); + not_idle |= !idle; + if (!idle) + IA_CSS_WARNING("SP not idle"); + + idle = isp_ctrl_getbit(ISP0_ID, ISP_SC_REG, ISP_IDLE_BIT); + not_idle |= !idle; + if (!idle) + IA_CSS_WARNING("ISP not idle"); + + for (ch=0; ch +#include + +#include + +/* SP access */ +void sh_css_hrt_sp_start_si(void); + +void sh_css_hrt_sp_start_copy_frame(void); + +void sh_css_hrt_sp_start_isp(void); + +enum ia_css_err sh_css_hrt_sp_wait(void); + +bool sh_css_hrt_system_is_idle(void); + +#endif /* _SH_CSS_HRT_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_internal.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_internal.h new file mode 100644 index 0000000000000000000000000000000000000000..c5a87b999ea2b87fede73500e4aafa7f74d00606 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_internal.h @@ -0,0 +1,1119 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_INTERNAL_H_ +#define _SH_CSS_INTERNAL_H_ + +#include +#include +#include +#include +#include + +#if !defined(HAS_NO_INPUT_FORMATTER) +#include "input_formatter.h" +#endif +#if !defined(HAS_NO_INPUT_SYSTEM) +#include "input_system.h" +#endif + +#include "ia_css_types.h" +#include "ia_css_acc_types.h" +#include "ia_css_buffer.h" + +#include "ia_css_binary.h" +#if !defined(__ISP) && !defined(__SP) +#include "sh_css_firmware.h" /* not needed/desired on SP/ISP */ +#endif +#include "sh_css_legacy.h" +#include "sh_css_defs.h" +#include "sh_css_uds.h" +#include "dma.h" /* N_DMA_CHANNEL_ID */ +#include "ia_css_circbuf_comm.h" /* Circular buffer */ +#include "ia_css_frame_comm.h" +#include "ia_css_3a.h" +#include "ia_css_dvs.h" +#include "ia_css_lace_stat.h" +#include "ia_css_metadata.h" +#include "runtime/bufq/interface/ia_css_bufq.h" +#include "ia_css_timer.h" + +/* TODO: Move to a more suitable place when sp pipeline design is done. */ +#define IA_CSS_NUM_CB_SEM_READ_RESOURCE 2 +#define IA_CSS_NUM_CB_SEM_WRITE_RESOURCE 1 +#define IA_CSS_NUM_CBS 2 +#define IA_CSS_CB_MAX_ELEMS 2 + +/* Use case specific. index limited to IA_CSS_NUM_CB_SEM_READ_RESOURCE or + * IA_CSS_NUM_CB_SEM_WRITE_RESOURCE for read and write respectively. + * TODO: Enforce the limitation above. +*/ +#define IA_CSS_COPYSINK_SEM_INDEX 0 +#define IA_CSS_TAGGER_SEM_INDEX 1 + +/* Force generation of output event. Used by acceleration pipe. */ +#define IA_CSS_POST_OUT_EVENT_FORCE 2 + +#define SH_CSS_MAX_BINARY_NAME 64 + +#define SP_DEBUG_NONE (0) +#define SP_DEBUG_DUMP (1) +#define SP_DEBUG_COPY (2) +#define SP_DEBUG_TRACE (3) +#define SP_DEBUG_MINIMAL (4) + +#define SP_DEBUG SP_DEBUG_NONE +#define SP_DEBUG_MINIMAL_OVERWRITE 1 + +#define SH_CSS_TNR_BIT_DEPTH 8 +#define SH_CSS_REF_BIT_DEPTH 8 + +/* keep next up to date with the definition for MAX_CB_ELEMS_FOR_TAGGER in tagger.sp.c */ +#if defined(HAS_SP_2400) +#define NUM_CONTINUOUS_FRAMES 15 +#else +#define NUM_CONTINUOUS_FRAMES 10 +#endif +#define NUM_MIPI_FRAMES_PER_STREAM 2 + +#define NUM_ONLINE_INIT_CONTINUOUS_FRAMES 2 + +#define NR_OF_PIPELINES IA_CSS_PIPE_ID_NUM /* Must match with IA_CSS_PIPE_ID_NUM */ + +#define SH_CSS_MAX_IF_CONFIGS 3 /* Must match with IA_CSS_NR_OF_CONFIGS (not defined yet).*/ +#define SH_CSS_IF_CONFIG_NOT_NEEDED 0xFF + +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) +#define SH_CSS_ENABLE_METADATA +#endif + +#if defined(SH_CSS_ENABLE_METADATA) && !defined(USE_INPUT_SYSTEM_VERSION_2401) +#define SH_CSS_ENABLE_METADATA_THREAD +#endif + + + /* + * SH_CSS_MAX_SP_THREADS: + * sp threads visible to host with connected communication queues + * these threads are capable of running an image pipe + * SH_CSS_MAX_SP_INTERNAL_THREADS: + * internal sp service threads, no communication queues to host + * these threads can't be used as image pipe + */ + +#if defined(SH_CSS_ENABLE_METADATA_THREAD) +#define SH_CSS_SP_INTERNAL_METADATA_THREAD 1 +#else +#define SH_CSS_SP_INTERNAL_METADATA_THREAD 0 +#endif + +#define SH_CSS_SP_INTERNAL_SERVICE_THREAD 1 + +#ifdef __DISABLE_UNUSED_THREAD__ + #define SH_CSS_MAX_SP_THREADS 0 +#else + #define SH_CSS_MAX_SP_THREADS 5 +#endif + +#define SH_CSS_MAX_SP_INTERNAL_THREADS (\ + SH_CSS_SP_INTERNAL_SERVICE_THREAD +\ + SH_CSS_SP_INTERNAL_METADATA_THREAD) + +#define SH_CSS_MAX_PIPELINES SH_CSS_MAX_SP_THREADS + +/** + * The C99 standard does not specify the exact object representation of structs; + * the representation is compiler dependent. + * + * The structs that are communicated between host and SP/ISP should have the + * exact same object representation. The compiler that is used to compile the + * firmware is hivecc. + * + * To check if a different compiler, used to compile a host application, uses + * another object representation, macros are defined specifying the size of + * the structs as expected by the firmware. + * + * A host application shall verify that a sizeof( ) of the struct is equal to + * the SIZE_OF_XXX macro of the corresponding struct. If they are not + * equal, functionality will break. + */ +#define CALC_ALIGNMENT_MEMBER(x, y) (CEIL_MUL(x, y) - x) +#define SIZE_OF_HRT_VADDRESS sizeof(hive_uint32) +#define SIZE_OF_IA_CSS_PTR sizeof(uint32_t) + +/* Number of SP's */ +#if defined(HAS_SEC_SP) +#define NUM_OF_SPS 2 +#else +#define NUM_OF_SPS 1 +#endif /* HAS_SEC_SP */ + +#if defined(HAS_BL) +#define NUM_OF_BLS 1 +#else +#define NUM_OF_BLS 0 +#endif + +/* Enum for order of Binaries */ +enum sh_css_order_binaries { + SP_FIRMWARE = 0, +#if defined(HAS_SEC_SP) + SP1_FIRMWARE, +#endif /* HAS_SEC_SP */ +#if defined(HAS_BL) + BOOTLOADER_FIRMWARE, +#endif + ISP_FIRMWARE +}; + + /* + * JB: keep next enum in sync with thread id's + * and pipe id's + */ +enum sh_css_pipe_config_override { + SH_CSS_PIPE_CONFIG_OVRD_NONE = 0, + SH_CSS_PIPE_CONFIG_OVRD_NO_OVRD = 0xffff +}; + +enum host2sp_commands { + host2sp_cmd_error = 0, + /* + * The host2sp_cmd_ready command is the only command written by the SP + * It acknowledges that is previous command has been received. + * (this does not mean that the command has been executed) + * It also indicates that a new command can be send (it is a queue + * with depth 1). + */ + host2sp_cmd_ready = 1, + /* Command written by the Host */ + host2sp_cmd_dummy, /* No action, can be used as watchdog */ + host2sp_cmd_start_flash, /* Request SP to start the flash */ + host2sp_cmd_terminate, /* SP should terminate itself */ + N_host2sp_cmd +}; + +/** Enumeration used to indicate the events that are produced by + * the SP and consumed by the Host. + * + * !!!IMPORTANT!!! KEEP THE FOLLOWING IN SYNC: + * 1) "enum ia_css_event_type" (ia_css_event_public.h) + * 2) "enum sh_css_sp_event_type" (sh_css_internal.h) + * 3) "enum ia_css_event_type event_id_2_event_mask" (event_handler.sp.c) + * 4) "enum ia_css_event_type convert_event_sp_to_host_domain" (sh_css.c) + */ +enum sh_css_sp_event_type { + SH_CSS_SP_EVENT_OUTPUT_FRAME_DONE, + SH_CSS_SP_EVENT_SECOND_OUTPUT_FRAME_DONE, + SH_CSS_SP_EVENT_VF_OUTPUT_FRAME_DONE, + SH_CSS_SP_EVENT_SECOND_VF_OUTPUT_FRAME_DONE, + SH_CSS_SP_EVENT_3A_STATISTICS_DONE, + SH_CSS_SP_EVENT_DIS_STATISTICS_DONE, + SH_CSS_SP_EVENT_PIPELINE_DONE, + SH_CSS_SP_EVENT_FRAME_TAGGED, + SH_CSS_SP_EVENT_INPUT_FRAME_DONE, + SH_CSS_SP_EVENT_METADATA_DONE, + SH_CSS_SP_EVENT_LACE_STATISTICS_DONE, + SH_CSS_SP_EVENT_ACC_STAGE_COMPLETE, + SH_CSS_SP_EVENT_TIMER, + SH_CSS_SP_EVENT_PORT_EOF, + SH_CSS_SP_EVENT_FW_WARNING, + SH_CSS_SP_EVENT_FW_ASSERT, + SH_CSS_SP_EVENT_NR_OF_TYPES /* must be last */ +}; + +/* xmem address map allocation per pipeline, css pointers */ +/* Note that the struct below should only consist of hrt_vaddress-es + Otherwise this will cause a fail in the function ref_sh_css_ddr_address_map + */ +struct sh_css_ddr_address_map { + hrt_vaddress isp_param; + hrt_vaddress isp_mem_param[SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES]; + hrt_vaddress macc_tbl; + hrt_vaddress fpn_tbl; + hrt_vaddress sc_tbl; + hrt_vaddress tetra_r_x; + hrt_vaddress tetra_r_y; + hrt_vaddress tetra_gr_x; + hrt_vaddress tetra_gr_y; + hrt_vaddress tetra_gb_x; + hrt_vaddress tetra_gb_y; + hrt_vaddress tetra_b_x; + hrt_vaddress tetra_b_y; + hrt_vaddress tetra_ratb_x; + hrt_vaddress tetra_ratb_y; + hrt_vaddress tetra_batr_x; + hrt_vaddress tetra_batr_y; + hrt_vaddress dvs_6axis_params_y; +}; +#define SIZE_OF_SH_CSS_DDR_ADDRESS_MAP_STRUCT \ + (SIZE_OF_HRT_VADDRESS + \ + (SH_CSS_MAX_STAGES * IA_CSS_NUM_MEMORIES * SIZE_OF_HRT_VADDRESS) + \ + (16 * SIZE_OF_HRT_VADDRESS)) + +/* xmem address map allocation per pipeline */ +struct sh_css_ddr_address_map_size { + size_t isp_param; + size_t isp_mem_param[SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES]; + size_t macc_tbl; + size_t fpn_tbl; + size_t sc_tbl; + size_t tetra_r_x; + size_t tetra_r_y; + size_t tetra_gr_x; + size_t tetra_gr_y; + size_t tetra_gb_x; + size_t tetra_gb_y; + size_t tetra_b_x; + size_t tetra_b_y; + size_t tetra_ratb_x; + size_t tetra_ratb_y; + size_t tetra_batr_x; + size_t tetra_batr_y; + size_t dvs_6axis_params_y; +}; + +struct sh_css_ddr_address_map_compound { + struct sh_css_ddr_address_map map; + struct sh_css_ddr_address_map_size size; +}; + +struct ia_css_isp_parameter_set_info { + struct sh_css_ddr_address_map mem_map;/**< pointers to Parameters in ISP format IMPT: + This should be first member of this struct */ + uint32_t isp_parameters_id;/**< Unique ID to track which config was actually applied to a particular frame */ + ia_css_ptr output_frame_ptr;/**< Output frame to which this config has to be applied (optional) */ +}; + +/* this struct contains all arguments that can be passed to + a binary. It depends on the binary which ones are used. */ +struct sh_css_binary_args { + struct ia_css_frame *in_frame; /* input frame */ + struct ia_css_frame *delay_frames[MAX_NUM_VIDEO_DELAY_FRAMES]; /* reference input frame */ +#ifndef ISP2401 + struct ia_css_frame *tnr_frames[NUM_VIDEO_TNR_FRAMES]; /* tnr frames */ +#else + struct ia_css_frame *tnr_frames[NUM_TNR_FRAMES]; /* tnr frames */ +#endif + struct ia_css_frame *out_frame[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; /* output frame */ + struct ia_css_frame *out_vf_frame; /* viewfinder output frame */ + bool copy_vf; + bool copy_output; + unsigned vf_downscale_log2; +}; + +#if SP_DEBUG == SP_DEBUG_DUMP + +#define SH_CSS_NUM_SP_DEBUG 48 + +struct sh_css_sp_debug_state { + unsigned int error; + unsigned int debug[SH_CSS_NUM_SP_DEBUG]; +}; + +#elif SP_DEBUG == SP_DEBUG_COPY + +#define SH_CSS_SP_DBG_TRACE_DEPTH (40) + +struct sh_css_sp_debug_trace { + uint16_t frame; + uint16_t line; + uint16_t pixel_distance; + uint16_t mipi_used_dword; + uint16_t sp_index; +}; + +struct sh_css_sp_debug_state { + uint16_t if_start_line; + uint16_t if_start_column; + uint16_t if_cropped_height; + uint16_t if_cropped_width; + unsigned int index; + struct sh_css_sp_debug_trace + trace[SH_CSS_SP_DBG_TRACE_DEPTH]; +}; + +#elif SP_DEBUG == SP_DEBUG_TRACE + +#if 1 +/* Example of just one global trace */ +#define SH_CSS_SP_DBG_NR_OF_TRACES (1) +#define SH_CSS_SP_DBG_TRACE_DEPTH (40) +#else +/* E.g. if you like seperate traces for 4 threads */ +#define SH_CSS_SP_DBG_NR_OF_TRACES (4) +#define SH_CSS_SP_DBG_TRACE_DEPTH (10) +#endif + +#define SH_CSS_SP_DBG_TRACE_FILE_ID_BIT_POS (13) + +struct sh_css_sp_debug_trace { + uint16_t time_stamp; + uint16_t location; /* bit 15..13 = file_id, 12..0 = line nr. */ + uint32_t data; +}; + +struct sh_css_sp_debug_state { + struct sh_css_sp_debug_trace + trace[SH_CSS_SP_DBG_NR_OF_TRACES][SH_CSS_SP_DBG_TRACE_DEPTH]; + uint16_t index_last[SH_CSS_SP_DBG_NR_OF_TRACES]; + uint8_t index[SH_CSS_SP_DBG_NR_OF_TRACES]; +}; + +#elif SP_DEBUG == SP_DEBUG_MINIMAL + +#define SH_CSS_NUM_SP_DEBUG 128 + +struct sh_css_sp_debug_state { + unsigned int error; + unsigned int debug[SH_CSS_NUM_SP_DEBUG]; +}; + +#endif + + +struct sh_css_sp_debug_command { + /* + * The DMA software-mask, + * Bit 31...24: unused. + * Bit 23...16: unused. + * Bit 15...08: reading-request enabling bits for DMA channel 7..0 + * Bit 07...00: writing-reqeust enabling bits for DMA channel 7..0 + * + * For example, "0...0 0...0 11111011 11111101" indicates that the + * writing request through DMA Channel 1 and the reading request + * through DMA channel 2 are both disabled. The others are enabled. + */ + uint32_t dma_sw_reg; +}; + +#if !defined(HAS_NO_INPUT_FORMATTER) +/* SP input formatter configuration.*/ +struct sh_css_sp_input_formatter_set { + uint32_t stream_format; + input_formatter_cfg_t config_a; + input_formatter_cfg_t config_b; +}; +#endif + +#if !defined(HAS_NO_INPUT_SYSTEM) +#define IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT (3) +#endif + +/* SP configuration information */ +struct sh_css_sp_config { + uint8_t no_isp_sync; /* Signal host immediately after start */ + uint8_t enable_raw_pool_locking; /**< Enable Raw Buffer Locking for HALv3 Support */ + uint8_t lock_all; + /**< If raw buffer locking is enabled, this flag indicates whether raw + frames are locked when their EOF event is successfully sent to the + host (true) or when they are passed to the preview/video pipe + (false). */ +#if !defined(HAS_NO_INPUT_FORMATTER) + struct { + uint8_t a_changed; + uint8_t b_changed; + uint8_t isp_2ppc; + struct sh_css_sp_input_formatter_set set[SH_CSS_MAX_IF_CONFIGS]; /* CSI-2 port is used as index. */ + } input_formatter; +#endif +#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2) + sync_generator_cfg_t sync_gen; + tpg_cfg_t tpg; + prbs_cfg_t prbs; + input_system_cfg_t input_circuit; + uint8_t input_circuit_cfg_changed; + uint32_t mipi_sizes_for_check[N_CSI_PORTS][IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT]; +#endif +#if !defined(HAS_NO_INPUT_SYSTEM) + uint8_t enable_isys_event_queue; +#endif + uint8_t disable_cont_vf; +}; + +enum sh_css_stage_type { + SH_CSS_SP_STAGE_TYPE = 0, + SH_CSS_ISP_STAGE_TYPE = 1 +}; +#define SH_CSS_NUM_STAGE_TYPES 2 + +#define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS (1 << 0) +#define SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS_MASK \ + ((SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS << SH_CSS_MAX_SP_THREADS)-1) + +#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2401) +struct sh_css_sp_pipeline_terminal { + union { + /* Input System 2401 */ + virtual_input_system_stream_t virtual_input_system_stream[IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH]; + } context; + /* + * TODO + * - Remove "virtual_input_system_cfg" when the ISYS2401 DLI is ready. + */ + union { + /* Input System 2401 */ + virtual_input_system_stream_cfg_t virtual_input_system_stream_cfg[IA_CSS_STREAM_MAX_ISYS_STREAM_PER_CH]; + } ctrl; +}; + +struct sh_css_sp_pipeline_io { + struct sh_css_sp_pipeline_terminal input; + /* pqiao: comment out temporarily to save dmem */ + /*struct sh_css_sp_pipeline_terminal output;*/ +}; + +/** This struct tracks how many streams are registered per CSI port. + * This is used to track which streams have already been configured. + * Only when all streams are configured, the CSI RX is started for that port. + */ +struct sh_css_sp_pipeline_io_status { + uint32_t active[N_INPUT_SYSTEM_CSI_PORT]; /**< registered streams */ + uint32_t running[N_INPUT_SYSTEM_CSI_PORT]; /**< configured streams */ +}; + +#endif +enum sh_css_port_dir { + SH_CSS_PORT_INPUT = 0, + SH_CSS_PORT_OUTPUT = 1 +}; + +enum sh_css_port_type { + SH_CSS_HOST_TYPE = 0, + SH_CSS_COPYSINK_TYPE = 1, + SH_CSS_TAGGERSINK_TYPE = 2 +}; + +/* Pipe inout settings: output port on 7-4bits, input port on 3-0bits */ +#define SH_CSS_PORT_FLD_WIDTH_IN_BITS (4) +#define SH_CSS_PORT_TYPE_BIT_FLD(pt) (0x1 << (pt)) +#define SH_CSS_PORT_FLD(pd) ((pd) ? SH_CSS_PORT_FLD_WIDTH_IN_BITS : 0) +#define SH_CSS_PIPE_PORT_CONFIG_ON(p, pd, pt) ((p) |= (SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd))) +#define SH_CSS_PIPE_PORT_CONFIG_OFF(p, pd, pt) ((p) &= ~(SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd))) +#define SH_CSS_PIPE_PORT_CONFIG_SET(p, pd, pt, val) ((val) ? \ + SH_CSS_PIPE_PORT_CONFIG_ON(p, pd, pt) : SH_CSS_PIPE_PORT_CONFIG_OFF(p, pd, pt)) +#define SH_CSS_PIPE_PORT_CONFIG_GET(p, pd, pt) ((p) & (SH_CSS_PORT_TYPE_BIT_FLD(pt) << SH_CSS_PORT_FLD(pd))) +#define SH_CSS_PIPE_PORT_CONFIG_IS_CONTINUOUS(p) \ + (!(SH_CSS_PIPE_PORT_CONFIG_GET(p, SH_CSS_PORT_INPUT, SH_CSS_HOST_TYPE) && \ + SH_CSS_PIPE_PORT_CONFIG_GET(p, SH_CSS_PORT_OUTPUT, SH_CSS_HOST_TYPE))) + +#define IA_CSS_ACQUIRE_ISP_POS 31 + +/* Flags for metadata processing */ +#define SH_CSS_METADATA_ENABLED 0x01 +#define SH_CSS_METADATA_PROCESSED 0x02 +#define SH_CSS_METADATA_OFFLINE_MODE 0x04 +#define SH_CSS_METADATA_WAIT_INPUT 0x08 + +/** @brief Free an array of metadata buffers. + * + * @param[in] num_bufs Number of metadata buffers to be freed. + * @param[in] bufs Pointer of array of metadata buffers. + * + * This function frees an array of metadata buffers. + */ +void +ia_css_metadata_free_multiple(unsigned int num_bufs, struct ia_css_metadata **bufs); + +/* Macro for handling pipe_qos_config */ +#define QOS_INVALID (~0U) +#define QOS_ALL_STAGES_DISABLED (0U) +#define QOS_STAGE_MASK(num) (0x00000001 << num) +#define SH_CSS_IS_QOS_PIPE(pipe) ((pipe)->pipe_qos_config != QOS_INVALID) +#define SH_CSS_QOS_STAGE_ENABLE(pipe, num) ((pipe)->pipe_qos_config |= QOS_STAGE_MASK(num)) +#define SH_CSS_QOS_STAGE_DISABLE(pipe, num) ((pipe)->pipe_qos_config &= ~QOS_STAGE_MASK(num)) +#define SH_CSS_QOS_STAGE_IS_ENABLED(pipe, num) ((pipe)->pipe_qos_config & QOS_STAGE_MASK(num)) +#define SH_CSS_QOS_STAGE_IS_ALL_DISABLED(pipe) ((pipe)->pipe_qos_config == QOS_ALL_STAGES_DISABLED) +#define SH_CSS_QOS_MODE_PIPE_ADD(mode, pipe) ((mode) |= (0x1 << (pipe)->pipe_id)) +#define SH_CSS_QOS_MODE_PIPE_REMOVE(mode, pipe) ((mode) &= ~(0x1 << (pipe)->pipe_id)) +#define SH_CSS_IS_QOS_ONLY_MODE(mode) ((mode) == (0x1 << IA_CSS_PIPE_ID_ACC)) + +/* Information for a pipeline */ +struct sh_css_sp_pipeline { + uint32_t pipe_id; /* the pipe ID */ + uint32_t pipe_num; /* the dynamic pipe number */ + uint32_t thread_id; /* the sp thread ID */ + uint32_t pipe_config; /* the pipe config */ + uint32_t pipe_qos_config; /* Bitmap of multiple QOS extension fw state. + (0xFFFFFFFF) indicates non QOS pipe.*/ + uint32_t inout_port_config; + uint32_t required_bds_factor; + uint32_t dvs_frame_delay; +#if !defined(HAS_NO_INPUT_SYSTEM) + uint32_t input_system_mode; /* enum ia_css_input_mode */ + uint32_t port_id; /* port_id for input system */ +#endif + uint32_t num_stages; /* the pipe config */ + uint32_t running; /* needed for pipe termination */ + hrt_vaddress sp_stage_addr[SH_CSS_MAX_STAGES]; + hrt_vaddress scaler_pp_lut; /* Early bound LUT */ +#ifndef __SP + uint32_t dummy; /* stage ptr is only used on sp but lives in + this struct; needs cleanup */ +#else + struct sh_css_sp_stage *stage; /* Current stage for this pipeline */ +#endif + int32_t num_execs; /* number of times to run if this is + an acceleration pipe. */ +#if defined(SH_CSS_ENABLE_METADATA) + struct { + uint32_t format; /* Metadata format in hrt format */ + uint32_t width; /* Width of a line */ + uint32_t height; /* Number of lines */ + uint32_t stride; /* Stride (in bytes) per line */ + uint32_t size; /* Total size (in bytes) */ + hrt_vaddress cont_buf; /* Address of continuous buffer */ + } metadata; +#endif +#if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS) + uint32_t output_frame_queue_id; +#endif + union { + struct { + uint32_t bytes_available; + } bin; + struct { + uint32_t height; + uint32_t width; + uint32_t padded_width; + uint32_t max_input_width; + uint32_t raw_bit_depth; + } raw; + } copy; +#ifdef ISP2401 + + /* Parameters passed to Shading Correction kernel. */ + struct { + uint32_t internal_frame_origin_x_bqs_on_sctbl; /* Origin X (bqs) of internal frame on shading table */ + uint32_t internal_frame_origin_y_bqs_on_sctbl; /* Origin Y (bqs) of internal frame on shading table */ + } shading; +#endif +}; + +/* + * The first frames (with comment Dynamic) can be dynamic or static + * The other frames (ref_in and below) can only be static + * Static means that the data addres will not change during the life time + * of the associated pipe. Dynamic means that the data address can + * change with every (frame) iteration of the associated pipe + * + * s3a and dis are now also dynamic but (stil) handled seperately + */ +#define SH_CSS_NUM_DYNAMIC_FRAME_IDS (3) + +struct ia_css_frames_sp { + struct ia_css_frame_sp in; + struct ia_css_frame_sp out[IA_CSS_BINARY_MAX_OUTPUT_PORTS]; + struct ia_css_resolution effective_in_res; + struct ia_css_frame_sp out_vf; + struct ia_css_frame_sp_info internal_frame_info; + struct ia_css_buffer_sp s3a_buf; + struct ia_css_buffer_sp dvs_buf; +#if defined SH_CSS_ENABLE_METADATA + struct ia_css_buffer_sp metadata_buf; +#endif +}; + +/* Information for a single pipeline stage for an ISP */ +struct sh_css_isp_stage { + /* + * For compatability and portabilty, only types + * from "stdint.h" are allowed + * + * Use of "enum" and "bool" is prohibited + * Multiple boolean flags can be stored in an + * integer + */ + struct ia_css_blob_info blob_info; + struct ia_css_binary_info binary_info; + char binary_name[SH_CSS_MAX_BINARY_NAME]; + struct ia_css_isp_param_css_segments mem_initializers; +}; + +/* Information for a single pipeline stage */ +struct sh_css_sp_stage { + /* + * For compatability and portabilty, only types + * from "stdint.h" are allowed + * + * Use of "enum" and "bool" is prohibited + * Multiple boolean flags can be stored in an + * integer + */ + uint8_t num; /* Stage number */ + uint8_t isp_online; + uint8_t isp_copy_vf; + uint8_t isp_copy_output; + uint8_t sp_enable_xnr; + uint8_t isp_deci_log_factor; + uint8_t isp_vf_downscale_bits; + uint8_t deinterleaved; +/* + * NOTE: Programming the input circuit can only be done at the + * start of a session. It is illegal to program it during execution + * The input circuit defines the connectivity + */ + uint8_t program_input_circuit; +/* enum ia_css_pipeline_stage_sp_func func; */ + uint8_t func; + /* The type of the pipe-stage */ + /* enum sh_css_stage_type stage_type; */ + uint8_t stage_type; + uint8_t num_stripes; + uint8_t isp_pipe_version; + struct { + uint8_t vf_output; + uint8_t s3a; + uint8_t sdis; + uint8_t dvs_stats; + uint8_t lace_stats; + } enable; + /* Add padding to come to a word boundary */ + /* unsigned char padding[0]; */ + + struct sh_css_crop_pos sp_out_crop_pos; + struct ia_css_frames_sp frames; + struct ia_css_resolution dvs_envelope; + struct sh_css_uds_info uds; + hrt_vaddress isp_stage_addr; + hrt_vaddress xmem_bin_addr; + hrt_vaddress xmem_map_addr; + + uint16_t top_cropping; + uint16_t row_stripes_height; + uint16_t row_stripes_overlap_lines; + uint8_t if_config_index; /* Which should be applied by this stage. */ +}; + +/* + * Time: 2012-07-19, 17:40. + * Note: Add a new data memeber "debug" in "sh_css_sp_group". This + * data member is used to pass the debugging command from the + * Host to the SP. + * + * Time: Before 2012-07-19. + * Note: + * Group all host initialized SP variables into this struct. + * This is initialized every stage through dma. + * The stage part itself is transfered through sh_css_sp_stage. +*/ +struct sh_css_sp_group { + struct sh_css_sp_config config; + struct sh_css_sp_pipeline pipe[SH_CSS_MAX_SP_THREADS]; +#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2401) + struct sh_css_sp_pipeline_io pipe_io[SH_CSS_MAX_SP_THREADS]; + struct sh_css_sp_pipeline_io_status pipe_io_status; +#endif + struct sh_css_sp_debug_command debug; +}; + +/* Data in SP dmem that is set from the host every stage. */ +struct sh_css_sp_per_frame_data { + /* ddr address of sp_group and sp_stage */ + hrt_vaddress sp_group_addr; +}; + +#define SH_CSS_NUM_SDW_IRQS 3 + +/* Output data from SP to css */ +struct sh_css_sp_output { + unsigned int bin_copy_bytes_copied; +#if SP_DEBUG != SP_DEBUG_NONE + struct sh_css_sp_debug_state debug; +#endif + unsigned int sw_interrupt_value[SH_CSS_NUM_SDW_IRQS]; +}; + +#define CONFIG_ON_FRAME_ENQUEUE() 0 + +/** + * @brief Data structure for the circular buffer. + * The circular buffer is empty if "start == end". The + * circular buffer is full if "(end + 1) % size == start". + */ +/* Variable Sized Buffer Queue Elements */ + +#define IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE 6 +#define IA_CSS_NUM_ELEMS_HOST2SP_PARAM_QUEUE 3 +#define IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE 6 + +#if !defined(HAS_NO_INPUT_SYSTEM) +/* sp-to-host queue is expected to be emptied in ISR since + * it is used instead of HW interrupts (due to HW design issue). + * We need one queue element per CSI port. */ +#define IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE (2 * N_CSI_PORTS) +/* The host-to-sp queue needs to allow for some delay + * in the emptying of this queue in the SP since there is no + * separate SP thread for this. */ +#define IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE (2 * N_CSI_PORTS) +#else +#define IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE 0 +#define IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE 0 +#define IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE 0 +#endif + +#if defined(HAS_SP_2400) +#define IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE 13 +#define IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE 19 +#define IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE 26 /* holds events for all type of buffers, hence deeper */ +#else +#define IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE 6 +#define IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE 6 +#define IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE 6 +#endif + +struct sh_css_hmm_buffer { + union { + struct ia_css_isp_3a_statistics s3a; + struct ia_css_isp_dvs_statistics dis; + hrt_vaddress skc_dvs_statistics; + hrt_vaddress lace_stat; + struct ia_css_metadata metadata; + struct frame_data_wrapper { + hrt_vaddress frame_data; + uint32_t flashed; + uint32_t exp_id; + uint32_t isp_parameters_id; /**< Unique ID to track which config was + actually applied to a particular frame */ +#if CONFIG_ON_FRAME_ENQUEUE() + struct sh_css_config_on_frame_enqueue config_on_frame_enqueue; +#endif + } frame; + hrt_vaddress ddr_ptrs; + } payload; + /* + * kernel_ptr is present for host administration purposes only. + * type is uint64_t in order to be 64-bit host compatible. + * uint64_t does not exist on SP/ISP. + * Size of the struct is checked by sp.hive.c. + */ +#if !defined(__SP) && !defined(__ISP) + CSS_ALIGN(uint64_t cookie_ptr, 8); /* TODO: check if this alignment is needed */ + uint64_t kernel_ptr; +#else + CSS_ALIGN(struct { uint32_t a[2]; } cookie_ptr, 8); /* TODO: check if this alignment is needed */ + struct { uint32_t a[2]; } kernel_ptr; +#endif + struct ia_css_time_meas timing_data; + clock_value_t isys_eof_clock_tick; +}; +#if CONFIG_ON_FRAME_ENQUEUE() +#define SIZE_OF_FRAME_STRUCT \ + (SIZE_OF_HRT_VADDRESS + \ + (3 * sizeof(uint32_t)) + \ + sizeof(uint32_t)) +#else +#define SIZE_OF_FRAME_STRUCT \ + (SIZE_OF_HRT_VADDRESS + \ + (3 * sizeof(uint32_t))) +#endif + +#define SIZE_OF_PAYLOAD_UNION \ + (MAX(MAX(MAX(MAX( \ + SIZE_OF_IA_CSS_ISP_3A_STATISTICS_STRUCT, \ + SIZE_OF_IA_CSS_ISP_DVS_STATISTICS_STRUCT), \ + SIZE_OF_IA_CSS_METADATA_STRUCT), \ + SIZE_OF_FRAME_STRUCT), \ + SIZE_OF_HRT_VADDRESS)) + +/* Do not use sizeof(uint64_t) since that does not exist of SP */ +#define SIZE_OF_SH_CSS_HMM_BUFFER_STRUCT \ + (SIZE_OF_PAYLOAD_UNION + \ + CALC_ALIGNMENT_MEMBER(SIZE_OF_PAYLOAD_UNION, 8) + \ + 8 + \ + 8 + \ + SIZE_OF_IA_CSS_TIME_MEAS_STRUCT + \ + SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT + \ + CALC_ALIGNMENT_MEMBER(SIZE_OF_IA_CSS_CLOCK_TICK_STRUCT, 8)) + +enum sh_css_queue_type { + sh_css_invalid_queue_type = -1, + sh_css_host2sp_buffer_queue, + sh_css_sp2host_buffer_queue, + sh_css_host2sp_psys_event_queue, + sh_css_sp2host_psys_event_queue, +#if !defined(HAS_NO_INPUT_SYSTEM) + sh_css_sp2host_isys_event_queue, + sh_css_host2sp_isys_event_queue, + sh_css_host2sp_tag_cmd_queue, +#endif +}; + +struct sh_css_event_irq_mask { + uint16_t or_mask; + uint16_t and_mask; +}; +#define SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT \ + (2 * sizeof(uint16_t)) + +struct host_sp_communication { + /* + * Don't use enum host2sp_commands, because the sizeof an enum is + * compiler dependant and thus non-portable + */ + uint32_t host2sp_command; + + /* + * The frame buffers that are reused by the + * copy pipe in the offline preview mode. + * + * host2sp_offline_frames[0]: the input frame of the preview pipe. + * host2sp_offline_frames[1]: the output frame of the copy pipe. + * + * TODO: + * Remove it when the Host and the SP is decoupled. + */ + hrt_vaddress host2sp_offline_frames[NUM_CONTINUOUS_FRAMES]; + hrt_vaddress host2sp_offline_metadata[NUM_CONTINUOUS_FRAMES]; + +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) + hrt_vaddress host2sp_mipi_frames[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM]; + hrt_vaddress host2sp_mipi_metadata[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM]; + uint32_t host2sp_num_mipi_frames[N_CSI_PORTS]; +#endif + uint32_t host2sp_cont_avail_num_raw_frames; + uint32_t host2sp_cont_extra_num_raw_frames; + uint32_t host2sp_cont_target_num_raw_frames; + struct sh_css_event_irq_mask host2sp_event_irq_mask[NR_OF_PIPELINES]; + +}; + +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) +#define SIZE_OF_HOST_SP_COMMUNICATION_STRUCT \ + (sizeof(uint32_t) + \ + (NUM_CONTINUOUS_FRAMES * SIZE_OF_HRT_VADDRESS * 2) + \ + (N_CSI_PORTS * NUM_MIPI_FRAMES_PER_STREAM * SIZE_OF_HRT_VADDRESS * 2) + \ + ((3 + N_CSI_PORTS) * sizeof(uint32_t)) + \ + (NR_OF_PIPELINES * SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT)) +#else +#define SIZE_OF_HOST_SP_COMMUNICATION_STRUCT \ + (sizeof(uint32_t) + \ + (NUM_CONTINUOUS_FRAMES * SIZE_OF_HRT_VADDRESS * 2) + \ + (3 * sizeof(uint32_t)) + \ + (NR_OF_PIPELINES * SIZE_OF_SH_CSS_EVENT_IRQ_MASK_STRUCT)) +#endif + +struct host_sp_queues { + /* + * Queues for the dynamic frame information, + * i.e. the "in_frame" buffer, the "out_frame" + * buffer and the "vf_out_frame" buffer. + */ + ia_css_circbuf_desc_t host2sp_buffer_queues_desc + [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES]; + ia_css_circbuf_elem_t host2sp_buffer_queues_elems + [SH_CSS_MAX_SP_THREADS][SH_CSS_MAX_NUM_QUEUES] + [IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE]; + ia_css_circbuf_desc_t sp2host_buffer_queues_desc + [SH_CSS_MAX_NUM_QUEUES]; + ia_css_circbuf_elem_t sp2host_buffer_queues_elems + [SH_CSS_MAX_NUM_QUEUES][IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE]; + + /* + * The queues for the events. + */ + ia_css_circbuf_desc_t host2sp_psys_event_queue_desc; + ia_css_circbuf_elem_t host2sp_psys_event_queue_elems + [IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE]; + ia_css_circbuf_desc_t sp2host_psys_event_queue_desc; + ia_css_circbuf_elem_t sp2host_psys_event_queue_elems + [IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE]; + +#if !defined(HAS_NO_INPUT_SYSTEM) + /* + * The queues for the ISYS events. + */ + ia_css_circbuf_desc_t host2sp_isys_event_queue_desc; + ia_css_circbuf_elem_t host2sp_isys_event_queue_elems + [IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE]; + ia_css_circbuf_desc_t sp2host_isys_event_queue_desc; + ia_css_circbuf_elem_t sp2host_isys_event_queue_elems + [IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE]; + /* + * The queue for the tagger commands. + * CHECK: are these last two present on the 2401 ? + */ + ia_css_circbuf_desc_t host2sp_tag_cmd_queue_desc; + ia_css_circbuf_elem_t host2sp_tag_cmd_queue_elems + [IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE]; +#endif +}; + +#define SIZE_OF_QUEUES_ELEMS \ + (SIZE_OF_IA_CSS_CIRCBUF_ELEM_S_STRUCT * \ + ((SH_CSS_MAX_SP_THREADS * SH_CSS_MAX_NUM_QUEUES * IA_CSS_NUM_ELEMS_HOST2SP_BUFFER_QUEUE) + \ + (SH_CSS_MAX_NUM_QUEUES * IA_CSS_NUM_ELEMS_SP2HOST_BUFFER_QUEUE) + \ + (IA_CSS_NUM_ELEMS_HOST2SP_PSYS_EVENT_QUEUE) + \ + (IA_CSS_NUM_ELEMS_SP2HOST_PSYS_EVENT_QUEUE) + \ + (IA_CSS_NUM_ELEMS_HOST2SP_ISYS_EVENT_QUEUE) + \ + (IA_CSS_NUM_ELEMS_SP2HOST_ISYS_EVENT_QUEUE) + \ + (IA_CSS_NUM_ELEMS_HOST2SP_TAG_CMD_QUEUE))) + +#if !defined(HAS_NO_INPUT_SYSTEM) +#define IA_CSS_NUM_CIRCBUF_DESCS 5 +#else +#ifndef ISP2401 +#define IA_CSS_NUM_CIRCBUF_DESCS 3 +#else +#define IA_CSS_NUM_CIRCBUF_DESCS 2 +#endif +#endif + +#define SIZE_OF_QUEUES_DESC \ + ((SH_CSS_MAX_SP_THREADS * SH_CSS_MAX_NUM_QUEUES * \ + SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT) + \ + (SH_CSS_MAX_NUM_QUEUES * SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT) + \ + (IA_CSS_NUM_CIRCBUF_DESCS * SIZE_OF_IA_CSS_CIRCBUF_DESC_S_STRUCT)) + +#define SIZE_OF_HOST_SP_QUEUES_STRUCT \ + (SIZE_OF_QUEUES_ELEMS + SIZE_OF_QUEUES_DESC) + +extern int (*sh_css_printf)(const char *fmt, va_list args); + +#ifndef __HIVECC +STORAGE_CLASS_INLINE void +sh_css_print(const char *fmt, ...) +{ + va_list ap; + + if (sh_css_printf) { + va_start(ap, fmt); + sh_css_printf(fmt, ap); + va_end(ap); + } +} + +STORAGE_CLASS_INLINE void +sh_css_vprint(const char *fmt, va_list args) +{ + if (sh_css_printf) + sh_css_printf(fmt, args); +} +#endif + +/* The following #if is there because this header file is also included + by SP and ISP code but they do not need this data and HIVECC has alignment + issue with the firmware struct/union's. + More permanent solution will be to refactor this include. +*/ +#if !defined(__ISP) && !defined(__SP) +hrt_vaddress +sh_css_params_ddr_address_map(void); + +enum ia_css_err +sh_css_params_init(void); + +void +sh_css_params_uninit(void); + +#define sh_css_malloc(size) sh_css_malloc_ex(size, __func__, __LINE__) +#define sh_css_calloc(N, size) sh_css_calloc_ex(N, size, __func__, __LINE__) +#define sh_css_free(ptr) sh_css_free_ex(ptr, __func__, __LINE__) + + +void * +sh_css_malloc_ex(size_t size, const char *caller_func, int caller_line); + +void * +sh_css_calloc_ex(size_t N, size_t size, const char *caller_func, int caller_lin); + +void +sh_css_free_ex(void *ptr, const char *caller_func, int caller_line); + +/* For Acceleration API: Flush FW (shared buffer pointer) arguments */ +void +sh_css_flush(struct ia_css_acc_fw *fw); + + +void +sh_css_binary_args_reset(struct sh_css_binary_args *args); + +/* Check two frames for equality (format, resolution, bits per element) */ +bool +sh_css_frame_equal_types(const struct ia_css_frame *frame_a, + const struct ia_css_frame *frame_b); + +bool +sh_css_frame_info_equal_resolution(const struct ia_css_frame_info *info_a, + const struct ia_css_frame_info *info_b); + +void +sh_css_capture_enable_bayer_downscaling(bool enable); + +void +sh_css_binary_print(const struct ia_css_binary *binary); + +/* aligned argument of sh_css_frame_info_set_width can be used for an extra alignment requirement. + When 0, no extra alignment is done. */ +void +sh_css_frame_info_set_width(struct ia_css_frame_info *info, + unsigned int width, + unsigned int aligned); + +#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2) + +unsigned int +sh_css_get_mipi_sizes_for_check(const unsigned int port, const unsigned int idx); + +#endif + +hrt_vaddress +sh_css_store_sp_group_to_ddr(void); + +hrt_vaddress +sh_css_store_sp_stage_to_ddr(unsigned pipe, unsigned stage); + +hrt_vaddress +sh_css_store_isp_stage_to_ddr(unsigned pipe, unsigned stage); + + +void +sh_css_update_uds_and_crop_info( + const struct ia_css_binary_info *info, + const struct ia_css_frame_info *in_frame_info, + const struct ia_css_frame_info *out_frame_info, + const struct ia_css_resolution *dvs_env, + const struct ia_css_dz_config *zoom, + const struct ia_css_vector *motion_vector, + struct sh_css_uds_info *uds, /* out */ + struct sh_css_crop_pos *sp_out_crop_pos, /* out */ + bool enable_zoom + ); + +void +sh_css_invalidate_shading_tables(struct ia_css_stream *stream); + +struct ia_css_pipeline * +ia_css_pipe_get_pipeline(const struct ia_css_pipe *pipe); + +unsigned int +ia_css_pipe_get_pipe_num(const struct ia_css_pipe *pipe); + +unsigned int +ia_css_pipe_get_isp_pipe_version(const struct ia_css_pipe *pipe); + +bool +sh_css_continuous_is_enabled(uint8_t pipe_num); + +struct ia_css_pipe * +find_pipe_by_num(uint32_t pipe_num); + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 +void +ia_css_get_crop_offsets( + struct ia_css_pipe *pipe, + struct ia_css_frame_info *in_frame); +#endif +#endif /* !defined(__ISP) && !defined(__SP) */ + +#endif /* _SH_CSS_INTERNAL_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_irq.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_irq.c new file mode 100644 index 0000000000000000000000000000000000000000..37e954aea36f73bfe9ea0ba4d24ff021bd500df3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_irq.c @@ -0,0 +1,16 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* This file will contain the code to implement the functions declared in ia_css_irq.h + and associated helper functions */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_lace_stat.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_lace_stat.c new file mode 100644 index 0000000000000000000000000000000000000000..850aa5e5f811ef7e9bf5f200cb129f67163ff789 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_lace_stat.c @@ -0,0 +1,16 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* This file will contain the code to implement the functions declared in ia_css_lace_stat.h + and associated helper functions */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_legacy.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_legacy.h new file mode 100644 index 0000000000000000000000000000000000000000..e12789236bb9abadae85a6e27fbbb8089858255d --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_legacy.h @@ -0,0 +1,88 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_LEGACY_H_ +#define _SH_CSS_LEGACY_H_ + +#include +#include +#include +#include +#include +#include + +/** The pipe id type, distinguishes the kind of pipes that + * can be run in parallel. + */ +enum ia_css_pipe_id { + IA_CSS_PIPE_ID_PREVIEW, + IA_CSS_PIPE_ID_COPY, + IA_CSS_PIPE_ID_VIDEO, + IA_CSS_PIPE_ID_CAPTURE, + IA_CSS_PIPE_ID_YUVPP, +#ifndef ISP2401 + IA_CSS_PIPE_ID_ACC, + IA_CSS_PIPE_ID_NUM +#else + IA_CSS_PIPE_ID_ACC +#endif +}; +#ifdef ISP2401 +#define IA_CSS_PIPE_ID_NUM (IA_CSS_PIPE_ID_ACC+1) +#endif + +struct ia_css_pipe_extra_config { + bool enable_raw_binning; + bool enable_yuv_ds; + bool enable_high_speed; + bool enable_dvs_6axis; + bool enable_reduced_pipe; + bool enable_fractional_ds; + bool disable_vf_pp; +}; + +#define DEFAULT_PIPE_EXTRA_CONFIG \ +{ \ + false, /* enable_raw_binning */ \ + false, /* enable_yuv_ds */ \ + false, /* enable_high_speed */ \ + false, /* enable_dvs_6axis */ \ + false, /* enable_reduced_pipe */ \ + false, /* enable_fractional_ds */ \ + false, /* disable_vf_pp */ \ +} + +enum ia_css_err +ia_css_pipe_create_extra(const struct ia_css_pipe_config *config, + const struct ia_css_pipe_extra_config *extra_config, + struct ia_css_pipe **pipe); + +void +ia_css_pipe_extra_config_defaults(struct ia_css_pipe_extra_config *extra_config); + +enum ia_css_err +ia_css_temp_pipe_to_pipe_id(const struct ia_css_pipe *pipe, + enum ia_css_pipe_id *pipe_id); + +/* DEPRECATED. FPN is not supported. */ +enum ia_css_err +sh_css_set_black_frame(struct ia_css_stream *stream, + const struct ia_css_frame *raw_black_frame); + +#ifndef ISP2401 +void +sh_css_enable_cont_capt(bool enable, bool stop_copy_preview); + +#endif +#endif /* _SH_CSS_LEGACY_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_metadata.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_metadata.c new file mode 100644 index 0000000000000000000000000000000000000000..ebdf84d4a1380d6e81f8a1885ac28b07e539b36b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_metadata.c @@ -0,0 +1,16 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* This file will contain the code to implement the functions declared in ia_css_metadata.h + and associated helper functions */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_metrics.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_metrics.c new file mode 100644 index 0000000000000000000000000000000000000000..48e5542b3a43ec685ad06bbf29bf75eb87983bb3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_metrics.c @@ -0,0 +1,176 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "assert_support.h" +#include "sh_css_metrics.h" + +#include "sp.h" +#include "isp.h" + +#include "sh_css_internal.h" + +#define MULTIPLE_PCS 0 +#define SUSPEND 0 +#define NOF_PCS 1 +#define RESUME_MASK 0x8 +#define STOP_MASK 0x0 + +static bool pc_histogram_enabled; +static struct sh_css_pc_histogram *isp_histogram; +static struct sh_css_pc_histogram *sp_histogram; + +struct sh_css_metrics sh_css_metrics; + +void +sh_css_metrics_start_frame(void) +{ + sh_css_metrics.frame_metrics.num_frames++; +} + +static void +clear_histogram(struct sh_css_pc_histogram *histogram) +{ + unsigned i; + + assert(histogram != NULL); + + for (i = 0; i < histogram->length; i++) { + histogram->run[i] = 0; + histogram->stall[i] = 0; + histogram->msink[i] = 0xFFFF; + } +} + +void +sh_css_metrics_enable_pc_histogram(bool enable) +{ + pc_histogram_enabled = enable; +} + +static void +make_histogram(struct sh_css_pc_histogram *histogram, unsigned length) +{ + assert(histogram != NULL); + + if (histogram->length) + return; + if (histogram->run) + return; + histogram->run = sh_css_malloc(length * sizeof(*histogram->run)); + if (!histogram->run) + return; + histogram->stall = sh_css_malloc(length * sizeof(*histogram->stall)); + if (!histogram->stall) + return; + histogram->msink = sh_css_malloc(length * sizeof(*histogram->msink)); + if (!histogram->msink) + return; + + histogram->length = length; + clear_histogram(histogram); +} + +static void +insert_binary_metrics(struct sh_css_binary_metrics **l, + struct sh_css_binary_metrics *metrics) +{ + assert(l != NULL); + assert(*l != NULL); + assert(metrics != NULL); + + for (; *l; l = &(*l)->next) + if (*l == metrics) + return; + + *l = metrics; + metrics->next = NULL; +} + +void +sh_css_metrics_start_binary(struct sh_css_binary_metrics *metrics) +{ + assert(metrics != NULL); + + if (!pc_histogram_enabled) + return; + + isp_histogram = &metrics->isp_histogram; + sp_histogram = &metrics->sp_histogram; + make_histogram(isp_histogram, ISP_PMEM_DEPTH); + make_histogram(sp_histogram, SP_PMEM_DEPTH); + insert_binary_metrics(&sh_css_metrics.binary_metrics, metrics); +} + +void +sh_css_metrics_sample_pcs(void) +{ + bool stall; + unsigned int pc; + unsigned int msink; + +#if SUSPEND + unsigned int sc = 0; + unsigned int stopped_sc = 0; + unsigned int resume_sc = 0; +#endif + + +#if MULTIPLE_PCS + int i; + unsigned int pc_tab[NOF_PCS]; + + for (i = 0; i < NOF_PCS; i++) + pc_tab[i] = 0; +#endif + + if (!pc_histogram_enabled) + return; + + if (isp_histogram) { +#if SUSPEND + /* STOP the ISP */ + isp_ctrl_store(ISP0_ID, ISP_SC_REG, STOP_MASK); +#endif + msink = isp_ctrl_load(ISP0_ID, ISP_CTRL_SINK_REG); +#if MULTIPLE_PCS + for (i = 0; i < NOF_PCS; i++) + pc_tab[i] = isp_ctrl_load(ISP0_ID, ISP_PC_REG); +#else + pc = isp_ctrl_load(ISP0_ID, ISP_PC_REG); +#endif + +#if SUSPEND + /* RESUME the ISP */ + isp_ctrl_store(ISP0_ID, ISP_SC_REG, RESUME_MASK); +#endif + isp_histogram->msink[pc] &= msink; + stall = (msink != 0x7FF); + + if (stall) + isp_histogram->stall[pc]++; + else + isp_histogram->run[pc]++; + } + + if (sp_histogram && 0) { + msink = sp_ctrl_load(SP0_ID, SP_CTRL_SINK_REG); + pc = sp_ctrl_load(SP0_ID, SP_PC_REG); + sp_histogram->msink[pc] &= msink; + stall = (msink != 0x7FF); + if (stall) + sp_histogram->stall[pc]++; + else + sp_histogram->run[pc]++; + } +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_metrics.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_metrics.h new file mode 100644 index 0000000000000000000000000000000000000000..40840ea318ab66c8d1907de8c96ebee5c8c5a72f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_metrics.h @@ -0,0 +1,76 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_METRICS_H_ +#define _SH_CSS_METRICS_H_ + +#include + +struct sh_css_pc_histogram { + unsigned length; + unsigned *run; + unsigned *stall; + unsigned *msink; +}; + +#if !defined(__USE_DESIGNATED_INITIALISERS__) +#define DEFAULT_PC_HISTOGRAM \ +{ \ + 0, \ + NULL, \ + NULL, \ + NULL \ +} +#endif + +struct sh_css_binary_metrics { + unsigned mode; + unsigned id; + struct sh_css_pc_histogram isp_histogram; + struct sh_css_pc_histogram sp_histogram; + struct sh_css_binary_metrics *next; +}; + +#if !defined(__USE_DESIGNATED_INITIALISERS__) +#define DEFAULT_BINARY_METRICS \ +{ \ + 0, \ + 0, \ + DEFAULT_PC_HISTOGRAM, \ + DEFAULT_PC_HISTOGRAM, \ + NULL \ +} +#endif + +struct ia_css_frame_metrics { + unsigned num_frames; +}; + +struct sh_css_metrics { + struct sh_css_binary_metrics *binary_metrics; + struct ia_css_frame_metrics frame_metrics; +}; + +extern struct sh_css_metrics sh_css_metrics; + +/* includes ia_css_binary.h, which depends on sh_css_metrics.h */ +#include "ia_css_types.h" + +/* Sample ISP and SP pc and add to histogram */ +void sh_css_metrics_enable_pc_histogram(bool enable); +void sh_css_metrics_start_frame(void); +void sh_css_metrics_start_binary(struct sh_css_binary_metrics *metrics); +void sh_css_metrics_sample_pcs(void); + +#endif /* _SH_CSS_METRICS_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_mipi.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_mipi.c new file mode 100644 index 0000000000000000000000000000000000000000..1210c21d8caefd69d9ca07aa217a6ac676190ab0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_mipi.c @@ -0,0 +1,754 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_mipi.h" +#include "sh_css_mipi.h" +#include +#include "system_global.h" +#include "ia_css_err.h" +#include "ia_css_pipe.h" +#include "ia_css_stream_format.h" +#include "sh_css_stream_format.h" +#include "ia_css_stream_public.h" +#include "ia_css_frame_public.h" +#include "ia_css_input_port.h" +#include "ia_css_debug.h" +#include "sh_css_struct.h" +#include "sh_css_defs.h" +#include "sh_css_sp.h" /* sh_css_update_host2sp_mipi_frame sh_css_update_host2sp_num_mipi_frames ... */ +#include "sw_event_global.h" /* IA_CSS_PSYS_SW_EVENT_MIPI_BUFFERS_READY */ + +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) +static uint32_t ref_count_mipi_allocation[N_CSI_PORTS]; /* Initialized in mipi_init */ +#endif + +enum ia_css_err +ia_css_mipi_frame_specify(const unsigned int size_mem_words, + const bool contiguous) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + my_css.size_mem_words = size_mem_words; + (void)contiguous; + + return err; +} + +#ifdef ISP2401 +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) +/* + * Check if a source port or TPG/PRBS ID is valid + */ +static bool ia_css_mipi_is_source_port_valid(struct ia_css_pipe *pipe, + unsigned int *pport) +{ + bool ret = true; + unsigned int port = 0; + unsigned int max_ports = 0; + + switch (pipe->stream->config.mode) { + case IA_CSS_INPUT_MODE_BUFFERED_SENSOR: + port = (unsigned int) pipe->stream->config.source.port.port; + max_ports = N_CSI_PORTS; + break; + case IA_CSS_INPUT_MODE_TPG: + port = (unsigned int) pipe->stream->config.source.tpg.id; + max_ports = N_CSS_TPG_IDS; + break; + case IA_CSS_INPUT_MODE_PRBS: + port = (unsigned int) pipe->stream->config.source.prbs.id; + max_ports = N_CSS_PRBS_IDS; + break; + default: + assert(false); + ret = false; + break; + } + + if (ret) { + assert(port < max_ports); + + if (port >= max_ports) { + ret = false; + } + } + + *pport = port; + + return ret; +} +#endif + +#endif +/* Assumptions: + * - A line is multiple of 4 bytes = 1 word. + * - Each frame has SOF and EOF (each 1 word). + * - Each line has format header and optionally SOL and EOL (each 1 word). + * - Odd and even lines of YUV420 format are different in bites per pixel size. + * - Custom size of embedded data. + * -- Interleaved frames are not taken into account. + * -- Lines are multiples of 8B, and not necessary of (custom 3B, or 7B + * etc.). + * Result is given in DDR mem words, 32B or 256 bits + */ +enum ia_css_err +ia_css_mipi_frame_calculate_size(const unsigned int width, + const unsigned int height, + const enum ia_css_stream_format format, + const bool hasSOLandEOL, + const unsigned int embedded_data_size_words, + unsigned int *size_mem_words) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + unsigned int bits_per_pixel = 0; + unsigned int even_line_bytes = 0; + unsigned int odd_line_bytes = 0; + unsigned int words_per_odd_line = 0; + unsigned int words_for_first_line = 0; + unsigned int words_per_even_line = 0; + unsigned int mem_words_per_even_line = 0; + unsigned int mem_words_per_odd_line = 0; + unsigned int mem_words_for_first_line = 0; + unsigned int mem_words_for_EOF = 0; + unsigned int mem_words = 0; + unsigned int width_padded = width; + +#if defined(USE_INPUT_SYSTEM_VERSION_2401) + /* The changes will be reverted as soon as RAW + * Buffers are deployed by the 2401 Input System + * in the non-continuous use scenario. + */ + width_padded += (2 * ISP_VEC_NELEMS); +#endif + + IA_CSS_ENTER("padded_width=%d, height=%d, format=%d, hasSOLandEOL=%d, embedded_data_size_words=%d\n", + width_padded, height, format, hasSOLandEOL, embedded_data_size_words); + + switch (format) { + case IA_CSS_STREAM_FORMAT_RAW_6: /* 4p, 3B, 24bits */ + bits_per_pixel = 6; break; + case IA_CSS_STREAM_FORMAT_RAW_7: /* 8p, 7B, 56bits */ + bits_per_pixel = 7; break; + case IA_CSS_STREAM_FORMAT_RAW_8: /* 1p, 1B, 8bits */ + case IA_CSS_STREAM_FORMAT_BINARY_8: /* 8bits, TODO: check. */ + case IA_CSS_STREAM_FORMAT_YUV420_8: /* odd 2p, 2B, 16bits, even 2p, 4B, 32bits */ + bits_per_pixel = 8; break; + case IA_CSS_STREAM_FORMAT_YUV420_10: /* odd 4p, 5B, 40bits, even 4p, 10B, 80bits */ + case IA_CSS_STREAM_FORMAT_RAW_10: /* 4p, 5B, 40bits */ +#if !defined(HAS_NO_PACKED_RAW_PIXELS) + /* The changes will be reverted as soon as RAW + * Buffers are deployed by the 2401 Input System + * in the non-continuous use scenario. + */ + bits_per_pixel = 10; +#else + bits_per_pixel = 16; +#endif + break; + case IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY: /* 2p, 3B, 24bits */ + case IA_CSS_STREAM_FORMAT_RAW_12: /* 2p, 3B, 24bits */ + bits_per_pixel = 12; break; + case IA_CSS_STREAM_FORMAT_RAW_14: /* 4p, 7B, 56bits */ + bits_per_pixel = 14; break; + case IA_CSS_STREAM_FORMAT_RGB_444: /* 1p, 2B, 16bits */ + case IA_CSS_STREAM_FORMAT_RGB_555: /* 1p, 2B, 16bits */ + case IA_CSS_STREAM_FORMAT_RGB_565: /* 1p, 2B, 16bits */ + case IA_CSS_STREAM_FORMAT_YUV422_8: /* 2p, 4B, 32bits */ + bits_per_pixel = 16; break; + case IA_CSS_STREAM_FORMAT_RGB_666: /* 4p, 9B, 72bits */ + bits_per_pixel = 18; break; + case IA_CSS_STREAM_FORMAT_YUV422_10: /* 2p, 5B, 40bits */ + bits_per_pixel = 20; break; + case IA_CSS_STREAM_FORMAT_RGB_888: /* 1p, 3B, 24bits */ + bits_per_pixel = 24; break; + + case IA_CSS_STREAM_FORMAT_YUV420_16: /* Not supported */ + case IA_CSS_STREAM_FORMAT_YUV422_16: /* Not supported */ + case IA_CSS_STREAM_FORMAT_RAW_16: /* TODO: not specified in MIPI SPEC, check */ + default: + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + odd_line_bytes = (width_padded * bits_per_pixel + 7) >> 3; /* ceil ( bits per line / 8) */ + + /* Even lines for YUV420 formats are double in bits_per_pixel. */ + if (format == IA_CSS_STREAM_FORMAT_YUV420_8 + || format == IA_CSS_STREAM_FORMAT_YUV420_10 + || format == IA_CSS_STREAM_FORMAT_YUV420_16) { + even_line_bytes = (width_padded * 2 * bits_per_pixel + 7) >> 3; /* ceil ( bits per line / 8) */ + } else { + even_line_bytes = odd_line_bytes; + } + + /* a frame represented in memory: ()- optional; data - payload words. + * addr 0 1 2 3 4 5 6 7: + * first SOF (SOL) PACK_H data data data data data + * data data data data data data data data + * ... + * data data 0 0 0 0 0 0 + * second (EOL) (SOL) PACK_H data data data data data + * data data data data data data data data + * ... + * data data 0 0 0 0 0 0 + * ... + * last (EOL) EOF 0 0 0 0 0 0 + * + * Embedded lines are regular lines stored before the first and after + * payload lines. + */ + + + words_per_odd_line = ((odd_line_bytes + 3) >> 2); /* ceil(odd_line_bytes/4); word = 4 bytes */ + words_per_even_line = ((even_line_bytes + 3) >> 2); + words_for_first_line = words_per_odd_line + 2 + (hasSOLandEOL ? 1 : 0); + /* + SOF +packet header + optionally (SOL), but (EOL) is not in the first line */ + words_per_odd_line += (1 + (hasSOLandEOL ? 2 : 0)); + /* each non-first line has format header, and optionally (SOL) and (EOL). */ + words_per_even_line += (1 + (hasSOLandEOL ? 2 : 0)); + + mem_words_per_odd_line = ((words_per_odd_line + 7) >> 3); + /* ceil(words_per_odd_line/8); mem_word = 32 bytes, 8 words */ + mem_words_for_first_line = ((words_for_first_line + 7) >> 3); + mem_words_per_even_line = ((words_per_even_line + 7) >> 3); + mem_words_for_EOF = 1; /* last line consisit of the optional (EOL) and EOF */ + + mem_words = ((embedded_data_size_words + 7) >> 3) + + mem_words_for_first_line + + (((height + 1) >> 1) - 1) * mem_words_per_odd_line + + /* ceil (height/2) - 1 (first line is calculated separatelly) */ + (height >> 1) * mem_words_per_even_line + /* floor(height/2) */ + mem_words_for_EOF; + + *size_mem_words = mem_words; /* ceil(words/8); mem word is 32B = 8words. */ + /* Check if the above is still needed. */ + + IA_CSS_LEAVE_ERR(err); + return err; +} + +#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2) +enum ia_css_err +ia_css_mipi_frame_enable_check_on_size(const enum ia_css_csi2_port port, + const unsigned int size_mem_words) +{ + uint32_t idx; + + enum ia_css_err err = IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + + OP___assert(port < N_CSI_PORTS); + OP___assert(size_mem_words != 0); + + + for (idx = 0; idx < IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT && + my_css.mipi_sizes_for_check[port][idx] != 0; + idx++) { /* do nothing */ + } + if (idx < IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT) { + my_css.mipi_sizes_for_check[port][idx] = size_mem_words; + err = IA_CSS_SUCCESS; + } + + return err; +} +#endif + +void +mipi_init(void) +{ +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) + unsigned int i; + + for (i = 0; i < N_CSI_PORTS; i++) + ref_count_mipi_allocation[i] = 0; +#endif +} + +enum ia_css_err +calculate_mipi_buff_size( + struct ia_css_stream_config *stream_cfg, + unsigned int *size_mem_words) +{ +#if !defined(USE_INPUT_SYSTEM_VERSION_2401) + enum ia_css_err err = IA_CSS_ERR_INTERNAL_ERROR; + (void)stream_cfg; + (void)size_mem_words; +#else + unsigned int width; + unsigned int height; + enum ia_css_stream_format format; + bool pack_raw_pixels; + + unsigned int width_padded; + unsigned int bits_per_pixel = 0; + + unsigned int even_line_bytes = 0; + unsigned int odd_line_bytes = 0; + + unsigned int words_per_odd_line = 0; + unsigned int words_per_even_line = 0; + + unsigned int mem_words_per_even_line = 0; + unsigned int mem_words_per_odd_line = 0; + + unsigned int mem_words_per_buff_line = 0; + unsigned int mem_words_per_buff = 0; + enum ia_css_err err = IA_CSS_SUCCESS; + + /** +#ifndef ISP2401 + * zhengjie.lu@intel.com + * +#endif + * NOTE + * - In the struct "ia_css_stream_config", there + * are two members: "input_config" and "isys_config". + * Both of them provide the same information, e.g. + * input_res and format. + * + * Question here is that: which one shall be used? + */ + width = stream_cfg->input_config.input_res.width; + height = stream_cfg->input_config.input_res.height; + format = stream_cfg->input_config.format; + pack_raw_pixels = stream_cfg->pack_raw_pixels; + /** end of NOTE */ + + /** +#ifndef ISP2401 + * zhengjie.lu@intel.com + * +#endif + * NOTE + * - The following code is derived from the + * existing code "ia_css_mipi_frame_calculate_size()". + * + * Question here is: why adding "2 * ISP_VEC_NELEMS" + * to "width_padded", but not making "width_padded" + * aligned with "2 * ISP_VEC_NELEMS"? + */ + /* The changes will be reverted as soon as RAW + * Buffers are deployed by the 2401 Input System + * in the non-continuous use scenario. + */ + width_padded = width + (2 * ISP_VEC_NELEMS); + /** end of NOTE */ + + IA_CSS_ENTER("padded_width=%d, height=%d, format=%d\n", + width_padded, height, format); + + bits_per_pixel = sh_css_stream_format_2_bits_per_subpixel(format); + bits_per_pixel = + (format == IA_CSS_STREAM_FORMAT_RAW_10 && pack_raw_pixels) ? bits_per_pixel : 16; + if (bits_per_pixel == 0) + return IA_CSS_ERR_INTERNAL_ERROR; + + odd_line_bytes = (width_padded * bits_per_pixel + 7) >> 3; /* ceil ( bits per line / 8) */ + + /* Even lines for YUV420 formats are double in bits_per_pixel. */ + if (format == IA_CSS_STREAM_FORMAT_YUV420_8 + || format == IA_CSS_STREAM_FORMAT_YUV420_10) { + even_line_bytes = (width_padded * 2 * bits_per_pixel + 7) >> 3; /* ceil ( bits per line / 8) */ + } else { + even_line_bytes = odd_line_bytes; + } + + words_per_odd_line = ((odd_line_bytes + 3) >> 2); + /* ceil(odd_line_bytes/4); word = 4 bytes */ + words_per_even_line = ((even_line_bytes + 3) >> 2); + + mem_words_per_odd_line = ((words_per_odd_line + 7) >> 3); + /* ceil(words_per_odd_line/8); mem_word = 32 bytes, 8 words */ + mem_words_per_even_line = ((words_per_even_line + 7) >> 3); + + mem_words_per_buff_line = + (mem_words_per_odd_line > mem_words_per_even_line) ? mem_words_per_odd_line : mem_words_per_even_line; + mem_words_per_buff = mem_words_per_buff_line * height; + + *size_mem_words = mem_words_per_buff; + + IA_CSS_LEAVE_ERR(err); +#endif + return err; +} + +enum ia_css_err +allocate_mipi_frames(struct ia_css_pipe *pipe, struct ia_css_stream_info *info) +{ +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) + enum ia_css_err err = IA_CSS_ERR_INTERNAL_ERROR; +#ifndef ISP2401 + unsigned int port; +#else + unsigned int port = 0; +#endif + struct ia_css_frame_info mipi_intermediate_info; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "allocate_mipi_frames(%p) enter:\n", pipe); + + assert(pipe != NULL); + assert(pipe->stream != NULL); + if ((pipe == NULL) || (pipe->stream == NULL)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "allocate_mipi_frames(%p) exit: pipe or stream is null.\n", + pipe); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + if (pipe->stream->config.online) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "allocate_mipi_frames(%p) exit: no buffers needed for 2401 pipe mode.\n", + pipe); + return IA_CSS_SUCCESS; + } + +#endif +#ifndef ISP2401 + if (pipe->stream->config.mode != IA_CSS_INPUT_MODE_BUFFERED_SENSOR) { +#else + if (!(pipe->stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR || + pipe->stream->config.mode == IA_CSS_INPUT_MODE_TPG || + pipe->stream->config.mode == IA_CSS_INPUT_MODE_PRBS)) { +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "allocate_mipi_frames(%p) exit: no buffers needed for pipe mode.\n", + pipe); + return IA_CSS_SUCCESS; /* AM TODO: Check */ + } + +#ifndef ISP2401 + port = (unsigned int) pipe->stream->config.source.port.port; + assert(port < N_CSI_PORTS); + if (port >= N_CSI_PORTS) { +#else + if (!ia_css_mipi_is_source_port_valid(pipe, &port)) { +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "allocate_mipi_frames(%p) exit: error: port is not correct (port=%d).\n", + pipe, port); + return IA_CSS_ERR_INTERNAL_ERROR; + } + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 + err = calculate_mipi_buff_size( + &(pipe->stream->config), + &(my_css.mipi_frame_size[port])); +#endif + +#if defined(USE_INPUT_SYSTEM_VERSION_2) + if (ref_count_mipi_allocation[port] != 0) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "allocate_mipi_frames(%p) exit: already allocated for this port (port=%d).\n", + pipe, port); + return IA_CSS_SUCCESS; + } +#else + /* 2401 system allows multiple streams to use same physical port. This is not + * true for 2400 system. Currently 2401 uses MIPI buffers as a temporary solution. + * TODO AM: Once that is changed (removed) this code should be removed as well. + * In that case only 2400 related code should remain. + */ + if (ref_count_mipi_allocation[port] != 0) { + ref_count_mipi_allocation[port]++; + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "allocate_mipi_frames(%p) leave: nothing to do, already allocated for this port (port=%d).\n", + pipe, port); + return IA_CSS_SUCCESS; + } +#endif + + ref_count_mipi_allocation[port]++; + + /* TODO: Cleaning needed. */ + /* This code needs to modified to allocate the MIPI frames in the correct normal way + with an allocate from info, by justin */ + mipi_intermediate_info = pipe->pipe_settings.video.video_binary.internal_frame_info; + mipi_intermediate_info.res.width = 0; + mipi_intermediate_info.res.height = 0; + /* To indicate it is not (yet) valid format. */ + mipi_intermediate_info.format = IA_CSS_FRAME_FORMAT_NUM; + mipi_intermediate_info.padded_width = 0; + mipi_intermediate_info.raw_bit_depth = 0; + + /* AM TODO: mipi frames number should come from stream struct. */ + my_css.num_mipi_frames[port] = NUM_MIPI_FRAMES_PER_STREAM; + + /* Incremental allocation (per stream), not for all streams at once. */ + { /* limit the scope of i,j */ + unsigned i, j; + for (i = 0; i < my_css.num_mipi_frames[port]; i++) { + /* free previous frame */ + if (my_css.mipi_frames[port][i]) { + ia_css_frame_free(my_css.mipi_frames[port][i]); + my_css.mipi_frames[port][i] = NULL; + } + /* check if new frame is needed */ + if (i < my_css.num_mipi_frames[port]) { + /* allocate new frame */ + err = ia_css_frame_allocate_with_buffer_size( + &my_css.mipi_frames[port][i], + my_css.mipi_frame_size[port] * HIVE_ISP_DDR_WORD_BYTES, + false); + if (err != IA_CSS_SUCCESS) { + for (j = 0; j < i; j++) { + if (my_css.mipi_frames[port][j]) { + ia_css_frame_free(my_css.mipi_frames[port][j]); + my_css.mipi_frames[port][j] = NULL; + } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "allocate_mipi_frames(%p, %d) exit: error: allocation failed.\n", + pipe, port); + return err; + } +#ifdef HRT_CSIM + ia_css_frame_zero(my_css.mipi_frames[port][i]); +#endif + } + if (info->metadata_info.size > 0) { + /* free previous metadata buffer */ + if (my_css.mipi_metadata[port][i] != NULL) { + ia_css_metadata_free(my_css.mipi_metadata[port][i]); + my_css.mipi_metadata[port][i] = NULL; + } + /* check if need to allocate a new metadata buffer */ + if (i < my_css.num_mipi_frames[port]) { + /* allocate new metadata buffer */ + my_css.mipi_metadata[port][i] = ia_css_metadata_allocate(&info->metadata_info); + if (my_css.mipi_metadata[port][i] == NULL) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "allocate_mipi_metadata(%p, %d) failed.\n", + pipe, port); + return err; + } + } + } + } + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "allocate_mipi_frames(%p) exit:\n", pipe); + + return err; +#else + (void)pipe; + (void)info; + return IA_CSS_SUCCESS; +#endif +} + +enum ia_css_err +free_mipi_frames(struct ia_css_pipe *pipe) +{ +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) + enum ia_css_err err = IA_CSS_ERR_INTERNAL_ERROR; +#ifndef ISP2401 + unsigned int port; +#else + unsigned int port = 0; +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "free_mipi_frames(%p) enter:\n", pipe); + + /* assert(pipe != NULL); TEMP: TODO: Should be assert only. */ + if (pipe != NULL) { + assert(pipe->stream != NULL); + if ((pipe == NULL) || (pipe->stream == NULL)) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "free_mipi_frames(%p) exit: error: pipe or stream is null.\n", + pipe); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + +#ifndef ISP2401 + if (pipe->stream->config.mode != IA_CSS_INPUT_MODE_BUFFERED_SENSOR) { +#else + if (!(pipe->stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR || + pipe->stream->config.mode == IA_CSS_INPUT_MODE_TPG || + pipe->stream->config.mode == IA_CSS_INPUT_MODE_PRBS)) { +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "free_mipi_frames(%p) exit: error: wrong mode.\n", + pipe); + return err; + } + +#ifndef ISP2401 + port = (unsigned int) pipe->stream->config.source.port.port; + assert(port < N_CSI_PORTS); + if (port >= N_CSI_PORTS) { +#else + if (!ia_css_mipi_is_source_port_valid(pipe, &port)) { +#endif + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, +#ifndef ISP2401 + "free_mipi_frames(%p, %d) exit: error: pipe port is not correct.\n", +#else + "free_mipi_frames(%p) exit: error: pipe port is not correct (port=%d).\n", +#endif + pipe, port); + return err; + } +#ifdef ISP2401 + +#endif + if (ref_count_mipi_allocation[port] > 0) { +#if defined(USE_INPUT_SYSTEM_VERSION_2) + assert(ref_count_mipi_allocation[port] == 1); + if (ref_count_mipi_allocation[port] != 1) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "free_mipi_frames(%p) exit: error: wrong ref_count (ref_count=%d).\n", + pipe, ref_count_mipi_allocation[port]); + return err; + } +#endif + + ref_count_mipi_allocation[port]--; + + if (ref_count_mipi_allocation[port] == 0) { + /* no streams are using this buffer, so free it */ + unsigned int i; + for (i = 0; i < my_css.num_mipi_frames[port]; i++) { + if (my_css.mipi_frames[port][i] != NULL) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "free_mipi_frames(port=%d, num=%d).\n", port, i); + ia_css_frame_free(my_css.mipi_frames[port][i]); + my_css.mipi_frames[port][i] = NULL; + } + if (my_css.mipi_metadata[port][i] != NULL) { + ia_css_metadata_free(my_css.mipi_metadata[port][i]); + my_css.mipi_metadata[port][i] = NULL; + } + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "free_mipi_frames(%p) exit (deallocated).\n", pipe); + } +#if defined(USE_INPUT_SYSTEM_VERSION_2401) + else { + /* 2401 system allows multiple streams to use same physical port. This is not + * true for 2400 system. Currently 2401 uses MIPI buffers as a temporary solution. + * TODO AM: Once that is changed (removed) this code should be removed as well. + * In that case only 2400 related code should remain. + */ + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "free_mipi_frames(%p) leave: nothing to do, other streams still use this port (port=%d).\n", + pipe, port); + } +#endif + } + } else { /* pipe ==NULL */ + /* AM TEMP: free-ing all mipi buffers just like a legacy code. */ + for (port = CSI_PORT0_ID; port < N_CSI_PORTS; port++) { + unsigned int i; + for (i = 0; i < my_css.num_mipi_frames[port]; i++) { + if (my_css.mipi_frames[port][i] != NULL) { + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "free_mipi_frames(port=%d, num=%d).\n", port, i); + ia_css_frame_free(my_css.mipi_frames[port][i]); + my_css.mipi_frames[port][i] = NULL; + } + if (my_css.mipi_metadata[port][i] != NULL) { + ia_css_metadata_free(my_css.mipi_metadata[port][i]); + my_css.mipi_metadata[port][i] = NULL; + } + } + ref_count_mipi_allocation[port] = 0; + } + } +#else + (void)pipe; +#endif + return IA_CSS_SUCCESS; +} + +enum ia_css_err +send_mipi_frames(struct ia_css_pipe *pipe) +{ +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) + enum ia_css_err err = IA_CSS_ERR_INTERNAL_ERROR; + unsigned int i; +#ifndef ISP2401 + unsigned int port; +#else + unsigned int port = 0; +#endif + + IA_CSS_ENTER_PRIVATE("pipe=%d", pipe); + + assert(pipe != NULL); + assert(pipe->stream != NULL); + if (pipe == NULL || pipe->stream == NULL) { + IA_CSS_ERROR("pipe or stream is null"); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + /* multi stream video needs mipi buffers */ + /* nothing to be done in other cases. */ +#ifndef ISP2401 + if (pipe->stream->config.mode != IA_CSS_INPUT_MODE_BUFFERED_SENSOR) { +#else + if (!(pipe->stream->config.mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR || + pipe->stream->config.mode == IA_CSS_INPUT_MODE_TPG || + pipe->stream->config.mode == IA_CSS_INPUT_MODE_PRBS)) { +#endif + IA_CSS_LOG("nothing to be done for this mode"); + return IA_CSS_SUCCESS; + /* TODO: AM: maybe this should be returning an error. */ + } + +#ifndef ISP2401 + port = (unsigned int) pipe->stream->config.source.port.port; + assert(port < N_CSI_PORTS); + if (port >= N_CSI_PORTS) { + IA_CSS_ERROR("invalid port specified (%d)", port); +#else + if (!ia_css_mipi_is_source_port_valid(pipe, &port)) { + IA_CSS_ERROR("send_mipi_frames(%p) exit: invalid port specified (port=%d).\n", pipe, port); +#endif + return err; + } + + /* Hand-over the SP-internal mipi buffers */ + for (i = 0; i < my_css.num_mipi_frames[port]; i++) { + /* Need to include the ofset for port. */ + sh_css_update_host2sp_mipi_frame(port * NUM_MIPI_FRAMES_PER_STREAM + i, + my_css.mipi_frames[port][i]); + sh_css_update_host2sp_mipi_metadata(port * NUM_MIPI_FRAMES_PER_STREAM + i, + my_css.mipi_metadata[port][i]); + } + sh_css_update_host2sp_num_mipi_frames(my_css.num_mipi_frames[port]); + + /********************************** + * Send an event to inform the SP + * that all MIPI frames are passed. + **********************************/ + if (!sh_css_sp_is_running()) { + /* SP is not running. The queues are not valid */ + IA_CSS_ERROR("sp is not running"); + return err; + } + + ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_MIPI_BUFFERS_READY, + (uint8_t)port, + (uint8_t)my_css.num_mipi_frames[port], + 0 /* not used */); + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); +#else + (void)pipe; +#endif + return IA_CSS_SUCCESS; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_mipi.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_mipi.h new file mode 100644 index 0000000000000000000000000000000000000000..990f678422fd2b2e30327d4ffe1091a0c5124e45 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_mipi.h @@ -0,0 +1,49 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SH_CSS_MIPI_H +#define __SH_CSS_MIPI_H + +#include /* ia_css_err */ +#include /* ia_css_pipe */ +#include /* ia_css_stream_config */ + +void +mipi_init(void); + +enum ia_css_err +allocate_mipi_frames(struct ia_css_pipe *pipe, struct ia_css_stream_info *info); + +enum ia_css_err +free_mipi_frames(struct ia_css_pipe *pipe); + +enum ia_css_err +send_mipi_frames(struct ia_css_pipe *pipe); + +/** + * @brief Calculate the required MIPI buffer sizes. + * Based on the stream configuration, calculate the + * required MIPI buffer sizes (in DDR words). + * + * @param[in] stream_cfg Point to the target stream configuration + * @param[out] size_mem_words MIPI buffer size in DDR words. + * + * @return + */ +enum ia_css_err +calculate_mipi_buff_size( + struct ia_css_stream_config *stream_cfg, + unsigned int *size_mem_words); + +#endif /* __SH_CSS_MIPI_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_mmu.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_mmu.c new file mode 100644 index 0000000000000000000000000000000000000000..6de8472f1b073ed3ab256977e835afbb339150ea --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_mmu.c @@ -0,0 +1,62 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_mmu.h" +#ifdef ISP2401 +#include "ia_css_mmu_private.h" +#endif +#include +#include "sh_css_sp.h" +#include "sh_css_firmware.h" +#include "sp.h" +#ifdef ISP2401 +#include "mmu_device.h" +#endif + +void +ia_css_mmu_invalidate_cache(void) +{ + const struct ia_css_fw_info *fw = &sh_css_sp_fw; + unsigned int HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_mmu_invalidate_cache() enter\n"); + + /* if the SP is not running we should not access its dmem */ + if (sh_css_sp_is_running()) { + HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb = fw->info.sp.invalidate_tlb; + + (void)HIVE_ADDR_ia_css_dmaproxy_sp_invalidate_tlb; /* Suppres warnings in CRUN */ + + sp_dmem_store_uint32(SP0_ID, + (unsigned int)sp_address_of(ia_css_dmaproxy_sp_invalidate_tlb), + true); + } + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "ia_css_mmu_invalidate_cache() leave\n"); +} +#ifdef ISP2401 + +/* Deprecated, this is an HRT backend function (memory_access.h) */ +void +sh_css_mmu_set_page_table_base_index(hrt_data base_index) +{ + int i; + IA_CSS_ENTER_PRIVATE("base_index=0x%08x\n", base_index); + for (i = 0; i < N_MMU_ID; i++) { + mmu_ID_t mmu_id = i; + mmu_set_page_table_base_index(mmu_id, base_index); + mmu_invalidate_cache(mmu_id); + } + IA_CSS_LEAVE_PRIVATE(""); +} +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_morph.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_morph.c new file mode 100644 index 0000000000000000000000000000000000000000..1f4fa25b1e79cfb36e6e662b9a436851691af625 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_morph.c @@ -0,0 +1,16 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* This file will contain the code to implement the functions declared in ia_css_morph.h + and associated helper functions */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_param_dvs.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_param_dvs.c new file mode 100644 index 0000000000000000000000000000000000000000..57dd5e7988c986f3b353991fd795975448bf427e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_param_dvs.c @@ -0,0 +1,267 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "sh_css_param_dvs.h" +#include +#include +#include +#include +#include "ia_css_debug.h" +#include "memory_access.h" + +static struct ia_css_dvs_6axis_config * +alloc_dvs_6axis_table(const struct ia_css_resolution *frame_res, struct ia_css_dvs_6axis_config *dvs_config_src) +{ + unsigned int width_y = 0; + unsigned int height_y = 0; + unsigned int width_uv = 0; + unsigned int height_uv = 0; + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_dvs_6axis_config *dvs_config = NULL; + + dvs_config = (struct ia_css_dvs_6axis_config *)sh_css_malloc(sizeof(struct ia_css_dvs_6axis_config)); + if (dvs_config == NULL) { + IA_CSS_ERROR("out of memory"); + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + } + else + { /*Initialize new struct with latest config settings*/ + if (NULL != dvs_config_src) { + dvs_config->width_y = width_y = dvs_config_src->width_y; + dvs_config->height_y = height_y = dvs_config_src->height_y; + dvs_config->width_uv = width_uv = dvs_config_src->width_uv; + dvs_config->height_uv = height_uv = dvs_config_src->height_uv; + IA_CSS_LOG("alloc_dvs_6axis_table Y: W %d H %d", width_y, height_y); + } + else if (NULL != frame_res) { + dvs_config->width_y = width_y = DVS_TABLE_IN_BLOCKDIM_X_LUMA(frame_res->width); + dvs_config->height_y = height_y = DVS_TABLE_IN_BLOCKDIM_Y_LUMA(frame_res->height); + dvs_config->width_uv = width_uv = DVS_TABLE_IN_BLOCKDIM_X_CHROMA(frame_res->width / 2); /* UV = Y/2, depens on colour format YUV 4.2.0*/ + dvs_config->height_uv = height_uv = DVS_TABLE_IN_BLOCKDIM_Y_CHROMA(frame_res->height / 2);/* UV = Y/2, depens on colour format YUV 4.2.0*/ + IA_CSS_LOG("alloc_dvs_6axis_table Y: W %d H %d", width_y, height_y); + } + + /* Generate Y buffers */ + dvs_config->xcoords_y = (uint32_t *)sh_css_malloc(width_y * height_y * sizeof(uint32_t)); + if (dvs_config->xcoords_y == NULL) { + IA_CSS_ERROR("out of memory"); + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + goto exit; + } + + dvs_config->ycoords_y = (uint32_t *)sh_css_malloc(width_y * height_y * sizeof(uint32_t)); + if (dvs_config->ycoords_y == NULL) { + IA_CSS_ERROR("out of memory"); + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + goto exit; + } + + /* Generate UV buffers */ + IA_CSS_LOG("UV W %d H %d", width_uv, height_uv); + + dvs_config->xcoords_uv = (uint32_t *)sh_css_malloc(width_uv * height_uv * sizeof(uint32_t)); + if (dvs_config->xcoords_uv == NULL) { + IA_CSS_ERROR("out of memory"); + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + goto exit; + } + + dvs_config->ycoords_uv = (uint32_t *)sh_css_malloc(width_uv * height_uv * sizeof(uint32_t)); + if (dvs_config->ycoords_uv == NULL) { + IA_CSS_ERROR("out of memory"); + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + } +exit: + if (err != IA_CSS_SUCCESS) { + free_dvs_6axis_table(&dvs_config); /* we might have allocated some memory, release this */ + dvs_config = NULL; + } + } + + IA_CSS_LEAVE("dvs_config=%p", dvs_config); + return dvs_config; +} + +static void +init_dvs_6axis_table_from_default(struct ia_css_dvs_6axis_config *dvs_config, const struct ia_css_resolution *dvs_offset) +{ + unsigned int x, y; + unsigned int width_y = dvs_config->width_y; + unsigned int height_y = dvs_config->height_y; + unsigned int width_uv = dvs_config->width_uv; + unsigned int height_uv = dvs_config->height_uv; + + IA_CSS_LOG("Env_X=%d, Env_Y=%d, width_y=%d, height_y=%d", + dvs_offset->width, dvs_offset->height, width_y, height_y); + for (y = 0; y < height_y; y++) { + for (x = 0; x < width_y; x++) { + dvs_config->xcoords_y[y*width_y + x] = (dvs_offset->width + x*DVS_BLOCKDIM_X) << DVS_COORD_FRAC_BITS; + } + } + + for (y = 0; y < height_y; y++) { + for (x = 0; x < width_y; x++) { + dvs_config->ycoords_y[y*width_y + x] = (dvs_offset->height + y*DVS_BLOCKDIM_Y_LUMA) << DVS_COORD_FRAC_BITS; + } + } + + for (y = 0; y < height_uv; y++) { + for (x = 0; x < width_uv; x++) { /* Envelope dimensions set in Ypixels hence offset UV = offset Y/2 */ + dvs_config->xcoords_uv[y*width_uv + x] = ((dvs_offset->width / 2) + x*DVS_BLOCKDIM_X) << DVS_COORD_FRAC_BITS; + } + } + + for (y = 0; y < height_uv; y++) { + for (x = 0; x < width_uv; x++) { /* Envelope dimensions set in Ypixels hence offset UV = offset Y/2 */ + dvs_config->ycoords_uv[y*width_uv + x] = ((dvs_offset->height / 2) + y*DVS_BLOCKDIM_Y_CHROMA) << DVS_COORD_FRAC_BITS; + } + } + +} + +static void +init_dvs_6axis_table_from_config(struct ia_css_dvs_6axis_config *dvs_config, struct ia_css_dvs_6axis_config *dvs_config_src) +{ + unsigned int width_y = dvs_config->width_y; + unsigned int height_y = dvs_config->height_y; + unsigned int width_uv = dvs_config->width_uv; + unsigned int height_uv = dvs_config->height_uv; + + memcpy(dvs_config->xcoords_y, dvs_config_src->xcoords_y, (width_y * height_y * sizeof(uint32_t))); + memcpy(dvs_config->ycoords_y, dvs_config_src->ycoords_y, (width_y * height_y * sizeof(uint32_t))); + memcpy(dvs_config->xcoords_uv, dvs_config_src->xcoords_uv, (width_uv * height_uv * sizeof(uint32_t))); + memcpy(dvs_config->ycoords_uv, dvs_config_src->ycoords_uv, (width_uv * height_uv * sizeof(uint32_t))); +} + +struct ia_css_dvs_6axis_config * +generate_dvs_6axis_table(const struct ia_css_resolution *frame_res, const struct ia_css_resolution *dvs_offset) +{ + struct ia_css_dvs_6axis_config *dvs_6axis_table; + + assert(frame_res != NULL); + assert(dvs_offset != NULL); + + dvs_6axis_table = alloc_dvs_6axis_table(frame_res, NULL); + if (dvs_6axis_table) { + init_dvs_6axis_table_from_default(dvs_6axis_table, dvs_offset); + return dvs_6axis_table; + } + return NULL; +} + +struct ia_css_dvs_6axis_config * +generate_dvs_6axis_table_from_config(struct ia_css_dvs_6axis_config *dvs_config_src) +{ + struct ia_css_dvs_6axis_config *dvs_6axis_table; + + assert(NULL != dvs_config_src); + + dvs_6axis_table = alloc_dvs_6axis_table(NULL, dvs_config_src); + if (dvs_6axis_table) { + init_dvs_6axis_table_from_config(dvs_6axis_table, dvs_config_src); + return dvs_6axis_table; + } + return NULL; +} + +void +free_dvs_6axis_table(struct ia_css_dvs_6axis_config **dvs_6axis_config) +{ + assert(dvs_6axis_config != NULL); + assert(*dvs_6axis_config != NULL); + + if ((dvs_6axis_config != NULL) && (*dvs_6axis_config != NULL)) + { + IA_CSS_ENTER_PRIVATE("dvs_6axis_config %p", (*dvs_6axis_config)); + if ((*dvs_6axis_config)->xcoords_y != NULL) + { + sh_css_free((*dvs_6axis_config)->xcoords_y); + (*dvs_6axis_config)->xcoords_y = NULL; + } + + if ((*dvs_6axis_config)->ycoords_y != NULL) + { + sh_css_free((*dvs_6axis_config)->ycoords_y); + (*dvs_6axis_config)->ycoords_y = NULL; + } + + /* Free up UV buffers */ + if ((*dvs_6axis_config)->xcoords_uv != NULL) + { + sh_css_free((*dvs_6axis_config)->xcoords_uv); + (*dvs_6axis_config)->xcoords_uv = NULL; + } + + if ((*dvs_6axis_config)->ycoords_uv != NULL) + { + sh_css_free((*dvs_6axis_config)->ycoords_uv); + (*dvs_6axis_config)->ycoords_uv = NULL; + } + + IA_CSS_LEAVE_PRIVATE("dvs_6axis_config %p", (*dvs_6axis_config)); + sh_css_free(*dvs_6axis_config); + *dvs_6axis_config = NULL; + } +} + +void copy_dvs_6axis_table(struct ia_css_dvs_6axis_config *dvs_config_dst, + const struct ia_css_dvs_6axis_config *dvs_config_src) +{ + unsigned int width_y; + unsigned int height_y; + unsigned int width_uv; + unsigned int height_uv; + + assert(dvs_config_src != NULL); + assert(dvs_config_dst != NULL); + assert(dvs_config_src->xcoords_y != NULL); + assert(dvs_config_src->xcoords_uv != NULL); + assert(dvs_config_src->ycoords_y != NULL); + assert(dvs_config_src->ycoords_uv != NULL); + assert(dvs_config_src->width_y == dvs_config_dst->width_y); + assert(dvs_config_src->width_uv == dvs_config_dst->width_uv); + assert(dvs_config_src->height_y == dvs_config_dst->height_y); + assert(dvs_config_src->height_uv == dvs_config_dst->height_uv); + + width_y = dvs_config_src->width_y; + height_y = dvs_config_src->height_y; + width_uv = dvs_config_src->width_uv; /* = Y/2, depens on colour format YUV 4.2.0*/ + height_uv = dvs_config_src->height_uv; + + memcpy(dvs_config_dst->xcoords_y, dvs_config_src->xcoords_y, (width_y * height_y * sizeof(uint32_t))); + memcpy(dvs_config_dst->ycoords_y, dvs_config_src->ycoords_y, (width_y * height_y * sizeof(uint32_t))); + + memcpy(dvs_config_dst->xcoords_uv, dvs_config_src->xcoords_uv, (width_uv * height_uv * sizeof(uint32_t))); + memcpy(dvs_config_dst->ycoords_uv, dvs_config_src->ycoords_uv, (width_uv * height_uv * sizeof(uint32_t))); + +} + +void +ia_css_dvs_statistics_get(enum dvs_statistics_type type, + union ia_css_dvs_statistics_host *host_stats, + const union ia_css_dvs_statistics_isp *isp_stats) +{ + + if (DVS_STATISTICS == type) + { + ia_css_get_dvs_statistics(host_stats->p_dvs_statistics_host, + isp_stats->p_dvs_statistics_isp); + } else if (DVS2_STATISTICS == type) + { + ia_css_get_dvs2_statistics(host_stats->p_dvs2_statistics_host, + isp_stats->p_dvs_statistics_isp); + } + return; +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_param_dvs.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_param_dvs.h new file mode 100644 index 0000000000000000000000000000000000000000..79b563dc78eea23ad95b5f07693eb8ee761e230a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_param_dvs.h @@ -0,0 +1,86 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_PARAMS_DVS_H_ +#define _SH_CSS_PARAMS_DVS_H_ + +#include +#include +#ifdef ISP2401 +#include +#endif +#include "gdc_global.h" /* gdc_warp_param_mem_t */ + +#define DVS_ENV_MIN_X (12) +#define DVS_ENV_MIN_Y (12) + +#define DVS_BLOCKDIM_X (64) /* X block height*/ +#define DVS_BLOCKDIM_Y_LUMA (64) /* Y block height*/ +#define DVS_BLOCKDIM_Y_CHROMA (32) /* UV height block size is half the Y block height*/ + +#ifndef ISP2401 +/* horizontal 64x64 blocks round up to DVS_BLOCKDIM_X, make even */ +#define DVS_NUM_BLOCKS_X(X) (CEIL_MUL(CEIL_DIV((X), DVS_BLOCKDIM_X), 2)) + +/* vertical 64x64 blocks round up to DVS_BLOCKDIM_Y */ +#define DVS_NUM_BLOCKS_Y(X) (CEIL_DIV((X), DVS_BLOCKDIM_Y_LUMA)) +#define DVS_NUM_BLOCKS_X_CHROMA(X) (CEIL_DIV((X), DVS_BLOCKDIM_X)) +#define DVS_NUM_BLOCKS_Y_CHROMA(X) (CEIL_DIV((X), DVS_BLOCKDIM_Y_CHROMA)) + + +#endif +#define DVS_TABLE_IN_BLOCKDIM_X_LUMA(X) (DVS_NUM_BLOCKS_X(X) + 1) /* N blocks have N + 1 set of coords */ +#define DVS_TABLE_IN_BLOCKDIM_X_CHROMA(X) (DVS_NUM_BLOCKS_X_CHROMA(X) + 1) +#define DVS_TABLE_IN_BLOCKDIM_Y_LUMA(X) (DVS_NUM_BLOCKS_Y(X) + 1) +#define DVS_TABLE_IN_BLOCKDIM_Y_CHROMA(X) (DVS_NUM_BLOCKS_Y_CHROMA(X) + 1) + +#define DVS_ENVELOPE_X(X) (((X) == 0) ? (DVS_ENV_MIN_X) : (X)) +#define DVS_ENVELOPE_Y(X) (((X) == 0) ? (DVS_ENV_MIN_Y) : (X)) + +#define DVS_COORD_FRAC_BITS (10) +#ifndef ISP2401 +#define DVS_INPUT_BYTES_PER_PIXEL (1) +#endif +#define XMEM_ALIGN_LOG2 (5) + +#define DVS_6AXIS_COORDS_ELEMS CEIL_MUL(sizeof(gdc_warp_param_mem_t) \ + , HIVE_ISP_DDR_WORD_BYTES) + +/* currently we only support two output with the same resolution, output 0 is th default one. */ +#define DVS_6AXIS_BYTES(binary) \ + (DVS_6AXIS_COORDS_ELEMS \ + * DVS_NUM_BLOCKS_X((binary)->out_frame_info[0].res.width) \ + * DVS_NUM_BLOCKS_Y((binary)->out_frame_info[0].res.height)) + +#ifndef ISP2401 +/* Bilinear interpolation (HRT_GDC_BLI_MODE) is the supported method currently. + * Bicubic interpolation (HRT_GDC_BCI_MODE) is not supported yet */ +#define DVS_GDC_INTERP_METHOD HRT_GDC_BLI_MODE + +#endif +struct ia_css_dvs_6axis_config * +generate_dvs_6axis_table(const struct ia_css_resolution *frame_res, const struct ia_css_resolution *dvs_offset); + +struct ia_css_dvs_6axis_config * +generate_dvs_6axis_table_from_config(struct ia_css_dvs_6axis_config *dvs_config_src); + +void +free_dvs_6axis_table(struct ia_css_dvs_6axis_config **dvs_6axis_config); + +void +copy_dvs_6axis_table(struct ia_css_dvs_6axis_config *dvs_config_dst, + const struct ia_css_dvs_6axis_config *dvs_config_src); + + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_param_shading.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_param_shading.c new file mode 100644 index 0000000000000000000000000000000000000000..7c600fa58079d6db930f26ebed0e51c87cebf728 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_param_shading.c @@ -0,0 +1,417 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include +#include "sh_css_param_shading.h" +#include "ia_css_shading.h" +#include "assert_support.h" +#include "sh_css_defs.h" +#include "sh_css_internal.h" +#include "ia_css_debug.h" +#include "ia_css_pipe_binarydesc.h" + +#include "sh_css_hrt.h" + +#include "platform_support.h" + +/* Bilinear interpolation on shading tables: + * For each target point T, we calculate the 4 surrounding source points: + * ul (upper left), ur (upper right), ll (lower left) and lr (lower right). + * We then calculate the distances from the T to the source points: x0, x1, + * y0 and y1. + * We then calculate the value of T: + * dx0*dy0*Slr + dx0*dy1*Sur + dx1*dy0*Sll + dx1*dy1*Sul. + * We choose a grid size of 1x1 which means: + * dx1 = 1-dx0 + * dy1 = 1-dy0 + * + * Sul dx0 dx1 Sur + * .<----->|<------------->. + * ^ + * dy0| + * v T + * - . + * ^ + * | + * dy1| + * v + * . . + * Sll Slr + * + * Padding: + * The area that the ISP operates on can include padding both on the left + * and the right. We need to padd the shading table such that the shading + * values end up on the correct pixel values. This means we must padd the + * shading table to match the ISP padding. + * We can have 5 cases: + * 1. All 4 points fall in the left padding. + * 2. The left 2 points fall in the left padding. + * 3. All 4 points fall in the cropped (target) region. + * 4. The right 2 points fall in the right padding. + * 5. All 4 points fall in the right padding. + * Cases 1 and 5 are easy to handle: we simply use the + * value 1 in the shading table. + * Cases 2 and 4 require interpolation that takes into + * account how far into the padding area the pixels + * fall. We extrapolate the shading table into the + * padded area and then interpolate. + */ +static void +crop_and_interpolate(unsigned int cropped_width, + unsigned int cropped_height, + unsigned int left_padding, + int right_padding, + int top_padding, + const struct ia_css_shading_table *in_table, + struct ia_css_shading_table *out_table, + enum ia_css_sc_color color) +{ + unsigned int i, j, + sensor_width, + sensor_height, + table_width, + table_height, + table_cell_h, + out_cell_size, + in_cell_size, + out_start_row, + padded_width; + int out_start_col, /* can be negative to indicate padded space */ + table_cell_w; + unsigned short *in_ptr, + *out_ptr; + + assert(in_table != NULL); + assert(out_table != NULL); + + sensor_width = in_table->sensor_width; + sensor_height = in_table->sensor_height; + table_width = in_table->width; + table_height = in_table->height; + in_ptr = in_table->data[color]; + out_ptr = out_table->data[color]; + + padded_width = cropped_width + left_padding + right_padding; + out_cell_size = CEIL_DIV(padded_width, out_table->width - 1); + in_cell_size = CEIL_DIV(sensor_width, table_width - 1); + + out_start_col = ((int)sensor_width - (int)cropped_width)/2 - left_padding; + out_start_row = ((int)sensor_height - (int)cropped_height)/2 - top_padding; + table_cell_w = (int)((table_width-1) * in_cell_size); + table_cell_h = (table_height-1) * in_cell_size; + + for (i = 0; i < out_table->height; i++) { + int ty, src_y0, src_y1; + unsigned int sy0, sy1, dy0, dy1, divy; + + /* calculate target point and make sure it falls within + the table */ + ty = out_start_row + i * out_cell_size; + + /* calculate closest source points in shading table and + make sure they fall within the table */ + src_y0 = ty / (int)in_cell_size; + if (in_cell_size < out_cell_size) + src_y1 = (ty + out_cell_size) / in_cell_size; + else + src_y1 = src_y0 + 1; + src_y0 = clamp(src_y0, 0, (int)table_height-1); + src_y1 = clamp(src_y1, 0, (int)table_height-1); + ty = min(clamp(ty, 0, (int)sensor_height-1), + (int)table_cell_h); + + /* calculate closest source points for distance computation */ + sy0 = min(src_y0 * in_cell_size, sensor_height-1); + sy1 = min(src_y1 * in_cell_size, sensor_height-1); + /* calculate distance between source and target pixels */ + dy0 = ty - sy0; + dy1 = sy1 - ty; + divy = sy1 - sy0; + if (divy == 0) { + dy0 = 1; + divy = 1; + } + + for (j = 0; j < out_table->width; j++, out_ptr++) { + int tx, src_x0, src_x1; + unsigned int sx0, sx1, dx0, dx1, divx; + unsigned short s_ul, s_ur, s_ll, s_lr; + + /* calculate target point */ + tx = out_start_col + j * out_cell_size; + /* calculate closest source points. */ + src_x0 = tx / (int)in_cell_size; + if (in_cell_size < out_cell_size) { + src_x1 = (tx + out_cell_size) / + (int)in_cell_size; + } else { + src_x1 = src_x0 + 1; + } + /* if src points fall in padding, select closest ones.*/ + src_x0 = clamp(src_x0, 0, (int)table_width-1); + src_x1 = clamp(src_x1, 0, (int)table_width-1); + tx = min(clamp(tx, 0, (int)sensor_width-1), + (int)table_cell_w); + /* calculate closest source points for distance + computation */ + sx0 = min(src_x0 * in_cell_size, sensor_width-1); + sx1 = min(src_x1 * in_cell_size, sensor_width-1); + /* calculate distances between source and target + pixels */ + dx0 = tx - sx0; + dx1 = sx1 - tx; + divx = sx1 - sx0; + /* if we're at the edge, we just use the closest + point still in the grid. We make up for the divider + in this case by setting the distance to + out_cell_size, since it's actually 0. */ + if (divx == 0) { + dx0 = 1; + divx = 1; + } + + /* get source pixel values */ + s_ul = in_ptr[(table_width*src_y0)+src_x0]; + s_ur = in_ptr[(table_width*src_y0)+src_x1]; + s_ll = in_ptr[(table_width*src_y1)+src_x0]; + s_lr = in_ptr[(table_width*src_y1)+src_x1]; + + *out_ptr = (unsigned short) ((dx0*dy0*s_lr + dx0*dy1*s_ur + dx1*dy0*s_ll + dx1*dy1*s_ul) / + (divx*divy)); + } + } +} + +void +sh_css_params_shading_id_table_generate( + struct ia_css_shading_table **target_table, +#ifndef ISP2401 + const struct ia_css_binary *binary) +#else + unsigned int table_width, + unsigned int table_height) +#endif +{ + /* initialize table with ones, shift becomes zero */ +#ifndef ISP2401 + unsigned int i, j, table_width, table_height; +#else + unsigned int i, j; +#endif + struct ia_css_shading_table *result; + + assert(target_table != NULL); +#ifndef ISP2401 + assert(binary != NULL); +#endif + +#ifndef ISP2401 + table_width = binary->sctbl_width_per_color; + table_height = binary->sctbl_height; +#endif + result = ia_css_shading_table_alloc(table_width, table_height); + if (result == NULL) { + *target_table = NULL; + return; + } + + for (i = 0; i < IA_CSS_SC_NUM_COLORS; i++) { + for (j = 0; j < table_height * table_width; j++) + result->data[i][j] = 1; + } + result->fraction_bits = 0; + *target_table = result; +} + +void +prepare_shading_table(const struct ia_css_shading_table *in_table, + unsigned int sensor_binning, + struct ia_css_shading_table **target_table, + const struct ia_css_binary *binary, + unsigned int bds_factor) +{ + unsigned int input_width, + input_height, + table_width, + table_height, + left_padding, + top_padding, + padded_width, + left_cropping, + i; + unsigned int bds_numerator, bds_denominator; + int right_padding; + + struct ia_css_shading_table *result; + + assert(target_table != NULL); + assert(binary != NULL); + + if (!in_table) { +#ifndef ISP2401 + sh_css_params_shading_id_table_generate(target_table, binary); +#else + sh_css_params_shading_id_table_generate(target_table, + binary->sctbl_legacy_width_per_color, binary->sctbl_legacy_height); +#endif + return; + } + + padded_width = binary->in_frame_info.padded_width; + /* We use the ISP input resolution for the shading table because + shading correction is performed in the bayer domain (before bayer + down scaling). */ +#if defined(USE_INPUT_SYSTEM_VERSION_2401) + padded_width = CEIL_MUL(binary->effective_in_frame_res.width + 2*ISP_VEC_NELEMS, + 2*ISP_VEC_NELEMS); +#endif + input_height = binary->in_frame_info.res.height; + input_width = binary->in_frame_info.res.width; + left_padding = binary->left_padding; + left_cropping = (binary->info->sp.pipeline.left_cropping == 0) ? + binary->dvs_envelope.width : 2*ISP_VEC_NELEMS; + + sh_css_bds_factor_get_numerator_denominator + (bds_factor, &bds_numerator, &bds_denominator); + + left_padding = (left_padding + binary->info->sp.pipeline.left_cropping) * bds_numerator / bds_denominator - binary->info->sp.pipeline.left_cropping; + right_padding = (binary->internal_frame_info.res.width - binary->effective_in_frame_res.width * bds_denominator / bds_numerator - left_cropping) * bds_numerator / bds_denominator; + top_padding = binary->info->sp.pipeline.top_cropping * bds_numerator / bds_denominator - binary->info->sp.pipeline.top_cropping; + +#if !defined(USE_WINDOWS_BINNING_FACTOR) + /* @deprecated{This part of the code will be replaced by the code + * in the #else section below to make the calculation same across + * all platforms. + * Android and Windows platforms interpret the binning_factor parameter + * differently. In Android, the binning factor is expressed in the form + * 2^N * 2^N, whereas in Windows platform, the binning factor is N*N} + */ + + /* We take into account the binning done by the sensor. We do this + by cropping the non-binned part of the shading table and then + increasing the size of a grid cell with this same binning factor. */ + input_width <<= sensor_binning; + input_height <<= sensor_binning; + /* We also scale the padding by the same binning factor. This will + make it much easier later on to calculate the padding of the + shading table. */ + left_padding <<= sensor_binning; + right_padding <<= sensor_binning; + top_padding <<= sensor_binning; +#else + input_width *= sensor_binning; + input_height *= sensor_binning; + left_padding *= sensor_binning; + right_padding *= sensor_binning; + top_padding *= sensor_binning; +#endif /*USE_WINDOWS_BINNING_FACTOR*/ + + /* during simulation, the used resolution can exceed the sensor + resolution, so we clip it. */ + input_width = min(input_width, in_table->sensor_width); + input_height = min(input_height, in_table->sensor_height); + +#ifndef ISP2401 + table_width = binary->sctbl_width_per_color; + table_height = binary->sctbl_height; +#else + /* This prepare_shading_table() function is called only in legacy API (not in new API). + Then, the legacy shading table width and height should be used. */ + table_width = binary->sctbl_legacy_width_per_color; + table_height = binary->sctbl_legacy_height; +#endif + + result = ia_css_shading_table_alloc(table_width, table_height); + if (result == NULL) { + *target_table = NULL; + return; + } + result->sensor_width = in_table->sensor_width; + result->sensor_height = in_table->sensor_height; + result->fraction_bits = in_table->fraction_bits; + + /* now we crop the original shading table and then interpolate to the + requested resolution and decimation factor. */ + for (i = 0; i < IA_CSS_SC_NUM_COLORS; i++) { + crop_and_interpolate(input_width, input_height, + left_padding, right_padding, top_padding, + in_table, + result, i); + } + *target_table = result; +} + +struct ia_css_shading_table * +ia_css_shading_table_alloc( + unsigned int width, + unsigned int height) +{ + unsigned int i; + struct ia_css_shading_table *me; + + IA_CSS_ENTER(""); + + me = sh_css_malloc(sizeof(*me)); + if (me == NULL) { + IA_CSS_ERROR("out of memory"); + return me; + } + + me->width = width; + me->height = height; + me->sensor_width = 0; + me->sensor_height = 0; + me->fraction_bits = 0; + for (i = 0; i < IA_CSS_SC_NUM_COLORS; i++) { + me->data[i] = + sh_css_malloc(width * height * sizeof(*me->data[0])); + if (me->data[i] == NULL) { + unsigned int j; + for (j = 0; j < i; j++) { + sh_css_free(me->data[j]); + me->data[j] = NULL; + } + sh_css_free(me); + return NULL; + } + } + + IA_CSS_LEAVE(""); + return me; +} + +void +ia_css_shading_table_free(struct ia_css_shading_table *table) +{ + unsigned int i; + + if (table == NULL) + return; + + /* We only output logging when the table is not NULL, otherwise + * logs will give the impression that a table was freed. + * */ + IA_CSS_ENTER(""); + + for (i = 0; i < IA_CSS_SC_NUM_COLORS; i++) { + if (table->data[i]) { + sh_css_free(table->data[i]); + table->data[i] = NULL; + } + } + sh_css_free(table); + + IA_CSS_LEAVE(""); +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_param_shading.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_param_shading.h new file mode 100644 index 0000000000000000000000000000000000000000..e87863b7c8cce37655ff3324c4e33f31c22a4a0e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_param_shading.h @@ -0,0 +1,39 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SH_CSS_PARAMS_SHADING_H +#define __SH_CSS_PARAMS_SHADING_H + +#include +#include + +void +sh_css_params_shading_id_table_generate( + struct ia_css_shading_table **target_table, +#ifndef ISP2401 + const struct ia_css_binary *binary); +#else + unsigned int table_width, + unsigned int table_height); +#endif + +void +prepare_shading_table(const struct ia_css_shading_table *in_table, + unsigned int sensor_binning, + struct ia_css_shading_table **target_table, + const struct ia_css_binary *binary, + unsigned int bds_factor); + +#endif /* __SH_CSS_PARAMS_SHADING_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_params.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_params.c new file mode 100644 index 0000000000000000000000000000000000000000..37a26908c6192060bce034d471a5507ed731e491 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_params.c @@ -0,0 +1,5314 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "gdc_device.h" /* gdc_lut_store(), ... */ +#include "isp.h" /* ISP_VEC_ELEMBITS */ +#include "vamem.h" +#if !defined(HAS_NO_HMEM) +#ifndef __INLINE_HMEM__ +#define __INLINE_HMEM__ +#endif +#include "hmem.h" +#endif /* !defined(HAS_NO_HMEM) */ +#define IA_CSS_INCLUDE_PARAMETERS +#define IA_CSS_INCLUDE_ACC_PARAMETERS + +#include "sh_css_params.h" +#include "ia_css_queue.h" +#include "sw_event_global.h" /* Event IDs */ + +#include "platform_support.h" +#include "assert_support.h" +#include "misc_support.h" /* NOT_USED */ +#include "math_support.h" /* max(), min() EVEN_FLOOR()*/ + +#include "ia_css_stream.h" +#include "sh_css_params_internal.h" +#include "sh_css_param_shading.h" +#include "sh_css_param_dvs.h" +#include "ia_css_refcount.h" +#include "sh_css_internal.h" +#include "ia_css_control.h" +#include "ia_css_shading.h" +#include "sh_css_defs.h" +#include "sh_css_sp.h" +#include "ia_css_pipeline.h" +#include "ia_css_debug.h" +#include "memory_access.h" +#if 0 /* FIXME */ +#include "memory_realloc.h" +#endif +#include "ia_css_isp_param.h" +#include "ia_css_isp_params.h" +#include "ia_css_mipi.h" +#include "ia_css_morph.h" +#include "ia_css_host_data.h" +#include "ia_css_pipe.h" +#include "ia_css_pipe_binarydesc.h" +#if 0 +#include "ia_css_system_ctrl.h" +#endif + +/* Include all kernel host interfaces for ISP1 */ + +#include "anr/anr_1.0/ia_css_anr.host.h" +#include "cnr/cnr_1.0/ia_css_cnr.host.h" +#include "csc/csc_1.0/ia_css_csc.host.h" +#include "de/de_1.0/ia_css_de.host.h" +#include "dp/dp_1.0/ia_css_dp.host.h" +#include "bnr/bnr_1.0/ia_css_bnr.host.h" +#include "dvs/dvs_1.0/ia_css_dvs.host.h" +#include "fpn/fpn_1.0/ia_css_fpn.host.h" +#include "gc/gc_1.0/ia_css_gc.host.h" +#include "macc/macc_1.0/ia_css_macc.host.h" +#include "ctc/ctc_1.0/ia_css_ctc.host.h" +#include "ob/ob_1.0/ia_css_ob.host.h" +#include "raw/raw_1.0/ia_css_raw.host.h" +#include "fixedbds/fixedbds_1.0/ia_css_fixedbds.host.h" +#include "s3a/s3a_1.0/ia_css_s3a.host.h" +#include "sc/sc_1.0/ia_css_sc.host.h" +#include "sdis/sdis_1.0/ia_css_sdis.host.h" +#include "tnr/tnr_1.0/ia_css_tnr.host.h" +#include "uds/uds_1.0/ia_css_uds.host.h" +#include "wb/wb_1.0/ia_css_wb.host.h" +#include "ynr/ynr_1.0/ia_css_ynr.host.h" +#include "xnr/xnr_1.0/ia_css_xnr.host.h" + +/* Include additional kernel host interfaces for ISP2 */ + +#include "aa/aa_2/ia_css_aa2.host.h" +#include "anr/anr_2/ia_css_anr2.host.h" +#include "bh/bh_2/ia_css_bh.host.h" +#include "cnr/cnr_2/ia_css_cnr2.host.h" +#include "ctc/ctc1_5/ia_css_ctc1_5.host.h" +#include "de/de_2/ia_css_de2.host.h" +#include "gc/gc_2/ia_css_gc2.host.h" +#include "sdis/sdis_2/ia_css_sdis2.host.h" +#include "ynr/ynr_2/ia_css_ynr2.host.h" +#include "fc/fc_1.0/ia_css_formats.host.h" + +#include "xnr/xnr_3.0/ia_css_xnr3.host.h" + +#if defined(HAS_OUTPUT_SYSTEM) +#include +#endif + +#include "sh_css_frac.h" +#include "ia_css_bufq.h" + +#define FPNTBL_BYTES(binary) \ + (sizeof(char) * (binary)->in_frame_info.res.height * \ + (binary)->in_frame_info.padded_width) + +#ifndef ISP2401 + +#define SCTBL_BYTES(binary) \ + (sizeof(unsigned short) * (binary)->sctbl_height * \ + (binary)->sctbl_aligned_width_per_color * IA_CSS_SC_NUM_COLORS) + +#else + +#define SCTBL_BYTES(binary) \ + (sizeof(unsigned short) * max((binary)->sctbl_height, (binary)->sctbl_legacy_height) * \ + /* height should be the larger height between new api and legacy api */ \ + (binary)->sctbl_aligned_width_per_color * IA_CSS_SC_NUM_COLORS) + +#endif + +#define MORPH_PLANE_BYTES(binary) \ + (SH_CSS_MORPH_TABLE_ELEM_BYTES * (binary)->morph_tbl_aligned_width * \ + (binary)->morph_tbl_height) + +/* We keep a second copy of the ptr struct for the SP to access. + Again, this would not be necessary on the chip. */ +static hrt_vaddress sp_ddr_ptrs; + +/* sp group address on DDR */ +static hrt_vaddress xmem_sp_group_ptrs; + +static hrt_vaddress xmem_sp_stage_ptrs[IA_CSS_PIPE_ID_NUM] + [SH_CSS_MAX_STAGES]; +static hrt_vaddress xmem_isp_stage_ptrs[IA_CSS_PIPE_ID_NUM] + [SH_CSS_MAX_STAGES]; + +static hrt_vaddress default_gdc_lut; +static int interleaved_lut_temp[4][HRT_GDC_N]; + +/* END DO NOT MOVE INTO VIMALS_WORLD */ + +/* Digital Zoom lookup table. See documentation for more details about the + * contents of this table. + */ +#if defined(HAS_GDC_VERSION_2) +#if defined(CONFIG_CSI2_PLUS) +/* + * Coefficients from + * Css_Mizuchi/regressions/20140424_0930/all/applications/common/gdc_v2_common/lut.h + */ + +static const int zoom_table[4][HRT_GDC_N] = { + { 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, 0, 0, 0, 0, 0, -1, + -1, -1, -1, -1, -1, -1, -1, -1, + -1, -2, -2, -2, -2, -2, -2, -2, + -3, -3, -3, -3, -3, -3, -3, -4, + -4, -4, -4, -4, -5, -5, -5, -5, + -5, -5, -6, -6, -6, -6, -7, -7, + -7, -7, -7, -8, -8, -8, -8, -9, + -9, -9, -9, -10, -10, -10, -10, -11, + -11, -11, -12, -12, -12, -12, -13, -13, + -13, -14, -14, -14, -15, -15, -15, -15, + -16, -16, -16, -17, -17, -17, -18, -18, + -18, -19, -19, -20, -20, -20, -21, -21, + -21, -22, -22, -22, -23, -23, -24, -24, + -24, -25, -25, -25, -26, -26, -27, -27, + -28, -28, -28, -29, -29, -30, -30, -30, + -31, -31, -32, -32, -33, -33, -33, -34, + -34, -35, -35, -36, -36, -37, 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-117, + -116, -115, -115, -115, -114, -113, -111, -111, + -110, -110, -109, -109, -108, -107, -107, -106, + -105, -104, -104, -103, -102, -103, -102, -101, + -101, -100, -99, -99, -98, -97, -97, -96, + -96, -95, -94, -94, -93, -92, -92, -91, + -91, -90, -89, -88, -88, -88, -87, -86, + -85, -86, -84, -84, -83, -82, -82, -81, + -81, -80, -80, -78, -79, -77, -77, -77, + -76, -76, -75, -74, -74, -73, -72, -72, + -72, -71, -70, -70, -69, -68, -68, -68, + -66, -67, -66, -65, -65, -65, -63, -63, + -62, -62, -61, -61, -60, -60, -60, -58, + -58, -58, -56, -56, -56, -55, -54, -55, + -54, -54, -53, -52, -51, -51, -51, -50, + -49, -49, -49, -49, -48, -47, -46, -46, + -46, -46, -45, -43, -43, -43, -43, -42, + -42, -42, -40, -40, -40, -39, -39, -38, + -38, -38, -37, -37, -36, -36, -35, -35, + -34, -35, -34, -33, -33, -32, -32, -31, + -31, -31, -30, -29, -29, -29, -28, -27, + -28, -28, -27, -26, -26, -25, -25, -25, + -24, -24, -24, -23, -23, -22, -22, -22, + -21, -21, -20, -20, -20, -20, -19, -18, + -19, -18, -18, -17, -18, -17, -16, -17, + -16, -15, -15, -15, -14, -14, -15, -13, + -13, -13, -13, -12, -12, -11, -12, -11, + -12, -10, -10, -10, -10, -10, -9, -10, + -9, -9, -9, -8, -8, -7, -8, -7, + -7, -7, -6, -6, -6, -7, -6, -6, + -5, -5, -5, -5, -5, -4, -4, -5, + -4, -4, -3, -3, -3, -3, -3, -2, + -3, -2, -2, -2, -1, -2, -1, -2, + -1, -1, -1, -1, -1, 0, -1, 0, + -1, -1, 0, 0, -1, 0, 0, -1, + 1, 1, 0, 0, 0, 1, 0, 0, + 0, 0, 0, 0, 0, 0, 0, 0 + } +}; +#else /* defined(CONFIG_CSI2_PLUS) */ +static const int zoom_table[4][HRT_GDC_N] = { + { 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, + 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, + 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, + 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, + 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, + 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, + 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, + 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, + 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, + 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, + 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, + 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, + -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, + -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, + -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, + -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, + -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, + -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, -1<<4, + -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, + -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, + -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, + -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, -2<<4, + -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, + -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, + -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, + -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, -3<<4, + -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, + -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, + -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, + -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, -4<<4, + -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, + -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, -5<<4, + -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, + -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, + -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, + -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, -6<<4, + -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, + -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, + -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, + -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, -7<<4, + -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, + -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, + -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, + -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, + -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, + -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, + -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, + -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, -10<<4, + -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, + -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, + -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, + -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, + -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, + -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, + -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, + -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, + -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, + -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, + -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, + -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, + -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, + -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, + -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, + -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, + -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, + -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, + -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, + -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, + -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, + -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, + -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, + -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, + -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, + -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, -18<<4, + -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, + -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, + -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, + -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, -17<<4, + -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, + -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, -16<<4, + -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, + -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, + -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, + -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, -15<<4, + -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, + -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, -14<<4, + -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, + -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, -13<<4, + -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, + -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, -12<<4, + -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, + -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, -11<<4, + -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, + -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, -9<<4, + -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, + -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, -8<<4, + -7<<4, -7<<4, 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1<<4, + 1<<4, 1<<4, 1<<4, 1<<4, 1<<4, 1<<4, 1<<4, 1<<4, + 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, + 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, + 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, + 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, + 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, + 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4, 0<<4 + } +}; +#endif +#else +#error "sh_css_params.c: GDC version must be \ + one of {GDC_VERSION_2}" +#endif + +static const struct ia_css_dz_config default_dz_config = { + HRT_GDC_N, + HRT_GDC_N, + { \ + {0, 0}, \ + {0, 0}, \ + } +}; + +static const struct ia_css_vector default_motion_config = { + 0, + 0 +}; + +/* ------ deprecated(bz675) : from ------ */ +static const struct ia_css_shading_settings default_shading_settings = { + 1 /* enable shading table conversion in the css + (This matches the legacy way.) */ +}; +/* ------ deprecated(bz675) : to ------ */ + +struct ia_css_isp_skc_dvs_statistics { + ia_css_ptr p_data; +}; + +struct ia_css_isp_lace_statistics { + ia_css_ptr p_data; +}; + +static enum ia_css_err +ref_sh_css_ddr_address_map( + struct sh_css_ddr_address_map *map, + struct sh_css_ddr_address_map *out); + +static enum ia_css_err +write_ia_css_isp_parameter_set_info_to_ddr( + struct ia_css_isp_parameter_set_info *me, + hrt_vaddress *out); + +static enum ia_css_err +free_ia_css_isp_parameter_set_info(hrt_vaddress ptr); + +static enum ia_css_err +sh_css_params_write_to_ddr_internal( + struct ia_css_pipe *pipe, + unsigned pipe_id, + struct ia_css_isp_parameters *params, + const struct ia_css_pipeline_stage *stage, + struct sh_css_ddr_address_map *ddr_map, + struct sh_css_ddr_address_map_size *ddr_map_size); + +static enum ia_css_err +sh_css_create_isp_params(struct ia_css_stream *stream, + struct ia_css_isp_parameters **isp_params_out); + +static bool +sh_css_init_isp_params_from_global(struct ia_css_stream *stream, + struct ia_css_isp_parameters *params, + bool use_default_config, + struct ia_css_pipe *pipe_in); + +static enum ia_css_err +sh_css_init_isp_params_from_config(struct ia_css_pipe *pipe, + struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config, + struct ia_css_pipe *pipe_in); + +static enum ia_css_err +sh_css_set_global_isp_config_on_pipe( + struct ia_css_pipe *curr_pipe, + const struct ia_css_isp_config *config, + struct ia_css_pipe *pipe); + +#if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS) +static enum ia_css_err +sh_css_set_per_frame_isp_config_on_pipe( + struct ia_css_stream *stream, + const struct ia_css_isp_config *config, + struct ia_css_pipe *pipe); +#endif + +static enum ia_css_err +sh_css_update_uds_and_crop_info_based_on_zoom_region( + const struct ia_css_binary_info *info, + const struct ia_css_frame_info *in_frame_info, + const struct ia_css_frame_info *out_frame_info, + const struct ia_css_resolution *dvs_env, + const struct ia_css_dz_config *zoom, + const struct ia_css_vector *motion_vector, + struct sh_css_uds_info *uds, /* out */ + struct sh_css_crop_pos *sp_out_crop_pos, /* out */ + struct ia_css_resolution pipe_in_res, + bool enable_zoom); + +hrt_vaddress +sh_css_params_ddr_address_map(void) +{ + return sp_ddr_ptrs; +} + +/* **************************************************** + * Each coefficient is stored as 7bits to fit 2 of them into one + * ISP vector element, so we will store 4 coefficents on every + * memory word (32bits) + * + * 0: Coefficient 0 used bits + * 1: Coefficient 1 used bits + * 2: Coefficient 2 used bits + * 3: Coefficient 3 used bits + * x: not used + * + * xx33333332222222 | xx11111110000000 + * + * *************************************************** + */ +static struct ia_css_host_data * +convert_allocate_fpntbl(struct ia_css_isp_parameters *params) +{ + unsigned int i, j; + short *data_ptr; + struct ia_css_host_data *me; + unsigned int isp_format_data_size; + uint32_t *isp_format_data_ptr; + + assert(params != NULL); + + data_ptr = params->fpn_config.data; + isp_format_data_size = params->fpn_config.height * params->fpn_config.width * sizeof(uint32_t); + + me = ia_css_host_data_allocate(isp_format_data_size); + + if (!me) + return NULL; + + isp_format_data_ptr = (uint32_t *)me->address; + + for (i = 0; i < params->fpn_config.height; i++) { + for (j = 0; + j < params->fpn_config.width; + j += 4, data_ptr += 4, isp_format_data_ptr++) { + int data = data_ptr[0] << 0 | + data_ptr[1] << 7 | + data_ptr[2] << 16 | + data_ptr[3] << 23; + *isp_format_data_ptr = data; + } + } + return me; +} + +static enum ia_css_err +store_fpntbl(struct ia_css_isp_parameters *params, hrt_vaddress ptr) +{ + struct ia_css_host_data *isp_data; + + assert(params != NULL); + assert(ptr != mmgr_NULL); + + isp_data = convert_allocate_fpntbl(params); + if (!isp_data) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY); + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + } + ia_css_params_store_ia_css_host_data(ptr, isp_data); + + ia_css_host_data_free(isp_data); + return IA_CSS_SUCCESS; +} + +static void +convert_raw_to_fpn(struct ia_css_isp_parameters *params) +{ + int maxval = 0; + unsigned int i; + + assert(params != NULL); + + /* Find the maximum value in the table */ + for (i = 0; i < params->fpn_config.height * params->fpn_config.width; i++) { + int val = params->fpn_config.data[i]; + /* Make sure FPN value can be represented in 13-bit unsigned + * number (ISP precision - 1), but note that actual input range + * depends on precision of input frame data. + */ + if (val < 0) { +/* Checkpatch patch */ + val = 0; + } else if (val >= (1 << 13)) { +/* Checkpatch patch */ +/* MW: BUG, is "13" a system or application property */ + val = (1 << 13) - 1; + } + maxval = max(maxval, val); + } + /* Find the lowest shift value to remap the values in the range + * 0..maxval to 0..2^shiftval*63. + */ + params->fpn_config.shift = 0; + while (maxval > 63) { +/* MW: BUG, is "63" a system or application property */ + maxval >>= 1; + params->fpn_config.shift++; + } + /* Adjust the values in the table for the shift value */ + for (i = 0; i < params->fpn_config.height * params->fpn_config.width; i++) + ((unsigned short *) params->fpn_config.data)[i] >>= params->fpn_config.shift; +} + +static void +ia_css_process_kernel(struct ia_css_stream *stream, + struct ia_css_isp_parameters *params, + void (*process)(unsigned pipe_id, + const struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params)) +{ + int i; + for (i = 0; i < stream->num_pipes; i++) { + struct ia_css_pipe *pipe = stream->pipes[i]; + struct ia_css_pipeline *pipeline = ia_css_pipe_get_pipeline(pipe); + struct ia_css_pipeline_stage *stage; + + /* update the other buffers to the pipe specific copies */ + for (stage = pipeline->stages; stage; stage = stage->next) { + if (!stage || !stage->binary) continue; + process(pipeline->pipe_id, stage, params); + } + } +} + +static enum ia_css_err +sh_css_select_dp_10bpp_config(const struct ia_css_pipe *pipe, bool *is_dp_10bpp) { + + enum ia_css_err err = IA_CSS_SUCCESS; + /* Currently we check if 10bpp DPC configuration is required based + * on the use case,i.e. if BDS and DPC is both enabled. The more cleaner + * design choice would be to expose the type of DPC (either 10bpp or 13bpp) + * using the binary info, but the current control flow does not allow this + * implementation. (This is because the configuration is set before a + * binary is selected, and the binary info is not available) + */ + if((pipe == NULL) || (is_dp_10bpp == NULL)) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INTERNAL_ERROR); + err = IA_CSS_ERR_INTERNAL_ERROR; + } else { + *is_dp_10bpp = false; + + /* check if DPC is enabled from the host */ + if (pipe->config.enable_dpc) { + /*check if BDS is enabled*/ + unsigned int required_bds_factor = SH_CSS_BDS_FACTOR_1_00; + if ((pipe->config.bayer_ds_out_res.width != 0) && + (pipe->config.bayer_ds_out_res.height != 0)) { + if (IA_CSS_SUCCESS == binarydesc_calculate_bds_factor( + pipe->config.input_effective_res, + pipe->config.bayer_ds_out_res, + &required_bds_factor)) { + if (SH_CSS_BDS_FACTOR_1_00 != required_bds_factor) { + /*we use 10bpp BDS configuration*/ + *is_dp_10bpp = true; + } + } + } + } + } + + return err; +} + +enum ia_css_err +sh_css_set_black_frame(struct ia_css_stream *stream, + const struct ia_css_frame *raw_black_frame) +{ + struct ia_css_isp_parameters *params; + /* this function desperately needs to be moved to the ISP or SP such + * that it can use the DMA. + */ + unsigned int height, width, y, x, k, data; + hrt_vaddress ptr; + + assert(stream != NULL); + assert(raw_black_frame != NULL); + + params = stream->isp_params_configs; + height = raw_black_frame->info.res.height; + width = raw_black_frame->info.padded_width, + + ptr = raw_black_frame->data + + raw_black_frame->planes.raw.offset; + + IA_CSS_ENTER_PRIVATE("black_frame=%p", raw_black_frame); + + if (params->fpn_config.data && + (params->fpn_config.width != width || params->fpn_config.height != height)) { + sh_css_free(params->fpn_config.data); + params->fpn_config.data = NULL; + } + if (params->fpn_config.data == NULL) { + params->fpn_config.data = sh_css_malloc(height * width * sizeof(short)); + if (!params->fpn_config.data) { + IA_CSS_ERROR("out of memory"); + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY); + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + } + params->fpn_config.width = width; + params->fpn_config.height = height; + params->fpn_config.shift = 0; + } + + /* store raw to fpntbl */ + for (y = 0; y < height; y++) { + for (x = 0; x < width; x += (ISP_VEC_NELEMS * 2)) { + int ofs = y * width + x; + for (k = 0; k < ISP_VEC_NELEMS; k += 2) { + mmgr_load(ptr, (void *)(&data), sizeof(int)); + params->fpn_config.data[ofs + 2 * k] = + (short) (data & 0xFFFF); + params->fpn_config.data[ofs + 2 * k + 2] = + (short) ((data >> 16) & 0xFFFF); + ptr += sizeof(int); /* byte system address */ + } + for (k = 0; k < ISP_VEC_NELEMS; k += 2) { + mmgr_load(ptr, (void *)(&data), sizeof(int)); + params->fpn_config.data[ofs + 2 * k + 1] = + (short) (data & 0xFFFF); + params->fpn_config.data[ofs + 2 * k + 3] = + (short) ((data >> 16) & 0xFFFF); + ptr += sizeof(int); /* byte system address */ + } + } + } + + /* raw -> fpn */ + convert_raw_to_fpn(params); + + /* overwrite isp parameter */ + ia_css_process_kernel(stream, params, ia_css_kernel_process_param[IA_CSS_FPN_ID]); + + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + + return IA_CSS_SUCCESS; +} + +bool +sh_css_params_set_binning_factor(struct ia_css_stream *stream, unsigned int binning_fact) +{ + struct ia_css_isp_parameters *params; + + IA_CSS_ENTER_PRIVATE("void"); + assert(stream != NULL); + + params = stream->isp_params_configs; + + if (params->sensor_binning != binning_fact) { + params->sensor_binning = binning_fact; + params->sc_table_changed = true; + } + + IA_CSS_LEAVE_PRIVATE("void"); + + return params->sc_table_changed; +} + +static void +sh_css_update_shading_table_status(struct ia_css_pipe *pipe, + struct ia_css_isp_parameters *params) +{ + if (params && pipe && (pipe->pipe_num != params->sc_table_last_pipe_num)) { + params->sc_table_dirty = true; + params->sc_table_last_pipe_num = pipe->pipe_num; + } +} + +static void +sh_css_set_shading_table(struct ia_css_stream *stream, + struct ia_css_isp_parameters *params, + const struct ia_css_shading_table *table) +{ + IA_CSS_ENTER_PRIVATE(""); + if (table == NULL) + return; + assert(stream != NULL); + + if (!table->enable) + table = NULL; + + if ((table != params->sc_table) || params->sc_table_dirty) { + params->sc_table = table; + params->sc_table_changed = true; + params->sc_table_dirty = false; + /* Not very clean, this goes to sh_css.c to invalidate the + * shading table for all pipes. Should replaced by a loop + * and a pipe-specific call. + */ + if (!params->output_frame) + sh_css_invalidate_shading_tables(stream); + } + + IA_CSS_LEAVE_PRIVATE("void"); +} + +void +ia_css_params_store_ia_css_host_data( + hrt_vaddress ddr_addr, + struct ia_css_host_data *data) +{ + assert(data != NULL); + assert(data->address != NULL); + assert(ddr_addr != mmgr_NULL); + + IA_CSS_ENTER_PRIVATE(""); + + mmgr_store(ddr_addr, + (void *)(data->address), + (size_t)data->size); + + IA_CSS_LEAVE_PRIVATE("void"); +} + +struct ia_css_host_data * +ia_css_params_alloc_convert_sctbl( + const struct ia_css_pipeline_stage *stage, + const struct ia_css_shading_table *shading_table) +{ + const struct ia_css_binary *binary = stage->binary; + struct ia_css_host_data *sctbl; + unsigned int i, j, aligned_width, row_padding; + unsigned int sctbl_size; + short int *ptr; + + assert(binary != NULL); + assert(shading_table != NULL); + + IA_CSS_ENTER_PRIVATE(""); + + if (shading_table == NULL) { + IA_CSS_LEAVE_PRIVATE("void"); + return NULL; + } + + aligned_width = binary->sctbl_aligned_width_per_color; + row_padding = aligned_width - shading_table->width; + sctbl_size = shading_table->height * IA_CSS_SC_NUM_COLORS * aligned_width * sizeof(short); + + sctbl = ia_css_host_data_allocate((size_t)sctbl_size); + + if (!sctbl) + return NULL; + ptr = (short int*)sctbl->address; + memset(ptr, + 0, + sctbl_size); + + for (i = 0; i < shading_table->height; i++) { + for (j = 0; j < IA_CSS_SC_NUM_COLORS; j++) { + memcpy(ptr, + &shading_table->data[j] + [i*shading_table->width], + shading_table->width * sizeof(short)); + ptr += aligned_width; + } + } + + IA_CSS_LEAVE_PRIVATE("void"); + return sctbl; +} + +enum ia_css_err ia_css_params_store_sctbl( + const struct ia_css_pipeline_stage *stage, + hrt_vaddress sc_tbl, + const struct ia_css_shading_table *sc_config) +{ + struct ia_css_host_data *isp_sc_tbl; + + IA_CSS_ENTER_PRIVATE(""); + + if (sc_config == NULL) { + IA_CSS_LEAVE_PRIVATE("void"); + return IA_CSS_SUCCESS; + } + + isp_sc_tbl = ia_css_params_alloc_convert_sctbl(stage, sc_config); + if (!isp_sc_tbl) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY); + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + } + /* store the shading table to ddr */ + ia_css_params_store_ia_css_host_data(sc_tbl, isp_sc_tbl); + ia_css_host_data_free(isp_sc_tbl); + + IA_CSS_LEAVE_PRIVATE("void"); + + return IA_CSS_SUCCESS; +} + +static void +sh_css_enable_pipeline(const struct ia_css_binary *binary) +{ + if (!binary) + return; + + IA_CSS_ENTER_PRIVATE(""); + + ia_css_isp_param_enable_pipeline(&binary->mem_params); + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static enum ia_css_err +ia_css_process_zoom_and_motion( + struct ia_css_isp_parameters *params, + const struct ia_css_pipeline_stage *first_stage) +{ + /* first_stage can be NULL */ + const struct ia_css_pipeline_stage *stage; + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_resolution pipe_in_res; + pipe_in_res.width = 0; + pipe_in_res.height = 0; + + assert(params != NULL); + + IA_CSS_ENTER_PRIVATE(""); + + /* Go through all stages to udate uds and cropping */ + for (stage = first_stage; stage; stage = stage->next) { + + struct ia_css_binary *binary; + /* note: the var below is made static as it is quite large; + if it is not static it ends up on the stack which could + cause issues for drivers + */ + static struct ia_css_binary tmp_binary; + + const struct ia_css_binary_xinfo *info = NULL; + + binary = stage->binary; + if (binary) { + info = binary->info; + } else { + const struct sh_css_binary_args *args = &stage->args; + const struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS] = {NULL}; + if (args->out_frame[0]) + out_infos[0] = &args->out_frame[0]->info; + info = &stage->firmware->info.isp; + ia_css_binary_fill_info(info, false, false, + IA_CSS_STREAM_FORMAT_RAW_10, + args->in_frame ? &args->in_frame->info : NULL, + NULL, + out_infos, + args->out_vf_frame ? &args->out_vf_frame->info + : NULL, + &tmp_binary, + NULL, + -1, true); + binary = &tmp_binary; + binary->info = info; + } + + if (stage == first_stage) { + /* we will use pipe_in_res to scale the zoom crop region if needed */ + pipe_in_res = binary->effective_in_frame_res; + } + + assert(stage->stage_num < SH_CSS_MAX_STAGES); + if (params->dz_config.zoom_region.resolution.width == 0 && + params->dz_config.zoom_region.resolution.height == 0) { + sh_css_update_uds_and_crop_info( + &info->sp, + &binary->in_frame_info, + &binary->out_frame_info[0], + &binary->dvs_envelope, + ¶ms->dz_config, + ¶ms->motion_config, + ¶ms->uds[stage->stage_num].uds, + ¶ms->uds[stage->stage_num].crop_pos, + stage->enable_zoom); + } else { + err = sh_css_update_uds_and_crop_info_based_on_zoom_region( + &info->sp, + &binary->in_frame_info, + &binary->out_frame_info[0], + &binary->dvs_envelope, + ¶ms->dz_config, + ¶ms->motion_config, + ¶ms->uds[stage->stage_num].uds, + ¶ms->uds[stage->stage_num].crop_pos, + pipe_in_res, + stage->enable_zoom); + if (err != IA_CSS_SUCCESS) + return err; + } + } + params->isp_params_changed = true; + + IA_CSS_LEAVE_PRIVATE("void"); + return err; +} + +static void +sh_css_set_gamma_table(struct ia_css_isp_parameters *params, + const struct ia_css_gamma_table *table) +{ + if (table == NULL) + return; + IA_CSS_ENTER_PRIVATE("table=%p", table); + + assert(params != NULL); + params->gc_table = *table; + params->config_changed[IA_CSS_GC_ID] = true; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_get_gamma_table(const struct ia_css_isp_parameters *params, + struct ia_css_gamma_table *table) +{ + if (table == NULL) + return; + IA_CSS_ENTER_PRIVATE("table=%p", table); + + assert(params != NULL); + *table = params->gc_table; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_set_ctc_table(struct ia_css_isp_parameters *params, + const struct ia_css_ctc_table *table) +{ + if (table == NULL) + return; + + IA_CSS_ENTER_PRIVATE("table=%p", table); + + assert(params != NULL); + params->ctc_table = *table; + params->config_changed[IA_CSS_CTC_ID] = true; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_get_ctc_table(const struct ia_css_isp_parameters *params, + struct ia_css_ctc_table *table) +{ + if (table == NULL) + return; + + IA_CSS_ENTER_PRIVATE("table=%p", table); + + assert(params != NULL); + *table = params->ctc_table; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_set_macc_table(struct ia_css_isp_parameters *params, + const struct ia_css_macc_table *table) +{ + if (table == NULL) + return; + + IA_CSS_ENTER_PRIVATE("table=%p", table); + + assert(params != NULL); + params->macc_table = *table; + params->config_changed[IA_CSS_MACC_ID] = true; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_get_macc_table(const struct ia_css_isp_parameters *params, + struct ia_css_macc_table *table) +{ + if (table == NULL) + return; + + IA_CSS_ENTER_PRIVATE("table=%p", table); + + assert(params != NULL); + *table = params->macc_table; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +void ia_css_morph_table_free( + struct ia_css_morph_table *me) +{ + + unsigned int i; + + if (me == NULL) + return; + + IA_CSS_ENTER(""); + + + + for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) { + if (me->coordinates_x[i]) { + sh_css_free(me->coordinates_x[i]); + me->coordinates_x[i] = NULL; + } + if (me->coordinates_y[i]) { + sh_css_free(me->coordinates_y[i]); + me->coordinates_y[i] = NULL; + } + } + + sh_css_free(me); + IA_CSS_LEAVE("void"); + +} + + +struct ia_css_morph_table *ia_css_morph_table_allocate( + unsigned int width, + unsigned int height) +{ + + unsigned int i; + struct ia_css_morph_table *me; + + IA_CSS_ENTER(""); + + me = sh_css_malloc(sizeof(*me)); + if (me == NULL) { + IA_CSS_ERROR("out of memory"); + return me; + } + + for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) { + me->coordinates_x[i] = NULL; + me->coordinates_y[i] = NULL; + } + + for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) { + me->coordinates_x[i] = + sh_css_malloc(height * width * + sizeof(*me->coordinates_x[i])); + me->coordinates_y[i] = + sh_css_malloc(height * width * + sizeof(*me->coordinates_y[i])); + + if ((me->coordinates_x[i] == NULL) || + (me->coordinates_y[i] == NULL)) { + ia_css_morph_table_free(me); + me = NULL; + return me; + } + } + me->width = width; + me->height = height; + IA_CSS_LEAVE(""); + return me; + +} + + +static enum ia_css_err sh_css_params_default_morph_table( + struct ia_css_morph_table **table, + const struct ia_css_binary *binary) +{ + /* MW 2400 advanced requires different scaling */ + unsigned int i, j, k, step, width, height; + short start_x[IA_CSS_MORPH_TABLE_NUM_PLANES] = { -8, 0, -8, 0, 0, -8 }, + start_y[IA_CSS_MORPH_TABLE_NUM_PLANES] = { 0, 0, -8, -8, -8, 0 }; + struct ia_css_morph_table *tab; + + assert(table != NULL); + assert(binary != NULL); + + IA_CSS_ENTER_PRIVATE(""); + + step = (ISP_VEC_NELEMS / 16) * 128, + width = binary->morph_tbl_width, + height = binary->morph_tbl_height; + + tab = ia_css_morph_table_allocate(width, height); + if (tab == NULL) + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + + for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) { + short val_y = start_y[i]; + for (j = 0; j < height; j++) { + short val_x = start_x[i]; + unsigned short *x_ptr, *y_ptr; + + x_ptr = &tab->coordinates_x[i][j * width]; + y_ptr = &tab->coordinates_y[i][j * width]; + for (k = 0; k < width; + k++, x_ptr++, y_ptr++, val_x += (short)step) { + if (k == 0) + *x_ptr = 0; + else if (k == width - 1) + *x_ptr = val_x + 2 * start_x[i]; + else + *x_ptr = val_x; + if (j == 0) + *y_ptr = 0; + else + *y_ptr = val_y; + } + val_y += (short)step; + } + } + *table = tab; + + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + + return IA_CSS_SUCCESS; +} + +static void +sh_css_set_morph_table(struct ia_css_isp_parameters *params, + const struct ia_css_morph_table *table) +{ + if (table == NULL) + return; + + IA_CSS_ENTER_PRIVATE("table=%p", table); + + assert(params != NULL); + if (table->enable == false) + table = NULL; + params->morph_table = table; + params->morph_table_changed = true; + IA_CSS_LEAVE_PRIVATE("void"); +} + +void +ia_css_translate_3a_statistics( + struct ia_css_3a_statistics *host_stats, + const struct ia_css_isp_3a_statistics_map *isp_stats) +{ + IA_CSS_ENTER(""); + if (host_stats->grid.use_dmem) { + IA_CSS_LOG("3A: DMEM"); + ia_css_s3a_dmem_decode(host_stats, isp_stats->dmem_stats); + } else { + IA_CSS_LOG("3A: VMEM"); + ia_css_s3a_vmem_decode(host_stats, isp_stats->vmem_stats_hi, + isp_stats->vmem_stats_lo); + } +#if !defined(HAS_NO_HMEM) + IA_CSS_LOG("3A: HMEM"); + ia_css_s3a_hmem_decode(host_stats, isp_stats->hmem_stats); +#endif + + IA_CSS_LEAVE("void"); +} + +void +ia_css_isp_3a_statistics_map_free(struct ia_css_isp_3a_statistics_map *me) +{ + if (me) { + if (me->data_allocated) { + sh_css_free(me->data_ptr); + me->data_ptr = NULL; + me->data_allocated = false; + } + sh_css_free(me); + } +} + +struct ia_css_isp_3a_statistics_map * +ia_css_isp_3a_statistics_map_allocate( + const struct ia_css_isp_3a_statistics *isp_stats, + void *data_ptr) +{ + struct ia_css_isp_3a_statistics_map *me; + /* Windows compiler does not like adding sizes to a void * + * so we use a local char * instead. */ + char *base_ptr; + + me = sh_css_malloc(sizeof(*me)); + if (!me) { + IA_CSS_LEAVE("cannot allocate memory"); + goto err; + } + + me->data_ptr = data_ptr; + me->data_allocated = data_ptr == NULL; + if (!data_ptr) { + me->data_ptr = sh_css_malloc(isp_stats->size); + if (!me->data_ptr) { + IA_CSS_LEAVE("cannot allocate memory"); + goto err; + } + } + base_ptr = me->data_ptr; + + me->size = isp_stats->size; + /* GCC complains when we assign a char * to a void *, so these + * casts are necessary unfortunately. */ + me->dmem_stats = (void *)base_ptr; + me->vmem_stats_hi = (void *)(base_ptr + isp_stats->dmem_size); + me->vmem_stats_lo = (void *)(base_ptr + isp_stats->dmem_size + + isp_stats->vmem_size); + me->hmem_stats = (void *)(base_ptr + isp_stats->dmem_size + + 2 * isp_stats->vmem_size); + + IA_CSS_LEAVE("map=%p", me); + return me; + +err: + if (me) + sh_css_free(me); + return NULL; + +} + +enum ia_css_err +ia_css_get_3a_statistics(struct ia_css_3a_statistics *host_stats, + const struct ia_css_isp_3a_statistics *isp_stats) +{ + struct ia_css_isp_3a_statistics_map *map; + enum ia_css_err ret = IA_CSS_SUCCESS; + + IA_CSS_ENTER("host_stats=%p, isp_stats=%p", host_stats, isp_stats); + + assert(host_stats != NULL); + assert(isp_stats != NULL); + + map = ia_css_isp_3a_statistics_map_allocate(isp_stats, NULL); + if (map) { + mmgr_load(isp_stats->data_ptr, map->data_ptr, isp_stats->size); + ia_css_translate_3a_statistics(host_stats, map); + ia_css_isp_3a_statistics_map_free(map); + } else { + IA_CSS_ERROR("out of memory"); + ret = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + } + + IA_CSS_LEAVE_ERR(ret); + return ret; +} + +/* Parameter encoding is not yet orthogonal. + This function hnadles some of the exceptions. +*/ +static void +ia_css_set_param_exceptions(const struct ia_css_pipe *pipe, + struct ia_css_isp_parameters *params) +{ + assert(params != NULL); + + /* Copy also to DP. Should be done by the driver. */ + params->dp_config.gr = params->wb_config.gr; + params->dp_config.r = params->wb_config.r; + params->dp_config.b = params->wb_config.b; + params->dp_config.gb = params->wb_config.gb; +#ifdef ISP2401 + assert(pipe != NULL); + assert(pipe->mode < IA_CSS_PIPE_ID_NUM); + + if (pipe->mode < IA_CSS_PIPE_ID_NUM) { + params->pipe_dp_config[pipe->mode].gr = params->wb_config.gr; + params->pipe_dp_config[pipe->mode].r = params->wb_config.r; + params->pipe_dp_config[pipe->mode].b = params->wb_config.b; + params->pipe_dp_config[pipe->mode].gb = params->wb_config.gb; + } +#endif +} + +#ifdef ISP2401 +static void +sh_css_set_dp_config(const struct ia_css_pipe *pipe, + struct ia_css_isp_parameters *params, + const struct ia_css_dp_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + assert(pipe != NULL); + assert(pipe->mode < IA_CSS_PIPE_ID_NUM); + + IA_CSS_ENTER_PRIVATE("config=%p", config); + ia_css_dp_debug_dtrace(config, IA_CSS_DEBUG_TRACE_PRIVATE); + if (pipe->mode < IA_CSS_PIPE_ID_NUM) { + params->pipe_dp_config[pipe->mode] = *config; + params->pipe_dpc_config_changed[pipe->mode] = true; + } + IA_CSS_LEAVE_PRIVATE("void"); +} +#endif + +static void +sh_css_get_dp_config(const struct ia_css_pipe *pipe, + const struct ia_css_isp_parameters *params, + struct ia_css_dp_config *config) +{ + if (config == NULL) + return; + + assert(params != NULL); + assert(pipe != NULL); + IA_CSS_ENTER_PRIVATE("config=%p", config); + + *config = params->pipe_dp_config[pipe->mode]; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_set_nr_config(struct ia_css_isp_parameters *params, + const struct ia_css_nr_config *config) +{ + if (config == NULL) + return; + assert(params != NULL); + + IA_CSS_ENTER_PRIVATE("config=%p", config); + + ia_css_nr_debug_dtrace(config, IA_CSS_DEBUG_TRACE_PRIVATE); + params->nr_config = *config; + params->yee_config.nr = *config; + params->config_changed[IA_CSS_NR_ID] = true; + params->config_changed[IA_CSS_YEE_ID] = true; + params->config_changed[IA_CSS_BNR_ID] = true; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_set_ee_config(struct ia_css_isp_parameters *params, + const struct ia_css_ee_config *config) +{ + if (config == NULL) + return; + assert(params != NULL); + + IA_CSS_ENTER_PRIVATE("config=%p", config); + ia_css_ee_debug_dtrace(config, IA_CSS_DEBUG_TRACE_PRIVATE); + + params->ee_config = *config; + params->yee_config.ee = *config; + params->config_changed[IA_CSS_YEE_ID] = true; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_get_ee_config(const struct ia_css_isp_parameters *params, + struct ia_css_ee_config *config) +{ + if (config == NULL) + return; + + IA_CSS_ENTER_PRIVATE("config=%p", config); + + assert(params != NULL); + *config = params->ee_config; + + ia_css_ee_debug_dtrace(config, IA_CSS_DEBUG_TRACE_PRIVATE); + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_set_pipe_dvs_6axis_config(const struct ia_css_pipe *pipe, + struct ia_css_isp_parameters *params, + const struct ia_css_dvs_6axis_config *dvs_config) +{ + if (dvs_config == NULL) + return; + assert(params != NULL); + assert(pipe != NULL); + assert(dvs_config->height_y == dvs_config->height_uv); + assert((dvs_config->width_y - 1) == 2 * (dvs_config->width_uv - 1)); + assert(pipe->mode < IA_CSS_PIPE_ID_NUM); + + IA_CSS_ENTER_PRIVATE("dvs_config=%p", dvs_config); + + copy_dvs_6axis_table(params->pipe_dvs_6axis_config[pipe->mode], dvs_config); + +#if !defined(HAS_NO_DVS_6AXIS_CONFIG_UPDATE) + params->pipe_dvs_6axis_config_changed[pipe->mode] = true; +#endif + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_get_pipe_dvs_6axis_config(const struct ia_css_pipe *pipe, + const struct ia_css_isp_parameters *params, + struct ia_css_dvs_6axis_config *dvs_config) +{ + if (dvs_config == NULL) + return; + assert(params != NULL); + assert(pipe != NULL); + assert(dvs_config->height_y == dvs_config->height_uv); + assert((dvs_config->width_y - 1) == 2 * dvs_config->width_uv - 1); + + IA_CSS_ENTER_PRIVATE("dvs_config=%p", dvs_config); + + if ((pipe->mode < IA_CSS_PIPE_ID_NUM) && + (dvs_config->width_y == params->pipe_dvs_6axis_config[pipe->mode]->width_y) && + (dvs_config->height_y == params->pipe_dvs_6axis_config[pipe->mode]->height_y) && + (dvs_config->width_uv == params->pipe_dvs_6axis_config[pipe->mode]->width_uv) && + (dvs_config->height_uv == params->pipe_dvs_6axis_config[pipe->mode]->height_uv) && + dvs_config->xcoords_y && + dvs_config->ycoords_y && + dvs_config->xcoords_uv && + dvs_config->ycoords_uv) + { + copy_dvs_6axis_table(dvs_config, params->pipe_dvs_6axis_config[pipe->mode]); + } + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_set_baa_config(struct ia_css_isp_parameters *params, + const struct ia_css_aa_config *config) +{ + if (config == NULL) + return; + assert(params != NULL); + + IA_CSS_ENTER_PRIVATE("config=%p", config); + ia_css_aa_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + + params->bds_config = *config; + params->config_changed[IA_CSS_BDS_ID] = true; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_get_baa_config(const struct ia_css_isp_parameters *params, + struct ia_css_aa_config *config) +{ + if (config == NULL) + return; + assert(params != NULL); + + IA_CSS_ENTER_PRIVATE("config=%p", config); + + *config = params->bds_config; + + ia_css_aa_debug_dtrace(config, IA_CSS_DEBUG_TRACE); + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_set_dz_config(struct ia_css_isp_parameters *params, + const struct ia_css_dz_config *config) +{ + if (config == NULL) + return; + assert(params != NULL); + + IA_CSS_ENTER_PRIVATE("dx=%d, dy=%d", config->dx, config->dy); + + assert(config->dx <= HRT_GDC_N); + assert(config->dy <= HRT_GDC_N); + + params->dz_config = *config; + params->dz_config_changed = true; + /* JK: Why isp params changed?? */ + params->isp_params_changed = true; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_get_dz_config(const struct ia_css_isp_parameters *params, + struct ia_css_dz_config *config) +{ + if (config == NULL) + return; + assert(params != NULL); + + IA_CSS_ENTER_PRIVATE("config=%p", config); + + *config = params->dz_config; + + IA_CSS_LEAVE_PRIVATE("dx=%d, dy=%d", config->dx, config->dy); +} + +static void +sh_css_set_motion_vector(struct ia_css_isp_parameters *params, + const struct ia_css_vector *motion) +{ + if (motion == NULL) + return; + assert(params != NULL); + + IA_CSS_ENTER_PRIVATE("x=%d, y=%d", motion->x, motion->y); + + params->motion_config = *motion; + /* JK: Why do isp params change? */ + params->motion_config_changed = true; + params->isp_params_changed = true; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +sh_css_get_motion_vector(const struct ia_css_isp_parameters *params, + struct ia_css_vector *motion) +{ + if (motion == NULL) + return; + assert(params != NULL); + + IA_CSS_ENTER_PRIVATE("motion=%p", motion); + + *motion = params->motion_config; + + IA_CSS_LEAVE_PRIVATE("x=%d, y=%d", motion->x, motion->y); +} + +struct ia_css_isp_config * +sh_css_pipe_isp_config_get(struct ia_css_pipe *pipe) +{ + if (pipe == NULL) + { + IA_CSS_ERROR("pipe=%p", NULL); + return NULL; + } + return pipe->config.p_isp_config; +} + +enum ia_css_err +ia_css_stream_set_isp_config( + struct ia_css_stream *stream, + const struct ia_css_isp_config *config) +{ + return ia_css_stream_set_isp_config_on_pipe(stream, config, NULL); +} + +enum ia_css_err +ia_css_stream_set_isp_config_on_pipe( + struct ia_css_stream *stream, + const struct ia_css_isp_config *config, + struct ia_css_pipe *pipe) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + if ((stream == NULL) || (config == NULL)) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + IA_CSS_ENTER("stream=%p, config=%p, pipe=%p", stream, config, pipe); + +#if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS) + if (config->output_frame) + err = sh_css_set_per_frame_isp_config_on_pipe(stream, config, pipe); + else +#endif + err = sh_css_set_global_isp_config_on_pipe(stream->pipes[0], config, pipe); + + IA_CSS_LEAVE_ERR(err); + return err; +} + +enum ia_css_err +ia_css_pipe_set_isp_config(struct ia_css_pipe *pipe, + struct ia_css_isp_config *config) +{ + struct ia_css_pipe *pipe_in = pipe; + enum ia_css_err err = IA_CSS_SUCCESS; + + IA_CSS_ENTER("pipe=%p", pipe); + + if ((pipe == NULL) || (pipe->stream == NULL)) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "config=%p\n", config); + +#if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS) + if (config->output_frame) + err = sh_css_set_per_frame_isp_config_on_pipe(pipe->stream, config, pipe); + else +#endif + err = sh_css_set_global_isp_config_on_pipe(pipe, config, pipe_in); + IA_CSS_LEAVE_ERR(err); + return err; +} + +static enum ia_css_err +sh_css_set_global_isp_config_on_pipe( + struct ia_css_pipe *curr_pipe, + const struct ia_css_isp_config *config, + struct ia_css_pipe *pipe) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + enum ia_css_err err1 = IA_CSS_SUCCESS; + enum ia_css_err err2 = IA_CSS_SUCCESS; + + IA_CSS_ENTER_PRIVATE("stream=%p, config=%p, pipe=%p", curr_pipe, config, pipe); + + err1 = sh_css_init_isp_params_from_config(curr_pipe, curr_pipe->stream->isp_params_configs, config, pipe); + + /* Now commit all changes to the SP */ + err2 = sh_css_param_update_isp_params(curr_pipe, curr_pipe->stream->isp_params_configs, sh_css_sp_is_running(), pipe); + + /* The following code is intentional. The sh_css_init_isp_params_from_config interface + * throws an error when both DPC and BDS is enabled. The CSS API must pass this error + * information to the caller, ie. the host. We do not return this error immediately, + * but instead continue with updating the ISP params to enable testing of features + * which are currently in TR phase. */ + + err = (err1 != IA_CSS_SUCCESS ) ? err1 : ((err2 != IA_CSS_SUCCESS) ? err2 : err); + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +#if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS) +static enum ia_css_err +sh_css_set_per_frame_isp_config_on_pipe( + struct ia_css_stream *stream, + const struct ia_css_isp_config *config, + struct ia_css_pipe *pipe) +{ + unsigned i; + bool per_frame_config_created = false; + enum ia_css_err err = IA_CSS_SUCCESS; + enum ia_css_err err1 = IA_CSS_SUCCESS; + enum ia_css_err err2 = IA_CSS_SUCCESS; + enum ia_css_err err3 = IA_CSS_SUCCESS; + + struct sh_css_ddr_address_map *ddr_ptrs; + struct sh_css_ddr_address_map_size *ddr_ptrs_size; + struct ia_css_isp_parameters *params; + + IA_CSS_ENTER_PRIVATE("stream=%p, config=%p, pipe=%p", stream, config, pipe); + + if (!pipe) { + err = IA_CSS_ERR_INVALID_ARGUMENTS; + goto exit; + } + + /* create per-frame ISP params object with default values + * from stream->isp_params_configs if one doesn't already exist + */ + if (!stream->per_frame_isp_params_configs) + { + err = sh_css_create_isp_params(stream, + &stream->per_frame_isp_params_configs); + if(err != IA_CSS_SUCCESS) + goto exit; + per_frame_config_created = true; + } + + params = stream->per_frame_isp_params_configs; + + /* update new ISP params object with the new config */ + if (!sh_css_init_isp_params_from_global(stream, params, false, pipe)) { + err1 = IA_CSS_ERR_INVALID_ARGUMENTS; + } + + err2 = sh_css_init_isp_params_from_config(stream->pipes[0], params, config, pipe); + + if (per_frame_config_created) + { + ddr_ptrs = ¶ms->ddr_ptrs; + ddr_ptrs_size = ¶ms->ddr_ptrs_size; + /* create per pipe reference to general ddr_ptrs */ + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { + ref_sh_css_ddr_address_map(ddr_ptrs, ¶ms->pipe_ddr_ptrs[i]); + params->pipe_ddr_ptrs_size[i] = *ddr_ptrs_size; + } + } + + /* now commit to ddr */ + err3 = sh_css_param_update_isp_params(stream->pipes[0], params, sh_css_sp_is_running(), pipe); + + /* The following code is intentional. The sh_css_init_sp_params_from_config and + * sh_css_init_isp_params_from_config throws an error when both DPC and BDS is enabled. + * The CSS API must pass this error information to the caller, ie. the host. + * We do not return this error immediately, but instead continue with updating the ISP params + * to enable testing of features which are currently in TR phase. */ + err = (err1 != IA_CSS_SUCCESS) ? err1 : + (err2 != IA_CSS_SUCCESS) ? err2 : + (err3 != IA_CSS_SUCCESS) ? err3 : err; +exit: + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} +#endif + +static enum ia_css_err +sh_css_init_isp_params_from_config(struct ia_css_pipe *pipe, + struct ia_css_isp_parameters *params, + const struct ia_css_isp_config *config, + struct ia_css_pipe *pipe_in) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + bool is_dp_10bpp = true; + assert(pipe != NULL); + + IA_CSS_ENTER_PRIVATE("pipe=%p, config=%p, params=%p", pipe, config, params); + + ia_css_set_configs(params, config); + + + sh_css_set_nr_config(params, config->nr_config); + sh_css_set_ee_config(params, config->ee_config); + sh_css_set_baa_config(params, config->baa_config); + if ((pipe->mode < IA_CSS_PIPE_ID_NUM) && + (params->pipe_dvs_6axis_config[pipe->mode])) + sh_css_set_pipe_dvs_6axis_config(pipe, params, config->dvs_6axis_config); + sh_css_set_dz_config(params, config->dz_config); + sh_css_set_motion_vector(params, config->motion_vector); + sh_css_update_shading_table_status(pipe_in, params); + sh_css_set_shading_table(pipe->stream, params, config->shading_table); + sh_css_set_morph_table(params, config->morph_table); + sh_css_set_macc_table(params, config->macc_table); + sh_css_set_gamma_table(params, config->gamma_table); + sh_css_set_ctc_table(params, config->ctc_table); +/* ------ deprecated(bz675) : from ------ */ + sh_css_set_shading_settings(params, config->shading_settings); +/* ------ deprecated(bz675) : to ------ */ + + params->dis_coef_table_changed = (config->dvs_coefs != NULL); + params->dvs2_coef_table_changed = (config->dvs2_coefs != NULL); + + params->output_frame = config->output_frame; + params->isp_parameters_id = config->isp_config_id; +#ifdef ISP2401 + /* Currently we do not offer CSS interface to set different + * configurations for DPC, i.e. depending on DPC being enabled + * before (NORM+OBC) or after. The folllowing code to set the + * DPC configuration should be updated when this interface is made + * available */ + sh_css_set_dp_config(pipe, params, config->dp_config); + ia_css_set_param_exceptions(pipe, params); +#endif + + if (IA_CSS_SUCCESS == + sh_css_select_dp_10bpp_config(pipe, &is_dp_10bpp)) { + /* return an error when both DPC and BDS is enabled by the + * user. */ + /* we do not exit from this point immediately to allow internal + * firmware feature testing. */ + if(is_dp_10bpp) { + err = IA_CSS_ERR_INVALID_ARGUMENTS; + } + } else { + err = IA_CSS_ERR_INTERNAL_ERROR; + goto exit; + } + +#ifndef ISP2401 + ia_css_set_param_exceptions(pipe, params); +#endif +exit: + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +void +ia_css_stream_get_isp_config( + const struct ia_css_stream *stream, + struct ia_css_isp_config *config) +{ + IA_CSS_ENTER("void"); + ia_css_pipe_get_isp_config(stream->pipes[0], config); + IA_CSS_LEAVE("void"); +} + +void +ia_css_pipe_get_isp_config(struct ia_css_pipe *pipe, + struct ia_css_isp_config *config) +{ + struct ia_css_isp_parameters *params = NULL; + + assert(config != NULL); + + IA_CSS_ENTER("config=%p", config); + + params = pipe->stream->isp_params_configs; + assert(params != NULL); + + ia_css_get_configs(params, config); + + sh_css_get_ee_config(params, config->ee_config); + sh_css_get_baa_config(params, config->baa_config); + sh_css_get_pipe_dvs_6axis_config(pipe, params, config->dvs_6axis_config); + sh_css_get_dp_config(pipe, params, config->dp_config); + sh_css_get_macc_table(params, config->macc_table); + sh_css_get_gamma_table(params, config->gamma_table); + sh_css_get_ctc_table(params, config->ctc_table); + sh_css_get_dz_config(params, config->dz_config); + sh_css_get_motion_vector(params, config->motion_vector); +/* ------ deprecated(bz675) : from ------ */ + sh_css_get_shading_settings(params, config->shading_settings); +/* ------ deprecated(bz675) : to ------ */ + + config->output_frame = params->output_frame; + config->isp_config_id = params->isp_parameters_id; + + IA_CSS_LEAVE("void"); +} + +#ifndef ISP2401 +/* + * coding style says the return of "mmgr_NULL" is the error signal + * + * Deprecated: Implement mmgr_realloc() + */ +static bool realloc_isp_css_mm_buf( + hrt_vaddress *curr_buf, + size_t *curr_size, + size_t needed_size, + bool force, + enum ia_css_err *err, + uint16_t mmgr_attribute) +{ + int32_t id; + + *err = IA_CSS_SUCCESS; + /* Possible optimization: add a function sh_css_isp_css_mm_realloc() + * and implement on top of hmm. */ + + IA_CSS_ENTER_PRIVATE("void"); + + if (!force && *curr_size >= needed_size) { + IA_CSS_LEAVE_PRIVATE("false"); + return false; + } + /* don't reallocate if single ref to buffer and same size */ + if (*curr_size == needed_size && ia_css_refcount_is_single(*curr_buf)) { + IA_CSS_LEAVE_PRIVATE("false"); + return false; + } + + id = IA_CSS_REFCOUNT_PARAM_BUFFER; + ia_css_refcount_decrement(id, *curr_buf); + *curr_buf = ia_css_refcount_increment(id, mmgr_alloc_attr(needed_size, + mmgr_attribute)); + + if (!*curr_buf) { + *err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + *curr_size = 0; + } else { + *curr_size = needed_size; + } + IA_CSS_LEAVE_PRIVATE("true"); + return true; +} + +static bool reallocate_buffer( + hrt_vaddress *curr_buf, + size_t *curr_size, + size_t needed_size, + bool force, + enum ia_css_err *err) +{ + bool ret; + uint16_t mmgr_attribute = MMGR_ATTRIBUTE_DEFAULT; + + IA_CSS_ENTER_PRIVATE("void"); + + ret = realloc_isp_css_mm_buf(curr_buf, + curr_size, needed_size, force, err, mmgr_attribute); + + IA_CSS_LEAVE_PRIVATE("ret=%d", ret); + return ret; +} + +#endif + +struct ia_css_isp_3a_statistics * +ia_css_isp_3a_statistics_allocate(const struct ia_css_3a_grid_info *grid) +{ + struct ia_css_isp_3a_statistics *me; + + IA_CSS_ENTER("grid=%p", grid); + + assert(grid != NULL); + + /* MW: Does "grid->enable" also control the histogram output ?? */ + if (!grid->enable) + return NULL; + + me = sh_css_calloc(1, sizeof(*me)); + if (!me) + goto err; + + if (grid->use_dmem) { + me->dmem_size = sizeof(struct ia_css_3a_output) * + grid->aligned_width * + grid->aligned_height; + } else { + me->vmem_size = ISP_S3ATBL_HI_LO_STRIDE_BYTES * + grid->aligned_height; + } +#if !defined(HAS_NO_HMEM) + me->hmem_size = sizeof_hmem(HMEM0_ID); +#endif + + /* All subsections need to be aligned to the system bus width */ + me->dmem_size = CEIL_MUL(me->dmem_size, HIVE_ISP_DDR_WORD_BYTES); + me->vmem_size = CEIL_MUL(me->vmem_size, HIVE_ISP_DDR_WORD_BYTES); + me->hmem_size = CEIL_MUL(me->hmem_size, HIVE_ISP_DDR_WORD_BYTES); + + me->size = me->dmem_size + me->vmem_size * 2 + me->hmem_size; + me->data_ptr = mmgr_malloc(me->size); + if (me->data_ptr == mmgr_NULL) { + sh_css_free(me); + me = NULL; + goto err; + } + if (me->dmem_size) + me->data.dmem.s3a_tbl = me->data_ptr; + if (me->vmem_size) { + me->data.vmem.s3a_tbl_hi = me->data_ptr + me->dmem_size; + me->data.vmem.s3a_tbl_lo = me->data_ptr + me->dmem_size + me->vmem_size; + } + if (me->hmem_size) + me->data_hmem.rgby_tbl = me->data_ptr + me->dmem_size + 2 * me->vmem_size; + + +err: + IA_CSS_LEAVE("return=%p", me); + return me; +} + +void +ia_css_isp_3a_statistics_free(struct ia_css_isp_3a_statistics *me) +{ + if (me != NULL) { + mmgr_free(me->data_ptr); + sh_css_free(me); + } +} + +struct ia_css_isp_skc_dvs_statistics *ia_css_skc_dvs_statistics_allocate(void) +{ + return NULL; +} + +void +ia_css_lace_statistics_free(struct ia_css_isp_lace_statistics *me) +{ + me = NULL; +} + +struct ia_css_isp_lace_statistics *ia_css_lace_statistics_allocate(void) +{ + return NULL; +} + +struct ia_css_metadata * +ia_css_metadata_allocate(const struct ia_css_metadata_info *metadata_info) +{ + struct ia_css_metadata *md = NULL; + + IA_CSS_ENTER(""); + + if (metadata_info->size == 0) + return NULL; + + md = sh_css_malloc(sizeof(*md)); + if (md == NULL) + goto error; + + md->info = *metadata_info; + md->exp_id = 0; + md->address = mmgr_malloc(metadata_info->size); + if (md->address == mmgr_NULL) + goto error; + + IA_CSS_LEAVE("return=%p", md); + return md; + +error: + ia_css_metadata_free(md); + IA_CSS_LEAVE("return=%p", NULL); + return NULL; +} + +void +ia_css_metadata_free(struct ia_css_metadata *me) +{ + if (me != NULL) { + /* The enter and leave macros are placed inside + * the condition to avoid false logging of metadata + * free events when metadata is disabled. + * We found this to be confusing during development + * and debugging. */ + IA_CSS_ENTER("me=%p", me); + mmgr_free(me->address); + sh_css_free(me); + IA_CSS_LEAVE("void"); + } +} + +void +ia_css_metadata_free_multiple(unsigned int num_bufs, struct ia_css_metadata **bufs) +{ + unsigned int i; + + if (bufs != NULL) { + for (i = 0; i < num_bufs; i++) + ia_css_metadata_free(bufs[i]); + } +} + +unsigned g_param_buffer_dequeue_count = 0; +unsigned g_param_buffer_enqueue_count = 0; + +enum ia_css_err +ia_css_stream_isp_parameters_init(struct ia_css_stream *stream) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + unsigned i; + struct sh_css_ddr_address_map *ddr_ptrs; + struct sh_css_ddr_address_map_size *ddr_ptrs_size; + struct ia_css_isp_parameters *params; + + assert(stream != NULL); + IA_CSS_ENTER_PRIVATE("void"); + + if (stream == NULL) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_INVALID_ARGUMENTS); + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + /* TMP: tracking of paramsets */ + g_param_buffer_dequeue_count = 0; + g_param_buffer_enqueue_count = 0; + + stream->per_frame_isp_params_configs = NULL; + err = sh_css_create_isp_params(stream, + &stream->isp_params_configs); + if(err != IA_CSS_SUCCESS) + goto ERR; + + params = stream->isp_params_configs; + if (!sh_css_init_isp_params_from_global(stream, params, true, NULL)) { + /* we do not return the error immediately to enable internal + * firmware feature testing */ + err = IA_CSS_ERR_INVALID_ARGUMENTS; + } + + ddr_ptrs = ¶ms->ddr_ptrs; + ddr_ptrs_size = ¶ms->ddr_ptrs_size; + + /* create per pipe reference to general ddr_ptrs */ + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { + ref_sh_css_ddr_address_map(ddr_ptrs, ¶ms->pipe_ddr_ptrs[i]); + params->pipe_ddr_ptrs_size[i] = *ddr_ptrs_size; + } + +ERR: + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static void +ia_css_set_sdis_config( + struct ia_css_isp_parameters *params, + const struct ia_css_dvs_coefficients *dvs_coefs) +{ + ia_css_set_sdis_horicoef_config(params, dvs_coefs); + ia_css_set_sdis_vertcoef_config(params, dvs_coefs); + ia_css_set_sdis_horiproj_config(params, dvs_coefs); + ia_css_set_sdis_vertproj_config(params, dvs_coefs); +} + +static void +ia_css_set_sdis2_config( + struct ia_css_isp_parameters *params, + const struct ia_css_dvs2_coefficients *dvs2_coefs) +{ + ia_css_set_sdis2_horicoef_config(params, dvs2_coefs); + ia_css_set_sdis2_vertcoef_config(params, dvs2_coefs); + ia_css_set_sdis2_horiproj_config(params, dvs2_coefs); + ia_css_set_sdis2_vertproj_config(params, dvs2_coefs); +} + +static enum ia_css_err +sh_css_create_isp_params(struct ia_css_stream *stream, + struct ia_css_isp_parameters **isp_params_out) +{ + bool succ = true; + unsigned i; + struct sh_css_ddr_address_map *ddr_ptrs; + struct sh_css_ddr_address_map_size *ddr_ptrs_size; + enum ia_css_err err = IA_CSS_SUCCESS; + size_t params_size; + struct ia_css_isp_parameters *params = + sh_css_malloc(sizeof(struct ia_css_isp_parameters)); + + if (!params) + { + *isp_params_out = NULL; + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + IA_CSS_ERROR("%s:%d error: cannot allocate memory", __FILE__, __LINE__); + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } else { + memset(params, 0, sizeof(struct ia_css_isp_parameters)); + } + + ddr_ptrs = ¶ms->ddr_ptrs; + ddr_ptrs_size = ¶ms->ddr_ptrs_size; + + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { + memset(¶ms->pipe_ddr_ptrs[i], 0, + sizeof(params->pipe_ddr_ptrs[i])); + memset(¶ms->pipe_ddr_ptrs_size[i], 0, + sizeof(params->pipe_ddr_ptrs_size[i])); + } + + memset(ddr_ptrs, 0, sizeof(*ddr_ptrs)); + memset(ddr_ptrs_size, 0, sizeof(*ddr_ptrs_size)); + + params_size = sizeof(params->uds); + ddr_ptrs_size->isp_param = params_size; + ddr_ptrs->isp_param = + ia_css_refcount_increment(IA_CSS_REFCOUNT_PARAM_BUFFER, + mmgr_malloc(params_size)); + succ &= (ddr_ptrs->isp_param != mmgr_NULL); + + ddr_ptrs_size->macc_tbl = sizeof(struct ia_css_macc_table); + ddr_ptrs->macc_tbl = + ia_css_refcount_increment(IA_CSS_REFCOUNT_PARAM_BUFFER, + mmgr_malloc(sizeof(struct ia_css_macc_table))); + succ &= (ddr_ptrs->macc_tbl != mmgr_NULL); + + *isp_params_out = params; + return err; +} + +static bool +sh_css_init_isp_params_from_global(struct ia_css_stream *stream, + struct ia_css_isp_parameters *params, + bool use_default_config, + struct ia_css_pipe *pipe_in) +{ + bool retval = true; + int i = 0; + bool is_dp_10bpp = true; + unsigned isp_pipe_version = ia_css_pipe_get_isp_pipe_version(stream->pipes[0]); + struct ia_css_isp_parameters *stream_params = stream->isp_params_configs; + + if (!use_default_config && !stream_params) { + retval = false; + goto exit; + } + + params->output_frame = NULL; + params->isp_parameters_id = 0; + + if (use_default_config) + { + ia_css_set_xnr3_config(params, &default_xnr3_config); + + sh_css_set_nr_config(params, &default_nr_config); + sh_css_set_ee_config(params, &default_ee_config); + if (isp_pipe_version == SH_CSS_ISP_PIPE_VERSION_1) + sh_css_set_macc_table(params, &default_macc_table); + else if (isp_pipe_version == SH_CSS_ISP_PIPE_VERSION_2_2) + sh_css_set_macc_table(params, &default_macc2_table); + sh_css_set_gamma_table(params, &default_gamma_table); + sh_css_set_ctc_table(params, &default_ctc_table); + sh_css_set_baa_config(params, &default_baa_config); + sh_css_set_dz_config(params, &default_dz_config); +/* ------ deprecated(bz675) : from ------ */ + sh_css_set_shading_settings(params, &default_shading_settings); +/* ------ deprecated(bz675) : to ------ */ + + ia_css_set_s3a_config(params, &default_3a_config); + ia_css_set_wb_config(params, &default_wb_config); + ia_css_set_csc_config(params, &default_cc_config); + ia_css_set_tnr_config(params, &default_tnr_config); + ia_css_set_ob_config(params, &default_ob_config); + ia_css_set_dp_config(params, &default_dp_config); +#ifndef ISP2401 + ia_css_set_param_exceptions(pipe_in, params); +#else + + for (i = 0; i < stream->num_pipes; i++) { + if (IA_CSS_SUCCESS == sh_css_select_dp_10bpp_config(stream->pipes[i], &is_dp_10bpp)) { + /* set the return value as false if both DPC and + * BDS is enabled by the user. But we do not return + * the value immediately to enable internal firmware + * feature testing. */ + if(is_dp_10bpp) { + sh_css_set_dp_config(stream->pipes[i], params, &default_dp_10bpp_config); + } else { + sh_css_set_dp_config(stream->pipes[i], params, &default_dp_config); + } + } else { + retval = false; + goto exit; + } + + ia_css_set_param_exceptions(stream->pipes[i], params); + } + +#endif + ia_css_set_de_config(params, &default_de_config); + ia_css_set_gc_config(params, &default_gc_config); + ia_css_set_anr_config(params, &default_anr_config); + ia_css_set_anr2_config(params, &default_anr_thres); + ia_css_set_ce_config(params, &default_ce_config); + ia_css_set_xnr_table_config(params, &default_xnr_table); + ia_css_set_ecd_config(params, &default_ecd_config); + ia_css_set_ynr_config(params, &default_ynr_config); + ia_css_set_fc_config(params, &default_fc_config); + ia_css_set_cnr_config(params, &default_cnr_config); + ia_css_set_macc_config(params, &default_macc_config); + ia_css_set_ctc_config(params, &default_ctc_config); + ia_css_set_aa_config(params, &default_aa_config); + ia_css_set_r_gamma_config(params, &default_r_gamma_table); + ia_css_set_g_gamma_config(params, &default_g_gamma_table); + ia_css_set_b_gamma_config(params, &default_b_gamma_table); + ia_css_set_yuv2rgb_config(params, &default_yuv2rgb_cc_config); + ia_css_set_rgb2yuv_config(params, &default_rgb2yuv_cc_config); + ia_css_set_xnr_config(params, &default_xnr_config); + ia_css_set_sdis_config(params, &default_sdis_config); + ia_css_set_sdis2_config(params, &default_sdis2_config); + ia_css_set_formats_config(params, &default_formats_config); + + params->fpn_config.data = NULL; + params->config_changed[IA_CSS_FPN_ID] = true; + params->fpn_config.enabled = 0; + + params->motion_config = default_motion_config; + params->motion_config_changed = true; + + params->morph_table = NULL; + params->morph_table_changed = true; + + params->sc_table = NULL; + params->sc_table_changed = true; + params->sc_table_dirty = false; + params->sc_table_last_pipe_num = 0; + + ia_css_sdis2_clear_coefficients(¶ms->dvs2_coefs); + params->dvs2_coef_table_changed = true; + + ia_css_sdis_clear_coefficients(¶ms->dvs_coefs); + params->dis_coef_table_changed = true; +#ifdef ISP2401 + ia_css_tnr3_set_default_config(¶ms->tnr3_config); +#endif + } + else + { + ia_css_set_xnr3_config(params, &stream_params->xnr3_config); + + sh_css_set_nr_config(params, &stream_params->nr_config); + sh_css_set_ee_config(params, &stream_params->ee_config); + if (isp_pipe_version == SH_CSS_ISP_PIPE_VERSION_1) + sh_css_set_macc_table(params, &stream_params->macc_table); + else if (isp_pipe_version == SH_CSS_ISP_PIPE_VERSION_2_2) + sh_css_set_macc_table(params, &stream_params->macc_table); + sh_css_set_gamma_table(params, &stream_params->gc_table); + sh_css_set_ctc_table(params, &stream_params->ctc_table); + sh_css_set_baa_config(params, &stream_params->bds_config); + sh_css_set_dz_config(params, &stream_params->dz_config); +/* ------ deprecated(bz675) : from ------ */ + sh_css_set_shading_settings(params, &stream_params->shading_settings); +/* ------ deprecated(bz675) : to ------ */ + + ia_css_set_s3a_config(params, &stream_params->s3a_config); + ia_css_set_wb_config(params, &stream_params->wb_config); + ia_css_set_csc_config(params, &stream_params->cc_config); + ia_css_set_tnr_config(params, &stream_params->tnr_config); + ia_css_set_ob_config(params, &stream_params->ob_config); + ia_css_set_dp_config(params, &stream_params->dp_config); + ia_css_set_de_config(params, &stream_params->de_config); + ia_css_set_gc_config(params, &stream_params->gc_config); + ia_css_set_anr_config(params, &stream_params->anr_config); + ia_css_set_anr2_config(params, &stream_params->anr_thres); + ia_css_set_ce_config(params, &stream_params->ce_config); + ia_css_set_xnr_table_config(params, &stream_params->xnr_table); + ia_css_set_ecd_config(params, &stream_params->ecd_config); + ia_css_set_ynr_config(params, &stream_params->ynr_config); + ia_css_set_fc_config(params, &stream_params->fc_config); + ia_css_set_cnr_config(params, &stream_params->cnr_config); + ia_css_set_macc_config(params, &stream_params->macc_config); + ia_css_set_ctc_config(params, &stream_params->ctc_config); + ia_css_set_aa_config(params, &stream_params->aa_config); + ia_css_set_r_gamma_config(params, &stream_params->r_gamma_table); + ia_css_set_g_gamma_config(params, &stream_params->g_gamma_table); + ia_css_set_b_gamma_config(params, &stream_params->b_gamma_table); + ia_css_set_yuv2rgb_config(params, &stream_params->yuv2rgb_cc_config); + ia_css_set_rgb2yuv_config(params, &stream_params->rgb2yuv_cc_config); + ia_css_set_xnr_config(params, &stream_params->xnr_config); + ia_css_set_formats_config(params, &stream_params->formats_config); + + for (i = 0; i < stream->num_pipes; i++) { + if (IA_CSS_SUCCESS == + sh_css_select_dp_10bpp_config(stream->pipes[i], &is_dp_10bpp)) { + /* set the return value as false if both DPC and + * BDS is enabled by the user. But we do not return + * the value immediately to enable internal firmware + * feature testing. */ +#ifndef ISP2401 + retval = !is_dp_10bpp; +#else + if (is_dp_10bpp) { + retval = false; + } + } else { + retval = false; + goto exit; + } + if (stream->pipes[i]->mode < IA_CSS_PIPE_ID_NUM) { + sh_css_set_dp_config(stream->pipes[i], params, + &stream_params->pipe_dp_config[stream->pipes[i]->mode]); + ia_css_set_param_exceptions(stream->pipes[i], params); +#endif + } else { + retval = false; + goto exit; + } + } + +#ifndef ISP2401 + ia_css_set_param_exceptions(pipe_in, params); + +#endif + params->fpn_config.data = stream_params->fpn_config.data; + params->config_changed[IA_CSS_FPN_ID] = stream_params->config_changed[IA_CSS_FPN_ID]; + params->fpn_config.enabled = stream_params->fpn_config.enabled; + + sh_css_set_motion_vector(params, &stream_params->motion_config); + sh_css_set_morph_table(params, stream_params->morph_table); + + if (stream_params->sc_table) { + sh_css_update_shading_table_status(pipe_in, params); + sh_css_set_shading_table(stream, params, stream_params->sc_table); + } + else { + params->sc_table = NULL; + params->sc_table_changed = true; + params->sc_table_dirty = false; + params->sc_table_last_pipe_num = 0; + } + + /* Only IA_CSS_PIPE_ID_VIDEO & IA_CSS_PIPE_ID_CAPTURE will support dvs_6axis_config*/ + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { + if (stream_params->pipe_dvs_6axis_config[i]) { + if (params->pipe_dvs_6axis_config[i]) { + copy_dvs_6axis_table(params->pipe_dvs_6axis_config[i], + stream_params->pipe_dvs_6axis_config[i]); + } else { + params->pipe_dvs_6axis_config[i] = + generate_dvs_6axis_table_from_config(stream_params->pipe_dvs_6axis_config[i]); + } + } + } + ia_css_set_sdis_config(params, &stream_params->dvs_coefs); + params->dis_coef_table_changed = stream_params->dis_coef_table_changed; + + ia_css_set_sdis2_config(params, &stream_params->dvs2_coefs); + params->dvs2_coef_table_changed = stream_params->dvs2_coef_table_changed; + params->sensor_binning = stream_params->sensor_binning; + } + +exit: + return retval; +} + +enum ia_css_err +sh_css_params_init(void) +{ + int i, p; + + IA_CSS_ENTER_PRIVATE("void"); + + /* TMP: tracking of paramsets */ + g_param_buffer_dequeue_count = 0; + g_param_buffer_enqueue_count = 0; + + for (p = 0; p < IA_CSS_PIPE_ID_NUM; p++) { + for (i = 0; i < SH_CSS_MAX_STAGES; i++) { + xmem_sp_stage_ptrs[p][i] = + ia_css_refcount_increment(-1, + mmgr_calloc(1, + sizeof(struct sh_css_sp_stage))); + xmem_isp_stage_ptrs[p][i] = + ia_css_refcount_increment(-1, + mmgr_calloc(1, + sizeof(struct sh_css_isp_stage))); + + if ((xmem_sp_stage_ptrs[p][i] == mmgr_NULL) || + (xmem_isp_stage_ptrs[p][i] == mmgr_NULL)) { + sh_css_params_uninit(); + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY); + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + } + } + } + + ia_css_config_gamma_table(); + ia_css_config_ctc_table(); + ia_css_config_rgb_gamma_tables(); + ia_css_config_xnr_table(); + + sp_ddr_ptrs = ia_css_refcount_increment(-1, mmgr_calloc(1, + CEIL_MUL(sizeof(struct sh_css_ddr_address_map), + HIVE_ISP_DDR_WORD_BYTES))); + xmem_sp_group_ptrs = ia_css_refcount_increment(-1, mmgr_calloc(1, + sizeof(struct sh_css_sp_group))); + + if ((sp_ddr_ptrs == mmgr_NULL) || + (xmem_sp_group_ptrs == mmgr_NULL)) { + ia_css_uninit(); + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY); + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + } + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + return IA_CSS_SUCCESS; +} + +static void host_lut_store(const void *lut) +{ + unsigned i; + + for (i = 0; i < N_GDC_ID; i++) + gdc_lut_store((gdc_ID_t)i, (const int (*)[HRT_GDC_N]) lut); +} + +/* Note that allocation is in ipu address space. */ +inline hrt_vaddress sh_css_params_alloc_gdc_lut(void) +{ + return mmgr_malloc(sizeof(zoom_table)); +} + +inline void sh_css_params_free_gdc_lut(hrt_vaddress addr) +{ + if (addr != mmgr_NULL) + mmgr_free(addr); +} + +enum ia_css_err ia_css_pipe_set_bci_scaler_lut(struct ia_css_pipe *pipe, + const void *lut) +{ + enum ia_css_err err = IA_CSS_SUCCESS; +#ifndef ISP2401 + bool store = true; +#else + bool stream_started = false; +#endif + IA_CSS_ENTER("pipe=%p lut=%p", pipe, lut); + + if (lut == NULL || pipe == NULL) { + err = IA_CSS_ERR_INVALID_ARGUMENTS; + IA_CSS_LEAVE("err=%d", err); + return err; + } + + /* If the pipe belongs to a stream and the stream has started, it is not + * safe to store lut to gdc HW. If pipe->stream is NULL, then no stream is + * created with this pipe, so it is safe to do this operation as long as + * ia_css_init() has been called. */ + if (pipe->stream && pipe->stream->started) { + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "unable to set scaler lut since stream has started\n"); +#ifndef ISP2401 + store = false; +#else + stream_started = true; +#endif + err = IA_CSS_ERR_NOT_SUPPORTED; + } + + /* Free any existing tables. */ +#ifndef ISP2401 + if (pipe->scaler_pp_lut != mmgr_NULL) { + mmgr_free(pipe->scaler_pp_lut); + pipe->scaler_pp_lut = mmgr_NULL; + } +#else + sh_css_params_free_gdc_lut(pipe->scaler_pp_lut); + pipe->scaler_pp_lut = mmgr_NULL; +#endif + +#ifndef ISP2401 + if (store) { + pipe->scaler_pp_lut = mmgr_malloc(sizeof(zoom_table)); +#else + if (!stream_started) { + pipe->scaler_pp_lut = sh_css_params_alloc_gdc_lut(); +#endif + if (pipe->scaler_pp_lut == mmgr_NULL) { +#ifndef ISP2401 + IA_CSS_LEAVE("lut(%p) err=%d", pipe->scaler_pp_lut, err); + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; +#else + ia_css_debug_dtrace(IA_CSS_DEBUG_ERROR, + "unable to allocate scaler_pp_lut\n"); + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + } else { + gdc_lut_convert_to_isp_format((const int(*)[HRT_GDC_N])lut, + interleaved_lut_temp); + mmgr_store(pipe->scaler_pp_lut, + (int *)interleaved_lut_temp, + sizeof(zoom_table)); +#endif + } +#ifndef ISP2401 + + gdc_lut_convert_to_isp_format((const int(*)[HRT_GDC_N])lut, interleaved_lut_temp); + mmgr_store(pipe->scaler_pp_lut, (int *)interleaved_lut_temp, + sizeof(zoom_table)); +#endif + } + + IA_CSS_LEAVE("lut(%p) err=%d", pipe->scaler_pp_lut, err); + return err; +} + +/* if pipe is NULL, returns default lut addr. */ +hrt_vaddress sh_css_pipe_get_pp_gdc_lut(const struct ia_css_pipe *pipe) +{ + assert(pipe != NULL); + + if (pipe->scaler_pp_lut != mmgr_NULL) + return pipe->scaler_pp_lut; + else + return sh_css_params_get_default_gdc_lut(); +} + +enum ia_css_err sh_css_params_map_and_store_default_gdc_lut(void) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + + IA_CSS_ENTER_PRIVATE("void"); + + /* Is table already mapped? Nothing to do if it is mapped. */ + if (default_gdc_lut != mmgr_NULL) + return err; + + host_lut_store((void *)zoom_table); + +#ifndef ISP2401 + default_gdc_lut = mmgr_malloc(sizeof(zoom_table)); +#else + default_gdc_lut = sh_css_params_alloc_gdc_lut(); +#endif + if (default_gdc_lut == mmgr_NULL) + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + + gdc_lut_convert_to_isp_format((const int(*)[HRT_GDC_N])zoom_table, + interleaved_lut_temp); + mmgr_store(default_gdc_lut, (int *)interleaved_lut_temp, + sizeof(zoom_table)); + + IA_CSS_LEAVE_PRIVATE("lut(%p) err=%d", default_gdc_lut, err); + return err; +} + +void sh_css_params_free_default_gdc_lut(void) +{ + IA_CSS_ENTER_PRIVATE("void"); + +#ifndef ISP2401 + if (default_gdc_lut != mmgr_NULL) { + mmgr_free(default_gdc_lut); + default_gdc_lut = mmgr_NULL; + } +#else + sh_css_params_free_gdc_lut(default_gdc_lut); + default_gdc_lut = mmgr_NULL; +#endif + + IA_CSS_LEAVE_PRIVATE("void"); + +} + +hrt_vaddress sh_css_params_get_default_gdc_lut(void) +{ + return default_gdc_lut; +} + +static void free_param_set_callback( + hrt_vaddress ptr) +{ + IA_CSS_ENTER_PRIVATE("void"); + + free_ia_css_isp_parameter_set_info(ptr); + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void free_buffer_callback( + hrt_vaddress ptr) +{ + IA_CSS_ENTER_PRIVATE("void"); + + mmgr_free(ptr); + + IA_CSS_LEAVE_PRIVATE("void"); +} + +void +sh_css_param_clear_param_sets(void) +{ + IA_CSS_ENTER_PRIVATE("void"); + + ia_css_refcount_clear(IA_CSS_REFCOUNT_PARAM_SET_POOL, &free_param_set_callback); + + IA_CSS_LEAVE_PRIVATE("void"); +} + +/* + * MW: we can define mmgr_free() to return a NULL + * then you can write ptr = mmgr_free(ptr); + */ +#define safe_free(id, x) \ + do { \ + ia_css_refcount_decrement(id, x); \ + (x) = mmgr_NULL; \ + } while(0) + +static void free_map(struct sh_css_ddr_address_map *map) +{ + unsigned int i; + + hrt_vaddress *addrs = (hrt_vaddress *)map; + + IA_CSS_ENTER_PRIVATE("void"); + + /* free buffers */ + for (i = 0; i < (sizeof(struct sh_css_ddr_address_map_size)/ + sizeof(size_t)); i++) { + if (addrs[i] == mmgr_NULL) + continue; + safe_free(IA_CSS_REFCOUNT_PARAM_BUFFER, addrs[i]); + } + + IA_CSS_LEAVE_PRIVATE("void"); +} + +void +ia_css_stream_isp_parameters_uninit(struct ia_css_stream *stream) +{ + int i; + struct ia_css_isp_parameters *params = stream->isp_params_configs; + struct ia_css_isp_parameters *per_frame_params = + stream->per_frame_isp_params_configs; + + IA_CSS_ENTER_PRIVATE("void"); + if (params == NULL) { + IA_CSS_LEAVE_PRIVATE("isp_param_configs is NULL"); + return; + } + + /* free existing ddr_ptr maps */ + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) + { + free_map(¶ms->pipe_ddr_ptrs[i]); + if (per_frame_params) + free_map(&per_frame_params->pipe_ddr_ptrs[i]); + /* Free up theDVS table memory blocks before recomputing new table */ + if (params->pipe_dvs_6axis_config[i]) + free_dvs_6axis_table(&(params->pipe_dvs_6axis_config[i])); + if (per_frame_params && per_frame_params->pipe_dvs_6axis_config[i]) + free_dvs_6axis_table(&(per_frame_params->pipe_dvs_6axis_config[i])); + } + free_map(¶ms->ddr_ptrs); + if (per_frame_params) + free_map(&per_frame_params->ddr_ptrs); + + if (params->fpn_config.data) { + sh_css_free(params->fpn_config.data); + params->fpn_config.data = NULL; + } + + /* Free up sc_config (temporal shading table) if it is allocated. */ + if (params->sc_config) { + ia_css_shading_table_free(params->sc_config); + params->sc_config = NULL; + } + if (per_frame_params) { + if (per_frame_params->sc_config) { + ia_css_shading_table_free(per_frame_params->sc_config); + per_frame_params->sc_config = NULL; + } + } + + sh_css_free(params); + if (per_frame_params) + sh_css_free(per_frame_params); + stream->isp_params_configs = NULL; + stream->per_frame_isp_params_configs = NULL; + + IA_CSS_LEAVE_PRIVATE("void"); +} + +void +sh_css_params_uninit(void) +{ + unsigned p, i; + + IA_CSS_ENTER_PRIVATE("void"); + + ia_css_refcount_decrement(-1, sp_ddr_ptrs); + sp_ddr_ptrs = mmgr_NULL; + ia_css_refcount_decrement(-1, xmem_sp_group_ptrs); + xmem_sp_group_ptrs = mmgr_NULL; + + for (p = 0; p < IA_CSS_PIPE_ID_NUM; p++) + for (i = 0; i < SH_CSS_MAX_STAGES; i++) { + ia_css_refcount_decrement(-1, xmem_sp_stage_ptrs[p][i]); + xmem_sp_stage_ptrs[p][i] = mmgr_NULL; + ia_css_refcount_decrement(-1, xmem_isp_stage_ptrs[p][i]); + xmem_isp_stage_ptrs[p][i] = mmgr_NULL; + } + + /* go through the pools to clear references */ + ia_css_refcount_clear(IA_CSS_REFCOUNT_PARAM_SET_POOL, &free_param_set_callback); + ia_css_refcount_clear(IA_CSS_REFCOUNT_PARAM_BUFFER, &free_buffer_callback); + ia_css_refcount_clear(-1, &free_buffer_callback); + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static struct ia_css_host_data * +convert_allocate_morph_plane( + unsigned short *data, + unsigned int width, + unsigned int height, + unsigned int aligned_width) +{ + unsigned int i, j, padding, w; + struct ia_css_host_data *me; + unsigned int isp_data_size; + uint16_t *isp_data_ptr; + + IA_CSS_ENTER_PRIVATE("void"); + + /* currently we don't have morph table interpolation yet, + * so we allow a wider table to be used. This will be removed + * in the future. */ + if (width > aligned_width) { + padding = 0; + w = aligned_width; + } else { + padding = aligned_width - width; + w = width; + } + isp_data_size = height * (w + padding) * sizeof(uint16_t); + + me = ia_css_host_data_allocate((size_t) isp_data_size); + + if (!me) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY); + return NULL; + } + + isp_data_ptr = (uint16_t *)me->address; + + memset(isp_data_ptr, 0, (size_t)isp_data_size); + + for (i = 0; i < height; i++) { + for (j = 0; j < w; j++) + *isp_data_ptr++ = (uint16_t)data[j]; + isp_data_ptr += padding; + data += width; + } + + IA_CSS_LEAVE_PRIVATE("void"); + return me; +} + +static enum ia_css_err +store_morph_plane( + unsigned short *data, + unsigned int width, + unsigned int height, + hrt_vaddress dest, + unsigned int aligned_width) +{ + struct ia_css_host_data *isp_data; + + assert(dest != mmgr_NULL); + + isp_data = convert_allocate_morph_plane(data, width, height, aligned_width); + if (!isp_data) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY); + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + } + ia_css_params_store_ia_css_host_data(dest, isp_data); + + ia_css_host_data_free(isp_data); + return IA_CSS_SUCCESS; +} + +static void sh_css_update_isp_params_to_ddr( + struct ia_css_isp_parameters *params, + hrt_vaddress ddr_ptr) +{ + size_t size = sizeof(params->uds); + + IA_CSS_ENTER_PRIVATE("void"); + + assert(params != NULL); + +#ifdef HRT_CSIM + { + /* ispparm struct is read with DMA which reads + * multiples of the DDR word with (32 bytes): + * So we pad with zeroes to prevent warnings in csim. + */ + unsigned int aligned_width, padding_bytes; + hrt_vaddress pad_ptr; + + aligned_width = CEIL_MUL( + size, + HIVE_ISP_DDR_WORD_BYTES); + padding_bytes = aligned_width - size; + pad_ptr = ddr_ptr + size; + mmgr_clear(pad_ptr, padding_bytes); + } +#endif + mmgr_store(ddr_ptr, &(params->uds), size); + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void sh_css_update_isp_mem_params_to_ddr( + const struct ia_css_binary *binary, + hrt_vaddress ddr_mem_ptr, + size_t size, + enum ia_css_isp_memories mem) +{ + const struct ia_css_host_data *params; + + IA_CSS_ENTER_PRIVATE("void"); + + params = ia_css_isp_param_get_mem_init(&binary->mem_params, IA_CSS_PARAM_CLASS_PARAM, mem); + mmgr_store(ddr_mem_ptr, params->address, size); + + IA_CSS_LEAVE_PRIVATE("void"); +} + +void ia_css_dequeue_param_buffers(/*unsigned int pipe_num*/) +{ + unsigned int i; + hrt_vaddress cpy; + enum sh_css_queue_id param_queue_ids[3] = { IA_CSS_PARAMETER_SET_QUEUE_ID, + IA_CSS_PER_FRAME_PARAMETER_SET_QUEUE_ID, + SH_CSS_INVALID_QUEUE_ID}; + + IA_CSS_ENTER_PRIVATE("void"); + + if (!sh_css_sp_is_running()) { + IA_CSS_LEAVE_PRIVATE("sp is not running"); + /* SP is not running. The queues are not valid */ + return; + } + + for (i = 0; SH_CSS_INVALID_QUEUE_ID != param_queue_ids[i]; i++) { + cpy = (hrt_vaddress)0; + /* clean-up old copy */ + while (IA_CSS_SUCCESS == ia_css_bufq_dequeue_buffer(param_queue_ids[i], (uint32_t *)&cpy)) { + /* TMP: keep track of dequeued param set count + */ + g_param_buffer_dequeue_count++; + ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_BUFFER_DEQUEUED, + 0, + param_queue_ids[i], + 0); + + IA_CSS_LOG("dequeued param set %x from %d, release ref", cpy, 0); + free_ia_css_isp_parameter_set_info(cpy); + cpy = (hrt_vaddress)0; + } + } + + IA_CSS_LEAVE_PRIVATE("void"); +} + +static void +process_kernel_parameters(unsigned int pipe_id, + struct ia_css_pipeline_stage *stage, + struct ia_css_isp_parameters *params, + unsigned int isp_pipe_version, + unsigned int raw_bit_depth) +{ + unsigned param_id; + + (void)isp_pipe_version; + (void)raw_bit_depth; + + sh_css_enable_pipeline(stage->binary); + + if (params->config_changed[IA_CSS_OB_ID]) { + ia_css_ob_configure(¶ms->stream_configs.ob, + isp_pipe_version, raw_bit_depth); + } + if (params->config_changed[IA_CSS_S3A_ID]) { + ia_css_s3a_configure(raw_bit_depth); + } + /* Copy stage uds parameters to config, since they can differ per stage. + */ + params->crop_config.crop_pos = params->uds[stage->stage_num].crop_pos; + params->uds_config.crop_pos = params->uds[stage->stage_num].crop_pos; + params->uds_config.uds = params->uds[stage->stage_num].uds; + /* Call parameter process functions for all kernels */ + /* Skip SC, since that is called on a temp sc table */ + for (param_id = 0; param_id < IA_CSS_NUM_PARAMETER_IDS; param_id++) { + if (param_id == IA_CSS_SC_ID) continue; + if (params->config_changed[param_id]) + ia_css_kernel_process_param[param_id](pipe_id, stage, params); + } +} + +enum ia_css_err +sh_css_param_update_isp_params(struct ia_css_pipe *curr_pipe, + struct ia_css_isp_parameters *params, + bool commit, + struct ia_css_pipe *pipe_in) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + hrt_vaddress cpy; + int i; + unsigned int raw_bit_depth = 10; + unsigned int isp_pipe_version = SH_CSS_ISP_PIPE_VERSION_1; + bool acc_cluster_params_changed = false; + unsigned int thread_id, pipe_num; + + (void)acc_cluster_params_changed; + + assert(curr_pipe != NULL); + + IA_CSS_ENTER_PRIVATE("pipe=%p, isp_parameters_id=%d", pipe_in, params->isp_parameters_id); + raw_bit_depth = ia_css_stream_input_format_bits_per_pixel(curr_pipe->stream); + + /* now make the map available to the sp */ + if (!commit) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + /* enqueue a copies of the mem_map to + the designated pipelines */ + for (i = 0; i < curr_pipe->stream->num_pipes; i++) { + struct ia_css_pipe *pipe; + struct sh_css_ddr_address_map *cur_map; + struct sh_css_ddr_address_map_size *cur_map_size; + struct ia_css_isp_parameter_set_info isp_params_info; + struct ia_css_pipeline *pipeline; + struct ia_css_pipeline_stage *stage; + + enum sh_css_queue_id queue_id; + + (void)stage; + pipe = curr_pipe->stream->pipes[i]; + pipeline = ia_css_pipe_get_pipeline(pipe); + pipe_num = ia_css_pipe_get_pipe_num(pipe); + isp_pipe_version = ia_css_pipe_get_isp_pipe_version(pipe); + ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id); + +#if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS) + ia_css_query_internal_queue_id(params->output_frame + ? IA_CSS_BUFFER_TYPE_PER_FRAME_PARAMETER_SET + : IA_CSS_BUFFER_TYPE_PARAMETER_SET, + thread_id, &queue_id); +#else + ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_PARAMETER_SET, thread_id, &queue_id); +#endif + if (!sh_css_sp_is_running()) { + /* SP is not running. The queues are not valid */ + err = IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + break; + } + cur_map = ¶ms->pipe_ddr_ptrs[pipeline->pipe_id]; + cur_map_size = ¶ms->pipe_ddr_ptrs_size[pipeline->pipe_id]; + + /* TODO: Normally, zoom and motion parameters shouldn't + * be part of "isp_params" as it is resolution/pipe dependant + * Therefore, move the zoom config elsewhere (e.g. shading + * table can be taken as an example! @GC + * */ + { + /* we have to do this per pipeline because */ + /* the processing is a.o. resolution dependent */ + err = ia_css_process_zoom_and_motion(params, + pipeline->stages); + if (err != IA_CSS_SUCCESS) + return err; + } + /* check if to actually update the parameters for this pipe */ + /* When API change is implemented making good distinction between + * stream config and pipe config this skipping code can be moved out of the #ifdef */ + if (pipe_in && (pipe != pipe_in)) { + IA_CSS_LOG("skipping pipe %x", pipe); + continue; + } + + /* BZ 125915, should be moved till after "update other buff" */ + /* update the other buffers to the pipe specific copies */ + for (stage = pipeline->stages; stage; stage = stage->next) { + unsigned mem; + + if (!stage || !stage->binary) + continue; + + process_kernel_parameters(pipeline->pipe_id, + stage, params, + isp_pipe_version, raw_bit_depth); + + err = sh_css_params_write_to_ddr_internal( + pipe, + pipeline->pipe_id, + params, + stage, + cur_map, + cur_map_size); + + if (err != IA_CSS_SUCCESS) + break; + for (mem = 0; mem < IA_CSS_NUM_MEMORIES; mem++) { + params->isp_mem_params_changed + [pipeline->pipe_id][stage->stage_num][mem] = false; + } + } /* for */ + if (err != IA_CSS_SUCCESS) + break; + /* update isp_params to pipe specific copies */ + if (params->isp_params_changed) { + reallocate_buffer(&cur_map->isp_param, + &cur_map_size->isp_param, + cur_map_size->isp_param, + true, + &err); + if (err != IA_CSS_SUCCESS) + break; + sh_css_update_isp_params_to_ddr(params, cur_map->isp_param); + } + + /* last make referenced copy */ + err = ref_sh_css_ddr_address_map( + cur_map, + &isp_params_info.mem_map); + if (err != IA_CSS_SUCCESS) + break; + + /* Update Parameters ID */ + isp_params_info.isp_parameters_id = params->isp_parameters_id; + + /* Update output frame pointer */ + isp_params_info.output_frame_ptr = + (params->output_frame) ? params->output_frame->data : mmgr_NULL; + + /* now write the copy to ddr */ + err = write_ia_css_isp_parameter_set_info_to_ddr(&isp_params_info, &cpy); + if (err != IA_CSS_SUCCESS) + break; + + /* enqueue the set to sp */ + IA_CSS_LOG("queue param set %x to %d", cpy, thread_id); + + err = ia_css_bufq_enqueue_buffer(thread_id, queue_id, (uint32_t)cpy); + if (IA_CSS_SUCCESS != err) { + free_ia_css_isp_parameter_set_info(cpy); +#if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS) + IA_CSS_LOG("pfp: FAILED to add config id %d for OF %d to q %d on thread %d", + isp_params_info.isp_parameters_id, + isp_params_info.output_frame_ptr, + queue_id, thread_id); +#endif + break; + } + else { + /* TMP: check discrepancy between nr of enqueued + * parameter sets and dequeued sets + */ + g_param_buffer_enqueue_count++; + assert(g_param_buffer_enqueue_count < g_param_buffer_dequeue_count+50); +#ifdef ISP2401 + ia_css_save_latest_paramset_ptr(pipe, cpy); +#endif + /* + * Tell the SP which queues are not empty, + * by sending the software event. + */ + if (!sh_css_sp_is_running()) { + /* SP is not running. The queues are not valid */ + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_RESOURCE_NOT_AVAILABLE); + return IA_CSS_ERR_RESOURCE_NOT_AVAILABLE; + } + ia_css_bufq_enqueue_psys_event( + IA_CSS_PSYS_SW_EVENT_BUFFER_ENQUEUED, + (uint8_t)thread_id, + (uint8_t)queue_id, + 0); +#if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS) + IA_CSS_LOG("pfp: added config id %d for OF %d to q %d on thread %d", + isp_params_info.isp_parameters_id, + isp_params_info.output_frame_ptr, + queue_id, thread_id); +#endif + } + /* clean-up old copy */ + ia_css_dequeue_param_buffers(/*pipe_num*/); + params->pipe_dvs_6axis_config_changed[pipeline->pipe_id] = false; + } /* end for each 'active' pipeline */ + /* clear the changed flags after all params + for all pipelines have been updated */ + params->isp_params_changed = false; + params->sc_table_changed = false; + params->dis_coef_table_changed = false; + params->dvs2_coef_table_changed = false; + params->morph_table_changed = false; + params->dz_config_changed = false; + params->motion_config_changed = false; +/* ------ deprecated(bz675) : from ------ */ + params->shading_settings_changed = false; +/* ------ deprecated(bz675) : to ------ */ + + memset(¶ms->config_changed[0], 0, sizeof(params->config_changed)); + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static enum ia_css_err +sh_css_params_write_to_ddr_internal( + struct ia_css_pipe *pipe, + unsigned pipe_id, + struct ia_css_isp_parameters *params, + const struct ia_css_pipeline_stage *stage, + struct sh_css_ddr_address_map *ddr_map, + struct sh_css_ddr_address_map_size *ddr_map_size) +{ + enum ia_css_err err; + const struct ia_css_binary *binary; + + unsigned stage_num; + unsigned mem; + bool buff_realloced; + + /* struct is > 128 bytes so it should not be on stack (see checkpatch) */ + static struct ia_css_macc_table converted_macc_table; + + IA_CSS_ENTER_PRIVATE("void"); + assert(params != NULL); + assert(ddr_map != NULL); + assert(ddr_map_size != NULL); + assert(stage != NULL); + + binary = stage->binary; + assert(binary != NULL); + + + stage_num = stage->stage_num; + + if (binary->info->sp.enable.fpnr) { + buff_realloced = reallocate_buffer(&ddr_map->fpn_tbl, + &ddr_map_size->fpn_tbl, + (size_t)(FPNTBL_BYTES(binary)), + params->config_changed[IA_CSS_FPN_ID], + &err); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + if (params->config_changed[IA_CSS_FPN_ID] || buff_realloced) { + if (params->fpn_config.enabled) { + err = store_fpntbl(params, ddr_map->fpn_tbl); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } +#ifdef HRT_CSIM + else { + hrt_vaddress ptr = + (hrt_vaddress)ddr_map->fpn_tbl; + /* prevent warnings when reading fpn table + * in csim.*/ + /* Actual values are not used when fpn is + * disabled. */ + /* MW: fpn_tbl_size*sizeof(whatever)? */ + mmgr_clear(ptr, ddr_map_size->fpn_tbl); + } +#endif + } + } + + if (binary->info->sp.enable.sc) { + uint32_t enable_conv = params-> + shading_settings.enable_shading_table_conversion; + + buff_realloced = reallocate_buffer(&ddr_map->sc_tbl, + &ddr_map_size->sc_tbl, + (size_t)(SCTBL_BYTES(binary)), + params->sc_table_changed, + &err); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + if (params->shading_settings_changed || + params->sc_table_changed || buff_realloced) { + if (enable_conv == 0) { + if (params->sc_table) { + /* store the shading table to ddr */ + err = ia_css_params_store_sctbl(stage, ddr_map->sc_tbl, params->sc_table); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + /* set sc_config to isp */ + params->sc_config = (struct ia_css_shading_table *)params->sc_table; + ia_css_kernel_process_param[IA_CSS_SC_ID](pipe_id, stage, params); + params->sc_config = NULL; + } else { + /* generate the identical shading table */ + if (params->sc_config) { + ia_css_shading_table_free(params->sc_config); + params->sc_config = NULL; + } +#ifndef ISP2401 + sh_css_params_shading_id_table_generate(¶ms->sc_config, binary); +#else + sh_css_params_shading_id_table_generate(¶ms->sc_config, + binary->sctbl_width_per_color, binary->sctbl_height); +#endif + if (params->sc_config == NULL) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY); + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + } + + /* store the shading table to ddr */ + err = ia_css_params_store_sctbl(stage, ddr_map->sc_tbl, params->sc_config); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + /* set sc_config to isp */ + ia_css_kernel_process_param[IA_CSS_SC_ID](pipe_id, stage, params); + + /* free the shading table */ + ia_css_shading_table_free(params->sc_config); + params->sc_config = NULL; + } + } else { /* legacy */ +/* ------ deprecated(bz675) : from ------ */ + /* shading table is full resolution, reduce */ + if (params->sc_config) { + ia_css_shading_table_free(params->sc_config); + params->sc_config = NULL; + } + prepare_shading_table( + (const struct ia_css_shading_table *)params->sc_table, + params->sensor_binning, + ¶ms->sc_config, + binary, pipe->required_bds_factor); + if (params->sc_config == NULL) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY); + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + } + + /* store the shading table to ddr */ + err = ia_css_params_store_sctbl(stage, ddr_map->sc_tbl, params->sc_config); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + /* set sc_config to isp */ + ia_css_kernel_process_param[IA_CSS_SC_ID](pipe_id, stage, params); + + /* free the shading table */ + ia_css_shading_table_free(params->sc_config); + params->sc_config = NULL; +/* ------ deprecated(bz675) : to ------ */ + } + } + } +#ifdef ISP2401 + /* DPC configuration is made pipe specific to allow flexibility in positioning of the + * DPC kernel. The code below sets the pipe specific configuration to + * individual binaries. */ + if (params->pipe_dpc_config_changed[pipe_id] && binary->info->sp.enable.dpc) { + unsigned size = stage->binary->info->mem_offsets.offsets.param->dmem.dp.size; + + unsigned offset = stage->binary->info->mem_offsets.offsets.param->dmem.dp.offset; + if (size) { + ia_css_dp_encode((struct sh_css_isp_dp_params *) + &binary->mem_params.params[IA_CSS_PARAM_CLASS_PARAM][IA_CSS_ISP_DMEM].address[offset], + ¶ms->pipe_dp_config[pipe_id], size); +#endif + +#ifdef ISP2401 + params->isp_params_changed = true; + params->isp_mem_params_changed[pipe_id][stage->stage_num][IA_CSS_ISP_DMEM] = true; + } + } +#endif + if (params->config_changed[IA_CSS_MACC_ID] && binary->info->sp.enable.macc) { + unsigned int i, j, idx; + unsigned int idx_map[] = { + 0, 1, 3, 2, 6, 7, 5, 4, 12, 13, 15, 14, 10, 11, 9, 8}; + + for (i = 0; i < IA_CSS_MACC_NUM_AXES; i++) { + idx = 4*idx_map[i]; + j = 4*i; + + if (binary->info->sp.pipeline.isp_pipe_version == SH_CSS_ISP_PIPE_VERSION_1) { + converted_macc_table.data[idx] = + (int16_t)sDIGIT_FITTING(params->macc_table.data[j], + 13, SH_CSS_MACC_COEF_SHIFT); + converted_macc_table.data[idx+1] = + (int16_t)sDIGIT_FITTING(params->macc_table.data[j+1], + 13, SH_CSS_MACC_COEF_SHIFT); + converted_macc_table.data[idx+2] = + (int16_t)sDIGIT_FITTING(params->macc_table.data[j+2], + 13, SH_CSS_MACC_COEF_SHIFT); + converted_macc_table.data[idx+3] = + (int16_t)sDIGIT_FITTING(params->macc_table.data[j+3], + 13, SH_CSS_MACC_COEF_SHIFT); + } else if (binary->info->sp.pipeline.isp_pipe_version == SH_CSS_ISP_PIPE_VERSION_2_2) { + converted_macc_table.data[idx] = + params->macc_table.data[j]; + converted_macc_table.data[idx+1] = + params->macc_table.data[j+1]; + converted_macc_table.data[idx+2] = + params->macc_table.data[j+2]; + converted_macc_table.data[idx+3] = + params->macc_table.data[j+3]; + } + } + reallocate_buffer(&ddr_map->macc_tbl, + &ddr_map_size->macc_tbl, + ddr_map_size->macc_tbl, + true, + &err); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + mmgr_store(ddr_map->macc_tbl, + converted_macc_table.data, + sizeof(converted_macc_table.data)); + } + + if (binary->info->sp.enable.dvs_6axis) { + /* because UV is packed into the Y plane, calc total + * YYU size = /2 gives size of UV-only, + * total YYU size = UV-only * 3. + */ + buff_realloced = reallocate_buffer( + &ddr_map->dvs_6axis_params_y, + &ddr_map_size->dvs_6axis_params_y, + (size_t)((DVS_6AXIS_BYTES(binary) / 2) * 3), + params->pipe_dvs_6axis_config_changed[pipe_id], + &err); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + if (params->pipe_dvs_6axis_config_changed[pipe_id] || buff_realloced) { + const struct ia_css_frame_info *dvs_in_frame_info; + + if ( stage->args.delay_frames[0] ) { + /*When delay frames are present(as in case of video), + they are used for dvs. Configure DVS using those params*/ + dvs_in_frame_info = &stage->args.delay_frames[0]->info; + } else { + /*Otherwise, use input frame to configure DVS*/ + dvs_in_frame_info = &stage->args.in_frame->info; + } + + /* Generate default DVS unity table on start up*/ + if (params->pipe_dvs_6axis_config[pipe_id] == NULL) { + +#ifndef ISP2401 + struct ia_css_resolution dvs_offset; + dvs_offset.width = +#else + struct ia_css_resolution dvs_offset = {0, 0}; + if (binary->dvs_envelope.width || binary->dvs_envelope.height) { + dvs_offset.width = +#endif + (PIX_SHIFT_FILTER_RUN_IN_X + binary->dvs_envelope.width) / 2; +#ifndef ISP2401 + dvs_offset.height = +#else + dvs_offset.height = +#endif + (PIX_SHIFT_FILTER_RUN_IN_Y + binary->dvs_envelope.height) / 2; +#ifdef ISP2401 + } +#endif + + params->pipe_dvs_6axis_config[pipe_id] = + generate_dvs_6axis_table(&binary->out_frame_info[0].res, &dvs_offset); + if (params->pipe_dvs_6axis_config[pipe_id] == NULL) { + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY); + return IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + } + params->pipe_dvs_6axis_config_changed[pipe_id] = true; + } + + store_dvs_6axis_config(params->pipe_dvs_6axis_config[pipe_id], + binary, + dvs_in_frame_info, + ddr_map->dvs_6axis_params_y); + params->isp_params_changed = true; + } + } + + if (binary->info->sp.enable.ca_gdc) { + unsigned int i; + hrt_vaddress *virt_addr_tetra_x[ + IA_CSS_MORPH_TABLE_NUM_PLANES]; + size_t *virt_size_tetra_x[ + IA_CSS_MORPH_TABLE_NUM_PLANES]; + hrt_vaddress *virt_addr_tetra_y[ + IA_CSS_MORPH_TABLE_NUM_PLANES]; + size_t *virt_size_tetra_y[ + IA_CSS_MORPH_TABLE_NUM_PLANES]; + + virt_addr_tetra_x[0] = &ddr_map->tetra_r_x; + virt_addr_tetra_x[1] = &ddr_map->tetra_gr_x; + virt_addr_tetra_x[2] = &ddr_map->tetra_gb_x; + virt_addr_tetra_x[3] = &ddr_map->tetra_b_x; + virt_addr_tetra_x[4] = &ddr_map->tetra_ratb_x; + virt_addr_tetra_x[5] = &ddr_map->tetra_batr_x; + + virt_size_tetra_x[0] = &ddr_map_size->tetra_r_x; + virt_size_tetra_x[1] = &ddr_map_size->tetra_gr_x; + virt_size_tetra_x[2] = &ddr_map_size->tetra_gb_x; + virt_size_tetra_x[3] = &ddr_map_size->tetra_b_x; + virt_size_tetra_x[4] = &ddr_map_size->tetra_ratb_x; + virt_size_tetra_x[5] = &ddr_map_size->tetra_batr_x; + + virt_addr_tetra_y[0] = &ddr_map->tetra_r_y; + virt_addr_tetra_y[1] = &ddr_map->tetra_gr_y; + virt_addr_tetra_y[2] = &ddr_map->tetra_gb_y; + virt_addr_tetra_y[3] = &ddr_map->tetra_b_y; + virt_addr_tetra_y[4] = &ddr_map->tetra_ratb_y; + virt_addr_tetra_y[5] = &ddr_map->tetra_batr_y; + + virt_size_tetra_y[0] = &ddr_map_size->tetra_r_y; + virt_size_tetra_y[1] = &ddr_map_size->tetra_gr_y; + virt_size_tetra_y[2] = &ddr_map_size->tetra_gb_y; + virt_size_tetra_y[3] = &ddr_map_size->tetra_b_y; + virt_size_tetra_y[4] = &ddr_map_size->tetra_ratb_y; + virt_size_tetra_y[5] = &ddr_map_size->tetra_batr_y; + + buff_realloced = false; + for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) { + buff_realloced |= + reallocate_buffer(virt_addr_tetra_x[i], + virt_size_tetra_x[i], + (size_t) + (MORPH_PLANE_BYTES(binary)), + params->morph_table_changed, + &err); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + buff_realloced |= + reallocate_buffer(virt_addr_tetra_y[i], + virt_size_tetra_y[i], + (size_t) + (MORPH_PLANE_BYTES(binary)), + params->morph_table_changed, + &err); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + } + if (params->morph_table_changed || buff_realloced) { + const struct ia_css_morph_table *table = params->morph_table; + struct ia_css_morph_table *id_table = NULL; + + if ((table != NULL) && + (table->width < binary->morph_tbl_width || + table->height < binary->morph_tbl_height)) { + table = NULL; + } + if (table == NULL) { + err = sh_css_params_default_morph_table(&id_table, + binary); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + table = id_table; + } + + for (i = 0; i < IA_CSS_MORPH_TABLE_NUM_PLANES; i++) { + store_morph_plane(table->coordinates_x[i], + table->width, + table->height, + *virt_addr_tetra_x[i], + binary->morph_tbl_aligned_width); + store_morph_plane(table->coordinates_y[i], + table->width, + table->height, + *virt_addr_tetra_y[i], + binary->morph_tbl_aligned_width); + } + if (id_table != NULL) + ia_css_morph_table_free(id_table); + } + } + + /* After special cases like SC, FPN since they may change parameters */ + for (mem = 0; mem < N_IA_CSS_MEMORIES; mem++) { + const struct ia_css_isp_data *isp_data = + ia_css_isp_param_get_isp_mem_init(&binary->info->sp.mem_initializers, IA_CSS_PARAM_CLASS_PARAM, mem); + size_t size = isp_data->size; + if (!size) continue; + buff_realloced = reallocate_buffer(&ddr_map->isp_mem_param[stage_num][mem], + &ddr_map_size->isp_mem_param[stage_num][mem], + size, + params->isp_mem_params_changed[pipe_id][stage_num][mem], + &err); + if (err != IA_CSS_SUCCESS) { + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + if (params->isp_mem_params_changed[pipe_id][stage_num][mem] || buff_realloced) { + sh_css_update_isp_mem_params_to_ddr(binary, + ddr_map->isp_mem_param[stage_num][mem], + ddr_map_size->isp_mem_param[stage_num][mem], mem); + } + } + + IA_CSS_LEAVE_ERR_PRIVATE(IA_CSS_SUCCESS); + return IA_CSS_SUCCESS; +} + +const struct ia_css_fpn_table *ia_css_get_fpn_table(struct ia_css_stream *stream) +{ + struct ia_css_isp_parameters *params; + + IA_CSS_ENTER_LEAVE("void"); + assert(stream != NULL); + + params = stream->isp_params_configs; + + return &(params->fpn_config); +} + +struct ia_css_shading_table *ia_css_get_shading_table(struct ia_css_stream *stream) +{ + struct ia_css_shading_table *table = NULL; + struct ia_css_isp_parameters *params; + + IA_CSS_ENTER("void"); + + assert(stream != NULL); + + params = stream->isp_params_configs; + if (!params) + return NULL; + + if (params->shading_settings.enable_shading_table_conversion == 0) { + if (params->sc_table) { + table = (struct ia_css_shading_table *)params->sc_table; + } else { + const struct ia_css_binary *binary + = ia_css_stream_get_shading_correction_binary(stream); + if (binary) { + /* generate the identical shading table */ + if (params->sc_config) { + ia_css_shading_table_free(params->sc_config); + params->sc_config = NULL; + } +#ifndef ISP2401 + sh_css_params_shading_id_table_generate(¶ms->sc_config, binary); + +#else + sh_css_params_shading_id_table_generate(¶ms->sc_config, + binary->sctbl_width_per_color, binary->sctbl_height); +#endif + table = params->sc_config; + /* The sc_config will be freed in the + * ia_css_stream_isp_parameters_uninit function. */ + } + } + } else { +/* ------ deprecated(bz675) : from ------ */ + const struct ia_css_binary *binary + = ia_css_stream_get_shading_correction_binary(stream); + struct ia_css_pipe *pipe; + + /**********************************************************************/ + /* following code is copied from function ia_css_stream_get_shading_correction_binary() + * to match with the binary */ + pipe = stream->pipes[0]; + + if (stream->num_pipes == 2) { + assert(stream->pipes[1] != NULL); + if (stream->pipes[1]->config.mode == IA_CSS_PIPE_MODE_VIDEO || + stream->pipes[1]->config.mode == IA_CSS_PIPE_MODE_PREVIEW) + pipe = stream->pipes[1]; + } + /**********************************************************************/ + if (binary) { + if (params->sc_config) { + ia_css_shading_table_free(params->sc_config); + params->sc_config = NULL; + } + prepare_shading_table( + (const struct ia_css_shading_table *)params->sc_table, + params->sensor_binning, + ¶ms->sc_config, + binary, pipe->required_bds_factor); + + table = params->sc_config; + /* The sc_config will be freed in the + * ia_css_stream_isp_parameters_uninit function. */ + } +/* ------ deprecated(bz675) : to ------ */ + } + + IA_CSS_LEAVE("table=%p", table); + + return table; +} + + +hrt_vaddress sh_css_store_sp_group_to_ddr(void) +{ + IA_CSS_ENTER_LEAVE_PRIVATE("void"); + mmgr_store(xmem_sp_group_ptrs, + &sh_css_sp_group, + sizeof(struct sh_css_sp_group)); + return xmem_sp_group_ptrs; +} + +hrt_vaddress sh_css_store_sp_stage_to_ddr( + unsigned pipe, + unsigned stage) +{ + IA_CSS_ENTER_LEAVE_PRIVATE("void"); + mmgr_store(xmem_sp_stage_ptrs[pipe][stage], + &sh_css_sp_stage, + sizeof(struct sh_css_sp_stage)); + return xmem_sp_stage_ptrs[pipe][stage]; +} + +hrt_vaddress sh_css_store_isp_stage_to_ddr( + unsigned pipe, + unsigned stage) +{ + IA_CSS_ENTER_LEAVE_PRIVATE("void"); + mmgr_store(xmem_isp_stage_ptrs[pipe][stage], + &sh_css_isp_stage, + sizeof(struct sh_css_isp_stage)); + return xmem_isp_stage_ptrs[pipe][stage]; +} + +static enum ia_css_err ref_sh_css_ddr_address_map( + struct sh_css_ddr_address_map *map, + struct sh_css_ddr_address_map *out) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + unsigned int i; + + /* we will use a union to copy things; overlaying an array + with the struct; that way adding fields in the struct + will keep things working, and we will not get type errors. + */ + union { + struct sh_css_ddr_address_map *map; + hrt_vaddress *addrs; + } in_addrs, to_addrs; + + IA_CSS_ENTER_PRIVATE("void"); + assert(map != NULL); + assert(out != NULL); + + in_addrs.map = map; + to_addrs.map = out; + + assert(sizeof(struct sh_css_ddr_address_map_size)/sizeof(size_t) == + sizeof(struct sh_css_ddr_address_map)/sizeof(hrt_vaddress)); + + /* copy map using size info */ + for (i = 0; i < (sizeof(struct sh_css_ddr_address_map_size)/ + sizeof(size_t)); i++) { + if (in_addrs.addrs[i] == mmgr_NULL) + to_addrs.addrs[i] = mmgr_NULL; + else + to_addrs.addrs[i] = ia_css_refcount_increment(IA_CSS_REFCOUNT_PARAM_BUFFER, in_addrs.addrs[i]); + } + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static enum ia_css_err write_ia_css_isp_parameter_set_info_to_ddr( + struct ia_css_isp_parameter_set_info *me, + hrt_vaddress *out) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + bool succ; + + IA_CSS_ENTER_PRIVATE("void"); + + assert(me != NULL); + assert(out != NULL); + + *out = ia_css_refcount_increment(IA_CSS_REFCOUNT_PARAM_SET_POOL, mmgr_malloc( + sizeof(struct ia_css_isp_parameter_set_info))); + succ = (*out != mmgr_NULL); + if (succ) + mmgr_store(*out, + me, sizeof(struct ia_css_isp_parameter_set_info)); + else + err = IA_CSS_ERR_CANNOT_ALLOCATE_MEMORY; + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +static enum ia_css_err +free_ia_css_isp_parameter_set_info( + hrt_vaddress ptr) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + struct ia_css_isp_parameter_set_info isp_params_info; + unsigned int i; + hrt_vaddress *addrs = (hrt_vaddress *)&isp_params_info.mem_map; + + IA_CSS_ENTER_PRIVATE("ptr = %p", ptr); + + /* sanity check - ptr must be valid */ + if (!ia_css_refcount_is_valid(ptr)) { + IA_CSS_ERROR("%s: IA_CSS_REFCOUNT_PARAM_SET_POOL(0x%x) invalid arg", __func__, ptr); + err = IA_CSS_ERR_INVALID_ARGUMENTS; + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; + } + + mmgr_load(ptr, &isp_params_info.mem_map, sizeof(struct sh_css_ddr_address_map)); + /* copy map using size info */ + for (i = 0; i < (sizeof(struct sh_css_ddr_address_map_size)/ + sizeof(size_t)); i++) { + if (addrs[i] == mmgr_NULL) + continue; + + /* sanity check - ptr must be valid */ +#ifndef ISP2401 + if (!ia_css_refcount_is_valid(addrs[i])) { +#else + if (ia_css_refcount_is_valid(addrs[i])) { + ia_css_refcount_decrement(IA_CSS_REFCOUNT_PARAM_BUFFER, addrs[i]); + } else { +#endif + IA_CSS_ERROR("%s: IA_CSS_REFCOUNT_PARAM_BUFFER(0x%x) invalid arg", __func__, ptr); + err = IA_CSS_ERR_INVALID_ARGUMENTS; + continue; + } +#ifndef ISP2401 + + ia_css_refcount_decrement(IA_CSS_REFCOUNT_PARAM_BUFFER, addrs[i]); +#endif + } + ia_css_refcount_decrement(IA_CSS_REFCOUNT_PARAM_SET_POOL, ptr); + + IA_CSS_LEAVE_ERR_PRIVATE(err); + return err; +} + +/* Mark all parameters as changed to force recomputing the derived ISP parameters */ +void +sh_css_invalidate_params(struct ia_css_stream *stream) +{ + struct ia_css_isp_parameters *params; + unsigned i, j, mem; + + IA_CSS_ENTER_PRIVATE("void"); + assert(stream != NULL); + + params = stream->isp_params_configs; + params->isp_params_changed = true; + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { + for (j = 0; j < SH_CSS_MAX_STAGES; j++) { + for (mem = 0; mem < N_IA_CSS_MEMORIES; mem++) { + params->isp_mem_params_changed[i][j][mem] = true; + } + } + } + + memset(¶ms->config_changed[0], 1, sizeof(params->config_changed)); + params->dis_coef_table_changed = true; + params->dvs2_coef_table_changed = true; + params->morph_table_changed = true; + params->sc_table_changed = true; + params->dz_config_changed = true; + params->motion_config_changed = true; + + /*Free up theDVS table memory blocks before recomputing new table */ + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { + if (params->pipe_dvs_6axis_config[i]) { + free_dvs_6axis_table(&(params->pipe_dvs_6axis_config[i])); + params->pipe_dvs_6axis_config_changed[i] = true; + } + } + + IA_CSS_LEAVE_PRIVATE("void"); +} + +void +sh_css_update_uds_and_crop_info( + const struct ia_css_binary_info *info, + const struct ia_css_frame_info *in_frame_info, + const struct ia_css_frame_info *out_frame_info, + const struct ia_css_resolution *dvs_env, + const struct ia_css_dz_config *zoom, + const struct ia_css_vector *motion_vector, + struct sh_css_uds_info *uds, /* out */ + struct sh_css_crop_pos *sp_out_crop_pos, /* out */ + bool enable_zoom) +{ + IA_CSS_ENTER_PRIVATE("void"); + + assert(info != NULL); + assert(in_frame_info != NULL); + assert(out_frame_info != NULL); + assert(dvs_env != NULL); + assert(zoom != NULL); + assert(motion_vector != NULL); + assert(uds != NULL); + assert(sp_out_crop_pos != NULL); + + uds->curr_dx = enable_zoom ? (uint16_t)zoom->dx : HRT_GDC_N; + uds->curr_dy = enable_zoom ? (uint16_t)zoom->dy : HRT_GDC_N; + + if (info->enable.dvs_envelope) { + unsigned int crop_x = 0, + crop_y = 0, + uds_xc = 0, + uds_yc = 0, + env_width, env_height; + int half_env_x, half_env_y; + int motion_x = motion_vector->x; + int motion_y = motion_vector->y; + bool upscale_x = in_frame_info->res.width < out_frame_info->res.width; + bool upscale_y = in_frame_info->res.height < out_frame_info->res.height; + + if (info->enable.uds && !info->enable.ds) { + /** + * we calculate with the envelope that we can actually + * use, the min dvs envelope is for the filter + * initialization. + */ + env_width = dvs_env->width - + SH_CSS_MIN_DVS_ENVELOPE; + env_height = dvs_env->height - + SH_CSS_MIN_DVS_ENVELOPE; + half_env_x = env_width / 2; + half_env_y = env_height / 2; + /** + * for digital zoom, we use the dvs envelope and make + * sure that we don't include the 8 leftmost pixels or + * 8 topmost rows. + */ + if (upscale_x) { + uds_xc = (in_frame_info->res.width + + env_width + + SH_CSS_MIN_DVS_ENVELOPE) / 2; + } else { + uds_xc = (out_frame_info->res.width + + env_width) / 2 + + SH_CSS_MIN_DVS_ENVELOPE; + } + if (upscale_y) { + uds_yc = (in_frame_info->res.height + + env_height + + SH_CSS_MIN_DVS_ENVELOPE) / 2; + } else { + uds_yc = (out_frame_info->res.height + + env_height) / 2 + + SH_CSS_MIN_DVS_ENVELOPE; + } + /* clip the motion vector to +/- half the envelope */ + motion_x = clamp(motion_x, -half_env_x, half_env_x); + motion_y = clamp(motion_y, -half_env_y, half_env_y); + uds_xc += motion_x; + uds_yc += motion_y; + /* uds can be pipelined, remove top lines */ + crop_y = 2; + } else if (info->enable.ds) { + env_width = dvs_env->width; + env_height = dvs_env->height; + half_env_x = env_width / 2; + half_env_y = env_height / 2; + /* clip the motion vector to +/- half the envelope */ + motion_x = clamp(motion_x, -half_env_x, half_env_x); + motion_y = clamp(motion_y, -half_env_y, half_env_y); + /* for video with downscaling, the envelope is included + in the input resolution. */ + uds_xc = in_frame_info->res.width/2 + motion_x; + uds_yc = in_frame_info->res.height/2 + motion_y; + crop_x = info->pipeline.left_cropping; + /* ds == 2 (yuv_ds) can be pipelined, remove top + lines */ + if (info->enable.ds & 1) + crop_y = info->pipeline.top_cropping; + else + crop_y = 2; + } else { + /* video nodz: here we can only crop. We make sure we + crop at least the first 8x8 pixels away. */ + env_width = dvs_env->width - + SH_CSS_MIN_DVS_ENVELOPE; + env_height = dvs_env->height - + SH_CSS_MIN_DVS_ENVELOPE; + half_env_x = env_width / 2; + half_env_y = env_height / 2; + motion_x = clamp(motion_x, -half_env_x, half_env_x); + motion_y = clamp(motion_y, -half_env_y, half_env_y); + crop_x = SH_CSS_MIN_DVS_ENVELOPE + + half_env_x + motion_x; + crop_y = SH_CSS_MIN_DVS_ENVELOPE + + half_env_y + motion_y; + } + + /* Must enforce that the crop position is even */ + crop_x = EVEN_FLOOR(crop_x); + crop_y = EVEN_FLOOR(crop_y); + uds_xc = EVEN_FLOOR(uds_xc); + uds_yc = EVEN_FLOOR(uds_yc); + + uds->xc = (uint16_t)uds_xc; + uds->yc = (uint16_t)uds_yc; + sp_out_crop_pos->x = (uint16_t)crop_x; + sp_out_crop_pos->y = (uint16_t)crop_y; + } + else { + /* for down scaling, we always use the center of the image */ + uds->xc = (uint16_t)in_frame_info->res.width / 2; + uds->yc = (uint16_t)in_frame_info->res.height / 2; + sp_out_crop_pos->x = (uint16_t)info->pipeline.left_cropping; + sp_out_crop_pos->y = (uint16_t)info->pipeline.top_cropping; + } + IA_CSS_LEAVE_PRIVATE("void"); +} + +static enum ia_css_err +sh_css_update_uds_and_crop_info_based_on_zoom_region( + const struct ia_css_binary_info *info, + const struct ia_css_frame_info *in_frame_info, + const struct ia_css_frame_info *out_frame_info, + const struct ia_css_resolution *dvs_env, + const struct ia_css_dz_config *zoom, + const struct ia_css_vector *motion_vector, + struct sh_css_uds_info *uds, /* out */ + struct sh_css_crop_pos *sp_out_crop_pos, /* out */ + struct ia_css_resolution pipe_in_res, + bool enable_zoom) +{ + unsigned int x0 = 0, y0 = 0, x1 = 0, y1 = 0; + enum ia_css_err err = IA_CSS_SUCCESS; + /* Note: + * Filter_Envelope = 0 for NND/LUT + * Filter_Envelope = 1 for BCI + * Filter_Envelope = 3 for BLI + * Currently, not considering this filter envelope because, In uds.sp.c is recalculating + * the dx/dy based on filter envelope and other information (ia_css_uds_sp_scale_params) + * Ideally, That should be done on host side not on sp side. + */ + unsigned int filter_envelope = 0; + IA_CSS_ENTER_PRIVATE("void"); + + assert(info != NULL); + assert(in_frame_info != NULL); + assert(out_frame_info != NULL); + assert(dvs_env != NULL); + assert(zoom != NULL); + assert(motion_vector != NULL); + assert(uds != NULL); + assert(sp_out_crop_pos != NULL); + x0 = zoom->zoom_region.origin.x; + y0 = zoom->zoom_region.origin.y; + x1 = zoom->zoom_region.resolution.width + x0; + y1 = zoom->zoom_region.resolution.height + y0; + + if ((x0 > x1) || (y0 > y1) || (x1 > pipe_in_res.width) || (y1 > pipe_in_res.height)) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + if (!enable_zoom) { + uds->curr_dx = HRT_GDC_N; + uds->curr_dy = HRT_GDC_N; + } + + if (info->enable.dvs_envelope) { + /* Zoom region is only supported by the UDS module on ISP + * 2 and higher. It is not supported in video mode on ISP 1 */ + return IA_CSS_ERR_INVALID_ARGUMENTS; + } else { + if (enable_zoom) { + /* A. Calculate dx/dy based on crop region using in_frame_info + * Scale the crop region if in_frame_info to the stage is not same as + * actual effective input of the pipeline + */ + if (in_frame_info->res.width != pipe_in_res.width || + in_frame_info->res.height != pipe_in_res.height) { + x0 = (x0 * in_frame_info->res.width) / (pipe_in_res.width); + y0 = (y0 * in_frame_info->res.height) / (pipe_in_res.height); + x1 = (x1 * in_frame_info->res.width) / (pipe_in_res.width); + y1 = (y1 * in_frame_info->res.height) / (pipe_in_res.height); + } + uds->curr_dx = + ((x1 - x0 - filter_envelope) * HRT_GDC_N) / in_frame_info->res.width; + uds->curr_dy = + ((y1 - y0 - filter_envelope) * HRT_GDC_N) / in_frame_info->res.height; + + /* B. Calculate xc/yc based on crop region */ + uds->xc = (uint16_t) x0 + (((x1)-(x0)) / 2); + uds->yc = (uint16_t) y0 + (((y1)-(y0)) / 2); + } else { + uds->xc = (uint16_t)in_frame_info->res.width / 2; + uds->yc = (uint16_t)in_frame_info->res.height / 2; + } + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "uds->curr_dx=%d, uds->xc=%d, uds->yc=%d\n", + uds->curr_dx, uds->xc, uds->yc); + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE, "x0=%d, y0=%d, x1=%d, y1=%d\n", + x0, y0, x1, y1); + sp_out_crop_pos->x = (uint16_t)info->pipeline.left_cropping; + sp_out_crop_pos->y = (uint16_t)info->pipeline.top_cropping; + } + IA_CSS_LEAVE_PRIVATE("void"); + return err; +} + +struct ia_css_3a_statistics * +ia_css_3a_statistics_allocate(const struct ia_css_3a_grid_info *grid) +{ + struct ia_css_3a_statistics *me; + int grid_size; + + IA_CSS_ENTER("grid=%p", grid); + + assert(grid != NULL); + + me = sh_css_calloc(1, sizeof(*me)); + if (!me) + goto err; + + me->grid = *grid; + grid_size = grid->width * grid->height; + me->data = sh_css_malloc(grid_size * sizeof(*me->data)); + if (!me->data) + goto err; +#if !defined(HAS_NO_HMEM) + /* No weighted histogram, no structure, treat the histogram data as a byte dump in a byte array */ + me->rgby_data = (struct ia_css_3a_rgby_output *)sh_css_malloc(sizeof_hmem(HMEM0_ID)); +#else + me->rgby_data = NULL; +#endif + + IA_CSS_LEAVE("return=%p", me); + return me; +err: + ia_css_3a_statistics_free(me); + + IA_CSS_LEAVE("return=%p", NULL); + return NULL; +} + +void +ia_css_3a_statistics_free(struct ia_css_3a_statistics *me) +{ + if (me) { + sh_css_free(me->rgby_data); + sh_css_free(me->data); + memset(me, 0, sizeof(struct ia_css_3a_statistics)); + sh_css_free(me); + } +} + +struct ia_css_dvs_statistics * +ia_css_dvs_statistics_allocate(const struct ia_css_dvs_grid_info *grid) +{ + struct ia_css_dvs_statistics *me; + + assert(grid != NULL); + + me = sh_css_calloc(1, sizeof(*me)); + if (!me) + goto err; + + me->grid = *grid; + me->hor_proj = sh_css_malloc(grid->height * IA_CSS_DVS_NUM_COEF_TYPES * + sizeof(*me->hor_proj)); + if (!me->hor_proj) + goto err; + + me->ver_proj = sh_css_malloc(grid->width * IA_CSS_DVS_NUM_COEF_TYPES * + sizeof(*me->ver_proj)); + if (!me->ver_proj) + goto err; + + return me; +err: + ia_css_dvs_statistics_free(me); + return NULL; + +} + +void +ia_css_dvs_statistics_free(struct ia_css_dvs_statistics *me) +{ + if (me) { + sh_css_free(me->hor_proj); + sh_css_free(me->ver_proj); + memset(me, 0, sizeof(struct ia_css_dvs_statistics)); + sh_css_free(me); + } +} + +struct ia_css_dvs_coefficients * +ia_css_dvs_coefficients_allocate(const struct ia_css_dvs_grid_info *grid) +{ + struct ia_css_dvs_coefficients *me; + + assert(grid != NULL); + + me = sh_css_calloc(1, sizeof(*me)); + if (!me) + goto err; + + me->grid = *grid; + + me->hor_coefs = sh_css_malloc(grid->num_hor_coefs * + IA_CSS_DVS_NUM_COEF_TYPES * + sizeof(*me->hor_coefs)); + if (!me->hor_coefs) + goto err; + + me->ver_coefs = sh_css_malloc(grid->num_ver_coefs * + IA_CSS_DVS_NUM_COEF_TYPES * + sizeof(*me->ver_coefs)); + if (!me->ver_coefs) + goto err; + + return me; +err: + ia_css_dvs_coefficients_free(me); + return NULL; +} + +void +ia_css_dvs_coefficients_free(struct ia_css_dvs_coefficients *me) +{ + if (me) { + sh_css_free(me->hor_coefs); + sh_css_free(me->ver_coefs); + memset(me, 0, sizeof(struct ia_css_dvs_coefficients)); + sh_css_free(me); + } +} + +struct ia_css_dvs2_statistics * +ia_css_dvs2_statistics_allocate(const struct ia_css_dvs_grid_info *grid) +{ + struct ia_css_dvs2_statistics *me; + + assert(grid != NULL); + + me = sh_css_calloc(1, sizeof(*me)); + if (!me) + goto err; + + me->grid = *grid; + + me->hor_prod.odd_real = sh_css_malloc(grid->aligned_width * + grid->aligned_height * sizeof(*me->hor_prod.odd_real)); + if (!me->hor_prod.odd_real) + goto err; + + me->hor_prod.odd_imag = sh_css_malloc(grid->aligned_width * + grid->aligned_height * sizeof(*me->hor_prod.odd_imag)); + if (!me->hor_prod.odd_imag) + goto err; + + me->hor_prod.even_real = sh_css_malloc(grid->aligned_width * + grid->aligned_height * sizeof(*me->hor_prod.even_real)); + if (!me->hor_prod.even_real) + goto err; + + me->hor_prod.even_imag = sh_css_malloc(grid->aligned_width * + grid->aligned_height * sizeof(*me->hor_prod.even_imag)); + if (!me->hor_prod.even_imag) + goto err; + + me->ver_prod.odd_real = sh_css_malloc(grid->aligned_width * + grid->aligned_height * sizeof(*me->ver_prod.odd_real)); + if (!me->ver_prod.odd_real) + goto err; + + me->ver_prod.odd_imag = sh_css_malloc(grid->aligned_width * + grid->aligned_height * sizeof(*me->ver_prod.odd_imag)); + if (!me->ver_prod.odd_imag) + goto err; + + me->ver_prod.even_real = sh_css_malloc(grid->aligned_width * + grid->aligned_height * sizeof(*me->ver_prod.even_real)); + if (!me->ver_prod.even_real) + goto err; + + me->ver_prod.even_imag = sh_css_malloc(grid->aligned_width * + grid->aligned_height * sizeof(*me->ver_prod.even_imag)); + if (!me->ver_prod.even_imag) + goto err; + + return me; +err: + ia_css_dvs2_statistics_free(me); + return NULL; + +} + +void +ia_css_dvs2_statistics_free(struct ia_css_dvs2_statistics *me) +{ + if (me) { + sh_css_free(me->hor_prod.odd_real); + sh_css_free(me->hor_prod.odd_imag); + sh_css_free(me->hor_prod.even_real); + sh_css_free(me->hor_prod.even_imag); + sh_css_free(me->ver_prod.odd_real); + sh_css_free(me->ver_prod.odd_imag); + sh_css_free(me->ver_prod.even_real); + sh_css_free(me->ver_prod.even_imag); + memset(me, 0, sizeof(struct ia_css_dvs2_statistics)); + sh_css_free(me); + } +} + + +struct ia_css_dvs2_coefficients * +ia_css_dvs2_coefficients_allocate(const struct ia_css_dvs_grid_info *grid) +{ + struct ia_css_dvs2_coefficients *me; + + assert(grid != NULL); + + me = sh_css_calloc(1, sizeof(*me)); + if (!me) + goto err; + + me->grid = *grid; + + me->hor_coefs.odd_real = sh_css_malloc(grid->num_hor_coefs * + sizeof(*me->hor_coefs.odd_real)); + if (!me->hor_coefs.odd_real) + goto err; + + me->hor_coefs.odd_imag = sh_css_malloc(grid->num_hor_coefs * + sizeof(*me->hor_coefs.odd_imag)); + if (!me->hor_coefs.odd_imag) + goto err; + + me->hor_coefs.even_real = sh_css_malloc(grid->num_hor_coefs * + sizeof(*me->hor_coefs.even_real)); + if (!me->hor_coefs.even_real) + goto err; + + me->hor_coefs.even_imag = sh_css_malloc(grid->num_hor_coefs * + sizeof(*me->hor_coefs.even_imag)); + if (!me->hor_coefs.even_imag) + goto err; + + me->ver_coefs.odd_real = sh_css_malloc(grid->num_ver_coefs * + sizeof(*me->ver_coefs.odd_real)); + if (!me->ver_coefs.odd_real) + goto err; + + me->ver_coefs.odd_imag = sh_css_malloc(grid->num_ver_coefs * + sizeof(*me->ver_coefs.odd_imag)); + if (!me->ver_coefs.odd_imag) + goto err; + + me->ver_coefs.even_real = sh_css_malloc(grid->num_ver_coefs * + sizeof(*me->ver_coefs.even_real)); + if (!me->ver_coefs.even_real) + goto err; + + me->ver_coefs.even_imag = sh_css_malloc(grid->num_ver_coefs * + sizeof(*me->ver_coefs.even_imag)); + if (!me->ver_coefs.even_imag) + goto err; + + return me; +err: + ia_css_dvs2_coefficients_free(me); + return NULL; +} + +void +ia_css_dvs2_coefficients_free(struct ia_css_dvs2_coefficients *me) +{ + if (me) { + sh_css_free(me->hor_coefs.odd_real); + sh_css_free(me->hor_coefs.odd_imag); + sh_css_free(me->hor_coefs.even_real); + sh_css_free(me->hor_coefs.even_imag); + sh_css_free(me->ver_coefs.odd_real); + sh_css_free(me->ver_coefs.odd_imag); + sh_css_free(me->ver_coefs.even_real); + sh_css_free(me->ver_coefs.even_imag); + memset(me, 0, sizeof(struct ia_css_dvs2_coefficients)); + sh_css_free(me); + } +} + +struct ia_css_dvs_6axis_config * +ia_css_dvs2_6axis_config_allocate(const struct ia_css_stream *stream) +{ + struct ia_css_dvs_6axis_config *dvs_config = NULL; + struct ia_css_isp_parameters *params = NULL; + unsigned int width_y; + unsigned int height_y; + unsigned int width_uv; + unsigned int height_uv; + + assert(stream != NULL); + params = stream->isp_params_configs; + + /* Backward compatibility by default consider pipe as Video*/ + if (!params || (params && !params->pipe_dvs_6axis_config[IA_CSS_PIPE_ID_VIDEO])) { + goto err; + } + + dvs_config = (struct ia_css_dvs_6axis_config *)sh_css_calloc(1, sizeof(struct ia_css_dvs_6axis_config)); + if (!dvs_config) + goto err; + + dvs_config->width_y = width_y = params->pipe_dvs_6axis_config[IA_CSS_PIPE_ID_VIDEO]->width_y; + dvs_config->height_y = height_y = params->pipe_dvs_6axis_config[IA_CSS_PIPE_ID_VIDEO]->height_y; + dvs_config->width_uv = width_uv = params->pipe_dvs_6axis_config[IA_CSS_PIPE_ID_VIDEO]->width_uv; + dvs_config->height_uv = height_uv = params->pipe_dvs_6axis_config[IA_CSS_PIPE_ID_VIDEO]->height_uv; + IA_CSS_LOG("table Y: W %d H %d", width_y, height_y); + IA_CSS_LOG("table UV: W %d H %d", width_uv, height_uv); + dvs_config->xcoords_y = (uint32_t *)sh_css_malloc(width_y * height_y * sizeof(uint32_t)); + if (!dvs_config->xcoords_y) + goto err; + + dvs_config->ycoords_y = (uint32_t *)sh_css_malloc(width_y * height_y * sizeof(uint32_t)); + if (!dvs_config->ycoords_y) + goto err; + + dvs_config->xcoords_uv = (uint32_t *)sh_css_malloc(width_uv * height_uv * sizeof(uint32_t)); + if (!dvs_config->xcoords_uv) + goto err; + + dvs_config->ycoords_uv = (uint32_t *)sh_css_malloc(width_uv * height_uv * sizeof(uint32_t)); + if (!dvs_config->ycoords_uv) + goto err; + + return dvs_config; +err: + ia_css_dvs2_6axis_config_free(dvs_config); + return NULL; +} + +void +ia_css_dvs2_6axis_config_free(struct ia_css_dvs_6axis_config *dvs_6axis_config) +{ + if (dvs_6axis_config) { + sh_css_free(dvs_6axis_config->xcoords_y); + sh_css_free(dvs_6axis_config->ycoords_y); + sh_css_free(dvs_6axis_config->xcoords_uv); + sh_css_free(dvs_6axis_config->ycoords_uv); + memset(dvs_6axis_config, 0, sizeof(struct ia_css_dvs_6axis_config)); + sh_css_free(dvs_6axis_config); + } +} + +void +ia_css_en_dz_capt_pipe(struct ia_css_stream *stream, bool enable) +{ + struct ia_css_pipe *pipe; + struct ia_css_pipeline *pipeline; + struct ia_css_pipeline_stage *stage; + enum ia_css_pipe_id pipe_id; + enum ia_css_err err; + int i; + + if (stream == NULL) + return; + + for (i = 0; i < stream->num_pipes; i++) { + pipe = stream->pipes[i]; + pipeline = ia_css_pipe_get_pipeline(pipe); + pipe_id = pipeline->pipe_id; + + if (pipe_id == IA_CSS_PIPE_ID_CAPTURE) { + err = ia_css_pipeline_get_stage(pipeline, IA_CSS_BINARY_MODE_CAPTURE_PP, &stage); + if (err == IA_CSS_SUCCESS) + stage->enable_zoom = enable; + break; + } + } +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_params.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_params.h new file mode 100644 index 0000000000000000000000000000000000000000..a7ffe6d8331bd68a7d5e3d53f87f978bf73c99b0 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_params.h @@ -0,0 +1,188 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_PARAMS_H_ +#define _SH_CSS_PARAMS_H_ + +/*! \file */ + +/* Forward declaration to break mutual dependency */ +struct ia_css_isp_parameters; + +#include +#include "ia_css_types.h" +#include "ia_css_binary.h" +#include "sh_css_legacy.h" + +#include "sh_css_defs.h" /* SH_CSS_MAX_STAGES */ +#include "ia_css_pipeline.h" +#include "ia_css_isp_params.h" +#include "uds/uds_1.0/ia_css_uds_param.h" +#include "crop/crop_1.0/ia_css_crop_types.h" + + +#define PIX_SHIFT_FILTER_RUN_IN_X 12 +#define PIX_SHIFT_FILTER_RUN_IN_Y 12 + +#include "ob/ob_1.0/ia_css_ob_param.h" +/* Isp configurations per stream */ +struct sh_css_isp_param_configs { + /* OB (Optical Black) */ + struct sh_css_isp_ob_stream_config ob; +}; + + +/* Isp parameters per stream */ +struct ia_css_isp_parameters { + /* UDS */ + struct sh_css_sp_uds_params uds[SH_CSS_MAX_STAGES]; + struct sh_css_isp_param_configs stream_configs; + struct ia_css_fpn_table fpn_config; + struct ia_css_vector motion_config; + const struct ia_css_morph_table *morph_table; + const struct ia_css_shading_table *sc_table; + struct ia_css_shading_table *sc_config; + struct ia_css_macc_table macc_table; + struct ia_css_gamma_table gc_table; + struct ia_css_ctc_table ctc_table; + struct ia_css_xnr_table xnr_table; + + struct ia_css_dz_config dz_config; + struct ia_css_3a_config s3a_config; + struct ia_css_wb_config wb_config; + struct ia_css_cc_config cc_config; + struct ia_css_cc_config yuv2rgb_cc_config; + struct ia_css_cc_config rgb2yuv_cc_config; + struct ia_css_tnr_config tnr_config; + struct ia_css_ob_config ob_config; + /*----- DPC configuration -----*/ + /* The default DPC configuration is retained and currently set + * using the stream configuration. The code generated from genparams + * uses this configuration to set the DPC parameters per stage but this + * will be overwritten by the per pipe configuration */ + struct ia_css_dp_config dp_config; + /* ------ pipe specific DPC configuration ------ */ + /* Please note that this implementation is a temporary solution and + * should be replaced by CSS per pipe configuration when the support + * is ready (HSD 1303967698)*/ + struct ia_css_dp_config pipe_dp_config[IA_CSS_PIPE_ID_NUM]; + struct ia_css_nr_config nr_config; + struct ia_css_ee_config ee_config; + struct ia_css_de_config de_config; + struct ia_css_gc_config gc_config; + struct ia_css_anr_config anr_config; + struct ia_css_ce_config ce_config; + struct ia_css_formats_config formats_config; +/* ---- deprecated: replaced with pipe_dvs_6axis_config---- */ + struct ia_css_dvs_6axis_config *dvs_6axis_config; + struct ia_css_ecd_config ecd_config; + struct ia_css_ynr_config ynr_config; + struct ia_css_yee_config yee_config; + struct ia_css_fc_config fc_config; + struct ia_css_cnr_config cnr_config; + struct ia_css_macc_config macc_config; + struct ia_css_ctc_config ctc_config; + struct ia_css_aa_config aa_config; + struct ia_css_aa_config bds_config; + struct ia_css_aa_config raa_config; + struct ia_css_rgb_gamma_table r_gamma_table; + struct ia_css_rgb_gamma_table g_gamma_table; + struct ia_css_rgb_gamma_table b_gamma_table; + struct ia_css_anr_thres anr_thres; + struct ia_css_xnr_config xnr_config; + struct ia_css_xnr3_config xnr3_config; + struct ia_css_uds_config uds_config; + struct ia_css_crop_config crop_config; + struct ia_css_output_config output_config; + struct ia_css_dvs_6axis_config *pipe_dvs_6axis_config[IA_CSS_PIPE_ID_NUM]; +/* ------ deprecated(bz675) : from ------ */ + struct ia_css_shading_settings shading_settings; +/* ------ deprecated(bz675) : to ------ */ + struct ia_css_dvs_coefficients dvs_coefs; + struct ia_css_dvs2_coefficients dvs2_coefs; + + bool isp_params_changed; + bool isp_mem_params_changed + [IA_CSS_PIPE_ID_NUM][SH_CSS_MAX_STAGES][IA_CSS_NUM_MEMORIES]; + bool dz_config_changed; + bool motion_config_changed; + bool dis_coef_table_changed; + bool dvs2_coef_table_changed; + bool morph_table_changed; + bool sc_table_changed; + bool sc_table_dirty; + unsigned int sc_table_last_pipe_num; + bool anr_thres_changed; +/* ---- deprecated: replaced with pipe_dvs_6axis_config_changed ---- */ + bool dvs_6axis_config_changed; + /* ------ pipe specific DPC configuration ------ */ + /* Please note that this implementation is a temporary solution and + * should be replaced by CSS per pipe configuration when the support + * is ready (HSD 1303967698) */ + bool pipe_dpc_config_changed[IA_CSS_PIPE_ID_NUM]; +/* ------ deprecated(bz675) : from ------ */ + bool shading_settings_changed; +/* ------ deprecated(bz675) : to ------ */ + bool pipe_dvs_6axis_config_changed[IA_CSS_PIPE_ID_NUM]; + + bool config_changed[IA_CSS_NUM_PARAMETER_IDS]; + + unsigned int sensor_binning; + /* local buffers, used to re-order the 3a statistics in vmem-format */ + struct sh_css_ddr_address_map pipe_ddr_ptrs[IA_CSS_PIPE_ID_NUM]; + struct sh_css_ddr_address_map_size pipe_ddr_ptrs_size[IA_CSS_PIPE_ID_NUM]; + struct sh_css_ddr_address_map ddr_ptrs; + struct sh_css_ddr_address_map_size ddr_ptrs_size; + struct ia_css_frame *output_frame; /**< Output frame the config is to be applied to (optional) */ + uint32_t isp_parameters_id; /**< Unique ID to track which config was actually applied to a particular frame */ +}; + +void +ia_css_params_store_ia_css_host_data( + hrt_vaddress ddr_addr, + struct ia_css_host_data *data); + +enum ia_css_err +ia_css_params_store_sctbl( + const struct ia_css_pipeline_stage *stage, + hrt_vaddress ddr_addr, + const struct ia_css_shading_table *shading_table); + +struct ia_css_host_data * +ia_css_params_alloc_convert_sctbl( + const struct ia_css_pipeline_stage *stage, + const struct ia_css_shading_table *shading_table); + +struct ia_css_isp_config * +sh_css_pipe_isp_config_get(struct ia_css_pipe *pipe); + +/* ipu address allocation/free for gdc lut */ +hrt_vaddress +sh_css_params_alloc_gdc_lut(void); +void +sh_css_params_free_gdc_lut(hrt_vaddress addr); + +enum ia_css_err +sh_css_params_map_and_store_default_gdc_lut(void); + +void +sh_css_params_free_default_gdc_lut(void); + +hrt_vaddress +sh_css_params_get_default_gdc_lut(void); + +hrt_vaddress +sh_css_pipe_get_pp_gdc_lut(const struct ia_css_pipe *pipe); + +#endif /* _SH_CSS_PARAMS_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_params_internal.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_params_internal.h new file mode 100644 index 0000000000000000000000000000000000000000..baca24532f9ffaf21c5f5621ae0d0c574f27cf9a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_params_internal.h @@ -0,0 +1,21 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_PARAMS_INTERNAL_H_ +#define _SH_CSS_PARAMS_INTERNAL_H_ + +void +sh_css_param_clear_param_sets(void); + +#endif /* _SH_CSS_PARAMS_INTERNAL_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_pipe.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_pipe.c new file mode 100644 index 0000000000000000000000000000000000000000..1f57ffad89214c873d40ba2e12d48596170f2f43 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_pipe.c @@ -0,0 +1,16 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* This file will contain the code to implement the functions declared in ia_css_pipe.h and ia_css_pipe_public.h + and associated helper functions */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_properties.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_properties.c new file mode 100644 index 0000000000000000000000000000000000000000..ad46996cfbd34afc9349755fbbb7ff72658e58f8 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_properties.c @@ -0,0 +1,43 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_properties.h" +#include +#include "ia_css_types.h" +#include "gdc_device.h" + +void +ia_css_get_properties(struct ia_css_properties *properties) +{ + assert(properties != NULL); +#if defined(HAS_GDC_VERSION_2) || defined(HAS_GDC_VERSION_3) +/* + * MW: We don't want to store the coordinates + * full range in memory: Truncate + */ + properties->gdc_coord_one = gdc_get_unity(GDC0_ID)/HRT_GDC_COORD_SCALE; +#else +#error "Unknown GDC version" +#endif + + properties->l1_base_is_index = true; + +#if defined(HAS_VAMEM_VERSION_1) + properties->vamem_type = IA_CSS_VAMEM_TYPE_1; +#elif defined(HAS_VAMEM_VERSION_2) + properties->vamem_type = IA_CSS_VAMEM_TYPE_2; +#else +#error "Unknown VAMEM version" +#endif +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_shading.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_shading.c new file mode 100644 index 0000000000000000000000000000000000000000..2a2d0f4db44b087246d550edc26e5dbae0e1a505 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_shading.c @@ -0,0 +1,16 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* This file will contain the code to implement the functions declared in ia_css_shading.h + and associated helper functions */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_sp.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_sp.c new file mode 100644 index 0000000000000000000000000000000000000000..00b2d1689c50dd9424929aaeb6e89b13800972ca --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_sp.c @@ -0,0 +1,1898 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "sh_css_sp.h" + +#if !defined(HAS_NO_INPUT_FORMATTER) +#include "input_formatter.h" +#endif + +#include "dma.h" /* N_DMA_CHANNEL_ID */ + +#include "ia_css_buffer.h" +#include "ia_css_binary.h" +#include "sh_css_hrt.h" +#include "sh_css_defs.h" +#include "sh_css_internal.h" +#include "ia_css_control.h" +#include "ia_css_debug.h" +#include "ia_css_debug_pipe.h" +#include "ia_css_event_public.h" +#include "ia_css_mmu.h" +#include "ia_css_stream.h" +#include "ia_css_isp_param.h" +#include "sh_css_params.h" +#include "sh_css_legacy.h" +#include "ia_css_frame_comm.h" +#if !defined(HAS_NO_INPUT_SYSTEM) +#include "ia_css_isys.h" +#endif + +#include "gdc_device.h" /* HRT_GDC_N */ + +/*#include "sp.h"*/ /* host2sp_enqueue_frame_data() */ + +#include "memory_access.h" + +#include "assert_support.h" +#include "platform_support.h" /* hrt_sleep() */ + +#include "sw_event_global.h" /* Event IDs.*/ +#include "ia_css_event.h" +#include "mmu_device.h" +#include "ia_css_spctrl.h" + +#ifndef offsetof +#define offsetof(T, x) ((unsigned)&(((T *)0)->x)) +#endif + +#define IA_CSS_INCLUDE_CONFIGURATIONS +#include "ia_css_isp_configs.h" +#define IA_CSS_INCLUDE_STATES +#include "ia_css_isp_states.h" + +#ifndef ISP2401 +#include "isp/kernels/io_ls/bayer_io_ls/ia_css_bayer_io.host.h" +#else +#include "isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io.host.h" +#endif + +struct sh_css_sp_group sh_css_sp_group; +struct sh_css_sp_stage sh_css_sp_stage; +struct sh_css_isp_stage sh_css_isp_stage; +struct sh_css_sp_output sh_css_sp_output; +static struct sh_css_sp_per_frame_data per_frame_data; + +/* true if SP supports frame loop and host2sp_commands */ +/* For the moment there is only code that sets this bool to true */ +/* TODO: add code that sets this bool to false */ +static bool sp_running; +#if defined(HAS_SEC_SP) +static bool sp1_running; +#endif /* HAS_SEC_SP */ + +static enum ia_css_err +set_output_frame_buffer(const struct ia_css_frame *frame, + unsigned idx); + +static void +sh_css_copy_buffer_attr_to_spbuffer(struct ia_css_buffer_sp *dest_buf, + const enum sh_css_queue_id queue_id, + const hrt_vaddress xmem_addr, + const enum ia_css_buffer_type buf_type); + +static void +initialize_frame_buffer_attribute(struct ia_css_buffer_sp *buf_attr); + +static void +initialize_stage_frames(struct ia_css_frames_sp *frames); + +/* This data is stored every frame */ +void +store_sp_group_data(void) +{ + per_frame_data.sp_group_addr = sh_css_store_sp_group_to_ddr(); +} + +static void +copy_isp_stage_to_sp_stage(void) +{ + /* [WW07.5]type casting will cause potential issues */ + sh_css_sp_stage.num_stripes = (uint8_t) sh_css_isp_stage.binary_info.iterator.num_stripes; + sh_css_sp_stage.row_stripes_height = (uint16_t) sh_css_isp_stage.binary_info.iterator.row_stripes_height; + sh_css_sp_stage.row_stripes_overlap_lines = (uint16_t) sh_css_isp_stage.binary_info.iterator.row_stripes_overlap_lines; + sh_css_sp_stage.top_cropping = (uint16_t) sh_css_isp_stage.binary_info.pipeline.top_cropping; + /* moved to sh_css_sp_init_stage + sh_css_sp_stage.enable.vf_output = + sh_css_isp_stage.binary_info.enable.vf_veceven || + sh_css_isp_stage.binary_info.num_output_pins > 1; + */ + sh_css_sp_stage.enable.sdis = sh_css_isp_stage.binary_info.enable.dis; + sh_css_sp_stage.enable.s3a = sh_css_isp_stage.binary_info.enable.s3a; +#ifdef ISP2401 + sh_css_sp_stage.enable.lace_stats = sh_css_isp_stage.binary_info.enable.lace_stats; +#endif +} + +void +store_sp_stage_data(enum ia_css_pipe_id id, unsigned int pipe_num, unsigned stage) +{ + unsigned int thread_id; + ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id); + copy_isp_stage_to_sp_stage(); + if (id != IA_CSS_PIPE_ID_COPY) + sh_css_sp_stage.isp_stage_addr = + sh_css_store_isp_stage_to_ddr(pipe_num, stage); + sh_css_sp_group.pipe[thread_id].sp_stage_addr[stage] = + sh_css_store_sp_stage_to_ddr(pipe_num, stage); + + /* Clear for next frame */ + sh_css_sp_stage.program_input_circuit = false; +} + +static void +store_sp_per_frame_data(const struct ia_css_fw_info *fw) +{ + unsigned int HIVE_ADDR_sp_per_frame_data = 0; + + assert(fw != NULL); + + switch (fw->type) { + case ia_css_sp_firmware: + HIVE_ADDR_sp_per_frame_data = fw->info.sp.per_frame_data; + break; +#if defined(HAS_SEC_SP) + case ia_css_sp1_firmware: + (void)fw; + break; +#endif /* HAS_SEC_SP */ + case ia_css_acc_firmware: + HIVE_ADDR_sp_per_frame_data = fw->info.acc.per_frame_data; + break; + case ia_css_isp_firmware: + return; + } + + sp_dmem_store(SP0_ID, + (unsigned int)sp_address_of(sp_per_frame_data), + &per_frame_data, + sizeof(per_frame_data)); +} + +static void +sh_css_store_sp_per_frame_data(enum ia_css_pipe_id pipe_id, + unsigned int pipe_num, + const struct ia_css_fw_info *sp_fw) +{ + if (!sp_fw) + sp_fw = &sh_css_sp_fw; + + store_sp_stage_data(pipe_id, pipe_num, 0); + store_sp_group_data(); + store_sp_per_frame_data(sp_fw); +} + +#if SP_DEBUG != SP_DEBUG_NONE + +void +sh_css_sp_get_debug_state(struct sh_css_sp_debug_state *state) +{ + const struct ia_css_fw_info *fw = &sh_css_sp_fw; + unsigned int HIVE_ADDR_sp_output = fw->info.sp.output; + unsigned i; + unsigned offset = (unsigned int)offsetof(struct sh_css_sp_output, debug)/sizeof(int); + + assert(state != NULL); + + (void)HIVE_ADDR_sp_output; /* To get rid of warning in CRUN */ + for (i = 0; i < sizeof(*state)/sizeof(int); i++) + ((unsigned *)state)[i] = load_sp_array_uint(sp_output, i+offset); +} + +#endif + +void +sh_css_sp_start_binary_copy(unsigned int pipe_num, struct ia_css_frame *out_frame, + unsigned two_ppc) +{ + enum ia_css_pipe_id pipe_id; + unsigned int thread_id; + struct sh_css_sp_pipeline *pipe; + uint8_t stage_num = 0; + + assert(out_frame != NULL); + pipe_id = IA_CSS_PIPE_ID_CAPTURE; + ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id); + pipe = &sh_css_sp_group.pipe[thread_id]; + + pipe->copy.bin.bytes_available = out_frame->data_bytes; + pipe->num_stages = 1; + pipe->pipe_id = pipe_id; + pipe->pipe_num = pipe_num; + pipe->thread_id = thread_id; + pipe->pipe_config = 0x0; /* No parameters */ + pipe->pipe_qos_config = QOS_INVALID; + + if (pipe->inout_port_config == 0) { + SH_CSS_PIPE_PORT_CONFIG_SET(pipe->inout_port_config, + (uint8_t)SH_CSS_PORT_INPUT, + (uint8_t)SH_CSS_HOST_TYPE, 1); + SH_CSS_PIPE_PORT_CONFIG_SET(pipe->inout_port_config, + (uint8_t)SH_CSS_PORT_OUTPUT, + (uint8_t)SH_CSS_HOST_TYPE, 1); + } + IA_CSS_LOG("pipe_id %d port_config %08x", + pipe->pipe_id, pipe->inout_port_config); + +#if !defined(HAS_NO_INPUT_FORMATTER) + sh_css_sp_group.config.input_formatter.isp_2ppc = (uint8_t)two_ppc; +#else + (void)two_ppc; +#endif + + sh_css_sp_stage.num = stage_num; + sh_css_sp_stage.stage_type = SH_CSS_SP_STAGE_TYPE; + sh_css_sp_stage.func = + (unsigned int)IA_CSS_PIPELINE_BIN_COPY; + + set_output_frame_buffer(out_frame, 0); + + /* sp_bin_copy_init on the SP does not deal with dynamica/static yet */ + /* For now always update the dynamic data from out frames. */ + sh_css_store_sp_per_frame_data(pipe_id, pipe_num, &sh_css_sp_fw); +} + +static void +sh_css_sp_start_raw_copy(struct ia_css_frame *out_frame, + unsigned pipe_num, + unsigned two_ppc, + unsigned max_input_width, + enum sh_css_pipe_config_override pipe_conf_override, + unsigned int if_config_index) +{ + enum ia_css_pipe_id pipe_id; + unsigned int thread_id; + uint8_t stage_num = 0; + struct sh_css_sp_pipeline *pipe; + + assert(out_frame != NULL); + + { + /** + * Clear sh_css_sp_stage for easy debugging. + * program_input_circuit must be saved as it is set outside + * this function. + */ + uint8_t program_input_circuit; + program_input_circuit = sh_css_sp_stage.program_input_circuit; + memset(&sh_css_sp_stage, 0, sizeof(sh_css_sp_stage)); + sh_css_sp_stage.program_input_circuit = program_input_circuit; + } + + pipe_id = IA_CSS_PIPE_ID_COPY; + ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id); + pipe = &sh_css_sp_group.pipe[thread_id]; + + pipe->copy.raw.height = out_frame->info.res.height; + pipe->copy.raw.width = out_frame->info.res.width; + pipe->copy.raw.padded_width = out_frame->info.padded_width; + pipe->copy.raw.raw_bit_depth = out_frame->info.raw_bit_depth; + pipe->copy.raw.max_input_width = max_input_width; + pipe->num_stages = 1; + pipe->pipe_id = pipe_id; + /* TODO: next indicates from which queues parameters need to be + sampled, needs checking/improvement */ + if (pipe_conf_override == SH_CSS_PIPE_CONFIG_OVRD_NO_OVRD) + pipe->pipe_config = + (SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS << thread_id); + else + pipe->pipe_config = pipe_conf_override; + + pipe->pipe_qos_config = QOS_INVALID; + + if (pipe->inout_port_config == 0) { + SH_CSS_PIPE_PORT_CONFIG_SET(pipe->inout_port_config, + (uint8_t)SH_CSS_PORT_INPUT, + (uint8_t)SH_CSS_HOST_TYPE, 1); + SH_CSS_PIPE_PORT_CONFIG_SET(pipe->inout_port_config, + (uint8_t)SH_CSS_PORT_OUTPUT, + (uint8_t)SH_CSS_HOST_TYPE, 1); + } + IA_CSS_LOG("pipe_id %d port_config %08x", + pipe->pipe_id, pipe->inout_port_config); + +#if !defined(HAS_NO_INPUT_FORMATTER) + sh_css_sp_group.config.input_formatter.isp_2ppc = (uint8_t)two_ppc; +#else + (void)two_ppc; +#endif + + sh_css_sp_stage.num = stage_num; + sh_css_sp_stage.xmem_bin_addr = 0x0; + sh_css_sp_stage.stage_type = SH_CSS_SP_STAGE_TYPE; + sh_css_sp_stage.func = (unsigned int)IA_CSS_PIPELINE_RAW_COPY; + sh_css_sp_stage.if_config_index = (uint8_t) if_config_index; + set_output_frame_buffer(out_frame, 0); + + ia_css_debug_pipe_graph_dump_sp_raw_copy(out_frame); +} + +static void +sh_css_sp_start_isys_copy(struct ia_css_frame *out_frame, + unsigned pipe_num, unsigned max_input_width, unsigned int if_config_index) +{ + enum ia_css_pipe_id pipe_id; + unsigned int thread_id; + uint8_t stage_num = 0; + struct sh_css_sp_pipeline *pipe; +#if defined SH_CSS_ENABLE_METADATA + enum sh_css_queue_id queue_id; +#endif + + assert(out_frame != NULL); + + { + /** + * Clear sh_css_sp_stage for easy debugging. + * program_input_circuit must be saved as it is set outside + * this function. + */ + uint8_t program_input_circuit; + program_input_circuit = sh_css_sp_stage.program_input_circuit; + memset(&sh_css_sp_stage, 0, sizeof(sh_css_sp_stage)); + sh_css_sp_stage.program_input_circuit = program_input_circuit; + } + + pipe_id = IA_CSS_PIPE_ID_COPY; + ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id); + pipe = &sh_css_sp_group.pipe[thread_id]; + + pipe->copy.raw.height = out_frame->info.res.height; + pipe->copy.raw.width = out_frame->info.res.width; + pipe->copy.raw.padded_width = out_frame->info.padded_width; + pipe->copy.raw.raw_bit_depth = out_frame->info.raw_bit_depth; + pipe->copy.raw.max_input_width = max_input_width; + pipe->num_stages = 1; + pipe->pipe_id = pipe_id; + pipe->pipe_config = 0x0; /* No parameters */ + pipe->pipe_qos_config = QOS_INVALID; + + initialize_stage_frames(&sh_css_sp_stage.frames); + sh_css_sp_stage.num = stage_num; + sh_css_sp_stage.xmem_bin_addr = 0x0; + sh_css_sp_stage.stage_type = SH_CSS_SP_STAGE_TYPE; + sh_css_sp_stage.func = (unsigned int)IA_CSS_PIPELINE_ISYS_COPY; + sh_css_sp_stage.if_config_index = (uint8_t) if_config_index; + + set_output_frame_buffer(out_frame, 0); + +#if defined SH_CSS_ENABLE_METADATA + if (pipe->metadata.height > 0) { + ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_METADATA, thread_id, &queue_id); + sh_css_copy_buffer_attr_to_spbuffer(&sh_css_sp_stage.frames.metadata_buf, queue_id, mmgr_EXCEPTION, IA_CSS_BUFFER_TYPE_METADATA); + } +#endif + + ia_css_debug_pipe_graph_dump_sp_raw_copy(out_frame); +} + +unsigned int +sh_css_sp_get_binary_copy_size(void) +{ + const struct ia_css_fw_info *fw = &sh_css_sp_fw; + unsigned int HIVE_ADDR_sp_output = fw->info.sp.output; + unsigned int offset = (unsigned int)offsetof(struct sh_css_sp_output, + bin_copy_bytes_copied) / sizeof(int); + (void)HIVE_ADDR_sp_output; /* To get rid of warning in CRUN */ + return load_sp_array_uint(sp_output, offset); +} + +unsigned int +sh_css_sp_get_sw_interrupt_value(unsigned int irq) +{ + const struct ia_css_fw_info *fw = &sh_css_sp_fw; + unsigned int HIVE_ADDR_sp_output = fw->info.sp.output; + unsigned int offset = (unsigned int)offsetof(struct sh_css_sp_output, sw_interrupt_value) + / sizeof(int); + (void)HIVE_ADDR_sp_output; /* To get rid of warning in CRUN */ + return load_sp_array_uint(sp_output, offset+irq); +} + +static void +sh_css_copy_buffer_attr_to_spbuffer(struct ia_css_buffer_sp *dest_buf, + const enum sh_css_queue_id queue_id, + const hrt_vaddress xmem_addr, + const enum ia_css_buffer_type buf_type) +{ + assert(buf_type < IA_CSS_NUM_BUFFER_TYPE); + if (queue_id > SH_CSS_INVALID_QUEUE_ID) { + /* + * value >=0 indicates that function init_frame_pointers() + * should use the dynamic data address + */ + assert(queue_id < SH_CSS_MAX_NUM_QUEUES); + + /* Klocwork assumes assert can be disabled; + Since we can get there with any type, and it does not + know that frame_in->dynamic_data_index can only be set + for one of the types in the assert) it has to assume we + can get here for any type. however this could lead to an + out of bounds reference when indexing buf_type about 10 + lines below. In order to satisfy KW an additional if + has been added. This one will always yield true. + */ + if ((queue_id < SH_CSS_MAX_NUM_QUEUES)) + { + dest_buf->buf_src.queue_id = queue_id; + } + } else { + assert(xmem_addr != mmgr_EXCEPTION); + dest_buf->buf_src.xmem_addr = xmem_addr; + } + dest_buf->buf_type = buf_type; +} + +static void +sh_css_copy_frame_to_spframe(struct ia_css_frame_sp *sp_frame_out, + const struct ia_css_frame *frame_in) +{ + assert(frame_in != NULL); + + ia_css_debug_dtrace(IA_CSS_DEBUG_TRACE_PRIVATE, + "sh_css_copy_frame_to_spframe():\n"); + + + sh_css_copy_buffer_attr_to_spbuffer(&sp_frame_out->buf_attr, + frame_in->dynamic_queue_id, + frame_in->data, + frame_in->buf_type); + + ia_css_frame_info_to_frame_sp_info(&sp_frame_out->info, &frame_in->info); + + switch (frame_in->info.format) { + case IA_CSS_FRAME_FORMAT_RAW_PACKED: + case IA_CSS_FRAME_FORMAT_RAW: + sp_frame_out->planes.raw.offset = frame_in->planes.raw.offset; + break; + case IA_CSS_FRAME_FORMAT_RGB565: + case IA_CSS_FRAME_FORMAT_RGBA888: + sp_frame_out->planes.rgb.offset = frame_in->planes.rgb.offset; + break; + case IA_CSS_FRAME_FORMAT_PLANAR_RGB888: + sp_frame_out->planes.planar_rgb.r.offset = + frame_in->planes.planar_rgb.r.offset; + sp_frame_out->planes.planar_rgb.g.offset = + frame_in->planes.planar_rgb.g.offset; + sp_frame_out->planes.planar_rgb.b.offset = + frame_in->planes.planar_rgb.b.offset; + break; + case IA_CSS_FRAME_FORMAT_YUYV: + case IA_CSS_FRAME_FORMAT_UYVY: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8: + case IA_CSS_FRAME_FORMAT_YUV_LINE: + sp_frame_out->planes.yuyv.offset = frame_in->planes.yuyv.offset; + break; + case IA_CSS_FRAME_FORMAT_NV11: + case IA_CSS_FRAME_FORMAT_NV12: + case IA_CSS_FRAME_FORMAT_NV12_16: + case IA_CSS_FRAME_FORMAT_NV12_TILEY: + case IA_CSS_FRAME_FORMAT_NV21: + case IA_CSS_FRAME_FORMAT_NV16: + case IA_CSS_FRAME_FORMAT_NV61: + sp_frame_out->planes.nv.y.offset = + frame_in->planes.nv.y.offset; + sp_frame_out->planes.nv.uv.offset = + frame_in->planes.nv.uv.offset; + break; + case IA_CSS_FRAME_FORMAT_YUV420: + case IA_CSS_FRAME_FORMAT_YUV422: + case IA_CSS_FRAME_FORMAT_YUV444: + case IA_CSS_FRAME_FORMAT_YUV420_16: + case IA_CSS_FRAME_FORMAT_YUV422_16: + case IA_CSS_FRAME_FORMAT_YV12: + case IA_CSS_FRAME_FORMAT_YV16: + sp_frame_out->planes.yuv.y.offset = + frame_in->planes.yuv.y.offset; + sp_frame_out->planes.yuv.u.offset = + frame_in->planes.yuv.u.offset; + sp_frame_out->planes.yuv.v.offset = + frame_in->planes.yuv.v.offset; + break; + case IA_CSS_FRAME_FORMAT_QPLANE6: + sp_frame_out->planes.plane6.r.offset = + frame_in->planes.plane6.r.offset; + sp_frame_out->planes.plane6.r_at_b.offset = + frame_in->planes.plane6.r_at_b.offset; + sp_frame_out->planes.plane6.gr.offset = + frame_in->planes.plane6.gr.offset; + sp_frame_out->planes.plane6.gb.offset = + frame_in->planes.plane6.gb.offset; + sp_frame_out->planes.plane6.b.offset = + frame_in->planes.plane6.b.offset; + sp_frame_out->planes.plane6.b_at_r.offset = + frame_in->planes.plane6.b_at_r.offset; + break; + case IA_CSS_FRAME_FORMAT_BINARY_8: + sp_frame_out->planes.binary.data.offset = + frame_in->planes.binary.data.offset; + break; + default: + /* This should not happen, but in case it does, + * nullify the planes + */ + memset(&sp_frame_out->planes, 0, sizeof(sp_frame_out->planes)); + break; + } + +} + +static enum ia_css_err +set_input_frame_buffer(const struct ia_css_frame *frame) +{ + if (frame == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + switch (frame->info.format) { + case IA_CSS_FRAME_FORMAT_QPLANE6: + case IA_CSS_FRAME_FORMAT_YUV420_16: + case IA_CSS_FRAME_FORMAT_RAW_PACKED: + case IA_CSS_FRAME_FORMAT_RAW: + case IA_CSS_FRAME_FORMAT_YUV420: + case IA_CSS_FRAME_FORMAT_YUYV: + case IA_CSS_FRAME_FORMAT_YUV_LINE: + case IA_CSS_FRAME_FORMAT_NV12: + case IA_CSS_FRAME_FORMAT_NV12_16: + case IA_CSS_FRAME_FORMAT_NV12_TILEY: + case IA_CSS_FRAME_FORMAT_NV21: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_10: + break; + default: + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + sh_css_copy_frame_to_spframe(&sh_css_sp_stage.frames.in, frame); + + return IA_CSS_SUCCESS; +} + +static enum ia_css_err +set_output_frame_buffer(const struct ia_css_frame *frame, + unsigned idx) +{ + if (frame == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + switch (frame->info.format) { + case IA_CSS_FRAME_FORMAT_YUV420: + case IA_CSS_FRAME_FORMAT_YUV422: + case IA_CSS_FRAME_FORMAT_YUV444: + case IA_CSS_FRAME_FORMAT_YV12: + case IA_CSS_FRAME_FORMAT_YV16: + case IA_CSS_FRAME_FORMAT_YUV420_16: + case IA_CSS_FRAME_FORMAT_YUV422_16: + case IA_CSS_FRAME_FORMAT_NV11: + case IA_CSS_FRAME_FORMAT_NV12: + case IA_CSS_FRAME_FORMAT_NV12_16: + case IA_CSS_FRAME_FORMAT_NV12_TILEY: + case IA_CSS_FRAME_FORMAT_NV16: + case IA_CSS_FRAME_FORMAT_NV21: + case IA_CSS_FRAME_FORMAT_NV61: + case IA_CSS_FRAME_FORMAT_YUYV: + case IA_CSS_FRAME_FORMAT_UYVY: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8: + case IA_CSS_FRAME_FORMAT_YUV_LINE: + case IA_CSS_FRAME_FORMAT_RGB565: + case IA_CSS_FRAME_FORMAT_RGBA888: + case IA_CSS_FRAME_FORMAT_PLANAR_RGB888: + case IA_CSS_FRAME_FORMAT_RAW: + case IA_CSS_FRAME_FORMAT_RAW_PACKED: + case IA_CSS_FRAME_FORMAT_QPLANE6: + case IA_CSS_FRAME_FORMAT_BINARY_8: + break; + default: + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + sh_css_copy_frame_to_spframe(&sh_css_sp_stage.frames.out[idx], frame); + return IA_CSS_SUCCESS; +} + +static enum ia_css_err +set_view_finder_buffer(const struct ia_css_frame *frame) +{ + if (frame == NULL) + return IA_CSS_ERR_INVALID_ARGUMENTS; + + switch (frame->info.format) { + /* the dual output pin */ + case IA_CSS_FRAME_FORMAT_NV12: + case IA_CSS_FRAME_FORMAT_NV12_16: + case IA_CSS_FRAME_FORMAT_NV21: + case IA_CSS_FRAME_FORMAT_YUYV: + case IA_CSS_FRAME_FORMAT_UYVY: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_YUV420_8: + case IA_CSS_FRAME_FORMAT_CSI_MIPI_LEGACY_YUV420_8: + case IA_CSS_FRAME_FORMAT_YUV420: + case IA_CSS_FRAME_FORMAT_YV12: + case IA_CSS_FRAME_FORMAT_NV12_TILEY: + + /* for vf_veceven */ + case IA_CSS_FRAME_FORMAT_YUV_LINE: + break; + default: + return IA_CSS_ERR_INVALID_ARGUMENTS; + } + + sh_css_copy_frame_to_spframe(&sh_css_sp_stage.frames.out_vf, frame); + return IA_CSS_SUCCESS; +} + +#if !defined(HAS_NO_INPUT_FORMATTER) +void sh_css_sp_set_if_configs( + const input_formatter_cfg_t *config_a, + const input_formatter_cfg_t *config_b, + const uint8_t if_config_index + ) +{ + assert(if_config_index < SH_CSS_MAX_IF_CONFIGS); + assert(config_a != NULL); + + sh_css_sp_group.config.input_formatter.set[if_config_index].config_a = *config_a; + sh_css_sp_group.config.input_formatter.a_changed = true; + + if (config_b != NULL) { + sh_css_sp_group.config.input_formatter.set[if_config_index].config_b = *config_b; + sh_css_sp_group.config.input_formatter.b_changed = true; + } + + return; +} +#endif + +#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2) +void +sh_css_sp_program_input_circuit(int fmt_type, + int ch_id, + enum ia_css_input_mode input_mode) +{ + sh_css_sp_group.config.input_circuit.no_side_band = false; + sh_css_sp_group.config.input_circuit.fmt_type = fmt_type; + sh_css_sp_group.config.input_circuit.ch_id = ch_id; + sh_css_sp_group.config.input_circuit.input_mode = input_mode; +/* + * The SP group is only loaded at SP boot time and is read once + * change flags as "input_circuit_cfg_changed" must be reset on the SP + */ + sh_css_sp_group.config.input_circuit_cfg_changed = true; + sh_css_sp_stage.program_input_circuit = true; +} +#endif + +#if !defined(HAS_NO_INPUT_SYSTEM) && defined(USE_INPUT_SYSTEM_VERSION_2) +void +sh_css_sp_configure_sync_gen(int width, int height, + int hblank_cycles, + int vblank_cycles) +{ + sh_css_sp_group.config.sync_gen.width = width; + sh_css_sp_group.config.sync_gen.height = height; + sh_css_sp_group.config.sync_gen.hblank_cycles = hblank_cycles; + sh_css_sp_group.config.sync_gen.vblank_cycles = vblank_cycles; +} + +void +sh_css_sp_configure_tpg(int x_mask, + int y_mask, + int x_delta, + int y_delta, + int xy_mask) +{ + sh_css_sp_group.config.tpg.x_mask = x_mask; + sh_css_sp_group.config.tpg.y_mask = y_mask; + sh_css_sp_group.config.tpg.x_delta = x_delta; + sh_css_sp_group.config.tpg.y_delta = y_delta; + sh_css_sp_group.config.tpg.xy_mask = xy_mask; +} + +void +sh_css_sp_configure_prbs(int seed) +{ + sh_css_sp_group.config.prbs.seed = seed; +} +#endif + +void +sh_css_sp_configure_enable_raw_pool_locking(bool lock_all) +{ + sh_css_sp_group.config.enable_raw_pool_locking = true; + sh_css_sp_group.config.lock_all = lock_all; +} + +void +sh_css_sp_enable_isys_event_queue(bool enable) +{ +#if !defined(HAS_NO_INPUT_SYSTEM) + sh_css_sp_group.config.enable_isys_event_queue = enable; +#else + (void)enable; +#endif +} + +void +sh_css_sp_set_disable_continuous_viewfinder(bool flag) +{ + sh_css_sp_group.config.disable_cont_vf = flag; +} + +static enum ia_css_err +sh_css_sp_write_frame_pointers(const struct sh_css_binary_args *args) +{ + enum ia_css_err err = IA_CSS_SUCCESS; + int i; + + assert(args != NULL); + + if (args->in_frame) + err = set_input_frame_buffer(args->in_frame); + if (err == IA_CSS_SUCCESS && args->out_vf_frame) + err = set_view_finder_buffer(args->out_vf_frame); + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + if (err == IA_CSS_SUCCESS && args->out_frame[i]) + err = set_output_frame_buffer(args->out_frame[i], i); + } + + /* we don't pass this error back to the upper layer, so we add a assert here + because we actually hit the error here but it still works by accident... */ + if (err != IA_CSS_SUCCESS) assert(false); + return err; +} + +static void +sh_css_sp_init_group(bool two_ppc, + enum ia_css_stream_format input_format, + bool no_isp_sync, + uint8_t if_config_index) +{ +#if !defined(HAS_NO_INPUT_FORMATTER) + sh_css_sp_group.config.input_formatter.isp_2ppc = two_ppc; +#else + (void)two_ppc; +#endif + + sh_css_sp_group.config.no_isp_sync = (uint8_t)no_isp_sync; + /* decide whether the frame is processed online or offline */ + if (if_config_index == SH_CSS_IF_CONFIG_NOT_NEEDED) return; +#if !defined(HAS_NO_INPUT_FORMATTER) + assert(if_config_index < SH_CSS_MAX_IF_CONFIGS); + sh_css_sp_group.config.input_formatter.set[if_config_index].stream_format = input_format; +#else + (void)input_format; +#endif +} + +void +sh_css_stage_write_binary_info(struct ia_css_binary_info *info) +{ + assert(info != NULL); + sh_css_isp_stage.binary_info = *info; +} + +static enum ia_css_err +copy_isp_mem_if_to_ddr(struct ia_css_binary *binary) +{ + enum ia_css_err err; + + err = ia_css_isp_param_copy_isp_mem_if_to_ddr( + &binary->css_params, + &binary->mem_params, + IA_CSS_PARAM_CLASS_CONFIG); + if (err != IA_CSS_SUCCESS) + return err; + err = ia_css_isp_param_copy_isp_mem_if_to_ddr( + &binary->css_params, + &binary->mem_params, + IA_CSS_PARAM_CLASS_STATE); + if (err != IA_CSS_SUCCESS) + return err; + return IA_CSS_SUCCESS; +} + +static bool +is_sp_stage(struct ia_css_pipeline_stage *stage) +{ + assert(stage != NULL); + return stage->sp_func != IA_CSS_PIPELINE_NO_FUNC; +} + +static enum ia_css_err +configure_isp_from_args( + const struct sh_css_sp_pipeline *pipeline, + const struct ia_css_binary *binary, + const struct sh_css_binary_args *args, + bool two_ppc, + bool deinterleaved) +{ + enum ia_css_err err = IA_CSS_SUCCESS; +#ifdef ISP2401 + struct ia_css_pipe *pipe = find_pipe_by_num(pipeline->pipe_num); + const struct ia_css_resolution *res; + +#endif + ia_css_fpn_configure(binary, &binary->in_frame_info); + ia_css_crop_configure(binary, &args->delay_frames[0]->info); + ia_css_qplane_configure(pipeline, binary, &binary->in_frame_info); + ia_css_output0_configure(binary, &args->out_frame[0]->info); + ia_css_output1_configure(binary, &args->out_vf_frame->info); + ia_css_copy_output_configure(binary, args->copy_output); + ia_css_output0_configure(binary, &args->out_frame[0]->info); +#ifdef ISP2401 + ia_css_sc_configure(binary, pipeline->shading.internal_frame_origin_x_bqs_on_sctbl, + pipeline->shading.internal_frame_origin_y_bqs_on_sctbl); +#endif + ia_css_iterator_configure(binary, &args->in_frame->info); + ia_css_dvs_configure(binary, &args->out_frame[0]->info); + ia_css_output_configure(binary, &args->out_frame[0]->info); + ia_css_raw_configure(pipeline, binary, &args->in_frame->info, &binary->in_frame_info, two_ppc, deinterleaved); + ia_css_ref_configure(binary, (const struct ia_css_frame **)args->delay_frames, pipeline->dvs_frame_delay); + ia_css_tnr_configure(binary, (const struct ia_css_frame **)args->tnr_frames); + ia_css_bayer_io_config(binary, args); +#ifdef HAS_TNR3 + /* Remove support for TNR2 once TNR3 fully integrated */ + ia_css_tnr3_configure(binary, (const struct ia_css_frame **)args->tnr_frames); +#endif + return err; +} + +static void +initialize_isp_states(const struct ia_css_binary *binary) +{ + unsigned int i; + + if (!binary->info->mem_offsets.offsets.state) + return; + for (i = 0; i < IA_CSS_NUM_STATE_IDS; i++) { + ia_css_kernel_init_state[i](binary); + } +} + +static void +initialize_frame_buffer_attribute(struct ia_css_buffer_sp *buf_attr) +{ + buf_attr->buf_src.queue_id = SH_CSS_INVALID_QUEUE_ID; + buf_attr->buf_type = IA_CSS_BUFFER_TYPE_INVALID; +} + +static void +initialize_stage_frames(struct ia_css_frames_sp *frames) +{ + unsigned int i; + + initialize_frame_buffer_attribute(&frames->in.buf_attr); + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + initialize_frame_buffer_attribute(&frames->out[i].buf_attr); + } + initialize_frame_buffer_attribute(&frames->out_vf.buf_attr); + initialize_frame_buffer_attribute(&frames->s3a_buf); + initialize_frame_buffer_attribute(&frames->dvs_buf); +#if defined SH_CSS_ENABLE_METADATA + initialize_frame_buffer_attribute(&frames->metadata_buf); +#endif +} + +static enum ia_css_err +sh_css_sp_init_stage(struct ia_css_binary *binary, + const char *binary_name, + const struct ia_css_blob_info *blob_info, + const struct sh_css_binary_args *args, + unsigned int pipe_num, + unsigned stage, + bool xnr, + const struct ia_css_isp_param_css_segments *isp_mem_if, + unsigned int if_config_index, + bool two_ppc) +{ + const struct ia_css_binary_xinfo *xinfo; + const struct ia_css_binary_info *info; + enum ia_css_err err = IA_CSS_SUCCESS; + int i; + struct ia_css_pipe *pipe = NULL; + unsigned int thread_id; + enum sh_css_queue_id queue_id; + bool continuous = sh_css_continuous_is_enabled((uint8_t)pipe_num); + + assert(binary != NULL); + assert(blob_info != NULL); + assert(args != NULL); + assert(isp_mem_if != NULL); + + xinfo = binary->info; + info = &xinfo->sp; + { + /** + * Clear sh_css_sp_stage for easy debugging. + * program_input_circuit must be saved as it is set outside + * this function. + */ + uint8_t program_input_circuit; + program_input_circuit = sh_css_sp_stage.program_input_circuit; + memset(&sh_css_sp_stage, 0, sizeof(sh_css_sp_stage)); + sh_css_sp_stage.program_input_circuit = (uint8_t)program_input_circuit; + } + + ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id); + + if (info == NULL) { + sh_css_sp_group.pipe[thread_id].sp_stage_addr[stage] = mmgr_NULL; + return IA_CSS_SUCCESS; + } + +#if defined(USE_INPUT_SYSTEM_VERSION_2401) + (void)continuous; + sh_css_sp_stage.deinterleaved = 0; +#else + sh_css_sp_stage.deinterleaved = ((stage == 0) && continuous); +#endif + + initialize_stage_frames(&sh_css_sp_stage.frames); + /* + * TODO: Make the Host dynamically determine + * the stage type. + */ + sh_css_sp_stage.stage_type = SH_CSS_ISP_STAGE_TYPE; + sh_css_sp_stage.num = (uint8_t)stage; + sh_css_sp_stage.isp_online = (uint8_t)binary->online; + sh_css_sp_stage.isp_copy_vf = (uint8_t)args->copy_vf; + sh_css_sp_stage.isp_copy_output = (uint8_t)args->copy_output; + sh_css_sp_stage.enable.vf_output = (args->out_vf_frame != NULL); + + /* Copy the frame infos first, to be overwritten by the frames, + if these are present. + */ + sh_css_sp_stage.frames.effective_in_res.width = binary->effective_in_frame_res.width; + sh_css_sp_stage.frames.effective_in_res.height = binary->effective_in_frame_res.height; + + ia_css_frame_info_to_frame_sp_info(&sh_css_sp_stage.frames.in.info, + &binary->in_frame_info); + for (i = 0; i < IA_CSS_BINARY_MAX_OUTPUT_PORTS; i++) { + ia_css_frame_info_to_frame_sp_info(&sh_css_sp_stage.frames.out[i].info, + &binary->out_frame_info[i]); + } + ia_css_frame_info_to_frame_sp_info(&sh_css_sp_stage.frames.internal_frame_info, + &binary->internal_frame_info); + sh_css_sp_stage.dvs_envelope.width = binary->dvs_envelope.width; + sh_css_sp_stage.dvs_envelope.height = binary->dvs_envelope.height; + sh_css_sp_stage.isp_pipe_version = (uint8_t)info->pipeline.isp_pipe_version; + sh_css_sp_stage.isp_deci_log_factor = (uint8_t)binary->deci_factor_log2; + sh_css_sp_stage.isp_vf_downscale_bits = (uint8_t)binary->vf_downscale_log2; + + sh_css_sp_stage.if_config_index = (uint8_t) if_config_index; + + sh_css_sp_stage.sp_enable_xnr = (uint8_t)xnr; + sh_css_sp_stage.xmem_bin_addr = xinfo->xmem_addr; + sh_css_sp_stage.xmem_map_addr = sh_css_params_ddr_address_map(); + sh_css_isp_stage.blob_info = *blob_info; + sh_css_stage_write_binary_info((struct ia_css_binary_info *)info); + + /* Make sure binary name is smaller than allowed string size */ + assert(strlen(binary_name) < SH_CSS_MAX_BINARY_NAME-1); + strncpy(sh_css_isp_stage.binary_name, binary_name, SH_CSS_MAX_BINARY_NAME-1); + sh_css_isp_stage.binary_name[SH_CSS_MAX_BINARY_NAME - 1] = 0; + sh_css_isp_stage.mem_initializers = *isp_mem_if; + + /** + * Even when a stage does not need uds and does not params, + * ia_css_uds_sp_scale_params() seems to be called (needs + * further investigation). This function can not deal with + * dx, dy = {0, 0} + */ + + err = sh_css_sp_write_frame_pointers(args); + /* TODO: move it to a better place */ + if (binary->info->sp.enable.s3a) { + ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_3A_STATISTICS, thread_id, &queue_id); + sh_css_copy_buffer_attr_to_spbuffer(&sh_css_sp_stage.frames.s3a_buf, queue_id, mmgr_EXCEPTION, IA_CSS_BUFFER_TYPE_3A_STATISTICS); + } + if (binary->info->sp.enable.dis) { + ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_DIS_STATISTICS, thread_id, &queue_id); + sh_css_copy_buffer_attr_to_spbuffer(&sh_css_sp_stage.frames.dvs_buf, queue_id, mmgr_EXCEPTION, IA_CSS_BUFFER_TYPE_DIS_STATISTICS); + } +#if defined SH_CSS_ENABLE_METADATA + ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_METADATA, thread_id, &queue_id); + sh_css_copy_buffer_attr_to_spbuffer(&sh_css_sp_stage.frames.metadata_buf, queue_id, mmgr_EXCEPTION, IA_CSS_BUFFER_TYPE_METADATA); +#endif + if (err != IA_CSS_SUCCESS) + return err; + +#ifdef USE_INPUT_SYSTEM_VERSION_2401 +#ifndef ISP2401 + if (args->in_frame) { + pipe = find_pipe_by_num(sh_css_sp_group.pipe[thread_id].pipe_num); + if (pipe == NULL) + return IA_CSS_ERR_INTERNAL_ERROR; + ia_css_get_crop_offsets(pipe, &args->in_frame->info); + } else if (&binary->in_frame_info) { + pipe = find_pipe_by_num(sh_css_sp_group.pipe[thread_id].pipe_num); + if (pipe == NULL) + return IA_CSS_ERR_INTERNAL_ERROR; + ia_css_get_crop_offsets(pipe, &binary->in_frame_info); +#else + if (stage == 0) { + if (args->in_frame) { + pipe = find_pipe_by_num(sh_css_sp_group.pipe[thread_id].pipe_num); + if (pipe == NULL) + return IA_CSS_ERR_INTERNAL_ERROR; + ia_css_get_crop_offsets(pipe, &args->in_frame->info); + } else if (&binary->in_frame_info) { + pipe = find_pipe_by_num(sh_css_sp_group.pipe[thread_id].pipe_num); + if (pipe == NULL) + return IA_CSS_ERR_INTERNAL_ERROR; + ia_css_get_crop_offsets(pipe, &binary->in_frame_info); + } +#endif + } +#else + (void)pipe; /*avoid build warning*/ +#endif + + err = configure_isp_from_args(&sh_css_sp_group.pipe[thread_id], + binary, args, two_ppc, sh_css_sp_stage.deinterleaved); + if (err != IA_CSS_SUCCESS) + return err; + + initialize_isp_states(binary); + + /* we do this only for preview pipe because in fill_binary_info function + * we assign vf_out res to out res, but for ISP internal processing, we need + * the original out res. for video pipe, it has two output pins --- out and + * vf_out, so it can keep these two resolutions already. */ + if (binary->info->sp.pipeline.mode == IA_CSS_BINARY_MODE_PREVIEW && + (binary->vf_downscale_log2 > 0)) { + /* TODO: Remove this after preview output decimation is fixed + * by configuring out&vf info fiels properly */ + sh_css_sp_stage.frames.out[0].info.padded_width + <<= binary->vf_downscale_log2; + sh_css_sp_stage.frames.out[0].info.res.width + <<= binary->vf_downscale_log2; + sh_css_sp_stage.frames.out[0].info.res.height + <<= binary->vf_downscale_log2; + } + err = copy_isp_mem_if_to_ddr(binary); + if (err != IA_CSS_SUCCESS) + return err; + + return IA_CSS_SUCCESS; +} + +static enum ia_css_err +sp_init_stage(struct ia_css_pipeline_stage *stage, + unsigned int pipe_num, + bool xnr, + unsigned int if_config_index, + bool two_ppc) +{ + struct ia_css_binary *binary; + const struct ia_css_fw_info *firmware; + const struct sh_css_binary_args *args; + unsigned stage_num; +/* + * Initialiser required because of the "else" path below. + * Is this a valid path ? + */ + const char *binary_name = ""; + const struct ia_css_binary_xinfo *info = NULL; + /* note: the var below is made static as it is quite large; + if it is not static it ends up on the stack which could + cause issues for drivers + */ + static struct ia_css_binary tmp_binary; + const struct ia_css_blob_info *blob_info = NULL; + struct ia_css_isp_param_css_segments isp_mem_if; + /* LA: should be ia_css_data, should not contain host pointer. + However, CSS/DDR pointer is not available yet. + Hack is to store it in params->ddr_ptrs and then copy it late in the SP just before vmem init. + TODO: Call this after CSS/DDR allocation and store that pointer. + Best is to allocate it at stage creation time together with host pointer. + Remove vmem from params. + */ + struct ia_css_isp_param_css_segments *mem_if = &isp_mem_if; + + enum ia_css_err err = IA_CSS_SUCCESS; + + assert(stage != NULL); + + binary = stage->binary; + firmware = stage->firmware; + args = &stage->args; + stage_num = stage->stage_num; + + + if (binary) { + info = binary->info; + binary_name = (const char *)(info->blob->name); + blob_info = &info->blob->header.blob; + ia_css_init_memory_interface(mem_if, &binary->mem_params, &binary->css_params); + } else if (firmware) { + const struct ia_css_frame_info *out_infos[IA_CSS_BINARY_MAX_OUTPUT_PORTS] = {NULL}; + if (args->out_frame[0]) + out_infos[0] = &args->out_frame[0]->info; + info = &firmware->info.isp; + ia_css_binary_fill_info(info, false, false, + IA_CSS_STREAM_FORMAT_RAW_10, + args->in_frame ? &args->in_frame->info : NULL, + NULL, + out_infos, + args->out_vf_frame ? &args->out_vf_frame->info + : NULL, + &tmp_binary, + NULL, + -1, true); + binary = &tmp_binary; + binary->info = info; + binary_name = IA_CSS_EXT_ISP_PROG_NAME(firmware); + blob_info = &firmware->blob; + mem_if = (struct ia_css_isp_param_css_segments *)&firmware->mem_initializers; + } else { + /* SP stage */ + assert(stage->sp_func != IA_CSS_PIPELINE_NO_FUNC); + /* binary and blob_info are now NULL. + These will be passed to sh_css_sp_init_stage + and dereferenced there, so passing a NULL + pointer is no good. return an error */ + return IA_CSS_ERR_INTERNAL_ERROR; + } + + err = sh_css_sp_init_stage(binary, + (const char *)binary_name, + blob_info, + args, + pipe_num, + stage_num, + xnr, + mem_if, + if_config_index, + two_ppc); + return err; +} + +static void +sp_init_sp_stage(struct ia_css_pipeline_stage *stage, + unsigned pipe_num, + bool two_ppc, + enum sh_css_pipe_config_override copy_ovrd, + unsigned int if_config_index) +{ + const struct sh_css_binary_args *args = &stage->args; + + assert(stage != NULL); + switch (stage->sp_func) { + case IA_CSS_PIPELINE_RAW_COPY: + sh_css_sp_start_raw_copy(args->out_frame[0], + pipe_num, two_ppc, + stage->max_input_width, + copy_ovrd, if_config_index); + break; + case IA_CSS_PIPELINE_BIN_COPY: + assert(false); /* TBI */ + case IA_CSS_PIPELINE_ISYS_COPY: + sh_css_sp_start_isys_copy(args->out_frame[0], + pipe_num, stage->max_input_width, if_config_index); + break; + case IA_CSS_PIPELINE_NO_FUNC: + assert(false); + } +} + +void +sh_css_sp_init_pipeline(struct ia_css_pipeline *me, + enum ia_css_pipe_id id, + uint8_t pipe_num, + bool xnr, + bool two_ppc, + bool continuous, + bool offline, + unsigned int required_bds_factor, + enum sh_css_pipe_config_override copy_ovrd, + enum ia_css_input_mode input_mode, + const struct ia_css_metadata_config *md_config, + const struct ia_css_metadata_info *md_info, +#if !defined(HAS_NO_INPUT_SYSTEM) + const mipi_port_ID_t port_id +#endif +#ifdef ISP2401 + , + const struct ia_css_coordinate *internal_frame_origin_bqs_on_sctbl, /* Origin of internal frame + positioned on shading table at shading correction in ISP. */ + const struct ia_css_isp_parameters *params +#endif + ) +{ + /* Get first stage */ + struct ia_css_pipeline_stage *stage = NULL; + struct ia_css_binary *first_binary = NULL; + struct ia_css_pipe *pipe = NULL; + unsigned num; + + enum ia_css_pipe_id pipe_id = id; + unsigned int thread_id; + uint8_t if_config_index, tmp_if_config_index; + + assert(me != NULL); + +#if !defined(HAS_NO_INPUT_SYSTEM) + assert(me->stages != NULL); + + first_binary = me->stages->binary; + + if (input_mode == IA_CSS_INPUT_MODE_SENSOR || + input_mode == IA_CSS_INPUT_MODE_BUFFERED_SENSOR) { + assert(port_id < N_MIPI_PORT_ID); + if (port_id >= N_MIPI_PORT_ID) /* should not happen but KW does not know */ + return; /* we should be able to return an error */ + if_config_index = (uint8_t) (port_id - MIPI_PORT0_ID); + } else if (input_mode == IA_CSS_INPUT_MODE_MEMORY) { + if_config_index = SH_CSS_IF_CONFIG_NOT_NEEDED; + } else { + if_config_index = 0x0; + } +#else + (void)input_mode; + if_config_index = SH_CSS_IF_CONFIG_NOT_NEEDED; +#endif + + ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id); + memset(&sh_css_sp_group.pipe[thread_id], 0, sizeof(struct sh_css_sp_pipeline)); + + /* Count stages */ + for (stage = me->stages, num = 0; stage; stage = stage->next, num++) { + stage->stage_num = num; + ia_css_debug_pipe_graph_dump_stage(stage, id); + } + me->num_stages = num; + + if (first_binary != NULL) { + /* Init pipeline data */ + sh_css_sp_init_group(two_ppc, first_binary->input_format, + offline, if_config_index); + } /* if (first_binary != NULL) */ + +#if defined(USE_INPUT_SYSTEM_VERSION_2401) || defined(USE_INPUT_SYSTEM_VERSION_2) + /* Signal the host immediately after start for SP_ISYS_COPY only */ + if ((me->num_stages == 1) && me->stages && + (me->stages->sp_func == IA_CSS_PIPELINE_ISYS_COPY)) + sh_css_sp_group.config.no_isp_sync = true; +#endif + + /* Init stage data */ + sh_css_init_host2sp_frame_data(); + + sh_css_sp_group.pipe[thread_id].num_stages = 0; + sh_css_sp_group.pipe[thread_id].pipe_id = pipe_id; + sh_css_sp_group.pipe[thread_id].thread_id = thread_id; + sh_css_sp_group.pipe[thread_id].pipe_num = pipe_num; + sh_css_sp_group.pipe[thread_id].num_execs = me->num_execs; + sh_css_sp_group.pipe[thread_id].pipe_qos_config = me->pipe_qos_config; + sh_css_sp_group.pipe[thread_id].required_bds_factor = required_bds_factor; +#if !defined(HAS_NO_INPUT_SYSTEM) + sh_css_sp_group.pipe[thread_id].input_system_mode + = (uint32_t)input_mode; + sh_css_sp_group.pipe[thread_id].port_id = port_id; +#endif + sh_css_sp_group.pipe[thread_id].dvs_frame_delay = (uint32_t)me->dvs_frame_delay; + + /* TODO: next indicates from which queues parameters need to be + sampled, needs checking/improvement */ + if (ia_css_pipeline_uses_params(me)) { + sh_css_sp_group.pipe[thread_id].pipe_config = + SH_CSS_PIPE_CONFIG_SAMPLE_PARAMS << thread_id; + } + + /* For continuous use-cases, SP copy is responsible for sampling the + * parameters */ + if (continuous) + sh_css_sp_group.pipe[thread_id].pipe_config = 0; + + sh_css_sp_group.pipe[thread_id].inout_port_config = me->inout_port_config; + + pipe = find_pipe_by_num(pipe_num); + assert(pipe != NULL); + if (pipe == NULL) { + return; + } + sh_css_sp_group.pipe[thread_id].scaler_pp_lut = sh_css_pipe_get_pp_gdc_lut(pipe); + +#if defined(SH_CSS_ENABLE_METADATA) + if (md_info != NULL && md_info->size > 0) { + sh_css_sp_group.pipe[thread_id].metadata.width = md_info->resolution.width; + sh_css_sp_group.pipe[thread_id].metadata.height = md_info->resolution.height; + sh_css_sp_group.pipe[thread_id].metadata.stride = md_info->stride; + sh_css_sp_group.pipe[thread_id].metadata.size = md_info->size; + ia_css_isys_convert_stream_format_to_mipi_format( + md_config->data_type, MIPI_PREDICTOR_NONE, + &sh_css_sp_group.pipe[thread_id].metadata.format); + } +#else + (void)md_config; + (void)md_info; +#endif + +#if defined(SH_CSS_ENABLE_PER_FRAME_PARAMS) + sh_css_sp_group.pipe[thread_id].output_frame_queue_id = (uint32_t)SH_CSS_INVALID_QUEUE_ID; + if (IA_CSS_PIPE_ID_COPY != pipe_id) { + ia_css_query_internal_queue_id(IA_CSS_BUFFER_TYPE_OUTPUT_FRAME, thread_id, (enum sh_css_queue_id *)(&sh_css_sp_group.pipe[thread_id].output_frame_queue_id)); + } +#endif + +#ifdef ISP2401 + /* For the shading correction type 1 (the legacy shading table conversion in css is not used), + * the parameters are passed to the isp for the shading table centering. + */ + if (internal_frame_origin_bqs_on_sctbl != NULL && + params != NULL && params->shading_settings.enable_shading_table_conversion == 0) { + sh_css_sp_group.pipe[thread_id].shading.internal_frame_origin_x_bqs_on_sctbl + = (uint32_t)internal_frame_origin_bqs_on_sctbl->x; + sh_css_sp_group.pipe[thread_id].shading.internal_frame_origin_y_bqs_on_sctbl + = (uint32_t)internal_frame_origin_bqs_on_sctbl->y; + } else { + sh_css_sp_group.pipe[thread_id].shading.internal_frame_origin_x_bqs_on_sctbl = 0; + sh_css_sp_group.pipe[thread_id].shading.internal_frame_origin_y_bqs_on_sctbl = 0; + } + +#endif + IA_CSS_LOG("pipe_id %d port_config %08x", + pipe_id, sh_css_sp_group.pipe[thread_id].inout_port_config); + + for (stage = me->stages, num = 0; stage; stage = stage->next, num++) { + sh_css_sp_group.pipe[thread_id].num_stages++; + if (is_sp_stage(stage)) { + sp_init_sp_stage(stage, pipe_num, two_ppc, + copy_ovrd, if_config_index); + } else { + if ((stage->stage_num != 0) || SH_CSS_PIPE_PORT_CONFIG_IS_CONTINUOUS(me->inout_port_config)) + tmp_if_config_index = SH_CSS_IF_CONFIG_NOT_NEEDED; + else + tmp_if_config_index = if_config_index; + sp_init_stage(stage, pipe_num, + xnr, tmp_if_config_index, two_ppc); + } + + store_sp_stage_data(pipe_id, pipe_num, num); + } + sh_css_sp_group.pipe[thread_id].pipe_config |= (uint32_t) + (me->acquire_isp_each_stage << IA_CSS_ACQUIRE_ISP_POS); + store_sp_group_data(); + +} + +void +sh_css_sp_uninit_pipeline(unsigned int pipe_num) +{ + unsigned int thread_id; + ia_css_pipeline_get_sp_thread_id(pipe_num, &thread_id); + /*memset(&sh_css_sp_group.pipe[thread_id], 0, sizeof(struct sh_css_sp_pipeline));*/ + sh_css_sp_group.pipe[thread_id].num_stages = 0; +} + +#if defined(HAS_SEC_SP) +void +sh_css_write_host2sp1_command(enum host2sp_commands host2sp_command) +{ + unsigned int HIVE_ADDR_host_sp1_com = sh_css_sp1_fw.info.sp1.host_sp_com; + unsigned int offset = (unsigned int)offsetof(struct host_sp_communication, host2sp_command) + / sizeof(int); + (void)HIVE_ADDR_host_sp1_com; /* Suppres warnings in CRUN */ + + /* Previous command must be handled by SP1 (by design) */ + if (host2sp_command == host2sp_cmd_terminate) + assert(load_sp1_array_uint(host_sp1_com, offset) == host2sp_cmd_ready); + + store_sp1_array_uint(host_sp1_com, offset, host2sp_command); +} +#endif /* HAS_SEC_SP */ + +bool sh_css_write_host2sp_command(enum host2sp_commands host2sp_command) +{ + unsigned int HIVE_ADDR_host_sp_com = sh_css_sp_fw.info.sp.host_sp_com; + unsigned int offset = (unsigned int)offsetof(struct host_sp_communication, host2sp_command) + / sizeof(int); + enum host2sp_commands last_cmd = host2sp_cmd_error; + (void)HIVE_ADDR_host_sp_com; /* Suppres warnings in CRUN */ + + /* Previous command must be handled by SP (by design) */ + last_cmd = load_sp_array_uint(host_sp_com, offset); + if (last_cmd != host2sp_cmd_ready) + IA_CSS_ERROR("last host command not handled by SP(%d)", last_cmd); + + store_sp_array_uint(host_sp_com, offset, host2sp_command); + + return (last_cmd == host2sp_cmd_ready); +} + +enum host2sp_commands +sh_css_read_host2sp_command(void) +{ + unsigned int HIVE_ADDR_host_sp_com = sh_css_sp_fw.info.sp.host_sp_com; + unsigned int offset = (unsigned int)offsetof(struct host_sp_communication, host2sp_command) + / sizeof(int); + (void)HIVE_ADDR_host_sp_com; /* Suppres warnings in CRUN */ + return (enum host2sp_commands)load_sp_array_uint(host_sp_com, offset); +} + + +/* + * Frame data is no longer part of the sp_stage structure but part of a + * seperate structure. The aim is to make the sp_data struct static + * (it defines a pipeline) and that the dynamic (per frame) data is stored + * separetly. + * + * This function must be called first every where were you start constructing + * a new pipeline by defining one or more stages with use of variable + * sh_css_sp_stage. Even the special cases like accelerator and copy_frame + * These have a pipeline of just 1 stage. + */ +void +sh_css_init_host2sp_frame_data(void) +{ + /* Clean table */ + unsigned int HIVE_ADDR_host_sp_com = sh_css_sp_fw.info.sp.host_sp_com; + + (void)HIVE_ADDR_host_sp_com; /* Suppres warnings in CRUN */ + /* + * rvanimme: don't clean it to save static frame info line ref_in + * ref_out, and tnr_frames. Once this static data is in a + * seperate data struct, this may be enable (but still, there is + * no need for it) + */ +} + + +/** + * @brief Update the offline frame information in host_sp_communication. + * Refer to "sh_css_sp.h" for more details. + */ +void +sh_css_update_host2sp_offline_frame( + unsigned frame_num, + struct ia_css_frame *frame, + struct ia_css_metadata *metadata) +{ + unsigned int HIVE_ADDR_host_sp_com; + unsigned int offset; + + (void)HIVE_ADDR_host_sp_com; /* Suppres warnings in CRUN */ + + assert(frame_num < NUM_CONTINUOUS_FRAMES); + + /* Write new frame data into SP DMEM */ + HIVE_ADDR_host_sp_com = sh_css_sp_fw.info.sp.host_sp_com; + offset = (unsigned int)offsetof(struct host_sp_communication, host2sp_offline_frames) + / sizeof(int); + offset += frame_num; + store_sp_array_uint(host_sp_com, offset, frame ? frame->data : 0); + + /* Write metadata buffer into SP DMEM */ + offset = (unsigned int)offsetof(struct host_sp_communication, host2sp_offline_metadata) + / sizeof(int); + offset += frame_num; + store_sp_array_uint(host_sp_com, offset, metadata ? metadata->address : 0); +} + +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) +/** + * @brief Update the mipi frame information in host_sp_communication. + * Refer to "sh_css_sp.h" for more details. + */ +void +sh_css_update_host2sp_mipi_frame( + unsigned frame_num, + struct ia_css_frame *frame) +{ + unsigned int HIVE_ADDR_host_sp_com; + unsigned int offset; + + (void)HIVE_ADDR_host_sp_com; /* Suppres warnings in CRUN */ + + /* MIPI buffers are dedicated to port, so now there are more of them. */ + assert(frame_num < (N_CSI_PORTS * NUM_MIPI_FRAMES_PER_STREAM)); + + /* Write new frame data into SP DMEM */ + HIVE_ADDR_host_sp_com = sh_css_sp_fw.info.sp.host_sp_com; + offset = (unsigned int)offsetof(struct host_sp_communication, host2sp_mipi_frames) + / sizeof(int); + offset += frame_num; + + store_sp_array_uint(host_sp_com, offset, + frame ? frame->data : 0); +} + +/** + * @brief Update the mipi metadata information in host_sp_communication. + * Refer to "sh_css_sp.h" for more details. + */ +void +sh_css_update_host2sp_mipi_metadata( + unsigned frame_num, + struct ia_css_metadata *metadata) +{ + unsigned int HIVE_ADDR_host_sp_com; + unsigned int o; + + (void)HIVE_ADDR_host_sp_com; /* Suppres warnings in CRUN */ + + /* MIPI buffers are dedicated to port, so now there are more of them. */ + assert(frame_num < (N_CSI_PORTS * NUM_MIPI_FRAMES_PER_STREAM)); + + /* Write new frame data into SP DMEM */ + HIVE_ADDR_host_sp_com = sh_css_sp_fw.info.sp.host_sp_com; + o = offsetof(struct host_sp_communication, host2sp_mipi_metadata) + / sizeof(int); + o += frame_num; + store_sp_array_uint(host_sp_com, o, + metadata ? metadata->address : 0); +} + +void +sh_css_update_host2sp_num_mipi_frames(unsigned num_frames) +{ + unsigned int HIVE_ADDR_host_sp_com; + unsigned int offset; + + (void)HIVE_ADDR_host_sp_com; /* Suppres warnings in CRUN */ + + /* Write new frame data into SP DMEM */ + HIVE_ADDR_host_sp_com = sh_css_sp_fw.info.sp.host_sp_com; + offset = (unsigned int)offsetof(struct host_sp_communication, host2sp_num_mipi_frames) + / sizeof(int); + + store_sp_array_uint(host_sp_com, offset, num_frames); +} +#endif + +void +sh_css_update_host2sp_cont_num_raw_frames(unsigned num_frames, bool set_avail) +{ + const struct ia_css_fw_info *fw; + unsigned int HIVE_ADDR_host_sp_com; + unsigned int extra_num_frames, avail_num_frames; + unsigned int offset, offset_extra; + + (void)HIVE_ADDR_host_sp_com; /* Suppres warnings in CRUN */ + + /* Write new frame data into SP DMEM */ + fw = &sh_css_sp_fw; + HIVE_ADDR_host_sp_com = fw->info.sp.host_sp_com; + if (set_avail) { + offset = (unsigned int)offsetof(struct host_sp_communication, host2sp_cont_avail_num_raw_frames) + / sizeof(int); + avail_num_frames = load_sp_array_uint(host_sp_com, offset); + extra_num_frames = num_frames - avail_num_frames; + offset_extra = (unsigned int)offsetof(struct host_sp_communication, host2sp_cont_extra_num_raw_frames) + / sizeof(int); + store_sp_array_uint(host_sp_com, offset_extra, extra_num_frames); + } else + offset = (unsigned int)offsetof(struct host_sp_communication, host2sp_cont_target_num_raw_frames) + / sizeof(int); + + store_sp_array_uint(host_sp_com, offset, num_frames); +} + +void +sh_css_event_init_irq_mask(void) +{ + int i; + unsigned int HIVE_ADDR_host_sp_com = sh_css_sp_fw.info.sp.host_sp_com; + unsigned int offset; + struct sh_css_event_irq_mask event_irq_mask_init; + + event_irq_mask_init.or_mask = IA_CSS_EVENT_TYPE_ALL; + event_irq_mask_init.and_mask = IA_CSS_EVENT_TYPE_NONE; + (void)HIVE_ADDR_host_sp_com; /* Suppress warnings in CRUN */ + + assert(sizeof(event_irq_mask_init) % HRT_BUS_BYTES == 0); + for (i = 0; i < IA_CSS_PIPE_ID_NUM; i++) { + offset = (unsigned int)offsetof(struct host_sp_communication, + host2sp_event_irq_mask[i]); + assert(offset % HRT_BUS_BYTES == 0); + sp_dmem_store(SP0_ID, + (unsigned int)sp_address_of(host_sp_com) + offset, + &event_irq_mask_init, sizeof(event_irq_mask_init)); + } + +} + +enum ia_css_err +ia_css_pipe_set_irq_mask(struct ia_css_pipe *pipe, + unsigned int or_mask, + unsigned int and_mask) +{ + unsigned int HIVE_ADDR_host_sp_com = sh_css_sp_fw.info.sp.host_sp_com; + unsigned int offset; + struct sh_css_event_irq_mask event_irq_mask; + unsigned int pipe_num; + + assert(pipe != NULL); + + assert(IA_CSS_PIPE_ID_NUM == NR_OF_PIPELINES); + /* Linux kernel does not have UINT16_MAX + * Therefore decided to comment out these 2 asserts for Linux + * Alternatives that were not chosen: + * - add a conditional #define for UINT16_MAX + * - compare with (uint16_t)~0 or 0xffff + * - different assert for Linux and Windows + */ +#ifndef __KERNEL__ + assert(or_mask <= UINT16_MAX); + assert(and_mask <= UINT16_MAX); +#endif + + (void)HIVE_ADDR_host_sp_com; /* Suppres warnings in CRUN */ + + IA_CSS_LOG("or_mask=%x, and_mask=%x", or_mask, and_mask); + event_irq_mask.or_mask = (uint16_t)or_mask; + event_irq_mask.and_mask = (uint16_t)and_mask; + + pipe_num = ia_css_pipe_get_pipe_num(pipe); + if (pipe_num >= IA_CSS_PIPE_ID_NUM) + return IA_CSS_ERR_INTERNAL_ERROR; + offset = (unsigned int)offsetof(struct host_sp_communication, + host2sp_event_irq_mask[pipe_num]); + assert(offset % HRT_BUS_BYTES == 0); + sp_dmem_store(SP0_ID, + (unsigned int)sp_address_of(host_sp_com) + offset, + &event_irq_mask, sizeof(event_irq_mask)); + + return IA_CSS_SUCCESS; +} + +enum ia_css_err +ia_css_event_get_irq_mask(const struct ia_css_pipe *pipe, + unsigned int *or_mask, + unsigned int *and_mask) +{ + unsigned int HIVE_ADDR_host_sp_com = sh_css_sp_fw.info.sp.host_sp_com; + unsigned int offset; + struct sh_css_event_irq_mask event_irq_mask; + unsigned int pipe_num; + + (void)HIVE_ADDR_host_sp_com; /* Suppres warnings in CRUN */ + + IA_CSS_ENTER_LEAVE(""); + + assert(pipe != NULL); + assert(IA_CSS_PIPE_ID_NUM == NR_OF_PIPELINES); + + pipe_num = ia_css_pipe_get_pipe_num(pipe); + if (pipe_num >= IA_CSS_PIPE_ID_NUM) + return IA_CSS_ERR_INTERNAL_ERROR; + offset = (unsigned int)offsetof(struct host_sp_communication, + host2sp_event_irq_mask[pipe_num]); + assert(offset % HRT_BUS_BYTES == 0); + sp_dmem_load(SP0_ID, + (unsigned int)sp_address_of(host_sp_com) + offset, + &event_irq_mask, sizeof(event_irq_mask)); + + if (or_mask) + *or_mask = event_irq_mask.or_mask; + + if (and_mask) + *and_mask = event_irq_mask.and_mask; + + return IA_CSS_SUCCESS; +} + +void +sh_css_sp_set_sp_running(bool flag) +{ + sp_running = flag; +} + +#if defined(HAS_SEC_SP) +void +sh_css_sp1_set_sp1_running(bool flag) +{ + sp1_running = flag; +} +#endif /* HAS_SEC_SP */ + +bool +sh_css_sp_is_running(void) +{ + return sp_running; +} + +#if defined(HAS_SEC_SP) +void +sh_css_sp1_start(void) +{ + const struct ia_css_fw_info *fw; + unsigned int HIVE_ADDR_sp_sw_state; + fw = &sh_css_sp1_fw; + HIVE_ADDR_sp_sw_state = fw->info.sp1.sw_state; + + if (sp1_running) + return; + + (void)HIVE_ADDR_sp_sw_state; /* Suppres warnings in CRUN */ + + /* no longer here, sp started immediately */ + /*ia_css_debug_pipe_graph_dump_epilogue();*/ + + /*store_sp_group_data(); + store_sp_per_frame_data(fw);*/ + sp_dmem_store_uint32(SP1_ID, + (unsigned int)sp1_address_of(sp_sw_state), + (uint32_t)(IA_CSS_SP_SW_TERMINATED)); + + /* Note 1: The sp_start_isp function contains a wait till + * the input network is configured by the SP. + * Note 2: Not all SP binaries supports host2sp_commands. + * In case a binary does support it, the host2sp_command + * will have status cmd_ready after return of the function + * sh_css_hrt_sp_start_isp. There is no race-condition here + * because only after the process_frame command has been + * received, the SP starts configuring the input network. + */ + + /* we need to set sp_running before we call ia_css_mmu_invalidate_cache + * as ia_css_mmu_invalidate_cache checks on sp_running to + * avoid that it accesses dmem while the SP is not powered + */ + sp1_running = true; + /* ia_css_mmu_invalidate_cache(); */ + /* Invalidate all MMU caches */ + /* mmu_invalidate_cache_all(); */ + + ia_css_spctrl_start(SP1_ID); + +} +#endif /* HAS_SEC_SP */ + +void +sh_css_sp_start_isp(void) +{ + const struct ia_css_fw_info *fw; + unsigned int HIVE_ADDR_sp_sw_state; + + fw = &sh_css_sp_fw; + HIVE_ADDR_sp_sw_state = fw->info.sp.sw_state; + + + if (sp_running) + return; + + (void)HIVE_ADDR_sp_sw_state; /* Suppres warnings in CRUN */ + + /* no longer here, sp started immediately */ + /*ia_css_debug_pipe_graph_dump_epilogue();*/ + + store_sp_group_data(); + store_sp_per_frame_data(fw); + + sp_dmem_store_uint32(SP0_ID, + (unsigned int)sp_address_of(sp_sw_state), + (uint32_t)(IA_CSS_SP_SW_TERMINATED)); + + + /* Note 1: The sp_start_isp function contains a wait till + * the input network is configured by the SP. + * Note 2: Not all SP binaries supports host2sp_commands. + * In case a binary does support it, the host2sp_command + * will have status cmd_ready after return of the function + * sh_css_hrt_sp_start_isp. There is no race-condition here + * because only after the process_frame command has been + * received, the SP starts configuring the input network. + */ + + /* we need to set sp_running before we call ia_css_mmu_invalidate_cache + * as ia_css_mmu_invalidate_cache checks on sp_running to + * avoid that it accesses dmem while the SP is not powered + */ + sp_running = true; + ia_css_mmu_invalidate_cache(); + /* Invalidate all MMU caches */ + mmu_invalidate_cache_all(); + + ia_css_spctrl_start(SP0_ID); + +} + +bool +ia_css_isp_has_started(void) +{ + const struct ia_css_fw_info *fw = &sh_css_sp_fw; + unsigned int HIVE_ADDR_ia_css_ispctrl_sp_isp_started = fw->info.sp.isp_started; + (void)HIVE_ADDR_ia_css_ispctrl_sp_isp_started; /* Suppres warnings in CRUN */ + + return (bool)load_sp_uint(ia_css_ispctrl_sp_isp_started); +} + + +/** + * @brief Initialize the DMA software-mask in the debug mode. + * Refer to "sh_css_sp.h" for more details. + */ +bool +sh_css_sp_init_dma_sw_reg(int dma_id) +{ + int i; + + /* enable all the DMA channels */ + for (i = 0; i < N_DMA_CHANNEL_ID; i++) { + /* enable the writing request */ + sh_css_sp_set_dma_sw_reg(dma_id, + i, + 0, + true); + /* enable the reading request */ + sh_css_sp_set_dma_sw_reg(dma_id, + i, + 1, + true); + } + + return true; +} + +/** + * @brief Set the DMA software-mask in the debug mode. + * Refer to "sh_css_sp.h" for more details. + */ +bool +sh_css_sp_set_dma_sw_reg(int dma_id, + int channel_id, + int request_type, + bool enable) +{ + uint32_t sw_reg; + uint32_t bit_val; + uint32_t bit_offset; + uint32_t bit_mask; + + (void)dma_id; + + assert(channel_id >= 0 && channel_id < N_DMA_CHANNEL_ID); + assert(request_type >= 0); + + /* get the software-mask */ + sw_reg = + sh_css_sp_group.debug.dma_sw_reg; + + /* get the offest of the target bit */ + bit_offset = (8 * request_type) + channel_id; + + /* clear the value of the target bit */ + bit_mask = ~(1 << bit_offset); + sw_reg &= bit_mask; + + /* set the value of the bit for the DMA channel */ + bit_val = enable ? 1 : 0; + bit_val <<= bit_offset; + sw_reg |= bit_val; + + /* update the software status of DMA channels */ + sh_css_sp_group.debug.dma_sw_reg = sw_reg; + + return true; +} + +void +sh_css_sp_reset_global_vars(void) +{ + memset(&sh_css_sp_group, 0, sizeof(struct sh_css_sp_group)); + memset(&sh_css_sp_stage, 0, sizeof(struct sh_css_sp_stage)); + memset(&sh_css_isp_stage, 0, sizeof(struct sh_css_isp_stage)); + memset(&sh_css_sp_output, 0, sizeof(struct sh_css_sp_output)); + memset(&per_frame_data, 0, sizeof(struct sh_css_sp_per_frame_data)); +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_sp.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_sp.h new file mode 100644 index 0000000000000000000000000000000000000000..5b730118afc6cb16ff2d756d9f89bdf5b8e1170e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_sp.h @@ -0,0 +1,262 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_SP_H_ +#define _SH_CSS_SP_H_ + +#include +#include +#if !defined(HAS_NO_INPUT_FORMATTER) +#include "input_formatter.h" +#endif + +#include "ia_css_binary.h" +#include "ia_css_types.h" +#include "ia_css_pipeline.h" + +/* Function to initialize the data and bss section descr of the binary */ +void +sh_css_sp_store_init_dmem(const struct ia_css_fw_info *fw); + +void +store_sp_stage_data(enum ia_css_pipe_id id, unsigned int pipe_num, unsigned stage); + +void +sh_css_stage_write_binary_info(struct ia_css_binary_info *info); + +void +store_sp_group_data(void); + +/* Start binary (jpeg) copy on the SP */ +void +sh_css_sp_start_binary_copy(unsigned int pipe_num, struct ia_css_frame *out_frame, + unsigned two_ppc); + +unsigned int +sh_css_sp_get_binary_copy_size(void); + +/* Return the value of a SW interrupt */ +unsigned int +sh_css_sp_get_sw_interrupt_value(unsigned int irq); + +void +sh_css_sp_init_pipeline(struct ia_css_pipeline *me, + enum ia_css_pipe_id id, + uint8_t pipe_num, + bool xnr, + bool two_ppc, + bool continuous, + bool offline, + unsigned int required_bds_factor, + enum sh_css_pipe_config_override copy_ovrd, + enum ia_css_input_mode input_mode, + const struct ia_css_metadata_config *md_config, + const struct ia_css_metadata_info *md_info, +#if !defined(HAS_NO_INPUT_SYSTEM) + const mipi_port_ID_t port_id +#endif +#ifdef ISP2401 + , + const struct ia_css_coordinate *internal_frame_origin_bqs_on_sctbl, /* Origin of internal frame + positioned on shading table at shading correction in ISP. */ + const struct ia_css_isp_parameters *params +#endif + ); + +void +sh_css_sp_uninit_pipeline(unsigned int pipe_num); + +bool sh_css_write_host2sp_command(enum host2sp_commands host2sp_command); + +#if defined(HAS_SEC_SP) +void +sh_css_write_host2sp1_command(enum host2sp_commands host2sp_command); +#endif /* HAS_SEC_SP */ + +enum host2sp_commands +sh_css_read_host2sp_command(void); + +void +sh_css_init_host2sp_frame_data(void); + +/** + * @brief Update the offline frame information in host_sp_communication. + * + * @param[in] frame_num The offline frame number. + * @param[in] frame The pointer to the offline frame. + */ +void +sh_css_update_host2sp_offline_frame( + unsigned frame_num, + struct ia_css_frame *frame, + struct ia_css_metadata *metadata); + +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) +/** + * @brief Update the mipi frame information in host_sp_communication. + * + * @param[in] frame_num The mipi frame number. + * @param[in] frame The pointer to the mipi frame. + */ +void +sh_css_update_host2sp_mipi_frame( + unsigned frame_num, + struct ia_css_frame *frame); + +/** + * @brief Update the mipi metadata information in host_sp_communication. + * + * @param[in] frame_num The mipi frame number. + * @param[in] metadata The pointer to the mipi metadata. + */ +void +sh_css_update_host2sp_mipi_metadata( + unsigned frame_num, + struct ia_css_metadata *metadata); + +/** + * @brief Update the nr of mipi frames to use in host_sp_communication. + * + * @param[in] num_frames The number of mipi frames to use. + */ +void +sh_css_update_host2sp_num_mipi_frames(unsigned num_frames); +#endif + +/** + * @brief Update the nr of offline frames to use in host_sp_communication. + * + * @param[in] num_frames The number of raw frames to use. + */ +void +sh_css_update_host2sp_cont_num_raw_frames(unsigned num_frames, bool set_avail); + +void +sh_css_event_init_irq_mask(void); + +void +sh_css_sp_start_isp(void); +#if defined(HAS_SEC_SP) +void +sh_css_sp1_start(void); +#endif /* HAS_SEC_SP */ + +void +sh_css_sp_set_sp_running(bool flag); + +#if defined(HAS_SEC_SP) +void +sh_css_sp1_set_sp1_running(bool flag); +#endif /* HAS_SEC_SP */ + +bool +sh_css_sp_is_running(void); + +#if SP_DEBUG != SP_DEBUG_NONE + +void +sh_css_sp_get_debug_state(struct sh_css_sp_debug_state *state); + +#endif + +#if !defined(HAS_NO_INPUT_FORMATTER) +void +sh_css_sp_set_if_configs( + const input_formatter_cfg_t *config_a, + const input_formatter_cfg_t *config_b, + const uint8_t if_config_index); +#endif + +void +sh_css_sp_program_input_circuit(int fmt_type, + int ch_id, + enum ia_css_input_mode input_mode); + +void +sh_css_sp_configure_sync_gen(int width, + int height, + int hblank_cycles, + int vblank_cycles); + +void +sh_css_sp_configure_tpg(int x_mask, + int y_mask, + int x_delta, + int y_delta, + int xy_mask); + +void +sh_css_sp_configure_prbs(int seed); + +void +sh_css_sp_configure_enable_raw_pool_locking(bool lock_all); + +void +sh_css_sp_enable_isys_event_queue(bool enable); + +void +sh_css_sp_set_disable_continuous_viewfinder(bool flag); + +void +sh_css_sp_reset_global_vars(void); + +/** + * @brief Initialize the DMA software-mask in the debug mode. + * This API should be ONLY called in the debugging mode. + * And it should be always called before the first call of + * "sh_css_set_dma_sw_reg(...)". + * + * @param[in] dma_id The ID of the target DMA. + * + * @return + * - true, if it is successful. + * - false, otherwise. + */ +bool +sh_css_sp_init_dma_sw_reg(int dma_id); + +/** + * @brief Set the DMA software-mask in the debug mode. + * This API should be ONLYL called in the debugging mode. Must + * call "sh_css_set_dma_sw_reg(...)" before this + * API is called for the first time. + * + * @param[in] dma_id The ID of the target DMA. + * @param[in] channel_id The ID of the target DMA channel. + * @param[in] request_type The type of the DMA request. + * For example: + * - "0" indicates the writing request. + * - "1" indicates the reading request. + * + * @param[in] enable If it is "true", the target DMA + * channel is enabled in the software. + * Otherwise, the target DMA channel + * is disabled in the software. + * + * @return + * - true, if it is successful. + * - false, otherwise. + */ +bool +sh_css_sp_set_dma_sw_reg(int dma_id, + int channel_id, + int request_type, + bool enable); + + +extern struct sh_css_sp_group sh_css_sp_group; +extern struct sh_css_sp_stage sh_css_sp_stage; +extern struct sh_css_isp_stage sh_css_isp_stage; + +#endif /* _SH_CSS_SP_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_stream.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_stream.c new file mode 100644 index 0000000000000000000000000000000000000000..60bddbb3d4c6cdd5b891f495673744b61a103faa --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_stream.c @@ -0,0 +1,16 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +/* This file will contain the code to implement the functions declared in ia_css_stream.h + and associated helper functions */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_stream_format.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_stream_format.c new file mode 100644 index 0000000000000000000000000000000000000000..52d0a647159784900da27fcc61bc5c779de6d3d4 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_stream_format.c @@ -0,0 +1,76 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "sh_css_stream_format.h" +#include + +unsigned int sh_css_stream_format_2_bits_per_subpixel( + enum ia_css_stream_format format) +{ + unsigned int rval; + + switch (format) { + case IA_CSS_STREAM_FORMAT_RGB_444: + rval = 4; + break; + case IA_CSS_STREAM_FORMAT_RGB_555: + rval = 5; + break; + case IA_CSS_STREAM_FORMAT_RGB_565: + case IA_CSS_STREAM_FORMAT_RGB_666: + case IA_CSS_STREAM_FORMAT_RAW_6: + rval = 6; + break; + case IA_CSS_STREAM_FORMAT_RAW_7: + rval = 7; + break; + case IA_CSS_STREAM_FORMAT_YUV420_8_LEGACY: + case IA_CSS_STREAM_FORMAT_YUV420_8: + case IA_CSS_STREAM_FORMAT_YUV422_8: + case IA_CSS_STREAM_FORMAT_RGB_888: + case IA_CSS_STREAM_FORMAT_RAW_8: + case IA_CSS_STREAM_FORMAT_BINARY_8: + case IA_CSS_STREAM_FORMAT_USER_DEF1: + case IA_CSS_STREAM_FORMAT_USER_DEF2: + case IA_CSS_STREAM_FORMAT_USER_DEF3: + case IA_CSS_STREAM_FORMAT_USER_DEF4: + case IA_CSS_STREAM_FORMAT_USER_DEF5: + case IA_CSS_STREAM_FORMAT_USER_DEF6: + case IA_CSS_STREAM_FORMAT_USER_DEF7: + case IA_CSS_STREAM_FORMAT_USER_DEF8: + rval = 8; + break; + case IA_CSS_STREAM_FORMAT_YUV420_10: + case IA_CSS_STREAM_FORMAT_YUV422_10: + case IA_CSS_STREAM_FORMAT_RAW_10: + rval = 10; + break; + case IA_CSS_STREAM_FORMAT_RAW_12: + rval = 12; + break; + case IA_CSS_STREAM_FORMAT_RAW_14: + rval = 14; + break; + case IA_CSS_STREAM_FORMAT_RAW_16: + case IA_CSS_STREAM_FORMAT_YUV420_16: + case IA_CSS_STREAM_FORMAT_YUV422_16: + rval = 16; + break; + default: + rval = 0; + break; + } + + return rval; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_stream_format.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_stream_format.h new file mode 100644 index 0000000000000000000000000000000000000000..aab2b6207051ec04c1fbd257e3c43a001ea61703 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_stream_format.h @@ -0,0 +1,23 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SH_CSS_STREAM_FORMAT_H +#define __SH_CSS_STREAM_FORMAT_H + +#include + +unsigned int sh_css_stream_format_2_bits_per_subpixel( + enum ia_css_stream_format format); + +#endif /* __SH_CSS_STREAM_FORMAT_H */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_struct.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_struct.h new file mode 100644 index 0000000000000000000000000000000000000000..e49e478ab3547e9b565315374a3954a4da2c60f3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_struct.h @@ -0,0 +1,80 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef __SH_CSS_STRUCT_H +#define __SH_CSS_STRUCT_H + +/* This header files contains the definition of the + sh_css struct and friends; locigally the file would + probably be called sh_css.h after the pattern + .h but sh_css.h is the predecesssor of ia_css.h + so this could cause confusion; hence the _struct + in the filename +*/ + +#include +#include +#include "ia_css_pipeline.h" +#include "ia_css_pipe_public.h" +#include "ia_css_frame_public.h" +#include "ia_css_queue.h" +#include "ia_css_irq.h" + +struct sh_css { + struct ia_css_pipe *active_pipes[IA_CSS_PIPELINE_NUM_MAX]; + /* All of the pipes created at any point of time. At this moment there can + * be no more than MAX_SP_THREADS of them because pipe_num is reused as SP + * thread_id to which a pipe's pipeline is associated. At a later point, if + * we support more pipe objects, we should add test code to test that + * possibility. Also, active_pipes[] should be able to hold only + * SH_CSS_MAX_SP_THREADS objects. Anything else is misleading. */ + struct ia_css_pipe *all_pipes[IA_CSS_PIPELINE_NUM_MAX]; + void * (*malloc)(size_t bytes, bool zero_mem); + void (*free)(void *ptr); +#ifdef ISP2401 + void * (*malloc_ex)(size_t bytes, bool zero_mem, const char *caller_func, int caller_line); + void (*free_ex)(void *ptr, const char *caller_func, int caller_line); +#endif + void (*flush)(struct ia_css_acc_fw *fw); + bool check_system_idle; +#ifndef ISP2401 + bool stop_copy_preview; +#endif + unsigned int num_cont_raw_frames; +#if defined(USE_INPUT_SYSTEM_VERSION_2) || defined(USE_INPUT_SYSTEM_VERSION_2401) + unsigned int num_mipi_frames[N_CSI_PORTS]; + struct ia_css_frame *mipi_frames[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM]; + struct ia_css_metadata *mipi_metadata[N_CSI_PORTS][NUM_MIPI_FRAMES_PER_STREAM]; + unsigned int mipi_sizes_for_check[N_CSI_PORTS][IA_CSS_MIPI_SIZE_CHECK_MAX_NOF_ENTRIES_PER_PORT]; + unsigned int mipi_frame_size[N_CSI_PORTS]; +#endif + hrt_vaddress sp_bin_addr; + hrt_data page_table_base_index; + unsigned int size_mem_words; /** \deprecated{Use ia_css_mipi_buffer_config instead.}*/ + enum ia_css_irq_type irq_type; + unsigned int pipe_counter; + + unsigned int type; /* 2400 or 2401 for now */ +}; + +#define IPU_2400 1 +#define IPU_2401 2 + +#define IS_2400() (my_css.type == IPU_2400) +#define IS_2401() (my_css.type == IPU_2401) + +extern struct sh_css my_css; + +#endif /* __SH_CSS_STRUCT_H */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_uds.h b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_uds.h new file mode 100644 index 0000000000000000000000000000000000000000..5ded3a1437bf7bb53e85e8d09484cb7889bed115 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_uds.h @@ -0,0 +1,37 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#ifndef _SH_CSS_UDS_H_ +#define _SH_CSS_UDS_H_ + +#include + +#define SIZE_OF_SH_CSS_UDS_INFO_IN_BITS (4 * 16) +#define SIZE_OF_SH_CSS_CROP_POS_IN_BITS (2 * 16) + +/* Uds types, used in pipeline_global.h and sh_css_internal.h */ + +struct sh_css_uds_info { + uint16_t curr_dx; + uint16_t curr_dy; + uint16_t xc; + uint16_t yc; +}; + +struct sh_css_crop_pos { + uint16_t x; + uint16_t y; +}; + +#endif /* _SH_CSS_UDS_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_version.c b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_version.c new file mode 100644 index 0000000000000000000000000000000000000000..6e0c5e7f8620d04237cd6e19d4dcb7dd9e5ca210 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/css2400/sh_css_version.c @@ -0,0 +1,30 @@ +/* + * Support for Intel Camera Imaging ISP subsystem. + * Copyright (c) 2015, Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + */ + +#include "ia_css_version.h" +#include "ia_css_version_data.h" +#include "ia_css_err.h" +#include "sh_css_firmware.h" + +enum ia_css_err +ia_css_get_version(char *version, int max_size) +{ + if (max_size <= (int)strlen(CSS_VERSION_STRING) + (int)strlen(sh_css_get_fw_version()) + 5) + return IA_CSS_ERR_INVALID_ARGUMENTS; + strcpy(version, CSS_VERSION_STRING); + strcat(version, "FW:"); + strcat(version, sh_css_get_fw_version()); + strcat(version, "; "); + return IA_CSS_SUCCESS; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/hmm/hmm.c b/drivers/staging/media/atomisp/pci/atomisp2/hmm/hmm.c new file mode 100644 index 0000000000000000000000000000000000000000..358d340e74348fda0d4e3eb93b7eef4fbf7a539f --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/hmm/hmm.c @@ -0,0 +1,769 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +/* + * This file contains entry functions for memory management of ISP driver + */ +#include +#include +#include +#include /* for kmap */ +#include /* for page_to_phys */ +#include + +#include "hmm/hmm.h" +#include "hmm/hmm_pool.h" +#include "hmm/hmm_bo.h" + +#include "atomisp_internal.h" +#include "asm/cacheflush.h" +#include "mmu/isp_mmu.h" +#include "mmu/sh_mmu_mrfld.h" + +#ifdef USE_SSSE3 +#include +#endif + +struct hmm_bo_device bo_device; +struct hmm_pool dynamic_pool; +struct hmm_pool reserved_pool; +static ia_css_ptr dummy_ptr; +struct _hmm_mem_stat hmm_mem_stat; + +const char *hmm_bo_type_strings[HMM_BO_LAST] = { + "p", /* private */ + "s", /* shared */ + "u", /* user */ +#ifdef CONFIG_ION + "i", /* ion */ +#endif +}; + +static ssize_t bo_show(struct device *dev, struct device_attribute *attr, + char *buf, struct list_head *bo_list, bool active) +{ + ssize_t ret = 0; + struct hmm_buffer_object *bo; + unsigned long flags; + int i; + long total[HMM_BO_LAST] = { 0 }; + long count[HMM_BO_LAST] = { 0 }; + int index1 = 0; + int index2 = 0; + + ret = scnprintf(buf, PAGE_SIZE, "type pgnr\n"); + if (ret <= 0) + return 0; + + index1 += ret; + + spin_lock_irqsave(&bo_device.list_lock, flags); + list_for_each_entry(bo, bo_list, list) { + if ((active && (bo->status & HMM_BO_ALLOCED)) || + (!active && !(bo->status & HMM_BO_ALLOCED))) { + ret = scnprintf(buf + index1, PAGE_SIZE - index1, + "%s %d\n", + hmm_bo_type_strings[bo->type], bo->pgnr); + + total[bo->type] += bo->pgnr; + count[bo->type]++; + if (ret > 0) + index1 += ret; + } + } + spin_unlock_irqrestore(&bo_device.list_lock, flags); + + for (i = 0; i < HMM_BO_LAST; i++) { + if (count[i]) { + ret = scnprintf(buf + index1 + index2, + PAGE_SIZE - index1 - index2, + "%ld %s buffer objects: %ld KB\n", + count[i], hmm_bo_type_strings[i], total[i] * 4); + if (ret > 0) + index2 += ret; + } + } + + /* Add trailing zero, not included by scnprintf */ + return index1 + index2 + 1; +} + +static ssize_t active_bo_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return bo_show(dev, attr, buf, &bo_device.entire_bo_list, true); +} + +static ssize_t free_bo_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + return bo_show(dev, attr, buf, &bo_device.entire_bo_list, false); +} + +static ssize_t reserved_pool_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + ssize_t ret = 0; + + struct hmm_reserved_pool_info *pinfo = reserved_pool.pool_info; + unsigned long flags; + + if (!pinfo || !pinfo->initialized) + return 0; + + spin_lock_irqsave(&pinfo->list_lock, flags); + ret = scnprintf(buf, PAGE_SIZE, "%d out of %d pages available\n", + pinfo->index, pinfo->pgnr); + spin_unlock_irqrestore(&pinfo->list_lock, flags); + + if (ret > 0) + ret++; /* Add trailing zero, not included by scnprintf */ + + return ret; +}; + +static ssize_t dynamic_pool_show(struct device *dev, + struct device_attribute *attr, + char *buf) +{ + ssize_t ret = 0; + + struct hmm_dynamic_pool_info *pinfo = dynamic_pool.pool_info; + unsigned long flags; + + if (!pinfo || !pinfo->initialized) + return 0; + + spin_lock_irqsave(&pinfo->list_lock, flags); + ret = scnprintf(buf, PAGE_SIZE, "%d (max %d) pages available\n", + pinfo->pgnr, pinfo->pool_size); + spin_unlock_irqrestore(&pinfo->list_lock, flags); + + if (ret > 0) + ret++; /* Add trailing zero, not included by scnprintf */ + + return ret; +}; + +static DEVICE_ATTR(active_bo, S_IRUGO, active_bo_show, NULL); +static DEVICE_ATTR(free_bo, S_IRUGO, free_bo_show, NULL); +static DEVICE_ATTR(reserved_pool, S_IRUGO, reserved_pool_show, NULL); +static DEVICE_ATTR(dynamic_pool, S_IRUGO, dynamic_pool_show, NULL); + +static struct attribute *sysfs_attrs_ctrl[] = { + &dev_attr_active_bo.attr, + &dev_attr_free_bo.attr, + &dev_attr_reserved_pool.attr, + &dev_attr_dynamic_pool.attr, + NULL +}; + +static struct attribute_group atomisp_attribute_group[] = { + {.attrs = sysfs_attrs_ctrl }, +}; + +int hmm_init(void) +{ + int ret; + + ret = hmm_bo_device_init(&bo_device, &sh_mmu_mrfld, + ISP_VM_START, ISP_VM_SIZE); + if (ret) + dev_err(atomisp_dev, "hmm_bo_device_init failed.\n"); + + /* + * As hmm use NULL to indicate invalid ISP virtual address, + * and ISP_VM_START is defined to 0 too, so we allocate + * one piece of dummy memory, which should return value 0, + * at the beginning, to avoid hmm_alloc return 0 in the + * further allocation. + */ + dummy_ptr = hmm_alloc(1, HMM_BO_PRIVATE, 0, 0, HMM_UNCACHED); + + if (!ret) { + ret = sysfs_create_group(&atomisp_dev->kobj, + atomisp_attribute_group); + if (ret) + dev_err(atomisp_dev, + "%s Failed to create sysfs\n", __func__); + } + + return ret; +} + +void hmm_cleanup(void) +{ + sysfs_remove_group(&atomisp_dev->kobj, atomisp_attribute_group); + + /* + * free dummy memory first + */ + hmm_free(dummy_ptr); + dummy_ptr = 0; + + hmm_bo_device_exit(&bo_device); +} + +ia_css_ptr hmm_alloc(size_t bytes, enum hmm_bo_type type, + int from_highmem, void *userptr, bool cached) +{ + unsigned int pgnr; + struct hmm_buffer_object *bo; + int ret; + + /*Get page number from size*/ + pgnr = size_to_pgnr_ceil(bytes); + + /*Buffer object structure init*/ + bo = hmm_bo_alloc(&bo_device, pgnr); + if (!bo) { + dev_err(atomisp_dev, "hmm_bo_create failed.\n"); + goto create_bo_err; + } + + /*Allocate pages for memory*/ + ret = hmm_bo_alloc_pages(bo, type, from_highmem, userptr, cached); + if (ret) { + dev_err(atomisp_dev, + "hmm_bo_alloc_pages failed.\n"); + goto alloc_page_err; + } + + /*Combind the virtual address and pages togather*/ + ret = hmm_bo_bind(bo); + if (ret) { + dev_err(atomisp_dev, "hmm_bo_bind failed.\n"); + goto bind_err; + } + + hmm_mem_stat.tol_cnt += pgnr; + + return bo->start; + +bind_err: + hmm_bo_free_pages(bo); +alloc_page_err: + hmm_bo_unref(bo); +create_bo_err: + return 0; +} + +void hmm_free(ia_css_ptr virt) +{ + struct hmm_buffer_object *bo; + + bo = hmm_bo_device_search_start(&bo_device, (unsigned int)virt); + + if (!bo) { + dev_err(atomisp_dev, + "can not find buffer object start with " + "address 0x%x\n", (unsigned int)virt); + return; + } + + hmm_mem_stat.tol_cnt -= bo->pgnr; + + hmm_bo_unbind(bo); + + hmm_bo_free_pages(bo); + + hmm_bo_unref(bo); +} + +static inline int hmm_check_bo(struct hmm_buffer_object *bo, unsigned int ptr) +{ + if (!bo) { + dev_err(atomisp_dev, + "can not find buffer object contains " + "address 0x%x\n", ptr); + return -EINVAL; + } + + if (!hmm_bo_page_allocated(bo)) { + dev_err(atomisp_dev, + "buffer object has no page allocated.\n"); + return -EINVAL; + } + + if (!hmm_bo_allocated(bo)) { + dev_err(atomisp_dev, + "buffer object has no virtual address" + " space allocated.\n"); + return -EINVAL; + } + + return 0; +} + +/*Read function in ISP memory management*/ +static int load_and_flush_by_kmap(ia_css_ptr virt, void *data, unsigned int bytes) +{ + struct hmm_buffer_object *bo; + unsigned int idx, offset, len; + char *src, *des; + int ret; + + bo = hmm_bo_device_search_in_range(&bo_device, virt); + ret = hmm_check_bo(bo, virt); + if (ret) + return ret; + + des = (char *)data; + while (bytes) { + idx = (virt - bo->start) >> PAGE_SHIFT; + offset = (virt - bo->start) - (idx << PAGE_SHIFT); + + src = (char *)kmap(bo->page_obj[idx].page); + if (!src) { + dev_err(atomisp_dev, + "kmap buffer object page failed: " + "pg_idx = %d\n", idx); + return -EINVAL; + } + + src += offset; + + if ((bytes + offset) >= PAGE_SIZE) { + len = PAGE_SIZE - offset; + bytes -= len; + } else { + len = bytes; + bytes = 0; + } + + virt += len; /* update virt for next loop */ + + if (des) { + +#ifdef USE_SSSE3 + _ssse3_memcpy(des, src, len); +#else + memcpy(des, src, len); +#endif + des += len; + } + + clflush_cache_range(src, len); + + kunmap(bo->page_obj[idx].page); + } + + return 0; +} + +/*Read function in ISP memory management*/ +static int load_and_flush(ia_css_ptr virt, void *data, unsigned int bytes) +{ + struct hmm_buffer_object *bo; + int ret; + + bo = hmm_bo_device_search_in_range(&bo_device, virt); + ret = hmm_check_bo(bo, virt); + if (ret) + return ret; + + if (bo->status & HMM_BO_VMAPED || bo->status & HMM_BO_VMAPED_CACHED) { + void *src = bo->vmap_addr; + + src += (virt - bo->start); +#ifdef USE_SSSE3 + _ssse3_memcpy(data, src, bytes); +#else + memcpy(data, src, bytes); +#endif + if (bo->status & HMM_BO_VMAPED_CACHED) + clflush_cache_range(src, bytes); + } else { + void *vptr; + + vptr = hmm_bo_vmap(bo, true); + if (!vptr) + return load_and_flush_by_kmap(virt, data, bytes); + else + vptr = vptr + (virt - bo->start); + +#ifdef USE_SSSE3 + _ssse3_memcpy(data, vptr, bytes); +#else + memcpy(data, vptr, bytes); +#endif + clflush_cache_range(vptr, bytes); + hmm_bo_vunmap(bo); + } + + return 0; +} + +/*Read function in ISP memory management*/ +int hmm_load(ia_css_ptr virt, void *data, unsigned int bytes) +{ + if (!data) { + dev_err(atomisp_dev, + "hmm_load NULL argument\n"); + return -EINVAL; + } + return load_and_flush(virt, data, bytes); +} + +/*Flush hmm data from the data cache*/ +int hmm_flush(ia_css_ptr virt, unsigned int bytes) +{ + return load_and_flush(virt, NULL, bytes); +} + +/*Write function in ISP memory management*/ +int hmm_store(ia_css_ptr virt, const void *data, unsigned int bytes) +{ + struct hmm_buffer_object *bo; + unsigned int idx, offset, len; + char *src, *des; + int ret; + + bo = hmm_bo_device_search_in_range(&bo_device, virt); + ret = hmm_check_bo(bo, virt); + if (ret) + return ret; + + if (bo->status & HMM_BO_VMAPED || bo->status & HMM_BO_VMAPED_CACHED) { + void *dst = bo->vmap_addr; + + dst += (virt - bo->start); +#ifdef USE_SSSE3 + _ssse3_memcpy(dst, data, bytes); +#else + memcpy(dst, data, bytes); +#endif + if (bo->status & HMM_BO_VMAPED_CACHED) + clflush_cache_range(dst, bytes); + } else { + void *vptr; + + vptr = hmm_bo_vmap(bo, true); + if (vptr) { + vptr = vptr + (virt - bo->start); + +#ifdef USE_SSSE3 + _ssse3_memcpy(vptr, data, bytes); +#else + memcpy(vptr, data, bytes); +#endif + clflush_cache_range(vptr, bytes); + hmm_bo_vunmap(bo); + return 0; + } + } + + src = (char *)data; + while (bytes) { + idx = (virt - bo->start) >> PAGE_SHIFT; + offset = (virt - bo->start) - (idx << PAGE_SHIFT); + + if (in_atomic()) + des = (char *)kmap_atomic(bo->page_obj[idx].page); + else + des = (char *)kmap(bo->page_obj[idx].page); + + if (!des) { + dev_err(atomisp_dev, + "kmap buffer object page failed: " + "pg_idx = %d\n", idx); + return -EINVAL; + } + + des += offset; + + if ((bytes + offset) >= PAGE_SIZE) { + len = PAGE_SIZE - offset; + bytes -= len; + } else { + len = bytes; + bytes = 0; + } + + virt += len; + +#ifdef USE_SSSE3 + _ssse3_memcpy(des, src, len); +#else + memcpy(des, src, len); +#endif + src += len; + + clflush_cache_range(des, len); + + if (in_atomic()) + /* + * Note: kunmap_atomic requires return addr from + * kmap_atomic, not the page. See linux/highmem.h + */ + kunmap_atomic(des - offset); + else + kunmap(bo->page_obj[idx].page); + } + + return 0; +} + +/*memset function in ISP memory management*/ +int hmm_set(ia_css_ptr virt, int c, unsigned int bytes) +{ + struct hmm_buffer_object *bo; + unsigned int idx, offset, len; + char *des; + int ret; + + bo = hmm_bo_device_search_in_range(&bo_device, virt); + ret = hmm_check_bo(bo, virt); + if (ret) + return ret; + + if (bo->status & HMM_BO_VMAPED || bo->status & HMM_BO_VMAPED_CACHED) { + void *dst = bo->vmap_addr; + + dst += (virt - bo->start); + memset(dst, c, bytes); + + if (bo->status & HMM_BO_VMAPED_CACHED) + clflush_cache_range(dst, bytes); + } else { + void *vptr; + + vptr = hmm_bo_vmap(bo, true); + if (vptr) { + vptr = vptr + (virt - bo->start); + memset((void *)vptr, c, bytes); + clflush_cache_range(vptr, bytes); + hmm_bo_vunmap(bo); + return 0; + } + } + + while (bytes) { + idx = (virt - bo->start) >> PAGE_SHIFT; + offset = (virt - bo->start) - (idx << PAGE_SHIFT); + + des = (char *)kmap(bo->page_obj[idx].page); + if (!des) { + dev_err(atomisp_dev, + "kmap buffer object page failed: " + "pg_idx = %d\n", idx); + return -EINVAL; + } + des += offset; + + if ((bytes + offset) >= PAGE_SIZE) { + len = PAGE_SIZE - offset; + bytes -= len; + } else { + len = bytes; + bytes = 0; + } + + virt += len; + + memset(des, c, len); + + clflush_cache_range(des, len); + + kunmap(bo->page_obj[idx].page); + } + + return 0; +} + +/*Virtual address to physical address convert*/ +phys_addr_t hmm_virt_to_phys(ia_css_ptr virt) +{ + unsigned int idx, offset; + struct hmm_buffer_object *bo; + + bo = hmm_bo_device_search_in_range(&bo_device, virt); + if (!bo) { + dev_err(atomisp_dev, + "can not find buffer object contains address 0x%x\n", + virt); + return -1; + } + + idx = (virt - bo->start) >> PAGE_SHIFT; + offset = (virt - bo->start) - (idx << PAGE_SHIFT); + + return page_to_phys(bo->page_obj[idx].page) + offset; +} + +int hmm_mmap(struct vm_area_struct *vma, ia_css_ptr virt) +{ + struct hmm_buffer_object *bo; + + bo = hmm_bo_device_search_start(&bo_device, virt); + if (!bo) { + dev_err(atomisp_dev, + "can not find buffer object start with address 0x%x\n", + virt); + return -EINVAL; + } + + return hmm_bo_mmap(vma, bo); +} + +/*Map ISP virtual address into IA virtual address*/ +void *hmm_vmap(ia_css_ptr virt, bool cached) +{ + struct hmm_buffer_object *bo; + void *ptr; + + bo = hmm_bo_device_search_in_range(&bo_device, virt); + if (!bo) { + dev_err(atomisp_dev, + "can not find buffer object contains address 0x%x\n", + virt); + return NULL; + } + + ptr = hmm_bo_vmap(bo, cached); + if (ptr) + return ptr + (virt - bo->start); + else + return NULL; +} + +/* Flush the memory which is mapped as cached memory through hmm_vmap */ +void hmm_flush_vmap(ia_css_ptr virt) +{ + struct hmm_buffer_object *bo; + + bo = hmm_bo_device_search_in_range(&bo_device, virt); + if (!bo) { + dev_warn(atomisp_dev, + "can not find buffer object contains address 0x%x\n", + virt); + return; + } + + hmm_bo_flush_vmap(bo); +} + +void hmm_vunmap(ia_css_ptr virt) +{ + struct hmm_buffer_object *bo; + + bo = hmm_bo_device_search_in_range(&bo_device, virt); + if (!bo) { + dev_warn(atomisp_dev, + "can not find buffer object contains address 0x%x\n", + virt); + return; + } + + return hmm_bo_vunmap(bo); +} + +int hmm_pool_register(unsigned int pool_size, + enum hmm_pool_type pool_type) +{ + switch (pool_type) { + case HMM_POOL_TYPE_RESERVED: + reserved_pool.pops = &reserved_pops; + return reserved_pool.pops->pool_init(&reserved_pool.pool_info, + pool_size); + case HMM_POOL_TYPE_DYNAMIC: + dynamic_pool.pops = &dynamic_pops; + return dynamic_pool.pops->pool_init(&dynamic_pool.pool_info, + pool_size); + default: + dev_err(atomisp_dev, "invalid pool type.\n"); + return -EINVAL; + } +} + +void hmm_pool_unregister(enum hmm_pool_type pool_type) +{ + switch (pool_type) { + case HMM_POOL_TYPE_RESERVED: + if (reserved_pool.pops && reserved_pool.pops->pool_exit) + reserved_pool.pops->pool_exit(&reserved_pool.pool_info); + break; + case HMM_POOL_TYPE_DYNAMIC: + if (dynamic_pool.pops && dynamic_pool.pops->pool_exit) + dynamic_pool.pops->pool_exit(&dynamic_pool.pool_info); + break; + default: + dev_err(atomisp_dev, "invalid pool type.\n"); + break; + } + + return; +} + +void *hmm_isp_vaddr_to_host_vaddr(ia_css_ptr ptr, bool cached) +{ + return hmm_vmap(ptr, cached); + /* vmunmap will be done in hmm_bo_release() */ +} + +ia_css_ptr hmm_host_vaddr_to_hrt_vaddr(const void *ptr) +{ + struct hmm_buffer_object *bo; + + bo = hmm_bo_device_search_vmap_start(&bo_device, ptr); + if (bo) + return bo->start; + + dev_err(atomisp_dev, + "can not find buffer object whose kernel virtual address is %p\n", + ptr); + return 0; +} + +void hmm_show_mem_stat(const char *func, const int line) +{ + trace_printk("tol_cnt=%d usr_size=%d res_size=%d res_cnt=%d sys_size=%d dyc_thr=%d dyc_size=%d.\n", + hmm_mem_stat.tol_cnt, + hmm_mem_stat.usr_size, hmm_mem_stat.res_size, + hmm_mem_stat.res_cnt, hmm_mem_stat.sys_size, + hmm_mem_stat.dyc_thr, hmm_mem_stat.dyc_size); +} + +void hmm_init_mem_stat(int res_pgnr, int dyc_en, int dyc_pgnr) +{ + hmm_mem_stat.res_size = res_pgnr; + /* If reserved mem pool is not enabled, set its "mem stat" values as -1. */ + if (0 == hmm_mem_stat.res_size) { + hmm_mem_stat.res_size = -1; + hmm_mem_stat.res_cnt = -1; + } + + /* If dynamic memory pool is not enabled, set its "mem stat" values as -1. */ + if (!dyc_en) { + hmm_mem_stat.dyc_size = -1; + hmm_mem_stat.dyc_thr = -1; + } else { + hmm_mem_stat.dyc_size = 0; + hmm_mem_stat.dyc_thr = dyc_pgnr; + } + hmm_mem_stat.usr_size = 0; + hmm_mem_stat.sys_size = 0; + hmm_mem_stat.tol_cnt = 0; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/hmm/hmm_bo.c b/drivers/staging/media/atomisp/pci/atomisp2/hmm/hmm_bo.c new file mode 100644 index 0000000000000000000000000000000000000000..05ff912f3b5c05ab59e137f539c66c42c44357e5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/hmm/hmm_bo.c @@ -0,0 +1,1542 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +/* + * This file contains functions for buffer object structure management + */ +#include +#include +#include /* for GFP_ATOMIC */ +#include +#include +#include +#include +#include /* for kmalloc */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "atomisp_internal.h" +#include "hmm/hmm_common.h" +#include "hmm/hmm_pool.h" +#include "hmm/hmm_bo.h" + +static unsigned int order_to_nr(unsigned int order) +{ + return 1U << order; +} + +static unsigned int nr_to_order_bottom(unsigned int nr) +{ + return fls(nr) - 1; +} + +struct hmm_buffer_object *__bo_alloc(struct kmem_cache *bo_cache) +{ + struct hmm_buffer_object *bo; + + bo = kmem_cache_alloc(bo_cache, GFP_KERNEL); + if (!bo) + dev_err(atomisp_dev, "%s: __bo_alloc failed!\n", __func__); + + return bo; +} + +static int __bo_init(struct hmm_bo_device *bdev, struct hmm_buffer_object *bo, + unsigned int pgnr) +{ + check_bodev_null_return(bdev, -EINVAL); + var_equal_return(hmm_bo_device_inited(bdev), 0, -EINVAL, + "hmm_bo_device not inited yet.\n"); + /* prevent zero size buffer object */ + if (pgnr == 0) { + dev_err(atomisp_dev, "0 size buffer is not allowed.\n"); + return -EINVAL; + } + + memset(bo, 0, sizeof(*bo)); + mutex_init(&bo->mutex); + + /* init the bo->list HEAD as an element of entire_bo_list */ + INIT_LIST_HEAD(&bo->list); + + bo->bdev = bdev; + bo->vmap_addr = NULL; + bo->status = HMM_BO_FREE; + bo->start = bdev->start; + bo->pgnr = pgnr; + bo->end = bo->start + pgnr_to_size(pgnr); + bo->prev = NULL; + bo->next = NULL; + + return 0; +} + +struct hmm_buffer_object *__bo_search_and_remove_from_free_rbtree( + struct rb_node *node, unsigned int pgnr) +{ + struct hmm_buffer_object *this, *ret_bo, *temp_bo; + + this = rb_entry(node, struct hmm_buffer_object, node); + if (this->pgnr == pgnr || + (this->pgnr > pgnr && this->node.rb_left == NULL)) { + goto remove_bo_and_return; + } else { + if (this->pgnr < pgnr) { + if (!this->node.rb_right) + return NULL; + ret_bo = __bo_search_and_remove_from_free_rbtree( + this->node.rb_right, pgnr); + } else { + ret_bo = __bo_search_and_remove_from_free_rbtree( + this->node.rb_left, pgnr); + } + if (!ret_bo) { + if (this->pgnr > pgnr) + goto remove_bo_and_return; + else + return NULL; + } + return ret_bo; + } + +remove_bo_and_return: + /* NOTE: All nodes on free rbtree have a 'prev' that points to NULL. + * 1. check if 'this->next' is NULL: + * yes: erase 'this' node and rebalance rbtree, return 'this'. + */ + if (this->next == NULL) { + rb_erase(&this->node, &this->bdev->free_rbtree); + return this; + } + /* NOTE: if 'this->next' is not NULL, always return 'this->next' bo. + * 2. check if 'this->next->next' is NULL: + * yes: change the related 'next/prev' pointer, + * return 'this->next' but the rbtree stays unchanged. + */ + temp_bo = this->next; + this->next = temp_bo->next; + if (temp_bo->next) + temp_bo->next->prev = this; + temp_bo->next = NULL; + temp_bo->prev = NULL; + return temp_bo; +} + +struct hmm_buffer_object *__bo_search_by_addr(struct rb_root *root, + ia_css_ptr start) +{ + struct rb_node *n = root->rb_node; + struct hmm_buffer_object *bo; + + do { + bo = rb_entry(n, struct hmm_buffer_object, node); + + if (bo->start > start) { + if (n->rb_left == NULL) + return NULL; + n = n->rb_left; + } else if (bo->start < start) { + if (n->rb_right == NULL) + return NULL; + n = n->rb_right; + } else { + return bo; + } + } while (n); + + return NULL; +} + +struct hmm_buffer_object *__bo_search_by_addr_in_range(struct rb_root *root, + unsigned int start) +{ + struct rb_node *n = root->rb_node; + struct hmm_buffer_object *bo; + + do { + bo = rb_entry(n, struct hmm_buffer_object, node); + + if (bo->start > start) { + if (n->rb_left == NULL) + return NULL; + n = n->rb_left; + } else { + if (bo->end > start) + return bo; + if (n->rb_right == NULL) + return NULL; + n = n->rb_right; + } + } while (n); + + return NULL; +} + +static void __bo_insert_to_free_rbtree(struct rb_root *root, + struct hmm_buffer_object *bo) +{ + struct rb_node **new = &(root->rb_node); + struct rb_node *parent = NULL; + struct hmm_buffer_object *this; + unsigned int pgnr = bo->pgnr; + + while (*new) { + parent = *new; + this = container_of(*new, struct hmm_buffer_object, node); + + if (pgnr < this->pgnr) { + new = &((*new)->rb_left); + } else if (pgnr > this->pgnr) { + new = &((*new)->rb_right); + } else { + bo->prev = this; + bo->next = this->next; + if (this->next) + this->next->prev = bo; + this->next = bo; + bo->status = (bo->status & ~HMM_BO_MASK) | HMM_BO_FREE; + return; + } + } + + bo->status = (bo->status & ~HMM_BO_MASK) | HMM_BO_FREE; + + rb_link_node(&bo->node, parent, new); + rb_insert_color(&bo->node, root); +} + +static void __bo_insert_to_alloc_rbtree(struct rb_root *root, + struct hmm_buffer_object *bo) +{ + struct rb_node **new = &(root->rb_node); + struct rb_node *parent = NULL; + struct hmm_buffer_object *this; + unsigned int start = bo->start; + + while (*new) { + parent = *new; + this = container_of(*new, struct hmm_buffer_object, node); + + if (start < this->start) + new = &((*new)->rb_left); + else + new = &((*new)->rb_right); + } + + kref_init(&bo->kref); + bo->status = (bo->status & ~HMM_BO_MASK) | HMM_BO_ALLOCED; + + rb_link_node(&bo->node, parent, new); + rb_insert_color(&bo->node, root); +} + +struct hmm_buffer_object *__bo_break_up(struct hmm_bo_device *bdev, + struct hmm_buffer_object *bo, + unsigned int pgnr) +{ + struct hmm_buffer_object *new_bo; + unsigned long flags; + int ret; + + new_bo = __bo_alloc(bdev->bo_cache); + if (!new_bo) { + dev_err(atomisp_dev, "%s: __bo_alloc failed!\n", __func__); + return NULL; + } + ret = __bo_init(bdev, new_bo, pgnr); + if (ret) { + dev_err(atomisp_dev, "%s: __bo_init failed!\n", __func__); + kmem_cache_free(bdev->bo_cache, new_bo); + return NULL; + } + + new_bo->start = bo->start; + new_bo->end = new_bo->start + pgnr_to_size(pgnr); + bo->start = new_bo->end; + bo->pgnr = bo->pgnr - pgnr; + + spin_lock_irqsave(&bdev->list_lock, flags); + list_add_tail(&new_bo->list, &bo->list); + spin_unlock_irqrestore(&bdev->list_lock, flags); + + return new_bo; +} + +static void __bo_take_off_handling(struct hmm_buffer_object *bo) +{ + struct hmm_bo_device *bdev = bo->bdev; + /* There are 4 situations when we take off a known bo from free rbtree: + * 1. if bo->next && bo->prev == NULL, bo is a rbtree node + * and does not have a linked list after bo, to take off this bo, + * we just need erase bo directly and rebalance the free rbtree + */ + if (bo->prev == NULL && bo->next == NULL) { + rb_erase(&bo->node, &bdev->free_rbtree); + /* 2. when bo->next != NULL && bo->prev == NULL, bo is a rbtree node, + * and has a linked list,to take off this bo we need erase bo + * first, then, insert bo->next into free rbtree and rebalance + * the free rbtree + */ + } else if (bo->prev == NULL && bo->next != NULL) { + bo->next->prev = NULL; + rb_erase(&bo->node, &bdev->free_rbtree); + __bo_insert_to_free_rbtree(&bdev->free_rbtree, bo->next); + bo->next = NULL; + /* 3. when bo->prev != NULL && bo->next == NULL, bo is not a rbtree + * node, bo is the last element of the linked list after rbtree + * node, to take off this bo, we just need set the "prev/next" + * pointers to NULL, the free rbtree stays unchaged + */ + } else if (bo->prev != NULL && bo->next == NULL) { + bo->prev->next = NULL; + bo->prev = NULL; + /* 4. when bo->prev != NULL && bo->next != NULL ,bo is not a rbtree + * node, bo is in the middle of the linked list after rbtree node, + * to take off this bo, we just set take the "prev/next" pointers + * to NULL, the free rbtree stays unchaged + */ + } else { + bo->next->prev = bo->prev; + bo->prev->next = bo->next; + bo->next = NULL; + bo->prev = NULL; + } +} + +struct hmm_buffer_object *__bo_merge(struct hmm_buffer_object *bo, + struct hmm_buffer_object *next_bo) +{ + struct hmm_bo_device *bdev; + unsigned long flags; + + bdev = bo->bdev; + next_bo->start = bo->start; + next_bo->pgnr = next_bo->pgnr + bo->pgnr; + + spin_lock_irqsave(&bdev->list_lock, flags); + list_del(&bo->list); + spin_unlock_irqrestore(&bdev->list_lock, flags); + + kmem_cache_free(bo->bdev->bo_cache, bo); + + return next_bo; +} + +/* + * hmm_bo_device functions. + */ +int hmm_bo_device_init(struct hmm_bo_device *bdev, + struct isp_mmu_client *mmu_driver, + unsigned int vaddr_start, + unsigned int size) +{ + struct hmm_buffer_object *bo; + unsigned long flags; + int ret; + + check_bodev_null_return(bdev, -EINVAL); + + ret = isp_mmu_init(&bdev->mmu, mmu_driver); + if (ret) { + dev_err(atomisp_dev, "isp_mmu_init failed.\n"); + return ret; + } + + bdev->start = vaddr_start; + bdev->pgnr = size_to_pgnr_ceil(size); + bdev->size = pgnr_to_size(bdev->pgnr); + + spin_lock_init(&bdev->list_lock); + mutex_init(&bdev->rbtree_mutex); + + bdev->flag = HMM_BO_DEVICE_INITED; + + INIT_LIST_HEAD(&bdev->entire_bo_list); + bdev->allocated_rbtree = RB_ROOT; + bdev->free_rbtree = RB_ROOT; + + bdev->bo_cache = kmem_cache_create("bo_cache", + sizeof(struct hmm_buffer_object), 0, 0, NULL); + if (!bdev->bo_cache) { + dev_err(atomisp_dev, "%s: create cache failed!\n", __func__); + isp_mmu_exit(&bdev->mmu); + return -ENOMEM; + } + + bo = __bo_alloc(bdev->bo_cache); + if (!bo) { + dev_err(atomisp_dev, "%s: __bo_alloc failed!\n", __func__); + isp_mmu_exit(&bdev->mmu); + return -ENOMEM; + } + + ret = __bo_init(bdev, bo, bdev->pgnr); + if (ret) { + dev_err(atomisp_dev, "%s: __bo_init failed!\n", __func__); + kmem_cache_free(bdev->bo_cache, bo); + isp_mmu_exit(&bdev->mmu); + return -EINVAL; + } + + spin_lock_irqsave(&bdev->list_lock, flags); + list_add_tail(&bo->list, &bdev->entire_bo_list); + spin_unlock_irqrestore(&bdev->list_lock, flags); + + __bo_insert_to_free_rbtree(&bdev->free_rbtree, bo); + + return 0; +} + +struct hmm_buffer_object *hmm_bo_alloc(struct hmm_bo_device *bdev, + unsigned int pgnr) +{ + struct hmm_buffer_object *bo, *new_bo; + struct rb_root *root = &bdev->free_rbtree; + + check_bodev_null_return(bdev, NULL); + var_equal_return(hmm_bo_device_inited(bdev), 0, NULL, + "hmm_bo_device not inited yet.\n"); + + if (pgnr == 0) { + dev_err(atomisp_dev, "0 size buffer is not allowed.\n"); + return NULL; + } + + mutex_lock(&bdev->rbtree_mutex); + bo = __bo_search_and_remove_from_free_rbtree(root->rb_node, pgnr); + if (!bo) { + mutex_unlock(&bdev->rbtree_mutex); + dev_err(atomisp_dev, "%s: Out of Memory! hmm_bo_alloc failed", + __func__); + return NULL; + } + + if (bo->pgnr > pgnr) { + new_bo = __bo_break_up(bdev, bo, pgnr); + if (!new_bo) { + mutex_unlock(&bdev->rbtree_mutex); + dev_err(atomisp_dev, "%s: __bo_break_up failed!\n", + __func__); + return NULL; + } + + __bo_insert_to_alloc_rbtree(&bdev->allocated_rbtree, new_bo); + __bo_insert_to_free_rbtree(&bdev->free_rbtree, bo); + + mutex_unlock(&bdev->rbtree_mutex); + return new_bo; + } + + __bo_insert_to_alloc_rbtree(&bdev->allocated_rbtree, bo); + + mutex_unlock(&bdev->rbtree_mutex); + return bo; +} + +void hmm_bo_release(struct hmm_buffer_object *bo) +{ + struct hmm_bo_device *bdev = bo->bdev; + struct hmm_buffer_object *next_bo, *prev_bo; + + mutex_lock(&bdev->rbtree_mutex); + + /* + * FIX ME: + * + * how to destroy the bo when it is stilled MMAPED? + * + * ideally, this will not happened as hmm_bo_release + * will only be called when kref reaches 0, and in mmap + * operation the hmm_bo_ref will eventually be called. + * so, if this happened, something goes wrong. + */ + if (bo->status & HMM_BO_MMAPED) { + mutex_unlock(&bdev->rbtree_mutex); + dev_dbg(atomisp_dev, "destroy bo which is MMAPED, do nothing\n"); + return; + } + + if (bo->status & HMM_BO_BINDED) { + dev_warn(atomisp_dev, "the bo is still binded, unbind it first...\n"); + hmm_bo_unbind(bo); + } + + if (bo->status & HMM_BO_PAGE_ALLOCED) { + dev_warn(atomisp_dev, "the pages is not freed, free pages first\n"); + hmm_bo_free_pages(bo); + } + if (bo->status & HMM_BO_VMAPED || bo->status & HMM_BO_VMAPED_CACHED) { + dev_warn(atomisp_dev, "the vunmap is not done, do it...\n"); + hmm_bo_vunmap(bo); + } + + rb_erase(&bo->node, &bdev->allocated_rbtree); + + prev_bo = list_entry(bo->list.prev, struct hmm_buffer_object, list); + next_bo = list_entry(bo->list.next, struct hmm_buffer_object, list); + + if (bo->list.prev != &bdev->entire_bo_list && + prev_bo->end == bo->start && + (prev_bo->status & HMM_BO_MASK) == HMM_BO_FREE) { + __bo_take_off_handling(prev_bo); + bo = __bo_merge(prev_bo, bo); + } + + if (bo->list.next != &bdev->entire_bo_list && + next_bo->start == bo->end && + (next_bo->status & HMM_BO_MASK) == HMM_BO_FREE) { + __bo_take_off_handling(next_bo); + bo = __bo_merge(bo, next_bo); + } + + __bo_insert_to_free_rbtree(&bdev->free_rbtree, bo); + + mutex_unlock(&bdev->rbtree_mutex); + return; +} + +void hmm_bo_device_exit(struct hmm_bo_device *bdev) +{ + struct hmm_buffer_object *bo; + unsigned long flags; + + dev_dbg(atomisp_dev, "%s: entering!\n", __func__); + + check_bodev_null_return_void(bdev); + + /* + * release all allocated bos even they a in use + * and all bos will be merged into a big bo + */ + while (!RB_EMPTY_ROOT(&bdev->allocated_rbtree)) + hmm_bo_release( + rbtree_node_to_hmm_bo(bdev->allocated_rbtree.rb_node)); + + dev_dbg(atomisp_dev, "%s: finished releasing all allocated bos!\n", + __func__); + + /* free all bos to release all ISP virtual memory */ + while (!list_empty(&bdev->entire_bo_list)) { + bo = list_to_hmm_bo(bdev->entire_bo_list.next); + + spin_lock_irqsave(&bdev->list_lock, flags); + list_del(&bo->list); + spin_unlock_irqrestore(&bdev->list_lock, flags); + + kmem_cache_free(bdev->bo_cache, bo); + } + + dev_dbg(atomisp_dev, "%s: finished to free all bos!\n", __func__); + + kmem_cache_destroy(bdev->bo_cache); + + isp_mmu_exit(&bdev->mmu); +} + +int hmm_bo_device_inited(struct hmm_bo_device *bdev) +{ + check_bodev_null_return(bdev, -EINVAL); + + return bdev->flag == HMM_BO_DEVICE_INITED; +} + +int hmm_bo_allocated(struct hmm_buffer_object *bo) +{ + check_bo_null_return(bo, 0); + + return bo->status & HMM_BO_ALLOCED; +} + +struct hmm_buffer_object *hmm_bo_device_search_start( + struct hmm_bo_device *bdev, ia_css_ptr vaddr) +{ + struct hmm_buffer_object *bo; + + check_bodev_null_return(bdev, NULL); + + mutex_lock(&bdev->rbtree_mutex); + bo = __bo_search_by_addr(&bdev->allocated_rbtree, vaddr); + if (!bo) { + mutex_unlock(&bdev->rbtree_mutex); + dev_err(atomisp_dev, "%s can not find bo with addr: 0x%x\n", + __func__, vaddr); + return NULL; + } + mutex_unlock(&bdev->rbtree_mutex); + + return bo; +} + +struct hmm_buffer_object *hmm_bo_device_search_in_range( + struct hmm_bo_device *bdev, unsigned int vaddr) +{ + struct hmm_buffer_object *bo; + + check_bodev_null_return(bdev, NULL); + + mutex_lock(&bdev->rbtree_mutex); + bo = __bo_search_by_addr_in_range(&bdev->allocated_rbtree, vaddr); + if (!bo) { + mutex_unlock(&bdev->rbtree_mutex); + dev_err(atomisp_dev, "%s can not find bo contain addr: 0x%x\n", + __func__, vaddr); + return NULL; + } + mutex_unlock(&bdev->rbtree_mutex); + + return bo; +} + +struct hmm_buffer_object *hmm_bo_device_search_vmap_start( + struct hmm_bo_device *bdev, const void *vaddr) +{ + struct list_head *pos; + struct hmm_buffer_object *bo; + unsigned long flags; + + check_bodev_null_return(bdev, NULL); + + spin_lock_irqsave(&bdev->list_lock, flags); + list_for_each(pos, &bdev->entire_bo_list) { + bo = list_to_hmm_bo(pos); + /* pass bo which has no vm_node allocated */ + if ((bo->status & HMM_BO_MASK) == HMM_BO_FREE) + continue; + if (bo->vmap_addr == vaddr) + goto found; + } + spin_unlock_irqrestore(&bdev->list_lock, flags); + return NULL; +found: + spin_unlock_irqrestore(&bdev->list_lock, flags); + return bo; + +} + + +static void free_private_bo_pages(struct hmm_buffer_object *bo, + struct hmm_pool *dypool, + struct hmm_pool *repool, + int free_pgnr) +{ + int i, ret; + + for (i = 0; i < free_pgnr; i++) { + switch (bo->page_obj[i].type) { + case HMM_PAGE_TYPE_RESERVED: + if (repool->pops + && repool->pops->pool_free_pages) { + repool->pops->pool_free_pages(repool->pool_info, + &bo->page_obj[i]); + hmm_mem_stat.res_cnt--; + } + break; + /* + * HMM_PAGE_TYPE_GENERAL indicates that pages are from system + * memory, so when free them, they should be put into dynamic + * pool. + */ + case HMM_PAGE_TYPE_DYNAMIC: + case HMM_PAGE_TYPE_GENERAL: + if (dypool->pops + && dypool->pops->pool_inited + && dypool->pops->pool_inited(dypool->pool_info)) { + if (dypool->pops->pool_free_pages) + dypool->pops->pool_free_pages( + dypool->pool_info, + &bo->page_obj[i]); + break; + } + + /* + * if dynamic memory pool doesn't exist, need to free + * pages to system directly. + */ + default: + ret = set_pages_wb(bo->page_obj[i].page, 1); + if (ret) + dev_err(atomisp_dev, + "set page to WB err ...ret = %d\n", + ret); + /* + W/A: set_pages_wb seldom return value = -EFAULT + indicate that address of page is not in valid + range(0xffff880000000000~0xffffc7ffffffffff) + then, _free_pages would panic; Do not know why page + address be valid,it maybe memory corruption by lowmemory + */ + if (!ret) { + __free_pages(bo->page_obj[i].page, 0); + hmm_mem_stat.sys_size--; + } + break; + } + } + + return; +} + +/*Allocate pages which will be used only by ISP*/ +static int alloc_private_pages(struct hmm_buffer_object *bo, + int from_highmem, + bool cached, + struct hmm_pool *dypool, + struct hmm_pool *repool) +{ + int ret; + unsigned int pgnr, order, blk_pgnr, alloc_pgnr; + struct page *pages; + gfp_t gfp = GFP_NOWAIT | __GFP_NOWARN; /* REVISIT: need __GFP_FS too? */ + int i, j; + int failure_number = 0; + bool reduce_order = false; + bool lack_mem = true; + + if (from_highmem) + gfp |= __GFP_HIGHMEM; + + pgnr = bo->pgnr; + + bo->page_obj = atomisp_kernel_malloc( + sizeof(struct hmm_page_object) * pgnr); + if (unlikely(!bo->page_obj)) { + dev_err(atomisp_dev, "out of memory for bo->page_obj\n"); + return -ENOMEM; + } + + i = 0; + alloc_pgnr = 0; + + /* + * get physical pages from dynamic pages pool. + */ + if (dypool->pops && dypool->pops->pool_alloc_pages) { + alloc_pgnr = dypool->pops->pool_alloc_pages(dypool->pool_info, + bo->page_obj, pgnr, + cached); + hmm_mem_stat.dyc_size -= alloc_pgnr; + + if (alloc_pgnr == pgnr) + return 0; + } + + pgnr -= alloc_pgnr; + i += alloc_pgnr; + + /* + * get physical pages from reserved pages pool for atomisp. + */ + if (repool->pops && repool->pops->pool_alloc_pages) { + alloc_pgnr = repool->pops->pool_alloc_pages(repool->pool_info, + &bo->page_obj[i], pgnr, + cached); + hmm_mem_stat.res_cnt += alloc_pgnr; + if (alloc_pgnr == pgnr) + return 0; + } + + pgnr -= alloc_pgnr; + i += alloc_pgnr; + + while (pgnr) { + order = nr_to_order_bottom(pgnr); + /* + * if be short of memory, we will set order to 0 + * everytime. + */ + if (lack_mem) + order = HMM_MIN_ORDER; + else if (order > HMM_MAX_ORDER) + order = HMM_MAX_ORDER; +retry: + /* + * When order > HMM_MIN_ORDER, for performance reasons we don't + * want alloc_pages() to sleep. In case it fails and fallbacks + * to HMM_MIN_ORDER or in case the requested order is originally + * the minimum value, we can allow alloc_pages() to sleep for + * robustness purpose. + * + * REVISIT: why __GFP_FS is necessary? + */ + if (order == HMM_MIN_ORDER) { + gfp &= ~GFP_NOWAIT; + gfp |= __GFP_RECLAIM | __GFP_FS; + } + + pages = alloc_pages(gfp, order); + if (unlikely(!pages)) { + /* + * in low memory case, if allocation page fails, + * we turn to try if order=0 allocation could + * succeed. if order=0 fails too, that means there is + * no memory left. + */ + if (order == HMM_MIN_ORDER) { + dev_err(atomisp_dev, + "%s: cannot allocate pages\n", + __func__); + goto cleanup; + } + order = HMM_MIN_ORDER; + failure_number++; + reduce_order = true; + /* + * if fail two times continuously, we think be short + * of memory now. + */ + if (failure_number == 2) { + lack_mem = true; + failure_number = 0; + } + goto retry; + } else { + blk_pgnr = order_to_nr(order); + + if (!cached) { + /* + * set memory to uncacheable -- UC_MINUS + */ + ret = set_pages_uc(pages, blk_pgnr); + if (ret) { + dev_err(atomisp_dev, + "set page uncacheable" + "failed.\n"); + + __free_pages(pages, order); + + goto cleanup; + } + } + + for (j = 0; j < blk_pgnr; j++) { + bo->page_obj[i].page = pages + j; + bo->page_obj[i++].type = HMM_PAGE_TYPE_GENERAL; + } + + pgnr -= blk_pgnr; + hmm_mem_stat.sys_size += blk_pgnr; + + /* + * if order is not reduced this time, clear + * failure_number. + */ + if (reduce_order) + reduce_order = false; + else + failure_number = 0; + } + } + + return 0; +cleanup: + alloc_pgnr = i; + free_private_bo_pages(bo, dypool, repool, alloc_pgnr); + + atomisp_kernel_free(bo->page_obj); + + return -ENOMEM; +} + +static void free_private_pages(struct hmm_buffer_object *bo, + struct hmm_pool *dypool, + struct hmm_pool *repool) +{ + free_private_bo_pages(bo, dypool, repool, bo->pgnr); + + atomisp_kernel_free(bo->page_obj); +} + +/* + * Hacked from kernel function __get_user_pages in mm/memory.c + * + * Handle buffers allocated by other kernel space driver and mmaped into user + * space, function Ignore the VM_PFNMAP and VM_IO flag in VMA structure + * + * Get physical pages from user space virtual address and update into page list + */ +static int __get_pfnmap_pages(struct task_struct *tsk, struct mm_struct *mm, + unsigned long start, int nr_pages, + unsigned int gup_flags, struct page **pages, + struct vm_area_struct **vmas) +{ + int i, ret; + unsigned long vm_flags; + + if (nr_pages <= 0) + return 0; + + VM_BUG_ON(!!pages != !!(gup_flags & FOLL_GET)); + + /* + * Require read or write permissions. + * If FOLL_FORCE is set, we only require the "MAY" flags. + */ + vm_flags = (gup_flags & FOLL_WRITE) ? + (VM_WRITE | VM_MAYWRITE) : (VM_READ | VM_MAYREAD); + vm_flags &= (gup_flags & FOLL_FORCE) ? + (VM_MAYREAD | VM_MAYWRITE) : (VM_READ | VM_WRITE); + i = 0; + + do { + struct vm_area_struct *vma; + + vma = find_vma(mm, start); + if (!vma) { + dev_err(atomisp_dev, "find_vma failed\n"); + return i ? : -EFAULT; + } + + if (is_vm_hugetlb_page(vma)) { + /* + i = follow_hugetlb_page(mm, vma, pages, vmas, + &start, &nr_pages, i, gup_flags); + */ + continue; + } + + do { + struct page *page; + unsigned long pfn; + + /* + * If we have a pending SIGKILL, don't keep faulting + * pages and potentially allocating memory. + */ + if (unlikely(fatal_signal_pending(current))) { + dev_err(atomisp_dev, + "fatal_signal_pending in %s\n", + __func__); + return i ? i : -ERESTARTSYS; + } + + ret = follow_pfn(vma, start, &pfn); + if (ret) { + dev_err(atomisp_dev, "follow_pfn() failed\n"); + return i ? : -EFAULT; + } + + page = pfn_to_page(pfn); + if (IS_ERR(page)) + return i ? i : PTR_ERR(page); + if (pages) { + pages[i] = page; + get_page(page); + flush_anon_page(vma, page, start); + flush_dcache_page(page); + } + if (vmas) + vmas[i] = vma; + i++; + start += PAGE_SIZE; + nr_pages--; + } while (nr_pages && start < vma->vm_end); + } while (nr_pages); + + return i; +} + +static int get_pfnmap_pages(struct task_struct *tsk, struct mm_struct *mm, + unsigned long start, int nr_pages, int write, int force, + struct page **pages, struct vm_area_struct **vmas) +{ + int flags = FOLL_TOUCH; + + if (pages) + flags |= FOLL_GET; + if (write) + flags |= FOLL_WRITE; + if (force) + flags |= FOLL_FORCE; + + return __get_pfnmap_pages(tsk, mm, start, nr_pages, flags, pages, vmas); +} + +/* + * Convert user space virtual address into pages list + */ +static int alloc_user_pages(struct hmm_buffer_object *bo, + void *userptr, bool cached) +{ + int page_nr; + int i; + struct vm_area_struct *vma; + struct page **pages; + + pages = atomisp_kernel_malloc(sizeof(struct page *) * bo->pgnr); + if (unlikely(!pages)) { + dev_err(atomisp_dev, "out of memory for pages...\n"); + return -ENOMEM; + } + + bo->page_obj = atomisp_kernel_malloc( + sizeof(struct hmm_page_object) * bo->pgnr); + if (unlikely(!bo->page_obj)) { + dev_err(atomisp_dev, "out of memory for bo->page_obj...\n"); + atomisp_kernel_free(pages); + return -ENOMEM; + } + + mutex_unlock(&bo->mutex); + down_read(¤t->mm->mmap_sem); + vma = find_vma(current->mm, (unsigned long)userptr); + up_read(¤t->mm->mmap_sem); + if (vma == NULL) { + dev_err(atomisp_dev, "find_vma failed\n"); + atomisp_kernel_free(bo->page_obj); + atomisp_kernel_free(pages); + return -EFAULT; + } + mutex_lock(&bo->mutex); + /* + * Handle frame buffer allocated in other kerenl space driver + * and map to user space + */ + if (vma->vm_flags & (VM_IO | VM_PFNMAP)) { + page_nr = get_pfnmap_pages(current, current->mm, + (unsigned long)userptr, + (int)(bo->pgnr), 1, 0, + pages, NULL); + bo->mem_type = HMM_BO_MEM_TYPE_PFN; + } else { + /*Handle frame buffer allocated in user space*/ + mutex_unlock(&bo->mutex); + down_read(¤t->mm->mmap_sem); + page_nr = get_user_pages((unsigned long)userptr, + (int)(bo->pgnr), 1, pages, NULL); + up_read(¤t->mm->mmap_sem); + mutex_lock(&bo->mutex); + bo->mem_type = HMM_BO_MEM_TYPE_USER; + } + + /* can be written by caller, not forced */ + if (page_nr != bo->pgnr) { + dev_err(atomisp_dev, + "get_user_pages err: bo->pgnr = %d, " + "pgnr actually pinned = %d.\n", + bo->pgnr, page_nr); + goto out_of_mem; + } + + for (i = 0; i < bo->pgnr; i++) { + bo->page_obj[i].page = pages[i]; + bo->page_obj[i].type = HMM_PAGE_TYPE_GENERAL; + } + hmm_mem_stat.usr_size += bo->pgnr; + atomisp_kernel_free(pages); + + return 0; + +out_of_mem: + for (i = 0; i < page_nr; i++) + put_page(pages[i]); + atomisp_kernel_free(pages); + atomisp_kernel_free(bo->page_obj); + + return -ENOMEM; +} + +static void free_user_pages(struct hmm_buffer_object *bo) +{ + int i; + + for (i = 0; i < bo->pgnr; i++) + put_page(bo->page_obj[i].page); + hmm_mem_stat.usr_size -= bo->pgnr; + + atomisp_kernel_free(bo->page_obj); +} + +/* + * allocate/free physical pages for the bo. + * + * type indicate where are the pages from. currently we have 3 types + * of memory: HMM_BO_PRIVATE, HMM_BO_USER, HMM_BO_SHARE. + * + * from_highmem is only valid when type is HMM_BO_PRIVATE, it will + * try to alloc memory from highmem if from_highmem is set. + * + * userptr is only valid when type is HMM_BO_USER, it indicates + * the start address from user space task. + * + * from_highmem and userptr will both be ignored when type is + * HMM_BO_SHARE. + */ +int hmm_bo_alloc_pages(struct hmm_buffer_object *bo, + enum hmm_bo_type type, int from_highmem, + void *userptr, bool cached) +{ + int ret = -EINVAL; + + check_bo_null_return(bo, -EINVAL); + + mutex_lock(&bo->mutex); + check_bo_status_no_goto(bo, HMM_BO_PAGE_ALLOCED, status_err); + + /* + * TO DO: + * add HMM_BO_USER type + */ + if (type == HMM_BO_PRIVATE) { + ret = alloc_private_pages(bo, from_highmem, + cached, &dynamic_pool, &reserved_pool); + } else if (type == HMM_BO_USER) { + ret = alloc_user_pages(bo, userptr, cached); + } else { + dev_err(atomisp_dev, "invalid buffer type.\n"); + ret = -EINVAL; + } + if (ret) + goto alloc_err; + + bo->type = type; + + bo->status |= HMM_BO_PAGE_ALLOCED; + + mutex_unlock(&bo->mutex); + + return 0; + +alloc_err: + mutex_unlock(&bo->mutex); + dev_err(atomisp_dev, "alloc pages err...\n"); + return ret; +status_err: + mutex_unlock(&bo->mutex); + dev_err(atomisp_dev, + "buffer object has already page allocated.\n"); + return -EINVAL; +} + +/* + * free physical pages of the bo. + */ +void hmm_bo_free_pages(struct hmm_buffer_object *bo) +{ + check_bo_null_return_void(bo); + + mutex_lock(&bo->mutex); + + check_bo_status_yes_goto(bo, HMM_BO_PAGE_ALLOCED, status_err2); + + /* clear the flag anyway. */ + bo->status &= (~HMM_BO_PAGE_ALLOCED); + + if (bo->type == HMM_BO_PRIVATE) + free_private_pages(bo, &dynamic_pool, &reserved_pool); + else if (bo->type == HMM_BO_USER) + free_user_pages(bo); + else + dev_err(atomisp_dev, "invalid buffer type.\n"); + mutex_unlock(&bo->mutex); + + return; + +status_err2: + mutex_unlock(&bo->mutex); + dev_err(atomisp_dev, + "buffer object not page allocated yet.\n"); +} + +int hmm_bo_page_allocated(struct hmm_buffer_object *bo) +{ + int ret; + + check_bo_null_return(bo, 0); + + ret = bo->status & HMM_BO_PAGE_ALLOCED; + + return ret; +} + +/* + * get physical page info of the bo. + */ +int hmm_bo_get_page_info(struct hmm_buffer_object *bo, + struct hmm_page_object **page_obj, int *pgnr) +{ + check_bo_null_return(bo, -EINVAL); + + mutex_lock(&bo->mutex); + + check_bo_status_yes_goto(bo, HMM_BO_PAGE_ALLOCED, status_err); + + *page_obj = bo->page_obj; + *pgnr = bo->pgnr; + + mutex_unlock(&bo->mutex); + + return 0; + +status_err: + dev_err(atomisp_dev, + "buffer object not page allocated yet.\n"); + mutex_unlock(&bo->mutex); + return -EINVAL; +} + +/* + * bind the physical pages to a virtual address space. + */ +int hmm_bo_bind(struct hmm_buffer_object *bo) +{ + int ret; + unsigned int virt; + struct hmm_bo_device *bdev; + unsigned int i; + + check_bo_null_return(bo, -EINVAL); + + mutex_lock(&bo->mutex); + + check_bo_status_yes_goto(bo, + HMM_BO_PAGE_ALLOCED | HMM_BO_ALLOCED, + status_err1); + + check_bo_status_no_goto(bo, HMM_BO_BINDED, status_err2); + + bdev = bo->bdev; + + virt = bo->start; + + for (i = 0; i < bo->pgnr; i++) { + ret = + isp_mmu_map(&bdev->mmu, virt, + page_to_phys(bo->page_obj[i].page), 1); + if (ret) + goto map_err; + virt += (1 << PAGE_SHIFT); + } + + /* + * flush TBL here. + * + * theoretically, we donot need to flush TLB as we didnot change + * any existed address mappings, but for Silicon Hive's MMU, its + * really a bug here. I guess when fetching PTEs (page table entity) + * to TLB, its MMU will fetch additional INVALID PTEs automatically + * for performance issue. EX, we only set up 1 page address mapping, + * meaning updating 1 PTE, but the MMU fetches 4 PTE at one time, + * so the additional 3 PTEs are invalid. + */ + if (bo->start != 0x0) + isp_mmu_flush_tlb_range(&bdev->mmu, bo->start, + (bo->pgnr << PAGE_SHIFT)); + + bo->status |= HMM_BO_BINDED; + + mutex_unlock(&bo->mutex); + + return 0; + +map_err: + /* unbind the physical pages with related virtual address space */ + virt = bo->start; + for ( ; i > 0; i--) { + isp_mmu_unmap(&bdev->mmu, virt, 1); + virt += pgnr_to_size(1); + } + + mutex_unlock(&bo->mutex); + dev_err(atomisp_dev, + "setup MMU address mapping failed.\n"); + return ret; + +status_err2: + mutex_unlock(&bo->mutex); + dev_err(atomisp_dev, "buffer object already binded.\n"); + return -EINVAL; +status_err1: + mutex_unlock(&bo->mutex); + dev_err(atomisp_dev, + "buffer object vm_node or page not allocated.\n"); + return -EINVAL; +} + +/* + * unbind the physical pages with related virtual address space. + */ +void hmm_bo_unbind(struct hmm_buffer_object *bo) +{ + unsigned int virt; + struct hmm_bo_device *bdev; + unsigned int i; + + check_bo_null_return_void(bo); + + mutex_lock(&bo->mutex); + + check_bo_status_yes_goto(bo, + HMM_BO_PAGE_ALLOCED | + HMM_BO_ALLOCED | + HMM_BO_BINDED, status_err); + + bdev = bo->bdev; + + virt = bo->start; + + for (i = 0; i < bo->pgnr; i++) { + isp_mmu_unmap(&bdev->mmu, virt, 1); + virt += pgnr_to_size(1); + } + + /* + * flush TLB as the address mapping has been removed and + * related TLBs should be invalidated. + */ + isp_mmu_flush_tlb_range(&bdev->mmu, bo->start, + (bo->pgnr << PAGE_SHIFT)); + + bo->status &= (~HMM_BO_BINDED); + + mutex_unlock(&bo->mutex); + + return; + +status_err: + mutex_unlock(&bo->mutex); + dev_err(atomisp_dev, + "buffer vm or page not allocated or not binded yet.\n"); +} + +int hmm_bo_binded(struct hmm_buffer_object *bo) +{ + int ret; + + check_bo_null_return(bo, 0); + + mutex_lock(&bo->mutex); + + ret = bo->status & HMM_BO_BINDED; + + mutex_unlock(&bo->mutex); + + return ret; +} + +void *hmm_bo_vmap(struct hmm_buffer_object *bo, bool cached) +{ + struct page **pages; + int i; + + check_bo_null_return(bo, NULL); + + mutex_lock(&bo->mutex); + if (((bo->status & HMM_BO_VMAPED) && !cached) || + ((bo->status & HMM_BO_VMAPED_CACHED) && cached)) { + mutex_unlock(&bo->mutex); + return bo->vmap_addr; + } + + /* cached status need to be changed, so vunmap first */ + if (bo->status & HMM_BO_VMAPED || bo->status & HMM_BO_VMAPED_CACHED) { + vunmap(bo->vmap_addr); + bo->vmap_addr = NULL; + bo->status &= ~(HMM_BO_VMAPED | HMM_BO_VMAPED_CACHED); + } + + pages = atomisp_kernel_malloc(sizeof(*pages) * bo->pgnr); + if (unlikely(!pages)) { + mutex_unlock(&bo->mutex); + dev_err(atomisp_dev, "out of memory for pages...\n"); + return NULL; + } + + for (i = 0; i < bo->pgnr; i++) + pages[i] = bo->page_obj[i].page; + + bo->vmap_addr = vmap(pages, bo->pgnr, VM_MAP, + cached ? PAGE_KERNEL : PAGE_KERNEL_NOCACHE); + if (unlikely(!bo->vmap_addr)) { + atomisp_kernel_free(pages); + mutex_unlock(&bo->mutex); + dev_err(atomisp_dev, "vmap failed...\n"); + return NULL; + } + bo->status |= (cached ? HMM_BO_VMAPED_CACHED : HMM_BO_VMAPED); + + atomisp_kernel_free(pages); + + mutex_unlock(&bo->mutex); + return bo->vmap_addr; +} + +void hmm_bo_flush_vmap(struct hmm_buffer_object *bo) +{ + check_bo_null_return_void(bo); + + mutex_lock(&bo->mutex); + if (!(bo->status & HMM_BO_VMAPED_CACHED) || !bo->vmap_addr) { + mutex_unlock(&bo->mutex); + return; + } + + clflush_cache_range(bo->vmap_addr, bo->pgnr * PAGE_SIZE); + mutex_unlock(&bo->mutex); +} + +void hmm_bo_vunmap(struct hmm_buffer_object *bo) +{ + check_bo_null_return_void(bo); + + mutex_lock(&bo->mutex); + if (bo->status & HMM_BO_VMAPED || bo->status & HMM_BO_VMAPED_CACHED) { + vunmap(bo->vmap_addr); + bo->vmap_addr = NULL; + bo->status &= ~(HMM_BO_VMAPED | HMM_BO_VMAPED_CACHED); + } + + mutex_unlock(&bo->mutex); + return; +} + +void hmm_bo_ref(struct hmm_buffer_object *bo) +{ + check_bo_null_return_void(bo); + + kref_get(&bo->kref); +} + +static void kref_hmm_bo_release(struct kref *kref) +{ + if (!kref) + return; + + hmm_bo_release(kref_to_hmm_bo(kref)); +} + +void hmm_bo_unref(struct hmm_buffer_object *bo) +{ + check_bo_null_return_void(bo); + + kref_put(&bo->kref, kref_hmm_bo_release); +} + +static void hmm_bo_vm_open(struct vm_area_struct *vma) +{ + struct hmm_buffer_object *bo = + (struct hmm_buffer_object *)vma->vm_private_data; + + check_bo_null_return_void(bo); + + hmm_bo_ref(bo); + + mutex_lock(&bo->mutex); + + bo->status |= HMM_BO_MMAPED; + + bo->mmap_count++; + + mutex_unlock(&bo->mutex); +} + +static void hmm_bo_vm_close(struct vm_area_struct *vma) +{ + struct hmm_buffer_object *bo = + (struct hmm_buffer_object *)vma->vm_private_data; + + check_bo_null_return_void(bo); + + hmm_bo_unref(bo); + + mutex_lock(&bo->mutex); + + bo->mmap_count--; + + if (!bo->mmap_count) { + bo->status &= (~HMM_BO_MMAPED); + vma->vm_private_data = NULL; + } + + mutex_unlock(&bo->mutex); +} + +static const struct vm_operations_struct hmm_bo_vm_ops = { + .open = hmm_bo_vm_open, + .close = hmm_bo_vm_close, +}; + +/* + * mmap the bo to user space. + */ +int hmm_bo_mmap(struct vm_area_struct *vma, struct hmm_buffer_object *bo) +{ + unsigned int start, end; + unsigned int virt; + unsigned int pgnr, i; + unsigned int pfn; + + check_bo_null_return(bo, -EINVAL); + + check_bo_status_yes_goto(bo, HMM_BO_PAGE_ALLOCED, status_err); + + pgnr = bo->pgnr; + start = vma->vm_start; + end = vma->vm_end; + + /* + * check vma's virtual address space size and buffer object's size. + * must be the same. + */ + if ((start + pgnr_to_size(pgnr)) != end) { + dev_warn(atomisp_dev, + "vma's address space size not equal" + " to buffer object's size"); + return -EINVAL; + } + + virt = vma->vm_start; + for (i = 0; i < pgnr; i++) { + pfn = page_to_pfn(bo->page_obj[i].page); + if (remap_pfn_range(vma, virt, pfn, PAGE_SIZE, PAGE_SHARED)) { + dev_warn(atomisp_dev, + "remap_pfn_range failed:" + " virt = 0x%x, pfn = 0x%x," + " mapped_pgnr = %d\n", virt, pfn, 1); + return -EINVAL; + } + virt += PAGE_SIZE; + } + + vma->vm_private_data = bo; + + vma->vm_ops = &hmm_bo_vm_ops; + vma->vm_flags |= VM_IO|VM_DONTEXPAND|VM_DONTDUMP; + + /* + * call hmm_bo_vm_open explictly. + */ + hmm_bo_vm_open(vma); + + return 0; + +status_err: + dev_err(atomisp_dev, "buffer page not allocated yet.\n"); + return -EINVAL; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/hmm/hmm_bo_dev.c b/drivers/staging/media/atomisp/pci/atomisp2/hmm/hmm_bo_dev.c new file mode 100644 index 0000000000000000000000000000000000000000..87090cea5b9d02a16c6d1671cb1715a5ca885fe3 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/hmm/hmm_bo_dev.c @@ -0,0 +1,333 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include +#include +#include +#include /* for GFP_ATOMIC */ +#include /* for kmalloc */ +#include +#include +#include +#include +#include + +#ifdef CONFIG_ION +#include +#endif + +#include "atomisp_internal.h" +#include "hmm/hmm_common.h" +#include "hmm/hmm_bo_dev.h" +#include "hmm/hmm_bo.h" + +/* + * hmm_bo_device functions. + */ +int hmm_bo_device_init(struct hmm_bo_device *bdev, + struct isp_mmu_client *mmu_driver, + unsigned int vaddr_start, unsigned int size) +{ + int ret; + + check_bodev_null_return(bdev, -EINVAL); + + ret = isp_mmu_init(&bdev->mmu, mmu_driver); + if (ret) { + dev_err(atomisp_dev, "isp_mmu_init failed.\n"); + goto isp_mmu_init_err; + } + + ret = hmm_vm_init(&bdev->vaddr_space, vaddr_start, size); + if (ret) { + dev_err(atomisp_dev, "hmm_vm_init falied. vaddr_start = 0x%x, size = %d\n", + vaddr_start, size); + goto vm_init_err; + } + + INIT_LIST_HEAD(&bdev->free_bo_list); + INIT_LIST_HEAD(&bdev->active_bo_list); + + spin_lock_init(&bdev->list_lock); +#ifdef CONFIG_ION + /* + * TODO: + * The ion_dev should be defined by ION driver. But ION driver does + * not implement it yet, will fix it when it is ready. + */ + if (!ion_dev) + goto vm_init_err; + + bdev->iclient = ion_client_create(ion_dev, "atomisp"); + if (IS_ERR_OR_NULL(bdev->iclient)) { + ret = PTR_ERR(bdev->iclient); + if (!bdev->iclient) + ret = -EINVAL; + goto vm_init_err; + } +#endif + bdev->flag = HMM_BO_DEVICE_INITED; + + return 0; + +vm_init_err: + isp_mmu_exit(&bdev->mmu); +isp_mmu_init_err: + return ret; +} + +void hmm_bo_device_exit(struct hmm_bo_device *bdev) +{ + check_bodev_null_return_void(bdev); + + /* + * destroy all bos in the bo list, even they are in use. + */ + if (!list_empty(&bdev->active_bo_list)) + dev_warn(atomisp_dev, + "there're still activated bo in use. " + "force to free them.\n"); + + while (!list_empty(&bdev->active_bo_list)) + hmm_bo_unref(list_to_hmm_bo(bdev->active_bo_list.next)); + + if (!list_empty(&bdev->free_bo_list)) + dev_warn(atomisp_dev, + "there're still bo in free_bo_list. " + "force to free them.\n"); + + while (!list_empty(&bdev->free_bo_list)) + hmm_bo_unref(list_to_hmm_bo(bdev->free_bo_list.next)); + + isp_mmu_exit(&bdev->mmu); + hmm_vm_clean(&bdev->vaddr_space); +#ifdef CONFIG_ION + if (bdev->iclient != NULL) + ion_client_destroy(bdev->iclient); +#endif +} + +int hmm_bo_device_inited(struct hmm_bo_device *bdev) +{ + check_bodev_null_return(bdev, -EINVAL); + + return bdev->flag == HMM_BO_DEVICE_INITED; +} + +/* + * find the buffer object with virtual address vaddr. + * return NULL if no such buffer object found. + */ +struct hmm_buffer_object *hmm_bo_device_search_start(struct hmm_bo_device *bdev, + ia_css_ptr vaddr) +{ + struct list_head *pos; + struct hmm_buffer_object *bo; + unsigned long flags; + + check_bodev_null_return(bdev, NULL); + + spin_lock_irqsave(&bdev->list_lock, flags); + list_for_each(pos, &bdev->active_bo_list) { + bo = list_to_hmm_bo(pos); + /* pass bo which has no vm_node allocated */ + if (!hmm_bo_vm_allocated(bo)) + continue; + if (bo->vm_node->start == vaddr) + goto found; + } + spin_unlock_irqrestore(&bdev->list_lock, flags); + return NULL; +found: + spin_unlock_irqrestore(&bdev->list_lock, flags); + return bo; +} + +static int in_range(unsigned int start, unsigned int size, unsigned int addr) +{ + return (start <= addr) && (start + size > addr); +} + +struct hmm_buffer_object *hmm_bo_device_search_in_range(struct hmm_bo_device + *bdev, + unsigned int vaddr) +{ + struct list_head *pos; + struct hmm_buffer_object *bo; + unsigned long flags; + int cnt = 0; + + check_bodev_null_return(bdev, NULL); + + spin_lock_irqsave(&bdev->list_lock, flags); + list_for_each(pos, &bdev->active_bo_list) { + cnt++; + bo = list_to_hmm_bo(pos); + /* pass bo which has no vm_node allocated */ + if (!hmm_bo_vm_allocated(bo)) + continue; + if (in_range(bo->vm_node->start, bo->vm_node->size, vaddr)) + goto found; + } + spin_unlock_irqrestore(&bdev->list_lock, flags); + return NULL; +found: + if (cnt > HMM_BO_CACHE_SIZE) + list_move(pos, &bdev->active_bo_list); + spin_unlock_irqrestore(&bdev->list_lock, flags); + return bo; +} + +struct hmm_buffer_object * +hmm_bo_device_search_vmap_start(struct hmm_bo_device *bdev, const void *vaddr) +{ + struct list_head *pos; + struct hmm_buffer_object *bo; + unsigned long flags; + + check_bodev_null_return(bdev, NULL); + + spin_lock_irqsave(&bdev->list_lock, flags); + list_for_each(pos, &bdev->active_bo_list) { + bo = list_to_hmm_bo(pos); + /* pass bo which has no vm_node allocated */ + if (!hmm_bo_vm_allocated(bo)) + continue; + if (bo->vmap_addr == vaddr) + goto found; + } + spin_unlock_irqrestore(&bdev->list_lock, flags); + return NULL; +found: + spin_unlock_irqrestore(&bdev->list_lock, flags); + return bo; +} + +/* + * find a buffer object with pgnr pages from free_bo_list and + * activate it (remove from free_bo_list and add to + * active_bo_list) + * + * return NULL if no such buffer object found. + */ +struct hmm_buffer_object *hmm_bo_device_get_bo(struct hmm_bo_device *bdev, + unsigned int pgnr) +{ + struct list_head *pos; + struct hmm_buffer_object *bo; + unsigned long flags; + + check_bodev_null_return(bdev, NULL); + + spin_lock_irqsave(&bdev->list_lock, flags); + list_for_each(pos, &bdev->free_bo_list) { + bo = list_to_hmm_bo(pos); + if (bo->pgnr == pgnr) + goto found; + } + spin_unlock_irqrestore(&bdev->list_lock, flags); + return NULL; +found: + list_del(&bo->list); + list_add(&bo->list, &bdev->active_bo_list); + spin_unlock_irqrestore(&bdev->list_lock, flags); + + return bo; +} + +/* + * destroy all buffer objects in the free_bo_list. + */ +void hmm_bo_device_destroy_free_bo_list(struct hmm_bo_device *bdev) +{ + struct hmm_buffer_object *bo, *tmp; + unsigned long flags; + struct list_head new_head; + + check_bodev_null_return_void(bdev); + + spin_lock_irqsave(&bdev->list_lock, flags); + list_replace_init(&bdev->free_bo_list, &new_head); + spin_unlock_irqrestore(&bdev->list_lock, flags); + + list_for_each_entry_safe(bo, tmp, &new_head, list) { + list_del(&bo->list); + hmm_bo_unref(bo); + } +} + +/* + * destroy buffer object with start virtual address vaddr. + */ +void hmm_bo_device_destroy_free_bo_addr(struct hmm_bo_device *bdev, + unsigned int vaddr) +{ + struct list_head *pos; + struct hmm_buffer_object *bo; + unsigned long flags; + + check_bodev_null_return_void(bdev); + + spin_lock_irqsave(&bdev->list_lock, flags); + list_for_each(pos, &bdev->free_bo_list) { + bo = list_to_hmm_bo(pos); + /* pass bo which has no vm_node allocated */ + if (!hmm_bo_vm_allocated(bo)) + continue; + if (bo->vm_node->start == vaddr) + goto found; + } + spin_unlock_irqrestore(&bdev->list_lock, flags); + return; +found: + list_del(&bo->list); + spin_unlock_irqrestore(&bdev->list_lock, flags); + hmm_bo_unref(bo); +} + +/* + * destroy all buffer objects with pgnr pages. + */ +void hmm_bo_device_destroy_free_bo_size(struct hmm_bo_device *bdev, + unsigned int pgnr) +{ + struct list_head *pos; + struct hmm_buffer_object *bo; + unsigned long flags; + + check_bodev_null_return_void(bdev); + +retry: + spin_lock_irqsave(&bdev->list_lock, flags); + list_for_each(pos, &bdev->free_bo_list) { + bo = list_to_hmm_bo(pos); + if (bo->pgnr == pgnr) + goto found; + } + spin_unlock_irqrestore(&bdev->list_lock, flags); + return; +found: + list_del(&bo->list); + spin_unlock_irqrestore(&bdev->list_lock, flags); + hmm_bo_unref(bo); + goto retry; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/hmm/hmm_dynamic_pool.c b/drivers/staging/media/atomisp/pci/atomisp2/hmm/hmm_dynamic_pool.c new file mode 100644 index 0000000000000000000000000000000000000000..f1ebc355ec72309d91b55774f16590714d85d814 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/hmm/hmm_dynamic_pool.c @@ -0,0 +1,257 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +/* + * This file contains functions for dynamic memory pool management + */ +#include +#include +#include + +#include "asm/cacheflush.h" + +#include "atomisp_internal.h" + +#include "hmm/hmm_pool.h" + +/* + * dynamic memory pool ops. + */ +static unsigned int get_pages_from_dynamic_pool(void *pool, + struct hmm_page_object *page_obj, + unsigned int size, bool cached) +{ + struct hmm_page *hmm_page; + unsigned long flags; + unsigned int i = 0; + struct hmm_dynamic_pool_info *dypool_info = pool; + + if (!dypool_info) + return 0; + + spin_lock_irqsave(&dypool_info->list_lock, flags); + if (dypool_info->initialized) { + while (!list_empty(&dypool_info->pages_list)) { + hmm_page = list_entry(dypool_info->pages_list.next, + struct hmm_page, list); + + list_del(&hmm_page->list); + dypool_info->pgnr--; + spin_unlock_irqrestore(&dypool_info->list_lock, flags); + + page_obj[i].page = hmm_page->page; + page_obj[i++].type = HMM_PAGE_TYPE_DYNAMIC; +#ifdef USE_KMEM_CACHE + kmem_cache_free(dypool_info->pgptr_cache, hmm_page); +#else + atomisp_kernel_free(hmm_page); +#endif + + if (i == size) + return i; + + spin_lock_irqsave(&dypool_info->list_lock, flags); + } + } + spin_unlock_irqrestore(&dypool_info->list_lock, flags); + + return i; +} + +static void free_pages_to_dynamic_pool(void *pool, + struct hmm_page_object *page_obj) +{ + struct hmm_page *hmm_page; + unsigned long flags; + int ret; + struct hmm_dynamic_pool_info *dypool_info = pool; + + if (!dypool_info) + return; + + spin_lock_irqsave(&dypool_info->list_lock, flags); + if (!dypool_info->initialized) { + spin_unlock_irqrestore(&dypool_info->list_lock, flags); + return; + } + spin_unlock_irqrestore(&dypool_info->list_lock, flags); + + if (page_obj->type == HMM_PAGE_TYPE_RESERVED) + return; + + if (dypool_info->pgnr >= dypool_info->pool_size) { + /* free page directly back to system */ + ret = set_pages_wb(page_obj->page, 1); + if (ret) + dev_err(atomisp_dev, + "set page to WB err ...ret=%d\n", ret); + /* + W/A: set_pages_wb seldom return value = -EFAULT + indicate that address of page is not in valid + range(0xffff880000000000~0xffffc7ffffffffff) + then, _free_pages would panic; Do not know why page + address be valid, it maybe memory corruption by lowmemory + */ + if (!ret) { + __free_pages(page_obj->page, 0); + hmm_mem_stat.sys_size--; + } + return; + } +#ifdef USE_KMEM_CACHE + hmm_page = kmem_cache_zalloc(dypool_info->pgptr_cache, + GFP_KERNEL); +#else + hmm_page = atomisp_kernel_malloc(sizeof(struct hmm_page)); +#endif + if (!hmm_page) { + dev_err(atomisp_dev, "out of memory for hmm_page.\n"); + + /* free page directly */ + ret = set_pages_wb(page_obj->page, 1); + if (ret) + dev_err(atomisp_dev, + "set page to WB err ...ret=%d\n", ret); + if (!ret) { + __free_pages(page_obj->page, 0); + hmm_mem_stat.sys_size--; + } + return; + } + + hmm_page->page = page_obj->page; + + /* + * add to pages_list of pages_pool + */ + spin_lock_irqsave(&dypool_info->list_lock, flags); + list_add_tail(&hmm_page->list, &dypool_info->pages_list); + dypool_info->pgnr++; + spin_unlock_irqrestore(&dypool_info->list_lock, flags); + hmm_mem_stat.dyc_size++; +} + +static int hmm_dynamic_pool_init(void **pool, unsigned int pool_size) +{ + struct hmm_dynamic_pool_info *dypool_info; + + if (pool_size == 0) + return 0; + + dypool_info = atomisp_kernel_malloc( + sizeof(struct hmm_dynamic_pool_info)); + if (unlikely(!dypool_info)) { + dev_err(atomisp_dev, "out of memory for repool_info.\n"); + return -ENOMEM; + } + +#ifdef USE_KMEM_CACHE + dypool_info->pgptr_cache = kmem_cache_create("pgptr_cache", + sizeof(struct hmm_page), 0, + SLAB_HWCACHE_ALIGN, NULL); + if (!dypool_info->pgptr_cache) { + atomisp_kernel_free(dypool_info); + return -ENOMEM; + } +#endif + + INIT_LIST_HEAD(&dypool_info->pages_list); + spin_lock_init(&dypool_info->list_lock); + dypool_info->initialized = true; + dypool_info->pool_size = pool_size; + dypool_info->pgnr = 0; + + *pool = dypool_info; + + return 0; +} + +static void hmm_dynamic_pool_exit(void **pool) +{ + struct hmm_dynamic_pool_info *dypool_info = *pool; + struct hmm_page *hmm_page; + unsigned long flags; + int ret; + + if (!dypool_info) + return; + + spin_lock_irqsave(&dypool_info->list_lock, flags); + if (!dypool_info->initialized) { + spin_unlock_irqrestore(&dypool_info->list_lock, flags); + return; + } + dypool_info->initialized = false; + + while (!list_empty(&dypool_info->pages_list)) { + hmm_page = list_entry(dypool_info->pages_list.next, + struct hmm_page, list); + + list_del(&hmm_page->list); + spin_unlock_irqrestore(&dypool_info->list_lock, flags); + + /* can cause thread sleep, so cannot be put into spin_lock */ + ret = set_pages_wb(hmm_page->page, 1); + if (ret) + dev_err(atomisp_dev, + "set page to WB err...ret=%d\n", ret); + if (!ret) { + __free_pages(hmm_page->page, 0); + hmm_mem_stat.dyc_size--; + hmm_mem_stat.sys_size--; + } +#ifdef USE_KMEM_CACHE + kmem_cache_free(dypool_info->pgptr_cache, hmm_page); +#else + atomisp_kernel_free(hmm_page); +#endif + spin_lock_irqsave(&dypool_info->list_lock, flags); + } + + spin_unlock_irqrestore(&dypool_info->list_lock, flags); + +#ifdef USE_KMEM_CACHE + kmem_cache_destroy(dypool_info->pgptr_cache); +#endif + + atomisp_kernel_free(dypool_info); + + *pool = NULL; +} + +static int hmm_dynamic_pool_inited(void *pool) +{ + struct hmm_dynamic_pool_info *dypool_info = pool; + + if (!dypool_info) + return 0; + + return dypool_info->initialized; +} + +struct hmm_pool_ops dynamic_pops = { + .pool_init = hmm_dynamic_pool_init, + .pool_exit = hmm_dynamic_pool_exit, + .pool_alloc_pages = get_pages_from_dynamic_pool, + .pool_free_pages = free_pages_to_dynamic_pool, + .pool_inited = hmm_dynamic_pool_inited, +}; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/hmm/hmm_reserved_pool.c b/drivers/staging/media/atomisp/pci/atomisp2/hmm/hmm_reserved_pool.c new file mode 100644 index 0000000000000000000000000000000000000000..590ff7bc6c5f1ffc4fb40695d89da6e4961b434a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/hmm/hmm_reserved_pool.c @@ -0,0 +1,258 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +/* + * This file contains functions for reserved memory pool management + */ +#include +#include +#include + +#include "asm/cacheflush.h" +#include "atomisp_internal.h" +#include "hmm/hmm_pool.h" + +/* + * reserved memory pool ops. + */ +static unsigned int get_pages_from_reserved_pool(void *pool, + struct hmm_page_object *page_obj, + unsigned int size, bool cached) +{ + unsigned long flags; + unsigned int i = 0; + unsigned int repool_pgnr; + int j; + struct hmm_reserved_pool_info *repool_info = pool; + + if (!repool_info) + return 0; + + spin_lock_irqsave(&repool_info->list_lock, flags); + if (repool_info->initialized) { + repool_pgnr = repool_info->index; + + for (j = repool_pgnr-1; j >= 0; j--) { + page_obj[i].page = repool_info->pages[j]; + page_obj[i].type = HMM_PAGE_TYPE_RESERVED; + i++; + repool_info->index--; + if (i == size) + break; + } + } + spin_unlock_irqrestore(&repool_info->list_lock, flags); + return i; +} + +static void free_pages_to_reserved_pool(void *pool, + struct hmm_page_object *page_obj) +{ + unsigned long flags; + struct hmm_reserved_pool_info *repool_info = pool; + + if (!repool_info) + return; + + spin_lock_irqsave(&repool_info->list_lock, flags); + + if (repool_info->initialized && + repool_info->index < repool_info->pgnr && + page_obj->type == HMM_PAGE_TYPE_RESERVED) { + repool_info->pages[repool_info->index++] = page_obj->page; + } + + spin_unlock_irqrestore(&repool_info->list_lock, flags); +} + +static int hmm_reserved_pool_setup(struct hmm_reserved_pool_info **repool_info, + unsigned int pool_size) +{ + struct hmm_reserved_pool_info *pool_info; + + pool_info = atomisp_kernel_malloc( + sizeof(struct hmm_reserved_pool_info)); + if (unlikely(!pool_info)) { + dev_err(atomisp_dev, "out of memory for repool_info.\n"); + return -ENOMEM; + } + + pool_info->pages = atomisp_kernel_malloc( + sizeof(struct page *) * pool_size); + if (unlikely(!pool_info->pages)) { + dev_err(atomisp_dev, "out of memory for repool_info->pages.\n"); + atomisp_kernel_free(pool_info); + return -ENOMEM; + } + + pool_info->index = 0; + pool_info->pgnr = 0; + spin_lock_init(&pool_info->list_lock); + pool_info->initialized = true; + + *repool_info = pool_info; + + return 0; +} + +static int hmm_reserved_pool_init(void **pool, unsigned int pool_size) +{ + int ret; + unsigned int blk_pgnr; + unsigned int pgnr = pool_size; + unsigned int order = 0; + unsigned int i = 0; + int fail_number = 0; + struct page *pages; + int j; + struct hmm_reserved_pool_info *repool_info; + if (pool_size == 0) + return 0; + + ret = hmm_reserved_pool_setup(&repool_info, pool_size); + if (ret) { + dev_err(atomisp_dev, "hmm_reserved_pool_setup failed.\n"); + return ret; + } + + pgnr = pool_size; + + i = 0; + order = MAX_ORDER; + + while (pgnr) { + blk_pgnr = 1U << order; + while (blk_pgnr > pgnr) { + order--; + blk_pgnr >>= 1U; + } + BUG_ON(order > MAX_ORDER); + + pages = alloc_pages(GFP_KERNEL | __GFP_NOWARN, order); + if (unlikely(!pages)) { + if (order == 0) { + fail_number++; + dev_err(atomisp_dev, "%s: alloc_pages failed: %d\n", + __func__, fail_number); + /* if fail five times, will goto end */ + + /* FIXME: whether is the mechanism is ok? */ + if (fail_number == ALLOC_PAGE_FAIL_NUM) + goto end; + } else { + order--; + } + } else { + blk_pgnr = 1U << order; + + ret = set_pages_uc(pages, blk_pgnr); + if (ret) { + dev_err(atomisp_dev, + "set pages uncached failed\n"); + __free_pages(pages, order); + goto end; + } + + for (j = 0; j < blk_pgnr; j++) + repool_info->pages[i++] = pages + j; + + repool_info->index += blk_pgnr; + repool_info->pgnr += blk_pgnr; + + pgnr -= blk_pgnr; + + fail_number = 0; + } + } + +end: + repool_info->initialized = true; + + *pool = repool_info; + + dev_info(atomisp_dev, + "hmm_reserved_pool init successfully," + "hmm_reserved_pool is with %d pages.\n", + repool_info->pgnr); + return 0; +} + +static void hmm_reserved_pool_exit(void **pool) +{ + unsigned long flags; + int i, ret; + unsigned int pgnr; + struct hmm_reserved_pool_info *repool_info = *pool; + + if (!repool_info) + return; + + spin_lock_irqsave(&repool_info->list_lock, flags); + if (!repool_info->initialized) { + spin_unlock_irqrestore(&repool_info->list_lock, flags); + return; + } + pgnr = repool_info->pgnr; + repool_info->index = 0; + repool_info->pgnr = 0; + repool_info->initialized = false; + spin_unlock_irqrestore(&repool_info->list_lock, flags); + + for (i = 0; i < pgnr; i++) { + ret = set_pages_wb(repool_info->pages[i], 1); + if (ret) + dev_err(atomisp_dev, + "set page to WB err...ret=%d\n", ret); + /* + W/A: set_pages_wb seldom return value = -EFAULT + indicate that address of page is not in valid + range(0xffff880000000000~0xffffc7ffffffffff) + then, _free_pages would panic; Do not know why + page address be valid, it maybe memory corruption by lowmemory + */ + if (!ret) + __free_pages(repool_info->pages[i], 0); + } + + atomisp_kernel_free(repool_info->pages); + atomisp_kernel_free(repool_info); + + *pool = NULL; +} + +static int hmm_reserved_pool_inited(void *pool) +{ + struct hmm_reserved_pool_info *repool_info = pool; + + if (!repool_info) + return 0; + + return repool_info->initialized; +} + +struct hmm_pool_ops reserved_pops = { + .pool_init = hmm_reserved_pool_init, + .pool_exit = hmm_reserved_pool_exit, + .pool_alloc_pages = get_pages_from_reserved_pool, + .pool_free_pages = free_pages_to_reserved_pool, + .pool_inited = hmm_reserved_pool_inited, +}; diff --git a/drivers/staging/media/atomisp/pci/atomisp2/hmm/hmm_vm.c b/drivers/staging/media/atomisp/pci/atomisp2/hmm/hmm_vm.c new file mode 100644 index 0000000000000000000000000000000000000000..0722a68a49e7f6c5329e46be00d5206c3e8552aa --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/hmm/hmm_vm.c @@ -0,0 +1,218 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +/* + * This file contains function for ISP virtual address management in ISP driver + */ +#include +#include +#include +#include +#include + +#include "atomisp_internal.h" +#include "mmu/isp_mmu.h" +#include "hmm/hmm_vm.h" +#include "hmm/hmm_common.h" + +static unsigned int vm_node_end(unsigned int start, unsigned int pgnr) +{ + return start + pgnr_to_size(pgnr); +} + +static int addr_in_vm_node(unsigned int addr, + struct hmm_vm_node *node) +{ + return (addr >= node->start) && (addr < (node->start + node->size)); +} + +int hmm_vm_init(struct hmm_vm *vm, unsigned int start, + unsigned int size) +{ + if (!vm) + return -1; + + vm->start = start; + vm->pgnr = size_to_pgnr_ceil(size); + vm->size = pgnr_to_size(vm->pgnr); + + INIT_LIST_HEAD(&vm->vm_node_list); + spin_lock_init(&vm->lock); + vm->cache = kmem_cache_create("atomisp_vm", sizeof(struct hmm_vm_node), + 0, 0, NULL); + + return vm->cache != NULL ? 0 : -ENOMEM; +} + +void hmm_vm_clean(struct hmm_vm *vm) +{ + struct hmm_vm_node *node, *tmp; + struct list_head new_head; + + if (!vm) + return; + + spin_lock(&vm->lock); + list_replace_init(&vm->vm_node_list, &new_head); + spin_unlock(&vm->lock); + + list_for_each_entry_safe(node, tmp, &new_head, list) { + list_del(&node->list); + kmem_cache_free(vm->cache, node); + } + + kmem_cache_destroy(vm->cache); +} + +static struct hmm_vm_node *alloc_hmm_vm_node(unsigned int pgnr, + struct hmm_vm *vm) +{ + struct hmm_vm_node *node; + + node = kmem_cache_alloc(vm->cache, GFP_KERNEL); + if (!node) { + dev_err(atomisp_dev, "out of memory.\n"); + return NULL; + } + + INIT_LIST_HEAD(&node->list); + node->pgnr = pgnr; + node->size = pgnr_to_size(pgnr); + node->vm = vm; + + return node; +} + +struct hmm_vm_node *hmm_vm_alloc_node(struct hmm_vm *vm, unsigned int pgnr) +{ + struct list_head *head; + struct hmm_vm_node *node, *cur, *next; + unsigned int vm_start, vm_end; + unsigned int addr; + unsigned int size; + + if (!vm) + return NULL; + + vm_start = vm->start; + vm_end = vm_node_end(vm->start, vm->pgnr); + size = pgnr_to_size(pgnr); + + addr = vm_start; + head = &vm->vm_node_list; + + node = alloc_hmm_vm_node(pgnr, vm); + if (!node) { + dev_err(atomisp_dev, "no memory to allocate hmm vm node.\n"); + return NULL; + } + + spin_lock(&vm->lock); + /* + * if list is empty, the loop code will not be executed. + */ + list_for_each_entry(cur, head, list) { + /* Add gap between vm areas as helper to not hide overflow */ + addr = PAGE_ALIGN(vm_node_end(cur->start, cur->pgnr) + 1); + + if (list_is_last(&cur->list, head)) { + if (addr + size > vm_end) { + /* vm area does not have space anymore */ + spin_unlock(&vm->lock); + kmem_cache_free(vm->cache, node); + dev_err(atomisp_dev, + "no enough virtual address space.\n"); + return NULL; + } + + /* We still have vm space to add new node to tail */ + break; + } + + next = list_entry(cur->list.next, struct hmm_vm_node, list); + if ((next->start - addr) > size) + break; + } + node->start = addr; + node->vm = vm; + list_add(&node->list, &cur->list); + spin_unlock(&vm->lock); + + return node; +} + +void hmm_vm_free_node(struct hmm_vm_node *node) +{ + struct hmm_vm *vm; + + if (!node) + return; + + vm = node->vm; + + spin_lock(&vm->lock); + list_del(&node->list); + spin_unlock(&vm->lock); + + kmem_cache_free(vm->cache, node); +} + +struct hmm_vm_node *hmm_vm_find_node_start(struct hmm_vm *vm, unsigned int addr) +{ + struct hmm_vm_node *node; + + if (!vm) + return NULL; + + spin_lock(&vm->lock); + + list_for_each_entry(node, &vm->vm_node_list, list) { + if (node->start == addr) { + spin_unlock(&vm->lock); + return node; + } + } + + spin_unlock(&vm->lock); + return NULL; +} + +struct hmm_vm_node *hmm_vm_find_node_in_range(struct hmm_vm *vm, + unsigned int addr) +{ + struct hmm_vm_node *node; + + if (!vm) + return NULL; + + spin_lock(&vm->lock); + + list_for_each_entry(node, &vm->vm_node_list, list) { + if (addr_in_vm_node(addr, node)) { + spin_unlock(&vm->lock); + return node; + } + } + + spin_unlock(&vm->lock); + return NULL; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/hrt/device_access.c b/drivers/staging/media/atomisp/pci/atomisp2/hrt/device_access.c new file mode 100644 index 0000000000000000000000000000000000000000..1e1ac99a3972a83e4df67fdb8e071fea9a1cc5ee --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/hrt/device_access.c @@ -0,0 +1,127 @@ + +#include "device_access.h" + +#include "assert_support.h" + +#include /* hrt_master_port_load() */ +#ifdef C_RUN +#include /* memcpy() */ +#endif + +/* + * This is an HRT backend implementation for CSIM + */ + +static sys_address base_address = (sys_address)-1; + +void device_set_base_address( + const sys_address base_addr) +{ + base_address = base_addr; +return; +} + + +sys_address device_get_base_address(void) +{ +return base_address; +} + +uint8_t device_load_uint8( + const hrt_address addr) +{ +assert(base_address != (sys_address)-1); +return hrt_master_port_uload_8(base_address + addr); +} + +uint16_t device_load_uint16( + const hrt_address addr) +{ +assert(base_address != (sys_address)-1); +assert((addr & 0x01) == 0); +return hrt_master_port_uload_16(base_address + addr); +} + +uint32_t device_load_uint32( + const hrt_address addr) +{ +assert(base_address != (sys_address)-1); +assert((addr & 0x03) == 0); +return hrt_master_port_uload_32(base_address + addr); +} + +uint64_t device_load_uint64( + const hrt_address addr) +{ +assert(base_address != (sys_address)-1); +assert((addr & 0x07) == 0); +assert(0); +return 0; +} + +void device_store_uint8( + const hrt_address addr, + const uint8_t data) +{ +assert(base_address != (sys_address)-1); +hrt_master_port_store_8(base_address + addr, data); +return; +} + +void device_store_uint16( + const hrt_address addr, + const uint16_t data) +{ +assert(base_address != (sys_address)-1); +assert((addr & 0x01) == 0); +hrt_master_port_store_16(base_address + addr, data); +return; +} + +void device_store_uint32( + const hrt_address addr, + const uint32_t data) +{ +assert(base_address != (sys_address)-1); +assert((addr & 0x03) == 0); +hrt_master_port_store_32(base_address + addr, data); +return; +} + +void device_store_uint64( + const hrt_address addr, + const uint64_t data) +{ +assert(base_address != (sys_address)-1); +assert((addr & 0x07) == 0); +assert(0); +(void)data; +return; +} + +void device_load( + const hrt_address addr, + void *data, + const size_t size) +{ +assert(base_address != (sys_address)-1); +#ifndef C_RUN + hrt_master_port_load((uint32_t)(base_address + addr), data, size); +#else + memcpy(data, (void *)addr, size); +#endif +} + +void device_store( + const hrt_address addr, + const void *data, + const size_t size) +{ +assert(base_address != (sys_address)-1); +#ifndef C_RUN + hrt_master_port_store((uint32_t)(base_address + addr), data, size); +#else + memcpy((void *)addr, data, size); +#endif +return; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/hrt/hive_isp_css_custom_host_hrt.h b/drivers/staging/media/atomisp/pci/atomisp2/hrt/hive_isp_css_custom_host_hrt.h new file mode 100644 index 0000000000000000000000000000000000000000..46a5d29e2d3acf4eead0faf785b1250494e3c07e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/hrt/hive_isp_css_custom_host_hrt.h @@ -0,0 +1,107 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#ifndef _hive_isp_css_custom_host_hrt_h_ +#define _hive_isp_css_custom_host_hrt_h_ + +#include +#include "atomisp_helper.h" + +/* + * _hrt_master_port_store/load/uload -macros using __force attributed + * cast to intentional dereferencing __iomem attributed (noderef) + * pointer from atomisp_get_io_virt_addr + */ +#define _hrt_master_port_store_8(a, d) \ + (*((s8 __force *)atomisp_get_io_virt_addr(a)) = (d)) + +#define _hrt_master_port_store_16(a, d) \ + (*((s16 __force *)atomisp_get_io_virt_addr(a)) = (d)) + +#define _hrt_master_port_store_32(a, d) \ + (*((s32 __force *)atomisp_get_io_virt_addr(a)) = (d)) + +#define _hrt_master_port_load_8(a) \ + (*(s8 __force *)atomisp_get_io_virt_addr(a)) + +#define _hrt_master_port_load_16(a) \ + (*(s16 __force *)atomisp_get_io_virt_addr(a)) + +#define _hrt_master_port_load_32(a) \ + (*(s32 __force *)atomisp_get_io_virt_addr(a)) + +#define _hrt_master_port_uload_8(a) \ + (*(u8 __force *)atomisp_get_io_virt_addr(a)) + +#define _hrt_master_port_uload_16(a) \ + (*(u16 __force *)atomisp_get_io_virt_addr(a)) + +#define _hrt_master_port_uload_32(a) \ + (*(u32 __force *)atomisp_get_io_virt_addr(a)) + +#define _hrt_master_port_store_8_volatile(a, d) _hrt_master_port_store_8(a, d) +#define _hrt_master_port_store_16_volatile(a, d) _hrt_master_port_store_16(a, d) +#define _hrt_master_port_store_32_volatile(a, d) _hrt_master_port_store_32(a, d) + +#define _hrt_master_port_load_8_volatile(a) _hrt_master_port_load_8(a) +#define _hrt_master_port_load_16_volatile(a) _hrt_master_port_load_16(a) +#define _hrt_master_port_load_32_volatile(a) _hrt_master_port_load_32(a) + +#define _hrt_master_port_uload_8_volatile(a) _hrt_master_port_uload_8(a) +#define _hrt_master_port_uload_16_volatile(a) _hrt_master_port_uload_16(a) +#define _hrt_master_port_uload_32_volatile(a) _hrt_master_port_uload_32(a) + +static inline void hrt_sleep(void) +{ + udelay(1); +} + +static inline uint32_t _hrt_mem_store(uint32_t to, const void *from, size_t n) +{ + unsigned i; + uint32_t _to = to; + const char *_from = (const char *)from; + for (i = 0; i < n; i++, _to++, _from++) + _hrt_master_port_store_8(_to, *_from); + return _to; +} + +static inline void *_hrt_mem_load(uint32_t from, void *to, size_t n) +{ + unsigned i; + char *_to = (char *)to; + uint32_t _from = from; + for (i = 0; i < n; i++, _to++, _from++) + *_to = _hrt_master_port_load_8(_from); + return _to; +} + +static inline uint32_t _hrt_mem_set(uint32_t to, int c, size_t n) +{ + unsigned i; + uint32_t _to = to; + for (i = 0; i < n; i++, _to++) + _hrt_master_port_store_8(_to, c); + return _to; +} + +#endif /* _hive_isp_css_custom_host_hrt_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/hrt/hive_isp_css_mm_hrt.c b/drivers/staging/media/atomisp/pci/atomisp2/hrt/hive_isp_css_mm_hrt.c new file mode 100644 index 0000000000000000000000000000000000000000..9f8267ad06b1b5b3751e35ee0f152a94425da91b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/hrt/hive_isp_css_mm_hrt.c @@ -0,0 +1,193 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#include "atomisp_internal.h" + +#include "hive_isp_css_mm_hrt.h" +#include "hmm/hmm.h" + +#define __page_align(size) (((size) + (PAGE_SIZE-1)) & (~(PAGE_SIZE-1))) + +static unsigned init_done; +void hrt_isp_css_mm_init(void) +{ + hmm_init(); + init_done = 1; +} + +int hrt_isp_css_mm_set(ia_css_ptr virt_addr, int c, size_t bytes) +{ + if (virt_addr) + return hmm_set(virt_addr, c, bytes); + + return -EFAULT; +} + +int hrt_isp_css_mm_load(ia_css_ptr virt_addr, void *data, size_t bytes) +{ + if (virt_addr && data) + return hmm_load(virt_addr, data, bytes); + return -EFAULT; +} + +int hrt_isp_css_mm_store(ia_css_ptr virt_addr, const void *data, size_t bytes) +{ + if (virt_addr && data) + return hmm_store(virt_addr, data, bytes); + return -EFAULT; +} + +void hrt_isp_css_mm_free(ia_css_ptr virt_addr) +{ + if (virt_addr) + hmm_free(virt_addr); +} + +void hrt_isp_css_mm_clear(void) +{ + if (init_done) { + hmm_cleanup(); + init_done = 0; + } +} + +static void *my_userptr; +static unsigned my_num_pages; +static enum hrt_userptr_type my_usr_type; + +void hrt_isp_css_mm_set_user_ptr(void *userptr, + unsigned int num_pages, + enum hrt_userptr_type type) +{ + my_userptr = userptr; + my_num_pages = num_pages; + my_usr_type = type; +} + +static ia_css_ptr __hrt_isp_css_mm_alloc(size_t bytes, void *userptr, + unsigned int num_pages, + enum hrt_userptr_type type, + bool cached) +{ + if (!init_done) + hrt_isp_css_mm_init(); +#ifdef CONFIG_ION + if (type == HRT_USR_ION) + return hmm_alloc(bytes, HMM_BO_ION, 0, + userptr, cached); + +#endif + if (type == HRT_USR_PTR) { + if (userptr == NULL) + return hmm_alloc(bytes, HMM_BO_PRIVATE, 0, + 0, cached); + else { + if (num_pages < ((__page_align(bytes)) >> PAGE_SHIFT)) + dev_err(atomisp_dev, + "user space memory size is less" + " than the expected size..\n"); + else if (num_pages > ((__page_align(bytes)) + >> PAGE_SHIFT)) + dev_err(atomisp_dev, + "user space memory size is" + " large than the expected size..\n"); + + return hmm_alloc(bytes, HMM_BO_USER, 0, + userptr, cached); + } + } else { + dev_err(atomisp_dev, "user ptr type is incorrect.\n"); + return 0; + } +} + +ia_css_ptr hrt_isp_css_mm_alloc(size_t bytes) +{ + return __hrt_isp_css_mm_alloc(bytes, my_userptr, + my_num_pages, my_usr_type, false); +} + +ia_css_ptr hrt_isp_css_mm_alloc_user_ptr(size_t bytes, void *userptr, + unsigned int num_pages, + enum hrt_userptr_type type, + bool cached) +{ + return __hrt_isp_css_mm_alloc(bytes, userptr, num_pages, + type, cached); +} + +ia_css_ptr hrt_isp_css_mm_alloc_cached(size_t bytes) +{ + if (!init_done) + hrt_isp_css_mm_init(); + + if (my_userptr == NULL) + return hmm_alloc(bytes, HMM_BO_PRIVATE, 0, 0, + HMM_CACHED); + else { + if (my_num_pages < ((__page_align(bytes)) >> PAGE_SHIFT)) + dev_err(atomisp_dev, + "user space memory size is less" + " than the expected size..\n"); + else if (my_num_pages > ((__page_align(bytes)) >> PAGE_SHIFT)) + dev_err(atomisp_dev, + "user space memory size is" + " large than the expected size..\n"); + + return hmm_alloc(bytes, HMM_BO_USER, 0, + my_userptr, HMM_CACHED); + } +} + +ia_css_ptr hrt_isp_css_mm_calloc(size_t bytes) +{ + ia_css_ptr ptr = hrt_isp_css_mm_alloc(bytes); + if (ptr) + hmm_set(ptr, 0, bytes); + return ptr; +} + +ia_css_ptr hrt_isp_css_mm_calloc_cached(size_t bytes) +{ + ia_css_ptr ptr = hrt_isp_css_mm_alloc_cached(bytes); + if (ptr) + hmm_set(ptr, 0, bytes); + return ptr; +} + +phys_addr_t hrt_isp_css_virt_to_phys(ia_css_ptr virt_addr) +{ + return hmm_virt_to_phys(virt_addr); +} + +ia_css_ptr hrt_isp_css_mm_alloc_contiguous(size_t bytes) +{ + BUG_ON(false); + return 0; +} +ia_css_ptr hrt_isp_css_mm_calloc_contiguous(size_t bytes) +{ + BUG_ON(false); + return 0; +} + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/hrt/hive_isp_css_mm_hrt.h b/drivers/staging/media/atomisp/pci/atomisp2/hrt/hive_isp_css_mm_hrt.h new file mode 100644 index 0000000000000000000000000000000000000000..5363c5a9b1314e0a5166df7774d0cd7e9601ff4b --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/hrt/hive_isp_css_mm_hrt.h @@ -0,0 +1,92 @@ +/* + * Support for Medfield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef _hive_isp_css_mm_hrt_h_ +#define _hive_isp_css_mm_hrt_h_ + +#ifndef HRT_KERNEL +/* size_t is defined already in kernel mode */ +#include +#endif +#include +#include + +#define HRT_BUF_FLAG_CACHED (1 << 0) + +enum hrt_userptr_type { + HRT_USR_PTR = 0, +#ifdef CONFIG_ION + HRT_USR_ION, +#endif +}; + +struct hrt_userbuffer_attr { + enum hrt_userptr_type type; + unsigned int pgnr; +}; + +void hrt_isp_css_mm_init(void); +void hrt_isp_css_mm_set_user_ptr(void *userptr, + unsigned int num_pages, enum hrt_userptr_type); + +int hrt_isp_css_mm_set(ia_css_ptr virt_addr, int c, size_t bytes); + +/* Allocate memory, returns a virtual address */ +ia_css_ptr hrt_isp_css_mm_alloc(size_t bytes); +ia_css_ptr hrt_isp_css_mm_alloc_user_ptr(size_t bytes, void *userptr, + unsigned int num_pages, + enum hrt_userptr_type, + bool cached); +ia_css_ptr hrt_isp_css_mm_alloc_cached(size_t bytes); + +/* allocate memory and initialize with zeros, + returns a virtual address */ +ia_css_ptr hrt_isp_css_mm_calloc(size_t bytes); +ia_css_ptr hrt_isp_css_mm_calloc_cached(size_t bytes); + +/* Free memory, given a virtual address */ +void hrt_isp_css_mm_free(ia_css_ptr virt_addr); + +/* Store data to a virtual address */ +int hrt_isp_css_mm_load(ia_css_ptr virt_addr, void *data, size_t bytes); + +/* Load data from a virtual address */ +int hrt_isp_css_mm_store(ia_css_ptr virt_addr, const void *data, size_t bytes); + +int hrt_isp_css_mm_load_int(ia_css_ptr virt_addr, int *data); +int hrt_isp_css_mm_load_short(ia_css_ptr virt_addr, short *data); +int hrt_isp_css_mm_load_char(ia_css_ptr virt_addr, char *data); + +int hrt_isp_css_mm_store_char(ia_css_ptr virt_addr, char data); +int hrt_isp_css_mm_store_short(ia_css_ptr virt_addr, short data); +int hrt_isp_css_mm_store_int(ia_css_ptr virt_addr, int data); + +/* translate a virtual to a physical address, used to program + the display driver on the FPGA system */ +phys_addr_t hrt_isp_css_virt_to_phys(ia_css_ptr virt_addr); + +ia_css_ptr hrt_isp_css_mm_alloc_contiguous(size_t bytes); +ia_css_ptr hrt_isp_css_mm_calloc_contiguous(size_t bytes); + +void hrt_isp_css_mm_clear(void); +#endif /* _hive_isp_css_mm_hrt_h_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/hrt/memory_access.c b/drivers/staging/media/atomisp/pci/atomisp2/hrt/memory_access.c new file mode 100644 index 0000000000000000000000000000000000000000..362707d8201e6cb2c25767664fe85addc89ed827 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/hrt/memory_access.c @@ -0,0 +1,369 @@ + +#include "memory_access.h" + +#include /* NULL */ +#include + +#include "device_access.h" + +#include "mmu_device.h" + +#include "assert_support.h" + +/* Presently system specific */ +#include +/* Presently system specific */ +#include "hive_isp_css_mm_hrt.h" + +/* + * This is an HRT backend implementation for CSIM + * 31 July 2012, rvanimme: this implementation is also used in Android context + */ + +static sys_address page_table_base_address = (sys_address)-1; + +#ifndef SH_CSS_MEMORY_GUARDING +/* Choose default in case not defined */ +#ifdef HRT_CSIM +#define SH_CSS_MEMORY_GUARDING (1) +#else +#define SH_CSS_MEMORY_GUARDING (0) +#endif +#endif + +#if SH_CSS_MEMORY_GUARDING +#define CEIL_DIV(a, b) ((b) ? ((a)+(b)-1)/(b) : 0) +#define CEIL_MUL(a, b) (CEIL_DIV(a, b) * (b)) +#define DDR_ALIGN(a) (CEIL_MUL((a), (HIVE_ISP_DDR_WORD_BYTES))) + +#define MEM_GUARD_START 0xABBAABBA +#define MEM_GUARD_END 0xBEEFBEEF +#define GUARD_SIZE sizeof(unsigned long) +#define GUARD_SIZE_ALIGNED DDR_ALIGN(GUARD_SIZE) + +#define MAX_ALLOC_ENTRIES (256) +#define INVALID_VBASE ((ia_css_ptr)-1) +#define INVALID_SIZE ((unsigned long)-1) + +struct alloc_info { + ia_css_ptr vbase; + unsigned long size; +}; + +static struct alloc_info alloc_admin[MAX_ALLOC_ENTRIES]; + +static struct alloc_info const alloc_info_invalid + = { INVALID_VBASE, INVALID_SIZE }; + +static void alloc_admin_init(void) +{ + int i; + + for (i = 0; i < MAX_ALLOC_ENTRIES; i++) + alloc_admin[i] = alloc_info_invalid; +} + +static struct alloc_info const *alloc_admin_find(ia_css_ptr vaddr) +{ + int i; + /** + * Note that we use <= instead of < because we like to accept + * zero-sized operations at the last allocated address + * e.g. mmgr_set(vbase+alloc_size, data, 0) + */ + for (i = 0; i < MAX_ALLOC_ENTRIES; i++) { + if (alloc_admin[i].vbase != INVALID_VBASE && + vaddr >= alloc_admin[i].vbase && + vaddr <= alloc_admin[i].vbase + + alloc_admin[i].size) { + return &alloc_admin[i]; + } + } + return &alloc_info_invalid; +} + +static bool mem_guard_valid(ia_css_ptr vaddr, unsigned long size) +{ + unsigned long mem_guard; + struct alloc_info const *info; + + info = alloc_admin_find(vaddr); + if (info->vbase == INVALID_VBASE) { + assert(false); + return false; + } + + /* Check if end is in alloc range*/ + if ((vaddr + size) > (info->vbase + info->size)) { + assert(false); + return false; + } + + hrt_isp_css_mm_load((info->vbase - sizeof(mem_guard)), + &mem_guard, sizeof(mem_guard)); + if (mem_guard != MEM_GUARD_START) { + assert(false); + return false; + } + + hrt_isp_css_mm_load((info->vbase + info->size), + &mem_guard, sizeof(mem_guard)); + if (mem_guard != MEM_GUARD_END) { + assert(false); + return false; + } + + return true; + +} + +static void alloc_admin_add(ia_css_ptr vbase, unsigned long size) +{ + int i; + unsigned long mem_guard; + + assert(alloc_admin_find(vbase)->vbase == INVALID_VBASE); + + mem_guard = MEM_GUARD_START; + hrt_isp_css_mm_store((vbase - sizeof(mem_guard)), + &mem_guard, sizeof(mem_guard)); + + mem_guard = MEM_GUARD_END; + hrt_isp_css_mm_store((vbase + size), + &mem_guard, sizeof(mem_guard)); + + for (i = 0; i < MAX_ALLOC_ENTRIES; i++) { + if (alloc_admin[i].vbase == INVALID_VBASE) { + alloc_admin[i].vbase = vbase; + alloc_admin[i].size = size; + return; + } + } + assert(false); +} + +static void alloc_admin_remove(ia_css_ptr vbase) +{ + int i; + assert(mem_guard_valid(vbase, 0)); + for (i = 0; i < MAX_ALLOC_ENTRIES; i++) { + if (alloc_admin[i].vbase == vbase) { + alloc_admin[i] = alloc_info_invalid; + return; + } + } + assert(false); +} + +#endif + +void mmgr_set_base_address( + const sys_address base_addr) +{ + page_table_base_address = base_addr; + +#if SH_CSS_MEMORY_GUARDING + alloc_admin_init(); +#endif +/* + * This is part of "device_access.h", but it may be + * that "hive_isp_css_mm_hrt.h" requires it + */ +/* hrt_isp_css_mm_set_ddr_address_offset(offset); */ +/* mmu_set_page_table_base_index(MMU0_ID, page_table_base_address); */ +return; +} + +sys_address mmgr_get_base_address(void) +{ +return page_table_base_address; +} + +void mmgr_set_base_index( + const hrt_data base_index) +{ +/* This system only defines the MMU base address */ +assert(0); +(void)base_index; +return; +} + +hrt_data mmgr_get_base_index(void) +{ +/* This system only defines the MMU base address */ +assert(0); +return 0; +} + +ia_css_ptr mmgr_malloc( + const size_t size) +{ +return mmgr_alloc_attr(size, MMGR_ATTRIBUTE_CACHED); +} + +ia_css_ptr mmgr_calloc( + const size_t N, + const size_t size) +{ +return mmgr_alloc_attr(N * size, MMGR_ATTRIBUTE_CLEARED|MMGR_ATTRIBUTE_CACHED); +} + +ia_css_ptr mmgr_realloc( + ia_css_ptr vaddr, + const size_t size) +{ +return mmgr_realloc_attr(vaddr, size, MMGR_ATTRIBUTE_DEFAULT); +} + +void mmgr_free( + ia_css_ptr vaddr) +{ +/* "free()" should accept NULL, "hrt_isp_css_mm_free()" may not */ + if (vaddr) { +#if SH_CSS_MEMORY_GUARDING + alloc_admin_remove(vaddr); + /* Reconstruct the "original" address used with the alloc */ + vaddr -= GUARD_SIZE_ALIGNED; +#endif + hrt_isp_css_mm_free(vaddr); + } +return; +} + +ia_css_ptr mmgr_alloc_attr( + const size_t size, + const uint16_t attribute) +{ + ia_css_ptr ptr; + size_t extra_space = 0; + size_t aligned_size = size; + +assert(page_table_base_address != (sys_address)-1); +assert((attribute & MMGR_ATTRIBUTE_UNUSED) == 0); + +#if SH_CSS_MEMORY_GUARDING + /* Add DDR aligned space for a guard at begin and end */ + /* Begin guard must be DDR aligned, "end" guard not */ + extra_space = GUARD_SIZE_ALIGNED + GUARD_SIZE; + /* SP DMA operates on multiple of 32 bytes, also with writes. + * To prevent that the guard is being overwritten by SP DMA, + * the "end" guard must start DDR aligned. + */ + aligned_size = DDR_ALIGN(aligned_size); +#endif + + if (attribute & MMGR_ATTRIBUTE_CLEARED) { + if (attribute & MMGR_ATTRIBUTE_CACHED) { + if (attribute & MMGR_ATTRIBUTE_CONTIGUOUS) /* { */ + ptr = hrt_isp_css_mm_calloc_contiguous( + aligned_size + extra_space); + /* } */ else /* { */ + ptr = hrt_isp_css_mm_calloc_cached( + aligned_size + extra_space); + /* } */ + } else { /* !MMGR_ATTRIBUTE_CACHED */ + if (attribute & MMGR_ATTRIBUTE_CONTIGUOUS) /* { */ + ptr = hrt_isp_css_mm_calloc_contiguous( + aligned_size + extra_space); + /* } */ else /* { */ + ptr = hrt_isp_css_mm_calloc( + aligned_size + extra_space); + /* } */ + } + } else { /* MMGR_ATTRIBUTE_CLEARED */ + if (attribute & MMGR_ATTRIBUTE_CACHED) { + if (attribute & MMGR_ATTRIBUTE_CONTIGUOUS) /* { */ + ptr = hrt_isp_css_mm_alloc_contiguous( + aligned_size + extra_space); + /* } */ else /* { */ + ptr = hrt_isp_css_mm_alloc_cached( + aligned_size + extra_space); + /* } */ + } else { /* !MMGR_ATTRIBUTE_CACHED */ + if (attribute & MMGR_ATTRIBUTE_CONTIGUOUS) /* { */ + ptr = hrt_isp_css_mm_alloc_contiguous( + aligned_size + extra_space); + /* } */ else /* { */ + ptr = hrt_isp_css_mm_alloc( + aligned_size + extra_space); + /* } */ + } + } + +#if SH_CSS_MEMORY_GUARDING + /* ptr is the user pointer, so we need to skip the "begin" guard */ + ptr += GUARD_SIZE_ALIGNED; + alloc_admin_add(ptr, aligned_size); +#endif + + return ptr; +} + +ia_css_ptr mmgr_realloc_attr( + ia_css_ptr vaddr, + const size_t size, + const uint16_t attribute) +{ +assert(page_table_base_address != (sys_address)-1); +assert((attribute & MMGR_ATTRIBUTE_UNUSED) == 0); +/* assert(attribute == MMGR_ATTRIBUTE_DEFAULT); */ +/* Apparently we don't have this one */ +assert(0); +(void)vaddr; +(void)size; +(void)attribute; +return 0; +} + +ia_css_ptr mmgr_mmap(const void *ptr, const size_t size, uint16_t attribute, + void *context) +{ + struct hrt_userbuffer_attr *userbuffer_attr = context; + return hrt_isp_css_mm_alloc_user_ptr(size, (void *)ptr, + userbuffer_attr->pgnr, + userbuffer_attr->type, + attribute & HRT_BUF_FLAG_CACHED); +} + +void mmgr_clear( + ia_css_ptr vaddr, + const size_t size) +{ + mmgr_set(vaddr, (uint8_t)0, size); +} + +void mmgr_set( + ia_css_ptr vaddr, + const uint8_t data, + const size_t size) +{ +#if SH_CSS_MEMORY_GUARDING + assert(mem_guard_valid(vaddr, size)); +#endif + hrt_isp_css_mm_set(vaddr, (int)data, size); +return; +} + +void mmgr_load( + const ia_css_ptr vaddr, + void *data, + const size_t size) +{ +#if SH_CSS_MEMORY_GUARDING + assert(mem_guard_valid(vaddr, size)); +#endif + hrt_isp_css_mm_load(vaddr, data, size); +return; +} + +void mmgr_store( + const ia_css_ptr vaddr, + const void *data, + const size_t size) +{ +#if SH_CSS_MEMORY_GUARDING + assert(mem_guard_valid(vaddr, size)); +#endif + hrt_isp_css_mm_store(vaddr, data, size); +return; +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/include/hmm/hmm.h b/drivers/staging/media/atomisp/pci/atomisp2/include/hmm/hmm.h new file mode 100644 index 0000000000000000000000000000000000000000..6b9fb1b2caaf83eef5c7debd4801a938b476c641 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/include/hmm/hmm.h @@ -0,0 +1,106 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __HMM_H__ +#define __HMM_H__ + +#include +#include +#include +#include + +#include "hmm/hmm_pool.h" +#include "ia_css_types.h" + +#define HMM_CACHED true +#define HMM_UNCACHED false + +int hmm_pool_register(unsigned int pool_size, enum hmm_pool_type pool_type); +void hmm_pool_unregister(enum hmm_pool_type pool_type); + +int hmm_init(void); +void hmm_cleanup(void); + +ia_css_ptr hmm_alloc(size_t bytes, enum hmm_bo_type type, + int from_highmem, void *userptr, bool cached); +void hmm_free(ia_css_ptr ptr); +int hmm_load(ia_css_ptr virt, void *data, unsigned int bytes); +int hmm_store(ia_css_ptr virt, const void *data, unsigned int bytes); +int hmm_set(ia_css_ptr virt, int c, unsigned int bytes); +int hmm_flush(ia_css_ptr virt, unsigned int bytes); + +/* + * get kernel memory physical address from ISP virtual address. + */ +phys_addr_t hmm_virt_to_phys(ia_css_ptr virt); + +/* + * map ISP memory starts with virt to kernel virtual address + * by using vmap. return NULL if failed. + * + * virt must be the start address of ISP memory (return by hmm_alloc), + * do not pass any other address. + */ +void *hmm_vmap(ia_css_ptr virt, bool cached); +void hmm_vunmap(ia_css_ptr virt); + +/* + * flush the cache for the vmapped buffer. + * if the buffer has not been vmapped, return directly. + */ +void hmm_flush_vmap(ia_css_ptr virt); + +/* + * Address translation from ISP shared memory address to kernel virtual address + * if the memory is not vmmaped, then do it. + */ +void *hmm_isp_vaddr_to_host_vaddr(ia_css_ptr ptr, bool cached); + +/* + * Address translation from kernel virtual address to ISP shared memory address + */ +ia_css_ptr hmm_host_vaddr_to_hrt_vaddr(const void *ptr); + +/* + * map ISP memory starts with virt to specific vma. + * + * used for mmap operation. + * + * virt must be the start address of ISP memory (return by hmm_alloc), + * do not pass any other address. + */ +int hmm_mmap(struct vm_area_struct *vma, ia_css_ptr virt); + +/* show memory statistic + */ +void hmm_show_mem_stat(const char *func, const int line); + +/* init memory statistic + */ +void hmm_init_mem_stat(int res_pgnr, int dyc_en, int dyc_pgnr); + +extern bool dypool_enable; +extern unsigned int dypool_pgnr; +extern struct hmm_bo_device bo_device; + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/include/hmm/hmm_bo.h b/drivers/staging/media/atomisp/pci/atomisp2/include/hmm/hmm_bo.h new file mode 100644 index 0000000000000000000000000000000000000000..dffd6e9cf6938f824230e66fdc326dd7c6c0c25e --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/include/hmm/hmm_bo.h @@ -0,0 +1,323 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __HMM_BO_H__ +#define __HMM_BO_H__ + +#include +#include +#include +#include +#include +#include "mmu/isp_mmu.h" +#include "hmm/hmm_common.h" +#include "ia_css_types.h" + +#define check_bodev_null_return(bdev, exp) \ + check_null_return(bdev, exp, \ + "NULL hmm_bo_device.\n") + +#define check_bodev_null_return_void(bdev) \ + check_null_return_void(bdev, \ + "NULL hmm_bo_device.\n") + +#define check_bo_status_yes_goto(bo, _status, label) \ + var_not_equal_goto((bo->status & (_status)), (_status), \ + label, \ + "HMM buffer status not contain %s.\n", \ + #_status) + +#define check_bo_status_no_goto(bo, _status, label) \ + var_equal_goto((bo->status & (_status)), (_status), \ + label, \ + "HMM buffer status contains %s.\n", \ + #_status) + +#define rbtree_node_to_hmm_bo(root_node) \ + container_of((root_node), struct hmm_buffer_object, node) + +#define list_to_hmm_bo(list_ptr) \ + list_entry((list_ptr), struct hmm_buffer_object, list) + +#define kref_to_hmm_bo(kref_ptr) \ + list_entry((kref_ptr), struct hmm_buffer_object, kref) + +#define check_bo_null_return(bo, exp) \ + check_null_return(bo, exp, "NULL hmm buffer object.\n") + +#define check_bo_null_return_void(bo) \ + check_null_return_void(bo, "NULL hmm buffer object.\n") + +#define HMM_MAX_ORDER 3 +#define HMM_MIN_ORDER 0 + +#define ISP_VM_START 0x0 +#define ISP_VM_SIZE (0x7FFFFFFF) /* 2G address space */ +#define ISP_PTR_NULL NULL + +#define HMM_BO_DEVICE_INITED 0x1 + +enum hmm_bo_type { + HMM_BO_PRIVATE, + HMM_BO_SHARE, + HMM_BO_USER, +#ifdef CONFIG_ION + HMM_BO_ION, +#endif + HMM_BO_LAST, +}; + +enum hmm_page_type { + HMM_PAGE_TYPE_RESERVED, + HMM_PAGE_TYPE_DYNAMIC, + HMM_PAGE_TYPE_GENERAL, +}; + +#define HMM_BO_MASK 0x1 +#define HMM_BO_FREE 0x0 +#define HMM_BO_ALLOCED 0x1 +#define HMM_BO_PAGE_ALLOCED 0x2 +#define HMM_BO_BINDED 0x4 +#define HMM_BO_MMAPED 0x8 +#define HMM_BO_VMAPED 0x10 +#define HMM_BO_VMAPED_CACHED 0x20 +#define HMM_BO_ACTIVE 0x1000 +#define HMM_BO_MEM_TYPE_USER 0x1 +#define HMM_BO_MEM_TYPE_PFN 0x2 + +struct hmm_bo_device { + struct isp_mmu mmu; + + /* start/pgnr/size is used to record the virtual memory of this bo */ + unsigned int start; + unsigned int pgnr; + unsigned int size; + + /* list lock is used to protect the entire_bo_list */ + spinlock_t list_lock; +#ifdef CONFIG_ION + struct ion_client *iclient; +#endif + int flag; + + /* linked list for entire buffer object */ + struct list_head entire_bo_list; + /* rbtree for maintain entire allocated vm */ + struct rb_root allocated_rbtree; + /* rbtree for maintain entire free vm */ + struct rb_root free_rbtree; + struct mutex rbtree_mutex; + struct kmem_cache *bo_cache; +}; + +struct hmm_page_object { + struct page *page; + enum hmm_page_type type; +}; + +struct hmm_buffer_object { + struct hmm_bo_device *bdev; + struct list_head list; + struct kref kref; + + /* mutex protecting this BO */ + struct mutex mutex; + enum hmm_bo_type type; + struct hmm_page_object *page_obj; /* physical pages */ + int from_highmem; + int mmap_count; +#ifdef CONFIG_ION + struct ion_handle *ihandle; +#endif + int status; + int mem_type; + void *vmap_addr; /* kernel virtual address by vmap */ + + struct rb_node node; + unsigned int start; + unsigned int end; + unsigned int pgnr; + /* + * When insert a bo which has the same pgnr with an existed + * bo node in the free_rbtree, using "prev & next" pointer + * to maintain a bo linked list instead of insert this bo + * into free_rbtree directly, it will make sure each node + * in free_rbtree has different pgnr. + * "prev & next" default is NULL. + */ + struct hmm_buffer_object *prev; + struct hmm_buffer_object *next; +}; + +struct hmm_buffer_object *hmm_bo_alloc(struct hmm_bo_device *bdev, + unsigned int pgnr); + +void hmm_bo_release(struct hmm_buffer_object *bo); + +int hmm_bo_device_init(struct hmm_bo_device *bdev, + struct isp_mmu_client *mmu_driver, + unsigned int vaddr_start, unsigned int size); + +/* + * clean up all hmm_bo_device related things. + */ +void hmm_bo_device_exit(struct hmm_bo_device *bdev); + +/* + * whether the bo device is inited or not. + */ +int hmm_bo_device_inited(struct hmm_bo_device *bdev); + +/* + * increse buffer object reference. + */ +void hmm_bo_ref(struct hmm_buffer_object *bo); + +/* + * decrese buffer object reference. if reference reaches 0, + * release function of the buffer object will be called. + * + * this call is also used to release hmm_buffer_object or its + * upper level object with it embedded in. you need to call + * this function when it is no longer used. + * + * Note: + * + * user dont need to care about internal resource release of + * the buffer object in the release callback, it will be + * handled internally. + * + * this call will only release internal resource of the buffer + * object but will not free the buffer object itself, as the + * buffer object can be both pre-allocated statically or + * dynamically allocated. so user need to deal with the release + * of the buffer object itself manually. below example shows + * the normal case of using the buffer object. + * + * struct hmm_buffer_object *bo = hmm_bo_create(bdev, pgnr); + * ...... + * hmm_bo_unref(bo); + * + * or: + * + * struct hmm_buffer_object bo; + * + * hmm_bo_init(bdev, &bo, pgnr, NULL); + * ... + * hmm_bo_unref(&bo); + */ +void hmm_bo_unref(struct hmm_buffer_object *bo); + + +/* + * allocate/free physical pages for the bo. will try to alloc mem + * from highmem if from_highmem is set, and type indicate that the + * pages will be allocated by using video driver (for share buffer) + * or by ISP driver itself. + */ + + +int hmm_bo_allocated(struct hmm_buffer_object *bo); + + +/* + * allocate/free physical pages for the bo. will try to alloc mem + * from highmem if from_highmem is set, and type indicate that the + * pages will be allocated by using video driver (for share buffer) + * or by ISP driver itself. + */ +int hmm_bo_alloc_pages(struct hmm_buffer_object *bo, + enum hmm_bo_type type, int from_highmem, + void *userptr, bool cached); +void hmm_bo_free_pages(struct hmm_buffer_object *bo); +int hmm_bo_page_allocated(struct hmm_buffer_object *bo); + +/* + * get physical page info of the bo. + */ +int hmm_bo_get_page_info(struct hmm_buffer_object *bo, + struct hmm_page_object **page_obj, int *pgnr); + +/* + * bind/unbind the physical pages to a virtual address space. + */ +int hmm_bo_bind(struct hmm_buffer_object *bo); +void hmm_bo_unbind(struct hmm_buffer_object *bo); +int hmm_bo_binded(struct hmm_buffer_object *bo); + +/* + * vmap buffer object's pages to contiguous kernel virtual address. + * if the buffer has been vmaped, return the virtual address directly. + */ +void *hmm_bo_vmap(struct hmm_buffer_object *bo, bool cached); + +/* + * flush the cache for the vmapped buffer object's pages, + * if the buffer has not been vmapped, return directly. + */ +void hmm_bo_flush_vmap(struct hmm_buffer_object *bo); + +/* + * vunmap buffer object's kernel virtual address. + */ +void hmm_bo_vunmap(struct hmm_buffer_object *bo); + +/* + * mmap the bo's physical pages to specific vma. + * + * vma's address space size must be the same as bo's size, + * otherwise it will return -EINVAL. + * + * vma->vm_flags will be set to (VM_RESERVED | VM_IO). + */ +int hmm_bo_mmap(struct vm_area_struct *vma, + struct hmm_buffer_object *bo); + +extern struct hmm_pool dynamic_pool; +extern struct hmm_pool reserved_pool; + +/* + * find the buffer object by its virtual address vaddr. + * return NULL if no such buffer object found. + */ +struct hmm_buffer_object *hmm_bo_device_search_start( + struct hmm_bo_device *bdev, ia_css_ptr vaddr); + +/* + * find the buffer object by its virtual address. + * it does not need to be the start address of one bo, + * it can be an address within the range of one bo. + * return NULL if no such buffer object found. + */ +struct hmm_buffer_object *hmm_bo_device_search_in_range( + struct hmm_bo_device *bdev, ia_css_ptr vaddr); + +/* + * find the buffer object with kernel virtual address vaddr. + * return NULL if no such buffer object found. + */ +struct hmm_buffer_object *hmm_bo_device_search_vmap_start( + struct hmm_bo_device *bdev, const void *vaddr); + + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/include/hmm/hmm_bo_dev.h b/drivers/staging/media/atomisp/pci/atomisp2/include/hmm/hmm_bo_dev.h new file mode 100644 index 0000000000000000000000000000000000000000..a9446adb4c7057fc0ebb8c1643cecf4492f027da --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/include/hmm/hmm_bo_dev.h @@ -0,0 +1,130 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __HMM_BO_DEV_H__ +#define __HMM_BO_DEV_H__ + +#include +#include +#include +#include +#include +#include "mmu/isp_mmu.h" +#include "hmm/hmm_common.h" +#include "hmm/hmm_vm.h" +#include "ia_css_types.h" + +#define check_bodev_null_return(bdev, exp) \ + check_null_return(bdev, exp, \ + "NULL hmm_bo_device.\n") + +#define check_bodev_null_return_void(bdev) \ + check_null_return_void(bdev, \ + "NULL hmm_bo_device.\n") + +#define HMM_BO_DEVICE_INITED 0x1 + +#define HMM_BO_CACHE_SIZE 2 + + +struct hmm_buffer_object; + +struct hmm_bo_device { + /* isp_mmu provides lock itself */ + struct isp_mmu mmu; + + /* hmm_vm provides lock itself */ + struct hmm_vm vaddr_space; + + struct list_head free_bo_list; + struct list_head active_bo_list; + + /* list lock is used to protect both of the buffer object lists */ + spinlock_t list_lock; +#ifdef CONFIG_ION + struct ion_client *iclient; +#endif + int flag; +}; + +int hmm_bo_device_init(struct hmm_bo_device *bdev, + struct isp_mmu_client *mmu_driver, + unsigned int vaddr_start, unsigned int size); + +/* + * clean up all hmm_bo_device related things. + */ +void hmm_bo_device_exit(struct hmm_bo_device *bdev); + +/* + * whether the bo device is inited or not. + */ +int hmm_bo_device_inited(struct hmm_bo_device *bdev); + +/* + * find the buffer object with virtual address vaddr. + * return NULL if no such buffer object found. + */ +struct hmm_buffer_object *hmm_bo_device_search_start( + struct hmm_bo_device *bdev, ia_css_ptr vaddr); + +/* + * find the buffer object with virtual address vaddr. + * return NULL if no such buffer object found. + */ +struct hmm_buffer_object *hmm_bo_device_search_in_range( + struct hmm_bo_device *bdev, ia_css_ptr vaddr); + +/* + * find the buffer object with kernel virtual address vaddr. + * return NULL if no such buffer object found. + */ +struct hmm_buffer_object *hmm_bo_device_search_vmap_start( + struct hmm_bo_device *bdev, const void *vaddr); + +/* + * find a buffer object with pgnr pages from free_bo_list and + * activate it (remove from free_bo_list and add to + * active_bo_list) + * + * return NULL if no such buffer object found. + */ +struct hmm_buffer_object *hmm_bo_device_get_bo( + struct hmm_bo_device *bdev, unsigned int pgnr); + +/* + * destroy all buffer objects in the free_bo_list. + */ +void hmm_bo_device_destroy_free_bo_list(struct hmm_bo_device *bdev); +/* + * destroy buffer object with start virtual address vaddr. + */ +void hmm_bo_device_destroy_free_bo_addr(struct hmm_bo_device *bdev, + ia_css_ptr vaddr); +/* + * destroy all buffer objects with pgnr pages. + */ +void hmm_bo_device_destroy_free_bo_size(struct hmm_bo_device *bdev, + unsigned int pgnr); + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/include/hmm/hmm_common.h b/drivers/staging/media/atomisp/pci/atomisp2/include/hmm/hmm_common.h new file mode 100644 index 0000000000000000000000000000000000000000..f1593aa38ce143f8d7bd61a6c5729d3b1aa7cf68 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/include/hmm/hmm_common.h @@ -0,0 +1,100 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __HMM_BO_COMMON_H__ +#define __HMM_BO_COMMON_H__ + +#define HMM_BO_NAME "HMM" + +/* + * some common use micros + */ +#define var_equal_return(var1, var2, exp, fmt, arg ...) \ + do { \ + if ((var1) == (var2)) { \ + dev_err(atomisp_dev, \ + fmt, ## arg); \ + return exp;\ + } \ + } while (0) + +#define var_equal_return_void(var1, var2, fmt, arg ...) \ + do { \ + if ((var1) == (var2)) { \ + dev_err(atomisp_dev, \ + fmt, ## arg); \ + return;\ + } \ + } while (0) + +#define var_equal_goto(var1, var2, label, fmt, arg ...) \ + do { \ + if ((var1) == (var2)) { \ + dev_err(atomisp_dev, \ + fmt, ## arg); \ + goto label;\ + } \ + } while (0) + +#define var_not_equal_goto(var1, var2, label, fmt, arg ...) \ + do { \ + if ((var1) != (var2)) { \ + dev_err(atomisp_dev, \ + fmt, ## arg); \ + goto label;\ + } \ + } while (0) + +#define check_null_return(ptr, exp, fmt, arg ...) \ + var_equal_return(ptr, NULL, exp, fmt, ## arg) + +#define check_null_return_void(ptr, fmt, arg ...) \ + var_equal_return_void(ptr, NULL, fmt, ## arg) + +/* hmm_mem_stat is used to trace the hmm mem used by ISP pipe. The unit is page + * number. + * + * res_size: reserved mem pool size, being allocated from system at system boot time. + * res_size >= res_cnt. + * sys_size: system mem pool size, being allocated from system at camera running time. + * dyc_size: dynamic mem pool size. + * dyc_thr: dynamic mem pool high watermark. + * dyc_size <= dyc_thr. + * usr_size: user ptr mem size. + * + * res_cnt: track the mem allocated from reserved pool at camera running time. + * tol_cnt: track the total mem used by ISP pipe at camera running time. + */ +struct _hmm_mem_stat { + int res_size; + int sys_size; + int dyc_size; + int dyc_thr; + int usr_size; + int res_cnt; + int tol_cnt; +}; + +extern struct _hmm_mem_stat hmm_mem_stat; + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/include/hmm/hmm_pool.h b/drivers/staging/media/atomisp/pci/atomisp2/include/hmm/hmm_pool.h new file mode 100644 index 0000000000000000000000000000000000000000..304037bd1d82305a8692ac39ef46f6677b82157c --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/include/hmm/hmm_pool.h @@ -0,0 +1,121 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#ifndef __HMM_POOL_H__ +#define __HMM_POOL_H__ + +#include +#include +#include +#include +#include +#include +#include "hmm_common.h" +#include "hmm/hmm_bo.h" + +#define ALLOC_PAGE_FAIL_NUM 5 + +enum hmm_pool_type { + HMM_POOL_TYPE_RESERVED, + HMM_POOL_TYPE_DYNAMIC, +}; + +/** + * struct hmm_pool_ops - memory pool callbacks. + * + * @pool_init: initialize the memory pool. + * @pool_exit: uninitialize the memory pool. + * @pool_alloc_pages: allocate pages from memory pool. + * @pool_free_pages: free pages to memory pool. + * @pool_inited: check whether memory pool is initialized. + */ +struct hmm_pool_ops { + int (*pool_init)(void **pool, unsigned int pool_size); + void (*pool_exit)(void **pool); + unsigned int (*pool_alloc_pages)(void *pool, + struct hmm_page_object *page_obj, + unsigned int size, bool cached); + void (*pool_free_pages)(void *pool, + struct hmm_page_object *page_obj); + int (*pool_inited)(void *pool); +}; + +struct hmm_pool { + struct hmm_pool_ops *pops; + + void *pool_info; +}; + +/** + * struct hmm_reserved_pool_info - represents reserved pool private data. + * @pages: a array that store physical pages. + * The array is as reserved memory pool. + * @index: to indicate the first blank page number + * in reserved memory pool(pages array). + * @pgnr: the valid page amount in reserved memory + * pool. + * @list_lock: list lock is used to protect the operation + * to reserved memory pool. + * @flag: reserved memory pool state flag. + */ +struct hmm_reserved_pool_info { + struct page **pages; + + unsigned int index; + unsigned int pgnr; + spinlock_t list_lock; + bool initialized; +}; + +/** + * struct hmm_dynamic_pool_info - represents dynamic pool private data. + * @pages_list: a list that store physical pages. + * The pages list is as dynamic memory pool. + * @list_lock: list lock is used to protect the operation + * to dynamic memory pool. + * @flag: dynamic memory pool state flag. + * @pgptr_cache: struct kmem_cache, manages a cache. + */ +struct hmm_dynamic_pool_info { + struct list_head pages_list; + + /* list lock is used to protect the free pages block lists */ + spinlock_t list_lock; + +#ifdef USE_KMEM_CACHE + struct kmem_cache *pgptr_cache; +#endif + bool initialized; + + unsigned int pool_size; + unsigned int pgnr; +}; + +struct hmm_page { + struct page *page; + struct list_head list; +}; + +extern struct hmm_pool_ops reserved_pops; +extern struct hmm_pool_ops dynamic_pops; + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/include/hmm/hmm_vm.h b/drivers/staging/media/atomisp/pci/atomisp2/include/hmm/hmm_vm.h new file mode 100644 index 0000000000000000000000000000000000000000..07d40662de32712058c6effb234f52a907424848 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/include/hmm/hmm_vm.h @@ -0,0 +1,68 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __HMM_VM_H__ +#define __HMM_VM_H__ + +#include +#include +#include +#include + +struct hmm_vm { + unsigned int start; + unsigned int pgnr; + unsigned int size; + struct list_head vm_node_list; + spinlock_t lock; + struct kmem_cache *cache; +}; + +struct hmm_vm_node { + struct list_head list; + unsigned int start; + unsigned int pgnr; + unsigned int size; + struct hmm_vm *vm; +}; +#define ISP_VM_START 0x0 +#define ISP_VM_SIZE (0x7FFFFFFF) /* 2G address space */ +#define ISP_PTR_NULL NULL + +int hmm_vm_init(struct hmm_vm *vm, unsigned int start, + unsigned int size); + +void hmm_vm_clean(struct hmm_vm *vm); + +struct hmm_vm_node *hmm_vm_alloc_node(struct hmm_vm *vm, + unsigned int pgnr); + +void hmm_vm_free_node(struct hmm_vm_node *node); + +struct hmm_vm_node *hmm_vm_find_node_start(struct hmm_vm *vm, + unsigned int addr); + +struct hmm_vm_node *hmm_vm_find_node_in_range(struct hmm_vm *vm, + unsigned int addr); + +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/include/mmu/isp_mmu.h b/drivers/staging/media/atomisp/pci/atomisp2/include/mmu/isp_mmu.h new file mode 100644 index 0000000000000000000000000000000000000000..790d5064b06bf697fac5eb33aa20b5fca3a36bb5 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/include/mmu/isp_mmu.h @@ -0,0 +1,177 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +/* + * ISP MMU driver for classic two-level page tables + */ +#ifndef __ISP_MMU_H__ +#define __ISP_MMU_H__ + +#include +#include +#include + +/* + * do not change these values, the page size for ISP must be the + * same as kernel's page size. + */ +#define ISP_PAGE_OFFSET 12 +#define ISP_PAGE_SIZE (1U << ISP_PAGE_OFFSET) +#define ISP_PAGE_MASK (~(phys_addr_t)(ISP_PAGE_SIZE - 1)) + +#define ISP_L1PT_OFFSET 22 +#define ISP_L1PT_MASK (~((1U << ISP_L1PT_OFFSET) - 1)) + +#define ISP_L2PT_OFFSET 12 +#define ISP_L2PT_MASK (~(ISP_L1PT_MASK|(~(ISP_PAGE_MASK)))) + +#define ISP_L1PT_PTES 1024 +#define ISP_L2PT_PTES 1024 + +#define ISP_PTR_TO_L1_IDX(x) ((((x) & ISP_L1PT_MASK)) \ + >> ISP_L1PT_OFFSET) + +#define ISP_PTR_TO_L2_IDX(x) ((((x) & ISP_L2PT_MASK)) \ + >> ISP_L2PT_OFFSET) + +#define ISP_PAGE_ALIGN(x) (((x) + (ISP_PAGE_SIZE-1)) \ + & ISP_PAGE_MASK) + +#define ISP_PT_TO_VIRT(l1_idx, l2_idx, offset) do {\ + ((l1_idx) << ISP_L1PT_OFFSET) | \ + ((l2_idx) << ISP_L2PT_OFFSET) | \ + (offset)\ +} while (0) + +#define pgnr_to_size(pgnr) ((pgnr) << ISP_PAGE_OFFSET) +#define size_to_pgnr_ceil(size) (((size) + (1 << ISP_PAGE_OFFSET) - 1)\ + >> ISP_PAGE_OFFSET) +#define size_to_pgnr_bottom(size) ((size) >> ISP_PAGE_OFFSET) + +struct isp_mmu; + +struct isp_mmu_client { + /* + * const value + * + * @name: + * driver name + * @pte_valid_mask: + * should be 1 bit valid data, meaning the value should + * be power of 2. + */ + char *name; + unsigned int pte_valid_mask; + unsigned int null_pte; + + /* + * set/get page directory base address (physical address). + * + * must be provided. + */ + int (*set_pd_base) (struct isp_mmu *mmu, + phys_addr_t pd_base); + unsigned int (*get_pd_base) (struct isp_mmu *mmu, phys_addr_t pd_base); + /* + * callback to flush tlb. + * + * tlb_flush_range will at least flush TLBs containing + * address mapping from addr to addr + size. + * + * tlb_flush_all will flush all TLBs. + * + * tlb_flush_all is must be provided. if tlb_flush_range is + * not valid, it will set to tlb_flush_all by default. + */ + void (*tlb_flush_range) (struct isp_mmu *mmu, + unsigned int addr, unsigned int size); + void (*tlb_flush_all) (struct isp_mmu *mmu); + unsigned int (*phys_to_pte) (struct isp_mmu *mmu, + phys_addr_t phys); + phys_addr_t (*pte_to_phys) (struct isp_mmu *mmu, + unsigned int pte); + +}; + +struct isp_mmu { + struct isp_mmu_client *driver; + unsigned int l1_pte; + int l2_pgt_refcount[ISP_L1PT_PTES]; + phys_addr_t base_address; + + struct mutex pt_mutex; +#ifdef USE_KMEM_CACHE + struct kmem_cache *tbl_cache; +#endif +}; + +/* flags for PDE and PTE */ +#define ISP_PTE_VALID_MASK(mmu) \ + ((mmu)->driver->pte_valid_mask) + +#define ISP_PTE_VALID(mmu, pte) \ + ((pte) & ISP_PTE_VALID_MASK(mmu)) + +#define NULL_PAGE ((phys_addr_t)(-1) & ISP_PAGE_MASK) +#define PAGE_VALID(page) ((page) != NULL_PAGE) + +/* + * init mmu with specific mmu driver. + */ +int isp_mmu_init(struct isp_mmu *mmu, struct isp_mmu_client *driver); +/* + * cleanup all mmu related things. + */ +void isp_mmu_exit(struct isp_mmu *mmu); + +/* + * setup/remove address mapping for pgnr continous physical pages + * and isp_virt. + * + * map/unmap is mutex lock protected, and caller does not have + * to do lock/unlock operation. + * + * map/unmap will not flush tlb, and caller needs to deal with + * this itself. + */ +int isp_mmu_map(struct isp_mmu *mmu, unsigned int isp_virt, + phys_addr_t phys, unsigned int pgnr); + +void isp_mmu_unmap(struct isp_mmu *mmu, unsigned int isp_virt, + unsigned int pgnr); + +static inline void isp_mmu_flush_tlb_all(struct isp_mmu *mmu) +{ + if (mmu->driver && mmu->driver->tlb_flush_all) + mmu->driver->tlb_flush_all(mmu); +} + +#define isp_mmu_flush_tlb isp_mmu_flush_tlb_all + +static inline void isp_mmu_flush_tlb_range(struct isp_mmu *mmu, + unsigned int start, unsigned int size) +{ + if (mmu->driver && mmu->driver->tlb_flush_range) + mmu->driver->tlb_flush_range(mmu, start, size); +} + +#endif /* ISP_MMU_H_ */ diff --git a/drivers/staging/media/atomisp/pci/atomisp2/include/mmu/sh_mmu.h b/drivers/staging/media/atomisp/pci/atomisp2/include/mmu/sh_mmu.h new file mode 100644 index 0000000000000000000000000000000000000000..06041e94cbb26440051db9e00b22cbf8cd2cc8cc --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/include/mmu/sh_mmu.h @@ -0,0 +1,76 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#ifndef SH_MMU_H_ +#define SH_MMU_H_ + + +#include + +#include "mmu/isp_mmu.h" + + +/* + * include SH header file here + */ + +/* + * set page directory base address (physical address). + * + * must be provided. + */ +static int sh_set_pd_base(struct isp_mmu *mmu, + unsigned int phys) +{ + sh_css_mmu_set_page_table_base_address((void *)phys); + return 0; +} + +/* + * callback to flush tlb. + * + * tlb_flush_range will at least flush TLBs containing + * address mapping from addr to addr + size. + * + * tlb_flush_all will flush all TLBs. + * + * tlb_flush_all is must be provided. if tlb_flush_range is + * not valid, it will set to tlb_flush_all by default. + */ +static void sh_tlb_flush(struct isp_mmu *mmu) +{ + sh_css_mmu_invalidate_cache(); +} + +static struct isp_mmu_driver sh_mmu_driver = { + .name = "Silicon Hive ISP3000 MMU", + .pte_valid_mask = 0x1, + .set_pd_base = sh_set_pd_base, + .tlb_flush_all = sh_tlb_flush, +}; + +#define ISP_VM_START 0x0 +#define ISP_VM_SIZE (1 << 30) /* 1G address space */ +#define ISP_PTR_NULL NULL + +#endif /* SH_MMU_H_ */ + diff --git a/drivers/staging/media/atomisp/pci/atomisp2/include/mmu/sh_mmu_mrfld.h b/drivers/staging/media/atomisp/pci/atomisp2/include/mmu/sh_mmu_mrfld.h new file mode 100644 index 0000000000000000000000000000000000000000..b9bad9f06235eba1839954fabc852ad7031f8b8a --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/include/mmu/sh_mmu_mrfld.h @@ -0,0 +1,28 @@ +/* + * Support for Merrifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ + +#ifndef __SH_MMU_MRFLD_H__ +#define __SH_MMU_MRFLD_H__ + +extern struct isp_mmu_client sh_mmu_mrfld; +#endif diff --git a/drivers/staging/media/atomisp/pci/atomisp2/list b/drivers/staging/media/atomisp/pci/atomisp2/list new file mode 100644 index 0000000000000000000000000000000000000000..dc7e4a8d5da93d60fb6d2be9d0aeff8aade422c7 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/list @@ -0,0 +1,182 @@ + ./atomisp_drvfs.o \ + ./atomisp_file.o \ + ./css2400/sh_css_mipi.o \ + ./css2400/css_2401_system/spmem_dump.o \ + ./css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_states.o \ + ./css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_configs.o \ + ./css2400/css_2401_system/hive_isp_css_2401_system_generated/ia_css_isp_params.o \ + ./css2400/runtime/pipeline/src/pipeline.o \ + ./css2400/runtime/spctrl/src/spctrl.o \ + ./css2400/runtime/rmgr/src/rmgr.o \ + ./css2400/runtime/rmgr/src/rmgr_vbuf.o \ + ./css2400/runtime/isp_param/src/isp_param.o \ + ./css2400/runtime/inputfifo/src/inputfifo.o \ + ./css2400/runtime/queue/src/queue_access.o \ + ./css2400/runtime/queue/src/queue.o \ + ./css2400/runtime/frame/src/frame.o \ + ./css2400/runtime/eventq/src/eventq.o \ + ./css2400/runtime/binary/src/binary.o \ + ./css2400/runtime/timer/src/timer.o \ + ./css2400/runtime/isys/src/csi_rx_rmgr.o \ + ./css2400/runtime/isys/src/isys_stream2mmio_rmgr.o \ + ./css2400/runtime/isys/src/virtual_isys.o \ + ./css2400/runtime/isys/src/rx.o \ + ./css2400/runtime/isys/src/isys_dma_rmgr.o \ + ./css2400/runtime/isys/src/ibuf_ctrl_rmgr.o \ + ./css2400/runtime/isys/src/isys_init.o \ + ./css2400/runtime/bufq/src/bufq.o \ + ./css2400/runtime/ifmtr/src/ifmtr.o \ + ./css2400/runtime/debug/src/ia_css_debug.o \ + ./css2400/runtime/event/src/event.o \ + ./css2400/sh_css_sp.o \ + ./css2400/css_2400_system/spmem_dump.o \ + ./css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_states.o \ + ./css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_configs.o \ + ./css2400/css_2400_system/hive_isp_css_2400_system_generated/ia_css_isp_params.o \ + ./css2400/sh_css_stream_format.o \ + ./css2400/sh_css_hrt.o \ + ./css2400/sh_css_properties.o \ + ./css2400/memory_realloc.o \ + ./css2400/hive_isp_css_shared/host/tag.o \ + ./css2400/sh_css_params.o \ + ./css2400/sh_css.o \ + ./css2400/isp/kernels/hdr/ia_css_hdr.host.o \ + ./css2400/isp/kernels/uds/uds_1.0/ia_css_uds.host.o \ + ./css2400/isp/kernels/ynr/ynr_2/ia_css_ynr2.host.o \ + ./css2400/isp/kernels/ynr/ynr_1.0/ia_css_ynr.host.o \ + ./css2400/isp/kernels/conversion/conversion_1.0/ia_css_conversion.host.o \ + ./css2400/isp/kernels/fpn/fpn_1.0/ia_css_fpn.host.o \ + ./css2400/isp/kernels/tnr/tnr_1.0/ia_css_tnr.host.o \ + ./css2400/isp/kernels/vf/vf_1.0/ia_css_vf.host.o \ + ./css2400/isp/kernels/raw/raw_1.0/ia_css_raw.host.o \ + ./css2400/isp/kernels/ref/ref_1.0/ia_css_ref.host.o \ + ./css2400/isp/kernels/qplane/qplane_2/ia_css_qplane.host.o \ + ./css2400/isp/kernels/norm/norm_1.0/ia_css_norm.host.o \ + ./css2400/isp/kernels/output/output_1.0/ia_css_output.host.o \ + ./css2400/isp/kernels/raw_aa_binning/raw_aa_binning_1.0/ia_css_raa.host.o \ + ./css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5_table.host.o \ + ./css2400/isp/kernels/macc/macc1_5/ia_css_macc1_5.host.o \ + ./css2400/isp/kernels/macc/macc_1.0/ia_css_macc.host.o \ + ./css2400/isp/kernels/macc/macc_1.0/ia_css_macc_table.host.o \ + ./css2400/isp/kernels/csc/csc_1.0/ia_css_csc.host.o \ + ./css2400/isp/kernels/iefd2_6/ia_css_iefd2_6_default.host.o \ + ./css2400/isp/kernels/iefd2_6/ia_css_iefd2_6.host.o \ + ./css2400/isp/kernels/bnr/bnr_1.0/ia_css_bnr.host.o \ + ./css2400/isp/kernels/bnr/bnr2_2/ia_css_bnr2_2.host.o \ + ./css2400/isp/kernels/dpc2/ia_css_dpc2.host.o \ + ./css2400/isp/kernels/dpc2/ia_css_dpc2_default.host.o \ + ./css2400/isp/kernels/fc/fc_1.0/ia_css_formats.host.o \ + ./css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc.host.o \ + ./css2400/isp/kernels/ctc/ctc_1.0/ia_css_ctc_table.host.o \ + ./css2400/isp/kernels/ctc/ctc2/ia_css_ctc2.host.o \ + ./css2400/isp/kernels/ctc/ctc1_5/ia_css_ctc1_5.host.o \ + ./css2400/isp/kernels/fixedbds/fixedbds_1.0/ia_css_fixedbds.host.o \ + ./css2400/isp/kernels/bh/bh_2/ia_css_bh.host.o \ + ./css2400/isp/kernels/bnlm/ia_css_bnlm_default.host.o \ + ./css2400/isp/kernels/bnlm/ia_css_bnlm.host.o \ + ./css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf.host.o \ + ./css2400/isp/kernels/tdf/tdf_1.0/ia_css_tdf_default.host.o \ + ./css2400/isp/kernels/dvs/dvs_1.0/ia_css_dvs.host.o \ + ./css2400/isp/kernels/anr/anr_1.0/ia_css_anr.host.o \ + ./css2400/isp/kernels/anr/anr_2/ia_css_anr2_table.host.o \ + ./css2400/isp/kernels/anr/anr_2/ia_css_anr2.host.o \ + ./css2400/isp/kernels/dp/dp_1.0/ia_css_dp.host.o \ + ./css2400/isp/kernels/sdis/sdis_1.0/ia_css_sdis.host.o \ + ./css2400/isp/kernels/sdis/sdis_2/ia_css_sdis2.host.o \ + ./css2400/isp/kernels/cnr/cnr_2/ia_css_cnr2.host.o \ + ./css2400/isp/kernels/cnr/cnr_1.0/ia_css_cnr.host.o \ + ./css2400/isp/kernels/satm/ia_css_satm.host.o \ + ./css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr.host.o \ + ./css2400/isp/kernels/xnr/xnr_1.0/ia_css_xnr_table.host.o \ + ./css2400/isp/kernels/xnr/xnr3_0_5/ia_css_xnr3_0_5.host.o \ + ./css2400/isp/kernels/xnr/xnr_3.0/ia_css_xnr3.host.o \ + ./css2400/isp/kernels/xnr/xnr3_0_11/ia_css_xnr3_0_11.host.o \ + ./css2400/isp/kernels/de/de_1.0/ia_css_de.host.o \ + ./css2400/isp/kernels/de/de_2/ia_css_de2.host.o \ + ./css2400/isp/kernels/gc/gc_2/ia_css_gc2.host.o \ + ./css2400/isp/kernels/gc/gc_2/ia_css_gc2_table.host.o \ + ./css2400/isp/kernels/gc/gc_1.0/ia_css_gc.host.o \ + ./css2400/isp/kernels/gc/gc_1.0/ia_css_gc_table.host.o \ + ./css2400/isp/kernels/crop/crop_1.0/ia_css_crop.host.o \ + ./css2400/isp/kernels/io_ls/bayer_io_ls/ia_css_bayer_io.host.o \ + ./css2400/isp/kernels/aa/aa_2/ia_css_aa2.host.o \ + ./css2400/isp/kernels/pdaf/ia_css_pdaf.host.o \ + ./css2400/isp/kernels/copy_output/copy_output_1.0/ia_css_copy_output.host.o \ + ./css2400/isp/kernels/ob/ob_1.0/ia_css_ob.host.o \ + ./css2400/isp/kernels/ob/ob2/ia_css_ob2.host.o \ + ./css2400/isp/kernels/iterator/iterator_1.0/ia_css_iterator.host.o \ + ./css2400/isp/kernels/wb/wb_1.0/ia_css_wb.host.o \ + ./css2400/isp/kernels/eed1_8/ia_css_eed1_8_default.host.o \ + ./css2400/isp/kernels/eed1_8/ia_css_eed1_8.host.o \ + ./css2400/isp/kernels/sc/sc_1.0/ia_css_sc.host.o \ + ./css2400/isp/kernels/ipu2_io_ls/bayer_io_ls/ia_css_bayer_io.host.o \ + ./css2400/isp/kernels/ipu2_io_ls/yuv444_io_ls/ia_css_yuv444_io.host.o \ + ./css2400/isp/kernels/s3a/s3a_1.0/ia_css_s3a.host.o \ + ./css2400/sh_css_lace_stat.o \ + ./css2400/sh_css_pipe.o \ + ./css2400/ia_css_device_access.o \ + ./css2400/sh_css_host_data.o \ + ./css2400/sh_css_mmu.o \ + ./css2400/sh_css_metadata.o \ + ./css2400/base/refcount/src/refcount.o \ + ./css2400/base/circbuf/src/circbuf.o \ + ./css2400/sh_css_irq.o \ + ./css2400/camera/pipe/src/pipe_binarydesc.o \ + ./css2400/camera/pipe/src/pipe_util.o \ + ./css2400/camera/pipe/src/pipe_stagedesc.o \ + ./css2400/camera/util/src/util.o \ + ./css2400/css_2401_csi2p_system/spmem_dump.o \ + ./css2400/css_2401_csi2p_system/host/isys_stream2mmio.o \ + ./css2400/css_2401_csi2p_system/host/ibuf_ctrl.o \ + ./css2400/css_2401_csi2p_system/host/isys_irq.o \ + ./css2400/css_2401_csi2p_system/host/isys_dma.o \ + ./css2400/css_2401_csi2p_system/host/csi_rx.o \ + ./css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_states.o \ + ./css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_configs.o \ + ./css2400/css_2401_csi2p_system/hive_isp_css_2401_system_csi2p_generated/ia_css_isp_params.o \ + ./css2400/sh_css_metrics.o \ + ./css2400/sh_css_version.o \ + ./css2400/ia_css_memory_access.o \ + ./css2400/sh_css_param_shading.o \ + ./css2400/sh_css_morph.o \ + ./css2400/sh_css_firmware.o \ + ./css2400/hive_isp_css_common/host/isp.o \ + ./css2400/hive_isp_css_common/host/gdc.o \ + ./css2400/hive_isp_css_common/host/sp.o \ + ./css2400/hive_isp_css_common/host/vmem.o \ + ./css2400/hive_isp_css_common/host/dma.o \ + ./css2400/hive_isp_css_common/host/input_formatter.o \ + ./css2400/hive_isp_css_common/host/debug.o \ + ./css2400/hive_isp_css_common/host/hmem.o \ + ./css2400/hive_isp_css_common/host/gp_device.o \ + ./css2400/hive_isp_css_common/host/fifo_monitor.o \ + ./css2400/hive_isp_css_common/host/gp_timer.o \ + ./css2400/hive_isp_css_common/host/irq.o \ + ./css2400/hive_isp_css_common/host/input_system.o \ + ./css2400/hive_isp_css_common/host/timed_ctrl.o \ + ./css2400/hive_isp_css_common/host/mmu.o \ + ./css2400/hive_isp_css_common/host/event_fifo.o \ + ./css2400/sh_css_param_dvs.o \ + ./css2400/sh_css_shading.o \ + ./css2400/sh_css_stream.o \ + ./mmu/sh_mmu_mrfld.o \ + ./mmu/isp_mmu.o \ + ./atomisp_acc.o \ + ./atomisp_compat_css20.o \ + ./atomisp_fops.o \ + ./atomisp_subdev.o \ + ./hmm/hmm_dynamic_pool.o \ + ./hmm/hmm_vm.o \ + ./hmm/hmm_reserved_pool.o \ + ./hmm/hmm_bo_dev.o \ + ./hmm/hmm.o \ + ./hmm/hmm_bo.o \ + ./hrt/hive_isp_css_mm_hrt.o \ + ./hrt/memory_access.o \ + ./hrt/device_access.o \ + ./atomisp_ioctl.o \ + ./atomisp_compat_ioctl32.o \ + ./atomisp_csi2.o \ + ./atomisp_cmd.o \ + ./atomisp_tpg.o \ + ./atomisp_v4l2.o diff --git a/drivers/staging/media/atomisp/pci/atomisp2/mmu/isp_mmu.c b/drivers/staging/media/atomisp/pci/atomisp2/mmu/isp_mmu.c new file mode 100644 index 0000000000000000000000000000000000000000..b53aaa06e7d8f0492d4e5ac615e2671e71a60a05 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/mmu/isp_mmu.c @@ -0,0 +1,606 @@ +/* + * Support for Medifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2010 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2010 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +/* + * ISP MMU management wrap code + */ +#include +#include +#include +#include /* for GFP_ATOMIC */ +#include /* for kmalloc */ +#include +#include +#include +#include +#include +#include +#include +#include + +#include "atomisp_internal.h" +#include "mmu/isp_mmu.h" + +/* + * 64-bit x86 processor physical address layout: + * 0 - 0x7fffffff DDR RAM (2GB) + * 0x80000000 - 0xffffffff MMIO (2GB) + * 0x100000000 - 0x3fffffffffff DDR RAM (64TB) + * So if the system has more than 2GB DDR memory, the lower 2GB occupies the + * physical address 0 - 0x7fffffff and the rest will start from 0x100000000. + * We have to make sure memory is allocated from the lower 2GB for devices + * that are only 32-bit capable(e.g. the ISP MMU). + * + * For any confusion, contact bin.gao@intel.com. + */ +#define NR_PAGES_2GB (SZ_2G / PAGE_SIZE) + +static void free_mmu_map(struct isp_mmu *mmu, unsigned int start_isp_virt, + unsigned int end_isp_virt); + +static unsigned int atomisp_get_pte(phys_addr_t pt, unsigned int idx) +{ + unsigned int *pt_virt = phys_to_virt(pt); + return *(pt_virt + idx); +} + +static void atomisp_set_pte(phys_addr_t pt, + unsigned int idx, unsigned int pte) +{ + unsigned int *pt_virt = phys_to_virt(pt); + *(pt_virt + idx) = pte; +} + +static void *isp_pt_phys_to_virt(phys_addr_t phys) +{ + return phys_to_virt(phys); +} + +static phys_addr_t isp_pte_to_pgaddr(struct isp_mmu *mmu, + unsigned int pte) +{ + return mmu->driver->pte_to_phys(mmu, pte); +} + +static unsigned int isp_pgaddr_to_pte_valid(struct isp_mmu *mmu, + phys_addr_t phys) +{ + unsigned int pte = mmu->driver->phys_to_pte(mmu, phys); + return (unsigned int) (pte | ISP_PTE_VALID_MASK(mmu)); +} + +/* + * allocate a uncacheable page table. + * return physical address. + */ +static phys_addr_t alloc_page_table(struct isp_mmu *mmu) +{ + int i; + phys_addr_t page; + void *virt; + + /*page table lock may needed here*/ + /* + * The slab allocator(kmem_cache and kmalloc family) doesn't handle + * GFP_DMA32 flag, so we have to use buddy allocator. + */ +#ifdef USE_KMEM_CACHE + if (totalram_pages > (unsigned long)NR_PAGES_2GB) + virt = (void *)__get_free_page(GFP_KERNEL | GFP_DMA32); + else + virt = kmem_cache_zalloc(mmu->tbl_cache, GFP_KERNEL); +#else + virt = (void *)__get_free_page(GFP_KERNEL | GFP_DMA32); +#endif + if (!virt) + return (phys_addr_t)NULL_PAGE; + + /* + * we need a uncacheable page table. + */ +#ifdef CONFIG_X86 + set_memory_uc((unsigned long)virt, 1); +#endif + + page = virt_to_phys(virt); + + for (i = 0; i < 1024; i++) { + /* NEED CHECK */ + atomisp_set_pte(page, i, mmu->driver->null_pte); + } + + return page; +} + +static void free_page_table(struct isp_mmu *mmu, phys_addr_t page) +{ + void *virt; + page &= ISP_PAGE_MASK; + /* + * reset the page to write back before free + */ + virt = phys_to_virt(page); + +#ifdef CONFIG_X86 + set_memory_wb((unsigned long)virt, 1); +#endif + +#ifdef USE_KMEM_CACHE + kmem_cache_free(mmu->tbl_cache, virt); +#else + free_page((unsigned long)virt); +#endif +} + +static void mmu_remap_error(struct isp_mmu *mmu, + phys_addr_t l1_pt, unsigned int l1_idx, + phys_addr_t l2_pt, unsigned int l2_idx, + unsigned int isp_virt, phys_addr_t old_phys, + phys_addr_t new_phys) +{ + dev_err(atomisp_dev, "address remap:\n\n" + "\tL1 PT: virt = %p, phys = 0x%llx, " + "idx = %d\n" + "\tL2 PT: virt = %p, phys = 0x%llx, " + "idx = %d\n" + "\told: isp_virt = 0x%x, phys = 0x%llx\n" + "\tnew: isp_virt = 0x%x, phys = 0x%llx\n", + isp_pt_phys_to_virt(l1_pt), + (u64)l1_pt, l1_idx, + isp_pt_phys_to_virt(l2_pt), + (u64)l2_pt, l2_idx, isp_virt, + (u64)old_phys, isp_virt, + (u64)new_phys); +} + +static void mmu_unmap_l2_pte_error(struct isp_mmu *mmu, + phys_addr_t l1_pt, unsigned int l1_idx, + phys_addr_t l2_pt, unsigned int l2_idx, + unsigned int isp_virt, unsigned int pte) +{ + dev_err(atomisp_dev, "unmap unvalid L2 pte:\n\n" + "\tL1 PT: virt = %p, phys = 0x%llx, " + "idx = %d\n" + "\tL2 PT: virt = %p, phys = 0x%llx, " + "idx = %d\n" + "\tisp_virt = 0x%x, pte(page phys) = 0x%x\n", + isp_pt_phys_to_virt(l1_pt), + (u64)l1_pt, l1_idx, + isp_pt_phys_to_virt(l2_pt), + (u64)l2_pt, l2_idx, isp_virt, + pte); +} + +static void mmu_unmap_l1_pte_error(struct isp_mmu *mmu, + phys_addr_t l1_pt, unsigned int l1_idx, + unsigned int isp_virt, unsigned int pte) +{ + dev_err(atomisp_dev, "unmap unvalid L1 pte (L2 PT):\n\n" + "\tL1 PT: virt = %p, phys = 0x%llx, " + "idx = %d\n" + "\tisp_virt = 0x%x, l1_pte(L2 PT) = 0x%x\n", + isp_pt_phys_to_virt(l1_pt), + (u64)l1_pt, l1_idx, (unsigned int)isp_virt, + pte); +} + +static void mmu_unmap_l1_pt_error(struct isp_mmu *mmu, unsigned int pte) +{ + dev_err(atomisp_dev, "unmap unvalid L1PT:\n\n" + "L1PT = 0x%x\n", (unsigned int)pte); +} + +/* + * Update L2 page table according to isp virtual address and page physical + * address + */ +static int mmu_l2_map(struct isp_mmu *mmu, phys_addr_t l1_pt, + unsigned int l1_idx, phys_addr_t l2_pt, + unsigned int start, unsigned int end, phys_addr_t phys) +{ + unsigned int ptr; + unsigned int idx; + unsigned int pte; + + l2_pt &= ISP_PAGE_MASK; + + start = start & ISP_PAGE_MASK; + end = ISP_PAGE_ALIGN(end); + phys &= ISP_PAGE_MASK; + + ptr = start; + do { + idx = ISP_PTR_TO_L2_IDX(ptr); + + pte = atomisp_get_pte(l2_pt, idx); + + if (ISP_PTE_VALID(mmu, pte)) { + mmu_remap_error(mmu, l1_pt, l1_idx, + l2_pt, idx, ptr, pte, phys); + + /* free all mapped pages */ + free_mmu_map(mmu, start, ptr); + + return -EINVAL; + } + + pte = isp_pgaddr_to_pte_valid(mmu, phys); + + atomisp_set_pte(l2_pt, idx, pte); + mmu->l2_pgt_refcount[l1_idx]++; + ptr += (1U << ISP_L2PT_OFFSET); + phys += (1U << ISP_L2PT_OFFSET); + } while (ptr < end && idx < ISP_L2PT_PTES - 1); + + return 0; +} + +/* + * Update L1 page table according to isp virtual address and page physical + * address + */ +static int mmu_l1_map(struct isp_mmu *mmu, phys_addr_t l1_pt, + unsigned int start, unsigned int end, + phys_addr_t phys) +{ + phys_addr_t l2_pt; + unsigned int ptr, l1_aligned; + unsigned int idx; + unsigned int l2_pte; + int ret; + + l1_pt &= ISP_PAGE_MASK; + + start = start & ISP_PAGE_MASK; + end = ISP_PAGE_ALIGN(end); + phys &= ISP_PAGE_MASK; + + ptr = start; + do { + idx = ISP_PTR_TO_L1_IDX(ptr); + + l2_pte = atomisp_get_pte(l1_pt, idx); + + if (!ISP_PTE_VALID(mmu, l2_pte)) { + l2_pt = alloc_page_table(mmu); + if (l2_pt == NULL_PAGE) { + dev_err(atomisp_dev, + "alloc page table fail.\n"); + + /* free all mapped pages */ + free_mmu_map(mmu, start, ptr); + + return -ENOMEM; + } + + l2_pte = isp_pgaddr_to_pte_valid(mmu, l2_pt); + + atomisp_set_pte(l1_pt, idx, l2_pte); + mmu->l2_pgt_refcount[idx] = 0; + } + + l2_pt = isp_pte_to_pgaddr(mmu, l2_pte); + + l1_aligned = (ptr & ISP_PAGE_MASK) + (1U << ISP_L1PT_OFFSET); + + if (l1_aligned < end) { + ret = mmu_l2_map(mmu, l1_pt, idx, + l2_pt, ptr, l1_aligned, phys); + phys += (l1_aligned - ptr); + ptr = l1_aligned; + } else { + ret = mmu_l2_map(mmu, l1_pt, idx, + l2_pt, ptr, end, phys); + phys += (end - ptr); + ptr = end; + } + + if (ret) { + dev_err(atomisp_dev, "setup mapping in L2PT fail.\n"); + + /* free all mapped pages */ + free_mmu_map(mmu, start, ptr); + + return -EINVAL; + } + } while (ptr < end && idx < ISP_L1PT_PTES); + + return 0; +} + +/* + * Update page table according to isp virtual address and page physical + * address + */ +static int mmu_map(struct isp_mmu *mmu, unsigned int isp_virt, + phys_addr_t phys, unsigned int pgnr) +{ + unsigned int start, end; + phys_addr_t l1_pt; + int ret; + + mutex_lock(&mmu->pt_mutex); + if (!ISP_PTE_VALID(mmu, mmu->l1_pte)) { + /* + * allocate 1 new page for L1 page table + */ + l1_pt = alloc_page_table(mmu); + if (l1_pt == NULL_PAGE) { + dev_err(atomisp_dev, "alloc page table fail.\n"); + mutex_unlock(&mmu->pt_mutex); + return -ENOMEM; + } + + /* + * setup L1 page table physical addr to MMU + */ + ret = mmu->driver->set_pd_base(mmu, l1_pt); + if (ret) { + dev_err(atomisp_dev, + "set page directory base address fail.\n"); + mutex_unlock(&mmu->pt_mutex); + return ret; + } + mmu->base_address = l1_pt; + mmu->l1_pte = isp_pgaddr_to_pte_valid(mmu, l1_pt); + memset(mmu->l2_pgt_refcount, 0, sizeof(int) * ISP_L1PT_PTES); + } + + l1_pt = isp_pte_to_pgaddr(mmu, mmu->l1_pte); + + start = (isp_virt) & ISP_PAGE_MASK; + end = start + (pgnr << ISP_PAGE_OFFSET); + phys &= ISP_PAGE_MASK; + + ret = mmu_l1_map(mmu, l1_pt, start, end, phys); + + if (ret) + dev_err(atomisp_dev, "setup mapping in L1PT fail.\n"); + + mutex_unlock(&mmu->pt_mutex); + return ret; +} + +/* + * Free L2 page table according to isp virtual address and page physical + * address + */ +static void mmu_l2_unmap(struct isp_mmu *mmu, phys_addr_t l1_pt, + unsigned int l1_idx, phys_addr_t l2_pt, + unsigned int start, unsigned int end) +{ + + unsigned int ptr; + unsigned int idx; + unsigned int pte; + + l2_pt &= ISP_PAGE_MASK; + + start = start & ISP_PAGE_MASK; + end = ISP_PAGE_ALIGN(end); + + ptr = start; + do { + idx = ISP_PTR_TO_L2_IDX(ptr); + + pte = atomisp_get_pte(l2_pt, idx); + + if (!ISP_PTE_VALID(mmu, pte)) + mmu_unmap_l2_pte_error(mmu, l1_pt, l1_idx, + l2_pt, idx, ptr, pte); + + atomisp_set_pte(l2_pt, idx, mmu->driver->null_pte); + mmu->l2_pgt_refcount[l1_idx]--; + ptr += (1U << ISP_L2PT_OFFSET); + } while (ptr < end && idx < ISP_L2PT_PTES - 1); + + if (mmu->l2_pgt_refcount[l1_idx] == 0) { + free_page_table(mmu, l2_pt); + atomisp_set_pte(l1_pt, l1_idx, mmu->driver->null_pte); + } +} + +/* + * Free L1 page table according to isp virtual address and page physical + * address + */ +static void mmu_l1_unmap(struct isp_mmu *mmu, phys_addr_t l1_pt, + unsigned int start, unsigned int end) +{ + phys_addr_t l2_pt; + unsigned int ptr, l1_aligned; + unsigned int idx; + unsigned int l2_pte; + + l1_pt &= ISP_PAGE_MASK; + + start = start & ISP_PAGE_MASK; + end = ISP_PAGE_ALIGN(end); + + ptr = start; + do { + idx = ISP_PTR_TO_L1_IDX(ptr); + + l2_pte = atomisp_get_pte(l1_pt, idx); + + if (!ISP_PTE_VALID(mmu, l2_pte)) { + mmu_unmap_l1_pte_error(mmu, l1_pt, idx, ptr, l2_pte); + continue; + } + + l2_pt = isp_pte_to_pgaddr(mmu, l2_pte); + + l1_aligned = (ptr & ISP_PAGE_MASK) + (1U << ISP_L1PT_OFFSET); + + if (l1_aligned < end) { + mmu_l2_unmap(mmu, l1_pt, idx, l2_pt, ptr, l1_aligned); + ptr = l1_aligned; + } else { + mmu_l2_unmap(mmu, l1_pt, idx, l2_pt, ptr, end); + ptr = end; + } + /* + * use the same L2 page next time, so we dont + * need to invalidate and free this PT. + */ + /* atomisp_set_pte(l1_pt, idx, NULL_PTE); */ + } while (ptr < end && idx < ISP_L1PT_PTES); +} + +/* + * Free page table according to isp virtual address and page physical + * address + */ +static void mmu_unmap(struct isp_mmu *mmu, unsigned int isp_virt, + unsigned int pgnr) +{ + unsigned int start, end; + phys_addr_t l1_pt; + + mutex_lock(&mmu->pt_mutex); + if (!ISP_PTE_VALID(mmu, mmu->l1_pte)) { + mmu_unmap_l1_pt_error(mmu, mmu->l1_pte); + mutex_unlock(&mmu->pt_mutex); + return; + } + + l1_pt = isp_pte_to_pgaddr(mmu, mmu->l1_pte); + + start = (isp_virt) & ISP_PAGE_MASK; + end = start + (pgnr << ISP_PAGE_OFFSET); + + mmu_l1_unmap(mmu, l1_pt, start, end); + mutex_unlock(&mmu->pt_mutex); +} + +/* + * Free page tables according to isp start virtual address and end virtual + * address. + */ +static void free_mmu_map(struct isp_mmu *mmu, unsigned int start_isp_virt, + unsigned int end_isp_virt) +{ + unsigned int pgnr; + unsigned int start, end; + + start = (start_isp_virt) & ISP_PAGE_MASK; + end = (end_isp_virt) & ISP_PAGE_MASK; + pgnr = (end - start) >> ISP_PAGE_OFFSET; + mmu_unmap(mmu, start, pgnr); +} + +int isp_mmu_map(struct isp_mmu *mmu, unsigned int isp_virt, + phys_addr_t phys, unsigned int pgnr) +{ + return mmu_map(mmu, isp_virt, phys, pgnr); +} + +void isp_mmu_unmap(struct isp_mmu *mmu, unsigned int isp_virt, + unsigned int pgnr) +{ + mmu_unmap(mmu, isp_virt, pgnr); +} + +static void isp_mmu_flush_tlb_range_default(struct isp_mmu *mmu, + unsigned int start, + unsigned int size) +{ + isp_mmu_flush_tlb(mmu); +} + +/*MMU init for internal structure*/ +int isp_mmu_init(struct isp_mmu *mmu, struct isp_mmu_client *driver) +{ + if (!mmu) /* error */ + return -EINVAL; + if (!driver) /* error */ + return -EINVAL; + + if (!driver->name) + dev_warn(atomisp_dev, "NULL name for MMU driver...\n"); + + mmu->driver = driver; + + if (!driver->set_pd_base || !driver->tlb_flush_all) { + dev_err(atomisp_dev, + "set_pd_base or tlb_flush_all operation " + "not provided.\n"); + return -EINVAL; + } + + if (!driver->tlb_flush_range) + driver->tlb_flush_range = isp_mmu_flush_tlb_range_default; + + if (!driver->pte_valid_mask) { + dev_err(atomisp_dev, "PTE_MASK is missing from mmu driver\n"); + return -EINVAL; + } + + mmu->l1_pte = driver->null_pte; + + mutex_init(&mmu->pt_mutex); + +#ifdef USE_KMEM_CACHE + mmu->tbl_cache = kmem_cache_create("iopte_cache", ISP_PAGE_SIZE, + ISP_PAGE_SIZE, SLAB_HWCACHE_ALIGN, + NULL); + if (!mmu->tbl_cache) + return -ENOMEM; +#endif + + return 0; +} + +/*Free L1 and L2 page table*/ +void isp_mmu_exit(struct isp_mmu *mmu) +{ + unsigned int idx; + unsigned int pte; + phys_addr_t l1_pt, l2_pt; + + if (!mmu) + return; + + if (!ISP_PTE_VALID(mmu, mmu->l1_pte)) { + dev_warn(atomisp_dev, "invalid L1PT: pte = 0x%x\n", + (unsigned int)mmu->l1_pte); + return; + } + + l1_pt = isp_pte_to_pgaddr(mmu, mmu->l1_pte); + + for (idx = 0; idx < ISP_L1PT_PTES; idx++) { + pte = atomisp_get_pte(l1_pt, idx); + + if (ISP_PTE_VALID(mmu, pte)) { + l2_pt = isp_pte_to_pgaddr(mmu, pte); + + free_page_table(mmu, l2_pt); + } + } + + free_page_table(mmu, l1_pt); + +#ifdef USE_KMEM_CACHE + kmem_cache_destroy(mmu->tbl_cache); +#endif +} diff --git a/drivers/staging/media/atomisp/pci/atomisp2/mmu/sh_mmu_mrfld.c b/drivers/staging/media/atomisp/pci/atomisp2/mmu/sh_mmu_mrfld.c new file mode 100644 index 0000000000000000000000000000000000000000..97546bd124cd2ae539b57a3a0ff49eaef4e84568 --- /dev/null +++ b/drivers/staging/media/atomisp/pci/atomisp2/mmu/sh_mmu_mrfld.c @@ -0,0 +1,93 @@ +/* + * Support for Merrifield PNW Camera Imaging ISP subsystem. + * + * Copyright (c) 2012 Intel Corporation. All Rights Reserved. + * + * Copyright (c) 2012 Silicon Hive www.siliconhive.com. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License version + * 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA + * 02110-1301, USA. + * + */ +#include "type_support.h" +#include "mmu/isp_mmu.h" +#include "memory_access/memory_access.h" +#include "atomisp_compat.h" + +#define MERR_VALID_PTE_MASK 0x80000000 + +/* + * include SH header file here + */ + +static unsigned int sh_phys_to_pte(struct isp_mmu *mmu, + phys_addr_t phys) +{ + return phys >> ISP_PAGE_OFFSET; +} + +static phys_addr_t sh_pte_to_phys(struct isp_mmu *mmu, + unsigned int pte) +{ + unsigned int mask = mmu->driver->pte_valid_mask; + return (phys_addr_t)((pte & ~mask) << ISP_PAGE_OFFSET); +} + +/* + * set page directory base address (physical address). + * + * must be provided. + */ +static int sh_set_pd_base(struct isp_mmu *mmu, + phys_addr_t phys) +{ + unsigned int pte = sh_phys_to_pte(mmu, phys); + /*mmgr_set_base_address(HOST_ADDRESS(pte));*/ + atomisp_css_mmu_set_page_table_base_index(HOST_ADDRESS(pte)); + return 0; +} + +static unsigned int sh_get_pd_base(struct isp_mmu *mmu, + phys_addr_t phys) +{ + unsigned int pte = sh_phys_to_pte(mmu, phys); + return HOST_ADDRESS(pte); +} + +/* + * callback to flush tlb. + * + * tlb_flush_range will at least flush TLBs containing + * address mapping from addr to addr + size. + * + * tlb_flush_all will flush all TLBs. + * + * tlb_flush_all is must be provided. if tlb_flush_range is + * not valid, it will set to tlb_flush_all by default. + */ +static void sh_tlb_flush(struct isp_mmu *mmu) +{ + atomisp_css_mmu_invalidate_cache(); +} + +struct isp_mmu_client sh_mmu_mrfld = { + .name = "Silicon Hive ISP3000 MMU", + .pte_valid_mask = MERR_VALID_PTE_MASK, + .null_pte = ~MERR_VALID_PTE_MASK, + .set_pd_base = sh_set_pd_base, + .get_pd_base = sh_get_pd_base, + .tlb_flush_all = sh_tlb_flush, + .phys_to_pte = sh_phys_to_pte, + .pte_to_phys = sh_pte_to_phys, +}; diff --git a/drivers/staging/media/atomisp/platform/Makefile b/drivers/staging/media/atomisp/platform/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..df157630bda90e38c2f910cd76987543523ce673 --- /dev/null +++ b/drivers/staging/media/atomisp/platform/Makefile @@ -0,0 +1,6 @@ +# +# Makefile for camera drivers. +# + +obj-$(CONFIG_INTEL_ATOMISP) += clock/ +obj-$(CONFIG_INTEL_ATOMISP) += intel-mid/ diff --git a/drivers/staging/media/atomisp/platform/clock/Makefile b/drivers/staging/media/atomisp/platform/clock/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..82fbe8b6968a3313edfc33077f049e18c66e0f57 --- /dev/null +++ b/drivers/staging/media/atomisp/platform/clock/Makefile @@ -0,0 +1,6 @@ +# +# Makefile for clock devices. +# + +obj-$(CONFIG_INTEL_ATOMISP) += vlv2_plat_clock.o +obj-$(CONFIG_INTEL_ATOMISP) += platform_vlv2_plat_clk.o diff --git a/drivers/staging/media/atomisp/platform/clock/platform_vlv2_plat_clk.c b/drivers/staging/media/atomisp/platform/clock/platform_vlv2_plat_clk.c new file mode 100644 index 0000000000000000000000000000000000000000..0aae9b0283bbae865bff6748858ef85de87c8a6f --- /dev/null +++ b/drivers/staging/media/atomisp/platform/clock/platform_vlv2_plat_clk.c @@ -0,0 +1,40 @@ +/* + * platform_vlv2_plat_clk.c - VLV2 platform clock driver + * Copyright (C) 2013 Intel Corporation + * + * Author: Asutosh Pathak + * Author: Chandra Sekhar Anagani + * Author: Sergio Aguirre + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + */ + +#include +#include +#include +#include +#include + +static int __init vlv2_plat_clk_init(void) +{ + struct platform_device *pdev; + + pdev = platform_device_register_simple("vlv2_plat_clk", -1, NULL, 0); + if (IS_ERR(pdev)) { + pr_err("platform_vlv2_plat_clk:register failed: %ld\n", + PTR_ERR(pdev)); + return PTR_ERR(pdev); + } + + return 0; +} + +device_initcall(vlv2_plat_clk_init); diff --git a/drivers/staging/media/atomisp/platform/clock/platform_vlv2_plat_clk.h b/drivers/staging/media/atomisp/platform/clock/platform_vlv2_plat_clk.h new file mode 100644 index 0000000000000000000000000000000000000000..b730ab0e8223c4513ea39f0762bb56d10df1b45d --- /dev/null +++ b/drivers/staging/media/atomisp/platform/clock/platform_vlv2_plat_clk.h @@ -0,0 +1,27 @@ +/* + * platform_vlv2_plat_clk.h: platform clock driver library header file + * Copyright (C) 2013 Intel Corporation + * + * Author: Asutosh Pathak + * Author: Chandra Sekhar Anagani + * Author: Sergio Aguirre + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + */ +#ifndef _PLATFORM_VLV2_PLAT_CLK_H_ +#define _PLATFORM_VLV2_PLAT_CLK_H_ + +#include +#include + +extern void __init *vlv2_plat_clk_device_platform_data( + void *info) __attribute__((weak)); +#endif diff --git a/drivers/staging/media/atomisp/platform/clock/vlv2_plat_clock.c b/drivers/staging/media/atomisp/platform/clock/vlv2_plat_clock.c new file mode 100644 index 0000000000000000000000000000000000000000..01bef3570e215239d9db74d09c8624fd5d8d2dfd --- /dev/null +++ b/drivers/staging/media/atomisp/platform/clock/vlv2_plat_clock.c @@ -0,0 +1,266 @@ +/* + * vlv2_plat_clock.c - VLV2 platform clock driver + * Copyright (C) 2013 Intel Corporation + * + * Author: Asutosh Pathak + * Author: Chandra Sekhar Anagani + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, but + * WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA. + */ + +#include +#include +#include +#include + +/* NOTE: Most of below constants could come from platform data. + * To be fixed when appropriate ACPI support comes. + */ +#define VLV2_PMC_CLK_BASE_ADDRESS 0xfed03060 +#define PLT_CLK_CTL_OFFSET(x) (0x04 * (x)) + +#define CLK_CONFG_BIT_POS 0 +#define CLK_CONFG_BIT_LEN 2 +#define CLK_CONFG_D3_GATED 0 +#define CLK_CONFG_FORCE_ON 1 +#define CLK_CONFG_FORCE_OFF 2 + +#define CLK_FREQ_TYPE_BIT_POS 2 +#define CLK_FREQ_TYPE_BIT_LEN 1 +#define CLK_FREQ_TYPE_XTAL 0 /* 25 MHz */ +#define CLK_FREQ_TYPE_PLL 1 /* 19.2 MHz */ + +#define MAX_CLK_COUNT 5 + +/* Helper macros to manipulate bitfields */ +#define REG_MASK(n) (((1 << (n##_BIT_LEN)) - 1) << (n##_BIT_POS)) +#define REG_SET_FIELD(r, n, v) (((r) & ~REG_MASK(n)) | \ + (((v) << (n##_BIT_POS)) & REG_MASK(n))) +#define REG_GET_FIELD(r, n) (((r) & REG_MASK(n)) >> n##_BIT_POS) +/* + * vlv2 platform has 6 platform clocks, controlled by 4 byte registers + * Total size required for mapping is 6*4 = 24 bytes + */ +#define PMC_MAP_SIZE 24 + +static DEFINE_MUTEX(clk_mutex); +static void __iomem *pmc_base; + +/* + * vlv2_plat_set_clock_freq - Set clock frequency to a specified platform clock + * @clk_num: Platform clock number (i.e. 0, 1, 2, ...,5) + * @freq_type: Clock frequency (0-25 MHz(XTAL), 1-19.2 MHz(PLL) ) + */ +int vlv2_plat_set_clock_freq(int clk_num, int freq_type) +{ + void __iomem *addr; + + if (clk_num < 0 && clk_num > MAX_CLK_COUNT) { + pr_err("Clock number out of range (%d)\n", clk_num); + return -EINVAL; + } + + if (freq_type != CLK_FREQ_TYPE_XTAL && + freq_type != CLK_FREQ_TYPE_PLL) { + pr_err("wrong clock type\n"); + return -EINVAL; + } + + if (!pmc_base) { + pr_err("memio map is not set\n"); + return -EINVAL; + } + + addr = pmc_base + PLT_CLK_CTL_OFFSET(clk_num); + + mutex_lock(&clk_mutex); + writel(REG_SET_FIELD(readl(addr), CLK_FREQ_TYPE, freq_type), addr); + mutex_unlock(&clk_mutex); + + return 0; +} +EXPORT_SYMBOL_GPL(vlv2_plat_set_clock_freq); + +/* + * vlv2_plat_get_clock_freq - Get the status of specified platform clock + * @clk_num: Platform clock number (i.e. 0, 1, 2, ...,5) + * + * Returns 0 for 25 MHz(XTAL) and 1 for 19.2 MHz(PLL) + */ +int vlv2_plat_get_clock_freq(int clk_num) +{ + u32 ret; + + if (clk_num < 0 && clk_num > MAX_CLK_COUNT) { + pr_err("Clock number out of range (%d)\n", clk_num); + return -EINVAL; + } + + if (!pmc_base) { + pr_err("memio map is not set\n"); + return -EINVAL; + } + + mutex_lock(&clk_mutex); + ret = REG_GET_FIELD(readl(pmc_base + PLT_CLK_CTL_OFFSET(clk_num)), + CLK_FREQ_TYPE); + mutex_unlock(&clk_mutex); + return ret; +} +EXPORT_SYMBOL_GPL(vlv2_plat_get_clock_freq); + +/* + * vlv2_plat_configure_clock - Configure the specified platform clock + * @clk_num: Platform clock number (i.e. 0, 1, 2, ...,5) + * @conf: Clock gating: + * 0 - Clock gated on D3 state + * 1 - Force on + * 2,3 - Force off + */ +int vlv2_plat_configure_clock(int clk_num, u32 conf) +{ + void __iomem *addr; + + if (clk_num < 0 && clk_num > MAX_CLK_COUNT) { + pr_err("Clock number out of range (%d)\n", clk_num); + return -EINVAL; + } + + if (conf != CLK_CONFG_D3_GATED && + conf != CLK_CONFG_FORCE_ON && + conf != CLK_CONFG_FORCE_OFF) { + pr_err("Invalid clock configuration requested\n"); + return -EINVAL; + } + + if (!pmc_base) { + pr_err("memio map is not set\n"); + return -EINVAL; + } + + addr = pmc_base + PLT_CLK_CTL_OFFSET(clk_num); + + mutex_lock(&clk_mutex); + writel(REG_SET_FIELD(readl(addr), CLK_CONFG, conf), addr); + mutex_unlock(&clk_mutex); + return 0; +} +EXPORT_SYMBOL_GPL(vlv2_plat_configure_clock); + +/* + * vlv2_plat_get_clock_status - Get the status of specified platform clock + * @clk_num: Platform clock number (i.e. 0, 1, 2, ...,5) + * + * Returns 1 - On, 0 - Off + */ +int vlv2_plat_get_clock_status(int clk_num) +{ + int ret; + + if (clk_num < 0 && clk_num > MAX_CLK_COUNT) { + pr_err("Clock number out of range (%d)\n", clk_num); + return -EINVAL; + } + + if (!pmc_base) { + pr_err("memio map is not set\n"); + return -EINVAL; + } + + mutex_lock(&clk_mutex); + ret = (int)REG_GET_FIELD(readl(pmc_base + PLT_CLK_CTL_OFFSET(clk_num)), + CLK_CONFG); + mutex_unlock(&clk_mutex); + return ret; +} +EXPORT_SYMBOL_GPL(vlv2_plat_get_clock_status); + +static int vlv2_plat_clk_probe(struct platform_device *pdev) +{ + int i = 0; + + pmc_base = ioremap_nocache(VLV2_PMC_CLK_BASE_ADDRESS, PMC_MAP_SIZE); + if (!pmc_base) { + dev_err(&pdev->dev, "I/O memory remapping failed\n"); + return -ENOMEM; + } + + /* Initialize all clocks as disabled */ + for (i = 0; i < MAX_CLK_COUNT; i++) + vlv2_plat_configure_clock(i, CLK_CONFG_FORCE_OFF); + + dev_info(&pdev->dev, "vlv2_plat_clk initialized\n"); + return 0; +} + +static int vlv2_plat_clk_remove(struct platform_device *pdev) +{ + iounmap(pmc_base); + pmc_base = NULL; + return 0; +} + +static const struct platform_device_id vlv2_plat_clk_id[] = { + {"vlv2_plat_clk", 0}, + {} +}; +MODULE_DEVICE_TABLE(platform, vlv2_plat_clk_id); + +static int vlv2_resume(struct device *device) +{ + int i; + + /* Initialize all clocks as disabled */ + for (i = 0; i < MAX_CLK_COUNT; i++) + vlv2_plat_configure_clock(i, CLK_CONFG_FORCE_OFF); + + return 0; +} + +static int vlv2_suspend(struct device *device) +{ + return 0; +} + +static const struct dev_pm_ops vlv2_pm_ops = { + .suspend = vlv2_suspend, + .resume = vlv2_resume, +}; + +static struct platform_driver vlv2_plat_clk_driver = { + .probe = vlv2_plat_clk_probe, + .remove = vlv2_plat_clk_remove, + .id_table = vlv2_plat_clk_id, + .driver = { + .name = "vlv2_plat_clk", + .pm = &vlv2_pm_ops, + .owner = THIS_MODULE, + }, +}; + +static int __init vlv2_plat_clk_init(void) +{ + return platform_driver_register(&vlv2_plat_clk_driver); +} +arch_initcall(vlv2_plat_clk_init); + +static void __exit vlv2_plat_clk_exit(void) +{ + platform_driver_unregister(&vlv2_plat_clk_driver); +} +module_exit(vlv2_plat_clk_exit); + +MODULE_AUTHOR("Asutosh Pathak "); +MODULE_DESCRIPTION("Intel VLV2 platform clock driver"); +MODULE_LICENSE("GPL v2"); diff --git a/drivers/staging/media/atomisp/platform/intel-mid/Makefile b/drivers/staging/media/atomisp/platform/intel-mid/Makefile new file mode 100644 index 0000000000000000000000000000000000000000..4621261c35dbc13919f526b279e30a927fd92679 --- /dev/null +++ b/drivers/staging/media/atomisp/platform/intel-mid/Makefile @@ -0,0 +1,5 @@ +# +# Makefile for intel-mid devices. +# +obj-$(CONFIG_INTEL_ATOMISP) += intel_mid_pcihelpers.o +obj-$(CONFIG_INTEL_ATOMISP) += atomisp_gmin_platform.o diff --git a/drivers/staging/media/atomisp/platform/intel-mid/atomisp_gmin_platform.c b/drivers/staging/media/atomisp/platform/intel-mid/atomisp_gmin_platform.c new file mode 100644 index 0000000000000000000000000000000000000000..39765bd081e2f5c9648d6d826989989902816791 --- /dev/null +++ b/drivers/staging/media/atomisp/platform/intel-mid/atomisp_gmin_platform.c @@ -0,0 +1,760 @@ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MAX_SUBDEVS 8 + +/* Should be defined in vlv2_plat_clock API, isn't: */ +#define VLV2_CLK_PLL_19P2MHZ 1 +#define VLV2_CLK_XTAL_19P2MHZ 0 +#define VLV2_CLK_ON 1 +#define VLV2_CLK_OFF 2 +#define ELDO1_SEL_REG 0x19 +#define ELDO1_1P8V 0x16 +#define ELDO1_CTRL_SHIFT 0x00 +#define ELDO2_SEL_REG 0x1a +#define ELDO2_1P8V 0x16 +#define ELDO2_CTRL_SHIFT 0x01 + + +struct gmin_subdev { + struct v4l2_subdev *subdev; + int clock_num; + int clock_src; + struct gpio_desc *gpio0; + struct gpio_desc *gpio1; + struct regulator *v1p8_reg; + struct regulator *v2p8_reg; + struct regulator *v1p2_reg; + struct regulator *v2p8_vcm_reg; + enum atomisp_camera_port csi_port; + unsigned int csi_lanes; + enum atomisp_input_format csi_fmt; + enum atomisp_bayer_order csi_bayer; + bool v1p8_on; + bool v2p8_on; + bool v1p2_on; + bool v2p8_vcm_on; +}; + +static struct gmin_subdev gmin_subdevs[MAX_SUBDEVS]; + +static enum { PMIC_UNSET = 0, PMIC_REGULATOR, PMIC_AXP, PMIC_TI , + PMIC_CRYSTALCOVE } pmic_id; + +/* The atomisp uses type==0 for the end-of-list marker, so leave space. */ +static struct intel_v4l2_subdev_table pdata_subdevs[MAX_SUBDEVS+1]; + +static const struct atomisp_platform_data pdata = { + .subdevs = pdata_subdevs, +}; + +/* + * Something of a hack. The ECS E7 board drives camera 2.8v from an + * external regulator instead of the PMIC. There's a gmin_CamV2P8 + * config variable that specifies the GPIO to handle this particular + * case, but this needs a broader architecture for handling camera + * power. + */ +enum { V2P8_GPIO_UNSET = -2, V2P8_GPIO_NONE = -1 }; +static int v2p8_gpio = V2P8_GPIO_UNSET; + +/* + * Something of a hack. The CHT RVP board drives camera 1.8v from an + * external regulator instead of the PMIC just like ECS E7 board, see the + * comments above. + */ +enum { V1P8_GPIO_UNSET = -2, V1P8_GPIO_NONE = -1 }; +static int v1p8_gpio = V1P8_GPIO_UNSET; + +static LIST_HEAD(vcm_devices); +static DEFINE_MUTEX(vcm_lock); + +static struct gmin_subdev *find_gmin_subdev(struct v4l2_subdev *subdev); + +/* + * Legacy/stub behavior copied from upstream platform_camera.c. The + * atomisp driver relies on these values being non-NULL in a few + * places, even though they are hard-coded in all current + * implementations. + */ +const struct atomisp_camera_caps *atomisp_get_default_camera_caps(void) +{ + static const struct atomisp_camera_caps caps = { + .sensor_num = 1, + .sensor = { + { .stream_num = 1, }, + }, + }; + return ∩︀ +} +EXPORT_SYMBOL_GPL(atomisp_get_default_camera_caps); + +const struct atomisp_platform_data *atomisp_get_platform_data(void) +{ + return &pdata; +} +EXPORT_SYMBOL_GPL(atomisp_get_platform_data); + +static int af_power_ctrl(struct v4l2_subdev *subdev, int flag) +{ + struct gmin_subdev *gs = find_gmin_subdev(subdev); + + if (gs && gs->v2p8_vcm_on == flag) + return 0; + gs->v2p8_vcm_on = flag; + + /* + * The power here is used for dw9817, + * regulator is from rear sensor + */ + if (gs->v2p8_vcm_reg) { + if (flag) + return regulator_enable(gs->v2p8_vcm_reg); + else + return regulator_disable(gs->v2p8_vcm_reg); + } + return 0; +} + +/* + * Used in a handful of modules. Focus motor control, I think. Note + * that there is no configurability in the API, so this needs to be + * fixed where it is used. + * + * struct camera_af_platform_data { + * int (*power_ctrl)(struct v4l2_subdev *subdev, int flag); + * }; + * + * Note that the implementation in MCG platform_camera.c is stubbed + * out anyway (i.e. returns zero from the callback) on BYT. So + * neither needed on gmin platforms or supported upstream. + */ +const struct camera_af_platform_data *camera_get_af_platform_data(void) +{ + static struct camera_af_platform_data afpd = { + .power_ctrl = af_power_ctrl, + }; + return &afpd; +} +EXPORT_SYMBOL_GPL(camera_get_af_platform_data); + +int atomisp_register_i2c_module(struct v4l2_subdev *subdev, + struct camera_sensor_platform_data *plat_data, + enum intel_v4l2_subdev_type type) +{ + int i; + struct i2c_board_info *bi; + struct gmin_subdev *gs; + struct i2c_client *client = v4l2_get_subdevdata(subdev); + struct acpi_device *adev; + + dev_info(&client->dev, "register atomisp i2c module type %d\n", type); + + /* The windows driver model (and thus most BIOSes by default) + * uses ACPI runtime power management for camera devices, but + * we don't. Disable it, or else the rails will be needlessly + * tickled during suspend/resume. This has caused power and + * performance issues on multiple devices. */ + adev = ACPI_COMPANION(&client->dev); + if (adev) + adev->power.flags.power_resources = 0; + + for (i=0; i < MAX_SUBDEVS; i++) + if (!pdata.subdevs[i].type) + break; + + if (pdata.subdevs[i].type) + return -ENOMEM; + + /* Note subtlety of initialization order: at the point where + * this registration API gets called, the platform data + * callbacks have probably already been invoked, so the + * gmin_subdev struct is already initialized for us. */ + gs = find_gmin_subdev(subdev); + + pdata.subdevs[i].type = type; + pdata.subdevs[i].port = gs->csi_port; + pdata.subdevs[i].subdev = subdev; + pdata.subdevs[i].v4l2_subdev.i2c_adapter_id = client->adapter->nr; + + /* Convert i2c_client to i2c_board_info */ + bi = &pdata.subdevs[i].v4l2_subdev.board_info; + memcpy(bi->type, client->name, I2C_NAME_SIZE); + bi->flags = client->flags; + bi->addr = client->addr; + bi->irq = client->irq; + bi->platform_data = plat_data; + + return 0; +} +EXPORT_SYMBOL_GPL(atomisp_register_i2c_module); + +struct v4l2_subdev *atomisp_gmin_find_subdev(struct i2c_adapter *adapter, + struct i2c_board_info *board_info) +{ + int i; + for (i=0; i < MAX_SUBDEVS && pdata.subdevs[i].type; i++) { + struct intel_v4l2_subdev_table *sd = &pdata.subdevs[i]; + if (sd->v4l2_subdev.i2c_adapter_id == adapter->nr && + sd->v4l2_subdev.board_info.addr == board_info->addr) + return sd->subdev; + } + return NULL; +} +EXPORT_SYMBOL_GPL(atomisp_gmin_find_subdev); + +int atomisp_gmin_remove_subdev(struct v4l2_subdev *sd) +{ + int i, j; + + if (!sd) + return 0; + + for (i = 0; i < MAX_SUBDEVS; i++) { + if (pdata.subdevs[i].subdev == sd) { + for (j = i + 1; j <= MAX_SUBDEVS; j++) + pdata.subdevs[j - 1] = pdata.subdevs[j]; + } + if (gmin_subdevs[i].subdev == sd) { + if (gmin_subdevs[i].gpio0) + gpiod_put(gmin_subdevs[i].gpio0); + gmin_subdevs[i].gpio0 = NULL; + if (gmin_subdevs[i].gpio1) + gpiod_put(gmin_subdevs[i].gpio1); + gmin_subdevs[i].gpio1 = NULL; + if (pmic_id == PMIC_REGULATOR) { + regulator_put(gmin_subdevs[i].v1p8_reg); + regulator_put(gmin_subdevs[i].v2p8_reg); + regulator_put(gmin_subdevs[i].v1p2_reg); + regulator_put(gmin_subdevs[i].v2p8_vcm_reg); + } + gmin_subdevs[i].subdev = NULL; + } + } + return 0; +} +EXPORT_SYMBOL_GPL(atomisp_gmin_remove_subdev); + +struct gmin_cfg_var { + const char *name, *val; +}; + +static const struct gmin_cfg_var ffrd8_vars[] = { + { "INTCF1B:00_ImxId", "0x134" }, + { "INTCF1B:00_CsiPort", "1" }, + { "INTCF1B:00_CsiLanes", "4" }, + { "INTCF1B:00_CamClk", "0" }, + {}, +}; + +/* Cribbed from MCG defaults in the mt9m114 driver, not actually verified + * vs. T100 hardware */ +static const struct gmin_cfg_var t100_vars[] = { + { "INT33F0:00_CsiPort", "0" }, + { "INT33F0:00_CsiLanes", "1" }, + { "INT33F0:00_CamClk", "1" }, + {}, +}; + +static const struct gmin_cfg_var mrd7_vars[] = { + {"INT33F8:00_CamType", "1"}, + {"INT33F8:00_CsiPort", "1"}, + {"INT33F8:00_CsiLanes","2"}, + {"INT33F8:00_CsiFmt","13"}, + {"INT33F8:00_CsiBayer", "0"}, + {"INT33F8:00_CamClk", "0"}, + {"INT33F9:00_CamType", "1"}, + {"INT33F9:00_CsiPort", "0"}, + {"INT33F9:00_CsiLanes","1"}, + {"INT33F9:00_CsiFmt","13"}, + {"INT33F9:00_CsiBayer", "0"}, + {"INT33F9:00_CamClk", "1"}, + {}, +}; + +static const struct gmin_cfg_var ecs7_vars[] = { + {"INT33BE:00_CsiPort", "1"}, + {"INT33BE:00_CsiLanes","2"}, + {"INT33BE:00_CsiFmt","13"}, + {"INT33BE:00_CsiBayer", "2"}, + {"INT33BE:00_CamClk", "0"}, + {"INT33F0:00_CsiPort", "0"}, + {"INT33F0:00_CsiLanes","1"}, + {"INT33F0:00_CsiFmt","13"}, + {"INT33F0:00_CsiBayer", "0"}, + {"INT33F0:00_CamClk", "1"}, + {"gmin_V2P8GPIO","402"}, + {}, +}; + + +static const struct gmin_cfg_var i8880_vars[] = { + {"XXOV2680:00_CsiPort", "1"}, + {"XXOV2680:00_CsiLanes","1"}, + {"XXOV2680:00_CamClk","0"}, + {"XXGC0310:00_CsiPort", "0"}, + {"XXGC0310:00_CsiLanes", "1"}, + {"XXGC0310:00_CamClk", "1"}, + {}, +}; + +static const struct { + const char *dmi_board_name; + const struct gmin_cfg_var *vars; +} hard_vars[] = { + { "BYT-T FFD8", ffrd8_vars }, + { "T100TA", t100_vars }, + { "MRD7", mrd7_vars }, + { "ST70408", ecs7_vars }, + { "VTA0803", i8880_vars }, +}; + + +#define GMIN_CFG_VAR_EFI_GUID EFI_GUID(0xecb54cd9, 0xe5ae, 0x4fdc, \ + 0xa9, 0x71, 0xe8, 0x77, \ + 0x75, 0x60, 0x68, 0xf7) + +#define CFG_VAR_NAME_MAX 64 + +static int gmin_platform_init(struct i2c_client *client) +{ + return 0; +} + +static int gmin_platform_deinit(void) +{ + return 0; +} + +static struct gmin_subdev *gmin_subdev_add(struct v4l2_subdev *subdev) +{ + int i, ret; + struct device *dev; + struct i2c_client *client = v4l2_get_subdevdata(subdev); + + if (!pmic_id) { + + pmic_id = PMIC_REGULATOR; + } + + if (!client) + return NULL; + + dev = client ? &client->dev : NULL; + + for (i=0; i < MAX_SUBDEVS && gmin_subdevs[i].subdev; i++) + ; + if (i >= MAX_SUBDEVS) + return NULL; + + dev_info(dev, + "gmin: initializing atomisp module subdev data.PMIC ID %d\n", + pmic_id); + + gmin_subdevs[i].subdev = subdev; + gmin_subdevs[i].clock_num = gmin_get_var_int(dev, "CamClk", 0); + /*WA:CHT requires XTAL clock as PLL is not stable.*/ + gmin_subdevs[i].clock_src = gmin_get_var_int(dev, "ClkSrc", + VLV2_CLK_PLL_19P2MHZ); + gmin_subdevs[i].csi_port = gmin_get_var_int(dev, "CsiPort", 0); + gmin_subdevs[i].csi_lanes = gmin_get_var_int(dev, "CsiLanes", 1); + gmin_subdevs[i].gpio0 = gpiod_get_index(dev, NULL, 0, GPIOD_OUT_LOW); + gmin_subdevs[i].gpio1 = gpiod_get_index(dev, NULL, 1, GPIOD_OUT_LOW); + + if (!IS_ERR(gmin_subdevs[i].gpio0)) { + ret = gpiod_direction_output(gmin_subdevs[i].gpio0, 0); + if (ret) + dev_err(dev, "gpio0 set output failed: %d\n", ret); + } else { + gmin_subdevs[i].gpio0 = NULL; + } + + if (!IS_ERR(gmin_subdevs[i].gpio1)) { + ret = gpiod_direction_output(gmin_subdevs[i].gpio1, 0); + if (ret) + dev_err(dev, "gpio1 set output failed: %d\n", ret); + } else { + gmin_subdevs[i].gpio1 = NULL; + } + + if (pmic_id == PMIC_REGULATOR) { + gmin_subdevs[i].v1p8_reg = regulator_get(dev, "V1P8SX"); + gmin_subdevs[i].v2p8_reg = regulator_get(dev, "V2P8SX"); + gmin_subdevs[i].v1p2_reg = regulator_get(dev, "V1P2A"); + gmin_subdevs[i].v2p8_vcm_reg = regulator_get(dev, "VPROG4B"); + + /* Note: ideally we would initialize v[12]p8_on to the + * output of regulator_is_enabled(), but sadly that + * API is broken with the current drivers, returning + * "1" for a regulator that will then emit a + * "unbalanced disable" WARNing if we try to disable + * it. */ + } + + return &gmin_subdevs[i]; +} + +static struct gmin_subdev *find_gmin_subdev(struct v4l2_subdev *subdev) +{ + int i; + for (i=0; i < MAX_SUBDEVS; i++) + if (gmin_subdevs[i].subdev == subdev) + return &gmin_subdevs[i]; + return gmin_subdev_add(subdev); +} + +static int gmin_gpio0_ctrl(struct v4l2_subdev *subdev, int on) +{ + struct gmin_subdev *gs = find_gmin_subdev(subdev); + if (gs && gs->gpio0) { + gpiod_set_value(gs->gpio0, on); + return 0; + } + return -EINVAL; +} + +static int gmin_gpio1_ctrl(struct v4l2_subdev *subdev, int on) +{ + struct gmin_subdev *gs = find_gmin_subdev(subdev); + if (gs && gs->gpio1) { + gpiod_set_value(gs->gpio1, on); + return 0; + } + return -EINVAL; +} + +int gmin_v1p2_ctrl(struct v4l2_subdev *subdev, int on) +{ + struct gmin_subdev *gs = find_gmin_subdev(subdev); + + if (gs && gs->v1p2_on == on) + return 0; + gs->v1p2_on = on; + + if (gs->v1p2_reg) { + if (on) + return regulator_enable(gs->v1p2_reg); + else + return regulator_disable(gs->v1p2_reg); + } + + /*TODO:v1p2 needs to extend to other PMICs*/ + + return -EINVAL; +} +int gmin_v1p8_ctrl(struct v4l2_subdev *subdev, int on) +{ + struct gmin_subdev *gs = find_gmin_subdev(subdev); + int ret; + + if (v1p8_gpio == V1P8_GPIO_UNSET) { + v1p8_gpio = gmin_get_var_int(NULL, "V1P8GPIO", V1P8_GPIO_NONE); + if (v1p8_gpio != V1P8_GPIO_NONE) { + pr_info("atomisp_gmin_platform: 1.8v power on GPIO %d\n", + v1p8_gpio); + ret = gpio_request(v1p8_gpio, "camera_v1p8_en"); + if (!ret) + ret = gpio_direction_output(v1p8_gpio, 0); + if (ret) + pr_err("V1P8 GPIO initialization failed\n"); + } + } + + if (gs && gs->v1p8_on == on) + return 0; + gs->v1p8_on = on; + + if (v1p8_gpio >= 0) + gpio_set_value(v1p8_gpio, on); + + if (gs->v1p8_reg) { + regulator_set_voltage(gs->v1p8_reg, 1800000, 1800000); + if (on) + return regulator_enable(gs->v1p8_reg); + else + return regulator_disable(gs->v1p8_reg); + } + + + return -EINVAL; +} + +int gmin_v2p8_ctrl(struct v4l2_subdev *subdev, int on) +{ + struct gmin_subdev *gs = find_gmin_subdev(subdev); + int ret; + + if (v2p8_gpio == V2P8_GPIO_UNSET) { + v2p8_gpio = gmin_get_var_int(NULL, "V2P8GPIO", V2P8_GPIO_NONE); + if (v2p8_gpio != V2P8_GPIO_NONE) { + pr_info("atomisp_gmin_platform: 2.8v power on GPIO %d\n", + v2p8_gpio); + ret = gpio_request(v2p8_gpio, "camera_v2p8"); + if (!ret) + ret = gpio_direction_output(v2p8_gpio, 0); + if (ret) + pr_err("V2P8 GPIO initialization failed\n"); + } + } + + if (gs && gs->v2p8_on == on) + return 0; + gs->v2p8_on = on; + + if (v2p8_gpio >= 0) + gpio_set_value(v2p8_gpio, on); + + if (gs->v2p8_reg) { + regulator_set_voltage(gs->v2p8_reg, 2900000, 2900000); + if (on) + return regulator_enable(gs->v2p8_reg); + else + return regulator_disable(gs->v2p8_reg); + } + + return -EINVAL; +} + +int gmin_flisclk_ctrl(struct v4l2_subdev *subdev, int on) +{ + int ret = 0; + struct gmin_subdev *gs = find_gmin_subdev(subdev); + if (on) + ret = vlv2_plat_set_clock_freq(gs->clock_num, gs->clock_src); + if (ret) + return ret; + return vlv2_plat_configure_clock(gs->clock_num, + on ? VLV2_CLK_ON : VLV2_CLK_OFF); +} + +static int gmin_csi_cfg(struct v4l2_subdev *sd, int flag) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct gmin_subdev *gs = find_gmin_subdev(sd); + + if (!client || !gs) + return -ENODEV; + + return camera_sensor_csi(sd, gs->csi_port, gs->csi_lanes, + gs->csi_fmt, gs->csi_bayer, flag); +} + +static struct camera_vcm_control *gmin_get_vcm_ctrl(struct v4l2_subdev *subdev, + char *camera_module) +{ + struct i2c_client *client = v4l2_get_subdevdata(subdev); + struct gmin_subdev *gs = find_gmin_subdev(subdev); + struct camera_vcm_control *vcm; + + if (client == NULL || gs == NULL) + return NULL; + + if (!camera_module) + return NULL; + + mutex_lock(&vcm_lock); + list_for_each_entry(vcm, &vcm_devices, list) { + if (!strcmp(camera_module, vcm->camera_module)) { + mutex_unlock(&vcm_lock); + return vcm; + } + } + + mutex_unlock(&vcm_lock); + return NULL; +} + +static struct camera_sensor_platform_data gmin_plat = { + .gpio0_ctrl = gmin_gpio0_ctrl, + .gpio1_ctrl = gmin_gpio1_ctrl, + .v1p8_ctrl = gmin_v1p8_ctrl, + .v2p8_ctrl = gmin_v2p8_ctrl, + .v1p2_ctrl = gmin_v1p2_ctrl, + .flisclk_ctrl = gmin_flisclk_ctrl, + .platform_init = gmin_platform_init, + .platform_deinit = gmin_platform_deinit, + .csi_cfg = gmin_csi_cfg, + .get_vcm_ctrl = gmin_get_vcm_ctrl, +}; + +struct camera_sensor_platform_data *gmin_camera_platform_data( + struct v4l2_subdev *subdev, + enum atomisp_input_format csi_format, + enum atomisp_bayer_order csi_bayer) +{ + struct gmin_subdev *gs = find_gmin_subdev(subdev); + gs->csi_fmt = csi_format; + gs->csi_bayer = csi_bayer; + + return &gmin_plat; +} +EXPORT_SYMBOL_GPL(gmin_camera_platform_data); + +int atomisp_gmin_register_vcm_control(struct camera_vcm_control *vcmCtrl) +{ + if (!vcmCtrl) + return -EINVAL; + + mutex_lock(&vcm_lock); + list_add_tail(&vcmCtrl->list, &vcm_devices); + mutex_unlock(&vcm_lock); + + return 0; +} +EXPORT_SYMBOL_GPL(atomisp_gmin_register_vcm_control); + +/* Retrieves a device-specific configuration variable. The dev + * argument should be a device with an ACPI companion, as all + * configuration is based on firmware ID. */ +int gmin_get_config_var(struct device *dev, const char *var, char *out, size_t *out_len) +{ + char var8[CFG_VAR_NAME_MAX]; + efi_char16_t var16[CFG_VAR_NAME_MAX]; + struct efivar_entry *ev; + u32 efiattr_dummy; + int i, j, ret; + unsigned long efilen; + + if (dev && ACPI_COMPANION(dev)) + dev = &ACPI_COMPANION(dev)->dev; + + if (dev) + ret = snprintf(var8, sizeof(var8), "%s_%s", dev_name(dev), var); + else + ret = snprintf(var8, sizeof(var8), "gmin_%s", var); + + if (ret < 0 || ret >= sizeof(var8)-1) + return -EINVAL; + + /* First check a hard-coded list of board-specific variables. + * Some device firmwares lack the ability to set EFI variables at + * runtime. */ + for (i = 0; i < ARRAY_SIZE(hard_vars); i++) { + if (dmi_match(DMI_BOARD_NAME, hard_vars[i].dmi_board_name)) { + for (j = 0; hard_vars[i].vars[j].name; j++) { + size_t vl; + const struct gmin_cfg_var *gv; + + gv = &hard_vars[i].vars[j]; + vl = strlen(gv->val); + + if (strcmp(var8, gv->name)) + continue; + if (vl > *out_len-1) + return -ENOSPC; + + memcpy(out, gv->val, min(*out_len, vl+1)); + out[*out_len-1] = 0; + *out_len = vl; + + return 0; + } + } + } + + /* Our variable names are ASCII by construction, but EFI names + * are wide chars. Convert and zero-pad. */ + memset(var16, 0, sizeof(var16)); + for (i=0; var8[i] && i < sizeof(var8); i++) + var16[i] = var8[i]; + + /* To avoid owerflows when calling the efivar API */ + if (*out_len > ULONG_MAX) + return -EINVAL; + + /* Not sure this API usage is kosher; efivar_entry_get()'s + * implementation simply uses VariableName and VendorGuid from + * the struct and ignores the rest, but it seems like there + * ought to be an "official" efivar_entry registered + * somewhere? */ + ev = kzalloc(sizeof(*ev), GFP_KERNEL); + if (!ev) + return -ENOMEM; + memcpy(&ev->var.VariableName, var16, sizeof(var16)); + ev->var.VendorGuid = GMIN_CFG_VAR_EFI_GUID; + + efilen = *out_len; + ret = efivar_entry_get(ev, &efiattr_dummy, &efilen, out); + + kfree(ev); + *out_len = efilen; + + if (ret) + dev_warn(dev, "Failed to find gmin variable %s\n", var8); + + return ret; +} +EXPORT_SYMBOL_GPL(gmin_get_config_var); + +int gmin_get_var_int(struct device *dev, const char *var, int def) +{ + char val[CFG_VAR_NAME_MAX]; + size_t len = sizeof(val); + long result; + int ret; + + ret = gmin_get_config_var(dev, var, val, &len); + if (!ret) { + val[len] = 0; + ret = kstrtol(val, 0, &result); + } + + return ret ? def : result; +} +EXPORT_SYMBOL_GPL(gmin_get_var_int); + +int camera_sensor_csi(struct v4l2_subdev *sd, u32 port, + u32 lanes, u32 format, u32 bayer_order, int flag) +{ + struct i2c_client *client = v4l2_get_subdevdata(sd); + struct camera_mipi_info *csi = NULL; + + if (flag) { + csi = kzalloc(sizeof(*csi), GFP_KERNEL); + if (!csi) { + dev_err(&client->dev, "out of memory\n"); + return -ENOMEM; + } + csi->port = port; + csi->num_lanes = lanes; + csi->input_format = format; + csi->raw_bayer_order = bayer_order; + v4l2_set_subdev_hostdata(sd, (void *)csi); + csi->metadata_format = ATOMISP_INPUT_FORMAT_EMBEDDED; + csi->metadata_effective_width = NULL; + dev_info(&client->dev, + "camera pdata: port: %d lanes: %d order: %8.8x\n", + port, lanes, bayer_order); + } else { + csi = v4l2_get_subdev_hostdata(sd); + kfree(csi); + } + + return 0; +} +EXPORT_SYMBOL_GPL(camera_sensor_csi); + +/* PCI quirk: The BYT ISP advertises PCI runtime PM but it doesn't + * work. Disable so the kernel framework doesn't hang the device + * trying. The driver itself does direct calls to the PUNIT to manage + * ISP power. */ +static void isp_pm_cap_fixup(struct pci_dev *dev) +{ + dev_info(&dev->dev, "Disabling PCI power management on camera ISP\n"); + dev->pm_cap = 0; +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0f38, isp_pm_cap_fixup); diff --git a/drivers/staging/media/atomisp/platform/intel-mid/intel_mid_pcihelpers.c b/drivers/staging/media/atomisp/platform/intel-mid/intel_mid_pcihelpers.c new file mode 100644 index 0000000000000000000000000000000000000000..1f97dff1c9b08d36d4daefbc56c54d73be451e1d --- /dev/null +++ b/drivers/staging/media/atomisp/platform/intel-mid/intel_mid_pcihelpers.c @@ -0,0 +1,297 @@ +#include +#include +#include +#include + +/* G-Min addition: "platform_is()" lives in intel_mid_pm.h in the MCG + * tree, but it's just platform ID info and we don't want to pull in + * the whole SFI-based PM architecture. */ +#define INTEL_ATOM_MRST 0x26 +#define INTEL_ATOM_MFLD 0x27 +#define INTEL_ATOM_CLV 0x35 +#define INTEL_ATOM_MRFLD 0x4a +#define INTEL_ATOM_BYT 0x37 +#define INTEL_ATOM_MOORFLD 0x5a +#define INTEL_ATOM_CHT 0x4c +/* synchronization for sharing the I2C controller */ +#define PUNIT_PORT 0x04 +#define PUNIT_DOORBELL_OPCODE (0xE0) +#define PUNIT_DOORBELL_REG (0x0) +#ifndef CSTATE_EXIT_LATENCY +#define CSTATE_EXIT_LATENCY_C1 1 +#endif +static inline int platform_is(u8 model) +{ + return (boot_cpu_data.x86_model == model); +} + +#include + +/* Unified message bus read/write operation */ +static DEFINE_SPINLOCK(msgbus_lock); + +static struct pci_dev *pci_root; +static struct pm_qos_request pm_qos; +int qos; + +#define DW_I2C_NEED_QOS (platform_is(INTEL_ATOM_BYT)) + +static int intel_mid_msgbus_init(void) +{ + pci_root = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)); + if (!pci_root) { + pr_err("%s: Error: msgbus PCI handle NULL\n", __func__); + return -ENODEV; + } + + if (DW_I2C_NEED_QOS) { + pm_qos_add_request(&pm_qos, + PM_QOS_CPU_DMA_LATENCY, + PM_QOS_DEFAULT_VALUE); + } + return 0; +} +fs_initcall(intel_mid_msgbus_init); + +u32 intel_mid_msgbus_read32_raw(u32 cmd) +{ + unsigned long irq_flags; + u32 data; + + spin_lock_irqsave(&msgbus_lock, irq_flags); + pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_REG, cmd); + pci_read_config_dword(pci_root, PCI_ROOT_MSGBUS_DATA_REG, &data); + spin_unlock_irqrestore(&msgbus_lock, irq_flags); + + return data; +} +EXPORT_SYMBOL(intel_mid_msgbus_read32_raw); + +/* + * GU: this function is only used by the VISA and 'VXD' drivers. + */ +u32 intel_mid_msgbus_read32_raw_ext(u32 cmd, u32 cmd_ext) +{ + unsigned long irq_flags; + u32 data; + + spin_lock_irqsave(&msgbus_lock, irq_flags); + pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_EXT_REG, cmd_ext); + pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_REG, cmd); + pci_read_config_dword(pci_root, PCI_ROOT_MSGBUS_DATA_REG, &data); + spin_unlock_irqrestore(&msgbus_lock, irq_flags); + + return data; +} +EXPORT_SYMBOL(intel_mid_msgbus_read32_raw_ext); + +void intel_mid_msgbus_write32_raw(u32 cmd, u32 data) +{ + unsigned long irq_flags; + + spin_lock_irqsave(&msgbus_lock, irq_flags); + pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_DATA_REG, data); + pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_REG, cmd); + spin_unlock_irqrestore(&msgbus_lock, irq_flags); +} +EXPORT_SYMBOL(intel_mid_msgbus_write32_raw); + +/* + * GU: this function is only used by the VISA and 'VXD' drivers. + */ +void intel_mid_msgbus_write32_raw_ext(u32 cmd, u32 cmd_ext, u32 data) +{ + unsigned long irq_flags; + + spin_lock_irqsave(&msgbus_lock, irq_flags); + pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_DATA_REG, data); + pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_EXT_REG, cmd_ext); + pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_REG, cmd); + spin_unlock_irqrestore(&msgbus_lock, irq_flags); +} +EXPORT_SYMBOL(intel_mid_msgbus_write32_raw_ext); + +u32 intel_mid_msgbus_read32(u8 port, u32 addr) +{ + unsigned long irq_flags; + u32 data; + u32 cmd; + u32 cmdext; + + cmd = (PCI_ROOT_MSGBUS_READ << 24) | (port << 16) | + ((addr & 0xff) << 8) | PCI_ROOT_MSGBUS_DWORD_ENABLE; + cmdext = addr & 0xffffff00; + + spin_lock_irqsave(&msgbus_lock, irq_flags); + + if (cmdext) { + /* This resets to 0 automatically, no need to write 0 */ + pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_EXT_REG, + cmdext); + } + + pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_REG, cmd); + pci_read_config_dword(pci_root, PCI_ROOT_MSGBUS_DATA_REG, &data); + spin_unlock_irqrestore(&msgbus_lock, irq_flags); + + return data; +} + +EXPORT_SYMBOL(intel_mid_msgbus_read32); +void intel_mid_msgbus_write32(u8 port, u32 addr, u32 data) +{ + unsigned long irq_flags; + u32 cmd; + u32 cmdext; + + cmd = (PCI_ROOT_MSGBUS_WRITE << 24) | (port << 16) | + ((addr & 0xFF) << 8) | PCI_ROOT_MSGBUS_DWORD_ENABLE; + cmdext = addr & 0xffffff00; + + spin_lock_irqsave(&msgbus_lock, irq_flags); + pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_DATA_REG, data); + + if (cmdext) { + /* This resets to 0 automatically, no need to write 0 */ + pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_EXT_REG, + cmdext); + } + + pci_write_config_dword(pci_root, PCI_ROOT_MSGBUS_CTRL_REG, cmd); + spin_unlock_irqrestore(&msgbus_lock, irq_flags); +} +EXPORT_SYMBOL(intel_mid_msgbus_write32); + +/* called only from where is later then fs_initcall */ +u32 intel_mid_soc_stepping(void) +{ + return pci_root->revision; +} +EXPORT_SYMBOL(intel_mid_soc_stepping); + +static bool is_south_complex_device(struct pci_dev *dev) +{ + unsigned base_class = dev->class >> 16; + unsigned sub_class = (dev->class & SUB_CLASS_MASK) >> 8; + + /* other than camera, pci bridges and display, + * everything else are south complex devices. + */ + if (((base_class == PCI_BASE_CLASS_MULTIMEDIA) && + (sub_class == ISP_SUB_CLASS)) || + (base_class == PCI_BASE_CLASS_BRIDGE) || + ((base_class == PCI_BASE_CLASS_DISPLAY) && !sub_class)) + return false; + else + return true; +} + +/* In BYT platform, d3_delay for internal south complex devices, + * they are not subject to 10 ms d3 to d0 delay required by pci spec. + */ +static void pci_d3_delay_fixup(struct pci_dev *dev) +{ + if (platform_is(INTEL_ATOM_BYT) || + platform_is(INTEL_ATOM_CHT)) { + /* All internal devices are in bus 0. */ + if (dev->bus->number == 0 && is_south_complex_device(dev)) { + dev->d3_delay = INTERNAL_PCI_PM_D3_WAIT; + dev->d3cold_delay = INTERNAL_PCI_PM_D3_WAIT; + } + } +} +DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3_delay_fixup); + +#define PUNIT_SEMAPHORE (platform_is(INTEL_ATOM_BYT) ? 0x7 : 0x10E) +#define GET_SEM() (intel_mid_msgbus_read32(PUNIT_PORT, PUNIT_SEMAPHORE) & 0x1) + +static void reset_semaphore(void) +{ + u32 data; + + data = intel_mid_msgbus_read32(PUNIT_PORT, PUNIT_SEMAPHORE); + smp_mb(); + data = data & 0xfffffffc; + intel_mid_msgbus_write32(PUNIT_PORT, PUNIT_SEMAPHORE, data); + smp_mb(); + +} + +int intel_mid_dw_i2c_acquire_ownership(void) +{ + u32 ret = 0; + u32 data = 0; /* data sent to PUNIT */ + u32 cmd; + u32 cmdext; + int timeout = 1000; + + if (DW_I2C_NEED_QOS) + pm_qos_update_request(&pm_qos, CSTATE_EXIT_LATENCY_C1 - 1); + + /* + * We need disable irq. Otherwise, the main thread + * might be preempted and the other thread jumps to + * disable irq for a long time. Another case is + * some irq handlers might trigger power voltage change + */ + BUG_ON(irqs_disabled()); + local_irq_disable(); + + /* host driver writes 0x2 to side band register 0x7 */ + intel_mid_msgbus_write32(PUNIT_PORT, PUNIT_SEMAPHORE, 0x2); + smp_mb(); + + /* host driver sends 0xE0 opcode to PUNIT and writes 0 register */ + cmd = (PUNIT_DOORBELL_OPCODE << 24) | (PUNIT_PORT << 16) | + ((PUNIT_DOORBELL_REG & 0xFF) << 8) | PCI_ROOT_MSGBUS_DWORD_ENABLE; + cmdext = PUNIT_DOORBELL_REG & 0xffffff00; + + if (cmdext) + intel_mid_msgbus_write32_raw_ext(cmd, cmdext, data); + else + intel_mid_msgbus_write32_raw(cmd, data); + + /* host driver waits for bit 0 to be set in side band 0x7 */ + while (GET_SEM() != 0x1) { + udelay(100); + timeout--; + if (timeout <= 0) { + pr_err("Timeout: semaphore timed out, reset sem\n"); + ret = -ETIMEDOUT; + reset_semaphore(); + /*Delay 1ms in case race with punit*/ + udelay(1000); + if (GET_SEM() != 0) { + /*Reset again as kernel might race with punit*/ + reset_semaphore(); + } + pr_err("PUNIT SEM: %d\n", + intel_mid_msgbus_read32(PUNIT_PORT, + PUNIT_SEMAPHORE)); + local_irq_enable(); + + if (DW_I2C_NEED_QOS) { + pm_qos_update_request(&pm_qos, + PM_QOS_DEFAULT_VALUE); + } + + return ret; + } + } + smp_mb(); + + return ret; +} +EXPORT_SYMBOL(intel_mid_dw_i2c_acquire_ownership); + +int intel_mid_dw_i2c_release_ownership(void) +{ + reset_semaphore(); + local_irq_enable(); + + if (DW_I2C_NEED_QOS) + pm_qos_update_request(&pm_qos, PM_QOS_DEFAULT_VALUE); + + return 0; +} +EXPORT_SYMBOL(intel_mid_dw_i2c_release_ownership);