diff --git a/.mailmap b/.mailmap index ccba4cf0d893849363c2d9a44d304d3f23f5de6a..a872c9683958cc391359ecb569aae157affad08b 100644 --- a/.mailmap +++ b/.mailmap @@ -25,6 +25,8 @@ Aleksey Gorelov Alexander Lobakin Alexander Lobakin Alexander Lobakin +Alexander Mikhalitsyn +Alexander Mikhalitsyn Alexandre Belloni Alexei Starovoitov Alexei Starovoitov @@ -130,6 +132,7 @@ Domen Puncer Douglas Gilbert Ed L. Cashin Erik Kaneda +Eugen Hristev Evgeniy Polyakov Ezequiel Garcia Felipe W Damasio @@ -214,6 +217,7 @@ Jisheng Zhang Jisheng Zhang Johan Hovold Johan Hovold +John Crispin John Paul Adrian Glaubitz John Stultz Jordan Crouse @@ -371,6 +375,7 @@ Rémi Denis-Courmont Ricardo Ribalda Ricardo Ribalda Ricardo Ribalda Delgado Ricardo Ribalda +Robert Foss Roman Gushchin Roman Gushchin Roman Gushchin @@ -422,6 +427,7 @@ Tony Luck TripleX Chung TripleX Chung Tsuneo Yoshioka +Tudor Ambarus Tycho Andersen Tzung-Bi Shih Uwe Kleine-König diff --git a/CREDITS b/CREDITS index 4e302a459ddf069ce3b59b3dd7bbebcd8476ef46..5f5d70c9c03892b428e73a71f3fd97fec0fef511 100644 --- a/CREDITS +++ b/CREDITS @@ -1173,6 +1173,10 @@ D: Future Domain TMC-16x0 SCSI driver (author) D: APM driver (early port) D: DRM drivers (author of several) +N: Veaceslav Falico +E: vfalico@gmail.com +D: Co-maintainer and co-author of the network bonding driver. + N: János Farkas E: chexum@shadow.banki.hu D: romfs, various (mostly networking) fixes @@ -2489,6 +2493,13 @@ D: XF86_Mach8 D: XF86_8514 D: cfdisk (curses based disk partitioning program) +N: Mat Martineau +E: mat@martineau.name +D: MPTCP subsystem co-maintainer 2020-2023 +D: Keyctl restricted keyring and Diffie-Hellman UAPI +D: Bluetooth L2CAP ERTM mode and AMP +S: USA + N: John S. Marvin E: jsm@fc.hp.com D: PA-RISC port @@ -4172,6 +4183,10 @@ S: B-1206 Jingmao Guojigongyu S: 16 Baliqiao Nanjie, Beijing 101100 S: People's Repulic of China +N: Vlad Yasevich +E: vyasevich@gmail.com +D: SCTP protocol maintainer. + N: Aviad Yehezkel E: aviadye@nvidia.com D: Kernel TLS implementation and offload support. diff --git a/Documentation/ABI/stable/sysfs-block b/Documentation/ABI/stable/sysfs-block index cd14ecb3c9a5af03845de206a53b88f6a6c78153..ac1e519272aa2bb40a72eed5c50c49e51429a8e4 100644 --- a/Documentation/ABI/stable/sysfs-block +++ b/Documentation/ABI/stable/sysfs-block @@ -432,7 +432,8 @@ Contact: linux-block@vger.kernel.org Description: [RW] This is the maximum number of kilobytes that the block layer will allow for a filesystem request. Must be smaller than - or equal to the maximum size allowed by the hardware. + or equal to the maximum size allowed by the hardware. Write 0 + to use default kernel settings. What: /sys/block//queue/max_segment_size diff --git a/Documentation/ABI/stable/sysfs-driver-mlxreg-io b/Documentation/ABI/stable/sysfs-driver-mlxreg-io index af0cbf143c4809dee1ab70dc87731fd4f99bb14a..60953903d0077488d58f66efadc31f1588ffcde7 100644 --- a/Documentation/ABI/stable/sysfs-driver-mlxreg-io +++ b/Documentation/ABI/stable/sysfs-driver-mlxreg-io @@ -522,7 +522,6 @@ Description: These files allow to each of ASICs by writing 1. The files are write only. - What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/comm_chnl_ready Date: July 2022 KernelVersion: 5.20 @@ -542,3 +541,124 @@ Description: The file indicates COME module hardware configuration. The purpose is to expose some minor BOM changes for the same system SKU. The file is read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_pwr_converter_fail +Date: February 2023 +KernelVersion: 6.3 +Contact: Vadim Pasternak +Description: This file shows the system reset cause due to power converter + devices failure. + Value 1 in file means this is reset cause, 0 - otherwise. + + The file is read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot1_ap_reset +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot2_ap_reset +Date: February 2023 +KernelVersion: 6.3 +Contact: Vadim Pasternak +Description: These files aim to monitor the status of the External Root of Trust (EROT) + processor's RESET output to the Application Processor (AP). + By reading this file, could be determined if the EROT has invalidated or + revoked AP Firmware, at which point it will hold the AP in RESET until a + valid firmware is loaded. This protects the AP from running an + unauthorized firmware. In the normal flow, the AP reset should be released + after the EROT validates the integrity of the FW, and it should be done so + as quickly as possible so that the AP boots before the CPU starts to + communicate to each ASIC. + + The files are read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot1_recovery +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot2_recovery +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot1_reset +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot2_reset +Date: February 2023 +KernelVersion: 6.3 +Contact: Vadim Pasternak +Description: These files aim to perform External Root of Trust (EROT) recovery + sequence after EROT device failure. + These EROT devices protect ASICs from unauthorized access and in normal + flow their reset should be released with system power – earliest power + up stage, so that EROTs can begin boot and authentication process before + CPU starts to communicate to ASICs. + Issuing a reset to the EROT while asserting the recovery signal will cause + the EROT Application Processor to enter recovery mode so that the EROT FW + can be updated/recovered. + For reset/recovery the related file should be toggled by 1/0. + + The files are read/write. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot1_wp +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/erot2_wp +Date: February 2023 +KernelVersion: 6.3 +Contact: Vadim Pasternak +Description: These files allow access to External Root of Trust (EROT) for reset + and recovery sequence after EROT device failure. + Default is 0 (programming disabled). + If the system is in locked-down mode writing this file will not be allowed. + + The files are read/write. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/spi_chnl_select +Date: February 2023 +KernelVersion: 6.3 +Contact: Vadim Pasternak +Description: This file allows SPI chip selection for External Root of Trust (EROT) + device Out-of-Band recovery. + File can be written with 0 or with 1. It selects which EROT can be accessed + through SPI device. + + The file is read/write. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/asic_pg_fail +Date: February 2023 +KernelVersion: 6.3 +Contact: Vadim Pasternak vadimp@nvidia.com +Description: This file shows ASIC Power Good status. + Value 1 in file means ASIC Power Good failed, 0 - otherwise. + + The file is read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/clk_brd1_boot_fail +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/clk_brd2_boot_fail +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/clk_brd_fail +Date: February 2023 +KernelVersion: 6.3 +Contact: Vadim Pasternak vadimp@nvidia.com +Description: These files are related to clock boards status in system. + - clk_brd1_boot_fail: warning about 1-st clock board failed to boot from CI. + - clk_brd2_boot_fail: warning about 2-nd clock board failed to boot from CI. + - clk_brd_fail: error about common clock board boot failure. + + The files are read only. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/clk_brd_prog_en +Date: February 2023 +KernelVersion: 6.3 +Contact: Vadim Pasternak +Description: This file enables programming of clock boards. + Default is 0 (programming disabled). + If the system is in locked-down mode writing this file will not be allowed. + + The file is read/write. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/pwr_converter_prog_en +Date: February 2023 +KernelVersion: 6.3 +Contact: Vadim Pasternak +Description: This file enables programming of power converters. + Default is 0 (programming disabled). + If the system is in locked-down mode writing this file will not be allowed. + + The file is read/write. + +What: /sys/devices/platform/mlxplat/mlxreg-io/hwmon/hwmon*/reset_ac_ok_fail +Date: February 2023 +KernelVersion: 6.3 +Contact: Vadim Pasternak +Description: This file shows the system reset cause due to AC power failure. + Value 1 in file means this is reset cause, 0 - otherwise. + + The file is read only. diff --git a/Documentation/ABI/stable/sysfs-hypervisor-xen b/Documentation/ABI/stable/sysfs-hypervisor-xen index 748593c64568ba4a62d7473addacd5687392a400..be9ca9981bb1a22c0775ea47a30380b86eac2360 100644 --- a/Documentation/ABI/stable/sysfs-hypervisor-xen +++ b/Documentation/ABI/stable/sysfs-hypervisor-xen @@ -120,3 +120,16 @@ Contact: xen-devel@lists.xenproject.org Description: If running under Xen: The Xen version is in the format . This is the part of it. + +What: /sys/hypervisor/start_flags/* +Date: March 2023 +KernelVersion: 6.3.0 +Contact: xen-devel@lists.xenproject.org +Description: If running under Xen: + All bits in Xen's start-flags are represented as + boolean files, returning '1' if set, '0' otherwise. + This takes the place of the defunct /proc/xen/capabilities, + which would contain "control_d" on dom0, and be empty + otherwise. This flag is now exposed as "initdomain" in + addition to the "privileged" flag; all other possible flags + are accessible as "unknownXX". diff --git a/Documentation/ABI/testing/debugfs-pktcdvd b/Documentation/ABI/testing/debugfs-pktcdvd new file mode 100644 index 0000000000000000000000000000000000000000..f6f65a4faea06c0fc3286b4c4b54c927f0d0fa5c --- /dev/null +++ b/Documentation/ABI/testing/debugfs-pktcdvd @@ -0,0 +1,18 @@ +What: /sys/kernel/debug/pktcdvd/pktcdvd[0-7] +Date: Oct. 2006 +KernelVersion: 2.6.20 +Contact: Thomas Maier +Description: + +The pktcdvd module (packet writing driver) creates +these files in debugfs: + +/sys/kernel/debug/pktcdvd/pktcdvd[0-7]/ + + ==== ====== ==================================== + info 0444 Lots of driver statistics and infos. + ==== ====== ==================================== + +Example:: + + cat /sys/kernel/debug/pktcdvd/pktcdvd0/info diff --git a/Documentation/ABI/testing/sysfs-bus-css b/Documentation/ABI/testing/sysfs-bus-css index 12a733fe357fd43a8128d20cbbd6ae548e838832..d4d5cfb63b906faff1e0bad490664e7d223876ee 100644 --- a/Documentation/ABI/testing/sysfs-bus-css +++ b/Documentation/ABI/testing/sysfs-bus-css @@ -1,22 +1,19 @@ What: /sys/bus/css/devices/.../type Date: March 2008 -Contact: Cornelia Huck - linux-s390@vger.kernel.org +Contact: linux-s390@vger.kernel.org Description: Contains the subchannel type, as reported by the hardware. This attribute is present for all subchannel types. What: /sys/bus/css/devices/.../modalias Date: March 2008 -Contact: Cornelia Huck - linux-s390@vger.kernel.org +Contact: linux-s390@vger.kernel.org Description: Contains the module alias as reported with uevents. It is of the format css:t and present for all subchannel types. What: /sys/bus/css/drivers/io_subchannel/.../chpids Date: December 2002 -Contact: Cornelia Huck - linux-s390@vger.kernel.org +Contact: linux-s390@vger.kernel.org Description: Contains the ids of the channel paths used by this subchannel, as reported by the channel subsystem during subchannel recognition. @@ -26,8 +23,7 @@ Users: s390-tools, HAL What: /sys/bus/css/drivers/io_subchannel/.../pimpampom Date: December 2002 -Contact: Cornelia Huck - linux-s390@vger.kernel.org +Contact: linux-s390@vger.kernel.org Description: Contains the PIM/PAM/POM values, as reported by the channel subsystem when last queried by the common I/O layer (this implies that this attribute is not necessarily @@ -38,8 +34,7 @@ Users: s390-tools, HAL What: /sys/bus/css/devices/.../driver_override Date: June 2019 -Contact: Cornelia Huck - linux-s390@vger.kernel.org +Contact: linux-s390@vger.kernel.org Description: This file allows the driver for a device to be specified. When specified, only a driver with a name matching the value written to driver_override will have an opportunity to bind to the diff --git a/Documentation/ABI/testing/sysfs-class-pktcdvd b/Documentation/ABI/testing/sysfs-class-pktcdvd new file mode 100644 index 0000000000000000000000000000000000000000..ba1ce626591d9c4e666fea449075c44a3f447b17 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-pktcdvd @@ -0,0 +1,97 @@ +sysfs interface +--------------- +The pktcdvd module (packet writing driver) creates the following files in the +sysfs: ( is in the format major:minor) + +What: /sys/class/pktcdvd/add +What: /sys/class/pktcdvd/remove +What: /sys/class/pktcdvd/device_map +Date: Oct. 2006 +KernelVersion: 2.6.20 +Contact: Thomas Maier +Description: + + ========== ============================================== + add (WO) Write a block device id (major:minor) to + create a new pktcdvd device and map it to the + block device. + + remove (WO) Write the pktcdvd device id (major:minor) + to remove the pktcdvd device. + + device_map (RO) Shows the device mapping in format: + pktcdvd[0-7] + ========== ============================================== + + +What: /sys/class/pktcdvd/pktcdvd[0-7]/dev +What: /sys/class/pktcdvd/pktcdvd[0-7]/uevent +Date: Oct. 2006 +KernelVersion: 2.6.20 +Contact: Thomas Maier +Description: + dev: (RO) Device id + + uevent: (WO) To send a uevent + + +What: /sys/class/pktcdvd/pktcdvd[0-7]/stat/packets_started +What: /sys/class/pktcdvd/pktcdvd[0-7]/stat/packets_finished +What: /sys/class/pktcdvd/pktcdvd[0-7]/stat/kb_written +What: /sys/class/pktcdvd/pktcdvd[0-7]/stat/kb_read +What: /sys/class/pktcdvd/pktcdvd[0-7]/stat/kb_read_gather +What: /sys/class/pktcdvd/pktcdvd[0-7]/stat/reset +Date: Oct. 2006 +KernelVersion: 2.6.20 +Contact: Thomas Maier +Description: + packets_started: (RO) Number of started packets. + + packets_finished: (RO) Number of finished packets. + + kb_written: (RO) kBytes written. + + kb_read: (RO) kBytes read. + + kb_read_gather: (RO) kBytes read to fill write packets. + + reset: (WO) Write any value to it to reset + pktcdvd device statistic values, like + bytes read/written. + + +What: /sys/class/pktcdvd/pktcdvd[0-7]/write_queue/size +What: /sys/class/pktcdvd/pktcdvd[0-7]/write_queue/congestion_off +What: /sys/class/pktcdvd/pktcdvd[0-7]/write_queue/congestion_on +Date: Oct. 2006 +KernelVersion: 2.6.20 +Contact: Thomas Maier +Description: + ============== ================================================ + size (RO) Contains the size of the bio write queue. + + congestion_off (RW) If bio write queue size is below this mark, + accept new bio requests from the block layer. + + congestion_on (RW) If bio write queue size is higher as this + mark, do no longer accept bio write requests + from the block layer and wait till the pktcdvd + device has processed enough bio's so that bio + write queue size is below congestion off mark. + A value of <= 0 disables congestion control. + ============== ================================================ + + +Example: +-------- +To use the pktcdvd sysfs interface directly, you can do:: + + # create a new pktcdvd device mapped to /dev/hdc + echo "22:0" >/sys/class/pktcdvd/add + cat /sys/class/pktcdvd/device_map + # assuming device pktcdvd0 was created, look at stat's + cat /sys/class/pktcdvd/pktcdvd0/stat/kb_written + # print the device id of the mapped block device + fgrep pktcdvd0 /sys/class/pktcdvd/device_map + # remove device, using pktcdvd0 device id 253:0 + echo "253:0" >/sys/class/pktcdvd/remove diff --git a/Documentation/ABI/testing/sysfs-fs-erofs b/Documentation/ABI/testing/sysfs-fs-erofs index bb4681a01811603caad50466790d1bd4794c98f0..284224d1b56fe1bae7722d549410053c59d68cd1 100644 --- a/Documentation/ABI/testing/sysfs-fs-erofs +++ b/Documentation/ABI/testing/sysfs-fs-erofs @@ -4,7 +4,8 @@ Contact: "Huang Jianan" Description: Shows all enabled kernel features. Supported features: zero_padding, compr_cfgs, big_pcluster, chunked_file, - device_table, compr_head2, sb_chksum. + device_table, compr_head2, sb_chksum, ztailpacking, + dedupe, fragments. What: /sys/fs/erofs//sync_decompress Date: November 2021 diff --git a/Documentation/RCU/NMI-RCU.rst b/Documentation/RCU/NMI-RCU.rst index 2a92bc685ef1ac043f33e6cb04f61fd9705dddba..dff60a80b386ef43ce1c68a00a5e8e67736f6a2f 100644 --- a/Documentation/RCU/NMI-RCU.rst +++ b/Documentation/RCU/NMI-RCU.rst @@ -8,7 +8,7 @@ Although RCU is usually used to protect read-mostly data structures, it is possible to use RCU to provide dynamic non-maskable interrupt handlers, as well as dynamic irq handlers. This document describes how to do this, drawing loosely from Zwane Mwaikambo's NMI-timer -work in "arch/x86/kernel/traps.c". +work in an old version of "arch/x86/kernel/traps.c". The relevant pieces of code are listed below, each followed by a brief explanation:: @@ -116,7 +116,7 @@ Answer to Quick Quiz: This same sad story can happen on other CPUs when using a compiler with aggressive pointer-value speculation - optimizations. + optimizations. (But please don't!) More important, the rcu_dereference_sched() makes it clear to someone reading the code that the pointer is diff --git a/Documentation/RCU/UP.rst b/Documentation/RCU/UP.rst index e26dda27430c8f3ec078b318821ed9697107e068..8b20fd45f2558d8d5d6d6076d624b134f0b70bdf 100644 --- a/Documentation/RCU/UP.rst +++ b/Documentation/RCU/UP.rst @@ -38,7 +38,7 @@ by having call_rcu() directly invoke its arguments only if it was called from process context. However, this can fail in a similar manner. Suppose that an RCU-based algorithm again scans a linked list containing -elements A, B, and C in process contexts, but that it invokes a function +elements A, B, and C in process context, but that it invokes a function on each element as it is scanned. Suppose further that this function deletes element B from the list, then passes it to call_rcu() for deferred freeing. This may be a bit unconventional, but it is perfectly legal @@ -59,7 +59,8 @@ Example 3: Death by Deadlock Suppose that call_rcu() is invoked while holding a lock, and that the callback function must acquire this same lock. In this case, if call_rcu() were to directly invoke the callback, the result would -be self-deadlock. +be self-deadlock *even if* this invocation occurred from a later +call_rcu() invocation a full grace period later. In some cases, it would possible to restructure to code so that the call_rcu() is delayed until after the lock is released. However, @@ -85,6 +86,14 @@ Quick Quiz #2: :ref:`Answers to Quick Quiz ` +It is important to note that userspace RCU implementations *do* +permit call_rcu() to directly invoke callbacks, but only if a full +grace period has elapsed since those callbacks were queued. This is +the case because some userspace environments are extremely constrained. +Nevertheless, people writing userspace RCU implementations are strongly +encouraged to avoid invoking callbacks from call_rcu(), thus obtaining +the deadlock-avoidance benefits called out above. + Summary ------- diff --git a/Documentation/RCU/lockdep.rst b/Documentation/RCU/lockdep.rst index 9308f1bdba05de32ff9c462307d86530abb21c48..2749f43ec1b03f68c11291b956f07641e1bfd8ec 100644 --- a/Documentation/RCU/lockdep.rst +++ b/Documentation/RCU/lockdep.rst @@ -69,9 +69,8 @@ checking of rcu_dereference() primitives: value of the pointer itself, for example, against NULL. The rcu_dereference_check() check expression can be any boolean -expression, but would normally include a lockdep expression. However, -any boolean expression can be used. For a moderately ornate example, -consider the following:: +expression, but would normally include a lockdep expression. For a +moderately ornate example, consider the following:: file = rcu_dereference_check(fdt->fd[fd], lockdep_is_held(&files->file_lock) || @@ -97,10 +96,10 @@ code, it could instead be written as follows:: atomic_read(&files->count) == 1); This would verify cases #2 and #3 above, and furthermore lockdep would -complain if this was used in an RCU read-side critical section unless one -of these two cases held. Because rcu_dereference_protected() omits all -barriers and compiler constraints, it generates better code than do the -other flavors of rcu_dereference(). On the other hand, it is illegal +complain even if this was used in an RCU read-side critical section unless +one of these two cases held. Because rcu_dereference_protected() omits +all barriers and compiler constraints, it generates better code than do +the other flavors of rcu_dereference(). On the other hand, it is illegal to use rcu_dereference_protected() if either the RCU-protected pointer or the RCU-protected data that it points to can change concurrently. diff --git a/Documentation/RCU/rcu.rst b/Documentation/RCU/rcu.rst index 3cfe01ba9a4944b20b89399ffeee9cdfd7dfb4d9..bf6617b330a74a8a43de8648316b2691b2c5e6f4 100644 --- a/Documentation/RCU/rcu.rst +++ b/Documentation/RCU/rcu.rst @@ -77,15 +77,17 @@ Frequently Asked Questions search for the string "Patent" in Documentation/RCU/RTFP.txt to find them. Of these, one was allowed to lapse by the assignee, and the others have been contributed to the Linux kernel under GPL. + Many (but not all) have long since expired. There are now also LGPL implementations of user-level RCU available (https://liburcu.org/). - I hear that RCU needs work in order to support realtime kernels? - Realtime-friendly RCU can be enabled via the CONFIG_PREEMPT_RCU + Realtime-friendly RCU are enabled via the CONFIG_PREEMPTION kernel configuration parameter. - Where can I find more information on RCU? See the Documentation/RCU/RTFP.txt file. - Or point your browser at (http://www.rdrop.com/users/paulmck/RCU/). + Or point your browser at (https://docs.google.com/document/d/1X0lThx8OK0ZgLMqVoXiR4ZrGURHrXK6NyLRbeXe3Xac/edit) + or (https://docs.google.com/document/d/1GCdQC8SDbb54W1shjEXqGZ0Rq8a6kIeYutdSIajfpLA/edit?usp=sharing). diff --git a/Documentation/RCU/rcu_dereference.rst b/Documentation/RCU/rcu_dereference.rst index 81e828c8313b8eb2effa026366476a73e29aae5c..3b739f6243c85e83a5b5c066ff84a4d577339577 100644 --- a/Documentation/RCU/rcu_dereference.rst +++ b/Documentation/RCU/rcu_dereference.rst @@ -19,8 +19,9 @@ Follow these rules to keep your RCU code working properly: can reload the value, and won't your code have fun with two different values for a single pointer! Without rcu_dereference(), DEC Alpha can load a pointer, dereference that pointer, and - return data preceding initialization that preceded the store of - the pointer. + return data preceding initialization that preceded the store + of the pointer. (As noted later, in recent kernels READ_ONCE() + also prevents DEC Alpha from playing these tricks.) In addition, the volatile cast in rcu_dereference() prevents the compiler from deducing the resulting pointer value. Please see @@ -34,7 +35,7 @@ Follow these rules to keep your RCU code working properly: takes on the role of the lockless_dereference() primitive that was removed in v4.15. -- You are only permitted to use rcu_dereference on pointer values. +- You are only permitted to use rcu_dereference() on pointer values. The compiler simply knows too much about integral values to trust it to carry dependencies through integer operations. There are a very few exceptions, namely that you can temporarily @@ -240,6 +241,7 @@ precautions. To see this, consider the following code fragment:: struct foo *q; int r1, r2; + rcu_read_lock(); p = rcu_dereference(gp2); if (p == NULL) return; @@ -248,7 +250,10 @@ precautions. To see this, consider the following code fragment:: if (p == q) { /* The compiler decides that q->c is same as p->c. */ r2 = p->c; /* Could get 44 on weakly order system. */ + } else { + r2 = p->c - r1; /* Unconditional access to p->c. */ } + rcu_read_unlock(); do_something_with(r1, r2); } @@ -297,6 +302,7 @@ Then one approach is to use locking, for example, as follows:: struct foo *q; int r1, r2; + rcu_read_lock(); p = rcu_dereference(gp2); if (p == NULL) return; @@ -306,7 +312,12 @@ Then one approach is to use locking, for example, as follows:: if (p == q) { /* The compiler decides that q->c is same as p->c. */ r2 = p->c; /* Locking guarantees r2 == 144. */ + } else { + spin_lock(&q->lock); + r2 = q->c - r1; + spin_unlock(&q->lock); } + rcu_read_unlock(); spin_unlock(&p->lock); do_something_with(r1, r2); } @@ -364,7 +375,7 @@ the exact value of "p" even in the not-equals case. This allows the compiler to make the return values independent of the load from "gp", in turn destroying the ordering between this load and the loads of the return values. This can result in "p->b" returning pre-initialization -garbage values. +garbage values on weakly ordered systems. In short, rcu_dereference() is *not* optional when you are going to dereference the resulting pointer. @@ -430,7 +441,7 @@ member of the rcu_dereference() to use in various situations: SPARSE CHECKING OF RCU-PROTECTED POINTERS ----------------------------------------- -The sparse static-analysis tool checks for direct access to RCU-protected +The sparse static-analysis tool checks for non-RCU access to RCU-protected pointers, which can result in "interesting" bugs due to compiler optimizations involving invented loads and perhaps also load tearing. For example, suppose someone mistakenly does something like this:: diff --git a/Documentation/RCU/rcubarrier.rst b/Documentation/RCU/rcubarrier.rst index 3b4a248774961c37f9063195c411a520ce2b9ad7..6da7f66da2a808005c3f6173d9a0b21d24bd5488 100644 --- a/Documentation/RCU/rcubarrier.rst +++ b/Documentation/RCU/rcubarrier.rst @@ -5,37 +5,12 @@ RCU and Unloadable Modules [Originally published in LWN Jan. 14, 2007: http://lwn.net/Articles/217484/] -RCU (read-copy update) is a synchronization mechanism that can be thought -of as a replacement for read-writer locking (among other things), but with -very low-overhead readers that are immune to deadlock, priority inversion, -and unbounded latency. RCU read-side critical sections are delimited -by rcu_read_lock() and rcu_read_unlock(), which, in non-CONFIG_PREEMPTION -kernels, generate no code whatsoever. - -This means that RCU writers are unaware of the presence of concurrent -readers, so that RCU updates to shared data must be undertaken quite -carefully, leaving an old version of the data structure in place until all -pre-existing readers have finished. These old versions are needed because -such readers might hold a reference to them. RCU updates can therefore be -rather expensive, and RCU is thus best suited for read-mostly situations. - -How can an RCU writer possibly determine when all readers are finished, -given that readers might well leave absolutely no trace of their -presence? There is a synchronize_rcu() primitive that blocks until all -pre-existing readers have completed. An updater wishing to delete an -element p from a linked list might do the following, while holding an -appropriate lock, of course:: - - list_del_rcu(p); - synchronize_rcu(); - kfree(p); - -But the above code cannot be used in IRQ context -- the call_rcu() -primitive must be used instead. This primitive takes a pointer to an -rcu_head struct placed within the RCU-protected data structure and -another pointer to a function that may be invoked later to free that -structure. Code to delete an element p from the linked list from IRQ -context might then be as follows:: +RCU updaters sometimes use call_rcu() to initiate an asynchronous wait for +a grace period to elapse. This primitive takes a pointer to an rcu_head +struct placed within the RCU-protected data structure and another pointer +to a function that may be invoked later to free that structure. Code to +delete an element p from the linked list from IRQ context might then be +as follows:: list_del_rcu(p); call_rcu(&p->rcu, p_callback); @@ -54,7 +29,7 @@ IRQ context. The function p_callback() might be defined as follows:: Unloading Modules That Use call_rcu() ------------------------------------- -But what if p_callback is defined in an unloadable module? +But what if the p_callback() function is defined in an unloadable module? If we unload the module while some RCU callbacks are pending, the CPUs executing these callbacks are going to be severely @@ -67,20 +42,21 @@ grace period to elapse, it does not wait for the callbacks to complete. One might be tempted to try several back-to-back synchronize_rcu() calls, but this is still not guaranteed to work. If there is a very -heavy RCU-callback load, then some of the callbacks might be deferred -in order to allow other processing to proceed. Such deferral is required -in realtime kernels in order to avoid excessive scheduling latencies. +heavy RCU-callback load, then some of the callbacks might be deferred in +order to allow other processing to proceed. For but one example, such +deferral is required in realtime kernels in order to avoid excessive +scheduling latencies. rcu_barrier() ------------- -We instead need the rcu_barrier() primitive. Rather than waiting for -a grace period to elapse, rcu_barrier() waits for all outstanding RCU -callbacks to complete. Please note that rcu_barrier() does **not** imply -synchronize_rcu(), in particular, if there are no RCU callbacks queued -anywhere, rcu_barrier() is within its rights to return immediately, -without waiting for a grace period to elapse. +This situation can be handled by the rcu_barrier() primitive. Rather +than waiting for a grace period to elapse, rcu_barrier() waits for all +outstanding RCU callbacks to complete. Please note that rcu_barrier() +does **not** imply synchronize_rcu(), in particular, if there are no RCU +callbacks queued anywhere, rcu_barrier() is within its rights to return +immediately, without waiting for anything, let alone a grace period. Pseudo-code using rcu_barrier() is as follows: @@ -89,83 +65,86 @@ Pseudo-code using rcu_barrier() is as follows: 3. Allow the module to be unloaded. There is also an srcu_barrier() function for SRCU, and you of course -must match the flavor of rcu_barrier() with that of call_rcu(). If your -module uses multiple flavors of call_rcu(), then it must also use multiple -flavors of rcu_barrier() when unloading that module. For example, if -it uses call_rcu(), call_srcu() on srcu_struct_1, and call_srcu() on -srcu_struct_2, then the following three lines of code will be required -when unloading:: - - 1 rcu_barrier(); - 2 srcu_barrier(&srcu_struct_1); - 3 srcu_barrier(&srcu_struct_2); - -The rcutorture module makes use of rcu_barrier() in its exit function -as follows:: - - 1 static void - 2 rcu_torture_cleanup(void) - 3 { - 4 int i; - 5 - 6 fullstop = 1; - 7 if (shuffler_task != NULL) { - 8 VERBOSE_PRINTK_STRING("Stopping rcu_torture_shuffle task"); - 9 kthread_stop(shuffler_task); - 10 } - 11 shuffler_task = NULL; +must match the flavor of srcu_barrier() with that of call_srcu(). +If your module uses multiple srcu_struct structures, then it must also +use multiple invocations of srcu_barrier() when unloading that module. +For example, if it uses call_rcu(), call_srcu() on srcu_struct_1, and +call_srcu() on srcu_struct_2, then the following three lines of code +will be required when unloading:: + + 1 rcu_barrier(); + 2 srcu_barrier(&srcu_struct_1); + 3 srcu_barrier(&srcu_struct_2); + +If latency is of the essence, workqueues could be used to run these +three functions concurrently. + +An ancient version of the rcutorture module makes use of rcu_barrier() +in its exit function as follows:: + + 1 static void + 2 rcu_torture_cleanup(void) + 3 { + 4 int i; + 5 + 6 fullstop = 1; + 7 if (shuffler_task != NULL) { + 8 VERBOSE_PRINTK_STRING("Stopping rcu_torture_shuffle task"); + 9 kthread_stop(shuffler_task); + 10 } + 11 shuffler_task = NULL; 12 - 13 if (writer_task != NULL) { - 14 VERBOSE_PRINTK_STRING("Stopping rcu_torture_writer task"); - 15 kthread_stop(writer_task); - 16 } - 17 writer_task = NULL; + 13 if (writer_task != NULL) { + 14 VERBOSE_PRINTK_STRING("Stopping rcu_torture_writer task"); + 15 kthread_stop(writer_task); + 16 } + 17 writer_task = NULL; 18 - 19 if (reader_tasks != NULL) { - 20 for (i = 0; i < nrealreaders; i++) { - 21 if (reader_tasks[i] != NULL) { - 22 VERBOSE_PRINTK_STRING( - 23 "Stopping rcu_torture_reader task"); - 24 kthread_stop(reader_tasks[i]); - 25 } - 26 reader_tasks[i] = NULL; - 27 } - 28 kfree(reader_tasks); - 29 reader_tasks = NULL; - 30 } - 31 rcu_torture_current = NULL; + 19 if (reader_tasks != NULL) { + 20 for (i = 0; i < nrealreaders; i++) { + 21 if (reader_tasks[i] != NULL) { + 22 VERBOSE_PRINTK_STRING( + 23 "Stopping rcu_torture_reader task"); + 24 kthread_stop(reader_tasks[i]); + 25 } + 26 reader_tasks[i] = NULL; + 27 } + 28 kfree(reader_tasks); + 29 reader_tasks = NULL; + 30 } + 31 rcu_torture_current = NULL; 32 - 33 if (fakewriter_tasks != NULL) { - 34 for (i = 0; i < nfakewriters; i++) { - 35 if (fakewriter_tasks[i] != NULL) { - 36 VERBOSE_PRINTK_STRING( - 37 "Stopping rcu_torture_fakewriter task"); - 38 kthread_stop(fakewriter_tasks[i]); - 39 } - 40 fakewriter_tasks[i] = NULL; - 41 } - 42 kfree(fakewriter_tasks); - 43 fakewriter_tasks = NULL; - 44 } + 33 if (fakewriter_tasks != NULL) { + 34 for (i = 0; i < nfakewriters; i++) { + 35 if (fakewriter_tasks[i] != NULL) { + 36 VERBOSE_PRINTK_STRING( + 37 "Stopping rcu_torture_fakewriter task"); + 38 kthread_stop(fakewriter_tasks[i]); + 39 } + 40 fakewriter_tasks[i] = NULL; + 41 } + 42 kfree(fakewriter_tasks); + 43 fakewriter_tasks = NULL; + 44 } 45 - 46 if (stats_task != NULL) { - 47 VERBOSE_PRINTK_STRING("Stopping rcu_torture_stats task"); - 48 kthread_stop(stats_task); - 49 } - 50 stats_task = NULL; + 46 if (stats_task != NULL) { + 47 VERBOSE_PRINTK_STRING("Stopping rcu_torture_stats task"); + 48 kthread_stop(stats_task); + 49 } + 50 stats_task = NULL; 51 - 52 /* Wait for all RCU callbacks to fire. */ - 53 rcu_barrier(); + 52 /* Wait for all RCU callbacks to fire. */ + 53 rcu_barrier(); 54 - 55 rcu_torture_stats_print(); /* -After- the stats thread is stopped! */ + 55 rcu_torture_stats_print(); /* -After- the stats thread is stopped! */ 56 - 57 if (cur_ops->cleanup != NULL) - 58 cur_ops->cleanup(); - 59 if (atomic_read(&n_rcu_torture_error)) - 60 rcu_torture_print_module_parms("End of test: FAILURE"); - 61 else - 62 rcu_torture_print_module_parms("End of test: SUCCESS"); - 63 } + 57 if (cur_ops->cleanup != NULL) + 58 cur_ops->cleanup(); + 59 if (atomic_read(&n_rcu_torture_error)) + 60 rcu_torture_print_module_parms("End of test: FAILURE"); + 61 else + 62 rcu_torture_print_module_parms("End of test: SUCCESS"); + 63 } Line 6 sets a global variable that prevents any RCU callbacks from re-posting themselves. This will not be necessary in most cases, since @@ -190,16 +169,17 @@ Quick Quiz #1: :ref:`Answer to Quick Quiz #1 ` Your module might have additional complications. For example, if your -module invokes call_rcu() from timers, you will need to first cancel all -the timers, and only then invoke rcu_barrier() to wait for any remaining +module invokes call_rcu() from timers, you will need to first refrain +from posting new timers, cancel (or wait for) all the already-posted +timers, and only then invoke rcu_barrier() to wait for any remaining RCU callbacks to complete. -Of course, if you module uses call_rcu(), you will need to invoke +Of course, if your module uses call_rcu(), you will need to invoke rcu_barrier() before unloading. Similarly, if your module uses call_srcu(), you will need to invoke srcu_barrier() before unloading, and on the same srcu_struct structure. If your module uses call_rcu() -**and** call_srcu(), then you will need to invoke rcu_barrier() **and** -srcu_barrier(). +**and** call_srcu(), then (as noted above) you will need to invoke +rcu_barrier() **and** srcu_barrier(). Implementing rcu_barrier() @@ -211,27 +191,40 @@ queues. His implementation queues an RCU callback on each of the per-CPU callback queues, and then waits until they have all started executing, at which point, all earlier RCU callbacks are guaranteed to have completed. -The original code for rcu_barrier() was as follows:: - - 1 void rcu_barrier(void) - 2 { - 3 BUG_ON(in_interrupt()); - 4 /* Take cpucontrol mutex to protect against CPU hotplug */ - 5 mutex_lock(&rcu_barrier_mutex); - 6 init_completion(&rcu_barrier_completion); - 7 atomic_set(&rcu_barrier_cpu_count, 0); - 8 on_each_cpu(rcu_barrier_func, NULL, 0, 1); - 9 wait_for_completion(&rcu_barrier_completion); - 10 mutex_unlock(&rcu_barrier_mutex); - 11 } - -Line 3 verifies that the caller is in process context, and lines 5 and 10 +The original code for rcu_barrier() was roughly as follows:: + + 1 void rcu_barrier(void) + 2 { + 3 BUG_ON(in_interrupt()); + 4 /* Take cpucontrol mutex to protect against CPU hotplug */ + 5 mutex_lock(&rcu_barrier_mutex); + 6 init_completion(&rcu_barrier_completion); + 7 atomic_set(&rcu_barrier_cpu_count, 1); + 8 on_each_cpu(rcu_barrier_func, NULL, 0, 1); + 9 if (atomic_dec_and_test(&rcu_barrier_cpu_count)) + 10 complete(&rcu_barrier_completion); + 11 wait_for_completion(&rcu_barrier_completion); + 12 mutex_unlock(&rcu_barrier_mutex); + 13 } + +Line 3 verifies that the caller is in process context, and lines 5 and 12 use rcu_barrier_mutex to ensure that only one rcu_barrier() is using the global completion and counters at a time, which are initialized on lines 6 and 7. Line 8 causes each CPU to invoke rcu_barrier_func(), which is shown below. Note that the final "1" in on_each_cpu()'s argument list ensures that all the calls to rcu_barrier_func() will have completed -before on_each_cpu() returns. Line 9 then waits for the completion. +before on_each_cpu() returns. Line 9 removes the initial count from +rcu_barrier_cpu_count, and if this count is now zero, line 10 finalizes +the completion, which prevents line 11 from blocking. Either way, +line 11 then waits (if needed) for the completion. + +.. _rcubarrier_quiz_2: + +Quick Quiz #2: + Why doesn't line 8 initialize rcu_barrier_cpu_count to zero, + thereby avoiding the need for lines 9 and 10? + +:ref:`Answer to Quick Quiz #2 ` This code was rewritten in 2008 and several times thereafter, but this still gives the general idea. @@ -239,21 +232,21 @@ still gives the general idea. The rcu_barrier_func() runs on each CPU, where it invokes call_rcu() to post an RCU callback, as follows:: - 1 static void rcu_barrier_func(void *notused) - 2 { - 3 int cpu = smp_processor_id(); - 4 struct rcu_data *rdp = &per_cpu(rcu_data, cpu); - 5 struct rcu_head *head; - 6 - 7 head = &rdp->barrier; - 8 atomic_inc(&rcu_barrier_cpu_count); - 9 call_rcu(head, rcu_barrier_callback); - 10 } + 1 static void rcu_barrier_func(void *notused) + 2 { + 3 int cpu = smp_processor_id(); + 4 struct rcu_data *rdp = &per_cpu(rcu_data, cpu); + 5 struct rcu_head *head; + 6 + 7 head = &rdp->barrier; + 8 atomic_inc(&rcu_barrier_cpu_count); + 9 call_rcu(head, rcu_barrier_callback); + 10 } Lines 3 and 4 locate RCU's internal per-CPU rcu_data structure, which contains the struct rcu_head that needed for the later call to call_rcu(). Line 7 picks up a pointer to this struct rcu_head, and line -8 increments a global counter. This counter will later be decremented +8 increments the global counter. This counter will later be decremented by the callback. Line 9 then registers the rcu_barrier_callback() on the current CPU's queue. @@ -261,33 +254,34 @@ The rcu_barrier_callback() function simply atomically decrements the rcu_barrier_cpu_count variable and finalizes the completion when it reaches zero, as follows:: - 1 static void rcu_barrier_callback(struct rcu_head *notused) - 2 { - 3 if (atomic_dec_and_test(&rcu_barrier_cpu_count)) - 4 complete(&rcu_barrier_completion); - 5 } + 1 static void rcu_barrier_callback(struct rcu_head *notused) + 2 { + 3 if (atomic_dec_and_test(&rcu_barrier_cpu_count)) + 4 complete(&rcu_barrier_completion); + 5 } -.. _rcubarrier_quiz_2: +.. _rcubarrier_quiz_3: -Quick Quiz #2: +Quick Quiz #3: What happens if CPU 0's rcu_barrier_func() executes immediately (thus incrementing rcu_barrier_cpu_count to the value one), but the other CPU's rcu_barrier_func() invocations are delayed for a full grace period? Couldn't this result in rcu_barrier() returning prematurely? -:ref:`Answer to Quick Quiz #2 ` +:ref:`Answer to Quick Quiz #3 ` The current rcu_barrier() implementation is more complex, due to the need to avoid disturbing idle CPUs (especially on battery-powered systems) and the need to minimally disturb non-idle CPUs in real-time systems. -However, the code above illustrates the concepts. +In addition, a great many optimizations have been applied. However, +the code above illustrates the concepts. rcu_barrier() Summary --------------------- -The rcu_barrier() primitive has seen relatively little use, since most +The rcu_barrier() primitive is used relatively infrequently, since most code using RCU is in the core kernel rather than in modules. However, if you are using RCU from an unloadable module, you need to use rcu_barrier() so that your module may be safely unloaded. @@ -302,7 +296,8 @@ Quick Quiz #1: Is there any other situation where rcu_barrier() might be required? -Answer: Interestingly enough, rcu_barrier() was not originally +Answer: + Interestingly enough, rcu_barrier() was not originally implemented for module unloading. Nikita Danilov was using RCU in a filesystem, which resulted in a similar situation at filesystem-unmount time. Dipankar Sarma coded up rcu_barrier() @@ -318,13 +313,48 @@ Answer: Interestingly enough, rcu_barrier() was not originally .. _answer_rcubarrier_quiz_2: Quick Quiz #2: + Why doesn't line 8 initialize rcu_barrier_cpu_count to zero, + thereby avoiding the need for lines 9 and 10? + +Answer: + Suppose that the on_each_cpu() function shown on line 8 was + delayed, so that CPU 0's rcu_barrier_func() executed and + the corresponding grace period elapsed, all before CPU 1's + rcu_barrier_func() started executing. This would result in + rcu_barrier_cpu_count being decremented to zero, so that line + 11's wait_for_completion() would return immediately, failing to + wait for CPU 1's callbacks to be invoked. + + Note that this was not a problem when the rcu_barrier() code + was first added back in 2005. This is because on_each_cpu() + disables preemption, which acted as an RCU read-side critical + section, thus preventing CPU 0's grace period from completing + until on_each_cpu() had dealt with all of the CPUs. However, + with the advent of preemptible RCU, rcu_barrier() no longer + waited on nonpreemptible regions of code in preemptible kernels, + that being the job of the new rcu_barrier_sched() function. + + However, with the RCU flavor consolidation around v4.20, this + possibility was once again ruled out, because the consolidated + RCU once again waits on nonpreemptible regions of code. + + Nevertheless, that extra count might still be a good idea. + Relying on these sort of accidents of implementation can result + in later surprise bugs when the implementation changes. + +:ref:`Back to Quick Quiz #2 ` + +.. _answer_rcubarrier_quiz_3: + +Quick Quiz #3: What happens if CPU 0's rcu_barrier_func() executes immediately (thus incrementing rcu_barrier_cpu_count to the value one), but the other CPU's rcu_barrier_func() invocations are delayed for a full grace period? Couldn't this result in rcu_barrier() returning prematurely? -Answer: This cannot happen. The reason is that on_each_cpu() has its last +Answer: + This cannot happen. The reason is that on_each_cpu() has its last argument, the wait flag, set to "1". This flag is passed through to smp_call_function() and further to smp_call_function_on_cpu(), causing this latter to spin until the cross-CPU invocation of @@ -336,18 +366,15 @@ Answer: This cannot happen. The reason is that on_each_cpu() has its last Therefore, on_each_cpu() disables preemption across its call to smp_call_function() and also across the local call to - rcu_barrier_func(). This prevents the local CPU from context - switching, again preventing grace periods from completing. This + rcu_barrier_func(). Because recent RCU implementations treat + preemption-disabled regions of code as RCU read-side critical + sections, this prevents grace periods from completing. This means that all CPUs have executed rcu_barrier_func() before the first rcu_barrier_callback() can possibly execute, in turn preventing rcu_barrier_cpu_count from prematurely reaching zero. - Currently, -rt implementations of RCU keep but a single global - queue for RCU callbacks, and thus do not suffer from this - problem. However, when the -rt RCU eventually does have per-CPU - callback queues, things will have to change. One simple change - is to add an rcu_read_lock() before line 8 of rcu_barrier() - and an rcu_read_unlock() after line 8 of this same function. If - you can think of a better change, please let me know! + But if on_each_cpu() ever decides to forgo disabling preemption, + as might well happen due to real-time latency considerations, + initializing rcu_barrier_cpu_count to one will save the day. -:ref:`Back to Quick Quiz #2 ` +:ref:`Back to Quick Quiz #3 ` diff --git a/Documentation/RCU/rculist_nulls.rst b/Documentation/RCU/rculist_nulls.rst index ca4692775ad41a68fb35175cc510a18ffcaaf492..9a734bf54b7664ce11670027d1b9c56ba71aa350 100644 --- a/Documentation/RCU/rculist_nulls.rst +++ b/Documentation/RCU/rculist_nulls.rst @@ -14,19 +14,19 @@ Using 'nulls' ============= Using special makers (called 'nulls') is a convenient way -to solve following problem : +to solve following problem. -A typical RCU linked list managing objects which are -allocated with SLAB_TYPESAFE_BY_RCU kmem_cache can -use following algos : +Without 'nulls', a typical RCU linked list managing objects which are +allocated with SLAB_TYPESAFE_BY_RCU kmem_cache can use the following +algorithms: -1) Lookup algo --------------- +1) Lookup algorithm +------------------- :: - rcu_read_lock() begin: + rcu_read_lock() obj = lockless_lookup(key); if (obj) { if (!try_get_ref(obj)) // might fail for free objects @@ -38,6 +38,7 @@ use following algos : */ if (obj->key != key) { // not the object we expected put_ref(obj); + rcu_read_unlock(); goto begin; } } @@ -52,9 +53,9 @@ but a version with an additional memory barrier (smp_rmb()) { struct hlist_node *node, *next; for (pos = rcu_dereference((head)->first); - pos && ({ next = pos->next; smp_rmb(); prefetch(next); 1; }) && - ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1; }); - pos = rcu_dereference(next)) + pos && ({ next = pos->next; smp_rmb(); prefetch(next); 1; }) && + ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1; }); + pos = rcu_dereference(next)) if (obj->key == key) return obj; return NULL; @@ -64,9 +65,9 @@ And note the traditional hlist_for_each_entry_rcu() misses this smp_rmb():: struct hlist_node *node; for (pos = rcu_dereference((head)->first); - pos && ({ prefetch(pos->next); 1; }) && - ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1; }); - pos = rcu_dereference(pos->next)) + pos && ({ prefetch(pos->next); 1; }) && + ({ tpos = hlist_entry(pos, typeof(*tpos), member); 1; }); + pos = rcu_dereference(pos->next)) if (obj->key == key) return obj; return NULL; @@ -82,36 +83,32 @@ Quoting Corey Minyard:: solved by pre-fetching the "next" field (with proper barriers) before checking the key." -2) Insert algo --------------- +2) Insertion algorithm +---------------------- We need to make sure a reader cannot read the new 'obj->obj_next' value -and previous value of 'obj->key'. Or else, an item could be deleted +and previous value of 'obj->key'. Otherwise, an item could be deleted from a chain, and inserted into another chain. If new chain was empty -before the move, 'next' pointer is NULL, and lockless reader can -not detect it missed following items in original chain. +before the move, 'next' pointer is NULL, and lockless reader can not +detect the fact that it missed following items in original chain. :: /* - * Please note that new inserts are done at the head of list, - * not in the middle or end. - */ + * Please note that new inserts are done at the head of list, + * not in the middle or end. + */ obj = kmem_cache_alloc(...); lock_chain(); // typically a spin_lock() obj->key = key; - /* - * we need to make sure obj->key is updated before obj->next - * or obj->refcnt - */ - smp_wmb(); - atomic_set(&obj->refcnt, 1); + atomic_set_release(&obj->refcnt, 1); // key before refcnt hlist_add_head_rcu(&obj->obj_node, list); unlock_chain(); // typically a spin_unlock() -3) Remove algo --------------- +3) Removal algorithm +-------------------- + Nothing special here, we can use a standard RCU hlist deletion. But thanks to SLAB_TYPESAFE_BY_RCU, beware a deleted object can be reused very very fast (before the end of RCU grace period) @@ -133,7 +130,7 @@ Avoiding extra smp_rmb() ======================== With hlist_nulls we can avoid extra smp_rmb() in lockless_lookup() -and extra smp_wmb() in insert function. +and extra _release() in insert function. For example, if we choose to store the slot number as the 'nulls' end-of-list marker for each slot of the hash table, we can detect @@ -142,59 +139,61 @@ to another chain) checking the final 'nulls' value if the lookup met the end of chain. If final 'nulls' value is not the slot number, then we must restart the lookup at the beginning. If the object was moved to the same chain, -then the reader doesn't care : It might eventually +then the reader doesn't care: It might occasionally scan the list again without harm. -1) lookup algo --------------- +1) lookup algorithm +------------------- :: head = &table[slot]; - rcu_read_lock(); begin: + rcu_read_lock(); hlist_nulls_for_each_entry_rcu(obj, node, head, member) { if (obj->key == key) { - if (!try_get_ref(obj)) // might fail for free objects + if (!try_get_ref(obj)) { // might fail for free objects + rcu_read_unlock(); goto begin; + } if (obj->key != key) { // not the object we expected put_ref(obj); + rcu_read_unlock(); goto begin; } - goto out; + goto out; + } + } + + // If the nulls value we got at the end of this lookup is + // not the expected one, we must restart lookup. + // We probably met an item that was moved to another chain. + if (get_nulls_value(node) != slot) { + put_ref(obj); + rcu_read_unlock(); + goto begin; } - /* - * if the nulls value we got at the end of this lookup is - * not the expected one, we must restart lookup. - * We probably met an item that was moved to another chain. - */ - if (get_nulls_value(node) != slot) - goto begin; obj = NULL; out: rcu_read_unlock(); -2) Insert function ------------------- +2) Insert algorithm +------------------- :: /* - * Please note that new inserts are done at the head of list, - * not in the middle or end. - */ + * Please note that new inserts are done at the head of list, + * not in the middle or end. + */ obj = kmem_cache_alloc(cachep); lock_chain(); // typically a spin_lock() obj->key = key; + atomic_set_release(&obj->refcnt, 1); // key before refcnt /* - * changes to obj->key must be visible before refcnt one - */ - smp_wmb(); - atomic_set(&obj->refcnt, 1); - /* - * insert obj in RCU way (readers might be traversing chain) - */ + * insert obj in RCU way (readers might be traversing chain) + */ hlist_nulls_add_head_rcu(&obj->obj_node, list); unlock_chain(); // typically a spin_unlock() diff --git a/Documentation/RCU/stallwarn.rst b/Documentation/RCU/stallwarn.rst index e38c587067fc8c38d5c65eb03f5ab38b852d3c27..ca7b7cd806a16c9c98fdf04eadbe4f4997249c82 100644 --- a/Documentation/RCU/stallwarn.rst +++ b/Documentation/RCU/stallwarn.rst @@ -25,10 +25,10 @@ warnings: - A CPU looping with bottom halves disabled. -- For !CONFIG_PREEMPTION kernels, a CPU looping anywhere in the kernel - without invoking schedule(). If the looping in the kernel is - really expected and desirable behavior, you might need to add - some calls to cond_resched(). +- For !CONFIG_PREEMPTION kernels, a CPU looping anywhere in the + kernel without potentially invoking schedule(). If the looping + in the kernel is really expected and desirable behavior, you + might need to add some calls to cond_resched(). - Booting Linux using a console connection that is too slow to keep up with the boot-time console-message rate. For example, @@ -108,16 +108,17 @@ warnings: - A bug in the RCU implementation. -- A hardware failure. This is quite unlikely, but has occurred - at least once in real life. A CPU failed in a running system, - becoming unresponsive, but not causing an immediate crash. - This resulted in a series of RCU CPU stall warnings, eventually - leading the realization that the CPU had failed. +- A hardware failure. This is quite unlikely, but is not at all + uncommon in large datacenter. In one memorable case some decades + back, a CPU failed in a running system, becoming unresponsive, + but not causing an immediate crash. This resulted in a series + of RCU CPU stall warnings, eventually leading the realization + that the CPU had failed. -The RCU, RCU-sched, and RCU-tasks implementations have CPU stall warning. -Note that SRCU does *not* have CPU stall warnings. Please note that -RCU only detects CPU stalls when there is a grace period in progress. -No grace period, no CPU stall warnings. +The RCU, RCU-sched, RCU-tasks, and RCU-tasks-trace implementations have +CPU stall warning. Note that SRCU does *not* have CPU stall warnings. +Please note that RCU only detects CPU stalls when there is a grace period +in progress. No grace period, no CPU stall warnings. To diagnose the cause of the stall, inspect the stack traces. The offending function will usually be near the top of the stack. @@ -205,16 +206,21 @@ RCU_STALL_RAT_DELAY rcupdate.rcu_task_stall_timeout ------------------------------- - This boot/sysfs parameter controls the RCU-tasks stall warning - interval. A value of zero or less suppresses RCU-tasks stall - warnings. A positive value sets the stall-warning interval - in seconds. An RCU-tasks stall warning starts with the line: + This boot/sysfs parameter controls the RCU-tasks and + RCU-tasks-trace stall warning intervals. A value of zero or less + suppresses RCU-tasks stall warnings. A positive value sets the + stall-warning interval in seconds. An RCU-tasks stall warning + starts with the line: INFO: rcu_tasks detected stalls on tasks: And continues with the output of sched_show_task() for each task stalling the current RCU-tasks grace period. + An RCU-tasks-trace stall warning starts (and continues) similarly: + + INFO: rcu_tasks_trace detected stalls on tasks + Interpreting RCU's CPU Stall-Detector "Splats" ============================================== @@ -248,7 +254,8 @@ dynticks counter, which will have an even-numbered value if the CPU is in dyntick-idle mode and an odd-numbered value otherwise. The hex number between the two "/"s is the value of the nesting, which will be a small non-negative number if in the idle loop (as shown above) and a -very large positive number otherwise. +very large positive number otherwise. The number following the final +"/" is the NMI nesting, which will be a small non-negative number. The "softirq=" portion of the message tracks the number of RCU softirq handlers that the stalled CPU has executed. The number before the "/" @@ -383,3 +390,95 @@ for example, "P3421". It is entirely possible to see stall warnings from normal and from expedited grace periods at about the same time during the same run. + +RCU_CPU_STALL_CPUTIME +===================== + +In kernels built with CONFIG_RCU_CPU_STALL_CPUTIME=y or booted with +rcupdate.rcu_cpu_stall_cputime=1, the following additional information +is supplied with each RCU CPU stall warning:: + + rcu: hardirqs softirqs csw/system + rcu: number: 624 45 0 + rcu: cputime: 69 1 2425 ==> 2500(ms) + +These statistics are collected during the sampling period. The values +in row "number:" are the number of hard interrupts, number of soft +interrupts, and number of context switches on the stalled CPU. The +first three values in row "cputime:" indicate the CPU time in +milliseconds consumed by hard interrupts, soft interrupts, and tasks +on the stalled CPU. The last number is the measurement interval, again +in milliseconds. Because user-mode tasks normally do not cause RCU CPU +stalls, these tasks are typically kernel tasks, which is why only the +system CPU time are considered. + +The sampling period is shown as follows:: + + |<------------first timeout---------->|<-----second timeout----->| + |<--half timeout-->|<--half timeout-->| | + | |<--first period-->| | + | |<-----------second sampling period---------->| + | | | | + snapshot time point 1st-stall 2nd-stall + +The following describes four typical scenarios: + +1. A CPU looping with interrupts disabled. + + :: + + rcu: hardirqs softirqs csw/system + rcu: number: 0 0 0 + rcu: cputime: 0 0 0 ==> 2500(ms) + + Because interrupts have been disabled throughout the measurement + interval, there are no interrupts and no context switches. + Furthermore, because CPU time consumption was measured using interrupt + handlers, the system CPU consumption is misleadingly measured as zero. + This scenario will normally also have "(0 ticks this GP)" printed on + this CPU's summary line. + +2. A CPU looping with bottom halves disabled. + + This is similar to the previous example, but with non-zero number of + and CPU time consumed by hard interrupts, along with non-zero CPU + time consumed by in-kernel execution:: + + rcu: hardirqs softirqs csw/system + rcu: number: 624 0 0 + rcu: cputime: 49 0 2446 ==> 2500(ms) + + The fact that there are zero softirqs gives a hint that these were + disabled, perhaps via local_bh_disable(). It is of course possible + that there were no softirqs, perhaps because all events that would + result in softirq execution are confined to other CPUs. In this case, + the diagnosis should continue as shown in the next example. + +3. A CPU looping with preemption disabled. + + Here, only the number of context switches is zero:: + + rcu: hardirqs softirqs csw/system + rcu: number: 624 45 0 + rcu: cputime: 69 1 2425 ==> 2500(ms) + + This situation hints that the stalled CPU was looping with preemption + disabled. + +4. No looping, but massive hard and soft interrupts. + + :: + + rcu: hardirqs softirqs csw/system + rcu: number: xx xx 0 + rcu: cputime: xx xx 0 ==> 2500(ms) + + Here, the number and CPU time of hard interrupts are all non-zero, + but the number of context switches and the in-kernel CPU time consumed + are zero. The number and cputime of soft interrupts will usually be + non-zero, but could be zero, for example, if the CPU was spinning + within a single hard interrupt handler. + + If this type of RCU CPU stall warning can be reproduced, you can + narrow it down by looking at /proc/interrupts or by writing code to + trace each interrupt, for example, by referring to show_interrupts(). diff --git a/Documentation/RCU/torture.rst b/Documentation/RCU/torture.rst index a9014771306292f305dc2b3df6f21f9846e85764..0316ba0c692255d523a885abba51997085f7e8be 100644 --- a/Documentation/RCU/torture.rst +++ b/Documentation/RCU/torture.rst @@ -206,7 +206,11 @@ values for memory may require disabling the callback-flooding tests using the --bootargs parameter discussed below. Sometimes additional debugging is useful, and in such cases the --kconfig -parameter to kvm.sh may be used, for example, ``--kconfig 'CONFIG_KASAN=y'``. +parameter to kvm.sh may be used, for example, ``--kconfig 'CONFIG_RCU_EQS_DEBUG=y'``. +In addition, there are the --gdb, --kasan, and --kcsan parameters. +Note that --gdb limits you to one scenario per kvm.sh run and requires +that you have another window open from which to run ``gdb`` as instructed +by the script. Kernel boot arguments can also be supplied, for example, to control rcutorture's module parameters. For example, to test a change to RCU's @@ -219,10 +223,17 @@ require disabling rcutorture's callback-flooding tests:: --bootargs 'rcutorture.fwd_progress=0' Sometimes all that is needed is a full set of kernel builds. This is -what the --buildonly argument does. +what the --buildonly parameter does. -Finally, the --trust-make argument allows each kernel build to reuse what -it can from the previous kernel build. +The --duration parameter can override the default run time of 30 minutes. +For example, ``--duration 2d`` would run for two days, ``--duration 3h`` +would run for three hours, ``--duration 5m`` would run for five minutes, +and ``--duration 45s`` would run for 45 seconds. This last can be useful +for tracking down rare boot-time failures. + +Finally, the --trust-make parameter allows each kernel build to reuse what +it can from the previous kernel build. Please note that without the +--trust-make parameter, your tags files may be demolished. There are additional more arcane arguments that are documented in the source code of the kvm.sh script. @@ -291,3 +302,73 @@ the following summary at the end of the run on a 12-CPU system:: TREE07 ------- 167347 GPs (30.9902/s) [rcu: g1079021 f0x0 ] n_max_cbs: 478732 CPU count limited from 16 to 12 TREE09 ------- 752238 GPs (139.303/s) [rcu: g13075057 f0x0 ] n_max_cbs: 99011 + + +Repeated Runs +============= + +Suppose that you are chasing down a rare boot-time failure. Although you +could use kvm.sh, doing so will rebuild the kernel on each run. If you +need (say) 1,000 runs to have confidence that you have fixed the bug, +these pointless rebuilds can become extremely annoying. + +This is why kvm-again.sh exists. + +Suppose that a previous kvm.sh run left its output in this directory:: + + tools/testing/selftests/rcutorture/res/2022.11.03-11.26.28 + +Then this run can be re-run without rebuilding as follow: + + kvm-again.sh tools/testing/selftests/rcutorture/res/2022.11.03-11.26.28 + +A few of the original run's kvm.sh parameters may be overridden, perhaps +most notably --duration and --bootargs. For example:: + + kvm-again.sh tools/testing/selftests/rcutorture/res/2022.11.03-11.26.28 \ + --duration 45s + +would re-run the previous test, but for only 45 seconds, thus facilitating +tracking down the aforementioned rare boot-time failure. + + +Distributed Runs +================ + +Although kvm.sh is quite useful, its testing is confined to a single +system. It is not all that hard to use your favorite framework to cause +(say) 5 instances of kvm.sh to run on your 5 systems, but this will very +likely unnecessarily rebuild kernels. In addition, manually distributing +the desired rcutorture scenarios across the available systems can be +painstaking and error-prone. + +And this is why the kvm-remote.sh script exists. + +If you the following command works:: + + ssh system0 date + +and if it also works for system1, system2, system3, system4, and system5, +and all of these systems have 64 CPUs, you can type:: + + kvm-remote.sh "system0 system1 system2 system3 system4 system5" \ + --cpus 64 --duration 8h --configs "5*CFLIST" + +This will build each default scenario's kernel on the local system, then +spread each of five instances of each scenario over the systems listed, +running each scenario for eight hours. At the end of the runs, the +results will be gathered, recorded, and printed. Most of the parameters +that kvm.sh will accept can be passed to kvm-remote.sh, but the list of +systems must come first. + +The kvm.sh ``--dryrun scenarios`` argument is useful for working out +how many scenarios may be run in one batch across a group of systems. + +You can also re-run a previous remote run in a manner similar to kvm.sh: + + kvm-remote.sh "system0 system1 system2 system3 system4 system5" \ + tools/testing/selftests/rcutorture/res/2022.11.03-11.26.28-remote \ + --duration 24h + +In this case, most of the kvm-again.sh parmeters may be supplied following +the pathname of the old run-results directory. diff --git a/Documentation/RCU/whatisRCU.rst b/Documentation/RCU/whatisRCU.rst index 1c747ac3f2c8e0db247382490adefdfb7d88bba3..2c5563a91998f93d25c2e81c49336b60c26d330e 100644 --- a/Documentation/RCU/whatisRCU.rst +++ b/Documentation/RCU/whatisRCU.rst @@ -16,18 +16,23 @@ to start learning about RCU: | 6. The RCU API, 2019 Edition https://lwn.net/Articles/777036/ | 2019 Big API Table https://lwn.net/Articles/777165/ +For those preferring video: + +| 1. Unraveling RCU Mysteries: Fundamentals https://www.linuxfoundation.org/webinars/unraveling-rcu-usage-mysteries +| 2. Unraveling RCU Mysteries: Additional Use Cases https://www.linuxfoundation.org/webinars/unraveling-rcu-usage-mysteries-additional-use-cases + What is RCU? RCU is a synchronization mechanism that was added to the Linux kernel during the 2.5 development effort that is optimized for read-mostly -situations. Although RCU is actually quite simple once you understand it, -getting there can sometimes be a challenge. Part of the problem is that -most of the past descriptions of RCU have been written with the mistaken -assumption that there is "one true way" to describe RCU. Instead, -the experience has been that different people must take different paths -to arrive at an understanding of RCU. This document provides several -different paths, as follows: +situations. Although RCU is actually quite simple, making effective use +of it requires you to think differently about your code. Another part +of the problem is the mistaken assumption that there is "one true way" to +describe and to use RCU. Instead, the experience has been that different +people must take different paths to arrive at an understanding of RCU, +depending on their experiences and use cases. This document provides +several different paths, as follows: :ref:`1. RCU OVERVIEW <1_whatisRCU>` @@ -157,34 +162,36 @@ rcu_read_lock() ^^^^^^^^^^^^^^^ void rcu_read_lock(void); - Used by a reader to inform the reclaimer that the reader is - entering an RCU read-side critical section. It is illegal - to block while in an RCU read-side critical section, though - kernels built with CONFIG_PREEMPT_RCU can preempt RCU - read-side critical sections. Any RCU-protected data structure - accessed during an RCU read-side critical section is guaranteed to - remain unreclaimed for the full duration of that critical section. - Reference counts may be used in conjunction with RCU to maintain - longer-term references to data structures. + This temporal primitive is used by a reader to inform the + reclaimer that the reader is entering an RCU read-side critical + section. It is illegal to block while in an RCU read-side + critical section, though kernels built with CONFIG_PREEMPT_RCU + can preempt RCU read-side critical sections. Any RCU-protected + data structure accessed during an RCU read-side critical section + is guaranteed to remain unreclaimed for the full duration of that + critical section. Reference counts may be used in conjunction + with RCU to maintain longer-term references to data structures. rcu_read_unlock() ^^^^^^^^^^^^^^^^^ void rcu_read_unlock(void); - Used by a reader to inform the reclaimer that the reader is - exiting an RCU read-side critical section. Note that RCU - read-side critical sections may be nested and/or overlapping. + This temporal primitives is used by a reader to inform the + reclaimer that the reader is exiting an RCU read-side critical + section. Note that RCU read-side critical sections may be nested + and/or overlapping. synchronize_rcu() ^^^^^^^^^^^^^^^^^ void synchronize_rcu(void); - Marks the end of updater code and the beginning of reclaimer - code. It does this by blocking until all pre-existing RCU - read-side critical sections on all CPUs have completed. - Note that synchronize_rcu() will **not** necessarily wait for - any subsequent RCU read-side critical sections to complete. - For example, consider the following sequence of events:: + This temporal primitive marks the end of updater code and the + beginning of reclaimer code. It does this by blocking until + all pre-existing RCU read-side critical sections on all CPUs + have completed. Note that synchronize_rcu() will **not** + necessarily wait for any subsequent RCU read-side critical + sections to complete. For example, consider the following + sequence of events:: CPU 0 CPU 1 CPU 2 ----------------- ------------------------- --------------- @@ -211,13 +218,13 @@ synchronize_rcu() to be useful in all but the most read-intensive situations, synchronize_rcu()'s overhead must also be quite small. - The call_rcu() API is a callback form of synchronize_rcu(), - and is described in more detail in a later section. Instead of - blocking, it registers a function and argument which are invoked - after all ongoing RCU read-side critical sections have completed. - This callback variant is particularly useful in situations where - it is illegal to block or where update-side performance is - critically important. + The call_rcu() API is an asynchronous callback form of + synchronize_rcu(), and is described in more detail in a later + section. Instead of blocking, it registers a function and + argument which are invoked after all ongoing RCU read-side + critical sections have completed. This callback variant is + particularly useful in situations where it is illegal to block + or where update-side performance is critically important. However, the call_rcu() API should not be used lightly, as use of the synchronize_rcu() API generally results in simpler code. @@ -236,11 +243,13 @@ rcu_assign_pointer() would be cool to be able to declare a function in this manner. (Compiler experts will no doubt disagree.) - The updater uses this function to assign a new value to an + The updater uses this spatial macro to assign a new value to an RCU-protected pointer, in order to safely communicate the change - in value from the updater to the reader. This macro does not - evaluate to an rvalue, but it does execute any memory-barrier - instructions required for a given CPU architecture. + in value from the updater to the reader. This is a spatial (as + opposed to temporal) macro. It does not evaluate to an rvalue, + but it does execute any memory-barrier instructions required + for a given CPU architecture. Its ordering properties are that + of a store-release operation. Perhaps just as important, it serves to document (1) which pointers are protected by RCU and (2) the point at which a @@ -255,14 +264,15 @@ rcu_dereference() Like rcu_assign_pointer(), rcu_dereference() must be implemented as a macro. - The reader uses rcu_dereference() to fetch an RCU-protected - pointer, which returns a value that may then be safely - dereferenced. Note that rcu_dereference() does not actually - dereference the pointer, instead, it protects the pointer for - later dereferencing. It also executes any needed memory-barrier - instructions for a given CPU architecture. Currently, only Alpha - needs memory barriers within rcu_dereference() -- on other CPUs, - it compiles to nothing, not even a compiler directive. + The reader uses the spatial rcu_dereference() macro to fetch + an RCU-protected pointer, which returns a value that may + then be safely dereferenced. Note that rcu_dereference() + does not actually dereference the pointer, instead, it + protects the pointer for later dereferencing. It also + executes any needed memory-barrier instructions for a given + CPU architecture. Currently, only Alpha needs memory barriers + within rcu_dereference() -- on other CPUs, it compiles to a + volatile load. Common coding practice uses rcu_dereference() to copy an RCU-protected pointer to a local variable, then dereferences @@ -355,12 +365,15 @@ reader, updater, and reclaimer. synchronize_rcu() & call_rcu() -The RCU infrastructure observes the time sequence of rcu_read_lock(), +The RCU infrastructure observes the temporal sequence of rcu_read_lock(), rcu_read_unlock(), synchronize_rcu(), and call_rcu() invocations in order to determine when (1) synchronize_rcu() invocations may return to their callers and (2) call_rcu() callbacks may be invoked. Efficient implementations of the RCU infrastructure make heavy use of batching in order to amortize their overhead over many uses of the corresponding APIs. +The rcu_assign_pointer() and rcu_dereference() invocations communicate +spatial changes via stores to and loads from the RCU-protected pointer in +question. There are at least three flavors of RCU usage in the Linux kernel. The diagram above shows the most common one. On the updater side, the rcu_assign_pointer(), @@ -392,7 +405,9 @@ b. RCU applied to networking data structures that may be subjected c. RCU applied to scheduler and interrupt/NMI-handler tasks. Again, most uses will be of (a). The (b) and (c) cases are important -for specialized uses, but are relatively uncommon. +for specialized uses, but are relatively uncommon. The SRCU, RCU-Tasks, +RCU-Tasks-Rude, and RCU-Tasks-Trace have similar relationships among +their assorted primitives. .. _3_whatisRCU: @@ -468,7 +483,7 @@ So, to sum up: - Within an RCU read-side critical section, use rcu_dereference() to dereference RCU-protected pointers. -- Use some solid scheme (such as locks or semaphores) to +- Use some solid design (such as locks or semaphores) to keep concurrent updates from interfering with each other. - Use rcu_assign_pointer() to update an RCU-protected pointer. @@ -579,6 +594,14 @@ to avoid having to write your own callback:: kfree_rcu(old_fp, rcu); +If the occasional sleep is permitted, the single-argument form may +be used, omitting the rcu_head structure from struct foo. + + kfree_rcu(old_fp); + +This variant of kfree_rcu() almost never blocks, but might do so by +invoking synchronize_rcu() in response to memory-allocation failure. + Again, see checklist.rst for additional rules governing the use of RCU. .. _5_whatisRCU: @@ -596,7 +619,7 @@ lacking both functionality and performance. However, they are useful in getting a feel for how RCU works. See kernel/rcu/update.c for a production-quality implementation, and see: - http://www.rdrop.com/users/paulmck/RCU + https://docs.google.com/document/d/1X0lThx8OK0ZgLMqVoXiR4ZrGURHrXK6NyLRbeXe3Xac/edit for papers describing the Linux kernel RCU implementation. The OLS'01 and OLS'02 papers are a good introduction, and the dissertation provides @@ -929,6 +952,8 @@ unfortunately any spinlock in a ``SLAB_TYPESAFE_BY_RCU`` object must be initialized after each and every call to kmem_cache_alloc(), which renders reference-free spinlock acquisition completely unsafe. Therefore, when using ``SLAB_TYPESAFE_BY_RCU``, make proper use of a reference counter. +(Those willing to use a kmem_cache constructor may also use locking, +including cache-friendly sequence locking.) With traditional reference counting -- such as that implemented by the kref library in Linux -- there is typically code that runs when the last @@ -1047,6 +1072,30 @@ sched:: rcu_read_lock_sched_held +RCU-Tasks:: + + Critical sections Grace period Barrier + + N/A call_rcu_tasks rcu_barrier_tasks + synchronize_rcu_tasks + + +RCU-Tasks-Rude:: + + Critical sections Grace period Barrier + + N/A call_rcu_tasks_rude rcu_barrier_tasks_rude + synchronize_rcu_tasks_rude + + +RCU-Tasks-Trace:: + + Critical sections Grace period Barrier + + rcu_read_lock_trace call_rcu_tasks_trace rcu_barrier_tasks_trace + rcu_read_unlock_trace synchronize_rcu_tasks_trace + + SRCU:: Critical sections Grace period Barrier @@ -1087,35 +1136,43 @@ list can be helpful: a. Will readers need to block? If so, you need SRCU. -b. What about the -rt patchset? If readers would need to block - in an non-rt kernel, you need SRCU. If readers would block - in a -rt kernel, but not in a non-rt kernel, SRCU is not - necessary. (The -rt patchset turns spinlocks into sleeplocks, - hence this distinction.) +b. Will readers need to block and are you doing tracing, for + example, ftrace or BPF? If so, you need RCU-tasks, + RCU-tasks-rude, and/or RCU-tasks-trace. + +c. What about the -rt patchset? If readers would need to block in + an non-rt kernel, you need SRCU. If readers would block when + acquiring spinlocks in a -rt kernel, but not in a non-rt kernel, + SRCU is not necessary. (The -rt patchset turns spinlocks into + sleeplocks, hence this distinction.) -c. Do you need to treat NMI handlers, hardirq handlers, +d. Do you need to treat NMI handlers, hardirq handlers, and code segments with preemption disabled (whether via preempt_disable(), local_irq_save(), local_bh_disable(), or some other mechanism) as if they were explicit RCU readers? - If so, RCU-sched is the only choice that will work for you. - -d. Do you need RCU grace periods to complete even in the face - of softirq monopolization of one or more of the CPUs? For - example, is your code subject to network-based denial-of-service - attacks? If so, you should disable softirq across your readers, - for example, by using rcu_read_lock_bh(). - -e. Is your workload too update-intensive for normal use of + If so, RCU-sched readers are the only choice that will work + for you, but since about v4.20 you use can use the vanilla RCU + update primitives. + +e. Do you need RCU grace periods to complete even in the face of + softirq monopolization of one or more of the CPUs? For example, + is your code subject to network-based denial-of-service attacks? + If so, you should disable softirq across your readers, for + example, by using rcu_read_lock_bh(). Since about v4.20 you + use can use the vanilla RCU update primitives. + +f. Is your workload too update-intensive for normal use of RCU, but inappropriate for other synchronization mechanisms? If so, consider SLAB_TYPESAFE_BY_RCU (which was originally named SLAB_DESTROY_BY_RCU). But please be careful! -f. Do you need read-side critical sections that are respected - even though they are in the middle of the idle loop, during - user-mode execution, or on an offlined CPU? If so, SRCU is the - only choice that will work for you. +g. Do you need read-side critical sections that are respected even + on CPUs that are deep in the idle loop, during entry to or exit + from user-mode execution, or on an offlined CPU? If so, SRCU + and RCU Tasks Trace are the only choices that will work for you, + with SRCU being strongly preferred in almost all cases. -g. Otherwise, use RCU. +h. Otherwise, use RCU. Of course, this all assumes that you have determined that RCU is in fact the right tool for your job. diff --git a/Documentation/admin-guide/cgroup-v1/cgroups.rst b/Documentation/admin-guide/cgroup-v1/cgroups.rst index b0688011ed06de4f48a1bc2602a767018f3250ab..9343148ee99366ff499f069ebcd94eeedf44b2ec 100644 --- a/Documentation/admin-guide/cgroup-v1/cgroups.rst +++ b/Documentation/admin-guide/cgroup-v1/cgroups.rst @@ -80,6 +80,8 @@ access. For example, cpusets (see Documentation/admin-guide/cgroup-v1/cpusets.rs you to associate a set of CPUs and a set of memory nodes with the tasks in each cgroup. +.. _cgroups-why-needed: + 1.2 Why are cgroups needed ? ---------------------------- diff --git a/Documentation/admin-guide/cgroup-v1/memory.rst b/Documentation/admin-guide/cgroup-v1/memory.rst index 60370f2c67b99c5541fb7de4cc99878833580174..27d89495ac880a5acc43b97ab5f76c483373a81d 100644 --- a/Documentation/admin-guide/cgroup-v1/memory.rst +++ b/Documentation/admin-guide/cgroup-v1/memory.rst @@ -2,18 +2,18 @@ Memory Resource Controller ========================== -NOTE: +.. caution:: This document is hopelessly outdated and it asks for a complete rewrite. It still contains a useful information so we are keeping it here but make sure to check the current code if you need a deeper understanding. -NOTE: +.. note:: The Memory Resource Controller has generically been referred to as the memory controller in this document. Do not confuse memory controller used here with the memory controller that is used in hardware. -(For editors) In this document: +.. hint:: When we mention a cgroup (cgroupfs's directory) with memory controller, we call it "memory cgroup". When you see git-log and source code, you'll see patch's title and function names tend to use "memcg". @@ -23,7 +23,7 @@ Benefits and Purpose of the memory controller ============================================= The memory controller isolates the memory behaviour of a group of tasks -from the rest of the system. The article on LWN [12] mentions some probable +from the rest of the system. The article on LWN [12]_ mentions some probable uses of the memory controller. The memory controller can be used to a. Isolate an application or a group of applications @@ -55,7 +55,8 @@ Features: - Root cgroup has no limit controls. Kernel memory support is a work in progress, and the current version provides - basically functionality. (See Section 2.7) + basically functionality. (See :ref:`section 2.7 + `) Brief summary of control files. @@ -107,16 +108,16 @@ Brief summary of control files. ========== The memory controller has a long history. A request for comments for the memory -controller was posted by Balbir Singh [1]. At the time the RFC was posted +controller was posted by Balbir Singh [1]_. At the time the RFC was posted there were several implementations for memory control. The goal of the RFC was to build consensus and agreement for the minimal features required -for memory control. The first RSS controller was posted by Balbir Singh[2] -in Feb 2007. Pavel Emelianov [3][4][5] has since posted three versions of the -RSS controller. At OLS, at the resource management BoF, everyone suggested -that we handle both page cache and RSS together. Another request was raised -to allow user space handling of OOM. The current memory controller is +for memory control. The first RSS controller was posted by Balbir Singh [2]_ +in Feb 2007. Pavel Emelianov [3]_ [4]_ [5]_ has since posted three versions +of the RSS controller. At OLS, at the resource management BoF, everyone +suggested that we handle both page cache and RSS together. Another request was +raised to allow user space handling of OOM. The current memory controller is at version 6; it combines both mapped (RSS) and unmapped Page -Cache Control [11]. +Cache Control [11]_. 2. Memory Control ================= @@ -147,7 +148,8 @@ specific data structure (mem_cgroup) associated with it. 2.2. Accounting --------------- -:: +.. code-block:: + :caption: Figure 1: Hierarchy of Accounting +--------------------+ | mem_cgroup | @@ -167,7 +169,6 @@ specific data structure (mem_cgroup) associated with it. | | | | +---------------+ +---------------+ - (Figure 1: Hierarchy of Accounting) Figure 1 shows the important aspects of the controller @@ -221,8 +222,9 @@ behind this approach is that a cgroup that aggressively uses a shared page will eventually get charged for it (once it is uncharged from the cgroup that brought it in -- this will happen on memory pressure). -But see section 8.2: when moving a task to another cgroup, its pages may -be recharged to the new cgroup, if move_charge_at_immigrate has been chosen. +But see :ref:`section 8.2 ` when moving a +task to another cgroup, its pages may be recharged to the new cgroup, if +move_charge_at_immigrate has been chosen. 2.4 Swap Extension -------------------------------------- @@ -244,7 +246,8 @@ In this case, setting memsw.limit_in_bytes=3G will prevent bad use of swap. By using the memsw limit, you can avoid system OOM which can be caused by swap shortage. -**why 'memory+swap' rather than swap** +2.4.1 why 'memory+swap' rather than swap +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ The global LRU(kswapd) can swap out arbitrary pages. Swap-out means to move account from memory to swap...there is no change in usage of @@ -252,7 +255,8 @@ memory+swap. In other words, when we want to limit the usage of swap without affecting global LRU, memory+swap limit is better than just limiting swap from an OS point of view. -**What happens when a cgroup hits memory.memsw.limit_in_bytes** +2.4.2. What happens when a cgroup hits memory.memsw.limit_in_bytes +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ When a cgroup hits memory.memsw.limit_in_bytes, it's useless to do swap-out in this cgroup. Then, swap-out will not be done by cgroup routine and file @@ -268,26 +272,26 @@ global VM. When a cgroup goes over its limit, we first try to reclaim memory from the cgroup so as to make space for the new pages that the cgroup has touched. If the reclaim is unsuccessful, an OOM routine is invoked to select and kill the bulkiest task in the -cgroup. (See 10. OOM Control below.) +cgroup. (See :ref:`10. OOM Control ` below.) The reclaim algorithm has not been modified for cgroups, except that pages that are selected for reclaiming come from the per-cgroup LRU list. -NOTE: - Reclaim does not work for the root cgroup, since we cannot set any - limits on the root cgroup. +.. note:: + Reclaim does not work for the root cgroup, since we cannot set any + limits on the root cgroup. -Note2: - When panic_on_oom is set to "2", the whole system will panic. +.. note:: + When panic_on_oom is set to "2", the whole system will panic. When oom event notifier is registered, event will be delivered. -(See oom_control section) +(See :ref:`oom_control ` section) 2.6 Locking ----------- -Lock order is as follows: +Lock order is as follows:: Page lock (PG_locked bit of page->flags) mm->page_table_lock or split pte_lock @@ -299,6 +303,8 @@ Per-node-per-memcgroup LRU (cgroup's private LRU) is guarded by lruvec->lru_lock; PG_lru bit of page->flags is cleared before isolating a page from its LRU under lruvec->lru_lock. +.. _cgroup-v1-memory-kernel-extension: + 2.7 Kernel Memory Extension ----------------------------------------------- @@ -367,10 +373,10 @@ U != 0, K < U: never greater than the total memory, and freely set U at the cost of his QoS. -WARNING: - In the current implementation, memory reclaim will NOT be - triggered for a cgroup when it hits K while staying below U, which makes - this setup impractical. + .. warning:: + In the current implementation, memory reclaim will NOT be triggered for + a cgroup when it hits K while staying below U, which makes this setup + impractical. U != 0, K >= U: Since kmem charges will also be fed to the user counter and reclaim will be @@ -381,45 +387,41 @@ U != 0, K >= U: 3. User Interface ================= -3.0. Configuration ------------------- - -a. Enable CONFIG_CGROUPS -b. Enable CONFIG_MEMCG - -3.1. Prepare the cgroups (see cgroups.txt, Why are cgroups needed?) -------------------------------------------------------------------- +To use the user interface: -:: +1. Enable CONFIG_CGROUPS and CONFIG_MEMCG options +2. Prepare the cgroups (see :ref:`Why are cgroups needed? + ` for the background information):: # mount -t tmpfs none /sys/fs/cgroup # mkdir /sys/fs/cgroup/memory # mount -t cgroup none /sys/fs/cgroup/memory -o memory -3.2. Make the new group and move bash into it:: +3. Make the new group and move bash into it:: # mkdir /sys/fs/cgroup/memory/0 # echo $$ > /sys/fs/cgroup/memory/0/tasks -Since now we're in the 0 cgroup, we can alter the memory limit:: +4. Since now we're in the 0 cgroup, we can alter the memory limit:: # echo 4M > /sys/fs/cgroup/memory/0/memory.limit_in_bytes -NOTE: - We can use a suffix (k, K, m, M, g or G) to indicate values in kilo, - mega or gigabytes. (Here, Kilo, Mega, Giga are Kibibytes, Mebibytes, - Gibibytes.) + The limit can now be queried:: -NOTE: - We can write "-1" to reset the ``*.limit_in_bytes(unlimited)``. + # cat /sys/fs/cgroup/memory/0/memory.limit_in_bytes + 4194304 -NOTE: - We cannot set limits on the root cgroup any more. +.. note:: + We can use a suffix (k, K, m, M, g or G) to indicate values in kilo, + mega or gigabytes. (Here, Kilo, Mega, Giga are Kibibytes, Mebibytes, + Gibibytes.) -:: +.. note:: + We can write "-1" to reset the ``*.limit_in_bytes(unlimited)``. + +.. note:: + We cannot set limits on the root cgroup any more. - # cat /sys/fs/cgroup/memory/0/memory.limit_in_bytes - 4194304 We can check the usage:: @@ -458,6 +460,8 @@ test because it has noise of shared objects/status. But the above two are testing extreme situations. Trying usual test under memory controller is always helpful. +.. _cgroup-v1-memory-test-troubleshoot: + 4.1 Troubleshooting ------------------- @@ -470,8 +474,11 @@ terminated by the OOM killer. There are several causes for this: A sync followed by echo 1 > /proc/sys/vm/drop_caches will help get rid of some of the pages cached in the cgroup (page cache pages). -To know what happens, disabling OOM_Kill as per "10. OOM Control" (below) and -seeing what happens will be helpful. +To know what happens, disabling OOM_Kill as per :ref:`"10. OOM Control" +` (below) and seeing what happens will be +helpful. + +.. _cgroup-v1-memory-test-task-migration: 4.2 Task migration ------------------ @@ -482,15 +489,16 @@ remain charged to it, the charge is dropped when the page is freed or reclaimed. You can move charges of a task along with task migration. -See 8. "Move charges at task migration" +See :ref:`8. "Move charges at task migration" ` 4.3 Removing a cgroup --------------------- -A cgroup can be removed by rmdir, but as discussed in sections 4.1 and 4.2, a -cgroup might have some charge associated with it, even though all -tasks have migrated away from it. (because we charge against pages, not -against tasks.) +A cgroup can be removed by rmdir, but as discussed in :ref:`sections 4.1 +` and :ref:`4.2 +`, a cgroup might have some charge +associated with it, even though all tasks have migrated away from it. (because +we charge against pages, not against tasks.) We move the stats to parent, and no change on the charge except uncharging from the child. @@ -519,67 +527,66 @@ will be charged as a new owner of it. 5.2 stat file ------------- -memory.stat file includes following statistics - -per-memory cgroup local status -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -=============== =============================================================== -cache # of bytes of page cache memory. -rss # of bytes of anonymous and swap cache memory (includes - transparent hugepages). -rss_huge # of bytes of anonymous transparent hugepages. -mapped_file # of bytes of mapped file (includes tmpfs/shmem) -pgpgin # of charging events to the memory cgroup. The charging - event happens each time a page is accounted as either mapped - anon page(RSS) or cache page(Page Cache) to the cgroup. -pgpgout # of uncharging events to the memory cgroup. The uncharging - event happens each time a page is unaccounted from the cgroup. -swap # of bytes of swap usage -dirty # of bytes that are waiting to get written back to the disk. -writeback # of bytes of file/anon cache that are queued for syncing to - disk. -inactive_anon # of bytes of anonymous and swap cache memory on inactive - LRU list. -active_anon # of bytes of anonymous and swap cache memory on active - LRU list. -inactive_file # of bytes of file-backed memory and MADV_FREE anonymous memory( - LazyFree pages) on inactive LRU list. -active_file # of bytes of file-backed memory on active LRU list. -unevictable # of bytes of memory that cannot be reclaimed (mlocked etc). -=============== =============================================================== - -status considering hierarchy (see memory.use_hierarchy settings) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -========================= =================================================== -hierarchical_memory_limit # of bytes of memory limit with regard to hierarchy - under which the memory cgroup is -hierarchical_memsw_limit # of bytes of memory+swap limit with regard to - hierarchy under which memory cgroup is. - -total_ # hierarchical version of , which in - addition to the cgroup's own value includes the - sum of all hierarchical children's values of - , i.e. total_cache -========================= =================================================== - -The following additional stats are dependent on CONFIG_DEBUG_VM -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -========================= ======================================== -recent_rotated_anon VM internal parameter. (see mm/vmscan.c) -recent_rotated_file VM internal parameter. (see mm/vmscan.c) -recent_scanned_anon VM internal parameter. (see mm/vmscan.c) -recent_scanned_file VM internal parameter. (see mm/vmscan.c) -========================= ======================================== - -Memo: +memory.stat file includes following statistics: + + * per-memory cgroup local status + + =============== =============================================================== + cache # of bytes of page cache memory. + rss # of bytes of anonymous and swap cache memory (includes + transparent hugepages). + rss_huge # of bytes of anonymous transparent hugepages. + mapped_file # of bytes of mapped file (includes tmpfs/shmem) + pgpgin # of charging events to the memory cgroup. The charging + event happens each time a page is accounted as either mapped + anon page(RSS) or cache page(Page Cache) to the cgroup. + pgpgout # of uncharging events to the memory cgroup. The uncharging + event happens each time a page is unaccounted from the + cgroup. + swap # of bytes of swap usage + dirty # of bytes that are waiting to get written back to the disk. + writeback # of bytes of file/anon cache that are queued for syncing to + disk. + inactive_anon # of bytes of anonymous and swap cache memory on inactive + LRU list. + active_anon # of bytes of anonymous and swap cache memory on active + LRU list. + inactive_file # of bytes of file-backed memory and MADV_FREE anonymous + memory (LazyFree pages) on inactive LRU list. + active_file # of bytes of file-backed memory on active LRU list. + unevictable # of bytes of memory that cannot be reclaimed (mlocked etc). + =============== =============================================================== + + * status considering hierarchy (see memory.use_hierarchy settings): + + ========================= =================================================== + hierarchical_memory_limit # of bytes of memory limit with regard to + hierarchy + under which the memory cgroup is + hierarchical_memsw_limit # of bytes of memory+swap limit with regard to + hierarchy under which memory cgroup is. + + total_ # hierarchical version of , which in + addition to the cgroup's own value includes the + sum of all hierarchical children's values of + , i.e. total_cache + ========================= =================================================== + + * additional vm parameters (depends on CONFIG_DEBUG_VM): + + ========================= ======================================== + recent_rotated_anon VM internal parameter. (see mm/vmscan.c) + recent_rotated_file VM internal parameter. (see mm/vmscan.c) + recent_scanned_anon VM internal parameter. (see mm/vmscan.c) + recent_scanned_file VM internal parameter. (see mm/vmscan.c) + ========================= ======================================== + +.. hint:: recent_rotated means recent frequency of LRU rotation. recent_scanned means recent # of scans to LRU. showing for better debug please see the code for meanings. -Note: +.. note:: Only anonymous and swap cache memory is listed as part of 'rss' stat. This should not be confused with the true 'resident set size' or the amount of physical memory used by the cgroup. @@ -710,13 +717,16 @@ If we want to change this to 1G, we can at any time use:: # echo 1G > memory.soft_limit_in_bytes -NOTE1: +.. note:: Soft limits take effect over a long period of time, since they involve reclaiming memory for balancing between memory cgroups -NOTE2: + +.. note:: It is recommended to set the soft limit always below the hard limit, otherwise the hard limit will take precedence. +.. _cgroup-v1-memory-move-charges: + 8. Move charges at task migration ================================= @@ -735,23 +745,29 @@ If you want to enable it:: # echo (some positive value) > memory.move_charge_at_immigrate -Note: +.. note:: Each bits of move_charge_at_immigrate has its own meaning about what type - of charges should be moved. See 8.2 for details. -Note: + of charges should be moved. See :ref:`section 8.2 + ` for details. + +.. note:: Charges are moved only when you move mm->owner, in other words, a leader of a thread group. -Note: + +.. note:: If we cannot find enough space for the task in the destination cgroup, we try to make space by reclaiming memory. Task migration may fail if we cannot make enough space. -Note: + +.. note:: It can take several seconds if you move charges much. And if you want disable it again:: # echo 0 > memory.move_charge_at_immigrate +.. _cgroup-v1-memory-movable-charges: + 8.2 Type of charges which can be moved -------------------------------------- @@ -801,6 +817,8 @@ threshold in any direction. It's applicable for root and non-root cgroup. +.. _cgroup-v1-memory-oom-control: + 10. OOM Control =============== @@ -956,15 +974,16 @@ commented and discussed quite extensively in the community. References ========== -1. Singh, Balbir. RFC: Memory Controller, http://lwn.net/Articles/206697/ -2. Singh, Balbir. Memory Controller (RSS Control), +.. [1] Singh, Balbir. RFC: Memory Controller, http://lwn.net/Articles/206697/ +.. [2] Singh, Balbir. Memory Controller (RSS Control), http://lwn.net/Articles/222762/ -3. Emelianov, Pavel. Resource controllers based on process cgroups +.. [3] Emelianov, Pavel. Resource controllers based on process cgroups https://lore.kernel.org/r/45ED7DEC.7010403@sw.ru -4. Emelianov, Pavel. RSS controller based on process cgroups (v2) +.. [4] Emelianov, Pavel. RSS controller based on process cgroups (v2) https://lore.kernel.org/r/461A3010.90403@sw.ru -5. Emelianov, Pavel. RSS controller based on process cgroups (v3) +.. [5] Emelianov, Pavel. RSS controller based on process cgroups (v3) https://lore.kernel.org/r/465D9739.8070209@openvz.org + 6. Menage, Paul. Control Groups v10, http://lwn.net/Articles/236032/ 7. Vaidyanathan, Srinivasan, Control Groups: Pagecache accounting and control subsystem (v3), http://lwn.net/Articles/235534/ @@ -974,7 +993,8 @@ References https://lore.kernel.org/r/464D267A.50107@linux.vnet.ibm.com 10. Singh, Balbir. Memory controller v6 test results, https://lore.kernel.org/r/20070819094658.654.84837.sendpatchset@balbir-laptop -11. Singh, Balbir. Memory controller introduction (v6), - https://lore.kernel.org/r/20070817084228.26003.12568.sendpatchset@balbir-laptop -12. Corbet, Jonathan, Controlling memory use in cgroups, - http://lwn.net/Articles/243795/ + +.. [11] Singh, Balbir. Memory controller introduction (v6), + https://lore.kernel.org/r/20070817084228.26003.12568.sendpatchset@balbir-laptop +.. [12] Corbet, Jonathan, Controlling memory use in cgroups, + http://lwn.net/Articles/243795/ diff --git a/Documentation/admin-guide/cgroup-v2.rst b/Documentation/admin-guide/cgroup-v2.rst index c8ae7c897f142a329e9f3ac6c496435460ef1c8b..5db4c4dd5bb465365c9778bc92ac69568058d6f6 100644 --- a/Documentation/admin-guide/cgroup-v2.rst +++ b/Documentation/admin-guide/cgroup-v2.rst @@ -619,6 +619,8 @@ process migrations. and is an example of this type. +.. _cgroupv2-limits-distributor: + Limits ------ @@ -635,6 +637,7 @@ process migrations. "io.max" limits the maximum BPS and/or IOPS that a cgroup can consume on an IO device and is an example of this type. +.. _cgroupv2-protections-distributor: Protections ----------- @@ -1245,13 +1248,17 @@ PAGE_SIZE multiple when read back. This is a simple interface to trigger memory reclaim in the target cgroup. - This file accepts a string which contains the number of bytes to - reclaim. + This file accepts a single key, the number of bytes to reclaim. + No nested keys are currently supported. Example:: echo "1G" > memory.reclaim + The interface can be later extended with nested keys to + configure the reclaim behavior. For example, specify the + type of memory to reclaim from (anon, file, ..). + Please note that the kernel can over or under reclaim from the target cgroup. If less bytes are reclaimed than the specified amount, -EAGAIN is returned. @@ -1263,13 +1270,6 @@ PAGE_SIZE multiple when read back. This means that the networking layer will not adapt based on reclaim induced by memory.reclaim. - This file also allows the user to specify the nodes to reclaim from, - via the 'nodes=' key, for example:: - - echo "1G nodes=0,1" > memory.reclaim - - The above instructs the kernel to reclaim memory from nodes 0,1. - memory.peak A read-only single value file which exists on non-root cgroups. diff --git a/Documentation/admin-guide/hw-vuln/cross-thread-rsb.rst b/Documentation/admin-guide/hw-vuln/cross-thread-rsb.rst new file mode 100644 index 0000000000000000000000000000000000000000..875616d675fe6beaaca9529e4123965d61f19ca2 --- /dev/null +++ b/Documentation/admin-guide/hw-vuln/cross-thread-rsb.rst @@ -0,0 +1,91 @@ + +.. SPDX-License-Identifier: GPL-2.0 + +Cross-Thread Return Address Predictions +======================================= + +Certain AMD and Hygon processors are subject to a cross-thread return address +predictions vulnerability. When running in SMT mode and one sibling thread +transitions out of C0 state, the other sibling thread could use return target +predictions from the sibling thread that transitioned out of C0. + +The Spectre v2 mitigations protect the Linux kernel, as it fills the return +address prediction entries with safe targets when context switching to the idle +thread. However, KVM does allow a VMM to prevent exiting guest mode when +transitioning out of C0. This could result in a guest-controlled return target +being consumed by the sibling thread. + +Affected processors +------------------- + +The following CPUs are vulnerable: + + - AMD Family 17h processors + - Hygon Family 18h processors + +Related CVEs +------------ + +The following CVE entry is related to this issue: + + ============== ======================================= + CVE-2022-27672 Cross-Thread Return Address Predictions + ============== ======================================= + +Problem +------- + +Affected SMT-capable processors support 1T and 2T modes of execution when SMT +is enabled. In 2T mode, both threads in a core are executing code. For the +processor core to enter 1T mode, it is required that one of the threads +requests to transition out of the C0 state. This can be communicated with the +HLT instruction or with an MWAIT instruction that requests non-C0. +When the thread re-enters the C0 state, the processor transitions back +to 2T mode, assuming the other thread is also still in C0 state. + +In affected processors, the return address predictor (RAP) is partitioned +depending on the SMT mode. For instance, in 2T mode each thread uses a private +16-entry RAP, but in 1T mode, the active thread uses a 32-entry RAP. Upon +transition between 1T/2T mode, the RAP contents are not modified but the RAP +pointers (which control the next return target to use for predictions) may +change. This behavior may result in return targets from one SMT thread being +used by RET predictions in the sibling thread following a 1T/2T switch. In +particular, a RET instruction executed immediately after a transition to 1T may +use a return target from the thread that just became idle. In theory, this +could lead to information disclosure if the return targets used do not come +from trustworthy code. + +Attack scenarios +---------------- + +An attack can be mounted on affected processors by performing a series of CALL +instructions with targeted return locations and then transitioning out of C0 +state. + +Mitigation mechanism +-------------------- + +Before entering idle state, the kernel context switches to the idle thread. The +context switch fills the RAP entries (referred to as the RSB in Linux) with safe +targets by performing a sequence of CALL instructions. + +Prevent a guest VM from directly putting the processor into an idle state by +intercepting HLT and MWAIT instructions. + +Both mitigations are required to fully address this issue. + +Mitigation control on the kernel command line +--------------------------------------------- + +Use existing Spectre v2 mitigations that will fill the RSB on context switch. + +Mitigation control for KVM - module parameter +--------------------------------------------- + +By default, the KVM hypervisor mitigates this issue by intercepting guest +attempts to transition out of C0. A VMM can use the KVM_CAP_X86_DISABLE_EXITS +capability to override those interceptions, but since this is not common, the +mitigation that covers this path is not enabled by default. + +The mitigation for the KVM_CAP_X86_DISABLE_EXITS capability can be turned on +using the boolean module parameter mitigate_smt_rsb, e.g. ``kvm.mitigate_smt_rsb=1``. diff --git a/Documentation/admin-guide/hw-vuln/index.rst b/Documentation/admin-guide/hw-vuln/index.rst index 4df436e7c4177996cb5a7f02b0dfc136c7d41d21..e0614760a99e7e919b8052003a61f5d9609c2a87 100644 --- a/Documentation/admin-guide/hw-vuln/index.rst +++ b/Documentation/admin-guide/hw-vuln/index.rst @@ -18,3 +18,4 @@ are configurable at compile, boot or run time. core-scheduling.rst l1d_flush.rst processor_mmio_stale_data.rst + cross-thread-rsb.rst diff --git a/Documentation/admin-guide/hw-vuln/spectre.rst b/Documentation/admin-guide/hw-vuln/spectre.rst index c4dcdb3d0d45109f79ed08287394df35e01afce7..3fe6511c54050dfc128fb5a9bc1aa01bc03aa1be 100644 --- a/Documentation/admin-guide/hw-vuln/spectre.rst +++ b/Documentation/admin-guide/hw-vuln/spectre.rst @@ -610,9 +610,9 @@ kernel command line. retpoline,generic Retpolines retpoline,lfence LFENCE; indirect branch retpoline,amd alias for retpoline,lfence - eibrs enhanced IBRS - eibrs,retpoline enhanced IBRS + Retpolines - eibrs,lfence enhanced IBRS + LFENCE + eibrs Enhanced/Auto IBRS + eibrs,retpoline Enhanced/Auto IBRS + Retpolines + eibrs,lfence Enhanced/Auto IBRS + LFENCE ibrs use IBRS to protect kernel Not specifying this option is equivalent to diff --git a/Documentation/admin-guide/index.rst b/Documentation/admin-guide/index.rst index 5bfafcbb9562c106f78e49eab3309fc0fb9b7644..0571938ecdc868c6ed559d217b3eff3cd7513e4b 100644 --- a/Documentation/admin-guide/index.rst +++ b/Documentation/admin-guide/index.rst @@ -116,6 +116,7 @@ configure specific aspects of kernel behavior to your liking. svga syscall-user-dispatch sysrq + thermal/index thunderbolt ufs unicode diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 6cfa6e3996cf75ee6bb1e8b399daa4d5701ab92b..993f3b6c10ff881840cd49a6a0b6f5d1353d65f9 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5113,6 +5113,17 @@ rcupdate.rcu_cpu_stall_timeout to be used (after conversion from seconds to milliseconds). + rcupdate.rcu_cpu_stall_cputime= [KNL] + Provide statistics on the cputime and count of + interrupts and tasks during the sampling period. For + multiple continuous RCU stalls, all sampling periods + begin at half of the first RCU stall timeout. + + rcupdate.rcu_exp_stall_task_details= [KNL] + Print stack dumps of any tasks blocking the + current expedited RCU grace period during an + expedited RCU CPU stall warning. + rcupdate.rcu_expedited= [KNL] Use expedited grace-period primitives, for example, synchronize_rcu_expedited() instead @@ -5221,7 +5232,7 @@ rdt= [HW,X86,RDT] Turn on/off individual RDT features. List is: cmt, mbmtotal, mbmlocal, l3cat, l3cdp, l2cat, l2cdp, - mba. + mba, smba, bmec. E.g. to turn on cmt and turn off mba use: rdt=cmt,!mba @@ -5729,9 +5740,9 @@ retpoline,generic - Retpolines retpoline,lfence - LFENCE; indirect branch retpoline,amd - alias for retpoline,lfence - eibrs - enhanced IBRS - eibrs,retpoline - enhanced IBRS + Retpolines - eibrs,lfence - enhanced IBRS + LFENCE + eibrs - Enhanced/Auto IBRS + eibrs,retpoline - Enhanced/Auto IBRS + Retpolines + eibrs,lfence - Enhanced/Auto IBRS + LFENCE ibrs - use IBRS to protect kernel Not specifying this option is equivalent to @@ -6369,6 +6380,16 @@ in situations with strict latency requirements (where interruptions from clocksource watchdog are not acceptable). + [x86] recalibrate: force recalibration against a HW timer + (HPET or PM timer) on systems whose TSC frequency was + obtained from HW or FW using either an MSR or CPUID(0x15). + Warn if the difference is more than 500 ppm. + [x86] watchdog: Use TSC as the watchdog clocksource with + which to check other HW timers (HPET or PM timer), but + only on systems where TSC has been deemed trustworthy. + This will be suppressed by an earlier tsc=nowatchdog and + can be overridden by a later tsc=nowatchdog. A console + message will flag any such suppression or overriding. tsc_early_khz= [X86] Skip early TSC calibration and use the given value instead. Useful when the early TSC frequency discovery @@ -7020,3 +7041,10 @@ management firmware translates the requests into actual hardware states (core frequency, data fabric and memory clocks etc.) + active + Use amd_pstate_epp driver instance as the scaling driver, + driver provides a hint to the hardware if software wants + to bias toward performance (0x0) or energy efficiency (0xff) + to the CPPC firmware. then CPPC power algorithm will + calculate the runtime workload and adjust the realtime cores + frequency. diff --git a/Documentation/admin-guide/media/davinci-vpbe.rst b/Documentation/admin-guide/media/davinci-vpbe.rst deleted file mode 100644 index 9e6360fd02db390e2de3da16359643733d689a4c..0000000000000000000000000000000000000000 --- a/Documentation/admin-guide/media/davinci-vpbe.rst +++ /dev/null @@ -1,65 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -The VPBE V4L2 driver design -=========================== - -Functional partitioning ------------------------ - -Consists of the following: - - 1. V4L2 display driver - - Implements creation of video2 and video3 device nodes and - provides v4l2 device interface to manage VID0 and VID1 layers. - - 2. Display controller - - Loads up VENC, OSD and external encoders such as ths8200. It provides - a set of API calls to V4L2 drivers to set the output/standards - in the VENC or external sub devices. It also provides - a device object to access the services from OSD subdevice - using sub device ops. The connection of external encoders to VENC LCD - controller port is done at init time based on default output and standard - selection or at run time when application change the output through - V4L2 IOCTLs. - - When connected to an external encoder, vpbe controller is also responsible - for setting up the interface between VENC and external encoders based on - board specific settings (specified in board-xxx-evm.c). This allows - interfacing external encoders such as ths8200. The setup_if_config() - is implemented for this as well as configure_venc() (part of the next patch) - API to set timings in VENC for a specific display resolution. As of this - patch series, the interconnection and enabling and setting of the external - encoders is not present, and would be a part of the next patch series. - - 3. VENC subdevice module - - Responsible for setting outputs provided through internal DACs and also - setting timings at LCD controller port when external encoders are connected - at the port or LCD panel timings required. When external encoder/LCD panel - is connected, the timings for a specific standard/preset is retrieved from - the board specific table and the values are used to set the timings in - venc using non-standard timing mode. - - Support LCD Panel displays using the VENC. For example to support a Logic - PD display, it requires setting up the LCD controller port with a set of - timings for the resolution supported and setting the dot clock. So we could - add the available outputs as a board specific entry (i.e add the "LogicPD" - output name to board-xxx-evm.c). A table of timings for various LCDs - supported can be maintained in the board specific setup file to support - various LCD displays.As of this patch a basic driver is present, and this - support for external encoders and displays forms a part of the next - patch series. - - 4. OSD module - - OSD module implements all OSD layer management and hardware specific - features. The VPBE module interacts with the OSD for enabling and - disabling appropriate features of the OSD. - -Current status --------------- - -A fully functional working version of the V4L2 driver is available. This -driver has been tested with NTSC and PAL standards and buffer streaming. diff --git a/Documentation/admin-guide/media/platform-cardlist.rst b/Documentation/admin-guide/media/platform-cardlist.rst index ac73c4166d1e572356381fac0cc91f5b3fed42a6..8ef57cd13dec239c1ec9a1b1e3618ca4e78d3fa4 100644 --- a/Documentation/admin-guide/media/platform-cardlist.rst +++ b/Documentation/admin-guide/media/platform-cardlist.rst @@ -73,7 +73,6 @@ via-camera VIAFB camera controller video-mux Video Multiplexer vpif_display TI DaVinci VPIF V4L2-Display vpif_capture TI DaVinci VPIF video capture -vpss TI DaVinci VPBE V4L2-Display vsp1 Renesas VSP1 Video Processing Engine xilinx-tpg Xilinx Video Test Pattern Generator xilinx-video Xilinx Video IP (EXPERIMENTAL) diff --git a/Documentation/admin-guide/media/v4l-drivers.rst b/Documentation/admin-guide/media/v4l-drivers.rst index 90a026ee05c6e4021ecce9ca04bb25a2b920e976..734e18c310bdef39738e45d8bf8e9cc90ed71b15 100644 --- a/Documentation/admin-guide/media/v4l-drivers.rst +++ b/Documentation/admin-guide/media/v4l-drivers.rst @@ -13,7 +13,6 @@ Video4Linux (V4L) driver-specific documentation cafe_ccic cpia2 cx88 - davinci-vpbe fimc imx imx7 diff --git a/Documentation/admin-guide/mm/zswap.rst b/Documentation/admin-guide/mm/zswap.rst index f67de481c7f60559c169ac0ba7e8dcaff24b5da9..6dd74a18268baa6c74acfd55499ad769e04c12b2 100644 --- a/Documentation/admin-guide/mm/zswap.rst +++ b/Documentation/admin-guide/mm/zswap.rst @@ -70,9 +70,7 @@ e.g. ``zswap.zpool=zbud``. It can also be changed at runtime using the sysfs The zbud type zpool allocates exactly 1 page to store 2 compressed pages, which means the compression ratio will always be 2:1 or worse (because of half-full zbud pages). The zsmalloc type zpool has a more complex compressed page -storage method, and it can achieve greater storage densities. However, -zsmalloc does not implement compressed page eviction, so once zswap fills it -cannot evict the oldest page, it can only reject new pages. +storage method, and it can achieve greater storage densities. When a swap page is passed from frontswap to zswap, zswap maintains a mapping of the swap entry, a combination of the swap type and swap offset, to the zpool diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 5376d53faaa8e734f1e75c0a147a1b6122b65c02..d143e72cf93ed102e68331cec8666d9e10938581 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -230,8 +230,8 @@ with :c:macro:`MSR_AMD_CPPC_ENABLE` or ``cppc_set_enable``, it will respond to the request from AMD P-States. -User Space Interface in ``sysfs`` -================================== +User Space Interface in ``sysfs`` - Per-policy control +====================================================== ``amd-pstate`` exposes several global attributes (files) in ``sysfs`` to control its functionality at the system level. They are located in the @@ -262,6 +262,25 @@ lowest non-linear performance in `AMD CPPC Performance Capability `_.) This attribute is read-only. +``energy_performance_available_preferences`` + +A list of all the supported EPP preferences that could be used for +``energy_performance_preference`` on this system. +These profiles represent different hints that are provided +to the low-level firmware about the user's desired energy vs efficiency +tradeoff. ``default`` represents the epp value is set by platform +firmware. This attribute is read-only. + +``energy_performance_preference`` + +The current energy performance preference can be read from this attribute. +and user can change current preference according to energy or performance needs +Please get all support profiles list from +``energy_performance_available_preferences`` attribute, all the profiles are +integer values defined between 0 to 255 when EPP feature is enabled by platform +firmware, if EPP feature is disabled, driver will ignore the written value +This attribute is read-write. + Other performance and frequency values can be read back from ``/sys/devices/system/cpu/cpuX/acpi_cppc/``, see :ref:`cppc_sysfs`. @@ -280,8 +299,30 @@ module which supports the new AMD P-States mechanism on most of the future AMD platforms. The AMD P-States mechanism is the more performance and energy efficiency frequency management method on AMD processors. -Kernel Module Options for ``amd-pstate`` -========================================= + +AMD Pstate Driver Operation Modes +================================= + +``amd_pstate`` CPPC has two operation modes: CPPC Autonomous(active) mode and +CPPC non-autonomous(passive) mode. +active mode and passive mode can be chosen by different kernel parameters. +When in Autonomous mode, CPPC ignores requests done in the Desired Performance +Target register and takes into account only the values set to the Minimum requested +performance, Maximum requested performance, and Energy Performance Preference +registers. When Autonomous is disabled, it only considers the Desired Performance Target. + +Active Mode +------------ + +``amd_pstate=active`` + +This is the low-level firmware control mode which is implemented by ``amd_pstate_epp`` +driver with ``amd_pstate=active`` passed to the kernel in the command line. +In this mode, ``amd_pstate_epp`` driver provides a hint to the hardware if software +wants to bias toward performance (0x0) or energy efficiency (0xff) to the CPPC firmware. +then CPPC power algorithm will calculate the runtime workload and adjust the realtime +cores frequency according to the power supply and thermal, core voltage and some other +hardware conditions. Passive Mode ------------ @@ -298,6 +339,35 @@ processor must provide at least nominal performance requested and go higher if c operating conditions allow. +User Space Interface in ``sysfs`` - General +=========================================== + +Global Attributes +----------------- + +``amd-pstate`` exposes several global attributes (files) in ``sysfs`` to +control its functionality at the system level. They are located in the +``/sys/devices/system/cpu/amd-pstate/`` directory and affect all CPUs. + +``status`` + Operation mode of the driver: "active", "passive" or "disable". + + "active" + The driver is functional and in the ``active mode`` + + "passive" + The driver is functional and in the ``passive mode`` + + "disable" + The driver is unregistered and not functional now. + + This attribute can be written to in order to change the driver's + operation mode or to unregister it. The string written to it must be + one of the possible values of it and, if successful, writing one of + these values to the sysfs file will cause the driver to switch over + to the operation mode represented by that string - or to be + unregistered in the "disable" case. + ``cpupower`` tool support for ``amd-pstate`` =============================================== diff --git a/Documentation/admin-guide/thermal/index.rst b/Documentation/admin-guide/thermal/index.rst new file mode 100644 index 0000000000000000000000000000000000000000..193b7b01a87d7e32587322f0f57e96aab2beb6fe --- /dev/null +++ b/Documentation/admin-guide/thermal/index.rst @@ -0,0 +1,8 @@ +================= +Thermal Subsystem +================= + +.. toctree:: + :maxdepth: 1 + + intel_powerclamp diff --git a/Documentation/driver-api/thermal/intel_powerclamp.rst b/Documentation/admin-guide/thermal/intel_powerclamp.rst similarity index 91% rename from Documentation/driver-api/thermal/intel_powerclamp.rst rename to Documentation/admin-guide/thermal/intel_powerclamp.rst index 3f6dfb0b3ea6796ed00f881e7f593c5749b1889e..3ce96043af17975733ea49c8bddcf5ca6438cee1 100644 --- a/Documentation/driver-api/thermal/intel_powerclamp.rst +++ b/Documentation/admin-guide/thermal/intel_powerclamp.rst @@ -26,6 +26,8 @@ By: - Generic Thermal Layer (sysfs) - Kernel APIs (TBD) + (*) Module Parameters + INTRODUCTION ============ @@ -153,13 +155,15 @@ b) determine the amount of compensation needed at each target ratio Compensation to each target ratio consists of two parts: a) steady state error compensation - This is to offset the error occurring when the system can - enter idle without extra wakeups (such as external interrupts). + + This is to offset the error occurring when the system can + enter idle without extra wakeups (such as external interrupts). b) dynamic error compensation - When an excessive amount of wakeups occurs during idle, an - additional idle ratio can be added to quiet interrupts, by - slowing down CPU activities. + + When an excessive amount of wakeups occurs during idle, an + additional idle ratio can be added to quiet interrupts, by + slowing down CPU activities. A debugfs file is provided for the user to examine compensation progress and results, such as on a Westmere system:: @@ -281,6 +285,7 @@ cur_state returns value -1 instead of 0 which is to avoid confusing 100% busy state with the disabled state. Example usage: + - To inject 25% idle time:: $ sudo sh -c "echo 25 > /sys/class/thermal/cooling_device80/cur_state @@ -318,3 +323,23 @@ device, a PID based userspace thermal controller can manage to control CPU temperature effectively, when no other thermal influence is added. For example, a UltraBook user can compile the kernel under certain temperature (below most active trip points). + +Module Parameters +================= + +``cpumask`` (RW) + A bit mask of CPUs to inject idle. The format of the bitmask is same as + used in other subsystems like in /proc/irq/\*/smp_affinity. The mask is + comma separated 32 bit groups. Each CPU is one bit. For example for a 256 + CPU system the full mask is: + ffffffff,ffffffff,ffffffff,ffffffff,ffffffff,ffffffff,ffffffff,ffffffff + + The rightmost mask is for CPU 0-32. + +``max_idle`` (RW) + Maximum injected idle time to the total CPU time ratio in percent range + from 1 to 100. Even if the cooling device max_state is always 100 (100%), + this parameter allows to add a max idle percent limit. The default is 50, + to match the current implementation of powerclamp driver. Also doesn't + allow value more than 75, if the cpumask includes every CPU present in + the system. diff --git a/Documentation/arm/index.rst b/Documentation/arm/index.rst index 8c636d4a061f571b520e0bcef1a471ecfacada60..ae42fe886f0dc622787f84dde8b3d2582ecd5c63 100644 --- a/Documentation/arm/index.rst +++ b/Documentation/arm/index.rst @@ -64,7 +64,6 @@ SoC-specific documents sunxi samsung/index - samsung-s3c24xx/index sunxi/clocks diff --git a/Documentation/arm/samsung-s3c24xx/cpufreq.rst b/Documentation/arm/samsung-s3c24xx/cpufreq.rst deleted file mode 100644 index cd22697cf60660086a1df0b99133035064ef7941..0000000000000000000000000000000000000000 --- a/Documentation/arm/samsung-s3c24xx/cpufreq.rst +++ /dev/null @@ -1,77 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0-only - -======================= -S3C24XX CPUfreq support -======================= - -Introduction ------------- - - The S3C24XX series support a number of power saving systems, such as - the ability to change the core, memory and peripheral operating - frequencies. The core control is exported via the CPUFreq driver - which has a number of different manual or automatic controls over the - rate the core is running at. - - There are two forms of the driver depending on the specific CPU and - how the clocks are arranged. The first implementation used as single - PLL to feed the ARM, memory and peripherals via a series of dividers - and muxes and this is the implementation that is documented here. A - newer version where there is a separate PLL and clock divider for the - ARM core is available as a separate driver. - - -Layout ------- - - The code core manages the CPU specific drivers, any data that they - need to register and the interface to the generic drivers/cpufreq - system. Each CPU registers a driver to control the PLL, clock dividers - and anything else associated with it. Any board that wants to use this - framework needs to supply at least basic details of what is required. - - The core registers with drivers/cpufreq at init time if all the data - necessary has been supplied. - - -CPU support ------------ - - The support for each CPU depends on the facilities provided by the - SoC and the driver as each device has different PLL and clock chains - associated with it. - - -Slow Mode ---------- - - The SLOW mode where the PLL is turned off altogether and the - system is fed by the external crystal input is currently not - supported. - - -sysfs ------ - - The core code exports extra information via sysfs in the directory - devices/system/cpu/cpu0/arch-freq. - - -Board Support -------------- - - Each board that wants to use the cpufreq code must register some basic - information with the core driver to provide information about what the - board requires and any restrictions being placed on it. - - The board needs to supply information about whether it needs the IO bank - timings changing, any maximum frequency limits and information about the - SDRAM refresh rate. - - - - -Document Author ---------------- - -Ben Dooks, Copyright 2009 Simtec Electronics diff --git a/Documentation/arm/samsung-s3c24xx/eb2410itx.rst b/Documentation/arm/samsung-s3c24xx/eb2410itx.rst deleted file mode 100644 index 7863c93652f8392fadfcb6fca9f0ef41752ea086..0000000000000000000000000000000000000000 --- a/Documentation/arm/samsung-s3c24xx/eb2410itx.rst +++ /dev/null @@ -1,59 +0,0 @@ -=================================== -Simtec Electronics EB2410ITX (BAST) -=================================== - - http://www.simtec.co.uk/products/EB2410ITX/ - -Introduction ------------- - - The EB2410ITX is a S3C2410 based development board with a variety of - peripherals and expansion connectors. This board is also known by - the shortened name of Bast. - - -Configuration -------------- - - To set the default configuration, use `make bast_defconfig` which - supports the commonly used features of this board. - - -Support -------- - - Official support information can be found on the Simtec Electronics - website, at the product page http://www.simtec.co.uk/products/EB2410ITX/ - - Useful links: - - - Resources Page http://www.simtec.co.uk/products/EB2410ITX/resources.html - - - Board FAQ at http://www.simtec.co.uk/products/EB2410ITX/faq.html - - - Bootloader info http://www.simtec.co.uk/products/SWABLE/resources.html - and FAQ http://www.simtec.co.uk/products/SWABLE/faq.html - - -MTD ---- - - The NAND and NOR support has been merged from the linux-mtd project. - Any problems, see http://www.linux-mtd.infradead.org/ for more - information or up-to-date versions of linux-mtd. - - -IDE ---- - - Both onboard IDE ports are supported, however there is no support for - changing speed of devices, PIO Mode 4 capable drives should be used. - - -Maintainers ------------ - - This board is maintained by Simtec Electronics. - - -Copyright 2004 Ben Dooks, Simtec Electronics diff --git a/Documentation/arm/samsung-s3c24xx/gpio.rst b/Documentation/arm/samsung-s3c24xx/gpio.rst deleted file mode 100644 index f4a8c800a457012ddb97310ce26da32be293459a..0000000000000000000000000000000000000000 --- a/Documentation/arm/samsung-s3c24xx/gpio.rst +++ /dev/null @@ -1,172 +0,0 @@ -==================== -S3C24XX GPIO Control -==================== - -Introduction ------------- - - The s3c2410 kernel provides an interface to configure and - manipulate the state of the GPIO pins, and find out other - information about them. - - There are a number of conditions attached to the configuration - of the s3c2410 GPIO system, please read the Samsung provided - data-sheet/users manual to find out the complete list. - - See Documentation/arm/samsung/gpio.rst for the core implementation. - - -GPIOLIB -------- - - With the event of the GPIOLIB in drivers/gpio, support for some - of the GPIO functions such as reading and writing a pin will - be removed in favour of this common access method. - - Once all the extant drivers have been converted, the functions - listed below will be removed (they may be marked as __deprecated - in the near future). - - The following functions now either have a `s3c_` specific variant - or are merged into gpiolib. See the definitions in - arch/arm/mach-s3c/gpio-cfg.h: - - - s3c2410_gpio_setpin() gpio_set_value() or gpio_direction_output() - - s3c2410_gpio_getpin() gpio_get_value() or gpio_direction_input() - - s3c2410_gpio_getirq() gpio_to_irq() - - s3c2410_gpio_cfgpin() s3c_gpio_cfgpin() - - s3c2410_gpio_getcfg() s3c_gpio_getcfg() - - s3c2410_gpio_pullup() s3c_gpio_setpull() - - -GPIOLIB conversion ------------------- - -If you need to convert your board or driver to use gpiolib from the phased -out s3c2410 API, then here are some notes on the process. - -1) If your board is exclusively using an GPIO, say to control peripheral - power, then it will require to claim the gpio with gpio_request() before - it can use it. - - It is recommended to check the return value, with at least WARN_ON() - during initialisation. - -2) The s3c2410_gpio_cfgpin() can be directly replaced with s3c_gpio_cfgpin() - as they have the same arguments, and can either take the pin specific - values, or the more generic special-function-number arguments. - -3) s3c2410_gpio_pullup() changes have the problem that while the - s3c2410_gpio_pullup(x, 1) can be easily translated to the - s3c_gpio_setpull(x, S3C_GPIO_PULL_NONE), the s3c2410_gpio_pullup(x, 0) - are not so easy. - - The s3c2410_gpio_pullup(x, 0) case enables the pull-up (or in the case - of some of the devices, a pull-down) and as such the new API distinguishes - between the UP and DOWN case. There is currently no 'just turn on' setting - which may be required if this becomes a problem. - -4) s3c2410_gpio_setpin() can be replaced by gpio_set_value(), the old call - does not implicitly configure the relevant gpio to output. The gpio - direction should be changed before using gpio_set_value(). - -5) s3c2410_gpio_getpin() is replaceable by gpio_get_value() if the pin - has been set to input. It is currently unknown what the behaviour is - when using gpio_get_value() on an output pin (s3c2410_gpio_getpin - would return the value the pin is supposed to be outputting). - -6) s3c2410_gpio_getirq() should be directly replaceable with the - gpio_to_irq() call. - -The s3c2410_gpio and `gpio_` calls have always operated on the same gpio -numberspace, so there is no problem with converting the gpio numbering -between the calls. - - -Headers -------- - - See arch/arm/mach-s3c/regs-gpio-s3c24xx.h for the list - of GPIO pins, and the configuration values for them. This - is included by using #include - - -PIN Numbers ------------ - - Each pin has an unique number associated with it in regs-gpio.h, - e.g. S3C2410_GPA(0) or S3C2410_GPF(1). These defines are used to tell - the GPIO functions which pin is to be used. - - With the conversion to gpiolib, there is no longer a direct conversion - from gpio pin number to register base address as in earlier kernels. This - is due to the number space required for newer SoCs where the later - GPIOs are not contiguous. - - -Configuring a pin ------------------ - - The following function allows the configuration of a given pin to - be changed. - - void s3c_gpio_cfgpin(unsigned int pin, unsigned int function); - - e.g.: - - s3c_gpio_cfgpin(S3C2410_GPA(0), S3C_GPIO_SFN(1)); - s3c_gpio_cfgpin(S3C2410_GPE(8), S3C_GPIO_SFN(2)); - - which would turn GPA(0) into the lowest Address line A0, and set - GPE(8) to be connected to the SDIO/MMC controller's SDDAT1 line. - - -Reading the current configuration ---------------------------------- - - The current configuration of a pin can be read by using standard - gpiolib function: - - s3c_gpio_getcfg(unsigned int pin); - - The return value will be from the same set of values which can be - passed to s3c_gpio_cfgpin(). - - -Configuring a pull-up resistor ------------------------------- - - A large proportion of the GPIO pins on the S3C2410 can have weak - pull-up resistors enabled. This can be configured by the following - function: - - void s3c_gpio_setpull(unsigned int pin, unsigned int to); - - Where the to value is S3C_GPIO_PULL_NONE to set the pull-up off, - and S3C_GPIO_PULL_UP to enable the specified pull-up. Any other - values are currently undefined. - - -Getting and setting the state of a PIN --------------------------------------- - - These calls are now implemented by the relevant gpiolib calls, convert - your board or driver to use gpiolib. - - -Getting the IRQ number associated with a PIN --------------------------------------------- - - A standard gpiolib function can map the given pin number to an IRQ - number to pass to the IRQ system. - - int gpio_to_irq(unsigned int pin); - - Note, not all pins have an IRQ. - - -Author -------- - -Ben Dooks, 03 October 2004 -Copyright 2004 Ben Dooks, Simtec Electronics diff --git a/Documentation/arm/samsung-s3c24xx/h1940.rst b/Documentation/arm/samsung-s3c24xx/h1940.rst deleted file mode 100644 index 62a562c178e33ed9d1bd7537929ffb1239abc974..0000000000000000000000000000000000000000 --- a/Documentation/arm/samsung-s3c24xx/h1940.rst +++ /dev/null @@ -1,41 +0,0 @@ -============= -HP IPAQ H1940 -============= - -http://www.handhelds.org/projects/h1940.html - -Introduction ------------- - - The HP H1940 is a S3C2410 based handheld device, with - bluetooth connectivity. - - -Support -------- - - A variety of information is available - - handhelds.org project page: - - http://www.handhelds.org/projects/h1940.html - - handhelds.org wiki page: - - http://handhelds.org/moin/moin.cgi/HpIpaqH1940 - - Herbert Pötzl pages: - - http://vserver.13thfloor.at/H1940/ - - -Maintainers ------------ - - This project is being maintained and developed by a variety - of people, including Ben Dooks, Arnaud Patard, and Herbert Pötzl. - - Thanks to the many others who have also provided support. - - -(c) 2005 Ben Dooks diff --git a/Documentation/arm/samsung-s3c24xx/index.rst b/Documentation/arm/samsung-s3c24xx/index.rst deleted file mode 100644 index ccb951a0bedbce451405eca212539d2e90880cb7..0000000000000000000000000000000000000000 --- a/Documentation/arm/samsung-s3c24xx/index.rst +++ /dev/null @@ -1,20 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -========================== -Samsung S3C24XX SoC Family -========================== - -.. toctree:: - :maxdepth: 1 - - h1940 - gpio - cpufreq - suspend - usb-host - s3c2412 - eb2410itx - nand - smdk2440 - s3c2413 - overview diff --git a/Documentation/arm/samsung-s3c24xx/nand.rst b/Documentation/arm/samsung-s3c24xx/nand.rst deleted file mode 100644 index 938995694ee765a5df5dfd00c9246c413607a3a2..0000000000000000000000000000000000000000 --- a/Documentation/arm/samsung-s3c24xx/nand.rst +++ /dev/null @@ -1,30 +0,0 @@ -==================== -S3C24XX NAND Support -==================== - -Introduction ------------- - -Small Page NAND ---------------- - -The driver uses a 512 byte (1 page) ECC code for this setup. The -ECC code is not directly compatible with the default kernel ECC -code, so the driver enforces its own OOB layout and ECC parameters - -Large Page NAND ---------------- - -The driver is capable of handling NAND flash with a 2KiB page -size, with support for hardware ECC generation and correction. - -Unlike the 512byte page mode, the driver generates ECC data for -each 256 byte block in an 2KiB page. This means that more than -one error in a page can be rectified. It also means that the -OOB layout remains the default kernel layout for these flashes. - - -Document Author ---------------- - -Ben Dooks, Copyright 2007 Simtec Electronics diff --git a/Documentation/arm/samsung-s3c24xx/overview.rst b/Documentation/arm/samsung-s3c24xx/overview.rst deleted file mode 100644 index 14535e5cffb7879eb304dd840ced03e45c55a905..0000000000000000000000000000000000000000 --- a/Documentation/arm/samsung-s3c24xx/overview.rst +++ /dev/null @@ -1,311 +0,0 @@ -========================== -S3C24XX ARM Linux Overview -========================== - - - -Introduction ------------- - - The Samsung S3C24XX range of ARM9 System-on-Chip CPUs are supported - by the 's3c2410' architecture of ARM Linux. Currently the S3C2410, - S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443 and S3C2450 devices - are supported. - - Support for the S3C2400 and S3C24A0 series was never completed and the - corresponding code has been removed after a while. If someone wishes to - revive this effort, partial support can be retrieved from earlier Linux - versions. - - The S3C2416 and S3C2450 devices are very similar and S3C2450 support is - included under the arch/arm/mach-s3c directory. Note, while core - support for these SoCs is in, work on some of the extra peripherals - and extra interrupts is still ongoing. - - -Configuration -------------- - - A generic S3C2410 configuration is provided, and can be used as the - default by `make s3c2410_defconfig`. This configuration has support - for all the machines, and the commonly used features on them. - - Certain machines may have their own default configurations as well, - please check the machine specific documentation. - - -Layout ------- - - The core support files, register, kernel and paltform data are located in the - platform code contained in arch/arm/mach-s3c with headers in - arch/arm/mach-s3c/include - -arch/arm/mach-s3c: - - Files in here are either common to all the s3c24xx family, - or are common to only some of them with names to indicate this - status. The files that are not common to all are generally named - with the initial cpu they support in the series to ensure a short - name without any possibility of confusion with newer devices. - - As an example, initially s3c244x would cover s3c2440 and s3c2442, but - with the s3c2443 which does not share many of the same drivers in - this directory, the name becomes invalid. We stick to s3c2440- - to indicate a driver that is s3c2440 and s3c2442 compatible. - - This does mean that to find the status of any given SoC, a number - of directories may need to be searched. - - -Machines --------- - - The currently supported machines are as follows: - - Simtec Electronics EB2410ITX (BAST) - - A general purpose development board, see EB2410ITX.txt for further - details - - Simtec Electronics IM2440D20 (Osiris) - - CPU Module from Simtec Electronics, with a S3C2440A CPU, nand flash - and a PCMCIA controller. - - Samsung SMDK2410 - - Samsung's own development board, geared for PDA work. - - Samsung/Aiji SMDK2412 - - The S3C2412 version of the SMDK2440. - - Samsung/Aiji SMDK2413 - - The S3C2412 version of the SMDK2440. - - Samsung/Meritech SMDK2440 - - The S3C2440 compatible version of the SMDK2440, which has the - option of an S3C2440 or S3C2442 CPU module. - - Thorcom VR1000 - - Custom embedded board - - HP IPAQ 1940 - - Handheld (IPAQ), available in several varieties - - HP iPAQ rx3715 - - S3C2440 based IPAQ, with a number of variations depending on - features shipped. - - Acer N30 - - A S3C2410 based PDA from Acer. There is a Wiki page at - http://handhelds.org/moin/moin.cgi/AcerN30Documentation . - - AML M5900 - - American Microsystems' M5900 - - Nex Vision Nexcoder - Nex Vision Otom - - Two machines by Nex Vision - - -Adding New Machines -------------------- - - The architecture has been designed to support as many machines as can - be configured for it in one kernel build, and any future additions - should keep this in mind before altering items outside of their own - machine files. - - Machine definitions should be kept in arch/arm/mach-s3c, - and there are a number of examples that can be looked at. - - Read the kernel patch submission policies as well as the - Documentation/arm directory before submitting patches. The - ARM kernel series is managed by Russell King, and has a patch system - located at http://www.arm.linux.org.uk/developer/patches/ - as well as mailing lists that can be found from the same site. - - As a courtesy, please notify of any new - machines or other modifications. - - Any large scale modifications, or new drivers should be discussed - on the ARM kernel mailing list (linux-arm-kernel) before being - attempted. See http://www.arm.linux.org.uk/mailinglists/ for the - mailing list information. - - -I2C ---- - - The hardware I2C core in the CPU is supported in single master - mode, and can be configured via platform data. - - -RTC ---- - - Support for the onboard RTC unit, including alarm function. - - This has recently been upgraded to use the new RTC core, - and the module has been renamed to rtc-s3c to fit in with - the new rtc naming scheme. - - -Watchdog --------- - - The onchip watchdog is available via the standard watchdog - interface. - - -NAND ----- - - The current kernels now have support for the s3c2410 NAND - controller. If there are any problems the latest linux-mtd - code can be found from http://www.linux-mtd.infradead.org/ - - For more information see Documentation/arm/samsung-s3c24xx/nand.rst - - -SD/MMC ------- - - The SD/MMC hardware pre S3C2443 is supported in the current - kernel, the driver is drivers/mmc/host/s3cmci.c and supports - 1 and 4 bit SD or MMC cards. - - The SDIO behaviour of this driver has not been fully tested. There is no - current support for hardware SDIO interrupts. - - -Serial ------- - - The s3c2410 serial driver provides support for the internal - serial ports. These devices appear as /dev/ttySAC0 through 3. - - To create device nodes for these, use the following commands - - mknod ttySAC0 c 204 64 - mknod ttySAC1 c 204 65 - mknod ttySAC2 c 204 66 - - -GPIO ----- - - The core contains support for manipulating the GPIO, see the - documentation in GPIO.txt in the same directory as this file. - - Newer kernels carry GPIOLIB, and support is being moved towards - this with some of the older support in line to be removed. - - As of v2.6.34, the move towards using gpiolib support is almost - complete, and very little of the old calls are left. - - See Documentation/arm/samsung-s3c24xx/gpio.rst for the S3C24XX specific - support and Documentation/arm/samsung/gpio.rst for the core Samsung - implementation. - - -Clock Management ----------------- - - The core provides the interface defined in the header file - include/asm-arm/hardware/clock.h, to allow control over the - various clock units - - -Suspend to RAM --------------- - - For boards that provide support for suspend to RAM, the - system can be placed into low power suspend. - - See Suspend.txt for more information. - - -SPI ---- - - SPI drivers are available for both the in-built hardware - (although there is no DMA support yet) and a generic - GPIO based solution. - - -LEDs ----- - - There is support for GPIO based LEDs via a platform driver - in the LED subsystem. - - -Platform Data -------------- - - Whenever a device has platform specific data that is specified - on a per-machine basis, care should be taken to ensure the - following: - - 1) that default data is not left in the device to confuse the - driver if a machine does not set it at startup - - 2) the data should (if possible) be marked as __initdata, - to ensure that the data is thrown away if the machine is - not the one currently in use. - - The best way of doing this is to make a function that - kmalloc()s an area of memory, and copies the __initdata - and then sets the relevant device's platform data. Making - the function `__init` takes care of ensuring it is discarded - with the rest of the initialisation code:: - - static __init void s3c24xx_xxx_set_platdata(struct xxx_data *pd) - { - struct s3c2410_xxx_mach_info *npd; - - npd = kmalloc(sizeof(struct s3c2410_xxx_mach_info), GFP_KERNEL); - if (npd) { - memcpy(npd, pd, sizeof(struct s3c2410_xxx_mach_info)); - s3c_device_xxx.dev.platform_data = npd; - } else { - printk(KERN_ERR "no memory for xxx platform data\n"); - } - } - - Note, since the code is marked as __init, it should not be - exported outside arch/arm/mach-s3c/, or exported to - modules via EXPORT_SYMBOL() and related functions. - - -Port Contributors ------------------ - - Ben Dooks (BJD) - Vincent Sanders - Herbert Potzl - Arnaud Patard (RTP) - Roc Wu - Klaus Fetscher - Dimitry Andric - Shannon Holland - Guillaume Gourat (NexVision) - Christer Weinigel (wingel) (Acer N30) - Lucas Correia Villa Real (S3C2400 port) - - -Document Author ---------------- - -Ben Dooks, Copyright 2004-2006 Simtec Electronics diff --git a/Documentation/arm/samsung-s3c24xx/s3c2412.rst b/Documentation/arm/samsung-s3c24xx/s3c2412.rst deleted file mode 100644 index 68b985fc6bf4c4bdcc9fb90fa9b1f7361c567193..0000000000000000000000000000000000000000 --- a/Documentation/arm/samsung-s3c24xx/s3c2412.rst +++ /dev/null @@ -1,121 +0,0 @@ -========================== -S3C2412 ARM Linux Overview -========================== - -Introduction ------------- - - The S3C2412 is part of the S3C24XX range of ARM9 System-on-Chip CPUs - from Samsung. This part has an ARM926-EJS core, capable of running up - to 266MHz (see data-sheet for more information) - - -Clock ------ - - The core clock code provides a set of clocks to the drivers, and allows - for source selection and a number of other features. - - -Power ------ - - No support for suspend/resume to RAM in the current system. - - -DMA ---- - - No current support for DMA. - - -GPIO ----- - - There is support for setting the GPIO to input/output/special function - and reading or writing to them. - - -UART ----- - - The UART hardware is similar to the S3C2440, and is supported by the - s3c2410 driver in the drivers/serial directory. - - -NAND ----- - - The NAND hardware is similar to the S3C2440, and is supported by the - s3c2410 driver in the drivers/mtd/nand/raw directory. - - -USB Host --------- - - The USB hardware is similar to the S3C2410, with extended clock source - control. The OHCI portion is supported by the ohci-s3c2410 driver, and - the clock control selection is supported by the core clock code. - - -USB Device ----------- - - No current support in the kernel - - -IRQs ----- - - All the standard, and external interrupt sources are supported. The - extra sub-sources are not yet supported. - - -RTC ---- - - The RTC hardware is similar to the S3C2410, and is supported by the - s3c2410-rtc driver. - - -Watchdog --------- - - The watchdog hardware is the same as the S3C2410, and is supported by - the s3c2410_wdt driver. - - -MMC/SD/SDIO ------------ - - No current support for the MMC/SD/SDIO block. - -IIC ---- - - The IIC hardware is the same as the S3C2410, and is supported by the - i2c-s3c24xx driver. - - -IIS ---- - - No current support for the IIS interface. - - -SPI ---- - - No current support for the SPI interfaces. - - -ATA ---- - - No current support for the on-board ATA block. - - -Document Author ---------------- - -Ben Dooks, Copyright 2006 Simtec Electronics diff --git a/Documentation/arm/samsung-s3c24xx/s3c2413.rst b/Documentation/arm/samsung-s3c24xx/s3c2413.rst deleted file mode 100644 index 1f51e207fc46f03a796d83c8fd6086c4a7fb773a..0000000000000000000000000000000000000000 --- a/Documentation/arm/samsung-s3c24xx/s3c2413.rst +++ /dev/null @@ -1,22 +0,0 @@ -========================== -S3C2413 ARM Linux Overview -========================== - -Introduction ------------- - - The S3C2413 is an extended version of the S3C2412, with an camera - interface and mobile DDR memory support. See the S3C2412 support - documentation for more information. - - -Camera Interface ----------------- - - This block is currently not supported. - - -Document Author ---------------- - -Ben Dooks, Copyright 2006 Simtec Electronics diff --git a/Documentation/arm/samsung-s3c24xx/smdk2440.rst b/Documentation/arm/samsung-s3c24xx/smdk2440.rst deleted file mode 100644 index 524fd0b4afaf9135af2ce42119b55ca3b4147cc6..0000000000000000000000000000000000000000 --- a/Documentation/arm/samsung-s3c24xx/smdk2440.rst +++ /dev/null @@ -1,57 +0,0 @@ -========================= -Samsung/Meritech SMDK2440 -========================= - -Introduction ------------- - - The SMDK2440 is a two part evaluation board for the Samsung S3C2440 - processor. It includes support for LCD, SmartMedia, Audio, SD and - 10MBit Ethernet, and expansion headers for various signals, including - the camera and unused GPIO. - - -Configuration -------------- - - To set the default configuration, use `make smdk2440_defconfig` which - will configure the common features of this board, or use - `make s3c2410_config` to include support for all s3c2410/s3c2440 machines - - -Support -------- - - Ben Dooks' SMDK2440 site at http://www.fluff.org/ben/smdk2440/ which - includes linux based USB download tools. - - Some of the h1940 patches that can be found from the H1940 project - site at http://www.handhelds.org/projects/h1940.html can also be - applied to this board. - - -Peripherals ------------ - - There is no current support for any of the extra peripherals on the - base-board itself. - - -MTD ---- - - The NAND flash should be supported by the in kernel MTD NAND support, - NOR flash will be added later. - - -Maintainers ------------ - - This board is being maintained by Ben Dooks, for more info, see - http://www.fluff.org/ben/smdk2440/ - - Many thanks to Dimitry Andric of TomTom for the loan of the SMDK2440, - and to Simtec Electronics for allowing me time to work on this. - - -(c) 2004 Ben Dooks diff --git a/Documentation/arm/samsung-s3c24xx/suspend.rst b/Documentation/arm/samsung-s3c24xx/suspend.rst deleted file mode 100644 index b4f3ae9fe76eef39ba4484d7ddfdc8f457057d69..0000000000000000000000000000000000000000 --- a/Documentation/arm/samsung-s3c24xx/suspend.rst +++ /dev/null @@ -1,137 +0,0 @@ -======================= -S3C24XX Suspend Support -======================= - - -Introduction ------------- - - The S3C24XX supports a low-power suspend mode, where the SDRAM is kept - in Self-Refresh mode, and all but the essential peripheral blocks are - powered down. For more information on how this works, please look - at the relevant CPU datasheet from Samsung. - - -Requirements ------------- - - 1) A bootloader that can support the necessary resume operation - - 2) Support for at least 1 source for resume - - 3) CONFIG_PM enabled in the kernel - - 4) Any peripherals that are going to be powered down at the same - time require suspend/resume support. - - -Resuming --------- - - The S3C2410 user manual defines the process of sending the CPU to - sleep and how it resumes. The default behaviour of the Linux code - is to set the GSTATUS3 register to the physical address of the - code to resume Linux operation. - - GSTATUS4 is currently left alone by the sleep code, and is free to - use for any other purposes (for example, the EB2410ITX uses this to - save memory configuration in). - - -Machine Support ---------------- - - The machine specific functions must call the s3c_pm_init() function - to say that its bootloader is capable of resuming. This can be as - simple as adding the following to the machine's definition: - - INITMACHINE(s3c_pm_init) - - A board can do its own setup before calling s3c_pm_init, if it - needs to setup anything else for power management support. - - There is currently no support for over-riding the default method of - saving the resume address, if your board requires it, then contact - the maintainer and discuss what is required. - - Note, the original method of adding an late_initcall() is wrong, - and will end up initialising all compiled machines' pm init! - - The following is an example of code used for testing wakeup from - an falling edge on IRQ_EINT0:: - - - static irqreturn_t button_irq(int irq, void *pw) - { - return IRQ_HANDLED; - } - - statuc void __init machine_init(void) - { - ... - - request_irq(IRQ_EINT0, button_irq, IRQF_TRIGGER_FALLING, - "button-irq-eint0", NULL); - - enable_irq_wake(IRQ_EINT0); - - s3c_pm_init(); - } - - -Debugging ---------- - - There are several important things to remember when using PM suspend: - - 1) The uart drivers will disable the clocks to the UART blocks when - suspending, which means that use of printascii() or similar direct - access to the UARTs will cause the debug to stop. - - 2) While the pm code itself will attempt to re-enable the UART clocks, - care should be taken that any external clock sources that the UARTs - rely on are still enabled at that point. - - 3) If any debugging is placed in the resume path, then it must have the - relevant clocks and peripherals setup before use (ie, bootloader). - - For example, if you transmit a character from the UART, the baud - rate and uart controls must be setup beforehand. - - -Configuration -------------- - - The S3C2410 specific configuration in `System Type` defines various - aspects of how the S3C2410 suspend and resume support is configured - - `S3C2410 PM Suspend debug` - - This option prints messages to the serial console before and after - the actual suspend, giving detailed information on what is - happening - - - `S3C2410 PM Suspend Memory CRC` - - Allows the entire memory to be checksummed before and after the - suspend to see if there has been any corruption of the contents. - - Note, the time to calculate the CRC is dependent on the CPU speed - and the size of memory. For an 64Mbyte RAM area on an 200MHz - S3C2410, this can take approximately 4 seconds to complete. - - This support requires the CRC32 function to be enabled. - - - `S3C2410 PM Suspend CRC Chunksize (KiB)` - - Defines the size of memory each CRC chunk covers. A smaller value - will mean that the CRC data block will take more memory, but will - identify any faults with better precision - - -Document Author ---------------- - -Ben Dooks, Copyright 2004 Simtec Electronics diff --git a/Documentation/arm/samsung-s3c24xx/usb-host.rst b/Documentation/arm/samsung-s3c24xx/usb-host.rst deleted file mode 100644 index 7aaffac89e0473fff6b3dbffde2ddf5d01749908..0000000000000000000000000000000000000000 --- a/Documentation/arm/samsung-s3c24xx/usb-host.rst +++ /dev/null @@ -1,91 +0,0 @@ -======================== -S3C24XX USB Host support -======================== - - - -Introduction ------------- - - This document details the S3C2410/S3C2440 in-built OHCI USB host support. - -Configuration -------------- - - Enable at least the following kernel options: - - menuconfig:: - - Device Drivers ---> - USB support ---> - <*> Support for Host-side USB - <*> OHCI HCD support - - - .config: - - - CONFIG_USB - - CONFIG_USB_OHCI_HCD - - - Once these options are configured, the standard set of USB device - drivers can be configured and used. - - -Board Support -------------- - - The driver attaches to a platform device, which will need to be - added by the board specific support file in arch/arm/mach-s3c, - such as mach-bast.c or mach-smdk2410.c - - The platform device's platform_data field is only needed if the - board implements extra power control or over-current monitoring. - - The OHCI driver does not ensure the state of the S3C2410's MISCCTRL - register, so if both ports are to be used for the host, then it is - the board support file's responsibility to ensure that the second - port is configured to be connected to the OHCI core. - - -Platform Data -------------- - - See include/linux/platform_data/usb-ohci-s3c2410.h for the - descriptions of the platform device data. An implementation - can be found in arch/arm/mach-s3c/simtec-usb.c . - - The `struct s3c2410_hcd_info` contains a pair of functions - that get called to enable over-current detection, and to - control the port power status. - - The ports are numbered 0 and 1. - - power_control: - Called to enable or disable the power on the port. - - enable_oc: - Called to enable or disable the over-current monitoring. - This should claim or release the resources being used to - check the power condition on the port, such as an IRQ. - - report_oc: - The OHCI driver fills this field in for the over-current code - to call when there is a change to the over-current state on - an port. The ports argument is a bitmask of 1 bit per port, - with bit X being 1 for an over-current on port X. - - The function s3c2410_usb_report_oc() has been provided to - ensure this is called correctly. - - port[x]: - This is struct describes each port, 0 or 1. The platform driver - should set the flags field of each port to S3C_HCDFLG_USED if - the port is enabled. - - - -Document Author ---------------- - -Ben Dooks, Copyright 2005 Simtec Electronics diff --git a/Documentation/arm/samsung/gpio.rst b/Documentation/arm/samsung/gpio.rst index f6e27b07c9939faa5cd1f0326ebc7b7645354402..27fae0d50361545479a43d604863db298ce5a750 100644 --- a/Documentation/arm/samsung/gpio.rst +++ b/Documentation/arm/samsung/gpio.rst @@ -9,14 +9,6 @@ This outlines the Samsung GPIO implementation and the architecture specific calls provided alongside the drivers/gpio core. -S3C24XX (Legacy) ----------------- - -See Documentation/arm/samsung-s3c24xx/gpio.rst for more information -about these devices. Their implementation has been brought into line -with the core samsung implementation described in this document. - - GPIOLIB integration ------------------- diff --git a/Documentation/arm/samsung/overview.rst b/Documentation/arm/samsung/overview.rst index e74307897416c523fea78dc59ed6f18e63d6f533..8b15a190169b006da4a7e13f6027850c7ffff762 100644 --- a/Documentation/arm/samsung/overview.rst +++ b/Documentation/arm/samsung/overview.rst @@ -12,21 +12,10 @@ Introduction The currently supported SoCs are: - - S3C24XX: See Documentation/arm/samsung-s3c24xx/overview.rst for full list - S3C64XX: S3C6400 and S3C6410 - S5PC110 / S5PV210 -S3C24XX Systems ---------------- - - There is still documentation in Documnetation/arm/Samsung-S3C24XX/ which - deals with the architecture and drivers specific to these devices. - - See Documentation/arm/samsung-s3c24xx/overview.rst for more information - on the implementation details and specific support. - - Configuration ------------- @@ -51,8 +40,6 @@ Layout specific information. It contains the base clock, GPIO and device definitions to get the system running. - plat-s3c24xx is for s3c24xx specific builds, see the S3C24XX docs. - plat-s5p is for s5p specific builds, and contains common support for the S5P specific systems. Not all S5Ps use all the features in this directory due to differences in the hardware. diff --git a/Documentation/arm64/booting.rst b/Documentation/arm64/booting.rst index 96fe10ec6c24018b655f0db36a9d662ee9f52c17..ffeccdd6bdac94420d2839c6f1966faa6d253fd3 100644 --- a/Documentation/arm64/booting.rst +++ b/Documentation/arm64/booting.rst @@ -223,7 +223,7 @@ Before jumping into the kernel, the following conditions must be met: For systems with a GICv3 interrupt controller to be used in v3 mode: - If EL3 is present: - - ICC_SRE_EL3.Enable (bit 3) must be initialiased to 0b1. + - ICC_SRE_EL3.Enable (bit 3) must be initialised to 0b1. - ICC_SRE_EL3.SRE (bit 0) must be initialised to 0b1. - ICC_CTLR_EL3.PMHE (bit 6) must be set to the same value across all CPUs the kernel is executing on, and must stay constant @@ -369,6 +369,16 @@ Before jumping into the kernel, the following conditions must be met: - HCR_EL2.ATA (bit 56) must be initialised to 0b1. + For CPUs with the Scalable Matrix Extension version 2 (FEAT_SME2): + + - If EL3 is present: + + - SMCR_EL3.EZT0 (bit 30) must be initialised to 0b1. + + - If the kernel is entered at EL1 and EL2 is present: + + - SMCR_EL2.EZT0 (bit 30) must be initialised to 0b1. + The requirements described above for CPU mode, caches, MMUs, architected timers, coherency and system registers apply to all CPUs. All CPUs must enter the kernel in the same exception level. Where the values documented diff --git a/Documentation/arm64/elf_hwcaps.rst b/Documentation/arm64/elf_hwcaps.rst index 6fed84f935dfed57f2227a05ce99dce56b90db6b..83e57e4d38e2a49d5bf63748c8b6e6dcfe10e8c5 100644 --- a/Documentation/arm64/elf_hwcaps.rst +++ b/Documentation/arm64/elf_hwcaps.rst @@ -14,7 +14,7 @@ Some hardware or software features are only available on some CPU implementations, and/or with certain kernel configurations, but have no architected discovery mechanism available to userspace code at EL0. The kernel exposes the presence of these features to userspace through a set -of flags called hwcaps, exposed in the auxilliary vector. +of flags called hwcaps, exposed in the auxiliary vector. Userspace software can test for features by acquiring the AT_HWCAP or AT_HWCAP2 entry of the auxiliary vector, and testing whether the relevant @@ -284,6 +284,24 @@ HWCAP2_RPRFM HWCAP2_SVE2P1 Functionality implied by ID_AA64ZFR0_EL1.SVEver == 0b0010. +HWCAP2_SME2 + Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0001. + +HWCAP2_SME2P1 + Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0010. + +HWCAP2_SMEI16I32 + Functionality implied by ID_AA64SMFR0_EL1.I16I32 == 0b0101 + +HWCAP2_SMEBI32I32 + Functionality implied by ID_AA64SMFR0_EL1.BI32I32 == 0b1 + +HWCAP2_SMEB16B16 + Functionality implied by ID_AA64SMFR0_EL1.B16B16 == 0b1 + +HWCAP2_SMEF16F16 + Functionality implied by ID_AA64SMFR0_EL1.F16F16 == 0b1 + 4. Unused AT_HWCAP bits ----------------------- diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst index 808ade4cc008ac7c41b0a13e5685fe5afae1dfe3..ec5f889d76819fd2fae733997d61ff1c33114ace 100644 --- a/Documentation/arm64/silicon-errata.rst +++ b/Documentation/arm64/silicon-errata.rst @@ -120,6 +120,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A710 | #2224489 | ARM64_ERRATUM_2224489 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A715 | #2645198 | ARM64_ERRATUM_2645198 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 | diff --git a/Documentation/arm64/sme.rst b/Documentation/arm64/sme.rst index 16d2db4c2e2e9b08c5a1005dbfd1ab9d8be7c7d0..1c43ea12eb4fdfb1682aa1d02bdae56e5931c410 100644 --- a/Documentation/arm64/sme.rst +++ b/Documentation/arm64/sme.rst @@ -18,14 +18,19 @@ model features for SME is included in Appendix A. 1. General ----------- -* PSTATE.SM, PSTATE.ZA, the streaming mode vector length, the ZA - register state and TPIDR2_EL0 are tracked per thread. +* PSTATE.SM, PSTATE.ZA, the streaming mode vector length, the ZA and (when + present) ZTn register state and TPIDR2_EL0 are tracked per thread. * The presence of SME is reported to userspace via HWCAP2_SME in the aux vector AT_HWCAP2 entry. Presence of this flag implies the presence of the SME instructions and registers, and the Linux-specific system interfaces described in this document. SME is reported in /proc/cpuinfo as "sme". +* The presence of SME2 is reported to userspace via HWCAP2_SME2 in the + aux vector AT_HWCAP2 entry. Presence of this flag implies the presence of + the SME2 instructions and ZT0, and the Linux-specific system interfaces + described in this document. SME2 is reported in /proc/cpuinfo as "sme2". + * Support for the execution of SME instructions in userspace can also be detected by reading the CPU ID register ID_AA64PFR1_EL1 using an MRS instruction, and checking that the value of the SME field is nonzero. [3] @@ -44,6 +49,7 @@ model features for SME is included in Appendix A. HWCAP2_SME_B16F32 HWCAP2_SME_F32F32 HWCAP2_SME_FA64 + HWCAP2_SME2 This list may be extended over time as the SME architecture evolves. @@ -52,8 +58,8 @@ model features for SME is included in Appendix A. cpu-feature-registers.txt for details. * Debuggers should restrict themselves to interacting with the target via the - NT_ARM_SVE, NT_ARM_SSVE and NT_ARM_ZA regsets. The recommended way - of detecting support for these regsets is to connect to a target process + NT_ARM_SVE, NT_ARM_SSVE, NT_ARM_ZA and NT_ARM_ZT regsets. The recommended + way of detecting support for these regsets is to connect to a target process first and then attempt a ptrace(PTRACE_GETREGSET, pid, NT_ARM_, &iov). @@ -89,13 +95,13 @@ be zeroed. ------------------------- * On syscall PSTATE.ZA is preserved, if PSTATE.ZA==1 then the contents of the - ZA matrix are preserved. + ZA matrix and ZTn (if present) are preserved. * On syscall PSTATE.SM will be cleared and the SVE registers will be handled as per the standard SVE ABI. -* Neither the SVE registers nor ZA are used to pass arguments to or receive - results from any syscall. +* None of the SVE registers, ZA or ZTn are used to pass arguments to + or receive results from any syscall. * On process creation (eg, clone()) the newly created process will have PSTATE.SM cleared. @@ -111,6 +117,9 @@ be zeroed. * Signal handlers are invoked with streaming mode and ZA disabled. +* A new signal frame record TPIDR2_MAGIC is added formatted as a struct + tpidr2_context to allow access to TPIDR2_EL0 from signal handlers. + * A new signal frame record za_context encodes the ZA register contents on signal delivery. [1] @@ -134,6 +143,14 @@ be zeroed. __reserved[] referencing this space. za_context is then written in the extra space. Refer to [1] for further details about this mechanism. +* If ZTn is supported and PSTATE.ZA==1 then a signal frame record for ZTn will + be generated. + +* The signal record for ZTn has magic ZT_MAGIC (0x5a544e01) and consists of a + standard signal frame header followed by a struct zt_context specifying + the number of ZTn registers supported by the system, then zt_context.nregs + blocks of 64 bytes of data per register. + 5. Signal return ----------------- @@ -151,6 +168,9 @@ When returning from a signal handler: the signal frame does not match the current vector length, the signal return attempt is treated as illegal, resulting in a forced SIGSEGV. +* If ZTn is not supported or PSTATE.ZA==0 then it is illegal to have a + signal frame record for ZTn, resulting in a forced SIGSEGV. + 6. prctl extensions -------------------- @@ -214,8 +234,8 @@ prctl(PR_SME_SET_VL, unsigned long arg) vector length that will be applied at the next execve() by the calling thread. - * Changing the vector length causes all of ZA, P0..P15, FFR and all bits of - Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become + * Changing the vector length causes all of ZA, ZTn, P0..P15, FFR and all + bits of Z0..Z31 except for Z0 bits [127:0] .. Z31 bits [127:0] to become unspecified, including both streaming and non-streaming SVE state. Calling PR_SME_SET_VL with vl equal to the thread's current vector length, or calling PR_SME_SET_VL with the PR_SVE_SET_VL_ONEXEC flag, @@ -317,6 +337,15 @@ The regset data starts with struct user_za_header, containing: * The effect of writing a partial, incomplete payload is unspecified. +* A new regset NT_ARM_ZT is defined for access to ZTn state via + PTRACE_GETREGSET and PTRACE_SETREGSET. + +* The NT_ARM_ZT regset consists of a single 512 bit register. + +* When PSTATE.ZA==0 reads of NT_ARM_ZT will report all bits of ZTn as 0. + +* Writes to NT_ARM_ZT will set PSTATE.ZA to 1. + 8. ELF coredump extensions --------------------------- @@ -331,6 +360,11 @@ The regset data starts with struct user_za_header, containing: been read if a PTRACE_GETREGSET of NT_ARM_ZA were executed for each thread when the coredump was generated. +* A NT_ARM_ZT note will be added to each coredump for each thread of the + dumped process. The contents will be equivalent to the data that would have + been read if a PTRACE_GETREGSET of NT_ARM_ZT were executed for each thread + when the coredump was generated. + * The NT_ARM_TLS note will be extended to two registers, the second register will contain TPIDR2_EL0 on systems that support SME and will be read as zero with writes ignored otherwise. @@ -406,6 +440,9 @@ In A64 state, SME adds the following: For best system performance it is strongly encouraged for software to enable ZA only when it is actively being used. +* A new ZT0 register is introduced when SME2 is present. This is a 512 bit + register which is accessible when PSTATE.ZA is set, as ZA itself is. + * Two new 1 bit fields in PSTATE which may be controlled via the SMSTART and SMSTOP instructions or by access to the SVCR system register: diff --git a/Documentation/arm64/sve.rst b/Documentation/arm64/sve.rst index c7a356bf4e8f824fffb38dfaf7307d5e503549ff..1b90a30382ac04e46b75061dd3ea8a4432eb76a5 100644 --- a/Documentation/arm64/sve.rst +++ b/Documentation/arm64/sve.rst @@ -175,7 +175,7 @@ the SVE instruction set architecture. When returning from a signal handler: * If there is no sve_context record in the signal frame, or if the record is - present but contains no register data as desribed in the previous section, + present but contains no register data as described in the previous section, then the SVE registers/bits become non-live and take unspecified values. * If sve_context is present in the signal frame and contains full register @@ -223,7 +223,7 @@ prctl(PR_SVE_SET_VL, unsigned long arg) Defer the requested vector length change until the next execve() performed by this thread. - The effect is equivalent to implicit exceution of the following + The effect is equivalent to implicit execution of the following call immediately after the next execve() (if any) by the thread: prctl(PR_SVE_SET_VL, arg & ~PR_SVE_SET_VL_ONEXEC) diff --git a/Documentation/block/capability.rst b/Documentation/block/capability.rst deleted file mode 100644 index 2ae7f064736ad3d16fcbc7e138834aa41d0f92b6..0000000000000000000000000000000000000000 --- a/Documentation/block/capability.rst +++ /dev/null @@ -1,10 +0,0 @@ -=============================== -Generic Block Device Capability -=============================== - -This file documents the sysfs file ``block//capability``. - -``capability`` is a bitfield, printed in hexadecimal, indicating which -capabilities a specific block device supports: - -.. kernel-doc:: include/linux/blkdev.h diff --git a/Documentation/block/index.rst b/Documentation/block/index.rst index c4c73db748a81f8c782db1e60dbe7b59480a3883..102953166429bfea82614f452a8b17e38adcde49 100644 --- a/Documentation/block/index.rst +++ b/Documentation/block/index.rst @@ -10,7 +10,6 @@ Block bfq-iosched biovecs blk-mq - capability cmdline-partition data-integrity deadline-iosched diff --git a/Documentation/block/ublk.rst b/Documentation/block/ublk.rst index ba45c46cc0dacf558308833bafa95441c6437d82..1713b2890abb04e4bd05ce240171fd444c4078a0 100644 --- a/Documentation/block/ublk.rst +++ b/Documentation/block/ublk.rst @@ -144,6 +144,43 @@ managing and controlling ublk devices with help of several control commands: For retrieving device info via ``ublksrv_ctrl_dev_info``. It is the server's responsibility to save IO target specific info in userspace. +- ``UBLK_CMD_GET_DEV_INFO2`` + Same purpose with ``UBLK_CMD_GET_DEV_INFO``, but ublk server has to + provide path of the char device of ``/dev/ublkc*`` for kernel to run + permission check, and this command is added for supporting unprivileged + ublk device, and introduced with ``UBLK_F_UNPRIVILEGED_DEV`` together. + Only the user owning the requested device can retrieve the device info. + + How to deal with userspace/kernel compatibility: + + 1) if kernel is capable of handling ``UBLK_F_UNPRIVILEGED_DEV`` + + If ublk server supports ``UBLK_F_UNPRIVILEGED_DEV``: + + ublk server should send ``UBLK_CMD_GET_DEV_INFO2``, given anytime + unprivileged application needs to query devices the current user owns, + when the application has no idea if ``UBLK_F_UNPRIVILEGED_DEV`` is set + given the capability info is stateless, and application should always + retrieve it via ``UBLK_CMD_GET_DEV_INFO2`` + + If ublk server doesn't support ``UBLK_F_UNPRIVILEGED_DEV``: + + ``UBLK_CMD_GET_DEV_INFO`` is always sent to kernel, and the feature of + UBLK_F_UNPRIVILEGED_DEV isn't available for user + + 2) if kernel isn't capable of handling ``UBLK_F_UNPRIVILEGED_DEV`` + + If ublk server supports ``UBLK_F_UNPRIVILEGED_DEV``: + + ``UBLK_CMD_GET_DEV_INFO2`` is tried first, and will be failed, then + ``UBLK_CMD_GET_DEV_INFO`` needs to be retried given + ``UBLK_F_UNPRIVILEGED_DEV`` can't be set + + If ublk server doesn't support ``UBLK_F_UNPRIVILEGED_DEV``: + + ``UBLK_CMD_GET_DEV_INFO`` is always sent to kernel, and the feature of + ``UBLK_F_UNPRIVILEGED_DEV`` isn't available for user + - ``UBLK_CMD_START_USER_RECOVERY`` This command is valid if ``UBLK_F_USER_RECOVERY`` feature is enabled. This @@ -180,6 +217,15 @@ managing and controlling ublk devices with help of several control commands: double-write since the driver may issue the same I/O request twice. It might be useful to a read-only FS or a VM backend. +Unprivileged ublk device is supported by passing ``UBLK_F_UNPRIVILEGED_DEV``. +Once the flag is set, all control commands can be sent by unprivileged +user. Except for command of ``UBLK_CMD_ADD_DEV``, permission check on +the specified char device(``/dev/ublkc*``) is done for all other control +commands by ublk driver, for doing that, path of the char device has to +be provided in these commands' payload from ublk server. With this way, +ublk device becomes container-ware, and device created in one container +can be controlled/accessed just inside this container. + Data plane ---------- @@ -254,15 +300,6 @@ with specified IO tag in the command data: Future development ================== -Container-aware ublk deivice ----------------------------- - -ublk driver doesn't handle any IO logic. Its function is well defined -for now and very limited userspace interfaces are needed, which is also -well defined too. It is possible to make ublk devices container-aware block -devices in future as Stefan Hajnoczi suggested [#stefan]_, by removing -ADMIN privilege. - Zero copy --------- diff --git a/Documentation/conf.py b/Documentation/conf.py index a5c45df0bd83978028691abca71ab9d6c5155d8c..d927737e3c10fe207456f9eb360958c8b8a500a4 100644 --- a/Documentation/conf.py +++ b/Documentation/conf.py @@ -31,6 +31,12 @@ def have_command(cmd): # Get Sphinx version major, minor, patch = sphinx.version_info[:3] +# +# Warn about older versions that we don't want to support for much +# longer. +# +if (major < 2) or (major == 2 and minor < 4): + print('WARNING: support for Sphinx < 2.4 will be removed soon.') # If extensions (or modules to document with autodoc) are in another directory, # add these directories to sys.path here. If the directory is relative to the @@ -339,7 +345,11 @@ html_use_smartypants = False # Custom sidebar templates, maps document names to template names. # Note that the RTD theme ignores this -html_sidebars = { '**': ["about.html", 'searchbox.html', 'localtoc.html', 'sourcelink.html']} +html_sidebars = { '**': ['searchbox.html', 'localtoc.html', 'sourcelink.html']} + +# about.html is available for alabaster theme. Add it at the front. +if html_theme == 'alabaster': + html_sidebars['**'].insert(0, 'about.html') # Output file base name for HTML help builder. htmlhelp_basename = 'TheLinuxKerneldoc' diff --git a/Documentation/devicetree/bindings/.gitignore b/Documentation/devicetree/bindings/.gitignore index a77719968a7e1a71f8b3e87b8e1ede10b2a4ea1b..51ddb26d93f029725f6b01be971e8445ab2f0578 100644 --- a/Documentation/devicetree/bindings/.gitignore +++ b/Documentation/devicetree/bindings/.gitignore @@ -2,3 +2,8 @@ *.example.dts /processed-schema*.yaml /processed-schema*.json + +# +# We don't want to ignore the following even if they are dot-files +# +!.yamllint diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 3eee03aa935c7e83479e14a83cdc4e174557fe08..8c757545542243e8297c0dfd8513d19f4d74811c 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -31,6 +31,7 @@ properties: - description: Mercury+ AA1 boards items: - enum: + - enclustra,mercury-pe1 - google,chameleon-v3 - const: enclustra,mercury-aa1 - const: altr,socfpga-arria10 diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index e16b5fa5584727388ed67b5d0a89b3e5aa64ea27..b634d5b04e1550353e293f52c4add18149118ade 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -154,6 +154,7 @@ properties: items: - enum: - khadas,vim3 + - radxa,zero2 - const: amlogic,a311d - const: amlogic,g12b @@ -165,6 +166,7 @@ properties: - azw,gtking-pro - hardkernel,odroid-go-ultra - hardkernel,odroid-n2 + - hardkernel,odroid-n2l - hardkernel,odroid-n2-plus - khadas,vim3 - ugoos,am6 @@ -176,6 +178,7 @@ properties: - enum: - amediatech,x96-air - amediatech,x96-air-gbit + - bananapi,bpi-m2-pro - bananapi,bpi-m5 - cyx,a95xf3-air - cyx,a95xf3-air-gbit diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 73f272664e83500a350b4db95222547af9ffa1b3..e0eff4c05879baa717aa5f26f8b9a5e34355baca 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -78,6 +78,7 @@ properties: - facebook,cloudripper-bmc - facebook,elbert-bmc - facebook,fuji-bmc + - facebook,greatlakes-bmc - ibm,everest-bmc - ibm,rainier-bmc - ibm,tacoma-bmc @@ -85,6 +86,7 @@ properties: - jabil,rbp-bmc - qcom,dc-scm-v1-bmc - quanta,s6q-bmc + - ufispace,ncplite-bmc - const: aspeed,ast2600 additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/atmel-at91.yaml b/Documentation/devicetree/bindings/arm/atmel-at91.yaml index 2224b18801a1993a2607e2cd9aafea78d750635e..dfb8fd0891973536bedd656cda5b38289f807408 100644 --- a/Documentation/devicetree/bindings/arm/atmel-at91.yaml +++ b/Documentation/devicetree/bindings/arm/atmel-at91.yaml @@ -91,9 +91,11 @@ properties: - const: atmel,sama5d2 - const: atmel,sama5 - - description: SAM9X60-EK board + - description: Microchip SAM9X60 Evaluation Boards items: - - const: microchip,sam9x60ek + - enum: + - microchip,sam9x60ek + - microchip,sam9x60-curiosity - const: microchip,sam9x60 - const: atmel,at91sam9 diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 05b5276a0e14cf7fa85aca88ed6dfa402eb89bf5..442ce8f4d67560eae4220e907e08f2f0fc944418 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -88,12 +88,56 @@ properties: items: - enum: - armadeus,imx28-apf28 # APF28 SoM - - armadeus,imx28-apf28dev # APF28 SoM on APF28Dev board + - bluegiga,apx4devkit # Bluegiga APx4 SoM on dev board + - crystalfontz,cfa10036 # Crystalfontz CFA-10036 SoM + - eukrea,mbmx28lc - fsl,imx28-evk - i2se,duckbill - i2se,duckbill-2 + - karo,tx28 # Ka-Ro electronics TX28 module + - lwn,imx28-xea + - msr,m28cu3 # M28 SoM with custom base board + - schulercontrol,imx28-sps1 - technologic,imx28-ts4600 - const: fsl,imx28 + + - description: i.MX28 Aries M28 SoM Board + items: + - const: aries,m28 + - const: denx,m28 + - const: fsl,imx28 + + - description: i.MX28 Aries M28EVK Board + items: + - const: aries,m28evk + - const: denx,m28evk + - const: fsl,imx28 + + - description: i.MX28 Armadeus Systems APF28Dev Board + items: + - const: armadeus,imx28-apf28dev + - const: armadeus,imx28-apf28 + - const: fsl,imx28 + + - description: i.MX28 Crystalfontz CFA-10036 based Boards + items: + - enum: + - crystalfontz,cfa10037 + - crystalfontz,cfa10049 + - crystalfontz,cfa10057 + - crystalfontz,cfa10058 + - const: crystalfontz,cfa10036 + - const: fsl,imx28 + + - description: i.MX28 Crystalfontz CFA-10037 based Boards + items: + - enum: + - crystalfontz,cfa10055 + - crystalfontz,cfa10056 + - const: crystalfontz,cfa10037 + - const: crystalfontz,cfa10036 + - const: fsl,imx28 + - description: i.MX28 Duckbill 2 based Boards items: - enum: @@ -103,6 +147,19 @@ properties: - const: i2se,duckbill-2 - const: fsl,imx28 + - description: i.MX28 Eukrea Electromatique MBMX283LC Board + items: + - const: eukrea,mbmx283lc + - const: eukrea,mbmx28lc + - const: fsl,imx28 + + - description: i.MX28 Eukrea Electromatique MBMX287LC Board + items: + - const: eukrea,mbmx287lc + - const: eukrea,mbmx283lc + - const: eukrea,mbmx28lc + - const: fsl,imx28 + - description: i.MX31 based Boards items: - enum: @@ -173,6 +230,7 @@ properties: - kiebackpeter,imx53-ddc # K+P imx53 DDC - kiebackpeter,imx53-hsc # K+P imx53 HSC - menlo,m53menlo # i.MX53 Menlo board + - starterkit,sk-imx53 - voipac,imx53-dmm-668 # Voipac i.MX53 X53-DMM-668 - const: fsl,imx53 @@ -644,6 +702,16 @@ properties: - const: armadeus,imx6ull-opos6ul # OPOS6UL (i.MX6ULL) SoM - const: fsl,imx6ull + - description: i.MX6ULL DHCOM SoM based Boards + items: + - enum: + - dh,imx6ull-dhcom-drc02 + - dh,imx6ull-dhcom-pdk2 + - dh,imx6ull-dhcom-picoitx + - const: dh,imx6ull-dhcom-som # The DHCOR is soldered on the DHCOM + - const: dh,imx6ull-dhcor-som + - const: fsl,imx6ull + - description: i.MX6ULL PHYTEC phyBOARD-Segin items: - enum: @@ -815,7 +883,6 @@ properties: - enum: - beacon,imx8mm-beacon-kit # i.MX8MM Beacon Development Kit - boundary,imx8mm-nitrogen8mm # i.MX8MM Nitrogen Board - - cloos,imx8mm-phg # i.MX8MM Cloos PHG Board - dmo,imx8mm-data-modul-edm-sbc # i.MX8MM eDM SBC - emtrion,emcon-mx8mm-avari # emCON-MX8MM SoM on Avari Base - fsl,imx8mm-ddr4-evk # i.MX8MM DDR4 EVK Board @@ -830,7 +897,6 @@ properties: - innocomm,wb15-evk # i.MX8MM Innocomm EVK board with WB15 SoM - kontron,imx8mm-sl # i.MX8MM Kontron SL (N801X) SOM - kontron,imx8mm-osm-s # i.MX8MM Kontron OSM-S (N802X) SOM - - menlo,mx8menlo # i.MX8MM Menlo board with Verdin SoM - toradex,verdin-imx8mm # Verdin iMX8M Mini Modules - toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Modules without Wi-Fi / BT - toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Modules @@ -861,8 +927,10 @@ properties: - description: Toradex Boards with Verdin iMX8M Mini Modules items: - enum: + - menlo,mx8menlo # Verdin iMX8M Mini Module on i.MX8MM Menlo board - toradex,verdin-imx8mm-nonwifi-dahlia # Verdin iMX8M Mini Module on Dahlia - toradex,verdin-imx8mm-nonwifi-dev # Verdin iMX8M Mini Module on Verdin Development Board + - toradex,verdin-imx8mm-nonwifi-yavia # Verdin iMX8M Mini Module on Yavia - const: toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Module without Wi-Fi / BT - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module - const: fsl,imx8mm @@ -872,6 +940,7 @@ properties: - enum: - toradex,verdin-imx8mm-wifi-dahlia # Verdin iMX8M Mini Wi-Fi / BT Module on Dahlia - toradex,verdin-imx8mm-wifi-dev # Verdin iMX8M Mini Wi-Fi / BT M. on Verdin Development B. + - toradex,verdin-imx8mm-wifi-yavia # Verdin iMX8M Mini Wi-Fi / BT Module on Yavia - const: toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Module - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module - const: fsl,imx8mm @@ -895,6 +964,7 @@ properties: one compatible is needed. items: - enum: + - cloos,imx8mm-phg # i.MX8MM Cloos PHG Board - tq,imx8mm-tqma8mqml-mba8mx # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM on MBa8Mx - const: tq,imx8mm-tqma8mqml # TQ-Systems GmbH i.MX8MM TQMa8MQML SOM - const: fsl,imx8mm @@ -931,10 +1001,11 @@ properties: - description: i.MX8MP based Boards items: - enum: - - dh,imx8mp-dhcom-som # i.MX8MP DHCOM SoM - - dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board + - beacon,imx8mp-beacon-kit # i.MX8MP Beacon Development Kit - fsl,imx8mp-evk # i.MX8MP EVK Board - gateworks,imx8mp-gw74xx # i.MX8MP Gateworks Board + - polyhex,imx8mp-debix # Polyhex Debix boards + - polyhex,imx8mp-debix-model-a # Polyhex Debix Model A Board - toradex,verdin-imx8mp # Verdin iMX8M Plus Modules - toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Modules without Wi-Fi / BT - toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Modules @@ -947,6 +1018,12 @@ properties: - const: avnet,sm2s-imx8mp # SM2S-IMX8PLUS SoM - const: fsl,imx8mp + - description: i.MX8MP DHCOM based Boards + items: + - const: dh,imx8mp-dhcom-pdk2 # i.MX8MP DHCOM SoM on PDK2 board + - const: dh,imx8mp-dhcom-som # i.MX8MP DHCOM SoM + - const: fsl,imx8mp + - description: Engicam i.Core MX8M Plus SoM based boards items: - enum: @@ -965,6 +1042,7 @@ properties: - enum: - toradex,verdin-imx8mp-nonwifi-dahlia # Verdin iMX8M Plus Module on Dahlia - toradex,verdin-imx8mp-nonwifi-dev # Verdin iMX8M Plus Module on Verdin Development Board + - toradex,verdin-imx8mp-nonwifi-yavia # Verdin iMX8M Plus Module on Yavia - const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module - const: fsl,imx8mp @@ -974,6 +1052,7 @@ properties: - enum: - toradex,verdin-imx8mp-wifi-dahlia # Verdin iMX8M Plus Wi-Fi / BT Module on Dahlia - toradex,verdin-imx8mp-wifi-dev # Verdin iMX8M Plus Wi-Fi / BT M. on Verdin Development B. + - toradex,verdin-imx8mp-wifi-yavia # Verdin iMX8M Plus Wi-Fi / BT Module on Yavia - const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module - const: fsl,imx8mp @@ -999,12 +1078,17 @@ properties: - fsl,imx8mq-evk # i.MX8MQ EVK Board - google,imx8mq-phanbell # Google Coral Edge TPU - kontron,pitx-imx8m # Kontron pITX-imx8m Board - - mntre,reform2 # MNT Reform2 Laptop - purism,librem5-devkit # Purism Librem5 devkit - solidrun,hummingboard-pulse # SolidRun Hummingboard Pulse - technexion,pico-pi-imx8m # TechNexion PICO-PI-8M evk - const: fsl,imx8mq + - description: i.MX8MQ NITROGEN SoM based Boards + items: + - const: mntre,reform2 # MNT Reform2 Laptop + - const: boundary,imx8mq-nitrogen8m-som # i.MX8MQ NITROGEN SoM + - const: fsl,imx8mq + - description: Purism Librem5 phones items: - enum: diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 2275e5d93721b654aafeeb092329a826f1868db9..ae12b1cab9fbde5aca05765b1c471af93943d334 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -244,6 +244,10 @@ properties: - enum: - mediatek,mt8183-pumpkin - const: mediatek,mt8183 + - items: + - enum: + - mediatek,mt8365-evk + - const: mediatek,mt8365 - items: - enum: - mediatek,mt8516-pumpkin diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index 27063a045bd0a8cef1dc578eb8d32de7b1c0ed2d..1bb24d46e4eec9fe39ab8b9c2cfd83fce01a1e3a 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -35,6 +35,8 @@ description: | mdm9615 msm8226 msm8916 + msm8939 + msm8953 msm8956 msm8974 msm8976 @@ -47,11 +49,13 @@ description: | qru1000 sa8155p sa8540p + sa8775p sc7180 sc7280 sc8180x sc8280xp sda660 + sdm450 sdm630 sdm632 sdm636 @@ -62,6 +66,7 @@ description: | sdx65 sm4250 sm6115 + sm6115p sm6125 sm6350 sm6375 @@ -70,6 +75,7 @@ description: | sm8250 sm8350 sm8450 + sm8550 The 'board' element must be one of the following strings: @@ -84,6 +90,7 @@ description: | liquid mtp qrd + ride sbc x100 @@ -160,6 +167,12 @@ properties: - samsung,s3ve3g - const: qcom,msm8226 + - items: + - enum: + - sony,kanuti-tulip + - square,apq8039-t2 + - const: qcom,msm8939 + - items: - enum: - sony,kugo-row @@ -194,8 +207,10 @@ properties: - items: - enum: + - acer,a1-724 - alcatel,idol347 - asus,z00l + - gplus,fl8005a - huawei,g7 - longcheer,l8910 - samsung,a3u-eur @@ -203,8 +218,13 @@ properties: - samsung,e5 - samsung,e7 - samsung,grandmax + - samsung,gt510 + - samsung,gt58 - samsung,j5 + - samsung,j5x - samsung,serranove + - thwc,uf896 + - thwc,ufi001c - wingtech,wt88047 - const: qcom,msm8916 @@ -213,6 +233,15 @@ properties: - const: qcom,msm8916-v1-qrd/9-v1 - const: qcom,msm8916 + - items: + - enum: + - motorola,potter + - xiaomi,daisy + - xiaomi,mido + - xiaomi,tissot + - xiaomi,vince + - const: qcom,msm8953 + - items: - enum: - lg,bullhead @@ -627,6 +656,12 @@ properties: - const: google,hoglin - const: qcom,sc7280 + - description: Qualcomm Technologies, Inc. sc7280 CRD Pro platform (newest rev) + items: + - const: google,zoglin-sku1536 + - const: google,hoglin-sku1536 + - const: qcom,sc7280 + - description: Qualcomm Technologies, Inc. sc7280 IDP SKU1 platform items: - const: qcom,sc7280-idp @@ -679,6 +714,18 @@ properties: - const: google,zombie-sku512 - const: qcom,sc7280 + - description: Google Zombie with NVMe (newest rev) + items: + - const: google,zombie-sku2 + - const: google,zombie-sku3 + - const: google,zombie-sku515 + - const: qcom,sc7280 + + - description: Google Zombie with LTE and NVMe (newest rev) + items: + - const: google,zombie-sku514 + - const: qcom,sc7280 + - items: - enum: - lenovo,flex-5g @@ -693,6 +740,11 @@ properties: - qcom,sc8280xp-qrd - const: qcom,sc8280xp + - items: + - enum: + - motorola,ali + - const: qcom,sdm450 + - items: - enum: - sony,discovery-row @@ -709,6 +761,7 @@ properties: - items: - enum: - fairphone,fp3 + - motorola,ocean - const: qcom,sdm632 - items: @@ -762,6 +815,11 @@ properties: - qcom,sa8540p-ride - const: qcom,sa8540p + - items: + - enum: + - qcom,sa8775p-ride + - const: qcom,sa8775p + - items: - enum: - google,cheza @@ -790,6 +848,12 @@ properties: - oneplus,billie2 - const: qcom,sm4250 + - items: + - enum: + - lenovo,j606f + - const: qcom,sm6115p + - const: qcom,sm6115 + - items: - enum: - sony,pdx201 @@ -826,6 +890,7 @@ properties: - qcom,sm8250-mtp - sony,pdx203-generic - sony,pdx206-generic + - xiaomi,elish - const: qcom,sm8250 - items: @@ -845,6 +910,11 @@ properties: - sony,pdx224 - const: qcom,sm8450 + - items: + - enum: + - qcom,sm8550-mtp + - const: qcom,sm8550 + # Board compatibles go above qcom,msm-id: @@ -922,15 +992,22 @@ allOf: - qcom,apq8026 - qcom,apq8094 - qcom,apq8096 + - qcom,msm8939 + - qcom,msm8953 + - qcom,msm8956 - qcom,msm8992 - qcom,msm8994 - qcom,msm8996 - qcom,msm8998 + - qcom,sdm450 - qcom,sdm630 - qcom,sdm632 + - qcom,sdm636 - qcom,sdm845 - qcom,sdx55 - qcom,sdx65 + - qcom,sm4250 + - qcom,sm6115 - qcom,sm6125 - qcom,sm6350 - qcom,sm7225 @@ -954,6 +1031,8 @@ allOf: - oneplus,dumpling - oneplus,enchilada - oneplus,fajita + - oneplus,oneplus3 + - oneplus,oneplus3t then: properties: qcom,board-id: diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 88ff4422a8c10ac7d075085d814f275e9683fd0e..35f74eda30aea07a5d9a3bb61f172312a60f1fd7 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -90,11 +90,33 @@ properties: - const: chipspark,rayeager-px2 - const: rockchip,rk3066a + - description: Edgeble Neural Compute Module 2(Neu2) SoM based boards + items: + - const: edgeble,neural-compute-module-2-io # Edgeble Neural Compute Module 2 IO Board + - const: edgeble,neural-compute-module-2 # Edgeble Neural Compute Module 2 SoM + - const: rockchip,rv1126 + + - description: Edgeble Neural Compute Module 6(Neu6) Model A SoM based boards + items: + - const: edgeble,neural-compute-module-6a-io # Edgeble Neural Compute Module 6A IO Board + - const: edgeble,neural-compute-module-6a # Edgeble Neural Compute Module 6A SoM + - const: rockchip,rk3588 + - description: Elgin RV1108 R1 items: - const: elgin,rv1108-r1 - const: rockchip,rv1108 + - description: EmbedFire LubanCat 1 + items: + - const: embedfire,lubancat-1 + - const: rockchip,rk3566 + + - description: EmbedFire LubanCat 2 + items: + - const: embedfire,lubancat-2 + - const: rockchip,rk3568 + - description: Engicam PX30.Core C.TOUCH 2.0 items: - const: engicam,px30-core-ctouch2 @@ -599,6 +621,20 @@ properties: - const: pine64,soquartz - const: rockchip,rk3566 + - description: Radxa Compute Module 3(CM3) + items: + - enum: + - radxa,cm3-io + - const: radxa,cm3 + - const: rockchip,rk3566 + + - description: Radxa CM3 Industrial + items: + - enum: + - radxa,e25 + - const: radxa,cm3i + - const: rockchip,rk3568 + - description: Radxa Rock items: - const: radxa,rock @@ -652,6 +688,16 @@ properties: - const: radxa,rock3a - const: rockchip,rk3568 + - description: Radxa ROCK 5 Model A + items: + - const: radxa,rock-5a + - const: rockchip,rk3588s + + - description: Radxa ROCK 5 Model B + items: + - const: radxa,rock-5b + - const: rockchip,rk3588 + - description: Rikomagic MK808 v1 items: - const: rikomagic,mk808 @@ -689,6 +735,11 @@ properties: - const: rockchip,rk3036-evb - const: rockchip,rk3036 + - description: Rockchip RK3128 Evaluation board + items: + - const: rockchip,rk3128-evb + - const: rockchip,rk3128 + - description: Rockchip RK3228 Evaluation board items: - const: rockchip,rk3228-evb @@ -736,6 +787,11 @@ properties: - const: rockchip,rk3399-sapphire-excavator - const: rockchip,rk3399 + - description: Rockchip RK3588 Evaluation board + items: + - const: rockchip,rk3588-evb1-v10 + - const: rockchip,rk3588 + - description: Rockchip RV1108 Evaluation board items: - const: rockchip,rv1108-evb @@ -761,6 +817,11 @@ properties: - const: tronsmart,orion-r68-meta - const: rockchip,rk3368 + - description: Xunlong Orange Pi R1 Plus + items: + - const: xunlong,orangepi-r1-plus + - const: rockchip,rk3328 + - description: Zkmagic A95X Z2 items: - const: zkmagic,a95x-z2 diff --git a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml index 8c73bc7f4009fc3a3241a783f1d81cbbf724680c..b79c81cd9f0e65f04e46690f3192502a8437e34e 100644 --- a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml @@ -27,6 +27,7 @@ select: - rockchip,rk3399-pmu - rockchip,rk3568-pmu - rockchip,rk3588-pmu + - rockchip,rv1126-pmu required: - compatible @@ -43,6 +44,7 @@ properties: - rockchip,rk3399-pmu - rockchip,rk3568-pmu - rockchip,rk3588-pmu + - rockchip,rv1126-pmu - const: syscon - const: simple-mfd diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index faea33e4f7316043b932bc4af8a834fc978a2087..deb2cf97187188d3a969d8ae1cb48a07504224b5 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -171,6 +171,7 @@ properties: - hardkernel,odroid-xu3-lite # Hardkernel Odroid XU3 Lite - hardkernel,odroid-xu4 # Hardkernel Odroid XU4 - hardkernel,odroid-hc1 # Hardkernel Odroid HC1 + - samsung,k3g # Samsung Galaxy S5 (SM-G900H) - const: samsung,exynos5800 - const: samsung,exynos5 diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 203faab80142bbd4bca7edc22164b81bc733cd8c..a60a4065caa82394fc8bd5c338e44e44815fa2f0 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -38,10 +38,17 @@ properties: - ti,am642-sk - const: ti,am642 + - description: K3 AM642 SoC PHYTEC phyBOARD-Electra + items: + - const: phytec,am642-phyboard-electra-rdk + - const: phytec,am64-phycore-som + - const: ti,am642 + - description: K3 AM654 SoC items: - enum: - siemens,iot2050-advanced + - siemens,iot2050-advanced-m2 - siemens,iot2050-advanced-pg2 - siemens,iot2050-basic - siemens,iot2050-basic-pg2 @@ -69,9 +76,17 @@ properties: - description: K3 J721s2 SoC items: - enum: + - ti,am68-sk - ti,j721s2-evm - const: ti,j721s2 + - description: K3 J784s4 SoC + items: + - enum: + - ti,am69-sk + - ti,j784s4-evm + - const: ti,j784s4 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml index d3ed048c952165a685b02a19ac54a2644ab226cd..4157e885c6e7dee478e771945ab6d763efef5d1f 100644 --- a/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml +++ b/Documentation/devicetree/bindings/bus/nvidia,tegra210-aconnect.yaml @@ -40,10 +40,10 @@ properties: maxItems: 1 "#address-cells": - const: 1 + enum: [ 1, 2 ] "#size-cells": - const: 1 + enum: [ 1, 2 ] ranges: true diff --git a/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..767a9d03aa3274be0af6f60d3489a895af92d4df --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,qdu1000-gcc.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,qdu1000-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller for QDU1000 and QRU1000 + +maintainers: + - Melody Olvera + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on QDU1000 and QRU1000 + + See also:: include/dt-bindings/clock/qcom,qdu1000-gcc.h + +properties: + compatible: + const: qcom,qdu1000-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source + - description: PCIE 0 Phy Auxiliary clock source + - description: USB3 Phy wrapper pipe clock source + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@100000 { + compatible = "qcom,qdu1000-gcc"; + reg = <0x00100000 0x001f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&pcie_0_pipe_clk>, <&pcie_0_phy_aux_clk>, + <&usb3_phy_wrapper_pipe_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..fd6658cb793dbb32526f7208f29a7cde9fa027b2 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm6350-camcc.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm6350-camcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Camera Clock & Reset Controller on SM6350 + +maintainers: + - Konrad Dybcio + +description: | + Qualcomm camera clock control module provides the clocks, resets and power + domains on SM6350. + + See also:: include/dt-bindings/clock/qcom,sm6350-camcc.h + +properties: + compatible: + const: qcom,sm6350-camcc + + clocks: + items: + - description: Board XO source + + reg: + maxItems: 1 + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@ad00000 { + compatible = "qcom,sm6350-camcc"; + reg = <0x0ad00000 0x16000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..ab25f7cbaa2ee3b11c45eed46f01f99afe108528 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-dispcc.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8550-dispcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Display Clock & Reset Controller for SM8550 + +maintainers: + - Bjorn Andersson + - Neil Armstrong + +description: | + Qualcomm display clock control module provides the clocks, resets and power + domains on SM8550. + + See also:: include/dt-bindings/clock/qcom,sm8550-dispcc.h + +properties: + compatible: + enum: + - qcom,sm8550-dispcc + + clocks: + items: + - description: Board XO source + - description: Board Always On XO source + - description: Display's AHB clock + - description: sleep clock + - description: Byte clock from DSI PHY0 + - description: Pixel clock from DSI PHY0 + - description: Byte clock from DSI PHY1 + - description: Pixel clock from DSI PHY1 + - description: Link clock from DP PHY0 + - description: VCO DIV clock from DP PHY0 + - description: Link clock from DP PHY1 + - description: VCO DIV clock from DP PHY1 + - description: Link clock from DP PHY2 + - description: VCO DIV clock from DP PHY2 + - description: Link clock from DP PHY3 + - description: VCO DIV clock from DP PHY3 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + '#power-domain-cells': + const: 1 + + reg: + maxItems: 1 + + power-domains: + description: + A phandle and PM domain specifier for the MMCX power domain. + maxItems: 1 + + required-opps: + description: + A phandle to an OPP node describing required MMCX performance point. + maxItems: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#reset-cells' + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + #include + #include + clock-controller@af00000 { + compatible = "qcom,sm8550-dispcc"; + reg = <0x0af00000 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <&dsi0_phy 0>, + <&dsi0_phy 1>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <&dp0_phy 0>, + <&dp0_phy 1>, + <&dp1_phy 0>, + <&dp1_phy 1>, + <&dp2_phy 0>, + <&dp2_phy 1>, + <&dp3_phy 0>, + <&dp3_phy 1>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + power-domains = <&rpmhpd SM8550_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml new file mode 100644 index 0000000000000000000000000000000000000000..1bf1a41fd89c2bc1237d41f4de2b6f8f61cd2622 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,sm8550-tcsr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm TCSR Clock Controller on SM8550 + +maintainers: + - Bjorn Andersson + +description: | + Qualcomm TCSR clock control module provides the clocks, resets and + power domains on SM8550 + + See also:: include/dt-bindings/clock/qcom,sm8550-tcsr.h + +properties: + compatible: + items: + - const: qcom,sm8550-tcsr + - const: syscon + + clocks: + items: + - description: TCXO pad clock + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + +required: + - compatible + - clocks + +additionalProperties: false + +examples: + - | + #include + + clock-controller@1fc0000 { + compatible = "qcom,sm8550-tcsr", "syscon"; + reg = <0x1fc0000 0x30000>; + clocks = <&rpmhcc RPMH_CXO_CLK>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt deleted file mode 100644 index 2632d3f130045ff4523b07f676ed126200cdd4b1..0000000000000000000000000000000000000000 --- a/Documentation/devicetree/bindings/clock/samsung,s3c2410-clock.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Samsung S3C2410 Clock Controller - -The S3C2410 clock controller generates and supplies clock to various controllers -within the SoC. The clock binding described here is applicable to the s3c2410, -s3c2440 and s3c2442 SoCs in the s3c24x family. - -Required Properties: - -- compatible: should be one of the following. - - "samsung,s3c2410-clock" - controller compatible with S3C2410 SoC. - - "samsung,s3c2440-clock" - controller compatible with S3C2440 SoC. - - "samsung,s3c2442-clock" - controller compatible with S3C2442 SoC. -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. Some of the clocks are available only -on a particular SoC. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/s3c2410.h header and can be used in device -tree sources. - -External clocks: - -The xti clock used as input for the plls is generated outside the SoC. It is -expected that is are defined using standard clock bindings with a -clock-output-names value of "xti". - -Example: Clock controller node: - - clocks: clock-controller@4c000000 { - compatible = "samsung,s3c2410-clock"; - reg = <0x4c000000 0x20>; - #clock-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller (refer to the standard clock bindings for information about - "clocks" and "clock-names" properties): - - serial@50004000 { - compatible = "samsung,s3c2440-uart"; - reg = <0x50004000 0x4000>; - interrupts = <1 23 3 4>, <1 23 4 4>; - clock-names = "uart", "clk_uart_baud2"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>; - }; diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c2412-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s3c2412-clock.txt deleted file mode 100644 index 21a8c23e658f3458167124a20a3f700b5a8566b2..0000000000000000000000000000000000000000 --- a/Documentation/devicetree/bindings/clock/samsung,s3c2412-clock.txt +++ /dev/null @@ -1,49 +0,0 @@ -* Samsung S3C2412 Clock Controller - -The S3C2412 clock controller generates and supplies clock to various controllers -within the SoC. The clock binding described here is applicable to the s3c2412 -and s3c2413 SoCs in the s3c24x family. - -Required Properties: - -- compatible: should be "samsung,s3c2412-clock" -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. Some of the clocks are available only -on a particular SoC. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/s3c2412.h header and can be used in device -tree sources. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xti" - crystal input - required, - - "ext" - external clock source - optional, - -Example: Clock controller node: - - clocks: clock-controller@4c000000 { - compatible = "samsung,s3c2412-clock"; - reg = <0x4c000000 0x20>; - #clock-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller (refer to the standard clock bindings for information about - "clocks" and "clock-names" properties): - - serial@50004000 { - compatible = "samsung,s3c2412-uart"; - reg = <0x50004000 0x4000>; - interrupts = <1 23 3 4>, <1 23 4 4>; - clock-names = "uart", "clk_uart_baud2", "clk_uart_baud3"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, - <&clocks SCLK_UART>; - }; diff --git a/Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt b/Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt deleted file mode 100644 index 985c0f574e9a831cbef4a874587eb12c133c7625..0000000000000000000000000000000000000000 --- a/Documentation/devicetree/bindings/clock/samsung,s3c2443-clock.txt +++ /dev/null @@ -1,55 +0,0 @@ -* Samsung S3C2443 Clock Controller - -The S3C2443 clock controller generates and supplies clock to various controllers -within the SoC. The clock binding described here is applicable to all SoCs in -the s3c24x family starting with the s3c2443. - -Required Properties: - -- compatible: should be one of the following. - - "samsung,s3c2416-clock" - controller compatible with S3C2416 SoC. - - "samsung,s3c2443-clock" - controller compatible with S3C2443 SoC. - - "samsung,s3c2450-clock" - controller compatible with S3C2450 SoC. -- reg: physical base address of the controller and length of memory mapped - region. -- #clock-cells: should be 1. - -Each clock is assigned an identifier and client nodes can use this identifier -to specify the clock which they consume. Some of the clocks are available only -on a particular SoC. - -All available clocks are defined as preprocessor macros in -dt-bindings/clock/s3c2443.h header and can be used in device -tree sources. - -External clocks: - -There are several clocks that are generated outside the SoC. It is expected -that they are defined using standard clock bindings with following -clock-output-names: - - "xti" - crystal input - required, - - "ext" - external clock source - optional, - - "ext_i2s" - external I2S clock - optional, - - "ext_uart" - external uart clock - optional, - -Example: Clock controller node: - - clocks: clock-controller@4c000000 { - compatible = "samsung,s3c2416-clock"; - reg = <0x4c000000 0x40>; - #clock-cells = <1>; - }; - -Example: UART controller node that consumes the clock generated by the clock - controller (refer to the standard clock bindings for information about - "clocks" and "clock-names" properties): - - serial@50004000 { - compatible = "samsung,s3c2440-uart"; - reg = <0x50004000 0x4000>; - interrupts = <1 23 3 4>, <1 23 4 4>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, - <&clocks SCLK_UART>; - }; diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index 903b31129f012b1d755ab612e1ec804ca3407f87..e4aa8c67d5327060abba422393c072064dc4b83c 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -26,8 +26,13 @@ properties: items: - enum: - qcom,qdu1000-cpufreq-epss + - qcom,sc7280-cpufreq-epss + - qcom,sc8280xp-cpufreq-epss - qcom,sm6375-cpufreq-epss - qcom,sm8250-cpufreq-epss + - qcom,sm8350-cpufreq-epss + - qcom,sm8450-cpufreq-epss + - qcom,sm8550-cpufreq-epss - const: qcom,cpufreq-epss reg: @@ -54,6 +59,17 @@ properties: - const: xo - const: alternate + interrupts: + minItems: 1 + maxItems: 3 + + interrupt-names: + minItems: 1 + items: + - const: dcvsh-irq-0 + - const: dcvsh-irq-1 + - const: dcvsh-irq-2 + '#freq-domain-cells': const: 1 diff --git a/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml index 9c086eac6ca71ebcf0e7128e2a51bc2ff943a355..6f5e7904181f1d31309f78fbfbebf4ba4c65a1c5 100644 --- a/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml +++ b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml @@ -17,6 +17,9 @@ description: | on the CPU OPP in use. The CPUFreq driver sets the CPR power domain level according to the required OPPs defined in the CPU OPP tables. + For old implementation efuses are parsed to select the correct opp table and + voltage and CPR is not supported/used. + select: properties: compatible: @@ -33,37 +36,65 @@ select: required: - compatible -properties: - cpus: - type: object - - patternProperties: - '^cpu@[0-9a-f]+$': - type: object - - properties: - power-domains: - maxItems: 1 - - power-domain-names: - items: - - const: cpr - - required: - - power-domains - - power-domain-names - patternProperties: '^opp-table(-[a-z0-9]+)?$': - if: + allOf: + - if: + properties: + compatible: + const: operating-points-v2-kryo-cpu + then: + $ref: /schemas/opp/opp-v2-kryo-cpu.yaml# + + - if: + properties: + compatible: + const: operating-points-v2-qcom-level + then: + $ref: /schemas/opp/opp-v2-qcom-level.yaml# + + unevaluatedProperties: false + +allOf: + - if: properties: compatible: - const: operating-points-v2-kryo-cpu + contains: + enum: + - qcom,qcs404 + then: + properties: + cpus: + type: object + + patternProperties: + '^cpu@[0-9a-f]+$': + type: object + + properties: + power-domains: + maxItems: 1 + + power-domain-names: + items: + - const: cpr + + required: + - power-domains + - power-domain-names + patternProperties: - '^opp-?[0-9]+$': - required: - - required-opps + '^opp-table(-[a-z0-9]+)?$': + if: + properties: + compatible: + const: operating-points-v2-kryo-cpu + then: + patternProperties: + '^opp-?[0-9]+$': + required: + - required-opps additionalProperties: true diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml index 0ccaab16dc614ea6c72cd67279b945ed8a117b41..0b7383b3106b51aa937bb25f569d78a5bea474d7 100644 --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-aes.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Atmel Advanced Encryption Standard (AES) HW cryptographic accelerator maintainers: - - Tudor Ambarus + - Tudor Ambarus properties: compatible: diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml index 5163c51b4547b512f9aace6777d7d4be5ce7fec7..ee2ffb0343251f5a2ce7c4d94286ae898db43baa 100644 --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-sha.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Atmel Secure Hash Algorithm (SHA) HW cryptographic accelerator maintainers: - - Tudor Ambarus + - Tudor Ambarus properties: compatible: diff --git a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml index fcc5adf03cadba45800bc1082f5e51a20adddadb..3d6ed24b1b006480d9e4d86793078b9a5422eb72 100644 --- a/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml +++ b/Documentation/devicetree/bindings/crypto/atmel,at91sam9g46-tdes.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Atmel Triple Data Encryption Standard (TDES) HW cryptographic accelerator maintainers: - - Tudor Ambarus + - Tudor Ambarus properties: compatible: diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index f2c143730a551fe8b6f68dd35fc18a3c6a633b22..6e2fd6e9fa7f0aec445c2d04dfecc892d1806dfc 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -32,7 +32,7 @@ properties: - description: Display byte clock - description: Display byte interface clock - description: Display pixel clock - - description: Display escape clock + - description: Display core clock - description: Display AHB clock - description: Display AXI clock @@ -137,8 +137,6 @@ required: - phys - assigned-clocks - assigned-clock-parents - - power-domains - - operating-points-v2 - ports additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml index d9ad8b659f58ee0f5bf3b64b696beb64914c9609..3ec466c3ab38bfe31588b5154a675dd5af5126b3 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-10nm.yaml @@ -69,7 +69,6 @@ required: - compatible - reg - reg-names - - vdds-supply unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml index 819de5ce0bc9170b8949f21724172da863ced56a..a43e11d3b00d2cfe74b24187114415336d876b2e 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-14nm.yaml @@ -39,7 +39,6 @@ required: - compatible - reg - reg-names - - vcca-supply unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml index 3d8540a06fe22a4865f9d45b2bcc3b8e009a646f..2f1fd140c87df95ec60fe37614b724e97ba3395c 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml @@ -34,6 +34,10 @@ properties: vddio-supply: description: Phandle to vdd-io regulator device node. + qcom,dsi-phy-regulator-ldo-mode: + type: boolean + description: Indicates if the LDO mode PHY regulator is wanted. + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml index d6f043a4b08d2dbf86108d15168510dacd78e4f3..4795e13c7b597baaffa5a30db4df769bc51a3cfd 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,qcm2290-mdss.yaml @@ -72,7 +72,7 @@ examples: #include #include - mdss@5e00000 { + display-subsystem@5e00000 { #address-cells = <1>; #size-cells = <1>; compatible = "qcom,qcm2290-mdss"; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml index a86d7f53fa84dfcf2c8fe12d12c38a7c5d07757e..886858ef67000537e05e031650dfd897eb9311cc 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm6115-mdss.yaml @@ -62,7 +62,7 @@ examples: #include #include - mdss@5e00000 { + display-subsystem@5e00000 { #address-cells = <1>; #size-cells = <1>; compatible = "qcom,sm6115-mdss"; diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml index ce5c673f940caefee159e0fff5588e9ad3d08f8e..117c371ce24b39a613e33e1646c6def59c48d9b1 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra186-display.yaml @@ -20,10 +20,10 @@ properties: - nvidia,tegra194-display '#address-cells': - const: 1 + enum: [ 1, 2 ] '#size-cells': - const: 1 + enum: [ 1, 2 ] reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/i2c/renesas,rzv2m.yaml b/Documentation/devicetree/bindings/i2c/renesas,rzv2m.yaml index c46378efc12399dda5b85ce961cfe8ea53453868..92e899905ef88915179a3a92d604cbc3149e8e51 100644 --- a/Documentation/devicetree/bindings/i2c/renesas,rzv2m.yaml +++ b/Documentation/devicetree/bindings/i2c/renesas,rzv2m.yaml @@ -16,7 +16,7 @@ properties: compatible: items: - enum: - - renesas,i2c-r9a09g011 # RZ/V2M + - renesas,r9a09g011-i2c # RZ/V2M - const: renesas,rzv2m-i2c reg: @@ -66,7 +66,7 @@ examples: #include i2c0: i2c@a4030000 { - compatible = "renesas,i2c-r9a09g011", "renesas,rzv2m-i2c"; + compatible = "renesas,r9a09g011-i2c", "renesas,rzv2m-i2c"; reg = <0xa4030000 0x80>; interrupts = , ; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,qdu1000-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,qdu1000-rpmh.yaml new file mode 100644 index 0000000000000000000000000000000000000000..0070b0396e317628174f1569de0682873d07e24e --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,qdu1000-rpmh.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,qdu1000-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on QDU1000 + +maintainers: + - Georgi Djakov + - Odelu Kukatla + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + +properties: + compatible: + enum: + - qcom,qdu1000-clk-virt + - qcom,qdu1000-gem-noc + - qcom,qdu1000-mc-virt + - qcom,qdu1000-system-noc + + '#interconnect-cells': true + + reg: + maxItems: 1 + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,qdu1000-clk-virt + - qcom,qdu1000-mc-virt + then: + properties: + reg: false + else: + required: + - reg + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + + system_noc: interconnect@1640000 { + compatible = "qcom,qdu1000-system-noc"; + reg = <0x1640000 0x45080>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + clk_virt: interconnect-0 { + compatible = "qcom,qdu1000-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml index 4b37aa88a375b12ebffd09f43e6539a61cfb9c65..5e6be4e79201eeb09903ea8a1af78ffab305f44f 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,rpm.yaml @@ -84,7 +84,6 @@ allOf: - qcom,msm8939-pcnoc - qcom,msm8939-snoc - qcom,msm8996-a1noc - - qcom,msm8996-a2noc - qcom,msm8996-bimc - qcom,msm8996-cnoc - qcom,msm8996-pnoc @@ -186,6 +185,29 @@ allOf: required: - power-domains + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8996-a2noc + + then: + properties: + clock-names: + items: + - const: bus + - const: bus_a + - const: aggre2_ufs_axi + - const: ufs_axi + + clocks: + items: + - description: Bus Clock + - description: Bus A Clock + - description: Aggregate2 NoC UFS AXI Clock + - description: UFS AXI Clock + - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sm8550-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sm8550-rpmh.yaml new file mode 100644 index 0000000000000000000000000000000000000000..716bd21f6041404522d17c232c301cfa49eca042 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,sm8550-rpmh.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,sm8550-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on SM8550 + +maintainers: + - Abel Vesa + - Neil Armstrong + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + + See also:: include/dt-bindings/interconnect/qcom,sm8550-rpmh.h + +properties: + compatible: + enum: + - qcom,sm8550-aggre1-noc + - qcom,sm8550-aggre2-noc + - qcom,sm8550-clk-virt + - qcom,sm8550-cnoc-main + - qcom,sm8550-config-noc + - qcom,sm8550-gem-noc + - qcom,sm8550-lpass-ag-noc + - qcom,sm8550-lpass-lpiaon-noc + - qcom,sm8550-lpass-lpicx-noc + - qcom,sm8550-mc-virt + - qcom,sm8550-mmss-noc + - qcom,sm8550-nsp-noc + - qcom,sm8550-pcie-anoc + - qcom,sm8550-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8550-clk-virt + - qcom,sm8550-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8550-pcie-anoc + then: + properties: + clocks: + items: + - description: aggre-NOC PCIe AXI clock + - description: cfg-NOC PCIe a-NOC AHB clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8550-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB3 PRIM AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8550-aggre2-noc + then: + properties: + clocks: + items: + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,sm8550-aggre1-noc + - qcom,sm8550-aggre2-noc + - qcom,sm8550-pcie-anoc + then: + required: + - clocks + else: + properties: + clocks: false + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + + clk_virt: interconnect-0 { + compatible = "qcom,sm8550-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc: interconnect@16e0000 { + compatible = "qcom,sm8550-aggre1-noc"; + reg = <0x016e0000 0x14400>; + #interconnect-cells = <2>; + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml index 9f7d3e11aacb8aa377f05a7a08666a12a81b54e2..8449e14af9f3580fae820a1efd31f713d58af297 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml @@ -108,7 +108,7 @@ properties: msi-controller: description: - Only present if the Message Based Interrupt functionnality is + Only present if the Message Based Interrupt functionality is being exposed by the HW, and the mbi-ranges property present. mbi-ranges: diff --git a/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt b/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt deleted file mode 100644 index c54c5a9a2a9085935096b502f606d40acebaa9c7..0000000000000000000000000000000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/samsung,s3c24xx-irq.txt +++ /dev/null @@ -1,53 +0,0 @@ -Samsung S3C24XX Interrupt Controllers - -The S3C24XX SoCs contain a custom set of interrupt controllers providing a -varying number of interrupt sources. The set consists of a main- and sub- -controller and on newer SoCs even a second main controller. - -Required properties: -- compatible: Compatible property value should be "samsung,s3c2410-irq" - for machines before s3c2416 and "samsung,s3c2416-irq" for s3c2416 and later. - -- reg: Physical base address of the controller and length of memory mapped - region. - -- interrupt-controller : Identifies the node as an interrupt controller - -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value shall be 4 and interrupt descriptor shall - have the following format: - - - ctrl_num contains the controller to use: - - 0 ... main controller - - 1 ... sub controller - - 2 ... second main controller on s3c2416 and s3c2450 - parent_irq contains the parent bit in the main controller and will be - ignored in main controllers - ctrl_irq contains the interrupt bit of the controller - type contains the trigger type to use - -Example: - - interrupt-controller@4a000000 { - compatible = "samsung,s3c2410-irq"; - reg = <0x4a000000 0x100>; - interrupt-controller; - #interrupt-cells=<4>; - }; - - [...] - - serial@50000000 { - compatible = "samsung,s3c2410-uart"; - reg = <0x50000000 0x4000>; - interrupt-parent = <&subintc>; - interrupts = <1 28 0 4>, <1 28 1 4>; - }; - - rtc@57000000 { - compatible = "samsung,s3c2410-rtc"; - reg = <0x57000000 0x100>; - interrupt-parent = <&intc>; - interrupts = <0 30 0 3>, <0 8 0 3>; - }; diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml new file mode 100644 index 0000000000000000000000000000000000000000..ca9fc747bf4feb7adf701ab98d19c2c8c798dfe6 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Zynqmp OCM(On-Chip Memory) Controller + +maintainers: + - Shubhrajyoti Datta + - Sai Krishna Potthuri + +description: | + The OCM supports 64-bit wide ECC functionality to detect multi-bit errors + and recover from a single-bit memory fault.On a write, if all bytes are + being written, the ECC is generated and written into the ECC RAM along with + the write-data that is written into the data RAM. If one or more bytes are + not written, then the read operation results in an correctable error or + uncorrectable error. + +properties: + compatible: + const: xlnx,zynqmp-ocmc-1.0 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + memory-controller@ff960000 { + compatible = "xlnx,zynqmp-ocmc-1.0"; + reg = <0xff960000 0x1000>; + interrupts = ; + }; diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 1b01bd01043161821fd58f1db414d8a39d003fb2..b73ba1ea08f7d426548f83044b3d1159f1274813 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -64,12 +64,6 @@ properties: - rockchip,rk3568-qos - rockchip,rk3588-qos - rockchip,rv1126-qos - - samsung,exynos3-sysreg - - samsung,exynos4-sysreg - - samsung,exynos5-sysreg - - samsung,exynos5433-sysreg - - samsung,exynos850-sysreg - - samsung,exynosautov9-sysreg - const: syscon diff --git a/Documentation/devicetree/bindings/mmc/samsung,s3cmci.txt b/Documentation/devicetree/bindings/mmc/samsung,s3cmci.txt deleted file mode 100644 index 5f68feb9f9d61f2bd0cadfe38e8b5cd6d834cbec..0000000000000000000000000000000000000000 --- a/Documentation/devicetree/bindings/mmc/samsung,s3cmci.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Samsung's S3C24XX MMC/SD/SDIO controller device tree bindings - -Samsung's S3C24XX MMC/SD/SDIO controller is used as a connectivity interface -with external MMC, SD and SDIO storage mediums. - -This file documents differences between the core mmc properties described by -mmc.txt and the properties used by the Samsung S3C24XX MMC/SD/SDIO controller -implementation. - -Required SoC Specific Properties: -- compatible: should be one of the following - - "samsung,s3c2410-sdi": for controllers compatible with s3c2410 - - "samsung,s3c2412-sdi": for controllers compatible with s3c2412 - - "samsung,s3c2440-sdi": for controllers compatible with s3c2440 -- reg: register location and length -- interrupts: mmc controller interrupt -- clocks: Should reference the controller clock -- clock-names: Should contain "sdi" - -Required Board Specific Properties: -- pinctrl-0: Should specify pin control groups used for this controller. -- pinctrl-names: Should contain only one value - "default". - -Optional Properties: -- bus-width: number of data lines (see mmc.txt) -- cd-gpios: gpio for card detection (see mmc.txt) -- wp-gpios: gpio for write protection (see mmc.txt) - -Example: - - mmc0: mmc@5a000000 { - compatible = "samsung,s3c2440-sdi"; - pinctrl-names = "default"; - pinctrl-0 = <&sdi_pins>; - reg = <0x5a000000 0x100000>; - interrupts = <0 0 21 3>; - clocks = <&clocks PCLK_SDI>; - clock-names = "sdi"; - bus-width = <4>; - cd-gpios = <&gpg 8 GPIO_ACTIVE_LOW>; - wp-gpios = <&gph 8 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml index 1432fda3b603f74e11d287f8a29d7bf03a042e79..47bc2057e6292a829dc25b2ef5e2f70ea6a3efa8 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -40,6 +40,9 @@ properties: clock-names: const: stmmaceth + phy-supply: + description: PHY regulator + syscon: $ref: /schemas/types.yaml#/definitions/phandle description: diff --git a/Documentation/devicetree/bindings/net/marvell,orion-mdio.yaml b/Documentation/devicetree/bindings/net/marvell,orion-mdio.yaml index d2906b4a0f5957bb13b20554a6e404ecd4ed489b..e35da8b01dc257f9d5a96fcad1807ae5ea3df06e 100644 --- a/Documentation/devicetree/bindings/net/marvell,orion-mdio.yaml +++ b/Documentation/devicetree/bindings/net/marvell,orion-mdio.yaml @@ -16,9 +16,6 @@ description: | 8k has a second unit which provides an interface with the xMDIO bus. This driver handles these interfaces. -allOf: - - $ref: "mdio.yaml#" - properties: compatible: enum: @@ -39,13 +36,38 @@ required: - compatible - reg +allOf: + - $ref: mdio.yaml# + + - if: + required: + - interrupts + + then: + properties: + reg: + items: + - items: + - $ref: /schemas/types.yaml#/definitions/cell + - const: 0x84 + + else: + properties: + reg: + items: + - items: + - $ref: /schemas/types.yaml#/definitions/cell + - enum: + - 0x4 + - 0x10 + unevaluatedProperties: false examples: - | mdio@d0072004 { compatible = "marvell,orion-mdio"; - reg = <0xd0072004 0x4>; + reg = <0xd0072004 0x84>; #address-cells = <1>; #size-cells = <0>; interrupts = <30>; diff --git a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml index 60cf3cbde4c5b5bc5fff2887577340bf606d470e..bbbad31ae4caf84cd354840a481af03c0b36db2e 100644 --- a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml @@ -50,12 +50,22 @@ patternProperties: opp-supported-hw: description: | A single 32 bit bitmap value, representing compatible HW. - Bitmap: + Bitmap for MSM8996 format: 0: MSM8996, speedbin 0 1: MSM8996, speedbin 1 2: MSM8996, speedbin 2 - 3-31: unused - maximum: 0x7 + 3: MSM8996, speedbin 3 + 4-31: unused + + Bitmap for MSM8996SG format (speedbin shifted of 4 left): + 0-3: unused + 4: MSM8996SG, speedbin 0 + 5: MSM8996SG, speedbin 1 + 6: MSM8996SG, speedbin 2 + 7-31: unused + enum: [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, + 0x9, 0xd, 0xe, 0xf, + 0x10, 0x20, 0x30, 0x70] clock-latency-ns: true @@ -106,6 +116,7 @@ examples: L2_0: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; @@ -140,6 +151,7 @@ examples: L2_1: l2-cache { compatible = "cache"; cache-level = <2>; + cache-unified; }; }; diff --git a/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml b/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml index b9ce2e099ce9a953622358d96f8ca97042d44d35..a30ef93213c0990f4a4ab993f546ee140958ba47 100644 --- a/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml @@ -30,7 +30,9 @@ patternProperties: this OPP node. Sometimes several corners/levels shares a certain fuse corner/level. A fuse corner/level contains e.g. ref uV, min uV, and max uV. - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 required: - opp-level diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,g12a-usb2-phy.yaml similarity index 85% rename from Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml rename to Documentation/devicetree/bindings/phy/amlogic,g12a-usb2-phy.yaml index f3a5fbabbbb5971b343ea6f892a49033dddbf5d0..bb01c6b34dabcb1f5bbbf3ae51aba0fba4027e07 100644 --- a/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/amlogic,g12a-usb2-phy.yaml @@ -2,7 +2,7 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/phy/amlogic,meson-g12a-usb2-phy.yaml#" +$id: "http://devicetree.org/schemas/phy/amlogic,g12a-usb2-phy.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: Amlogic G12A USB2 PHY @@ -13,8 +13,8 @@ maintainers: properties: compatible: enum: - - amlogic,meson-g12a-usb2-phy - - amlogic,meson-a1-usb2-phy + - amlogic,g12a-usb2-phy + - amlogic,a1-usb2-phy reg: maxItems: 1 @@ -68,7 +68,7 @@ additionalProperties: false examples: - | phy@36000 { - compatible = "amlogic,meson-g12a-usb2-phy"; + compatible = "amlogic,g12a-usb2-phy"; reg = <0x36000 0x2000>; clocks = <&xtal>; clock-names = "xtal"; diff --git a/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/amlogic,g12a-usb3-pcie-phy.yaml similarity index 82% rename from Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml rename to Documentation/devicetree/bindings/phy/amlogic,g12a-usb3-pcie-phy.yaml index 868b4e6fde71f1fb68d49b9ce8f73fc5176a12e6..129d26e99776b6e730dbfe23cf8e742b6de9a9a6 100644 --- a/Documentation/devicetree/bindings/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/amlogic,g12a-usb3-pcie-phy.yaml @@ -2,7 +2,7 @@ # Copyright 2019 BayLibre, SAS %YAML 1.2 --- -$id: "http://devicetree.org/schemas/phy/amlogic,meson-g12a-usb3-pcie-phy.yaml#" +$id: "http://devicetree.org/schemas/phy/amlogic,g12a-usb3-pcie-phy.yaml#" $schema: "http://devicetree.org/meta-schemas/core.yaml#" title: Amlogic G12A USB3 + PCIE Combo PHY @@ -13,7 +13,7 @@ maintainers: properties: compatible: enum: - - amlogic,meson-g12a-usb3-pcie-phy + - amlogic,g12a-usb3-pcie-phy reg: maxItems: 1 @@ -49,7 +49,7 @@ additionalProperties: false examples: - | phy@46000 { - compatible = "amlogic,meson-g12a-usb3-pcie-phy"; + compatible = "amlogic,g12a-usb3-pcie-phy"; reg = <0x46000 0x2000>; clocks = <&ref_clk>; clock-names = "ref_clk"; diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml index abcc4373f39e1898244abeca9f7308f4de357d51..ca6a0836b53c4168e29830b1a5591cfc9453ed70 100644 --- a/Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml @@ -16,7 +16,6 @@ properties: compatible: enum: - qcom,usb-hs-28nm-femtophy - - qcom,usb-hs-28nm-mdm9607 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml similarity index 98% rename from Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml rename to Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml index f71920082fa3e6a09673ba08ad761c9bf5ea0ebf..0d6b8c28be07103639bee941ed8ce1cd67635cc3 100644 --- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 %YAML 1.2 --- -$id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml# +$id: http://devicetree.org/schemas/phy/rockchip,inno-usb2phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Rockchip USB2.0 phy with inno IP block diff --git a/Documentation/devicetree/bindings/phy/rockchip,rk3288-dp-phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,rk3288-dp-phy.yaml new file mode 100644 index 0000000000000000000000000000000000000000..2538235c5ac62137598218e491b464530483761d --- /dev/null +++ b/Documentation/devicetree/bindings/phy/rockchip,rk3288-dp-phy.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/rockchip,rk3288-dp-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip specific extensions to the Analogix Display Port PHY + +maintainers: + - Heiko Stuebner + +properties: + compatible: + const: rockchip,rk3288-dp-phy + + clocks: + maxItems: 1 + + clock-names: + const: 24m + + "#phy-cells": + const: 0 + +required: + - compatible + - clocks + - clock-names + - "#phy-cells" + +additionalProperties: false + +examples: + - | + #include + edp-phy { + compatible = "rockchip,rk3288-dp-phy"; + clocks = <&cru SCLK_EDP_24M>; + clock-names = "24m"; + #phy-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt b/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt deleted file mode 100644 index e3b4809fbe82c4798b7e5bef55e666505d6df527..0000000000000000000000000000000000000000 --- a/Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt +++ /dev/null @@ -1,26 +0,0 @@ -Rockchip specific extensions to the Analogix Display Port PHY ------------------------------------- - -Required properties: -- compatible : should be one of the following supported values: - - "rockchip.rk3288-dp-phy" -- clocks: from common clock binding: handle to dp clock. - of memory mapped region. -- clock-names: from common clock binding: - Required elements: "24m" -- #phy-cells : from the generic PHY bindings, must be 0; - -Example: - -grf: syscon@ff770000 { - compatible = "rockchip,rk3288-grf", "syscon", "simple-mfd"; - -... - - edp_phy: edp-phy { - compatible = "rockchip,rk3288-dp-phy"; - clocks = <&cru SCLK_EDP_24M>; - clock-names = "24m"; - #phy-cells = <0>; - }; -}; diff --git a/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml b/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml index 777e1d852dddb525b9fce3415349a5f8d88a8f94..c21a66422d4feef60f56b62824543bd7eb397be2 100644 --- a/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml +++ b/Documentation/devicetree/bindings/power/fsl,imx-gpc.yaml @@ -23,11 +23,16 @@ description: | properties: compatible: - enum: - - fsl,imx6q-gpc - - fsl,imx6qp-gpc - - fsl,imx6sl-gpc - - fsl,imx6sx-gpc + oneOf: + - enum: + - fsl,imx6q-gpc + - items: + - enum: + - fsl,imx6qp-gpc + - fsl,imx6sl-gpc + - fsl,imx6sx-gpc + - fsl,imx6ul-gpc + - const: fsl,imx6q-gpc reg: maxItems: 1 @@ -35,6 +40,10 @@ properties: interrupts: maxItems: 1 + interrupt-controller: true + '#interrupt-cells': + const: 3 + clocks: maxItems: 1 diff --git a/Documentation/devicetree/bindings/regulator/samsung,s2mps14.yaml b/Documentation/devicetree/bindings/regulator/samsung,s2mps14.yaml index 01f9d4e236e94901e9eb6e7f2d731d00c06cb77a..a7feb497eb89bdc278b4c315df1aa8f499a8bf41 100644 --- a/Documentation/devicetree/bindings/regulator/samsung,s2mps14.yaml +++ b/Documentation/devicetree/bindings/regulator/samsung,s2mps14.yaml @@ -19,8 +19,8 @@ description: | additional information and example. patternProperties: - # 25 LDOs - "^LDO([1-9]|[1][0-9]|2[0-5])$": + # 25 LDOs, without LDO10-12 + "^LDO([1-9]|1[3-9]|2[0-5])$": type: object $ref: regulator.yaml# unevaluatedProperties: false @@ -30,6 +30,23 @@ patternProperties: required: - regulator-name + "^LDO(1[0-2])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator. + + properties: + samsung,ext-control-gpios: + maxItems: 1 + description: + LDO10, LDO11 and LDO12 can be configured to external control over + GPIO. + + required: + - regulator-name + # 5 bucks "^BUCK[1-5]$": type: object diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index c6720764e765c70af73cc0dffc6e837888c74a19..a2884e3113daded85e13b8a218b472bf5c61cf80 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -83,7 +83,7 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ + pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 714d0fcab39964d1ed7cad0756c8d41eb091adfa..4a29c890619ab86cc96f910ef145ce9facad62b3 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -27,6 +27,7 @@ properties: - items: - enum: + - aldec,tysom-m-mpfs250t-rev2 - aries,m100pfsevp - microchip,mpfs-sev-kit - sundance,polarberry diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml index 5d3fcee52d59665f483c05ce2f955a088ab8cce2..cc4d92f0a1bf8233879c9f9fc89aab78b43315ba 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -24,6 +24,12 @@ properties: - starfive,visionfive-v1 - const: starfive,jh7100 + - items: + - enum: + - starfive,visionfive-2-v1.2a + - starfive,visionfive-2-v1.3b + - const: starfive,jh7110 + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/riscv/sunxi.yaml b/Documentation/devicetree/bindings/riscv/sunxi.yaml new file mode 100644 index 0000000000000000000000000000000000000000..9edb5e5992b19585ec350a11cadef3e6bd82ea9c --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/sunxi.yaml @@ -0,0 +1,69 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/sunxi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Allwinner RISC-V SoC-based boards + +maintainers: + - Chen-Yu Tsai + - Jernej Skrabec + - Samuel Holland + +description: + Allwinner RISC-V SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Dongshan Nezha STU SoM + items: + - const: 100ask,dongshan-nezha-stu + - const: allwinner,sun20i-d1 + + - description: D1 Nezha board + items: + - const: allwinner,d1-nezha + - const: allwinner,sun20i-d1 + + - description: ClockworkPi R-01 SoM and v3.14 board + items: + - const: clockwork,r-01-clockworkpi-v3.14 + - const: allwinner,sun20i-d1 + + - description: ClockworkPi R-01 SoM, v3.14 board, and DevTerm expansion + items: + - const: clockwork,r-01-devterm-v3.14 + - const: clockwork,r-01-clockworkpi-v3.14 + - const: allwinner,sun20i-d1 + + - description: Lichee RV SoM + items: + - const: sipeed,lichee-rv + - const: allwinner,sun20i-d1 + + - description: Carrier boards for the Lichee RV SoM + items: + - enum: + - sipeed,lichee-rv-86-panel-480p + - sipeed,lichee-rv-86-panel-720p + - sipeed,lichee-rv-dock + - const: sipeed,lichee-rv + - const: allwinner,sun20i-d1 + + - description: MangoPi MQ board + items: + - const: widora,mangopi-mq + - const: allwinner,sun20i-d1s + + - description: MangoPi MQ Pro board + items: + - const: widora,mangopi-mq-pro + - const: allwinner,sun20i-d1 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml b/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml index 0a7aa29563c1c86d90aa31425beb4ba27963fc23..21c8ea08ff0a226c5d6a5d71dc4f3c64eb95f5b7 100644 --- a/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/qcom-pm8xxx-rtc.yaml @@ -40,6 +40,8 @@ properties: description: Indicates that the setting of RTC time is allowed by the host CPU. + wakeup-source: true + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml new file mode 100644 index 0000000000000000000000000000000000000000..1da1b758b4ae50adc22e25cdfc51d2b111493c57 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/imx/fsl,imx-iomuxc-gpr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale IOMUX Controller General Purpose Registers + +maintainers: + - Peng Fan + +description: + i.MX Processors have an IOMUXC General Purpose Register group for + various System Settings + +properties: + compatible: + oneOf: + - items: + - const: fsl,imx8mq-iomuxc-gpr + - const: syscon + - const: simple-mfd + - items: + - enum: + - fsl,imx8mm-iomuxc-gpr + - fsl,imx8mn-iomuxc-gpr + - fsl,imx8mp-iomuxc-gpr + - const: syscon + + reg: + maxItems: 1 + + mux-controller: + type: object + $ref: /schemas/mux/reg-mux.yaml + +additionalProperties: false + +required: + - compatible + - reg + +examples: + # Pinmux controller node + - | + iomuxc_gpr: syscon@30340000 { + compatible = "fsl,imx8mq-iomuxc-gpr", "syscon", "simple-mfd"; + reg = <0x30340000 0x10000>; + + mux: mux-controller { + compatible = "mmio-mux"; + #mux-control-cells = <1>; + mux-reg-masks = <0x34 0x00000004>; /* MIPI_MUX_SEL */ + }; + }; + +... diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml index c29181a9745b96ac4fc3ed8282d41aeb6ba9bcd1..1fe68b53b1d83c6983cac39fe6acc208868e0ef0 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx8mp-hsio-blk-ctrl.yaml @@ -39,6 +39,9 @@ properties: - const: pcie - const: pcie-phy + '#clock-cells': + const: 0 + clocks: minItems: 2 maxItems: 2 @@ -85,4 +88,5 @@ examples: power-domain-names = "bus", "usb", "usb-phy1", "usb-phy2", "pcie", "pcie-phy"; #power-domain-cells = <1>; + #clock-cells = <0>; }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,apr-services.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,apr-services.yaml index 290555426c39ca90ebeb087cce514f51c4cc92ff..bdf482db32aac1fc84f42aa9b72cf6d64c798933 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,apr-services.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,apr-services.yaml @@ -39,8 +39,8 @@ properties: qcom,protection-domain: $ref: /schemas/types.yaml#/definitions/string-array description: | - Protection domain service name and path for APR service - possible values are:: + Protection domain service name and path for APR service (if supported). + Possible values are:: "avs/audio", "msm/adsp/audio_pd". "kernel/elf_loader", "msm/modem/wlan_pd". "tms/servreg", "msm/adsp/audio_pd". @@ -49,6 +49,5 @@ properties: required: - reg - - qcom,protection-domain additionalProperties: true diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,rzv2m-pwc.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,rzv2m-pwc.yaml new file mode 100644 index 0000000000000000000000000000000000000000..12df33f5848434f9dcf2dff0107539639326d9fe --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,rzv2m-pwc.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas,rzv2m-pwc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/V2M External Power Sequence Controller (PWC) + +description: |+ + The PWC IP found in the RZ/V2M family of chips comes with the below + capabilities + - external power supply on/off sequence generation + - on/off signal generation for the LPDDR4 core power supply (LPVDD) + - key input signals processing + - general-purpose output pins + +maintainers: + - Fabrizio Castro + +properties: + compatible: + items: + - enum: + - renesas,r9a09g011-pwc # RZ/V2M + - renesas,r9a09g055-pwc # RZ/V2MA + - const: renesas,rzv2m-pwc + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + renesas,rzv2m-pwc-power: + description: The PWC is used to control the system power supplies. + type: boolean + +required: + - compatible + - reg + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + pwc: pwc@a3700000 { + compatible = "renesas,r9a09g011-pwc", "renesas,rzv2m-pwc"; + reg = <0xa3700000 0x800>; + gpio-controller; + #gpio-cells = <2>; + renesas,rzv2m-pwc-power; + }; diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 2ed8cca79b59cb89dc5050ceb6897ac0dddbf2ea..e697c928900d6860d803e985df6901fc9ac02f46 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -20,6 +20,11 @@ properties: - rockchip,rk3568-pipe-grf - rockchip,rk3568-pipe-phy-grf - rockchip,rk3568-usb2phy-grf + - rockchip,rk3588-bigcore0-grf + - rockchip,rk3588-bigcore1-grf + - rockchip,rk3588-ioc + - rockchip,rk3588-php-grf + - rockchip,rk3588-sys-grf - rockchip,rk3588-pcie3-phy-grf - rockchip,rk3588-pcie3-pipe-grf - rockchip,rv1108-usbgrf @@ -92,8 +97,9 @@ allOf: then: properties: edp-phy: - description: - Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt + type: object + $ref: /schemas/phy/rockchip,rk3288-dp-phy.yaml# + unevaluatedProperties: false - if: properties: @@ -200,7 +206,7 @@ allOf: "usb2phy@[0-9a-f]+$": type: object - $ref: "/schemas/phy/phy-rockchip-inno-usb2.yaml#" + $ref: /schemas/phy/rockchip,inno-usb2phy.yaml# unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml index 13bb8dfcefe6eaf5308403c2b3c4bdc429a1fc49..f7c141dd11ecb835cfe61640a7764edd73e8fe7a 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-pmu.yaml @@ -31,20 +31,28 @@ select: properties: compatible: - items: - - enum: - - samsung,exynos3250-pmu - - samsung,exynos4210-pmu - - samsung,exynos4412-pmu - - samsung,exynos5250-pmu - - samsung,exynos5260-pmu - - samsung,exynos5410-pmu - - samsung,exynos5420-pmu - - samsung,exynos5433-pmu - - samsung,exynos7-pmu - - samsung,exynos850-pmu - - samsung-s5pv210-pmu - - const: syscon + oneOf: + - items: + - enum: + - samsung,exynos3250-pmu + - samsung,exynos4210-pmu + - samsung,exynos4412-pmu + - samsung,exynos5250-pmu + - samsung,exynos5260-pmu + - samsung,exynos5410-pmu + - samsung,exynos5420-pmu + - samsung,exynos5433-pmu + - samsung,exynos7-pmu + - samsung,exynos850-pmu + - samsung-s5pv210-pmu + - const: syscon + - items: + - enum: + - samsung,exynos5250-pmu + - samsung,exynos5420-pmu + - samsung,exynos5433-pmu + - const: simple-mfd + - const: syscon reg: maxItems: 1 @@ -64,6 +72,10 @@ properties: minItems: 1 maxItems: 32 + dp-phy: + $ref: /schemas/phy/samsung,dp-video-phy.yaml + unevaluatedProperties: false + interrupt-controller: description: Some PMUs are capable of behaving as an interrupt controller (mostly @@ -74,6 +86,10 @@ properties: Must be identical to the that of the parent interrupt controller. const: 3 + mipi-phy: + $ref: /schemas/phy/samsung,mipi-video-phy.yaml + unevaluatedProperties: false + reboot-mode: $ref: /schemas/power/reset/syscon-reboot-mode.yaml type: object @@ -117,6 +133,23 @@ allOf: - clock-names - clocks + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos5250-pmu + - samsung,exynos5420-pmu + - samsung,exynos5433-pmu + then: + properties: + dp-phy: true + mipi-phy: true + else: + properties: + dp-phy: false + mipi-phy: false + examples: - | #include @@ -130,4 +163,14 @@ examples: #clock-cells = <1>; clock-names = "clkout16"; clocks = <&clock CLK_FIN_PLL>; + + dp-phy { + compatible = "samsung,exynos5250-dp-video-phy"; + #phy-cells = <0>; + }; + + mipi-phy { + compatible = "samsung,s5pv210-mipi-video-phy"; + #phy-cells = <1>; + }; }; diff --git a/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml new file mode 100644 index 0000000000000000000000000000000000000000..163e912e9cadcdfb5825803ba2693c844a6e50fe --- /dev/null +++ b/Documentation/devicetree/bindings/soc/samsung/samsung,exynos-sysreg.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/samsung/samsung,exynos-sysreg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos SoC series System Registers (SYSREG) + +maintainers: + - Krzysztof Kozlowski + +properties: + compatible: + oneOf: + - items: + - enum: + - samsung,exynos3-sysreg + - samsung,exynos4-sysreg + - samsung,exynos5-sysreg + - tesla,fsd-cam-sysreg + - tesla,fsd-fsys0-sysreg + - tesla,fsd-fsys1-sysreg + - tesla,fsd-peric-sysreg + - const: syscon + - items: + - enum: + - samsung,exynos5433-cam0-sysreg + - samsung,exynos5433-cam1-sysreg + - samsung,exynos5433-disp-sysreg + - samsung,exynos5433-fsys-sysreg + - const: samsung,exynos5433-sysreg + - const: syscon + - items: + - enum: + - samsung,exynos5433-sysreg + - samsung,exynos850-sysreg + - samsung,exynosautov9-sysreg + - const: syscon + deprecated: true + - items: + - enum: + - samsung,exynos850-cmgp-sysreg + - samsung,exynos850-peri-sysreg + - const: samsung,exynos850-sysreg + - const: syscon + - items: + - enum: + - samsung,exynosautov9-fsys2-sysreg + - samsung,exynosautov9-peric0-sysreg + - samsung,exynosautov9-peric1-sysreg + - const: samsung,exynosautov9-sysreg + - const: syscon + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,exynos850-cmgp-sysreg + - samsung,exynos850-peri-sysreg + - samsung,exynos850-sysreg + then: + required: + - clocks + else: + properties: + clocks: false + +additionalProperties: false + +examples: + - | + system-controller@10010000 { + compatible = "samsung,exynos4-sysreg", "syscon"; + reg = <0x10010000 0x400>; + }; diff --git a/Documentation/devicetree/bindings/sound/everest,es8326.yaml b/Documentation/devicetree/bindings/sound/everest,es8326.yaml old mode 100755 new mode 100644 diff --git a/Documentation/devicetree/bindings/sound/mt8186-mt6366-rt1019-rt5682s.yaml b/Documentation/devicetree/bindings/sound/mt8186-mt6366-rt1019-rt5682s.yaml index 9d3139990237408ce2ff823cfb9b869cd84d4b56..aa23b0024c461d596f81071a70833daa565c7358 100644 --- a/Documentation/devicetree/bindings/sound/mt8186-mt6366-rt1019-rt5682s.yaml +++ b/Documentation/devicetree/bindings/sound/mt8186-mt6366-rt1019-rt5682s.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - mediatek,mt8186-mt6366-rt1019-rt5682s-sound + - mediatek,mt8186-mt6366-rt5682s-max98360-sound mediatek,platform: $ref: "/schemas/types.yaml#/definitions/phandle" diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml index 89f7805de2741c3238f02a0ca7f0b6f61f55a927..c4abac81f2074791dab0894d7213884533611852 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ahub.yaml @@ -50,10 +50,10 @@ properties: maxItems: 1 "#address-cells": - const: 1 + enum: [ 1, 2 ] "#size-cells": - const: 1 + enum: [ 1, 2 ] ranges: true diff --git a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml index 5fc03b8771b1c79e456d1c790b435815e9a430e9..9017fb6d575d9c069b5981f7f115b204ff5af91c 100644 --- a/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml +++ b/Documentation/devicetree/bindings/sound/nvidia,tegra210-ope.yaml @@ -34,10 +34,10 @@ properties: maxItems: 1 "#address-cells": - const: 1 + enum: [ 1, 2 ] "#size-cells": - const: 1 + enum: [ 1, 2 ] ranges: true diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml index 66431aade3b70a1794bd317af60a9a2cadd8cefd..da5f70910da5204ee0c37bba62f3f7473852983d 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml @@ -30,7 +30,9 @@ properties: const: 0 clocks: - maxItems: 5 + oneOf: + - maxItems: 3 + - maxItems: 5 clock-names: oneOf: diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml index 2bf8d082f8f1044d64bb9493eea892f14b629378..66cbb1f5e31a5cdaf53126972b1f32c4122fed67 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml @@ -9,9 +9,6 @@ title: LPASS(Low Power Audio Subsystem) VA Macro audio codec maintainers: - Srinivas Kandagatla -allOf: - - $ref: dai-common.yaml# - properties: compatible: enum: @@ -30,15 +27,12 @@ properties: const: 0 clocks: - maxItems: 5 + minItems: 5 + maxItems: 6 clock-names: - items: - - const: mclk - - const: npl - - const: macro - - const: dcodec - - const: fsgen + minItems: 5 + maxItems: 6 clock-output-names: maxItems: 1 @@ -55,10 +49,51 @@ required: - reg - "#sound-dai-cells" +allOf: + - $ref: dai-common.yaml# + + - if: + properties: + compatible: + enum: + - qcom,sc7280-lpass-wsa-macro + - qcom,sm8450-lpass-wsa-macro + - qcom,sc8280xp-lpass-wsa-macro + then: + properties: + clocks: + maxItems: 5 + clock-names: + items: + - const: mclk + - const: npl + - const: macro + - const: dcodec + - const: fsgen + + - if: + properties: + compatible: + enum: + - qcom,sm8250-lpass-wsa-macro + then: + properties: + clocks: + minItems: 6 + clock-names: + items: + - const: mclk + - const: npl + - const: macro + - const: dcodec + - const: va + - const: fsgen + unevaluatedProperties: false examples: - | + #include #include codec@3240000 { compatible = "qcom,sm8250-lpass-wsa-macro"; @@ -69,7 +104,8 @@ examples: <&audiocc 0>, <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&aoncc LPASS_CDC_VA_MCLK>, <&vamacro>; - clock-names = "mclk", "npl", "macro", "dcodec", "fsgen"; + clock-names = "mclk", "npl", "macro", "dcodec", "va", "fsgen"; clock-output-names = "mclk"; }; diff --git a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml index bcbfa71536cda602d40e1e6a4a0d3b9bfb468a31..3efdc192ab019182571338fef555dd3a9653c6f7 100644 --- a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml +++ b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml @@ -80,7 +80,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 5 + maxItems: 8 qcom,ports-sinterval-low: $ref: /schemas/types.yaml#/definitions/uint8-array @@ -124,7 +124,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 5 + maxItems: 8 qcom,ports-block-pack-mode: $ref: /schemas/types.yaml#/definitions/uint8-array @@ -154,7 +154,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 5 + maxItems: 8 items: oneOf: - minimum: 0 @@ -171,7 +171,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 5 + maxItems: 8 items: oneOf: - minimum: 0 @@ -187,7 +187,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 5 + maxItems: 8 items: oneOf: - minimum: 0 diff --git a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml index 4dd973e341e6c772a2f6f1d945ce31eb6aab325e..6c57dd6c3a3614d3ed883bff2d1ed2fb20edf483 100644 --- a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml +++ b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml @@ -8,7 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Atmel SPI device maintainers: - - Tudor Ambarus + - Tudor Ambarus allOf: - $ref: spi-controller.yaml# diff --git a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml index 1d493add4053dd11add73e67e0e35ca81a12f16b..b0d99bc105352c5bcae56708896d508b2680850d 100644 --- a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml +++ b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Atmel Quad Serial Peripheral Interface (QSPI) maintainers: - - Tudor Ambarus + - Tudor Ambarus allOf: - $ref: spi-controller.yaml# diff --git a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml index ead2cccf658fdee57208afaa695fabe68668d1a4..9a60c0664bbe7df45fb113c3a314105c2ad5e4c0 100644 --- a/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml +++ b/Documentation/devicetree/bindings/spi/spi-peripheral-props.yaml @@ -44,9 +44,9 @@ properties: description: Maximum SPI clocking speed of the device in Hz. - spi-cs-setup-ns: + spi-cs-setup-delay-ns: description: - Delay in nanosecods to be introduced by the controller after CS is + Delay in nanoseconds to be introduced by the controller after CS is asserted. spi-rx-bus-width: diff --git a/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml new file mode 100644 index 0000000000000000000000000000000000000000..fe9ae4c425c08ab2b534ba74d51a87ebc8b58cdb --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/mediatek,lvts-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SoC Low Voltage Thermal Sensor (LVTS) + +maintainers: + - Balsam CHIHI + +description: | + LVTS is a thermal management architecture composed of three subsystems, + a Sensing device - Thermal Sensing Micro Circuit Unit (TSMCU), + a Converter - Low Voltage Thermal Sensor converter (LVTS), and + a Digital controller (LVTS_CTRL). + +properties: + compatible: + enum: + - mediatek,mt8192-lvts-ap + - mediatek,mt8192-lvts-mcu + - mediatek,mt8195-lvts-ap + - mediatek,mt8195-lvts-mcu + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + description: LVTS reset for clearing temporary data on AP/MCU. + + nvmem-cells: + minItems: 1 + items: + - description: Calibration eFuse data 1 for LVTS + - description: Calibration eFuse data 2 for LVTS + + nvmem-cell-names: + minItems: 1 + items: + - const: lvts-calib-data-1 + - const: lvts-calib-data-2 + + "#thermal-sensor-cells": + const: 1 + +allOf: + - $ref: thermal-sensor.yaml# + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8192-lvts-ap + - mediatek,mt8192-lvts-mcu + then: + properties: + nvmem-cells: + maxItems: 1 + + nvmem-cell-names: + maxItems: 1 + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8195-lvts-ap + - mediatek,mt8195-lvts-mcu + then: + properties: + nvmem-cells: + minItems: 2 + + nvmem-cell-names: + minItems: 2 + +required: + - compatible + - reg + - interrupts + - clocks + - resets + - nvmem-cells + - nvmem-cell-names + - "#thermal-sensor-cells" + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + lvts_mcu: thermal-sensor@11278000 { + compatible = "mediatek,mt8195-lvts-mcu"; + reg = <0 0x11278000 0 0x1000>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; + nvmem-cell-names = "lvts-calib-data-1", "lvts-calib-data-2"; + #thermal-sensor-cells = <1>; + }; + }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; + thermal-sensors = <&lvts_mcu MT8195_MCU_LITTLE_CPU0>; + + trips { + cpu0_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu0_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml index d20569b9b76396c82c7ea0b6905756c6610d71eb..52ec18cf1edaa38e5e774e67e4cce9fcb4ed61e8 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-spmi-adc-tm5.yaml @@ -13,6 +13,7 @@ properties: enum: - qcom,spmi-adc-tm5 - qcom,spmi-adc-tm5-gen2 + - qcom,adc-tm7 # Incomplete / subject to change reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 0231f187b09775bdd7eba1680130439bc4c745a7..926e9c51c93cbd7201e03eac48b89d7306ff1e46 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -37,6 +37,7 @@ properties: - description: v1 of TSENS items: - enum: + - qcom,msm8956-tsens - qcom,msm8976-tsens - qcom,qcs404-tsens - const: qcom,tsens-v1 @@ -80,18 +81,120 @@ properties: maxItems: 2 nvmem-cells: - minItems: 1 - maxItems: 2 - description: - Reference to an nvmem node for the calibration data + oneOf: + - minItems: 1 + maxItems: 2 + description: + Reference to an nvmem node for the calibration data + - minItems: 5 + maxItems: 35 + description: | + Reference to nvmem cells for the calibration mode, two calibration + bases and two cells per each sensor + # special case for msm8974 / apq8084 + - maxItems: 51 + description: | + Reference to nvmem cells for the calibration mode, two calibration + bases and two cells per each sensor, main and backup copies, plus use_backup cell nvmem-cell-names: - minItems: 1 - items: - - const: calib - - enum: - - calib_backup - - calib_sel + oneOf: + - minItems: 1 + items: + - const: calib + - enum: + - calib_backup + - calib_sel + - minItems: 5 + items: + - const: mode + - const: base1 + - const: base2 + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + - pattern: '^s[0-9]+_p1$' + - pattern: '^s[0-9]+_p2$' + # special case for msm8974 / apq8084 + - items: + - const: mode + - const: base1 + - const: base2 + - const: use_backup + - const: mode_backup + - const: base1_backup + - const: base2_backup + - const: s0_p1 + - const: s0_p2 + - const: s1_p1 + - const: s1_p2 + - const: s2_p1 + - const: s2_p2 + - const: s3_p1 + - const: s3_p2 + - const: s4_p1 + - const: s4_p2 + - const: s5_p1 + - const: s5_p2 + - const: s6_p1 + - const: s6_p2 + - const: s7_p1 + - const: s7_p2 + - const: s8_p1 + - const: s8_p2 + - const: s9_p1 + - const: s9_p2 + - const: s10_p1 + - const: s10_p2 + - const: s0_p1_backup + - const: s0_p2_backup + - const: s1_p1_backup + - const: s1_p2_backup + - const: s2_p1_backup + - const: s2_p2_backup + - const: s3_p1_backup + - const: s3_p2_backup + - const: s4_p1_backup + - const: s4_p2_backup + - const: s5_p1_backup + - const: s5_p2_backup + - const: s6_p1_backup + - const: s6_p2_backup + - const: s7_p1_backup + - const: s7_p2_backup + - const: s8_p1_backup + - const: s8_p2_backup + - const: s9_p1_backup + - const: s9_p2_backup + - const: s10_p1_backup + - const: s10_p2_backup "#qcom,sensors": description: @@ -220,6 +323,36 @@ examples: }; }; + - | + #include + // Example 1 (new calbiration data: for pre v1 IP): + thermal-sensor@900000 { + compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; + reg = <0x4a9000 0x1000>, /* TM */ + <0x4a8000 0x1000>; /* SROT */ + + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2"; + + interrupts = ; + interrupt-names = "uplow"; + + #qcom,sensors = <5>; + #thermal-sensor-cells = <1>; + }; + - | #include // Example 1 (legacy: for pre v1 IP): diff --git a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.yaml b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.yaml index 0f05f5c886c5fe1df2a4110b827a72dff4ccab57..ecf276fd155cfb2730ac5d9a91e9feecb72fd46b 100644 --- a/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/rcar-gen3-thermal.yaml @@ -28,6 +28,7 @@ properties: - renesas,r8a77980-thermal # R-Car V3H - renesas,r8a779a0-thermal # R-Car V3U - renesas,r8a779f0-thermal # R-Car S4-8 + - renesas,r8a779g0-thermal # R-Car V4H reg: true @@ -80,6 +81,7 @@ else: - description: TSC1 registers - description: TSC2 registers - description: TSC3 registers + - description: TSC4 registers if: not: properties: @@ -87,6 +89,7 @@ else: contains: enum: - renesas,r8a779f0-thermal + - renesas,r8a779g0-thermal then: required: - interrupts diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt index 8bbb6e94508b25c5773f9e8436cac9575215bf6a..b3e797e8aa3133df9cf4c3e80740e3504bb6a10b 100644 --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt @@ -33,6 +33,7 @@ Required properties: For those SoCs that use CPUX * "mediatek,mt6795-systimer" for MT6795 compatible timers (CPUX) + * "mediatek,mt8365-systimer" for MT8365 compatible timers (CPUX) - reg: Should contain location and length for timer register. - clocks: Should contain system clock. diff --git a/Documentation/devicetree/bindings/timer/riscv,timer.yaml b/Documentation/devicetree/bindings/timer/riscv,timer.yaml new file mode 100644 index 0000000000000000000000000000000000000000..38d67e1a5a7946528a460e7bae164405b08264a4 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/riscv,timer.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/riscv,timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V timer + +maintainers: + - Anup Patel + +description: |+ + RISC-V platforms always have a RISC-V timer device for the supervisor-mode + based on the time CSR defined by the RISC-V privileged specification. The + timer interrupts of this device are configured using the RISC-V SBI Time + extension or the RISC-V Sstc extension. + + The clock frequency of RISC-V timer device is specified via the + "timebase-frequency" DT property of "/cpus" DT node which is described + in Documentation/devicetree/bindings/riscv/cpus.yaml + +properties: + compatible: + enum: + - riscv,timer + + interrupts-extended: + minItems: 1 + maxItems: 4096 # Should be enough? + + riscv,timer-cannot-wake-cpu: + type: boolean + description: + If present, the timer interrupt cannot wake up the CPU from one or + more suspend/idle states. + +additionalProperties: false + +required: + - compatible + - interrupts-extended + +examples: + - | + timer { + compatible = "riscv,timer"; + interrupts-extended = <&cpu1intc 5>, + <&cpu2intc 5>, + <&cpu3intc 5>, + <&cpu4intc 5>; + }; +... diff --git a/Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml b/Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml index b61ed1a431bb3a1725c18709894e1e7d05f3568e..65e59836a660c4bc2a439cf0a49be2e77df877d0 100644 --- a/Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml +++ b/Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml @@ -17,6 +17,7 @@ properties: - items: - enum: - rockchip,rv1108-timer + - rockchip,rv1126-timer - rockchip,rk3036-timer - rockchip,rk3128-timer - rockchip,rk3188-timer diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index bbad241658374a954111c7fc14c1b74ade970581..aada6957216c398395e1f7d692d4261803804caf 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -20,6 +20,10 @@ description: property of "/cpus" DT node. The "timebase-frequency" DT property is described in Documentation/devicetree/bindings/riscv/cpus.yaml + T-Head C906/C910 CPU cores include an implementation of CLINT too, however + their implementation lacks a memory-mapped MTIME register, thus not + compatible with SiFive ones. + properties: compatible: oneOf: @@ -29,6 +33,10 @@ properties: - starfive,jh7100-clint - canaan,k210-clint - const: sifive,clint0 + - items: + - enum: + - allwinner,sun20i-d1-clint + - const: thead,c900-clint - items: - const: sifive,clint0 - const: riscv,clint0 diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 70ffb3780621bdf4a7c6e6e951de4a92cd11165e..852910c0ce3051173b5bf70b65a691e44f6069c1 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -69,6 +69,8 @@ patternProperties: description: Annapurna Labs "^alcatel,.*": description: Alcatel + "^aldec,.*": + description: Aldec, Inc. "^alfa-network,.*": description: ALFA Network Inc. "^allegro,.*": @@ -264,6 +266,8 @@ patternProperties: description: Cirrus Logic, Inc. "^cisco,.*": description: Cisco Systems, Inc. + "^clockwork,.*": + description: Clockwork Tech LLC "^cloos,.*": description: Carl Cloos Schweisstechnik GmbH. "^cloudengines,.*": @@ -374,6 +378,8 @@ patternProperties: description: EBV Elektronik "^eckelmann,.*": description: Eckelmann AG + "^edgeble,.*": + description: Edgeble AI Technologies Pvt. Ltd. "^edimax,.*": description: EDIMAX Technology Co., Ltd "^edt,.*": @@ -396,6 +402,8 @@ patternProperties: description: Elimo Engineering Ltd. "^elpida,.*": description: Elpida Memory, Inc. + "^embedfire,.*": + description: Dongguan EmbedFire Electronic Technology Co., Ltd. "^embest,.*": description: Shenzhen Embest Technology Co., Ltd. "^emlid,.*": @@ -512,6 +520,8 @@ patternProperties: description: Shenzhen Huiding Technology Co., Ltd. "^google,.*": description: Google, Inc. + "^gplus,.*": + description: GPLUS "^grinn,.*": description: Grinn "^grmn,.*": @@ -1025,6 +1035,8 @@ patternProperties: description: PocketBook International SA "^polaroid,.*": description: Polaroid Corporation + "^polyhex,.*": + description: Polyhex Technology Co. Ltd. "^portwell,.*": description: Portwell Inc. "^poslab,.*": @@ -1246,6 +1258,8 @@ patternProperties: description: Starry Electronic Technology (ShenZhen) Co., LTD "^startek,.*": description: Startek + "^starterkit,.*": + description: Starterkit "^ste,.*": description: ST-Ericsson deprecated: true @@ -1319,6 +1333,8 @@ patternProperties: description: thingy.jp "^thundercomm,.*": description: Thundercomm Technology Co., Ltd. + "^thwc,.*": + description: Shenzhen Tong Heng Wei Chuang Technology Co., Ltd. "^ti,.*": description: Texas Instruments "^tianma,.*": @@ -1372,6 +1388,8 @@ patternProperties: description: uCRobotics "^udoo,.*": description: Udoo + "^ufispace,.*": + description: Ufi Space Co., Ltd. "^ugoos,.*": description: Ugoos Industrial Co., Ltd. "^uniwest,.*": @@ -1444,6 +1462,8 @@ patternProperties: description: Shenzhen whwave Electronics, Inc. "^wi2wi,.*": description: Wi2Wi, Inc. + "^widora,.*": + description: Beijing Widora Technology Co., Ltd. "^wiligear,.*": description: Wiligear, Ltd. "^willsemi,.*": diff --git a/Documentation/driver-api/media/drivers/davinci-vpbe-devel.rst b/Documentation/driver-api/media/drivers/davinci-vpbe-devel.rst deleted file mode 100644 index 4e87bdbc7ae41e3c64dffc77c9fa6b58e3e4dfe1..0000000000000000000000000000000000000000 --- a/Documentation/driver-api/media/drivers/davinci-vpbe-devel.rst +++ /dev/null @@ -1,39 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -The VPBE V4L2 driver design -=========================== - -File partitioning ------------------ - - V4L2 display device driver - drivers/media/platform/ti/davinci/vpbe_display.c - drivers/media/platform/ti/davinci/vpbe_display.h - - VPBE display controller - drivers/media/platform/ti/davinci/vpbe.c - drivers/media/platform/ti/davinci/vpbe.h - - VPBE venc sub device driver - drivers/media/platform/ti/davinci/vpbe_venc.c - drivers/media/platform/ti/davinci/vpbe_venc.h - drivers/media/platform/ti/davinci/vpbe_venc_regs.h - - VPBE osd driver - drivers/media/platform/ti/davinci/vpbe_osd.c - drivers/media/platform/ti/davinci/vpbe_osd.h - drivers/media/platform/ti/davinci/vpbe_osd_regs.h - -To be done ----------- - -vpbe display controller - - Add support for external encoders. - - add support for selecting external encoder as default at probe time. - -vpbe venc sub device - - add timings for supporting ths8200 - - add support for LogicPD LCD. - -FB drivers - - Add support for fbdev drivers.- Ready and part of subsequent patches. diff --git a/Documentation/driver-api/media/drivers/index.rst b/Documentation/driver-api/media/drivers/index.rst index 32406490557cff02f7f7f76abb147411be224b06..3c17d48f83c0b0f407331ac017d3b33659e136f5 100644 --- a/Documentation/driver-api/media/drivers/index.rst +++ b/Documentation/driver-api/media/drivers/index.rst @@ -16,7 +16,6 @@ Video4Linux (V4L) drivers cpia2_devel cx2341x-devel cx88-devel - davinci-vpbe-devel fimc-devel pvrusb2 pxa_camera diff --git a/Documentation/driver-api/surface_aggregator/client.rst b/Documentation/driver-api/surface_aggregator/client.rst index 27f95abdbe99732f79be64bf741c6e02fbd22f84..e100ab0a24cc4ac9aed5578b4d657ee579df47b1 100644 --- a/Documentation/driver-api/surface_aggregator/client.rst +++ b/Documentation/driver-api/surface_aggregator/client.rst @@ -19,7 +19,7 @@ .. |ssam_notifier_unregister| replace:: :c:func:`ssam_notifier_unregister` .. |ssam_device_notifier_register| replace:: :c:func:`ssam_device_notifier_register` .. |ssam_device_notifier_unregister| replace:: :c:func:`ssam_device_notifier_unregister` -.. |ssam_request_sync| replace:: :c:func:`ssam_request_sync` +.. |ssam_request_do_sync| replace:: :c:func:`ssam_request_do_sync` .. |ssam_event_mask| replace:: :c:type:`enum ssam_event_mask ` @@ -191,7 +191,7 @@ data received from it is converted from little-endian to host endianness. * they do not correspond to an actual SAM/EC request. */ rqst.target_category = SSAM_SSH_TC_SAM; - rqst.target_id = 0x01; + rqst.target_id = SSAM_SSH_TID_SAM; rqst.command_id = 0x02; rqst.instance_id = 0x03; rqst.flags = SSAM_REQUEST_HAS_RESPONSE; @@ -209,12 +209,12 @@ data received from it is converted from little-endian to host endianness. * with the SSAM_REQUEST_HAS_RESPONSE flag set in the specification * above. */ - status = ssam_request_sync(ctrl, &rqst, &resp); + status = ssam_request_do_sync(ctrl, &rqst, &resp); /* * Alternatively use * - * ssam_request_sync_onstack(ctrl, &rqst, &resp, sizeof(arg_le)); + * ssam_request_do_sync_onstack(ctrl, &rqst, &resp, sizeof(arg_le)); * * to perform the request, allocating the message buffer directly * on the stack as opposed to allocation via kzalloc(). @@ -230,7 +230,7 @@ data received from it is converted from little-endian to host endianness. return status; } -Note that |ssam_request_sync| in its essence is a wrapper over lower-level +Note that |ssam_request_do_sync| in its essence is a wrapper over lower-level request primitives, which may also be used to perform requests. Refer to its implementation and documentation for more details. @@ -241,7 +241,7 @@ one of the generator macros, for example via: SSAM_DEFINE_SYNC_REQUEST_W(__ssam_tmp_perf_mode_set, __le32, { .target_category = SSAM_SSH_TC_TMP, - .target_id = 0x01, + .target_id = SSAM_SSH_TID_SAM, .command_id = 0x03, .instance_id = 0x00, }); diff --git a/Documentation/driver-api/surface_aggregator/ssh.rst b/Documentation/driver-api/surface_aggregator/ssh.rst index bf007d6c987321edf9dee963dce8c56faef7810b..18fd0f0aee84b90649a5b2303e397bf6bb176800 100644 --- a/Documentation/driver-api/surface_aggregator/ssh.rst +++ b/Documentation/driver-api/surface_aggregator/ssh.rst @@ -13,6 +13,7 @@ .. |DATA_NSQ| replace:: ``DATA_NSQ`` .. |TC| replace:: ``TC`` .. |TID| replace:: ``TID`` +.. |SID| replace:: ``SID`` .. |IID| replace:: ``IID`` .. |RQID| replace:: ``RQID`` .. |CID| replace:: ``CID`` @@ -219,13 +220,13 @@ following fields, packed together and in order: - |u8| - Target category. - * - |TID| (out) + * - |TID| - |u8| - - Target ID for outgoing (host to EC) commands. + - Target ID for commands/messages. - * - |TID| (in) + * - |SID| - |u8| - - Target ID for incoming (EC to host) commands. + - Source ID for commands/messages. * - |IID| - |u8| @@ -286,19 +287,20 @@ general, however, a single target category should map to a single reserved event request ID. Furthermore, requests, responses, and events have an associated target ID -(``TID``). This target ID is split into output (host to EC) and input (EC to -host) fields, with the respecting other field (e.g. output field on incoming -messages) set to zero. Two ``TID`` values are known: Primary (``0x01``) and -secondary (``0x02``). In general, the response to a request should have the -same ``TID`` value, however, the field (output vs. input) should be used in -accordance to the direction in which the response is sent (i.e. on the input -field, as responses are generally sent from the EC to the host). - -Note that, even though requests and events should be uniquely identifiable -by target category and command ID alone, the EC may require specific -target ID and instance ID values to accept a command. A command that is -accepted for ``TID=1``, for example, may not be accepted for ``TID=2`` -and vice versa. +(``TID``) and source ID (``SID``). These two fields indicate where a message +originates from (``SID``) and what the intended target of the message is +(``TID``). Note that a response to a specific request therefore has the source +and target IDs swapped when compared to the original request (i.e. the request +target is the response source and the request source is the response target). +See (:c:type:`enum ssh_request_id `) for possible values of +both. + +Note that, even though requests and events should be uniquely identifiable by +target category and command ID alone, the EC may require specific target ID and +instance ID values to accept a command. A command that is accepted for +``TID=1``, for example, may not be accepted for ``TID=2`` and vice versa. While +this may not always hold in reality, you can think of different target/source +IDs indicating different physical ECs with potentially different feature sets. Limitations and Observations diff --git a/Documentation/driver-api/thermal/index.rst b/Documentation/driver-api/thermal/index.rst index 030306ffa408b5dd711e1848d8e273525cf3593f..a886028014ab0922ed4b4b4fec9bd9db78c0a6bf 100644 --- a/Documentation/driver-api/thermal/index.rst +++ b/Documentation/driver-api/thermal/index.rst @@ -14,7 +14,6 @@ Thermal exynos_thermal exynos_thermal_emulation - intel_powerclamp nouveau_thermal x86_pkg_temperature_thermal intel_dptf diff --git a/Documentation/driver-api/thermal/intel_dptf.rst b/Documentation/driver-api/thermal/intel_dptf.rst index 372bdb4d04c6d4f1c885d21e7d1f623c21065bbd..f5c193cccbda01a714c51d2c022823d1a063f1f0 100644 --- a/Documentation/driver-api/thermal/intel_dptf.rst +++ b/Documentation/driver-api/thermal/intel_dptf.rst @@ -84,6 +84,9 @@ DPTF ACPI Drivers interface https:/github.com/intel/thermal_daemon for decoding thermal table. +``production_mode`` (RO) + When different from zero, manufacturer locked thermal configuration + from further changes. ACPI Thermal Relationship table interface ------------------------------------------ diff --git a/Documentation/features/seccomp/seccomp-filter/arch-support.txt b/Documentation/features/seccomp/seccomp-filter/arch-support.txt index dc71bf7b1a7ef33381248e7463e7856b29fd6926..3a7237b989cd7fd3031928c6af9137b8a420ddc5 100644 --- a/Documentation/features/seccomp/seccomp-filter/arch-support.txt +++ b/Documentation/features/seccomp/seccomp-filter/arch-support.txt @@ -14,7 +14,7 @@ | hexagon: | TODO | | ia64: | TODO | | loongarch: | ok | - | m68k: | TODO | + | m68k: | ok | | microblaze: | TODO | | mips: | ok | | nios2: | TODO | diff --git a/Documentation/filesystems/erofs.rst b/Documentation/filesystems/erofs.rst index 067fd1670b1f1d6937d214f33309c4fc55e29923..a43aacf1494e778585aea093fb4c099dc4459be7 100644 --- a/Documentation/filesystems/erofs.rst +++ b/Documentation/filesystems/erofs.rst @@ -120,6 +120,8 @@ dax={always,never} Use direct access (no page cache). See dax A legacy option which is an alias for ``dax=always``. device=%s Specify a path to an extra device to be used together. fsid=%s Specify a filesystem image ID for Fscache back-end. +domain_id=%s Specify a domain ID in fscache mode so that different images + with the same blobs under a given domain ID can share storage. =================== ========================================================= Sysfs Entries diff --git a/Documentation/filesystems/fscrypt.rst b/Documentation/filesystems/fscrypt.rst index ef183387da208af15575f5a176e646e66e8d50fd..eccd327e6df504508bb6b8cd1ff7beb132acdb42 100644 --- a/Documentation/filesystems/fscrypt.rst +++ b/Documentation/filesystems/fscrypt.rst @@ -1277,8 +1277,8 @@ the file contents themselves, as described below: For the read path (->read_folio()) of regular files, filesystems can read the ciphertext into the page cache and decrypt it in-place. The -page lock must be held until decryption has finished, to prevent the -page from becoming visible to userspace prematurely. +folio lock must be held until decryption has finished, to prevent the +folio from becoming visible to userspace prematurely. For the write path (->writepage()) of regular files, filesystems cannot encrypt data in-place in the page cache, since the cached diff --git a/Documentation/filesystems/fsverity.rst b/Documentation/filesystems/fsverity.rst index cb8e7573882a1e4509f9baa2dedd353ece60defa..ede672dedf110d58e53b8e7124b49da389f740fe 100644 --- a/Documentation/filesystems/fsverity.rst +++ b/Documentation/filesystems/fsverity.rst @@ -118,10 +118,11 @@ as follows: - ``hash_algorithm`` must be the identifier for the hash algorithm to use for the Merkle tree, such as FS_VERITY_HASH_ALG_SHA256. See ``include/uapi/linux/fsverity.h`` for the list of possible values. -- ``block_size`` must be the Merkle tree block size. Currently, this - must be equal to the system page size, which is usually 4096 bytes. - Other sizes may be supported in the future. This value is not - necessarily the same as the filesystem block size. +- ``block_size`` is the Merkle tree block size, in bytes. In Linux + v6.3 and later, this can be any power of 2 between (inclusively) + 1024 and the minimum of the system page size and the filesystem + block size. In earlier versions, the page size was the only allowed + value. - ``salt_size`` is the size of the salt in bytes, or 0 if no salt is provided. The salt is a value that is prepended to every hashed block; it can be used to personalize the hashing for a particular @@ -161,6 +162,7 @@ FS_IOC_ENABLE_VERITY can fail with the following errors: - ``EBUSY``: this ioctl is already running on the file - ``EEXIST``: the file already has verity enabled - ``EFAULT``: the caller provided inaccessible memory +- ``EFBIG``: the file is too large to enable verity on - ``EINTR``: the operation was interrupted by a fatal signal - ``EINVAL``: unsupported version, hash algorithm, or block size; or reserved bits are set; or the file descriptor refers to neither a @@ -495,9 +497,11 @@ To create verity files on an ext4 filesystem, the filesystem must have been formatted with ``-O verity`` or had ``tune2fs -O verity`` run on it. "verity" is an RO_COMPAT filesystem feature, so once set, old kernels will only be able to mount the filesystem readonly, and old -versions of e2fsck will be unable to check the filesystem. Moreover, -currently ext4 only supports mounting a filesystem with the "verity" -feature when its block size is equal to PAGE_SIZE (often 4096 bytes). +versions of e2fsck will be unable to check the filesystem. + +Originally, an ext4 filesystem with the "verity" feature could only be +mounted when its block size was equal to the system page size +(typically 4096 bytes). In Linux v6.3, this limitation was removed. ext4 sets the EXT4_VERITY_FL on-disk inode flag on verity files. It can only be set by `FS_IOC_ENABLE_VERITY`_, and it cannot be cleared. @@ -518,9 +522,7 @@ support paging multi-gigabyte xattrs into memory, and to support encrypting xattrs. Note that the verity metadata *must* be encrypted when the file is, since it contains hashes of the plaintext data. -Currently, ext4 verity only supports the case where the Merkle tree -block size, filesystem block size, and page size are all the same. It -also only supports extent-based files. +ext4 only allows verity on extent-based files. f2fs ---- @@ -538,11 +540,10 @@ Like ext4, f2fs stores the verity metadata (Merkle tree and fsverity_descriptor) past the end of the file, starting at the first 64K boundary beyond i_size. See explanation for ext4 above. Moreover, f2fs supports at most 4096 bytes of xattr entries per inode -which wouldn't be enough for even a single Merkle tree block. +which usually wouldn't be enough for even a single Merkle tree block. -Currently, f2fs verity only supports a Merkle tree block size of 4096. -Also, f2fs doesn't support enabling verity on files that currently -have atomic or volatile writes pending. +f2fs doesn't support enabling verity on files that currently have +atomic or volatile writes pending. btrfs ----- @@ -567,51 +568,48 @@ Pagecache ~~~~~~~~~ For filesystems using Linux's pagecache, the ``->read_folio()`` and -``->readahead()`` methods must be modified to verify pages before they -are marked Uptodate. Merely hooking ``->read_iter()`` would be +``->readahead()`` methods must be modified to verify folios before +they are marked Uptodate. Merely hooking ``->read_iter()`` would be insufficient, since ``->read_iter()`` is not used for memory maps. -Therefore, fs/verity/ provides a function fsverity_verify_page() which -verifies a page that has been read into the pagecache of a verity -inode, but is still locked and not Uptodate, so it's not yet readable -by userspace. As needed to do the verification, -fsverity_verify_page() will call back into the filesystem to read -Merkle tree pages via fsverity_operations::read_merkle_tree_page(). +Therefore, fs/verity/ provides the function fsverity_verify_blocks() +which verifies data that has been read into the pagecache of a verity +inode. The containing folio must still be locked and not Uptodate, so +it's not yet readable by userspace. As needed to do the verification, +fsverity_verify_blocks() will call back into the filesystem to read +hash blocks via fsverity_operations::read_merkle_tree_page(). -fsverity_verify_page() returns false if verification failed; in this -case, the filesystem must not set the page Uptodate. Following this, +fsverity_verify_blocks() returns false if verification failed; in this +case, the filesystem must not set the folio Uptodate. Following this, as per the usual Linux pagecache behavior, attempts by userspace to -read() from the part of the file containing the page will fail with -EIO, and accesses to the page within a memory map will raise SIGBUS. - -fsverity_verify_page() currently only supports the case where the -Merkle tree block size is equal to PAGE_SIZE (often 4096 bytes). +read() from the part of the file containing the folio will fail with +EIO, and accesses to the folio within a memory map will raise SIGBUS. -In principle, fsverity_verify_page() verifies the entire path in the -Merkle tree from the data page to the root hash. However, for -efficiency the filesystem may cache the hash pages. Therefore, -fsverity_verify_page() only ascends the tree reading hash pages until -an already-verified hash page is seen, as indicated by the PageChecked -bit being set. It then verifies the path to that page. +In principle, verifying a data block requires verifying the entire +path in the Merkle tree from the data block to the root hash. +However, for efficiency the filesystem may cache the hash blocks. +Therefore, fsverity_verify_blocks() only ascends the tree reading hash +blocks until an already-verified hash block is seen. It then verifies +the path to that block. This optimization, which is also used by dm-verity, results in excellent sequential read performance. This is because usually (e.g. -127 in 128 times for 4K blocks and SHA-256) the hash page from the +127 in 128 times for 4K blocks and SHA-256) the hash block from the bottom level of the tree will already be cached and checked from -reading a previous data page. However, random reads perform worse. +reading a previous data block. However, random reads perform worse. Block device based filesystems ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Block device based filesystems (e.g. ext4 and f2fs) in Linux also use the pagecache, so the above subsection applies too. However, they -also usually read many pages from a file at once, grouped into a +also usually read many data blocks from a file at once, grouped into a structure called a "bio". To make it easier for these types of filesystems to support fs-verity, fs/verity/ also provides a function -fsverity_verify_bio() which verifies all pages in a bio. +fsverity_verify_bio() which verifies all data blocks in a bio. ext4 and f2fs also support encryption. If a verity file is also -encrypted, the pages must be decrypted before being verified. To +encrypted, the data must be decrypted before being verified. To support this, these filesystems allocate a "post-read context" for each bio and store it in ``->bi_private``:: @@ -626,14 +624,14 @@ each bio and store it in ``->bi_private``:: verity, or both is enabled. After the bio completes, for each needed postprocessing step the filesystem enqueues the bio_post_read_ctx on a workqueue, and then the workqueue work does the decryption or -verification. Finally, pages where no decryption or verity error -occurred are marked Uptodate, and the pages are unlocked. +verification. Finally, folios where no decryption or verity error +occurred are marked Uptodate, and the folios are unlocked. On many filesystems, files can contain holes. Normally, -``->readahead()`` simply zeroes holes and sets the corresponding pages -Uptodate; no bios are issued. To prevent this case from bypassing -fs-verity, these filesystems use fsverity_verify_page() to verify hole -pages. +``->readahead()`` simply zeroes hole blocks and considers the +corresponding data to be up-to-date; no bios are issued. To prevent +this case from bypassing fs-verity, filesystems use +fsverity_verify_blocks() to verify hole blocks. Filesystems also disable direct I/O on verity files, since otherwise direct I/O would bypass fs-verity. @@ -644,7 +642,7 @@ Userspace utility This document focuses on the kernel, but a userspace utility for fs-verity can be found at: - https://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/fsverity-utils.git + https://git.kernel.org/pub/scm/fs/fsverity/fsverity-utils.git See the README.md file in the fsverity-utils source tree for details, including examples of setting up fs-verity protected files. @@ -793,9 +791,9 @@ weren't already directly answered in other parts of this document. :A: There are many reasons why this is not possible or would be very difficult, including the following: - - To prevent bypassing verification, pages must not be marked + - To prevent bypassing verification, folios must not be marked Uptodate until they've been verified. Currently, each - filesystem is responsible for marking pages Uptodate via + filesystem is responsible for marking folios Uptodate via ``->readahead()``. Therefore, currently it's not possible for the VFS to do the verification on its own. Changing this would require significant changes to the VFS and all filesystems. diff --git a/Documentation/filesystems/locking.rst b/Documentation/filesystems/locking.rst index 36fa2a83d71410119bd9ee67e7e4494743abbc8b..7de7a7272a5e834bcb388b8a1645afd68d5051d6 100644 --- a/Documentation/filesystems/locking.rst +++ b/Documentation/filesystems/locking.rst @@ -56,35 +56,35 @@ inode_operations prototypes:: - int (*create) (struct inode *,struct dentry *,umode_t, bool); + int (*create) (struct mnt_idmap *, struct inode *,struct dentry *,umode_t, bool); struct dentry * (*lookup) (struct inode *,struct dentry *, unsigned int); int (*link) (struct dentry *,struct inode *,struct dentry *); int (*unlink) (struct inode *,struct dentry *); - int (*symlink) (struct inode *,struct dentry *,const char *); - int (*mkdir) (struct inode *,struct dentry *,umode_t); + int (*symlink) (struct mnt_idmap *, struct inode *,struct dentry *,const char *); + int (*mkdir) (struct mnt_idmap *, struct inode *,struct dentry *,umode_t); int (*rmdir) (struct inode *,struct dentry *); - int (*mknod) (struct inode *,struct dentry *,umode_t,dev_t); - int (*rename) (struct inode *, struct dentry *, + int (*mknod) (struct mnt_idmap *, struct inode *,struct dentry *,umode_t,dev_t); + int (*rename) (struct mnt_idmap *, struct inode *, struct dentry *, struct inode *, struct dentry *, unsigned int); int (*readlink) (struct dentry *, char __user *,int); const char *(*get_link) (struct dentry *, struct inode *, struct delayed_call *); void (*truncate) (struct inode *); - int (*permission) (struct inode *, int, unsigned int); + int (*permission) (struct mnt_idmap *, struct inode *, int, unsigned int); struct posix_acl * (*get_inode_acl)(struct inode *, int, bool); - int (*setattr) (struct dentry *, struct iattr *); - int (*getattr) (const struct path *, struct kstat *, u32, unsigned int); + int (*setattr) (struct mnt_idmap *, struct dentry *, struct iattr *); + int (*getattr) (struct mnt_idmap *, const struct path *, struct kstat *, u32, unsigned int); ssize_t (*listxattr) (struct dentry *, char *, size_t); int (*fiemap)(struct inode *, struct fiemap_extent_info *, u64 start, u64 len); void (*update_time)(struct inode *, struct timespec *, int); int (*atomic_open)(struct inode *, struct dentry *, struct file *, unsigned open_flag, umode_t create_mode); - int (*tmpfile) (struct user_namespace *, struct inode *, + int (*tmpfile) (struct mnt_idmap *, struct inode *, struct file *, umode_t); - int (*fileattr_set)(struct user_namespace *mnt_userns, + int (*fileattr_set)(struct mnt_idmap *idmap, struct dentry *dentry, struct fileattr *fa); int (*fileattr_get)(struct dentry *dentry, struct fileattr *fa); - struct posix_acl * (*get_acl)(struct user_namespace *, struct dentry *, int); + struct posix_acl * (*get_acl)(struct mnt_idmap *, struct dentry *, int); locking rules: all may block @@ -135,7 +135,7 @@ prototypes:: struct inode *inode, const char *name, void *buffer, size_t size); int (*set)(const struct xattr_handler *handler, - struct user_namespace *mnt_userns, + struct mnt_idmap *idmap, struct dentry *dentry, struct inode *inode, const char *name, const void *buffer, size_t size, int flags); diff --git a/Documentation/filesystems/vfs.rst b/Documentation/filesystems/vfs.rst index 2c15e70531137565ed5ab6b20fe690b60dafedce..c53f30251a660c8b143e32bac800420fb9afe057 100644 --- a/Documentation/filesystems/vfs.rst +++ b/Documentation/filesystems/vfs.rst @@ -421,31 +421,31 @@ As of kernel 2.6.22, the following members are defined: .. code-block:: c struct inode_operations { - int (*create) (struct user_namespace *, struct inode *,struct dentry *, umode_t, bool); + int (*create) (struct mnt_idmap *, struct inode *,struct dentry *, umode_t, bool); struct dentry * (*lookup) (struct inode *,struct dentry *, unsigned int); int (*link) (struct dentry *,struct inode *,struct dentry *); int (*unlink) (struct inode *,struct dentry *); - int (*symlink) (struct user_namespace *, struct inode *,struct dentry *,const char *); - int (*mkdir) (struct user_namespace *, struct inode *,struct dentry *,umode_t); + int (*symlink) (struct mnt_idmap *, struct inode *,struct dentry *,const char *); + int (*mkdir) (struct mnt_idmap *, struct inode *,struct dentry *,umode_t); int (*rmdir) (struct inode *,struct dentry *); - int (*mknod) (struct user_namespace *, struct inode *,struct dentry *,umode_t,dev_t); - int (*rename) (struct user_namespace *, struct inode *, struct dentry *, + int (*mknod) (struct mnt_idmap *, struct inode *,struct dentry *,umode_t,dev_t); + int (*rename) (struct mnt_idmap *, struct inode *, struct dentry *, struct inode *, struct dentry *, unsigned int); int (*readlink) (struct dentry *, char __user *,int); const char *(*get_link) (struct dentry *, struct inode *, struct delayed_call *); - int (*permission) (struct user_namespace *, struct inode *, int); + int (*permission) (struct mnt_idmap *, struct inode *, int); struct posix_acl * (*get_inode_acl)(struct inode *, int, bool); - int (*setattr) (struct user_namespace *, struct dentry *, struct iattr *); - int (*getattr) (struct user_namespace *, const struct path *, struct kstat *, u32, unsigned int); + int (*setattr) (struct mnt_idmap *, struct dentry *, struct iattr *); + int (*getattr) (struct mnt_idmap *, const struct path *, struct kstat *, u32, unsigned int); ssize_t (*listxattr) (struct dentry *, char *, size_t); void (*update_time)(struct inode *, struct timespec *, int); int (*atomic_open)(struct inode *, struct dentry *, struct file *, unsigned open_flag, umode_t create_mode); - int (*tmpfile) (struct user_namespace *, struct inode *, struct file *, umode_t); - struct posix_acl * (*get_acl)(struct user_namespace *, struct dentry *, int); - int (*set_acl)(struct user_namespace *, struct dentry *, struct posix_acl *, int); - int (*fileattr_set)(struct user_namespace *mnt_userns, + int (*tmpfile) (struct mnt_idmap *, struct inode *, struct file *, umode_t); + struct posix_acl * (*get_acl)(struct mnt_idmap *, struct dentry *, int); + int (*set_acl)(struct mnt_idmap *, struct dentry *, struct posix_acl *, int); + int (*fileattr_set)(struct mnt_idmap *idmap, struct dentry *dentry, struct fileattr *fa); int (*fileattr_get)(struct dentry *dentry, struct fileattr *fa); }; diff --git a/Documentation/firmware-guide/acpi/acpi-lid.rst b/Documentation/firmware-guide/acpi/acpi-lid.rst index 71b9af13a048fc80fd0680033b0be9146c7fbe86..03cbad6c67307584396ece6a040144ce644ef94b 100644 --- a/Documentation/firmware-guide/acpi/acpi-lid.rst +++ b/Documentation/firmware-guide/acpi/acpi-lid.rst @@ -34,7 +34,7 @@ state upon the last _LID evaluation. There won't be difference when the _LID control method is evaluated during the runtime, the problem is its initial returning value. When the AML tables implement this control method with cached value, the initial returning value is likely not reliable. -There are platforms always retun "closed" as initial lid state. +There are platforms always return "closed" as initial lid state. Restrictions of the lid state change notifications ================================================== diff --git a/Documentation/firmware-guide/acpi/gpio-properties.rst b/Documentation/firmware-guide/acpi/gpio-properties.rst index eaec732cc77cfdf6674da052b8a3dae266b0af2f..db0c0b1f370081691d1e2b14b7445a677064e5d5 100644 --- a/Documentation/firmware-guide/acpi/gpio-properties.rst +++ b/Documentation/firmware-guide/acpi/gpio-properties.rst @@ -67,17 +67,30 @@ state of the output pin which driver should use during its initialization. Linux tries to use common sense here and derives the state from the bias and polarity settings. The table below shows the expectations: -========= ============= ============== -Pull Bias Polarity Requested... -========= ============= ============== -Implicit x AS IS (assumed firmware configured for us) -Explicit x (no _DSD) as Pull Bias (Up == High, Down == Low), - assuming non-active (Polarity = !Pull Bias) -Down Low as low, assuming active -Down High as low, assuming non-active -Up Low as high, assuming non-active -Up High as high, assuming active -========= ============= ============== ++-------------+-------------+-----------------------------------------------+ +| Pull Bias | Polarity | Requested... | ++=============+=============+===============================================+ +| Implicit | ++-------------+-------------+-----------------------------------------------+ +| **Default** | x | AS IS (assumed firmware configured it for us) | ++-------------+-------------+-----------------------------------------------+ +| Explicit | ++-------------+-------------+-----------------------------------------------+ +| **None** | x | AS IS (assumed firmware configured it for us) | +| | | with no Pull Bias | ++-------------+-------------+-----------------------------------------------+ +| **Up** | x (no _DSD) | | +| +-------------+ as high, assuming non-active | +| | Low | | +| +-------------+-----------------------------------------------+ +| | High | as high, assuming active | ++-------------+-------------+-----------------------------------------------+ +| **Down** | x (no _DSD) | | +| +-------------+ as low, assuming non-active | +| | High | | +| +-------------+-----------------------------------------------+ +| | Low | as low, assuming active | ++-------------+-------------+-----------------------------------------------+ That said, for our above example the both GPIOs, since the bias setting is explicit and _DSD is present, will be treated as active with a high diff --git a/Documentation/firmware-guide/acpi/namespace.rst b/Documentation/firmware-guide/acpi/namespace.rst index 6193582a2204db02f16d928160709edb5b11d5fb..4ef963679a3d07e2e32b46b5f184bd8bd89fd832 100644 --- a/Documentation/firmware-guide/acpi/namespace.rst +++ b/Documentation/firmware-guide/acpi/namespace.rst @@ -31,7 +31,7 @@ Description Table). The XSDT always points to the FADT (Fixed ACPI Description Table) using its first entry, the data within the FADT includes various fixed-length entries that describe fixed ACPI features of the hardware. The FADT contains a pointer to the DSDT -(Differentiated System Descripition Table). The XSDT also contains +(Differentiated System Description Table). The XSDT also contains entries pointing to possibly multiple SSDTs (Secondary System Description Table). diff --git a/Documentation/kbuild/makefiles.rst b/Documentation/kbuild/makefiles.rst index 6b7368d1f51639c016e4be5f4c3c4f51b0f29991..38bc74eaa547403935a2ae645cb0ec875a1a0279 100644 --- a/Documentation/kbuild/makefiles.rst +++ b/Documentation/kbuild/makefiles.rst @@ -1042,7 +1042,7 @@ $(clean-files). When executing "make clean", the file "crc32table.h" will be deleted. Kbuild will assume files to be in the same relative directory as the -Makefile, except if prefixed with $(objtree). +Makefile. To exclude certain files or directories from make clean, use the $(no-clean-files) variable. diff --git a/Documentation/kernel-hacking/locking.rst b/Documentation/kernel-hacking/locking.rst index c756786e17aea3d9081a61720611e898c846bb3d..dff0646a717bff27f6b82d3a8090876e99d23cec 100644 --- a/Documentation/kernel-hacking/locking.rst +++ b/Documentation/kernel-hacking/locking.rst @@ -1277,11 +1277,11 @@ Manfred Spraul points out that you can still do this, even if the data is very occasionally accessed in user context or softirqs/tasklets. The irq handler doesn't use a lock, and all other accesses are done as so:: - spin_lock(&lock); + mutex_lock(&lock); disable_irq(irq); ... enable_irq(irq); - spin_unlock(&lock); + mutex_unlock(&lock); The disable_irq() prevents the irq handler from running (and waits for it to finish if it's currently running on other CPUs). diff --git a/Documentation/networking/bridge.rst b/Documentation/networking/bridge.rst index 4aef9cddde2fd68bf75a1ec8c3453ad6cb88237c..c859f3c1636edfa30a4f2cde792608fb949a58b3 100644 --- a/Documentation/networking/bridge.rst +++ b/Documentation/networking/bridge.rst @@ -8,7 +8,7 @@ In order to use the Ethernet bridging functionality, you'll need the userspace tools. Documentation for Linux bridging is on: - http://www.linuxfoundation.org/collaborate/workgroups/networking/bridge + https://wiki.linuxfoundation.org/networking/bridge The bridge-utilities are maintained at: git://git.kernel.org/pub/scm/linux/kernel/git/shemminger/bridge-utils.git diff --git a/Documentation/networking/device_drivers/ethernet/intel/ice.rst b/Documentation/networking/device_drivers/ethernet/intel/ice.rst index dc2e60ced927c378b4c91b1eadb52085e5c7d46e..b481b81f3be5ba6ee35af1e46ce3f44589efa22a 100644 --- a/Documentation/networking/device_drivers/ethernet/intel/ice.rst +++ b/Documentation/networking/device_drivers/ethernet/intel/ice.rst @@ -819,7 +819,7 @@ NAPI ---- This driver supports NAPI (Rx polling mode). For more information on NAPI, see -https://www.linuxfoundation.org/collaborate/workgroups/networking/napi +https://wiki.linuxfoundation.org/networking/napi MACVLAN diff --git a/Documentation/networking/device_drivers/ethernet/wangxun/txgbe.rst b/Documentation/networking/device_drivers/ethernet/wangxun/txgbe.rst index eaa87dbe8848d404dd2c893c6f27d19f2f2fa0c4..d052ef40fe36735f730b682b06e819012a0d38e4 100644 --- a/Documentation/networking/device_drivers/ethernet/wangxun/txgbe.rst +++ b/Documentation/networking/device_drivers/ethernet/wangxun/txgbe.rst @@ -16,5 +16,5 @@ Contents Support ======= -If you got any problem, contact Wangxun support team via support@trustnetic.com +If you got any problem, contact Wangxun support team via nic-support@net-swift.com and Cc: netdev. diff --git a/Documentation/networking/nf_conntrack-sysctl.rst b/Documentation/networking/nf_conntrack-sysctl.rst index 49db1d11d7c4a8788f5068e4ac97a420202044f7..8b1045c3b59e0ef0675d0ed113139b4e84b8b81d 100644 --- a/Documentation/networking/nf_conntrack-sysctl.rst +++ b/Documentation/networking/nf_conntrack-sysctl.rst @@ -173,7 +173,9 @@ nf_conntrack_sctp_timeout_cookie_echoed - INTEGER (seconds) default 3 nf_conntrack_sctp_timeout_established - INTEGER (seconds) - default 432000 (5 days) + default 210 + + Default is set to (hb_interval * path_max_retrans + rto_max) nf_conntrack_sctp_timeout_shutdown_sent - INTEGER (seconds) default 0.3 @@ -190,12 +192,6 @@ nf_conntrack_sctp_timeout_heartbeat_sent - INTEGER (seconds) This timeout is used to setup conntrack entry on secondary paths. Default is set to hb_interval. -nf_conntrack_sctp_timeout_heartbeat_acked - INTEGER (seconds) - default 210 - - This timeout is used to setup conntrack entry on secondary paths. - Default is set to (hb_interval * path_max_retrans + rto_max) - nf_conntrack_udp_timeout - INTEGER (seconds) default 30 diff --git a/Documentation/networking/rxrpc.rst b/Documentation/networking/rxrpc.rst index 39494a6ea739cf02217f088721ff23e1751521fe..e1af54424192b375f701992a95ffeeb68a76de8c 100644 --- a/Documentation/networking/rxrpc.rst +++ b/Documentation/networking/rxrpc.rst @@ -880,8 +880,8 @@ The kernel interface functions are as follows: notify_end_rx can be NULL or it can be used to specify a function to be called when the call changes state to end the Tx phase. This function is - called with the call-state spinlock held to prevent any reply or final ACK - from being delivered first. + called with a spinlock held to prevent the last DATA packet from being + transmitted until the function returns. (#) Receive data from a call:: diff --git a/Documentation/power/power_supply_class.rst b/Documentation/power/power_supply_class.rst index c04fabee0a583e612dade511b1717634d778b704..da8e275a14ffb9f84bae9ae1efc4720a55ea3010 100644 --- a/Documentation/power/power_supply_class.rst +++ b/Documentation/power/power_supply_class.rst @@ -40,8 +40,8 @@ kind of power supply, and can process/present them to a user in consistent manner. Results for different power supplies and machines are also directly comparable. -See drivers/power/supply/ds2760_battery.c and drivers/power/supply/pda_power.c -for the example how to declare and handle attributes. +See drivers/power/supply/ds2760_battery.c for the example how to declare +and handle attributes. Units diff --git a/Documentation/power/suspend-and-interrupts.rst b/Documentation/power/suspend-and-interrupts.rst index 4cda6617709af3c287b43400fa488cb50578f7a4..dfbace2f4600c8dbbdaa58a748e6377577685f8c 100644 --- a/Documentation/power/suspend-and-interrupts.rst +++ b/Documentation/power/suspend-and-interrupts.rst @@ -67,7 +67,7 @@ That may involve turning on a special signal handling logic within the platform during system sleep so as to trigger a system wakeup when needed. For example, the platform may include a dedicated interrupt controller used specifically for handling system wakeup events. Then, if a given interrupt line is supposed to -wake up the system from sleep sates, the corresponding input of that interrupt +wake up the system from sleep states, the corresponding input of that interrupt controller needs to be enabled to receive signals from the line in question. After wakeup, it generally is better to disable that input to prevent the dedicated controller from triggering interrupts unnecessarily. diff --git a/Documentation/process/maintainer-netdev.rst b/Documentation/process/maintainer-netdev.rst index 1fa5ab8754d358a80f707e544ab03d4b9734e3b1..4a75686d35ab4a646babcadb8d187bde8600038a 100644 --- a/Documentation/process/maintainer-netdev.rst +++ b/Documentation/process/maintainer-netdev.rst @@ -2,9 +2,9 @@ .. _netdev-FAQ: -========== -netdev FAQ -========== +============================= +Networking subsystem (netdev) +============================= tl;dr ----- @@ -15,14 +15,15 @@ tl;dr - don't repost your patches within one 24h period - reverse xmas tree -What is netdev? ---------------- -It is a mailing list for all network-related Linux stuff. This +netdev +------ + +netdev is a mailing list for all network-related Linux stuff. This includes anything found under net/ (i.e. core code like IPv6) and drivers/net (i.e. hardware specific drivers) in the Linux source tree. Note that some subsystems (e.g. wireless drivers) which have a high -volume of traffic have their own specific mailing lists. +volume of traffic have their own specific mailing lists and trees. The netdev list is managed (like many other Linux mailing lists) through VGER (http://vger.kernel.org/) with archives available at @@ -32,32 +33,10 @@ Aside from subsystems like those mentioned above, all network-related Linux development (i.e. RFC, review, comments, etc.) takes place on netdev. -How do the changes posted to netdev make their way into Linux? --------------------------------------------------------------- -There are always two trees (git repositories) in play. Both are -driven by David Miller, the main network maintainer. There is the -``net`` tree, and the ``net-next`` tree. As you can probably guess from -the names, the ``net`` tree is for fixes to existing code already in the -mainline tree from Linus, and ``net-next`` is where the new code goes -for the future release. You can find the trees here: - -- https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git -- https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git - -How do I indicate which tree (net vs. net-next) my patch should be in? ----------------------------------------------------------------------- -To help maintainers and CI bots you should explicitly mark which tree -your patch is targeting. Assuming that you use git, use the prefix -flag:: - - git format-patch --subject-prefix='PATCH net-next' start..finish +Development cycle +----------------- -Use ``net`` instead of ``net-next`` (always lower case) in the above for -bug-fix ``net`` content. - -How often do changes from these trees make it to the mainline Linus tree? -------------------------------------------------------------------------- -To understand this, you need to know a bit of background information on +Here is a bit of background information on the cadence of Linux development. Each new release starts off with a two week "merge window" where the main maintainers feed their new stuff to Linus for merging into the mainline tree. After the two weeks, the @@ -69,9 +48,33 @@ rc2 is released. This repeats on a roughly weekly basis until rc7 state of churn), and a week after the last vX.Y-rcN was done, the official vX.Y is released. -Relating that to netdev: At the beginning of the 2-week merge window, -the ``net-next`` tree will be closed - no new changes/features. The -accumulated new content of the past ~10 weeks will be passed onto +To find out where we are now in the cycle - load the mainline (Linus) +page here: + + https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git + +and note the top of the "tags" section. If it is rc1, it is early in +the dev cycle. If it was tagged rc7 a week ago, then a release is +probably imminent. If the most recent tag is a final release tag +(without an ``-rcN`` suffix) - we are most likely in a merge window +and ``net-next`` is closed. + +git trees and patch flow +------------------------ + +There are two networking trees (git repositories) in play. Both are +driven by David Miller, the main network maintainer. There is the +``net`` tree, and the ``net-next`` tree. As you can probably guess from +the names, the ``net`` tree is for fixes to existing code already in the +mainline tree from Linus, and ``net-next`` is where the new code goes +for the future release. You can find the trees here: + +- https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git +- https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git + +Relating that to kernel development: At the beginning of the 2-week +merge window, the ``net-next`` tree will be closed - no new changes/features. +The accumulated new content of the past ~10 weeks will be passed onto mainline/Linus via a pull request for vX.Y -- at the same time, the ``net`` tree will start accumulating fixes for this pulled content relating to vX.Y @@ -103,22 +106,14 @@ focus for ``net`` is on stabilization and bug fixes. Finally, the vX.Y gets released, and the whole cycle starts over. -So where are we now in this cycle? ----------------------------------- +netdev patch review +------------------- -Load the mainline (Linus) page here: +Patch status +~~~~~~~~~~~~ - https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git - -and note the top of the "tags" section. If it is rc1, it is early in -the dev cycle. If it was tagged rc7 a week ago, then a release is -probably imminent. If the most recent tag is a final release tag -(without an ``-rcN`` suffix) - we are most likely in a merge window -and ``net-next`` is closed. - -How can I tell the status of a patch I've sent? ------------------------------------------------ -Start by looking at the main patchworks queue for netdev: +Status of a patch can be checked by looking at the main patchwork +queue for netdev: https://patchwork.kernel.org/project/netdevbpf/list/ @@ -127,73 +122,141 @@ patch. Patches are indexed by the ``Message-ID`` header of the emails which carried them so if you have trouble finding your patch append the value of ``Message-ID`` to the URL above. -How long before my patch is accepted? -------------------------------------- -Generally speaking, the patches get triaged quickly (in less than -48h). But be patient, if your patch is active in patchwork (i.e. it's -listed on the project's patch list) the chances it was missed are close to zero. -Asking the maintainer for status updates on your -patch is a good way to ensure your patch is ignored or pushed to the -bottom of the priority list. +Updating patch status +~~~~~~~~~~~~~~~~~~~~~ -Should I directly update patchwork state of my own patches? ------------------------------------------------------------ It may be tempting to help the maintainers and update the state of your -own patches when you post a new version or spot a bug. Please do not do that. +own patches when you post a new version or spot a bug. Please **do not** +do that. Interfering with the patch status on patchwork will only cause confusion. Leave it to the maintainer to figure out what is the most recent and current version that should be applied. If there is any doubt, the maintainer will reply and ask what should be done. -How do I divide my work into patches? -------------------------------------- +Review timelines +~~~~~~~~~~~~~~~~ -Put yourself in the shoes of the reviewer. Each patch is read separately -and therefore should constitute a comprehensible step towards your stated -goal. +Generally speaking, the patches get triaged quickly (in less than +48h). But be patient, if your patch is active in patchwork (i.e. it's +listed on the project's patch list) the chances it was missed are close to zero. +Asking the maintainer for status updates on your +patch is a good way to ensure your patch is ignored or pushed to the +bottom of the priority list. -Avoid sending series longer than 15 patches. Larger series takes longer -to review as reviewers will defer looking at it until they find a large -chunk of time. A small series can be reviewed in a short time, so Maintainers -just do it. As a result, a sequence of smaller series gets merged quicker and -with better review coverage. Re-posting large series also increases the mailing -list traffic. +Partial resends +~~~~~~~~~~~~~~~ -I made changes to only a few patches in a patch series should I resend only those changed? ------------------------------------------------------------------------------------------- -No, please resend the entire patch series and make sure you do number your +Please always resend the entire patch series and make sure you do number your patches such that it is clear this is the latest and greatest set of patches -that can be applied. - -I have received review feedback, when should I post a revised version of the patches? -------------------------------------------------------------------------------------- -Allow at least 24 hours to pass between postings. This will ensure reviewers -from all geographical locations have a chance to chime in. Do not wait -too long (weeks) between postings either as it will make it harder for reviewers -to recall all the context. +that can be applied. Do not try to resend just the patches which changed. -Make sure you address all the feedback in your new posting. Do not post a new -version of the code if the discussion about the previous version is still -ongoing, unless directly instructed by a reviewer. +Handling misapplied patches +~~~~~~~~~~~~~~~~~~~~~~~~~~~ -I submitted multiple versions of a patch series and it looks like a version other than the last one has been accepted, what should I do? ----------------------------------------------------------------------------------------------------------------------------------------- +Occasionally a patch series gets applied before receiving critical feedback, +or the wrong version of a series gets applied. There is no revert possible, once it is pushed out, it stays like that. Please send incremental versions on top of what has been merged in order to fix the patches the way they would look like if your latest patch series was to be merged. -Are there special rules regarding stable submissions on netdev? ---------------------------------------------------------------- +Stable tree +~~~~~~~~~~~ + While it used to be the case that netdev submissions were not supposed to carry explicit ``CC: stable@vger.kernel.org`` tags that is no longer the case today. Please follow the standard stable rules in :ref:`Documentation/process/stable-kernel-rules.rst `, and make sure you include appropriate Fixes tags! -Is the comment style convention different for the networking content? ---------------------------------------------------------------------- -Yes, in a largely trivial way. Instead of this:: +Security fixes +~~~~~~~~~~~~~~ + +Do not email netdev maintainers directly if you think you discovered +a bug that might have possible security implications. +The current netdev maintainer has consistently requested that +people use the mailing lists and not reach out directly. If you aren't +OK with that, then perhaps consider mailing security@kernel.org or +reading about http://oss-security.openwall.org/wiki/mailing-lists/distros +as possible alternative mechanisms. + + +Co-posting changes to user space components +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +User space code exercising kernel features should be posted +alongside kernel patches. This gives reviewers a chance to see +how any new interface is used and how well it works. + +When user space tools reside in the kernel repo itself all changes +should generally come as one series. If series becomes too large +or the user space project is not reviewed on netdev include a link +to a public repo where user space patches can be seen. + +In case user space tooling lives in a separate repository but is +reviewed on netdev (e.g. patches to ``iproute2`` tools) kernel and +user space patches should form separate series (threads) when posted +to the mailing list, e.g.:: + + [PATCH net-next 0/3] net: some feature cover letter + └─ [PATCH net-next 1/3] net: some feature prep + └─ [PATCH net-next 2/3] net: some feature do it + └─ [PATCH net-next 3/3] selftest: net: some feature + + [PATCH iproute2-next] ip: add support for some feature + +Posting as one thread is discouraged because it confuses patchwork +(as of patchwork 2.2.2). + +Preparing changes +----------------- + +Attention to detail is important. Re-read your own work as if you were the +reviewer. You can start with using ``checkpatch.pl``, perhaps even with +the ``--strict`` flag. But do not be mindlessly robotic in doing so. +If your change is a bug fix, make sure your commit log indicates the +end-user visible symptom, the underlying reason as to why it happens, +and then if necessary, explain why the fix proposed is the best way to +get things done. Don't mangle whitespace, and as is common, don't +mis-indent function arguments that span multiple lines. If it is your +first patch, mail it to yourself so you can test apply it to an +unpatched tree to confirm infrastructure didn't mangle it. + +Finally, go back and read +:ref:`Documentation/process/submitting-patches.rst ` +to be sure you are not repeating some common mistake documented there. + +Indicating target tree +~~~~~~~~~~~~~~~~~~~~~~ + +To help maintainers and CI bots you should explicitly mark which tree +your patch is targeting. Assuming that you use git, use the prefix +flag:: + + git format-patch --subject-prefix='PATCH net-next' start..finish + +Use ``net`` instead of ``net-next`` (always lower case) in the above for +bug-fix ``net`` content. + +Dividing work into patches +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Put yourself in the shoes of the reviewer. Each patch is read separately +and therefore should constitute a comprehensible step towards your stated +goal. + +Avoid sending series longer than 15 patches. Larger series takes longer +to review as reviewers will defer looking at it until they find a large +chunk of time. A small series can be reviewed in a short time, so Maintainers +just do it. As a result, a sequence of smaller series gets merged quicker and +with better review coverage. Re-posting large series also increases the mailing +list traffic. + +Multi-line comments +~~~~~~~~~~~~~~~~~~~ + +Comment style convention is slightly different for networking and most of +the tree. Instead of this:: /* * foobar blah blah blah @@ -206,8 +269,8 @@ it is requested that you make it look like this:: * another line of text */ -What is "reverse xmas tree"? ----------------------------- +Local variable ordering ("reverse xmas tree", "RCS") +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Netdev has a convention for ordering local variables in functions. Order the variable declaration lines longest to shortest, e.g.:: @@ -219,21 +282,31 @@ Order the variable declaration lines longest to shortest, e.g.:: If there are dependencies between the variables preventing the ordering move the initialization out of line. -I am working in existing code which uses non-standard formatting. Which formatting should I use? ------------------------------------------------------------------------------------------------- -Make your code follow the most recent guidelines, so that eventually all code +Format precedence +~~~~~~~~~~~~~~~~~ + +When working in existing code which uses nonstandard formatting make +your code follow the most recent guidelines, so that eventually all code in the domain of netdev is in the preferred format. -I found a bug that might have possible security implications or similar. Should I mail the main netdev maintainer off-list? ---------------------------------------------------------------------------------------------------------------------------- -No. The current netdev maintainer has consistently requested that -people use the mailing lists and not reach out directly. If you aren't -OK with that, then perhaps consider mailing security@kernel.org or -reading about http://oss-security.openwall.org/wiki/mailing-lists/distros -as possible alternative mechanisms. +Resending after review +~~~~~~~~~~~~~~~~~~~~~~ + +Allow at least 24 hours to pass between postings. This will ensure reviewers +from all geographical locations have a chance to chime in. Do not wait +too long (weeks) between postings either as it will make it harder for reviewers +to recall all the context. + +Make sure you address all the feedback in your new posting. Do not post a new +version of the code if the discussion about the previous version is still +ongoing, unless directly instructed by a reviewer. + +Testing +------- + +Expected level of testing +~~~~~~~~~~~~~~~~~~~~~~~~~ -What level of testing is expected before I submit my change? ------------------------------------------------------------- At the very minimum your changes must survive an ``allyesconfig`` and an ``allmodconfig`` build with ``W=1`` set without new warnings or failures. @@ -244,86 +317,42 @@ and the patch series contains a set of kernel selftest for You are expected to test your changes on top of the relevant networking tree (``net`` or ``net-next``) and not e.g. a stable tree or ``linux-next``. -How do I post corresponding changes to user space components? -------------------------------------------------------------- -User space code exercising kernel features should be posted -alongside kernel patches. This gives reviewers a chance to see -how any new interface is used and how well it works. - -When user space tools reside in the kernel repo itself all changes -should generally come as one series. If series becomes too large -or the user space project is not reviewed on netdev include a link -to a public repo where user space patches can be seen. - -In case user space tooling lives in a separate repository but is -reviewed on netdev (e.g. patches to ``iproute2`` tools) kernel and -user space patches should form separate series (threads) when posted -to the mailing list, e.g.:: - - [PATCH net-next 0/3] net: some feature cover letter - └─ [PATCH net-next 1/3] net: some feature prep - └─ [PATCH net-next 2/3] net: some feature do it - └─ [PATCH net-next 3/3] selftest: net: some feature - - [PATCH iproute2-next] ip: add support for some feature - -Posting as one thread is discouraged because it confuses patchwork -(as of patchwork 2.2.2). - -Can I reproduce the checks from patchwork on my local machine? --------------------------------------------------------------- +patchwork checks +~~~~~~~~~~~~~~~~ Checks in patchwork are mostly simple wrappers around existing kernel scripts, the sources are available at: https://github.com/kuba-moo/nipa/tree/master/tests -Running all the builds and checks locally is a pain, can I post my patches and have the patchwork bot validate them? --------------------------------------------------------------------------------------------------------------------- - -No, you must ensure that your patches are ready by testing them locally +**Do not** post your patches just to run them through the checks. +You must ensure that your patches are ready by testing them locally before posting to the mailing list. The patchwork build bot instance gets overloaded very easily and netdev@vger really doesn't need more traffic if we can help it. -netdevsim is great, can I extend it for my out-of-tree tests? -------------------------------------------------------------- +netdevsim +~~~~~~~~~ -No, ``netdevsim`` is a test vehicle solely for upstream tests. -(Please add your tests under ``tools/testing/selftests/``.) +``netdevsim`` is a test driver which can be used to exercise driver +configuration APIs without requiring capable hardware. +Mock-ups and tests based on ``netdevsim`` are strongly encouraged when +adding new APIs, but ``netdevsim`` in itself is **not** considered +a use case/user. You must also implement the new APIs in a real driver. -We also give no guarantees that ``netdevsim`` won't change in the future +We give no guarantees that ``netdevsim`` won't change in the future in a way which would break what would normally be considered uAPI. -Is netdevsim considered a "user" of an API? -------------------------------------------- - -Linux kernel has a long standing rule that no API should be added unless -it has a real, in-tree user. Mock-ups and tests based on ``netdevsim`` are -strongly encouraged when adding new APIs, but ``netdevsim`` in itself -is **not** considered a use case/user. - -Any other tips to help ensure my net/net-next patch gets OK'd? --------------------------------------------------------------- -Attention to detail. Re-read your own work as if you were the -reviewer. You can start with using ``checkpatch.pl``, perhaps even with -the ``--strict`` flag. But do not be mindlessly robotic in doing so. -If your change is a bug fix, make sure your commit log indicates the -end-user visible symptom, the underlying reason as to why it happens, -and then if necessary, explain why the fix proposed is the best way to -get things done. Don't mangle whitespace, and as is common, don't -mis-indent function arguments that span multiple lines. If it is your -first patch, mail it to yourself so you can test apply it to an -unpatched tree to confirm infrastructure didn't mangle it. - -Finally, go back and read -:ref:`Documentation/process/submitting-patches.rst ` -to be sure you are not repeating some common mistake documented there. +``netdevsim`` is reserved for use by upstream tests only, so any +new ``netdevsim`` features must be accompanied by selftests under +``tools/testing/selftests/``. -My company uses peer feedback in employee performance reviews. Can I ask netdev maintainers for feedback? ---------------------------------------------------------------------------------------------------------- +Testimonials / feedback +----------------------- -Yes, especially if you spend significant amount of time reviewing code +Some companies use peer feedback in employee performance reviews. +Please feel free to request feedback from netdev maintainers, +especially if you spend significant amount of time reviewing code and go out of your way to improve shared infrastructure. The feedback must be requested by you, the contributor, and will always diff --git a/Documentation/s390/pci.rst b/Documentation/s390/pci.rst index 8157f0cddbc248cb197172c19222c20dbddf8fed..a1a72a47dc96060ea31a0b01340c2c70d4ed6a1c 100644 --- a/Documentation/s390/pci.rst +++ b/Documentation/s390/pci.rst @@ -51,7 +51,7 @@ Entries specific to zPCI functions and entries that hold zPCI information. The slot entries are set up using the function identifier (FID) of the PCI function. The format depicted as XXXXXXXX above is 8 hexadecimal digits - with 0 padding and lower case hexadecimal digitis. + with 0 padding and lower case hexadecimal digits. - /sys/bus/pci/slots/XXXXXXXX/power @@ -66,7 +66,7 @@ Entries specific to zPCI functions and entries that hold zPCI information. - function_handle Low-level identifier used for a configured PCI function. - It might be useful for debuging. + It might be useful for debugging. - pchid Model-dependent location of the I/O adapter. diff --git a/Documentation/s390/vfio-ccw.rst b/Documentation/s390/vfio-ccw.rst index ea928a3806f43f8f6133e8e8e7d657da699250e1..37026fa181794b0951440577747015af0520cbb8 100644 --- a/Documentation/s390/vfio-ccw.rst +++ b/Documentation/s390/vfio-ccw.rst @@ -176,7 +176,7 @@ The process of how these work together. Use the 'mdev_create' sysfs file, we need to manually create one (and only one for our case) mediated device. 3. vfio_mdev.ko drives the mediated ccw device. - vfio_mdev is also the vfio device drvier. It will probe the mdev and + vfio_mdev is also the vfio device driver. It will probe the mdev and add it to an iommu_group and a vfio_group. Then we could pass through the mdev to a guest. @@ -219,8 +219,8 @@ values may occur: The operation was successful. ``-EOPNOTSUPP`` - The orb specified transport mode or an unidentified IDAW format, or the - scsw specified a function other than the start function. + The ORB specified transport mode or the + SCSW specified a function other than the start function. ``-EIO`` A request was issued while the device was not in a state ready to accept diff --git a/Documentation/scheduler/index.rst b/Documentation/scheduler/index.rst index b430d856056a05df276c79da02754fe2e899c1fa..f12d0d06de3a451b228d9f851cee820c5e513ff2 100644 --- a/Documentation/scheduler/index.rst +++ b/Documentation/scheduler/index.rst @@ -15,6 +15,7 @@ Linux Scheduler sched-capacity sched-energy schedutil + sched-util-clamp sched-nice-design sched-rt-group sched-stats diff --git a/Documentation/scheduler/sched-util-clamp.rst b/Documentation/scheduler/sched-util-clamp.rst new file mode 100644 index 0000000000000000000000000000000000000000..74d5b7c6431d1a5ef0bdb8d388ec9c02bb5804b6 --- /dev/null +++ b/Documentation/scheduler/sched-util-clamp.rst @@ -0,0 +1,741 @@ +.. SPDX-License-Identifier: GPL-2.0 + +==================== +Utilization Clamping +==================== + +1. Introduction +=============== + +Utilization clamping, also known as util clamp or uclamp, is a scheduler +feature that allows user space to help in managing the performance requirement +of tasks. It was introduced in v5.3 release. The CGroup support was merged in +v5.4. + +Uclamp is a hinting mechanism that allows the scheduler to understand the +performance requirements and restrictions of the tasks, thus it helps the +scheduler to make a better decision. And when schedutil cpufreq governor is +used, util clamp will influence the CPU frequency selection as well. + +Since the scheduler and schedutil are both driven by PELT (util_avg) signals, +util clamp acts on that to achieve its goal by clamping the signal to a certain +point; hence the name. That is, by clamping utilization we are making the +system run at a certain performance point. + +The right way to view util clamp is as a mechanism to make request or hint on +performance constraints. It consists of two tunables: + + * UCLAMP_MIN, which sets the lower bound. + * UCLAMP_MAX, which sets the upper bound. + +These two bounds will ensure a task will operate within this performance range +of the system. UCLAMP_MIN implies boosting a task, while UCLAMP_MAX implies +capping a task. + +One can tell the system (scheduler) that some tasks require a minimum +performance point to operate at to deliver the desired user experience. Or one +can tell the system that some tasks should be restricted from consuming too +much resources and should not go above a specific performance point. Viewing +the uclamp values as performance points rather than utilization is a better +abstraction from user space point of view. + +As an example, a game can use util clamp to form a feedback loop with its +perceived Frames Per Second (FPS). It can dynamically increase the minimum +performance point required by its display pipeline to ensure no frame is +dropped. It can also dynamically 'prime' up these tasks if it knows in the +coming few hundred milliseconds a computationally intensive scene is about to +happen. + +On mobile hardware where the capability of the devices varies a lot, this +dynamic feedback loop offers a great flexibility to ensure best user experience +given the capabilities of any system. + +Of course a static configuration is possible too. The exact usage will depend +on the system, application and the desired outcome. + +Another example is in Android where tasks are classified as background, +foreground, top-app, etc. Util clamp can be used to constrain how much +resources background tasks are consuming by capping the performance point they +can run at. This constraint helps reserve resources for important tasks, like +the ones belonging to the currently active app (top-app group). Beside this +helps in limiting how much power they consume. This can be more obvious in +heterogeneous systems (e.g. Arm big.LITTLE); the constraint will help bias the +background tasks to stay on the little cores which will ensure that: + + 1. The big cores are free to run top-app tasks immediately. top-app + tasks are the tasks the user is currently interacting with, hence + the most important tasks in the system. + 2. They don't run on a power hungry core and drain battery even if they + are CPU intensive tasks. + +.. note:: + **little cores**: + CPUs with capacity < 1024 + + **big cores**: + CPUs with capacity = 1024 + +By making these uclamp performance requests, or rather hints, user space can +ensure system resources are used optimally to deliver the best possible user +experience. + +Another use case is to help with **overcoming the ramp up latency inherit in +how scheduler utilization signal is calculated**. + +On the other hand, a busy task for instance that requires to run at maximum +performance point will suffer a delay of ~200ms (PELT HALFIFE = 32ms) for the +scheduler to realize that. This is known to affect workloads like gaming on +mobile devices where frames will drop due to slow response time to select the +higher frequency required for the tasks to finish their work in time. Setting +UCLAMP_MIN=1024 will ensure such tasks will always see the highest performance +level when they start running. + +The overall visible effect goes beyond better perceived user +experience/performance and stretches to help achieve a better overall +performance/watt if used effectively. + +User space can form a feedback loop with the thermal subsystem too to ensure +the device doesn't heat up to the point where it will throttle. + +Both SCHED_NORMAL/OTHER and SCHED_FIFO/RR honour uclamp requests/hints. + +In the SCHED_FIFO/RR case, uclamp gives the option to run RT tasks at any +performance point rather than being tied to MAX frequency all the time. Which +can be useful on general purpose systems that run on battery powered devices. + +Note that by design RT tasks don't have per-task PELT signal and must always +run at a constant frequency to combat undeterministic DVFS rampup delays. + +Note that using schedutil always implies a single delay to modify the frequency +when an RT task wakes up. This cost is unchanged by using uclamp. Uclamp only +helps picking what frequency to request instead of schedutil always requesting +MAX for all RT tasks. + +See :ref:`section 3.4 ` for default values and +:ref:`3.4.1 ` on how to change RT tasks +default value. + +2. Design +========= + +Util clamp is a property of every task in the system. It sets the boundaries of +its utilization signal; acting as a bias mechanism that influences certain +decisions within the scheduler. + +The actual utilization signal of a task is never clamped in reality. If you +inspect PELT signals at any point of time you should continue to see them as +they are intact. Clamping happens only when needed, e.g: when a task wakes up +and the scheduler needs to select a suitable CPU for it to run on. + +Since the goal of util clamp is to allow requesting a minimum and maximum +performance point for a task to run on, it must be able to influence the +frequency selection as well as task placement to be most effective. Both of +which have implications on the utilization value at CPU runqueue (rq for short) +level, which brings us to the main design challenge. + +When a task wakes up on an rq, the utilization signal of the rq will be +affected by the uclamp settings of all the tasks enqueued on it. For example if +a task requests to run at UTIL_MIN = 512, then the util signal of the rq needs +to respect to this request as well as all other requests from all of the +enqueued tasks. + +To be able to aggregate the util clamp value of all the tasks attached to the +rq, uclamp must do some housekeeping at every enqueue/dequeue, which is the +scheduler hot path. Hence care must be taken since any slow down will have +significant impact on a lot of use cases and could hinder its usability in +practice. + +The way this is handled is by dividing the utilization range into buckets +(struct uclamp_bucket) which allows us to reduce the search space from every +task on the rq to only a subset of tasks on the top-most bucket. + +When a task is enqueued, the counter in the matching bucket is incremented, +and on dequeue it is decremented. This makes keeping track of the effective +uclamp value at rq level a lot easier. + +As tasks are enqueued and dequeued, we keep track of the current effective +uclamp value of the rq. See :ref:`section 2.1 ` for details on +how this works. + +Later at any path that wants to identify the effective uclamp value of the rq, +it will simply need to read this effective uclamp value of the rq at that exact +moment of time it needs to take a decision. + +For task placement case, only Energy Aware and Capacity Aware Scheduling +(EAS/CAS) make use of uclamp for now, which implies that it is applied on +heterogeneous systems only. +When a task wakes up, the scheduler will look at the current effective uclamp +value of every rq and compare it with the potential new value if the task were +to be enqueued there. Favoring the rq that will end up with the most energy +efficient combination. + +Similarly in schedutil, when it needs to make a frequency update it will look +at the current effective uclamp value of the rq which is influenced by the set +of tasks currently enqueued there and select the appropriate frequency that +will satisfy constraints from requests. + +Other paths like setting overutilization state (which effectively disables EAS) +make use of uclamp as well. Such cases are considered necessary housekeeping to +allow the 2 main use cases above and will not be covered in detail here as they +could change with implementation details. + +.. _uclamp-buckets: + +2.1. Buckets +------------ + +:: + + [struct rq] + + (bottom) (top) + + 0 1024 + | | + +-----------+-----------+-----------+---- ----+-----------+ + | Bucket 0 | Bucket 1 | Bucket 2 | ... | Bucket N | + +-----------+-----------+-----------+---- ----+-----------+ + : : : + +- p0 +- p3 +- p4 + : : + +- p1 +- p5 + : + +- p2 + + +.. note:: + The diagram above is an illustration rather than a true depiction of the + internal data structure. + +To reduce the search space when trying to decide the effective uclamp value of +an rq as tasks are enqueued/dequeued, the whole utilization range is divided +into N buckets where N is configured at compile time by setting +CONFIG_UCLAMP_BUCKETS_COUNT. By default it is set to 5. + +The rq has a bucket for each uclamp_id tunables: [UCLAMP_MIN, UCLAMP_MAX]. + +The range of each bucket is 1024/N. For example, for the default value of +5 there will be 5 buckets, each of which will cover the following range: + +:: + + DELTA = round_closest(1024/5) = 204.8 = 205 + + Bucket 0: [0:204] + Bucket 1: [205:409] + Bucket 2: [410:614] + Bucket 3: [615:819] + Bucket 4: [820:1024] + +When a task p with following tunable parameters + +:: + + p->uclamp[UCLAMP_MIN] = 300 + p->uclamp[UCLAMP_MAX] = 1024 + +is enqueued into the rq, bucket 1 will be incremented for UCLAMP_MIN and bucket +4 will be incremented for UCLAMP_MAX to reflect the fact the rq has a task in +this range. + +The rq then keeps track of its current effective uclamp value for each +uclamp_id. + +When a task p is enqueued, the rq value changes to: + +:: + + // update bucket logic goes here + rq->uclamp[UCLAMP_MIN] = max(rq->uclamp[UCLAMP_MIN], p->uclamp[UCLAMP_MIN]) + // repeat for UCLAMP_MAX + +Similarly, when p is dequeued the rq value changes to: + +:: + + // update bucket logic goes here + rq->uclamp[UCLAMP_MIN] = search_top_bucket_for_highest_value() + // repeat for UCLAMP_MAX + +When all buckets are empty, the rq uclamp values are reset to system defaults. +See :ref:`section 3.4 ` for details on default values. + + +2.2. Max aggregation +-------------------- + +Util clamp is tuned to honour the request for the task that requires the +highest performance point. + +When multiple tasks are attached to the same rq, then util clamp must make sure +the task that needs the highest performance point gets it even if there's +another task that doesn't need it or is disallowed from reaching this point. + +For example, if there are multiple tasks attached to an rq with the following +values: + +:: + + p0->uclamp[UCLAMP_MIN] = 300 + p0->uclamp[UCLAMP_MAX] = 900 + + p1->uclamp[UCLAMP_MIN] = 500 + p1->uclamp[UCLAMP_MAX] = 500 + +then assuming both p0 and p1 are enqueued to the same rq, both UCLAMP_MIN +and UCLAMP_MAX become: + +:: + + rq->uclamp[UCLAMP_MIN] = max(300, 500) = 500 + rq->uclamp[UCLAMP_MAX] = max(900, 500) = 900 + +As we shall see in :ref:`section 5.1 `, this max +aggregation is the cause of one of limitations when using util clamp, in +particular for UCLAMP_MAX hint when user space would like to save power. + +2.3. Hierarchical aggregation +----------------------------- + +As stated earlier, util clamp is a property of every task in the system. But +the actual applied (effective) value can be influenced by more than just the +request made by the task or another actor on its behalf (middleware library). + +The effective util clamp value of any task is restricted as follows: + + 1. By the uclamp settings defined by the cgroup CPU controller it is attached + to, if any. + 2. The restricted value in (1) is then further restricted by the system wide + uclamp settings. + +:ref:`Section 3 ` discusses the interfaces and will expand +further on that. + +For now suffice to say that if a task makes a request, its actual effective +value will have to adhere to some restrictions imposed by cgroup and system +wide settings. + +The system will still accept the request even if effectively will be beyond the +constraints, but as soon as the task moves to a different cgroup or a sysadmin +modifies the system settings, the request will be satisfied only if it is +within new constraints. + +In other words, this aggregation will not cause an error when a task changes +its uclamp values, but rather the system may not be able to satisfy requests +based on those factors. + +2.4. Range +---------- + +Uclamp performance request has the range of 0 to 1024 inclusive. + +For cgroup interface percentage is used (that is 0 to 100 inclusive). +Just like other cgroup interfaces, you can use 'max' instead of 100. + +.. _uclamp-interfaces: + +3. Interfaces +============= + +3.1. Per task interface +----------------------- + +sched_setattr() syscall was extended to accept two new fields: + +* sched_util_min: requests the minimum performance point the system should run + at when this task is running. Or lower performance bound. +* sched_util_max: requests the maximum performance point the system should run + at when this task is running. Or upper performance bound. + +For example, the following scenario have 40% to 80% utilization constraints: + +:: + + attr->sched_util_min = 40% * 1024; + attr->sched_util_max = 80% * 1024; + +When task @p is running, **the scheduler should try its best to ensure it +starts at 40% performance level**. If the task runs for a long enough time so +that its actual utilization goes above 80%, the utilization, or performance +level, will be capped. + +The special value -1 is used to reset the uclamp settings to the system +default. + +Note that resetting the uclamp value to system default using -1 is not the same +as manually setting uclamp value to system default. This distinction is +important because as we shall see in system interfaces, the default value for +RT could be changed. SCHED_NORMAL/OTHER might gain similar knobs too in the +future. + +3.2. cgroup interface +--------------------- + +There are two uclamp related values in the CPU cgroup controller: + +* cpu.uclamp.min +* cpu.uclamp.max + +When a task is attached to a CPU controller, its uclamp values will be impacted +as follows: + +* cpu.uclamp.min is a protection as described in :ref:`section 3-3 of cgroup + v2 documentation `. + + If a task uclamp_min value is lower than cpu.uclamp.min, then the task will + inherit the cgroup cpu.uclamp.min value. + + In a cgroup hierarchy, effective cpu.uclamp.min is the max of (child, + parent). + +* cpu.uclamp.max is a limit as described in :ref:`section 3-2 of cgroup v2 + documentation `. + + If a task uclamp_max value is higher than cpu.uclamp.max, then the task will + inherit the cgroup cpu.uclamp.max value. + + In a cgroup hierarchy, effective cpu.uclamp.max is the min of (child, + parent). + +For example, given following parameters: + +:: + + p0->uclamp[UCLAMP_MIN] = // system default; + p0->uclamp[UCLAMP_MAX] = // system default; + + p1->uclamp[UCLAMP_MIN] = 40% * 1024; + p1->uclamp[UCLAMP_MAX] = 50% * 1024; + + cgroup0->cpu.uclamp.min = 20% * 1024; + cgroup0->cpu.uclamp.max = 60% * 1024; + + cgroup1->cpu.uclamp.min = 60% * 1024; + cgroup1->cpu.uclamp.max = 100% * 1024; + +when p0 and p1 are attached to cgroup0, the values become: + +:: + + p0->uclamp[UCLAMP_MIN] = cgroup0->cpu.uclamp.min = 20% * 1024; + p0->uclamp[UCLAMP_MAX] = cgroup0->cpu.uclamp.max = 60% * 1024; + + p1->uclamp[UCLAMP_MIN] = 40% * 1024; // intact + p1->uclamp[UCLAMP_MAX] = 50% * 1024; // intact + +when p0 and p1 are attached to cgroup1, these instead become: + +:: + + p0->uclamp[UCLAMP_MIN] = cgroup1->cpu.uclamp.min = 60% * 1024; + p0->uclamp[UCLAMP_MAX] = cgroup1->cpu.uclamp.max = 100% * 1024; + + p1->uclamp[UCLAMP_MIN] = cgroup1->cpu.uclamp.min = 60% * 1024; + p1->uclamp[UCLAMP_MAX] = 50% * 1024; // intact + +Note that cgroup interfaces allows cpu.uclamp.max value to be lower than +cpu.uclamp.min. Other interfaces don't allow that. + +3.3. System interface +--------------------- + +3.3.1 sched_util_clamp_min +-------------------------- + +System wide limit of allowed UCLAMP_MIN range. By default it is set to 1024, +which means that permitted effective UCLAMP_MIN range for tasks is [0:1024]. +By changing it to 512 for example the range reduces to [0:512]. This is useful +to restrict how much boosting tasks are allowed to acquire. + +Requests from tasks to go above this knob value will still succeed, but +they won't be satisfied until it is more than p->uclamp[UCLAMP_MIN]. + +The value must be smaller than or equal to sched_util_clamp_max. + +3.3.2 sched_util_clamp_max +-------------------------- + +System wide limit of allowed UCLAMP_MAX range. By default it is set to 1024, +which means that permitted effective UCLAMP_MAX range for tasks is [0:1024]. + +By changing it to 512 for example the effective allowed range reduces to +[0:512]. This means is that no task can run above 512, which implies that all +rqs are restricted too. IOW, the whole system is capped to half its performance +capacity. + +This is useful to restrict the overall maximum performance point of the system. +For example, it can be handy to limit performance when running low on battery +or when the system wants to limit access to more energy hungry performance +levels when it's in idle state or screen is off. + +Requests from tasks to go above this knob value will still succeed, but they +won't be satisfied until it is more than p->uclamp[UCLAMP_MAX]. + +The value must be greater than or equal to sched_util_clamp_min. + +.. _uclamp-default-values: + +3.4. Default values +------------------- + +By default all SCHED_NORMAL/SCHED_OTHER tasks are initialized to: + +:: + + p_fair->uclamp[UCLAMP_MIN] = 0 + p_fair->uclamp[UCLAMP_MAX] = 1024 + +That is, by default they're boosted to run at the maximum performance point of +changed at boot or runtime. No argument was made yet as to why we should +provide this, but can be added in the future. + +For SCHED_FIFO/SCHED_RR tasks: + +:: + + p_rt->uclamp[UCLAMP_MIN] = 1024 + p_rt->uclamp[UCLAMP_MAX] = 1024 + +That is by default they're boosted to run at the maximum performance point of +the system which retains the historical behavior of the RT tasks. + +RT tasks default uclamp_min value can be modified at boot or runtime via +sysctl. See below section. + +.. _sched-util-clamp-min-rt-default: + +3.4.1 sched_util_clamp_min_rt_default +------------------------------------- + +Running RT tasks at maximum performance point is expensive on battery powered +devices and not necessary. To allow system developer to offer good performance +guarantees for these tasks without pushing it all the way to maximum +performance point, this sysctl knob allows tuning the best boost value to +address the system requirement without burning power running at maximum +performance point all the time. + +Application developer are encouraged to use the per task util clamp interface +to ensure they are performance and power aware. Ideally this knob should be set +to 0 by system designers and leave the task of managing performance +requirements to the apps. + +4. How to use util clamp +======================== + +Util clamp promotes the concept of user space assisted power and performance +management. At the scheduler level there is no info required to make the best +decision. However, with util clamp user space can hint to the scheduler to make +better decision about task placement and frequency selection. + +Best results are achieved by not making any assumptions about the system the +application is running on and to use it in conjunction with a feedback loop to +dynamically monitor and adjust. Ultimately this will allow for a better user +experience at a better perf/watt. + +For some systems and use cases, static setup will help to achieve good results. +Portability will be a problem in this case. How much work one can do at 100, +200 or 1024 is different for each system. Unless there's a specific target +system, static setup should be avoided. + +There are enough possibilities to create a whole framework based on util clamp +or self contained app that makes use of it directly. + +4.1. Boost important and DVFS-latency-sensitive tasks +----------------------------------------------------- + +A GUI task might not be busy to warrant driving the frequency high when it +wakes up. However, it requires to finish its work within a specific time window +to deliver the desired user experience. The right frequency it requires at +wakeup will be system dependent. On some underpowered systems it will be high, +on other overpowered ones it will be low or 0. + +This task can increase its UCLAMP_MIN value every time it misses the deadline +to ensure on next wake up it runs at a higher performance point. It should try +to approach the lowest UCLAMP_MIN value that allows to meet its deadline on any +particular system to achieve the best possible perf/watt for that system. + +On heterogeneous systems, it might be important for this task to run on +a faster CPU. + +**Generally it is advised to perceive the input as performance level or point +which will imply both task placement and frequency selection**. + +4.2. Cap background tasks +------------------------- + +Like explained for Android case in the introduction. Any app can lower +UCLAMP_MAX for some background tasks that don't care about performance but +could end up being busy and consume unnecessary system resources on the system. + +4.3. Powersave mode +------------------- + +sched_util_clamp_max system wide interface can be used to limit all tasks from +operating at the higher performance points which are usually energy +inefficient. + +This is not unique to uclamp as one can achieve the same by reducing max +frequency of the cpufreq governor. It can be considered a more convenient +alternative interface. + +4.4. Per-app performance restriction +------------------------------------ + +Middleware/Utility can provide the user an option to set UCLAMP_MIN/MAX for an +app every time it is executed to guarantee a minimum performance point and/or +limit it from draining system power at the cost of reduced performance for +these apps. + +If you want to prevent your laptop from heating up while on the go from +compiling the kernel and happy to sacrifice performance to save power, but +still would like to keep your browser performance intact, uclamp makes it +possible. + +5. Limitations +============== + +.. _uclamp-capping-fail: + +5.1. Capping frequency with uclamp_max fails under certain conditions +--------------------------------------------------------------------- + +If task p0 is capped to run at 512: + +:: + + p0->uclamp[UCLAMP_MAX] = 512 + +and it shares the rq with p1 which is free to run at any performance point: + +:: + + p1->uclamp[UCLAMP_MAX] = 1024 + +then due to max aggregation the rq will be allowed to reach max performance +point: + +:: + + rq->uclamp[UCLAMP_MAX] = max(512, 1024) = 1024 + +Assuming both p0 and p1 have UCLAMP_MIN = 0, then the frequency selection for +the rq will depend on the actual utilization value of the tasks. + +If p1 is a small task but p0 is a CPU intensive task, then due to the fact that +both are running at the same rq, p1 will cause the frequency capping to be left +from the rq although p1, which is allowed to run at any performance point, +doesn't actually need to run at that frequency. + +5.2. UCLAMP_MAX can break PELT (util_avg) signal +------------------------------------------------ + +PELT assumes that frequency will always increase as the signals grow to ensure +there's always some idle time on the CPU. But with UCLAMP_MAX, this frequency +increase will be prevented which can lead to no idle time in some +circumstances. When there's no idle time, a task will stuck in a busy loop, +which would result in util_avg being 1024. + +Combing with issue described below, this can lead to unwanted frequency spikes +when severely capped tasks share the rq with a small non capped task. + +As an example if task p, which have: + +:: + + p0->util_avg = 300 + p0->uclamp[UCLAMP_MAX] = 0 + +wakes up on an idle CPU, then it will run at min frequency (Fmin) this +CPU is capable of. The max CPU frequency (Fmax) matters here as well, +since it designates the shortest computational time to finish the task's +work on this CPU. + +:: + + rq->uclamp[UCLAMP_MAX] = 0 + +If the ratio of Fmax/Fmin is 3, then maximum value will be: + +:: + + 300 * (Fmax/Fmin) = 900 + +which indicates the CPU will still see idle time since 900 is < 1024. The +_actual_ util_avg will not be 900 though, but somewhere between 300 and 900. As +long as there's idle time, p->util_avg updates will be off by a some margin, +but not proportional to Fmax/Fmin. + +:: + + p0->util_avg = 300 + small_error + +Now if the ratio of Fmax/Fmin is 4, the maximum value becomes: + +:: + + 300 * (Fmax/Fmin) = 1200 + +which is higher than 1024 and indicates that the CPU has no idle time. When +this happens, then the _actual_ util_avg will become: + +:: + + p0->util_avg = 1024 + +If task p1 wakes up on this CPU, which have: + +:: + + p1->util_avg = 200 + p1->uclamp[UCLAMP_MAX] = 1024 + +then the effective UCLAMP_MAX for the CPU will be 1024 according to max +aggregation rule. But since the capped p0 task was running and throttled +severely, then the rq->util_avg will be: + +:: + + p0->util_avg = 1024 + p1->util_avg = 200 + + rq->util_avg = 1024 + rq->uclamp[UCLAMP_MAX] = 1024 + +Hence lead to a frequency spike since if p0 wasn't throttled we should get: + +:: + + p0->util_avg = 300 + p1->util_avg = 200 + + rq->util_avg = 500 + +and run somewhere near mid performance point of that CPU, not the Fmax we get. + +5.3. Schedutil response time issues +----------------------------------- + +schedutil has three limitations: + + 1. Hardware takes non-zero time to respond to any frequency change + request. On some platforms can be in the order of few ms. + 2. Non fast-switch systems require a worker deadline thread to wake up + and perform the frequency change, which adds measurable overhead. + 3. schedutil rate_limit_us drops any requests during this rate_limit_us + window. + +If a relatively small task is doing critical job and requires a certain +performance point when it wakes up and starts running, then all these +limitations will prevent it from getting what it wants in the time scale it +expects. + +This limitation is not only impactful when using uclamp, but will be more +prevalent as we no longer gradually ramp up or down. We could easily be +jumping between frequencies depending on the order tasks wake up, and their +respective uclamp values. + +We regard that as a limitation of the capabilities of the underlying system +itself. + +There is room to improve the behavior of schedutil rate_limit_us, but not much +to be done for 1 or 2. They are considered hard limitations of the system. diff --git a/Documentation/sphinx/load_config.py b/Documentation/sphinx/load_config.py index eeb394b39e2cc8dc8d8f866a379cf492f5d8b73b..8b416bfd75ac1711d0a6275a5bf84f71c3e40a88 100644 --- a/Documentation/sphinx/load_config.py +++ b/Documentation/sphinx/load_config.py @@ -3,7 +3,7 @@ import os import sys -from sphinx.util.pycompat import execfile_ +from sphinx.util.osutil import fs_encoding # ------------------------------------------------------------------------------ def loadConfig(namespace): @@ -48,7 +48,9 @@ def loadConfig(namespace): sys.stdout.write("load additional sphinx-config: %s\n" % config_file) config = namespace.copy() config['__file__'] = config_file - execfile_(config_file, config) + with open(config_file, 'rb') as f: + code = compile(f.read(), fs_encoding, 'exec') + exec(code, config) del config['__file__'] namespace.update(config) else: diff --git a/Documentation/translations/it_IT/kernel-hacking/locking.rst b/Documentation/translations/it_IT/kernel-hacking/locking.rst index b8ecf41273c574411123fbbc8c65b9502f70360d..05d362b16bf0b2af3b7c9049f1b5b022bc949589 100644 --- a/Documentation/translations/it_IT/kernel-hacking/locking.rst +++ b/Documentation/translations/it_IT/kernel-hacking/locking.rst @@ -1307,11 +1307,11 @@ se i dati vengono occasionalmente utilizzati da un contesto utente o da un'interruzione software. Il gestore d'interruzione non utilizza alcun *lock*, e tutti gli altri accessi verranno fatti così:: - spin_lock(&lock); + mutex_lock(&lock); disable_irq(irq); ... enable_irq(irq); - spin_unlock(&lock); + mutex_unlock(&lock); La funzione disable_irq() impedisce al gestore d'interruzioni d'essere eseguito (e aspetta che finisca nel caso fosse in esecuzione su diff --git a/Documentation/userspace-api/ioctl/ioctl-number.rst b/Documentation/userspace-api/ioctl/ioctl-number.rst index eb045fc495a4e3426604eedde78fd5656d6b6920..362bee0be8abd8c3533b49114d78cf8b8bc58dd2 100644 --- a/Documentation/userspace-api/ioctl/ioctl-number.rst +++ b/Documentation/userspace-api/ioctl/ioctl-number.rst @@ -201,7 +201,6 @@ Code Seq# Include File Comments 'V' all linux/videodev2.h conflict! 'V' C0 linux/ivtvfb.h conflict! 'V' C0 linux/ivtv.h conflict! -'V' C0 media/davinci/vpfe_capture.h conflict! 'V' C0 media/si4713.h conflict! 'W' 00-1F linux/watchdog.h conflict! 'W' 00-1F linux/wanrouter.h conflict! (pre 3.9) diff --git a/Documentation/virt/kvm/api.rst b/Documentation/virt/kvm/api.rst index deb494f759ed39c4b0f70bf19af63ec5d921dd6c..0a67cb738013e6e2419e17b5ce91e211bf422d30 100644 --- a/Documentation/virt/kvm/api.rst +++ b/Documentation/virt/kvm/api.rst @@ -1354,6 +1354,14 @@ the memory region are automatically reflected into the guest. For example, an mmap() that affects the region will be made visible immediately. Another example is madvise(MADV_DROP). +Note: On arm64, a write generated by the page-table walker (to update +the Access and Dirty flags, for example) never results in a +KVM_EXIT_MMIO exit when the slot has the KVM_MEM_READONLY flag. This +is because KVM cannot provide the data that would be written by the +page-table walker, making it impossible to emulate the access. +Instead, an abort (data abort if the cause of the page-table update +was a load or a store, instruction abort if it was an instruction +fetch) is injected in the guest. 4.36 KVM_SET_TSS_ADDR --------------------- @@ -8062,9 +8070,13 @@ considering the state as complete. VMM needs to ensure that the dirty state is final and avoid missing dirty pages from another ioctl ordered after the bitmap collection. -NOTE: One example of using the backup bitmap is saving arm64 vgic/its -tables through KVM_DEV_ARM_{VGIC_GRP_CTRL, ITS_SAVE_TABLES} command on -KVM device "kvm-arm-vgic-its" when dirty ring is enabled. +NOTE: Multiple examples of using the backup bitmap: (1) save vgic/its +tables through command KVM_DEV_ARM_{VGIC_GRP_CTRL, ITS_SAVE_TABLES} on +KVM device "kvm-arm-vgic-its". (2) restore vgic/its tables through +command KVM_DEV_ARM_{VGIC_GRP_CTRL, ITS_RESTORE_TABLES} on KVM device +"kvm-arm-vgic-its". VGICv3 LPI pending status is restored. (3) save +vgic3 pending table through KVM_DEV_ARM_VGIC_{GRP_CTRL, SAVE_PENDING_TABLES} +command on KVM device "kvm-arm-vgic-v3". 8.30 KVM_CAP_XEN_HVM -------------------- @@ -8310,6 +8322,20 @@ CPU[EAX=1]:ECX[24] (TSC_DEADLINE) is not reported by ``KVM_GET_SUPPORTED_CPUID`` It can be enabled if ``KVM_CAP_TSC_DEADLINE_TIMER`` is present and the kernel has enabled in-kernel emulation of the local APIC. +CPU topology +~~~~~~~~~~~~ + +Several CPUID values include topology information for the host CPU: +0x0b and 0x1f for Intel systems, 0x8000001e for AMD systems. Different +versions of KVM return different values for this information and userspace +should not rely on it. Currently they return all zeroes. + +If userspace wishes to set up a guest topology, it should be careful that +the values of these three leaves differ for each CPU. In particular, +the APIC ID is found in EDX for all subleaves of 0x0b and 0x1f, and in EAX +for 0x8000001e; the latter also encodes the core id and node id in bits +7:0 of EBX and ECX respectively. + Obsolete ioctls and capabilities ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/Documentation/virt/kvm/locking.rst b/Documentation/virt/kvm/locking.rst index a3ca76f9be751091e1f0a437a1e2693d9ee30e06..a0146793d1972daabb5bb424ae07484c0c5188e7 100644 --- a/Documentation/virt/kvm/locking.rst +++ b/Documentation/virt/kvm/locking.rst @@ -24,21 +24,22 @@ The acquisition orders for mutexes are as follows: For SRCU: -- ``synchronize_srcu(&kvm->srcu)`` is called _inside_ - the kvm->slots_lock critical section, therefore kvm->slots_lock - cannot be taken inside a kvm->srcu read-side critical section. - Instead, kvm->slots_arch_lock is released before the call - to ``synchronize_srcu()`` and _can_ be taken inside a - kvm->srcu read-side critical section. - -- kvm->lock is taken inside kvm->srcu, therefore - ``synchronize_srcu(&kvm->srcu)`` cannot be called inside - a kvm->lock critical section. If you cannot delay the - call until after kvm->lock is released, use ``call_srcu``. +- ``synchronize_srcu(&kvm->srcu)`` is called inside critical sections + for kvm->lock, vcpu->mutex and kvm->slots_lock. These locks _cannot_ + be taken inside a kvm->srcu read-side critical section; that is, the + following is broken:: + + srcu_read_lock(&kvm->srcu); + mutex_lock(&kvm->slots_lock); + +- kvm->slots_arch_lock instead is released before the call to + ``synchronize_srcu()``. It _can_ therefore be taken inside a + kvm->srcu read-side critical section, for example while processing + a vmexit. On x86: -- vcpu->mutex is taken outside kvm->arch.hyperv.hv_lock +- vcpu->mutex is taken outside kvm->arch.hyperv.hv_lock and kvm->arch.xen.xen_lock - kvm->arch.mmu_lock is an rwlock. kvm->arch.tdp_mmu_pages_lock and kvm->arch.mmu_unsync_pages_lock are taken inside kvm->arch.mmu_lock, and diff --git a/Documentation/x86/amd-memory-encryption.rst b/Documentation/x86/amd-memory-encryption.rst index a1940ebe7be50cb17260b240a3ce78ec4f6a2242..934310ce7258298008e4c6ba5be611105993e1c1 100644 --- a/Documentation/x86/amd-memory-encryption.rst +++ b/Documentation/x86/amd-memory-encryption.rst @@ -95,3 +95,39 @@ by supplying mem_encrypt=on on the kernel command line. However, if BIOS does not enable SME, then Linux will not be able to activate memory encryption, even if configured to do so by default or the mem_encrypt=on command line parameter is specified. + +Secure Nested Paging (SNP) +========================== + +SEV-SNP introduces new features (SEV_FEATURES[1:63]) which can be enabled +by the hypervisor for security enhancements. Some of these features need +guest side implementation to function correctly. The below table lists the +expected guest behavior with various possible scenarios of guest/hypervisor +SNP feature support. + ++-----------------+---------------+---------------+------------------+ +| Feature Enabled | Guest needs | Guest has | Guest boot | +| by the HV | implementation| implementation| behaviour | ++=================+===============+===============+==================+ +| No | No | No | Boot | +| | | | | ++-----------------+---------------+---------------+------------------+ +| No | Yes | No | Boot | +| | | | | ++-----------------+---------------+---------------+------------------+ +| No | Yes | Yes | Boot | +| | | | | ++-----------------+---------------+---------------+------------------+ +| Yes | No | No | Boot with | +| | | | feature enabled | ++-----------------+---------------+---------------+------------------+ +| Yes | Yes | No | Graceful boot | +| | | | failure | ++-----------------+---------------+---------------+------------------+ +| Yes | Yes | Yes | Boot with | +| | | | feature enabled | ++-----------------+---------------+---------------+------------------+ + +More details in AMD64 APM[1] Vol 2: 15.34.10 SEV_STATUS MSR + +[1] https://www.amd.com/system/files/TechDocs/40332.pdf diff --git a/Documentation/x86/resctrl.rst b/Documentation/x86/resctrl.rst index 71a531061e4e2d1d5116a744ae30136efdd8757e..058257dc56c8b5ed65c0b7ee934b5dac0405ac80 100644 --- a/Documentation/x86/resctrl.rst +++ b/Documentation/x86/resctrl.rst @@ -17,14 +17,21 @@ AMD refers to this feature as AMD Platform Quality of Service(AMD QoS). This feature is enabled by the CONFIG_X86_CPU_RESCTRL and the x86 /proc/cpuinfo flag bits: -============================================= ================================ +=============================================== ================================ RDT (Resource Director Technology) Allocation "rdt_a" CAT (Cache Allocation Technology) "cat_l3", "cat_l2" CDP (Code and Data Prioritization) "cdp_l3", "cdp_l2" CQM (Cache QoS Monitoring) "cqm_llc", "cqm_occup_llc" MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_mbm_local" MBA (Memory Bandwidth Allocation) "mba" -============================================= ================================ +SMBA (Slow Memory Bandwidth Allocation) "" +BMEC (Bandwidth Monitoring Event Configuration) "" +=============================================== ================================ + +Historically, new features were made visible by default in /proc/cpuinfo. This +resulted in the feature flags becoming hard to parse by humans. Adding a new +flag to /proc/cpuinfo should be avoided if user space can obtain information +about the feature from resctrl's info directory. To use the feature mount the file system:: @@ -161,6 +168,83 @@ with the following files: "mon_features": Lists the monitoring events if monitoring is enabled for the resource. + Example:: + + # cat /sys/fs/resctrl/info/L3_MON/mon_features + llc_occupancy + mbm_total_bytes + mbm_local_bytes + + If the system supports Bandwidth Monitoring Event + Configuration (BMEC), then the bandwidth events will + be configurable. The output will be:: + + # cat /sys/fs/resctrl/info/L3_MON/mon_features + llc_occupancy + mbm_total_bytes + mbm_total_bytes_config + mbm_local_bytes + mbm_local_bytes_config + +"mbm_total_bytes_config", "mbm_local_bytes_config": + Read/write files containing the configuration for the mbm_total_bytes + and mbm_local_bytes events, respectively, when the Bandwidth + Monitoring Event Configuration (BMEC) feature is supported. + The event configuration settings are domain specific and affect + all the CPUs in the domain. When either event configuration is + changed, the bandwidth counters for all RMIDs of both events + (mbm_total_bytes as well as mbm_local_bytes) are cleared for that + domain. The next read for every RMID will report "Unavailable" + and subsequent reads will report the valid value. + + Following are the types of events supported: + + ==== ======================================================== + Bits Description + ==== ======================================================== + 6 Dirty Victims from the QOS domain to all types of memory + 5 Reads to slow memory in the non-local NUMA domain + 4 Reads to slow memory in the local NUMA domain + 3 Non-temporal writes to non-local NUMA domain + 2 Non-temporal writes to local NUMA domain + 1 Reads to memory in the non-local NUMA domain + 0 Reads to memory in the local NUMA domain + ==== ======================================================== + + By default, the mbm_total_bytes configuration is set to 0x7f to count + all the event types and the mbm_local_bytes configuration is set to + 0x15 to count all the local memory events. + + Examples: + + * To view the current configuration:: + :: + + # cat /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config + 0=0x7f;1=0x7f;2=0x7f;3=0x7f + + # cat /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config + 0=0x15;1=0x15;3=0x15;4=0x15 + + * To change the mbm_total_bytes to count only reads on domain 0, + the bits 0, 1, 4 and 5 needs to be set, which is 110011b in binary + (in hexadecimal 0x33): + :: + + # echo "0=0x33" > /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config + + # cat /sys/fs/resctrl/info/L3_MON/mbm_total_bytes_config + 0=0x33;1=0x7f;2=0x7f;3=0x7f + + * To change the mbm_local_bytes to count all the slow memory reads on + domain 0 and 1, the bits 4 and 5 needs to be set, which is 110000b + in binary (in hexadecimal 0x30): + :: + + # echo "0=0x30;1=0x30" > /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config + + # cat /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config + 0=0x30;1=0x30;3=0x15;4=0x15 "max_threshold_occupancy": Read/write file provides the largest value (in @@ -464,6 +548,25 @@ Memory bandwidth domain is L3 cache. MB:=bw_MBps0;=bw_MBps1;... +Slow Memory Bandwidth Allocation (SMBA) +--------------------------------------- +AMD hardware supports Slow Memory Bandwidth Allocation (SMBA). +CXL.memory is the only supported "slow" memory device. With the +support of SMBA, the hardware enables bandwidth allocation on +the slow memory devices. If there are multiple such devices in +the system, the throttling logic groups all the slow sources +together and applies the limit on them as a whole. + +The presence of SMBA (with CXL.memory) is independent of slow memory +devices presence. If there are no such devices on the system, then +configuring SMBA will have no impact on the performance of the system. + +The bandwidth domain for slow memory is L3 cache. Its schemata file +is formatted as: +:: + + SMBA:=bandwidth0;=bandwidth1;... + Reading/writing the schemata file --------------------------------- Reading the schemata file will show the state of all resources @@ -479,6 +582,46 @@ which you wish to change. E.g. L3DATA:0=fffff;1=fffff;2=3c0;3=fffff L3CODE:0=fffff;1=fffff;2=fffff;3=fffff +Reading/writing the schemata file (on AMD systems) +-------------------------------------------------- +Reading the schemata file will show the current bandwidth limit on all +domains. The allocated resources are in multiples of one eighth GB/s. +When writing to the file, you need to specify what cache id you wish to +configure the bandwidth limit. + +For example, to allocate 2GB/s limit on the first cache id: + +:: + + # cat schemata + MB:0=2048;1=2048;2=2048;3=2048 + L3:0=ffff;1=ffff;2=ffff;3=ffff + + # echo "MB:1=16" > schemata + # cat schemata + MB:0=2048;1= 16;2=2048;3=2048 + L3:0=ffff;1=ffff;2=ffff;3=ffff + +Reading/writing the schemata file (on AMD systems) with SMBA feature +-------------------------------------------------------------------- +Reading and writing the schemata file is the same as without SMBA in +above section. + +For example, to allocate 8GB/s limit on the first cache id: + +:: + + # cat schemata + SMBA:0=2048;1=2048;2=2048;3=2048 + MB:0=2048;1=2048;2=2048;3=2048 + L3:0=ffff;1=ffff;2=ffff;3=ffff + + # echo "SMBA:1=64" > schemata + # cat schemata + SMBA:0=2048;1= 64;2=2048;3=2048 + MB:0=2048;1=2048;2=2048;3=2048 + L3:0=ffff;1=ffff;2=ffff;3=ffff + Cache Pseudo-Locking ==================== CAT enables a user to specify the amount of cache space that an diff --git a/MAINTAINERS b/MAINTAINERS index 7f86d02cb427ab3b70937af638f8bc5c2f4d232f..2368a813e7ae0fa0fff1e25ff5a7a99bac653b5b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -361,6 +361,8 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm F: Documentation/ABI/testing/configfs-acpi F: Documentation/ABI/testing/sysfs-bus-acpi F: Documentation/firmware-guide/acpi/ +F: arch/x86/kernel/acpi/ +F: arch/x86/pci/acpi.c F: drivers/acpi/ F: drivers/pci/*/*acpi* F: drivers/pci/*acpi* @@ -383,7 +385,7 @@ ACPI COMPONENT ARCHITECTURE (ACPICA) M: Robert Moore M: "Rafael J. Wysocki" L: linux-acpi@vger.kernel.org -L: devel@acpica.org +L: acpica-devel@lists.linuxfoundation.org S: Supported W: https://acpica.org/ W: https://github.com/acpica/acpica/ @@ -1097,14 +1099,12 @@ S: Maintained F: drivers/dma/ptdma/ AMD SEATTLE DEVICE TREE SUPPORT -M: Brijesh Singh M: Suravee Suthikulpanit M: Tom Lendacky S: Supported F: arch/arm64/boot/dts/amd/ AMD XGBE DRIVER -M: Tom Lendacky M: "Shyam Sundar S K" L: netdev@vger.kernel.org S: Supported @@ -1853,21 +1853,6 @@ F: include/dt-bindings/reset/actions,* F: include/linux/soc/actions/ N: owl -ARM/ADS SPHERE MACHINE SUPPORT -M: Lennert Buytenhek -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained - -ARM/AFEB9260 MACHINE SUPPORT -M: Sergey Lapin -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained - -ARM/AJECO 1ARM MACHINE SUPPORT -M: Lennert Buytenhek -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained - ARM/Allwinner SoC Clock Support M: Emilio López S: Maintained @@ -1888,7 +1873,7 @@ F: drivers/pinctrl/sunxi/ F: drivers/soc/sunxi/ N: allwinner N: sun[x456789]i -N: sun50i +N: sun[25]0i ARM/Amlogic Meson SoC CLOCK FRAMEWORK M: Neil Armstrong @@ -2058,11 +2043,6 @@ F: arch/arm/boot/dts/ecx-*.dts* F: arch/arm/boot/dts/highbank.dts F: arch/arm/mach-highbank/ -ARM/CAVIUM NETWORKS CNS3XXX MACHINE SUPPORT -M: Krzysztof Halasa -S: Maintained -F: arch/arm/mach-cns3xxx/ - ARM/CAVIUM THUNDER NETWORK DRIVER M: Sunil Goutham L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -2091,8 +2071,8 @@ M: Hartley Sweeten M: Alexander Sverdlin L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained +F: arch/arm/boot/compressed/misc-ep93xx.h F: arch/arm/mach-ep93xx/ -F: arch/arm/mach-ep93xx/include/mach/ ARM/CLKDEV SUPPORT M: Russell King @@ -2108,11 +2088,6 @@ S: Maintained F: arch/arm/boot/dts/cx92755* N: digicolor -ARM/CONTEC MICRO9 MACHINE SUPPORT -M: Hubert Feurstein -S: Maintained -F: arch/arm/mach-ep93xx/micro9.c - ARM/CORESIGHT FRAMEWORK AND DRIVERS M: Mathieu Poirier M: Suzuki K Poulose @@ -2139,10 +2114,6 @@ F: tools/perf/arch/arm/util/pmu.c F: tools/perf/util/cs-etm-decoder/* F: tools/perf/util/cs-etm.* -ARM/CORGI MACHINE SUPPORT -M: Richard Purdie -S: Maintained - ARM/CORTINA SYSTEMS GEMINI ARM ARCHITECTURE M: Hans Ulli Kroll M: Linus Walleij @@ -2182,12 +2153,6 @@ F: include/dt-bindings/bus/moxtet.h F: include/linux/armada-37xx-rwtm-mailbox.h F: include/linux/moxtet.h -ARM/EZX SMARTPHONES (A780, A910, A1200, E680, ROKR E2 and ROKR E6) -M: Robert Jarzmik -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained -F: arch/arm/mach-pxa/ezx.c - ARM/FARADAY FA526 PORT M: Hans Ulli Kroll L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -2213,6 +2178,9 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git X: drivers/media/i2c/ +F: arch/arm64/boot/dts/freescale/ +X: arch/arm64/boot/dts/freescale/fsl-* +X: arch/arm64/boot/dts/freescale/qoriq-* N: imx N: mxs @@ -2237,25 +2205,11 @@ T: git git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux.git F: arch/arm/boot/dts/vf* F: arch/arm/mach-imx/*vf610* -ARM/GLOMATION GESBC9312SX MACHINE SUPPORT -M: Lennert Buytenhek -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained - ARM/GUMSTIX MACHINE SUPPORT M: Steve Sakoman L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -ARM/H4700 (HP IPAQ HX4700) MACHINE SUPPORT -M: Philipp Zabel -M: Paul Parsons -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained -F: arch/arm/mach-pxa/hx4700.c -F: arch/arm/mach-pxa/include/mach/hx4700.h -F: sound/soc/pxa/hx4700.c - ARM/HISILICON SOC SUPPORT M: Wei Xu L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -2298,27 +2252,6 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm/boot/dts/omap3-igep* -ARM/INCOME PXA270 SUPPORT -M: Marek Vasut -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained -F: arch/arm/mach-pxa/colibri-pxa270-income.c - -ARM/INTEL IOP32X ARM ARCHITECTURE -M: Lennert Buytenhek -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained - -ARM/INTEL IQ81342EX MACHINE SUPPORT -M: Lennert Buytenhek -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained - -ARM/INTEL IXDP2850 MACHINE SUPPORT -M: Lennert Buytenhek -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained - ARM/INTEL IXP4XX ARM ARCHITECTURE M: Linus Walleij M: Imre Kaloz @@ -2351,22 +2284,12 @@ M: Lennert Buytenhek L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained -ARM/IP FABRICS DOUBLE ESPRESSO MACHINE SUPPORT -M: Lennert Buytenhek -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained - ARM/LG1K ARCHITECTURE M: Chanho Min L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm64/boot/dts/lg/ -ARM/LOGICPD PXA270 MACHINE SUPPORT -M: Lennert Buytenhek -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained - ARM/LPC18XX ARCHITECTURE M: Vladimir Zapolskiy L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -2393,10 +2316,6 @@ F: drivers/usb/host/ohci-nxp.c F: drivers/watchdog/pnx4008_wdt.c N: lpc32xx -ARM/MAGICIAN MACHINE SUPPORT -M: Philipp Zabel -S: Maintained - ARM/Marvell Dove/MV78xx0/Orion SOC support M: Andrew Lunn M: Sebastian Hesselbarth @@ -2451,11 +2370,14 @@ F: drivers/rtc/rtc-mt7622.c ARM/Mediatek SoC support M: Matthias Brugger +R: AngeloGioacchino Del Regno +L: linux-kernel@vger.kernel.org L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-mediatek@lists.infradead.org (moderated for non-subscribers) S: Maintained W: https://mtk.wiki.kernel.org/ -C: irc://chat.freenode.net/linux-mediatek +C: irc://irc.libera.chat/linux-mediatek +F: arch/arm/boot/dts/mt2* F: arch/arm/boot/dts/mt6* F: arch/arm/boot/dts/mt7* F: arch/arm/boot/dts/mt8* @@ -2463,7 +2385,7 @@ F: arch/arm/mach-mediatek/ F: arch/arm64/boot/dts/mediatek/ F: drivers/soc/mediatek/ N: mtk -N: mt[678] +N: mt[2678] K: mediatek ARM/Mediatek USB3 PHY DRIVER @@ -2525,12 +2447,6 @@ F: arch/arm/boot/dts/milbeaut* F: arch/arm/mach-milbeaut/ N: milbeaut -ARM/MIOA701 MACHINE SUPPORT -M: Robert Jarzmik -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained -F: arch/arm/mach-pxa/mioa701.c - ARM/MStar/Sigmastar Armv7 SoC support M: Daniel Palmer M: Romain Perier @@ -2551,10 +2467,6 @@ F: drivers/watchdog/msc313e_wdt.c F: include/dt-bindings/clock/mstar-* F: include/dt-bindings/gpio/msc313-gpio.h -ARM/NEC MOBILEPRO 900/c MACHINE SUPPORT -M: Michael Petchkovsky -S: Maintained - ARM/NOMADIK/Ux500 ARCHITECTURES M: Linus Walleij L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -2610,6 +2522,7 @@ S: Maintained W: https://github.com/neuschaefer/wpcm450/wiki F: Documentation/devicetree/bindings/*/*wpcm* F: arch/arm/boot/dts/nuvoton-wpcm450* +F: arch/arm/configs/wpcm450_defconfig F: arch/arm/mach-npcm/wpcm450.c F: drivers/*/*/*wpcm* F: drivers/*/*wpcm* @@ -2623,13 +2536,6 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: arch/arm64/boot/dts/freescale/s32g*.dts* -ARM/OPENMOKO NEO FREERUNNER (GTA02) MACHINE SUPPORT -L: openmoko-kernel@lists.openmoko.org (subscribers-only) -S: Orphan -W: http://wiki.openmoko.org/wiki/Neo_FreeRunner -F: arch/arm/mach-s3c/gta02.h -F: arch/arm/mach-s3c/mach-gta02.c - ARM/Orion SoC/Technologic Systems TS-78xx platform support M: Alexander Clouter L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -2647,43 +2553,6 @@ F: arch/arm/mach-oxnas/ F: drivers/power/reset/oxnas-restart.c N: oxnas -ARM/PALM TREO SUPPORT -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Orphan -F: arch/arm/mach-pxa/palmtreo.* - -ARM/PALMTX,PALMT5,PALMLD,PALMTE2,PALMTC SUPPORT -M: Marek Vasut -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained -W: http://hackndev.com -F: arch/arm/mach-pxa/include/mach/palmld.h -F: arch/arm/mach-pxa/include/mach/palmtc.h -F: arch/arm/mach-pxa/include/mach/palmtx.h -F: arch/arm/mach-pxa/palmld.c -F: arch/arm/mach-pxa/palmt5.* -F: arch/arm/mach-pxa/palmtc.c -F: arch/arm/mach-pxa/palmte2.* -F: arch/arm/mach-pxa/palmtx.c - -ARM/PALMZ72 SUPPORT -M: Sergey Lapin -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained -W: http://hackndev.com -F: arch/arm/mach-pxa/palmz72.* - -ARM/PLEB SUPPORT -M: Peter Chubb -S: Maintained -W: http://www.disy.cse.unsw.edu.au/Hardware/PLEB - -ARM/PT DIGITAL BOARD PORT -M: Stefan Eletzhofer -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained -W: http://www.armlinux.org.uk/ - ARM/QUALCOMM SUPPORT M: Andy Gross M: Bjorn Andersson @@ -2727,11 +2596,6 @@ F: include/dt-bindings/*/qcom* F: include/linux/*/qcom* F: include/linux/soc/qcom/ -ARM/RADISYS ENP2611 MACHINE SUPPORT -M: Lennert Buytenhek -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained - ARM/RDA MICRO ARCHITECTURE M: Manivannan Sadhasivam L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -2807,7 +2671,7 @@ F: Documentation/devicetree/bindings/i2c/i2c-rk3x.yaml F: Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml F: Documentation/devicetree/bindings/spi/spi-rockchip.yaml F: arch/arm/boot/dts/rk3* -F: arch/arm/boot/dts/rv1108* +F: arch/arm/boot/dts/rv11* F: arch/arm/mach-rockchip/ F: drivers/*/*/*rockchip* F: drivers/*/*rockchip* @@ -2852,7 +2716,6 @@ F: include/linux/platform_data/*s3c* F: include/linux/serial_s3c.h F: include/linux/soc/samsung/ N: exynos -N: s3c2410 N: s3c64xx N: s5pv210 @@ -3010,7 +2873,7 @@ M: linux-fsd@tesla.com L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: linux-samsung-soc@vger.kernel.org S: Maintained -F: arch/arm64/boot/dts/tesla* +F: arch/arm64/boot/dts/tesla/ ARM/TETON BGA MACHINE SUPPORT M: "Mark F. Brown" @@ -3063,16 +2926,6 @@ F: arch/arm64/boot/dts/ti/Makefile F: arch/arm64/boot/dts/ti/k3-* F: include/dt-bindings/pinctrl/k3.h -ARM/THECUS N2100 MACHINE SUPPORT -M: Lennert Buytenhek -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained - -ARM/TOSA MACHINE SUPPORT -M: Dmitry Eremin-Solenikov -M: Dirk Opfer -S: Maintained - ARM/TOSHIBA VISCONTI ARCHITECTURE M: Nobuhiro Iwamatsu L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -3129,7 +2982,7 @@ S: Maintained F: */*/*/vexpress* F: */*/vexpress* F: arch/arm/boot/dts/vexpress* -F: arch/arm/mach-vexpress/ +F: arch/arm/mach-versatile/ F: arch/arm64/boot/dts/arm/ F: drivers/clk/versatile/clk-vexpress-osc.c F: drivers/clocksource/timer-versatile.c @@ -3142,13 +2995,6 @@ S: Maintained W: http://www.armlinux.org.uk/ F: arch/arm/vfp/ -ARM/VOIPAC PXA270 SUPPORT -M: Marek Vasut -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained -F: arch/arm/mach-pxa/include/mach/vpac270.h -F: arch/arm/mach-pxa/vpac270.c - ARM/VT8500 ARM ARCHITECTURE L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Orphan @@ -3166,13 +3012,6 @@ F: drivers/video/fbdev/vt8500lcdfb.* F: drivers/video/fbdev/wm8505fb* F: drivers/video/fbdev/wmt_ge_rops.* -ARM/ZIPIT Z2 SUPPORT -M: Marek Vasut -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Maintained -F: arch/arm/mach-pxa/include/mach/z2.h -F: arch/arm/mach-pxa/z2.c - ARM/ZYNQ ARCHITECTURE M: Michal Simek L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) @@ -3767,7 +3606,6 @@ F: net/bluetooth/ BONDING DRIVER M: Jay Vosburgh -M: Veaceslav Falico M: Andy Gospodarek L: netdev@vger.kernel.org S: Supported @@ -4985,6 +4823,13 @@ S: Maintained F: Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml F: sound/soc/codecs/cros_ec_codec.* +CHROMEOS EC UART DRIVER +M: Bhanu Prakash Maiya +R: Benson Leung +R: Tzung-Bi Shih +S: Maintained +F: drivers/platform/chrome/cros_ec_uart.c + CHROMEOS EC SUBDRIVERS M: Benson Leung R: Guenter Roeck @@ -4998,8 +4843,9 @@ CHROMEOS EC USB TYPE-C DRIVER M: Prashant Malani L: chrome-platform@lists.linux.dev S: Maintained -F: drivers/platform/chrome/cros_ec_typec.c +F: drivers/platform/chrome/cros_ec_typec.* F: drivers/platform/chrome/cros_typec_switch.c +F: drivers/platform/chrome/cros_typec_vdm.* CHROMEOS EC USB PD NOTIFY DRIVER M: Prashant Malani @@ -5927,7 +5773,6 @@ F: Documentation/ABI/testing/sysfs-platform-dell-wmi-ddv F: drivers/platform/x86/dell/dell-wmi-ddv.c DELL WMI SYSMAN DRIVER -M: Divya Bharathi M: Prasanth Ksr L: Dell.Client.Kernel@dell.com L: platform-driver-x86@vger.kernel.org @@ -6422,6 +6267,7 @@ T: git git://git.linbit.com/linux-drbd.git T: git git://git.linbit.com/drbd-8.4.git F: Documentation/admin-guide/blockdev/ F: drivers/block/drbd/ +F: include/linux/drbd* F: lib/lru_cache.c DRIVER COMPONENT FRAMEWORK @@ -6948,7 +6794,7 @@ F: drivers/gpu/drm/atmel-hlcdc/ DRM DRIVERS FOR BRIDGE CHIPS M: Andrzej Hajda M: Neil Armstrong -M: Robert Foss +M: Robert Foss R: Laurent Pinchart R: Jonas Karlman R: Jernej Skrabec @@ -7616,7 +7462,6 @@ S: Maintained F: drivers/firmware/efi/test/ EFI VARIABLE FILESYSTEM -M: Matthew Garrett M: Jeremy Kerr M: Ard Biesheuvel L: linux-efi@vger.kernel.org @@ -7745,6 +7590,7 @@ R: Jeffle Xu L: linux-erofs@lists.ozlabs.org S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/xiang/erofs.git +F: Documentation/ABI/testing/sysfs-fs-erofs F: Documentation/filesystems/erofs.rst F: fs/erofs/ F: include/trace/events/erofs.h @@ -7895,7 +7741,11 @@ F: include/linux/extcon/ EXTRA BOOT CONFIG M: Masami Hiramatsu +L: linux-kernel@vger.kernel.org +L: linux-trace-kernel@vger.kernel.org +Q: https://patchwork.kernel.org/project/linux-trace-kernel/list/ S: Maintained +T: git git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git F: Documentation/admin-guide/bootconfig.rst F: fs/proc/bootconfig.c F: include/linux/bootconfig.h @@ -8196,7 +8046,7 @@ F: drivers/fpga/microchip-spi.c FPU EMULATOR M: Bill Metzenthen S: Maintained -W: http://floatingpoint.sourceforge.net/emulator/index.html +W: https://floatingpoint.billm.au/ F: arch/x86/math-emu/ FRAMEBUFFER CORE @@ -8468,16 +8318,16 @@ F: fs/fscache/ F: include/linux/fscache*.h FSCRYPT: FILE SYSTEM LEVEL ENCRYPTION SUPPORT +M: Eric Biggers M: Theodore Y. Ts'o M: Jaegeuk Kim -M: Eric Biggers L: linux-fscrypt@vger.kernel.org S: Supported Q: https://patchwork.kernel.org/project/linux-fscrypt/list/ -T: git git://git.kernel.org/pub/scm/fs/fscrypt/fscrypt.git +T: git https://git.kernel.org/pub/scm/fs/fscrypt/linux.git F: Documentation/filesystems/fscrypt.rst F: fs/crypto/ -F: include/linux/fscrypt*.h +F: include/linux/fscrypt.h F: include/uapi/linux/fscrypt.h FSI SUBSYSTEM @@ -8520,10 +8370,10 @@ F: include/linux/fsnotify*.h FSVERITY: READ-ONLY FILE-BASED AUTHENTICITY PROTECTION M: Eric Biggers M: Theodore Y. Ts'o -L: linux-fscrypt@vger.kernel.org +L: fsverity@lists.linux.dev S: Supported -Q: https://patchwork.kernel.org/project/linux-fscrypt/list/ -T: git git://git.kernel.org/pub/scm/fs/fscrypt/fscrypt.git fsverity +Q: https://patchwork.kernel.org/project/fsverity/list/ +T: git https://git.kernel.org/pub/scm/fs/fsverity/linux.git F: Documentation/filesystems/fsverity.rst F: fs/verity/ F: include/linux/fsverity.h @@ -8571,6 +8421,7 @@ F: kernel/trace/fgraph.c F: arch/*/*/*/*ftrace* F: arch/*/*/*ftrace* F: include/*/ftrace.h +F: samples/ftrace FUNGIBLE ETHERNET DRIVERS M: Dimitris Michailidis @@ -9299,7 +9150,7 @@ F: net/dsa/tag_hellcreek.c HISILICON DMA DRIVER M: Zhou Wang -M: Jie Hai +M: Jie Hai L: dmaengine@vger.kernel.org S: Maintained F: drivers/dma/hisi_dma.c @@ -9989,7 +9840,7 @@ S: Maintained T: git://git.kernel.org/pub/scm/linux/kernel/git/vfs/idmapping.git F: Documentation/filesystems/idmappings.rst F: tools/testing/selftests/mount_setattr/ -F: include/linux/mnt_idmapping.h +F: include/linux/mnt_idmapping.* IDT VersaClock 5 CLOCK DRIVER M: Luca Ceresoli @@ -10683,6 +10534,13 @@ S: Maintained F: arch/x86/include/asm/intel_telemetry.h F: drivers/platform/x86/intel/telemetry/ +INTEL TPMI DRIVER +M: Srinivas Pandruvada +L: platform-driver-x86@vger.kernel.org +S: Maintained +F: drivers/platform/x86/intel/tpmi.c +F: include/linux/intel_tpmi.h + INTEL UNCORE FREQUENCY CONTROL M: Srinivas Pandruvada L: platform-driver-x86@vger.kernel.org @@ -10935,6 +10793,8 @@ L: linux-kernel@vger.kernel.org S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git irq/core F: kernel/irq/ +F: include/linux/group_cpus.h +F: lib/group_cpus.c IRQCHIP DRIVERS M: Thomas Gleixner @@ -11356,9 +11216,9 @@ F: virt/kvm/* KERNEL VIRTUAL MACHINE FOR ARM64 (KVM/arm64) M: Marc Zyngier R: James Morse -R: Alexandru Elisei R: Suzuki K Poulose R: Oliver Upton +R: Zenghui Yu L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: kvmarm@lists.linux.dev L: kvmarm@lists.cs.columbia.edu (deprecated, moderated for non-subscribers) @@ -13620,7 +13480,7 @@ F: arch/microblaze/ MICROCHIP AT91 DMA DRIVERS M: Ludovic Desroches -M: Tudor Ambarus +M: Tudor Ambarus L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) L: dmaengine@vger.kernel.org S: Supported @@ -13665,7 +13525,7 @@ F: Documentation/devicetree/bindings/media/microchip,csi2dc.yaml F: drivers/media/platform/microchip/microchip-csi2dc.c MICROCHIP ECC DRIVER -M: Tudor Ambarus +M: Tudor Ambarus L: linux-crypto@vger.kernel.org S: Maintained F: drivers/crypto/atmel-ecc.* @@ -13762,7 +13622,7 @@ S: Maintained F: drivers/mmc/host/atmel-mci.c MICROCHIP NAND DRIVER -M: Tudor Ambarus +M: Tudor Ambarus L: linux-mtd@lists.infradead.org S: Supported F: Documentation/devicetree/bindings/mtd/atmel-nand.txt @@ -13814,7 +13674,7 @@ S: Supported F: drivers/power/reset/at91-sama5d2_shdwc.c MICROCHIP SPI DRIVER -M: Tudor Ambarus +M: Tudor Ambarus S: Supported F: drivers/spi/spi-atmel.* @@ -14601,7 +14461,6 @@ F: tools/testing/selftests/net/ipsec.c NETWORKING [IPv4/IPv6] M: "David S. Miller" -M: Hideaki YOSHIFUJI M: David Ahern L: netdev@vger.kernel.org S: Maintained @@ -14634,7 +14493,6 @@ F: net/netfilter/xt_SECMARK.c F: net/netlabel/ NETWORKING [MPTCP] -M: Mat Martineau M: Matthieu Baerts L: netdev@vger.kernel.org L: mptcp@lists.linux.dev @@ -14919,7 +14777,8 @@ T: git://git.infradead.org/nvme.git F: Documentation/nvme/ F: drivers/nvme/host/ F: drivers/nvme/common/ -F: include/linux/nvme* +F: include/linux/nvme.h +F: include/linux/nvme-*.h F: include/uapi/linux/nvme_ioctl.h NVM EXPRESS FABRICS AUTHENTICATION @@ -15314,7 +15173,6 @@ Q: http://patchwork.kernel.org/project/linux-omap/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git F: arch/arm/configs/omap1_defconfig F: arch/arm/mach-omap1/ -F: arch/arm/plat-omap/ F: drivers/i2c/busses/i2c-omap.c F: include/linux/platform_data/ams-delta-fiq.h F: include/linux/platform_data/i2c-omap.h @@ -15329,7 +15187,6 @@ Q: http://patchwork.kernel.org/project/linux-omap/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap.git F: arch/arm/configs/omap2plus_defconfig F: arch/arm/mach-omap2/ -F: arch/arm/plat-omap/ F: drivers/bus/ti-sysc.c F: drivers/i2c/busses/i2c-omap.c F: drivers/irqchip/irq-omap-intc.c @@ -15658,7 +15515,7 @@ OPENRISC ARCHITECTURE M: Jonas Bonn M: Stefan Kristiansson M: Stafford Horne -L: openrisc@lists.librecores.org +L: linux-openrisc@vger.kernel.org S: Maintained W: http://openrisc.io T: git https://github.com/openrisc/linux.git @@ -15749,6 +15606,12 @@ S: Maintained W: https://wireless.wiki.kernel.org/en/users/Drivers/p54 F: drivers/net/wireless/intersil/p54/ +PACKET SOCKETS +M: Willem de Bruijn +S: Maintained +F: include/uapi/linux/if_packet.h +F: net/packet/af_packet.c + PACKING M: Vladimir Oltean L: netdev@vger.kernel.org @@ -16108,7 +15971,7 @@ F: drivers/pci/controller/pci-v3-semi.c PCI ENDPOINT SUBSYSTEM M: Lorenzo Pieralisi -R: Krzysztof Wilczyński +M: Krzysztof Wilczyński R: Manivannan Sadhasivam R: Kishon Vijay Abraham I L: linux-pci@vger.kernel.org @@ -16116,7 +15979,7 @@ S: Supported Q: https://patchwork.kernel.org/project/linux-pci/list/ B: https://bugzilla.kernel.org C: irc://irc.oftc.net/linux-pci -T: git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git F: Documentation/PCI/endpoint/* F: Documentation/misc-devices/pci-endpoint-test.rst F: drivers/misc/pci_endpoint_test.c @@ -16151,7 +16014,7 @@ S: Supported Q: https://patchwork.kernel.org/project/linux-pci/list/ B: https://bugzilla.kernel.org C: irc://irc.oftc.net/linux-pci -T: git git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git F: Documentation/driver-api/pci/p2pdma.rst F: drivers/pci/p2pdma.c F: include/linux/pci-p2pdma.h @@ -16173,14 +16036,14 @@ F: drivers/pci/controller/pci-xgene-msi.c PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS M: Lorenzo Pieralisi +M: Krzysztof Wilczyński R: Rob Herring -R: Krzysztof Wilczyński L: linux-pci@vger.kernel.org S: Supported Q: https://patchwork.kernel.org/project/linux-pci/list/ B: https://bugzilla.kernel.org C: irc://irc.oftc.net/linux-pci -T: git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git F: Documentation/devicetree/bindings/pci/ F: drivers/pci/controller/ F: drivers/pci/pci-bridge-emul.c @@ -16193,7 +16056,7 @@ S: Supported Q: https://patchwork.kernel.org/project/linux-pci/list/ B: https://bugzilla.kernel.org C: irc://irc.oftc.net/linux-pci -T: git git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git +T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git F: Documentation/PCI/ F: Documentation/devicetree/bindings/pci/ F: arch/x86/kernel/early-quirks.c @@ -16610,6 +16473,13 @@ S: Supported F: Documentation/devicetree/bindings/input/pine64,pinephone-keyboard.yaml F: drivers/input/keyboard/pinephone-keyboard.c +PKTCDVD DRIVER +M: linux-block@vger.kernel.org +S: Orphan +F: drivers/block/pktcdvd.c +F: include/linux/pktcdvd.h +F: include/uapi/linux/pktcdvd.h + PLANTOWER PMS7003 AIR POLLUTION SENSOR DRIVER M: Tomasz Duszynski S: Maintained @@ -17230,7 +17100,7 @@ F: Documentation/devicetree/bindings/net/qcom,bam-dmux.yaml F: drivers/net/wwan/qcom_bam_dmux.c QUALCOMM CAMERA SUBSYSTEM DRIVER -M: Robert Foss +M: Robert Foss M: Todor Tomov L: linux-media@vger.kernel.org S: Maintained @@ -17310,7 +17180,7 @@ F: drivers/dma/qcom/hidma* QUALCOMM I2C CCI DRIVER M: Loic Poulain -M: Robert Foss +M: Robert Foss L: linux-i2c@vger.kernel.org L: linux-arm-msm@vger.kernel.org S: Maintained @@ -17949,6 +17819,7 @@ M: Albert Ou L: linux-riscv@lists.infradead.org S: Supported Q: https://patchwork.kernel.org/project/linux-riscv/list/ +C: irc://irc.libera.chat/riscv P: Documentation/riscv/patch-acceptance.rst T: git git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git F: arch/riscv/ @@ -18214,6 +18085,7 @@ L: rust-for-linux@vger.kernel.org S: Supported W: https://github.com/Rust-for-Linux/linux B: https://github.com/Rust-for-Linux/linux/issues +C: zulip://rust-for-linux.zulipchat.com T: git https://github.com/Rust-for-Linux/linux.git rust-next F: Documentation/rust/ F: rust/ @@ -18253,6 +18125,7 @@ F: Documentation/driver-api/s390-drivers.rst F: Documentation/s390/ F: arch/s390/ F: drivers/s390/ +F: drivers/watchdog/diag288_wdt.c S390 COMMON I/O LAYER M: Vineeth Vijayan @@ -18313,6 +18186,13 @@ F: arch/s390/pci/ F: drivers/pci/hotplug/s390_pci_hpc.c F: Documentation/s390/pci.rst +S390 SCM DRIVER +M: Vineeth Vijayan +L: linux-s390@vger.kernel.org +S: Supported +F: drivers/s390/block/scm* +F: drivers/s390/cio/scm.c + S390 VFIO AP DRIVER M: Tony Krowiak M: Halil Pasic @@ -18356,19 +18236,6 @@ L: linux-s390@vger.kernel.org S: Supported F: drivers/s390/scsi/zfcp_* -S3C ADC BATTERY DRIVER -M: Krzysztof Kozlowski -L: linux-samsung-soc@vger.kernel.org -S: Odd Fixes -F: drivers/power/supply/s3c_adc_battery.c -F: include/linux/s3c_adc_battery.h - -S3C24XX SD/MMC Driver -M: Ben Dooks -L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) -S: Supported -F: drivers/mmc/host/s3cmci.* - SAA6588 RDS RECEIVER DRIVER M: Hans Verkuil L: linux-media@vger.kernel.org @@ -18521,11 +18388,9 @@ F: Documentation/devicetree/bindings/clock/samsung,*.yaml F: Documentation/devicetree/bindings/clock/samsung,s3c* F: drivers/clk/samsung/ F: include/dt-bindings/clock/exynos*.h -F: include/dt-bindings/clock/s3c*.h F: include/dt-bindings/clock/s5p*.h F: include/dt-bindings/clock/samsung,*.h F: include/linux/clk/samsung.h -F: include/linux/platform_data/clk-s3c2410.h SAMSUNG SPI DRIVERS M: Krzysztof Kozlowski @@ -18536,7 +18401,6 @@ S: Maintained F: Documentation/devicetree/bindings/spi/samsung,spi*.yaml F: drivers/spi/spi-s3c* F: include/linux/platform_data/spi-s3c64xx.h -F: include/linux/spi/s3c24xx-fiq.h SAMSUNG SXGBE DRIVERS M: Byungho An @@ -18670,9 +18534,9 @@ F: drivers/target/ F: include/target/ SCTP PROTOCOL -M: Vlad Yasevich M: Neil Horman M: Marcelo Ricardo Leitner +M: Xin Long L: linux-sctp@vger.kernel.org S: Maintained W: http://lksctp.sourceforge.net @@ -19106,14 +18970,6 @@ M: Simtec Linux Team S: Supported W: http://www.simtec.co.uk/products/EB110ATX/ -SIMTEC EB2410ITX (BAST) -M: Simtec Linux Team -S: Supported -W: http://www.simtec.co.uk/products/EB2410ITX/ -F: arch/arm/mach-s3c/bast-ide.c -F: arch/arm/mach-s3c/bast-irq.c -F: arch/arm/mach-s3c/mach-bast.c - SIOX M: Thorsten Scherer M: Uwe Kleine-König @@ -19318,6 +19174,13 @@ L: alsa-devel@alsa-project.org (moderated for non-subscribers) S: Orphan F: sound/soc/uniphier/ +SOCKET TIMESTAMPING +M: Willem de Bruijn +S: Maintained +F: Documentation/networking/timestamping.rst +F: include/uapi/linux/net_tstamp.h +F: tools/testing/selftests/net/so_txtime.c + SOEKRIS NET48XX LED SUPPORT M: Chris Boot S: Maintained @@ -19665,7 +19528,7 @@ F: drivers/clk/spear/ F: drivers/pinctrl/spear/ SPI NOR SUBSYSTEM -M: Tudor Ambarus +M: Tudor Ambarus M: Pratyush Yadav R: Michael Walle L: linux-mtd@lists.infradead.org @@ -20063,6 +19926,7 @@ F: drivers/watchdog/sunplus_wdt.c SUPERH M: Yoshinori Sato M: Rich Felker +M: John Paul Adrian Glaubitz L: linux-sh@vger.kernel.org S: Maintained Q: http://patchwork.kernel.org/project/linux-sh/list/ @@ -20078,7 +19942,8 @@ L: linux-pm@vger.kernel.org S: Supported B: https://bugzilla.kernel.org F: Documentation/power/ -F: arch/x86/kernel/acpi/ +F: arch/x86/kernel/acpi/sleep* +F: arch/x86/kernel/acpi/wakeup* F: drivers/base/power/ F: include/linux/freezer.h F: include/linux/pm.h @@ -20295,8 +20160,7 @@ S: Maintained F: drivers/platform/x86/system76_acpi.c SYSV FILESYSTEM -M: Christoph Hellwig -S: Maintained +S: Orphan F: Documentation/filesystems/sysv-fs.rst F: fs/sysv/ F: include/linux/sysv_fs.h @@ -20687,6 +20551,7 @@ S: Supported Q: https://patchwork.kernel.org/project/linux-pm/list/ T: git git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git thermal F: Documentation/ABI/testing/sysfs-class-thermal +F: Documentation/admin-guide/thermal/ F: Documentation/devicetree/bindings/thermal/ F: Documentation/driver-api/thermal/ F: drivers/thermal/ @@ -20843,7 +20708,6 @@ W: https://linuxtv.org Q: http://patchwork.linuxtv.org/project/linux-media/list/ T: git git://linuxtv.org/mhadli/v4l-dvb-davinci_devices.git F: drivers/media/platform/ti/davinci/ -F: drivers/staging/media/deprecated/vpfe_capture/ F: include/media/davinci/ TI ENHANCED CAPTURE (eCAP) DRIVER @@ -21703,6 +21567,7 @@ F: include/uapi/linux/uvcvideo.h USB WEBCAM GADGET M: Laurent Pinchart +M: Daniel Scally L: linux-usb@vger.kernel.org S: Maintained F: drivers/usb/gadget/function/*uvc* @@ -21738,6 +21603,13 @@ T: git git://linuxtv.org/media_tree.git F: Documentation/admin-guide/media/zr364xx* F: drivers/staging/media/deprecated/zr364xx/ +USER DATAGRAM PROTOCOL (UDP) +M: Willem de Bruijn +S: Maintained +F: include/linux/udp.h +F: net/ipv4/udp.c +F: net/ipv6/udp.c + USER-MODE LINUX (UML) M: Richard Weinberger M: Anton Ivanov @@ -21783,11 +21655,9 @@ W: http://en.wikipedia.org/wiki/Util-linux T: git git://git.kernel.org/pub/scm/utils/util-linux/util-linux.git UUID HELPERS -M: Christoph Hellwig R: Andy Shevchenko L: linux-kernel@vger.kernel.org S: Maintained -T: git git://git.infradead.org/users/hch/uuid.git F: include/linux/uuid.h F: include/uapi/linux/uuid.h F: lib/test_uuid.c @@ -22246,7 +22116,9 @@ F: drivers/scsi/vmw_pvscsi.c F: drivers/scsi/vmw_pvscsi.h VMWARE VIRTUAL PTP CLOCK DRIVER -M: Vivek Thampi +M: Srivatsa S. Bhat (VMware) +M: Deep Shah +R: Alexey Makhalov R: VMware PV-Drivers Reviewers L: netdev@vger.kernel.org S: Supported @@ -22614,6 +22486,7 @@ S: Maintained T: git git://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git F: drivers/platform/olpc/ F: drivers/platform/x86/ +F: include/linux/platform_data/x86/ X86 PLATFORM DRIVERS - ARCH R: Darren Hart @@ -22899,6 +22772,13 @@ F: Documentation/devicetree/bindings/dma/xilinx/xlnx,zynqmp-dpdma.yaml F: drivers/dma/xilinx/xilinx_dpdma.c F: include/dt-bindings/dma/xlnx-zynqmp-dpdma.h +XILINX ZYNQMP OCM EDAC DRIVER +M: Shubhrajyoti Datta +M: Sai Krishna Potthuri +S: Maintained +F: Documentation/devicetree/bindings/memory-controllers/xlnx,zynqmp-ocmc-1.0.yaml +F: drivers/edac/zynqmp_edac.c + XILINX ZYNQMP PSGTR PHY DRIVER M: Anurag Kumar Vulisha M: Laurent Pinchart diff --git a/Makefile b/Makefile index c05b4fb7121e5fecefa3865af5eefd26a356b49b..8e5621ddadb2023af6a3df11694af8a8357f76c6 100644 --- a/Makefile +++ b/Makefile @@ -2,7 +2,7 @@ VERSION = 6 PATCHLEVEL = 2 SUBLEVEL = 0 -EXTRAVERSION = -rc2 +EXTRAVERSION = NAME = Hurr durr I'ma ninja sloth # *DOCUMENTATION* @@ -549,7 +549,7 @@ LDFLAGS_MODULE = CFLAGS_KERNEL = RUSTFLAGS_KERNEL = AFLAGS_KERNEL = -export LDFLAGS_vmlinux = +LDFLAGS_vmlinux = # Use USERINCLUDE when you must reference the UAPI directories only. USERINCLUDE := \ @@ -1248,6 +1248,18 @@ vmlinux.o modules.builtin.modinfo modules.builtin: vmlinux_o @: PHONY += vmlinux +# LDFLAGS_vmlinux in the top Makefile defines linker flags for the top vmlinux, +# not for decompressors. LDFLAGS_vmlinux in arch/*/boot/compressed/Makefile is +# unrelated; the decompressors just happen to have the same base name, +# arch/*/boot/compressed/vmlinux. +# Export LDFLAGS_vmlinux only to scripts/Makefile.vmlinux. +# +# _LDFLAGS_vmlinux is a workaround for the 'private export' bug: +# https://savannah.gnu.org/bugs/?61463 +# For Make > 4.4, the following simple code will work: +# vmlinux: private export LDFLAGS_vmlinux := $(LDFLAGS_vmlinux) +vmlinux: private _LDFLAGS_vmlinux := $(LDFLAGS_vmlinux) +vmlinux: export LDFLAGS_vmlinux = $(_LDFLAGS_vmlinux) vmlinux: vmlinux.o $(KBUILD_LDS) modpost $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.vmlinux @@ -1533,6 +1545,7 @@ endif # *.ko are usually independent of vmlinux, but CONFIG_DEBUG_INFOBTF_MODULES # is an exception. ifdef CONFIG_DEBUG_INFO_BTF_MODULES +KBUILD_BUILTIN := 1 modules: vmlinux endif @@ -1589,7 +1602,7 @@ endif # CONFIG_MODULES CLEAN_FILES += include/ksym vmlinux.symvers modules-only.symvers \ modules.builtin modules.builtin.modinfo modules.nsdeps \ compile_commands.json .thinlto-cache rust/test rust/doc \ - .vmlinux.objs .vmlinux.export.c + rust-project.json .vmlinux.objs .vmlinux.export.c # Directories & files removed with 'make mrproper' MRPROPER_FILES += include/config include/generated \ @@ -1986,7 +1999,7 @@ $(single-no-ko): $(build-dir) # Remove MODORDER when done because it is not the real one. PHONY += single_modules single_modules: $(single-no-ko) modules_prepare - $(Q){ $(foreach m, $(single-ko), echo $(extmod_prefix)$m;) } > $(MODORDER) + $(Q){ $(foreach m, $(single-ko), echo $(extmod_prefix)$(m:%.ko=%.o);) } > $(MODORDER) $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modpost ifneq ($(KBUILD_MODPOST_NOFINAL),1) $(Q)$(MAKE) -f $(srctree)/scripts/Makefile.modfinal diff --git a/arch/alpha/include/asm/Kbuild b/arch/alpha/include/asm/Kbuild index 42911c8340c7869bdb47b31ea159a4b16f805409..54f5126628c67a6bea8d2536efe6f5410ba8fb7d 100644 --- a/arch/alpha/include/asm/Kbuild +++ b/arch/alpha/include/asm/Kbuild @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 generated-y += syscall_table.h +generic-y += agp.h generic-y += export.h generic-y += kvm_para.h generic-y += mcs_spinlock.h diff --git a/arch/alpha/include/asm/agp.h b/arch/alpha/include/asm/agp.h deleted file mode 100644 index 7874f063d00017feff5f673124c99673ce74823e..0000000000000000000000000000000000000000 --- a/arch/alpha/include/asm/agp.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -#ifndef AGP_H -#define AGP_H 1 - -#include - -/* dummy for now */ - -#define map_page_into_agp(page) do { } while (0) -#define unmap_page_from_agp(page) do { } while (0) -#define flush_agp_cache() mb() - -/* GATT allocation. Returns/accepts GATT kernel virtual address. */ -#define alloc_gatt_pages(order) \ - ((char *)__get_free_pages(GFP_KERNEL, (order))) -#define free_gatt_pages(table, order) \ - free_pages((unsigned long)(table), (order)) - -#endif diff --git a/arch/alpha/kernel/process.c b/arch/alpha/kernel/process.c index 65fdae9e48f38d600418dfef36b2e96d7059f254..ce20c31828a01ed2cfeab7c844d3362b1e483fd8 100644 --- a/arch/alpha/kernel/process.c +++ b/arch/alpha/kernel/process.c @@ -57,7 +57,6 @@ EXPORT_SYMBOL(pm_power_off); void arch_cpu_idle(void) { wtint(0); - raw_local_irq_enable(); } void arch_cpu_idle_dead(void) diff --git a/arch/alpha/kernel/vmlinux.lds.S b/arch/alpha/kernel/vmlinux.lds.S index 5b78d640725db85b9d416a5600876b79718436fd..2efa7dfc798a9577815244b68ee0da3bea316d06 100644 --- a/arch/alpha/kernel/vmlinux.lds.S +++ b/arch/alpha/kernel/vmlinux.lds.S @@ -27,7 +27,6 @@ SECTIONS HEAD_TEXT TEXT_TEXT SCHED_TEXT - CPUIDLE_TEXT LOCK_TEXT *(.fixup) *(.gnu.warning) diff --git a/arch/arc/kernel/process.c b/arch/arc/kernel/process.c index 3369f0700702b78ac26c95a582d8810e443ec990..980b71da2f6105ffd3db9cfd52f1410ce1106dfd 100644 --- a/arch/arc/kernel/process.c +++ b/arch/arc/kernel/process.c @@ -114,6 +114,8 @@ void arch_cpu_idle(void) "sleep %0 \n" : :"I"(arg)); /* can't be "r" has to be embedded const */ + + raw_local_irq_disable(); } #else /* ARC700 */ @@ -122,6 +124,7 @@ void arch_cpu_idle(void) { /* sleep, but enable both set E1/E2 (levels of interrupts) before committing */ __asm__ __volatile__("sleep 0x3 \n"); + raw_local_irq_disable(); } #endif diff --git a/arch/arc/kernel/vmlinux.lds.S b/arch/arc/kernel/vmlinux.lds.S index 529ae50f9fe23ced655e9dbf72a4914761ef02d9..549c3f407918693f4407e4b0854cdd63d2017952 100644 --- a/arch/arc/kernel/vmlinux.lds.S +++ b/arch/arc/kernel/vmlinux.lds.S @@ -85,7 +85,6 @@ SECTIONS _stext = .; TEXT_TEXT SCHED_TEXT - CPUIDLE_TEXT LOCK_TEXT KPROBES_TEXT IRQENTRY_TEXT diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 43c7773b89ae7972d82eb3ab15937bb787d715ed..e24a9820e12fa0bea7e8e9db4e1b773264681a98 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -282,8 +282,7 @@ config PHYS_OFFSET default DRAM_BASE if !MMU default 0x00000000 if ARCH_FOOTBRIDGE default 0x10000000 if ARCH_OMAP1 || ARCH_RPC - default 0x30000000 if ARCH_S3C24XX - default 0xa0000000 if ARCH_IOP32X || ARCH_PXA + default 0xa0000000 if ARCH_PXA default 0xc0000000 if ARCH_EP93XX || ARCH_SA1100 default 0 help @@ -345,14 +344,16 @@ comment "CPU Core family selection" config ARCH_MULTI_V4 bool "ARMv4 based platforms (FA526, StrongARM)" depends on !ARCH_MULTI_V6_V7 - depends on !LD_IS_LLD + # https://github.com/llvm/llvm-project/issues/50764 + depends on !LD_IS_LLD || LLD_VERSION >= 160000 select ARCH_MULTI_V4_V5 select CPU_FA526 if !(CPU_SA110 || CPU_SA1100) config ARCH_MULTI_V4T bool "ARMv4T based platforms (ARM720T, ARM920T, ...)" depends on !ARCH_MULTI_V6_V7 - depends on !LD_IS_LLD + # https://github.com/llvm/llvm-project/issues/50764 + depends on !LD_IS_LLD || LLD_VERSION >= 160000 select ARCH_MULTI_V4_V5 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \ CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \ @@ -438,8 +439,6 @@ source "arch/arm/mach-berlin/Kconfig" source "arch/arm/mach-clps711x/Kconfig" -source "arch/arm/mach-cns3xxx/Kconfig" - source "arch/arm/mach-davinci/Kconfig" source "arch/arm/mach-digicolor/Kconfig" @@ -462,8 +461,6 @@ source "arch/arm/mach-hpe/Kconfig" source "arch/arm/mach-imx/Kconfig" -source "arch/arm/mach-iop32x/Kconfig" - source "arch/arm/mach-ixp4xx/Kconfig" source "arch/arm/mach-keystone/Kconfig" @@ -661,7 +658,9 @@ config ARM_ERRATA_458693 hazard might then cause a processor deadlock. The workaround enables the L1 caching of the NEON accesses and disables the PLD instruction in the ACTLR register. Note that setting specific bits in the ACTLR - register may not be available in non-secure mode. + register may not be available in non-secure mode and thus is not + available on a multiplatform kernel. This should be applied by the + bootloader instead. config ARM_ERRATA_460075 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data" @@ -674,7 +673,9 @@ config ARM_ERRATA_460075 and overwritten with stale memory contents from external memory. The workaround disables the write-allocate mode for the L2 cache via the ACTLR register. Note that setting specific bits in the ACTLR register - may not be available in non-secure mode. + may not be available in non-secure mode and thus is not available on + a multiplatform kernel. This should be applied by the bootloader + instead. config ARM_ERRATA_742230 bool "ARM errata: DMB operation may be faulty" @@ -687,7 +688,10 @@ config ARM_ERRATA_742230 ordering of the two writes. This workaround sets a specific bit in the diagnostic register of the Cortex-A9 which causes the DMB instruction to behave as a DSB, ensuring the correct behaviour of - the two writes. + the two writes. Note that setting specific bits in the diagnostics + register may not be available in non-secure mode and thus is not + available on a multiplatform kernel. This should be applied by the + bootloader instead. config ARM_ERRATA_742231 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption" @@ -702,7 +706,10 @@ config ARM_ERRATA_742231 replaced from one of the CPUs at the same time as another CPU is accessing it. This workaround sets specific bits in the diagnostic register of the Cortex-A9 which reduces the linefill issuing - capabilities of the processor. + capabilities of the processor. Note that setting specific bits in the + diagnostics register may not be available in non-secure mode and thus + is not available on a multiplatform kernel. This should be applied by + the bootloader instead. config ARM_ERRATA_643719 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect" @@ -739,7 +746,9 @@ config ARM_ERRATA_743622 register of the Cortex-A9 which disables the Store Buffer optimisation, preventing the defect from occurring. This has no visible impact on the overall performance or power consumption of the - processor. + processor. Note that setting specific bits in the diagnostics register + may not be available in non-secure mode and thus is not available on a + multiplatform kernel. This should be applied by the bootloader instead. config ARM_ERRATA_751472 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation" @@ -751,6 +760,10 @@ config ARM_ERRATA_751472 completion of a following broadcasted operation if the second operation is received by a CPU before the ICIALLUIS has completed, potentially leading to corrupted entries in the cache or TLB. + Note that setting specific bits in the diagnostics register may + not be available in non-secure mode and thus is not available on + a multiplatform kernel. This should be applied by the bootloader + instead. config ARM_ERRATA_754322 bool "ARM errata: possible faulty MMU translations following an ASID switch" @@ -931,12 +944,6 @@ config ISA config ISA_DMA_API bool -config PCI_NANOENGINE - bool "BSE nanoEngine PCI support" - depends on SA1100_NANOENGINE - help - Enable PCI on the BSE nanoEngine board. - config ARM_ERRATA_814220 bool "ARM errata: Cache maintenance by set/way operations can execute out of order" depends on CPU_V7 @@ -1465,19 +1472,6 @@ config ATAGS the ARM_ATAG_DTB_COMPAT option) then you may unselect this option to remove ATAGS support from your kernel binary. -config UNUSED_BOARD_FILES - bool "Board support for machines without known users" - depends on ATAGS - help - Most ATAGS based board files are completely unused and are - scheduled for removal in early 2023, and left out of kernels - by default now. If you are using a board file that is marked - as unused, turn on this option to build support into the kernel. - - To keep support for your individual board from being removed, - send a reply to the email discussion at - https://lore.kernel.org/all/CAK8P3a0Z9vGEQbVRBo84bSyPFM-LF+hs5w8ZA51g2Z+NsdtDQA@mail.gmail.com/ - config DEPRECATED_PARAM_STRUCT bool "Provide old way to pass kernel parameters" depends on ATAGS diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug index c345775f035bc4c3c3d86a1a3591554529d5d509..b407b7b9b715d666ba6ae9afffb6abe7b703e2fa 100644 --- a/arch/arm/Kconfig.debug +++ b/arch/arm/Kconfig.debug @@ -307,14 +307,6 @@ choice Say Y here if you want the debug print routines to direct their output to the second serial port on these devices. - config DEBUG_CNS3XXX - bool "Kernel Kernel low-level debugging on Cavium Networks CNS3xxx" - depends on ARCH_CNS3XXX - select DEBUG_UART_8250 - help - Say Y here if you want the debug print routines to direct - their output to the CNS3xxx UART0. - config DEBUG_DAVINCI_DA8XX_UART1 bool "Kernel low-level debugging on DaVinci DA8XX using UART1" depends on ARCH_DAVINCI_DA8XX @@ -331,14 +323,6 @@ choice Say Y here if you want the debug print routines to direct their output to UART2 serial port on DaVinci DA8XX devices. - config DEBUG_DAVINCI_DMx_UART0 - bool "Kernel low-level debugging on DaVinci DMx using UART0" - depends on ARCH_DAVINCI_DMx - select DEBUG_UART_8250 - help - Say Y here if you want the debug print routines to direct - their output to UART0 serial port on DaVinci DMx devices. - config DEBUG_DC21285_PORT bool "Kernel low-level debugging messages via footbridge serial port" depends on FOOTBRIDGE @@ -768,30 +752,6 @@ choice depends on ARCH_OMAP2PLUS select DEBUG_UART_8250 - config DEBUG_OMAP7XXUART1 - bool "Kernel low-level debugging via OMAP730 UART1" - depends on ARCH_OMAP730 - select DEBUG_UART_8250 - help - Say Y here if you want kernel low-level debugging support - on OMAP730 based platforms on the UART1. - - config DEBUG_OMAP7XXUART2 - bool "Kernel low-level debugging via OMAP730 UART2" - depends on ARCH_OMAP730 - select DEBUG_UART_8250 - help - Say Y here if you want kernel low-level debugging support - on OMAP730 based platforms on the UART2. - - config DEBUG_OMAP7XXUART3 - bool "Kernel low-level debugging via OMAP730 UART3" - depends on ARCH_OMAP730 - select DEBUG_UART_8250 - help - Say Y here if you want kernel low-level debugging support - on OMAP730 based platforms on the UART3. - config DEBUG_TI81XXUART1 bool "Kernel low-level debugging messages via TI81XX UART1 (ti8148evm)" depends on ARCH_OMAP2PLUS @@ -1046,7 +1006,6 @@ choice config DEBUG_S3C_UART0 depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS select DEBUG_EXYNOS_UART if ARCH_EXYNOS - select DEBUG_S3C24XX_UART if ARCH_S3C24XX select DEBUG_S3C64XX_UART if ARCH_S3C64XX select DEBUG_S5PV210_UART if ARCH_S5PV210 bool "Use Samsung S3C UART 0 for low-level debug" @@ -1058,7 +1017,6 @@ choice config DEBUG_S3C_UART1 depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS select DEBUG_EXYNOS_UART if ARCH_EXYNOS - select DEBUG_S3C24XX_UART if ARCH_S3C24XX select DEBUG_S3C64XX_UART if ARCH_S3C64XX select DEBUG_S5PV210_UART if ARCH_S5PV210 bool "Use Samsung S3C UART 1 for low-level debug" @@ -1070,7 +1028,6 @@ choice config DEBUG_S3C_UART2 depends on PLAT_SAMSUNG || ARCH_S5PV210 || ARCH_EXYNOS select DEBUG_EXYNOS_UART if ARCH_EXYNOS - select DEBUG_S3C24XX_UART if ARCH_S3C24XX select DEBUG_S3C64XX_UART if ARCH_S3C64XX select DEBUG_S5PV210_UART if ARCH_S5PV210 bool "Use Samsung S3C UART 2 for low-level debug" @@ -1090,33 +1047,6 @@ choice their output to UART 3. The port must have been initialised by the boot-loader before use. - config DEBUG_S3C2410_UART0 - depends on ARCH_S3C24XX - select DEBUG_S3C2410_UART - bool "Use S3C2410/S3C2412 UART 0 for low-level debug" - help - Say Y here if you want the debug print routines to direct - their output to UART 0. The port must have been initialised - by the boot-loader before use. - - config DEBUG_S3C2410_UART1 - depends on ARCH_S3C24XX - select DEBUG_S3C2410_UART - bool "Use S3C2410/S3C2412 UART 1 for low-level debug" - help - Say Y here if you want the debug print routines to direct - their output to UART 1. The port must have been initialised - by the boot-loader before use. - - config DEBUG_S3C2410_UART2 - depends on ARCH_S3C24XX - select DEBUG_S3C2410_UART - bool "Use S3C2410/S3C2412 UART 2 for low-level debug" - help - Say Y here if you want the debug print routines to direct - their output to UART 2. The port must have been initialised - by the boot-loader before use. - config DEBUG_SA1100 depends on ARCH_SA1100 bool "Use SA1100 UARTs for low-level debug" @@ -1276,8 +1206,8 @@ choice depends on MACH_STM32MP157 select DEBUG_STM32_UART help - Say Y here if you want kernel low-level debugging support - on STM32MP1 based platforms, wich default UART is wired on + Say Y here if you want kernel low-level debugging support on + STM32MP1-based platforms, where the default UART is wired to UART4, but another UART instance can be selected by modifying CONFIG_DEBUG_UART_PHYS and CONFIG_DEBUG_UART_VIRT. @@ -1479,13 +1409,6 @@ config DEBUG_AT91_UART config DEBUG_EXYNOS_UART bool -config DEBUG_S3C2410_UART - bool - select DEBUG_S3C24XX_UART - -config DEBUG_S3C24XX_UART - bool - config DEBUG_S3C64XX_UART bool @@ -1493,8 +1416,7 @@ config DEBUG_S5PV210_UART bool config DEBUG_S3C_UART - depends on DEBUG_S3C2410_UART || DEBUG_S3C24XX_UART || \ - DEBUG_S3C64XX_UART || DEBUG_S5PV210_UART || \ + depends on DEBUG_S3C64XX_UART || DEBUG_S5PV210_UART || \ DEBUG_EXYNOS_UART int default "0" if DEBUG_S3C_UART0 @@ -1595,7 +1517,7 @@ config DEBUG_LL_INCLUDE default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA0 default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA1 default "debug/renesas-scif.S" if DEBUG_RMOBILE_SCIFA4 - default "debug/s3c24xx.S" if DEBUG_S3C24XX_UART || DEBUG_S3C64XX_UART + default "debug/s3c24xx.S" if DEBUG_S3C64XX_UART default "debug/s5pv210.S" if DEBUG_S5PV210_UART default "debug/sti.S" if DEBUG_STIH41X_ASC2 default "debug/sti.S" if DEBUG_STIH41X_SBC_ASC1 @@ -1618,11 +1540,10 @@ config DEBUG_UART_PL01X # Compatibility options for 8250 config DEBUG_UART_8250 - def_bool ARCH_IOP32X || ARCH_IXP4XX || ARCH_RPC + def_bool ARCH_IXP4XX || ARCH_RPC config DEBUG_UART_PHYS hex "Physical base address of debug UART" - default 0x01c20000 if DEBUG_DAVINCI_DMx_UART0 default 0x01c28000 if DEBUG_SUNXI_UART0 default 0x01c28400 if DEBUG_SUNXI_UART1 default 0x01d0c000 if DEBUG_DAVINCI_DA8XX_UART1 @@ -1679,13 +1600,6 @@ config DEBUG_UART_PHYS default 0x4806e000 if DEBUG_OMAP2UART3 || DEBUG_OMAP4UART4 default 0x49020000 if DEBUG_OMAP3UART3 default 0x49042000 if DEBUG_OMAP3UART4 - default 0x50000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \ - DEBUG_S3C2410_UART0) - default 0x50004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \ - DEBUG_S3C2410_UART1) - default 0x50008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \ - DEBUG_S3C2410_UART2) - default 0x78000000 if DEBUG_CNS3XXX default 0x7c0003f8 if DEBUG_FOOTBRIDGE_COM1 default 0x7f005000 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART0 default 0x7f005400 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART1 @@ -1729,7 +1643,6 @@ config DEBUG_UART_PHYS default 0xfcb00000 if DEBUG_HI3620_UART default 0xfd883000 if DEBUG_ALPINE_UART0 default 0xfe531000 if DEBUG_STIH41X_SBC_ASC1 - default 0xfe800000 if ARCH_IOP32X default 0xfed32000 if DEBUG_STIH41X_ASC2 default 0xff690000 if DEBUG_RK32_UART2 default 0xffc02000 if DEBUG_SOCFPGA_UART0 @@ -1738,9 +1651,9 @@ config DEBUG_UART_PHYS default 0xffe40000 if DEBUG_RCAR_GEN1_SCIF0 default 0xffe42000 if DEBUG_RCAR_GEN1_SCIF2 default 0xfff36000 if DEBUG_HIGHBANK_UART - default 0xfffb0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1 - default 0xfffb0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2 - default 0xfffb9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3 + default 0xfffb0000 if DEBUG_OMAP1UART1 + default 0xfffb0800 if DEBUG_OMAP1UART2 + default 0xfffb9800 if DEBUG_OMAP1UART3 default 0xfffe8600 if DEBUG_BCM63XX_UART default 0xffffee00 if DEBUG_AT91_SAM9263_DBGU default 0xfffff200 if DEBUG_AT91_RM9200_DBGU @@ -1754,7 +1667,7 @@ config DEBUG_UART_PHYS DEBUG_RCAR_GEN2_SCIF2 || DEBUG_RCAR_GEN2_SCIF4 || \ DEBUG_RCAR_GEN2_SCIFA2 || \ DEBUG_RMOBILE_SCIFA0 || DEBUG_RMOBILE_SCIFA1 || \ - DEBUG_RMOBILE_SCIFA4 || DEBUG_S3C24XX_UART || \ + DEBUG_RMOBILE_SCIFA4 || \ DEBUG_S3C64XX_UART || \ DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \ DEBUG_DIGICOLOR_UA0 || \ @@ -1791,15 +1704,9 @@ config DEBUG_UART_VIRT default 0xf6200000 if DEBUG_PXA_UART1 default 0xf7000000 if DEBUG_SUN9I_UART0 default 0xf7000000 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART0 - default 0xf7000000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART0 || \ - DEBUG_S3C2410_UART0) default 0xf7000400 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART1 default 0xf7000800 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART2 default 0xf7000c00 if DEBUG_S3C64XX_UART && DEBUG_S3C_UART3 - default 0xf7004000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART1 || \ - DEBUG_S3C2410_UART1) - default 0xf7008000 if DEBUG_S3C24XX_UART && (DEBUG_S3C_UART2 || \ - DEBUG_S3C2410_UART2) default 0xf7020000 if DEBUG_AT91_SAMA5D2_UART1 default 0xf7fc9000 if DEBUG_BERLIN_UART default 0xf8007000 if DEBUG_HIP04_UART @@ -1818,7 +1725,6 @@ config DEBUG_UART_VIRT DEBUG_OMAP4UART2 || DEBUG_OMAP5UART2 default 0xfa06e000 if DEBUG_OMAP2UART3 || DEBUG_OMAP4UART4 default 0xfa71e000 if DEBUG_QCOM_UARTDM - default 0xfb002000 if DEBUG_CNS3XXX default 0xfb009000 if DEBUG_REALVIEW_STD_PORT default 0xfb00c000 if DEBUG_AT91_SAMA5D4_USART3 default 0xfb020000 if DEBUG_OMAP3UART3 @@ -1835,7 +1741,6 @@ config DEBUG_UART_VIRT default 0xfe018000 if DEBUG_MMP_UART3 default 0xfe100000 if DEBUG_IMX23_UART || DEBUG_IMX28_UART default 0xfe300000 if DEBUG_BCM_KONA_UART - default 0xfe800000 if ARCH_IOP32X default 0xfeb00000 if DEBUG_HI3620_UART || DEBUG_HIX5HD2_UART default 0xfeb24000 if DEBUG_RK3X_UART0 default 0xfeb26000 if DEBUG_RK3X_UART1 @@ -1846,7 +1751,6 @@ config DEBUG_UART_VIRT default 0xfec03000 if DEBUG_SOCFPGA_CYCLONE5_UART1 default 0xfec12000 if DEBUG_MVEBU_UART0 || DEBUG_MVEBU_UART0_ALTERNATE default 0xfec12100 if DEBUG_MVEBU_UART1_ALTERNATE - default 0xfec20000 if DEBUG_DAVINCI_DMx_UART0 default 0xfec90000 if DEBUG_RK32_UART2 default 0xfed0c000 if DEBUG_DAVINCI_DA8XX_UART1 default 0xfed0d000 if DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_SD5203_UART @@ -1859,14 +1763,14 @@ config DEBUG_UART_VIRT default 0xfec00000 if ARCH_IXP4XX && !CPU_BIG_ENDIAN default 0xfec00003 if ARCH_IXP4XX && CPU_BIG_ENDIAN default 0xfef36000 if DEBUG_HIGHBANK_UART - default 0xff0b0000 if DEBUG_OMAP1UART1 || DEBUG_OMAP7XXUART1 - default 0xff0b0800 if DEBUG_OMAP1UART2 || DEBUG_OMAP7XXUART2 - default 0xff0b9800 if DEBUG_OMAP1UART3 || DEBUG_OMAP7XXUART3 + default 0xff0b0000 if DEBUG_OMAP1UART1 + default 0xff0b0800 if DEBUG_OMAP1UART2 + default 0xff0b9800 if DEBUG_OMAP1UART3 default 0xffd01000 if DEBUG_HIP01_UART default DEBUG_UART_PHYS if !MMU depends on DEBUG_LL_UART_8250 || DEBUG_LL_UART_PL01X || \ DEBUG_UART_8250 || DEBUG_UART_PL01X || DEBUG_MESON_UARTAO || \ - DEBUG_QCOM_UARTDM || DEBUG_S3C24XX_UART || \ + DEBUG_QCOM_UARTDM || \ DEBUG_S3C64XX_UART || \ DEBUG_BCM63XX_UART || DEBUG_ASM9260_UART || \ DEBUG_DIGICOLOR_UA0 || \ @@ -1877,9 +1781,8 @@ config DEBUG_UART_VIRT config DEBUG_UART_8250_SHIFT int "Register offset shift for the 8250 debug UART" depends on DEBUG_LL_UART_8250 || DEBUG_UART_8250 - default 0 if DEBUG_FOOTBRIDGE_COM1 || ARCH_IOP32X || DEBUG_BCM_5301X || \ - DEBUG_BCM_HR2 || DEBUG_OMAP7XXUART1 || DEBUG_OMAP7XXUART2 || \ - DEBUG_OMAP7XXUART3 + default 0 if DEBUG_FOOTBRIDGE_COM1 || DEBUG_BCM_5301X || \ + DEBUG_BCM_HR2 default 3 if DEBUG_MSTARV7_PMUART default 2 @@ -1890,9 +1793,9 @@ config DEBUG_UART_8250_WORD default y if DEBUG_SOCFPGA_UART0 || DEBUG_SOCFPGA_ARRIA10_UART1 || \ DEBUG_SOCFPGA_CYCLONE5_UART1 || DEBUG_KEYSTONE_UART0 || \ DEBUG_KEYSTONE_UART1 || DEBUG_ALPINE_UART0 || \ - DEBUG_DAVINCI_DMx_UART0 || DEBUG_DAVINCI_DA8XX_UART1 || \ - DEBUG_DAVINCI_DA8XX_UART2 || DEBUG_BCM_IPROC_UART3 || \ - DEBUG_BCM_KONA_UART || DEBUG_RK32_UART2 + DEBUG_DAVINCI_DA8XX_UART1 || DEBUG_DAVINCI_DA8XX_UART2 || \ + DEBUG_BCM_IPROC_UART3 || DEBUG_BCM_KONA_UART || \ + DEBUG_RK32_UART2 config DEBUG_UART_8250_PALMCHIP bool "8250 UART is Palmchip BK-310x" diff --git a/arch/arm/Makefile b/arch/arm/Makefile index 4067f5169144246b22e96e734d9af369a32b1e45..485a439e22ca8340ac740b31875672cdc0351bc1 100644 --- a/arch/arm/Makefile +++ b/arch/arm/Makefile @@ -132,7 +132,7 @@ AFLAGS_NOWARN :=$(call as-option,-Wa$(comma)-mno-warn-deprecated,-Wa$(comma)-W) ifeq ($(CONFIG_THUMB2_KERNEL),y) CFLAGS_ISA :=-Wa,-mimplicit-it=always $(AFLAGS_NOWARN) -AFLAGS_ISA :=$(CFLAGS_ISA) -Wa$(comma)-mthumb -D__thumb2__=2 +AFLAGS_ISA :=$(CFLAGS_ISA) -Wa$(comma)-mthumb CFLAGS_ISA +=-mthumb else CFLAGS_ISA :=$(call cc-option,-marm,) $(AFLAGS_NOWARN) @@ -152,8 +152,6 @@ CHECKFLAGS += -D__arm__ # during boot, and this offset is critical to the functioning of # kexec-tools. textofs-y := 0x00008000 -# We don't want the htc bootloader to corrupt kernel during resume -textofs-$(CONFIG_PM_H1940) := 0x00108000 # RTD1195 has Boot ROM at start of address space textofs-$(CONFIG_ARCH_REALTEK) := 0x00108000 # SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory @@ -178,7 +176,6 @@ machine-$(CONFIG_ARCH_AXXIA) += axxia machine-$(CONFIG_ARCH_BCM) += bcm machine-$(CONFIG_ARCH_BERLIN) += berlin machine-$(CONFIG_ARCH_CLPS711X) += clps711x -machine-$(CONFIG_ARCH_CNS3XXX) += cns3xxx machine-$(CONFIG_ARCH_DAVINCI) += davinci machine-$(CONFIG_ARCH_DIGICOLOR) += digicolor machine-$(CONFIG_ARCH_DOVE) += dove @@ -189,7 +186,6 @@ machine-$(CONFIG_ARCH_GEMINI) += gemini machine-$(CONFIG_ARCH_HIGHBANK) += highbank machine-$(CONFIG_ARCH_HISI) += hisi machine-$(CONFIG_ARCH_HPE) += hpe -machine-$(CONFIG_ARCH_IOP32X) += iop32x machine-$(CONFIG_ARCH_IXP4XX) += ixp4xx machine-$(CONFIG_ARCH_KEYSTONE) += keystone machine-$(CONFIG_ARCH_LPC18XX) += lpc18xx @@ -213,7 +209,6 @@ machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2 machine-$(CONFIG_ARCH_ORION5X) += orion5x machine-$(CONFIG_ARCH_PXA) += pxa machine-$(CONFIG_ARCH_QCOM) += qcom -machine-$(CONFIG_ARCH_RDA) += rda machine-$(CONFIG_ARCH_REALTEK) += realtek machine-$(CONFIG_ARCH_ROCKCHIP) += rockchip machine-$(CONFIG_ARCH_RPC) += rpc @@ -319,6 +314,10 @@ endif # My testing targets (bypasses dependencies) bp:; $(Q)$(MAKE) $(build)=$(boot) $(boot)/bootpImage +include $(srctree)/scripts/Makefile.defconf +PHONY += multi_v7_lpae_defconfig +multi_v7_lpae_defconfig: + $(call merge_into_defconfig,multi_v7_defconfig,lpae) define archhelp echo '* zImage - Compressed kernel image (arch/$(ARCH)/boot/zImage)' @@ -334,4 +333,6 @@ define archhelp echo ' (distribution) /sbin/$(INSTALLKERNEL) or' echo ' install to $$(INSTALL_PATH) and run lilo' echo ' vdso_install - Install unstripped vdso.so to $$(INSTALL_MOD_PATH)/vdso' + echo + echo ' multi_v7_lpae_defconfig - multi_v7_defconfig with CONFIG_ARM_LPAE enabled' endef diff --git a/arch/arm/boot/compressed/head-sa1100.S b/arch/arm/boot/compressed/head-sa1100.S index 95abdd850fe35bcb2257b4449e0112cd9b478aa5..23eae1a65064c8eeed36d174274b7cd8eaab6640 100644 --- a/arch/arm/boot/compressed/head-sa1100.S +++ b/arch/arm/boot/compressed/head-sa1100.S @@ -19,10 +19,6 @@ __SA1100_start: @ Preserve r8/r7 i.e. kernel entry values #ifdef CONFIG_SA1100_COLLIE mov r7, #MACH_TYPE_COLLIE -#endif -#ifdef CONFIG_SA1100_SIMPAD - @ UNTIL we've something like an open bootldr - mov r7, #MACH_TYPE_SIMPAD @should be 87 #endif mrc p15, 0, r0, c1, c0, 0 @ read control reg ands r0, r0, #0x0d diff --git a/arch/arm/boot/compressed/misc-ep93xx.h b/arch/arm/boot/compressed/misc-ep93xx.h index 3dc942589cba428936119f39f95d37a6cfa97dc2..65b4121d14904abd49eb9a9142f84a0c92fd3fc0 100644 --- a/arch/arm/boot/compressed/misc-ep93xx.h +++ b/arch/arm/boot/compressed/misc-ep93xx.h @@ -57,8 +57,7 @@ static inline void ep93xx_decomp_setup(void) if (machine_is_ts72xx()) ts72xx_watchdog_disable(); - if (machine_is_adssphere() || - machine_is_edb9301() || + if (machine_is_edb9301() || machine_is_edb9302() || machine_is_edb9302a() || machine_is_edb9302a() || @@ -69,16 +68,6 @@ static inline void ep93xx_decomp_setup(void) machine_is_edb9315() || machine_is_edb9315a() || machine_is_edb9315a() || - machine_is_gesbc9312() || - machine_is_micro9() || - machine_is_micro9l() || - machine_is_micro9m() || - machine_is_micro9s() || - machine_is_micro9m() || - machine_is_micro9l() || - machine_is_micro9s() || - machine_is_sim_one() || - machine_is_snapper_cl15() || machine_is_ts72xx() || machine_is_bk3() || machine_is_vision_ep9307()) diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index d08a3c450ce7266dcf49299bed99acbd6602c426..efe4152e5846dc0402a3d324cbf5b79981f694b6 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -51,6 +51,7 @@ dtb-$(CONFIG_SOC_AT91SAM9) += \ at91sam9x25ek.dtb \ at91sam9x35ek.dtb dtb-$(CONFIG_SOC_SAM9X60) += \ + at91-sam9x60_curiosity.dtb \ at91-sam9x60ek.dtb dtb-$(CONFIG_SOC_SAM_V7) += \ at91-kizbox2-2.dtb \ @@ -246,6 +247,7 @@ dtb-$(CONFIG_ARCH_EXYNOS5) += \ exynos5422-odroidxu3.dtb \ exynos5422-odroidxu3-lite.dtb \ exynos5422-odroidxu4.dtb \ + exynos5422-samsung-k3g.dtb \ exynos5800-peach-pi.dtb dtb-$(CONFIG_ARCH_GEMINI) += \ gemini-dlink-dir-685.dtb \ @@ -465,6 +467,7 @@ dtb-$(CONFIG_SOC_IMX53) += \ imx53-ppd.dtb \ imx53-qsb.dtb \ imx53-qsrb.dtb \ + imx53-sk-imx53.dtb \ imx53-smd.dtb \ imx53-tx53-x03x.dtb \ imx53-tx53-x13x.dtb \ @@ -740,6 +743,9 @@ dtb-$(CONFIG_SOC_IMX6UL) += \ imx6ull-colibri-wifi-eval-v3.dtb \ imx6ull-colibri-wifi-iris.dtb \ imx6ull-colibri-wifi-iris-v2.dtb \ + imx6ull-dhcom-drc02.dtb \ + imx6ull-dhcom-pdk2.dtb \ + imx6ull-dhcom-picoitx.dtb \ imx6ull-jozacp.dtb \ imx6ull-kontron-bl.dtb \ imx6ull-myir-mys-6ulx-eval.dtb \ @@ -1127,12 +1133,14 @@ dtb-$(CONFIG_ARCH_RENESAS) += \ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rv1108-elgin-r1.dtb \ rv1108-evb.dtb \ + rv1126-edgeble-neu2-io.dtb \ rk3036-evb.dtb \ rk3036-kylin.dtb \ rk3066a-bqcurie2.dtb \ rk3066a-marsboard.dtb \ rk3066a-mk808.dtb \ rk3066a-rayeager.dtb \ + rk3128-evb.dtb \ rk3188-bqedison2qc.dtb \ rk3188-px3-evb.dtb \ rk3188-radxarock.dtb \ @@ -1163,8 +1171,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += \ rk3288-veyron-speedy.dtb \ rk3288-veyron-tiger.dtb \ rk3288-vyasa.dtb -dtb-$(CONFIG_ARCH_S3C24XX) += \ - s3c2416-smdk2416.dtb dtb-$(CONFIG_ARCH_S3C64XX) += \ s3c6410-mini6410.dtb \ s3c6410-smdk6410.dtb @@ -1179,6 +1185,7 @@ dtb-$(CONFIG_ARCH_S5PV210) += \ dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += \ socfpga_arria5_socdk.dtb \ socfpga_arria10_chameleonv3.dtb \ + socfpga_arria10_mercury_pe1.dtb \ socfpga_arria10_socdk_nand.dtb \ socfpga_arria10_socdk_qspi.dtb \ socfpga_arria10_socdk_sdmmc.dtb \ @@ -1605,6 +1612,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-facebook-elbert.dtb \ aspeed-bmc-facebook-fuji.dtb \ aspeed-bmc-facebook-galaxy100.dtb \ + aspeed-bmc-facebook-greatlakes.dtb \ aspeed-bmc-facebook-minipack.dtb \ aspeed-bmc-facebook-tiogapass.dtb \ aspeed-bmc-facebook-wedge40.dtb \ @@ -1641,6 +1649,7 @@ dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-bmc-inventec-transformers.dtb \ aspeed-bmc-tyan-s7106.dtb \ aspeed-bmc-tyan-s8036.dtb \ + aspeed-bmc-ufispace-ncplite.dtb \ aspeed-bmc-vegman-n110.dtb \ aspeed-bmc-vegman-rx20.dtb \ aspeed-bmc-vegman-sx20.dtb diff --git a/arch/arm/boot/dts/alpine.dtsi b/arch/arm/boot/dts/alpine.dtsi index 4be9887033f99a318c383bb0ad9dad8f12c32673..ff68dfb4eb7874a00d398bf7dfc2d242385c5620 100644 --- a/arch/arm/boot/dts/alpine.dtsi +++ b/arch/arm/boot/dts/alpine.dtsi @@ -126,7 +126,7 @@ ; }; - uart0: uart@fd883000 { + uart0: serial@fd883000 { compatible = "ns16550a"; reg = <0x0 0xfd883000 0x0 0x1000>; clock-frequency = <375000000>; @@ -135,7 +135,7 @@ reg-io-width = <4>; }; - uart1: uart@fd884000 { + uart1: serial@fd884000 { compatible = "ns16550a"; reg = <0x0 0xfd884000 0x0 0x1000>; clock-frequency = <375000000>; diff --git a/arch/arm/boot/dts/am335x-nano.dts b/arch/arm/boot/dts/am335x-nano.dts index b6f2567bd65a448399a6b5ff94fc1d753e4f25ed..c447aebd8d8663c831e596d259a4e9a952257e52 100644 --- a/arch/arm/boot/dts/am335x-nano.dts +++ b/arch/arm/boot/dts/am335x-nano.dts @@ -120,8 +120,8 @@ uart3_pins: uart3_pins { pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data10.uart3_ctsn */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE6) /* lcd_data11.uart3_rtsn */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA10, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data10.gpio2[16] */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA11, PIN_OUTPUT, MUX_MODE7) /* lcd_data11.gpio2[17] */ AM33XX_PADCONF(AM335X_PIN_SPI0_CS1, PIN_INPUT, MUX_MODE1) /* spi0_cs1.uart3_rxd */ AM33XX_PADCONF(AM335X_PIN_ECAP0_IN_PWM0_OUT, PIN_OUTPUT, MUX_MODE1) /* ecap0_in_pwm0_out.uart3_txd */ >; @@ -129,8 +129,8 @@ uart4_pins: uart4_pins { pinctrl-single,pins = < - AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE6) /* lcd_data12.uart4_ctsn */ - AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE6) /* lcd_data13.uart4_rtsn */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA12, PIN_INPUT_PULLUP, MUX_MODE7) /* lcd_data12.gpio0[8] */ + AM33XX_PADCONF(AM335X_PIN_LCD_DATA13, PIN_OUTPUT, MUX_MODE7) /* lcd_data13.gpio0[9] */ AM33XX_PADCONF(AM335X_PIN_UART0_CTSN, PIN_INPUT, MUX_MODE1) /* uart0_ctsn.uart4_rxd */ AM33XX_PADCONF(AM335X_PIN_UART0_RTSN, PIN_OUTPUT, MUX_MODE1) /* uart0_rtsn.uart4_txd */ >; @@ -187,12 +187,22 @@ &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins>; + rts-gpio = <&gpio2 17 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + rs485-rx-during-tx; + rs485-rts-delay = <1 1>; + linux,rs485-enabled-at-boot-time; status = "okay"; }; &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins>; + rts-gpio = <&gpio0 9 GPIO_ACTIVE_HIGH>; + rs485-rts-active-high; + rs485-rx-during-tx; + rs485-rts-delay = <1 1>; + linux,rs485-enabled-at-boot-time; status = "okay"; }; @@ -220,6 +230,11 @@ reg = <0x24>; }; + temperature-sensor@48 { + compatible = "lm75"; + reg = <0x48>; + }; + eeprom@53 { compatible = "microchip,24c02", "atmel,24c02"; reg = <0x53>; @@ -403,8 +418,13 @@ pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; bus-width = <4>; - cd-gpios = <&gpio3 8 0>; - wp-gpios = <&gpio3 18 0>; + cd-debounce-delay-ms = <5>; + cd-gpios = <&gpio3 8 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>; +}; + +&usb0 { + dr_mode = "host"; }; #include "tps65217.dtsi" diff --git a/arch/arm/boot/dts/am3874-iceboard.dts b/arch/arm/boot/dts/am3874-iceboard.dts index d039af87936761a316c1d81080113219d81f12be..791478e81c5ad5b30239a1dc6905dbee10744c9d 100644 --- a/arch/arm/boot/dts/am3874-iceboard.dts +++ b/arch/arm/boot/dts/am3874-iceboard.dts @@ -106,7 +106,7 @@ * "i2c-mux-idle-disconnect" is important. */ - pca9548@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; reg = <0x70>; #address-cells = <1>; @@ -256,7 +256,7 @@ }; &i2c2 { - pca9548@71 { + i2c-mux@71 { compatible = "nxp,pca9548"; reg = <0x71>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/armada-38x.dtsi b/arch/arm/boot/dts/armada-38x.dtsi index 12933eff419ff877366f804e0488b666a5121230..446861b6b17b2ae628a42a4a32dca94a0b5b1f21 100644 --- a/arch/arm/boot/dts/armada-38x.dtsi +++ b/arch/arm/boot/dts/armada-38x.dtsi @@ -304,7 +304,7 @@ }; gpio0: gpio@18100 { - compatible = "marvell,armadaxp-gpio", + compatible = "marvell,armada-370-gpio", "marvell,orion-gpio"; reg = <0x18100 0x40>, <0x181c0 0x08>; reg-names = "gpio", "pwm"; @@ -323,7 +323,7 @@ }; gpio1: gpio@18140 { - compatible = "marvell,armadaxp-gpio", + compatible = "marvell,armada-370-gpio", "marvell,orion-gpio"; reg = <0x18140 0x40>, <0x181c8 0x08>; reg-names = "gpio", "pwm"; diff --git a/arch/arm/boot/dts/armada-39x.dtsi b/arch/arm/boot/dts/armada-39x.dtsi index 1e05208d9f3415f3ee5cd72084a69bf4460d9f8c..9d1cac49c022f07c315efabc57c5f08158c2833a 100644 --- a/arch/arm/boot/dts/armada-39x.dtsi +++ b/arch/arm/boot/dts/armada-39x.dtsi @@ -213,7 +213,7 @@ }; gpio0: gpio@18100 { - compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio"; + compatible = "marvell,orion-gpio"; reg = <0x18100 0x40>; ngpios = <32>; gpio-controller; @@ -227,7 +227,7 @@ }; gpio1: gpio@18140 { - compatible = "marvell,armadaxp-gpio", "marvell,orion-gpio"; + compatible = "marvell,orion-gpio"; reg = <0x18140 0x40>; ngpios = <28>; gpio-controller; diff --git a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts index 6406a0f080ee6b7c73db55e222d818f60c1e9afb..6bded774c45752dd84bf17b8ad8b495e6f1ab4aa 100644 --- a/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts +++ b/arch/arm/boot/dts/aspeed-bmc-amd-ethanolx.dts @@ -5,6 +5,7 @@ #include "aspeed-g5.dtsi" #include +#include / { model = "AMD EthanolX BMC"; @@ -58,10 +59,22 @@ flash@0 { status = "okay"; m25p,fast-read; + label = "bmc"; #include "openbmc-flash-layout.dtsi" }; }; +&spi1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_spi1_default>; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bios"; + spi-max-frequency = <100000000>; + }; +}; &mac0 { status = "okay"; @@ -78,7 +91,9 @@ status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_txd1_default - &pinctrl_rxd1_default>; + &pinctrl_rxd1_default + &pinctrl_nrts1_default + &pinctrl_ncts1_default>; }; &uart5 { @@ -160,7 +175,7 @@ &i2c3 { status = "okay"; eeprom@50 { - compatible = "atmel,24c256"; + compatible = "atmel,24c128"; reg = <0x50>; pagesize = <64>; }; @@ -261,6 +276,12 @@ status = "okay"; }; +&vuart { + status = "okay"; + aspeed,lpc-io-reg = <0x3f8>; + aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_HIGH>; +}; + &pwm_tacho { status = "okay"; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts index a619eec70633a38456267fe71ac7e0d0f10846e4..e899de681f4752d4077b55a0cd4f8858c6e23df0 100644 --- a/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts @@ -307,7 +307,7 @@ flash@1 { status = "okay"; m25p,fast-read; - label = "flash1"; + label = "alt-bmc"; spi-max-frequency = <50000000>; }; }; @@ -1064,3 +1064,14 @@ bias-disable; }; }; + +&wdt1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; + aspeed,reset-type = "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration = <256>; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts new file mode 100644 index 0000000000000000000000000000000000000000..8c05bd56ce1eb459fc2a80fbbe8adc2fb395d995 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-facebook-greatlakes.dts @@ -0,0 +1,241 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright 2022 Facebook Inc. + +/dts-v1/; +#include "aspeed-g6.dtsi" +#include +#include +#include + +/ { + model = "Facebook Greatlakes BMC"; + compatible = "facebook,greatlakes-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 0>, <&adc1 2>, <&adc1 3>, <&adc1 4>, + <&adc1 5>, <&adc1 6>; + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&wdt1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdtrst1_default>; + aspeed,reset-type = "soc"; + aspeed,external-signal; + aspeed,ext-push-pull; + aspeed,ext-active-high; + aspeed,ext-pulse-duration = <256>; +}; + +&mac3 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii4_default>; + no-hw-checksum; + use-ncsi; + mlx,multi-host; + ncsi-ctrl,start-redo-probe; + ncsi-ctrl,no-channel-monitor; + ncsi-package = <1>; + ncsi-channel = <1>; + ncsi-rexmit = <1>; + ncsi-timeout = <2>; +}; + +&rtc { + status = "okay"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; + flash@1 { + status = "okay"; + m25p,fast-read; + label = "bmc2"; + spi-rx-bus-width = <4>; + spi-max-frequency = <50000000>; + }; +}; + +&i2c0 { + status = "okay"; + multi-master; + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c1 { + status = "okay"; + multi-master; + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c2 { + status = "okay"; + multi-master; + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c3 { + status = "okay"; + multi-master; + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c4 { + status = "okay"; +}; + +&i2c5 { + status = "okay"; +}; + +&i2c6 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +}; + +&i2c8 { + status = "okay"; + temperature-sensor@1f { + compatible = "ti,tmp421"; + reg = <0x1f>; + }; + // NIC EEPROM + eeprom@50 { + compatible = "st,24c32"; + reg = <0x50>; + }; +}; + +&i2c9 { + status = "okay"; + multi-master; + ipmb@10 { + compatible = "ipmb-dev"; + reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>; + i2c-protocol; + }; +}; + +&i2c10 { + status = "okay"; +}; + +&i2c11 { + status = "okay"; + eeprom@51 { + compatible = "atmel,24c128"; + reg = <0x51>; + }; + eeprom@54 { + compatible = "atmel,24c128"; + reg = <0x54>; + }; +}; + +&i2c12 { + status = "okay"; + temperature-sensor@4f { + compatible = "lm75"; + reg = <0x4f>; + }; +}; + +&i2c13 { + status = "okay"; +}; + +&adc0 { + ref_voltage = <2500>; + status = "okay"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + ref_voltage = <2500>; + status = "okay"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc10_default + &pinctrl_adc11_default &pinctrl_adc12_default + &pinctrl_adc13_default &pinctrl_adc14_default>; +}; + + +&ehci0 { + status = "okay"; +}; + +&ehci1 { + status = "okay"; +}; + +&uhci { + status = "okay"; +}; + +&gpio0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiu1_default &pinctrl_gpiu7_default>; +}; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts index d1971ddf06a5d4e18b2e80dffe2b8fb4c7bce8b1..0f9a4f0a5571dd664f2c10ac250d208d1d57b1b9 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-bonnell.dts @@ -751,7 +751,7 @@ }; pca9849@75 { - compatible = "nxp,pca849"; + compatible = "nxp,pca9849"; reg = <0x75>; #address-cells = <1>; #size-cells = <0>; @@ -857,6 +857,10 @@ status = "okay"; }; +&uart2 { + status = "okay"; +}; + &vuart1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts index 1448ea895be439fd9a8e8ed3603bdfe59d324ad7..456ca2830a31b92c49b1696faad57766eaae0a6b 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts @@ -3649,6 +3649,10 @@ status = "okay"; }; +&uart2 { + status = "okay"; +}; + &vuart1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts index 20ef958698ec772a84420f0987c688cc081cfa45..e1b5d44308fe7008e22cd1d43625593c1dffb211 100644 --- a/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +++ b/arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts @@ -2352,6 +2352,10 @@ }; }; +&uart2 { + status = "okay"; +}; + &vuart1 { status = "okay"; }; diff --git a/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts b/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts index 708ee78e4b83066ef453e4b35863bed23cdf8fa5..f6c4549c0ac47a584235d648328d1b633d1aa65d 100644 --- a/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts +++ b/arch/arm/boot/dts/aspeed-bmc-tyan-s8036.dts @@ -364,6 +364,7 @@ &kcs3 { status = "okay"; aspeed,lpc-io-reg = <0xca2>; + aspeed,lpc-interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; }; /* Enable BMC VGA output to show an early (pre-BIOS) boot screen */ diff --git a/arch/arm/boot/dts/aspeed-bmc-ufispace-ncplite.dts b/arch/arm/boot/dts/aspeed-bmc-ufispace-ncplite.dts new file mode 100644 index 0000000000000000000000000000000000000000..7ab29129d1e4e98370e4b6575aee230b2bf65f19 --- /dev/null +++ b/arch/arm/boot/dts/aspeed-bmc-ufispace-ncplite.dts @@ -0,0 +1,360 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +// Copyright (c) 2022 Ufispace Co., Ltd. +/dts-v1/; + +#include "aspeed-g6.dtsi" +#include +#include + +/ { + model = "Ufispace NCPLite BMC"; + compatible = "ufispace,ncplite-bmc", "aspeed,ast2600"; + + aliases { + serial4 = &uart5; + }; + + chosen { + stdout-path = &uart5; + bootargs = "console=ttyS4,115200n8 earlycon"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x80000000 0x80000000>; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc0 0>, <&adc0 1>, <&adc0 2>, <&adc0 3>, + <&adc0 4>, <&adc0 5>, <&adc0 6>, <&adc0 7>, + <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>, + <&adc1 4>, <&adc1 5>, <&adc1 6>, <&adc1 7>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + fan-status-int-l { + label = "fan-status-int-l"; + gpios = <&gpio0 ASPEED_GPIO(M, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + allpwr-good { + label = "allpwr-good"; + gpios = <&gpio0 ASPEED_GPIO(V, 4) GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + + psu0-alert-n { + label = "psu0-alert-n"; + gpios = <&gpio0 ASPEED_GPIO(V, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + psu1-alert-n { + label = "psu1-alert-n"; + gpios = <&gpio0 ASPEED_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + int-thermal-alert { + label = "int-thermal-alert"; + gpios = <&gpio0 ASPEED_GPIO(P, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + cpu-caterr-l { + label = "cpu-caterr-l"; + gpios = <&gpio0 ASPEED_GPIO(N, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + cpu-thermtrip-l { + label = "cpu-thermtrip-l"; + gpios = <&gpio0 ASPEED_GPIO(V, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + psu0-presence-l { + label = "psu0-presence-l"; + gpios = <&gpio0 ASPEED_GPIO(F, 6) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + psu1-presence-l { + label = "psu1-presence-l"; + gpios = <&gpio0 ASPEED_GPIO(F, 7) GPIO_ACTIVE_LOW>; + linux,code = ; + }; + + psu0-power-ok { + label = "psu0-power-ok"; + gpios = <&gpio0 ASPEED_GPIO(M, 4) GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + + psu1-power-ok { + label = "psu1-power-ok"; + gpios = <&gpio0 ASPEED_GPIO(M, 5) GPIO_ACTIVE_HIGH>; + linux,code = ; + }; + }; + + gpio-keys-polled { + compatible = "gpio-keys-polled"; + #address-cells = <1>; + #size-cells = <0>; + poll-interval = <1000>; + + fan0-presence { + label = "fan0-presence"; + gpios = <&fan_ioexp 2 GPIO_ACTIVE_LOW>; + linux,code = <2>; + }; + + fan1-presence { + label = "fan1-presence"; + gpios = <&fan_ioexp 6 GPIO_ACTIVE_LOW>; + linux,code = <6>; + }; + + fan2-presence { + label = "fan2-presence"; + gpios = <&fan_ioexp 10 GPIO_ACTIVE_LOW>; + linux,code = <10>; + }; + + fan3-presence { + label = "fan3-presence"; + gpios = <&fan_ioexp 14 GPIO_ACTIVE_LOW>; + linux,code = <14>; + }; + }; +}; + +&mac2 { + status = "okay"; + use-ncsi; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rmii3_default>; + clocks = <&syscon ASPEED_CLK_GATE_MAC3CLK>, + <&syscon ASPEED_CLK_MAC3RCLK>; + clock-names = "MACCLK", "RCLK"; +}; + +&fmc { + status = "okay"; + flash@0 { + status = "okay"; + m25p,fast-read; + label = "bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64.dtsi" + }; + + flash@1 { + status = "okay"; + m25p,fast-read; + label = "alt-bmc"; + spi-max-frequency = <50000000>; +#include "openbmc-flash-layout-64-alt.dtsi" + }; +}; + +&uart1 { + status = "okay"; +}; + +&uart4 { + status = "okay"; +}; + +&uart5 { + status = "okay"; +}; + +&kcs3 { + status = "okay"; + aspeed,lpc-io-reg = <0xca2>; +}; + +&lpc_reset { + status = "okay"; +}; + +&lpc_ctrl { + status = "okay"; +}; + +&uart_routing { + status = "okay"; +}; + +&wdt1 { + status = "okay"; +}; + +&wdt2 { + status = "okay"; +}; + +&peci0 { + status = "okay"; +}; + +&udc { + status = "okay"; +}; + +&adc0 { + vref = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default + &pinctrl_adc2_default &pinctrl_adc3_default + &pinctrl_adc4_default &pinctrl_adc5_default + &pinctrl_adc6_default &pinctrl_adc7_default>; +}; + +&adc1 { + vref = <2500>; + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default + &pinctrl_adc10_default &pinctrl_adc11_default + &pinctrl_adc12_default &pinctrl_adc13_default + &pinctrl_adc14_default &pinctrl_adc15_default>; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + lm75@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + + lm75@49 { + compatible = "national,lm75"; + reg = <0x49>; + }; + + lm86@4c { + compatible = "national,lm86"; + reg = <0x4c>; + }; +}; + +&i2c2 { + status = "okay"; + + lm75@4f { + cpmpatible = "national,lm75"; + reg = <0x4f>; + }; + + fan_ioexp: pca9535@20 { + compatible = "nxp,pca9535"; + reg = <0x20>; + #address-cells = <1>; + #size-cells = <0>; + gpio-controller; + #gpio-cells = <2>; + + gpio-line-names = + "","","presence-fan0","", + "","","presence-fan1","", + "","","presence-fan2","", + "","","presence-fan3",""; + }; +}; + +&i2c3 { + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c128"; + reg = <0x50>; + pagesize = <64>; + }; +}; + +&i2c4 { + status = "okay"; + + psu@58 { + compatible = "pmbus"; + reg = <0x58>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <1>; + }; +}; + +&i2c5 { + status = "okay"; + + psu@58 { + compatible = "pmbus"; + reg = <0x58>; + }; + + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <1>; + }; +}; + +&i2c8 { + status = "okay"; +}; + +&i2c10 { + status = "okay"; + + lm75@4d { + compatible = "national,lm75"; + reg = <0x4d>; + }; +}; + +&gpio0 { + status = "okay"; + + gpio-line-names = + /*A0-A7*/ "","","","","","","","", + /*B0-B7*/ "","","","","","","","", + /*C0-C7*/ "","","","","","","","", + /*D0-D7*/ "","","","","","","","", + /*E0-E7*/ "","","","","","","","", + /*F0-F7*/ "CPU_PWRGD","","","power-button","host0-ready","","presence-ps0","presence-ps1", + /*G0-G7*/ "","","","","","","","", + /*H0-H7*/ "","","","","","","","", + /*I0-I7*/ "","","","","","reset-button","","", + /*J0-J7*/ "","","","","","","","", + /*K0-K7*/ "","","","","","","","", + /*L0-L7*/ "","","","","","","","", + /*M0-M7*/ "","","","","","","","", + /*N0-N7*/ "power-chassis-control0","power-chassis-control1","","","","","","", + /*O0-O7*/ "","","","","","","","", + /*P0-P7*/ "","","","","","","","", + /*Q0-Q7*/ "","","","","","","","", + /*R0-R7*/ "","","","","","","","", + /*S0-S7*/ "","","","","","","","", + /*T0-T7*/ "","","","","","","","", + /*U0-U7*/ "","","","","","","","", + /*V0-V7*/ "","","","","power-chassis-good","","",""; +}; diff --git a/arch/arm/boot/dts/at91-gatwick.dts b/arch/arm/boot/dts/at91-gatwick.dts index 2c718cf84d7b444926ec3db9a1bb204db0aedc2c..551300fd7746939df6e13a7d1fe5b83d99da978c 100644 --- a/arch/arm/boot/dts/at91-gatwick.dts +++ b/arch/arm/boot/dts/at91-gatwick.dts @@ -31,37 +31,37 @@ leds { compatible = "gpio-leds"; - ethernet { + led-ethernet { label = "gatwick:yellow:ethernet"; gpios = <&pioA 10 GPIO_ACTIVE_LOW>; default-state = "off"; }; - wifi { + led-wifi { label = "gatwick:green:wifi"; gpios = <&pioA 28 GPIO_ACTIVE_LOW>; default-state = "off"; }; - ble { + led-ble { label = "gatwick:blue:ble"; gpios = <&pioA 22 GPIO_ACTIVE_LOW>; default-state = "off"; }; - lora { + led-lora { label = "gatwick:orange:lora"; gpios = <&pioA 26 GPIO_ACTIVE_LOW>; default-state = "off"; }; - blank { + led-blank { label = "gatwick:green:blank"; gpios = <&pioA 24 GPIO_ACTIVE_LOW>; default-state = "off"; }; - user { + led-user { label = "gatwick:yellow:user"; gpios = <&pioA 12 GPIO_ACTIVE_LOW>; default-state = "off"; diff --git a/arch/arm/boot/dts/at91-sam9x60_curiosity.dts b/arch/arm/boot/dts/at91-sam9x60_curiosity.dts new file mode 100644 index 0000000000000000000000000000000000000000..cb86a3a170ce1481a16957c3b71b44089946a4e4 --- /dev/null +++ b/arch/arm/boot/dts/at91-sam9x60_curiosity.dts @@ -0,0 +1,503 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * at91-sam9x60_curiosity.dts - Device Tree file for Microchip SAM9X60 Curiosity board + * + * Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries + * + * Author: Durai Manickam KR + */ +/dts-v1/; +#include "sam9x60.dtsi" +#include + +/ { + model = "Microchip SAM9X60 Curiosity"; + compatible = "microchip,sam9x60-curiosity", "microchip,sam9x60", "atmel,at91sam9"; + + aliases { + i2c0 = &i2c0; + i2c1 = &i2c6; + serial2 = &uart7; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@20000000 { + reg = <0x20000000 0x8000000>; + }; + + clocks { + slow_xtal { + clock-frequency = <32768>; + }; + + main_xtal { + clock-frequency = <24000000>; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_key_gpio_default>; + + button-user { + label = "PB_USER"; + gpios = <&pioA 29 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_leds>; + + led-red { + label = "red"; + gpios = <&pioD 17 GPIO_ACTIVE_HIGH>; + }; + + led-green { + label = "green"; + gpios = <&pioD 19 GPIO_ACTIVE_HIGH>; + }; + + led-blue { + label = "blue"; + gpios = <&pioD 21 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + + vdd_1v8: regulator-0 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "VDD_1V8"; + }; + + vdd_1v15: regulator-1 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <1150000>; + regulator-min-microvolt = <1150000>; + regulator-name = "VDD_1V15"; + }; + + vdd1_3v3: regulator-2 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VDD1_3V3"; + }; +}; + +&adc { + vddana-supply = <&vdd1_3v3>; + vref-supply = <&vdd1_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc_default &pinctrl_adtrg_default>; + status = "okay"; +}; + +&can0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can0_rx_tx>; + status = "disabled"; /* Conflict with dbgu. */ +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1_rx_tx>; + status = "okay"; +}; + +&dbgu { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dbgu>; + status = "okay"; /* Conflict with can0. */ +}; + +&ebi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ebi_addr_nand &pinctrl_ebi_data_lsb>; + status = "okay"; + + nand_controller: nand-controller { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand_oe_we &pinctrl_nand_cs &pinctrl_nand_rb>; + status = "okay"; + + nand@3 { + reg = <0x3 0x0 0x800000>; + rb-gpios = <&pioD 5 GPIO_ACTIVE_HIGH>; + cs-gpios = <&pioD 4 GPIO_ACTIVE_HIGH>; + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + nand-on-flash-bbt; + label = "atmel_nand"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + at91bootstrap@0 { + label = "at91bootstrap"; + reg = <0x0 0x40000>; + }; + + uboot@40000 { + label = "u-boot"; + reg = <0x40000 0xc0000>; + }; + + ubootenvred@100000 { + label = "U-Boot Env Redundant"; + reg = <0x100000 0x40000>; + }; + + ubootenv@140000 { + label = "U-Boot Env"; + reg = <0x140000 0x40000>; + }; + + dtb@180000 { + label = "device tree"; + reg = <0x180000 0x80000>; + }; + + kernel@200000 { + label = "kernel"; + reg = <0x200000 0x600000>; + }; + + rootfs@800000 { + label = "rootfs"; + reg = <0x800000 0x1f800000>; + }; + }; + }; + }; +}; + +&flx0 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c0: i2c@600 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx0_default>; + #address-cells = <1>; + #size-cells = <0>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "okay"; + + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; + }; +}; + +&flx6 { + atmel,flexcom-mode = ; + status = "okay"; + + i2c6: i2c@600 { + dmas = <0>, <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx6_default>; + i2c-analog-filter; + i2c-digital-filter; + i2c-digital-filter-width-ns = <35>; + status = "disabled"; + }; +}; + +&flx7 { + atmel,flexcom-mode = ; + status = "okay"; + + uart7: serial@200 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flx7_default>; + status = "okay"; + }; +}; + +&macb0 { + phy-mode = "rmii"; + #address-cells = <1>; + #size-cells = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_macb0_rmii>; + status = "okay"; + + ethernet-phy@0 { + reg = <0x0>; + }; +}; + +&pinctrl { + adc { + pinctrl_adc_default: adc-default { + atmel,pins = ; + }; + + pinctrl_adtrg_default: adtrg-default { + atmel,pins = ; + }; + }; + + can0 { + pinctrl_can0_rx_tx: can0-rx-tx { + atmel,pins = + ; /* Enable CAN Transceivers */ + }; + }; + + can1 { + pinctrl_can1_rx_tx: can1-rx-tx { + atmel,pins = + ; /* Enable CAN Transceivers */ + }; + }; + + dbgu { + pinctrl_dbgu: dbgu-0 { + atmel,pins = ; + }; + }; + + ebi { + pinctrl_ebi_data_lsb: ebi-data-lsb { + atmel,pins = + ; + }; + + pinctrl_ebi_addr_nand: ebi-addr-nand { + atmel,pins = + ; + }; + }; + + flexcom { + pinctrl_flx0_default: flx0-twi { + atmel,pins = + ; + }; + + pinctrl_flx6_default: flx6-twi { + atmel,pins = + ; + }; + + pinctrl_flx7_default: flx7-usart { + atmel,pins = + ; + }; + }; + + gpio-keys { + pinctrl_key_gpio_default: pinctrl-key-gpio { + atmel,pins = ; + }; + }; + + leds { + pinctrl_gpio_leds: gpio-leds { + atmel,pins = ; + }; + }; + + macb0 { + pinctrl_macb0_rmii: macb0-rmii-0 { + atmel,pins = + ; /* PB10 periph A */ + }; + }; + + nand { + pinctrl_nand_oe_we: nand-oe-we-0 { + atmel,pins = + ; + }; + + pinctrl_nand_rb: nand-rb-0 { + atmel,pins = + ; + }; + + pinctrl_nand_cs: nand-cs-0 { + atmel,pins = + ; + }; + }; + + pwm0 { + pinctrl_pwm0_0: pwm0-0 { + atmel,pins = ; + }; + + pinctrl_pwm0_1: pwm0-1 { + atmel,pins = ; + }; + + pinctrl_pwm0_2: pwm0-2 { + atmel,pins = ; + }; + }; + + sdmmc0 { + pinctrl_sdmmc0_default: sdmmc0 { + atmel,pins = + ; /* PA20 DAT3 periph A with pullup */ + }; + + pinctrl_sdmmc0_cd: sdmmc0-cd { + atmel,pins = + ; + }; + }; + + sdmmc1 { + pinctrl_sdmmc1_default: sdmmc1 { + atmel,pins = + ; /* PA4 DAT3 periph B with pullup */ + }; + }; + + usb0 { + pinctrl_usba_vbus: usba-vbus { + atmel,pins = ; + }; + }; + + usb1 { + pinctrl_usb_default: usb-default { + atmel,pins = ; + }; + }; +}; /* pinctrl */ + +&pwm0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm0_0 &pinctrl_pwm0_1 &pinctrl_pwm0_2>; + status = "okay"; +}; + +&sdmmc0 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc0_default &pinctrl_sdmmc0_cd>; + cd-gpios = <&pioA 25 GPIO_ACTIVE_LOW>; + disable-wp; + status = "okay"; +}; + +&sdmmc1 { + bus-width = <4>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sdmmc1_default>; + disable-wp; + status = "okay"; +}; + +&shutdown_controller { + debounce-delay-us = <976>; + status = "okay"; + + input@0 { + reg = <0>; + }; +}; + +&tcb0 { + timer0: timer@0 { + compatible = "atmel,tcb-timer"; + reg = <0>; + }; + + timer1: timer@1 { + compatible = "atmel,tcb-timer"; + reg = <1>; + }; +}; + +&usb0 { + atmel,vbus-gpio = <&pioA 27 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usba_vbus>; + status = "okay"; +}; + +&usb1 { + num-ports = <3>; + atmel,vbus-gpio = <0 + &pioD 18 GPIO_ACTIVE_HIGH + &pioD 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_default>; + status = "okay"; +}; + +&usb2 { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts index d929c1ba57899a66732937ced3a94a3a348521cc..180e4b1aa2f6d3fe5043d27f8c0bf2d0092feed5 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -16,8 +16,8 @@ aliases { i2c0 = &i2c0; - i2c1 = &i2c1; - serial1 = &uart1; + i2c1 = &i2c6; + serial1 = &uart5; }; chosen { @@ -207,15 +207,11 @@ status = "okay"; i2c0: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; #address-cells = <1>; #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + dmas = <0>, <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx0_default>; - atmel,fifo-size = <16>; i2c-analog-filter; i2c-digital-filter; i2c-digital-filter-width-ns = <35>; @@ -234,17 +230,10 @@ atmel,flexcom-mode = ; status = "disabled"; - spi0: spi@400 { - compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; - reg = <0x400 0x200>; - interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; - clock-names = "spi_clk"; + spi4: spi@400 { + dmas = <0>, <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx4_default>; - atmel,fifo-size = <16>; - #address-cells = <1>; - #size-cells = <0>; status = "disabled"; }; }; @@ -253,24 +242,9 @@ atmel,flexcom-mode = ; status = "okay"; - uart1: serial@200 { - compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; - reg = <0x200 0x200>; - atmel,usart-mode = ; - interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; - dmas = <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(10))>, - <&dma0 - (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | - AT91_XDMAC_DT_PERID(11))>; - dma-names = "tx", "rx"; - clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; - clock-names = "usart"; - pinctrl-0 = <&pinctrl_flx5_default>; + uart5: serial@200 { pinctrl-names = "default"; - atmel,use-dma-rx; - atmel,use-dma-tx; + pinctrl-0 = <&pinctrl_flx5_default>; status = "okay"; }; }; @@ -279,16 +253,12 @@ atmel,flexcom-mode = ; status = "okay"; - i2c1: i2c@600 { - compatible = "microchip,sam9x60-i2c"; - reg = <0x600 0x200>; - interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; + i2c6: i2c@600 { #address-cells = <1>; #size-cells = <0>; - clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + dmas = <0>, <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flx6_default>; - atmel,fifo-size = <16>; i2c-analog-filter; i2c-digital-filter; i2c-digital-filter-width-ns = <35>; @@ -439,7 +409,7 @@ AT91_PIOA 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; }; - pinctrl_flx5_default: flx_uart { + pinctrl_flx5_default: flx5_uart { atmel,pins = ; status = "okay"; /* Conflict with pwm0. */ - red { + led-red { label = "red"; gpios = <&pioA PIN_PA10 GPIO_ACTIVE_HIGH>; }; - green { + led-green { label = "green"; gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>; }; - blue { + led-blue { label = "blue"; gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts index b665ddc6b0de9e08a3d59303f07a4a460cfadfc8..e055b9e2fe34463b2dd7a7f80abdbe2ce14acb4f 100644 --- a/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d27_wlsom1_ek.dts @@ -46,17 +46,17 @@ pinctrl-0 = <&pinctrl_led_gpio_default>; status = "okay"; - red { + led-red { label = "red"; gpios = <&pioA PIN_PA6 GPIO_ACTIVE_HIGH>; }; - green { + led-green { label = "green"; gpios = <&pioA PIN_PA7 GPIO_ACTIVE_HIGH>; }; - blue { + led-blue { label = "blue"; gpios = <&pioA PIN_PA8 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/at91-sama5d2_icp.dts b/arch/arm/boot/dts/at91-sama5d2_icp.dts index dd1dec9d4e07f293a86f2b4a12e2d67c9e28dcfe..1346b8f2b2597fd2f909f94009090e823d199594 100644 --- a/arch/arm/boot/dts/at91-sama5d2_icp.dts +++ b/arch/arm/boot/dts/at91-sama5d2_icp.dts @@ -62,17 +62,17 @@ pinctrl-0 = <&pinctrl_led_gpio_default>; status = "okay"; /* conflict with pwm0 */ - red { + led-red { label = "red"; gpios = <&pioA PIN_PB0 GPIO_ACTIVE_HIGH>; }; - green { + led-green { label = "green"; gpios = <&pioA PIN_PB1 GPIO_ACTIVE_HIGH>; }; - blue { + led-blue { label = "blue"; gpios = <&pioA PIN_PA31 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts index 76a711b167b0b5a92a10f626bc21df66acd8b7f5..bf1c9ca72a9f35a6e313670e6140a9e84dc4f0ae 100644 --- a/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts +++ b/arch/arm/boot/dts/at91-sama5d2_ptc_ek.dts @@ -416,17 +416,17 @@ pinctrl-0 = <&pinctrl_led_gpio_default>; status = "okay"; - red { + led-red { label = "red"; gpios = <&pioA PIN_PB10 GPIO_ACTIVE_HIGH>; }; - green { + led-green { label = "green"; gpios = <&pioA PIN_PB8 GPIO_ACTIVE_HIGH>; }; - blue { + led-blue { label = "blue"; gpios = <&pioA PIN_PB6 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/at91-sama5d2_xplained.dts b/arch/arm/boot/dts/at91-sama5d2_xplained.dts index 85949c24b6879a4e0c655221f8ad6726c214f336..2d53c47d7cc863a87338c22770e5d195465879d3 100644 --- a/arch/arm/boot/dts/at91-sama5d2_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d2_xplained.dts @@ -725,18 +725,18 @@ pinctrl-0 = <&pinctrl_led_gpio_default>; status = "okay"; /* conflict with pwm0 */ - red { + led-red { label = "red"; gpios = <&pioA PIN_PB6 GPIO_ACTIVE_LOW>; }; - green { + led-green { label = "green"; gpios = <&pioA PIN_PB5 GPIO_ACTIVE_LOW>; }; - blue { + led-blue { label = "blue"; gpios = <&pioA PIN_PB0 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/at91-sama5d3_xplained.dts b/arch/arm/boot/dts/at91-sama5d3_xplained.dts index 1f42a6a981bfed6ebbc9d5b20517c2476da5ca34..82003372708822130bdb73e415e5fafdbf3a9d78 100644 --- a/arch/arm/boot/dts/at91-sama5d3_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d3_xplained.dts @@ -392,13 +392,13 @@ pinctrl-0 = <&pinctrl_gpio_leds>; status = "okay"; - d2 { + led-d2 { label = "d2"; gpios = <&pioE 23 GPIO_ACTIVE_LOW>; /* PE23, conflicts with A23, CTS2 */ linux,default-trigger = "heartbeat"; }; - d3 { + led-d3 { label = "d3"; /* Conflict with EBI CS0, USART2 CTS. */ gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts index 4d7cee569ff2cfbeebfbb215b72441083d670979..8adf567f2f0fe1d3bc59fffa5d5cdb10ba2fe21b 100644 --- a/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts +++ b/arch/arm/boot/dts/at91-sama5d4_ma5d4evk.dts @@ -115,19 +115,19 @@ compatible = "gpio-leds"; status = "okay"; - user1 { + led-user1 { label = "user1"; gpios = <&pioD 28 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - user2 { + led-user2 { label = "user2"; gpios = <&pioD 29 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - user3 { + led-user3 { label = "user3"; gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/at91-sama5d4_xplained.dts b/arch/arm/boot/dts/at91-sama5d4_xplained.dts index f122f302f8e02892c495075036aba284a1a0b905..95d701d13fef665de48055e9ff8b300aee7c67b7 100644 --- a/arch/arm/boot/dts/at91-sama5d4_xplained.dts +++ b/arch/arm/boot/dts/at91-sama5d4_xplained.dts @@ -262,13 +262,13 @@ pinctrl-0 = <&pinctrl_gpio_leds>; status = "okay"; - d8 { + led-d8 { label = "d8"; gpios = <&pioD 30 GPIO_ACTIVE_HIGH>; default-state = "on"; }; - d10 { + led-d10 { label = "d10"; gpios = <&pioE 15 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/at91-sama5d4ek.dts b/arch/arm/boot/dts/at91-sama5d4ek.dts index fce4e93c6bee808bb52055d8b1b02225f0a8016d..20ac775059ca42d5a7ae66ad36dbb1be2055f768 100644 --- a/arch/arm/boot/dts/at91-sama5d4ek.dts +++ b/arch/arm/boot/dts/at91-sama5d4ek.dts @@ -287,18 +287,18 @@ compatible = "gpio-leds"; status = "okay"; - d8 { + led-d8 { label = "d8"; /* PE28, conflicts with usart4 rts pin */ gpios = <&pioE 28 GPIO_ACTIVE_LOW>; }; - d9 { + led-d9 { label = "d9"; gpios = <&pioE 9 GPIO_ACTIVE_HIGH>; }; - d10 { + led-d10 { label = "d10"; gpios = <&pioE 8 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/at91-tse850-3.dts b/arch/arm/boot/dts/at91-tse850-3.dts index 7e5c598e7e68f8457f930ae50d00be7e6485e6aa..b99a4fb44a364cd3f691bda2e62d8c026fa4e989 100644 --- a/arch/arm/boot/dts/at91-tse850-3.dts +++ b/arch/arm/boot/dts/at91-tse850-3.dts @@ -106,35 +106,35 @@ leds { compatible = "gpio-leds"; - ch1-red { + led-ch1-red { label = "ch-1:red"; gpios = <&pioA 23 GPIO_ACTIVE_LOW>; }; - ch1-green { + led-ch1-green { label = "ch-1:green"; gpios = <&pioA 22 GPIO_ACTIVE_LOW>; }; - ch2-red { + led-ch2-red { label = "ch-2:red"; gpios = <&pioA 21 GPIO_ACTIVE_LOW>; }; - ch2-green { + led-ch2-green { label = "ch-2:green"; gpios = <&pioA 20 GPIO_ACTIVE_LOW>; }; - data-red { + led-data-red { label = "data:red"; gpios = <&pioA 19 GPIO_ACTIVE_LOW>; }; - data-green { + led-data-green { label = "data:green"; gpios = <&pioA 18 GPIO_ACTIVE_LOW>; }; - alarm-red { + led-alarm-red { label = "alarm:red"; gpios = <&pioA 17 GPIO_ACTIVE_LOW>; }; - alarm-green { + led-alarm-green { label = "alarm:green"; gpios = <&pioA 16 GPIO_ACTIVE_LOW>; }; diff --git a/arch/arm/boot/dts/axm55xx.dtsi b/arch/arm/boot/dts/axm55xx.dtsi index 7676a65059a48e84b9dd43b65be764603429cb2b..5277890cfad2edd9d9793b7c7855725d522a9a20 100644 --- a/arch/arm/boot/dts/axm55xx.dtsi +++ b/arch/arm/boot/dts/axm55xx.dtsi @@ -108,7 +108,7 @@ #size-cells = <2>; ranges; - serial0: uart@2010080000 { + serial0: serial@2010080000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x20 0x10080000 0 0x1000>; interrupts = ; @@ -117,7 +117,7 @@ status = "disabled"; }; - serial1: uart@2010081000 { + serial1: serial@2010081000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x20 0x10081000 0 0x1000>; interrupts = ; @@ -126,7 +126,7 @@ status = "disabled"; }; - serial2: uart@2010082000 { + serial2: serial@2010082000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x20 0x10082000 0 0x1000>; interrupts = ; @@ -135,7 +135,7 @@ status = "disabled"; }; - serial3: uart@2010083000 { + serial3: serial@2010083000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x20 0x10083000 0 0x1000>; interrupts = ; diff --git a/arch/arm/boot/dts/bcm11351.dtsi b/arch/arm/boot/dts/bcm11351.dtsi index 53696078bbf0592148c6242ef8c0466aa9add832..ba75784d66a9726259b4949ddca243de5e9234a4 100644 --- a/arch/arm/boot/dts/bcm11351.dtsi +++ b/arch/arm/boot/dts/bcm11351.dtsi @@ -50,7 +50,7 @@ reg = <0x3404c000 0x400>; /* 1 KiB in SRAM */ }; - uart@3e000000 { + serial@3e000000 { compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; status = "disabled"; reg = <0x3e000000 0x1000>; @@ -60,7 +60,7 @@ reg-io-width = <4>; }; - uart@3e001000 { + serial@3e001000 { compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; status = "disabled"; reg = <0x3e001000 0x1000>; @@ -70,7 +70,7 @@ reg-io-width = <4>; }; - uart@3e002000 { + serial@3e002000 { compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; status = "disabled"; reg = <0x3e002000 0x1000>; @@ -80,7 +80,7 @@ reg-io-width = <4>; }; - uart@3e003000 { + serial@3e003000 { compatible = "brcm,bcm11351-dw-apb-uart", "snps,dw-apb-uart"; status = "disabled"; reg = <0x3e003000 0x1000>; diff --git a/arch/arm/boot/dts/bcm21664-garnet.dts b/arch/arm/boot/dts/bcm21664-garnet.dts index 1854cd907a1b14c587c97d20c5bdc1507f5c69e3..cd03fa0c2aae446f94c81471b958243570f98a3c 100644 --- a/arch/arm/boot/dts/bcm21664-garnet.dts +++ b/arch/arm/boot/dts/bcm21664-garnet.dts @@ -16,7 +16,7 @@ reg = <0x80000000 0x40000000>; /* 1 GB */ }; - uart@3e000000 { + serial@3e000000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/bcm21664.dtsi b/arch/arm/boot/dts/bcm21664.dtsi index 2684c37cb3a06f3b2a56926cfedbf5623359d724..ed4de031e48eef0f9ad4522cc667ce4f119a7052 100644 --- a/arch/arm/boot/dts/bcm21664.dtsi +++ b/arch/arm/boot/dts/bcm21664.dtsi @@ -50,7 +50,7 @@ reg = <0x3404e000 0x400>; /* 1 KiB in SRAM */ }; - uart@3e000000 { + serial@3e000000 { compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; status = "disabled"; reg = <0x3e000000 0x118>; @@ -60,7 +60,7 @@ reg-io-width = <4>; }; - uart@3e001000 { + serial@3e001000 { compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; status = "disabled"; reg = <0x3e001000 0x118>; @@ -70,7 +70,7 @@ reg-io-width = <4>; }; - uart@3e002000 { + serial@3e002000 { compatible = "brcm,bcm21664-dw-apb-uart", "snps,dw-apb-uart"; status = "disabled"; reg = <0x3e002000 0x118>; diff --git a/arch/arm/boot/dts/bcm28155-ap.dts b/arch/arm/boot/dts/bcm28155-ap.dts index fce3d5260b001e08f08dac281f7830db9c329d79..60c8ab8a28557063a565a1a4fc8325a298254064 100644 --- a/arch/arm/boot/dts/bcm28155-ap.dts +++ b/arch/arm/boot/dts/bcm28155-ap.dts @@ -16,7 +16,7 @@ reg = <0x80000000 0x40000000>; /* 1 GB */ }; - uart@3e000000 { + serial@3e000000 { status = "okay"; }; diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 598a46f96a8216692f05b40416ac9155602680e9..6edaefa617a58060dfc993da23b5b28cb4b34f66 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -581,7 +581,7 @@ status = "disabled"; }; - uart0: uart@9000 { + uart0: serial@9000 { compatible = "snps,dw-apb-uart"; reg = <0x9000 0x100>; interrupts = <8>; @@ -592,7 +592,7 @@ status = "disabled"; }; - uart1: uart@a000 { + uart1: serial@a000 { compatible = "snps,dw-apb-uart"; reg = <0xa000 0x100>; interrupts = <9>; diff --git a/arch/arm/boot/dts/cx92755.dtsi b/arch/arm/boot/dts/cx92755.dtsi index d2e8f36f8c60e1e191b12954ea006ea3a699ec67..227675fbe820829b125675dae42021fee148ffb4 100644 --- a/arch/arm/boot/dts/cx92755.dtsi +++ b/arch/arm/boot/dts/cx92755.dtsi @@ -107,7 +107,7 @@ reg = <0xf00003a0 0x10>; }; - uart0: uart@f0000740 { + uart0: serial@f0000740 { compatible = "cnxt,cx92755-usart"; reg = <0xf0000740 0x20>; clocks = <&main_clk>; @@ -115,7 +115,7 @@ status = "disabled"; }; - uart1: uart@f0000760 { + uart1: serial@f0000760 { compatible = "cnxt,cx92755-usart"; reg = <0xf0000760 0x20>; clocks = <&main_clk>; @@ -123,7 +123,7 @@ status = "disabled"; }; - uart2: uart@f0000780 { + uart2: serial@f0000780 { compatible = "cnxt,cx92755-usart"; reg = <0xf0000780 0x20>; clocks = <&main_clk>; diff --git a/arch/arm/boot/dts/dm814x.dtsi b/arch/arm/boot/dts/dm814x.dtsi index 8104969c67c10470168c920651679438943e8f3b..a8cd724ce4bc4eaf6208221238c4f2e85ece596d 100644 --- a/arch/arm/boot/dts/dm814x.dtsi +++ b/arch/arm/boot/dts/dm814x.dtsi @@ -333,7 +333,7 @@ }; }; - uart1: uart@20000 { + uart1: serial@20000 { compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart1"; reg = <0x20000 0x2000>; @@ -343,7 +343,7 @@ dma-names = "tx", "rx"; }; - uart2: uart@22000 { + uart2: serial@22000 { compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart2"; reg = <0x22000 0x2000>; @@ -353,7 +353,7 @@ dma-names = "tx", "rx"; }; - uart3: uart@24000 { + uart3: serial@24000 { compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart3"; reg = <0x24000 0x2000>; diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi index 649b33194455a4f625f7cc7456efe40482fa9657..b68686f0643b05d4ff0dce18f59aa35bacaec220 100644 --- a/arch/arm/boot/dts/dm816x.dtsi +++ b/arch/arm/boot/dts/dm816x.dtsi @@ -522,7 +522,7 @@ ti,timer-pwm; }; - uart1: uart@48020000 { + uart1: serial@48020000 { compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart1"; reg = <0x48020000 0x2000>; @@ -532,7 +532,7 @@ dma-names = "tx", "rx"; }; - uart2: uart@48022000 { + uart2: serial@48022000 { compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart2"; reg = <0x48022000 0x2000>; @@ -542,7 +542,7 @@ dma-names = "tx", "rx"; }; - uart3: uart@48024000 { + uart3: serial@48024000 { compatible = "ti,am3352-uart", "ti,omap3-uart"; ti,hwmods = "uart3"; reg = <0x48024000 0x2000>; diff --git a/arch/arm/boot/dts/dove-cm-a510.dtsi b/arch/arm/boot/dts/dove-cm-a510.dtsi index 9b9dfbe07be4c86c708163d8d09ee01d97cd2b1a..1082fdfbfe60d7406756cede1d32ecb89fc4eba9 100644 --- a/arch/arm/boot/dts/dove-cm-a510.dtsi +++ b/arch/arm/boot/dts/dove-cm-a510.dtsi @@ -101,7 +101,7 @@ pinctrl-0 = <&pmx_nand_gpo>; pinctrl-names = "default"; - system { + led-system { label = "cm-a510:system:green"; gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; default-state = "keep"; @@ -124,9 +124,17 @@ }; /* Optional RTL8211D GbE PHY on SMI address 0x03 */ -ðphy { - reg = <3>; - status = "disabled"; +&mdio { + ethphy: ethernet-phy@3 { + reg = <3>; + status = "disabled"; + }; +}; + +ð { + ethernet-port@0 { + phy-handle = <ðphy>; + }; }; &i2c0 { diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts index 2639b9fe0ab48532b17b0abd481d5cf0ea9b4870..dbba0c8cdab1a4740441bb3648798bd7d84e2f5a 100644 --- a/arch/arm/boot/dts/dove-cubox.dts +++ b/arch/arm/boot/dts/dove-cubox.dts @@ -21,7 +21,7 @@ pinctrl-0 = <&pmx_gpio_18>; pinctrl-names = "default"; - power { + led-power { label = "Power"; gpios = <&gpio0 18 1>; default-state = "keep"; @@ -72,11 +72,18 @@ &uart0 { status = "okay"; }; &sata0 { status = "okay"; }; &mdio { status = "okay"; }; -ð { status = "okay"; }; +ð { + status = "okay"; + ethernet-port@0 { + phy-handle = <ðphy>; + }; +}; -ðphy { - compatible = "marvell,88e1310"; - reg = <1>; +&mdio { + ethphy: ethernet-phy@1 { + compatible = "marvell,88e1310"; + reg = <1>; + }; }; &gpu { diff --git a/arch/arm/boot/dts/dove-d2plug.dts b/arch/arm/boot/dts/dove-d2plug.dts index a0e8996c2ffde7cb509992b4693bd342cbc2cc5a..79ee2b32409d57c60e01ce7c0747232eaa263136 100644 --- a/arch/arm/boot/dts/dove-d2plug.dts +++ b/arch/arm/boot/dts/dove-d2plug.dts @@ -21,17 +21,17 @@ pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>; pinctrl-names = "default"; - wlan-ap { + led-wlan-ap { label = "wlan-ap"; gpios = <&gpio0 0 1>; }; - wlan-act { + led-wlan-act { label = "wlan-act"; gpios = <&gpio0 1 1>; }; - bluetooth-act { + led-bluetooth-act { label = "bt-act"; gpios = <&gpio0 2 1>; }; diff --git a/arch/arm/boot/dts/dove-d3plug.dts b/arch/arm/boot/dts/dove-d3plug.dts index 1e81d1b970550b67a66cf25a24477dee1b556467..5aa5d4a7d51d766b92ef2b45270c21cd696ceb3d 100644 --- a/arch/arm/boot/dts/dove-d3plug.dts +++ b/arch/arm/boot/dts/dove-d3plug.dts @@ -21,17 +21,17 @@ pinctrl-0 = <&pmx_gpio_0 &pmx_gpio_1 &pmx_gpio_2>; pinctrl-names = "default"; - wlan-act { + led-wlan-act { label = "wlan-act"; gpios = <&gpio0 0 1>; }; - wlan-ap { + led-wlan-ap { label = "wlan-ap"; gpios = <&gpio0 1 1>; }; - status { + led-status { label = "status"; gpios = <&gpio0 2 1>; }; diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi index 9aee3cfd3e981b1af332425535babf1c472aea8a..85408d4c6f2ed2e494d0fc38a901467815ae0b16 100644 --- a/arch/arm/boot/dts/dove.dtsi +++ b/arch/arm/boot/dts/dove.dtsi @@ -382,7 +382,6 @@ interrupts = <29>; /* overwrite MAC address in bootloader */ local-mac-address = [00 00 00 00 00 00]; - phy-handle = <ðphy>; }; }; @@ -394,10 +393,6 @@ interrupts = <30>; clocks = <&gate_clk 2>; status = "disabled"; - - ethphy: ethernet-phy { - /* set phy address in board file */ - }; }; sdio0: sdio-host@92000 { diff --git a/arch/arm/boot/dts/e70k02.dtsi b/arch/arm/boot/dts/e70k02.dtsi index 27ef9a62b23cf4c9dd09fbc13130078e0a0e2001..ace3eb8a97b87c4002be0db5e21cb294d9aeccb1 100644 --- a/arch/arm/boot/dts/e70k02.dtsi +++ b/arch/arm/boot/dts/e70k02.dtsi @@ -122,7 +122,16 @@ clock-frequency = <100000>; status = "okay"; - /* TODO: CYTTSP5 touch controller at 0x24 */ + touchscreen@24 { + compatible = "cypress,tt21000"; + reg = <0x24>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_cyttsp5_gpio>; + interrupt-parent = <&gpio4>; + interrupts = <24 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 18 GPIO_ACTIVE_LOW>; + vdd-supply = <&ldo5_reg>; + }; /* TODO: SY7636 PMIC for E Ink at 0x62 */ diff --git a/arch/arm/boot/dts/exynos-syscon-restart.dtsi b/arch/arm/boot/dts/exynos-syscon-restart.dtsi index ecf416690a15290f0d08be5b4c1cdca49868ab8d..bc9a78f6d4b726d992540a0d326aeff880c14481 100644 --- a/arch/arm/boot/dts/exynos-syscon-restart.dtsi +++ b/arch/arm/boot/dts/exynos-syscon-restart.dtsi @@ -7,7 +7,7 @@ poweroff: syscon-poweroff { compatible = "syscon-poweroff"; regmap = <&pmu_system_controller>; - offset = <0x330C>; /* PS_HOLD_CONTROL */ + offset = <0x330c>; /* PS_HOLD_CONTROL */ mask = <0x5200>; /* reset value */ }; diff --git a/arch/arm/boot/dts/exynos3250-monk.dts b/arch/arm/boot/dts/exynos3250-monk.dts index 02a9dc479d34cb1e193805cebfa0c60aaf87360d..80d90fe7fad1b136c7d8dbd44d19731b63681164 100644 --- a/arch/arm/boot/dts/exynos3250-monk.dts +++ b/arch/arm/boot/dts/exynos3250-monk.dts @@ -31,7 +31,7 @@ firmware@205f000 { compatible = "samsung,secure-firmware"; - reg = <0x0205F000 0x1000>; + reg = <0x0205f000 0x1000>; }; gpio-keys { @@ -438,7 +438,6 @@ broken-cd; non-removable; cap-mmc-highspeed; - desc-num = <4>; mmc-hs200-1_8v; card-detect-delay = <200>; vmmc-supply = <&vemmc_reg>; diff --git a/arch/arm/boot/dts/exynos3250-rinato.dts b/arch/arm/boot/dts/exynos3250-rinato.dts index 6d2c7bb191842a6a92a2d06076b3f49a289c13a3..1f9cba0607e137c5332118c85d31787ee8726737 100644 --- a/arch/arm/boot/dts/exynos3250-rinato.dts +++ b/arch/arm/boot/dts/exynos3250-rinato.dts @@ -36,7 +36,7 @@ firmware@205f000 { compatible = "samsung,secure-firmware"; - reg = <0x0205F000 0x1000>; + reg = <0x0205f000 0x1000>; }; gpio-keys { @@ -250,7 +250,7 @@ i80-if-timings { cs-setup = <0>; wr-setup = <0>; - wr-act = <1>; + wr-active = <1>; wr-hold = <0>; }; }; @@ -619,7 +619,6 @@ broken-cd; non-removable; cap-mmc-highspeed; - desc-num = <4>; mmc-hs200-1_8v; card-detect-delay = <200>; vmmc-supply = <&ldo12_reg>; diff --git a/arch/arm/boot/dts/exynos3250.dtsi b/arch/arm/boot/dts/exynos3250.dtsi index a2d6ee7fff08d7f3d29bac62ce389e792f25ee35..28bb2ce8ccf7e3204f4f7821b787ffaa7c9948c5 100644 --- a/arch/arm/boot/dts/exynos3250.dtsi +++ b/arch/arm/boot/dts/exynos3250.dtsi @@ -46,6 +46,157 @@ serial2 = &serial_2; }; + bus_dmc: bus-dmc { + compatible = "samsung,exynos-bus"; + clocks = <&cmu_dmc CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + + bus_dmc_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <800000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <800000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <800000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <825000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <875000>; + }; + }; + }; + + bus_fsys: bus-fsys { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_isp: bus-isp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_266>; + clock-names = "bus"; + operating-points-v2 = <&bus_isp_opp_table>; + status = "disabled"; + + bus_isp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + }; + }; + }; + + bus_lcd0: bus-lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_160>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus: bus-leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mcuisp: bus-mcuisp { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; + clock-names = "bus"; + operating-points-v2 = <&bus_mcuisp_opp_table>; + status = "disabled"; + + bus_mcuisp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + }; + }; + }; + + bus_mfc: bus-mfc { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_peril: bus-peril { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_ACLK_100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peril_opp_table>; + status = "disabled"; + + bus_peril_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + }; + + bus_rightbus: bus-rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&cmu CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -129,6 +280,31 @@ clock-output-names = "xtcxo"; }; + bus_leftbus_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + opp-microvolt = <900000>; + }; + opp-80000000 { + opp-hz = /bits/ 64 <80000000>; + opp-microvolt = <900000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <1000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + }; + }; + pmu { compatible = "arm,cortex-a7-pmu"; interrupts = , @@ -188,35 +364,35 @@ pd_cam: power-domain@10023c00 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023C00 0x20>; + reg = <0x10023c00 0x20>; #power-domain-cells = <0>; label = "CAM"; }; pd_mfc: power-domain@10023c40 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023C40 0x20>; + reg = <0x10023c40 0x20>; #power-domain-cells = <0>; label = "MFC"; }; pd_g3d: power-domain@10023c60 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023C60 0x20>; + reg = <0x10023c60 0x20>; #power-domain-cells = <0>; label = "G3D"; }; pd_lcd0: power-domain@10023c80 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023C80 0x20>; + reg = <0x10023c80 0x20>; #power-domain-cells = <0>; label = "LCD0"; }; pd_isp: power-domain@10023ca0 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023CA0 0x20>; + reg = <0x10023ca0 0x20>; #power-domain-cells = <0>; label = "ISP"; }; @@ -233,7 +409,7 @@ cmu_dmc: clock-controller@105c0000 { compatible = "samsung,exynos3250-cmu-dmc"; - reg = <0x105C0000 0x2000>; + reg = <0x105c0000 0x2000>; #clock-cells = <1>; }; @@ -248,7 +424,7 @@ tmu: tmu@100c0000 { compatible = "samsung,exynos3250-tmu"; - reg = <0x100C0000 0x100>; + reg = <0x100c0000 0x100>; interrupts = ; clocks = <&cmu CLK_TMU_APBIF>; clock-names = "tmu_apbif"; @@ -342,7 +518,7 @@ dsi_0: dsi@11c80000 { compatible = "samsung,exynos3250-mipi-dsi"; - reg = <0x11C80000 0x10000>; + reg = <0x11c80000 0x10000>; interrupts = ; samsung,phy-type = <0>; power-domains = <&pd_lcd0>; @@ -365,7 +541,7 @@ #iommu-cells = <0>; }; - hsotg: hsotg@12480000 { + hsotg: usb@12480000 { compatible = "samsung,s3c6400-hsotg"; reg = <0x12480000 0x20000>; interrupts = ; @@ -412,9 +588,9 @@ status = "disabled"; }; - exynos_usbphy: exynos-usbphy@125b0000 { + exynos_usbphy: usb-phy@125b0000 { compatible = "samsung,exynos3250-usb2-phy"; - reg = <0x125B0000 0x100>; + reg = <0x125b0000 0x100>; samsung,pmureg-phandle = <&pmu_system_controller>; clocks = <&cmu CLK_USBOTG>, <&cmu CLK_SCLK_UPLL>; clock-names = "phy", "ref"; @@ -442,7 +618,7 @@ adc: adc@126c0000 { compatible = "samsung,exynos3250-adc"; - reg = <0x126C0000 0x100>; + reg = <0x126c0000 0x100>; interrupts = ; clock-names = "adc", "sclk"; clocks = <&cmu CLK_TSADC>, <&cmu CLK_SCLK_TSADC>; @@ -593,7 +769,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; - reg = <0x138A0000 0x100>; + reg = <0x138a0000 0x100>; interrupts = ; clocks = <&cmu CLK_I2C4>; clock-names = "i2c"; @@ -606,7 +782,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; - reg = <0x138B0000 0x100>; + reg = <0x138b0000 0x100>; interrupts = ; clocks = <&cmu CLK_I2C5>; clock-names = "i2c"; @@ -619,7 +795,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; - reg = <0x138C0000 0x100>; + reg = <0x138c0000 0x100>; interrupts = ; clocks = <&cmu CLK_I2C6>; clock-names = "i2c"; @@ -632,7 +808,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; - reg = <0x138D0000 0x100>; + reg = <0x138d0000 0x100>; interrupts = ; clocks = <&cmu CLK_I2C7>; clock-names = "i2c"; @@ -688,7 +864,7 @@ pwm: pwm@139d0000 { compatible = "samsung,exynos4210-pwm"; - reg = <0x139D0000 0x1000>; + reg = <0x139d0000 0x1000>; interrupts = , , , @@ -771,182 +947,6 @@ clock-names = "ppmu"; status = "disabled"; }; - - bus_dmc: bus-dmc { - compatible = "samsung,exynos-bus"; - clocks = <&cmu_dmc CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; - - bus_dmc_opp_table: opp-table1 { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - opp-microvolt = <800000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <800000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <800000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <825000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <875000>; - }; - }; - - bus_leftbus: bus-leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_rightbus: bus-rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_lcd0: bus-lcd0 { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_160>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_fsys: bus-fsys { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_200>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_mcuisp: bus-mcuisp { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_400_MCUISP>; - clock-names = "bus"; - operating-points-v2 = <&bus_mcuisp_opp_table>; - status = "disabled"; - }; - - bus_isp: bus-isp { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_266>; - clock-names = "bus"; - operating-points-v2 = <&bus_isp_opp_table>; - status = "disabled"; - }; - - bus_peril: bus-peril { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_DIV_ACLK_100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peril_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus-mfc { - compatible = "samsung,exynos-bus"; - clocks = <&cmu CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_leftbus_opp_table: opp-table2 { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - opp-microvolt = <900000>; - }; - opp-80000000 { - opp-hz = /bits/ 64 <80000000>; - opp-microvolt = <900000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <1000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <1000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <1000000>; - }; - }; - - bus_mcuisp_opp_table: opp-table3 { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-80000000 { - opp-hz = /bits/ 64 <80000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - }; - }; - - bus_isp_opp_table: opp-table4 { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-80000000 { - opp-hz = /bits/ 64 <80000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - opp-300000000 { - opp-hz = /bits/ 64 <300000000>; - }; - }; - - bus_peril_opp_table: opp-table5 { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-80000000 { - opp-hz = /bits/ 64 <80000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; }; }; diff --git a/arch/arm/boot/dts/exynos4.dtsi b/arch/arm/boot/dts/exynos4.dtsi index 5c4ecda27a476a0e0d713d3f40bdbf5ee3603d37..44dcb1377475a2f168d81801e19d99a3bd40b7ad 100644 --- a/arch/arm/boot/dts/exynos4.dtsi +++ b/arch/arm/boot/dts/exynos4.dtsi @@ -65,7 +65,7 @@ clock_audss: clock-controller@3810000 { compatible = "samsung,exynos4210-audss-clock"; - reg = <0x03810000 0x0C>; + reg = <0x03810000 0x0c>; #clock-cells = <1>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, <&clock CLK_SCLK_AUDIO0>, @@ -113,28 +113,28 @@ pd_mfc: power-domain@10023c40 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023C40 0x20>; + reg = <0x10023c40 0x20>; #power-domain-cells = <0>; label = "MFC"; }; pd_g3d: power-domain@10023c60 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023C60 0x20>; + reg = <0x10023c60 0x20>; #power-domain-cells = <0>; label = "G3D"; }; pd_lcd0: power-domain@10023c80 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023C80 0x20>; + reg = <0x10023c80 0x20>; #power-domain-cells = <0>; label = "LCD0"; }; pd_tv: power-domain@10023c20 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023C20 0x20>; + reg = <0x10023c20 0x20>; #power-domain-cells = <0>; power-domains = <&pd_lcd0>; label = "TV"; @@ -142,21 +142,21 @@ pd_cam: power-domain@10023c00 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023C00 0x20>; + reg = <0x10023c00 0x20>; #power-domain-cells = <0>; label = "CAM"; }; pd_gps: power-domain@10023ce0 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023CE0 0x20>; + reg = <0x10023ce0 0x20>; #power-domain-cells = <0>; label = "GPS"; }; pd_gps_alive: power-domain@10023d00 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023D00 0x20>; + reg = <0x10023d00 0x20>; #power-domain-cells = <0>; label = "GPS alive"; }; @@ -190,7 +190,7 @@ dsi_0: dsi@11c80000 { compatible = "samsung,exynos4210-mipi-dsi"; - reg = <0x11C80000 0x10000>; + reg = <0x11c80000 0x10000>; interrupts = ; power-domains = <&pd_lcd0>; phys = <&mipi_phy 1>; @@ -309,7 +309,7 @@ keypad: keypad@100a0000 { compatible = "samsung,s5pv210-keypad"; - reg = <0x100A0000 0x100>; + reg = <0x100a0000 0x100>; interrupts = ; clocks = <&clock CLK_KEYIF>; clock-names = "keypad"; @@ -352,9 +352,9 @@ status = "disabled"; }; - exynos_usbphy: exynos-usbphy@125b0000 { + exynos_usbphy: usb-phy@125b0000 { compatible = "samsung,exynos4210-usb2-phy"; - reg = <0x125B0000 0x100>; + reg = <0x125b0000 0x100>; samsung,pmureg-phandle = <&pmu_system_controller>; clocks = <&clock CLK_USB_DEVICE>, <&clock CLK_XUSBXTI>; clock-names = "phy", "ref"; @@ -362,7 +362,7 @@ status = "disabled"; }; - hsotg: hsotg@12480000 { + hsotg: usb@12480000 { compatible = "samsung,s3c6400-hsotg"; reg = <0x12480000 0x20000>; interrupts = ; @@ -546,7 +546,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; - reg = <0x138A0000 0x100>; + reg = <0x138a0000 0x100>; interrupts = ; clocks = <&clock CLK_I2C4>; clock-names = "i2c"; @@ -559,7 +559,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; - reg = <0x138B0000 0x100>; + reg = <0x138b0000 0x100>; interrupts = ; clocks = <&clock CLK_I2C5>; clock-names = "i2c"; @@ -572,7 +572,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; - reg = <0x138C0000 0x100>; + reg = <0x138c0000 0x100>; interrupts = ; clocks = <&clock CLK_I2C6>; clock-names = "i2c"; @@ -585,7 +585,7 @@ #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-i2c"; - reg = <0x138D0000 0x100>; + reg = <0x138d0000 0x100>; interrupts = ; clocks = <&clock CLK_I2C7>; clock-names = "i2c"; @@ -598,14 +598,14 @@ #address-cells = <1>; #size-cells = <0>; compatible = "samsung,s3c2440-hdmiphy-i2c"; - reg = <0x138E0000 0x100>; + reg = <0x138e0000 0x100>; interrupts = ; clocks = <&clock CLK_I2C_HDMI>; clock-names = "i2c"; status = "disabled"; - hdmi_i2c_phy: hdmiphy@38 { - compatible = "exynos4210-hdmiphy"; + hdmi_i2c_phy: hdmi-phy@38 { + compatible = "samsung,exynos4210-hdmiphy"; reg = <0x38>; }; }; @@ -657,7 +657,7 @@ pwm: pwm@139d0000 { compatible = "samsung,exynos4210-pwm"; - reg = <0x139D0000 0x1000>; + reg = <0x139d0000 0x1000>; interrupts = , , , @@ -712,7 +712,7 @@ tmu: tmu@100c0000 { interrupt-parent = <&combiner>; - reg = <0x100C0000 0x100>; + reg = <0x100c0000 0x100>; interrupts = <2 4>; status = "disabled"; #thermal-sensor-cells = <0>; @@ -739,7 +739,7 @@ hdmi: hdmi@12d00000 { compatible = "samsung,exynos4210-hdmi"; - reg = <0x12D00000 0x70000>; + reg = <0x12d00000 0x70000>; interrupts = ; clock-names = "hdmi", "sclk_hdmi", "sclk_pixel", "sclk_hdmiphy", "mout_hdmi"; @@ -756,7 +756,7 @@ hdmicec: cec@100b0000 { compatible = "samsung,s5p-cec"; - reg = <0x100B0000 0x200>; + reg = <0x100b0000 0x200>; interrupts = ; clocks = <&clock CLK_HDMI_CEC>; clock-names = "hdmicec"; @@ -770,7 +770,7 @@ mixer: mixer@12c10000 { compatible = "samsung,exynos4210-mixer"; interrupts = ; - reg = <0x12C10000 0x2100>, <0x12c00000 0x300>; + reg = <0x12c10000 0x2100>, <0x12c00000 0x300>; power-domains = <&pd_tv>; iommus = <&sysmmu_tv>; status = "disabled"; @@ -902,7 +902,7 @@ sysmmu_tv: sysmmu@12e20000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x12E20000 0x1000>; + reg = <0x12e20000 0x1000>; interrupt-parent = <&combiner>; interrupts = <5 4>; clock-names = "sysmmu", "master"; @@ -913,7 +913,7 @@ sysmmu_fimc0: sysmmu@11a20000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11A20000 0x1000>; + reg = <0x11a20000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 2>; clock-names = "sysmmu", "master"; @@ -924,7 +924,7 @@ sysmmu_fimc1: sysmmu@11a30000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11A30000 0x1000>; + reg = <0x11a30000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 3>; clock-names = "sysmmu", "master"; @@ -935,7 +935,7 @@ sysmmu_fimc2: sysmmu@11a40000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11A40000 0x1000>; + reg = <0x11a40000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 4>; clock-names = "sysmmu", "master"; @@ -946,7 +946,7 @@ sysmmu_fimc3: sysmmu@11a50000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11A50000 0x1000>; + reg = <0x11a50000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 5>; clock-names = "sysmmu", "master"; @@ -957,7 +957,7 @@ sysmmu_jpeg: sysmmu@11a60000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11A60000 0x1000>; + reg = <0x11a60000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 6>; clock-names = "sysmmu", "master"; @@ -968,7 +968,7 @@ sysmmu_rotator: sysmmu@12a30000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x12A30000 0x1000>; + reg = <0x12a30000 0x1000>; interrupt-parent = <&combiner>; interrupts = <5 0>; clock-names = "sysmmu", "master"; @@ -979,7 +979,7 @@ sysmmu_fimd0: sysmmu@11e20000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11E20000 0x1000>; + reg = <0x11e20000 0x1000>; interrupt-parent = <&combiner>; interrupts = <5 2>; clock-names = "sysmmu", "master"; diff --git a/arch/arm/boot/dts/exynos4210-origen.dts b/arch/arm/boot/dts/exynos4210-origen.dts index 5f37b751f70052d67dbb8fdafd66fa751d11fc08..1103e7f92b570ceb0df2c33d70a685d965e91374 100644 --- a/arch/arm/boot/dts/exynos4210-origen.dts +++ b/arch/arm/boot/dts/exynos4210-origen.dts @@ -85,7 +85,7 @@ leds { compatible = "gpio-leds"; - status { + led-status { gpios = <&gpx1 3 GPIO_ACTIVE_LOW>; function = LED_FUNCTION_HEARTBEAT; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/exynos4210-smdkv310.dts b/arch/arm/boot/dts/exynos4210-smdkv310.dts index a5dfd7fd49b3980d08fc5ca1fd77b0f4da383d85..181c99eca6751d070c158b9552cbae57469b633f 100644 --- a/arch/arm/boot/dts/exynos4210-smdkv310.dts +++ b/arch/arm/boot/dts/exynos4210-smdkv310.dts @@ -203,7 +203,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "w25x80"; + compatible = "winbond,w25x80", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <1000000>; diff --git a/arch/arm/boot/dts/exynos4210.dtsi b/arch/arm/boot/dts/exynos4210.dtsi index 2c25cc37934e89e7da257a4f31104c3cd83a74f3..5a1ec714c612e96c3bd344b3f6a86544bcbf7301 100644 --- a/arch/arm/boot/dts/exynos4210.dtsi +++ b/arch/arm/boot/dts/exynos4210.dtsi @@ -28,6 +28,151 @@ pinctrl2 = &pinctrl_2; }; + bus_acp: bus-acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_ACP>; + clock-names = "bus"; + operating-points-v2 = <&bus_acp_opp_table>; + status = "disabled"; + + bus_acp_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + }; + + bus_display: bus-display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + status = "disabled"; + + bus_display_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + }; + }; + + bus_dmc: bus-dmc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + + bus_dmc_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <1025000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <1050000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1150000>; + opp-suspend; + }; + }; + }; + + bus_fsys: bus-fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + + bus_fsys_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-10000000 { + opp-hz = /bits/ 64 <10000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + }; + }; + + bus_lcd0: bus-lcd0 { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK200>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_leftbus: bus-leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_mfc: bus-mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_peri: bus-peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + + bus_peri_opp_table: opp-table { + compatible = "operating-points-v2"; + opp-shared; + + opp-5000000 { + opp-hz = /bits/ 64 <5000000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + }; + + bus_rightbus: bus-rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -82,6 +227,22 @@ }; }; + bus_leftbus_opp_table: opp-table-0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-suspend; + }; + }; + soc: soc { sysram: sram@2020000 { compatible = "mmio-sram"; @@ -103,7 +264,7 @@ pd_lcd1: power-domain@10023ca0 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023CA0 0x20>; + reg = <0x10023ca0 0x20>; #power-domain-cells = <0>; label = "LCD1"; }; @@ -195,7 +356,7 @@ sysmmu_g2d: sysmmu@12a20000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x12A20000 0x1000>; + reg = <0x12a20000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 7>; clock-names = "sysmmu", "master"; @@ -214,167 +375,6 @@ power-domains = <&pd_lcd1>; #iommu-cells = <0>; }; - - bus_dmc: bus-dmc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; - - bus_acp: bus-acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_ACP>; - clock-names = "bus"; - operating-points-v2 = <&bus_acp_opp_table>; - status = "disabled"; - }; - - bus_peri: bus-peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peri_opp_table>; - status = "disabled"; - }; - - bus_fsys: bus-fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK133>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_opp_table>; - status = "disabled"; - }; - - bus_display: bus-display { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK160>; - clock-names = "bus"; - operating-points-v2 = <&bus_display_opp_table>; - status = "disabled"; - }; - - bus_lcd0: bus-lcd0 { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK200>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_leftbus: bus-leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_rightbus: bus-rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus-mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_dmc_opp_table: opp-table1 { - compatible = "operating-points-v2"; - opp-shared; - - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <1025000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <1050000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1150000>; - opp-suspend; - }; - }; - - bus_acp_opp_table: opp-table2 { - compatible = "operating-points-v2"; - opp-shared; - - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - }; - - bus_peri_opp_table: opp-table3 { - compatible = "operating-points-v2"; - opp-shared; - - opp-5000000 { - opp-hz = /bits/ 64 <5000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; - - bus_fsys_opp_table: opp-table4 { - compatible = "operating-points-v2"; - opp-shared; - - opp-10000000 { - opp-hz = /bits/ 64 <10000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - }; - - bus_display_opp_table: opp-table5 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - }; - - bus_leftbus_opp_table: opp-table6 { - compatible = "operating-points-v2"; - opp-shared; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-suspend; - }; - }; }; }; diff --git a/arch/arm/boot/dts/exynos4412-itop-elite.dts b/arch/arm/boot/dts/exynos4412-itop-elite.dts index 202ab0fee3b70bb573c7ce4eac3b161be9fed4c4..b596e997e451a1b191acb7ddd6b9b28e815fa908 100644 --- a/arch/arm/boot/dts/exynos4412-itop-elite.dts +++ b/arch/arm/boot/dts/exynos4412-itop-elite.dts @@ -214,7 +214,7 @@ bus-width = <4>; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_bus4>; pinctrl-names = "default"; - cd-gpio = <&gpx0 7 GPIO_ACTIVE_LOW>; + cd-gpios = <&gpx0 7 GPIO_ACTIVE_LOW>; cap-sd-highspeed; vmmc-supply = <&ldo23_reg>; vqmmc-supply = <&ldo17_reg>; diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi index a67cb61e3cbb3c52747df37a775d458b6d1b5654..e42e39dc0e40617bc997479cc0a1bb1045521c2f 100644 --- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi +++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi @@ -25,7 +25,7 @@ firmware@203f000 { compatible = "samsung,secure-firmware"; - reg = <0x0203F000 0x1000>; + reg = <0x0203f000 0x1000>; }; fixed-rate-clocks { diff --git a/arch/arm/boot/dts/exynos4412-midas.dtsi b/arch/arm/boot/dts/exynos4412-midas.dtsi index 8e1c19a8ad06da8d072ee9f1d25fabc7a174b323..525f945c4b911a18a583b3f28dac2b30509b220b 100644 --- a/arch/arm/boot/dts/exynos4412-midas.dtsi +++ b/arch/arm/boot/dts/exynos4412-midas.dtsi @@ -33,7 +33,7 @@ firmware@204f000 { compatible = "samsung,secure-firmware"; - reg = <0x0204F000 0x1000>; + reg = <0x0204f000 0x1000>; }; fixed-rate-clocks { @@ -273,9 +273,16 @@ interrupts = <5 IRQ_TYPE_LEVEL_HIGH>; reg = <0x39>; - port { - mhl_to_hdmi: endpoint { - remote-endpoint = <&hdmi_to_mhl>; + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mhl_to_hdmi: endpoint { + remote-endpoint = <&hdmi_to_mhl>; + }; }; }; }; @@ -646,8 +653,8 @@ CPVDD-supply = <&vbatt_reg>; SPKVDD1-supply = <&vbatt_reg>; SPKVDD2-supply = <&vbatt_reg>; - wlf,ldo1ena = <&gpj0 4 0>; - wlf,ldo2ena = <&gpj0 4 0>; + wlf,ldo1ena-gpios = <&gpj0 4 GPIO_ACTIVE_HIGH>; + wlf,ldo2ena-gpios = <&gpj0 4 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi index e7669b9e9edbe02548151f8c97bee5f11ec26f94..7c2780d3e37ce9ea66ffdacafe7dfa46fa76e0ce 100644 --- a/arch/arm/boot/dts/exynos4412-odroid-common.dtsi +++ b/arch/arm/boot/dts/exynos4412-odroid-common.dtsi @@ -19,7 +19,7 @@ firmware@204f000 { compatible = "samsung,secure-firmware"; - reg = <0x0204F000 0x1000>; + reg = <0x0204f000 0x1000>; }; gpio_keys: gpio-keys { diff --git a/arch/arm/boot/dts/exynos4412-odroidu3.dts b/arch/arm/boot/dts/exynos4412-odroidu3.dts index a5ad88b897ffc0cd6e1a30215bb17042228bda1f..42812da1f882356d340f2c9822854ce64ff8b77d 100644 --- a/arch/arm/boot/dts/exynos4412-odroidu3.dts +++ b/arch/arm/boot/dts/exynos4412-odroidu3.dts @@ -23,7 +23,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x7FF00000>; + reg = <0x40000000 0x7ff00000>; }; vbus_otg_reg: regulator-1 { diff --git a/arch/arm/boot/dts/exynos4412-odroidx.dts b/arch/arm/boot/dts/exynos4412-odroidx.dts index 68d589e081bc6b363cb0d31c053b8e6104113ceb..d5316cf2fbb6140bf9cd588d6ba12f56947eb9f8 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx.dts @@ -22,7 +22,7 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x3FF00000>; + reg = <0x40000000 0x3ff00000>; }; leds { diff --git a/arch/arm/boot/dts/exynos4412-odroidx2.dts b/arch/arm/boot/dts/exynos4412-odroidx2.dts index f4b68c75c962707649e3b44359e75513df8cad64..7be4cbdc4413fbd47b135b05a209639d62d3cd37 100644 --- a/arch/arm/boot/dts/exynos4412-odroidx2.dts +++ b/arch/arm/boot/dts/exynos4412-odroidx2.dts @@ -17,6 +17,6 @@ memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x7FF00000>; + reg = <0x40000000 0x7ff00000>; }; }; diff --git a/arch/arm/boot/dts/exynos4412-origen.dts b/arch/arm/boot/dts/exynos4412-origen.dts index a3905e27b9cd9e2728138a3d79aa5aee6d7eeab2..ea9fd284386d9c149c53a3bb62fd7e25b45d942c 100644 --- a/arch/arm/boot/dts/exynos4412-origen.dts +++ b/arch/arm/boot/dts/exynos4412-origen.dts @@ -31,7 +31,7 @@ firmware@203f000 { compatible = "samsung,secure-firmware"; - reg = <0x0203F000 0x1000>; + reg = <0x0203f000 0x1000>; }; mmc_reg: regulator-0 { diff --git a/arch/arm/boot/dts/exynos4412-p4note.dtsi b/arch/arm/boot/dts/exynos4412-p4note.dtsi index 7a515b87bc7c5d8b2b1c38e3bf8552979eb48e35..3e05a49f29ff6f1512f6e2bab0e1d4a50632963e 100644 --- a/arch/arm/boot/dts/exynos4412-p4note.dtsi +++ b/arch/arm/boot/dts/exynos4412-p4note.dtsi @@ -32,7 +32,7 @@ firmware@204f000 { compatible = "samsung,secure-firmware"; - reg = <0x0204F000 0x1000>; + reg = <0x0204f000 0x1000>; }; fixed-rate-clocks { @@ -132,8 +132,6 @@ precharge-current-microamp = <250000>; charge-term-current-microamp = <250000>; constant-charge-voltage-max-microvolt = <4200000>; - - power-supplies = <&power_supply>; }; i2c-gpio-1 { @@ -200,7 +198,7 @@ stmpe_adc { compatible = "st,stmpe-adc"; #io-channel-cells = <1>; - st,norequest-mask = <0x2F>; + st,norequest-mask = <0x2f>; }; }; }; @@ -247,6 +245,7 @@ pinctrl-0 = <&led_bl_reset>; pinctrl-names = "default"; enable-gpios = <&gpm0 1 GPIO_ACTIVE_HIGH>; + power-supply = <&panel_vdd>; pwms = <&pwm 1 78770 0>; brightness-levels = <0 48 128 255>; num-interpolated-steps = <8>; diff --git a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi index 58847d4fa846b281eb44ecbc433d9132d52b8e15..8ab31c3daa4815cf411fb8a9117e08f44d5108b7 100644 --- a/arch/arm/boot/dts/exynos4412-pinctrl.dtsi +++ b/arch/arm/boot/dts/exynos4412-pinctrl.dtsi @@ -12,7 +12,7 @@ #include "exynos-pinctrl.h" #define PIN_SLP(_pin, _mode, _pull) \ - _pin { \ + pin- ## _pin { \ samsung,pins = #_pin; \ samsung,pin-con-pdn = ; \ samsung,pin-pud-pdn = ; \ diff --git a/arch/arm/boot/dts/exynos4412-tiny4412.dts b/arch/arm/boot/dts/exynos4412-tiny4412.dts index 04388c575efe9925c64735b827554c90e2f3808b..e0b6162d2e2ae8ef30bea046fe3bee933efc1fa6 100644 --- a/arch/arm/boot/dts/exynos4412-tiny4412.dts +++ b/arch/arm/boot/dts/exynos4412-tiny4412.dts @@ -79,6 +79,7 @@ panel { compatible = "innolux,at070tn92"; + power-supply = <&vddq_lcd>; port { panel_input: endpoint { @@ -86,6 +87,13 @@ }; }; }; + + vddq_lcd: regulator-vddq-lcd { + compatible = "regulator-fixed"; + regulator-name = "vddq-lcd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; }; &cpu_thermal { diff --git a/arch/arm/boot/dts/exynos4412.dtsi b/arch/arm/boot/dts/exynos4412.dtsi index aa0b61b599705aeae345015b09f64059f9e9eff8..11f9dd94b6b33fcf9da9b5c2c6bf2b4f821d1fb5 100644 --- a/arch/arm/boot/dts/exynos4412.dtsi +++ b/arch/arm/boot/dts/exynos4412.dtsi @@ -31,6 +31,134 @@ mshc0 = &mshc_0; }; + bus_acp: bus-acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_ACP>; + clock-names = "bus"; + operating-points-v2 = <&bus_acp_opp_table>; + status = "disabled"; + + bus_acp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + }; + }; + }; + + bus_c2c: bus-c2c { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_C2C>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + status = "disabled"; + }; + + bus_dmc: bus-dmc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_DMC>; + clock-names = "bus"; + operating-points-v2 = <&bus_dmc_opp_table>; + samsung,data-clock-ratio = <4>; + #interconnect-cells = <0>; + status = "disabled"; + }; + + bus_display: bus-display { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK160>; + clock-names = "bus"; + operating-points-v2 = <&bus_display_opp_table>; + interconnects = <&bus_leftbus &bus_dmc>; + #interconnect-cells = <0>; + status = "disabled"; + + bus_display_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + }; + }; + }; + + bus_fsys: bus-fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK133>; + clock-names = "bus"; + operating-points-v2 = <&bus_fsys_opp_table>; + status = "disabled"; + + bus_fsys_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + }; + }; + }; + + bus_leftbus: bus-leftbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDL>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + interconnects = <&bus_dmc>; + #interconnect-cells = <0>; + status = "disabled"; + }; + + bus_mfc: bus-mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_SCLK_MFC>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + + bus_peri: bus-peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_ACLK100>; + clock-names = "bus"; + operating-points-v2 = <&bus_peri_opp_table>; + status = "disabled"; + + bus_peri_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + }; + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + }; + }; + }; + + bus_rightbus: bus-rightbus { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DIV_GDR>; + clock-names = "bus"; + operating-points-v2 = <&bus_leftbus_opp_table>; + status = "disabled"; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -55,7 +183,7 @@ cpu0: cpu@a00 { device_type = "cpu"; compatible = "arm,cortex-a9"; - reg = <0xA00>; + reg = <0xa00>; clocks = <&clock CLK_ARM_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; @@ -65,7 +193,7 @@ cpu1: cpu@a01 { device_type = "cpu"; compatible = "arm,cortex-a9"; - reg = <0xA01>; + reg = <0xa01>; clocks = <&clock CLK_ARM_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; @@ -75,7 +203,7 @@ cpu2: cpu@a02 { device_type = "cpu"; compatible = "arm,cortex-a9"; - reg = <0xA02>; + reg = <0xa02>; clocks = <&clock CLK_ARM_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; @@ -85,7 +213,7 @@ cpu3: cpu@a03 { device_type = "cpu"; compatible = "arm,cortex-a9"; - reg = <0xA03>; + reg = <0xa03>; clocks = <&clock CLK_ARM_CLK>; clock-names = "cpu"; operating-points-v2 = <&cpu0_opp_table>; @@ -93,7 +221,7 @@ }; }; - cpu0_opp_table: opp-table0 { + cpu0_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -171,6 +299,53 @@ }; }; + bus_dmc_opp_table: opp-table-1 { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <900000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <900000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <900000>; + }; + opp-267000000 { + opp-hz = /bits/ 64 <267000000>; + opp-microvolt = <950000>; + }; + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <1050000>; + opp-suspend; + }; + }; + + bus_leftbus_opp_table: opp-table-2 { + compatible = "operating-points-v2"; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + opp-microvolt = <900000>; + }; + opp-134000000 { + opp-hz = /bits/ 64 <134000000>; + opp-microvolt = <925000>; + }; + opp-160000000 { + opp-hz = /bits/ 64 <160000000>; + opp-microvolt = <950000>; + }; + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <1000000>; + opp-suspend; + }; + }; soc: soc { @@ -201,7 +376,7 @@ pinctrl_3: pinctrl@106e0000 { compatible = "samsung,exynos4x12-pinctrl"; - reg = <0x106E0000 0x1000>; + reg = <0x106e0000 0x1000>; interrupts = ; }; @@ -225,7 +400,7 @@ pd_isp: power-domain@10023ca0 { compatible = "samsung,exynos4210-pd"; - reg = <0x10023CA0 0x20>; + reg = <0x10023ca0 0x20>; #power-domain-cells = <0>; label = "ISP"; }; @@ -285,7 +460,7 @@ adc: adc@126c0000 { compatible = "samsung,exynos4212-adc"; - reg = <0x126C0000 0x100>; + reg = <0x126c0000 0x100>; interrupt-parent = <&combiner>; interrupts = <10 3>; clocks = <&clock CLK_TSADC>; @@ -318,7 +493,7 @@ sysmmu_g2d: sysmmu@10a40000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x10A40000 0x1000>; + reg = <0x10a40000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 7>; clock-names = "sysmmu", "master"; @@ -350,7 +525,7 @@ sysmmu_fimc_fd: sysmmu@122a0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x122A0000 0x1000>; + reg = <0x122a0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <16 4>; power-domains = <&pd_isp>; @@ -361,7 +536,7 @@ sysmmu_fimc_mcuctl: sysmmu@122b0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x122B0000 0x1000>; + reg = <0x122b0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <16 5>; power-domains = <&pd_isp>; @@ -372,7 +547,7 @@ sysmmu_fimc_lite0: sysmmu@123b0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x123B0000 0x1000>; + reg = <0x123b0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <16 0>; power-domains = <&pd_isp>; @@ -384,7 +559,7 @@ sysmmu_fimc_lite1: sysmmu@123c0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x123C0000 0x1000>; + reg = <0x123c0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <16 1>; power-domains = <&pd_isp>; @@ -393,182 +568,6 @@ <&isp_clock CLK_ISP_FIMC_LITE1>; #iommu-cells = <0>; }; - - bus_dmc: bus-dmc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_DMC>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - samsung,data-clock-ratio = <4>; - #interconnect-cells = <0>; - status = "disabled"; - }; - - bus_acp: bus-acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_ACP>; - clock-names = "bus"; - operating-points-v2 = <&bus_acp_opp_table>; - status = "disabled"; - }; - - bus_c2c: bus-c2c { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_C2C>; - clock-names = "bus"; - operating-points-v2 = <&bus_dmc_opp_table>; - status = "disabled"; - }; - - bus_dmc_opp_table: opp-table1 { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <900000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <900000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <900000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - opp-microvolt = <950000>; - }; - opp-400000000 { - opp-hz = /bits/ 64 <400000000>; - opp-microvolt = <1050000>; - opp-suspend; - }; - }; - - bus_acp_opp_table: opp-table2 { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-267000000 { - opp-hz = /bits/ 64 <267000000>; - }; - }; - - bus_leftbus: bus-leftbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDL>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - interconnects = <&bus_dmc>; - #interconnect-cells = <0>; - status = "disabled"; - }; - - bus_rightbus: bus-rightbus { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DIV_GDR>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_display: bus-display { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK160>; - clock-names = "bus"; - operating-points-v2 = <&bus_display_opp_table>; - interconnects = <&bus_leftbus &bus_dmc>; - #interconnect-cells = <0>; - status = "disabled"; - }; - - bus_fsys: bus-fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK133>; - clock-names = "bus"; - operating-points-v2 = <&bus_fsys_opp_table>; - status = "disabled"; - }; - - bus_peri: bus-peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_ACLK100>; - clock-names = "bus"; - operating-points-v2 = <&bus_peri_opp_table>; - status = "disabled"; - }; - - bus_mfc: bus-mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_SCLK_MFC>; - clock-names = "bus"; - operating-points-v2 = <&bus_leftbus_opp_table>; - status = "disabled"; - }; - - bus_leftbus_opp_table: opp-table3 { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - opp-microvolt = <900000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - opp-microvolt = <925000>; - }; - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - opp-microvolt = <950000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - opp-microvolt = <1000000>; - opp-suspend; - }; - }; - - bus_display_opp_table: opp-table4 { - compatible = "operating-points-v2"; - - opp-160000000 { - opp-hz = /bits/ 64 <160000000>; - }; - opp-200000000 { - opp-hz = /bits/ 64 <200000000>; - }; - }; - - bus_fsys_opp_table: opp-table5 { - compatible = "operating-points-v2"; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - opp-134000000 { - opp-hz = /bits/ 64 <134000000>; - }; - }; - - bus_peri_opp_table: opp-table6 { - compatible = "operating-points-v2"; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - }; - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - }; - }; }; }; @@ -615,7 +614,7 @@ fimc_lite_1: fimc-lite@123a0000 { compatible = "samsung,exynos4212-fimc-lite"; - reg = <0x123A0000 0x1000>; + reg = <0x123a0000 0x1000>; interrupts = ; power-domains = <&pd_isp>; clocks = <&isp_clock CLK_ISP_FIMC_LITE1>; @@ -812,7 +811,7 @@ compatible = "samsung,exynos4412-tmu"; interrupt-parent = <&combiner>; interrupts = <2 4>; - reg = <0x100C0000 0x100>; + reg = <0x100c0000 0x100>; clocks = <&clock CLK_TMU_APBIF>; clock-names = "tmu_apbif"; status = "disabled"; diff --git a/arch/arm/boot/dts/exynos5.dtsi b/arch/arm/boot/dts/exynos5.dtsi index c8da0d4b1b3332bd2f7a43e6bc425c1e0d999463..48e43b6b3213a245310d15d2372a81a6a7501a7b 100644 --- a/arch/arm/boot/dts/exynos5.dtsi +++ b/arch/arm/boot/dts/exynos5.dtsi @@ -104,31 +104,31 @@ serial_0: serial@12c00000 { compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; + reg = <0x12c00000 0x100>; interrupts = ; }; serial_1: serial@12c10000 { compatible = "samsung,exynos4210-uart"; - reg = <0x12C10000 0x100>; + reg = <0x12c10000 0x100>; interrupts = ; }; serial_2: serial@12c20000 { compatible = "samsung,exynos4210-uart"; - reg = <0x12C20000 0x100>; + reg = <0x12c20000 0x100>; interrupts = ; }; serial_3: serial@12c30000 { compatible = "samsung,exynos4210-uart"; - reg = <0x12C30000 0x100>; + reg = <0x12c30000 0x100>; interrupts = ; }; i2c_0: i2c@12c60000 { compatible = "samsung,s3c2440-i2c"; - reg = <0x12C60000 0x100>; + reg = <0x12c60000 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -138,7 +138,7 @@ i2c_1: i2c@12c70000 { compatible = "samsung,s3c2440-i2c"; - reg = <0x12C70000 0x100>; + reg = <0x12c70000 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -148,7 +148,7 @@ i2c_2: i2c@12c80000 { compatible = "samsung,s3c2440-i2c"; - reg = <0x12C80000 0x100>; + reg = <0x12c80000 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -158,7 +158,7 @@ i2c_3: i2c@12c90000 { compatible = "samsung,s3c2440-i2c"; - reg = <0x12C90000 0x100>; + reg = <0x12c90000 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -168,7 +168,7 @@ pwm: pwm@12dd0000 { compatible = "samsung,exynos4210-pwm"; - reg = <0x12DD0000 0x100>; + reg = <0x12dd0000 0x100>; interrupts = , , , @@ -180,7 +180,7 @@ rtc: rtc@101e0000 { compatible = "samsung,s3c6410-rtc"; - reg = <0x101E0000 0x100>; + reg = <0x101e0000 0x100>; interrupts = , ; status = "disabled"; @@ -198,7 +198,7 @@ dp: dp-controller@145b0000 { compatible = "samsung,exynos5-dp"; - reg = <0x145B0000 0x1000>; + reg = <0x145b0000 0x1000>; interrupts = <10 3>; interrupt-parent = <&combiner>; status = "disabled"; diff --git a/arch/arm/boot/dts/exynos5250-arndale.dts b/arch/arm/boot/dts/exynos5250-arndale.dts index 71c0e87d3a1d5983a8c6bd9c6e896b38550fdcb8..2e3da5670bc2c906c1ed2a3cc544a8563e655e01 100644 --- a/arch/arm/boot/dts/exynos5250-arndale.dts +++ b/arch/arm/boot/dts/exynos5250-arndale.dts @@ -73,6 +73,19 @@ }; }; + /* + * For unknown reasons HDMI-DDC does not work with Exynos I2C + * controllers. Lets use software I2C over GPIO pins as a workaround. + */ + i2c_ddc: i2c-10 { + compatible = "i2c-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_gpio_bus>; + sda-gpios = <&gpa0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&gpa0 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + }; + panel: panel { compatible = "boe,hv070wsa-100"; power-supply = <&vcc_3v3_reg>; @@ -524,8 +537,8 @@ SPKVDD1-supply = <&main_dc_reg>; SPKVDD2-supply = <&main_dc_reg>; - wlf,ldo1ena = <&gpb0 0 GPIO_ACTIVE_HIGH>; - wlf,ldo2ena = <&gpb0 1 GPIO_ACTIVE_HIGH>; + wlf,ldo1ena-gpios = <&gpb0 0 GPIO_ACTIVE_HIGH>; + wlf,ldo2ena-gpios = <&gpb0 1 GPIO_ACTIVE_HIGH>; }; }; @@ -615,24 +628,6 @@ status = "okay"; }; -&soc { - /* - * For unknown reasons HDMI-DDC does not work with Exynos I2C - * controllers. Lets use software I2C over GPIO pins as a workaround. - */ - i2c_ddc: i2c-10 { - pinctrl-names = "default"; - pinctrl-0 = <&i2c2_gpio_bus>; - status = "okay"; - compatible = "i2c-gpio"; - sda-gpios = <&gpa0 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - scl-gpios = <&gpa0 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; - i2c-gpio,delay-us = <2>; - #address-cells = <1>; - #size-cells = <0>; - }; -}; - &usbdrd { vdd10-supply = <&ldo15_reg>; vdd33-supply = <&ldo12_reg>; diff --git a/arch/arm/boot/dts/exynos5250-smdk5250.dts b/arch/arm/boot/dts/exynos5250-smdk5250.dts index 71293749ac481f30f304a5e9d98e437519eec31e..831b3494bd46567511dbe92cb187bdc691c856a4 100644 --- a/arch/arm/boot/dts/exynos5250-smdk5250.dts +++ b/arch/arm/boot/dts/exynos5250-smdk5250.dts @@ -391,7 +391,7 @@ flash@0 { #address-cells = <1>; #size-cells = <1>; - compatible = "w25x80"; + compatible = "winbond,w25x80", "jedec,spi-nor"; reg = <0>; spi-max-frequency = <1000000>; diff --git a/arch/arm/boot/dts/exynos5250-snow-rev5.dts b/arch/arm/boot/dts/exynos5250-snow-rev5.dts index 0a47597d6f0de6e33e12a09cb681d8e7b836decd..3d32c3476e84d96c9f087d7cfa8bd72f9ecddb21 100644 --- a/arch/arm/boot/dts/exynos5250-snow-rev5.dts +++ b/arch/arm/boot/dts/exynos5250-snow-rev5.dts @@ -27,7 +27,7 @@ }; codec { - sound-dai = <&max98090 0>, <&hdmi>; + sound-dai = <&max98090>, <&hdmi>; }; }; }; @@ -42,7 +42,7 @@ pinctrl-0 = <&max98090_irq>; clocks = <&pmu_system_controller 0>; clock-names = "mclk"; - #sound-dai-cells = <1>; + #sound-dai-cells = <0>; }; }; diff --git a/arch/arm/boot/dts/exynos5250.dtsi b/arch/arm/boot/dts/exynos5250.dtsi index 4708dcd575a7788074325772b53fc53601acd287..a5db4ac213d59c1b8fba78e0cbc0872e254eb23a 100644 --- a/arch/arm/boot/dts/exynos5250.dtsi +++ b/arch/arm/boot/dts/exynos5250.dtsi @@ -81,7 +81,7 @@ }; }; - cpu0_opp_table: opp-table0 { + cpu0_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -216,14 +216,14 @@ pd_disp1: power-domain@100440a0 { compatible = "samsung,exynos4210-pd"; - reg = <0x100440A0 0x20>; + reg = <0x100440a0 0x20>; #power-domain-cells = <0>; label = "DISP1"; }; pd_mau: power-domain@100440c0 { compatible = "samsung,exynos4210-pd"; - reg = <0x100440C0 0x20>; + reg = <0x100440c0 0x20>; #power-domain-cells = <0>; label = "MAU"; }; @@ -236,7 +236,7 @@ clock_audss: audss-clock-controller@3810000 { compatible = "samsung,exynos5250-audss-clock"; - reg = <0x03810000 0x0C>; + reg = <0x03810000 0x0c>; #clock-cells = <1>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>, <&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>; @@ -247,7 +247,7 @@ timer@101c0000 { compatible = "samsung,exynos5250-mct", "samsung,exynos4210-mct"; - reg = <0x101C0000 0x800>; + reg = <0x101c0000 0x800>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MCT>; clock-names = "fin_pll", "mct"; interrupts-extended = <&combiner 23 3>, @@ -302,7 +302,7 @@ watchdog@101d0000 { compatible = "samsung,exynos5250-wdt"; - reg = <0x101D0000 0x100>; + reg = <0x101d0000 0x100>; interrupts = ; clocks = <&clock CLK_WDT>; clock-names = "watchdog"; @@ -322,7 +322,7 @@ rotator: rotator@11c00000 { compatible = "samsung,exynos5250-rotator"; - reg = <0x11C00000 0x64>; + reg = <0x11c00000 0x64>; interrupts = ; clocks = <&clock CLK_ROTATOR>; clock-names = "rotator"; @@ -387,10 +387,10 @@ sata: sata@122f0000 { compatible = "snps,dwc-ahci"; - reg = <0x122F0000 0x1ff>; + reg = <0x122f0000 0x1ff>; interrupts = ; clocks = <&clock CLK_SATA>, <&clock CLK_SCLK_SATA>; - clock-names = "sata", "sclk_sata"; + clock-names = "sata", "pclk"; phys = <&sata_phy>; phy-names = "sata-phy"; ports-implemented = <0x1>; @@ -410,7 +410,7 @@ /* i2c_0-3 are defined in exynos5.dtsi */ i2c_4: i2c@12ca0000 { compatible = "samsung,s3c2440-i2c"; - reg = <0x12CA0000 0x100>; + reg = <0x12ca0000 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -423,7 +423,7 @@ i2c_5: i2c@12cb0000 { compatible = "samsung,s3c2440-i2c"; - reg = <0x12CB0000 0x100>; + reg = <0x12cb0000 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -436,7 +436,7 @@ i2c_6: i2c@12cc0000 { compatible = "samsung,s3c2440-i2c"; - reg = <0x12CC0000 0x100>; + reg = <0x12cc0000 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -449,7 +449,7 @@ i2c_7: i2c@12cd0000 { compatible = "samsung,s3c2440-i2c"; - reg = <0x12CD0000 0x100>; + reg = <0x12cd0000 0x100>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -462,7 +462,7 @@ i2c_8: i2c@12ce0000 { compatible = "samsung,s3c2440-hdmiphy-i2c"; - reg = <0x12CE0000 0x1000>; + reg = <0x12ce0000 0x1000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -470,7 +470,7 @@ clock-names = "i2c"; status = "disabled"; - hdmiphy: hdmiphy@38 { + hdmiphy: hdmi-phy@38 { compatible = "samsung,exynos4212-hdmiphy"; reg = <0x38>; }; @@ -478,7 +478,7 @@ i2c_9: i2c@121d0000 { compatible = "samsung,exynos5-sata-phy-i2c"; - reg = <0x121D0000 0x100>; + reg = <0x121d0000 0x100>; #address-cells = <1>; #size-cells = <0>; clocks = <&clock CLK_SATA_PHYI2C>; @@ -608,7 +608,7 @@ i2s1: i2s@12d60000 { compatible = "samsung,s3c6410-i2s"; status = "disabled"; - reg = <0x12D60000 0x100>; + reg = <0x12d60000 0x100>; dmas = <&pdma1 12>, <&pdma1 11>; dma-names = "tx", "rx"; @@ -623,7 +623,7 @@ i2s2: i2s@12d70000 { compatible = "samsung,s3c6410-i2s"; status = "disabled"; - reg = <0x12D70000 0x100>; + reg = <0x12d70000 0x100>; dmas = <&pdma0 12>, <&pdma0 11>; dma-names = "tx", "rx"; @@ -635,17 +635,17 @@ #sound-dai-cells = <1>; }; - usbdrd: usb3 { + usbdrd: usb@12000000 { compatible = "samsung,exynos5250-dwusb3"; clocks = <&clock CLK_USB3>; clock-names = "usbdrd30"; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0x0 0x12000000 0x10000>; - usbdrd_dwc3: usb@12000000 { + usbdrd_dwc3: usb@0 { compatible = "snps,dwc3"; - reg = <0x12000000 0x10000>; + reg = <0x0 0x10000>; interrupts = ; phys = <&usbdrd_phy 0>, <&usbdrd_phy 1>; phy-names = "usb2-phy", "usb3-phy"; @@ -695,7 +695,7 @@ pdma0: dma-controller@121a0000 { compatible = "arm,pl330", "arm,primecell"; - reg = <0x121A0000 0x1000>; + reg = <0x121a0000 0x1000>; interrupts = ; clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; @@ -704,7 +704,7 @@ pdma1: dma-controller@121b0000 { compatible = "arm,pl330", "arm,primecell"; - reg = <0x121B0000 0x1000>; + reg = <0x121b0000 0x1000>; interrupts = ; clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; @@ -722,7 +722,7 @@ mdma1: dma-controller@11c10000 { compatible = "arm,pl330", "arm,primecell"; - reg = <0x11C10000 0x1000>; + reg = <0x11c10000 0x1000>; interrupts = ; clocks = <&clock CLK_MDMA1>; clock-names = "apb_pclk"; @@ -787,7 +787,7 @@ hdmicec: cec@101b0000 { compatible = "samsung,s5p-cec"; - reg = <0x101B0000 0x200>; + reg = <0x101b0000 0x200>; interrupts = ; clocks = <&clock CLK_HDMI_CEC>; clock-names = "hdmicec"; @@ -838,7 +838,7 @@ adc: adc@12d10000 { compatible = "samsung,exynos-adc-v1"; - reg = <0x12D10000 0x100>; + reg = <0x12d10000 0x100>; interrupts = ; clocks = <&clock CLK_ADC>; clock-names = "adc"; @@ -849,7 +849,7 @@ sysmmu_g2d: sysmmu@10a60000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x10A60000 0x1000>; + reg = <0x10a60000 0x1000>; interrupt-parent = <&combiner>; interrupts = <24 5>; clock-names = "sysmmu", "master"; @@ -881,7 +881,7 @@ sysmmu_rotator: sysmmu@11d40000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11D40000 0x1000>; + reg = <0x11d40000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 0>; clock-names = "sysmmu", "master"; @@ -891,7 +891,7 @@ sysmmu_jpeg: sysmmu@11f20000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11F20000 0x1000>; + reg = <0x11f20000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 2>; power-domains = <&pd_gsc>; @@ -922,7 +922,7 @@ sysmmu_fimc_fd: sysmmu@132a0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x132A0000 0x1000>; + reg = <0x132a0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <5 0>; clock-names = "sysmmu"; @@ -952,7 +952,7 @@ sysmmu_fimc_mcuctl: sysmmu@132b0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x132B0000 0x1000>; + reg = <0x132b0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <5 4>; clock-names = "sysmmu"; @@ -962,7 +962,7 @@ sysmmu_fimc_odc: sysmmu@132c0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x132C0000 0x1000>; + reg = <0x132c0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <11 0>; clock-names = "sysmmu"; @@ -972,7 +972,7 @@ sysmmu_fimc_dis0: sysmmu@132d0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x132D0000 0x1000>; + reg = <0x132d0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <10 4>; clock-names = "sysmmu"; @@ -982,7 +982,7 @@ sysmmu_fimc_dis1: sysmmu@132e0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x132E0000 0x1000>; + reg = <0x132e0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <9 4>; clock-names = "sysmmu"; @@ -992,7 +992,7 @@ sysmmu_fimc_3dnr: sysmmu@132f0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x132F0000 0x1000>; + reg = <0x132f0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <5 6>; clock-names = "sysmmu"; @@ -1002,7 +1002,7 @@ sysmmu_fimc_lite0: sysmmu@13c40000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x13C40000 0x1000>; + reg = <0x13c40000 0x1000>; interrupt-parent = <&combiner>; interrupts = <3 4>; power-domains = <&pd_gsc>; @@ -1013,7 +1013,7 @@ sysmmu_fimc_lite1: sysmmu@13c50000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x13C50000 0x1000>; + reg = <0x13c50000 0x1000>; interrupt-parent = <&combiner>; interrupts = <24 1>; power-domains = <&pd_gsc>; @@ -1024,7 +1024,7 @@ sysmmu_gsc0: sysmmu@13e80000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x13E80000 0x1000>; + reg = <0x13e80000 0x1000>; interrupt-parent = <&combiner>; interrupts = <2 0>; power-domains = <&pd_gsc>; @@ -1035,7 +1035,7 @@ sysmmu_gsc1: sysmmu@13e90000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x13E90000 0x1000>; + reg = <0x13e90000 0x1000>; interrupt-parent = <&combiner>; interrupts = <2 2>; power-domains = <&pd_gsc>; @@ -1046,7 +1046,7 @@ sysmmu_gsc2: sysmmu@13ea0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x13EA0000 0x1000>; + reg = <0x13ea0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <2 4>; power-domains = <&pd_gsc>; @@ -1057,7 +1057,7 @@ sysmmu_gsc3: sysmmu@13eb0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x13EB0000 0x1000>; + reg = <0x13eb0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <2 6>; power-domains = <&pd_gsc>; diff --git a/arch/arm/boot/dts/exynos5260-xyref5260.dts b/arch/arm/boot/dts/exynos5260-xyref5260.dts index 3c3b751d43609cec49dae9d3a7b6dec97c2fd367..387b8494f18fb7cfae9d2912e453243975612209 100644 --- a/arch/arm/boot/dts/exynos5260-xyref5260.dts +++ b/arch/arm/boot/dts/exynos5260-xyref5260.dts @@ -87,7 +87,7 @@ status = "okay"; broken-cd; cap-mmc-highspeed; - supports-hs200-mode; /* 200 MHz */ + mmc-hs200-1_8v; card-detect-delay = <200>; samsung,dw-mshc-ciu-div = <3>; samsung,dw-mshc-sdr-timing = <0 4>; diff --git a/arch/arm/boot/dts/exynos5260.dtsi b/arch/arm/boot/dts/exynos5260.dtsi index ff1ee409eff31626940e2af6705eb4376e55e489..a97449b4640c7206bd8bde6218cb5cbcec2066cd 100644 --- a/arch/arm/boot/dts/exynos5260.dtsi +++ b/arch/arm/boot/dts/exynos5260.dtsi @@ -177,7 +177,7 @@ clock_g2d: clock-controller@10a00000 { compatible = "samsung,exynos5260-clock-g2d"; - reg = <0x10A00000 0x10000>; + reg = <0x10a00000 0x10000>; #clock-cells = <1>; clocks = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_G2D_333>; @@ -187,7 +187,7 @@ clock_mif: clock-controller@10ce0000 { compatible = "samsung,exynos5260-clock-mif"; - reg = <0x10CE0000 0x10000>; + reg = <0x10ce0000 0x10000>; #clock-cells = <1>; clocks = <&fin_pll>; clock-names = "fin_pll"; @@ -213,7 +213,7 @@ clock_fsys: clock-controller@122e0000 { compatible = "samsung,exynos5260-clock-fsys"; - reg = <0x122E0000 0x10000>; + reg = <0x122e0000 0x10000>; #clock-cells = <1>; clocks = <&fin_pll>, <&fin_pll>, @@ -233,7 +233,7 @@ clock_aud: clock-controller@128c0000 { compatible = "samsung,exynos5260-clock-aud"; - reg = <0x128C0000 0x10000>; + reg = <0x128c0000 0x10000>; #clock-cells = <1>; clocks = <&fin_pll>, <&clock_top TOP_FOUT_AUD_PLL>, @@ -247,7 +247,7 @@ clock_isp: clock-controller@133c0000 { compatible = "samsung,exynos5260-clock-isp"; - reg = <0x133C0000 0x10000>; + reg = <0x133c0000 0x10000>; #clock-cells = <1>; clocks = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_ISP1_266>, @@ -261,7 +261,7 @@ clock_gscl: clock-controller@13f00000 { compatible = "samsung,exynos5260-clock-gscl"; - reg = <0x13F00000 0x10000>; + reg = <0x13f00000 0x10000>; #clock-cells = <1>; clocks = <&fin_pll>, <&clock_top TOP_DOUT_ACLK_GSCL_400>, @@ -335,7 +335,7 @@ mct: timer@100b0000 { compatible = "samsung,exynos5260-mct", "samsung,exynos4210-mct"; - reg = <0x100B0000 0x1000>; + reg = <0x100b0000 0x1000>; clocks = <&fin_pll>, <&clock_peri PERI_CLK_MCT>; clock-names = "fin_pll", "mct"; interrupts = , @@ -356,8 +356,8 @@ compatible = "arm,cci-400"; #address-cells = <1>; #size-cells = <1>; - reg = <0x10F00000 0x1000>; - ranges = <0x0 0x10F00000 0x6000>; + reg = <0x10f00000 0x1000>; + ranges = <0x0 0x10f00000 0x6000>; cci_control0: slave-if@4000 { compatible = "arm,cci-400-ctrl-if"; @@ -392,18 +392,18 @@ pinctrl_2: pinctrl@128b0000 { compatible = "samsung,exynos5260-pinctrl"; - reg = <0x128B0000 0x1000>; + reg = <0x128b0000 0x1000>; interrupts = ; }; pmu_system_controller: system-controller@10d50000 { compatible = "samsung,exynos5260-pmu", "syscon"; - reg = <0x10D50000 0x10000>; + reg = <0x10d50000 0x10000>; }; uart0: serial@12c00000 { compatible = "samsung,exynos4210-uart"; - reg = <0x12C00000 0x100>; + reg = <0x12c00000 0x100>; interrupts = ; clocks = <&clock_peri PERI_CLK_UART0>, <&clock_peri PERI_SCLK_UART0>; clock-names = "uart", "clk_uart_baud0"; @@ -412,7 +412,7 @@ uart1: serial@12c10000 { compatible = "samsung,exynos4210-uart"; - reg = <0x12C10000 0x100>; + reg = <0x12c10000 0x100>; interrupts = ; clocks = <&clock_peri PERI_CLK_UART1>, <&clock_peri PERI_SCLK_UART1>; clock-names = "uart", "clk_uart_baud0"; @@ -421,7 +421,7 @@ uart2: serial@12c20000 { compatible = "samsung,exynos4210-uart"; - reg = <0x12C20000 0x100>; + reg = <0x12c20000 0x100>; interrupts = ; clocks = <&clock_peri PERI_CLK_UART2>, <&clock_peri PERI_SCLK_UART2>; clock-names = "uart", "clk_uart_baud0"; @@ -499,7 +499,7 @@ hsi2c_0: i2c@12da0000 { compatible = "samsung,exynos5260-hsi2c"; - reg = <0x12DA0000 0x1000>; + reg = <0x12da0000 0x1000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -512,7 +512,7 @@ hsi2c_1: i2c@12db0000 { compatible = "samsung,exynos5260-hsi2c"; - reg = <0x12DB0000 0x1000>; + reg = <0x12db0000 0x1000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -525,7 +525,7 @@ hsi2c_2: i2c@12dc0000 { compatible = "samsung,exynos5260-hsi2c"; - reg = <0x12DC0000 0x1000>; + reg = <0x12dc0000 0x1000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -538,7 +538,7 @@ hsi2c_3: i2c@12dd0000 { compatible = "samsung,exynos5260-hsi2c"; - reg = <0x12DD0000 0x1000>; + reg = <0x12dd0000 0x1000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/exynos5410-odroidxu.dts b/arch/arm/boot/dts/exynos5410-odroidxu.dts index d1cbc6b8a5703aa3fe09cd298777864651e7d953..232561620da2a003aabff3b1d9984600c37c75eb 100644 --- a/arch/arm/boot/dts/exynos5410-odroidxu.dts +++ b/arch/arm/boot/dts/exynos5410-odroidxu.dts @@ -164,8 +164,7 @@ }; &hsi2c_4 { - samsung,i2c-sda-delay = <100>; - samsung,i2c-max-bus-freq = <400000>; + clock-frequency = <400000>; status = "okay"; usb3503: usb-hub@8 { diff --git a/arch/arm/boot/dts/exynos5410.dtsi b/arch/arm/boot/dts/exynos5410.dtsi index 8a6b890fb8f712578e11dd864112c2e0c4b585cb..350b8afa0a3a039a8d95c33df795c7734b5dd21a 100644 --- a/arch/arm/boot/dts/exynos5410.dtsi +++ b/arch/arm/boot/dts/exynos5410.dtsi @@ -81,7 +81,7 @@ clock_audss: audss-clock-controller@3810000 { compatible = "samsung,exynos5410-audss-clock"; - reg = <0x03810000 0x0C>; + reg = <0x03810000 0x0c>; #clock-cells = <1>; clocks = <&fin_pll>, <&clock CLK_FOUT_EPLL>; clock-names = "pll_ref", "pll_in"; diff --git a/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi b/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi index d19bc3d266fa0f8d62721f451ec4808f37b664a0..63675fe189cdb6019139c404c38c52bdb76fda2c 100644 --- a/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi +++ b/arch/arm/boot/dts/exynos5420-galaxy-tab-common.dtsi @@ -51,7 +51,6 @@ gpio-keys { compatible = "gpio-keys"; - pinctrl-names = "default"; key-power { debounce-interval = <10>; diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi index 9f2523a873d9df41ff64e1162f06d64bac14eca1..13d7be236a23a5819cd4f73bb9a7eacc55541524 100644 --- a/arch/arm/boot/dts/exynos5420.dtsi +++ b/arch/arm/boot/dts/exynos5420.dtsi @@ -37,12 +37,123 @@ spi2 = &spi_2; }; + bus_disp1: bus-disp1 { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK400_DISP1>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_disp1_fimd: bus-disp1-fimd { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK300_DISP1>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_fsys: bus-fsys { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK200_FSYS>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_fsys2: bus-fsys2 { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_fsys_apb: bus-fsys-apb { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_PCLK200_FSYS>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_g2d: bus-g2d { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK333_G2D>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_g2d_acp: bus-g2d-acp { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK266_G2D>; + clock-names = "bus"; + status = "disabled"; + }; + bus_gen: bus-gen { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK266>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_gscl_scaler: bus-gscl-scaler { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK300_GSCL>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_jpeg: bus-jpeg { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK300_JPEG>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_jpeg_apb: bus-jpeg-apb { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK166>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_mfc: bus-mfc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK333>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_mscl: bus-mscl { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK400_MSCL>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_noc: bus-noc { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK100_NOC>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_peri: bus-peri { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK66>; + clock-names = "bus"; + status = "disabled"; + }; + + bus_wcore: bus-wcore { + compatible = "samsung,exynos-bus"; + clocks = <&clock CLK_DOUT_ACLK400_WCORE>; + clock-names = "bus"; + status = "disabled"; + }; + /* * The 'cpus' node is not present here but instead it is provided * by exynos5420-cpus.dtsi or exynos5422-cpus.dtsi. */ - cluster_a15_opp_table: opp-table0 { + cluster_a15_opp_table: opp-table-0 { compatible = "operating-points-v2"; opp-shared; @@ -108,7 +219,7 @@ }; }; - cluster_a7_opp_table: opp-table1 { + cluster_a7_opp_table: opp-table-1 { compatible = "operating-points-v2"; opp-shared; @@ -182,7 +293,7 @@ clock_audss: audss-clock-controller@3810000 { compatible = "samsung,exynos5420-audss-clock"; - reg = <0x03810000 0x0C>; + reg = <0x03810000 0x0c>; #clock-cells = <1>; clocks = <&clock CLK_FIN_PLL>, <&clock CLK_MAU_EPLL>, <&clock CLK_SCLK_MAUDIO0>, <&clock CLK_SCLK_MAUPCM0>; @@ -262,37 +373,37 @@ nocp_mem0_0: nocp@10ca1000 { compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1000 0x200>; + reg = <0x10ca1000 0x200>; status = "disabled"; }; nocp_mem0_1: nocp@10ca1400 { compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1400 0x200>; + reg = <0x10ca1400 0x200>; status = "disabled"; }; nocp_mem1_0: nocp@10ca1800 { compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1800 0x200>; + reg = <0x10ca1800 0x200>; status = "disabled"; }; nocp_mem1_1: nocp@10ca1c00 { compatible = "samsung,exynos5420-nocp"; - reg = <0x10CA1C00 0x200>; + reg = <0x10ca1c00 0x200>; status = "disabled"; }; nocp_g3d_0: nocp@11a51000 { compatible = "samsung,exynos5420-nocp"; - reg = <0x11A51000 0x200>; + reg = <0x11a51000 0x200>; status = "disabled"; }; nocp_g3d_1: nocp@11a51400 { compatible = "samsung,exynos5420-nocp"; - reg = <0x11A51400 0x200>; + reg = <0x11a51400 0x200>; status = "disabled"; }; @@ -374,14 +485,14 @@ disp_pd: power-domain@100440c0 { compatible = "samsung,exynos4210-pd"; - reg = <0x100440C0 0x20>; + reg = <0x100440c0 0x20>; #power-domain-cells = <0>; label = "DISP"; }; mau_pd: power-domain@100440e0 { compatible = "samsung,exynos4210-pd"; - reg = <0x100440E0 0x20>; + reg = <0x100440e0 0x20>; #power-domain-cells = <0>; label = "MAU"; }; @@ -442,7 +553,7 @@ pdma0: dma-controller@121a0000 { compatible = "arm,pl330", "arm,primecell"; - reg = <0x121A0000 0x1000>; + reg = <0x121a0000 0x1000>; interrupts = ; clocks = <&clock CLK_PDMA0>; clock-names = "apb_pclk"; @@ -451,7 +562,7 @@ pdma1: dma-controller@121b0000 { compatible = "arm,pl330", "arm,primecell"; - reg = <0x121B0000 0x1000>; + reg = <0x121b0000 0x1000>; interrupts = ; clocks = <&clock CLK_PDMA1>; clock-names = "apb_pclk"; @@ -469,7 +580,7 @@ mdma1: dma-controller@11c10000 { compatible = "arm,pl330", "arm,primecell"; - reg = <0x11C10000 0x1000>; + reg = <0x11c10000 0x1000>; interrupts = ; clocks = <&clock CLK_MDMA1>; clock-names = "apb_pclk"; @@ -507,7 +618,7 @@ i2s1: i2s@12d60000 { compatible = "samsung,exynos5420-i2s"; - reg = <0x12D60000 0x100>; + reg = <0x12d60000 0x100>; dmas = <&pdma1 12>, <&pdma1 11>; dma-names = "tx", "rx"; @@ -523,7 +634,7 @@ i2s2: i2s@12d70000 { compatible = "samsung,exynos5420-i2s"; - reg = <0x12D70000 0x100>; + reg = <0x12d70000 0x100>; dmas = <&pdma0 12>, <&pdma0 11>; dma-names = "tx", "rx"; @@ -592,12 +703,12 @@ }; mipi_phy: mipi-video-phy { - compatible = "samsung,s5pv210-mipi-video-phy"; + compatible = "samsung,exynos5420-mipi-video-phy"; syscon = <&pmu_system_controller>; #phy-cells = <1>; }; - dsi@14500000 { + dsi: dsi@14500000 { compatible = "samsung,exynos5410-mipi-dsi"; reg = <0x14500000 0x10000>; interrupts = ; @@ -612,7 +723,7 @@ hsi2c_8: i2c@12e00000 { compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12E00000 0x1000>; + reg = <0x12e00000 0x1000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -625,7 +736,7 @@ hsi2c_9: i2c@12e10000 { compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12E10000 0x1000>; + reg = <0x12e10000 0x1000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -638,7 +749,7 @@ hsi2c_10: i2c@12e20000 { compatible = "samsung,exynos5250-hsi2c"; - reg = <0x12E20000 0x1000>; + reg = <0x12e20000 0x1000>; interrupts = ; #address-cells = <1>; #size-cells = <0>; @@ -665,13 +776,13 @@ #sound-dai-cells = <0>; }; - hdmiphy: hdmiphy@145d0000 { - reg = <0x145D0000 0x20>; + hdmiphy: hdmi-phy@145d0000 { + reg = <0x145d0000 0x20>; }; hdmicec: cec@101b0000 { compatible = "samsung,s5p-cec"; - reg = <0x101B0000 0x200>; + reg = <0x101b0000 0x200>; interrupts = ; clocks = <&clock CLK_HDMI_CEC>; clock-names = "hdmicec"; @@ -696,7 +807,7 @@ rotator: rotator@11c00000 { compatible = "samsung,exynos5250-rotator"; - reg = <0x11C00000 0x64>; + reg = <0x11c00000 0x64>; interrupts = ; clocks = <&clock CLK_ROTATOR>; clock-names = "rotator"; @@ -805,7 +916,7 @@ jpeg_0: jpeg@11f50000 { compatible = "samsung,exynos5420-jpeg"; - reg = <0x11F50000 0x1000>; + reg = <0x11f50000 0x1000>; interrupts = ; clock-names = "jpeg"; clocks = <&clock CLK_JPEG>; @@ -814,7 +925,7 @@ jpeg_1: jpeg@11f60000 { compatible = "samsung,exynos5420-jpeg"; - reg = <0x11F60000 0x1000>; + reg = <0x11f60000 0x1000>; interrupts = ; clock-names = "jpeg"; clocks = <&clock CLK_JPEG2>; @@ -879,7 +990,7 @@ sysmmu_g2dr: sysmmu@10a60000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x10A60000 0x1000>; + reg = <0x10a60000 0x1000>; interrupt-parent = <&combiner>; interrupts = <24 5>; clock-names = "sysmmu", "master"; @@ -889,7 +1000,7 @@ sysmmu_g2dw: sysmmu@10a70000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x10A70000 0x1000>; + reg = <0x10a70000 0x1000>; interrupt-parent = <&combiner>; interrupts = <22 2>; clock-names = "sysmmu", "master"; @@ -910,7 +1021,7 @@ sysmmu_gscl0: sysmmu@13e80000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x13E80000 0x1000>; + reg = <0x13e80000 0x1000>; interrupt-parent = <&combiner>; interrupts = <2 0>; clock-names = "sysmmu", "master"; @@ -921,7 +1032,7 @@ sysmmu_gscl1: sysmmu@13e90000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x13E90000 0x1000>; + reg = <0x13e90000 0x1000>; interrupt-parent = <&combiner>; interrupts = <2 2>; clock-names = "sysmmu", "master"; @@ -953,7 +1064,7 @@ sysmmu_scaler2r: sysmmu@128a0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x128A0000 0x1000>; + reg = <0x128a0000 0x1000>; interrupts = ; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_MSCL2>, <&clock CLK_MSCL2>; @@ -963,7 +1074,7 @@ sysmmu_scaler0w: sysmmu@128c0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x128C0000 0x1000>; + reg = <0x128c0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <27 2>; clock-names = "sysmmu", "master"; @@ -974,7 +1085,7 @@ sysmmu_scaler1w: sysmmu@128d0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x128D0000 0x1000>; + reg = <0x128d0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <22 6>; clock-names = "sysmmu", "master"; @@ -985,7 +1096,7 @@ sysmmu_scaler2w: sysmmu@128e0000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x128E0000 0x1000>; + reg = <0x128e0000 0x1000>; interrupt-parent = <&combiner>; interrupts = <19 6>; clock-names = "sysmmu", "master"; @@ -996,7 +1107,7 @@ sysmmu_rotator: sysmmu@11d40000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11D40000 0x1000>; + reg = <0x11d40000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 0>; clock-names = "sysmmu", "master"; @@ -1006,7 +1117,7 @@ sysmmu_jpeg0: sysmmu@11f10000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11F10000 0x1000>; + reg = <0x11f10000 0x1000>; interrupt-parent = <&combiner>; interrupts = <4 2>; clock-names = "sysmmu", "master"; @@ -1016,7 +1127,7 @@ sysmmu_jpeg1: sysmmu@11f20000 { compatible = "samsung,exynos-sysmmu"; - reg = <0x11F20000 0x1000>; + reg = <0x11f20000 0x1000>; interrupts = ; clock-names = "sysmmu", "master"; clocks = <&clock CLK_SMMU_JPEG2>, <&clock CLK_JPEG2>; @@ -1066,118 +1177,6 @@ power-domains = <&disp_pd>; #iommu-cells = <0>; }; - - bus_wcore: bus-wcore { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_WCORE>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_noc: bus-noc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK100_NOC>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_fsys_apb: bus-fsys-apb { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_PCLK200_FSYS>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_fsys: bus-fsys { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK200_FSYS>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_fsys2: bus-fsys2 { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK200_FSYS2>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_mfc: bus-mfc { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK333>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_gen: bus-gen { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK266>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_peri: bus-peri { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK66>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_g2d: bus-g2d { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK333_G2D>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_g2d_acp: bus-g2d-acp { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK266_G2D>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_jpeg: bus-jpeg { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_JPEG>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_jpeg_apb: bus-jpeg-apb { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK166>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_disp1_fimd: bus-disp1-fimd { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_DISP1>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_disp1: bus-disp1 { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_DISP1>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_gscl_scaler: bus-gscl-scaler { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK300_GSCL>; - clock-names = "bus"; - status = "disabled"; - }; - - bus_mscl: bus-mscl { - compatible = "samsung,exynos-bus"; - clocks = <&clock CLK_DOUT_ACLK400_MSCL>; - clock-names = "bus"; - status = "disabled"; - }; }; thermal-zones { diff --git a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi index 35818c4cd8524ad264328ee667216cf7e8cfcbb0..30fc677d8bac5fdbe49cc081d21a5518f372d022 100644 --- a/arch/arm/boot/dts/exynos5422-odroid-core.dtsi +++ b/arch/arm/boot/dts/exynos5422-odroid-core.dtsi @@ -16,7 +16,7 @@ / { memory@40000000 { device_type = "memory"; - reg = <0x40000000 0x7EA00000>; + reg = <0x40000000 0x7ea00000>; }; chosen { @@ -35,7 +35,7 @@ }; }; - bus_wcore_opp_table: opp-table2 { + bus_wcore_opp_table: opp-table-2 { compatible = "operating-points-v2"; /* derived from 532MHz MPLL */ @@ -61,7 +61,7 @@ }; }; - bus_noc_opp_table: opp-table3 { + bus_noc_opp_table: opp-table-3 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -79,7 +79,7 @@ }; }; - bus_fsys_apb_opp_table: opp-table4 { + bus_fsys_apb_opp_table: opp-table-4 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -91,7 +91,7 @@ }; }; - bus_fsys2_opp_table: opp-table5 { + bus_fsys2_opp_table: opp-table-5 { compatible = "operating-points-v2"; /* derived from 600MHz DPLL */ @@ -106,7 +106,7 @@ }; }; - bus_mfc_opp_table: opp-table6 { + bus_mfc_opp_table: opp-table-6 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -127,7 +127,7 @@ }; }; - bus_gen_opp_table: opp-table7 { + bus_gen_opp_table: opp-table-7 { compatible = "operating-points-v2"; /* derived from 532MHz MPLL */ @@ -145,7 +145,7 @@ }; }; - bus_peri_opp_table: opp-table8 { + bus_peri_opp_table: opp-table-8 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -154,7 +154,7 @@ }; }; - bus_g2d_opp_table: opp-table9 { + bus_g2d_opp_table: opp-table-9 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -175,7 +175,7 @@ }; }; - bus_g2d_acp_opp_table: opp-table10 { + bus_g2d_acp_opp_table: opp-table-10 { compatible = "operating-points-v2"; /* derived from 532MHz MPLL */ @@ -193,7 +193,7 @@ }; }; - bus_jpeg_opp_table: opp-table11 { + bus_jpeg_opp_table: opp-table-11 { compatible = "operating-points-v2"; /* derived from 600MHz DPLL */ @@ -211,7 +211,7 @@ }; }; - bus_jpeg_apb_opp_table: opp-table12 { + bus_jpeg_apb_opp_table: opp-table-12 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -229,7 +229,7 @@ }; }; - bus_disp1_fimd_opp_table: opp-table13 { + bus_disp1_fimd_opp_table: opp-table-13 { compatible = "operating-points-v2"; /* derived from 600MHz DPLL */ @@ -241,7 +241,7 @@ }; }; - bus_disp1_opp_table: opp-table14 { + bus_disp1_opp_table: opp-table-14 { compatible = "operating-points-v2"; /* derived from 600MHz DPLL */ @@ -256,7 +256,7 @@ }; }; - bus_gscl_opp_table: opp-table15 { + bus_gscl_opp_table: opp-table-15 { compatible = "operating-points-v2"; /* derived from 600MHz DPLL */ @@ -271,7 +271,7 @@ }; }; - bus_mscl_opp_table: opp-table16 { + bus_mscl_opp_table: opp-table-16 { compatible = "operating-points-v2"; /* derived from 666MHz CPLL */ @@ -292,7 +292,7 @@ }; }; - dmc_opp_table: opp-table17 { + dmc_opp_table: opp-table-17 { compatible = "operating-points-v2"; opp00 { diff --git a/arch/arm/boot/dts/exynos5422-samsung-k3g.dts b/arch/arm/boot/dts/exynos5422-samsung-k3g.dts new file mode 100644 index 0000000000000000000000000000000000000000..df41723d56d40a4514ee8031c18101421f06c714 --- /dev/null +++ b/arch/arm/boot/dts/exynos5422-samsung-k3g.dts @@ -0,0 +1,674 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Samsung Galaxy S5 (SM-G900H) device-tree source + * + * Copyright (c) 2023 Markuss Broks + */ + +/dts-v1/; +#include +#include +#include +#include "exynos5800.dtsi" +#include "exynos5422-cpus.dtsi" + +/ { + model = "Samsung Galaxy S5 (SM-G900H)"; + compatible = "samsung,k3g", "samsung,exynos5800", \ + "samsung,exynos5"; + + chassis-type = "handset"; + + memory@20000000 { + device_type = "memory"; + reg = <0x20000000 0x80000000>; /* 2 GiB */ + }; + + fixed-rate-clocks { + oscclk { + compatible = "samsung,exynos5420-oscclk"; + clock-frequency = <24000000>; + }; + }; + + firmware@2073000 { + compatible = "samsung,secure-firmware"; + reg = <0x02073000 0x1000>; + }; + + tsp_vdd: regulator-tsp-vdd-en { + compatible = "regulator-fixed"; + regulator-name = "tsp_vdd_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpy3 5 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&cpu0 { + cpu-supply = <&buck2_reg>; +}; + +&cpu4 { + cpu-supply = <&buck6_reg>; +}; + +&gpu { + status = "okay"; + mali-supply = <&buck4_reg>; +}; + +&hsi2c_7 { + status = "okay"; + + pmic@66 { + compatible = "samsung,s2mps11-pmic"; + reg = <0x66>; + + interrupt-parent = <&gpx0>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + wakeup-source; + + pinctrl-names = "default"; + pinctrl-0 = <&s2mps11_irq>; + + s2mps11_osc: clocks { + compatible = "samsung,s2mps11-clk"; + #clock-cells = <1>; + clock-output-names = "s2mps11_ap", + "s2mps11_cp", "s2mps11_bt"; + }; + + regulators { + buck1_reg: BUCK1 { + regulator-name = "VDD_MIF"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1300000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck2_reg: BUCK2 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck3_reg: BUCK3 { + regulator-name = "VDD_INT"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck4_reg: BUCK4 { + regulator-name = "VDD_G3D"; + regulator-min-microvolt = <700000>; + regulator-max-microvolt = <1400000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck5_reg: BUCK5 { + regulator-name = "VDD_MEM"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck6_reg: BUCK6 { + regulator-name = "VDD_KFC"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + buck7_reg: BUCK7 { + regulator-name = "VIN_LLDO"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + }; + + buck8_reg: BUCK8 { + regulator-name = "VIN_MLDO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2100000>; + regulator-always-on; + }; + + buck9_reg: BUCK9 { + regulator-name = "VIN_HLDO"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3500000>; + regulator-always-on; + }; + + buck10_reg: BUCK10 { + regulator-name = "VDD_CAM_ISP"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3550000>; + }; + + ldo1_reg: LDO1 { + regulator-name = "VDD_ALIVE"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + + ldo2_reg: LDO2 { + regulator-name = "VDD_APIO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo3_reg: LDO3 { + regulator-name = "VDD_APIO_MMC01"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo4_reg: LDO4 { + regulator-name = "VDD_ADC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo5_reg: LDO5 { + regulator-name = "VDD_HRM_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + ldo6_reg: LDO6 { + regulator-name = "VDD_MIPI"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo7_reg: LDO7 { + regulator-name = "VDD_MIPI_PLL_ABB1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo8_reg: LDO8 { + regulator-name = "VDD_VTF"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo9_reg: LDO9 { + regulator-name = "VDD_UOTG"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo10_reg: LDO10 { + regulator-name = "VDDQ_PRE"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo11_reg: LDO11 { + regulator-name = "VDD_HSIC_1V0"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo12_reg: LDO12 { + regulator-name = "VDD_HSIC_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo13_reg: LDO13 { + regulator-name = "VDD_APIO_MMC2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <2800000>; + regulator-boot-on; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo14_reg: LDO14 { + regulator-name = "VDD_MOTOR"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo15_reg: LDO15 { + regulator-name = "VDD_CAM1_2V8"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo16_reg: LDO16 { + regulator-name = "VDD_AP"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-always-on; + regulator-boot-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo17_reg: LDO17 { + /* Unused */ + regulator-name = "VDD_LDO17"; + }; + + ldo18_reg: LDO18 { + regulator-name = "VDD_CODEC"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo19_reg: LDO19 { + regulator-name = "VDD_VMMC"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo20_reg: LDO20 { + regulator-name = "VDD_CAM1_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo21_reg: LDO21 { + regulator-name = "VDD_CAM_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo22_reg: LDO22 { + regulator-name = "VDD_CAM0_S_CORE"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo23_reg: LDO23 { + regulator-name = "VDD_MIFS"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo24_reg: LDO24 { + regulator-name = "VDD_MHL_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo25_reg: LDO25 { + regulator-name = "VDD_LCD_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo26_reg: LDO26 { + regulator-name = "VDD_CAM0_AF"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo27_reg: LDO27 { + regulator-name = "VDD_G3DS"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + ldo28_reg: LDO28 { + regulator-name = "VDD_LCD_3V0"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3000000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo29_reg: LDO29 { + /* Unused */ + regulator-name = "VDD_LDO29"; + }; + + ldo30_reg: LDO30 { + regulator-name = "VDD_TOUCH"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo31_reg: LDO31 { + regulator-name = "VDD_COMP"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo32_reg: LDO32 { + regulator-name = "VDD_TOUCH_IO"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo33_reg: LDO33 { + regulator-name = "VDD_MHL_1V8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo34_reg: LDO34 { + regulator-name = "VDD_HRM_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo35_reg: LDO35 { + regulator-name = "VDD_SIL"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + ldo36_reg: LDO36 { + /* Unused */ + regulator-name = "VDD_LDO36"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo37_reg: LDO37 { + /* Unused */ + regulator-name = "VDD_LDO37"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3950000>; + }; + + ldo38_reg: LDO38 { + regulator-name = "VDD_KEY_LED"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + }; + }; +}; + +&i2c_0 { + status = "okay"; + + touchscreen@20 { + compatible = "syna,rmi4-i2c"; + reg = <0x20>; + interrupt-parent = <&gpx1>; + interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + vio-supply = <&ldo32_reg>; + vdd-supply = <&tsp_vdd>; + syna,startup-delay-ms = <100>; + + pinctrl-0 = <&touch_irq>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + rmi4-f01@1 { + reg = <0x1>; + syna,nosleep-mode = <1>; + }; + + rmi4-f12@12 { + reg = <0x12>; + syna,sensor-type = <1>; + }; + }; +}; + +/* eMMC flash */ +&mmc_0 { + status = "okay"; + mmc-hs200-1_8v; + cap-mmc-highspeed; + non-removable; + clock-frequency = <400000000>; + samsung,dw-mshc-ciu-div = <3>; + samsung,dw-mshc-sdr-timing = <0 4>; + samsung,dw-mshc-ddr-timing = <0 2>; + samsung,dw-mshc-hs400-timing = <0 2>; + samsung,read-strobe-delay = <90>; + pinctrl-names = "default"; + pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus1 &sd0_bus4 &sd0_bus8 &sd0_rclk>; + bus-width = <8>; +}; + +&pinctrl_0 { + s2mps11_irq: s2mps11-irq-pins { + samsung,pins = "gpx0-7"; + samsung,pin-function = ; + samsung,pin-pud = ; + samsung,pin-drv = ; + }; + + touch_irq: touch-irq-pins { + samsung,pins = "gpx1-6"; + samsung,pin-pud = ; + }; +}; + +&rtc { + status = "okay"; + clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>; + clock-names = "rtc", "rtc_src"; +}; + +&timer { + arm,cpu-registers-not-fw-configured; +}; + +&tmu_cpu0 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu1 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu2 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_cpu3 { + vtmu-supply = <&ldo10_reg>; +}; + +&tmu_gpu { + vtmu-supply = <&ldo10_reg>; +}; + +&usbdrd_dwc3_0 { + dr_mode = "peripheral"; +}; + +&usbdrd_dwc3_1 { + dr_mode = "peripheral"; +}; + +&usbdrd3_0 { + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; +}; + +&usbdrd3_1 { + vdd33-supply = <&ldo9_reg>; + vdd10-supply = <&ldo11_reg>; +}; diff --git a/arch/arm/boot/dts/exynos54xx.dtsi b/arch/arm/boot/dts/exynos54xx.dtsi index 3ec43761d8b9393f48a13254fc9fb77ae877fad4..5c799886c2756292cf4f123bc676a458c21ab066 100644 --- a/arch/arm/boot/dts/exynos54xx.dtsi +++ b/arch/arm/boot/dts/exynos54xx.dtsi @@ -142,15 +142,15 @@ status = "disabled"; }; - usbdrd3_0: usb3-0 { + usbdrd3_0: usb@12000000 { compatible = "samsung,exynos5250-dwusb3"; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0x0 0x12000000 0x10000>; - usbdrd_dwc3_0: usb@12000000 { + usbdrd_dwc3_0: usb@0 { compatible = "snps,dwc3"; - reg = <0x12000000 0x10000>; + reg = <0x0 0x10000>; interrupts = ; phys = <&usbdrd_phy0 0>, <&usbdrd_phy0 1>; phy-names = "usb2-phy", "usb3-phy"; @@ -164,15 +164,15 @@ #phy-cells = <1>; }; - usbdrd3_1: usb3-1 { + usbdrd3_1: usb@12400000 { compatible = "samsung,exynos5250-dwusb3"; #address-cells = <1>; #size-cells = <1>; - ranges; + ranges = <0x0 0x12400000 0x10000>; - usbdrd_dwc3_1: usb@12400000 { + usbdrd_dwc3_1: usb@0 { compatible = "snps,dwc3"; - reg = <0x12400000 0x10000>; + reg = <0x0 0x10000>; phys = <&usbdrd_phy1 0>, <&usbdrd_phy1 1>; phy-names = "usb2-phy", "usb3-phy"; snps,dis_u3_susphy_quirk; diff --git a/arch/arm/boot/dts/exynos5800.dtsi b/arch/arm/boot/dts/exynos5800.dtsi index 526729dad53f1365ab05866ca73789d69860d088..8328ddb3b02f91ac73bbf756a93c1188afd9a586 100644 --- a/arch/arm/boot/dts/exynos5800.dtsi +++ b/arch/arm/boot/dts/exynos5800.dtsi @@ -148,6 +148,10 @@ }; }; +&dsi { + compatible = "samsung,exynos5422-mipi-dsi"; +}; + &mfc { compatible = "samsung,mfc-v8"; }; diff --git a/arch/arm/boot/dts/gemini-dlink-dns-313.dts b/arch/arm/boot/dts/gemini-dlink-dns-313.dts index eba1c94ed7f7742c20f9ff786a17da5c12195557..138c47e1ac1b1dee69caba7009adb486b8339715 100644 --- a/arch/arm/boot/dts/gemini-dlink-dns-313.dts +++ b/arch/arm/boot/dts/gemini-dlink-dns-313.dts @@ -80,6 +80,15 @@ #cooling-cells = <2>; }; + /* + * This is the type B USB connector on the device, + * a GPIO-controlled USB VBUS detect + */ + usb1_phy: phy { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + #phy-cells = <0>; + vbus-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; + }; /* Global Mixed-Mode Technology G751 mounted on GPIO I2C */ i2c { @@ -164,6 +173,8 @@ compatible = "cortina,gemini-flash", "jedec-flash"; status = "okay"; reg = <0x30000000 0x00080000>; + #address-cells = <1>; + #size-cells = <1>; /* * This "RedBoot" is the Storlink derivative. @@ -300,5 +311,13 @@ ide@63000000 { status = "okay"; }; + + usb@69000000 { + status = "okay"; + dr_mode = "peripheral"; + usb-phy = <&usb1_phy>; + pinctrl-names = "default"; + pinctrl-0 = <&usb_default_pins>; + }; }; }; diff --git a/arch/arm/boot/dts/gemini-wbd111.dts b/arch/arm/boot/dts/gemini-wbd111.dts index de3c4416b0fb090b6b57b8b644922273dc618629..3c88c59ab481c895014619902aa998c9d0efc4f7 100644 --- a/arch/arm/boot/dts/gemini-wbd111.dts +++ b/arch/arm/boot/dts/gemini-wbd111.dts @@ -87,33 +87,10 @@ /* 8MB of flash */ reg = <0x30000000 0x00800000>; - partition@0 { - label = "RedBoot"; - reg = <0x00000000 0x00020000>; - read-only; - }; - partition@20000 { - label = "kernel"; - reg = <0x00020000 0x00100000>; - }; - partition@120000 { - label = "rootfs"; - reg = <0x00120000 0x006a0000>; - }; - partition@7c0000 { - label = "VCTL"; - reg = <0x007c0000 0x00010000>; - read-only; - }; - partition@7d0000 { - label = "cfg"; - reg = <0x007d0000 0x00010000>; - read-only; - }; - partition@7e0000 { - label = "FIS"; - reg = <0x007e0000 0x00010000>; - read-only; + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x7e0000 */ + fis-index-block = <0x3f>; }; }; diff --git a/arch/arm/boot/dts/gemini-wbd222.dts b/arch/arm/boot/dts/gemini-wbd222.dts index e5ceaadbcc1a1f8cab3d586429c2b64b22897293..ff72bbc4db3e20439669e4f31072e16ac4757e2a 100644 --- a/arch/arm/boot/dts/gemini-wbd222.dts +++ b/arch/arm/boot/dts/gemini-wbd222.dts @@ -91,33 +91,10 @@ /* 8MB of flash */ reg = <0x30000000 0x00800000>; - partition@0 { - label = "RedBoot"; - reg = <0x00000000 0x00020000>; - read-only; - }; - partition@20000 { - label = "kernel"; - reg = <0x00020000 0x00100000>; - }; - partition@120000 { - label = "rootfs"; - reg = <0x00120000 0x006a0000>; - }; - partition@7c0000 { - label = "VCTL"; - reg = <0x007c0000 0x00010000>; - read-only; - }; - partition@7d0000 { - label = "cfg"; - reg = <0x007d0000 0x00010000>; - read-only; - }; - partition@7e0000 { - label = "FIS"; - reg = <0x007e0000 0x00010000>; - read-only; + partitions { + compatible = "redboot-fis"; + /* Eraseblock at 0x7e0000 */ + fis-index-block = <0x3f>; }; }; diff --git a/arch/arm/boot/dts/gemini.dtsi b/arch/arm/boot/dts/gemini.dtsi index e836bd0818d42b213cfc1545baa4b31c6e9ad606..befe322bd7de9f63033dd265a6c0870657d3e9dd 100644 --- a/arch/arm/boot/dts/gemini.dtsi +++ b/arch/arm/boot/dts/gemini.dtsi @@ -22,8 +22,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pflash_default_pins>; bank-width = <2>; - #address-cells = <1>; - #size-cells = <1>; status = "disabled"; }; @@ -441,7 +439,7 @@ }; usb0: usb@68000000 { - compatible = "cortina,gemini-usb", "faraday,fotg210"; + compatible = "cortina,gemini-usb", "faraday,fotg200"; reg = <0x68000000 0x1000>; interrupts = <10 IRQ_TYPE_LEVEL_HIGH>; resets = <&syscon GEMINI_RESET_USB0>; @@ -457,12 +455,14 @@ */ pinctrl-names = "default"; pinctrl-0 = <&usb_default_pins>; + /* Default to host mode */ + dr_mode = "host"; syscon = <&syscon>; status = "disabled"; }; usb1: usb@69000000 { - compatible = "cortina,gemini-usb", "faraday,fotg210"; + compatible = "cortina,gemini-usb", "faraday,fotg200"; reg = <0x69000000 0x1000>; interrupts = <11 IRQ_TYPE_LEVEL_HIGH>; resets = <&syscon GEMINI_RESET_USB1>; diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi index 7f4c602454a5fb0721a34833f773c98ea0d1b155..d19508c8f9ed63a98648ab1b9c7ea1f1d76660cd 100644 --- a/arch/arm/boot/dts/imx23.dtsi +++ b/arch/arm/boot/dts/imx23.dtsi @@ -64,8 +64,6 @@ reg = <0x80004000 0x2000>; interrupts = <0 14 20 0 13 13 13 13>; - interrupt-names = "empty", "ssp0", "ssp1", "empty", - "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <8>; clocks = <&clks 15>; diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi index 130b4145af827016d3da3856ab1256531d48fdc8..a8d3c3113e0f60b0414899d038bea32d818ec6a7 100644 --- a/arch/arm/boot/dts/imx28.dtsi +++ b/arch/arm/boot/dts/imx28.dtsi @@ -85,10 +85,6 @@ 88 88 88 88 88 88 88 88 87 86 0 0>; - interrupt-names = "ssp0", "ssp1", "ssp2", "ssp3", - "gpmi0", "gmpi1", "gpmi2", "gmpi3", - "gpmi4", "gmpi5", "gpmi6", "gmpi7", - "hsadc", "lcdif", "empty", "empty"; #dma-cells = <1>; dma-channels = <16>; clocks = <&clks 25>; @@ -1001,10 +997,6 @@ 80 81 68 69 70 71 72 73 74 75 76 77>; - interrupt-names = "auart4-rx", "auart4-tx", "spdif-tx", "empty", - "saif0", "saif1", "i2c0", "i2c1", - "auart0-rx", "auart0-tx", "auart1-rx", "auart1-tx", - "auart2-rx", "auart2-tx", "auart3-rx", "auart3-tx"; #dma-cells = <1>; dma-channels = <16>; clocks = <&clks 26>; diff --git a/arch/arm/boot/dts/imx50-kobo-aura.dts b/arch/arm/boot/dts/imx50-kobo-aura.dts index 51bf6117fb124078e3a0494c1f1a14f73aaafdef..467db6b4ed7f83cc97c0bb88a8e16d4408fe6322 100644 --- a/arch/arm/boot/dts/imx50-kobo-aura.dts +++ b/arch/arm/boot/dts/imx50-kobo-aura.dts @@ -26,7 +26,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_leds>; - on { + led-on { label = "kobo_aura:orange:on"; gpios = <&gpio6 24 GPIO_ACTIVE_LOW>; panic-indicator; diff --git a/arch/arm/boot/dts/imx51-zii-rdu1.dts b/arch/arm/boot/dts/imx51-zii-rdu1.dts index 3140f038aa982f9ee4ab7f4e308c774c565ccc50..e537e06e11d7e6ae198d599a30c41341c4ab9f0c 100644 --- a/arch/arm/boot/dts/imx51-zii-rdu1.dts +++ b/arch/arm/boot/dts/imx51-zii-rdu1.dts @@ -556,7 +556,7 @@ pinctrl-0 = <&pinctrl_uart3>; status = "okay"; - rave-sp { + mcu { compatible = "zii,rave-sp-rdu1"; current-speed = <38400>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts index aa91e5dde4b82c5422424b211c8ec9735184b859..21dd3f7abd488bd0d52b61e976afc659c878583d 100644 --- a/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts +++ b/arch/arm/boot/dts/imx51-zii-scu2-mezz.dts @@ -311,7 +311,7 @@ pinctrl-0 = <&pinctrl_uart3>; status = "okay"; - rave-sp { + mcu { compatible = "zii,rave-sp-mezz"; current-speed = <57600>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts index 875b10a7d6746b0a0fb8e90e8ade8879a509f3fa..9f857eb44bf722acef5be1c3e536213f0d8ea206 100644 --- a/arch/arm/boot/dts/imx51-zii-scu3-esb.dts +++ b/arch/arm/boot/dts/imx51-zii-scu3-esb.dts @@ -319,7 +319,7 @@ pinctrl-0 = <&pinctrl_uart3>; status = "okay"; - rave-sp { + mcu { compatible = "zii,rave-sp-esb"; current-speed = <57600>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx51.dtsi b/arch/arm/boot/dts/imx51.dtsi index 853707574d2e3e0e60294702d3b2369db265fbdc..ba92a3ea68728a1f32001ca75adafa65703ee2d3 100644 --- a/arch/arm/boot/dts/imx51.dtsi +++ b/arch/arm/boot/dts/imx51.dtsi @@ -124,6 +124,9 @@ iram: sram@1ffe0000 { compatible = "mmio-sram"; reg = <0x1ffe0000 0x20000>; + ranges = <0 0x1ffe0000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; }; gpu: gpu@30000000 { diff --git a/arch/arm/boot/dts/imx53-cx9020.dts b/arch/arm/boot/dts/imx53-cx9020.dts index cfb18849a92b4e249b1123cec4e295e5260d3185..055d23a9aee7c0f280c8bbac823294dcd54fcef8 100644 --- a/arch/arm/boot/dts/imx53-cx9020.dts +++ b/arch/arm/boot/dts/imx53-cx9020.dts @@ -86,27 +86,27 @@ leds { compatible = "gpio-leds"; - pwr-r { + led-pwr-r { gpios = <&gpio3 22 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - pwr-g { + led-pwr-g { gpios = <&gpio3 24 GPIO_ACTIVE_HIGH>; default-state = "on"; }; - pwr-b { + led-pwr-b { gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; default-state = "off"; }; - sd1-b { + led-sd1-b { linux,default-trigger = "mmc0"; gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; }; - sd2-b { + led-sd2-b { linux,default-trigger = "mmc1"; gpios = <&gpio3 17 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/imx53-m53evk.dts b/arch/arm/boot/dts/imx53-m53evk.dts index a1a6228d1aa66276923a83291d25c80389b733f6..2bd2432d317ff3459bb5bc0cc19a07e00c591d90 100644 --- a/arch/arm/boot/dts/imx53-m53evk.dts +++ b/arch/arm/boot/dts/imx53-m53evk.dts @@ -52,13 +52,13 @@ pinctrl-names = "default"; pinctrl-0 = <&led_pin_gpio>; - user1 { + led-user1 { label = "user1"; gpios = <&gpio2 8 0>; linux,default-trigger = "heartbeat"; }; - user2 { + led-user2 { label = "user2"; gpios = <&gpio2 9 0>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/imx53-m53menlo.dts b/arch/arm/boot/dts/imx53-m53menlo.dts index d5c68d1ea707c6610ff1ef2b1c3bb9883ad5e803..4d77b6077fc1bb6d2686de68e33a02463c33f841 100644 --- a/arch/arm/boot/dts/imx53-m53menlo.dts +++ b/arch/arm/boot/dts/imx53-m53menlo.dts @@ -34,19 +34,19 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led>; - user1 { + led-user1 { label = "TestLed601"; gpios = <&gpio6 1 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; }; - user2 { + led-user2 { label = "TestLed602"; gpios = <&gpio6 2 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; - eth { + led-eth { label = "EthLedYe"; gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; linux,default-trigger = "netdev"; diff --git a/arch/arm/boot/dts/imx53-ppd.dts b/arch/arm/boot/dts/imx53-ppd.dts index 37d0cffea99c56ec7e47bd817fe99eb366fc8375..70c4a4852256c4ef2321e25b878eb3b01e2780df 100644 --- a/arch/arm/boot/dts/imx53-ppd.dts +++ b/arch/arm/boot/dts/imx53-ppd.dts @@ -488,7 +488,7 @@ scl-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; status = "okay"; - i2c-switch@70 { + i2c-mux@70 { compatible = "nxp,pca9547"; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/imx53-sk-imx53.dts b/arch/arm/boot/dts/imx53-sk-imx53.dts new file mode 100644 index 0000000000000000000000000000000000000000..103e73176e47d643d77cb37c230261b2a0752d48 --- /dev/null +++ b/arch/arm/boot/dts/imx53-sk-imx53.dts @@ -0,0 +1,357 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright 2023 Linaro Ltd. + +/dts-v1/; + +#include "imx53.dtsi" + +/ { + model = "StarterKit SK-iMX53 Board"; + compatible = "starterkit,sk-imx53", "fsl,imx53"; + + aliases { + /* + * iMX RTC is not battery powered on this board. + * Use the i2c RTC as rtc0. + */ + rtc0 = &rtc; + rtc1 = &srtc; + }; + + chosen { + stdout-path = &uart1; + }; + + memory@70000000 { + device_type = "memory"; + /* v2 had only 256 MB, v3 has 512 MB */ + reg = <0x70000000 0x20000000>; + }; + + reg_usb1_vbus: regulator-usb-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 29 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_usb_otg_vbus: regulator-otg-vbus { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&gpio2 24 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio2 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&esdhc1 { + cd-gpios = <&gpio3 14 GPIO_ACTIVE_LOW>; + fsl,wp-controller; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_esdhc1>; + status = "okay"; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rmii"; + phy-handle = <&phy0>; + mac-address = [000000000000]; /* placeholder; will be overwritten by bootloader */ + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy0: ethernet-phy@0 { + reg = <0>; + reset-gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default", "gpio"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + sda-gpios = <&gpio4 13 GPIO_ACTIVE_HIGH>; + scl-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH>; + status = "okay"; + + tlv320aic23: codec@1a { + compatible = "ti,tlv320aic23"; + reg = <0x1a>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_codec>; + #sound-dai-cells = <0>; + }; + + rtc: rtc@68 { + compatible = "dallas,ds1338"; + reg = <0x68>; + }; +}; + +&iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX53_PAD_SD2_DATA3__AUDMUX_AUD4_TXC 0x1e4 + MX53_PAD_SD2_DATA2__AUDMUX_AUD4_TXD 0x1e4 + MX53_PAD_SD2_DATA1__AUDMUX_AUD4_TXFS 0x1e4 + MX53_PAD_SD2_DATA0__AUDMUX_AUD4_RXD 0x1e4 + >; + }; + + pinctrl_can1: can1grp { + fsl,pins = < + MX53_PAD_PATA_INTRQ__CAN1_TXCAN 0x1e4 + MX53_PAD_PATA_DIOR__CAN1_RXCAN 0x1e4 + >; + }; + + pinctrl_codec: codecgrp { + fsl,pins = < + MX53_PAD_GPIO_0__CCM_SSI_EXT1_CLK 0x1c4 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX53_PAD_EIM_D16__ECSPI1_SCLK 0x1e4 + MX53_PAD_EIM_D17__ECSPI1_MISO 0x1e4 + MX53_PAD_EIM_D18__ECSPI1_MOSI 0x1e4 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX53_PAD_CSI0_DAT9__ECSPI2_MOSI 0x1e4 + MX53_PAD_CSI0_DAT10__ECSPI2_MISO 0x1e4 + MX53_PAD_EIM_CS0__ECSPI2_SCLK 0x1e4 + >; + }; + + pinctrl_esdhc1: esdhc1grp { + fsl,pins = < + MX53_PAD_SD1_DATA0__ESDHC1_DAT0 0x1d5 + MX53_PAD_SD1_DATA1__ESDHC1_DAT1 0x1d5 + MX53_PAD_SD1_DATA2__ESDHC1_DAT2 0x1d5 + MX53_PAD_SD1_DATA3__ESDHC1_DAT3 0x1d5 + MX53_PAD_SD1_CMD__ESDHC1_CMD 0x1d5 + MX53_PAD_SD1_CLK__ESDHC1_CLK 0x1d5 + MX53_PAD_EIM_DA14__GPIO3_14 0x1f0 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + MX53_PAD_FEC_MDC__FEC_MDC 0x1e4 + MX53_PAD_FEC_MDIO__FEC_MDIO 0x1e4 + MX53_PAD_FEC_REF_CLK__FEC_TX_CLK 0x1e4 + MX53_PAD_FEC_RX_ER__FEC_RX_ER 0x1e4 + MX53_PAD_FEC_CRS_DV__FEC_RX_DV 0x1e4 + MX53_PAD_FEC_RXD1__FEC_RDATA_1 0x1e4 + MX53_PAD_FEC_RXD0__FEC_RDATA_0 0x1e4 + MX53_PAD_FEC_TX_EN__FEC_TX_EN 0x1c4 + MX53_PAD_FEC_TXD1__FEC_TDATA_1 0x1e4 + MX53_PAD_FEC_TXD0__FEC_TDATA_0 0x1e4 + MX53_PAD_GPIO_1__GPIO1_1 0x1c4 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX53_PAD_EIM_D21__I2C1_SCL 0x400001e4 + MX53_PAD_EIM_D28__I2C1_SDA 0x400001e4 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX53_PAD_KEY_ROW3__I2C2_SDA 0x400001e4 + MX53_PAD_EIM_EB2__I2C2_SCL 0x400001e4 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX53_PAD_KEY_ROW3__GPIO4_13 0x1e4 + MX53_PAD_EIM_EB2__GPIO2_30 0x1e4 + >; + }; + + pinctrl_nand: nandgrp { + fsl,pins = < + MX53_PAD_NANDF_WE_B__EMI_NANDF_WE_B 0x4 + MX53_PAD_NANDF_RE_B__EMI_NANDF_RE_B 0x4 + MX53_PAD_NANDF_CLE__EMI_NANDF_CLE 0x4 + MX53_PAD_NANDF_ALE__EMI_NANDF_ALE 0x4 + MX53_PAD_NANDF_WP_B__EMI_NANDF_WP_B 0xe0 + MX53_PAD_NANDF_RB0__EMI_NANDF_RB_0 0xe0 + MX53_PAD_NANDF_CS0__EMI_NANDF_CS_0 0x4 + MX53_PAD_NANDF_CS1__EMI_NANDF_CS_1 0x4 + MX53_PAD_NANDF_CS2__EMI_NANDF_CS_2 0x4 + MX53_PAD_NANDF_CS3__EMI_NANDF_CS_3 0x4 + MX53_PAD_EIM_DA0__EMI_NAND_WEIM_DA_0 0xa4 + MX53_PAD_EIM_DA1__EMI_NAND_WEIM_DA_1 0xa4 + MX53_PAD_EIM_DA2__EMI_NAND_WEIM_DA_2 0xa4 + MX53_PAD_EIM_DA3__EMI_NAND_WEIM_DA_3 0xa4 + MX53_PAD_EIM_DA4__EMI_NAND_WEIM_DA_4 0xa4 + MX53_PAD_EIM_DA5__EMI_NAND_WEIM_DA_5 0xa4 + MX53_PAD_EIM_DA6__EMI_NAND_WEIM_DA_6 0xa4 + MX53_PAD_EIM_DA7__EMI_NAND_WEIM_DA_7 0xa4 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX53_PAD_GPIO_9__PWM1_PWMO 0x5 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX53_PAD_PATA_DIOW__UART1_TXD_MUX 0x1e4 + MX53_PAD_PATA_DMACK__UART1_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX53_PAD_EIM_D24__UART3_TXD_MUX 0x1e4 + MX53_PAD_EIM_D25__UART3_RXD_MUX 0x1e4 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX53_PAD_KEY_COL0__UART4_TXD_MUX 0x1e4 + MX53_PAD_KEY_ROW0__UART4_RXD_MUX 0x1e4 + >; + }; +}; + +&nfc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_nand>; + nand-bus-width = <8>; + status = "okay"; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "boot"; + reg = <0x00000000 0x00100000>; + read-only; + }; + + partition@100000 { + label = "u-boot"; + reg = <0x00100000 0x00100000>; + read-only; + }; + + partition@200000 { + label = "u-boot-env"; + reg = <0x00200000 0x00100000>; + read-only; + }; + + partition@1000000 { + label = "kernel-safe"; + reg = <0x01000000 0x00a00000>; + read-only; + }; + + partition@1a00000 { + label = "kernel"; + reg = <0x01a00000 0x005e0000>; + }; + + partition@2000000 { + label = "ubifs"; + reg = <0x02000000 0x0e000000>; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&sata { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usb1_vbus>; + phy_type = "utmi"; + disable-over-current; + status = "okay"; +}; + +&usbotg { + dr_mode = "peripheral"; + disable-over-current; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx53-tx53.dtsi b/arch/arm/boot/dts/imx53-tx53.dtsi index 892dd1a4bac352f4f55517cf62a758c6e543e9ca..a439a47fb65ac66d02fa3bf02ab75cd93764154b 100644 --- a/arch/arm/boot/dts/imx53-tx53.dtsi +++ b/arch/arm/boot/dts/imx53-tx53.dtsi @@ -94,7 +94,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_stk5led>; - user { + led-user { label = "Heartbeat"; gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/imx53-usbarmory.dts b/arch/arm/boot/dts/imx53-usbarmory.dts index f34993a490ee86cbdbe7a9b8d2b4547b2057d036..acc44010d510695b28dc8e6599ba006856a89efb 100644 --- a/arch/arm/boot/dts/imx53-usbarmory.dts +++ b/arch/arm/boot/dts/imx53-usbarmory.dts @@ -67,7 +67,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led>; - user { + led-user { label = "LED"; gpios = <&gpio4 27 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/imx53.dtsi b/arch/arm/boot/dts/imx53.dtsi index 56b3c13f4eb7deabcdf566f4698da96cdfbcd394..17dc13719639a9ebd018b53d75c216547ccaa520 100644 --- a/arch/arm/boot/dts/imx53.dtsi +++ b/arch/arm/boot/dts/imx53.dtsi @@ -850,6 +850,9 @@ ocram: sram@f8000000 { compatible = "mmio-sram"; reg = <0xf8000000 0x20000>; + ranges = <0 0xf8000000 0x20000>; + #address-cells = <1>; + #size-cells = <1>; clocks = <&clks IMX5_CLK_OCRAM>; }; }; diff --git a/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi b/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi index 337db29b0010a9598dd0a45f3c270b32b5c4920d..37697fac9dea9e95c645804ccfc7092151069326 100644 --- a/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi +++ b/arch/arm/boot/dts/imx6dl-b1x5pv2.dtsi @@ -211,17 +211,17 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_q7_gpio1 &pinctrl_q7_gpio3 &pinctrl_q7_gpio5>; - alarm1 { + led-alarm1 { label = "alarm:red"; gpios = <&gpio1 8 GPIO_ACTIVE_HIGH>; }; - alarm2 { + led-alarm2 { label = "alarm:yellow"; gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; }; - alarm3 { + led-alarm3 { label = "alarm:blue"; gpios = <&gpio4 15 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/imx6dl-colibri-aster.dts b/arch/arm/boot/dts/imx6dl-colibri-aster.dts index a28e083f29d5db9ca1bb9c31fcb5d6ea8b2c4681..82a0d1a28d12f410f6d1cc03fd919a103b182f72 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-aster.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-aster.dts @@ -99,10 +99,12 @@ }; &usbh1 { + disable-over-current; status = "okay"; }; &usbotg { + disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts index a02981d4a3fce717dd059d720f4cf01f95486b32..f50a26dd34c031ebdd35ddeb58d77fa661e0d428 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-eval-v3.dts @@ -111,10 +111,12 @@ }; &usbh1 { + disable-over-current; status = "okay"; }; &usbotg { + disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6dl-colibri-iris.dts b/arch/arm/boot/dts/imx6dl-colibri-iris.dts index c5797ff35b71b1c8efb42943d7a02ad218fd5f7e..4303c88bb2a91d8aff1e7deb1731787c5efbf262 100644 --- a/arch/arm/boot/dts/imx6dl-colibri-iris.dts +++ b/arch/arm/boot/dts/imx6dl-colibri-iris.dts @@ -138,10 +138,12 @@ }; &usbh1 { + disable-over-current; status = "okay"; }; &usbotg { + disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6dl-riotboard.dts b/arch/arm/boot/dts/imx6dl-riotboard.dts index e7be05f205d32b6b3f6ac1c81858de4433384639..24c7f535f63bd94c9a54e6fa65fa39df1cbf187d 100644 --- a/arch/arm/boot/dts/imx6dl-riotboard.dts +++ b/arch/arm/boot/dts/imx6dl-riotboard.dts @@ -25,14 +25,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led>; - led0: user1 { + led0: led-user1 { label = "user1"; gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; default-state = "on"; linux,default-trigger = "heartbeat"; }; - led1: user2 { + led1: led-user2 { label = "user2"; gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; default-state = "off"; diff --git a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi index 52162e8c7274b4487073cc21d3fa9b9a21030d1f..aacbf317feea61aca221d7005519f278988b55a3 100644 --- a/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi +++ b/arch/arm/boot/dts/imx6dl-yapp4-common.dtsi @@ -274,7 +274,7 @@ #address-cells = <1>; #size-cells = <0>; - chan@0 { + led@0 { chan-name = "R"; led-cur = /bits/ 8 <0x20>; max-cur = /bits/ 8 <0x60>; @@ -282,7 +282,7 @@ color = ; }; - chan@1 { + led@1 { chan-name = "G"; led-cur = /bits/ 8 <0x20>; max-cur = /bits/ 8 <0x60>; @@ -290,7 +290,7 @@ color = ; }; - chan@2 { + led@2 { chan-name = "B"; led-cur = /bits/ 8 <0x20>; max-cur = /bits/ 8 <0x60>; diff --git a/arch/arm/boot/dts/imx6q-apalis-eval.dts b/arch/arm/boot/dts/imx6q-apalis-eval.dts index fa160a3898704d1e58db4aefb6a2d79212a55207..3fc079dfd61eed40ed9d13b8e13e922ffcf04ae0 100644 --- a/arch/arm/boot/dts/imx6q-apalis-eval.dts +++ b/arch/arm/boot/dts/imx6q-apalis-eval.dts @@ -147,11 +147,13 @@ }; &usbh1 { + disable-over-current; vbus-supply = <®_usb_host_vbus>; status = "okay"; }; &usbotg { + disable-over-current; vbus-supply = <®_usb_otg_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts index f9f7d99bd4db8516716423927e455daea8db315e..717decda0cebd5138a0febfed8e56c6a55fb67a3 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.2.dts @@ -202,11 +202,13 @@ }; &usbh1 { + disable-over-current; vbus-supply = <®_usb_host_vbus>; status = "okay"; }; &usbotg { + disable-over-current; vbus-supply = <®_usb_otg_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-apalis-ixora.dts b/arch/arm/boot/dts/imx6q-apalis-ixora.dts index ce39c6a3f64045c3aab5414faef2249e2682dba0..f338be4352779adf8a3a4428c9eab0003005a798 100644 --- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts +++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts @@ -151,11 +151,13 @@ }; &usbh1 { + disable-over-current; vbus-supply = <®_usb_host_vbus>; status = "okay"; }; &usbotg { + disable-over-current; vbus-supply = <®_usb_otg_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6q-gw5400-a.dts b/arch/arm/boot/dts/imx6q-gw5400-a.dts index e894faba571f964eb7608bd74f196c31f4f3b795..522a51042965ac9be87e2275b2dca0975525db41 100644 --- a/arch/arm/boot/dts/imx6q-gw5400-a.dts +++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts @@ -34,20 +34,20 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - led0: user1 { + led0: led-user1 { label = "user1"; gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 -> MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; - led1: user2 { + led1: led-user2 { label = "user2"; gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* 106 -> MX6_PANLEDR */ default-state = "off"; }; - led2: user3 { + led2: led-user3 { label = "user3"; gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* 111 -> MX6_LOCLED# */ default-state = "off"; diff --git a/arch/arm/boot/dts/imx6q-h100.dts b/arch/arm/boot/dts/imx6q-h100.dts index b8feadbff967dbd6a62778b60be894771f2da108..6406ade14f57b4b99b40a234976d4ff15fc5baa0 100644 --- a/arch/arm/boot/dts/imx6q-h100.dts +++ b/arch/arm/boot/dts/imx6q-h100.dts @@ -76,19 +76,19 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_h100_leds>; - led0: power { + led0: led-power { label = "power"; gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; default-state = "on"; }; - led1: stream { + led1: led-stream { label = "stream"; gpios = <&gpio2 29 GPIO_ACTIVE_LOW>; default-state = "off"; }; - led2: rec { + led2: led-rec { label = "rec"; gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; default-state = "off"; diff --git a/arch/arm/boot/dts/imx6q-kp.dtsi b/arch/arm/boot/dts/imx6q-kp.dtsi index 1ade0bff681d68fe6354ad14be378b49ca3c49ab..5e0ed556004058da72cd6f2931b540e65d09317c 100644 --- a/arch/arm/boot/dts/imx6q-kp.dtsi +++ b/arch/arm/boot/dts/imx6q-kp.dtsi @@ -66,14 +66,14 @@ leds { compatible = "gpio-leds"; - green { + led-green { label = "led1"; gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; linux,default-trigger = "gpio"; default-state = "off"; }; - red { + led-red { label = "led0"; gpios = <&gpio3 23 GPIO_ACTIVE_HIGH>; linux,default-trigger = "gpio"; diff --git a/arch/arm/boot/dts/imx6q-marsboard.dts b/arch/arm/boot/dts/imx6q-marsboard.dts index cc180100239427c8655014e120fe8ee730924e66..2c9961333b0a8656b648c7a848b6c20db61f790e 100644 --- a/arch/arm/boot/dts/imx6q-marsboard.dts +++ b/arch/arm/boot/dts/imx6q-marsboard.dts @@ -73,14 +73,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led>; - user1 { + led-user1 { label = "imx6:green:user1"; gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; default-state = "off"; linux,default-trigger = "heartbeat"; }; - user2 { + led-user2 { label = "imx6:green:user2"; gpios = <&gpio3 28 GPIO_ACTIVE_LOW>; default-state = "off"; diff --git a/arch/arm/boot/dts/imx6q-tbs2910.dts b/arch/arm/boot/dts/imx6q-tbs2910.dts index 8daef65d5bb3542a0d223d80a198dc26db2af336..2f576e2ce73f2e6be9d63c3fd61e113e344fee94 100644 --- a/arch/arm/boot/dts/imx6q-tbs2910.dts +++ b/arch/arm/boot/dts/imx6q-tbs2910.dts @@ -49,7 +49,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - blue { + led-blue { label = "blue_status_led"; gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; default-state = "keep"; diff --git a/arch/arm/boot/dts/imx6qdl-apalis.dtsi b/arch/arm/boot/dts/imx6qdl-apalis.dtsi index 7c17b91f09655837bf968af963a552ef840bf261..4cc965277c52199d665a7c7ea455b0d42cb92ea6 100644 --- a/arch/arm/boot/dts/imx6qdl-apalis.dtsi +++ b/arch/arm/boot/dts/imx6qdl-apalis.dtsi @@ -41,7 +41,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - wakeup { + key-wakeup { debounce-interval = <10>; gpios = <&gpio1 4 GPIO_ACTIVE_LOW>; label = "Wake-Up"; @@ -824,7 +824,6 @@ }; &usbotg { - disable-over-current; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg>; status = "disabled"; diff --git a/arch/arm/boot/dts/imx6qdl-colibri.dtsi b/arch/arm/boot/dts/imx6qdl-colibri.dtsi index d8f985f297e42f05ebf2798f15512e63c1943717..57099570750440ab0a62a03f02b50c87623950c7 100644 --- a/arch/arm/boot/dts/imx6qdl-colibri.dtsi +++ b/arch/arm/boot/dts/imx6qdl-colibri.dtsi @@ -36,9 +36,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_keys>; - wakeup { + key-wakeup { debounce-interval = <10>; - gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */ + gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */ label = "Wake-Up"; linux,code = ; wakeup-source; @@ -684,7 +684,6 @@ /* Colibri USBC */ &usbotg { - disable-over-current; dr_mode = "otg"; extcon = <0>, <&extcon_usbc_det>; status = "disabled"; diff --git a/arch/arm/boot/dts/imx6qdl-emcon.dtsi b/arch/arm/boot/dts/imx6qdl-emcon.dtsi index 7228b894a763f5be5820ab5233ad4c44893f82e2..ee2dd75cead6dbb6d3433dfebb477600c2463ca8 100644 --- a/arch/arm/boot/dts/imx6qdl-emcon.dtsi +++ b/arch/arm/boot/dts/imx6qdl-emcon.dtsi @@ -46,14 +46,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_som_leds>; - green { + led-green { label = "som:green"; gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; default-state = "on"; }; - red { + led-red { label = "som:red"; gpios = <&gpio3 1 GPIO_ACTIVE_LOW>; default-state = "keep"; diff --git a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi index 069c27fab432c445421e170d39eb236947757b2e..e75e1a5364b8544725ef4d57fbc178f310096cb8 100644 --- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi @@ -71,14 +71,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - led0: user1 { + led0: led-user1 { label = "user1"; gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; - led1: user2 { + led1: led-user2 { label = "user2"; gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ default-state = "off"; diff --git a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi index 728810b9d677da92f038dc582cfa32ca4386a9ab..47d9a8d08197df067490e3a12157d6bcb4119318 100644 --- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi @@ -80,20 +80,20 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - led0: user1 { + led0: led-user1 { label = "user1"; gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; - led1: user2 { + led1: led-user2 { label = "user2"; gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ default-state = "off"; }; - led2: user3 { + led2: led-user3 { label = "user3"; gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ default-state = "off"; diff --git a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi index 6c0c109046d80989c1a0da25978867787dbf6222..fb1d29abe0991644070e668e7336fbd490d69e79 100644 --- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi @@ -80,20 +80,20 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - led0: user1 { + led0: led-user1 { label = "user1"; gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; - led1: user2 { + led1: led-user2 { label = "user2"; gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ default-state = "off"; }; - led2: user3 { + led2: led-user3 { label = "user3"; gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ default-state = "off"; diff --git a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi index a9b04f9f1c2bc2ee7587caf86457d482b874a70a..4e20cb97058ebbbb1410f3eed36167a3afc751d9 100644 --- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi @@ -81,20 +81,20 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - led0: user1 { + led0: led-user1 { label = "user1"; gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; - led1: user2 { + led1: led-user2 { label = "user2"; gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ default-state = "off"; }; - led2: user3 { + led2: led-user3 { label = "user3"; gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ default-state = "off"; diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi index 435dec6338fe68f9d17aad3115c20eb099240bec..0fa4b8eeddee75870ccdf653d370ad33f8196dc1 100644 --- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi @@ -115,7 +115,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - led0: user1 { + led0: led-user1 { label = "user1"; gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; default-state = "on"; diff --git a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi index 2e61102ae6946593315767bda7b7ed1ae85f734c..77ae611b817a4c18dce02507e9569fa8223d836d 100644 --- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi @@ -72,20 +72,20 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - led0: user1 { + led0: led-user1 { label = "user1"; gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; - led1: user2 { + led1: led-user2 { label = "user2"; gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ default-state = "off"; }; - led2: user3 { + led2: led-user3 { label = "user3"; gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ default-state = "off"; diff --git a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi index 4662408b225a5bb8e9b350af5368d82b106109b7..7f16c602cc0757ab9a1cbd8f19f0d5ad29457495 100644 --- a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi @@ -113,14 +113,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - led0: user1 { + led0: led-user1 { label = "user1"; gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; - led1: user2 { + led1: led-user2 { label = "user2"; gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ default-state = "off"; diff --git a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi index 4bc4371e6bae56e02ee910b98f0f03656a3b4441..46cf4080fec384fc98413a48e59e3d52a1db6a62 100644 --- a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi @@ -139,20 +139,20 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - led0: user1 { + led0: led-user1 { label = "user1"; gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; - led1: user2 { + led1: led-user2 { label = "user2"; gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ default-state = "off"; }; - led2: user3 { + led2: led-user3 { label = "user3"; gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ default-state = "off"; @@ -632,7 +632,6 @@ &uart1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; rts-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi index 1fdb7ba630f1be20b4025d0ce802f52dd9274447..a74cde05015894c08543ee34eb380002f5355d6a 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5903.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5903.dtsi @@ -123,7 +123,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - led0: user1 { + led0: led-user1 { label = "user1"; gpios = <&gpio6 14 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ default-state = "off"; diff --git a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi index 612b6e068e282284dd9899fc47ebfefed96a8844..9fc79af2bc9aa18969a2bfe39369e7e83aca7875 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi @@ -120,20 +120,20 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - led0: user1 { + led0: led-user1 { label = "user1"; gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; - led1: user2 { + led1: led-user2 { label = "user2"; gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ default-state = "off"; }; - led2: user3 { + led2: led-user3 { label = "user3"; gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ default-state = "off"; diff --git a/arch/arm/boot/dts/imx6qdl-gw5907.dtsi b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi index fcd3bdfd6182724b2d081f56ca82e61f5586a6b8..955a51226eda7566e17bdb891bf964badea8000d 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5907.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi @@ -71,14 +71,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - led0: user1 { + led0: led-user1 { label = "user1"; gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; - led1: user2 { + led1: led-user2 { label = "user2"; gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ default-state = "off"; diff --git a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi index 6bb4855d13ce51ec179d82c622b1b24e05d15cfe..218d6e667ed24a4fb89553e31bc30ffb8d3ee50a 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi @@ -74,20 +74,20 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - led0: user1 { + led0: led-user1 { label = "user1"; gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; - led1: user2 { + led1: led-user2 { label = "user2"; gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ default-state = "off"; }; - led2: user3 { + led2: led-user3 { label = "user3"; gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ default-state = "off"; diff --git a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi index 0415bcb416400d9e81b6cbd788fcd22c4a3072a4..40e235e315cc45b9740a47dbb0f1c6b262fa9837 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5912.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi @@ -72,20 +72,20 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - led0: user1 { + led0: led-user1 { label = "user1"; gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; - led1: user2 { + led1: led-user2 { label = "user2"; gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ default-state = "off"; }; - led2: user3 { + led2: led-user3 { label = "user3"; gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */ default-state = "off"; diff --git a/arch/arm/boot/dts/imx6qdl-gw5913.dtsi b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi index 696427b487f0122a8e31af2c931dd4f32754e062..82f47c295b08559c69129fc073565fa6c24ca33f 100644 --- a/arch/arm/boot/dts/imx6qdl-gw5913.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi @@ -71,14 +71,14 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - led0: user1 { + led0: led-user1 { label = "user1"; gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */ default-state = "on"; linux,default-trigger = "heartbeat"; }; - led1: user2 { + led1: led-user2 { label = "user2"; gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */ default-state = "off"; diff --git a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi index a53a5d0766a5126c9de7f8512105fd04866e8b86..6d4eab1942b948321e6f1bac9dc287a73752e4d0 100644 --- a/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nit6xlite.dtsi @@ -85,31 +85,31 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_leds>; - j14-pin1 { + led-j14-pin1 { gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; retain-state-suspended; default-state = "off"; }; - j14-pin3 { + led-j14-pin3 { gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; retain-state-suspended; default-state = "off"; }; - j14-pins8-9 { + led-j14-pins8-9 { gpios = <&gpio3 29 GPIO_ACTIVE_LOW>; retain-state-suspended; default-state = "off"; }; - j46-pin2 { + led-j46-pin2 { gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; retain-state-suspended; default-state = "off"; }; - j46-pin3 { + led-j46-pin3 { gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; retain-state-suspended; default-state = "off"; diff --git a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi index 57c21a01f126d9d78714a4ab5b7fd0eaeca56d40..81a9a302aec1b531867f2f7674a2b3d79cab4414 100644 --- a/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi +++ b/arch/arm/boot/dts/imx6qdl-nitrogen6_max.dtsi @@ -181,13 +181,13 @@ leds { compatible = "gpio-leds"; - speaker-enable { + led-speaker-enable { gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; retain-state-suspended; default-state = "off"; }; - ttymxc4-rs232 { + led-ttymxc4-rs232 { gpios = <&gpio6 10 GPIO_ACTIVE_HIGH>; retain-state-suspended; default-state = "on"; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi index 120d6e997a4c5c55b505fc14a723db2aac066f27..1a599c294ab863e2c160f23a9e59da6b1ed79b66 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-mira.dtsi @@ -25,17 +25,17 @@ pinctrl-0 = <&pinctrl_gpioleds>; status = "disabled"; - red { + led-red { label = "phyboard-mira:red"; gpios = <&gpio5 22 GPIO_ACTIVE_HIGH>; }; - green { + led-green { label = "phyboard-mira:green"; gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; }; - blue { + led-blue { label = "phyboard-mira:blue"; gpios = <&gpio5 24 GPIO_ACTIVE_HIGH>; linux,default-trigger = "mmc0"; diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index 768bc0e3a2b3889d0eef18971eafc158147c37f5..80adb2a02cc94164d00491703d62d98f517d4d5d 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -47,12 +47,12 @@ pinctrl-0 = <&pinctrl_leds>; compatible = "gpio-leds"; - led_green: green { + led_green: led-green { label = "phyflex:green"; gpios = <&gpio1 30 0>; }; - led_red: red { + led_red: led-red { label = "phyflex:red"; gpios = <&gpio2 31 0>; }; diff --git a/arch/arm/boot/dts/imx6qdl-rex.dtsi b/arch/arm/boot/dts/imx6qdl-rex.dtsi index de514eb5aa99db4d47bf6d5082cedd3f760a367c..f804ff95a6ad6594942029950720da9286b7460c 100644 --- a/arch/arm/boot/dts/imx6qdl-rex.dtsi +++ b/arch/arm/boot/dts/imx6qdl-rex.dtsi @@ -55,7 +55,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led>; - led0: usr { + led0: led-usr { label = "usr"; gpios = <&gpio1 2 GPIO_ACTIVE_LOW>; default-state = "off"; diff --git a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi index eebcfe12142e2c7566c9f0eff58e9096bc5205aa..f79caa36f3d25e3cbac03cac74b3ebf2e20cc399 100644 --- a/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabreauto.dtsi @@ -21,7 +21,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - user { + led-user { label = "debug"; gpios = <&gpio5 15 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi index 09f4c2fa3ad6c61456e26c22103c5308c30b3e4f..53b080c97f2d990628515dba97f87c6f896f5262 100644 --- a/arch/arm/boot/dts/imx6qdl-sabresd.dtsi +++ b/arch/arm/boot/dts/imx6qdl-sabresd.dtsi @@ -130,7 +130,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; - red { + led-red { gpios = <&gpio1 2 0>; default-state = "on"; }; diff --git a/arch/arm/boot/dts/imx6qdl-ts7970.dtsi b/arch/arm/boot/dts/imx6qdl-ts7970.dtsi index c096d25a6f5b54f56289075d1041a3ad84aa804c..1e0a041e9f60a622d476b4a7d1d368c457703139 100644 --- a/arch/arm/boot/dts/imx6qdl-ts7970.dtsi +++ b/arch/arm/boot/dts/imx6qdl-ts7970.dtsi @@ -73,13 +73,13 @@ default-state = "off"; }; - en-usb-5v { + en-usb-5v-led { label = "en-usb-5v"; gpios = <&gpio2 22 GPIO_ACTIVE_HIGH>; default-state = "on"; }; - sel_dc_usb { + sel-dc-usb-led { label = "sel_dc_usb"; gpios = <&gpio5 17 GPIO_ACTIVE_HIGH>; default-state = "off"; diff --git a/arch/arm/boot/dts/imx6qdl-tx6.dtsi b/arch/arm/boot/dts/imx6qdl-tx6.dtsi index f41f86a76ea9571f3773d4a7915ae39482a60530..a197bac95cbace8b32c5bbbd298fb256302f24c7 100644 --- a/arch/arm/boot/dts/imx6qdl-tx6.dtsi +++ b/arch/arm/boot/dts/imx6qdl-tx6.dtsi @@ -92,7 +92,7 @@ leds { compatible = "gpio-leds"; - user_led: user { + user_led: led-user { label = "Heartbeat"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_user_led>; diff --git a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi index 525ff62b47f5ede8dde8ea367d47deb06f340b83..5bb47c79a4da23e96b634da82b7b75d11236e0b1 100644 --- a/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi +++ b/arch/arm/boot/dts/imx6qdl-zii-rdu2.dtsi @@ -277,7 +277,7 @@ pinctrl-0 = <&pinctrl_uart4>; status = "okay"; - rave-sp { + mcu { compatible = "zii,rave-sp-rdu2"; current-speed = <1000000>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx6qdl.dtsi b/arch/arm/boot/dts/imx6qdl.dtsi index ff1e0173b39be7d7986cc5a936a3d5513b6692b6..41e08fa23ccec5fb12de7129669274cc5d07cf49 100644 --- a/arch/arm/boot/dts/imx6qdl.dtsi +++ b/arch/arm/boot/dts/imx6qdl.dtsi @@ -157,7 +157,6 @@ <0 13 IRQ_TYPE_LEVEL_HIGH>, <0 13 IRQ_TYPE_LEVEL_HIGH>, <0 13 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; clocks = <&clks IMX6QDL_CLK_APBH_DMA>; @@ -1053,6 +1052,8 @@ <&clks IMX6QDL_CLK_ENET_REF>; clock-names = "ipg", "ahb", "ptp", "enet_out"; fsl,stop-mode = <&gpr 0x34 27>; + nvmem-cells = <&fec_mac_addr>; + nvmem-cell-names = "mac-address"; status = "disabled"; }; @@ -1186,6 +1187,10 @@ tempmon_temp_grade: temp-grade@20 { reg = <0x20 4>; }; + + fec_mac_addr: mac-addr@88 { + reg = <0x88 6>; + }; }; tzasc@21d0000 { /* TZASC1 */ diff --git a/arch/arm/boot/dts/imx6sl-evk.dts b/arch/arm/boot/dts/imx6sl-evk.dts index f16c830f1e9188d7877f937cfb71cdaeda099939..dc5d596c18db4788015c6c5b2d9bc5998e36da3a 100644 --- a/arch/arm/boot/dts/imx6sl-evk.dts +++ b/arch/arm/boot/dts/imx6sl-evk.dts @@ -33,7 +33,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led>; - user { + led-user { label = "debug"; gpios = <&gpio3 20 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/imx6sl-tolino-vision5.dts b/arch/arm/boot/dts/imx6sl-tolino-vision5.dts index ff6118df3946033fa6d03e3ecde5d1d6858b8de8..6bc342035e2b6f3bdd68ed42f7c4682dd470fd21 100644 --- a/arch/arm/boot/dts/imx6sl-tolino-vision5.dts +++ b/arch/arm/boot/dts/imx6sl-tolino-vision5.dts @@ -52,6 +52,13 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; + pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp { + fsl,pins = < + MX6SL_PAD_FEC_TXD0__GPIO4_IO24 0x17059 /* TP_INT */ + MX6SL_PAD_FEC_RXD1__GPIO4_IO18 0x10059 /* TP_RST */ + >; + }; + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < MX6SL_PAD_FEC_CRS_DV__GPIO4_IO25 0x17059 /* PWR_SW */ diff --git a/arch/arm/boot/dts/imx6sll-evk.dts b/arch/arm/boot/dts/imx6sll-evk.dts index 32b3d82fec53c37c703d0a5a9fafecf9a16437da..269092ac881c5c4e70e5fbbf8992ec7246ac4f6a 100644 --- a/arch/arm/boot/dts/imx6sll-evk.dts +++ b/arch/arm/boot/dts/imx6sll-evk.dts @@ -37,7 +37,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led>; - user { + led-user { label = "debug"; gpios = <&gpio2 4 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/imx6sll-kobo-librah2o.dts b/arch/arm/boot/dts/imx6sll-kobo-librah2o.dts index a8b0e88064d9f126ade062ba4e965e0b3657c543..7e4f38dd11e20b456c7685b70c48c74d2f3e1003 100644 --- a/arch/arm/boot/dts/imx6sll-kobo-librah2o.dts +++ b/arch/arm/boot/dts/imx6sll-kobo-librah2o.dts @@ -62,6 +62,13 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog>; + pinctrl_cyttsp5_gpio: cyttsp5-gpiogrp { + fsl,pins = < + MX6SLL_PAD_GPIO4_IO24__GPIO4_IO24 0x17059 /* TP_INT */ + MX6SLL_PAD_GPIO4_IO18__GPIO4_IO18 0x10059 /* TP_RST */ + >; + }; + pinctrl_gpio_keys: gpio-keysgrp { fsl,pins = < MX6SLL_PAD_GPIO4_IO25__GPIO4_IO25 0x17059 /* PWR_SW */ diff --git a/arch/arm/boot/dts/imx6sx-sabreauto.dts b/arch/arm/boot/dts/imx6sx-sabreauto.dts index 83ee97252ff11fd1266985713e67ea451512f1e1..b0c27b9b02446b400c7eebe69fb0b6350d61d84b 100644 --- a/arch/arm/boot/dts/imx6sx-sabreauto.dts +++ b/arch/arm/boot/dts/imx6sx-sabreauto.dts @@ -20,7 +20,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led>; - user { + led-user { label = "debug"; gpios = <&gpio1 24 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi index c84ea1fac5e98dd3206cbee2e02e80b3f84ded23..725d0b5cb55f6a4e3fd50bb1d7ca521dfb3039cb 100644 --- a/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi +++ b/arch/arm/boot/dts/imx6sx-udoo-neo.dtsi @@ -15,14 +15,14 @@ leds { compatible = "gpio-leds"; - red { + led-red { label = "udoo-neo:red:mmc"; gpios = <&gpio6 0 GPIO_ACTIVE_HIGH>; default-state = "off"; linux,default-trigger = "mmc0"; }; - orange { + led-orange { label = "udoo-neo:orange:user"; gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; default-state = "keep"; diff --git a/arch/arm/boot/dts/imx6sx.dtsi b/arch/arm/boot/dts/imx6sx.dtsi index 80f5efd65c2faa5c20a63a1897ec8908973fa547..93ac2380ca1ec6445f85b0b6bf215d57393971a6 100644 --- a/arch/arm/boot/dts/imx6sx.dtsi +++ b/arch/arm/boot/dts/imx6sx.dtsi @@ -216,7 +216,6 @@ , , ; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; clocks = <&clks IMX6SX_CLK_APBH_DMA>; diff --git a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi index c83e64a62d8a8dce9268c2d6aa7e6e9d83eb3606..7275a13664135db8f7e1896ad0245c1156fc3397 100644 --- a/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi +++ b/arch/arm/boot/dts/imx6ul-14x14-evk.dtsi @@ -2,6 +2,8 @@ // // Copyright (C) 2015 Freescale Semiconductor, Inc. +#include + / { chosen { stdout-path = &uart1; @@ -170,7 +172,7 @@ port { parallel_from_ov5640: endpoint { remote-endpoint = <&ov5640_to_parallel>; - bus-type = <5>; /* Parallel bus */ + bus-type = ; }; }; }; diff --git a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi index 5168ed0ffec375f52925b3a3b3c71b5304b879d8..a3ea1b20846253b8c4a5dc3a0ff0d505c24be3ff 100644 --- a/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi +++ b/arch/arm/boot/dts/imx6ul-phytec-phycore-som.dtsi @@ -30,7 +30,7 @@ pinctrl-0 = <&pinctrl_gpioleds_som>; compatible = "gpio-leds"; - phycore-green { + led-phycore-green { gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; }; diff --git a/arch/arm/boot/dts/imx6ul-pico-dwarf.dts b/arch/arm/boot/dts/imx6ul-pico-dwarf.dts index 162dc259edc8c5cb0c14b5c2b7dd9b948c861b61..5a74c7f68eb62dbf03b1af91a3b83241b5137717 100644 --- a/arch/arm/boot/dts/imx6ul-pico-dwarf.dts +++ b/arch/arm/boot/dts/imx6ul-pico-dwarf.dts @@ -32,7 +32,7 @@ }; &i2c2 { - clock_frequency = <100000>; + clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; diff --git a/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi b/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi index eca94ed6451b009d86e747d427cf2735692bbd43..57e647fc3237426c9fddacdf24b1ad58d6da2419 100644 --- a/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi +++ b/arch/arm/boot/dts/imx6ul-tqma6ul-common.dtsi @@ -116,8 +116,8 @@ }; }; - jc42_1a: eeprom-temperature-sensor@1a { - compatible = "nxp,se97", "jedec,jc-42.4-temp"; + jc42_1a: eeprom-temperature@1a { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; reg = <0x1a>; }; diff --git a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi index 15ee0275feaffd89920809d051a837d3a623afab..70cef5e817bd107f38d0b367fb1c99c28265ce32 100644 --- a/arch/arm/boot/dts/imx6ul-tx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul-tx6ul.dtsi @@ -131,7 +131,7 @@ leds { compatible = "gpio-leds"; - user_led: user { + user_led: led-user { label = "Heartbeat"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_led>; diff --git a/arch/arm/boot/dts/imx6ul.dtsi b/arch/arm/boot/dts/imx6ul.dtsi index 2b5996395701a07b12a13b1294eb7d782d9ef25a..f0a9139748b81eef471cc1bcfaddf6778c3f9980 100644 --- a/arch/arm/boot/dts/imx6ul.dtsi +++ b/arch/arm/boot/dts/imx6ul.dtsi @@ -171,7 +171,6 @@ <0 13 IRQ_TYPE_LEVEL_HIGH>, <0 13 IRQ_TYPE_LEVEL_HIGH>, <0 13 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; clocks = <&clks IMX6UL_CLK_APBHDMA>; diff --git a/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi index c9133ba2d705041d6edaad8cdfd54878f0327dc1..de4dc7c1a03aee71800eb509201bdd57af515205 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-aster.dtsi @@ -130,11 +130,13 @@ }; &usbotg1 { + disable-over-current; vbus-supply = <®_usbh_vbus>; status = "okay"; }; &usbotg2 { + disable-over-current; vbus-supply = <®_usbh_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi index e29907428c20f300a7be847a1a77b0be09f72494..692ef26fbab30724b5dc0f6aefd39a6109d11439 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-eval-v3.dtsi @@ -106,11 +106,13 @@ }; &usbotg1 { + disable-over-current; vbus-supply = <®_usbh_vbus>; status = "okay"; }; &usbotg2 { + disable-over-current; vbus-supply = <®_usbh_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi b/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi index 166a0aefc86986cb7d5ef25d4c4bce9671b44a71..f52f8b5ad8a6ee73f2d0ce1f1d2183893e8f7179 100644 --- a/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri-iris.dtsi @@ -117,11 +117,13 @@ }; &usbotg1 { + disable-over-current; vbus-supply = <®_usbh_vbus>; status = "okay"; }; &usbotg2 { + disable-over-current; vbus-supply = <®_usbh_vbus>; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx6ull-colibri.dtsi b/arch/arm/boot/dts/imx6ull-colibri.dtsi index 336ab2e0534c0e05c60fe42f1e627514711b8735..bf64ba84b358b59239d491fe2fd49fae0ffe7c03 100644 --- a/arch/arm/boot/dts/imx6ull-colibri.dtsi +++ b/arch/arm/boot/dts/imx6ull-colibri.dtsi @@ -51,9 +51,9 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_snvs_gpiokeys>; - wakeup { + key-wakeup { debounce-interval = <10>; - gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>; /* SODIMM 45 */ + gpios = <&gpio5 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */ label = "Wake-Up"; linux,code = ; wakeup-source; diff --git a/arch/arm/boot/dts/imx6ull-dhcom-drc02.dts b/arch/arm/boot/dts/imx6ull-dhcom-drc02.dts new file mode 100644 index 0000000000000000000000000000000000000000..b539975a872cdb0932b61d6bfc4bc9d855db2ecc --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-dhcom-drc02.dts @@ -0,0 +1,99 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2023 DH electronics GmbH + * + * DHCOM iMX6ULL variant: + * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-SD-RTC-ADC-I-01D2 + * DHCOR PCB number: 578-200 or newer + * DHCOM PCB number: 579-200 or newer + * DRC02 PCB number: 568-100 or newer (2nd ethernet by SoM) + */ +/dts-v1/; + +#include "imx6ull-dhcom-som.dtsi" +#include "imx6ull-dhcom-som-cfg-sdcard.dtsi" + +/ { + model = "DH electronics i.MX6ULL DHCOM on DRC02"; + compatible = "dh,imx6ull-dhcom-drc02", "dh,imx6ull-dhcom-som", + "dh,imx6ull-dhcor-som", "fsl,imx6ull"; +}; + +/* + * The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins. + * Therefore the UART RTS/CTS must be output on other DHCOM pins, see uart1 + * node below. + */ +&can2 { + status = "okay"; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "DRC02-In2", + "", "", "", "", + "", "", "DHCOM-I", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "DRC02-HW0", "DRC02-HW1", "DHCOM-M", + "DRC02-HW2", "DHCOM-U", "DHCOM-T", "DHCOM-S", + "DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O", + "DHCOM-N", "", "", ""; + /* + * NOTE: On DRC02, the RS485_RX_En is controlled by a separate + * GPIO line, however the i.MX6ULL UART driver assumes RX happens + * during TX anyway and that it only controls drive enable DE + * line. Hence, the RX is always enabled here. + */ + rs485-rx-en-hog { + gpio-hog; + gpios = <25 0>; /* GPIO Q */ + line-name = "rs485-rx-en"; + output-low; + }; +}; + +&gpio5 { + gpio-line-names = + "DHCOM-A", "DHCOM-B", "DHCOM-C", "DRC02-Out2", + "DHCOM-E", "", "", "DRC02-Out1", + "DRC02-In1", "DHCOM-H", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +/* DHCOM I2C2 */ +&i2c1 { + eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + pagesize = <16>; + }; +}; + +&uart1 { + /delete-property/ uart-has-rtscts; + rts-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */ + cts-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; /* GPIO M */ +}; + +/* Use UART as RS485 */ +&uart2 { + /delete-property/ uart-has-rtscts; + linux,rs485-enabled-at-boot-time; + rts-gpios = <&gpio4 26 GPIO_ACTIVE_HIGH>; /* GPIO P */ +}; diff --git a/arch/arm/boot/dts/imx6ull-dhcom-pdk2.dts b/arch/arm/boot/dts/imx6ull-dhcom-pdk2.dts new file mode 100644 index 0000000000000000000000000000000000000000..b29713831a74489e8cc0e651c18a40d85f9f9113 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-dhcom-pdk2.dts @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2023 DH electronics GmbH + * + * DHCOM iMX6ULL variant: + * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-RTC-WBT-ADC-I-01D2 + * DHCOR PCB number: 578-200 or newer + * DHCOM PCB number: 579-200 or newer + * PDK2 PCB number: 516-400 or newer + */ +/dts-v1/; + +#include "imx6ull-dhcom-som.dtsi" + +/ { + model = "DH electronics i.MX6ULL DHCOM on Premium Developer Kit (2)"; + compatible = "dh,imx6ull-dhcom-pdk2", "dh,imx6ull-dhcom-som", + "dh,imx6ull-dhcor-som", "fsl,imx6ull"; + + clk_ext_audio_codec: clock-codec { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + display_bl: display-bl { + compatible = "pwm-backlight"; + brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; + default-brightness-level = <8>; + enable-gpios = <&gpio5 8 GPIO_ACTIVE_HIGH>; /* GPIO G */ + power-supply = <®_panel_3v3>; + pwms = <&pwm1 0 50000 PWM_POLARITY_INVERTED>; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-0 { + gpios = <&gpio5 0 GPIO_ACTIVE_LOW>; /* GPIO A */ + label = "TA1-GPIO-A"; + linux,code = ; + wakeup-source; + }; + + button-1 { + gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; /* GPIO B */ + label = "TA2-GPIO-B"; + linux,code = ; + wakeup-source; + }; + + button-2 { + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; /* GPIO C */ + label = "TA3-GPIO-C"; + linux,code = ; + wakeup-source; + }; + + button-3 { + gpios = <&gpio5 3 GPIO_ACTIVE_LOW>; /* GPIO D */ + label = "TA4-GPIO-D"; + linux,code = ; + wakeup-source; + }; + }; + + led: led { + compatible = "gpio-leds"; + + /* + * Disable PDK2 LED5, because GPIO E is + * already used as touch interrupt. + */ + led-0 { + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <5>; /* PDK2 LED5 */ + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; /* GPIO E */ + status = "disabled"; + }; + + led-1 { + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <6>; /* PDK2 LED6 */ + gpios = <&gpio5 7 GPIO_ACTIVE_HIGH>; /* GPIO F */ + }; + + /* + * Disable PDK2 LED7, because GPIO H is + * already used for WiFi pin WL_REG_ON. + */ + led-2 { + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <7>; /* PDK2 LED7 */ + gpios = <&gpio5 9 GPIO_ACTIVE_HIGH>; /* GPIO H */ + status = "disabled"; + }; + + /* + * Disable PDK2 LED8, because GPIO I is + * already used for BT pin BT_REG_ON. + */ + led-3 { + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + function-enumerator = <8>; /* PDK2 LED8 */ + gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */ + status = "disabled"; + }; + }; + + panel { + compatible = "edt,etm0700g0edh6"; + backlight = <&display_bl>; + power-supply = <®_panel_3v3>; + + port { + lcd_panel_in: endpoint { + remote-endpoint = <&lcd_display_out>; + }; + }; + }; + + /* Filtered supply voltage */ + reg_pdk2_24v: regulator-pdk2-24v { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <24000000>; + regulator-min-microvolt = <24000000>; + regulator-name = "24V_PDK2"; + }; + + /* PDK2 U35 */ + reg_pdk2_3v3: regulator-pdk2-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "3V3_PDK2"; + vin-supply = <®_pdk2_24v>; + }; + + /* 560-200 U1 */ + reg_panel_3v3: regulator-panel-3v3 { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "3V3_PANEL"; + vin-supply = <®_pdk2_24v>; + }; + + sound { + compatible = "simple-audio-card"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,format = "i2s"; + simple-audio-card,frame-master = <&dailink_master>; + simple-audio-card,name = "sgtl5000"; + simple-audio-card,routing = + "MIC_IN", "Mic Jack", + "Mic Jack", "Mic Bias", + "LINE_IN", "Line In Jack", + "Headphone Jack", "HP_OUT"; + simple-audio-card,widgets = + "Microphone", "Mic Jack", + "Line", "Line In Jack", + "Headphone", "Headphone Jack"; + + simple-audio-card,cpu { + sound-dai = <&sai2>; + }; + + dailink_master: simple-audio-card,codec { + clocks = <&clk_ext_audio_codec>; + sound-dai = <&sgtl5000>; + }; + }; +}; + +/* DHCOM I2C1 */ +&i2c2 { + sgtl5000: audio-codec@a { + compatible = "fsl,sgtl5000"; + reg = <0x0a>; + #sound-dai-cells = <0>; + clocks = <&clk_ext_audio_codec>; + VDDA-supply = <®_pdk2_3v3>; + VDDIO-supply = <®_pdk2_3v3>; + }; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + interrupt-parent = <&gpio5>; + interrupts = <4 IRQ_TYPE_EDGE_FALLING>; /* GPIO E */ + power-supply = <®_panel_3v3>; + }; +}; + +&lcdif { + status = "okay"; + + port { + lcd_display_out: endpoint { + remote-endpoint = <&lcd_panel_in>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&sai2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/imx6ull-dhcom-picoitx.dts b/arch/arm/boot/dts/imx6ull-dhcom-picoitx.dts new file mode 100644 index 0000000000000000000000000000000000000000..e4cc2223583aa5b6c8adf7c88e177a56446d9e4b --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-dhcom-picoitx.dts @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2023 DH electronics GmbH + * + * DHCOM iMX6ULL variant: + * DHCM-iMX6ULL-C080-R051-F0409-SPI-E2-CAN2-SD-RTC-ADC-I-01D2 + * DHCOR PCB number: 578-200 or newer + * DHCOM PCB number: 579-200 or newer + * PicoITX PCB number: 487-600 or newer + */ +/dts-v1/; + +#include "imx6ull-dhcom-som.dtsi" +#include "imx6ull-dhcom-som-cfg-sdcard.dtsi" + +/ { + model = "DH electronics i.MX6ULL DHCOM on PicoITX"; + compatible = "dh,imx6ull-dhcom-picoitx", "dh,imx6ull-dhcom-som", + "dh,imx6ull-dhcor-som", "fsl,imx6ull"; + + led { + compatible = "gpio-leds"; + + led-0 { + color = ; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&gpio4 8 GPIO_ACTIVE_HIGH>; /* GPIO I */ + }; + }; +}; + +&fec1 { + phy-handle = <&mdio1_phy0>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + mdio1_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */ + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + clock-names = "rmii-ref"; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_fec1_phy &pinctrl_snvs_fec1_phy>; + pinctrl-names = "default"; + reset-assert-us = <500>; + reset-deassert-us = <500>; + reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + smsc,disable-energy-detect; /* Make plugin detection reliable */ + }; + }; +}; + +&fec2 { + status = "disabled"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "PicoITX-HW2", "PicoITX-HW1", "DHCOM-M", + "PicoITX-HW0", "DHCOM-U", "DHCOM-T", "DHCOM-S", + "DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O", + "DHCOM-N", "", "", ""; +}; + +&gpio5 { + gpio-line-names = + "DHCOM-A", "DHCOM-B", "PicoITX-In2", "PicoITX-Out2", + "PicoITX-In1", "", "", "PicoITX-Out1", + "DHCOM-G", "DHCOM-H", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; +}; + +&iomuxc { + pinctrl_fec1: fec1-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET1_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET1_MDIO 0x1b0b0 + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-dhcom-som-cfg-sdcard.dtsi b/arch/arm/boot/dts/imx6ull-dhcom-som-cfg-sdcard.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..040421f9c9700d66a9c94d906bbc95836ab38289 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-dhcom-som-cfg-sdcard.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2023 DH electronics GmbH + */ + +/* + * Special SoM configuration: SD card + * + * Enabled: Micro SD card on module or + * external SD card via DHCOM depends on hardware variant + * GPIO H and GPIO I will be available + * DHCOM UART2 will be available + * Disabled: WiFi and BT + */ + +/* + * To use usdhc1 as SD card, the WiFi node must be deleted. + * BT is also not available, so remove BT from the UART node. + */ +/delete-node/ &brcmf; +/delete-node/ &bluetooth; + +/ { + aliases { + mmc1 = &usdhc1; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart5; + serial5 = &uart6; + }; + + reg_sd1_vmmc: regulator-sd1-vmmc { + compatible = "regulator-fixed"; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + }; +}; + +/* Micro SD card on module or external SD card via DHCOM */ +&usdhc1 { + /delete-property/ #address-cells; + /delete-property/ #size-cells; + /delete-property/ keep-power-in-suspend; + /delete-property/ mmc-pwrseq; + /delete-property/ non-removable; + /delete-property/ wakeup-source; + cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; + no-1-8-v; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + vmmc-supply = <®_sd1_vmmc>; + status = "okay"; +}; + +&iomuxc { + pinctrl_usdhc1: usdhc1-grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x120b0 /* SD1 CD */ + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhz-grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x120b0 /* SD1 CD */ + + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhz-grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 + MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x120b0 /* SD1 CD */ + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-dhcom-som.dtsi b/arch/arm/boot/dts/imx6ull-dhcom-som.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..17837663c0b0d5903f5320390b6b7b5ee961df70 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-dhcom-som.dtsi @@ -0,0 +1,633 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2023 DH electronics GmbH + */ + +#include "imx6ull-dhcor-som.dtsi" + +/ { + aliases { + /delete-property/ mmc0; /* Avoid double definitions */ + /delete-property/ mmc1; + /delete-property/ spi2; + /delete-property/ spi3; + i2c0 = &i2c2; + i2c1 = &i2c1; + mmc2 = &usdhc2; + rtc0 = &rtc_i2c; + rtc1 = &snvs_rtc; + serial0 = &uart1; + serial1 = &uart6; /* DHCOM UART2, special hardware required */ + serial2 = &uart3; + serial3 = &uart2; /* Use BT UART always as ttymxc3 */ + serial4 = &uart4; + serial5 = &uart5; + spi0 = &ecspi1; + spi1 = &ecspi4; /* DHCOM SPI2, special hardware required */ + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + reg_ext_3v3_ref: regulator-ext-3v3-ref { + compatible = "regulator-fixed"; + regulator-always-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VCC_3V3_REF"; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1-vbus { + compatible = "regulator-fixed"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb-otg1-vbus"; + }; + + reg_usb_otg2_vbus: regulator-usb-otg2-vbus { + compatible = "regulator-fixed"; + gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb-otg2-vbus"; + }; + + /* SoM with WiFi/BT: WiFi pin WL_REG_ON is connected to a DHCOM GPIO */ + /omit-if-no-ref/ usdhc1_pwrseq: usdhc1-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; /* GPIO H */ + }; +}; + +/* SoM with WiFi/BT: BT pin BT_REG_ON is connected to a DHCOM GPIO */ +&bluetooth { + shutdown-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; /* GPIO I */ +}; + +&can1 { + pinctrl-0 = <&pinctrl_flexcan1>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* + * The signals for CAN2 TX and RX are routed to the DHCOM UART1 RTS/CTS pins. + * Only if this pins are used as CAN interface enable it on board layer. + */ +&can2 { + pinctrl-0 = <&pinctrl_flexcan2>; + pinctrl-names = "default"; +}; + +/* DHCOM SPI1 */ +&ecspi1 { + cs-gpios = <&gpio3 26 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi1>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* + * DHCOM SPI2 + * Special hardware required that uses the pins of FEC2. Therefore this SPI + * interface can only be used if FEC2 is disabled. + */ +&ecspi4 { + cs-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; + pinctrl-0 = <&pinctrl_ecspi4>; + pinctrl-names = "default"; +}; + +/* DHCOM ETH1 */ +&fec1 { + phy-handle = <&mdio2_phy0>; + phy-mode = "rmii"; + pinctrl-0 = <&pinctrl_fec1>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* DHCOM ETH2 */ +&fec2 { + phy-handle = <&mdio2_phy1>; + phy-mode = "rmii"; + pinctrl-0 = <&pinctrl_fec2>; + pinctrl-names = "default"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + mdio2_phy0: ethernet-phy@0 { + compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */ + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + clock-names = "rmii-ref"; + clocks = <&clks IMX6UL_CLK_ENET_REF>; + interrupt-parent = <&gpio5>; + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_fec1_phy &pinctrl_snvs_fec1_phy>; + pinctrl-names = "default"; + reset-assert-us = <500>; + reset-deassert-us = <500>; + reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + smsc,disable-energy-detect; /* Make plugin detection reliable */ + }; + + mdio2_phy1: ethernet-phy@1 { + compatible = "ethernet-phy-id0007.c0f0", /* SMSC LAN8710Ai */ + "ethernet-phy-ieee802.3-c22"; + reg = <1>; + clock-names = "rmii-ref"; + clocks = <&clks IMX6UL_CLK_ENET2_REF>; + interrupt-parent = <&gpio5>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; + pinctrl-0 = <&pinctrl_fec2_phy &pinctrl_snvs_fec2_phy>; + pinctrl-names = "default"; + reset-assert-us = <500>; + reset-deassert-us = <500>; + reset-gpios = <&gpio3 24 GPIO_ACTIVE_LOW>; + smsc,disable-energy-detect; /* Make plugin detection reliable */ + }; + }; +}; + +&gpio1 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "DHCOM-INT", + "", "", "", "", + "", "", "DHCOM-I", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; + pinctrl-0 = <&pinctrl_spi1_switch + &pinctrl_dhcom_i &pinctrl_dhcom_int>; + pinctrl-names = "default"; +}; + +&gpio4 { + gpio-line-names = + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "DHCOM-L", "DHCOM-K", "DHCOM-M", + "DHCOM-J", "DHCOM-U", "DHCOM-T", "DHCOM-S", + "DHCOM-R", "DHCOM-Q", "DHCOM-P", "DHCOM-O", + "DHCOM-N", "", "", ""; + pinctrl-0 = <&pinctrl_dhcom_j &pinctrl_dhcom_k + &pinctrl_dhcom_l &pinctrl_dhcom_m + &pinctrl_dhcom_n &pinctrl_dhcom_o + &pinctrl_dhcom_p &pinctrl_dhcom_q + &pinctrl_dhcom_r &pinctrl_dhcom_s + &pinctrl_dhcom_t &pinctrl_dhcom_u>; + pinctrl-names = "default"; +}; + +&gpio5 { + gpio-line-names = + "DHCOM-A", "DHCOM-B", "DHCOM-C", "DHCOM-D", + "DHCOM-E", "", "", "DHCOM-F", + "DHCOM-G", "DHCOM-H", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", "", + "", "", "", ""; + pinctrl-0 = <&pinctrl_snvs_dhcom_a &pinctrl_snvs_dhcom_b + &pinctrl_snvs_dhcom_c &pinctrl_snvs_dhcom_d + &pinctrl_snvs_dhcom_e &pinctrl_snvs_dhcom_f + &pinctrl_snvs_dhcom_g &pinctrl_snvs_dhcom_h>; + pinctrl-names = "default"; +}; + +/* DHCOM I2C2 */ +&i2c1 { + rtc_i2c: rtc@32 { + compatible = "microcrystal,rv8803"; + reg = <0x32>; + }; + + /* Microchip 24AA025E48T-I/OT containing MAC for DHCOM ETH1 */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + }; + + /* TI ADC101C027 */ + adc@51 { + compatible = "ti,adc101c"; + reg = <0x51>; + vref-supply = <®_ext_3v3_ref>; + }; + + /* TI ADC101C027 */ + adc@52 { + compatible = "ti,adc101c"; + reg = <0x52>; + vref-supply = <®_ext_3v3_ref>; + }; + + /* Microchip 24AA025E48T-I/OT containing MAC for DHCOM ETH2 */ + eeprom@53 { + compatible = "atmel,24c02"; + reg = <0x53>; + pagesize = <16>; + }; +}; + +/* DHCOM I2C1 */ +&i2c2 { + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio1 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&lcdif { + pinctrl-0 = <&pinctrl_lcdif>; + pinctrl-names = "default"; +}; + +&pwm1 { + pinctrl-0 = <&pinctrl_pwm1>; + pinctrl-names = "default"; +}; + +&sai2 { + assigned-clock-rates = <320000000>; + assigned-clocks = <&clks IMX6UL_CLK_PLL3_PFD2>; + pinctrl-0 = <&pinctrl_sai2>; + pinctrl-names = "default"; +}; + +&tsc { + measure-delay-time = <0xffff>; + pinctrl-0 = <&pinctrl_tsc>; + pinctrl-names = "default"; + pre-charge-time = <0xfff>; + touchscreen-average-samples = <32>; + xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; +}; + +/* DHCOM UART1 */ +&uart1 { + pinctrl-0 = <&pinctrl_uart1>; + pinctrl-names = "default"; + status = "okay"; +}; + +/* + * DHCOM UART2 (alternative) + * Special hardware required that uses DHCOM GPIO pins for DHCOM UART2. + * Therefore this UART interface can only be used if DHCOM GPIOs J/K/L/M are + * removed from GPIO hog muxing. + */ +&uart6 { + pinctrl-0 = <&pinctrl_uart6>; + pinctrl-names = "default"; + uart-has-rtscts; +}; + +&usbotg1 { + adp-disable; + disable-over-current; + dr_mode = "otg"; + hnp-disable; + pinctrl-0 = <&pinctrl_usbotg1>; + pinctrl-names = "default"; + srp-disable; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; /* Overcurrent pin is used for TSC */ + dr_mode = "host"; + pinctrl-0 = <&pinctrl_usbotg2>; + pinctrl-names = "default"; + tpl-support; + vbus-supply = <®_usb_otg2_vbus>; + status = "okay"; +}; + +&usbphy1 { + fsl,tx-d-cal = <106>; +}; + +&usbphy2 { + fsl,tx-d-cal = <106>; +}; + +/* WiFi on LGA */ +&usdhc1 { + mmc-pwrseq = <&usdhc1_pwrseq>; +}; + +/* eMMC on module */ +&usdhc2 { + bus-width = <8>; + no-1-8-v; + non-removable; + pinctrl-0 = <&pinctrl_usdhc2>; + pinctrl-names = "default"; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vcc_3v3>; + status = "okay"; +}; + +&iomuxc { + /* DHCOM GPIOs I..U + INT_HIGHEST_PRIORITY */ + pinctrl_dhcom_i: dhcom-i-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_j: dhcom-j-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_k: dhcom-k-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_l: dhcom-l-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_m: dhcom-m-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_n: dhcom-n-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_o: dhcom-o-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_p: dhcom-p-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_q: dhcom-q-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_r: dhcom-r-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_s: dhcom-s-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_t: dhcom-t-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_u: dhcom-u-grp { + fsl,pins = ; + }; + + pinctrl_dhcom_int: dhcom-int-grp { + fsl,pins = ; + }; + + pinctrl_ecspi1: ecspi1-grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA23__ECSPI1_MISO 0x100b1 + MX6UL_PAD_LCD_DATA22__ECSPI1_MOSI 0x100b1 + MX6UL_PAD_LCD_DATA20__ECSPI1_SCLK 0x100b1 + MX6UL_PAD_LCD_DATA21__GPIO3_IO26 0x1b0b0 /* SS0 */ + >; + }; + + pinctrl_ecspi4: ecspi4-grp { + fsl,pins = < + MX6UL_PAD_ENET2_TX_CLK__ECSPI4_MISO 0x100b1 + MX6UL_PAD_ENET2_TX_EN__ECSPI4_MOSI 0x100b1 + MX6UL_PAD_ENET2_TX_DATA1__ECSPI4_SCLK 0x100b1 + MX6UL_PAD_ENET2_RX_ER__GPIO2_IO15 0x1b0b0 /* SS0 */ + >; + }; + + pinctrl_fec1: fec1-grp { + fsl,pins = < + /* FEC1 uses MDIO bus from FEC2 */ + MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 + MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 + MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 + MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b010 + MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b010 + MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b010 + MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b010 + >; + }; + + pinctrl_fec1_phy: fec1-phy-grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA18__GPIO3_IO23 0xb0 /* SMSC PHY reset */ + >; + }; + + pinctrl_fec2: fec2-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 + MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 + MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 + MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 + MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 + MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b010 + MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b010 + MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b010 + MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b010 + >; + }; + + pinctrl_fec2_phy: fec2-phy-grp { + fsl,pins = < + MX6UL_PAD_LCD_DATA19__GPIO3_IO24 0xb0 /* SMSC PHY reset */ + >; + }; + + pinctrl_flexcan1: flexcan1-grp { + fsl,pins = < + MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 + MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 + >; + }; + + pinctrl_flexcan2: flexcan2-grp { + fsl,pins = < + MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 + MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 + >; + }; + + pinctrl_i2c2: i2c2-grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c2_gpio: i2c2-gpio-grp { + fsl,pins = < + MX6UL_PAD_UART5_TX_DATA__GPIO1_IO30 0x4001b8b0 + MX6UL_PAD_UART5_RX_DATA__GPIO1_IO31 0x4001b8b0 + >; + }; + + pinctrl_lcdif: lcdif-grp { + fsl,pins = < + MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 + MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 + MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 + MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 + MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 + MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 + MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 + MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 + MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 + MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 + MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 + MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 + MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 + MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 + MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 + MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 + MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 + MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 + MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 + MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 + MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 + MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 + >; + }; + + pinctrl_pwm1: pwm1-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 + >; + }; + + pinctrl_sai2: sai2-grp { + fsl,pins = < + MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x130b0 + MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 + MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 + MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x120b0 + >; + }; + + pinctrl_tsc: tsc-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 + MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 + MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 + MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 + >; + }; + + pinctrl_uart1: uart1-grp { + fsl,pins = < + MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 + MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 + >; + }; + + pinctrl_uart6: uart6-grp { + fsl,pins = < + MX6UL_PAD_CSI_MCLK__UART6_DCE_TX 0x1b0b1 + MX6UL_PAD_CSI_PIXCLK__UART6_DCE_RX 0x1b0b1 + MX6UL_PAD_CSI_VSYNC__UART6_DCE_RTS 0x1b0b1 + MX6UL_PAD_CSI_HSYNC__UART6_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usbotg1: usbotg1-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO00__ANATOP_OTG1_ID 0x17059 + >; + }; + + pinctrl_usbotg2: usbotg2-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO05__GPIO1_IO05 0x120b0 + >; + }; + + pinctrl_usdhc2: usdhc2-grp { + fsl,pins = < + MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x10069 + MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 + MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 + MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 + MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 + MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 + MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17059 + MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17059 + MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17059 + MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17059 + MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17059 /* SD2 Reset */ + >; + }; +}; + +&iomuxc_snvs { + /* DHCOM GPIOs A..H */ + pinctrl_snvs_dhcom_a: snvs-dhcom-a-grp { + fsl,pins = ; + }; + + pinctrl_snvs_dhcom_b: snvs-dhcom-b-grp { + fsl,pins = ; + }; + + pinctrl_snvs_dhcom_c: snvs-dhcom-c-grp { + fsl,pins = ; + }; + + pinctrl_snvs_dhcom_d: snvs-dhcom-d-grp { + fsl,pins = ; + }; + + pinctrl_snvs_dhcom_e: snvs-dhcom-e-grp { + fsl,pins = ; + }; + + pinctrl_snvs_dhcom_f: snvs-dhcom-f-grp { + fsl,pins = ; + }; + + pinctrl_snvs_dhcom_g: snvs-dhcom-g-grp { + fsl,pins = ; + }; + + pinctrl_snvs_dhcom_h: snvs-dhcom-h-grp { + fsl,pins = ; + }; + + pinctrl_snvs_fec1_phy: snvs-fec1-phy-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER5__GPIO5_IO05 0xb1 /* SMSC PHY Int */ + >; + }; + + pinctrl_snvs_fec2_phy: snvs-fec2-phy-grp { + fsl,pins = < + MX6ULL_PAD_SNVS_TAMPER6__GPIO5_IO06 0xb1 /* SMSC PHY Int */ + >; + }; +}; diff --git a/arch/arm/boot/dts/imx6ull-dhcor-som.dtsi b/arch/arm/boot/dts/imx6ull-dhcor-som.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..5882c7565f6495b31c0d2c5f88431658e3ecf758 --- /dev/null +++ b/arch/arm/boot/dts/imx6ull-dhcor-som.dtsi @@ -0,0 +1,255 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2023 DH electronics GmbH + */ + +#include +#include +#include +#include +#include +#include "imx6ull.dtsi" + +/ { + memory@80000000 { + /* Appropriate memory size will be filled by U-Boot */ + reg = <0x80000000 0>; + device_type = "memory"; + }; +}; + +&cpu0 { + /* + * Due to the design as a solderable SOM, there are no capacitors + * below the SoC, therefore higher voltages are required. + */ + operating-points = < + /* kHz uV */ + 900000 1275000 + 792000 1250000 /* Voltage increased */ + 528000 1175000 + 396000 1025000 + 198000 950000 + >; + fsl,soc-operating-points = < + /* KHz uV */ + 900000 1250000 + 792000 1250000 /* Voltage increased */ + 528000 1175000 + 396000 1175000 + 198000 1175000 + >; +}; + +&gpio1 { + pinctrl-0 = <&pinctrl_spi1_switch>; + pinctrl-names = "default"; + /* + * Pin SPI_BOOT_FLASH_EN (GPIO 1.9) is a switch for either using the + * DHCOM SPI1 interface or accessing the SPI bootflash. Both using + * ecspi1, but muxed to different pins. The DHCOM SPI1 interface uses + * the pins PAD_LCD_DATA21..23 and the SPI bootflash uses the pins + * PAD_CSI_DATA04..07. If the SPI bootflash is enabled the pins for + * DHCOM GPIOs N/O/P/Q/R/S/T/U aren't usable anymore, because they + * are used for the bus interface to the SPI bootflash. The GPIOs are + * disconnected by a buffer which is also controlled via the pin + * SPI_BOOT_FLASH_EN. Therefore the access to the bootflash is a + * special case and is disabled by setting GPIO 1.9 to high. + */ + spi1-switch-hog { + gpio-hog; + gpios = <9 0>; + output-high; + line-name = "spi1-switch"; + }; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-0 = <&pinctrl_i2c1>; + pinctrl-1 = <&pinctrl_i2c1_gpio>; + pinctrl-names = "default", "gpio"; + scl-gpios = <&gpio1 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio1 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + pmic@58 { + compatible = "dlg,da9061"; + reg = <0x58>; + + onkey { + compatible = "dlg,da9061-onkey", "dlg,da9062-onkey"; + status = "disabled"; + }; + + regulators { + vdd_soc_in_1v4: buck1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1400000>; + regulator-min-microvolt = <1400000>; + regulator-name = "vdd_soc_in_1v4"; + }; + + vcc_3v3: buck2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vcc_3v3"; + }; + + /* + * The current DRR3 memory can be supplied with a + * voltage of either 1.35V or 1.5V. For reasons of + * backward compatibility to only 1.5V DDR3 memory, + * the voltage is set to 1.5V. + */ + vcc_ddr_1v35: buck3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1500000>; + regulator-min-microvolt = <1500000>; + regulator-name = "vcc_ddr_1v35"; + }; + + vcc_2v5: ldo1 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <2500000>; + regulator-min-microvolt = <2500000>; + regulator-name = "vcc_2v5"; + }; + + vdd_snvs_in_3v3: ldo2 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "vdd_snvs_in_3v3"; + }; + + vcc_1v8: ldo3 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1800000>; + regulator-min-microvolt = <1800000>; + regulator-name = "vcc_1v8"; + }; + + vcc_1v2: ldo4 { + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <1200000>; + regulator-name = "vcc_1v2"; + }; + }; + + thermal { + compatible = "dlg,da9061-thermal", "dlg,da9062-thermal"; + status = "disabled"; + }; + + watchdog { + compatible = "dlg,da9061-watchdog", "dlg,da9062-watchdog"; + status = "disabled"; + }; + }; +}; + +&ocotp { + /* Don't get write access by default */ + read-only; +}; + +®_arm { + vin-supply = <&vdd_soc_in_1v4>; +}; + +®_soc { + vin-supply = <&vdd_soc_in_1v4>; +}; + +/* BT on LGA (BT_REG_ON is connected to LGA pin E1) */ +&uart2 { + pinctrl-0 = <&pinctrl_uart2>; + pinctrl-names = "default"; + uart-has-rtscts; + status = "okay"; + + /* + * Actually, the maximum speed of the chip is 4MBdps, but there are + * limitations that prevent this speed. It hasn't yet been figured out + * what the reason for this is. Currently, the maximum speed of 3MBdps + * can be used without any problems. If the limitation can be overcome, + * the speed can be increased accordingly. + */ + bluetooth: bluetooth { + compatible = "brcm,bcm43430a1-bt"; /* muRata 1DX */ + max-speed = <3000000>; + vbat-supply = <&vcc_3v3>; + vddio-supply = <&vcc_3v3>; + }; +}; + +/* WiFi on LGA (WL_REG_ON is connected to LGA pin E3) */ +&usdhc1 { + #address-cells = <1>; + #size-cells = <0>; + bus-width = <4>; + no-1-8-v; + non-removable; + keep-power-in-suspend; + pinctrl-0 = <&pinctrl_usdhc1_wifi>; + pinctrl-names = "default"; + wakeup-source; + status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm43430a1-fmac", "brcm,bcm4329-fmac"; /* muRata 1DX */ + reg = <1>; + }; +}; + +&iomuxc { + pinctrl_i2c1: i2c1-grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 + >; + }; + + pinctrl_i2c1_gpio: i2c1-gpio-grp { + fsl,pins = < + MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x4001b8b0 + MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x4001b8b0 + >; + }; + + pinctrl_spi1_switch: spi1-switch-grp { + fsl,pins = < + MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x120b0 /* SPI_BOOT_FLASH_EN */ + >; + }; + + pinctrl_uart2: uart2-grp { + fsl,pins = < + MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 + MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 + MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 + MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 + >; + }; + + pinctrl_usdhc1_wifi: usdhc1-wifi-grp { + fsl,pins = < + MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x1b0b0 + MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10010 + MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x1b0b0 + MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x1b0b0 + MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x1b0b0 + MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/boot/dts/imx7-colibri-aster.dtsi b/arch/arm/boot/dts/imx7-colibri-aster.dtsi index fa488a6de0d4629ce8d91e8f68fed2f2c6dca7db..01612741f792af2e985509457b1de7e0188eec25 100644 --- a/arch/arm/boot/dts/imx7-colibri-aster.dtsi +++ b/arch/arm/boot/dts/imx7-colibri-aster.dtsi @@ -70,6 +70,7 @@ /* Colibri USBC */ &usbotg1 { + disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi index 826f13da5b81c0c727b63223937e57f24ff62a8f..326440f2b4f4f2a185f418cf30a8a104ee8f4c75 100644 --- a/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi +++ b/arch/arm/boot/dts/imx7-colibri-eval-v3.dtsi @@ -101,6 +101,7 @@ /* Colibri USBC */ &usbotg1 { + disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi b/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi index 6e199613583c50b85aa5675691d34fcd7e08e846..b687727f956a6ad9be3631e670a1afeb5dca08d5 100644 --- a/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi +++ b/arch/arm/boot/dts/imx7-colibri-iris-v2.dtsi @@ -99,6 +99,7 @@ /* Colibri USBC */ &usbotg1 { + disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7-colibri-iris.dtsi b/arch/arm/boot/dts/imx7-colibri-iris.dtsi index 175c5d478d2e2110616de7f08748f16aaf233d35..6a9e5ab59691549bbf273e76eea2632b392a8097 100644 --- a/arch/arm/boot/dts/imx7-colibri-iris.dtsi +++ b/arch/arm/boot/dts/imx7-colibri-iris.dtsi @@ -99,6 +99,7 @@ /* Colibri USBC */ &usbotg1 { + disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7-colibri.dtsi b/arch/arm/boot/dts/imx7-colibri.dtsi index f8b8372b68511643e07a3186950ea21916fc4647..104580d51d745b56af6c76ee6ab03f3fd14b5070 100644 --- a/arch/arm/boot/dts/imx7-colibri.dtsi +++ b/arch/arm/boot/dts/imx7-colibri.dtsi @@ -39,7 +39,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpiokeys>; - wakeup { + key-wakeup { debounce-interval = <10>; gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_PULL_DOWN)>; /* SODIMM 45 */ label = "Wake-Up"; diff --git a/arch/arm/boot/dts/imx7d-colibri-aster.dts b/arch/arm/boot/dts/imx7d-colibri-aster.dts index 90aaeddfb4f6d75eee56df3715ebb6979e124bf2..00ab92e56da4df11d010ed72a0ecf1fd3786c3f4 100644 --- a/arch/arm/boot/dts/imx7d-colibri-aster.dts +++ b/arch/arm/boot/dts/imx7d-colibri-aster.dts @@ -36,5 +36,6 @@ /* Colibri USBH */ &usbotg2 { + disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts index 3ec9ef6baaa41b1850fc14aad1b5f4bdb38e71d0..d9c7045a55ba5989d2060f43eeafb9a328fee1f9 100644 --- a/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts +++ b/arch/arm/boot/dts/imx7d-colibri-emmc-aster.dts @@ -18,5 +18,6 @@ /* Colibri USBH */ &usbotg2 { + disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts index 6d505cb02aad68771e67b2fb8060b6a0c1c50ce0..96b599439dded490674db354e09c98f44345fc00 100644 --- a/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts +++ b/arch/arm/boot/dts/imx7d-colibri-emmc-eval-v3.dts @@ -17,5 +17,6 @@ /* Colibri USBH */ &usbotg2 { + disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts index 7347659557f3264a142b425e758ab4f954f83074..5eccb837b15841899b713e4e452c75e7afbc656f 100644 --- a/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts +++ b/arch/arm/boot/dts/imx7d-colibri-emmc-iris-v2.dts @@ -17,5 +17,6 @@ /* Colibri USBH */ &usbotg2 { + disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts b/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts index 5324c92e368d69ae741c952886c7f295df6e438d..ae10e8a66ff1932198793f7bbd2664642b8c7697 100644 --- a/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts +++ b/arch/arm/boot/dts/imx7d-colibri-emmc-iris.dts @@ -17,5 +17,6 @@ /* Colibri USBH */ &usbotg2 { + disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi index 2fb4d2133a1b2cae011571e7d6f62fa283e10256..3740e34ef99f1b6aebd4e6645fb29eb2c3af11f0 100644 --- a/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi +++ b/arch/arm/boot/dts/imx7d-colibri-emmc.dtsi @@ -51,6 +51,7 @@ /* Colibri USBH */ &usbotg2 { + disable-over-current; dr_mode = "host"; vbus-supply = <®_usbh_vbus>; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts index c7a8b5aa24085f01e4cbc7308b44ffa90109a662..33d787617db0d622de5af97b3ffa85a8b7aef421 100644 --- a/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/imx7d-colibri-eval-v3.dts @@ -52,5 +52,6 @@ /* Colibri USBH */ &usbotg2 { + disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts b/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts index 5762f51d5f0ff0af3c0d0e31d159336f308c6fd2..afdb1d06c7f61bf50e96ce955399cad4775e5e2d 100644 --- a/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts +++ b/arch/arm/boot/dts/imx7d-colibri-iris-v2.dts @@ -79,5 +79,6 @@ /* Colibri USBH */ &usbotg2 { + disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-colibri-iris.dts b/arch/arm/boot/dts/imx7d-colibri-iris.dts index 9c63cb9d9a6447feed03b8328578cf6d17e11483..531b0b99bd5ab764071ab6b4081ada502f1b0db6 100644 --- a/arch/arm/boot/dts/imx7d-colibri-iris.dts +++ b/arch/arm/boot/dts/imx7d-colibri-iris.dts @@ -52,5 +52,6 @@ /* Colibri USBH */ &usbotg2 { + disable-over-current; status = "okay"; }; diff --git a/arch/arm/boot/dts/imx7d-pico-dwarf.dts b/arch/arm/boot/dts/imx7d-pico-dwarf.dts index 5162fe227d1ea3eedd035577970f01ce70e69f54..fdc10563f1473eed1f9cd7aaec7d7c59820db1f1 100644 --- a/arch/arm/boot/dts/imx7d-pico-dwarf.dts +++ b/arch/arm/boot/dts/imx7d-pico-dwarf.dts @@ -32,7 +32,7 @@ }; &i2c1 { - clock_frequency = <100000>; + clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; @@ -52,7 +52,7 @@ }; &i2c4 { - clock_frequency = <100000>; + clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; diff --git a/arch/arm/boot/dts/imx7d-pico-nymph.dts b/arch/arm/boot/dts/imx7d-pico-nymph.dts index 104a85254adbbd8688f5294205e08b6250972bca..5afb1674e012518add059d5936fd438977c5a7e8 100644 --- a/arch/arm/boot/dts/imx7d-pico-nymph.dts +++ b/arch/arm/boot/dts/imx7d-pico-nymph.dts @@ -43,7 +43,7 @@ }; &i2c1 { - clock_frequency = <100000>; + clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c1>; status = "okay"; @@ -64,7 +64,7 @@ }; &i2c2 { - clock_frequency = <100000>; + clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2>; status = "okay"; diff --git a/arch/arm/boot/dts/imx7d-smegw01.dts b/arch/arm/boot/dts/imx7d-smegw01.dts index 546268b8d0b13b665d71fdfcf76a0e01e31b9ce4..c0f00f5db11e15004405675494eb5a1ed46262f8 100644 --- a/arch/arm/boot/dts/imx7d-smegw01.dts +++ b/arch/arm/boot/dts/imx7d-smegw01.dts @@ -198,6 +198,7 @@ &usbotg2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usbotg2>; + over-current-active-low; dr_mode = "host"; status = "okay"; }; @@ -374,7 +375,7 @@ pinctrl_usbotg2: usbotg2grp { fsl,pins = < - MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x04 + MX7D_PAD_UART3_RTS_B__USB_OTG2_OC 0x5c >; }; diff --git a/arch/arm/boot/dts/imx7d-zii-rmu2.dts b/arch/arm/boot/dts/imx7d-zii-rmu2.dts index 1c9f25848bf7fa5e1ad29b760c61f8fa0bd8822b..521493342fe972812c0947bccc10819b536a4f71 100644 --- a/arch/arm/boot/dts/imx7d-zii-rmu2.dts +++ b/arch/arm/boot/dts/imx7d-zii-rmu2.dts @@ -204,7 +204,7 @@ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; status = "okay"; - rave-sp { + mcu { compatible = "zii,rave-sp-rdu2"; current-speed = <1000000>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx7d-zii-rpu2.dts b/arch/arm/boot/dts/imx7d-zii-rpu2.dts index 9d29490ab4c9b0349ecef2ecf535c062f16cbcb3..decc19af3b83c9ff297f9d45cf6f2faf7fac0a72 100644 --- a/arch/arm/boot/dts/imx7d-zii-rpu2.dts +++ b/arch/arm/boot/dts/imx7d-zii-rpu2.dts @@ -607,7 +607,7 @@ assigned-clock-parents = <&clks IMX7D_PLL_SYS_MAIN_240M_CLK>; status = "okay"; - rave-sp { + mcu { compatible = "zii,rave-sp-rdu2"; current-speed = <1000000>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/imx7s.dtsi b/arch/arm/boot/dts/imx7s.dtsi index 0fc9e6b8b05dcfdcbc5b5da02236655afb5aa6e3..efe2525b62fa16225567d73ab6e4222470b6056d 100644 --- a/arch/arm/boot/dts/imx7s.dtsi +++ b/arch/arm/boot/dts/imx7s.dtsi @@ -513,7 +513,7 @@ mux: mux-controller { compatible = "mmio-mux"; - #mux-control-cells = <0>; + #mux-control-cells = <1>; mux-reg-masks = <0x14 0x00000010>; }; @@ -1264,7 +1264,6 @@ , , ; - interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; #dma-cells = <1>; dma-channels = <4>; clocks = <&clks IMX7D_NAND_USDHC_BUS_RAWNAND_CLK>; diff --git a/arch/arm/boot/dts/imxrt1050.dtsi b/arch/arm/boot/dts/imxrt1050.dtsi index 03e6a858a7beca7706d8796ce03d3573fe8102d1..852861558b4773eeec01e2e4d12d64437ac5abee 100644 --- a/arch/arm/boot/dts/imxrt1050.dtsi +++ b/arch/arm/boot/dts/imxrt1050.dtsi @@ -93,7 +93,7 @@ bus-width = <4>; fsl,wp-controller; no-1-8-v; - max-frequency = <4000000>; + max-frequency = <200000000>; fsl,tuning-start-tap = <20>; fsl,tuning-step = <2>; status = "disabled"; diff --git a/arch/arm/boot/dts/integrator.dtsi b/arch/arm/boot/dts/integrator.dtsi index ad868cfebc94ab38eff200d83f8e1c720ca1c20a..7f1c8ee9dd8aba0843d0f499ab3546860ab98a66 100644 --- a/arch/arm/boot/dts/integrator.dtsi +++ b/arch/arm/boot/dts/integrator.dtsi @@ -88,12 +88,12 @@ interrupts = <8>; }; - uart@16000000 { + serial@16000000 { reg = <0x16000000 0x1000>; interrupts = <1>; }; - uart@17000000 { + serial@17000000 { reg = <0x17000000 0x1000>; interrupts = <2>; }; diff --git a/arch/arm/boot/dts/integratorap-im-pd1.dts b/arch/arm/boot/dts/integratorap-im-pd1.dts index cc514cf07bff7dcab39cb2b33f87b43ad0c4d0b0..7072a70da00d950b1ec5362a532cc01a67b014f4 100644 --- a/arch/arm/boot/dts/integratorap-im-pd1.dts +++ b/arch/arm/boot/dts/integratorap-im-pd1.dts @@ -162,7 +162,7 @@ }; }; - uart@100000 { + serial@100000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00100000 0x1000>; interrupts-extended = <&impd1_vic 1>; @@ -170,7 +170,7 @@ clock-names = "uartclk", "apb_pclk"; }; - uart@200000 { + serial@200000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x00200000 0x1000>; interrupts-extended = <&impd1_vic 2>; diff --git a/arch/arm/boot/dts/integratorap.dts b/arch/arm/boot/dts/integratorap.dts index 9148287fa0a930de7c329d412cde880740256469..5b52d75bc6bed8d156588ec8b4ceb59967ef073e 100644 --- a/arch/arm/boot/dts/integratorap.dts +++ b/arch/arm/boot/dts/integratorap.dts @@ -218,14 +218,14 @@ clock-names = "apb_pclk"; }; - uart0: uart@16000000 { + uart0: serial@16000000 { compatible = "arm,pl010", "arm,primecell"; arm,primecell-periphid = <0x00041010>; clocks = <&uartclk>, <&pclk>; clock-names = "uartclk", "apb_pclk"; }; - uart1: uart@17000000 { + uart1: serial@17000000 { compatible = "arm,pl010", "arm,primecell"; arm,primecell-periphid = <0x00041010>; clocks = <&uartclk>, <&pclk>; diff --git a/arch/arm/boot/dts/integratorcp.dts b/arch/arm/boot/dts/integratorcp.dts index 38fc7e81bdb652e6fa94e88ec44e707bd19fd2a6..c011333eb165d769a2c0eca61470b1427469f936 100644 --- a/arch/arm/boot/dts/integratorcp.dts +++ b/arch/arm/boot/dts/integratorcp.dts @@ -244,13 +244,13 @@ clock-names = "apb_pclk"; }; - uart@16000000 { + serial@16000000 { compatible = "arm,pl011", "arm,primecell"; clocks = <&uartclk>, <&pclk>; clock-names = "uartclk", "apb_pclk"; }; - uart@17000000 { + serial@17000000 { compatible = "arm,pl011", "arm,primecell"; clocks = <&uartclk>, <&pclk>; clock-names = "uartclk", "apb_pclk"; diff --git a/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts b/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts index f5846a50e4d492804b6667a5a1a8f0b972b5a6fd..b444003c10e1cf116311e49a6eca553dbe7e0f0f 100644 --- a/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts +++ b/arch/arm/boot/dts/intel-ixp42x-welltech-epbx100.dts @@ -76,5 +76,23 @@ }; }; }; + + /* LAN port */ + ethernet@c8009000 { + status = "ok"; + queue-rx = <&qmgr 3>; + queue-txready = <&qmgr 20>; + phy-mode = "rgmii"; + phy-handle = <&phy5>; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + phy5: ethernet-phy@5 { + reg = <5>; + }; + }; + }; }; }; diff --git a/arch/arm/boot/dts/keystone-k2hk-evm.dts b/arch/arm/boot/dts/keystone-k2hk-evm.dts index 4a91f5ded402af22953a8204d11a65000c2e81c0..4352397b4f52e2fa78a582a7c49b447fb0329000 100644 --- a/arch/arm/boot/dts/keystone-k2hk-evm.dts +++ b/arch/arm/boot/dts/keystone-k2hk-evm.dts @@ -28,22 +28,22 @@ leds { compatible = "gpio-leds"; - debug1_1 { + led-debug-1-1 { label = "keystone:green:debug1"; gpios = <&gpio0 12 GPIO_ACTIVE_HIGH>; /* 12 */ }; - debug1_2 { + led-debug-1-2 { label = "keystone:red:debug1"; gpios = <&gpio0 13 GPIO_ACTIVE_HIGH>; /* 13 */ }; - debug2 { + led-debug-2 { label = "keystone:blue:debug2"; gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; /* 14 */ }; - debug3 { + led-debug-3 { label = "keystone:blue:debug3"; gpios = <&gpio0 15 GPIO_ACTIVE_HIGH>; /* 15 */ }; diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi index 7c5510e34494fc49afa91d614d1f491103d48032..49c78c84cd5dfde3b085281a3a4e4bcceeb6f107 100644 --- a/arch/arm/boot/dts/ls1021a.dtsi +++ b/arch/arm/boot/dts/ls1021a.dtsi @@ -866,6 +866,7 @@ clocks = <&clockgen 4 1>, <&clockgen 4 1>; clock-names = "ipg", "per"; big-endian; + status = "disabled"; }; can1: can@2a80000 { @@ -875,6 +876,7 @@ clocks = <&clockgen 4 1>, <&clockgen 4 1>; clock-names = "ipg", "per"; big-endian; + status = "disabled"; }; can2: can@2a90000 { @@ -884,6 +886,7 @@ clocks = <&clockgen 4 1>, <&clockgen 4 1>; clock-names = "ipg", "per"; big-endian; + status = "disabled"; }; can3: can@2aa0000 { @@ -893,6 +896,7 @@ clocks = <&clockgen 4 1>, <&clockgen 4 1>; clock-names = "ipg", "per"; big-endian; + status = "disabled"; }; ocram1: sram@10000000 { diff --git a/arch/arm/boot/dts/mba6ulx.dtsi b/arch/arm/boot/dts/mba6ulx.dtsi index aac42df9ecf6ea00e537594063e4d6234f4ff16b..5bf831b072d6a32aebff09edff60261abd9a12cd 100644 --- a/arch/arm/boot/dts/mba6ulx.dtsi +++ b/arch/arm/boot/dts/mba6ulx.dtsi @@ -226,7 +226,7 @@ }; jc42: temperature-sensor@19 { - compatible = "nxp,se97", "jedec,jc-42.4-temp"; + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; reg = <0x19>; }; diff --git a/arch/arm/boot/dts/meson8-minix-neo-x8.dts b/arch/arm/boot/dts/meson8-minix-neo-x8.dts index 56ea875c418cc69013c192830809a459f5b5f285..c6d1c5a8a3bfebe42f6f0368ad8352927a23ba89 100644 --- a/arch/arm/boot/dts/meson8-minix-neo-x8.dts +++ b/arch/arm/boot/dts/meson8-minix-neo-x8.dts @@ -27,7 +27,7 @@ gpio-leds { compatible = "gpio-leds"; - blue { + led-blue { label = "x8:blue:power"; gpios = <&gpio_ao GPIO_TEST_N GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/meson8.dtsi b/arch/arm/boot/dts/meson8.dtsi index 0f8bac8bac8bb37985eb5c8d2f8b1790bd714493..21eb59041a7d93c728f3d6a8d7f59f40f3bbcd0f 100644 --- a/arch/arm/boot/dts/meson8.dtsi +++ b/arch/arm/boot/dts/meson8.dtsi @@ -133,7 +133,7 @@ }; }; - gpu_opp_table: gpu-opp-table { + gpu_opp_table: opp-table-gpu { compatible = "operating-points-v2"; opp-182142857 { @@ -651,6 +651,9 @@ arm,filter-ranges = <0x100000 0xc0000000>; prefetch-data = <1>; prefetch-instr = <1>; + arm,prefetch-offset = <7>; + arm,double-linefill = <1>; + arm,prefetch-drop = <1>; arm,shared-override; }; diff --git a/arch/arm/boot/dts/meson8b-ec100.dts b/arch/arm/boot/dts/meson8b-ec100.dts index 77d4beeb8010d40fc6696121d949cc47e65d55fb..3da47349eaaf75065afd013fcaeaa3923578b78f 100644 --- a/arch/arm/boot/dts/meson8b-ec100.dts +++ b/arch/arm/boot/dts/meson8b-ec100.dts @@ -73,7 +73,7 @@ leds { compatible = "gpio-leds"; - power { + led-power { label = "ec100:red:power"; /* * Needs to go LOW (together with the poweroff GPIO) diff --git a/arch/arm/boot/dts/meson8b-odroidc1.dts b/arch/arm/boot/dts/meson8b-odroidc1.dts index 04356bc639fafdaf9d05aaf7acce28729a727d7e..73cdfe85568997f86f12066a8f08f18263e24473 100644 --- a/arch/arm/boot/dts/meson8b-odroidc1.dts +++ b/arch/arm/boot/dts/meson8b-odroidc1.dts @@ -34,7 +34,7 @@ leds { compatible = "gpio-leds"; - blue { + led-blue { label = "c1:blue:alive"; gpios = <&gpio_ao GPIOAO_13 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/meson8b.dtsi b/arch/arm/boot/dts/meson8b.dtsi index cf9c04a61ba3c62a04fcbc10f41715a3141b7c2b..d5a3fe21e8e7e5a2d2af42f8bef79fb4e9209b36 100644 --- a/arch/arm/boot/dts/meson8b.dtsi +++ b/arch/arm/boot/dts/meson8b.dtsi @@ -125,7 +125,7 @@ }; }; - gpu_opp_table: gpu-opp-table { + gpu_opp_table: opp-table-gpu { compatible = "operating-points-v2"; opp-255000000 { @@ -643,6 +643,9 @@ arm,filter-ranges = <0x100000 0xc0000000>; prefetch-data = <1>; prefetch-instr = <1>; + arm,prefetch-offset = <7>; + arm,double-linefill = <1>; + arm,prefetch-drop = <1>; arm,shared-override; }; diff --git a/arch/arm/boot/dts/moxart.dtsi b/arch/arm/boot/dts/moxart.dtsi index 764832ddfa78ace56941070a49915cc276669d11..11cbea5b94d2f9d3836f4642120bbe7bfd39c944 100644 --- a/arch/arm/boot/dts/moxart.dtsi +++ b/arch/arm/boot/dts/moxart.dtsi @@ -138,7 +138,7 @@ status = "disabled"; }; - uart0: uart@98200000 { + uart0: serial@98200000 { compatible = "ns16550a"; reg = <0x98200000 0x20>; interrupts = <31 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/mstar-v7.dtsi b/arch/arm/boot/dts/mstar-v7.dtsi index c26ba9b7b6ddfbcb7cad9d1730656717ae4adac9..3eeafd8c7121241232ca1f7d7e2ca8114fa8827d 100644 --- a/arch/arm/boot/dts/mstar-v7.dtsi +++ b/arch/arm/boot/dts/mstar-v7.dtsi @@ -174,7 +174,7 @@ status = "disabled"; }; - pm_uart: uart@221000 { + pm_uart: serial@221000 { compatible = "ns16550a"; reg = <0x221000 0x100>; reg-shift = <3>; diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index b8eba3ba153c25d6229e76e2fc10027e4faf01c1..0a0fe8c5a4059658ca53005a45a93b3163fe7d0a 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -178,7 +178,6 @@ compatible = "mediatek,mt2701-pinctrl"; reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a>; - pins-are-numbered; gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index 25d31e40a5535b64f6351710b86900b2b95bae95..11379c3e6b4ca75af0c6cc5efa555770071fde81 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -253,7 +253,6 @@ compatible = "mediatek,mt7623-pinctrl"; reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a>; - pins-are-numbered; gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi index 46fc236e1b89355a0d4a89e82c91aad1295dcc83..acab0883a3bbf28ed7e9c6e9ccca6425729051dd 100644 --- a/arch/arm/boot/dts/mt7629.dtsi +++ b/arch/arm/boot/dts/mt7629.dtsi @@ -106,8 +106,7 @@ compatible = "mediatek,mt7629-timer", "mediatek,mt6765-timer"; reg = <0x10009000 0x60>; - interrupts = , - ; + interrupts = ; clocks = <&clk20m>; clock-names = "clk20m"; }; diff --git a/arch/arm/boot/dts/mt8135.dtsi b/arch/arm/boot/dts/mt8135.dtsi index a031b36363187f58efd0187393c7a71dd01e22b0..0f291ad22d3afc20ef6e888d7c44c9128e5e85e6 100644 --- a/arch/arm/boot/dts/mt8135.dtsi +++ b/arch/arm/boot/dts/mt8135.dtsi @@ -152,7 +152,6 @@ compatible = "mediatek,mt8135-pinctrl"; reg = <0 0x1000b000 0 0x1000>; mediatek,pctl-regmap = <&syscfg_pctl_a &syscfg_pctl_b>; - pins-are-numbered; gpio-controller; #gpio-cells = <2>; interrupt-controller; diff --git a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi index b637241316bb4314ea6237fb8daef69124f4dd3b..fd671c7a1e5d64c6eafb0a7434c7d14b19f4d1b6 100644 --- a/arch/arm/boot/dts/nuvoton-wpcm450.dtsi +++ b/arch/arm/boot/dts/nuvoton-wpcm450.dtsi @@ -480,6 +480,7 @@ reg = <0xc8000000 0x1000>, <0xc0000000 0x4000000>; reg-names = "control", "memory"; clocks = <&clk 0>; + nuvoton,shm = <&shm>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/omap3-gta04a5.dts b/arch/arm/boot/dts/omap3-gta04a5.dts index 0b5bd7388877143895cebc40b4135505411ec26a..425081201fd42daf04d8a0a638d0878ee5be750e 100644 --- a/arch/arm/boot/dts/omap3-gta04a5.dts +++ b/arch/arm/boot/dts/omap3-gta04a5.dts @@ -75,6 +75,11 @@ >; }; + bno050_pins: pinmux-bno050-pins { + pinctrl-single,pins = < + OMAP3_CORE1_IOPAD(0x2136, PIN_INPUT | MUX_MODE4) /* gpin113 */ + >; + }; }; /* @@ -115,17 +120,17 @@ /delete-node/ itg3200@68; /delete-node/ hmc5843@1e; - bmg160@69 { + gyrometer@69 { compatible = "bosch,bmg160"; reg = <0x69>; }; - bmc150@10 { + accelerometer@10 { compatible = "bosch,bmc150_accel"; reg = <0x10>; }; - bmc150@12 { + magnetometer@12 { compatible = "bosch,bmc150_magn"; reg = <0x12>; }; @@ -136,4 +141,12 @@ vdda-supply = <&vio>; vddd-supply = <&vio>; }; + + imu@29 { + compatible = "bosch,bno055"; + reg = <0x29>; + pinctrl-names = "default"; + pinctrl-0 = <&bno050_pins>; + /* interrupt at &gpio4 17 */ + }; }; diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts index 6ba2e8f81973fc49c6edab67b220f9992cb80bc0..f9f9eca0c56ccfaaeba12b106050aa92a511f3cf 100644 --- a/arch/arm/boot/dts/omap3-n900.dts +++ b/arch/arm/boot/dts/omap3-n900.dts @@ -9,6 +9,7 @@ #include "omap34xx.dtsi" #include #include +#include /* * Default secure signed bootloader (Nokia X-Loader) does not enable L3 firewall @@ -194,7 +195,7 @@ csi_isp: endpoint { remote-endpoint = <&csi_cam1>; - bus-type = <3>; /* CCP2 */ + bus-type = ; clock-lanes = <1>; data-lanes = <0>; lane-polarity = <0 0>; @@ -767,56 +768,20 @@ clock-frequency = <400000>; - lis302dl: lis3lv02d@1d { - compatible = "st,lis3lv02d"; + accelerometer@1d { + compatible = "st,lis302dl"; reg = <0x1d>; - Vdd-supply = <&vaux1>; - Vdd_IO-supply = <&vio>; + vdd-supply = <&vaux1>; + vddio-supply = <&vio>; interrupt-parent = <&gpio6>; - interrupts = <21 20>; /* 181 and 180 */ - - /* click flags */ - st,click-single-x; - st,click-single-y; - st,click-single-z; - - /* Limits are 0.5g * value */ - st,click-threshold-x = <8>; - st,click-threshold-y = <8>; - st,click-threshold-z = <10>; - - /* Click must be longer than time limit */ - st,click-time-limit = <9>; - - /* Kind of debounce filter */ - st,click-latency = <50>; - - /* Interrupt line 2 for click detection */ - st,irq2-click; - - st,wakeup-x-hi; - st,wakeup-y-hi; - st,wakeup-threshold = <(800/18)>; /* millig-value / 18 to get HW values */ - - st,wakeup2-z-hi; - st,wakeup2-threshold = <(900/18)>; /* millig-value / 18 to get HW values */ - - st,hipass1-disable; - st,hipass2-disable; - - st,axis-x = <1>; /* LIS3_DEV_X */ - st,axis-y = <(-2)>; /* LIS3_INV_DEV_Y */ - st,axis-z = <(-3)>; /* LIS3_INV_DEV_Z */ - - st,min-limit-x = <(-32)>; - st,min-limit-y = <3>; - st,min-limit-z = <3>; + interrupts = <21 IRQ_TYPE_EDGE_RISING>, + <20 IRQ_TYPE_EDGE_RISING>; /* 181 and 180 */ - st,max-limit-x = <(-3)>; - st,max-limit-y = <32>; - st,max-limit-z = <32>; + mount-matrix = "-1", "0", "0", + "0", "1", "0", + "0", "0", "1"; }; cam1: camera@3e { @@ -835,7 +800,7 @@ port { csi_cam1: endpoint { - bus-type = <3>; /* CCP2 */ + bus-type = ; strobe = <1>; clock-inv = <0>; crc = <1>; diff --git a/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts b/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts index 1c52337af560383bdf8567a3caeeec676ce1c3a9..91b860e24681f13210dc368ab2f2ca0cf53a619f 100644 --- a/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts +++ b/arch/arm/boot/dts/qcom-apq8026-samsung-matisse-wifi.dts @@ -9,6 +9,9 @@ #include "qcom-msm8226.dtsi" #include "qcom-pm8226.dtsi" +/delete-node/ &adsp_region; +/delete-node/ &smem_region; + / { model = "Samsung Galaxy Tab 4 10.1"; compatible = "samsung,matisse-wifi", "qcom,apq8026"; @@ -77,6 +80,55 @@ }; }; + i2c-backlight { + compatible = "i2c-gpio"; + sda-gpios = <&tlmm 20 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + scl-gpios = <&tlmm 21 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; + + pinctrl-0 = <&backlight_i2c_default_state>; + pinctrl-names = "default"; + + i2c-gpio,delay-us = <4>; + + #address-cells = <1>; + #size-cells = <0>; + + backlight@2c { + compatible = "ti,lp8556"; + reg = <0x2c>; + + dev-ctrl = /bits/ 8 <0x80>; + init-brt = /bits/ 8 <0x3f>; + pwm-period = <100000>; + + pwms = <&backlight_pwm 0 100000>; + pwm-names = "lp8556"; + + rom-a0h { + rom-addr = /bits/ 8 <0xa0>; + rom-val = /bits/ 8 <0x44>; + }; + + rom-a1h { + rom-addr = /bits/ 8 <0xa1>; + rom-val = /bits/ 8 <0x6c>; + }; + + rom-a5h { + rom-addr = /bits/ 8 <0xa5>; + rom-val = /bits/ 8 <0x24>; + }; + }; + }; + + backlight_pwm: pwm { + compatible = "clk-pwm"; + #pwm-cells = <2>; + clocks = <&mmcc CAMSS_GP0_CLK>; + pinctrl-0 = <&backlight_pwm_default_state>; + pinctrl-names = "default"; + }; + reg_tsp_1p8v: regulator-tsp-1p8v { compatible = "regulator-fixed"; regulator-name = "tsp_1p8v"; @@ -133,7 +185,7 @@ no-map; }; - adsp@d900000 { + adsp_region: adsp@d900000 { reg = <0x0d900000 0x1800000>; no-map; }; @@ -143,7 +195,6 @@ no-map; }; - /delete-node/ smem@3000000; smem_region: smem@fa00000 { reg = <0x0fa00000 0x100000>; no-map; @@ -169,6 +220,10 @@ }; }; +&adsp { + status = "okay"; +}; + &blsp1_i2c2 { status = "okay"; @@ -412,6 +467,18 @@ bias-disable; }; + backlight_i2c_default_state: backlight-i2c-default-state { + pins = "gpio20", "gpio21"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + backlight_pwm_default_state: backlight-pwm-default-state { + pins = "gpio33"; + function = "gp0_clk"; + }; + muic_int_default_state: muic-int-default-state { pins = "gpio67"; function = "gpio"; diff --git a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts index 7a4c59e04af6e9042d351eb2edaab85b6dfc740c..8e4b61e4d4b1750c8afe8404de9158f32d8dcb5f 100644 --- a/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts +++ b/arch/arm/boot/dts/qcom-apq8060-dragonboard.dts @@ -435,15 +435,13 @@ &pm8058_mpps { dragon_cm3605_mpps: cm3605-mpps-state { - mpp5 { - pins = "mpp5"; - function = "analog"; - input-enable; - bias-high-impedance; - /* Let's use channel 5 */ - qcom,amux-route = ; - power-source = ; - }; + pins = "mpp5"; + function = "analog"; + input-enable; + bias-high-impedance; + /* Let's use channel 5 */ + qcom,amux-route = ; + power-source = ; }; }; diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index bf2fb0f70fe4f34350f1ba13c9c0f470e8433dcf..c57c27cd8a202a174b715b5035e40754e4472a68 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -22,7 +22,7 @@ #size-cells = <1>; ranges; - ramoops@88d00000{ + ramoops@88d00000 { compatible = "ramoops"; reg = <0x88d00000 0x100000>; record-size = <0x00020000>; diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 0da9623ea0849407cf63dfe7e92cd964dad21e6e..92aa2b081901f5fb73b08cb767c72d38ad6df673 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -375,14 +375,13 @@ }; timer@200a000 { - compatible = "qcom,kpss-timer", - "qcom,kpss-wdt-apq8064", "qcom,msm-timer"; + compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer", + "qcom,msm-timer"; interrupts = <1 1 0x301>, <1 2 0x301>, <1 3 0x301>; reg = <0x0200a000 0x100>; - clock-frequency = <27000000>, - <32768>; + clock-frequency = <27000000>; cpu-offset = <0x80000>; }; @@ -866,9 +865,9 @@ <&gcc PLL8_VOTE>, <&dsi0_phy 1>, <&dsi0_phy 0>, - <0>, - <0>, - <0>; + <&dsi1_phy 1>, + <&dsi1_phy 0>, + <&hdmi_phy>; clock-names = "pxo", "pll3", "pll8_vote", @@ -1102,7 +1101,7 @@ dma-names = "tx", "rx"; }; - sdcc3bam: dma-controller@12182000{ + sdcc3bam: dma-controller@12182000 { compatible = "qcom,bam-v1.3.0"; reg = <0x12182000 0x8000>; interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>; @@ -1130,7 +1129,7 @@ pinctrl-0 = <&sdc4_gpios>; }; - sdcc4bam: dma-controller@121c2000{ + sdcc4bam: dma-controller@121c2000 { compatible = "qcom,bam-v1.3.0"; reg = <0x121c2000 0x8000>; interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>; @@ -1159,7 +1158,7 @@ dma-names = "tx", "rx"; }; - sdcc1bam: dma-controller@12402000{ + sdcc1bam: dma-controller@12402000 { compatible = "qcom,bam-v1.3.0"; reg = <0x12402000 0x8000>; interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; @@ -1277,7 +1276,8 @@ }; dsi0: dsi@4700000 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,apq8064-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; label = "MDSS DSI CTRL->0"; #address-cells = <1>; #size-cells = <0>; @@ -1342,6 +1342,80 @@ status = "disabled"; }; + dsi1: dsi@5800000 { + compatible = "qcom,mdss-dsi-ctrl"; + interrupts = ; + reg = <0x05800000 0x200>; + reg-names = "dsi_ctrl"; + + clocks = <&mmcc DSI2_M_AHB_CLK>, + <&mmcc DSI2_S_AHB_CLK>, + <&mmcc AMP_AHB_CLK>, + <&mmcc DSI2_CLK>, + <&mmcc DSI2_BYTE_CLK>, + <&mmcc DSI2_PIXEL_CLK>, + <&mmcc DSI2_ESC_CLK>; + clock-names = "iface", + "bus", + "core_mmss", + "src", + "byte", + "pixel", + "core"; + + assigned-clocks = <&mmcc DSI2_BYTE_SRC>, + <&mmcc DSI2_ESC_SRC>, + <&mmcc DSI2_SRC>, + <&mmcc DSI2_PIXEL_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, + <&dsi1_phy 0>, + <&dsi1_phy 1>, + <&dsi1_phy 1>; + + syscon-sfpb = <&mmss_sfpb>; + phys = <&dsi1_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + + dsi1_phy: dsi-phy@5800200 { + compatible = "qcom,dsi-phy-28nm-8960"; + reg = <0x05800200 0x100>, + <0x05800300 0x200>, + <0x05800500 0x5c>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + clock-names = "iface", + "ref"; + clocks = <&mmcc DSI2_M_AHB_CLK>, + <&pxo_board>; + #clock-cells = <1>; + #phy-cells = <0>; + + status = "disabled"; + }; mdp_port0: iommu@7500000 { compatible = "qcom,apq8064-iommu"; @@ -1489,11 +1563,12 @@ clocks = <&mmcc HDMI_S_AHB_CLK>; clock-names = "slave_iface"; #phy-cells = <0>; + #clock-cells = <0>; status = "disabled"; }; - mdp: mdp@5100000 { + mdp: display-controller@5100000 { compatible = "qcom,mdp4"; reg = <0x05100000 0xf0000>; interrupts = ; diff --git a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts index 44cd72f1b1be4795e391d63c5088d8f00b54fa92..116e59a3b76d01e54306ced831dfbc2019b05754 100644 --- a/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts +++ b/arch/arm/boot/dts/qcom-apq8084-ifc6540.dts @@ -19,16 +19,16 @@ serial@f995e000 { status = "okay"; }; + }; +}; - sdhci@f9824900 { - bus-width = <8>; - non-removable; - status = "okay"; - }; +&sdhc_1 { + bus-width = <8>; + non-removable; + status = "okay"; +}; - sdhci@f98a4900 { - cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>; - bus-width = <4>; - }; - }; +&sdhc_2 { + cd-gpios = <&tlmm 122 GPIO_ACTIVE_LOW>; + bus-width = <4>; }; diff --git a/arch/arm/boot/dts/qcom-apq8084.dtsi b/arch/arm/boot/dts/qcom-apq8084.dtsi index fe30abfff90a77d10f51ca48105da0bbb7ca5944..fabd7455eb8f8a7ab0b38e03c568f549d8724590 100644 --- a/arch/arm/boot/dts/qcom-apq8084.dtsi +++ b/arch/arm/boot/dts/qcom-apq8084.dtsi @@ -249,11 +249,260 @@ reg = <0xfc4bc000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_calib: calib@d0 { - reg = <0xd0 0x18>; + + tsens_base1: base1@d0 { + reg = <0xd0 0x1>; + bits = <0 8>; + }; + + tsens_s0_p1: s0-p1@d1 { + reg = <0xd1 0x1>; + bits = <0 6>; + }; + + tsens_s1_p1: s1-p1@d2 { + reg = <0xd1 0x2>; + bits = <6 6>; + }; + + tsens_s2_p1: s2-p1@d2 { + reg = <0xd2 0x2>; + bits = <4 6>; + }; + + tsens_s3_p1: s3-p1@d3 { + reg = <0xd3 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1: s4-p1@d4 { + reg = <0xd4 0x1>; + bits = <0 6>; + }; + + tsens_s5_p1: s5-p1@d4 { + reg = <0xd4 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1: s6-p1@d5 { + reg = <0xd5 0x2>; + bits = <4 6>; + }; + + tsens_s7_p1: s7-p1@d6 { + reg = <0xd6 0x1>; + bits = <2 6>; + }; + + tsens_s8_p1: s8-p1@d7 { + reg = <0xd7 0x1>; + bits = <0 6>; + }; + + tsens_mode: mode@d7 { + reg = <0xd7 0x1>; + bits = <6 2>; + }; + + tsens_s9_p1: s9-p1@d8 { + reg = <0xd8 0x1>; + bits = <0 6>; + }; + + tsens_s10_p1: s10_p1@d8 { + reg = <0xd8 0x2>; + bits = <6 6>; + }; + + tsens_base2: base2@d9 { + reg = <0xd9 0x2>; + bits = <4 8>; + }; + + tsens_s0_p2: s0-p2@da { + reg = <0xda 0x2>; + bits = <4 6>; + }; + + tsens_s1_p2: s1-p2@db { + reg = <0xdb 0x1>; + bits = <2 6>; + }; + + tsens_s2_p2: s2-p2@dc { + reg = <0xdc 0x1>; + bits = <0 6>; + }; + + tsens_s3_p2: s3-p2@dc { + reg = <0xdc 0x2>; + bits = <6 6>; + }; + + tsens_s4_p2: s4-p2@dd { + reg = <0xdd 0x2>; + bits = <4 6>; + }; + + tsens_s5_p2: s5-p2@de { + reg = <0xde 0x2>; + bits = <2 6>; + }; + + tsens_s6_p2: s6-p2@df { + reg = <0xdf 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2: s7-p2@e0 { + reg = <0xe0 0x1>; + bits = <0 6>; + }; + + tsens_s8_p2: s8-p2@e0 { + reg = <0xe0 0x2>; + bits = <6 6>; + }; + + tsens_s9_p2: s9-p2@e1 { + reg = <0xe1 0x2>; + bits = <4 6>; + }; + + tsens_s10_p2: s10_p2@e2 { + reg = <0xe2 0x2>; + bits = <2 6>; + }; + + tsens_s5_p2_backup: s5-p2_backup@e3 { + reg = <0xe3 0x2>; + bits = <0 6>; + }; + + tsens_mode_backup: mode_backup@e3 { + reg = <0xe3 0x1>; + bits = <6 2>; + }; + + tsens_s6_p2_backup: s6-p2_backup@e4 { + reg = <0xe4 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2_backup: s7-p2_backup@e4 { + reg = <0xe4 0x2>; + bits = <6 6>; + }; + + tsens_s8_p2_backup: s8-p2_backup@e5 { + reg = <0xe5 0x2>; + bits = <4 6>; + }; + + tsens_s9_p2_backup: s9-p2_backup@e6 { + reg = <0xe6 0x2>; + bits = <2 6>; + }; + + tsens_s10_p2_backup: s10_p2_backup@e7 { + reg = <0xe7 0x1>; + bits = <0 6>; + }; + + tsens_base1_backup: base1_backup@440 { + reg = <0x440 0x1>; + bits = <0 8>; + }; + + tsens_s0_p1_backup: s0-p1_backup@441 { + reg = <0x441 0x1>; + bits = <0 6>; + }; + + tsens_s1_p1_backup: s1-p1_backup@442 { + reg = <0x441 0x2>; + bits = <6 6>; + }; + + tsens_s2_p1_backup: s2-p1_backup@442 { + reg = <0x442 0x2>; + bits = <4 6>; + }; + + tsens_s3_p1_backup: s3-p1_backup@443 { + reg = <0x443 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1_backup: s4-p1_backup@444 { + reg = <0x444 0x1>; + bits = <0 6>; }; - tsens_backup: backup@440 { - reg = <0x440 0x10>; + + tsens_s5_p1_backup: s5-p1_backup@444 { + reg = <0x444 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1_backup: s6-p1_backup@445 { + reg = <0x445 0x2>; + bits = <4 6>; + }; + + tsens_s7_p1_backup: s7-p1_backup@446 { + reg = <0x446 0x1>; + bits = <2 6>; + }; + + tsens_use_backup: use_backup@447 { + reg = <0x447 0x1>; + bits = <5 3>; + }; + + tsens_s8_p1_backup: s8-p1_backup@448 { + reg = <0x448 0x1>; + bits = <0 6>; + }; + + tsens_s9_p1_backup: s9-p1_backup@448 { + reg = <0x448 0x2>; + bits = <6 6>; + }; + + tsens_s10_p1_backup: s10_p1_backup@449 { + reg = <0x449 0x2>; + bits = <4 6>; + }; + + tsens_base2_backup: base2_backup@44a { + reg = <0x44a 0x2>; + bits = <2 8>; + }; + + tsens_s0_p2_backup: s0-p2_backup@44b { + reg = <0x44b 0x3>; + bits = <2 6>; + }; + + tsens_s1_p2_backup: s1-p2_backup@44c { + reg = <0x44c 0x1>; + bits = <0 6>; + }; + + tsens_s2_p2_backup: s2-p2_backup@44c { + reg = <0x44c 0x2>; + bits = <6 6>; + }; + + tsens_s3_p2_backup: s3-p2_backup@44d { + reg = <0x44d 0x2>; + bits = <4 6>; + }; + + tsens_s4_p2_backup: s4-p2_backup@44e { + reg = <0x44e 0x1>; + bits = <2 6>; }; }; @@ -261,8 +510,60 @@ compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; reg = <0xfc4a9000 0x1000>, /* TM */ <0xfc4a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_use_backup>, + <&tsens_mode_backup>, + <&tsens_base1_backup>, <&tsens_base2_backup>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>, + <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, + <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, + <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, + <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, + <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, + <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, + <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, + <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, + <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, + <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, + <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; + nvmem-cell-names = "mode", + "base1", "base2", + "use_backup", + "mode_backup", + "base1_backup", "base2_backup", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2", + "s0_p1_backup", "s0_p2_backup", + "s1_p1_backup", "s1_p2_backup", + "s2_p1_backup", "s2_p2_backup", + "s3_p1_backup", "s3_p2_backup", + "s4_p1_backup", "s4_p2_backup", + "s5_p1_backup", "s5_p2_backup", + "s6_p1_backup", "s6_p2_backup", + "s7_p1_backup", "s7_p2_backup", + "s8_p1_backup", "s8_p2_backup", + "s9_p1_backup", "s9_p2_backup", + "s10_p1_backup", "s10_p2_backup"; #qcom,sensors = <11>; interrupts = ; interrupt-names = "uplow"; @@ -388,6 +689,24 @@ #reset-cells = <1>; #power-domain-cells = <1>; reg = <0xfc400000 0x4000>; + clocks = <&xo_board>, + <&sleep_clk>, + <0>, /* ufs */ + <0>, + <0>, + <0>, + <0>, /* sata */ + <0>, + <0>; /* pcie */ + clock-names = "xo", + "sleep_clk", + "ufs_rx_symbol_0_clk_src", + "ufs_rx_symbol_1_clk_src", + "ufs_tx_symbol_0_clk_src", + "ufs_tx_symbol_1_clk_src", + "sata_asic0_clk", + "sata_rx_clk", + "pcie_pipe"; }; tcsr_mutex: hwlock@fd484000 { @@ -421,7 +740,7 @@ status = "disabled"; }; - mmc@f9824900 { + sdhc_1: mmc@f9824900 { compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf9824900 0x11c>, <0xf9824000 0x800>; reg-names = "hc", "core"; @@ -434,7 +753,7 @@ status = "disabled"; }; - mmc@f98a4900 { + sdhc_2: mmc@f98a4900 { compatible = "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"; reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>; reg-names = "hc", "core"; diff --git a/arch/arm/boot/dts/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom-ipq4019.dtsi index acb08dcf94428fb8b6b4e945353493f7908d19b9..02e9ea78405d01d6f01940427fd9c68eb7157ef4 100644 --- a/arch/arm/boot/dts/qcom-ipq4019.dtsi +++ b/arch/arm/boot/dts/qcom-ipq4019.dtsi @@ -106,7 +106,7 @@ }; }; - cpu0_opp_table: opp_table0 { + cpu0_opp_table: opp-table { compatible = "operating-points-v2"; opp-shared; @@ -400,7 +400,7 @@ }; watchdog: watchdog@b017000 { - compatible = "qcom,kpss-wdt", "qcom,kpss-wdt-ipq4019"; + compatible = "qcom,kpss-wdt-ipq4019", "qcom,kpss-wdt"; reg = <0xb017000 0x40>; clocks = <&sleep_clk>; timeout-sec = <10>; diff --git a/arch/arm/boot/dts/qcom-ipq8064.dtsi b/arch/arm/boot/dts/qcom-ipq8064.dtsi index 7e784b0995da2bd8186b3cc33320672d6a698c83..52d77e105957a9c841cb3d8a7839215728f96e03 100644 --- a/arch/arm/boot/dts/qcom-ipq8064.dtsi +++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi @@ -326,26 +326,26 @@ }; }; + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <7>; + snps,rd_osr_lmt = <7>; + snps,blen = <16 0 0 0 0 0 0>; + }; + + vsdcc_fixed: vsdcc-regulator { + compatible = "regulator-fixed"; + regulator-name = "SDCC Power"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + soc: soc { #address-cells = <1>; #size-cells = <1>; ranges; compatible = "simple-bus"; - stmmac_axi_setup: stmmac-axi-config { - snps,wr_osr_lmt = <7>; - snps,rd_osr_lmt = <7>; - snps,blen = <16 0 0 0 0 0 0>; - }; - - vsdcc_fixed: vsdcc-regulator { - compatible = "regulator-fixed"; - regulator-name = "SDCC Power"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - rpm: rpm@108000 { compatible = "qcom,rpm-ipq8064"; reg = <0x00108000 0x1000>; @@ -549,8 +549,8 @@ }; timer@200a000 { - compatible = "qcom,kpss-timer", - "qcom,kpss-wdt-ipq8064", "qcom,msm-timer"; + compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", + "qcom,msm-timer"; interrupts = , ; reg = <0x0200a000 0x100>; - clock-frequency = <25000000>, - <32768>; + clock-frequency = <25000000>; clocks = <&sleep_clk>; clock-names = "sleep"; cpu-offset = <0x80000>; diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index b0fe1d95d88f891c61935f5c7f353b05c24e077c..8e9ea61a1e48b4404a60c52407dccbe4ccc30273 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -79,13 +79,13 @@ }; timer@200a000 { - compatible = "qcom,kpss-timer", "qcom,msm-timer"; + compatible = "qcom,kpss-wdt-mdm9615", "qcom,kpss-timer", + "qcom,msm-timer"; interrupts = , , ; reg = <0x0200a000 0x100>; - clock-frequency = <27000000>, - <32768>; + clock-frequency = <27000000>; cpu-offset = <0x80000>; }; @@ -294,7 +294,7 @@ }; }; - sdcc1bam: dma-controller@12182000{ + sdcc1bam: dma-controller@12182000 { compatible = "qcom,bam-v1.3.0"; reg = <0x12182000 0x8000>; interrupts = ; @@ -304,7 +304,7 @@ qcom,ee = <0>; }; - sdcc2bam: dma-controller@12142000{ + sdcc2bam: dma-controller@12142000 { compatible = "qcom,bam-v1.3.0"; reg = <0x12142000 0x8000>; interrupts = ; diff --git a/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts b/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts index 6a082ad4418a918338830767ffe00a6a855977d2..288cacd5d1fabc171e24e60e15600f33003557f9 100644 --- a/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts +++ b/arch/arm/boot/dts/qcom-msm8226-samsung-s3ve3g.dts @@ -20,5 +20,5 @@ }; &blsp1_uart3 { - status = "ok"; + status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index 4cba25dad8d6995c3b1d1903a8917efb5de860d5..c373081bc21b29e0c42118eaedc18bd5562fa072 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -74,6 +74,13 @@ compatible = "qcom,rpm-msm8226"; qcom,smd-channels = "rpm_requests"; + rpmcc: clock-controller { + compatible = "qcom,rpmcc-msm8226", "qcom,rpmcc"; + #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; + }; + rpmpd: power-controller { compatible = "qcom,msm8226-rpmpd"; #power-domain-cells = <1>; diff --git a/arch/arm/boot/dts/qcom-msm8960.dtsi b/arch/arm/boot/dts/qcom-msm8960.dtsi index 7debf9db7cb16ba01bdd5afb36598633ad7102eb..a0369b38fe0724abaf4637dbda4d579a41e411bc 100644 --- a/arch/arm/boot/dts/qcom-msm8960.dtsi +++ b/arch/arm/boot/dts/qcom-msm8960.dtsi @@ -103,14 +103,13 @@ }; timer@200a000 { - compatible = "qcom,kpss-timer", - "qcom,kpss-wdt-msm8960", "qcom,msm-timer"; + compatible = "qcom,kpss-wdt-msm8960", "qcom,kpss-timer", + "qcom,msm-timer"; interrupts = , , ; reg = <0x0200a000 0x100>; - clock-frequency = <27000000>, - <32768>; + clock-frequency = <27000000>; cpu-offset = <0x80000>; }; diff --git a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts index 280e63e3ebf2eeac7bd1f2eb024bcbfdea6062b2..ab35f2d644c0e83b284d87ea8230ba9d9dcc0f1d 100644 --- a/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts +++ b/arch/arm/boot/dts/qcom-msm8974-lge-nexus5-hammerhead.dts @@ -319,6 +319,17 @@ }; }; +&remoteproc_adsp { + cx-supply = <&pm8841_s2>; +}; + +&remoteproc_mss { + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; +}; + &rpm_requests { regulators-0 { compatible = "qcom,rpm-pm8841-regulators"; diff --git a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi index 1b683690a1adef40b1ca253b32e2c57c1158ee99..d3bec03b126c8b68cb404fa68ab3b60e9579ef99 100644 --- a/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974-sony-xperia-rhine.dtsi @@ -188,6 +188,17 @@ qcom,num-strings = <2>; }; +&remoteproc_adsp { + cx-supply = <&pm8841_s2>; +}; + +&remoteproc_mss { + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; +}; + &rpm_requests { regulators-0 { compatible = "qcom,rpm-pm8841-regulators"; diff --git a/arch/arm/boot/dts/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom-msm8974.dtsi index 8d216a3c08511f39b2aa0a46bbfbba7b25aa7811..834ad95515b174394746dca035ea55373403ecdb 100644 --- a/arch/arm/boot/dts/qcom-msm8974.dtsi +++ b/arch/arm/boot/dts/qcom-msm8974.dtsi @@ -307,6 +307,8 @@ rpmcc: clock-controller { compatible = "qcom,rpmcc-msm8974", "qcom,rpmcc"; #clock-cells = <1>; + clocks = <&xo_board>; + clock-names = "xo"; }; }; }; @@ -1054,6 +1056,11 @@ #reset-cells = <1>; #power-domain-cells = <1>; reg = <0xfc400000 0x4000>; + + clocks = <&xo_board>, + <&sleep_clk>; + clock-names = "xo", + "sleep_clk"; }; rpm_msg_ram: sram@fc428000 { @@ -1119,8 +1126,60 @@ compatible = "qcom,msm8974-tsens", "qcom,tsens-v0_1"; reg = <0xfc4a9000 0x1000>, /* TM */ <0xfc4a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_calib>, <&tsens_backup>; - nvmem-cell-names = "calib", "calib_backup"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_use_backup>, + <&tsens_mode_backup>, + <&tsens_base1_backup>, <&tsens_base2_backup>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>, + <&tsens_s10_p1>, <&tsens_s10_p2>, + <&tsens_s0_p1_backup>, <&tsens_s0_p2_backup>, + <&tsens_s1_p1_backup>, <&tsens_s1_p2_backup>, + <&tsens_s2_p1_backup>, <&tsens_s2_p2_backup>, + <&tsens_s3_p1_backup>, <&tsens_s3_p2_backup>, + <&tsens_s4_p1_backup>, <&tsens_s4_p2_backup>, + <&tsens_s5_p1_backup>, <&tsens_s5_p2_backup>, + <&tsens_s6_p1_backup>, <&tsens_s6_p2_backup>, + <&tsens_s7_p1_backup>, <&tsens_s7_p2_backup>, + <&tsens_s8_p1_backup>, <&tsens_s8_p2_backup>, + <&tsens_s9_p1_backup>, <&tsens_s9_p2_backup>, + <&tsens_s10_p1_backup>, <&tsens_s10_p2_backup>; + nvmem-cell-names = "mode", + "base1", "base2", + "use_backup", + "mode_backup", + "base1_backup", "base2_backup", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2", + "s10_p1", "s10_p2", + "s0_p1_backup", "s0_p2_backup", + "s1_p1_backup", "s1_p2_backup", + "s2_p1_backup", "s2_p2_backup", + "s3_p1_backup", "s3_p2_backup", + "s4_p1_backup", "s4_p2_backup", + "s5_p1_backup", "s5_p2_backup", + "s6_p1_backup", "s6_p2_backup", + "s7_p1_backup", "s7_p2_backup", + "s8_p1_backup", "s8_p2_backup", + "s9_p1_backup", "s9_p2_backup", + "s10_p1_backup", "s10_p2_backup"; #qcom,sensors = <11>; interrupts = ; interrupt-names = "uplow"; @@ -1137,11 +1196,260 @@ reg = <0xfc4bc000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_calib: calib@d0 { - reg = <0xd0 0x18>; + + tsens_base1: base1@d0 { + reg = <0xd0 0x1>; + bits = <0 8>; + }; + + tsens_s0_p1: s0-p1@d1 { + reg = <0xd1 0x1>; + bits = <0 6>; + }; + + tsens_s1_p1: s1-p1@d2 { + reg = <0xd1 0x2>; + bits = <6 6>; + }; + + tsens_s2_p1: s2-p1@d2 { + reg = <0xd2 0x2>; + bits = <4 6>; + }; + + tsens_s3_p1: s3-p1@d3 { + reg = <0xd3 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1: s4-p1@d4 { + reg = <0xd4 0x1>; + bits = <0 6>; + }; + + tsens_s5_p1: s5-p1@d4 { + reg = <0xd4 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1: s6-p1@d5 { + reg = <0xd5 0x2>; + bits = <4 6>; + }; + + tsens_s7_p1: s7-p1@d6 { + reg = <0xd6 0x1>; + bits = <2 6>; + }; + + tsens_s8_p1: s8-p1@d7 { + reg = <0xd7 0x1>; + bits = <0 6>; + }; + + tsens_mode: mode@d7 { + reg = <0xd7 0x1>; + bits = <6 2>; + }; + + tsens_s9_p1: s9-p1@d8 { + reg = <0xd8 0x1>; + bits = <0 6>; + }; + + tsens_s10_p1: s10_p1@d8 { + reg = <0xd8 0x2>; + bits = <6 6>; + }; + + tsens_base2: base2@d9 { + reg = <0xd9 0x2>; + bits = <4 8>; + }; + + tsens_s0_p2: s0-p2@da { + reg = <0xda 0x2>; + bits = <4 6>; + }; + + tsens_s1_p2: s1-p2@db { + reg = <0xdb 0x1>; + bits = <2 6>; + }; + + tsens_s2_p2: s2-p2@dc { + reg = <0xdc 0x1>; + bits = <0 6>; + }; + + tsens_s3_p2: s3-p2@dc { + reg = <0xdc 0x2>; + bits = <6 6>; + }; + + tsens_s4_p2: s4-p2@dd { + reg = <0xdd 0x2>; + bits = <4 6>; + }; + + tsens_s5_p2: s5-p2@de { + reg = <0xde 0x2>; + bits = <2 6>; + }; + + tsens_s6_p2: s6-p2@df { + reg = <0xdf 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2: s7-p2@e0 { + reg = <0xe0 0x1>; + bits = <0 6>; + }; + + tsens_s8_p2: s8-p2@e0 { + reg = <0xe0 0x2>; + bits = <6 6>; + }; + + tsens_s9_p2: s9-p2@e1 { + reg = <0xe1 0x2>; + bits = <4 6>; + }; + + tsens_s10_p2: s10_p2@e2 { + reg = <0xe2 0x2>; + bits = <2 6>; + }; + + tsens_s5_p2_backup: s5-p2_backup@e3 { + reg = <0xe3 0x2>; + bits = <0 6>; + }; + + tsens_mode_backup: mode_backup@e3 { + reg = <0xe3 0x1>; + bits = <6 2>; + }; + + tsens_s6_p2_backup: s6-p2_backup@e4 { + reg = <0xe4 0x1>; + bits = <0 6>; + }; + + tsens_s7_p2_backup: s7-p2_backup@e4 { + reg = <0xe4 0x2>; + bits = <6 6>; + }; + + tsens_s8_p2_backup: s8-p2_backup@e5 { + reg = <0xe5 0x2>; + bits = <4 6>; + }; + + tsens_s9_p2_backup: s9-p2_backup@e6 { + reg = <0xe6 0x2>; + bits = <2 6>; + }; + + tsens_s10_p2_backup: s10_p2_backup@e7 { + reg = <0xe7 0x1>; + bits = <0 6>; + }; + + tsens_base1_backup: base1_backup@440 { + reg = <0x440 0x1>; + bits = <0 8>; + }; + + tsens_s0_p1_backup: s0-p1_backup@441 { + reg = <0x441 0x1>; + bits = <0 6>; + }; + + tsens_s1_p1_backup: s1-p1_backup@442 { + reg = <0x441 0x2>; + bits = <6 6>; + }; + + tsens_s2_p1_backup: s2-p1_backup@442 { + reg = <0x442 0x2>; + bits = <4 6>; + }; + + tsens_s3_p1_backup: s3-p1_backup@443 { + reg = <0x443 0x1>; + bits = <2 6>; + }; + + tsens_s4_p1_backup: s4-p1_backup@444 { + reg = <0x444 0x1>; + bits = <0 6>; + }; + + tsens_s5_p1_backup: s5-p1_backup@444 { + reg = <0x444 0x2>; + bits = <6 6>; + }; + + tsens_s6_p1_backup: s6-p1_backup@445 { + reg = <0x445 0x2>; + bits = <4 6>; + }; + + tsens_s7_p1_backup: s7-p1_backup@446 { + reg = <0x446 0x1>; + bits = <2 6>; + }; + + tsens_use_backup: use_backup@447 { + reg = <0x447 0x1>; + bits = <5 3>; }; - tsens_backup: backup@440 { - reg = <0x440 0x10>; + + tsens_s8_p1_backup: s8-p1_backup@448 { + reg = <0x448 0x1>; + bits = <0 6>; + }; + + tsens_s9_p1_backup: s9-p1_backup@448 { + reg = <0x448 0x2>; + bits = <6 6>; + }; + + tsens_s10_p1_backup: s10_p1_backup@449 { + reg = <0x449 0x2>; + bits = <4 6>; + }; + + tsens_base2_backup: base2_backup@44a { + reg = <0x44a 0x2>; + bits = <2 8>; + }; + + tsens_s0_p2_backup: s0-p2_backup@44b { + reg = <0x44b 0x3>; + bits = <2 6>; + }; + + tsens_s1_p2_backup: s1-p2_backup@44c { + reg = <0x44c 0x1>; + bits = <0 6>; + }; + + tsens_s2_p2_backup: s2-p2_backup@44c { + reg = <0x44c 0x2>; + bits = <6 6>; + }; + + tsens_s3_p2_backup: s3-p2_backup@44d { + reg = <0x44d 0x2>; + bits = <4 6>; + }; + + tsens_s4_p2_backup: s4-p2_backup@44e { + reg = <0x44e 0x1>; + bits = <2 6>; }; }; @@ -1523,9 +1831,33 @@ #reset-cells = <1>; #power-domain-cells = <1>; reg = <0xfd8c0000 0x6000>; - }; - - mdss: mdss@fd900000 { + clocks = <&xo_board>, + <&gcc GCC_MMSS_GPLL0_CLK_SRC>, + <&gcc GPLL0_VOTE>, + <&gcc GPLL1_VOTE>, + <&rpmcc RPM_SMD_GFX3D_CLK_SRC>, + <&dsi0_phy 1>, + <&dsi0_phy 0>, + <&dsi1_phy 1>, + <&dsi1_phy 0>, + <0>, + <0>, + <0>; + clock-names = "xo", + "mmss_gpll0_vote", + "gpll0_vote", + "gpll1_vote", + "gfx3d_clk_src", + "dsi0pll", + "dsi0pllbyte", + "dsi1pll", + "dsi1pllbyte", + "hdmipll", + "edp_link_clk", + "edp_vco_div"; + }; + + mdss: display-subsystem@fd900000 { compatible = "qcom,mdss"; reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; reg-names = "mdss_phys", "vbif_phys"; @@ -1548,8 +1880,8 @@ #size-cells = <1>; ranges; - mdp: mdp@fd900000 { - compatible = "qcom,mdp5"; + mdp: display-controller@fd900000 { + compatible = "qcom,msm8974-mdp5", "qcom,mdp5"; reg = <0xfd900100 0x22000>; reg-names = "mdp_phys"; @@ -1575,11 +1907,19 @@ remote-endpoint = <&dsi0_in>; }; }; + + port@1 { + reg = <1>; + mdp5_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; }; }; dsi0: dsi@fd922800 { - compatible = "qcom,mdss-dsi-ctrl"; + compatible = "qcom,msm8974-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; reg = <0xfd922800 0x1f8>; reg-names = "dsi_ctrl"; @@ -1647,6 +1987,77 @@ status = "disabled"; }; + + dsi1: dsi@fd922e00 { + compatible = "qcom,msm8974-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0xfd922e00 0x1f8>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + assigned-clocks = <&mmcc BYTE1_CLK_SRC>, <&mmcc PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE1_CLK>, + <&mmcc MDSS_PCLK1_CLK>, + <&mmcc MDSS_ESC1_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core", + "core_mmss"; + + phys = <&dsi1_phy>; + + status = "disabled"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&mdp5_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@fd923000 { + compatible = "qcom,dsi-phy-28nm-hpm"; + reg = <0xfd923000 0xd4>, + <0xfd923100 0x280>, + <0xfd923380 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, <&xo_board>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; }; cci: cci@fda0c000 { diff --git a/arch/arm/boot/dts/qcom-msm8974pro-oneplus-bacon.dts b/arch/arm/boot/dts/qcom-msm8974pro-oneplus-bacon.dts index b5606623f968396da884f210140f4d396e5b8ca6..8d2a054d8feed72afa744122f73b3ff94275a861 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-oneplus-bacon.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-oneplus-bacon.dts @@ -19,6 +19,38 @@ chosen { stdout-path = "serial0:115200n8"; }; + + gpio-keys { + compatible = "gpio-keys"; + + pinctrl-0 = <&gpio_keys_default>, <&gpio_hall_sensor_default>; + pinctrl-names = "default"; + + key-volume-down { + label = "Volume Down"; + gpios = <&pm8941_gpios 2 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&pm8941_gpios 5 GPIO_ACTIVE_LOW>; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + + event-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&tlmm 68 GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + debounce-interval = <150>; + }; + }; }; &blsp1_i2c1 { @@ -67,6 +99,49 @@ syna,clip-y-high = <1920>; }; }; + + led-controller@36 { + compatible = "ti,lm3630a"; + reg = <0x36>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + led-sources = <0 1>; + label = "lcd-backlight"; + default-brightness = <80>; + }; + }; + + led-controller@68 { + compatible = "si-en,sn3193"; + reg = <0x68>; + + shutdown-gpios = <&tlmm 45 GPIO_ACTIVE_HIGH>; + + #address-cells = <1>; + #size-cells = <0>; + + led@1 { + reg = <1>; + label = "red:status"; + led-max-microamp = <17500>; + }; + + led@2 { + reg = <2>; + label = "green:status"; + led-max-microamp = <17500>; + }; + + led@3 { + reg = <3>; + label = "blue:status"; + led-max-microamp = <17500>; + }; + }; }; &blsp1_i2c6 { @@ -95,6 +170,20 @@ status = "okay"; }; +&pm8941_gpios { + gpio_keys_default: gpio-keys-active-state { + pins = "gpio2", "gpio5"; + function = "normal"; + input-enable; + bias-disable; + power-source = ; + }; +}; + +&pm8941_vib { + status = "okay"; +}; + &pronto { vddmx-supply = <&pm8841_s1>; vddcx-supply = <&pm8841_s2>; @@ -345,6 +434,13 @@ }; &tlmm { + gpio_hall_sensor_default: gpio-hall-sensor-default-state { + pins = "gpio68"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + sdc1_on: sdc1-on-state { clk-pins { pins = "sdc1_clk"; diff --git a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts index 3b1cc39f22691057b106b340f747736e646c0a79..04bc58d87abf9c4948a5d025882ce6ec1e511705 100644 --- a/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts +++ b/arch/arm/boot/dts/qcom-msm8974pro-sony-xperia-shinano-castor.dts @@ -123,7 +123,7 @@ pinctrl-names = "default"; pinctrl-0 = <&ts_int_pin>; - syna,startup-delay-ms = <10>; + syna,startup-delay-ms = <100>; rmi-f01@1 { reg = <0x1>; @@ -294,8 +294,43 @@ }; }; +&remoteproc_adsp { + cx-supply = <&pm8841_s2>; +}; + +&remoteproc_mss { + cx-supply = <&pm8841_s2>; + mss-supply = <&pm8841_s3>; + mx-supply = <&pm8841_s1>; + pll-supply = <&pm8941_l12>; +}; + &rpm_requests { regulators-0 { + compatible = "qcom,rpm-pm8841-regulators"; + + pm8841_s1: s1 { + regulator-min-microvolt = <675000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s2: s2 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s3: s3 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + + pm8841_s4: s4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <1050000>; + }; + }; + + regulators-1 { compatible = "qcom,rpm-pm8941-regulators"; vdd_l1_l3-supply = <&pm8941_s1>; @@ -516,6 +551,7 @@ qcom,fast-charge-safe-current = <1500000>; qcom,fast-charge-current-limit = <1500000>; qcom,dc-current-limit = <1800000>; + usb-charge-current-limit = <1800000>; qcom,fast-charge-safe-voltage = <4400000>; qcom,fast-charge-high-threshold-voltage = <4350000>; qcom,fast-charge-low-threshold-voltage = <3400000>; diff --git a/arch/arm/boot/dts/qcom-pm8226.dtsi b/arch/arm/boot/dts/qcom-pm8226.dtsi index eb36d36624648a8d48dc41eb4d7956004b49e2c2..46ba84f86c9f180d4cd893822a3be63cb971326b 100644 --- a/arch/arm/boot/dts/qcom-pm8226.dtsi +++ b/arch/arm/boot/dts/qcom-pm8226.dtsi @@ -1,7 +1,8 @@ // SPDX-License-Identifier: BSD-3-Clause +#include +#include #include #include -#include &spmi_bus { pm8226_0: pm8226@0 { @@ -10,12 +11,25 @@ #address-cells = <1>; #size-cells = <0>; - pwrkey@800 { - compatible = "qcom,pm8941-pwrkey"; + pon@800 { + compatible = "qcom,pm8916-pon"; reg = <0x800>; - interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; - debounce = <15625>; - bias-pull-up; + + pwrkey { + compatible = "qcom,pm8941-pwrkey"; + interrupts = <0x0 0x8 0 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + linux,code = ; + }; + + pm8226_resin: resin { + compatible = "qcom,pm8941-resin"; + interrupts = <0x0 0x8 1 IRQ_TYPE_EDGE_BOTH>; + debounce = <15625>; + bias-pull-up; + status = "disabled"; + }; }; smbb: charger@1000 { @@ -41,13 +55,6 @@ chg_otg: otg-vbus { }; }; - rtc@6000 { - compatible = "qcom,pm8941-rtc"; - reg = <0x6000>, <0x6100>; - reg-names = "rtc", "alarm"; - interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; - }; - pm8226_vadc: adc@3100 { compatible = "qcom,spmi-vadc"; reg = <0x3100>; @@ -81,6 +88,19 @@ }; }; + pm8226_iadc: adc@3600 { + compatible = "qcom,pm8226-iadc", "qcom,spmi-iadc"; + reg = <0x3600>; + interrupts = <0x0 0x36 0x0 IRQ_TYPE_EDGE_RISING>; + }; + + rtc@6000 { + compatible = "qcom,pm8941-rtc"; + reg = <0x6000>, <0x6100>; + reg-names = "rtc", "alarm"; + interrupts = <0x0 0x61 0x1 IRQ_TYPE_EDGE_RISING>; + }; + pm8226_mpps: mpps@a000 { compatible = "qcom,pm8226-mpp", "qcom,spmi-mpp"; reg = <0xa000>; diff --git a/arch/arm/boot/dts/qcom-pm8941.dtsi b/arch/arm/boot/dts/qcom-pm8941.dtsi index cd957a1e7cdf7175702184f15b0e42345458d298..a821f0368a28921dedc25bb05de8c2c1da8a282c 100644 --- a/arch/arm/boot/dts/qcom-pm8941.dtsi +++ b/arch/arm/boot/dts/qcom-pm8941.dtsi @@ -161,6 +161,12 @@ status = "disabled"; }; + pm8941_vib: vibrator@c000 { + compatible = "qcom,pm8916-vib"; + reg = <0xc000>; + status = "disabled"; + }; + pm8941_wled: wled@d800 { compatible = "qcom,pm8941-wled"; reg = <0xd800>; diff --git a/arch/arm/boot/dts/qcom-sdx55-mtp.dts b/arch/arm/boot/dts/qcom-sdx55-mtp.dts index 9649c1e11311b2434c3bbf5f2f24fc29523a3377..7e97ad5803d87ba86b2538f3fe5a3d1d8f3b7121 100644 --- a/arch/arm/boot/dts/qcom-sdx55-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx55-mtp.dts @@ -75,7 +75,7 @@ }; &apps_rsc { - pmx55-rpmh-regulators { + regulators-0 { compatible = "qcom,pmx55-rpmh-regulators"; qcom,pmic-id = "e"; @@ -229,6 +229,10 @@ }; }; +&remoteproc_mpss { + memory-region = <&mpss_adsp_mem>; +}; + &usb { status = "okay"; }; diff --git a/arch/arm/boot/dts/qcom-sdx55-t55.dts b/arch/arm/boot/dts/qcom-sdx55-t55.dts index 7ed8feb99afbe1f9d9423ce79758d3e5f93c4ac6..d5343bb0daee06aaeda21a199e52f97e5037766c 100644 --- a/arch/arm/boot/dts/qcom-sdx55-t55.dts +++ b/arch/arm/boot/dts/qcom-sdx55-t55.dts @@ -98,7 +98,7 @@ }; &apps_rsc { - pmx55-rpmh-regulators { + regulators-0 { compatible = "qcom,pmx55-rpmh-regulators"; qcom,pmic-id = "e"; @@ -233,21 +233,21 @@ }; &blsp1_uart3 { - status = "ok"; + status = "okay"; }; &ipa { - status = "okay"; - + qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; + status = "okay"; }; &qpic_bam { - status = "ok"; + status = "okay"; }; &qpic_nand { - status = "ok"; + status = "okay"; nand@0 { reg = <0>; diff --git a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts index ac8b4626ae9accd09e43f8380115587cef2e45aa..ad74ecc2a196e56485b81f7eef4e47df52be81b0 100644 --- a/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts +++ b/arch/arm/boot/dts/qcom-sdx55-telit-fn980-tlb.dts @@ -98,7 +98,7 @@ }; &apps_rsc { - pmx55-rpmh-regulators { + regulators-0 { compatible = "qcom,pmx55-rpmh-regulators"; qcom,pmic-id = "e"; @@ -233,13 +233,13 @@ }; &blsp1_uart3 { - status = "ok"; + status = "okay"; }; &ipa { - status = "okay"; - + qcom,gsi-loader = "self"; memory-region = <&ipa_fw_mem>; + status = "okay"; }; &pcie0_phy { @@ -258,11 +258,11 @@ }; &qpic_bam { - status = "ok"; + status = "okay"; }; &qpic_nand { - status = "ok"; + status = "okay"; nand@0 { reg = <0>; diff --git a/arch/arm/boot/dts/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom-sdx55.dtsi index f1c0dab409922ead9a41026946fa1b5c274bff90..df7303c5c843aa9477196d98614ab4ed253d4ce6 100644 --- a/arch/arm/boot/dts/qcom-sdx55.dtsi +++ b/arch/arm/boot/dts/qcom-sdx55.dtsi @@ -62,7 +62,13 @@ }; }; - cpu_opp_table: cpu-opp-table { + firmware { + scm { + compatible = "qcom,scm-sdx55", "qcom,scm"; + }; + }; + + cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; @@ -87,12 +93,6 @@ }; }; - firmware { - scm { - compatible = "qcom,scm-sdx55", "qcom,scm"; - }; - }; - psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -214,7 +214,8 @@ }; usb_hsphy: phy@ff4000 { - compatible = "qcom,usb-snps-hs-7nm-phy"; + compatible = "qcom,sdx55-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; reg = <0x00ff4000 0x114>; status = "disabled"; #phy-cells = <0>; @@ -559,7 +560,7 @@ #gpio-cells = <2>; interrupt-controller; #interrupt-cells = <2>; - gpio-ranges = <&tlmm 0 0 109>; + gpio-ranges = <&tlmm 0 0 108>; }; sram@1468f000 { @@ -578,7 +579,7 @@ }; apps_smmu: iommu@15000000 { - compatible = "qcom,sdx55-smmu-500", "arm,mmu-500"; + compatible = "qcom,sdx55-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x15000000 0x20000>; #iommu-cells = <2>; #global-interrupts = <1>; diff --git a/arch/arm/boot/dts/qcom-sdx65-mtp.dts b/arch/arm/boot/dts/qcom-sdx65-mtp.dts index 85ea02d8362d40ef1c1b7066a4f7af3eff98b9c4..ed98c83c141fcaf980392aafdaee1315ff2831b9 100644 --- a/arch/arm/boot/dts/qcom-sdx65-mtp.dts +++ b/arch/arm/boot/dts/qcom-sdx65-mtp.dts @@ -65,7 +65,7 @@ }; &apps_rsc { - pmx65-rpmh-regulators { + regulators-0 { compatible = "qcom,pmx65-rpmh-regulators"; qcom,pmic-id = "b"; diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index b073e0c63df4f945ef32b84e6839ac2a15e89427..192f9f94bc8b4cedacf145a80d3e38f9f6ba62ec 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -61,7 +61,19 @@ }; }; - cpu_opp_table: cpu-opp-table { + firmware { + scm { + compatible = "qcom,scm-sdx65", "qcom,scm"; + }; + }; + + mc_virt: interconnect-mc-virt { + compatible = "qcom,sdx65-mc-virt"; + #interconnect-cells = <1>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; @@ -86,18 +98,6 @@ }; }; - firmware { - scm { - compatible = "qcom,scm-sdx65", "qcom,scm"; - }; - }; - - mc_virt: interconnect-mc-virt { - compatible = "qcom,sdx65-mc-virt"; - #interconnect-cells = <1>; - qcom,bcm-voters = <&apps_bcm_voter>; - }; - psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -219,7 +219,8 @@ }; usb_hsphy: phy@ff4000 { - compatible = "qcom,usb-snps-hs-7nm-phy"; + compatible = "qcom,sdx65-usb-hs-phy", + "qcom,usb-snps-hs-7nm-phy"; reg = <0xff4000 0x120>; #phy-cells = <0>; status = "disabled"; @@ -455,7 +456,7 @@ }; apps_smmu: iommu@15000000 { - compatible = "qcom,sdx65-smmu-500", "arm,mmu-500"; + compatible = "qcom,sdx65-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x15000000 0x40000>; #iommu-cells = <2>; #global-interrupts = <1>; diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts index 4e58c54cde17c382bf56ef058bf8473e985e7566..33ac4bd1e63bd223d79c495330f8ad2293a5b62a 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ca.dts @@ -7,6 +7,9 @@ */ /dts-v1/; + +#include + #include "r8a7742-iwg21d-q7.dts" / { @@ -242,7 +245,7 @@ vin0ep: endpoint { remote-endpoint = <&cam0ep>; bus-width = <8>; - bus-type = <6>; + bus-type = ; }; }; }; @@ -273,7 +276,7 @@ vin1ep: endpoint { remote-endpoint = <&cam1ep>; bus-width = <8>; - bus-type = <6>; + bus-type = ; }; }; }; @@ -305,7 +308,7 @@ remote-endpoint = <&cam2ep>; bus-width = <8>; data-shift = <8>; - bus-type = <6>; + bus-type = ; }; }; }; @@ -335,7 +338,7 @@ vin3ep: endpoint { remote-endpoint = <&cam3ep>; bus-width = <8>; - bus-type = <6>; + bus-type = ; }; }; }; diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi index 40cef0b1d1e6267f469d3777ed92cd2f9c155277..c73160df619de4ad8117fa3b2fa4ba01e4179d14 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov5640-single.dtsi @@ -7,6 +7,8 @@ * Copyright (C) 2020 Renesas Electronics Corp. */ +#include + #define CAM_ENABLED 1 &CAM_PARENT_I2C { @@ -26,7 +28,7 @@ CAM_EP: endpoint { bus-width = <8>; data-shift = <2>; - bus-type = <6>; + bus-type = ; pclk-sample = <1>; remote-endpoint = <&VIN_EP>; }; diff --git a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi index f5e77f02425167205d7366f6af33c71556c1b56d..a7f5cfec64b89da499157d8919a3d39c3932d515 100644 --- a/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi +++ b/arch/arm/boot/dts/r8a7742-iwg21d-q7-dbcm-ov7725-single.dtsi @@ -7,6 +7,8 @@ * Copyright (C) 2020 Renesas Electronics Corp. */ +#include + #define CAM_ENABLED 1 &CAM_PARENT_I2C { @@ -21,7 +23,7 @@ port { CAM_EP: endpoint { bus-width = <8>; - bus-type = <6>; + bus-type = ; remote-endpoint = <&VIN_EP>; }; }; diff --git a/arch/arm/boot/dts/r8a7742.dtsi b/arch/arm/boot/dts/r8a7742.dtsi index 73be346001cb403912437cc2927020c48a9a635d..16d146db824a09e6e0a86ecf9096a5ed5d76639f 100644 --- a/arch/arm/boot/dts/r8a7742.dtsi +++ b/arch/arm/boot/dts/r8a7742.dtsi @@ -1155,7 +1155,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi index 20f1d98a048dc1aff42c12c82e1fb6aa20f5d492..2245d19a23bb0a8b0e5b76ed14b59f14a56fb61e 100644 --- a/arch/arm/boot/dts/r8a7743.dtsi +++ b/arch/arm/boot/dts/r8a7743.dtsi @@ -1190,7 +1190,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm/boot/dts/r8a7744.dtsi b/arch/arm/boot/dts/r8a7744.dtsi index 96b2d5a4e8f64bd698f39e719a15e04a7bdb0c36..aa13841f978149bf0ce09baf6a47eeedad8646db 100644 --- a/arch/arm/boot/dts/r8a7744.dtsi +++ b/arch/arm/boot/dts/r8a7744.dtsi @@ -1190,7 +1190,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm/boot/dts/r8a7745.dtsi b/arch/arm/boot/dts/r8a7745.dtsi index afc902e532d8d45a4352287731b6b3d398fcbc6c..44688b8431c3f7b32daedac125ae8ca7222388c7 100644 --- a/arch/arm/boot/dts/r8a7745.dtsi +++ b/arch/arm/boot/dts/r8a7745.dtsi @@ -1120,7 +1120,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi index 95efbafb0b7077a2977069a87e15bbb7682364d3..8d4530ed2fc6ad15c1b5f155edb814b06d9ae676 100644 --- a/arch/arm/boot/dts/r8a7778.dtsi +++ b/arch/arm/boot/dts/r8a7778.dtsi @@ -241,7 +241,7 @@ rcar_sound: sound@ffd90000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi index 111a6d23159e99c538b39087140ca781260d5b35..2f2e483a2c2ac7f16654bf81915ce6adc95c6f43 100644 --- a/arch/arm/boot/dts/r8a7790.dtsi +++ b/arch/arm/boot/dts/r8a7790.dtsi @@ -1109,7 +1109,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi index 777b672b59cc2707710a4008c8a180ceccc73e5d..b9d34147628e120125fe85f451c666cc55442bf1 100644 --- a/arch/arm/boot/dts/r8a7791.dtsi +++ b/arch/arm/boot/dts/r8a7791.dtsi @@ -1223,7 +1223,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi index 3e0be1b589314b8c3895002b0cacc863c8ab0d5b..f51bf687f4bd55d3e40bbc70fa3601dad9ca45a3 100644 --- a/arch/arm/boot/dts/r8a7793.dtsi +++ b/arch/arm/boot/dts/r8a7793.dtsi @@ -988,7 +988,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index 7aa781ff3bff695234c0c0d072e5d52bd6398c5a..371dd4715ddef83d9486564a87830e4684a752ea 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -955,7 +955,7 @@ rcar_sound: sound@ec500000 { /* - * #sound-dai-cells is required + * #sound-dai-cells is required if simple-card * * Single DAI : #sound-dai-cells = <0>; <&rcar_sound>; * Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>; diff --git a/arch/arm/boot/dts/r9a06g032.dtsi b/arch/arm/boot/dts/r9a06g032.dtsi index 41e19c0986ce6e6b38f5c6193da09b3d49a363bb..0fa565a1c3ad3903b23b1be8e1da3fe26e400fe1 100644 --- a/arch/arm/boot/dts/r9a06g032.dtsi +++ b/arch/arm/boot/dts/r9a06g032.dtsi @@ -117,6 +117,18 @@ }; }; + udc: usb@4001e000 { + compatible = "renesas,r9a06g032-usbf", "renesas,rzn1-usbf"; + reg = <0x4001e000 0x2000>; + interrupts = , + ; + clocks = <&sysctrl R9A06G032_HCLK_USBF>, + <&sysctrl R9A06G032_HCLK_USBPM>; + clock-names = "hclkf", "hclkpm"; + power-domains = <&sysctrl>; + status = "disabled"; + }; + pci_usb: pci@40030000 { compatible = "renesas,pci-r9a06g032", "renesas,pci-rzn1"; device_type = "pci"; diff --git a/arch/arm/boot/dts/rk3066a-mk808.dts b/arch/arm/boot/dts/rk3066a-mk808.dts index 2db5ba7062086c3d6c08ebd9363c6215ca1ff911..06790f05b39537648c38b10ad6a4d9783b4bb076 100644 --- a/arch/arm/boot/dts/rk3066a-mk808.dts +++ b/arch/arm/boot/dts/rk3066a-mk808.dts @@ -157,7 +157,14 @@ pinctrl-0 = <&sd1_clk &sd1_cmd &sd1_bus4>; pinctrl-names = "default"; vmmc-supply = <&vcc_wifi>; + #address-cells = <1>; + #size-cells = <0>; status = "okay"; + + brcmf: wifi@1 { + compatible = "brcm,bcm4329-fmac"; + reg = <1>; + }; }; &nfc { diff --git a/arch/arm/boot/dts/rk3128-evb.dts b/arch/arm/boot/dts/rk3128-evb.dts new file mode 100644 index 0000000000000000000000000000000000000000..c38f42497cbd9eb8432dbcf7736fae37b273d7aa --- /dev/null +++ b/arch/arm/boot/dts/rk3128-evb.dts @@ -0,0 +1,109 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ + +/dts-v1/; + +#include "rk3128.dtsi" + +/ { + model = "Rockchip RK3128 Evaluation board"; + compatible = "rockchip,rk3128-evb", "rockchip,rk3128"; + + aliases { + gpio0 = &gpio0; + gpio1 = &gpio1; + gpio2 = &gpio2; + gpio3 = &gpio3; + i2c1 = &i2c1; + mmc0 = &emmc; + }; + + chosen { + stdout-path = &uart2; + }; + + memory@60000000 { + device_type = "memory"; + reg = <0x60000000 0x40000000>; + }; + + vcc5v0_otg: vcc5v0-otg-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio0 26 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&otg_vbus_drv>; + regulator-name = "vcc5v0_otg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vcc5v0_host: vcc5v0-host-regulator { + compatible = "regulator-fixed"; + gpio = <&gpio2 23 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&host_vbus_drv>; + regulator-name = "vcc5v0_host"; + regulator-always-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&emmc { + bus-width = <8>; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>; + status = "okay"; +}; + +&i2c1 { + status = "okay"; + + hym8563: rtc@51 { + compatible = "haoyu,hym8563"; + reg = <0x51>; + #clock-cells = <0>; + clock-output-names = "xin32k"; + }; +}; + +&usb2phy { + status = "okay"; +}; + +&usb2phy_host { + status = "okay"; +}; + +&usb2phy_otg { + status = "okay"; +}; + +&usb_host_ehci { + status = "okay"; +}; + +&usb_host_ohci { + status = "okay"; +}; + +&usb_otg { + vbus-supply = <&vcc5v0_otg>; + status = "okay"; +}; + +&pinctrl { + usb-host { + host_vbus_drv: host-vbus-drv { + rockchip,pins = <2 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + usb-otg { + otg_vbus_drv: otg-vbus-drv { + rockchip,pins = <0 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rk3128.dtsi b/arch/arm/boot/dts/rk3128.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..b63bd4ad3143c5467e315e2830c109d535fc49ef --- /dev/null +++ b/arch/arm/boot/dts/rk3128.dtsi @@ -0,0 +1,916 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2017 Rockchip Electronics Co., Ltd + */ + +#include +#include +#include +#include +#include + +/ { + compatible = "rockchip,rk3128"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + clock-latency = <40000>; + clocks = <&cru ARMCLK>; + operating-points = < + /* KHz uV */ + 816000 1000000 + >; + #cooling-cells = <2>; /* min followed by max */ + }; + + cpu1: cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + }; + + cpu2: cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + }; + + cpu3: cpu@f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + }; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + ; + arm,cpu-registers-not-fw-configured; + clock-frequency = <24000000>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + pmu: syscon@100a0000 { + compatible = "rockchip,rk3128-pmu", "syscon", "simple-mfd"; + reg = <0x100a0000 0x1000>; + }; + + gic: interrupt-controller@10139000 { + compatible = "arm,cortex-a7-gic"; + reg = <0x10139000 0x1000>, + <0x1013a000 0x1000>, + <0x1013c000 0x2000>, + <0x1013e000 0x2000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + }; + + usb_otg: usb@10180000 { + compatible = "rockchip,rk3128-usb", "rockchip,rk3066-usb", "snps,dwc2"; + reg = <0x10180000 0x40000>; + interrupts = ; + clocks = <&cru HCLK_OTG>; + clock-names = "otg"; + dr_mode = "otg"; + phys = <&usb2phy_otg>; + phy-names = "usb2-phy"; + status = "disabled"; + }; + + usb_host_ehci: usb@101c0000 { + compatible = "generic-ehci"; + reg = <0x101c0000 0x20000>; + interrupts = ; + phys = <&usb2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + + usb_host_ohci: usb@101e0000 { + compatible = "generic-ohci"; + reg = <0x101e0000 0x20000>; + interrupts = ; + phys = <&usb2phy_host>; + phy-names = "usb"; + status = "disabled"; + }; + + sdmmc: mmc@10214000 { + compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x10214000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + dmas = <&pdma 10>; + dma-names = "rx-tx"; + fifo-depth = <256>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMC>; + reset-names = "reset"; + status = "disabled"; + }; + + sdio: mmc@10218000 { + compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x10218000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + dmas = <&pdma 11>; + dma-names = "rx-tx"; + fifo-depth = <256>; + max-frequency = <150000000>; + resets = <&cru SRST_SDIO>; + reset-names = "reset"; + status = "disabled"; + }; + + emmc: mmc@1021c000 { + compatible = "rockchip,rk3128-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x1021c000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + dmas = <&pdma 12>; + dma-names = "rx-tx"; + fifo-depth = <256>; + max-frequency = <150000000>; + resets = <&cru SRST_EMMC>; + reset-names = "reset"; + status = "disabled"; + }; + + nfc: nand-controller@10500000 { + compatible = "rockchip,rk3128-nfc", "rockchip,rk2928-nfc"; + reg = <0x10500000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_NANDC>, <&cru SCLK_NANDC>; + clock-names = "ahb", "nfc"; + pinctrl-names = "default"; + pinctrl-0 = <&flash_ale &flash_bus8 &flash_cle &flash_cs0 + &flash_dqs &flash_rdn &flash_rdy &flash_wrn>; + status = "disabled"; + }; + + cru: clock-controller@20000000 { + compatible = "rockchip,rk3128-cru"; + reg = <0x20000000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + assigned-clocks = <&cru PLL_GPLL>; + assigned-clock-rates = <594000000>; + }; + + grf: syscon@20008000 { + compatible = "rockchip,rk3128-grf", "syscon", "simple-mfd"; + reg = <0x20008000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + usb2phy: usb2phy@17c { + compatible = "rockchip,rk3128-usb2phy"; + reg = <0x017c 0x0c>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + clock-output-names = "usb480m_phy"; + #clock-cells = <0>; + status = "disabled"; + + usb2phy_host: host-port { + interrupts = ; + interrupt-names = "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + + usb2phy_otg: otg-port { + interrupts = , + , + ; + interrupt-names = "otg-bvalid", "otg-id", + "linestate"; + #phy-cells = <0>; + status = "disabled"; + }; + }; + }; + + timer0: timer@20044000 { + compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; + reg = <0x20044000 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; + }; + + timer1: timer@20044020 { + compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; + reg = <0x20044020 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; + }; + + timer2: timer@20044040 { + compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; + reg = <0x20044040 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; + }; + + timer3: timer@20044060 { + compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; + reg = <0x20044060 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; + }; + + timer4: timer@20044080 { + compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; + reg = <0x20044080 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; + }; + + timer5: timer@200440a0 { + compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer"; + reg = <0x200440a0 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&xin24m>; + clock-names = "pclk", "timer"; + }; + + watchdog: watchdog@2004c000 { + compatible = "rockchip,rk3128-wdt", "snps,dw-wdt"; + reg = <0x2004c000 0x100>; + interrupts = ; + clocks = <&cru PCLK_WDT>; + status = "disabled"; + }; + + pwm0: pwm@20050000 { + compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; + reg = <0x20050000 0x10>; + clocks = <&cru PCLK_PWM>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm1: pwm@20050010 { + compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; + reg = <0x20050010 0x10>; + clocks = <&cru PCLK_PWM>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm1_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm2: pwm@20050020 { + compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; + reg = <0x20050020 0x10>; + clocks = <&cru PCLK_PWM>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm2_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + pwm3: pwm@20050030 { + compatible = "rockchip,rk3128-pwm", "rockchip,rk3288-pwm"; + reg = <0x20050030 0x10>; + clocks = <&cru PCLK_PWM>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm3_pin>; + #pwm-cells = <3>; + status = "disabled"; + }; + + i2c1: i2c@20056000 { + compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; + reg = <0x20056000 0x1000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C1>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@2005a000 { + compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; + reg = <0x2005a000 0x1000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C2>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@2005e000 { + compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; + reg = <0x2005e000 0x1000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C3>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart0: serial@20060000 { + compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; + reg = <0x20060000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&pdma 2>, <&pdma 3>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart1: serial@20064000 { + compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; + reg = <0x20064000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&pdma 4>, <&pdma 5>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_xfer>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + uart2: serial@20068000 { + compatible = "rockchip,rk3128-uart", "snps,dw-apb-uart"; + reg = <0x20068000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&pdma 6>, <&pdma 7>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_xfer>; + reg-io-width = <4>; + reg-shift = <2>; + status = "disabled"; + }; + + saradc: saradc@2006c000 { + compatible = "rockchip,saradc"; + reg = <0x2006c000 0x100>; + interrupts = ; + clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC>; + reset-names = "saradc-apb"; + #io-channel-cells = <1>; + status = "disabled"; + }; + + i2c0: i2c@20072000 { + compatible = "rockchip,rk3128-i2c", "rockchip,rk3288-i2c"; + reg = <20072000 0x1000>; + interrupts = ; + clock-names = "i2c"; + clocks = <&cru PCLK_I2C0>; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@20074000 { + compatible = "rockchip,rk3128-spi", "rockchip,rk3066-spi"; + reg = <0x20074000 0x1000>; + interrupts = ; + clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>; + clock-names = "spiclk", "apb_pclk"; + dmas = <&pdma 8>, <&pdma 9>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&spi0_tx &spi0_rx &spi0_clk &spi0_cs0 &spi0_cs1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pdma: dma-controller@20078000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0x20078000 0x4000>; + interrupts = , + ; + arm,pl330-broken-no-flushp; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + #dma-cells = <1>; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rk3128-pinctrl"; + rockchip,grf = <&grf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@2007c000 { + compatible = "rockchip,gpio-bank"; + reg = <0x2007c000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@20080000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20080000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@20084000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20084000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@20088000 { + compatible = "rockchip,gpio-bank"; + reg = <0x20088000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + pcfg_pull_default: pcfg-pull-default { + bias-pull-pin-default; + }; + + pcfg_pull_none: pcfg-pull-none { + bias-disable; + }; + + emmc { + emmc_clk: emmc-clk { + rockchip,pins = <2 RK_PA7 2 &pcfg_pull_none>; + }; + + emmc_cmd: emmc-cmd { + rockchip,pins = <1 RK_PC6 2 &pcfg_pull_default>; + }; + + emmc_cmd1: emmc-cmd1 { + rockchip,pins = <2 RK_PA4 2 &pcfg_pull_default>; + }; + + emmc_pwr: emmc-pwr { + rockchip,pins = <2 RK_PA5 2 &pcfg_pull_default>; + }; + + emmc_bus1: emmc-bus1 { + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>; + }; + + emmc_bus4: emmc-bus4 { + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, + <1 RK_PD1 2 &pcfg_pull_default>, + <1 RK_PD2 2 &pcfg_pull_default>, + <1 RK_PD3 2 &pcfg_pull_default>; + }; + + emmc_bus8: emmc-bus8 { + rockchip,pins = <1 RK_PD0 2 &pcfg_pull_default>, + <1 RK_PD1 2 &pcfg_pull_default>, + <1 RK_PD2 2 &pcfg_pull_default>, + <1 RK_PD3 2 &pcfg_pull_default>, + <1 RK_PD4 2 &pcfg_pull_default>, + <1 RK_PD5 2 &pcfg_pull_default>, + <1 RK_PD6 2 &pcfg_pull_default>, + <1 RK_PD7 2 &pcfg_pull_default>; + }; + }; + + gmac { + rgmii_pins: rgmii-pins { + rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, + <2 RK_PB1 3 &pcfg_pull_default>, + <2 RK_PB3 3 &pcfg_pull_default>, + <2 RK_PB4 3 &pcfg_pull_default>, + <2 RK_PB5 3 &pcfg_pull_default>, + <2 RK_PB6 3 &pcfg_pull_default>, + <2 RK_PC0 3 &pcfg_pull_default>, + <2 RK_PC1 3 &pcfg_pull_default>, + <2 RK_PC2 3 &pcfg_pull_default>, + <2 RK_PC3 3 &pcfg_pull_default>, + <2 RK_PD1 3 &pcfg_pull_default>, + <2 RK_PC4 4 &pcfg_pull_default>, + <2 RK_PC5 4 &pcfg_pull_default>, + <2 RK_PC6 4 &pcfg_pull_default>, + <2 RK_PC7 4 &pcfg_pull_default>; + }; + + rmii_pins: rmii-pins { + rockchip,pins = <2 RK_PB0 3 &pcfg_pull_default>, + <2 RK_PB4 3 &pcfg_pull_default>, + <2 RK_PB5 3 &pcfg_pull_default>, + <2 RK_PB6 3 &pcfg_pull_default>, + <2 RK_PB7 3 &pcfg_pull_default>, + <2 RK_PC0 3 &pcfg_pull_default>, + <2 RK_PC1 3 &pcfg_pull_default>, + <2 RK_PC2 3 &pcfg_pull_default>, + <2 RK_PC3 3 &pcfg_pull_default>, + <2 RK_PD1 3 &pcfg_pull_default>; + }; + }; + + hdmi { + hdmii2c_xfer: hdmii2c-xfer { + rockchip,pins = <0 RK_PA6 2 &pcfg_pull_none>, + <0 RK_PA7 2 &pcfg_pull_none>; + }; + + hdmi_hpd: hdmi-hpd { + rockchip,pins = <0 RK_PB7 1 &pcfg_pull_none>; + }; + + hdmi_cec: hdmi-cec { + rockchip,pins = <0 RK_PC4 1 &pcfg_pull_none>; + }; + }; + + i2c0 { + i2c0_xfer: i2c0-xfer { + rockchip,pins = <0 RK_PA0 1 &pcfg_pull_none>, + <0 RK_PA1 1 &pcfg_pull_none>; + }; + }; + + i2c1 { + i2c1_xfer: i2c1-xfer { + rockchip,pins = <0 RK_PA2 1 &pcfg_pull_none>, + <0 RK_PA3 1 &pcfg_pull_none>; + }; + }; + + i2c2 { + i2c2_xfer: i2c2-xfer { + rockchip,pins = <2 RK_PC4 3 &pcfg_pull_none>, + <2 RK_PC5 3 &pcfg_pull_none>; + }; + }; + + i2c3 { + i2c3_xfer: i2c3-xfer { + rockchip,pins = <0 RK_PA6 1 &pcfg_pull_none>, + <0 RK_PA7 1 &pcfg_pull_none>; + }; + }; + + i2s { + i2s_bus: i2s-bus { + rockchip,pins = <0 RK_PB0 1 &pcfg_pull_none>, + <0 RK_PB1 1 &pcfg_pull_none>, + <0 RK_PB3 1 &pcfg_pull_none>, + <0 RK_PB4 1 &pcfg_pull_none>, + <0 RK_PB5 1 &pcfg_pull_none>, + <0 RK_PB6 1 &pcfg_pull_none>; + }; + + i2s1_bus: i2s1-bus { + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_none>, + <1 RK_PA1 1 &pcfg_pull_none>, + <1 RK_PA2 1 &pcfg_pull_none>, + <1 RK_PA3 1 &pcfg_pull_none>, + <1 RK_PA4 1 &pcfg_pull_none>, + <1 RK_PA5 1 &pcfg_pull_none>; + }; + }; + + lcdc { + lcdc_dclk: lcdc-dclk { + rockchip,pins = <2 RK_PB0 1 &pcfg_pull_none>; + }; + + lcdc_den: lcdc-den { + rockchip,pins = <2 RK_PB3 1 &pcfg_pull_none>; + }; + + lcdc_hsync: lcdc-hsync { + rockchip,pins = <2 RK_PB1 1 &pcfg_pull_none>; + }; + + lcdc_vsync: lcdc-vsync { + rockchip,pins = <2 RK_PB2 1 &pcfg_pull_none>; + }; + + lcdc_rgb24: lcdc-rgb24 { + rockchip,pins = <2 RK_PB4 1 &pcfg_pull_none>, + <2 RK_PB5 1 &pcfg_pull_none>, + <2 RK_PB6 1 &pcfg_pull_none>, + <2 RK_PB7 1 &pcfg_pull_none>, + <2 RK_PC0 1 &pcfg_pull_none>, + <2 RK_PC1 1 &pcfg_pull_none>, + <2 RK_PC2 1 &pcfg_pull_none>, + <2 RK_PC3 1 &pcfg_pull_none>, + <2 RK_PC4 1 &pcfg_pull_none>, + <2 RK_PC5 1 &pcfg_pull_none>, + <2 RK_PC6 1 &pcfg_pull_none>, + <2 RK_PC7 1 &pcfg_pull_none>, + <2 RK_PD0 1 &pcfg_pull_none>, + <2 RK_PD1 1 &pcfg_pull_none>; + }; + }; + + nfc { + flash_ale: flash-ale { + rockchip,pins = <2 RK_PA0 1 &pcfg_pull_none>; + }; + + flash_cle: flash-cle { + rockchip,pins = <2 RK_PA1 1 &pcfg_pull_none>; + }; + + flash_wrn: flash-wrn { + rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>; + }; + + flash_rdn: flash-rdn { + rockchip,pins = <2 RK_PA3 1 &pcfg_pull_none>; + }; + + flash_rdy: flash-rdy { + rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>; + }; + + flash_cs0: flash-cs0 { + rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>; + }; + + flash_dqs: flash-dqs { + rockchip,pins = <2 RK_PA7 1 &pcfg_pull_none>; + }; + + flash_bus8: flash-bus8 { + rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>, + <1 RK_PD1 1 &pcfg_pull_none>, + <1 RK_PD2 1 &pcfg_pull_none>, + <1 RK_PD3 1 &pcfg_pull_none>, + <1 RK_PD4 1 &pcfg_pull_none>, + <1 RK_PD5 1 &pcfg_pull_none>, + <1 RK_PD6 1 &pcfg_pull_none>, + <1 RK_PD7 1 &pcfg_pull_none>; + }; + }; + + pwm0 { + pwm0_pin: pwm0-pin { + rockchip,pins = <0 RK_PD2 1 &pcfg_pull_none>; + }; + }; + + pwm1 { + pwm1_pin: pwm1-pin { + rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>; + }; + }; + + pwm2 { + pwm2_pin: pwm2-pin { + rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>; + }; + }; + + pwm3 { + pwm3_pin: pwm3-pin { + rockchip,pins = <3 RK_PD2 1 &pcfg_pull_none>; + }; + }; + + sdio { + sdio_clk: sdio-clk { + rockchip,pins = <1 RK_PA0 2 &pcfg_pull_none>; + }; + + sdio_cmd: sdio-cmd { + rockchip,pins = <0 RK_PA3 2 &pcfg_pull_default>; + }; + + sdio_pwren: sdio-pwren { + rockchip,pins = <0 RK_PD6 1 &pcfg_pull_default>; + }; + + sdio_bus4: sdio-bus4 { + rockchip,pins = <1 RK_PA1 2 &pcfg_pull_default>, + <1 RK_PA2 2 &pcfg_pull_default>, + <1 RK_PA4 2 &pcfg_pull_default>, + <1 RK_PA5 2 &pcfg_pull_default>; + }; + }; + + sdmmc { + sdmmc_clk: sdmmc-clk { + rockchip,pins = <1 RK_PC0 1 &pcfg_pull_none>; + }; + + sdmmc_cmd: sdmmc-cmd { + rockchip,pins = <1 RK_PB7 1 &pcfg_pull_default>; + }; + + sdmmc_wp: sdmmc-wp { + rockchip,pins = <1 RK_PA7 1 &pcfg_pull_default>; + }; + + sdmmc_pwren: sdmmc-pwren { + rockchip,pins = <1 RK_PB6 1 &pcfg_pull_default>; + }; + + sdmmc_bus4: sdmmc-bus4 { + rockchip,pins = <1 RK_PC2 1 &pcfg_pull_default>, + <1 RK_PC3 1 &pcfg_pull_default>, + <1 RK_PC4 1 &pcfg_pull_default>, + <1 RK_PC5 1 &pcfg_pull_default>; + }; + }; + + spdif { + spdif_tx: spdif-tx { + rockchip,pins = <3 RK_PD3 1 &pcfg_pull_none>; + }; + }; + + spi0 { + spi0_clk: spi0-clk { + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>; + }; + + spi0_cs0: spi0-cs0 { + rockchip,pins = <1 RK_PB3 1 &pcfg_pull_default>; + }; + + spi0_tx: spi0-tx { + rockchip,pins = <1 RK_PB1 1 &pcfg_pull_default>; + }; + + spi0_rx: spi0-rx { + rockchip,pins = <1 RK_PB2 1 &pcfg_pull_default>; + }; + + spi0_cs1: spi0-cs1 { + rockchip,pins = <1 RK_PB4 1 &pcfg_pull_default>; + }; + + spi1_clk: spi1-clk { + rockchip,pins = <2 RK_PA0 2 &pcfg_pull_default>; + }; + + spi1_cs0: spi1-cs0 { + rockchip,pins = <1 RK_PD6 3 &pcfg_pull_default>; + }; + + spi1_tx: spi1-tx { + rockchip,pins = <1 RK_PD5 3 &pcfg_pull_default>; + }; + + spi1_rx: spi1-rx { + rockchip,pins = <1 RK_PD4 3 &pcfg_pull_default>; + }; + + spi1_cs1: spi1-cs1 { + rockchip,pins = <1 RK_PD7 3 &pcfg_pull_default>; + }; + + spi2_clk: spi2-clk { + rockchip,pins = <0 RK_PB1 2 &pcfg_pull_default>; + }; + + spi2_cs0: spi2-cs0 { + rockchip,pins = <0 RK_PB6 2 &pcfg_pull_default>; + }; + + spi2_tx: spi2-tx { + rockchip,pins = <0 RK_PB3 2 &pcfg_pull_default>; + }; + + spi2_rx: spi2-rx { + rockchip,pins = <0 RK_PB5 2 &pcfg_pull_default>; + }; + }; + + uart0 { + uart0_xfer: uart0-xfer { + rockchip,pins = <2 RK_PD2 2 &pcfg_pull_default>, + <2 RK_PD3 2 &pcfg_pull_none>; + }; + + uart0_cts: uart0-cts { + rockchip,pins = <2 RK_PD5 2 &pcfg_pull_none>; + }; + + uart0_rts: uart0-rts { + rockchip,pins = <0 RK_PC1 2 &pcfg_pull_none>; + }; + }; + + uart1 { + uart1_xfer: uart1-xfer { + rockchip,pins = <1 RK_PB1 2 &pcfg_pull_default>, + <1 RK_PB2 2 &pcfg_pull_default>; + }; + + uart1_cts: uart1-cts { + rockchip,pins = <1 RK_PB0 2 &pcfg_pull_none>; + }; + + uart1_rts: uart1-rts { + rockchip,pins = <1 RK_PB3 2 &pcfg_pull_none>; + }; + }; + + uart2 { + uart2_xfer: uart2-xfer { + rockchip,pins = <1 RK_PC2 2 &pcfg_pull_default>, + <1 RK_PC3 2 &pcfg_pull_none>; + }; + + uart2_cts: uart2-cts { + rockchip,pins = <0 RK_PD1 1 &pcfg_pull_none>; + }; + + uart2_rts: uart2-rts { + rockchip,pins = <0 RK_PD0 1 &pcfg_pull_none>; + }; + }; + }; +}; diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index 487b0e03d4b438f49810415ff55bf997cb4abaa0..2ca76b69add78d5858064ac9707cbe34f922ea93 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -1181,6 +1181,7 @@ clock-names = "dp", "pclk"; phys = <&edp_phy>; phy-names = "dp"; + power-domains = <&power RK3288_PD_VIO>; resets = <&cru SRST_EDP>; reset-names = "dp"; rockchip,grf = <&grf>; diff --git a/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts new file mode 100644 index 0000000000000000000000000000000000000000..3340fc3f07393bbc66a3d927e5baa00b8167ad37 --- /dev/null +++ b/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +/dts-v1/; +#include "rv1126.dtsi" +#include "rv1126-edgeble-neu2.dtsi" + +/ { + model = "Edgeble Neu2 IO Board"; + compatible = "edgeble,neural-compute-module-2-io", + "edgeble,neural-compute-module-2", "rockchip,rv1126"; + + aliases { + serial2 = &uart2; + }; + + chosen { + stdout-path = "serial2:1500000n8"; + }; +}; + +&gmac { + assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, + <&cru CLK_GMAC_ETHERNET_OUT>; + assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>; + assigned-clock-rates = <125000000>, <0>, <25000000>; + clock_in_out = "input"; + phy-handle = <&phy>; + phy-mode = "rgmii"; + phy-supply = <&vcc_3v3>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>; + tx_delay = <0x2a>; + rx_delay = <0x1a>; + status = "okay"; +}; + +&mdio { + phy: ethernet-phy@0 { + compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg = <0x0>; + pinctrl-names = "default"; + pinctrl-0 = <ð_phy_rst>; + reset-assert-us = <20000>; + reset-deassert-us = <100000>; + reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>; + }; +}; + +&pinctrl { + ethernet { + eth_phy_rst: eth-phy-rst { + rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_down>; + }; + }; +}; + +&sdmmc { + bus-width = <4>; + cap-mmc-highspeed; + cap-sd-highspeed; + card-detect-delay = <200>; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc0_clk &sdmmc0_cmd &sdmmc0_bus4 &sdmmc0_det>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr104; + vqmmc-supply = <&vccio_sd>; + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; diff --git a/arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi b/arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..cc64ba4be344c3488e16cefcb07ff5ad3fac683f --- /dev/null +++ b/arch/arm/boot/dts/rv1126-edgeble-neu2.dtsi @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Rockchip Electronics Co., Ltd. + * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd. + */ + +/ { + compatible = "edgeble,neural-compute-module-2", "rockchip,rv1126"; + + aliases { + mmc0 = &emmc; + }; + + vcc5v0_sys: vcc5v0-sys-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc5v0_sys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + vccio_flash: vccio-flash-regulator { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&flash_vol_sel>; + regulator-name = "vccio_flash"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + vin-supply = <&vcc_3v3>; + }; + + sdio_pwrseq: pwrseq-sdio { + compatible = "mmc-pwrseq-simple"; + clocks = <&rk809 1>; + clock-names = "ext_clock"; + pinctrl-names = "default"; + pinctrl-0 = <&wifi_enable_h>; + reset-gpios = <&gpio1 RK_PD0 GPIO_ACTIVE_LOW>; + }; +}; + +&cpu0 { + cpu-supply = <&vdd_arm>; +}; + +&emmc { + bus-width = <8>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&emmc_bus8 &emmc_cmd &emmc_clk &emmc_rstnout>; + rockchip,default-sample-phase = <90>; + vmmc-supply = <&vcc_3v3>; + vqmmc-supply = <&vccio_flash>; + status = "okay"; +}; + +&i2c0 { + clock-frequency = <400000>; + status = "okay"; + + rk809: pmic@20 { + compatible = "rockchip,rk809"; + reg = <0x20>; + interrupt-parent = <&gpio0>; + interrupts = ; + #clock-cells = <1>; + clock-output-names = "rk808-clkout1", "rk808-clkout2"; + pinctrl-names = "default"; + pinctrl-0 = <&pmic_int_l>; + rockchip,system-power-controller; + wakeup-source; + + vcc1-supply = <&vcc5v0_sys>; + vcc2-supply = <&vcc5v0_sys>; + vcc3-supply = <&vcc5v0_sys>; + vcc4-supply = <&vcc5v0_sys>; + vcc5-supply = <&vcc_buck5>; + vcc6-supply = <&vcc_buck5>; + vcc7-supply = <&vcc5v0_sys>; + vcc8-supply = <&vcc3v3_sys>; + vcc9-supply = <&vcc5v0_sys>; + + regulators { + vdd_npu_vepu: DCDC_REG1 { + regulator-name = "vdd_npu_vepu"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <950000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vdd_arm: DCDC_REG2 { + regulator-name = "vdd_arm"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <725000>; + regulator-max-microvolt = <1350000>; + regulator-ramp-delay = <6001>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_ddr: DCDC_REG3 { + regulator-name = "vcc_ddr"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-state-mem { + regulator-on-in-suspend; + }; + }; + + vcc3v3_sys: DCDC_REG4 { + regulator-name = "vcc3v3_sys"; + regulator-always-on; + regulator-boot-on; + regulator-initial-mode = <0x2>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <3300000>; + }; + }; + + vcc_buck5: DCDC_REG5 { + regulator-name = "vcc_buck5"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <2200000>; + regulator-max-microvolt = <2200000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <2200000>; + }; + }; + + vcc_0v8: LDO_REG1 { + regulator-name = "vcc_0v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc1v8_pmu: LDO_REG2 { + regulator-name = "vcc1v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vdd0v8_pmu: LDO_REG3 { + regulator-name = "vcc0v8_pmu"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <800000>; + }; + }; + + vcc_1v8: LDO_REG4 { + regulator-name = "vcc_1v8"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-microvolt = <1800000>; + }; + }; + + vcc_dovdd: LDO_REG5 { + regulator-name = "vcc_dovdd"; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_dvdd: LDO_REG6 { + regulator-name = "vcc_dvdd"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_avdd: LDO_REG7 { + regulator-name = "vcc_avdd"; + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vccio_sd: LDO_REG8 { + regulator-name = "vccio_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc3v3_sd: LDO_REG9 { + regulator-name = "vcc3v3_sd"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-state-mem { + regulator-off-in-suspend; + }; + }; + + vcc_5v0: SWITCH_REG1 { + regulator-name = "vcc_5v0"; + }; + + vcc_3v3: SWITCH_REG2 { + regulator-name = "vcc_3v3"; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&pinctrl { + bt { + bt_enable: bt-enable { + rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + flash { + flash_vol_sel: flash-vol-sel { + rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + + pmic { + pmic_int_l: pmic-int-l { + rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>; + }; + }; + + wifi { + wifi_enable_h: wifi-enable-h { + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; +}; + +&pmu_io_domains { + pmuio0-supply = <&vcc1v8_pmu>; + pmuio1-supply = <&vcc3v3_sys>; + vccio1-supply = <&vccio_flash>; + vccio2-supply = <&vccio_sd>; + vccio3-supply = <&vcc_1v8>; + vccio4-supply = <&vcc_dovdd>; + vccio5-supply = <&vcc_1v8>; + vccio6-supply = <&vcc_1v8>; + vccio7-supply = <&vcc_dovdd>; + status = "okay"; +}; + +&saradc { + vref-supply = <&vcc_1v8>; + status = "okay"; +}; + +&sdio { + bus-width = <4>; + cap-sd-highspeed; + cap-sdio-irq; + keep-power-in-suspend; + max-frequency = <100000000>; + mmc-pwrseq = <&sdio_pwrseq>; + non-removable; + pinctrl-names = "default"; + pinctrl-0 = <&sdmmc1_clk &sdmmc1_cmd &sdmmc1_bus4>; + rockchip,default-sample-phase = <90>; + sd-uhs-sdr104; + vmmc-supply = <&vcc3v3_sys>; + vqmmc-supply = <&vcc_1v8>; + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer &uart0_ctsn &uart0_rtsn>; + status = "okay"; + + bluetooth { + compatible = "qcom,qca9377-bt"; + clocks = <&rk809 1>; + enable-gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>; /* BT_RST */ + max-speed = <2000000>; + pinctrl-names = "default"; + pinctrl-0 = <&bt_enable>; + vddxo-supply = <&vcc3v3_sys>; + vddio-supply = <&vcc_1v8>; + }; +}; diff --git a/arch/arm/boot/dts/rv1126-pinctrl.dtsi b/arch/arm/boot/dts/rv1126-pinctrl.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..b77021772781d22699d92735428c00708dc6933b --- /dev/null +++ b/arch/arm/boot/dts/rv1126-pinctrl.dtsi @@ -0,0 +1,253 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2020 Fuzhou Rockchip Electronics Co., Ltd + */ + +#include +#include + +/* + * This file is auto generated by pin2dts tool, please keep these code + * by adding changes at end of this file. + */ +&pinctrl { + clk_out_ethernet { + /omit-if-no-ref/ + clk_out_ethernetm1_pins: clk-out-ethernetm1-pins { + rockchip,pins = + /* clk_out_ethernet_m1 */ + <2 RK_PC5 2 &pcfg_pull_none>; + }; + }; + emmc { + /omit-if-no-ref/ + emmc_rstnout: emmc-rstnout { + rockchip,pins = + /* emmc_rstn */ + <1 RK_PA3 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + emmc_bus8: emmc-bus8 { + rockchip,pins = + /* emmc_d0 */ + <0 RK_PC4 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d1 */ + <0 RK_PC5 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d2 */ + <0 RK_PC6 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d3 */ + <0 RK_PC7 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d4 */ + <0 RK_PD0 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d5 */ + <0 RK_PD1 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d6 */ + <0 RK_PD2 2 &pcfg_pull_up_drv_level_2>, + /* emmc_d7 */ + <0 RK_PD3 2 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + emmc_clk: emmc-clk { + rockchip,pins = + /* emmc_clko */ + <0 RK_PD7 2 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + emmc_cmd: emmc-cmd { + rockchip,pins = + /* emmc_cmd */ + <0 RK_PD5 2 &pcfg_pull_up_drv_level_2>; + }; + }; + i2c0 { + /omit-if-no-ref/ + i2c0_xfer: i2c0-xfer { + rockchip,pins = + /* i2c0_scl */ + <0 RK_PB4 1 &pcfg_pull_none_drv_level_0_smt>, + /* i2c0_sda */ + <0 RK_PB5 1 &pcfg_pull_none_drv_level_0_smt>; + }; + }; + rgmii { + /omit-if-no-ref/ + rgmiim1_pins: rgmiim1-pins { + rockchip,pins = + /* rgmii_mdc_m1 */ + <2 RK_PC2 2 &pcfg_pull_none>, + /* rgmii_mdio_m1 */ + <2 RK_PC1 2 &pcfg_pull_none>, + /* rgmii_rxclk_m1 */ + <2 RK_PD3 2 &pcfg_pull_none>, + /* rgmii_rxd0_m1 */ + <2 RK_PB5 2 &pcfg_pull_none>, + /* rgmii_rxd1_m1 */ + <2 RK_PB6 2 &pcfg_pull_none>, + /* rgmii_rxd2_m1 */ + <2 RK_PC7 2 &pcfg_pull_none>, + /* rgmii_rxd3_m1 */ + <2 RK_PD0 2 &pcfg_pull_none>, + /* rgmii_rxdv_m1 */ + <2 RK_PB4 2 &pcfg_pull_none>, + /* rgmii_txclk_m1 */ + <2 RK_PD2 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd0_m1 */ + <2 RK_PC3 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd1_m1 */ + <2 RK_PC4 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd2_m1 */ + <2 RK_PD1 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txd3_m1 */ + <2 RK_PA4 2 &pcfg_pull_none_drv_level_3>, + /* rgmii_txen_m1 */ + <2 RK_PC6 2 &pcfg_pull_none_drv_level_3>; + }; + }; + sdmmc0 { + /omit-if-no-ref/ + sdmmc0_bus4: sdmmc0-bus4 { + rockchip,pins = + /* sdmmc0_d0 */ + <1 RK_PA4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d1 */ + <1 RK_PA5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d2 */ + <1 RK_PA6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc0_d3 */ + <1 RK_PA7 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_clk: sdmmc0-clk { + rockchip,pins = + /* sdmmc0_clk */ + <1 RK_PB0 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_cmd: sdmmc0-cmd { + rockchip,pins = + /* sdmmc0_cmd */ + <1 RK_PB1 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc0_det: sdmmc0-det { + rockchip,pins = + <0 RK_PA3 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc0_pwr: sdmmc0-pwr { + rockchip,pins = + <0 RK_PC0 1 &pcfg_pull_none>; + }; + }; + sdmmc1 { + /omit-if-no-ref/ + sdmmc1_bus4: sdmmc1-bus4 { + rockchip,pins = + /* sdmmc1_d0 */ + <1 RK_PB4 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d1 */ + <1 RK_PB5 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d2 */ + <1 RK_PB6 1 &pcfg_pull_up_drv_level_2>, + /* sdmmc1_d3 */ + <1 RK_PB7 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_clk: sdmmc1-clk { + rockchip,pins = + /* sdmmc1_clk */ + <1 RK_PB2 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_cmd: sdmmc1-cmd { + rockchip,pins = + /* sdmmc1_cmd */ + <1 RK_PB3 1 &pcfg_pull_up_drv_level_2>; + }; + /omit-if-no-ref/ + sdmmc1_det: sdmmc1-det { + rockchip,pins = + <1 RK_PD0 2 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + sdmmc1_pwr: sdmmc1-pwr { + rockchip,pins = + <1 RK_PD1 2 &pcfg_pull_none>; + }; + }; + uart0 { + /omit-if-no-ref/ + uart0_xfer: uart0-xfer { + rockchip,pins = + /* uart0_rx */ + <1 RK_PC2 1 &pcfg_pull_up>, + /* uart0_tx */ + <1 RK_PC3 1 &pcfg_pull_up>; + }; + /omit-if-no-ref/ + uart0_ctsn: uart0-ctsn { + rockchip,pins = + <1 RK_PC1 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart0_rtsn: uart0-rtsn { + rockchip,pins = + <1 RK_PC0 1 &pcfg_pull_none>; + }; + /omit-if-no-ref/ + uart0_rtsn_gpio: uart0-rts-pin { + rockchip,pins = + <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>; + }; + }; + uart1 { + /omit-if-no-ref/ + uart1m0_xfer: uart1m0-xfer { + rockchip,pins = + /* uart1_rx_m0 */ + <0 RK_PB7 2 &pcfg_pull_up>, + /* uart1_tx_m0 */ + <0 RK_PB6 2 &pcfg_pull_up>; + }; + }; + uart2 { + /omit-if-no-ref/ + uart2m1_xfer: uart2m1-xfer { + rockchip,pins = + /* uart2_rx_m1 */ + <3 RK_PA3 1 &pcfg_pull_up>, + /* uart2_tx_m1 */ + <3 RK_PA2 1 &pcfg_pull_up>; + }; + }; + uart3 { + /omit-if-no-ref/ + uart3m0_xfer: uart3m0-xfer { + rockchip,pins = + /* uart3_rx_m0 */ + <3 RK_PC7 4 &pcfg_pull_up>, + /* uart3_tx_m0 */ + <3 RK_PC6 4 &pcfg_pull_up>; + }; + }; + uart4 { + /omit-if-no-ref/ + uart4m0_xfer: uart4m0-xfer { + rockchip,pins = + /* uart4_rx_m0 */ + <3 RK_PA5 4 &pcfg_pull_up>, + /* uart4_tx_m0 */ + <3 RK_PA4 4 &pcfg_pull_up>; + }; + }; + uart5 { + /omit-if-no-ref/ + uart5m0_xfer: uart5m0-xfer { + rockchip,pins = + /* uart5_rx_m0 */ + <3 RK_PA7 4 &pcfg_pull_up>, + /* uart5_tx_m0 */ + <3 RK_PA6 4 &pcfg_pull_up>; + }; + }; +}; diff --git a/arch/arm/boot/dts/rv1126.dtsi b/arch/arm/boot/dts/rv1126.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..1f07d0a4fa73c62577c5a9117fb1e893ed8d5343 --- /dev/null +++ b/arch/arm/boot/dts/rv1126.dtsi @@ -0,0 +1,487 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + + compatible = "rockchip,rv1126"; + + interrupt-parent = <&gic>; + + aliases { + i2c0 = &i2c0; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + + cpu1: cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + + cpu2: cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + + cpu3: cpu@f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + enable-method = "psci"; + clocks = <&cru ARMCLK>; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = , + , + , + ; + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <24000000>; + }; + + xin24m: oscillator { + compatible = "fixed-clock"; + clock-frequency = <24000000>; + clock-output-names = "xin24m"; + #clock-cells = <0>; + }; + + grf: syscon@fe000000 { + compatible = "rockchip,rv1126-grf", "syscon", "simple-mfd"; + reg = <0xfe000000 0x20000>; + }; + + pmugrf: syscon@fe020000 { + compatible = "rockchip,rv1126-pmugrf", "syscon", "simple-mfd"; + reg = <0xfe020000 0x1000>; + + pmu_io_domains: io-domains { + compatible = "rockchip,rv1126-pmu-io-voltage-domain"; + status = "disabled"; + }; + }; + + qos_emmc: qos@fe860000 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe860000 0x20>; + }; + + qos_nandc: qos@fe860080 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe860080 0x20>; + }; + + qos_sfc: qos@fe860200 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe860200 0x20>; + }; + + qos_sdio: qos@fe86c000 { + compatible = "rockchip,rv1126-qos", "syscon"; + reg = <0xfe86c000 0x20>; + }; + + gic: interrupt-controller@feff0000 { + compatible = "arm,gic-400"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <0>; + + reg = <0xfeff1000 0x1000>, + <0xfeff2000 0x2000>, + <0xfeff4000 0x2000>, + <0xfeff6000 0x2000>; + interrupts = ; + }; + + pmu: power-management@ff3e0000 { + compatible = "rockchip,rv1126-pmu", "syscon", "simple-mfd"; + reg = <0xff3e0000 0x1000>; + + power: power-controller { + compatible = "rockchip,rv1126-power-controller"; + #power-domain-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; + + power-domain@RV1126_PD_NVM { + reg = ; + clocks = <&cru HCLK_EMMC>, + <&cru CLK_EMMC>, + <&cru HCLK_NANDC>, + <&cru CLK_NANDC>, + <&cru HCLK_SFC>, + <&cru HCLK_SFCXIP>, + <&cru SCLK_SFC>; + pm_qos = <&qos_emmc>, + <&qos_nandc>, + <&qos_sfc>; + #power-domain-cells = <0>; + }; + + power-domain@RV1126_PD_SDIO { + reg = ; + clocks = <&cru HCLK_SDIO>, + <&cru CLK_SDIO>; + pm_qos = <&qos_sdio>; + #power-domain-cells = <0>; + }; + }; + }; + + i2c0: i2c@ff3f0000 { + compatible = "rockchip,rv1126-i2c", "rockchip,rk3399-i2c"; + reg = <0xff3f0000 0x1000>; + interrupts = ; + rockchip,grf = <&pmugrf>; + clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>; + clock-names = "i2c", "pclk"; + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_xfer>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + uart1: serial@ff410000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff410000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&pmucru SCLK_UART1>, <&pmucru PCLK_UART1>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 7>, <&dmac 6>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart1m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + pmucru: clock-controller@ff480000 { + compatible = "rockchip,rv1126-pmucru"; + reg = <0xff480000 0x1000>; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + cru: clock-controller@ff490000 { + compatible = "rockchip,rv1126-cru"; + reg = <0xff490000 0x1000>; + clocks = <&xin24m>; + clock-names = "xin24m"; + rockchip,grf = <&grf>; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + dmac: dma-controller@ff4e0000 { + compatible = "arm,pl330", "arm,primecell"; + reg = <0xff4e0000 0x4000>; + interrupts = , + ; + #dma-cells = <1>; + arm,pl330-periph-burst; + clocks = <&cru ACLK_DMAC>; + clock-names = "apb_pclk"; + }; + + uart0: serial@ff560000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff560000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 5>, <&dmac 4>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart2: serial@ff570000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff570000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 9>, <&dmac 8>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart2m1_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart3: serial@ff580000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff580000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 11>, <&dmac 10>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart3m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart4: serial@ff590000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff590000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 13>, <&dmac 12>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart4m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + uart5: serial@ff5a0000 { + compatible = "rockchip,rv1126-uart", "snps,dw-apb-uart"; + reg = <0xff5a0000 0x100>; + interrupts = ; + clock-frequency = <24000000>; + clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>; + clock-names = "baudclk", "apb_pclk"; + dmas = <&dmac 15>, <&dmac 14>; + dma-names = "tx", "rx"; + pinctrl-names = "default"; + pinctrl-0 = <&uart5m0_xfer>; + reg-shift = <2>; + reg-io-width = <4>; + status = "disabled"; + }; + + saradc: adc@ff5e0000 { + compatible = "rockchip,rv1126-saradc", "rockchip,rk3399-saradc"; + reg = <0xff5e0000 0x100>; + interrupts = ; + #io-channel-cells = <1>; + clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>; + clock-names = "saradc", "apb_pclk"; + resets = <&cru SRST_SARADC_P>; + reset-names = "saradc-apb"; + status = "disabled"; + }; + + timer0: timer@ff660000 { + compatible = "rockchip,rv1126-timer", "rockchip,rk3288-timer"; + reg = <0xff660000 0x20>; + interrupts = ; + clocks = <&cru PCLK_TIMER>, <&cru CLK_TIMER0>; + clock-names = "pclk", "timer"; + }; + + gmac: ethernet@ffc40000 { + compatible = "rockchip,rv1126-gmac", "snps,dwmac-4.20a"; + reg = <0xffc40000 0x4000>; + interrupts = , + ; + interrupt-names = "macirq", "eth_wake_irq"; + rockchip,grf = <&grf>; + clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>, + <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_REF>, + <&cru ACLK_GMAC>, <&cru PCLK_GMAC>, + <&cru CLK_GMAC_TX_RX>, <&cru CLK_GMAC_PTPREF>; + clock-names = "stmmaceth", "mac_clk_rx", + "mac_clk_tx", "clk_mac_ref", + "aclk_mac", "pclk_mac", + "clk_mac_speed", "ptp_ref"; + resets = <&cru SRST_GMAC_A>; + reset-names = "stmmaceth"; + + snps,mixed-burst; + snps,tso; + + snps,axi-config = <&stmmac_axi_setup>; + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + status = "disabled"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <0x1>; + #size-cells = <0x0>; + }; + + stmmac_axi_setup: stmmac-axi-config { + snps,wr_osr_lmt = <4>; + snps,rd_osr_lmt = <8>; + snps,blen = <0 0 0 0 16 8 4>; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + queue0 {}; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + queue0 {}; + }; + }; + + emmc: mmc@ffc50000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc50000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_EMMC>, <&cru CLK_EMMC>, + <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + power-domains = <&power RV1126_PD_NVM>; + status = "disabled"; + }; + + sdmmc: mmc@ffc60000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc60000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDMMC>, <&cru CLK_SDMMC>, + <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + status = "disabled"; + }; + + sdio: mmc@ffc70000 { + compatible = "rockchip,rv1126-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0xffc70000 0x4000>; + interrupts = ; + clocks = <&cru HCLK_SDIO>, <&cru CLK_SDIO>, + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <200000000>; + power-domains = <&power RV1126_PD_SDIO>; + status = "disabled"; + }; + + pinctrl: pinctrl { + compatible = "rockchip,rv1126-pinctrl"; + rockchip,grf = <&grf>; + rockchip,pmu = <&pmugrf>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + gpio0: gpio@ff460000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff460000 0x100>; + interrupts = ; + clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio1: gpio@ff620000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff620000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@ff630000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff630000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio3: gpio@ff640000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff640000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio4: gpio@ff650000 { + compatible = "rockchip,gpio-bank"; + reg = <0xff650000 0x100>; + interrupts = ; + clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +#include "rv1126-pinctrl.dtsi" diff --git a/arch/arm/boot/dts/s3c2410-pinctrl.h b/arch/arm/boot/dts/s3c2410-pinctrl.h deleted file mode 100644 index 76b6171ae149376eac5dd54458cde06ebff25e09..0000000000000000000000000000000000000000 --- a/arch/arm/boot/dts/s3c2410-pinctrl.h +++ /dev/null @@ -1,19 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Samsung S3C2410 DTS pinctrl constants - * - * Copyright (c) 2016 Samsung Electronics Co., Ltd. - * http://www.samsung.com - * Copyright (c) 2022 Linaro Ltd - * Author: Krzysztof Kozlowski - */ - -#ifndef __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__ -#define __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__ - -#define S3C2410_PIN_FUNC_INPUT 0 -#define S3C2410_PIN_FUNC_OUTPUT 1 -#define S3C2410_PIN_FUNC_2 2 -#define S3C2410_PIN_FUNC_3 3 - -#endif /* __DTS_ARM_SAMSUNG_S3C2410_PINCTRL_H__ */ diff --git a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi b/arch/arm/boot/dts/s3c2416-pinctrl.dtsi deleted file mode 100644 index 3268366bd8bcc1741b2c3ed41022719d2ec9e658..0000000000000000000000000000000000000000 --- a/arch/arm/boot/dts/s3c2416-pinctrl.dtsi +++ /dev/null @@ -1,172 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung S3C2416 pinctrl settings - * - * Copyright (c) 2013 Heiko Stuebner - */ - -#include "s3c2410-pinctrl.h" - -&pinctrl_0 { - /* - * Pin banks - */ - - gpa: gpa-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpb: gpb-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpc: gpc-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpd: gpd-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpe: gpe-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpf: gpf-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gpg: gpg-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - }; - - gph: gph-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpj: gpj-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpk: gpk-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpl: gpl-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - gpm: gpm-gpio-bank { - gpio-controller; - #gpio-cells = <2>; - }; - - /* - * Pin groups - */ - - uart0_data: uart0-data-pins { - samsung,pins = "gph-0", "gph-1"; - samsung,pin-function = ; - }; - - uart0_fctl: uart0-fctl-pins { - samsung,pins = "gph-8", "gph-9"; - samsung,pin-function = ; - }; - - uart1_data: uart1-data-pins { - samsung,pins = "gph-2", "gph-3"; - samsung,pin-function = ; - }; - - uart1_fctl: uart1-fctl-pins { - samsung,pins = "gph-10", "gph-11"; - samsung,pin-function = ; - }; - - uart2_data: uart2-data-pins { - samsung,pins = "gph-4", "gph-5"; - samsung,pin-function = ; - }; - - uart2_fctl: uart2-fctl-pins { - samsung,pins = "gph-6", "gph-7"; - samsung,pin-function = ; - }; - - uart3_data: uart3-data-pins { - samsung,pins = "gph-6", "gph-7"; - samsung,pin-function = ; - }; - - extuart_clk: extuart-clk-pins { - samsung,pins = "gph-12"; - samsung,pin-function = ; - }; - - i2c0_bus: i2c0-bus-pins { - samsung,pins = "gpe-14", "gpe-15"; - samsung,pin-function = ; - }; - - spi0_bus: spi0-bus-pins { - samsung,pins = "gpe-11", "gpe-12", "gpe-13"; - samsung,pin-function = ; - }; - - sd0_clk: sd0-clk-pins { - samsung,pins = "gpe-5"; - samsung,pin-function = ; - }; - - sd0_cmd: sd0-cmd-pins { - samsung,pins = "gpe-6"; - samsung,pin-function = ; - }; - - sd0_bus1: sd0-bus1-pins { - samsung,pins = "gpe-7"; - samsung,pin-function = ; - }; - - sd0_bus4: sd0-bus4-pins { - samsung,pins = "gpe-8", "gpe-9", "gpe-10"; - samsung,pin-function = ; - }; - - sd1_cmd: sd1-cmd-pins { - samsung,pins = "gpl-8"; - samsung,pin-function = ; - }; - - sd1_clk: sd1-clk-pins { - samsung,pins = "gpl-9"; - samsung,pin-function = ; - }; - - sd1_bus1: sd1-bus1-pins { - samsung,pins = "gpl-0"; - samsung,pin-function = ; - }; - - sd1_bus4: sd1-bus4-pins { - samsung,pins = "gpl-1", "gpl-2", "gpl-3"; - samsung,pin-function = ; - }; -}; diff --git a/arch/arm/boot/dts/s3c2416-smdk2416.dts b/arch/arm/boot/dts/s3c2416-smdk2416.dts deleted file mode 100644 index e7c379a9842e9a35bccf3a01a057b0a51fc09c12..0000000000000000000000000000000000000000 --- a/arch/arm/boot/dts/s3c2416-smdk2416.dts +++ /dev/null @@ -1,77 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung SMDK2416 board device tree source - * - * Copyright (c) 2013 Heiko Stuebner - */ - -/dts-v1/; -#include "s3c2416.dtsi" - -/ { - model = "SMDK2416"; - compatible = "samsung,smdk2416", "samsung,s3c2416"; - - memory@30000000 { - device_type = "memory"; - reg = <0x30000000 0x4000000>; - }; - - xti: clock-0 { - compatible = "fixed-clock"; - clock-frequency = <12000000>; - clock-output-names = "xti"; - #clock-cells = <0>; - }; -}; - -&rtc { - status = "okay"; -}; - -&sdhci_0 { - pinctrl-names = "default"; - pinctrl-0 = <&sd1_clk>, <&sd1_cmd>, - <&sd1_bus1>, <&sd1_bus4>; - bus-width = <4>; - broken-cd; - status = "okay"; -}; - -&sdhci_1 { - pinctrl-names = "default"; - pinctrl-0 = <&sd0_clk>, <&sd0_cmd>, - <&sd0_bus1>, <&sd0_bus4>; - bus-width = <4>; - cd-gpios = <&gpf 1 0>; - cd-inverted; - status = "okay"; -}; - -&uart_0 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart0_data>, <&uart0_fctl>; -}; - -&uart_1 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart1_data>, <&uart1_fctl>; -}; - -&uart_2 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart2_data>; -}; - -&uart_3 { - status = "okay"; - pinctrl-names = "default"; - pinctrl-0 = <&uart3_data>; -}; - -&watchdog { - status = "okay"; -}; diff --git a/arch/arm/boot/dts/s3c2416.dtsi b/arch/arm/boot/dts/s3c2416.dtsi deleted file mode 100644 index 4660751cb207c33e7e8743dee3c9d26eb2244aa1..0000000000000000000000000000000000000000 --- a/arch/arm/boot/dts/s3c2416.dtsi +++ /dev/null @@ -1,124 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S3C2416 SoC device tree source - * - * Copyright (c) 2013 Heiko Stuebner - */ - -#include -#include "s3c24xx.dtsi" -#include "s3c2416-pinctrl.dtsi" - -/ { - model = "Samsung S3C2416 SoC"; - compatible = "samsung,s3c2416"; - - aliases { - serial3 = &uart_3; - }; - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "arm,arm926ej-s"; - reg = <0x0>; - }; - }; - - clocks: clock-controller@4c000000 { - compatible = "samsung,s3c2416-clock"; - reg = <0x4c000000 0x40>; - #clock-cells = <1>; - }; - - uart_3: serial@5000c000 { - compatible = "samsung,s3c2440-uart"; - reg = <0x5000C000 0x4000>; - interrupts = <1 18 24 4>, <1 18 25 4>; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART3>, <&clocks PCLK_UART3>, - <&clocks SCLK_UART>; - status = "disabled"; - }; - - sdhci_1: mmc@4ac00000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x4AC00000 0x100>; - interrupts = <0 0 21 3>; - clock-names = "hsmmc", "mmc_busclk.0", - "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC0>, <&clocks HCLK_HSMMC0>, - <&clocks MUX_HSMMC0>; - status = "disabled"; - }; - - sdhci_0: mmc@4a800000 { - compatible = "samsung,s3c6410-sdhci"; - reg = <0x4A800000 0x100>; - interrupts = <0 0 20 3>; - clock-names = "hsmmc", "mmc_busclk.0", - "mmc_busclk.2"; - clocks = <&clocks HCLK_HSMMC1>, <&clocks HCLK_HSMMC1>, - <&clocks MUX_HSMMC1>; - status = "disabled"; - }; -}; - -&i2c { - compatible = "samsung,s3c2440-i2c"; - clocks = <&clocks PCLK_I2C0>; - clock-names = "i2c"; -}; - -&intc { - compatible = "samsung,s3c2416-irq"; -}; - -&pinctrl_0 { - compatible = "samsung,s3c2416-pinctrl"; -}; - -&rtc { - compatible = "samsung,s3c2416-rtc"; - clocks = <&clocks PCLK_RTC>; - clock-names = "rtc"; -}; - -&timer { - clocks = <&clocks PCLK_PWM>; - clock-names = "timers"; -}; - -&uart_0 { - compatible = "samsung,s3c2440-uart"; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART0>, <&clocks PCLK_UART0>, - <&clocks SCLK_UART>; -}; - -&uart_1 { - compatible = "samsung,s3c2440-uart"; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART1>, <&clocks PCLK_UART1>, - <&clocks SCLK_UART>; -}; - -&uart_2 { - compatible = "samsung,s3c2440-uart"; - clock-names = "uart", "clk_uart_baud2", - "clk_uart_baud3"; - clocks = <&clocks PCLK_UART2>, <&clocks PCLK_UART2>, - <&clocks SCLK_UART>; -}; - -&watchdog { - interrupts = <1 9 27 3>; - clocks = <&clocks PCLK_WDT>; - clock-names = "watchdog"; -}; diff --git a/arch/arm/boot/dts/s3c24xx.dtsi b/arch/arm/boot/dts/s3c24xx.dtsi deleted file mode 100644 index 06f82c7e458e987b2f1cdf3b09854db417ebd2a6..0000000000000000000000000000000000000000 --- a/arch/arm/boot/dts/s3c24xx.dtsi +++ /dev/null @@ -1,92 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0 -/* - * Samsung's S3C24XX family device tree source - * - * Copyright (c) 2013 Heiko Stuebner - */ - -/ { - compatible = "samsung,s3c24xx"; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <1>; - - aliases { - pinctrl0 = &pinctrl_0; - serial0 = &uart_0; - serial1 = &uart_1; - serial2 = &uart_2; - }; - - intc: interrupt-controller@4a000000 { - compatible = "samsung,s3c2410-irq"; - reg = <0x4a000000 0x100>; - interrupt-controller; - #interrupt-cells = <4>; - }; - - pinctrl_0: pinctrl@56000000 { - reg = <0x56000000 0x1000>; - - wakeup-interrupt-controller { - compatible = "samsung,s3c2410-wakeup-eint"; - interrupts = <0 0 0 3>, - <0 0 1 3>, - <0 0 2 3>, - <0 0 3 3>, - <0 0 4 4>, - <0 0 5 4>; - }; - }; - - timer: pwm@51000000 { - compatible = "samsung,s3c2410-pwm"; - reg = <0x51000000 0x1000>; - interrupts = <0 0 10 3>, <0 0 11 3>, <0 0 12 3>, <0 0 13 3>, <0 0 14 3>; - #pwm-cells = <3>; - }; - - uart_0: serial@50000000 { - compatible = "samsung,s3c2410-uart"; - reg = <0x50000000 0x4000>; - interrupts = <1 28 0 4>, <1 28 1 4>; - status = "disabled"; - }; - - uart_1: serial@50004000 { - compatible = "samsung,s3c2410-uart"; - reg = <0x50004000 0x4000>; - interrupts = <1 23 3 4>, <1 23 4 4>; - status = "disabled"; - }; - - uart_2: serial@50008000 { - compatible = "samsung,s3c2410-uart"; - reg = <0x50008000 0x4000>; - interrupts = <1 15 6 4>, <1 15 7 4>; - status = "disabled"; - }; - - watchdog: watchdog@53000000 { - compatible = "samsung,s3c2410-wdt"; - reg = <0x53000000 0x100>; - interrupts = <0 0 9 3>; - status = "disabled"; - }; - - rtc: rtc@57000000 { - compatible = "samsung,s3c2410-rtc"; - reg = <0x57000000 0x100>; - interrupts = <0 0 30 3>, <0 0 8 3>; - status = "disabled"; - }; - - i2c: i2c@54000000 { - compatible = "samsung,s3c2410-i2c"; - reg = <0x54000000 0x100>; - interrupts = <0 0 27 3>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - }; -}; diff --git a/arch/arm/boot/dts/s5pv210-aries.dtsi b/arch/arm/boot/dts/s5pv210-aries.dtsi index 964c5fe517555516ec37203db601ce7cfed34541..f628d36604938984603947ab434450416203c8ec 100644 --- a/arch/arm/boot/dts/s5pv210-aries.dtsi +++ b/arch/arm/boot/dts/s5pv210-aries.dtsi @@ -135,8 +135,8 @@ 0xa101 0x0100 0x8100 0x0100 0x0100 0x0100>; - wlf,ldo1ena = <&gpf3 4 GPIO_ACTIVE_HIGH>; - wlf,ldo2ena = <&gpf3 4 GPIO_ACTIVE_HIGH>; + wlf,ldo1ena-gpios = <&gpf3 4 GPIO_ACTIVE_HIGH>; + wlf,ldo2ena-gpios = <&gpf3 4 GPIO_ACTIVE_HIGH>; wlf,lineout1-se; wlf,lineout2-se; diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi index 8f5477e307dd49e444d66289663f03048b59b5e2..e67ede940071f227170dba1bc1c35864915ec061 100644 --- a/arch/arm/boot/dts/sam9x60.dtsi +++ b/arch/arm/boot/dts/sam9x60.dtsi @@ -170,6 +170,64 @@ #size-cells = <1>; ranges = <0x0 0xf0000000 0x800>; status = "disabled"; + + uart4: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi4: spi@400 { + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c4: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(8))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(9))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; flx5: flexcom@f0004000 { @@ -180,6 +238,65 @@ #size-cells = <1>; ranges = <0x0 0xf0004000 0x800>; status = "disabled"; + + uart5: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + atmel,usart-mode = ; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi5: spi@400 { + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c5: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(10))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(11))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; dma0: dma-controller@f0008000 { @@ -251,6 +368,45 @@ #size-cells = <1>; ranges = <0x0 0xf0020000 0x800>; status = "disabled"; + + uart11: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c11: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(22))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(23))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; flx12: flexcom@f0024000 { @@ -261,6 +417,45 @@ #size-cells = <1>; ranges = <0x0 0xf0024000 0x800>; status = "disabled"; + + uart12: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c12: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(24))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(25))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; pit64b: timer@f0028000 { @@ -379,6 +574,45 @@ #size-cells = <1>; ranges = <0x0 0xf8010000 0x800>; status = "disabled"; + + uart6: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c6: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(12))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(13))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; flx7: flexcom@f8014000 { @@ -389,6 +623,45 @@ #size-cells = <1>; ranges = <0x0 0xf8014000 0x800>; status = "disabled"; + + uart7: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c7: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(14))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(15))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; flx8: flexcom@f8018000 { @@ -399,6 +672,45 @@ #size-cells = <1>; ranges = <0x0 0xf8018000 0x800>; status = "disabled"; + + uart8: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c8: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(16))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(17))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; flx0: flexcom@f801c000 { @@ -409,6 +721,64 @@ #size-cells = <1>; ranges = <0x0 0xf801c000 0x800>; status = "disabled"; + + uart0: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi0: spi@400 { + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c0: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(0))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(1))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; flx1: flexcom@f8020000 { @@ -419,6 +789,64 @@ #size-cells = <1>; ranges = <0x0 0xf8020000 0x800>; status = "disabled"; + + uart1: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi1: spi@400 { + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c1: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(2))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(3))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; flx2: flexcom@f8024000 { @@ -429,6 +857,64 @@ #size-cells = <1>; ranges = <0x0 0xf8024000 0x800>; status = "disabled"; + + uart2: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi2: spi@400 { + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c2: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(4))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(5))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; flx3: flexcom@f8028000 { @@ -439,6 +925,64 @@ #size-cells = <1>; ranges = <0x0 0xf8028000 0x800>; status = "disabled"; + + uart3: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + spi3: spi@400 { + compatible = "microchip,sam9x60-spi", "atmel,at91rm9200-spi"; + reg = <0x400 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + clock-names = "spi_clk"; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c3: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(6))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(7))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; macb0: ethernet@f802c000 { @@ -504,6 +1048,45 @@ #size-cells = <1>; ranges = <0x0 0xf8040000 0x800>; status = "disabled"; + + uart9: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c9: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(18))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(19))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; flx10: flexcom@f8044000 { @@ -514,6 +1097,45 @@ #size-cells = <1>; ranges = <0x0 0xf8044000 0x800>; status = "disabled"; + + uart10: serial@200 { + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; + reg = <0x200 0x200>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names = "tx", "rx"; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + atmel,fifo-size = <16>; + status = "disabled"; + }; + + i2c10: i2c@600 { + compatible = "microchip,sam9x60-i2c"; + reg = <0x600 0x200>; + interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; + dmas = <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(20))>, + <&dma0 + (AT91_XDMAC_DT_MEM_IF(0) | + AT91_XDMAC_DT_PER_IF(1) | + AT91_XDMAC_DT_PERID(21))>; + dma-names = "tx", "rx"; + atmel,fifo-size = <16>; + status = "disabled"; + }; }; isi: isi@f8048000 { @@ -564,7 +1186,7 @@ mpddrc: mpddrc@ffffe800 { compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc"; reg = <0xffffe800 0x200>; - clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>; + clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>; clock-names = "ddrck", "mpddr"; }; diff --git a/arch/arm/boot/dts/sama5d31ek.dts b/arch/arm/boot/dts/sama5d31ek.dts index 10fc80d6d30d134c6202fa8f277351f4c6b72fad..1f2dfb3127ab9faa5a484a5b913ed36b2daa916d 100644 --- a/arch/arm/boot/dts/sama5d31ek.dts +++ b/arch/arm/boot/dts/sama5d31ek.dts @@ -40,7 +40,7 @@ }; leds { - d3 { + led-d3 { label = "d3"; gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/sama5d34ek.dts b/arch/arm/boot/dts/sama5d34ek.dts index 2335bf906f694eaeb72bceebc62d200ac58d7a96..bffd61397cb532661d047a21f43a30ac3326cc0b 100644 --- a/arch/arm/boot/dts/sama5d34ek.dts +++ b/arch/arm/boot/dts/sama5d34ek.dts @@ -50,7 +50,7 @@ }; leds { - d3 { + led-d3 { label = "d3"; gpios = <&pioE 24 GPIO_ACTIVE_HIGH>; }; diff --git a/arch/arm/boot/dts/sama5d3xcm.dtsi b/arch/arm/boot/dts/sama5d3xcm.dtsi index 384335635792f811c59ede0ae4c8988978556aa0..7d1d7859edb433ef8bb1929a6817753a5264bc1f 100644 --- a/arch/arm/boot/dts/sama5d3xcm.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm.dtsi @@ -130,7 +130,7 @@ leds { compatible = "gpio-leds"; - d2 { + led-d2 { label = "d2"; gpios = <&pioE 25 GPIO_ACTIVE_LOW>; /* PE25, conflicts with A25, RXD2 */ linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi index 5579c955f1411e37485404777de35cc19767fc8d..830a0954ba1b01499c838595f73e57e23f21d246 100644 --- a/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi +++ b/arch/arm/boot/dts/sama5d3xcm_cmp.dtsi @@ -184,7 +184,7 @@ leds { compatible = "gpio-leds"; - d2 { + led-d2 { label = "d2"; gpios = <&pioE 25 GPIO_ACTIVE_LOW>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi index ab131762ecb58d99ec229333edcd0a1062183266..929ba73702e935acd74a859b745f3afbde5ad7e7 100644 --- a/arch/arm/boot/dts/sama7g5.dtsi +++ b/arch/arm/boot/dts/sama7g5.dtsi @@ -516,6 +516,57 @@ status = "disabled"; }; + csi2dc: csi2dc@e1404000 { + compatible = "microchip,sama7g5-csi2dc"; + reg = <0xe1404000 0x500>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&xisc>; + clock-names = "pclk", "scck"; + assigned-clocks = <&xisc>; + assigned-clock-rates = <266000000>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + csi2dc_in: endpoint { + }; + }; + + port@1 { + reg = <1>; + csi2dc_out: endpoint { + bus-width = <14>; + hsync-active = <1>; + vsync-active = <1>; + remote-endpoint = <&xisc_in>; + }; + }; + }; + }; + + xisc: xisc@e1408000 { + compatible = "microchip,sama7g5-isc"; + reg = <0xe1408000 0x2000>; + interrupts = ; + clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; + clock-names = "hclock"; + #clock-cells = <0>; + clock-output-names = "isc-mck"; + status = "disabled"; + + port { + xisc_in: endpoint { + bus-type = <5>; /* Parallel */ + bus-width = <14>; + hsync-active = <1>; + vsync-active = <1>; + remote-endpoint = <&csi2dc_out>; + }; + }; + }; + pwm: pwm@e1604000 { compatible = "microchip,sama7g5-pwm", "atmel,sama5d2-pwm"; reg = <0xe1604000 0x4000>; diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 6eda6fdc101bff088c8cced89bc8dedfbe34dde3..4c1d140f40f870740cbff91a33642f7cb1785014 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -749,7 +749,7 @@ arm,prefetch-offset = <7>; }; - l3regs@0xff800000 { + l3regs@ff800000 { compatible = "altr,l3regs", "syscon"; reg = <0xff800000 0x1000>; }; @@ -905,7 +905,7 @@ reset-names = "timer"; }; - uart0: serial0@ffc02000 { + uart0: serial@ffc02000 { compatible = "snps,dw-apb-uart"; reg = <0xffc02000 0x1000>; interrupts = <0 162 4>; @@ -918,7 +918,7 @@ resets = <&rst UART0_RESET>; }; - uart1: serial1@ffc03000 { + uart1: serial@ffc03000 { compatible = "snps,dw-apb-uart"; reg = <0xffc03000 0x1000>; interrupts = <0 163 4>; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 3b2a2c9c654731e1ba2f2bdd282fbae0663622ca..72c55e5187ca8922d6a1b444b3460d2f6e2950f6 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -845,7 +845,7 @@ reset-names = "timer"; }; - uart0: serial0@ffc02000 { + uart0: serial@ffc02000 { compatible = "snps,dw-apb-uart"; reg = <0xffc02000 0x100>; interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>; @@ -856,7 +856,7 @@ status = "disabled"; }; - uart1: serial1@ffc02100 { + uart1: serial@ffc02100 { compatible = "snps,dw-apb-uart"; reg = <0xffc02100 0x100>; interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_pe1.dts b/arch/arm/boot/dts/socfpga_arria10_mercury_pe1.dts new file mode 100644 index 0000000000000000000000000000000000000000..cf533f76a9fd309dff84846116a6edc8a4f7ec37 --- /dev/null +++ b/arch/arm/boot/dts/socfpga_arria10_mercury_pe1.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2023 Steffen Trumtrar + */ +/dts-v1/; +#include "socfpga_arria10_mercury_aa1.dtsi" + +/ { + model = "Enclustra Mercury+ PE1"; + compatible = "enclustra,mercury-pe1", "enclustra,mercury-aa1", + "altr,socfpga-arria10", "altr,socfpga"; + + aliases { + ethernet0 = &gmac0; + serial0 = &uart0; + serial1 = &uart1; + }; +}; + +&gmac0 { + status = "okay"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&gpio2 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&mmc { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; +}; diff --git a/arch/arm/boot/dts/socfpga_vt.dts b/arch/arm/boot/dts/socfpga_vt.dts index 3d0d806888b74418b4a9b2c9c15d0a162b7fb616..845ab2cc5ce611a1cb89bc22e4b5b3a9f4a0eb39 100644 --- a/arch/arm/boot/dts/socfpga_vt.dts +++ b/arch/arm/boot/dts/socfpga_vt.dts @@ -57,11 +57,11 @@ clock-frequency = <7000000>; }; - serial0@ffc02000 { + serial@ffc02000 { clock-frequency = <7372800>; }; - serial1@ffc03000 { + serial@ffc03000 { clock-frequency = <7372800>; }; diff --git a/arch/arm/boot/dts/ste-dbx5x0.dtsi b/arch/arm/boot/dts/ste-dbx5x0.dtsi index a42a4fd692993b891eca15380b4c0d526496376d..fead7afd551714b1cc14ec3132d5927f0de5ffcb 100644 --- a/arch/arm/boot/dts/ste-dbx5x0.dtsi +++ b/arch/arm/boot/dts/ste-dbx5x0.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -312,6 +313,11 @@ smp_twd_clk: smp-twd-clock { #clock-cells = <0>; }; + + clkout_clk: clkout-clock { + /* Cell 1 id, cell 2 source, cell 3 div */ + #clock-cells = <3>; + }; }; mtu@a03c6000 { diff --git a/arch/arm/boot/dts/ste-href.dtsi b/arch/arm/boot/dts/ste-href.dtsi index 8f1bb78fc1e48bd20abba7df9ea3caef536f9269..e716121a78cee094a7ee7d3524d47587661ec0f1 100644 --- a/arch/arm/boot/dts/ste-href.dtsi +++ b/arch/arm/boot/dts/ste-href.dtsi @@ -92,20 +92,20 @@ clock-mode = /bits/ 8 <2>; #address-cells = <1>; #size-cells = <0>; - chan@0 { + led@0 { reg = <0>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; color = ; linux,default-trigger = "heartbeat"; }; - chan@1 { + led@1 { reg = <1>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; color = ; }; - chan@2 { + led@2 { reg = <2>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; @@ -119,19 +119,19 @@ clock-mode = /bits/ 8 <2>; #address-cells = <1>; #size-cells = <0>; - chan@0 { + led@0 { reg = <0>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; color = ; }; - chan@1 { + led@1 { reg = <1>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; color = ; }; - chan@2 { + led@2 { reg = <2>; led-cur = /bits/ 8 <0x2f>; max-cur = /bits/ 8 <0x5f>; diff --git a/arch/arm/boot/dts/stih410.dtsi b/arch/arm/boot/dts/stih410.dtsi index a39dd5f7bcae629f5f54944c8e8d844373160676..29e95e9d3229c39fcb8fb415519fd981aecdc54d 100644 --- a/arch/arm/boot/dts/stih410.dtsi +++ b/arch/arm/boot/dts/stih410.dtsi @@ -272,7 +272,7 @@ interrupts = ; }; - sti-cec@94a087c { + cec@94a087c { compatible = "st,stih-cec"; reg = <0x94a087c 0x64>; clocks = <&clk_sysin>; diff --git a/arch/arm/boot/dts/stih418-b2264.dts b/arch/arm/boot/dts/stih418-b2264.dts index 34a518b037ab2e3f272436443b5070d4587a9fb6..fc32a03073b63a4431dbe6606196ea34465a446b 100644 --- a/arch/arm/boot/dts/stih418-b2264.dts +++ b/arch/arm/boot/dts/stih418-b2264.dts @@ -42,7 +42,7 @@ }; }; - cpu_opp_table: opp_table { + cpu_opp_table: opp-table { compatible = "operating-points-v2"; opp-shared; diff --git a/arch/arm/boot/dts/stihxxx-b2120.dtsi b/arch/arm/boot/dts/stihxxx-b2120.dtsi index 920a0bad74945e57acfd61c04aeb775ef3bd96f3..8d9a2dfa76f1fe55b954803cab8d00003a8ebec0 100644 --- a/arch/arm/boot/dts/stihxxx-b2120.dtsi +++ b/arch/arm/boot/dts/stihxxx-b2120.dtsi @@ -178,7 +178,7 @@ tsin-num = <0>; serial-not-parallel; i2c-bus = <&ssc2>; - reset-gpios = <&pio15 4 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio15 4 GPIO_ACTIVE_LOW>; dvb-card = ; }; }; diff --git a/arch/arm/boot/dts/stm32429i-eval.dts b/arch/arm/boot/dts/stm32429i-eval.dts index 3de0e9dbe030489dd1df6074058b43124aa8bb53..576235ec3c516ee2136dd2b4a9c95a2ded61a3b3 100644 --- a/arch/arm/boot/dts/stm32429i-eval.dts +++ b/arch/arm/boot/dts/stm32429i-eval.dts @@ -50,6 +50,7 @@ #include "stm32f429-pinctrl.dtsi" #include #include +#include / { model = "STMicroelectronics STM32429i-EVAL board"; @@ -186,7 +187,7 @@ port { dcmi_0: endpoint { remote-endpoint = <&ov2640_0>; - bus-type = <5>; + bus-type = ; bus-width = <8>; hsync-active = <0>; vsync-active = <0>; diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 500bcc302d422c27ceca09a69d99293b7ab06017..4523c63475e4cd330f641c0086a19ce63c598a60 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -51,7 +51,6 @@ ranges = <0 0x40020000 0x3000>; interrupt-parent = <&exti>; st,syscfg = <&syscfg 0x8>; - pins-are-numbered; gpioa: gpio@40020000 { gpio-controller; diff --git a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi index 8f37aefa7315035465d3dd1d850c056357634a11..c8e6c52fb248e0bb405472ceefa11828fa7e07a9 100644 --- a/arch/arm/boot/dts/stm32f7-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f7-pinctrl.dtsi @@ -15,7 +15,6 @@ ranges = <0 0x40020000 0x3000>; interrupt-parent = <&exti>; st,syscfg = <&syscfg 0x8>; - pins-are-numbered; gpioa: gpio@40020000 { gpio-controller; diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 28e3deb20e1e1b1c7dc1aceefe8a2593872f12b3..f30796f7adf36b0e23b603809b675b723bea7156 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -588,7 +588,6 @@ ranges = <0 0x58020000 0x3000>; interrupt-parent = <&exti>; st,syscfg = <&syscfg 0x8>; - pins-are-numbered; gpioa: gpio@58020000 { gpio-controller; diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi index d377d4c0bef544ca771f0620d0bf41889f46ab5a..b2dce3a29f39caeec22981b921d4997e90994ee8 100644 --- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi @@ -54,6 +54,66 @@ }; }; + pwm3_pins_a: pwm3-0 { + pins { + pinmux = ; /* TIM3_CH4 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm3_sleep_pins_a: pwm3-sleep-0 { + pins { + pinmux = ; /* TIM3_CH4 */ + }; + }; + + pwm4_pins_a: pwm4-0 { + pins { + pinmux = ; /* TIM4_CH2 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm4_sleep_pins_a: pwm4-sleep-0 { + pins { + pinmux = ; /* TIM4_CH2 */ + }; + }; + + pwm8_pins_a: pwm8-0 { + pins { + pinmux = ; /* TIM8_CH3 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm8_sleep_pins_a: pwm8-sleep-0 { + pins { + pinmux = ; /* TIM8_CH3 */ + }; + }; + + pwm14_pins_a: pwm14-0 { + pins { + pinmux = ; /* TIM14_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate = <0>; + }; + }; + + pwm14_sleep_pins_a: pwm14-sleep-0 { + pins { + pinmux = ; /* TIM14_CH1 */ + }; + }; + sdmmc1_b4_pins_a: sdmmc1-b4-0 { pins { pinmux = , /* SDMMC1_D0 */ diff --git a/arch/arm/boot/dts/stm32mp131.dtsi b/arch/arm/boot/dts/stm32mp131.dtsi index accc3824f7e98b9c0272fd754352f59113a4a697..5949473cbbfd5e5df0cb4e703a4d5209d3e281c9 100644 --- a/arch/arm/boot/dts/stm32mp131.dtsi +++ b/arch/arm/boot/dts/stm32mp131.dtsi @@ -119,6 +119,232 @@ }; }; + timers2: timer@40000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40000000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM2_K>; + clock-names = "int"; + dmas = <&dmamux1 18 0x400 0x1>, + <&dmamux1 19 0x400 0x1>, + <&dmamux1 20 0x400 0x1>, + <&dmamux1 21 0x400 0x1>, + <&dmamux1 22 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@1 { + compatible = "st,stm32h7-timer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers3: timer@40001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40001000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM3_K>; + clock-names = "int"; + dmas = <&dmamux1 23 0x400 0x1>, + <&dmamux1 24 0x400 0x1>, + <&dmamux1 25 0x400 0x1>, + <&dmamux1 26 0x400 0x1>, + <&dmamux1 27 0x400 0x1>, + <&dmamux1 28 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@2 { + compatible = "st,stm32h7-timer-trigger"; + reg = <2>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers4: timer@40002000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40002000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM4_K>; + clock-names = "int"; + dmas = <&dmamux1 29 0x400 0x1>, + <&dmamux1 30 0x400 0x1>, + <&dmamux1 31 0x400 0x1>, + <&dmamux1 32 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@3 { + compatible = "st,stm32h7-timer-trigger"; + reg = <3>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers5: timer@40003000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40003000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM5_K>; + clock-names = "int"; + dmas = <&dmamux1 55 0x400 0x1>, + <&dmamux1 56 0x400 0x1>, + <&dmamux1 57 0x400 0x1>, + <&dmamux1 58 0x400 0x1>, + <&dmamux1 59 0x400 0x1>, + <&dmamux1 60 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", "up", "trig"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@4 { + compatible = "st,stm32h7-timer-trigger"; + reg = <4>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers6: timer@40004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40004000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM6_K>; + clock-names = "int"; + dmas = <&dmamux1 69 0x400 0x1>; + dma-names = "up"; + status = "disabled"; + + timer@5 { + compatible = "st,stm32h7-timer-trigger"; + reg = <5>; + status = "disabled"; + }; + }; + + timers7: timer@40005000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x40005000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM7_K>; + clock-names = "int"; + dmas = <&dmamux1 70 0x400 0x1>; + dma-names = "up"; + status = "disabled"; + + timer@6 { + compatible = "st,stm32h7-timer-trigger"; + reg = <6>; + status = "disabled"; + }; + }; + + lptimer1: timer@40009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x40009000 0x400>; + interrupts-extended = <&exti 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM1_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@0 { + compatible = "st,stm32-lptimer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + i2s2: audio-controller@4000b000 { + compatible = "st,stm32h7-i2s"; + reg = <0x4000b000 0x400>; + #sound-dai-cells = <0>; + interrupts = ; + dmas = <&dmamux1 39 0x400 0x01>, + <&dmamux1 40 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spi2: spi@4000b000 { compatible = "st,stm32h7-spi"; reg = <0x4000b000 0x400>; @@ -133,6 +359,17 @@ status = "disabled"; }; + i2s3: audio-controller@4000c000 { + compatible = "st,stm32h7-i2s"; + reg = <0x4000c000 0x400>; + #sound-dai-cells = <0>; + interrupts = ; + dmas = <&dmamux1 61 0x400 0x01>, + <&dmamux1 62 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spi3: spi@4000c000 { compatible = "st,stm32h7-spi"; reg = <0x4000c000 0x400>; @@ -147,6 +384,19 @@ status = "disabled"; }; + spdifrx: audio-controller@4000d000 { + compatible = "st,stm32h7-spdifrx"; + reg = <0x4000d000 0x400>; + #sound-dai-cells = <0>; + clocks = <&rcc SPDIF_K>; + clock-names = "kclk"; + interrupts = ; + dmas = <&dmamux1 93 0x400 0x01>, + <&dmamux1 94 0x400 0x01>; + dma-names = "rx", "rx-ctrl"; + status = "disabled"; + }; + uart4: serial@40010000 { compatible = "st,stm32h7-uart"; reg = <0x40010000 0x400>; @@ -192,6 +442,99 @@ status = "disabled"; }; + timers1: timer@44000000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44000000 0x400>; + interrupts = , + , + , + ; + interrupt-names = "brk", "up", "trg-com", "cc"; + clocks = <&rcc TIM1_K>; + clock-names = "int"; + dmas = <&dmamux1 11 0x400 0x1>, + <&dmamux1 12 0x400 0x1>, + <&dmamux1 13 0x400 0x1>, + <&dmamux1 14 0x400 0x1>, + <&dmamux1 15 0x400 0x1>, + <&dmamux1 16 0x400 0x1>, + <&dmamux1 17 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@0 { + compatible = "st,stm32h7-timer-trigger"; + reg = <0>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + timers8: timer@44001000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x44001000 0x400>; + interrupts = , + , + , + ; + interrupt-names = "brk", "up", "trg-com", "cc"; + clocks = <&rcc TIM8_K>; + clock-names = "int"; + dmas = <&dmamux1 47 0x400 0x1>, + <&dmamux1 48 0x400 0x1>, + <&dmamux1 49 0x400 0x1>, + <&dmamux1 50 0x400 0x1>, + <&dmamux1 51 0x400 0x1>, + <&dmamux1 52 0x400 0x1>, + <&dmamux1 53 0x400 0x1>; + dma-names = "ch1", "ch2", "ch3", "ch4", + "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@7 { + compatible = "st,stm32h7-timer-trigger"; + reg = <7>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-timer-counter"; + status = "disabled"; + }; + }; + + i2s1: audio-controller@44004000 { + compatible = "st,stm32h7-i2s"; + reg = <0x44004000 0x400>; + #sound-dai-cells = <0>; + interrupts = ; + dmas = <&dmamux1 37 0x400 0x01>, + <&dmamux1 38 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spi1: spi@44004000 { compatible = "st,stm32h7-spi"; reg = <0x44004000 0x400>; @@ -206,6 +549,98 @@ status = "disabled"; }; + sai1: sai@4400a000 { + compatible = "st,stm32h7-sai"; + reg = <0x4400a000 0x4>, <0x4400a3f0 0x10>; + ranges = <0 0x4400a000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = ; + resets = <&rcc SAI1_R>; + status = "disabled"; + + sai1a: audio-controller@4400a004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 87 0x400 0x01>; + status = "disabled"; + }; + + sai1b: audio-controller@4400a024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc SAI1_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 88 0x400 0x01>; + status = "disabled"; + }; + }; + + sai2: sai@4400b000 { + compatible = "st,stm32h7-sai"; + reg = <0x4400b000 0x4>, <0x4400b3f0 0x10>; + ranges = <0 0x4400b000 0x400>; + #address-cells = <1>; + #size-cells = <1>; + interrupts = ; + resets = <&rcc SAI2_R>; + status = "disabled"; + + sai2a: audio-controller@4400b004 { + compatible = "st,stm32-sai-sub-a"; + reg = <0x4 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 89 0x400 0x01>; + status = "disabled"; + }; + + sai2b: audio-controller@4400b024 { + compatible = "st,stm32-sai-sub-b"; + reg = <0x24 0x20>; + #sound-dai-cells = <0>; + clocks = <&rcc SAI2_K>; + clock-names = "sai_ck"; + dmas = <&dmamux1 90 0x400 0x01>; + status = "disabled"; + }; + }; + + dfsdm: dfsdm@4400d000 { + compatible = "st,stm32mp1-dfsdm"; + reg = <0x4400d000 0x800>; + clocks = <&rcc DFSDM_K>; + clock-names = "dfsdm"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + dfsdm0: filter@0 { + compatible = "st,stm32-dfsdm-adc"; + reg = <0>; + #io-channel-cells = <1>; + interrupts = ; + dmas = <&dmamux1 101 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + + dfsdm1: filter@1 { + compatible = "st,stm32-dfsdm-adc"; + reg = <1>; + #io-channel-cells = <1>; + interrupts = ; + dmas = <&dmamux1 102 0x400 0x01>; + dma-names = "rx"; + status = "disabled"; + }; + }; + dma1: dma-controller@48000000 { compatible = "st,stm32-dma"; reg = <0x48000000 0x400>; @@ -313,6 +748,17 @@ status = "disabled"; }; + i2s4: audio-controller@4c002000 { + compatible = "st,stm32h7-i2s"; + reg = <0x4c002000 0x400>; + #sound-dai-cells = <0>; + interrupts = ; + dmas = <&dmamux1 83 0x400 0x01>, + <&dmamux1 84 0x400 0x01>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + spi4: spi@4c002000 { compatible = "st,stm32h7-spi"; reg = <0x4c002000 0x400>; @@ -395,6 +841,161 @@ status = "disabled"; }; + timers12: timer@4c007000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c007000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM12_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@11 { + compatible = "st,stm32h7-timer-trigger"; + reg = <11>; + status = "disabled"; + }; + }; + + timers13: timer@4c008000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c008000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM13_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@12 { + compatible = "st,stm32h7-timer-trigger"; + reg = <12>; + status = "disabled"; + }; + }; + + timers14: timer@4c009000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c009000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM14_K>; + clock-names = "int"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@13 { + compatible = "st,stm32h7-timer-trigger"; + reg = <13>; + status = "disabled"; + }; + }; + + timers15: timer@4c00a000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00a000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM15_K>; + clock-names = "int"; + dmas = <&dmamux1 105 0x400 0x1>, + <&dmamux1 106 0x400 0x1>, + <&dmamux1 107 0x400 0x1>, + <&dmamux1 108 0x400 0x1>; + dma-names = "ch1", "up", "trig", "com"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@14 { + compatible = "st,stm32h7-timer-trigger"; + reg = <14>; + status = "disabled"; + }; + }; + + timers16: timer@4c00b000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00b000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM16_K>; + clock-names = "int"; + dmas = <&dmamux1 109 0x400 0x1>, + <&dmamux1 110 0x400 0x1>; + dma-names = "ch1", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@15 { + compatible = "st,stm32h7-timer-trigger"; + reg = <15>; + status = "disabled"; + }; + }; + + timers17: timer@4c00c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-timers"; + reg = <0x4c00c000 0x400>; + interrupts = ; + interrupt-names = "global"; + clocks = <&rcc TIM17_K>; + clock-names = "int"; + dmas = <&dmamux1 111 0x400 0x1>, + <&dmamux1 112 0x400 0x1>; + dma-names = "ch1", "up"; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer@16 { + compatible = "st,stm32h7-timer-trigger"; + reg = <16>; + status = "disabled"; + }; + }; + rcc: rcc@50000000 { compatible = "st,stm32mp13-rcc", "syscon"; reg = <0x50000000 0x1000>; @@ -421,6 +1022,111 @@ clocks = <&rcc SYSCFG>; }; + lptimer2: timer@50021000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50021000 0x400>; + interrupts-extended = <&exti 48 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM2_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@1 { + compatible = "st,stm32-lptimer-trigger"; + reg = <1>; + status = "disabled"; + }; + + counter { + compatible = "st,stm32-lptimer-counter"; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + lptimer3: timer@50022000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32-lptimer"; + reg = <0x50022000 0x400>; + interrupts-extended = <&exti 50 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM3_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + trigger@2 { + compatible = "st,stm32-lptimer-trigger"; + reg = <2>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + lptimer4: timer@50023000 { + compatible = "st,stm32-lptimer"; + reg = <0x50023000 0x400>; + interrupts-extended = <&exti 52 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM4_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + + lptimer5: timer@50024000 { + compatible = "st,stm32-lptimer"; + reg = <0x50024000 0x400>; + interrupts-extended = <&exti 53 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&rcc LPTIM5_K>; + clock-names = "mux"; + wakeup-source; + status = "disabled"; + + pwm { + compatible = "st,stm32-pwm-lp"; + #pwm-cells = <3>; + status = "disabled"; + }; + + timer { + compatible = "st,stm32-lptimer-timer"; + status = "disabled"; + }; + }; + mdma: dma-controller@58000000 { compatible = "st,stm32h7-mdma"; reg = <0x58000000 0x1000>; @@ -520,13 +1226,14 @@ }; bsec: efuse@5c005000 { - compatible = "st,stm32mp15-bsec"; + compatible = "st,stm32mp13-bsec"; reg = <0x5c005000 0x400>; #address-cells = <1>; #size-cells = <1>; part_number_otp: part_number_otp@4 { reg = <0x4 0x2>; + bits = <0 12>; }; ts_cal1: calib@5c { reg = <0x5c 0x2>; @@ -547,7 +1254,6 @@ ranges = <0 0x50002000 0x8400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; - pins-are-numbered; gpioa: gpio@50002000 { gpio-controller; diff --git a/arch/arm/boot/dts/stm32mp135f-dk.dts b/arch/arm/boot/dts/stm32mp135f-dk.dts index 9ff5a3eaf55b9550e1f4733c2390b6050be861b7..c40686cb2b9a1ed1297eed07694cae0fce384345 100644 --- a/arch/arm/boot/dts/stm32mp135f-dk.dts +++ b/arch/arm/boot/dts/stm32mp135f-dk.dts @@ -40,7 +40,7 @@ gpio-keys { compatible = "gpio-keys"; - user-pa13 { + button-user { label = "User-PA13"; linux,code = ; gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; @@ -208,6 +208,64 @@ status = "disabled"; }; +&timers3 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm3_pins_a>; + pinctrl-1 = <&pwm3_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@2 { + status = "okay"; + }; +}; + +&timers4 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm4_pins_a>; + pinctrl-1 = <&pwm4_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@3 { + status = "okay"; + }; +}; + +&timers8 { + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; + pwm { + pinctrl-0 = <&pwm8_pins_a>; + pinctrl-1 = <&pwm8_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@7 { + status = "okay"; + }; +}; + +&timers14 { + status = "disabled"; + pwm { + pinctrl-0 = <&pwm14_pins_a>; + pinctrl-1 = <&pwm14_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + status = "okay"; + }; + timer@13 { + status = "okay"; + }; +}; + &uart4 { pinctrl-names = "default"; pinctrl-0 = <&uart4_pins_a>; diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 5491b6c4dec2037f926c0db61d36f381218573b6..4e437d3f2ed66e7bcc203f3a240ad0f29d083b0b 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1660,7 +1660,6 @@ ranges = <0 0x50002000 0xa400>; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; - pins-are-numbered; gpioa: gpio@50002000 { gpio-controller; @@ -1789,7 +1788,6 @@ #size-cells = <1>; compatible = "st,stm32mp157-z-pinctrl"; ranges = <0 0x54004000 0x400>; - pins-are-numbered; interrupt-parent = <&exti>; st,syscfg = <&exti 0x60 0xff>; diff --git a/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi b/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi index d865ab5d866b93bf16eac00e33080cecf40041cc..dd23de85100c483386d35307fc93f1e03c987982 100644 --- a/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi +++ b/arch/arm/boot/dts/stm32mp151a-prtt1l.dtsi @@ -101,8 +101,12 @@ &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi index aef02e6421a36ddf93a975b0798fb92c4326b5d1..7d11c50b9e4087afa226adc052449c3a38b3dd6e 100644 --- a/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi +++ b/arch/arm/boot/dts/stm32mp157c-emstamp-argon.dtsi @@ -391,8 +391,12 @@ &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index a665189fe621a4c4d749f4bfb2e7c7d40ce684de..542226cfcfdfb6ec60ec280c7ff46efe5cf79b07 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -8,6 +8,7 @@ #include "stm32mp157c-ed1.dts" #include #include +#include / { model = "STMicroelectronics STM32MP157C eval daughter on eval mother"; @@ -90,7 +91,7 @@ port { dcmi_0: endpoint { remote-endpoint = <&ov5640_0>; - bus-type = <5>; + bus-type = ; bus-width = <8>; hsync-active = <0>; vsync-active = <0>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 002f221f1694c79c70aba0d9d9e120c006de0a64..c06edd2eacb0cd3f35850f0247bda1dedab4f718 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -428,8 +428,12 @@ &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi index 134a798ad3f23f628e8673fadaf58b777cf64e41..bb40fb46da81d559084f680c11c5c072efa83073 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-som.dtsi @@ -247,8 +247,12 @@ &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a + &qspi_bk1_pins_a + &qspi_cs1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a + &qspi_bk1_sleep_pins_a + &qspi_cs1_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x200000>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi index 7798a2e17c5ca2b038be475c2949ef2791855426..11370ae0d868b71759946fb2151c8fac65d9287e 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dkx.dtsi @@ -72,7 +72,7 @@ sound { compatible = "audio-graph-card"; - label = "STM32MP1-DK"; + label = "STM32MP15-DK"; routing = "Playback" , "MCLK", "Capture" , "MCLK", @@ -501,8 +501,6 @@ sai2a: audio-controller@4400b004 { #clock-cells = <0>; dma-names = "tx"; - clocks = <&rcc SAI2_K>; - clock-names = "sai_ck"; status = "okay"; sai2a_port: port { diff --git a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts index a32cde3e32eb14a2163122bb12b804b0721b7335..5c3562b85a5bf95003b63013ba5d6e43cbda2d71 100644 --- a/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts +++ b/arch/arm/boot/dts/sun5i-gr8-chip-pro.dts @@ -70,7 +70,7 @@ leds { compatible = "gpio-leds"; - status { + led-0 { label = "chip-pro:white:status"; gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; default-state = "on"; diff --git a/arch/arm/boot/dts/sun5i-r8-chip.dts b/arch/arm/boot/dts/sun5i-r8-chip.dts index 4bf4943d4eb77c923ca25b57ecb678b5eb347bc7..fd37bd1f3920857f51ae9257a625f3c497bbe0c6 100644 --- a/arch/arm/boot/dts/sun5i-r8-chip.dts +++ b/arch/arm/boot/dts/sun5i-r8-chip.dts @@ -70,7 +70,7 @@ leds { compatible = "gpio-leds"; - status { + led-0 { label = "chip:white:status"; gpios = <&axp_gpio 2 GPIO_ACTIVE_HIGH>; default-state = "on"; diff --git a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts index 0af48e143b664c299e303418e0f01495e5e70ee4..56956352914d72536c4a169c1ffd576c2617ec5b 100644 --- a/arch/arm/boot/dts/sun6i-a31s-sina31s.dts +++ b/arch/arm/boot/dts/sun6i-a31s-sina31s.dts @@ -67,7 +67,7 @@ leds { compatible = "gpio-leds"; - status { + led-0 { label = "sina31s:status:usr"; gpios = <&pio 7 13 GPIO_ACTIVE_HIGH>; /* PH13 */ }; diff --git a/arch/arm/boot/dts/sun8i-a33.dtsi b/arch/arm/boot/dts/sun8i-a33.dtsi index b3d1bdfb5118e6291b2c8217083b610bcf776773..30fdd2703b1ff493f06d4c44f566608172daf45e 100644 --- a/arch/arm/boot/dts/sun8i-a33.dtsi +++ b/arch/arm/boot/dts/sun8i-a33.dtsi @@ -278,6 +278,7 @@ dphy: d-phy@1ca1000 { compatible = "allwinner,sun6i-a31-mipi-dphy"; reg = <0x01ca1000 0x1000>; + interrupts = ; clocks = <&ccu CLK_BUS_MIPI_DSI>, <&ccu CLK_DSI_DPHY>; clock-names = "bus", "mod"; diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts index 5a7e1bd5f8258bf90816e577fe4940a0f3887b8a..8d56b103f063049dac71fa02439b63ed7e70fd32 100644 --- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts +++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts @@ -105,6 +105,21 @@ /* enables internal regulator and de-asserts reset */ reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */ }; + + /* + * Power supply for the SATA disk, behind a USB-SATA bridge. + * Since it is a USB device, there is no consumer in the DT, so we + * have to keep this always on. + */ + regulator-sata-disk-pwr { + compatible = "regulator-fixed"; + regulator-name = "sata-disk-pwr"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + enable-active-high; + gpio = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */ + }; }; &cpu0 { diff --git a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts index 27a0d51289ddd4eeb9b9eaa14c1ebd565e30e38c..a6d38ecee141d438898325f08bcd5e595d425950 100644 --- a/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts +++ b/arch/arm/boot/dts/sun8i-h3-beelink-x2.dts @@ -57,7 +57,7 @@ ethernet1 = &sdiowifi; }; - cec-gpio { + cec { compatible = "cec-gpio"; cec-gpios = <&pio 0 14 (GPIO_ACTIVE_HIGH|GPIO_OPEN_DRAIN)>; /* PA14 */ hdmi-phandle = <&hdmi>; diff --git a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts index 43641cb82398fca8c5b234e492764441cebb1118..343b02b97155539c4b9b8a0356647c1dda691b17 100644 --- a/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts +++ b/arch/arm/boot/dts/sun8i-h3-nanopi-duo2.dts @@ -57,7 +57,7 @@ regulator-ramp-delay = <50>; /* 4ms */ enable-active-high; - enable-gpio = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + enable-gpios = <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ gpios = <&r_pio 0 6 GPIO_ACTIVE_HIGH>; /* PL6 */ gpios-states = <0x1>; states = <1100000 0>, <1300000 1>; diff --git a/arch/arm/boot/dts/tegra114-asus-tf701t.dts b/arch/arm/boot/dts/tegra114-asus-tf701t.dts index 9279d24db009c5c30c5988856466493dbebde67d..84a3eb38e71d2165f00d5c32189f4020f90e7541 100644 --- a/arch/arm/boot/dts/tegra114-asus-tf701t.dts +++ b/arch/arm/boot/dts/tegra114-asus-tf701t.dts @@ -25,6 +25,14 @@ serial2 = &uartb; /* GPS */ }; + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + memory@80000000 { reg = <0x80000000 0x80000000>; }; @@ -109,6 +117,15 @@ }; codec_default: pinmux-codec-default { + interrupt { + nvidia,pins = "gpio_w2_aud_pw2", + "gpio_w3_aud_pw3"; + nvidia,function = "spi6"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + ldo1-en { nvidia,pins = "sdmmc1_wp_n_pv3"; nvidia,function = "sdmmc1"; @@ -116,11 +133,12 @@ nvidia,tristate = ; nvidia,enable-input = ; }; + }; - interrupt { - nvidia,pins = "gpio_w2_aud_pw2", - "gpio_w3_aud_pw3"; - nvidia,function = "spi6"; + gpio_hall_sensor_default: pinmux-gpio-hall-sensor-default { + ulpi_data4_po5 { + nvidia,pins = "ulpi_data4_po5"; + nvidia,function = "spi2"; nvidia,pull = ; nvidia,tristate = ; nvidia,enable-input = ; @@ -146,16 +164,6 @@ }; }; - gpio_hall_sensor_default: pinmux-gpio-hall-sensor-default { - ulpi_data4_po5 { - nvidia,pins = "ulpi_data4_po5"; - nvidia,function = "spi2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - }; - }; - hp_det_default: pinmux-hp-det-default { gmi_iordy_pi5 { nvidia,pins = "kb_row7_pr7"; @@ -198,6 +206,16 @@ }; sdmmc3_default: pinmux-sdmmc3-default { + drive_sdio3 { + nvidia,pins = "drive_sdio3"; + nvidia,high-speed-mode = ; + nvidia,schmitt = ; + nvidia,pull-down-strength = <22>; + nvidia,pull-up-strength = <36>; + nvidia,slew-rate-rising = ; + nvidia,slew-rate-falling = ; + }; + sdmmc3_clk_pa6 { nvidia,pins = "sdmmc3_clk_pa6"; nvidia,function = "sdmmc3"; @@ -221,16 +239,6 @@ nvidia,tristate = ; nvidia,enable-input = ; }; - - drive_sdio3 { - nvidia,pins = "drive_sdio3"; - nvidia,high-speed-mode = ; - nvidia,schmitt = ; - nvidia,pull-down-strength = <22>; - nvidia,pull-up-strength = <36>; - nvidia,slew-rate-rising = ; - nvidia,slew-rate-falling = ; - }; }; sdmmc3_vdd_default: pinmux-sdmmc3-vdd-default { @@ -298,6 +306,14 @@ pinctrl-0 = <&codec_default>; }; + temp_sensor: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + motion-tracker@68 { compatible = "invensense,mpu6500"; reg = <0x68>; @@ -312,14 +328,6 @@ pinctrl-names = "default"; pinctrl-0 = <&imu_default>; }; - - temp_sensor: temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - - vcc-supply = <&vdd_3v3_sys>; - #thermal-sensor-cells = <1>; - }; }; i2c@7000c400 { @@ -368,6 +376,66 @@ #gpio-cells = <2>; }; + pinmux { + compatible = "ti,tps65913-pinctrl"; + ti,palmas-enable-dvfs1; + + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_gpio0 { + pins = "gpio0"; + function = "gpio"; + }; + + pin_gpio1 { + pins = "gpio1"; + function = "gpio"; + }; + + pin_gpio2 { + pins = "gpio2"; + function = "gpio"; + }; + + pin_gpio3 { + pins = "gpio3"; + function = "gpio"; + }; + + pin_gpio4 { + pins = "gpio4"; + function = "gpio"; + }; + + pin_gpio5 { + pins = "gpio5"; + function = "gpio"; + }; + + pin_gpio6 { + pins = "gpio6"; + function = "gpio"; + }; + + pin_gpio7 { + pins = "gpio7"; + function = "gpio"; + }; + + pin_powergood { + pins = "powergood"; + function = "powergood"; + }; + + pin_vac { + pins = "vac"; + function = "vac"; + }; + }; + }; + pmic { compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; @@ -528,66 +596,6 @@ interrupt-parent = <&palmas>; interrupts = <8 0>; }; - - pinmux { - compatible = "ti,tps65913-pinctrl"; - ti,palmas-enable-dvfs1; - - pinctrl-names = "default"; - pinctrl-0 = <&palmas_default>; - - palmas_default: pinmux { - pin_powergood { - pins = "powergood"; - function = "powergood"; - }; - - pin_vac { - pins = "vac"; - function = "vac"; - }; - - pin_gpio0 { - pins = "gpio0"; - function = "gpio"; - }; - - pin_gpio1 { - pins = "gpio1"; - function = "gpio"; - }; - - pin_gpio2 { - pins = "gpio2"; - function = "gpio"; - }; - - pin_gpio3 { - pins = "gpio3"; - function = "gpio"; - }; - - pin_gpio4 { - pins = "gpio4"; - function = "gpio"; - }; - - pin_gpio5 { - pins = "gpio5"; - function = "gpio"; - }; - - pin_gpio6 { - pins = "gpio6"; - function = "gpio"; - }; - - pin_gpio7 { - pins = "gpio7"; - function = "gpio"; - }; - }; - }; }; }; @@ -668,11 +676,21 @@ clock-output-names = "pmic-oscillator"; }; - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; + gpio-hall-sensor { + compatible = "gpio-keys"; + + label = "GPIO Hall Effect Sensor"; + + pinctrl-names = "default"; + pinctrl-0 = <&gpio_hall_sensor_default>; + + switch-hall-sensor { + label = "Hall Effect Sensor"; + gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + linux,can-disable; + wakeup-source; }; }; @@ -692,36 +710,18 @@ wakeup-source; }; - button-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - }; - button-volume-down { label = "Volume Down"; gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; linux,code = ; debounce-interval = <10>; }; - }; - - gpio-hall-sensor { - compatible = "gpio-keys"; - - label = "GPIO Hall Effect Sensor"; - pinctrl-names = "default"; - pinctrl-0 = <&gpio_hall_sensor_default>; - - switch-hall-sensor { - label = "Hall Effect Sensor"; - gpios = <&gpio TEGRA_GPIO(O, 5) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - linux,can-disable; - wakeup-source; + button-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; }; }; diff --git a/arch/arm/boot/dts/tegra114-dalmore.dts b/arch/arm/boot/dts/tegra114-dalmore.dts index fffd62bcea6a9b0abdc9602a05f349a753623fe1..a685fcb129d009040cf10b6755d5d951320dcf3c 100644 --- a/arch/arm/boot/dts/tegra114-dalmore.dts +++ b/arch/arm/boot/dts/tegra114-dalmore.dts @@ -909,6 +909,19 @@ #gpio-cells = <2>; }; + pinmux { + compatible = "ti,tps65913-pinctrl"; + pinctrl-names = "default"; + pinctrl-0 = <&palmas_default>; + + palmas_default: pinmux { + pin_gpio6 { + pins = "gpio6"; + function = "gpio"; + }; + }; + }; + pmic { compatible = "ti,tps65913-pmic", "ti,palmas-pmic"; smps1-in-supply = <&tps65090_dcdc3_reg>; @@ -1065,19 +1078,6 @@ interrupt-parent = <&palmas>; interrupts = <8 0>; }; - - pinmux { - compatible = "ti,tps65913-pinctrl"; - pinctrl-names = "default"; - pinctrl-0 = <&palmas_default>; - - palmas_default: pinmux { - pin_gpio6 { - pins = "gpio6"; - function = "gpio"; - }; - }; - }; }; }; diff --git a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi index 7143c6b2ec3ed804d5e67c93fa2555aa86f6e3d0..970f33dd9101ef09851d4c22cba02fd356132b6b 100644 --- a/arch/arm/boot/dts/tegra124-apalis-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-emc.dtsi @@ -4,6 +4,8 @@ * */ +#include + / { clock@60006000 { emc-timings-1 { @@ -1474,12 +1476,12 @@ }; }; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-1200000000-1100; -}; + opp-table-actmon { + /delete-node/ opp-1200000000; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-1200000000; + opp-table-emc { + /delete-node/ opp-1200000000-1100; + }; }; diff --git a/arch/arm/boot/dts/tegra124-apalis-eval.dts b/arch/arm/boot/dts/tegra124-apalis-eval.dts index bce12b3411fc782acaa6bf9459b80bc97837d4ad..2df2d8a6b552d9ad9d9e4c9792f62241cb6b89d0 100644 --- a/arch/arm/boot/dts/tegra124-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-eval.dts @@ -40,6 +40,16 @@ }; }; + gpio: gpio@6000d000 { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex-perst-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "PEX_PERST_N"; + }; + }; + /* Apalis UART1 */ serial@70006000 { status = "okay"; @@ -243,13 +253,3 @@ vin-supply = <®_5v0>; }; }; - -&gpio { - /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "PEX_PERST_N"; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts index 800283ad6bdc7712077fbfeb7a66276fed576f13..f4521fd15f6ad73e8306fa01c7803fa9c31a436a 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2-eval.dts @@ -41,6 +41,16 @@ }; }; + gpio@6000d000 { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex-perst-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "PEX_PERST_N"; + }; + }; + /* Apalis UART1 */ serial@70006000 { status = "okay"; @@ -245,13 +255,3 @@ vin-supply = <®_5v0>; }; }; - -&gpio { - /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "PEX_PERST_N"; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi index dbb0da08cb95d65b53926871e01d08bdc5d5eaa3..75cfe718737cda68de0f8e0216a8c3fa13754d68 100644 --- a/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis-v1.2.dtsi @@ -65,6 +65,24 @@ vdd-supply = <®_vdd_gpu>; }; + gpio@6000d000 { + /* I210 Gigabit Ethernet Controller Reset */ + lan-reset-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "LAN_RESET_N"; + }; + + /* Control MXM3 pin 26 Reset Module Output Carrier Input */ + reset-moci-ctrl-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "RESET_MOCI_CTRL"; + }; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -1585,18 +1603,18 @@ pinctrl-0 = <&as3722_default>; as3722_default: pinmux { + gpio0-1-3-4-5-6 { + pins = "gpio0", "gpio1", "gpio3", + "gpio4", "gpio5", "gpio6"; + bias-high-impedance; + }; + gpio2-7 { pins = "gpio2", /* PWR_EN_+V3.3 */ "gpio7"; /* +V1.6_LPO */ function = "gpio"; bias-pull-up; }; - - gpio0-1-3-4-5-6 { - pins = "gpio0", "gpio1", "gpio3", - "gpio4", "gpio5", "gpio6"; - bias-high-impedance; - }; }; regulators { @@ -1943,18 +1961,18 @@ }; }; - clk32k_in: osc3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - cpus { cpu@0 { vdd-cpu-supply = <®_vdd_cpu>; }; }; + clk32k_in: osc3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { compatible = "regulator-fixed"; regulator-name = "+V1.05_AVDD_HDMI_PLL"; @@ -2056,21 +2074,3 @@ }; }; }; - -&gpio { - /* I210 Gigabit Ethernet Controller Reset */ - lan-reset-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "LAN_RESET_N"; - }; - - /* Control MXM3 pin 26 Reset Module Output Carrier Input */ - reset-moci-ctrl-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "RESET_MOCI_CTRL"; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-apalis.dtsi b/arch/arm/boot/dts/tegra124-apalis.dtsi index d3f16c117b0ca2d2e34155bb2e70de395fc07972..554c8089491c95d323d26396cf6b096bb5893817 100644 --- a/arch/arm/boot/dts/tegra124-apalis.dtsi +++ b/arch/arm/boot/dts/tegra124-apalis.dtsi @@ -64,6 +64,24 @@ vdd-supply = <®_vdd_gpu>; }; + gpio@6000d000 { + /* I210 Gigabit Ethernet Controller Reset */ + lan-reset-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "LAN_RESET_N"; + }; + + /* Control MXM3 pin 26 Reset Module Output Carrier Input */ + reset-moci-ctrl-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "RESET_MOCI_CTRL"; + }; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -1578,18 +1596,18 @@ pinctrl-0 = <&as3722_default>; as3722_default: pinmux { + gpio0-1-3-4-5-6 { + pins = "gpio0", "gpio1", "gpio3", + "gpio4", "gpio5", "gpio6"; + bias-high-impedance; + }; + gpio2-7 { pins = "gpio2", /* PWR_EN_+V3.3 */ "gpio7"; /* +V1.6_LPO */ function = "gpio"; bias-pull-up; }; - - gpio0-1-3-4-5-6 { - pins = "gpio0", "gpio1", "gpio3", - "gpio4", "gpio5", "gpio6"; - bias-high-impedance; - }; }; regulators { @@ -1935,18 +1953,18 @@ }; }; - clk32k_in: osc3 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <32768>; - }; - cpus { cpu@0 { vdd-cpu-supply = <®_vdd_cpu>; }; }; + clk32k_in: osc3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + reg_1v05_avdd_hdmi_pll: regulator-1v05-avdd-hdmi-pll { compatible = "regulator-fixed"; regulator-name = "+V1.05_AVDD_HDMI_PLL"; @@ -2048,21 +2066,3 @@ }; }; }; - -&gpio { - /* I210 Gigabit Ethernet Controller Reset */ - lan-reset-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "LAN_RESET_N"; - }; - - /* Control MXM3 pin 26 Reset Module Output Carrier Input */ - reset-moci-ctrl-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "RESET_MOCI_CTRL"; - }; -}; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi index 79e776db5f3752e59d09480cbaeeef86c2cab4bc..d10e5334a6c67fffb4e6bda95866cc9c6937de78 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-jetson-tk1-emc.dtsi @@ -1,4 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 + +#include + / { clock@60006000 { emc-timings-3 { @@ -2429,12 +2432,12 @@ }; }; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-1200000000-1100; -}; + opp-table-actmon { + /delete-node/ opp-1200000000; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-1200000000; + opp-table-emc { + /delete-node/ opp-1200000000-1100; + }; }; diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index f41dd4039c07bba2a97f996834fe52bf7f570e43..4196f2401c90f14eabc266c9b8ce4918b177cc83 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -68,10 +68,6 @@ }; }; - cec@70015000 { - status = "okay"; - }; - gpu@57000000 { /* * Node left disabled on purpose - the bootloader will enable @@ -1683,6 +1679,10 @@ }; }; + cec@70015000 { + status = "okay"; + }; + /* Serial ATA */ sata@70020000 { status = "okay"; diff --git a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi index 31b2e26c69d46df9c6b3e25fb4229a8a09a4733c..cadb1969f1ccea97d4f65ba75f4ee4829fa362e8 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-big-emc.dtsi @@ -1,9 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 -/ { - apbmisc@70000800 { - nvidia,long-ram-code; - }; +#include + +/ { clock@60006000 { emc-timings-1 { nvidia,ram-code = <1>; @@ -249,6 +248,10 @@ }; }; + apbmisc@70000800 { + nvidia,long-ram-code; + }; + memory-controller@70019000 { emc-timings-1 { nvidia,ram-code = <1>; @@ -6678,14 +6681,14 @@ }; }; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-924000000-1100; - /delete-node/ opp-1200000000-1100; -}; + opp-table-actmon { + /delete-node/ opp-924000000; + /delete-node/ opp-1200000000; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-924000000; - /delete-node/ opp-1200000000; + opp-table-emc { + /delete-node/ opp-924000000-1100; + /delete-node/ opp-1200000000-1100; + }; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-big.dts b/arch/arm/boot/dts/tegra124-nyan-big.dts index 9a01dfed137910287814856b131273377e7021f6..8bca9599ad6ec6146dacae3a63f88ef7b3c0af99 100644 --- a/arch/arm/boot/dts/tegra124-nyan-big.dts +++ b/arch/arm/boot/dts/tegra124-nyan-big.dts @@ -25,17 +25,6 @@ }; }; - mmc@700b0400 { /* SD Card on this bus */ - wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - }; - - sound { - compatible = "nvidia,tegra-audio-max98090-nyan-big", - "nvidia,tegra-audio-max98090-nyan", - "nvidia,tegra-audio-max98090"; - nvidia,model = "GoogleNyanBig"; - }; - pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&pinmux_default>; @@ -1345,4 +1334,15 @@ }; }; }; + + mmc@700b0400 { /* SD Card on this bus */ + wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + }; + + sound { + compatible = "nvidia,tegra-audio-max98090-nyan-big", + "nvidia,tegra-audio-max98090-nyan", + "nvidia,tegra-audio-max98090"; + nvidia,model = "GoogleNyanBig"; + }; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi index 2ce1b12be44d22b7b9921bd26b253340889e38b1..e8dcc4f51fc591c446b6253084d4e0a9558d630d 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan-blaze-emc.dtsi @@ -1,4 +1,7 @@ // SPDX-License-Identifier: GPL-2.0 + +#include + / { clock@60006000 { emc-timings-1 { @@ -2055,14 +2058,14 @@ }; }; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-924000000-1100; - /delete-node/ opp-1200000000-1100; -}; + opp-table-actmon { + /delete-node/ opp-924000000; + /delete-node/ opp-1200000000; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-924000000; - /delete-node/ opp-1200000000; + opp-table-emc { + /delete-node/ opp-924000000-1100; + /delete-node/ opp-1200000000-1100; + }; }; diff --git a/arch/arm/boot/dts/tegra124-nyan-blaze.dts b/arch/arm/boot/dts/tegra124-nyan-blaze.dts index 0beef1c03ff333ae34e1c50c64efba5a66b88a5d..432540c1006534f58bb494d848d8a0085ba57635 100644 --- a/arch/arm/boot/dts/tegra124-nyan-blaze.dts +++ b/arch/arm/boot/dts/tegra124-nyan-blaze.dts @@ -27,13 +27,6 @@ }; }; - sound { - compatible = "nvidia,tegra-audio-max98090-nyan-blaze", - "nvidia,tegra-audio-max98090-nyan", - "nvidia,tegra-audio-max98090"; - nvidia,model = "GoogleNyanBlaze"; - }; - pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&pinmux_default>; @@ -1343,4 +1336,11 @@ }; }; }; + + sound { + compatible = "nvidia,tegra-audio-max98090-nyan-blaze", + "nvidia,tegra-audio-max98090-nyan", + "nvidia,tegra-audio-max98090"; + nvidia,model = "GoogleNyanBlaze"; + }; }; diff --git a/arch/arm/boot/dts/tegra124-nyan.dtsi b/arch/arm/boot/dts/tegra124-nyan.dtsi index 13061ab5247b36ec729d0e67f1cdd66477d9fe90..56952333ae2856eb3252025022ccb1746c901e69 100644 --- a/arch/arm/boot/dts/tegra124-nyan.dtsi +++ b/arch/arm/boot/dts/tegra124-nyan.dtsi @@ -498,12 +498,6 @@ }; }; - sdhci0_pwrseq: sdhci0_pwrseq { - compatible = "mmc-pwrseq-simple"; - - reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; - }; - mmc@700b0000 { /* WiFi/BT on this bus */ status = "okay"; bus-width = <4>; @@ -595,14 +589,35 @@ }; cpus { - cpu@0 { + cpu0: cpu@0 { + #cooling-cells = <2>; vdd-cpu-supply = <&vdd_cpu>; }; + + cpu1: cpu@1 { + #cooling-cells = <2>; + }; + + cpu2: cpu@2 { + #cooling-cells = <2>; + }; + + cpu3: cpu@3 { + #cooling-cells = <2>; + }; }; gpio-keys { compatible = "gpio-keys"; + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <30>; + wakeup-source; + }; + switch-lid { label = "Lid"; gpios = <&gpio TEGRA_GPIO(R, 4) GPIO_ACTIVE_LOW>; @@ -611,14 +626,18 @@ debounce-interval = <1>; wakeup-source; }; + }; - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <30>; - wakeup-source; - }; + gpio-restart { + compatible = "gpio-restart"; + gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; + priority = <200>; + }; + + sdhci0_pwrseq: pwrseq-sdhci0 { + compatible = "mmc-pwrseq-simple"; + + reset-gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>; }; vdd_mux: regulator-mux { @@ -785,30 +804,6 @@ <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>; }; - gpio-restart { - compatible = "gpio-restart"; - gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; - priority = <200>; - }; - - cpus { - cpu0: cpu@0 { - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - #cooling-cells = <2>; - }; - - cpu2: cpu@2 { - #cooling-cells = <2>; - }; - - cpu3: cpu@3 { - #cooling-cells = <2>; - }; - }; - thermal-zones { cpu-skin-thermal { polling-delay-passive = <1000>; /* milliseconds */ diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index a9ab548781e1c2a751485b4785e06503d36d97f2..b3fbecf5c818827a8e0d157b2ab7a072dc9256c1 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -639,6 +639,16 @@ reset-names = "fuse"; }; + cec@70015000 { + compatible = "nvidia,tegra124-cec"; + reg = <0x0 0x70015000 0x0 0x00001000>; + interrupts = ; + clocks = <&tegra_car TEGRA124_CLK_CEC>; + clock-names = "cec"; + status = "disabled"; + hdmi-phandle = <&hdmi>; + }; + mc: memory-controller@70019000 { compatible = "nvidia,tegra124-mc"; reg = <0x0 0x70019000 0x0 0x1000>; @@ -906,16 +916,6 @@ status = "disabled"; }; - cec@70015000 { - compatible = "nvidia,tegra124-cec"; - reg = <0x0 0x70015000 0x0 0x00001000>; - interrupts = ; - clocks = <&tegra_car TEGRA124_CLK_CEC>; - clock-names = "cec"; - status = "disabled"; - hdmi-phandle = <&hdmi>; - }; - soctherm: thermal-sensor@700e2000 { compatible = "nvidia,tegra124-soctherm"; reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */ diff --git a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts index 17afc2c7cb37b7fcc7d75d9a547027f097219044..08b42952f4de39530f9abc502e8948c4adb43443 100644 --- a/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts +++ b/arch/arm/boot/dts/tegra20-acer-a500-picasso.dts @@ -347,31 +347,34 @@ nvidia,pins = "ddc"; nvidia,function = "i2c2"; }; + pta { nvidia,pins = "pta"; nvidia,function = "rsvd4"; }; }; - state_i2cmux_pta: pinmux-i2cmux-pta { + state_i2cmux_idle: pinmux-i2cmux-idle { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; + pta { nvidia,pins = "pta"; - nvidia,function = "i2c2"; + nvidia,function = "rsvd4"; }; }; - state_i2cmux_idle: pinmux-i2cmux-idle { + state_i2cmux_pta: pinmux-i2cmux-pta { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; + pta { nvidia,pins = "pta"; - nvidia,function = "rsvd4"; + nvidia,function = "i2c2"; }; }; }; @@ -425,6 +428,10 @@ /* Docking station */ }; + pwm: pwm@7000a000 { + status = "okay"; + }; + i2c@7000c000 { clock-frequency = <400000>; status = "okay"; @@ -512,45 +519,6 @@ status = "okay"; }; - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - panel_ddc: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - embedded-controller@58 { - compatible = "acer,a500-iconia-ec", "ene,kb930"; - reg = <0x58>; - - system-power-controller; - - monitored-battery = <&bat1010>; - power-supplies = <&mains>; - }; - }; - }; - - pwm: pwm@7000a000 { - status = "okay"; - }; - i2c@7000d000 { clock-frequency = <100000>; status = "okay"; @@ -729,71 +697,456 @@ core-supply = <&vdd_core>; }; - usb@c5000000 { - compatible = "nvidia,tegra20-udc"; - status = "okay"; - dr_mode = "peripheral"; - }; + memory-controller@7000f400 { + nvidia,use-ram-code; - usb-phy@c5000000 { - status = "okay"; - dr_mode = "peripheral"; - nvidia,xcvr-setup-use-fuses; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - }; + emc-tables@0 { + nvidia,ram-code = <0>; /* elpida-8gb */ + reg = <0>; - usb@c5008000 { - status = "okay"; - }; + #address-cells = <1>; + #size-cells = <0>; - usb-phy@c5008000 { - status = "okay"; - nvidia,xcvr-setup-use-fuses; - nvidia,xcvr-lsfslew = <2>; - nvidia,xcvr-lsrslew = <2>; - vbus-supply = <&vdd_5v0_sys>; - }; + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; - brcm_wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; - clocks = <&rtc_32k_wifi>; - clock-names = "ext_clock"; + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; - reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <300>; - power-off-delay-us = <300>; - }; + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007dd510 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; - sdmmc1: mmc@c8000000 { - status = "okay"; + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e1 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e1510 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; - #address-cells = <1>; - #size-cells = <0>; + emc-tables@1 { + nvidia,ram-code = <1>; /* elpida-4gb */ + reg = <1>; - assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; - assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; - assigned-clock-rates = <50000000>; + #address-cells = <1>; + #size-cells = <0>; - max-frequency = <50000000>; - keep-power-in-suspend; - bus-width = <4>; - non-removable; + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; - mmc-pwrseq = <&brcm_wifi_pwrseq>; - vmmc-supply = <&vdd_3v3_sys>; - vqmmc-supply = <&vdd_1v8_sys>; + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00000000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; - /* Azurewave AW-NH611 BCM4329 */ - wifi@1 { - reg = <1>; - compatible = "brcm,bcm4329-fmac"; - interrupt-parent = <&gpio>; - interrupts = ; - interrupt-names = "host-wake"; - }; - }; + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007e4010 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e1 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e0010 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + + emc-tables@2 { + nvidia,ram-code = <2>; /* hynix-8gb */ + reg = <2>; + + #address-cells = <1>; + #size-cells = <0>; + + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x00070000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007dd010 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e1 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e2010 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + + emc-tables@3 { + nvidia,ram-code = <3>; /* hynix-4gb */ + reg = <3>; + + #address-cells = <1>; + #size-cells = <0>; + + emc-table@25000 { + reg = <25000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <25000>; + nvidia,emc-registers = <0x00000002 0x00000006 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000004 + 0x00000003 0x00000008 0x0000000b 0x0000004d + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000004 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000068 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00000000 0x00000000 0x00000003 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@50000 { + reg = <50000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <50000>; + nvidia,emc-registers = <0x00000003 0x00000007 + 0x00000003 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000009f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000007 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x000000d0 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00078000 0x00000000 0x00000005 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@75000 { + reg = <75000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <75000>; + nvidia,emc-registers = <0x00000005 0x0000000a + 0x00000004 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x000000ff + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x0000000b + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000138 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000282 0xa0ae04ae + 0x0007c000 0x00000000 0x00000000 0x00000007 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@150000 { + reg = <150000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <150000>; + nvidia,emc-registers = <0x00000009 0x00000014 + 0x00000007 0x00000003 0x00000006 0x00000004 + 0x00000002 0x00000009 0x00000003 0x00000003 + 0x00000002 0x00000002 0x00000002 0x00000005 + 0x00000003 0x00000008 0x0000000b 0x0000021f + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000008 0x00000001 0x0000000a 0x00000015 + 0x00000003 0x00000008 0x00000004 0x00000006 + 0x00000002 0x00000270 0x00000000 0x00000001 + 0x00000000 0x00000000 0x00000282 0xa07c04ae + 0x007e4010 0x00000000 0x00000000 0x0000000e + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@300000 { + reg = <300000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <300000>; + nvidia,emc-registers = <0x00000012 0x00000027 + 0x0000000d 0x00000006 0x00000007 0x00000005 + 0x00000003 0x00000009 0x00000006 0x00000006 + 0x00000003 0x00000003 0x00000002 0x00000006 + 0x00000003 0x00000009 0x0000000c 0x0000045f + 0x00000000 0x00000004 0x00000004 0x00000006 + 0x00000008 0x00000001 0x0000000e 0x0000002a + 0x00000003 0x0000000f 0x00000007 0x00000005 + 0x00000002 0x000004e1 0x00000005 0x00000002 + 0x00000000 0x00000000 0x00000282 0xe059048b + 0x007e0010 0x00000000 0x00000000 0x0000001b + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + }; + + usb@c5000000 { + compatible = "nvidia,tegra20-udc"; + status = "okay"; + dr_mode = "peripheral"; + }; + + usb-phy@c5000000 { + status = "okay"; + dr_mode = "peripheral"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + }; + + usb@c5008000 { + status = "okay"; + }; + + usb-phy@c5008000 { + status = "okay"; + nvidia,xcvr-setup-use-fuses; + nvidia,xcvr-lsfslew = <2>; + nvidia,xcvr-lsrslew = <2>; + vbus-supply = <&vdd_5v0_sys>; + }; + + sdmmc1: mmc@c8000000 { + status = "okay"; + + #address-cells = <1>; + #size-cells = <0>; + + assigned-clocks = <&tegra_car TEGRA20_CLK_SDMMC1>; + assigned-clock-parents = <&tegra_car TEGRA20_CLK_PLL_C>; + assigned-clock-rates = <50000000>; + + max-frequency = <50000000>; + keep-power-in-suspend; + bus-width = <4>; + non-removable; + + mmc-pwrseq = <&brcm_wifi_pwrseq>; + vmmc-supply = <&vdd_3v3_sys>; + vqmmc-supply = <&vdd_1v8_sys>; + + /* Azurewave AW-NH611 BCM4329 */ + wifi@1 { + reg = <1>; + compatible = "brcm,bcm4329-fmac"; + interrupt-parent = <&gpio>; + interrupts = ; + interrupt-names = "host-wake"; + }; + }; sdmmc3: mmc@c8000400 { status = "okay"; @@ -922,19 +1275,19 @@ debounce-interval = <10>; }; - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - linux,code = ; + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; + linux,code = ; debounce-interval = <10>; wakeup-event-action = ; wakeup-source; }; - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; - linux,code = ; + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + linux,code = ; debounce-interval = <10>; wakeup-event-action = ; wakeup-source; @@ -947,576 +1300,226 @@ vcc-supply = <&vdd_3v3_sys>; }; - lvds-encoder { - compatible = "ti,sn75lvds83", "lvds-encoder"; + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; - powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; - power-supply = <&vdd_3v3_sys>; + i2c-parent = <&{/i2c@7000c400}>; - ports { + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; #address-cells = <1>; #size-cells = <0>; - - port@0 { - reg = <0>; - - lvds_encoder_input: endpoint { - remote-endpoint = <&lcd_output>; - }; - }; - - port@1 { - reg = <1>; - - lvds_encoder_output: endpoint { - remote-endpoint = <&panel_input>; - }; - }; }; - }; - - vdd_5v0_sys: regulator-5v0 { - compatible = "regulator-fixed"; - regulator-name = "vdd_5v0"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - regulator-always-on; - }; - - vdd_3v3_sys: regulator-3v3 { - compatible = "regulator-fixed"; - regulator-name = "vdd_3v3_vs"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - vin-supply = <&vdd_5v0_sys>; - }; - vdd_1v8_sys: regulator-1v8 { - compatible = "regulator-fixed"; - regulator-name = "vdd_1v8_vs"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - vin-supply = <&vdd_5v0_sys>; - }; - - vdd_pnl: regulator-panel { - compatible = "regulator-fixed"; - regulator-name = "vdd_panel"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-enable-ramp-delay = <300000>; - gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; - enable-active-high; - vin-supply = <&vdd_5v0_sys>; - }; - - sound { - compatible = "nvidia,tegra-audio-wm8903-picasso", - "nvidia,tegra-audio-wm8903"; - nvidia,model = "Acer Iconia Tab A500 WM8903"; - - nvidia,audio-routing = - "Headphone Jack", "HPOUTR", - "Headphone Jack", "HPOUTL", - "Int Spk", "LINEOUTL", - "Int Spk", "LINEOUTR", - "Mic Jack", "MICBIAS", - "IN2L", "Mic Jack", - "IN2R", "Mic Jack", - "IN1L", "Int Mic", - "IN1R", "Int Mic"; - - nvidia,i2s-controller = <&tegra_i2s1>; - nvidia,audio-codec = <&wm8903>; - - nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; - nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; - nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>; - nvidia,headset; - - clocks = <&tegra_car TEGRA20_CLK_PLL_A>, - <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, - <&tegra_car TEGRA20_CLK_CDEV1>; - clock-names = "pll_a", "pll_a_out0", "mclk"; - }; - - thermal-zones { - /* - * NCT1008 has two sensors: - * - * 0: internal that monitors ambient/skin temperature - * 1: external that is connected to the CPU's diode - * - * Ideally we should use userspace thermal governor, - * but it's a much more complex solution. The "skin" - * zone is a simpler solution which prevents A500 from - * getting too hot from a user's tactile perspective. - * The CPU zone is intended to protect silicon from damage. - */ - - skin-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&nct1008 0>; - - trips { - trip0: skin-alert { - /* start throttling at 60C */ - temperature = <60000>; - hysteresis = <200>; - type = "passive"; - }; - - trip1: skin-crit { - /* shut down at 70C */ - temperature = <70000>; - hysteresis = <2000>; - type = "critical"; - }; - }; - - cooling-maps { - map0 { - trip = <&trip0>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - }; - }; - - cpu-thermal { - polling-delay-passive = <1000>; /* milliseconds */ - polling-delay = <5000>; /* milliseconds */ - - thermal-sensors = <&nct1008 1>; - - trips { - trip2: cpu-alert { - /* throttle at 85C until temperature drops to 84.8C */ - temperature = <85000>; - hysteresis = <200>; - type = "passive"; - }; - - trip3: cpu-crit { - /* shut down at 90C */ - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; + panel_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; - cooling-maps { - map1 { - trip = <&trip2>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; + embedded-controller@58 { + compatible = "acer,a500-iconia-ec", "ene,kb930"; + reg = <0x58>; + + system-power-controller; + + monitored-battery = <&bat1010>; + power-supplies = <&mains>; }; }; }; - memory-controller@7000f400 { - nvidia,use-ram-code; + lvds-encoder { + compatible = "ti,sn75lvds83", "lvds-encoder"; - emc-tables@0 { - nvidia,ram-code = <0>; /* elpida-8gb */ - reg = <0>; + powerdown-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_LOW>; + power-supply = <&vdd_3v3_sys>; + ports { #address-cells = <1>; #size-cells = <0>; - emc-table@25000 { - reg = <25000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <25000>; - nvidia,emc-registers = <0x00000002 0x00000006 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000004 - 0x00000003 0x00000008 0x0000000b 0x0000004d - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000004 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000068 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@50000 { - reg = <50000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <50000>; - nvidia,emc-registers = <0x00000003 0x00000007 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000009f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000007 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x000000d0 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000005 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + port@0 { + reg = <0>; - emc-table@75000 { - reg = <75000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <75000>; - nvidia,emc-registers = <0x00000005 0x0000000a - 0x00000004 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x000000ff - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x0000000b - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000138 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000007 - 0x00000000 0x00000000 0x00000000 0x00000000>; + lvds_encoder_input: endpoint { + remote-endpoint = <&lcd_output>; + }; }; - emc-table@150000 { - reg = <150000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <150000>; - nvidia,emc-registers = <0x00000009 0x00000014 - 0x00000007 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000021f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000015 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000270 0x00000000 0x00000001 - 0x00000000 0x00000000 0x00000282 0xa07c04ae - 0x007dd510 0x00000000 0x00000000 0x0000000e - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + port@1 { + reg = <1>; - emc-table@300000 { - reg = <300000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <300000>; - nvidia,emc-registers = <0x00000012 0x00000027 - 0x0000000d 0x00000006 0x00000007 0x00000005 - 0x00000003 0x00000009 0x00000006 0x00000006 - 0x00000003 0x00000003 0x00000002 0x00000006 - 0x00000003 0x00000009 0x0000000c 0x0000045f - 0x00000000 0x00000004 0x00000004 0x00000006 - 0x00000008 0x00000001 0x0000000e 0x0000002a - 0x00000003 0x0000000f 0x00000007 0x00000005 - 0x00000002 0x000004e1 0x00000005 0x00000002 - 0x00000000 0x00000000 0x00000282 0xe059048b - 0x007e1510 0x00000000 0x00000000 0x0000001b - 0x00000000 0x00000000 0x00000000 0x00000000>; + lvds_encoder_output: endpoint { + remote-endpoint = <&panel_input>; + }; }; }; + }; - emc-tables@1 { - nvidia,ram-code = <1>; /* elpida-4gb */ - reg = <1>; + opp-table-emc { + /delete-node/ opp-666000000; + /delete-node/ opp-760000000; + }; - #address-cells = <1>; - #size-cells = <0>; + vdd_5v0_sys: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "vdd_5v0"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; - emc-table@25000 { - reg = <25000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <25000>; - nvidia,emc-registers = <0x00000002 0x00000006 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000004 - 0x00000003 0x00000008 0x0000000b 0x0000004d - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000004 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000068 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x0007c000 0x00000000 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + vdd_3v3_sys: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "vdd_3v3_vs"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; - emc-table@50000 { - reg = <50000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <50000>; - nvidia,emc-registers = <0x00000003 0x00000007 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000009f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000007 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x000000d0 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x0007c000 0x00000000 0x00000000 0x00000005 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + vdd_1v8_sys: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "vdd_1v8_vs"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + vin-supply = <&vdd_5v0_sys>; + }; - emc-table@75000 { - reg = <75000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <75000>; - nvidia,emc-registers = <0x00000005 0x0000000a - 0x00000004 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x000000ff - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x0000000b - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000138 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x0007c000 0x00000000 0x00000000 0x00000007 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + vdd_pnl: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "vdd_panel"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-enable-ramp-delay = <300000>; + gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <&vdd_5v0_sys>; + }; - emc-table@150000 { - reg = <150000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <150000>; - nvidia,emc-registers = <0x00000009 0x00000014 - 0x00000007 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000021f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000015 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000270 0x00000000 0x00000001 - 0x00000000 0x00000000 0x00000282 0xa07c04ae - 0x007e4010 0x00000000 0x00000000 0x0000000e - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + sound { + compatible = "nvidia,tegra-audio-wm8903-picasso", + "nvidia,tegra-audio-wm8903"; + nvidia,model = "Acer Iconia Tab A500 WM8903"; - emc-table@300000 { - reg = <300000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <300000>; - nvidia,emc-registers = <0x00000012 0x00000027 - 0x0000000d 0x00000006 0x00000007 0x00000005 - 0x00000003 0x00000009 0x00000006 0x00000006 - 0x00000003 0x00000003 0x00000002 0x00000006 - 0x00000003 0x00000009 0x0000000c 0x0000045f - 0x00000000 0x00000004 0x00000004 0x00000006 - 0x00000008 0x00000001 0x0000000e 0x0000002a - 0x00000003 0x0000000f 0x00000007 0x00000005 - 0x00000002 0x000004e1 0x00000005 0x00000002 - 0x00000000 0x00000000 0x00000282 0xe059048b - 0x007e0010 0x00000000 0x00000000 0x0000001b - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - }; + nvidia,audio-routing = + "Headphone Jack", "HPOUTR", + "Headphone Jack", "HPOUTL", + "Int Spk", "LINEOUTL", + "Int Spk", "LINEOUTR", + "Mic Jack", "MICBIAS", + "IN2L", "Mic Jack", + "IN2R", "Mic Jack", + "IN1L", "Int Mic", + "IN1R", "Int Mic"; + + nvidia,i2s-controller = <&tegra_i2s1>; + nvidia,audio-codec = <&wm8903>; + + nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; + nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_LOW>; + nvidia,int-mic-en-gpios = <&wm8903 1 GPIO_ACTIVE_HIGH>; + nvidia,headset; - emc-tables@2 { - nvidia,ram-code = <2>; /* hynix-8gb */ - reg = <2>; + clocks = <&tegra_car TEGRA20_CLK_PLL_A>, + <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, + <&tegra_car TEGRA20_CLK_CDEV1>; + clock-names = "pll_a", "pll_a_out0", "mclk"; + }; - #address-cells = <1>; - #size-cells = <0>; + thermal-zones { + /* + * NCT1008 has two sensors: + * + * 0: internal that monitors ambient/skin temperature + * 1: external that is connected to the CPU's diode + * + * Ideally we should use userspace thermal governor, + * but it's a much more complex solution. The "skin" + * zone is a simpler solution which prevents A500 from + * getting too hot from a user's tactile perspective. + * The CPU zone is intended to protect silicon from damage. + */ - emc-table@25000 { - reg = <25000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <25000>; - nvidia,emc-registers = <0x00000002 0x00000006 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000004 - 0x00000003 0x00000008 0x0000000b 0x0000004d - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000004 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000068 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + skin-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ - emc-table@50000 { - reg = <50000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <50000>; - nvidia,emc-registers = <0x00000003 0x00000007 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000009f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000007 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x000000d0 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000005 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + thermal-sensors = <&nct1008 0>; - emc-table@75000 { - reg = <75000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <75000>; - nvidia,emc-registers = <0x00000005 0x0000000a - 0x00000004 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x000000ff - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x0000000b - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000138 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x00070000 0x00000000 0x00000000 0x00000007 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + trips { + trip0: skin-alert { + /* start throttling at 60C */ + temperature = <60000>; + hysteresis = <200>; + type = "passive"; + }; - emc-table@150000 { - reg = <150000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <150000>; - nvidia,emc-registers = <0x00000009 0x00000014 - 0x00000007 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000021f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000015 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000270 0x00000000 0x00000001 - 0x00000000 0x00000000 0x00000282 0xa07c04ae - 0x007dd010 0x00000000 0x00000000 0x0000000e - 0x00000000 0x00000000 0x00000000 0x00000000>; + trip1: skin-crit { + /* shut down at 70C */ + temperature = <70000>; + hysteresis = <2000>; + type = "critical"; + }; }; - emc-table@300000 { - reg = <300000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <300000>; - nvidia,emc-registers = <0x00000012 0x00000027 - 0x0000000d 0x00000006 0x00000007 0x00000005 - 0x00000003 0x00000009 0x00000006 0x00000006 - 0x00000003 0x00000003 0x00000002 0x00000006 - 0x00000003 0x00000009 0x0000000c 0x0000045f - 0x00000000 0x00000004 0x00000004 0x00000006 - 0x00000008 0x00000001 0x0000000e 0x0000002a - 0x00000003 0x0000000f 0x00000007 0x00000005 - 0x00000002 0x000004e1 0x00000005 0x00000002 - 0x00000000 0x00000000 0x00000282 0xe059048b - 0x007e2010 0x00000000 0x00000000 0x0000001b - 0x00000000 0x00000000 0x00000000 0x00000000>; + cooling-maps { + map0 { + trip = <&trip0>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; }; }; - emc-tables@3 { - nvidia,ram-code = <3>; /* hynix-4gb */ - reg = <3>; - - #address-cells = <1>; - #size-cells = <0>; - - emc-table@25000 { - reg = <25000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <25000>; - nvidia,emc-registers = <0x00000002 0x00000006 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000004 - 0x00000003 0x00000008 0x0000000b 0x0000004d - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000004 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000068 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x0007c000 0x00000000 0x00000000 0x00000003 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <5000>; /* milliseconds */ - emc-table@50000 { - reg = <50000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <50000>; - nvidia,emc-registers = <0x00000003 0x00000007 - 0x00000003 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000009f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000007 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x000000d0 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x0007c000 0x00078000 0x00000000 0x00000005 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + thermal-sensors = <&nct1008 1>; - emc-table@75000 { - reg = <75000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <75000>; - nvidia,emc-registers = <0x00000005 0x0000000a - 0x00000004 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x000000ff - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x0000000b - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000138 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000282 0xa0ae04ae - 0x0007c000 0x00000000 0x00000000 0x00000007 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; + trips { + trip2: cpu-alert { + /* throttle at 85C until temperature drops to 84.8C */ + temperature = <85000>; + hysteresis = <200>; + type = "passive"; + }; - emc-table@150000 { - reg = <150000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <150000>; - nvidia,emc-registers = <0x00000009 0x00000014 - 0x00000007 0x00000003 0x00000006 0x00000004 - 0x00000002 0x00000009 0x00000003 0x00000003 - 0x00000002 0x00000002 0x00000002 0x00000005 - 0x00000003 0x00000008 0x0000000b 0x0000021f - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000008 0x00000001 0x0000000a 0x00000015 - 0x00000003 0x00000008 0x00000004 0x00000006 - 0x00000002 0x00000270 0x00000000 0x00000001 - 0x00000000 0x00000000 0x00000282 0xa07c04ae - 0x007e4010 0x00000000 0x00000000 0x0000000e - 0x00000000 0x00000000 0x00000000 0x00000000>; + trip3: cpu-crit { + /* shut down at 90C */ + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; }; - emc-table@300000 { - reg = <300000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <300000>; - nvidia,emc-registers = <0x00000012 0x00000027 - 0x0000000d 0x00000006 0x00000007 0x00000005 - 0x00000003 0x00000009 0x00000006 0x00000006 - 0x00000003 0x00000003 0x00000002 0x00000006 - 0x00000003 0x00000009 0x0000000c 0x0000045f - 0x00000000 0x00000004 0x00000004 0x00000006 - 0x00000008 0x00000001 0x0000000e 0x0000002a - 0x00000003 0x0000000f 0x00000007 0x00000005 - 0x00000002 0x000004e1 0x00000005 0x00000002 - 0x00000000 0x00000000 0x00000282 0xe059048b - 0x007e0010 0x00000000 0x00000000 0x0000001b - 0x00000000 0x00000000 0x00000000 0x00000000>; + cooling-maps { + map1 { + trip = <&trip2>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; }; }; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-666000000; - /delete-node/ opp-760000000; + brcm_wifi_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + + clocks = <&rtc_32k_wifi>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; }; diff --git a/arch/arm/boot/dts/tegra20-asus-tf101.dts b/arch/arm/boot/dts/tegra20-asus-tf101.dts index c39ddb462ad01bf320d3c8a0b25dbb19fd22af84..7b2969656ec964a144a02b9617deed2cddc59d0f 100644 --- a/arch/arm/boot/dts/tegra20-asus-tf101.dts +++ b/arch/arm/boot/dts/tegra20-asus-tf101.dts @@ -411,7 +411,7 @@ }; }; - state_i2cmux_pta: pinmux-i2cmux-pta { + state_i2cmux_idle: pinmux-i2cmux-idle { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; @@ -419,11 +419,11 @@ pta { nvidia,pins = "pta"; - nvidia,function = "i2c2"; + nvidia,function = "rsvd4"; }; }; - state_i2cmux_idle: pinmux-i2cmux-idle { + state_i2cmux_pta: pinmux-i2cmux-pta { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; @@ -431,7 +431,7 @@ pta { nvidia,pins = "pta"; - nvidia,function = "rsvd4"; + nvidia,function = "i2c2"; }; }; }; @@ -764,13 +764,6 @@ #address-cells = <1>; #size-cells = <0>; - lpddr2 { - compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4"; - revision-id = <1 0>; - density = <2048>; - io-width = <16>; - }; - emc-table@25000 { reg = <25000>; compatible = "nvidia,tegra20-emc-table"; @@ -860,6 +853,13 @@ 0x007e0010 0x00000000 0x00000000 0x0000001b 0x00000000 0x00000000 0x00000000 0x00000000>; }; + + lpddr2 { + compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4"; + revision-id = <1 0>; + density = <2048>; + io-width = <16>; + }; }; }; @@ -977,47 +977,6 @@ }; }; - gpio-keys { - compatible = "gpio-keys"; - - switch-dock-hall-sensor { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <500>; - wakeup-event-action = ; - wakeup-source; - }; - - key-power { - label = "Power"; - gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; - wakeup-source; - }; - }; - display-panel { compatible = "auo,b101ew05", "panel-lvds"; @@ -1051,6 +1010,47 @@ }; }; + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 5) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + + switch-dock-hall-sensor { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(S, 4) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <500>; + wakeup-event-action = ; + wakeup-source; + }; + }; + i2cmux { compatible = "i2c-mux-pinctrl"; #address-cells = <1>; @@ -1112,6 +1112,11 @@ }; }; + opp-table-emc { + /delete-node/ opp-666000000; + /delete-node/ opp-760000000; + }; + vdd_5v0_sys: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; @@ -1283,8 +1288,3 @@ power-off-delay-us = <200>; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-666000000; - /delete-node/ opp-760000000; -}; diff --git a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts index cb1190b77db3530e8473165cba4f2f0cfd17d0c3..612f4e54cb2028e7fca5d9c7d287ca2db99e9566 100644 --- a/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra20-colibri-eval-v3.dts @@ -143,6 +143,24 @@ status = "okay"; }; + /* SPI4: Colibri SSP */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + + can@0 { + compatible = "microchip,mcp2515"; + reg = <0>; + clocks = <&clk16m>; + interrupt-parent = <&gpio>; + /* CAN_INT */ + interrupts = ; + spi-max-frequency = <10000000>; + vdd-supply = <®_3v3>; + xceiver-supply = <®_5v0>; + }; + }; + /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ usb@c5000000 { status = "okay"; @@ -164,24 +182,6 @@ vbus-supply = <®_usbh_vbus>; }; - /* SPI4: Colibri SSP */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - - can@0 { - compatible = "microchip,mcp2515"; - reg = <0>; - clocks = <&clk16m>; - interrupt-parent = <&gpio>; - /* CAN_INT */ - interrupts = ; - spi-max-frequency = <10000000>; - vdd-supply = <®_3v3>; - xceiver-supply = <®_5v0>; - }; - }; - /* SD/MMC */ mmc@c8000600 { status = "okay"; @@ -200,7 +200,7 @@ pwms = <&pwm 0 5000000>; /* PWM */ }; - clk16m: osc3 { + clk16m: clock-osc3 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <16000000>; diff --git a/arch/arm/boot/dts/tegra20-colibri-iris.dts b/arch/arm/boot/dts/tegra20-colibri-iris.dts index 53487cc21513809464c5514936349a08b4e50f60..25a9f5dfe62d00406f6de82b7fe491a84143b031 100644 --- a/arch/arm/boot/dts/tegra20-colibri-iris.dts +++ b/arch/arm/boot/dts/tegra20-colibri-iris.dts @@ -143,6 +143,12 @@ status = "okay"; }; + /* SPI4: Colibri SSP */ + spi@7000da00 { + status = "okay"; + spi-max-frequency = <25000000>; + }; + /* EHCI instance 0: USB1_DP/N -> USBC_P/N */ usb@c5000000 { status = "okay"; @@ -164,12 +170,6 @@ vbus-supply = <®_usbh_vbus>; }; - /* SPI4: Colibri SSP */ - spi@7000da00 { - status = "okay"; - spi-max-frequency = <25000000>; - }; - /* SD/MMC */ mmc@c8000600 { status = "okay"; diff --git a/arch/arm/boot/dts/tegra20-colibri.dtsi b/arch/arm/boot/dts/tegra20-colibri.dtsi index 8ebd8afc857da38193f0a08b481a083082537c70..0e03910abbe6406a62a3a94b4a36b7c641d68d98 100644 --- a/arch/arm/boot/dts/tegra20-colibri.dtsi +++ b/arch/arm/boot/dts/tegra20-colibri.dtsi @@ -27,6 +27,31 @@ }; }; + gpio@6000d000 { + lan-reset-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "LAN_RESET#"; + }; + + /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */ + npwe-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "Tri-state nPWE"; + }; + + /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */ + rdnwr-hog { + gpio-hog; + gpios = ; + output-low; + line-name = "Not tri-state RDnWR"; + }; + }; + pinmux@70000014 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -705,12 +730,16 @@ vbus-supply = <®_lan_v_bus>; }; - clk32k_in: xtal3 { + clk32k_in: clock-xtal3 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; }; + opp-table-emc { + /delete-node/ opp-760000000; + }; + reg_lan_v_bus: regulator-lan-v-bus { compatible = "regulator-fixed"; regulator-name = "LAN_V_BUS"; @@ -745,32 +774,3 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-760000000; -}; - -&gpio { - lan-reset-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "LAN_RESET#"; - }; - - /* Tri-stating GMI_WR_N on SODIMM pin 99 nPWE */ - npwe-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "Tri-state nPWE"; - }; - - /* Not tri-stating GMI_WR_N on SODIMM pin 93 RDnWR */ - rdnwr-hog { - gpio-hog; - gpios = ; - output-low; - line-name = "Not tri-state RDnWR"; - }; -}; diff --git a/arch/arm/boot/dts/tegra20-medcom-wide.dts b/arch/arm/boot/dts/tegra20-medcom-wide.dts index f144487c5da3c1dd2471768adb8da2ec73d67185..8c657182fff32c9255dffe80c60debdca03f8154 100644 --- a/arch/arm/boot/dts/tegra20-medcom-wide.dts +++ b/arch/arm/boot/dts/tegra20-medcom-wide.dts @@ -15,10 +15,6 @@ stdout-path = "serial0:115200n8"; }; - pwm@7000a000 { - status = "okay"; - }; - host1x@50000000 { dc@54200000 { rgb { @@ -28,6 +24,10 @@ }; }; + pwm@7000a000 { + status = "okay"; + }; + i2c@7000c000 { wm8903: wm8903@1a { compatible = "wlf,wm8903"; diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts index 48fe628c6d875223830b2c4d1e458250cb535128..e995f428dc2eae71389c80ff9005c7909f77eb8e 100644 --- a/arch/arm/boot/dts/tegra20-paz00.dts +++ b/arch/arm/boot/dts/tegra20-paz00.dts @@ -323,53 +323,6 @@ reset-names = "i2c"; }; - memory-controller@7000f400 { - nvidia,use-ram-code; - - emc-tables@0 { - nvidia,ram-code = <0x0>; - #address-cells = <1>; - #size-cells = <0>; - reg = <0>; - - emc-table@166500 { - reg = <166500>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <166500>; - nvidia,emc-registers = <0x0000000a 0x00000016 - 0x00000008 0x00000003 0x00000004 0x00000004 - 0x00000002 0x0000000c 0x00000003 0x00000003 - 0x00000002 0x00000001 0x00000004 0x00000005 - 0x00000004 0x00000009 0x0000000d 0x000004df - 0x00000000 0x00000003 0x00000003 0x00000003 - 0x00000003 0x00000001 0x0000000a 0x000000c8 - 0x00000003 0x00000006 0x00000004 0x00000008 - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0xe03b0323 - 0x007fe010 0x00001414 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - - emc-table@333000 { - reg = <333000>; - compatible = "nvidia,tegra20-emc-table"; - clock-frequency = <333000>; - nvidia,emc-registers = <0x00000018 0x00000033 - 0x00000012 0x00000004 0x00000004 0x00000005 - 0x00000003 0x0000000c 0x00000006 0x00000006 - 0x00000003 0x00000001 0x00000004 0x00000005 - 0x00000004 0x00000009 0x0000000d 0x00000bff - 0x00000000 0x00000003 0x00000003 0x00000006 - 0x00000006 0x00000001 0x00000011 0x000000c8 - 0x00000003 0x0000000e 0x00000007 0x00000008 - 0x00000002 0x00000000 0x00000000 0x00000002 - 0x00000000 0x00000000 0x00000083 0xf0440303 - 0x007fe010 0x00001414 0x00000000 0x00000000 - 0x00000000 0x00000000 0x00000000 0x00000000>; - }; - }; - }; - i2c@7000d000 { status = "okay"; clock-frequency = <400000>; @@ -532,6 +485,53 @@ core-supply = <&core_vdd_reg>; }; + memory-controller@7000f400 { + nvidia,use-ram-code; + + emc-tables@0 { + nvidia,ram-code = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + emc-table@166500 { + reg = <166500>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <166500>; + nvidia,emc-registers = <0x0000000a 0x00000016 + 0x00000008 0x00000003 0x00000004 0x00000004 + 0x00000002 0x0000000c 0x00000003 0x00000003 + 0x00000002 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x000004df + 0x00000000 0x00000003 0x00000003 0x00000003 + 0x00000003 0x00000001 0x0000000a 0x000000c8 + 0x00000003 0x00000006 0x00000004 0x00000008 + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xe03b0323 + 0x007fe010 0x00001414 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + + emc-table@333000 { + reg = <333000>; + compatible = "nvidia,tegra20-emc-table"; + clock-frequency = <333000>; + nvidia,emc-registers = <0x00000018 0x00000033 + 0x00000012 0x00000004 0x00000004 0x00000005 + 0x00000003 0x0000000c 0x00000006 0x00000006 + 0x00000003 0x00000001 0x00000004 0x00000005 + 0x00000004 0x00000009 0x0000000d 0x00000bff + 0x00000000 0x00000003 0x00000003 0x00000006 + 0x00000006 0x00000001 0x00000011 0x000000c8 + 0x00000003 0x0000000e 0x00000007 0x00000008 + 0x00000002 0x00000000 0x00000000 0x00000002 + 0x00000000 0x00000000 0x00000083 0xf0440303 + 0x007fe010 0x00001414 0x00000000 0x00000000 + 0x00000000 0x00000000 0x00000000 0x00000000>; + }; + }; + }; + usb@c5000000 { compatible = "nvidia,tegra20-udc"; status = "okay"; @@ -593,6 +593,20 @@ #clock-cells = <0>; }; + cpus { + cpu0: cpu@0 { + cpu-supply = <&cpu_vdd_reg>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + cpu-supply = <&cpu_vdd_reg>; + operating-points-v2 = <&cpu0_opp_table>; + #cooling-cells = <2>; + }; + }; + gpio-keys { compatible = "gpio-keys"; @@ -614,6 +628,10 @@ }; }; + opp-table-emc { + /delete-node/ opp-760000000; + }; + panel: panel { compatible = "samsung,ltn101nt05"; @@ -668,20 +686,6 @@ clock-names = "pll_a", "pll_a_out0", "mclk"; }; - cpus { - cpu0: cpu@0 { - cpu-supply = <&cpu_vdd_reg>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - - cpu1: cpu@1 { - cpu-supply = <&cpu_vdd_reg>; - operating-points-v2 = <&cpu0_opp_table>; - #cooling-cells = <2>; - }; - }; - thermal-zones { cpu-thermal { polling-delay-passive = <500>; /* milliseconds */ @@ -715,7 +719,3 @@ }; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-760000000; -}; diff --git a/arch/arm/boot/dts/tegra20-seaboard.dts b/arch/arm/boot/dts/tegra20-seaboard.dts index ab33ff67fdb9dcf9fbcd19f77a3bfc3851990995..bd4ff8b40b208fbd918134f68e036a48ac0f5705 100644 --- a/arch/arm/boot/dts/tegra20-seaboard.dts +++ b/arch/arm/boot/dts/tegra20-seaboard.dts @@ -296,25 +296,25 @@ }; }; - state_i2cmux_pta: pinmux-i2cmux-pta { + state_i2cmux_idle: pinmux-i2cmux-idle { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; pta { nvidia,pins = "pta"; - nvidia,function = "i2c2"; + nvidia,function = "rsvd4"; }; }; - state_i2cmux_idle: pinmux-i2cmux-idle { + state_i2cmux_pta: pinmux-i2cmux-pta { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; pta { nvidia,pins = "pta"; - nvidia,function = "rsvd4"; + nvidia,function = "i2c2"; }; }; }; @@ -370,38 +370,6 @@ clock-frequency = <100000>; }; - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - lvds_ddc: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - smart-battery@b { - compatible = "ti,bq20z75", "sbs,sbs-battery"; - reg = <0xb>; - sbs,i2c-retry-count = <2>; - sbs,poll-retry-count = <10>; - }; - }; - }; - i2c@7000c500 { status = "okay"; clock-frequency = <400000>; @@ -817,6 +785,38 @@ }; }; + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + lvds_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + smart-battery@b { + compatible = "ti,bq20z75", "sbs,sbs-battery"; + reg = <0xb>; + sbs,i2c-retry-count = <2>; + sbs,poll-retry-count = <10>; + }; + }; + }; + panel: panel { compatible = "chunghwa,claa101wa01a"; diff --git a/arch/arm/boot/dts/tegra20-tamonten.dtsi b/arch/arm/boot/dts/tegra20-tamonten.dtsi index 980272ad59a412827052af9d1c2b9ba2ba315511..ddb84e4a9f8b69e9314dd6aed7a7dc65a3233269 100644 --- a/arch/arm/boot/dts/tegra20-tamonten.dtsi +++ b/arch/arm/boot/dts/tegra20-tamonten.dtsi @@ -260,25 +260,25 @@ }; }; - state_i2cmux_pta: pinmux-i2cmux-pta { + state_i2cmux_idle: pinmux-i2cmux-idle { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; pta { nvidia,pins = "pta"; - nvidia,function = "i2c2"; + nvidia,function = "rsvd4"; }; }; - state_i2cmux_idle: pinmux-i2cmux-idle { + state_i2cmux_pta: pinmux-i2cmux-pta { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; pta { nvidia,pins = "pta"; - nvidia,function = "rsvd4"; + nvidia,function = "i2c2"; }; }; }; @@ -301,31 +301,6 @@ status = "okay"; }; - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - i2c@7000d000 { clock-frequency = <400000>; status = "okay"; @@ -509,6 +484,31 @@ #clock-cells = <0>; }; + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + pci_vdd_reg: regulator-1v05 { compatible = "regulator-fixed"; regulator-name = "vdd_1v05"; diff --git a/arch/arm/boot/dts/tegra20-trimslice.dts b/arch/arm/boot/dts/tegra20-trimslice.dts index dc51835423a9e760547a5a5aa855b7611c5b6d71..1944121e2dd6b713d4e8877f5ac1982477764ac2 100644 --- a/arch/arm/boot/dts/tegra20-trimslice.dts +++ b/arch/arm/boot/dts/tegra20-trimslice.dts @@ -385,6 +385,16 @@ #clock-cells = <0>; }; + cpus { + cpu0: cpu@0 { + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + gpio-keys { compatible = "gpio-keys"; @@ -462,14 +472,4 @@ <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; - - cpus { - cpu0: cpu@0 { - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@1 { - operating-points-v2 = <&cpu0_opp_table>; - }; - }; }; diff --git a/arch/arm/boot/dts/tegra20-ventana.dts b/arch/arm/boot/dts/tegra20-ventana.dts index 2d7bb442d6b6a0e0bcffa3b6dcf31bbd10398a43..433575a6ad38fe7a6c8e30ee080e1d4fec873738 100644 --- a/arch/arm/boot/dts/tegra20-ventana.dts +++ b/arch/arm/boot/dts/tegra20-ventana.dts @@ -295,25 +295,25 @@ }; }; - state_i2cmux_pta: pinmux-i2cmux-pta { + state_i2cmux_idle: pinmux-i2cmux-idle { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; pta { nvidia,pins = "pta"; - nvidia,function = "i2c2"; + nvidia,function = "rsvd4"; }; }; - state_i2cmux_idle: pinmux-i2cmux-idle { + state_i2cmux_pta: pinmux-i2cmux-pta { ddc { nvidia,pins = "ddc"; nvidia,function = "rsvd4"; }; pta { nvidia,pins = "pta"; - nvidia,function = "rsvd4"; + nvidia,function = "i2c2"; }; }; }; @@ -362,31 +362,6 @@ clock-frequency = <100000>; }; - i2cmux { - compatible = "i2c-mux-pinctrl"; - #address-cells = <1>; - #size-cells = <0>; - - i2c-parent = <&{/i2c@7000c400}>; - - pinctrl-names = "ddc", "pta", "idle"; - pinctrl-0 = <&state_i2cmux_ddc>; - pinctrl-1 = <&state_i2cmux_pta>; - pinctrl-2 = <&state_i2cmux_idle>; - - hdmi_ddc: i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - }; - - lvds_ddc: i2c@1 { - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - }; - }; - i2c@7000c500 { status = "okay"; clock-frequency = <400000>; @@ -636,6 +611,31 @@ }; }; + i2cmux { + compatible = "i2c-mux-pinctrl"; + #address-cells = <1>; + #size-cells = <0>; + + i2c-parent = <&{/i2c@7000c400}>; + + pinctrl-names = "ddc", "pta", "idle"; + pinctrl-0 = <&state_i2cmux_ddc>; + pinctrl-1 = <&state_i2cmux_pta>; + pinctrl-2 = <&state_i2cmux_idle>; + + hdmi_ddc: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + lvds_ddc: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; + panel: panel { compatible = "chunghwa,claa101wa01a"; diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi index 62bf0b3064721435f23b2624f716e2320bcd3496..4177d04265d83f26e1e1ed139873dd1175d61fa4 100644 --- a/arch/arm/boot/dts/tegra20.dtsi +++ b/arch/arm/boot/dts/tegra20.dtsi @@ -356,12 +356,6 @@ operating-points-v2 = <&vde_dvfs_opp_table>; }; - apbmisc@70000800 { - compatible = "nvidia,tegra20-apbmisc"; - reg = <0x70000800 0x64>, /* Chip revision */ - <0x70000008 0x04>; /* Strapping options */ - }; - pinmux: pinmux@70000014 { compatible = "nvidia,tegra20-pinmux"; reg = <0x70000014 0x10>, /* Tri-state registers */ @@ -370,6 +364,12 @@ <0x70000868 0xa8>; /* Pad control registers */ }; + apbmisc@70000800 { + compatible = "nvidia,tegra20-apbmisc"; + reg = <0x70000800 0x64>, /* Chip revision */ + <0x70000008 0x04>; /* Strapping options */ + }; + das@70000c00 { compatible = "nvidia,tegra20-das"; reg = <0x70000c00 0x80>; @@ -542,13 +542,6 @@ status = "disabled"; }; - rtc@7000e000 { - compatible = "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA20_CLK_RTC>; - }; - i2c@7000c000 { compatible = "nvidia,tegra20-i2c"; reg = <0x7000c000 0x100>; @@ -683,6 +676,13 @@ status = "disabled"; }; + rtc@7000e000 { + compatible = "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA20_CLK_RTC>; + }; + kbc@7000e200 { compatible = "nvidia,tegra20-kbc"; reg = <0x7000e200 0x100>; @@ -706,6 +706,16 @@ }; powergates { + pd_mpe: mpe { + clocks = <&tegra_car TEGRA20_CLK_MPE>; + resets = <&mc TEGRA20_MC_RESET_MPEA>, + <&mc TEGRA20_MC_RESET_MPEB>, + <&mc TEGRA20_MC_RESET_MPEC>, + <&tegra_car TEGRA20_CLK_MPE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + pd_3d: td { clocks = <&tegra_car TEGRA20_CLK_GR3D>; resets = <&mc TEGRA20_MC_RESET_3D>, @@ -714,6 +724,14 @@ #power-domain-cells = <0>; }; + pd_vde: vdec { + clocks = <&tegra_car TEGRA20_CLK_VDE>; + resets = <&mc TEGRA20_MC_RESET_VDE>, + <&tegra_car TEGRA20_CLK_VDE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + pd_venc: venc { clocks = <&tegra_car TEGRA20_CLK_ISP>, <&tegra_car TEGRA20_CLK_VI>, @@ -726,24 +744,6 @@ power-domains = <&pd_core>; #power-domain-cells = <0>; }; - - pd_vde: vdec { - clocks = <&tegra_car TEGRA20_CLK_VDE>; - resets = <&mc TEGRA20_MC_RESET_VDE>, - <&tegra_car TEGRA20_CLK_VDE>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_mpe: mpe { - clocks = <&tegra_car TEGRA20_CLK_MPE>; - resets = <&mc TEGRA20_MC_RESET_MPEA>, - <&mc TEGRA20_MC_RESET_MPEB>, - <&mc TEGRA20_MC_RESET_MPEC>, - <&tegra_car TEGRA20_CLK_MPE>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; }; }; @@ -1049,13 +1049,13 @@ simple-audio-card,dai-link@0 { reg = <0>; - cpu { - sound-dai = <&tegra_spdif>; - }; - codec { sound-dai = <&tegra_hdmi>; }; + + cpu { + sound-dai = <&tegra_spdif>; + }; }; }; }; diff --git a/arch/arm/boot/dts/tegra30-apalis-eval.dts b/arch/arm/boot/dts/tegra30-apalis-eval.dts index ad968ff968d77cfc66437c60e3a928778ae74974..842b5faba2856466956ce48db180e97943f0525a 100644 --- a/arch/arm/boot/dts/tegra30-apalis-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-eval.dts @@ -47,6 +47,16 @@ }; }; + gpio@6000d000 { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex-perst-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "PEX_PERST_N"; + }; + }; + /* Apalis UART1 */ serial@70006000 { status = "okay"; @@ -236,13 +246,3 @@ vin-supply = <®_5v0>; }; }; - -&gpio { - /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "PEX_PERST_N"; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts index c172fdb5e1aeb24cd1524d62b08c1686d40cc2ad..ca277bf1df7840ba0a280fefe218a0e1469e4a55 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1-eval.dts @@ -48,6 +48,16 @@ }; }; + gpio@6000d000 { + /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ + pex-perst-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "PEX_PERST_N"; + }; + }; + /* Apalis UART1 */ serial@70006000 { status = "okay"; @@ -254,13 +264,3 @@ vin-supply = <&vddio_sdmmc_1v8_reg>; }; }; - -&gpio { - /* Apalis GPIO7 MXM3 pin 15 PLX PEX 8605 PCIe Switch Reset */ - pex-perst-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "PEX_PERST_N"; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi index a1bcd67fa50591d6292165cf4cf3098c20f897f5..a4b7fe5c3d2369dd2403ebfe05eac3093b5ad6cc 100644 --- a/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis-v1.1.dtsi @@ -1007,6 +1007,12 @@ /* ADC converstion time: 80 clocks */ st,sample-time = <4>; + stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; + stmpe_touchscreen { compatible = "st,stmpe-ts"; /* 8 sample average control */ @@ -1023,12 +1029,6 @@ /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; }; - - stmpe_adc { - compatible = "st,stmpe-adc"; - /* forbid to use ADC channels 3-0 (touch) */ - st,norequest-mask = <0x0F>; - }; }; /* @@ -1122,16 +1122,16 @@ mmc-ddr-1_8v; }; - clk32k_in: xtal1 { + clk16m: clock-osc4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32768>; + clock-frequency = <16000000>; }; - clk16m: osc4 { + clk32k_in: clock-xtal1 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <16000000>; + clock-frequency = <32768>; }; reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { diff --git a/arch/arm/boot/dts/tegra30-apalis.dtsi b/arch/arm/boot/dts/tegra30-apalis.dtsi index 99d7dad72d29178a9e11605dfd0294696e30c6ea..d731038840008c87df6f72ac736e49d6ef69e7da 100644 --- a/arch/arm/boot/dts/tegra30-apalis.dtsi +++ b/arch/arm/boot/dts/tegra30-apalis.dtsi @@ -990,6 +990,12 @@ /* ADC converstion time: 80 clocks */ st,sample-time = <4>; + stmpe_adc { + compatible = "st,stmpe-adc"; + /* forbid to use ADC channels 3-0 (touch) */ + st,norequest-mask = <0x0F>; + }; + stmpe_touchscreen { compatible = "st,stmpe-ts"; /* 8 sample average control */ @@ -1006,12 +1012,6 @@ /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; }; - - stmpe_adc { - compatible = "st,stmpe-adc"; - /* forbid to use ADC channels 3-0 (touch) */ - st,norequest-mask = <0x0F>; - }; }; /* @@ -1105,16 +1105,16 @@ mmc-ddr-1_8v; }; - clk32k_in: xtal1 { + clk16m: clock-osc4 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <32768>; + clock-frequency = <16000000>; }; - clk16m: osc4 { + clk32k_in: clock-xtal1 { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <16000000>; + clock-frequency = <32768>; }; reg_1v8_avdd_hdmi_pll: regulator-1v8-avdd-hdmi-pll { diff --git a/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi b/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi index a047abfa6369210583cd7f789cb447a6bd5ffde6..bae09d82594d3d0d5ba084bac02fa26dd068dbb7 100644 --- a/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-lvds-display.dtsi @@ -2,6 +2,8 @@ /* This dtsi file describes parts common for Asus T30 devices with a LVDS panel. */ +#include + / { host1x@50000000 { lcd: dc@54200000 { diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi index ee683c5a9c6242f01b327ffe4039528137ed0467..c0062353c1f192980a27217ab1d3ffa9abf8c5ec 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-common.dtsi @@ -29,6 +29,14 @@ */ chosen {}; + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <0x0>; + tlm,version-minor = <0x0>; + }; + }; + memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -61,6 +69,12 @@ }; gpio@6000d000 { + init-low-power-mode-hog { + gpio-hog; + gpios = ; + input; + }; + init-mode-hog { gpio-hog; gpios = , @@ -68,12 +82,6 @@ ; output-low; }; - - init-low-power-mode-hog { - gpio-hog; - gpios = ; - input; - }; }; pinmux@70000868 { @@ -977,17 +985,6 @@ }; }; - brcm_wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "ext_clock"; - - reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <300>; - power-off-delay-us = <300>; - }; - sdmmc3: mmc@78000400 { status = "okay"; @@ -1113,27 +1110,9 @@ /delete-property/ ddc-i2c-bus; }; - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <0x0>; - tlm,version-minor = <0x0>; - }; - }; - gpio-keys { compatible = "gpio-keys"; - switch-hall-sensor { - label = "Lid"; - gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; - linux,input-type = ; - linux,code = ; - debounce-interval = <500>; - wakeup-event-action = ; - wakeup-source; - }; - key-power { label = "Power"; gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; @@ -1143,6 +1122,15 @@ wakeup-source; }; + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + wakeup-event-action = ; + wakeup-source; + }; + key-volume-up { label = "Volume Up"; gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; @@ -1152,16 +1140,28 @@ wakeup-source; }; - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - wakeup-event-action = ; + switch-hall-sensor { + label = "Lid"; + gpios = <&gpio TEGRA_GPIO(S, 6) GPIO_ACTIVE_LOW>; + linux,input-type = ; + linux,code = ; + debounce-interval = <500>; + wakeup-event-action = ; wakeup-source; }; }; + brcm_wifi_pwrseq: pwrseq-wifi { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 4) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + vdd_5v0_sys: regulator-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi index cd28e8782f7db1e29077f328d80cf15de145e7eb..694c7fe37eb880993ecea09a596773d783173d90 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-maxim-pmic.dtsi @@ -22,13 +22,6 @@ pinctrl-names = "default"; pinctrl-0 = <&max77620_default>; - max77620_default: pinmux { - gpio4 { - pins = "gpio4"; - function = "32k-out1"; - }; - }; - cpu-pwr-req-hog { gpio-hog; gpios = <6 GPIO_ACTIVE_HIGH>; @@ -49,6 +42,13 @@ }; }; + max77620_default: pinmux { + gpio4 { + pins = "gpio4"; + function = "32k-out1"; + }; + }; + regulators { in-sd0-supply = <&vdd_5v0_sys>; in-sd1-supply = <&vdd_5v0_sys>; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi index 6c229e1d67e7187f6ab65925004d69eeaee6f965..8944a4a5a8d7dfcd294972e7230f062866cee52f 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper-memory-timings.dtsi @@ -1562,16 +1562,16 @@ }; }; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-750000000-1300; - /delete-node/ opp-800000000-1300; - /delete-node/ opp-900000000-1350; -}; + opp-table-actmon { + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-750000000; - /delete-node/ opp-800000000; - /delete-node/ opp-900000000; + opp-table-emc { + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi index 564cfcde21a9c8eaf77007114d08b80716c8776c..c19a0419112a59c5fac917e2f90448f418e7eeee 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-grouper.dtsi @@ -6,20 +6,6 @@ / { compatible = "asus,grouper", "nvidia,tegra30"; - display-panel { - panel-timing { - clock-frequency = <68000000>; - hactive = <800>; - vactive = <1280>; - hfront-porch = <24>; - hback-porch = <32>; - hsync-len = <24>; - vsync-len = <1>; - vfront-porch = <5>; - vback-porch = <32>; - }; - }; - pinmux@70000868 { state_default: pinmux { lcd_dc1_pd2 { @@ -145,4 +131,18 @@ firmware-gpios = <&gpio TEGRA_GPIO(R, 3) GPIO_ACTIVE_HIGH>; }; }; + + display-panel { + panel-timing { + clock-frequency = <68000000>; + hactive = <800>; + vactive = <1280>; + hfront-porch = <24>; + hback-porch = <32>; + hsync-len = <24>; + vsync-len = <1>; + vfront-porch = <5>; + vback-porch = <32>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi index 1b241f0542b89f2265809456f0a324ed1667d1bb..94c80134574e95d1220fbb26cdd4f2f3c70e8e2c 100644 --- a/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-nexus7-tilapia.dtsi @@ -6,22 +6,6 @@ / { compatible = "asus,tilapia", "asus,grouper", "nvidia,tegra30"; - display-panel { - enable-gpios = <&gpio TEGRA_GPIO(V, 6) GPIO_ACTIVE_HIGH>; - - panel-timing { - clock-frequency = <81750000>; - hactive = <800>; - vactive = <1280>; - hfront-porch = <64>; - hback-porch = <128>; - hsync-len = <64>; - vsync-len = <1>; - vfront-porch = <5>; - vback-porch = <2>; - }; - }; - gpio@6000d000 { init-mode-3g-hog { gpio-hog; @@ -230,4 +214,20 @@ firmware-gpios = <&gpio TEGRA_GPIO(P, 3) GPIO_ACTIVE_HIGH>; }; }; + + display-panel { + enable-gpios = <&gpio TEGRA_GPIO(V, 6) GPIO_ACTIVE_HIGH>; + + panel-timing { + clock-frequency = <81750000>; + hactive = <800>; + vactive = <1280>; + hfront-porch = <64>; + hback-porch = <128>; + hsync-len = <64>; + vsync-len = <1>; + vfront-porch = <5>; + vback-porch = <2>; + }; + }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-tf201.dts b/arch/arm/boot/dts/tegra30-asus-tf201.dts index 315c6dc068c5f27554874acf13ca387f9e36ef04..3c2b9e93e0283588fc9e009b755a21e893727655 100644 --- a/arch/arm/boot/dts/tegra30-asus-tf201.dts +++ b/arch/arm/boot/dts/tegra30-asus-tf201.dts @@ -605,23 +605,23 @@ enable-gpios = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_HIGH>; vcc-supply = <&vdd_3v3_sys>; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-533000000-1200; - /delete-node/ opp-625000000-1200; - /delete-node/ opp-625000000-1250; - /delete-node/ opp-667000000-1200; - /delete-node/ opp-750000000-1300; - /delete-node/ opp-800000000-1300; - /delete-node/ opp-900000000-1350; -}; + opp-table-actmon { + /delete-node/ opp-533000000; + /delete-node/ opp-625000000; + /delete-node/ opp-667000000; + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-533000000; - /delete-node/ opp-625000000; - /delete-node/ opp-667000000; - /delete-node/ opp-750000000; - /delete-node/ opp-800000000; - /delete-node/ opp-900000000; + opp-table-emc { + /delete-node/ opp-533000000-1200; + /delete-node/ opp-625000000-1200; + /delete-node/ opp-625000000-1250; + /delete-node/ opp-667000000-1200; + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-tf300t.dts b/arch/arm/boot/dts/tegra30-asus-tf300t.dts index f47434871a5c81d1699a2830ce6f6ea5088b237a..506ae3626731b82a13501ce96da7f67c521c3f8b 100644 --- a/arch/arm/boot/dts/tegra30-asus-tf300t.dts +++ b/arch/arm/boot/dts/tegra30-asus-tf300t.dts @@ -999,6 +999,18 @@ compatible = "innolux,g101ice-l01"; }; + opp-table-emc { + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; + + opp-table-actmon { + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; + sound { compatible = "asus,tegra-audio-wm8903-tf300t", "nvidia,tegra-audio-wm8903"; @@ -1020,15 +1032,3 @@ nvidia,headset; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-750000000-1300; - /delete-node/ opp-800000000-1300; - /delete-node/ opp-900000000-1350; -}; - -&emc_bw_dfs_opp_table { - /delete-node/ opp-750000000; - /delete-node/ opp-800000000; - /delete-node/ opp-900000000; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-tf300tg.dts b/arch/arm/boot/dts/tegra30-asus-tf300tg.dts index 96345f821c3d2b90bbd6e8d74d7810eeefea8647..573deeafb7baae452ca62d5fd99c18a13b9937be 100644 --- a/arch/arm/boot/dts/tegra30-asus-tf300tg.dts +++ b/arch/arm/boot/dts/tegra30-asus-tf300tg.dts @@ -1072,16 +1072,16 @@ display-panel { compatible = "innolux,g101ice-l01"; }; -}; -&emc_icc_dvfs_opp_table { - /delete-node/ opp-750000000-1300; - /delete-node/ opp-800000000-1300; - /delete-node/ opp-900000000-1350; -}; + opp-table-emc { + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; -&emc_bw_dfs_opp_table { - /delete-node/ opp-750000000; - /delete-node/ opp-800000000; - /delete-node/ opp-900000000; + opp-table-actmon { + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; }; diff --git a/arch/arm/boot/dts/tegra30-asus-tf700t.dts b/arch/arm/boot/dts/tegra30-asus-tf700t.dts index 1a331dec3cfede702e233d1e410eb9d2cab39815..e7fe8c7a74351ca026f9d2bdd47fdd0952006df6 100644 --- a/arch/arm/boot/dts/tegra30-asus-tf700t.dts +++ b/arch/arm/boot/dts/tegra30-asus-tf700t.dts @@ -758,6 +758,24 @@ vddio-supply = <&vdd_1v8_vio>; vddmipi-supply = <&vdd_1v2_mipi>; + /* + * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1 + * LCD SuperIPS+ Full HD panel. + */ + panel@1 { + compatible = "panasonic,vvx10f004b00"; + reg = <1>; + + power-supply = <&vdd_pnl>; + backlight = <&backlight>; + + port { + panel_input: endpoint { + remote-endpoint = <&bridge_output>; + }; + }; + }; + ports { #address-cells = <1>; #size-cells = <0>; @@ -779,28 +797,18 @@ }; }; }; - - /* - * Panasonic VVX10F004B00 or HYDIS HV101WU1-1E1 - * LCD SuperIPS+ Full HD panel. - */ - panel@1 { - compatible = "panasonic,vvx10f004b00"; - reg = <1>; - - power-supply = <&vdd_pnl>; - backlight = <&backlight>; - - port { - panel_input: endpoint { - remote-endpoint = <&bridge_output>; - }; - }; - }; }; }; }; + opp-table-actmon { + /delete-node/ opp-900000000; + }; + + opp-table-emc { + /delete-node/ opp-900000000-1350; + }; + vdd_1v2_mipi: regulator-mipi { compatible = "regulator-fixed"; regulator-name = "tc358768_1v2_vdd"; @@ -813,11 +821,3 @@ vin-supply = <&vdd_3v3_sys>; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-900000000-1350; -}; - -&emc_bw_dfs_opp_table { - /delete-node/ opp-900000000; -}; diff --git a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi index 08ea9cb32d0ea26065e8fd9b174c3507308d75f3..1861b2de2dc3d43b47d151ad3167a5289467fa5c 100644 --- a/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi +++ b/arch/arm/boot/dts/tegra30-asus-transformer-common.dtsi @@ -33,6 +33,14 @@ */ chosen {}; + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -1187,17 +1195,6 @@ status = "okay"; clock-frequency = <400000>; - nct72: temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vcc-supply = <&vdd_3v3_sys>; - #thermal-sensor-cells = <1>; - }; - /* Texas Instruments TPS659110 PMIC */ pmic: pmic@2d { compatible = "ti,tps65911"; @@ -1323,6 +1320,17 @@ }; }; + nct72: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + vdd_core: core-regulator@60 { compatible = "ti,tps62361"; reg = <0x60>; @@ -1531,14 +1539,6 @@ }; }; - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; - }; - }; - gpio-keys { compatible = "gpio-keys"; @@ -1551,19 +1551,19 @@ wakeup-source; }; - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; - linux,code = ; + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; + linux,code = ; debounce-interval = <10>; wakeup-event-action = ; wakeup-source; }; - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 3) GPIO_ACTIVE_LOW>; - linux,code = ; + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 2) GPIO_ACTIVE_LOW>; + linux,code = ; debounce-interval = <10>; wakeup-event-action = ; wakeup-source; diff --git a/arch/arm/boot/dts/tegra30-beaver.dts b/arch/arm/boot/dts/tegra30-beaver.dts index 5ad62b567d32854e1c1b5e520ea2bc0ea4171aa9..51769d5132aec4f10bba7654b68726303ee7958d 100644 --- a/arch/arm/boot/dts/tegra30-beaver.dts +++ b/arch/arm/boot/dts/tegra30-beaver.dts @@ -1974,6 +1974,28 @@ #clock-cells = <0>; }; + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; + gpio-leds { compatible = "gpio-leds"; @@ -2113,26 +2135,4 @@ assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>, <&tegra_car TEGRA30_CLK_EXTERN1>; }; - - cpus { - cpu0: cpu@0 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@1 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@2 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - - cpu@3 { - cpu-supply = <&vddctrl_reg>; - operating-points-v2 = <&cpu0_opp_table>; - }; - }; }; diff --git a/arch/arm/boot/dts/tegra30-cardhu.dtsi b/arch/arm/boot/dts/tegra30-cardhu.dtsi index 540530c983ff56aea98f36d2d9e0608e59ed6315..37a9c5a0ca30344631d5e39c6dcee82e3d0cd31e 100644 --- a/arch/arm/boot/dts/tegra30-cardhu.dtsi +++ b/arch/arm/boot/dts/tegra30-cardhu.dtsi @@ -468,6 +468,33 @@ }; }; + gpio-keys { + compatible = "gpio-keys"; + + key-power { + label = "Power"; + interrupt-parent = <&pmic>; + interrupts = <2 0>; + linux,code = ; + debounce-interval = <100>; + wakeup-source; + }; + + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + }; + + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; + linux,code = ; + debounce-interval = <10>; + }; + }; + panel: panel { compatible = "chunghwa,claa101wb01"; ddc-i2c-bus = <&panelddc>; @@ -681,31 +708,4 @@ }; }; }; - - gpio-keys { - compatible = "gpio-keys"; - - key-power { - label = "Power"; - interrupt-parent = <&pmic>; - interrupts = <2 0>; - linux,code = ; - debounce-interval = <100>; - wakeup-source; - }; - - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - }; - - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>; - linux,code = ; - debounce-interval = <10>; - }; - }; }; diff --git a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts index 8dbc15f9a9e4f2b741f14e74ecacc709e7c50015..36615c5fda2cb89599ed8b7ac33e526b02b8c600 100644 --- a/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts +++ b/arch/arm/boot/dts/tegra30-colibri-eval-v3.dts @@ -136,7 +136,7 @@ pwms = <&pwm 0 5000000>; /* PWM */ }; - clk16m: osc3 { + clk16m: clock-osc3 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <16000000>; diff --git a/arch/arm/boot/dts/tegra30-colibri.dtsi b/arch/arm/boot/dts/tegra30-colibri.dtsi index 2867a138e011fc3866fda415942ebf23e8cd472b..ed6106f1bea115a38244062f61cf977447c88a76 100644 --- a/arch/arm/boot/dts/tegra30-colibri.dtsi +++ b/arch/arm/boot/dts/tegra30-colibri.dtsi @@ -20,6 +20,15 @@ }; }; + gpio: gpio@6000d000 { + lan-reset-n-hog { + gpio-hog; + gpios = ; + output-high; + line-name = "LAN_RESET#"; + }; + }; + pinmux@70000868 { pinctrl-names = "default"; pinctrl-0 = <&state_default>; @@ -864,6 +873,11 @@ st,sample-time = <4>; /* forbid to use ADC channels 3-0 (touch) */ + stmpe_adc { + compatible = "st,stmpe-adc"; + st,norequest-mask = <0x0F>; + }; + stmpe_touchscreen { compatible = "st,stmpe-ts"; /* 8 sample average control */ @@ -880,11 +894,6 @@ /* 5 ms touch detect interrupt delay */ st,touch-det-delay = <5>; }; - - stmpe_adc { - compatible = "st,stmpe-adc"; - st,norequest-mask = <0x0F>; - }; }; /* @@ -972,7 +981,7 @@ vbus-supply = <®_lan_v_bus>; }; - clk32k_in: xtal1 { + clk32k_in: clock-xtal1 { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <32768>; @@ -1053,12 +1062,3 @@ <&tegra_car TEGRA30_CLK_EXTERN1>; }; }; - -&gpio { - lan-reset-n-hog { - gpio-hog; - gpios = ; - output-high; - line-name = "LAN_RESET#"; - }; -}; diff --git a/arch/arm/boot/dts/tegra30-ouya.dts b/arch/arm/boot/dts/tegra30-ouya.dts index b7acea39b94225702179ee6ff9f5f997084df55f..eef27c82987b336848dc00b064f0c58596546057 100644 --- a/arch/arm/boot/dts/tegra30-ouya.dts +++ b/arch/arm/boot/dts/tegra30-ouya.dts @@ -26,6 +26,14 @@ stdout-path = "serial0:115200n8"; }; + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <0x0>; + tlm,version-minor = <0x0>; + }; + }; + memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -2037,17 +2045,6 @@ status = "okay"; clock-frequency = <400000>; - cpu_temp: nct1008@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - vcc-supply = <&sys_3v3_reg>; - - interrupt-parent = <&gpio>; - interrupts = ; - - #thermal-sensor-cells = <1>; - }; - pmic: pmic@2d { compatible = "ti,tps65911"; reg = <0x2d>; @@ -2161,6 +2158,17 @@ }; }; + cpu_temp: nct1008@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + vcc-supply = <&sys_3v3_reg>; + + interrupt-parent = <&gpio>; + interrupts = ; + + #thermal-sensor-cells = <1>; + }; + vdd_core: tps62361@60 { compatible = "ti,tps62361"; reg = <0x60>; @@ -4485,17 +4493,6 @@ status = "okay"; }; - wifi_pwrseq: wifi_pwrseq { - compatible = "mmc-pwrseq-simple"; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "ext_clock"; - - reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <300>; - power-off-delay-us = <300>; - }; - sdmmc3: mmc@78000400 { status = "okay"; @@ -4608,15 +4605,7 @@ }; }; - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <0x0>; - tlm,version-minor = <0x0>; - }; - }; - - fan: gpio_fan { + fan: fan { compatible = "gpio-fan"; gpios = <&gpio TEGRA_GPIO(J, 2) GPIO_ACTIVE_HIGH>; gpio-fan,speed-map = <0 0 @@ -4624,50 +4613,50 @@ #cooling-cells = <2>; }; - thermal-zones { - cpu_thermal: cpu-thermal { - polling-delay = <5000>; - polling-delay-passive = <5000>; + gpio-keys { + compatible = "gpio-keys"; - thermal-sensors = <&cpu_temp 1>; + key-power { + gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; + debounce-interval = <10>; + linux,code = ; + wakeup-event-action = ; + wakeup-source; + }; + }; - trips { - cpu_alert0: cpu-alert0 { - temperature = <50000>; - hysteresis = <10000>; - type = "active"; - }; - cpu_alert1: cpu-alert1 { - temperature = <70000>; - hysteresis = <5000>; - type = "passive"; - }; - cpu_crit: cpu-crit { - temperature = <90000>; - hysteresis = <2000>; - type = "critical"; - }; - }; + leds { + compatible = "gpio-leds"; - cooling-maps { - map0 { - trip = <&cpu_alert0>; - cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; - }; - map1 { - trip = <&cpu_alert1>; - cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, - <&actmon THERMAL_NO_LIMIT - THERMAL_NO_LIMIT>; - }; - }; + led-power { + label = "power-led"; + gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + retain-state-suspended; }; }; - vdd_12v_in: vdd_12v_in { + opp-table-actmon { + /delete-node/ opp-900000000; + }; + + opp-table-emc { + /delete-node/ opp-900000000-1350; + }; + + wifi_pwrseq: pwrseq-wifi { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + + vdd_12v_in: regulator-vdd-12v-in { compatible = "regulator-fixed"; regulator-name = "vdd_12v_in"; regulator-min-microvolt = <12000000>; @@ -4675,7 +4664,7 @@ regulator-always-on; }; - sdmmc_3v3_reg: sdmmc_3v3_reg { + sdmmc_3v3_reg: regulator-sdmmc-3v3 { compatible = "regulator-fixed"; regulator-name = "sdmmc_3v3"; regulator-min-microvolt = <3300000>; @@ -4686,7 +4675,7 @@ vin-supply = <&sys_3v3_reg>; }; - vdd_fuse_3v3_reg: vdd_fuse_3v3_reg { + vdd_fuse_3v3_reg: regulator-vdd-fuse-3v3 { compatible = "regulator-fixed"; regulator-name = "vdd_fuse_3v3"; regulator-min-microvolt = <3300000>; @@ -4697,7 +4686,7 @@ regulator-always-on; }; - vdd_vid_reg: vdd_vid_reg { + vdd_vid_reg: regulator-vdd-vid { compatible = "regulator-fixed"; regulator-name = "vddio_vid"; regulator-min-microvolt = <5000000>; @@ -4708,7 +4697,7 @@ regulator-boot-on; }; - ddr_reg: ddr_reg { + ddr_reg: regulator-ddr { compatible = "regulator-fixed"; regulator-name = "vdd_ddr"; regulator-min-microvolt = <1500000>; @@ -4720,7 +4709,7 @@ vin-supply = <&vdd_12v_in>; }; - sys_3v3_reg: sys_3v3_reg { + sys_3v3_reg: regulator-sys-3v3 { compatible = "regulator-fixed"; regulator-name = "sys_3v3"; regulator-min-microvolt = <3300000>; @@ -4732,7 +4721,7 @@ vin-supply = <&vdd_12v_in>; }; - vdd_5v0_reg: vdd_5v0_reg { + vdd_5v0_reg: regulator-vdd-5v0 { compatible = "regulator-fixed"; regulator-name = "vdd_5v0"; regulator-min-microvolt = <5000000>; @@ -4744,14 +4733,14 @@ vin-supply = <&vdd_12v_in>; }; - vdd_smsc: vdd_smsc { + vdd_smsc: regulator-vdd-smsc { compatible = "regulator-fixed"; regulator-name = "vdd_smsc"; enable-active-high; gpio = <&gpio TEGRA_GPIO(DD, 5) GPIO_ACTIVE_HIGH>; }; - usb3_vbus_reg: usb3_vbus_reg { + usb3_vbus_reg: regulator-usb3-vbus { compatible = "regulator-fixed"; regulator-name = "usb3_vbus"; regulator-min-microvolt = <5000000>; @@ -4761,36 +4750,46 @@ vin-supply = <&vdd_5v0_reg>; }; - gpio-keys { - compatible = "gpio-keys"; - - key-power { - gpios = <&gpio TEGRA_GPIO(V, 0) GPIO_ACTIVE_LOW>; - debounce-interval = <10>; - linux,code = ; - wakeup-event-action = ; - wakeup-source; - }; - }; + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay = <5000>; + polling-delay-passive = <5000>; + thermal-sensors = <&cpu_temp 1>; - leds { - compatible = "gpio-leds"; + trips { + cpu_alert0: cpu-alert0 { + temperature = <50000>; + hysteresis = <10000>; + type = "active"; + }; + cpu_alert1: cpu-alert1 { + temperature = <70000>; + hysteresis = <5000>; + type = "passive"; + }; + cpu_crit: cpu-crit { + temperature = <90000>; + hysteresis = <2000>; + type = "critical"; + }; + }; - led-power { - label = "power-led"; - gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; - default-state = "on"; - linux,default-trigger = "heartbeat"; - retain-state-suspended; + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + map1 { + trip = <&cpu_alert1>; + cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&actmon THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; + }; }; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-900000000-1350; -}; - -&emc_bw_dfs_opp_table { - /delete-node/ opp-900000000; -}; diff --git a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts index d9408a90653a2af01e22c0472cb7d6f007576cc2..8d10eb8b48b9522aa5bbc51a279442da11a04909 100644 --- a/arch/arm/boot/dts/tegra30-pegatron-chagall.dts +++ b/arch/arm/boot/dts/tegra30-pegatron-chagall.dts @@ -37,6 +37,14 @@ */ chosen {}; + firmware { + trusted-foundations { + compatible = "tlm,trusted-foundations"; + tlm,version-major = <2>; + tlm,version-minor = <8>; + }; + }; + memory@80000000 { reg = <0x80000000 0x40000000>; }; @@ -1190,16 +1198,6 @@ status = "okay"; clock-frequency = <400000>; - light-sensor@44 { - compatible = "isil,isl29023"; - reg = <0x44>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vcc-supply = <&vdd_3v3_sen>; - }; - /* AsahiKASEI AK8975 magnetometer sensor */ magnetometer@c { compatible = "asahi-kasei,ak8975"; @@ -1213,6 +1211,16 @@ "0", "0", "-1"; }; + light-sensor@44 { + compatible = "isil,isl29023"; + reg = <0x44>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_3v3_sen>; + }; + gyroscope@68 { compatible = "invensense,mpu3050"; reg = <0x68>; @@ -1259,17 +1267,6 @@ status = "okay"; clock-frequency = <400000>; - nct72: temperature-sensor@4c { - compatible = "onnn,nct1008"; - reg = <0x4c>; - - interrupt-parent = <&gpio>; - interrupts = ; - - vcc-supply = <&vdd_3v3_sys>; - #thermal-sensor-cells = <1>; - }; - /* Texas Instruments TPS659110 PMIC */ pmic: pmic@2d { compatible = "ti,tps65911"; @@ -1400,6 +1397,17 @@ }; }; + nct72: temperature-sensor@4c { + compatible = "onnn,nct1008"; + reg = <0x4c>; + + interrupt-parent = <&gpio>; + interrupts = ; + + vcc-supply = <&vdd_3v3_sys>; + #thermal-sensor-cells = <1>; + }; + vdd_core: core-regulator@60 { compatible = "ti,tps62361"; reg = <0x60>; @@ -2506,17 +2514,6 @@ vqmmc-supply = <&vddio_usd>; /* ldo3 */ }; - brcm_wifi_pwrseq: wifi-pwrseq { - compatible = "mmc-pwrseq-simple"; - - clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; - clock-names = "ext_clock"; - - reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; - post-power-on-delay-ms = <300>; - power-off-delay-us = <300>; - }; - sdmmc3: mmc@78000400 { status = "okay"; @@ -2674,14 +2671,6 @@ }; }; - firmware { - trusted-foundations { - compatible = "tlm,trusted-foundations"; - tlm,version-major = <2>; - tlm,version-minor = <8>; - }; - }; - gpio-keys { compatible = "gpio-keys"; @@ -2694,19 +2683,19 @@ wakeup-source; }; - key-volume-up { - label = "Volume Up"; - gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; - linux,code = ; + key-volume-down { + label = "Volume Down"; + gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>; + linux,code = ; debounce-interval = <10>; wakeup-event-action = ; wakeup-source; }; - key-volume-down { - label = "Volume Down"; - gpios = <&gpio TEGRA_GPIO(Q, 1) GPIO_ACTIVE_LOW>; - linux,code = ; + key-volume-up { + label = "Volume Up"; + gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; + linux,code = ; debounce-interval = <10>; wakeup-event-action = ; wakeup-source; @@ -2719,6 +2708,34 @@ vcc-supply = <&vdd_3v3_sys>; }; + opp-table-actmon { + /delete-node/ opp-625000000; + /delete-node/ opp-667000000; + /delete-node/ opp-750000000; + /delete-node/ opp-800000000; + /delete-node/ opp-900000000; + }; + + opp-table-emc { + /delete-node/ opp-625000000-1200; + /delete-node/ opp-625000000-1250; + /delete-node/ opp-667000000-1200; + /delete-node/ opp-750000000-1300; + /delete-node/ opp-800000000-1300; + /delete-node/ opp-900000000-1350; + }; + + brcm_wifi_pwrseq: pwrseq-wifi { + compatible = "mmc-pwrseq-simple"; + + clocks = <&tegra_pmc TEGRA_PMC_CLK_BLINK>; + clock-names = "ext_clock"; + + reset-gpios = <&gpio TEGRA_GPIO(D, 3) GPIO_ACTIVE_LOW>; + post-power-on-delay-ms = <300>; + power-off-delay-us = <300>; + }; + sound { compatible = "pegatron,tegra-audio-wm8903-chagall", "nvidia,tegra-audio-wm8903"; @@ -2839,20 +2856,3 @@ }; }; }; - -&emc_icc_dvfs_opp_table { - /delete-node/ opp-625000000-1200; - /delete-node/ opp-625000000-1250; - /delete-node/ opp-667000000-1200; - /delete-node/ opp-750000000-1300; - /delete-node/ opp-800000000-1300; - /delete-node/ opp-900000000-1350; -}; - -&emc_bw_dfs_opp_table { - /delete-node/ opp-625000000; - /delete-node/ opp-667000000; - /delete-node/ opp-750000000; - /delete-node/ opp-800000000; - /delete-node/ opp-900000000; -}; diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi index 9dab8d2c158a7b1fd8313fc9f75c3fb393b4bc0a..b6fcac6016e01d8e5449ff53fff2b9a40e84bdbe 100644 --- a/arch/arm/boot/dts/tegra30.dtsi +++ b/arch/arm/boot/dts/tegra30.dtsi @@ -397,13 +397,6 @@ #clock-cells = <1>; #reset-cells = <1>; - sclk { - compatible = "nvidia,tegra30-sclk"; - clocks = <&tegra_car TEGRA30_CLK_SCLK>; - power-domains = <&pd_core>; - operating-points-v2 = <&sclk_dvfs_opp_table>; - }; - pll-c { compatible = "nvidia,tegra30-pllc"; clocks = <&tegra_car TEGRA30_CLK_PLL_C>; @@ -424,6 +417,13 @@ power-domains = <&pd_core>; operating-points-v2 = <&pll_m_dvfs_opp_table>; }; + + sclk { + compatible = "nvidia,tegra30-sclk"; + clocks = <&tegra_car TEGRA30_CLK_SCLK>; + power-domains = <&pd_core>; + operating-points-v2 = <&sclk_dvfs_opp_table>; + }; }; flow-controller@60007000 { @@ -648,13 +648,6 @@ status = "disabled"; }; - rtc@7000e000 { - compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; - reg = <0x7000e000 0x100>; - interrupts = ; - clocks = <&tegra_car TEGRA30_CLK_RTC>; - }; - i2c@7000c000 { compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; reg = <0x7000c000 0x100>; @@ -831,6 +824,13 @@ status = "disabled"; }; + rtc@7000e000 { + compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; + reg = <0x7000e000 0x100>; + interrupts = ; + clocks = <&tegra_car TEGRA30_CLK_RTC>; + }; + kbc@7000e200 { compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; reg = <0x7000e200 0x100>; @@ -854,6 +854,28 @@ }; powergates { + pd_heg: heg { + clocks = <&tegra_car TEGRA30_CLK_GR2D>, + <&tegra_car TEGRA30_CLK_EPP>, + <&tegra_car TEGRA30_CLK_HOST1X>; + resets = <&mc TEGRA30_MC_RESET_2D>, + <&mc TEGRA30_MC_RESET_EPP>, + <&mc TEGRA30_MC_RESET_HC>, + <&tegra_car TEGRA30_CLK_GR2D>, + <&tegra_car TEGRA30_CLK_EPP>, + <&tegra_car TEGRA30_CLK_HOST1X>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + + pd_mpe: mpe { + clocks = <&tegra_car TEGRA30_CLK_MPE>; + resets = <&mc TEGRA30_MC_RESET_MPE>, + <&tegra_car TEGRA30_CLK_MPE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + pd_3d0: td { clocks = <&tegra_car TEGRA30_CLK_GR3D>; resets = <&mc TEGRA30_MC_RESET_3D>, @@ -870,6 +892,14 @@ #power-domain-cells = <0>; }; + pd_vde: vdec { + clocks = <&tegra_car TEGRA30_CLK_VDE>; + resets = <&mc TEGRA30_MC_RESET_VDE>, + <&tegra_car TEGRA30_CLK_VDE>; + power-domains = <&pd_core>; + #power-domain-cells = <0>; + }; + pd_venc: venc { clocks = <&tegra_car TEGRA30_CLK_ISP>, <&tegra_car TEGRA30_CLK_VI>, @@ -882,36 +912,6 @@ power-domains = <&pd_core>; #power-domain-cells = <0>; }; - - pd_vde: vdec { - clocks = <&tegra_car TEGRA30_CLK_VDE>; - resets = <&mc TEGRA30_MC_RESET_VDE>, - <&tegra_car TEGRA30_CLK_VDE>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_mpe: mpe { - clocks = <&tegra_car TEGRA30_CLK_MPE>; - resets = <&mc TEGRA30_MC_RESET_MPE>, - <&tegra_car TEGRA30_CLK_MPE>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; - - pd_heg: heg { - clocks = <&tegra_car TEGRA30_CLK_GR2D>, - <&tegra_car TEGRA30_CLK_EPP>, - <&tegra_car TEGRA30_CLK_HOST1X>; - resets = <&mc TEGRA30_MC_RESET_2D>, - <&mc TEGRA30_MC_RESET_EPP>, - <&mc TEGRA30_MC_RESET_HC>, - <&tegra_car TEGRA30_CLK_GR2D>, - <&tegra_car TEGRA30_CLK_EPP>, - <&tegra_car TEGRA30_CLK_HOST1X>; - power-domains = <&pd_core>; - #power-domain-cells = <0>; - }; }; }; diff --git a/arch/arm/boot/dts/uniphier-ld4.dtsi b/arch/arm/boot/dts/uniphier-ld4.dtsi index 9dceff12a6338c8b12bd271b208fd9ec71dea90f..df2de7a40211905a7b456dbcbdb423d57744e729 100644 --- a/arch/arm/boot/dts/uniphier-ld4.dtsi +++ b/arch/arm/boot/dts/uniphier-ld4.dtsi @@ -207,33 +207,33 @@ reg = <0x59801000 0x400>; }; - mioctrl@59810000 { + syscon@59810000 { compatible = "socionext,uniphier-ld4-mioctrl", "simple-mfd", "syscon"; reg = <0x59810000 0x800>; - mio_clk: clock { + mio_clk: clock-controller { compatible = "socionext,uniphier-ld4-mio-clock"; #clock-cells = <1>; }; - mio_rst: reset { + mio_rst: reset-controller { compatible = "socionext,uniphier-ld4-mio-reset"; #reset-cells = <1>; }; }; - perictrl@59820000 { + syscon@59820000 { compatible = "socionext,uniphier-ld4-perictrl", "simple-mfd", "syscon"; reg = <0x59820000 0x200>; - peri_clk: clock { + peri_clk: clock-controller { compatible = "socionext,uniphier-ld4-peri-clock"; #clock-cells = <1>; }; - peri_rst: reset { + peri_rst: reset-controller { compatible = "socionext,uniphier-ld4-peri-reset"; #reset-cells = <1>; }; @@ -334,7 +334,7 @@ has-transaction-translator; }; - soc-glue@5f800000 { + syscon@5f800000 { compatible = "socionext,uniphier-ld4-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; @@ -344,9 +344,10 @@ }; }; - soc-glue@5f900000 { + syscon@5f900000 { compatible = "socionext,uniphier-ld4-soc-glue-debug", - "simple-mfd"; + "simple-mfd", "syscon"; + reg = <0x5f900000 0x2000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x5f900000 0x2000>; @@ -393,17 +394,17 @@ #interrupt-cells = <2>; }; - sysctrl@61840000 { + syscon@61840000 { compatible = "socionext,uniphier-ld4-sysctrl", "simple-mfd", "syscon"; reg = <0x61840000 0x10000>; - sys_clk: clock { + sys_clk: clock-controller { compatible = "socionext,uniphier-ld4-clock"; #clock-cells = <1>; }; - sys_rst: reset { + sys_rst: reset-controller { compatible = "socionext,uniphier-ld4-reset"; #reset-cells = <1>; }; diff --git a/arch/arm/boot/dts/uniphier-pro4.dtsi b/arch/arm/boot/dts/uniphier-pro4.dtsi index a309e64c57c86b25d1b60b146d733205efafcc2f..ba55af30e9047e9b3a714af2b0987d2b4c3c20c4 100644 --- a/arch/arm/boot/dts/uniphier-pro4.dtsi +++ b/arch/arm/boot/dts/uniphier-pro4.dtsi @@ -241,33 +241,33 @@ reg = <0x59801000 0x400>; }; - mioctrl@59810000 { + mioctrl: syscon@59810000 { compatible = "socionext,uniphier-pro4-mioctrl", "simple-mfd", "syscon"; reg = <0x59810000 0x800>; - mio_clk: clock { + mio_clk: clock-controller { compatible = "socionext,uniphier-pro4-mio-clock"; #clock-cells = <1>; }; - mio_rst: reset { + mio_rst: reset-controller { compatible = "socionext,uniphier-pro4-mio-reset"; #reset-cells = <1>; }; }; - perictrl@59820000 { + syscon@59820000 { compatible = "socionext,uniphier-pro4-perictrl", "simple-mfd", "syscon"; reg = <0x59820000 0x200>; - peri_clk: clock { + peri_clk: clock-controller { compatible = "socionext,uniphier-pro4-peri-clock"; #clock-cells = <1>; }; - peri_rst: reset { + peri_rst: reset-controller { compatible = "socionext,uniphier-pro4-peri-reset"; #reset-cells = <1>; }; @@ -307,6 +307,7 @@ sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; + socionext,syscon-uhs-mode = <&mioctrl 0>; }; emmc: mmc@5a500000 { @@ -375,7 +376,7 @@ has-transaction-translator; }; - soc_glue: soc-glue@5f800000 { + soc_glue: syscon@5f800000 { compatible = "socionext,uniphier-pro4-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; @@ -384,7 +385,7 @@ compatible = "socionext,uniphier-pro4-pinctrl"; }; - usb-controller { + usb-hub { compatible = "socionext,uniphier-pro4-usb2-phy"; #address-cells = <1>; #size-cells = <0>; @@ -412,15 +413,16 @@ }; }; - sg_clk: clock { + sg_clk: clock-controller { compatible = "socionext,uniphier-pro4-sg-clock"; #clock-cells = <1>; }; }; - soc-glue@5f900000 { + syscon@5f900000 { compatible = "socionext,uniphier-pro4-soc-glue-debug", - "simple-mfd"; + "simple-mfd", "syscon"; + reg = <0x5f900000 0x2000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x5f900000 0x2000>; @@ -480,17 +482,17 @@ interrupt-controller; }; - sysctrl@61840000 { + syscon@61840000 { compatible = "socionext,uniphier-pro4-sysctrl", "simple-mfd", "syscon"; reg = <0x61840000 0x10000>; - sys_clk: clock { + sys_clk: clock-controller { compatible = "socionext,uniphier-pro4-clock"; #clock-cells = <1>; }; - sys_rst: reset { + sys_rst: reset-controller { compatible = "socionext,uniphier-pro4-reset"; #reset-cells = <1>; }; @@ -535,6 +537,7 @@ sata-controller@65700000 { compatible = "socionext,uniphier-pxs2-ahci-glue", "simple-mfd"; + reg = <0x65700000 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x65700000 0x100>; @@ -549,7 +552,7 @@ #reset-cells = <1>; }; - ahci0_phy: sata-phy@10 { + ahci0_phy: phy@10 { compatible = "socionext,uniphier-pro4-ahci-phy"; reg = <0x10 0x40>; clock-names = "link", "gio"; @@ -581,6 +584,7 @@ sata-controller@65900000 { compatible = "socionext,uniphier-pro4-ahci-glue", "simple-mfd"; + reg = <0x65900000 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x65900000 0x100>; @@ -595,7 +599,7 @@ #reset-cells = <1>; }; - ahci1_phy: sata-phy@10 { + ahci1_phy: phy@10 { compatible = "socionext,uniphier-pro4-ahci-phy"; reg = <0x10 0x40>; clock-names = "link", "gio"; @@ -629,6 +633,7 @@ usb-controller@65b00000 { compatible = "socionext,uniphier-pro4-dwc3-glue", "simple-mfd"; + reg = <0x65b00000 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x65b00000 0x100>; @@ -642,7 +647,7 @@ resets = <&sys_rst 12>, <&sys_rst 14>; }; - usb0_ssphy: ss-phy@10 { + usb0_ssphy: phy@10 { compatible = "socionext,uniphier-pro4-usb3-ssphy"; reg = <0x10 0x10>; #phy-cells = <0>; @@ -653,7 +658,7 @@ vbus-supply = <&usb0_vbus>; }; - usb0_rst: reset@40 { + usb0_rst: reset-controller@40 { compatible = "socionext,uniphier-pro4-usb3-reset"; reg = <0x40 0x4>; #reset-cells = <1>; @@ -683,6 +688,7 @@ usb-controller@65d00000 { compatible = "socionext,uniphier-pro4-dwc3-glue", "simple-mfd"; + reg = <0x65d00000 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x65d00000 0x100>; @@ -696,7 +702,7 @@ resets = <&sys_rst 12>, <&sys_rst 15>; }; - usb1_rst: reset@40 { + usb1_rst: reset-controller@40 { compatible = "socionext,uniphier-pro4-usb3-reset"; reg = <0x40 0x4>; #reset-cells = <1>; diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi index 100edd7438d8b7bb609990470f1675b49e8daedd..2d8591cdddb80c7911e551d781354d7c575161c0 100644 --- a/arch/arm/boot/dts/uniphier-pro5.dtsi +++ b/arch/arm/boot/dts/uniphier-pro5.dtsi @@ -341,39 +341,39 @@ reg = <0x59801000 0x400>; }; - sdctrl@59810000 { + sdctrl: syscon@59810000 { compatible = "socionext,uniphier-pro5-sdctrl", "simple-mfd", "syscon"; reg = <0x59810000 0x400>; - sd_clk: clock { + sd_clk: clock-controller { compatible = "socionext,uniphier-pro5-sd-clock"; #clock-cells = <1>; }; - sd_rst: reset { + sd_rst: reset-controller { compatible = "socionext,uniphier-pro5-sd-reset"; #reset-cells = <1>; }; }; - perictrl@59820000 { + syscon@59820000 { compatible = "socionext,uniphier-pro5-perictrl", "simple-mfd", "syscon"; reg = <0x59820000 0x200>; - peri_clk: clock { + peri_clk: clock-controller { compatible = "socionext,uniphier-pro5-peri-clock"; #clock-cells = <1>; }; - peri_rst: reset { + peri_rst: reset-controller { compatible = "socionext,uniphier-pro5-peri-reset"; #reset-cells = <1>; }; }; - soc-glue@5f800000 { + syscon@5f800000 { compatible = "socionext,uniphier-pro5-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; @@ -383,9 +383,10 @@ }; }; - soc-glue@5f900000 { + syscon@5f900000 { compatible = "socionext,uniphier-pro5-soc-glue-debug", - "simple-mfd"; + "simple-mfd", "syscon"; + reg = <0x5f900000 0x2000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x5f900000 0x2000>; @@ -455,17 +456,17 @@ interrupt-controller; }; - sysctrl@61840000 { + syscon@61840000 { compatible = "socionext,uniphier-pro5-sysctrl", "simple-mfd", "syscon"; reg = <0x61840000 0x10000>; - sys_clk: clock { + sys_clk: clock-controller { compatible = "socionext,uniphier-pro5-clock"; #clock-cells = <1>; }; - sys_rst: reset { + sys_rst: reset-controller { compatible = "socionext,uniphier-pro5-reset"; #reset-cells = <1>; }; @@ -489,11 +490,12 @@ usb-controller@65b00000 { compatible = "socionext,uniphier-pro5-dwc3-glue", "simple-mfd"; + reg = <0x65b00000 0x400>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x65b00000 0x400>; - usb0_rst: reset@0 { + usb0_rst: reset-controller@0 { compatible = "socionext,uniphier-pro5-usb3-reset"; reg = <0x0 0x4>; #reset-cells = <1>; @@ -512,7 +514,7 @@ resets = <&sys_rst 12>, <&sys_rst 14>; }; - usb0_hsphy0: hs-phy@280 { + usb0_hsphy0: phy@280 { compatible = "socionext,uniphier-pro5-usb3-hsphy"; reg = <0x280 0x10>; #phy-cells = <0>; @@ -523,7 +525,7 @@ vbus-supply = <&usb0_vbus0>; }; - usb0_ssphy0: ss-phy@380 { + usb0_ssphy0: phy@380 { compatible = "socionext,uniphier-pro5-usb3-ssphy"; reg = <0x380 0x10>; #phy-cells = <0>; @@ -553,11 +555,12 @@ usb-controller@65d00000 { compatible = "socionext,uniphier-pro5-dwc3-glue", "simple-mfd"; + reg = <0x65d00000 0x400>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x65d00000 0x400>; - usb1_rst: reset@0 { + usb1_rst: reset-controller@0 { compatible = "socionext,uniphier-pro5-usb3-reset"; reg = <0x0 0x4>; #reset-cells = <1>; @@ -585,7 +588,7 @@ resets = <&sys_rst 12>, <&sys_rst 15>; }; - usb1_hsphy0: hs-phy@280 { + usb1_hsphy0: phy@280 { compatible = "socionext,uniphier-pro5-usb3-hsphy"; reg = <0x280 0x10>; #phy-cells = <0>; @@ -596,7 +599,7 @@ vbus-supply = <&usb1_vbus0>; }; - usb1_hsphy1: hs-phy@290 { + usb1_hsphy1: phy@290 { compatible = "socionext,uniphier-pro5-usb3-hsphy"; reg = <0x290 0x10>; #phy-cells = <0>; @@ -607,7 +610,7 @@ vbus-supply = <&usb1_vbus1>; }; - usb1_ssphy0: ss-phy@380 { + usb1_ssphy0: phy@380 { compatible = "socionext,uniphier-pro5-usb3-ssphy"; reg = <0x380 0x10>; #phy-cells = <0>; @@ -696,6 +699,7 @@ sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; + socionext,syscon-uhs-mode = <&sdctrl 0>; }; }; }; diff --git a/arch/arm/boot/dts/uniphier-pxs2.dtsi b/arch/arm/boot/dts/uniphier-pxs2.dtsi index ca4dccf56a67632ba45444c24a144f3cbe5cf575..f97a57222101f289e7388339366c7c7ffdf5328b 100644 --- a/arch/arm/boot/dts/uniphier-pxs2.dtsi +++ b/arch/arm/boot/dts/uniphier-pxs2.dtsi @@ -422,33 +422,33 @@ reg = <0x59801000 0x400>; }; - sdctrl@59810000 { + sdctrl: syscon@59810000 { compatible = "socionext,uniphier-pxs2-sdctrl", "simple-mfd", "syscon"; reg = <0x59810000 0x400>; - sd_clk: clock { + sd_clk: clock-controller { compatible = "socionext,uniphier-pxs2-sd-clock"; #clock-cells = <1>; }; - sd_rst: reset { + sd_rst: reset-controller { compatible = "socionext,uniphier-pxs2-sd-reset"; #reset-cells = <1>; }; }; - perictrl@59820000 { + syscon@59820000 { compatible = "socionext,uniphier-pxs2-perictrl", "simple-mfd", "syscon"; reg = <0x59820000 0x200>; - peri_clk: clock { + peri_clk: clock-controller { compatible = "socionext,uniphier-pxs2-peri-clock"; #clock-cells = <1>; }; - peri_rst: reset { + peri_rst: reset-controller { compatible = "socionext,uniphier-pxs2-peri-reset"; #reset-cells = <1>; }; @@ -486,9 +486,10 @@ sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; + socionext,syscon-uhs-mode = <&sdctrl 0>; }; - soc_glue: soc-glue@5f800000 { + soc_glue: syscon@5f800000 { compatible = "socionext,uniphier-pxs2-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; @@ -498,9 +499,10 @@ }; }; - soc-glue@5f900000 { + syscon@5f900000 { compatible = "socionext,uniphier-pxs2-soc-glue-debug", - "simple-mfd"; + "simple-mfd", "syscon"; + reg = <0x5f900000 0x2000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x5f900000 0x2000>; @@ -555,17 +557,17 @@ interrupt-controller; }; - sysctrl@61840000 { + syscon@61840000 { compatible = "socionext,uniphier-pxs2-sysctrl", "simple-mfd", "syscon"; reg = <0x61840000 0x10000>; - sys_clk: clock { + sys_clk: clock-controller { compatible = "socionext,uniphier-pxs2-clock"; #clock-cells = <1>; }; - sys_rst: reset { + sys_rst: reset-controller { compatible = "socionext,uniphier-pxs2-reset"; #reset-cells = <1>; }; @@ -614,6 +616,7 @@ sata-controller@65700000 { compatible = "socionext,uniphier-pxs2-ahci-glue", "simple-mfd"; + reg = <0x65700000 0x100>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x65700000 0x100>; @@ -628,7 +631,7 @@ #reset-cells = <1>; }; - ahci_phy: sata-phy@10 { + ahci_phy: phy@10 { compatible = "socionext,uniphier-pxs2-ahci-phy"; reg = <0x10 0x10>; clock-names = "link"; @@ -658,11 +661,12 @@ usb-controller@65b00000 { compatible = "socionext,uniphier-pxs2-dwc3-glue", "simple-mfd"; + reg = <0x65b00000 0x400>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x65b00000 0x400>; - usb0_rst: reset@0 { + usb0_rst: reset-controller@0 { compatible = "socionext,uniphier-pxs2-usb3-reset"; reg = <0x0 0x4>; #reset-cells = <1>; @@ -690,7 +694,7 @@ resets = <&sys_rst 14>; }; - usb0_hsphy0: hs-phy@200 { + usb0_hsphy0: phy@200 { compatible = "socionext,uniphier-pxs2-usb3-hsphy"; reg = <0x200 0x10>; #phy-cells = <0>; @@ -701,7 +705,7 @@ vbus-supply = <&usb0_vbus0>; }; - usb0_hsphy1: hs-phy@210 { + usb0_hsphy1: phy@210 { compatible = "socionext,uniphier-pxs2-usb3-hsphy"; reg = <0x210 0x10>; #phy-cells = <0>; @@ -712,7 +716,7 @@ vbus-supply = <&usb0_vbus1>; }; - usb0_ssphy0: ss-phy@300 { + usb0_ssphy0: phy@300 { compatible = "socionext,uniphier-pxs2-usb3-ssphy"; reg = <0x300 0x10>; #phy-cells = <0>; @@ -723,7 +727,7 @@ vbus-supply = <&usb0_vbus0>; }; - usb0_ssphy1: ss-phy@310 { + usb0_ssphy1: phy@310 { compatible = "socionext,uniphier-pxs2-usb3-ssphy"; reg = <0x310 0x10>; #phy-cells = <0>; @@ -753,11 +757,12 @@ usb-controller@65d00000 { compatible = "socionext,uniphier-pxs2-dwc3-glue", "simple-mfd"; + reg = <0x65d00000 0x400>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x65d00000 0x400>; - usb1_rst: reset@0 { + usb1_rst: reset-controller@0 { compatible = "socionext,uniphier-pxs2-usb3-reset"; reg = <0x0 0x4>; #reset-cells = <1>; @@ -785,7 +790,7 @@ resets = <&sys_rst 15>; }; - usb1_hsphy0: hs-phy@200 { + usb1_hsphy0: phy@200 { compatible = "socionext,uniphier-pxs2-usb3-hsphy"; reg = <0x200 0x10>; #phy-cells = <0>; @@ -796,7 +801,7 @@ vbus-supply = <&usb1_vbus0>; }; - usb1_hsphy1: hs-phy@210 { + usb1_hsphy1: phy@210 { compatible = "socionext,uniphier-pxs2-usb3-hsphy"; reg = <0x210 0x10>; #phy-cells = <0>; @@ -807,7 +812,7 @@ vbus-supply = <&usb1_vbus1>; }; - usb1_ssphy0: ss-phy@300 { + usb1_ssphy0: phy@300 { compatible = "socionext,uniphier-pxs2-usb3-ssphy"; reg = <0x300 0x10>; #phy-cells = <0>; diff --git a/arch/arm/boot/dts/uniphier-sld8.dtsi b/arch/arm/boot/dts/uniphier-sld8.dtsi index 67b12dfe513be943d359fc041b16b622fb75e301..f876282760e9df155de1ebcc1acca1fc120293e0 100644 --- a/arch/arm/boot/dts/uniphier-sld8.dtsi +++ b/arch/arm/boot/dts/uniphier-sld8.dtsi @@ -211,33 +211,33 @@ reg = <0x59801000 0x400>; }; - mioctrl@59810000 { + mioctrl: syscon@59810000 { compatible = "socionext,uniphier-sld8-mioctrl", "simple-mfd", "syscon"; reg = <0x59810000 0x800>; - mio_clk: clock { + mio_clk: clock-controller { compatible = "socionext,uniphier-sld8-mio-clock"; #clock-cells = <1>; }; - mio_rst: reset { + mio_rst: reset-controller { compatible = "socionext,uniphier-sld8-mio-reset"; #reset-cells = <1>; }; }; - perictrl@59820000 { + syscon@59820000 { compatible = "socionext,uniphier-sld8-perictrl", "simple-mfd", "syscon"; reg = <0x59820000 0x200>; - peri_clk: clock { + peri_clk: clock-controller { compatible = "socionext,uniphier-sld8-peri-clock"; #clock-cells = <1>; }; - peri_rst: reset { + peri_rst: reset-controller { compatible = "socionext,uniphier-sld8-peri-reset"; #reset-cells = <1>; }; @@ -276,6 +276,7 @@ sd-uhs-sdr12; sd-uhs-sdr25; sd-uhs-sdr50; + socionext,syscon-uhs-mode = <&mioctrl 0>; }; emmc: mmc@5a500000 { @@ -338,7 +339,7 @@ has-transaction-translator; }; - soc-glue@5f800000 { + syscon@5f800000 { compatible = "socionext,uniphier-sld8-soc-glue", "simple-mfd", "syscon"; reg = <0x5f800000 0x2000>; @@ -348,9 +349,10 @@ }; }; - soc-glue@5f900000 { + syscon@5f900000 { compatible = "socionext,uniphier-sld8-soc-glue-debug", - "simple-mfd"; + "simple-mfd", "syscon"; + reg = <0x5f900000 0x2000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x5f900000 0x2000>; @@ -397,17 +399,17 @@ #interrupt-cells = <2>; }; - sysctrl@61840000 { + syscon@61840000 { compatible = "socionext,uniphier-sld8-sysctrl", "simple-mfd", "syscon"; reg = <0x61840000 0x10000>; - sys_clk: clock { + sys_clk: clock-controller { compatible = "socionext,uniphier-sld8-clock"; #clock-cells = <1>; }; - sys_rst: reset { + sys_rst: reset-controller { compatible = "socionext,uniphier-sld8-reset"; #reset-cells = <1>; }; diff --git a/arch/arm/boot/dts/versatile-ab.dts b/arch/arm/boot/dts/versatile-ab.dts index a520615f4d8dbc64bee0589b4d026cc164a1d588..f31dcf7e5862e9229716dbbcfe427b38a578a7e2 100644 --- a/arch/arm/boot/dts/versatile-ab.dts +++ b/arch/arm/boot/dts/versatile-ab.dts @@ -237,7 +237,7 @@ clock-names = "apb_pclk"; }; - uart0: uart@101f1000 { + uart0: serial@101f1000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x101f1000 0x1000>; interrupts = <12>; @@ -245,7 +245,7 @@ clock-names = "uartclk", "apb_pclk"; }; - uart1: uart@101f2000 { + uart1: serial@101f2000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x101f2000 0x1000>; interrupts = <13>; @@ -253,7 +253,7 @@ clock-names = "uartclk", "apb_pclk"; }; - uart2: uart@101f3000 { + uart2: serial@101f3000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x101f3000 0x1000>; interrupts = <14>; diff --git a/arch/arm/boot/dts/versatile-pb.dts b/arch/arm/boot/dts/versatile-pb.dts index e7e751a858d811ac4fa4e6c82d1707c560087f44..fc21ce54b33a57f4a53f92bf84dec76651755794 100644 --- a/arch/arm/boot/dts/versatile-pb.dts +++ b/arch/arm/boot/dts/versatile-pb.dts @@ -85,7 +85,7 @@ */ interrupts-extended = <&sic 22 &sic 23>; }; - uart@9000 { + serial@9000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x9000 0x1000>; interrupt-parent = <&sic>; diff --git a/arch/arm/boot/dts/vexpress-v2m.dtsi b/arch/arm/boot/dts/vexpress-v2m.dtsi index def538ce8769d9d593d9e21ab7087c2122deb756..c5e92f6d2fcd8a6ff0d05dcfd5f7b4ff2b140ec7 100644 --- a/arch/arm/boot/dts/vexpress-v2m.dtsi +++ b/arch/arm/boot/dts/vexpress-v2m.dtsi @@ -216,7 +216,7 @@ clock-names = "KMIREFCLK", "apb_pclk"; }; - v2m_serial0: uart@9000 { + v2m_serial0: serial@9000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x09000 0x1000>; interrupts = <5>; @@ -224,7 +224,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial1: uart@a000 { + v2m_serial1: serial@a000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0a000 0x1000>; interrupts = <6>; @@ -232,7 +232,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial2: uart@b000 { + v2m_serial2: serial@b000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0b000 0x1000>; interrupts = <7>; @@ -240,7 +240,7 @@ clock-names = "uartclk", "apb_pclk"; }; - v2m_serial3: uart@c000 { + v2m_serial3: serial@c000 { compatible = "arm,pl011", "arm,primecell"; reg = <0x0c000 0x1000>; interrupts = <8>; diff --git a/arch/arm/boot/dts/vf610-bk4.dts b/arch/arm/boot/dts/vf610-bk4.dts index 551a4c3ff4fa704cd3b263adfc546d02b1cefe2d..e4f691d601cc2e51c63d5d4f2daf909dbeceb232 100644 --- a/arch/arm/boot/dts/vf610-bk4.dts +++ b/arch/arm/boot/dts/vf610-bk4.dts @@ -38,7 +38,7 @@ pinctrl-0 = <&pinctrl_gpio_leds>; /* LED D5 */ - led0: heartbeat { + led0: led-heartbeat { label = "heartbeat"; gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; default-state = "on"; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts index 42ed4a04a12e250b3e4d3421d221658397560ead..6280c5e86a124e2f1547a2a7b74f7f4628db878d 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-b.dts @@ -345,7 +345,7 @@ }; &i2c2 { - tca9548@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; pinctrl-0 = <&pinctrl_i2c_mux_reset>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts index f892977da9e4e0311fd1e3dda5308a8b2811a2f6..c00d39562a10bb9487785b8f77f5fb181fc0cb90 100644 --- a/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts +++ b/arch/arm/boot/dts/vf610-zii-dev-rev-c.dts @@ -340,7 +340,7 @@ }; &i2c2 { - tca9548@70 { + i2c-mux@70 { compatible = "nxp,pca9548"; pinctrl-0 = <&pinctrl_i2c_mux_reset>; pinctrl-names = "default"; diff --git a/arch/arm/boot/dts/vf610-zii-dev.dtsi b/arch/arm/boot/dts/vf610-zii-dev.dtsi index f8299f33a6928a0f556845283ffce614976bf923..ce5e52896b19d1ce80c2f34bef160ab57f12885b 100644 --- a/arch/arm/boot/dts/vf610-zii-dev.dtsi +++ b/arch/arm/boot/dts/vf610-zii-dev.dtsi @@ -59,7 +59,7 @@ pinctrl-0 = <&pinctrl_leds_debug>; pinctrl-names = "default"; - debug { + led-debug { label = "zii:green:debug1"; gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts index 040a1f8b6130724dc953ba4317065f7cea2c678b..7b3276cd470fbd54f57610041b64979bb6379e65 100644 --- a/arch/arm/boot/dts/vf610-zii-scu4-aib.dts +++ b/arch/arm/boot/dts/vf610-zii-scu4-aib.dts @@ -23,7 +23,7 @@ pinctrl-0 = <&pinctrl_leds_debug>; pinctrl-names = "default"; - debug { + led-debug { label = "zii:green:debug1"; gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; linux,default-trigger = "heartbeat"; diff --git a/arch/arm/boot/dts/vf610-zii-spb4.dts b/arch/arm/boot/dts/vf610-zii-spb4.dts index 6c6ec46fd0154c492ffcbb566292017c9c3b617d..180acb0795b9e6fea995053c76c67805ecbff8ef 100644 --- a/arch/arm/boot/dts/vf610-zii-spb4.dts +++ b/arch/arm/boot/dts/vf610-zii-spb4.dts @@ -241,7 +241,7 @@ pinctrl-0 = <&pinctrl_uart2>; status = "okay"; - rave-sp { + mcu { compatible = "zii,rave-sp-rdu2"; current-speed = <1000000>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts index fe600ab2e4bd0a2d81053a66e012ac952beed942..20beaa8433b6cee26fa7c44c804579a927f29a44 100644 --- a/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts +++ b/arch/arm/boot/dts/vf610-zii-ssmb-spu3.dts @@ -254,7 +254,7 @@ pinctrl-0 = <&pinctrl_uart1>; status = "okay"; - rave-sp { + mcu { compatible = "zii,rave-sp-rdu2"; current-speed = <1000000>; #address-cells = <1>; diff --git a/arch/arm/boot/dts/vfxxx.dtsi b/arch/arm/boot/dts/vfxxx.dtsi index d53f9c9db8bfdacbe80cdb461b50d18ab72ab757..ff4479994b600c6eb8b23c885bb2575c628c77c3 100644 --- a/arch/arm/boot/dts/vfxxx.dtsi +++ b/arch/arm/boot/dts/vfxxx.dtsi @@ -191,9 +191,8 @@ <&clks VF610_CLK_SAI0_DIV>, <&clks 0>, <&clks 0>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 0 17>, - <&edma0 0 16>; + dma-names = "rx", "tx"; + dmas = <&edma0 0 16>, <&edma0 0 17>; status = "disabled"; }; @@ -205,9 +204,8 @@ <&clks VF610_CLK_SAI1_DIV>, <&clks 0>, <&clks 0>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 0 19>, - <&edma0 0 18>; + dma-names = "rx", "tx"; + dmas = <&edma0 0 18>, <&edma0 0 19>; status = "disabled"; }; @@ -219,9 +217,8 @@ <&clks VF610_CLK_SAI2_DIV>, <&clks 0>, <&clks 0>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 0 21>, - <&edma0 0 20>; + dma-names = "rx", "tx"; + dmas = <&edma0 0 20>, <&edma0 0 21>; status = "disabled"; }; @@ -233,9 +230,8 @@ <&clks VF610_CLK_SAI3_DIV>, <&clks 0>, <&clks 0>; clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 9>, - <&edma0 1 8>; + dma-names = "rx", "tx"; + dmas = <&edma0 1 8>, <&edma0 1 9>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi index c193264a86ffb8311ee0483391a61b0ad1e155fd..cd9931f6bcbdc4b71327a435970533fc752095c9 100644 --- a/arch/arm/boot/dts/zynq-7000.dtsi +++ b/arch/arm/boot/dts/zynq-7000.dtsi @@ -230,8 +230,20 @@ #size-cells = <0>; }; + qspi: spi@e000d000 { + compatible = "xlnx,zynq-qspi-1.0"; + reg = <0xe000d000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <0 19 4>; + clocks = <&clkc 10>, <&clkc 43>; + clock-names = "ref_clk", "pclk"; + status = "disabled"; + #address-cells = <1>; + #size-cells = <0>; + }; + gem0: ethernet@e000b000 { - compatible = "cdns,zynq-gem", "cdns,gem"; + compatible = "xlnx,zynq-gem", "cdns,gem"; reg = <0xe000b000 0x1000>; status = "disabled"; interrupts = <0 22 4>; @@ -242,7 +254,7 @@ }; gem1: ethernet@e000c000 { - compatible = "cdns,zynq-gem", "cdns,gem"; + compatible = "xlnx,zynq-gem", "cdns,gem"; reg = <0xe000c000 0x1000>; status = "disabled"; interrupts = <0 45 4>; @@ -331,12 +343,14 @@ }; }; - dmac_s: dmac@f8003000 { + dmac_s: dma-controller@f8003000 { compatible = "arm,pl330", "arm,primecell"; reg = <0xf8003000 0x1000>; interrupt-parent = <&intc>; - interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", - "dma4", "dma5", "dma6", "dma7"; + /* + * interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3", + * "dma4", "dma5", "dma6", "dma7"; + */ interrupts = <0 13 4>, <0 14 4>, <0 15 4>, <0 16 4>, <0 17 4>, diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 9ea08337b174cd2443525798fb3bff11d197ebd6..82bcf4dc7f5431da594e4daf755885aa293ae351 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -217,6 +217,7 @@ CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=y +CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_CFB=y CONFIG_CRYPTO_OFB=y @@ -224,7 +225,6 @@ CONFIG_CRYPTO_XTS=y CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_SKCIPHER=m CONFIG_CRYPTO_DEV_ATMEL_AES=y diff --git a/arch/arm/configs/badge4_defconfig b/arch/arm/configs/badge4_defconfig deleted file mode 100644 index 337e5c9718ae03162773ad899a65b5a96869dd69..0000000000000000000000000000000000000000 --- a/arch/arm/configs/badge4_defconfig +++ /dev/null @@ -1,105 +0,0 @@ -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EXPERT=y -CONFIG_ARCH_MULTI_V4=y -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_SA1100=y -CONFIG_SA1100_BADGE4=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="init=/linuxrc root=/dev/mtdblock3" -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_FPE_NWFPE=y -CONFIG_MODULES=y -CONFIG_MODVERSIONS=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_BINFMT_MISC=m -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_IPV6 is not set -CONFIG_BT=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIVHCI=m -# CONFIG_FW_LOADER is not set -CONFIG_MTD=y -CONFIG_MTD_DEBUG=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -# CONFIG_MTD_CFI_I2 is not set -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_RAM=y -CONFIG_MTD_SA1100=y -CONFIG_PARPORT=m -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=m -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=m -CONFIG_BLK_DEV_SR=m -CONFIG_CHR_DEV_SG=y -CONFIG_NETDEVICES=y -CONFIG_USB_CATC=m -CONFIG_USB_KAWETH=m -CONFIG_USB_PEGASUS=m -CONFIG_USB_USBNET=m -CONFIG_USB_ALI_M5632=y -CONFIG_USB_AN2720=y -CONFIG_USB_EPSON2888=y -CONFIG_USB_KC2190=y -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -CONFIG_SERIAL_SA1100=y -CONFIG_SERIAL_SA1100_CONSOLE=y -CONFIG_I2C=m -CONFIG_I2C_CHARDEV=m -CONFIG_I2C_ELEKTOR=m -CONFIG_WATCHDOG=y -CONFIG_SOFT_WATCHDOG=m -CONFIG_SA1100_WATCHDOG=m -CONFIG_SOUND=y -CONFIG_SOUND_PRIME=y -CONFIG_USB=y -CONFIG_USB_MON=y -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m -CONFIG_USB_STORAGE=y -CONFIG_USB_STORAGE_DEBUG=y -CONFIG_USB_MDC800=m -CONFIG_USB_MICROTEK=m -CONFIG_USB_USS720=m -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_BELKIN=m -CONFIG_USB_SERIAL_WHITEHEAT=m -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -CONFIG_USB_SERIAL_EMPEG=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_VISOR=m -CONFIG_USB_SERIAL_IR=m -CONFIG_USB_SERIAL_EDGEPORT=m -CONFIG_USB_SERIAL_KEYSPAN_PDA=m -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_OMNINET=m -CONFIG_EXT2_FS=m -CONFIG_EXT3_FS=m -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=m -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_CRAMFS=m -CONFIG_MINIX_FS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_SMB_FS=m -CONFIG_DEBUG_KERNEL=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/bcm2835_defconfig b/arch/arm/configs/bcm2835_defconfig index a51babd178c2609f27770858cd5191c23cd8cc63..ce092abcd3232b92a895d4ee39af64df5a1f3e79 100644 --- a/arch/arm/configs/bcm2835_defconfig +++ b/arch/arm/configs/bcm2835_defconfig @@ -107,7 +107,8 @@ CONFIG_MEDIA_CAMERA_SUPPORT=y CONFIG_DRM=y CONFIG_DRM_V3D=y CONFIG_DRM_VC4=y -CONFIG_FB_SIMPLE=y +CONFIG_DRM_SIMPLEDRM=y +CONFIG_FB=y CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_SOUND=y CONFIG_SND=y diff --git a/arch/arm/configs/cerfcube_defconfig b/arch/arm/configs/cerfcube_defconfig deleted file mode 100644 index 9ada868e2648b86de20e1893fd1dd83d76ef8255..0000000000000000000000000000000000000000 --- a/arch/arm/configs/cerfcube_defconfig +++ /dev/null @@ -1,73 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_ARCH_MULTI_V4=y -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_SA1100=y -CONFIG_SA1100_CERF=y -CONFIG_SA1100_CERF_FLASH_16MB=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="console=ttySA0,38400 root=/dev/mtdblock3 rootfstype=jffs2 rw mem=32M init=/linuxrc" -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=m -CONFIG_FPE_FASTFPE=y -CONFIG_PM=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_IPV6 is not set -CONFIG_PCCARD=m -CONFIG_PCMCIA_SA1100=m -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_SA1100=y -CONFIG_BLK_DEV_LOOP=m -CONFIG_BLK_DEV_RAM=m -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_NET_PCI=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_SA1100=y -CONFIG_SERIAL_SA1100_CONSOLE=y -CONFIG_WATCHDOG=y -CONFIG_SA1100_WATCHDOG=m -# CONFIG_VGA_CONSOLE is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_EXT2_FS=m -CONFIG_EXT3_FS=m -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_ROMFS_FS=y -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_NFSD=m -CONFIG_NFSD_V4=y -CONFIG_SMB_FS=m -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_ISO8859_1=m -CONFIG_DEBUG_KERNEL=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/cm_x300_defconfig b/arch/arm/configs/cm_x300_defconfig deleted file mode 100644 index 95144e380b4bfa3695f19869bf7cdc5cd545618a..0000000000000000000000000000000000000000 --- a/arch/arm/configs/cm_x300_defconfig +++ /dev/null @@ -1,163 +0,0 @@ -CONFIG_LOCALVERSION="-cm-x300" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_NO_HZ_IDLE=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=18 -CONFIG_BLK_DEV_INITRD=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_PXA=y -CONFIG_MACH_CM_X300=y -CONFIG_AEABI=y -CONFIG_HIGHMEM=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="root=/dev/mtdblock5 rootfstype=ubifs console=ttyS2,38400" -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_FPE_NWFPE=y -CONFIG_APM_EMULATION=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_BT=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m -CONFIG_BT_HCIBTUSB=m -CONFIG_LIB80211=m -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_NAND_MARVELL=y -CONFIG_MTD_UBI=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_DM9000=y -CONFIG_DM9000_DEBUGLEVEL=0 -CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_PXA27x=m -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -# CONFIG_TOUCHSCREEN_DA9034 is not set -CONFIG_TOUCHSCREEN_WM97XX=m -# CONFIG_TOUCHSCREEN_WM9705 is not set -# CONFIG_TOUCHSCREEN_WM9713 is not set -# CONFIG_SERIO is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_PXA=y -CONFIG_SERIAL_PXA_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_PXA=y -CONFIG_SPI=y -CONFIG_SPI_GPIO=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_PCA953X=y -# CONFIG_HWMON is not set -CONFIG_PMIC_DA903X=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_DA903X=y -CONFIG_FB=y -CONFIG_FB_PXA=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_TDO24M=y -CONFIG_BACKLIGHT_DA903X=m -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_LOGO=y -CONFIG_SOUND=m -CONFIG_SND=m -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_SPI is not set -# CONFIG_SND_USB is not set -CONFIG_SND_SOC=m -CONFIG_SND_PXA2XX_SOC=m -CONFIG_SND_PXA2XX_SOC_EM_X270=m -CONFIG_HID_DRAGONRISE=y -CONFIG_HID_GYRATION=y -CONFIG_HID_TWINHAN=y -CONFIG_HID_NTRIG=y -CONFIG_HID_PANTHERLORD=y -CONFIG_HID_PETALYNX=y -CONFIG_HID_SAMSUNG=y -CONFIG_HID_SONY=y -CONFIG_HID_SUNPLUS=y -CONFIG_HID_GREENASIA=y -CONFIG_HID_SMARTJOYPLUS=y -CONFIG_HID_TOPSEED=y -CONFIG_HID_THRUSTMASTER=y -CONFIG_HID_ZEROPLUS=y -CONFIG_USB=y -CONFIG_USB_MON=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_MMC=m -CONFIG_MMC_PXA=m -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_V3020=y -CONFIG_RTC_DRV_PXA=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_UBIFS_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_CIFS=m -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_ISO8859_1=m -CONFIG_CRYPTO_MICHAEL_MIC=m -# CONFIG_CRYPTO_HW is not set -CONFIG_CRC_T10DIF=y -CONFIG_FONTS=y -CONFIG_FONT_6x11=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_FS=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_FTRACE is not set -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_AES=m -# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/arm/configs/cns3420vb_defconfig b/arch/arm/configs/cns3420vb_defconfig deleted file mode 100644 index b3aab97c0728f6f9091d6b04ec62688b083c261f..0000000000000000000000000000000000000000 --- a/arch/arm/configs/cns3420vb_defconfig +++ /dev/null @@ -1,63 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_CGROUPS=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_RELAY=y -CONFIG_BLK_DEV_INITRD=y -# CONFIG_PERF_EVENTS is not set -CONFIG_PROFILING=y -CONFIG_ARCH_MULTI_V6=y -CONFIG_ARCH_CNS3XXX=y -CONFIG_MACH_CNS3420VB=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="console=ttyS0,38400 mem=128M root=/dev/mmcblk0p1 ro rootwait" -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_IOSCHED_BFQ=m -#CONFIG_ARCH_MULTI_V7 is not set -CONFIG_DEBUG_CNS3XXX=y -CONFIG_AEABI=y -# CONFIG_SWAP is not set -CONFIG_SLAB=y -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=20000 -CONFIG_BLK_DEV_SD=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ATA=y -# CONFIG_SATA_PMP is not set -# CONFIG_ATA_SFF is not set -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_LEGACY_PTY_COUNT=16 -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_AUTOFS4_FS=y -CONFIG_FSCACHE=y -CONFIG_TMPFS=y -# CONFIG_ENABLE_MUST_CHECK is not set -# CONFIG_ARM_UNWIND is not set -CONFIG_CRC_CCITT=y -CONFIG_DEBUG_FS=y diff --git a/arch/arm/configs/colibri_pxa270_defconfig b/arch/arm/configs/colibri_pxa270_defconfig deleted file mode 100644 index 8357d721c69c85803d471a91e903b2b1495d8d79..0000000000000000000000000000000000000000 --- a/arch/arm/configs/colibri_pxa270_defconfig +++ /dev/null @@ -1,157 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_PREEMPT=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -CONFIG_KALLSYMS_EXTRA_PASS=y -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_PXA=y -CONFIG_MACH_COLIBRI=y -CONFIG_AEABI=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_FPE_NWFPE=y -CONFIG_PM=y -CONFIG_SLAB=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=m -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -CONFIG_VLAN_8021Q=m -CONFIG_BT=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m -CONFIG_CFG80211=y -CONFIG_CONNECTOR=y -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_LE_BYTE_SWAP=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PXA2XX=y -CONFIG_MTD_BLOCK2MTD=y -CONFIG_MTD_ONENAND=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_NAND_DISKONCHIP=y -CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y -CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000 -CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y -CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m -CONFIG_BLK_DEV_NBD=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=8 -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_DM9000=y -CONFIG_PHYLIB=y -CONFIG_HOSTAP=y -CONFIG_HOSTAP_FIRMWARE=y -CONFIG_HOSTAP_FIRMWARE_NVRAM=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=640 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_ATKBD=m -# CONFIG_MOUSE_PS2 is not set -CONFIG_MOUSE_SERIAL=m -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_UINPUT=m -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIAL_PXA=y -CONFIG_SERIAL_PXA_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_WATCHDOG=y -CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y -CONFIG_FB_PXA=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_LOGO=y -# CONFIG_USB_HID is not set -CONFIG_USB=y -CONFIG_USB_SERIAL=m -CONFIG_USB_GADGET=m -CONFIG_USB_GADGET_DUMMY_HCD=y -CONFIG_MMC=y -CONFIG_NEW_LEDS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_HCTOSYS is not set -CONFIG_RTC_DRV_PCF8583=m -CONFIG_AUTOFS4_FS=y -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15" -CONFIG_TMPFS=y -CONFIG_CONFIGFS_FS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_DEBUG=1 -CONFIG_JFFS2_FS_WBUF_VERIFY=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_NFSD=y -CONFIG_NFSD_V4=y -CONFIG_NLS_DEFAULT="iso8859-15" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_UTF8=m -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y -CONFIG_KEYS=y -CONFIG_SECURITY=y -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_SHA1=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_DEFLATE=m -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -CONFIG_LIBCRC32C=y -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -CONFIG_PRINTK_TIME=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/colibri_pxa300_defconfig b/arch/arm/configs/colibri_pxa300_defconfig deleted file mode 100644 index 42adfefdb6dceaee5840a62f27f846c248696740..0000000000000000000000000000000000000000 --- a/arch/arm/configs/colibri_pxa300_defconfig +++ /dev/null @@ -1,60 +0,0 @@ -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_PXA=y -CONFIG_MACH_COLIBRI300=y -CONFIG_AEABI=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="console=ttyS0,115200 rw" -CONFIG_CPU_IDLE=y -CONFIG_FPE_NWFPE=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_NET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_SYN_COOKIES=y -CONFIG_IPV6=y -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_AX88796=y -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_MISC=y -CONFIG_INPUT_GPIO_ROTARY_ENCODER=y -CONFIG_SERIAL_PXA=y -CONFIG_SERIAL_PXA_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_DEBUG_GPIO=y -# CONFIG_HWMON is not set -CONFIG_FB=y -CONFIG_FB_PXA=y -# CONFIG_LCD_CLASS_DEVICE is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -CONFIG_USB=y -CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_MON=y -CONFIG_USB_STORAGE=y -CONFIG_MMC=y -CONFIG_MMC_PXA=y -CONFIG_EXT3_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_AES=y -CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y -CONFIG_CRYPTO_ARC4=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/arm/configs/corgi_defconfig b/arch/arm/configs/corgi_defconfig deleted file mode 100644 index df84640f4f57efdad28c0d54501eec1482e7daea..0000000000000000000000000000000000000000 --- a/arch/arm/configs/corgi_defconfig +++ /dev/null @@ -1,247 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_PREEMPT=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -CONFIG_PROFILING=y -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_PXA=y -CONFIG_PXA_SHARPSL=y -CONFIG_MACH_POODLE=y -CONFIG_MACH_CORGI=y -CONFIG_MACH_SHEPHERD=y -CONFIG_MACH_HUSKY=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="console=ttyS0,115200n8 console=tty1 noinitrd root=/dev/mtdblock2 rootfstype=jffs2 debug" -CONFIG_FPE_NWFPE=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_BINFMT_MISC=m -CONFIG_PM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=m -CONFIG_INET=y -CONFIG_SYN_COOKIES=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_TUNNEL=m -CONFIG_NETFILTER=y -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -CONFIG_BT=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIBCM203X=m -CONFIG_BT_HCIBPA10X=m -CONFIG_BT_HCIBFUSB=m -CONFIG_BT_HCIDTL1=m -CONFIG_BT_HCIBT3C=m -CONFIG_BT_HCIBLUECARD=m -CONFIG_BT_HCIBTUART=m -CONFIG_BT_HCIVHCI=m -CONFIG_PCCARD=y -CONFIG_PCMCIA_PXA2XX=y -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_ROM=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_NAND_SHARPSL=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=m -CONFIG_CHR_DEV_OSST=m -CONFIG_BLK_DEV_SR=m -CONFIG_CHR_DEV_SG=m -CONFIG_SCSI_MULTI_LUN=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ATA=y -CONFIG_PATA_PCMCIA=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_PCMCIA_PCNET=m -CONFIG_PPP=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_ASYNC=m -CONFIG_USB_CATC=m -CONFIG_USB_KAWETH=m -CONFIG_USB_PEGASUS=m -CONFIG_USB_RTL8150=m -CONFIG_USB_USBNET=m -# CONFIG_USB_NET_CDC_SUBSET is not set -CONFIG_NET_PCMCIA=y -CONFIG_INPUT_FF_MEMLESS=m -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_ADS7846=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_UINPUT=m -# CONFIG_SERIO is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_8250=m -CONFIG_SERIAL_8250_CS=m -CONFIG_SERIAL_PXA=y -CONFIG_SERIAL_PXA_CONSOLE=y -CONFIG_I2C=y -CONFIG_I2C_PXA=y -CONFIG_SPI=y -CONFIG_SPI_PXA2XX=y -CONFIG_FB=y -CONFIG_FB_W100=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_CORGI=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_SOUND=y -CONFIG_SOUND_PRIME=y -CONFIG_HID_A4TECH=m -CONFIG_HID_APPLE=m -CONFIG_HID_BELKIN=m -CONFIG_HID_CHERRY=m -CONFIG_HID_CHICONY=m -CONFIG_HID_CYPRESS=m -CONFIG_HID_EZKEY=m -CONFIG_HID_GYRATION=m -CONFIG_HID_LOGITECH=m -CONFIG_HID_MICROSOFT=m -CONFIG_HID_MONTEREY=m -CONFIG_HID_PANTHERLORD=m -CONFIG_HID_PETALYNX=m -CONFIG_HID_SAMSUNG=m -CONFIG_HID_SONY=m -CONFIG_HID_SUNPLUS=m -CONFIG_USB_KBD=m -CONFIG_USB_MOUSE=m -CONFIG_USB=m -CONFIG_USB_MON=m -CONFIG_USB_SL811_HCD=m -CONFIG_USB_SL811_CS=m -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m -CONFIG_USB_STORAGE=m -CONFIG_USB_MDC800=m -CONFIG_USB_MICROTEK=m -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_BELKIN=m -CONFIG_USB_SERIAL_DIGI_ACCELEPORT=m -CONFIG_USB_SERIAL_CYPRESS_M8=m -CONFIG_USB_SERIAL_EMPEG=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_VISOR=m -CONFIG_USB_SERIAL_IPAQ=m -CONFIG_USB_SERIAL_IR=m -CONFIG_USB_SERIAL_EDGEPORT=m -CONFIG_USB_SERIAL_EDGEPORT_TI=m -CONFIG_USB_SERIAL_GARMIN=m -CONFIG_USB_SERIAL_IPW=m -CONFIG_USB_SERIAL_KEYSPAN_PDA=m -CONFIG_USB_SERIAL_KEYSPAN=m -CONFIG_USB_SERIAL_KLSI=m -CONFIG_USB_SERIAL_KOBIL_SCT=m -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_SERIAL_PL2303=m -CONFIG_USB_SERIAL_SAFE=m -CONFIG_USB_SERIAL_TI=m -CONFIG_USB_SERIAL_CYBERJACK=m -CONFIG_USB_SERIAL_OMNINET=m -CONFIG_USB_EMI62=m -CONFIG_USB_EMI26=m -CONFIG_USB_LEGOTOWER=m -CONFIG_USB_LCD=m -CONFIG_USB_CYTHERM=m -CONFIG_USB_IDMOUSE=m -CONFIG_USB_GADGET=y -CONFIG_USB_ZERO=m -CONFIG_USB_ETH=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_MASS_STORAGE=m -CONFIG_USB_G_SERIAL=m -CONFIG_MMC=y -CONFIG_MMC_PXA=y -CONFIG_EXT2_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_RUBIN=y -CONFIG_CRAMFS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_SMB_FS=m -CONFIG_SMB_NLS_DEFAULT=y -CONFIG_NFS_V4=m -CONFIG_NLS_DEFAULT="cp437" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_UTF8=y -CONFIG_DEBUG_KERNEL=y -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_CRC_CCITT=y -CONFIG_LIBCRC32C=m -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -CONFIG_MAGIC_SYSRQ=y -# CONFIG_DEBUG_PREEMPT is not set -# CONFIG_FTRACE is not set diff --git a/arch/arm/configs/dove_defconfig b/arch/arm/configs/dove_defconfig index ff37f46c82fb5cf079b7dfa3258ef0fba1dcd72f..c8d559f38f48f8856b700f7fd4f2ebb416d3b169 100644 --- a/arch/arm/configs/dove_defconfig +++ b/arch/arm/configs/dove_defconfig @@ -117,6 +117,9 @@ CONFIG_NLS_ISO8859_2=y CONFIG_NLS_UTF8=y CONFIG_TIMER_STATS=y CONFIG_CRYPTO_NULL=y +CONFIG_CRYPTO_BLOWFISH=y +CONFIG_CRYPTO_TEA=y +CONFIG_CRYPTO_TWOFISH=y CONFIG_CRYPTO_ECB=m CONFIG_CRYPTO_PCBC=m CONFIG_CRYPTO_HMAC=y @@ -124,9 +127,6 @@ CONFIG_CRYPTO_MD4=y CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA256=y CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_TEA=y -CONFIG_CRYPTO_TWOFISH=y CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/arm/configs/eseries_pxa_defconfig b/arch/arm/configs/eseries_pxa_defconfig deleted file mode 100644 index b4c2e6457e043418fa28f4ae80c4d0ee9af958bb..0000000000000000000000000000000000000000 --- a/arch/arm/configs/eseries_pxa_defconfig +++ /dev/null @@ -1,97 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_KALLSYMS is not set -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_PXA=y -CONFIG_ARCH_PXA_ESERIES=y -CONFIG_IWMMXT=y -CONFIG_AEABI=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_KEXEC=y -CONFIG_FPE_NWFPE=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_BINFMT_MISC=y -CONFIG_PM=y -CONFIG_SLAB=y -# CONFIG_COMPAT_BRK is not set -CONFIG_NET=y -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_IPV6 is not set -CONFIG_CFG80211=m -CONFIG_MAC80211=m -CONFIG_MAC80211_RC_PID=y -# CONFIG_MAC80211_RC_MINSTREL is not set -CONFIG_PCCARD=y -CONFIG_PCMCIA=m -CONFIG_PCMCIA_PXA2XX=m -# CONFIG_STANDALONE is not set -CONFIG_MTD=m -CONFIG_MTD_RAW_NAND=m -CONFIG_MTD_NAND_TMIO=m -CONFIG_BLK_DEV_LOOP=m -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=m -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_ATA=m -# CONFIG_SATA_PMP is not set -CONFIG_PATA_PCMCIA=m -CONFIG_NETDEVICES=y -CONFIG_HERMES=m -CONFIG_PCMCIA_HERMES=m -CONFIG_NET_PCMCIA=y -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_INPUT_EVDEV=m -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_GPIO=m -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_WM97XX=m -# CONFIG_SERIO is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_PXA=y -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -CONFIG_MFD_T7L66XB=y -CONFIG_MFD_TC6387XB=y -CONFIG_MFD_TC6393XB=y -CONFIG_FB=y -CONFIG_FB_PXA=y -CONFIG_FB_W100=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_SOUND=y -CONFIG_SND=m -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -CONFIG_SND_DYNAMIC_MINORS=y -CONFIG_SND_VERBOSE_PRINTK=y -# CONFIG_SND_PCMCIA is not set -CONFIG_SND_SOC=m -CONFIG_SND_PXA2XX_SOC=m -CONFIG_SND_PXA2XX_SOC_E800=m -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -CONFIG_MMC_TMIO=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=m -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_CRYPTO_CBC=m -CONFIG_CRYPTO_PCBC=m -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_FONTS=y -CONFIG_FONT_MINI_4x6=y diff --git a/arch/arm/configs/exynos_defconfig b/arch/arm/configs/exynos_defconfig index 31e8e0c0ee1b77c903aa0a60a2935e4997a83ee4..b0f0baa3a6c48d683e7e06c88dc04c932d35a8af 100644 --- a/arch/arm/configs/exynos_defconfig +++ b/arch/arm/configs/exynos_defconfig @@ -32,11 +32,6 @@ CONFIG_KERNEL_MODE_NEON=y CONFIG_PM_DEBUG=y CONFIG_PM_ADVANCED_DEBUG=y CONFIG_ENERGY_MODEL=y -CONFIG_CRYPTO_SHA1_ARM_NEON=m -CONFIG_CRYPTO_SHA256_ARM=m -CONFIG_CRYPTO_SHA512_ARM=m -CONFIG_CRYPTO_AES_ARM_BS=m -CONFIG_CRYPTO_CHACHA20_NEON=m CONFIG_KALLSYMS_ALL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y @@ -364,6 +359,11 @@ CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_SKCIPHER=m CONFIG_CRYPTO_USER_API_RNG=m CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_SHA1_ARM_NEON=m +CONFIG_CRYPTO_SHA256_ARM=m +CONFIG_CRYPTO_SHA512_ARM=m +CONFIG_CRYPTO_AES_ARM_BS=m +CONFIG_CRYPTO_CHACHA20_NEON=m CONFIG_CRYPTO_DEV_EXYNOS_RNG=y CONFIG_CRYPTO_DEV_S5P=y CONFIG_CRC_CCITT=y diff --git a/arch/arm/configs/ezx_defconfig b/arch/arm/configs/ezx_defconfig deleted file mode 100644 index ef7b0a0aee3a55a93e02e38ce4cf14958f53dce8..0000000000000000000000000000000000000000 --- a/arch/arm/configs/ezx_defconfig +++ /dev/null @@ -1,389 +0,0 @@ -CONFIG_LOCALVERSION="-ezx200910312315" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_NO_HZ_IDLE=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_RD_BZIP2=y -CONFIG_RD_LZMA=y -CONFIG_EXPERT=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_PXA=y -CONFIG_PXA_EZX=y -CONFIG_AEABI=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="console=tty1 root=/dev/mmcblk0p2 rootfstype=ext2 rootdelay=3 ip=192.168.0.202:192.168.0.200:192.168.0.200:255.255.255.0 debug" -CONFIG_KEXEC=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=m -CONFIG_CPU_FREQ_GOV_USERSPACE=m -CONFIG_CPU_FREQ_GOV_ONDEMAND=m -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m -CONFIG_CPU_IDLE=y -CONFIG_FPE_NWFPE=y -CONFIG_PM=y -CONFIG_APM_EMULATION=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_BINFMT_MISC=m -CONFIG_SLAB=y -# CONFIG_COMPAT_BRK is not set -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_SYN_COOKIES=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=m -CONFIG_IPV6_TUNNEL=m -CONFIG_IPV6_MULTIPLE_TABLES=y -CONFIG_IPV6_SUBTREES=y -CONFIG_NETFILTER=y -CONFIG_NETFILTER_NETLINK_QUEUE=m -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CT_PROTO_SCTP=y -CONFIG_NF_CT_PROTO_UDPLITE=y -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_NETBIOS_NS=m -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -CONFIG_NF_NAT=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_LED=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_NF_CONNTRACK_IPV4=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_ADDRTYPE=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_TARGET_LOG=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_NF_NAT_SNMP_BASIC=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_NF_CONNTRACK_IPV6=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -CONFIG_BRIDGE=m -CONFIG_BT=y -CONFIG_BT_RFCOMM=y -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=y -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=y -CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIBTSDIO=m -CONFIG_BT_HCIUART=y -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIBCM203X=m -CONFIG_BT_HCIBPA10X=m -CONFIG_BT_HCIBFUSB=m -CONFIG_BT_HCIVHCI=m -CONFIG_BT_MRVL=m -CONFIG_BT_MRVL_SDIO=m -# CONFIG_WIRELESS is not set -CONFIG_FW_LOADER=m -CONFIG_CONNECTOR=m -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set -# CONFIG_MTD_CFI_I2 is not set -CONFIG_MTD_OTP=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_PXA2XX=y -CONFIG_BLK_DEV_LOOP=m -CONFIG_BLK_DEV_CRYPTOLOOP=m -CONFIG_BLK_DEV_NBD=m -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -CONFIG_DUMMY=y -CONFIG_PPP=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_MULTILINK=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_WLAN is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_GPIO=y -CONFIG_KEYBOARD_PXA27x=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_PCAP=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_UINPUT=y -CONFIG_INPUT_PCAP=y -# CONFIG_SERIO is not set -CONFIG_LEGACY_PTY_COUNT=8 -CONFIG_SERIAL_PXA=y -CONFIG_SERIAL_PXA_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_PXA=y -CONFIG_SPI=y -CONFIG_SPI_PXA2XX=y -CONFIG_GPIO_SYSFS=y -CONFIG_POWER_SUPPLY=y -# CONFIG_HWMON is not set -CONFIG_EZX_PCAP=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_DEBUG=y -CONFIG_REGULATOR_PCAP=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_VIDEO_DEV=y -CONFIG_MEDIA_TUNER_CUSTOMISE=y -CONFIG_RADIO_TEA5764=y -# CONFIG_MEDIA_TUNER_MC44S803 is not set -# CONFIG_MEDIA_TUNER_MT2060 is not set -# CONFIG_MEDIA_TUNER_MT20XX is not set -# CONFIG_MEDIA_TUNER_MT2131 is not set -# CONFIG_MEDIA_TUNER_MT2266 is not set -# CONFIG_MEDIA_TUNER_MXL5005S is not set -# CONFIG_MEDIA_TUNER_MXL5007T is not set -# CONFIG_MEDIA_TUNER_QT1010 is not set -# CONFIG_MEDIA_TUNER_SIMPLE is not set -# CONFIG_MEDIA_TUNER_TDA18271 is not set -# CONFIG_MEDIA_TUNER_TDA827X is not set -# CONFIG_MEDIA_TUNER_TDA8290 is not set -# CONFIG_MEDIA_TUNER_TDA9887 is not set -# CONFIG_MEDIA_TUNER_TEA5761 is not set -# CONFIG_MEDIA_TUNER_TEA5767 is not set -# CONFIG_MEDIA_TUNER_XC2028 is not set -# CONFIG_MEDIA_TUNER_XC5000 is not set -# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set -CONFIG_VIDEO_PXA27x=y -# CONFIG_V4L_USB_DRIVERS is not set -CONFIG_FB=y -CONFIG_FB_PXA=y -CONFIG_FB_PXA_OVERLAY=y -CONFIG_FB_PXA_PARAMETERS=y -# CONFIG_LCD_CLASS_DEVICE is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_PWM=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_ARM is not set -# CONFIG_SND_SPI is not set -# CONFIG_SND_USB is not set -CONFIG_SND_SOC=y -CONFIG_SND_PXA2XX_SOC=y -CONFIG_HID_APPLE=m -# CONFIG_USB_HID is not set -CONFIG_USB=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_GADGET=y -CONFIG_USB_PXA27X=y -CONFIG_USB_ETH=m -# CONFIG_USB_ETH_RNDIS is not set -CONFIG_MMC=y -CONFIG_SDIO_UART=m -CONFIG_MMC_PXA=y -CONFIG_MMC_SPI=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_LP3944=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_BACKLIGHT=y -CONFIG_LEDS_TRIGGER_GPIO=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_PCAP=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=m -CONFIG_REISERFS_FS=m -CONFIG_REISERFS_FS_XATTR=y -CONFIG_REISERFS_FS_POSIX_ACL=y -CONFIG_REISERFS_FS_SECURITY=y -CONFIG_XFS_FS=m -CONFIG_AUTOFS4_FS=y -CONFIG_FUSE_FS=m -CONFIG_CUSE=m -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_ZISOFS=y -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=m -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_JFFS2_RUBIN=y -CONFIG_CRAMFS=m -CONFIG_SQUASHFS=m -CONFIG_ROMFS_FS=m -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFSD=m -CONFIG_NFSD_V3_ACL=y -CONFIG_SMB_FS=m -CONFIG_CIFS=m -CONFIG_CIFS_STATS=y -CONFIG_CIFS_XATTR=y -CONFIG_CIFS_POSIX=y -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=m -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_RT_MUTEXES=y -CONFIG_CRYPTO_NULL=m -CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_VMAC=m -CONFIG_CRYPTO_GHASH=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MICHAEL_MIC=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_AES=m -CONFIG_CRYPTO_ARC4=m -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SEED=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -# CONFIG_CRYPTO_ANSI_CPRNG is not set -CONFIG_FONTS=y -CONFIG_FONT_MINI_4x6=y -CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_FS=y -# CONFIG_SCHED_DEBUG is not set -CONFIG_PROVE_LOCKING=y -# CONFIG_FTRACE is not set -CONFIG_DEBUG_USER=y diff --git a/arch/arm/configs/gemini_defconfig b/arch/arm/configs/gemini_defconfig index a80bc8a43091db668b8743b726ff024f1a07b96c..592a6e6024d4845d490eb52d2957bc52a0fcd5d3 100644 --- a/arch/arm/configs/gemini_defconfig +++ b/arch/arm/configs/gemini_defconfig @@ -83,9 +83,9 @@ CONFIG_LOGO=y CONFIG_USB=y CONFIG_USB_MON=y CONFIG_USB_EHCI_HCD=y -CONFIG_USB_FOTG210_HCD=y CONFIG_USB_UHCI_HCD=y CONFIG_USB_STORAGE=y +CONFIG_USB_FOTG210_HCD=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y diff --git a/arch/arm/configs/h5000_defconfig b/arch/arm/configs/h5000_defconfig deleted file mode 100644 index d01f1a6bd04d9d95463f7c02425115990662e6cb..0000000000000000000000000000000000000000 --- a/arch/arm/configs/h5000_defconfig +++ /dev/null @@ -1,74 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=16 -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_UID16 is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_PXA=y -CONFIG_MACH_H5000=y -CONFIG_AEABI=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="keepinitrd" -CONFIG_KEXEC=y -CONFIG_FPE_NWFPE=y -CONFIG_PM=y -CONFIG_APM_EMULATION=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_SLAB=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_PHYSMAP=y -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_LEGACY_PTY_COUNT=32 -CONFIG_SERIAL_PXA=y -CONFIG_SERIAL_PXA_CONSOLE=y -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -CONFIG_USB_GADGET=y -CONFIG_USB_ETH=m -# CONFIG_USB_ETH_RNDIS is not set -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_SA1100=y -CONFIG_EXT2_FS=y -# CONFIG_PROC_PAGE_MONITOR is not set -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -# CONFIG_NETWORK_FILESYSTEMS is not set -CONFIG_DEBUG_KERNEL=y -CONFIG_CRYPTO=y -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_MD5=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_DEFLATE=y -# CONFIG_CRYPTO_HW is not set -CONFIG_CRC_CCITT=y -CONFIG_PRINTK_TIME=y -# CONFIG_DEBUG_BUGVERBOSE is not set -# CONFIG_SCHED_DEBUG is not set -# CONFIG_FTRACE is not set diff --git a/arch/arm/configs/hackkit_defconfig b/arch/arm/configs/hackkit_defconfig deleted file mode 100644 index 3c91a851fd08de385e8e9f35dea25f461376c1ae..0000000000000000000000000000000000000000 --- a/arch/arm/configs/hackkit_defconfig +++ /dev/null @@ -1,48 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_ARCH_MULTI_V4=y -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_SA1100=y -CONFIG_SA1100_HACKKIT=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="console=ttySA0,115200 root=/dev/ram0 initrd=0xc0400000,8M init=/rootshell" -CONFIG_CPU_FREQ_GOV_PERFORMANCE=y -CONFIG_FPE_NWFPE=y -CONFIG_MODULES=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_SYN_COOKIES=y -# CONFIG_IPV6 is not set -CONFIG_MTD=y -CONFIG_MTD_DEBUG=y -CONFIG_MTD_DEBUG_VERBOSE=3 -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_NETDEVICES=y -CONFIG_DUMMY=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_SERIAL_SA1100=y -CONFIG_SERIAL_SA1100_CONSOLE=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_EXT2_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_CRAMFS=y -CONFIG_DEBUG_KERNEL=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_SPINLOCK=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y -# CONFIG_CRC32 is not set diff --git a/arch/arm/configs/imx_v6_v7_defconfig b/arch/arm/configs/imx_v6_v7_defconfig index 025eb333dcaa6bda40db13571cbf75798e20f59d..6dc6fed12af83065464c851554c58bd763da3428 100644 --- a/arch/arm/configs/imx_v6_v7_defconfig +++ b/arch/arm/configs/imx_v6_v7_defconfig @@ -416,8 +416,8 @@ CONFIG_PWM_FSL_FTM=y CONFIG_PWM_IMX27=y CONFIG_PWM_IMX_TPM=y CONFIG_NVMEM_IMX_OCOTP=y -CONFIG_NVMEM_VF610_OCOTP=y CONFIG_NVMEM_SNVS_LPGPR=y +CONFIG_NVMEM_VF610_OCOTP=y CONFIG_TEE=y CONFIG_OPTEE=y CONFIG_MUX_MMIO=y @@ -474,5 +474,4 @@ CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y # CONFIG_SLUB_DEBUG is not set # CONFIG_SCHED_DEBUG is not set -CONFIG_PROVE_LOCKING=y # CONFIG_FTRACE is not set diff --git a/arch/arm/configs/iop32x_defconfig b/arch/arm/configs/iop32x_defconfig deleted file mode 100644 index 19e30e790d3503a3224ba21c01fcefc2c2157ee6..0000000000000000000000000000000000000000 --- a/arch/arm/configs/iop32x_defconfig +++ /dev/null @@ -1,126 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_KALLSYMS_ALL=y -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_IOP32X=y -CONFIG_MACH_GLANTANK=y -CONFIG_ARCH_IQ80321=y -CONFIG_ARCH_IQ31244=y -CONFIG_MACH_N2100=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="console=ttyS0,115200 root=/dev/nfs ip=bootp cachepolicy=writealloc" -CONFIG_FPE_NWFPE=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_SLAB=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IPV6=y -# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET6_XFRM_MODE_TUNNEL is not set -# CONFIG_INET6_XFRM_MODE_BEET is not set -# CONFIG_IPV6_SIT is not set -CONFIG_MTD=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y -CONFIG_MTD_REDBOOT_PARTS_READONLY=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ATA=y -CONFIG_SATA_SIL=y -CONFIG_SATA_VITESSE=y -CONFIG_MD=y -CONFIG_BLK_DEV_MD=y -CONFIG_MD_RAID0=y -CONFIG_MD_RAID1=y -CONFIG_MD_RAID10=y -CONFIG_MD_RAID456=y -CONFIG_BLK_DEV_DM=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_NET_PCI=y -CONFIG_E100=y -CONFIG_E1000=y -CONFIG_R8169=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_IOP3XX=y -# CONFIG_VGA_CONSOLE is not set -# CONFIG_USB_HID is not set -CONFIG_USB=y -CONFIG_USB_MON=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_ROOT_HUB_TT=y -CONFIG_USB_EHCI_TT_NEWSCHED=y -CONFIG_USB_UHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_RS5C372=y -CONFIG_DMADEVICES=y -CONFIG_INTEL_IOP_ADMA=y -CONFIG_NET_DMA=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -CONFIG_TMPFS=y -CONFIG_ECRYPT_FS=y -CONFIG_JFFS2_FS=y -CONFIG_CRAMFS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_NFSD=y -CONFIG_KEYS=y -CONFIG_CRYPTO_NULL=y -CONFIG_CRYPTO_LRW=y -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_MD4=y -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_SHA256=y -CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_TGR192=y -CONFIG_CRYPTO_WP512=y -CONFIG_CRYPTO_AES=y -CONFIG_CRYPTO_ANUBIS=y -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_BLOWFISH=y -CONFIG_CRYPTO_CAST5=y -CONFIG_CRYPTO_CAST6=y -CONFIG_CRYPTO_DES=y -CONFIG_CRYPTO_KHAZAD=y -CONFIG_CRYPTO_SERPENT=y -CONFIG_CRYPTO_TEA=y -CONFIG_CRYPTO_TWOFISH=y -CONFIG_CRYPTO_DEFLATE=y -CONFIG_LIBCRC32C=y -CONFIG_DEBUG_KERNEL=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y -CONFIG_DEBUG_LL_UART_8250=y diff --git a/arch/arm/configs/jornada720_defconfig b/arch/arm/configs/jornada720_defconfig index ae1d68da4f2acfd1b8623c4097c076c98e78170c..91bdcc095884e12fcc138361cfdb8c817c05f59f 100644 --- a/arch/arm/configs/jornada720_defconfig +++ b/arch/arm/configs/jornada720_defconfig @@ -6,7 +6,6 @@ CONFIG_ARCH_MULTI_V4=y CONFIG_ARCH_SA1100=y CONFIG_SA1100_JORNADA720=y CONFIG_SA1100_JORNADA720_SSP=y -CONFIG_UNUSED_BOARD_FILES=y CONFIG_FPE_NWFPE=y CONFIG_PM=y CONFIG_MODULES=y diff --git a/arch/arm/configs/keystone_defconfig b/arch/arm/configs/keystone_defconfig index 4a5b9adbf2a1674c1d7e014094665b91e26f082b..d7a0bca641ebe1c7e71b4799aee1f13b85f0ef54 100644 --- a/arch/arm/configs/keystone_defconfig +++ b/arch/arm/configs/keystone_defconfig @@ -225,10 +225,10 @@ CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y CONFIG_CRYPTO_USER=y CONFIG_CRYPTO_AUTHENC=y +CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_CTR=y CONFIG_CRYPTO_XCBC=y -CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_ANSI_CPRNG=y CONFIG_CRYPTO_USER_API_HASH=y CONFIG_CRYPTO_USER_API_SKCIPHER=y diff --git a/arch/arm/configs/lart_defconfig b/arch/arm/configs/lart_defconfig deleted file mode 100644 index 916177d07a394aef0735c14b863c0a70bffe838e..0000000000000000000000000000000000000000 --- a/arch/arm/configs/lart_defconfig +++ /dev/null @@ -1,64 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_ARCH_MULTI_V4=y -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_SA1100=y -CONFIG_SA1100_LART=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="console=ttySA0,9600 root=/dev/ram" -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_FPE_NWFPE=y -CONFIG_PM=y -CONFIG_MODULES=y -CONFIG_NET=y -CONFIG_PACKET=m -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_SYN_COOKIES=y -# CONFIG_IPV6 is not set -CONFIG_MTD=y -CONFIG_MTD_DEBUG=y -CONFIG_MTD_DEBUG_VERBOSE=1 -CONFIG_MTD_BLOCK=y -CONFIG_MTD_LART=y -CONFIG_BLK_DEV_RAM=y -CONFIG_NETDEVICES=y -CONFIG_DUMMY=m -CONFIG_NET_ETHERNET=y -CONFIG_PPP=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_ASYNC=m -CONFIG_SLIP=m -CONFIG_SLIP_COMPRESSED=y -CONFIG_SERIAL_SA1100=y -CONFIG_SERIAL_SA1100_CONSOLE=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_SOUND=m -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=m -CONFIG_REISERFS_FS=m -CONFIG_ISO9660_FS=m -CONFIG_JOLIET=y -CONFIG_UDF_FS=m -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=m -CONFIG_JFFS2_FS_DEBUG=1 -CONFIG_CRAMFS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_NFSD=m -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_UTF8=m -CONFIG_DEBUG_USER=y -CONFIG_CRC32=m diff --git a/arch/arm/configs/lpae.config b/arch/arm/configs/lpae.config new file mode 100644 index 0000000000000000000000000000000000000000..a6d6f7ab3c01a130d9086af74290fdd37bd3bc82 --- /dev/null +++ b/arch/arm/configs/lpae.config @@ -0,0 +1,2 @@ +CONFIG_ARM_LPAE=y +CONFIG_VMSPLIT_2G=y diff --git a/arch/arm/configs/lpd270_defconfig b/arch/arm/configs/lpd270_defconfig deleted file mode 100644 index b0c21a99a0a8af0d73e4e8c849b53ef847b49a7e..0000000000000000000000000000000000000000 --- a/arch/arm/configs/lpd270_defconfig +++ /dev/null @@ -1,58 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_PXA=y -CONFIG_MACH_LOGICPD_PXA270=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="root=/dev/nfs ip=bootp console=ttyS0,115200 mem=64M" -CONFIG_FPE_NWFPE=y -CONFIG_MODULES=y -CONFIG_SLAB=y -CONFIG_NET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IPV6=y -# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET6_XFRM_MODE_TUNNEL is not set -# CONFIG_INET6_XFRM_MODE_BEET is not set -# CONFIG_IPV6_SIT is not set -CONFIG_MTD=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -# CONFIG_MTD_CFI_I1 is not set -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_BLK_DEV_NBD=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=y -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO_SERPORT is not set -CONFIG_SERIAL_PXA=y -CONFIG_SERIAL_PXA_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_FB=y -CONFIG_FB_PXA=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -CONFIG_SOUND=y -CONFIG_SND=y -# CONFIG_SND_SUPPORT_OLD_API is not set -CONFIG_SND_PXA2XX_AC97=y -CONFIG_EXT2_FS=y -CONFIG_MSDOS_FS=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_ISO8859_1=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/lubbock_defconfig b/arch/arm/configs/lubbock_defconfig deleted file mode 100644 index 4fc744c96196223db183b8297c2cf509e30d4f64..0000000000000000000000000000000000000000 --- a/arch/arm/configs/lubbock_defconfig +++ /dev/null @@ -1,53 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_PXA=y -CONFIG_ARCH_LUBBOCK=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="root=/dev/nfs ip=bootp console=ttyS0,115200 mem=64M" -CONFIG_FPE_NWFPE=y -CONFIG_MODULES=y -CONFIG_NET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IPV6 is not set -CONFIG_PCCARD=y -CONFIG_PCMCIA_PXA2XX=y -CONFIG_MTD=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -# CONFIG_MTD_CFI_I1 is not set -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_NET_PCMCIA=y -CONFIG_PCMCIA_PCNET=y -CONFIG_SMC91X=y -CONFIG_INPUT_EVDEV=y -# CONFIG_SERIO_SERPORT is not set -CONFIG_SERIO_SA1111=y -CONFIG_SERIAL_PXA=y -CONFIG_SERIAL_PXA_CONSOLE=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_USB_GADGET=y -CONFIG_USB_G_SERIAL=m -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_EXT2_FS=y -CONFIG_MSDOS_FS=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_ISO8859_1=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/magician_defconfig b/arch/arm/configs/magician_defconfig deleted file mode 100644 index 5a8776f6aba39d7ef297ddf0c64e19f8eb85327c..0000000000000000000000000000000000000000 --- a/arch/arm/configs/magician_defconfig +++ /dev/null @@ -1,151 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_NO_HZ_IDLE=y -CONFIG_PREEMPT=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_UID16 is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_PXA=y -CONFIG_MACH_H4700=y -CONFIG_MACH_MAGICIAN=y -CONFIG_AEABI=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="keepinitrd" -CONFIG_KEXEC=y -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_FPE_NWFPE=y -CONFIG_PM=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_SLAB=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_BT=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m -CONFIG_BT_HCIBTUSB=m -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_PHYSMAP=y -CONFIG_NETDEVICES=y -CONFIG_PPP=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_MPPE=m -# CONFIG_INPUT_MOUSEDEV is not set -CONFIG_PPP_ASYNC=m -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_GPIO=y -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_UINPUT=m -# CONFIG_SERIO is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_PXA=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=m -CONFIG_I2C_PXA=y -CONFIG_W1_MASTER_DS1WM=y -CONFIG_HTC_EGPIO=y -CONFIG_POWER_SUPPLY=y -CONFIG_PDA_POWER=y -CONFIG_BATTERY_DS2760=y -# CONFIG_HWMON is not set -CONFIG_MFD_ASIC3=y -CONFIG_HTC_PASIC3=y -CONFIG_REGULATOR=y -CONFIG_REGULATOR_GPIO=y -CONFIG_FB=y -CONFIG_FB_PXA=y -CONFIG_FB_PXA_OVERLAY=y -CONFIG_FB_W100=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_PWM=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_SOUND=y -CONFIG_SND=m -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -# CONFIG_SND_ARM is not set -# CONFIG_SND_USB is not set -CONFIG_SND_SOC=m -CONFIG_SND_PXA2XX_SOC=m -CONFIG_USB=y -CONFIG_USB_MON=m -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_GPIO_VBUS=y -CONFIG_USB_GADGET=y -CONFIG_USB_GADGET_VBUS_DRAW=500 -CONFIG_USB_PXA27X=y -CONFIG_USB_ETH=m -# CONFIG_USB_ETH_RNDIS is not set -CONFIG_USB_GADGETFS=m -CONFIG_USB_MASS_STORAGE=m -CONFIG_USB_G_SERIAL=m -CONFIG_USB_CDC_COMPOSITE=m -CONFIG_MMC=y -CONFIG_SDIO_UART=m -CONFIG_MMC_PXA=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_BACKLIGHT=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DEBUG=y -CONFIG_RTC_DRV_PXA=y -CONFIG_EXT2_FS=y -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_JFFS2_LZO=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_DEFAULT="utf8" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_UTF8=y -CONFIG_CRYPTO=y -# CONFIG_CRYPTO_HW is not set -CONFIG_CRC_CCITT=y -CONFIG_FONTS=y -CONFIG_FONT_MINI_4x6=y -CONFIG_PRINTK_TIME=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -CONFIG_TIMER_STATS=y -# CONFIG_DEBUG_PREEMPT is not set -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/arm/configs/mainstone_defconfig b/arch/arm/configs/mainstone_defconfig deleted file mode 100644 index 096cd7bc667ab88511bc3bcc573610aff7c9e40c..0000000000000000000000000000000000000000 --- a/arch/arm/configs/mainstone_defconfig +++ /dev/null @@ -1,51 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_PXA=y -CONFIG_MACH_MAINSTONE=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="root=/dev/nfs ip=bootp console=ttyS0,115200 mem=64M" -CONFIG_FPE_NWFPE=y -CONFIG_MODULES=y -CONFIG_NET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IPV6 is not set -CONFIG_MTD=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -# CONFIG_MTD_CFI_I1 is not set -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=y -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO_SERPORT is not set -CONFIG_SERIAL_PXA=y -CONFIG_SERIAL_PXA_CONSOLE=y -CONFIG_FB=y -CONFIG_FB_PXA=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_EXT2_FS=y -CONFIG_MSDOS_FS=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_ISO8859_1=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/milbeaut_m10v_defconfig b/arch/arm/configs/milbeaut_m10v_defconfig index a2e25bf843ccf4b6d80b8c803ed7485948e35eb7..bd29e5012cb0215049a37f4e9708c343f365e521 100644 --- a/arch/arm/configs/milbeaut_m10v_defconfig +++ b/arch/arm/configs/milbeaut_m10v_defconfig @@ -44,16 +44,6 @@ CONFIG_ARM_CPUIDLE=y CONFIG_VFP=y CONFIG_NEON=y CONFIG_KERNEL_MODE_NEON=y -CONFIG_CRYPTO_SHA1_ARM_NEON=m -CONFIG_CRYPTO_SHA1_ARM_CE=m -CONFIG_CRYPTO_SHA2_ARM_CE=m -CONFIG_CRYPTO_SHA512_ARM=m -CONFIG_CRYPTO_AES_ARM=m -CONFIG_CRYPTO_AES_ARM_BS=m -CONFIG_CRYPTO_AES_ARM_CE=m -CONFIG_CRYPTO_GHASH_ARM_CE=m -CONFIG_CRYPTO_CRC32_ARM_CE=m -CONFIG_CRYPTO_CHACHA20_NEON=m CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y @@ -105,9 +95,19 @@ CONFIG_NLS_UTF8=y CONFIG_KEYS=y CONFIG_CRYPTO_MANAGER=y # CONFIG_CRYPTO_MANAGER_DISABLE_TESTS is not set -CONFIG_CRYPTO_SEQIV=m # CONFIG_CRYPTO_ECHAINIV is not set CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_SEQIV=m +CONFIG_CRYPTO_GHASH_ARM_CE=m +CONFIG_CRYPTO_SHA1_ARM_NEON=m +CONFIG_CRYPTO_SHA1_ARM_CE=m +CONFIG_CRYPTO_SHA2_ARM_CE=m +CONFIG_CRYPTO_SHA512_ARM=m +CONFIG_CRYPTO_AES_ARM=m +CONFIG_CRYPTO_AES_ARM_BS=m +CONFIG_CRYPTO_AES_ARM_CE=m +CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_CRYPTO_CRC32_ARM_CE=m # CONFIG_CRYPTO_HW is not set CONFIG_CRC_CCITT=m CONFIG_CRC_ITU_T=m diff --git a/arch/arm/configs/mini2440_defconfig b/arch/arm/configs/mini2440_defconfig deleted file mode 100644 index 86e00f684e167eaf85e8c0599535982c4314c34e..0000000000000000000000000000000000000000 --- a/arch/arm/configs/mini2440_defconfig +++ /dev/null @@ -1,338 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_RELAY=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_ARCH_MULTI_V4T=y -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_S3C24XX=y -CONFIG_S3C_ADC=y -# CONFIG_CPU_S3C2410 is not set -CONFIG_CPU_S3C2440=y -CONFIG_MACH_MINI2440=y -CONFIG_AEABI=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_KEXEC=y -CONFIG_CPU_IDLE=y -CONFIG_APM_EMULATION=y -CONFIG_MODULES=y -CONFIG_MODULE_FORCE_LOAD=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_BLK_DEV_INTEGRITY=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_BSD_DISKLABEL=y -CONFIG_MINIX_SUBPARTITION=y -CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_UNIXWARE_DISKLABEL=y -CONFIG_LDM_PARTITION=y -CONFIG_BINFMT_MISC=m -# CONFIG_COMPAT_BRK is not set -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=m -CONFIG_NET_KEY=m -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_ADVANCED_ROUTER=y -CONFIG_IP_MULTIPLE_TABLES=y -CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_ROUTE_VERBOSE=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_IP_PNP_RARP=y -CONFIG_IP_MROUTE=y -CONFIG_IP_PIMSM_V1=y -CONFIG_IP_PIMSM_V2=y -CONFIG_SYN_COOKIES=y -CONFIG_INET_DIAG=m -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -CONFIG_BRIDGE=m -CONFIG_VLAN_8021Q=m -CONFIG_VLAN_8021Q_GVRP=y -CONFIG_NET_PKTGEN=m -CONFIG_BT=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m -CONFIG_BT_HCIBTUSB=m -CONFIG_BT_HCIBTSDIO=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIBCM203X=m -CONFIG_BT_HCIBPA10X=m -CONFIG_BT_HCIBFUSB=m -CONFIG_BT_HCIVHCI=m -CONFIG_CFG80211=m -CONFIG_MAC80211=m -CONFIG_MAC80211_MESH=y -CONFIG_MAC80211_LEDS=y -CONFIG_CONNECTOR=m -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_FTL=y -CONFIG_NFTL=y -CONFIG_NFTL_RW=y -CONFIG_INFTL=y -CONFIG_RFD_FTL=y -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_CFI_STAA=y -CONFIG_MTD_RAM=y -CONFIG_MTD_ROM=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_NAND_S3C2410=y -CONFIG_MTD_NAND_PLATFORM=y -CONFIG_MTD_LPDDR=y -CONFIG_BLK_DEV_LOOP=m -CONFIG_BLK_DEV_NBD=m -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=65536 -CONFIG_CDROM_PKTCDVD=m -CONFIG_SENSORS_TSL2550=m -CONFIG_EEPROM_AT24=y -CONFIG_SCSI=m -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=m -CONFIG_CHR_DEV_SG=m -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_NETDEVICES=y -CONFIG_TUN=m -CONFIG_DM9000=y -CONFIG_PPP=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_HOSTAP=m -CONFIG_HOSTAP_FIRMWARE=y -CONFIG_HOSTAP_FIRMWARE_NVRAM=y -CONFIG_LIBERTAS=m -CONFIG_LIBERTAS_SDIO=m -CONFIG_ZD1211RW=m -CONFIG_ZD1211RW_DEBUG=y -CONFIG_INPUT_EVDEV=y -CONFIG_INPUT_EVBUG=m -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_GPIO=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_SERIO_RAW=y -CONFIG_LEGACY_PTY_COUNT=128 -CONFIG_SERIAL_SAMSUNG=y -CONFIG_SERIAL_SAMSUNG_CONSOLE=y -CONFIG_SERIAL_DEV_BUS=m -CONFIG_IPMI_HANDLER=m -CONFIG_IPMI_DEVICE_INTERFACE=m -CONFIG_IPMI_SI=m -CONFIG_IPMI_WATCHDOG=m -CONFIG_IPMI_POWEROFF=m -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_S3C2410=y -CONFIG_I2C_SIMTEC=y -CONFIG_SPI=y -CONFIG_SPI_S3C24XX=y -CONFIG_SPI_SPIDEV=y -CONFIG_GPIO_SYSFS=y -CONFIG_SENSORS_LM75=y -CONFIG_THERMAL=y -CONFIG_WATCHDOG=y -CONFIG_S3C2410_WATCHDOG=y -CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_TILEBLITTING=y -CONFIG_FB_S3C2410=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_LCD_PLATFORM=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_PWM=y -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_LOGO=y -# CONFIG_LOGO_LINUX_MONO is not set -# CONFIG_LOGO_LINUX_VGA16 is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_DYNAMIC_MINORS=y -CONFIG_SND_SEQUENCER=m -CONFIG_SND_SEQ_DUMMY=m -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_ARM is not set -# CONFIG_SND_SPI is not set -CONFIG_SND_USB_AUDIO=m -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_USB_CAIAQ_INPUT=y -CONFIG_SND_SOC=y -CONFIG_HIDRAW=y -CONFIG_HID_GYRATION=y -CONFIG_HID_NTRIG=y -CONFIG_HID_PANTHERLORD=y -CONFIG_HID_PETALYNX=y -CONFIG_HID_SAMSUNG=y -CONFIG_HID_SONY=y -CONFIG_HID_SUNPLUS=y -CONFIG_HID_TOPSEED=y -CONFIG_HID_PID=y -CONFIG_USB_HIDDEV=y -CONFIG_USB=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_ACM=m -CONFIG_USB_WDM=m -CONFIG_USB_STORAGE=m -CONFIG_USB_STORAGE_DATAFAB=m -CONFIG_USB_STORAGE_ISD200=m -CONFIG_USB_STORAGE_USBAT=m -CONFIG_USB_STORAGE_SDDR09=m -CONFIG_USB_STORAGE_SDDR55=m -CONFIG_USB_STORAGE_JUMPSHOT=m -CONFIG_USB_STORAGE_ALAUDA=m -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_CP210X=m -CONFIG_USB_SERIAL_FTDI_SIO=m -CONFIG_USB_SERIAL_SPCP8X5=m -CONFIG_USB_GADGET=y -CONFIG_USB_S3C2410=y -CONFIG_USB_ZERO=m -CONFIG_USB_ETH=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_MASS_STORAGE=m -CONFIG_USB_G_SERIAL=m -CONFIG_USB_CDC_COMPOSITE=m -CONFIG_MMC=y -CONFIG_SDIO_UART=y -CONFIG_MMC_SDHCI=y -CONFIG_MMC_SPI=y -CONFIG_MMC_S3C=y -CONFIG_LEDS_S3C24XX=y -CONFIG_LEDS_GPIO=y -CONFIG_LEDS_TRIGGER_TIMER=y -CONFIG_LEDS_TRIGGER_HEARTBEAT=y -CONFIG_LEDS_TRIGGER_GPIO=y -CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_INTF_DEV_UIE_EMUL=y -CONFIG_RTC_DRV_S3C=y -CONFIG_DMADEVICES=y -CONFIG_S3C24XX_DMAC=y -CONFIG_PWM=y -CONFIG_PWM_SAMSUNG=y -CONFIG_EXT2_FS=m -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -CONFIG_AUTOFS4_FS=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_JFFS2_FS=y -CONFIG_CRAMFS=y -CONFIG_ROMFS_FS=y -CONFIG_ROMFS_BACKED_BY_BOTH=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3_ACL=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_DEFAULT="cp437" -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=m -CONFIG_CRYPTO_CRYPTD=m -CONFIG_CRYPTO_AUTHENC=m -CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_CTS=m -CONFIG_CRYPTO_ECB=y -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MICHAEL_MIC=y -CONFIG_CRYPTO_RMD128=m -CONFIG_CRYPTO_RMD160=m -CONFIG_CRYPTO_RMD256=m -CONFIG_CRYPTO_RMD320=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_ANUBIS=m -CONFIG_CRYPTO_ARC4=y -CONFIG_CRYPTO_BLOWFISH=m -CONFIG_CRYPTO_CAMELLIA=m -CONFIG_CRYPTO_CAST5=m -CONFIG_CRYPTO_CAST6=m -CONFIG_CRYPTO_FCRYPT=m -CONFIG_CRYPTO_KHAZAD=m -CONFIG_CRYPTO_SALSA20=m -CONFIG_CRYPTO_SEED=m -CONFIG_CRYPTO_SERPENT=m -CONFIG_CRYPTO_TEA=m -CONFIG_CRYPTO_TWOFISH=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRYPTO_LZO=m -CONFIG_LIBCRC32C=m -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -CONFIG_FONT_MINI_4x6=y -CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_DEBUG_KERNEL=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_FS=y -# CONFIG_SCHED_DEBUG is not set -CONFIG_DEBUG_USER=y diff --git a/arch/arm/configs/multi_v5_defconfig b/arch/arm/configs/multi_v5_defconfig index 60fc52b956902af3e466858dc215de82e127cb8f..52bb1a5e25fc49c914b73fe1ae0ec050c7163496 100644 --- a/arch/arm/configs/multi_v5_defconfig +++ b/arch/arm/configs/multi_v5_defconfig @@ -49,6 +49,7 @@ CONFIG_ARM_KIRKWOOD_CPUIDLE=y CONFIG_KPROBES=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y +CONFIG_IOSCHED_BFQ=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -138,6 +139,7 @@ CONFIG_HW_RANDOM_TIMERIOMEM=m CONFIG_I2C_CHARDEV=y CONFIG_I2C_ASPEED=m CONFIG_I2C_AT91=y +CONFIG_I2C_GPIO=m CONFIG_I2C_IMX=y CONFIG_I2C_MV64XXX=y CONFIG_SPI=y diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig index ee184eb37adcf4b888303ea544bf4785c53a4b03..084cc612ea23a1c7aabbf9af56b0117d21b38234 100644 --- a/arch/arm/configs/multi_v7_defconfig +++ b/arch/arm/configs/multi_v7_defconfig @@ -132,20 +132,11 @@ CONFIG_ARM_EXYNOS_CPUIDLE=y CONFIG_ARM_TEGRA_CPUIDLE=y CONFIG_ARM_QCOM_SPM_CPUIDLE=y CONFIG_KERNEL_MODE_NEON=y -CONFIG_CRYPTO_SHA1_ARM_NEON=m -CONFIG_CRYPTO_SHA1_ARM_CE=m -CONFIG_CRYPTO_SHA2_ARM_CE=m -CONFIG_CRYPTO_SHA512_ARM=m -CONFIG_CRYPTO_AES_ARM=m -CONFIG_CRYPTO_AES_ARM_BS=m -CONFIG_CRYPTO_AES_ARM_CE=m -CONFIG_CRYPTO_GHASH_ARM_CE=m -CONFIG_CRYPTO_CRC32_ARM_CE=m -CONFIG_CRYPTO_CHACHA20_NEON=m CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_PARTITION_ADVANCED=y CONFIG_CMDLINE_PARTITION=y +CONFIG_IOSCHED_BFQ=y CONFIG_NET=y CONFIG_PACKET=y CONFIG_UNIX=y @@ -191,6 +182,7 @@ CONFIG_PCI_TEGRA=y CONFIG_PCI_RCAR_GEN2=y CONFIG_PCIE_RCAR_HOST=y CONFIG_PCI_DRA7XX_EP=y +CONFIG_PCI_LAYERSCAPE=y CONFIG_PCI_ENDPOINT=y CONFIG_PCI_ENDPOINT_CONFIGFS=y CONFIG_PCI_EPF_TEST=m @@ -249,6 +241,7 @@ CONFIG_AHCI_ST=y CONFIG_AHCI_IMX=y CONFIG_AHCI_SUNXI=y CONFIG_AHCI_TEGRA=y +CONFIG_AHCI_QORIQ=y CONFIG_SATA_HIGHBANK=y CONFIG_SATA_MV=y CONFIG_SATA_RCAR=y @@ -329,6 +322,7 @@ CONFIG_TOUCHSCREEN_ADC=m CONFIG_TOUCHSCREEN_ATMEL_MXT=m CONFIG_TOUCHSCREEN_ELAN=m CONFIG_TOUCHSCREEN_MMS114=m +CONFIG_TOUCHSCREEN_EDT_FT5X06=m CONFIG_TOUCHSCREEN_WM97XX=m CONFIG_TOUCHSCREEN_ST1232=m CONFIG_TOUCHSCREEN_STMPE=y @@ -440,6 +434,7 @@ CONFIG_SPI_BCM2835AUX=y CONFIG_SPI_CADENCE=y CONFIG_SPI_DAVINCI=y CONFIG_SPI_FSL_QUADSPI=m +CONFIG_SPI_GXP=m CONFIG_SPI_GPIO=m CONFIG_SPI_FSL_DSPI=m CONFIG_SPI_OMAP24XX=y @@ -483,6 +478,7 @@ CONFIG_GPIO_ASPEED_SGPIO=y CONFIG_GPIO_DAVINCI=y CONFIG_GPIO_DWAPB=y CONFIG_GPIO_EM=y +CONFIG_GPIO_MPC8XXX=y CONFIG_GPIO_MXC=y CONFIG_GPIO_RCAR=y CONFIG_GPIO_SYSCON=y @@ -493,6 +489,7 @@ CONFIG_GPIO_PCA953X=y CONFIG_GPIO_PCA953X_IRQ=y CONFIG_GPIO_PCF857X=y CONFIG_GPIO_PALMAS=y +CONFIG_GPIO_STMPE=y CONFIG_GPIO_TPS6586X=y CONFIG_GPIO_TPS65910=y CONFIG_GPIO_TWL4030=y @@ -530,9 +527,11 @@ CONFIG_SENSORS_NTC_THERMISTOR=m CONFIG_SENSORS_PWM_FAN=m CONFIG_SENSORS_RASPBERRYPI_HWMON=m CONFIG_SENSORS_INA2XX=m +CONFIG_SENSORS_GXP_FAN_CTRL=m CONFIG_CPU_THERMAL=y CONFIG_DEVFREQ_THERMAL=y CONFIG_IMX_THERMAL=y +CONFIG_QORIQ_THERMAL=m CONFIG_ROCKCHIP_THERMAL=y CONFIG_RCAR_THERMAL=y CONFIG_ARMADA_THERMAL=y @@ -821,6 +820,10 @@ CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m CONFIG_SND_SOC_SGTL5000=m CONFIG_SND_SOC_STI_SAS=m +CONFIG_SND_SOC_TLV320AIC32X4=m +CONFIG_SND_SOC_TLV320AIC32X4_I2C=m +CONFIG_SND_SOC_WM8960=m +CONFIG_SND_SOC_WM8962=m CONFIG_SND_SOC_WM8978=m CONFIG_SND_AUDIO_GRAPH_CARD=m CONFIG_USB=y @@ -830,6 +833,7 @@ CONFIG_USB_XHCI_MVEBU=y CONFIG_USB_XHCI_TEGRA=m CONFIG_USB_BRCMSTB=m CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_FSL=m CONFIG_USB_EHCI_HCD_STI=y CONFIG_USB_EHCI_EXYNOS=m CONFIG_USB_EHCI_MV=m @@ -933,6 +937,8 @@ CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_CLASS_FLASH=m CONFIG_LEDS_CPCAP=m +CONFIG_LEDS_PCA9532=m +CONFIG_LEDS_PCA9532_GPIO=y CONFIG_LEDS_GPIO=y CONFIG_LEDS_PWM=y CONFIG_LEDS_MAX8997=m @@ -949,6 +955,7 @@ CONFIG_LEDS_TRIGGER_DEFAULT_ON=y CONFIG_LEDS_TRIGGER_TRANSIENT=y CONFIG_LEDS_TRIGGER_CAMERA=y CONFIG_EDAC=y +CONFIG_EDAC_LAYERSCAPE=y CONFIG_EDAC_HIGHBANK_MC=y CONFIG_EDAC_HIGHBANK_L2=y CONFIG_RTC_CLASS=y @@ -962,6 +969,7 @@ CONFIG_RTC_DRV_MAX8997=m CONFIG_RTC_DRV_MAX77686=y CONFIG_RTC_DRV_RK808=m CONFIG_RTC_DRV_RS5C372=m +CONFIG_RTC_DRV_PCF85063=m CONFIG_RTC_DRV_PCF85363=m CONFIG_RTC_DRV_BQ32K=m CONFIG_RTC_DRV_TWL4030=y @@ -1190,12 +1198,13 @@ CONFIG_TI_PIPE3=y CONFIG_TWL4030_USB=m CONFIG_RAS=y CONFIG_NVMEM_IMX_OCOTP=y +CONFIG_NVMEM_MESON_MX_EFUSE=m CONFIG_NVMEM_QCOM_QFPROM=y +CONFIG_NVMEM_RMEM=m CONFIG_NVMEM_ROCKCHIP_EFUSE=m +CONFIG_NVMEM_STM32_ROMEM=m CONFIG_NVMEM_SUNXI_SID=y CONFIG_NVMEM_VF610_OCOTP=y -CONFIG_NVMEM_MESON_MX_EFUSE=m -CONFIG_NVMEM_RMEM=m CONFIG_FSI=m CONFIG_FSI_MASTER_GPIO=m CONFIG_FSI_MASTER_HUB=m @@ -1236,6 +1245,16 @@ CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_SKCIPHER=m CONFIG_CRYPTO_USER_API_RNG=m CONFIG_CRYPTO_USER_API_AEAD=m +CONFIG_CRYPTO_GHASH_ARM_CE=m +CONFIG_CRYPTO_SHA1_ARM_NEON=m +CONFIG_CRYPTO_SHA1_ARM_CE=m +CONFIG_CRYPTO_SHA2_ARM_CE=m +CONFIG_CRYPTO_SHA512_ARM=m +CONFIG_CRYPTO_AES_ARM=m +CONFIG_CRYPTO_AES_ARM_BS=m +CONFIG_CRYPTO_AES_ARM_CE=m +CONFIG_CRYPTO_CHACHA20_NEON=m +CONFIG_CRYPTO_CRC32_ARM_CE=m CONFIG_CRYPTO_DEV_SUN4I_SS=m CONFIG_CRYPTO_DEV_FSL_CAAM=m CONFIG_CRYPTO_DEV_EXYNOS_RNG=m diff --git a/arch/arm/configs/mv78xx0_defconfig b/arch/arm/configs/mv78xx0_defconfig index 877c5150a98768ba3ad4ac037cc510eeb7e32d2f..4ed6e8c8e164d0da008f530e5136fcedb3c26d27 100644 --- a/arch/arm/configs/mv78xx0_defconfig +++ b/arch/arm/configs/mv78xx0_defconfig @@ -11,13 +11,10 @@ CONFIG_ARCH_MULTI_V5=y # CONFIG_ARCH_MULTI_V6 is not set # CONFIG_ARCH_MULTI_V7 is not set CONFIG_ARCH_MV78XX0=y -CONFIG_MACH_DB78X00_BP=y -CONFIG_MACH_RD78X00_MASA=y CONFIG_MACH_TERASTATION_WXL=y CONFIG_AEABI=y CONFIG_HIGHMEM=y CONFIG_FPE_NWFPE=y -CONFIG_UNUSED_BOARD_FILES=y CONFIG_VFP=y CONFIG_KPROBES=y CONFIG_MODULES=y @@ -118,12 +115,12 @@ CONFIG_CRYPTO_CBC=m CONFIG_CRYPTO_ECB=m CONFIG_CRYPTO_PCBC=m # CONFIG_DEBUG_BUGVERBOSE is not set +CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y CONFIG_DEBUG_KERNEL=y # CONFIG_SLUB_DEBUG is not set CONFIG_SCHEDSTATS=y -CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y CONFIG_DEBUG_USER=y CONFIG_DEBUG_LL=y # CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/arm/configs/nhk8815_defconfig b/arch/arm/configs/nhk8815_defconfig index d5881de4201836115986de950114dbeeb3d7da51..4171dafddc0a646e35f969d63828a6e5de4462f0 100644 --- a/arch/arm/configs/nhk8815_defconfig +++ b/arch/arm/configs/nhk8815_defconfig @@ -131,9 +131,9 @@ CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=y +CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_MD5=y CONFIG_CRYPTO_SHA1=y -CONFIG_CRYPTO_DES=y # CONFIG_DEBUG_BUGVERBOSE is not set CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y CONFIG_DEBUG_FS=y diff --git a/arch/arm/configs/omap1_defconfig b/arch/arm/configs/omap1_defconfig index 246f1bba7df52ce61152178bf6d12000b2f46cf6..53dd0717cea5173ba410e4cc0ccea97e875c2f9c 100644 --- a/arch/arm/configs/omap1_defconfig +++ b/arch/arm/configs/omap1_defconfig @@ -20,8 +20,6 @@ CONFIG_ARCH_OMAP=y CONFIG_ARCH_OMAP1=y CONFIG_OMAP_32K_TIMER=y CONFIG_OMAP_DM_TIMER=y -CONFIG_ARCH_OMAP730=y -CONFIG_ARCH_OMAP850=y CONFIG_ARCH_OMAP16XX=y # CONFIG_OMAP_MUX is not set CONFIG_OMAP_RESET_CLOCKS=y diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig index 2a66850d32882bceb75e5bef24007dee0c406161..c4216c5521000f6f92d09290f8477561393cd2e0 100644 --- a/arch/arm/configs/omap2plus_defconfig +++ b/arch/arm/configs/omap2plus_defconfig @@ -53,13 +53,6 @@ CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y CONFIG_KERNEL_MODE_NEON=y CONFIG_PM_DEBUG=y -CONFIG_CRYPTO_SHA1_ARM_NEON=m -CONFIG_CRYPTO_SHA256_ARM=m -CONFIG_CRYPTO_SHA512_ARM=m -CONFIG_CRYPTO_AES_ARM=m -CONFIG_CRYPTO_AES_ARM_BS=m -CONFIG_CRYPTO_GHASH_ARM_CE=m -CONFIG_CRYPTO_CHACHA20_NEON=m CONFIG_KPROBES=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y @@ -707,6 +700,13 @@ CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_ISO8859_1=y CONFIG_SECURITY=y CONFIG_CRYPTO_MICHAEL_MIC=y +CONFIG_CRYPTO_GHASH_ARM_CE=m +CONFIG_CRYPTO_SHA1_ARM_NEON=m +CONFIG_CRYPTO_SHA256_ARM=m +CONFIG_CRYPTO_SHA512_ARM=m +CONFIG_CRYPTO_AES_ARM=m +CONFIG_CRYPTO_AES_ARM_BS=m +CONFIG_CRYPTO_CHACHA20_NEON=m CONFIG_CRYPTO_DEV_OMAP=m CONFIG_CRYPTO_DEV_OMAP_SHAM=m CONFIG_CRYPTO_DEV_OMAP_AES=m diff --git a/arch/arm/configs/palmz72_defconfig b/arch/arm/configs/palmz72_defconfig deleted file mode 100644 index a9a808bc2f7040f58104a5d249e7ebf1de37eab0..0000000000000000000000000000000000000000 --- a/arch/arm/configs/palmz72_defconfig +++ /dev/null @@ -1,75 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_PREEMPT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_BLK_DEV_INITRD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_PXA=y -CONFIG_ARCH_PXA_PALM=y -# CONFIG_MACH_PALMTX is not set -CONFIG_AEABI=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="mem=32M console=tty root=/dev/mmcblk0" -CONFIG_FPE_NWFPE=y -CONFIG_PM=y -CONFIG_APM_EMULATION=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_SLAB=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_IPV6 is not set -CONFIG_BLK_DEV_LOOP=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_EVDEV=y -# CONFIG_KEYBOARD_ATKBD is not set -CONFIG_KEYBOARD_PXA27x=y -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_PXA=y -CONFIG_SPI=y -CONFIG_SPI_SPIDEV=y -CONFIG_GPIO_SYSFS=y -CONFIG_POWER_SUPPLY=y -CONFIG_PDA_POWER=y -# CONFIG_HWMON is not set -CONFIG_FB=y -CONFIG_FB_PXA=y -# CONFIG_LCD_CLASS_DEVICE is not set -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_BACKLIGHT_PWM=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -# CONFIG_USB_SUPPORT is not set -CONFIG_MMC=y -CONFIG_MMC_DEBUG=y -CONFIG_MMC_PXA=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_PXA=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_DNOTIFY is not set -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_CODEPAGE=866 -CONFIG_FAT_DEFAULT_IOCHARSET="utf8" -CONFIG_TMPFS=y -# CONFIG_NETWORK_FILESYSTEMS is not set -CONFIG_NLS_DEFAULT="utf8" -CONFIG_NLS_CODEPAGE_866=y -CONFIG_NLS_UTF8=y -CONFIG_CRC_T10DIF=y -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -CONFIG_DEBUG_USER=y diff --git a/arch/arm/configs/pcm027_defconfig b/arch/arm/configs/pcm027_defconfig deleted file mode 100644 index a392312a13ce288b9ccf04e7a5dde5eab0652495..0000000000000000000000000000000000000000 --- a/arch/arm/configs/pcm027_defconfig +++ /dev/null @@ -1,90 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_NO_HZ_IDLE=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_PREEMPT=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set -CONFIG_EXPERT=y -# CONFIG_KALLSYMS is not set -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_PXA=y -CONFIG_MACH_PCM027=y -CONFIG_MACH_PCM990_BASEBOARD=y -CONFIG_AEABI=y -# CONFIG_OABI_COMPAT is not set -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_PARTITION_ADVANCED=y -# CONFIG_SWAP is not set -CONFIG_SLAB=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_PHYSMAP=y -# CONFIG_BLK_DEV is not set -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_SCSI_LOWLEVEL is not set -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_PXA=y -CONFIG_SERIAL_PXA_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_PXA=y -# CONFIG_HWMON is not set -# CONFIG_VGA_CONSOLE is not set -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_PXA2XX_AC97=y -CONFIG_USB=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_STORAGE=y -CONFIG_MMC=y -CONFIG_MMC_PXA=y -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_PCF8563=m -CONFIG_RTC_DRV_PXA=m -CONFIG_EXT2_FS=m -CONFIG_EXT3_FS=m -# CONFIG_DNOTIFY is not set -CONFIG_VFAT_FS=m -CONFIG_FAT_DEFAULT_CODEPAGE=850 -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15" -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_DEFAULT="iso8859-15" -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_ISO8859_15=y -CONFIG_MAGIC_SYSRQ=y diff --git a/arch/arm/configs/pleb_defconfig b/arch/arm/configs/pleb_defconfig deleted file mode 100644 index fd26678732736fbeef7242b8305b4b981f1aa3d9..0000000000000000000000000000000000000000 --- a/arch/arm/configs/pleb_defconfig +++ /dev/null @@ -1,53 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_HOTPLUG is not set -# CONFIG_SHMEM is not set -CONFIG_ARCH_MULTI_V4=y -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_SA1100=y -CONFIG_SA1100_PLEB=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="console=ttySA0,9600 mem=16M@0xc0000000 mem=16M@0xc8000000 root=/dev/ram initrd=0xc0400000,4M" -CONFIG_CPU_FREQ_DEFAULT_GOV_PERFORMANCE=y -CONFIG_CPU_FREQ_GOV_ONDEMAND=y -CONFIG_FPE_NWFPE=y -CONFIG_MODULES=y -# CONFIG_SWAP is not set -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_SYN_COOKIES=y -# CONFIG_IPV6 is not set -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_SA1100=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=y -# CONFIG_INPUT is not set -# CONFIG_SERIO is not set -# CONFIG_VT is not set -CONFIG_SERIAL_SA1100=y -CONFIG_SERIAL_SA1100_CONSOLE=y -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_DNOTIFY is not set -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_NLS=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y diff --git a/arch/arm/configs/pxa168_defconfig b/arch/arm/configs/pxa168_defconfig index 826ebbef2e3c6483885f0d52f99175882edbf2de..8422ddc9bab236299a9f0425abcfbefde4851c90 100644 --- a/arch/arm/configs/pxa168_defconfig +++ b/arch/arm/configs/pxa168_defconfig @@ -1,9 +1,6 @@ CONFIG_SYSVIPC=y CONFIG_SYSFS_DEPRECATED_V2=y # CONFIG_BLK_DEV_BSG is not set -CONFIG_MACH_ASPENITE=y -CONFIG_MACH_ZYLONITE2=y -CONFIG_MACH_AVENGERS_LITE=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y CONFIG_PREEMPT=y diff --git a/arch/arm/configs/pxa255-idp_defconfig b/arch/arm/configs/pxa255-idp_defconfig deleted file mode 100644 index ae0444949a87e52733acd7f1241ef0f0c97de0fd..0000000000000000000000000000000000000000 --- a/arch/arm/configs/pxa255-idp_defconfig +++ /dev/null @@ -1,55 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_PXA=y -CONFIG_ARCH_PXA_IDP=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="root=/dev/nfs ip=dhcp console=ttyS0,115200 mem=64M" -CONFIG_FPE_NWFPE=y -CONFIG_MODULES=y -CONFIG_NET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -# CONFIG_IPV6 is not set -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -# CONFIG_MTD_MAP_BANK_WIDTH_1 is not set -# CONFIG_MTD_MAP_BANK_WIDTH_2 is not set -# CONFIG_MTD_CFI_I1 is not set -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=y -CONFIG_INPUT_EVDEV=y -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO_SERPORT is not set -CONFIG_SERIAL_PXA=y -CONFIG_SERIAL_PXA_CONSOLE=y -CONFIG_FB=y -CONFIG_FB_PXA=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_CPU=y -CONFIG_EXT2_FS=y -CONFIG_MSDOS_FS=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=y -CONFIG_ROOT_NFS=y -CONFIG_NLS_ISO8859_1=y -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/pxa910_defconfig b/arch/arm/configs/pxa910_defconfig index 353008de567832f7a2a54baaac87540cf601c1bf..48e41ca582afe458728242c6a062ad86c657f4e7 100644 --- a/arch/arm/configs/pxa910_defconfig +++ b/arch/arm/configs/pxa910_defconfig @@ -11,8 +11,6 @@ CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_BLK_DEV_BSG is not set -CONFIG_MACH_TAVOREVB=y -CONFIG_MACH_TTC_DKB=y CONFIG_AEABI=y CONFIG_FPE_NWFPE=y CONFIG_SLAB=y diff --git a/arch/arm/configs/pxa_defconfig b/arch/arm/configs/pxa_defconfig index 0a0f12df40b56492a54a3e18ad05c7ad6f8de925..e656d3af22666382ddbbfbb3d44c1aa5f72b3e75 100644 --- a/arch/arm/configs/pxa_defconfig +++ b/arch/arm/configs/pxa_defconfig @@ -19,7 +19,6 @@ CONFIG_ARCH_GUMSTIX=y CONFIG_PXA_SHARPSL=y CONFIG_MACH_AKITA=y CONFIG_MACH_BORZOI=y -CONFIG_PXA_SYSTEMS_CPLDS=y CONFIG_AEABI=y CONFIG_ARCH_FORCE_MAX_ORDER=9 CONFIG_CMDLINE="root=/dev/ram0 ro" @@ -34,10 +33,6 @@ CONFIG_CPUFREQ_DT=m CONFIG_ARM_PXA2xx_CPUFREQ=m CONFIG_CPU_IDLE=y CONFIG_ARM_CPUIDLE=y -CONFIG_CRYPTO_SHA1_ARM=m -CONFIG_CRYPTO_SHA256_ARM=m -CONFIG_CRYPTO_SHA512_ARM=m -CONFIG_CRYPTO_AES_ARM=m CONFIG_KPROBES=y CONFIG_MODULES=y CONFIG_MODULE_FORCE_LOAD=y @@ -397,9 +392,7 @@ CONFIG_FB_VIRTUAL=m CONFIG_FB_SIMPLE=y CONFIG_LCD_CORGI=m CONFIG_LCD_PLATFORM=m -CONFIG_LCD_TOSA=m CONFIG_BACKLIGHT_PWM=m -CONFIG_BACKLIGHT_TOSA=m CONFIG_FRAMEBUFFER_CONSOLE=y CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y CONFIG_LOGO=y @@ -652,15 +645,6 @@ CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_CRYPTD=m CONFIG_CRYPTO_AUTHENC=m CONFIG_CRYPTO_TEST=m -CONFIG_CRYPTO_LRW=m -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_XTS=m -CONFIG_CRYPTO_XCBC=m -CONFIG_CRYPTO_VMAC=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_TGR192=m -CONFIG_CRYPTO_WP512=m -CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_BLOWFISH=m CONFIG_CRYPTO_CAST5=m CONFIG_CRYPTO_CAST6=m @@ -670,8 +654,21 @@ CONFIG_CRYPTO_SEED=m CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_TEA=m CONFIG_CRYPTO_TWOFISH=m +CONFIG_CRYPTO_LRW=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_XTS=m +CONFIG_CRYPTO_VMAC=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_TGR192=m +CONFIG_CRYPTO_WP512=m +CONFIG_CRYPTO_ANUBIS=m +CONFIG_CRYPTO_XCBC=m CONFIG_CRYPTO_DEFLATE=y CONFIG_CRYPTO_LZO=y +CONFIG_CRYPTO_SHA1_ARM=m +CONFIG_CRYPTO_SHA256_ARM=m +CONFIG_CRYPTO_SHA512_ARM=m +CONFIG_CRYPTO_AES_ARM=m CONFIG_CRC_CCITT=y CONFIG_CRC_T10DIF=m CONFIG_FONTS=y diff --git a/arch/arm/configs/qcom_defconfig b/arch/arm/configs/qcom_defconfig index b41716c1ec645343c0ff95f9501cfccfc969f26d..ab686b9c2ad8e394fa10e0456c54ffbcfcee0497 100644 --- a/arch/arm/configs/qcom_defconfig +++ b/arch/arm/configs/qcom_defconfig @@ -257,9 +257,9 @@ CONFIG_QCOM_COMMAND_DB=y CONFIG_QCOM_GSBI=y CONFIG_QCOM_OCMEM=y CONFIG_QCOM_PM=y +CONFIG_QCOM_RMTFS_MEM=y CONFIG_QCOM_RPMH=y CONFIG_QCOM_RPMHPD=y -CONFIG_QCOM_RMTFS_MEM=y CONFIG_QCOM_RPMPD=y CONFIG_QCOM_SMEM=y CONFIG_QCOM_SMD_RPM=y diff --git a/arch/arm/configs/s3c2410_defconfig b/arch/arm/configs/s3c2410_defconfig deleted file mode 100644 index 41b40863a78ea2246d4835715740fc459234e09a..0000000000000000000000000000000000000000 --- a/arch/arm/configs/s3c2410_defconfig +++ /dev/null @@ -1,437 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_IKCONFIG=m -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_BLK_DEV_INITRD=y -CONFIG_ARCH_MULTI_V4T=y -CONFIG_ARCH_MULTI_V5=y -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_S3C24XX=y -CONFIG_S3C_ADC=y -CONFIG_CPU_S3C2412=y -CONFIG_CPU_S3C2416=y -CONFIG_CPU_S3C2440=y -CONFIG_CPU_S3C2442=y -CONFIG_CPU_S3C2443=y -CONFIG_MACH_AML_M5900=y -CONFIG_ARCH_BAST=y -CONFIG_ARCH_H1940=y -CONFIG_MACH_N30=y -CONFIG_MACH_OTOM=y -CONFIG_MACH_QT2410=y -CONFIG_ARCH_SMDK2410=y -CONFIG_MACH_TCT_HAMMER=y -CONFIG_MACH_VR1000=y -CONFIG_MACH_JIVE=y -CONFIG_MACH_SMDK2412=y -CONFIG_MACH_VSTMS=y -CONFIG_MACH_SMDK2416=y -CONFIG_MACH_ANUBIS=y -CONFIG_MACH_AT2440EVB=y -CONFIG_MACH_MINI2440=y -CONFIG_MACH_NEXCODER_2440=y -CONFIG_MACH_OSIRIS=y -CONFIG_MACH_OSIRIS_DVS=m -CONFIG_MACH_RX3715=y -CONFIG_ARCH_S3C2440=y -CONFIG_MACH_NEO1973_GTA02=y -CONFIG_MACH_RX1950=y -CONFIG_MACH_SMDK2443=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="root=/dev/hda1 ro init=/bin/bash console=ttySAC0" -CONFIG_FPE_NWFPE=y -CONFIG_FPE_NWFPE_XP=y -CONFIG_APM_EMULATION=m -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_BSD_DISKLABEL=y -CONFIG_SOLARIS_X86_PARTITION=y -CONFIG_SLAB=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=m -CONFIG_NET_KEY=m -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -CONFIG_NET_IPIP=m -CONFIG_INET_AH=m -CONFIG_INET_ESP=m -CONFIG_INET_IPCOMP=m -CONFIG_TCP_CONG_ADVANCED=y -CONFIG_TCP_CONG_HSTCP=m -CONFIG_TCP_CONG_HYBLA=m -CONFIG_TCP_CONG_SCALABLE=m -CONFIG_TCP_CONG_LP=m -CONFIG_TCP_CONG_VENO=m -CONFIG_TCP_CONG_YEAH=m -CONFIG_TCP_CONG_ILLINOIS=m -CONFIG_IPV6_ROUTER_PREF=y -CONFIG_INET6_AH=m -CONFIG_INET6_ESP=m -CONFIG_INET6_IPCOMP=m -CONFIG_IPV6_MIP6=m -CONFIG_IPV6_TUNNEL=m -CONFIG_NETFILTER=y -CONFIG_NF_CONNTRACK=m -CONFIG_NF_CONNTRACK_EVENTS=y -CONFIG_NF_CONNTRACK_AMANDA=m -CONFIG_NF_CONNTRACK_FTP=m -CONFIG_NF_CONNTRACK_H323=m -CONFIG_NF_CONNTRACK_IRC=m -CONFIG_NF_CONNTRACK_NETBIOS_NS=m -CONFIG_NF_CONNTRACK_PPTP=m -CONFIG_NF_CONNTRACK_SANE=m -CONFIG_NF_CONNTRACK_SIP=m -CONFIG_NF_CONNTRACK_TFTP=m -CONFIG_NF_CT_NETLINK=m -CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -CONFIG_NETFILTER_XT_TARGET_LED=m -CONFIG_NETFILTER_XT_TARGET_LOG=m -CONFIG_NETFILTER_XT_TARGET_MARK=m -CONFIG_NETFILTER_XT_TARGET_NFLOG=m -CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_CLUSTER=m -CONFIG_NETFILTER_XT_MATCH_COMMENT=m -CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -CONFIG_NETFILTER_XT_MATCH_DCCP=m -CONFIG_NETFILTER_XT_MATCH_DSCP=m -CONFIG_NETFILTER_XT_MATCH_ESP=m -CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -CONFIG_NETFILTER_XT_MATCH_HELPER=m -CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -CONFIG_NETFILTER_XT_MATCH_LENGTH=m -CONFIG_NETFILTER_XT_MATCH_LIMIT=m -CONFIG_NETFILTER_XT_MATCH_MAC=m -CONFIG_NETFILTER_XT_MATCH_MARK=m -CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -CONFIG_NETFILTER_XT_MATCH_OWNER=m -CONFIG_NETFILTER_XT_MATCH_POLICY=m -CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -CONFIG_NETFILTER_XT_MATCH_QUOTA=m -CONFIG_NETFILTER_XT_MATCH_RATEEST=m -CONFIG_NETFILTER_XT_MATCH_REALM=m -CONFIG_NETFILTER_XT_MATCH_RECENT=m -CONFIG_NETFILTER_XT_MATCH_SCTP=m -CONFIG_NETFILTER_XT_MATCH_STATE=m -CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -CONFIG_NETFILTER_XT_MATCH_STRING=m -CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -CONFIG_NETFILTER_XT_MATCH_TIME=m -CONFIG_NETFILTER_XT_MATCH_U32=m -CONFIG_IP_VS=m -CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_MATCH_AH=m -CONFIG_IP_NF_MATCH_ECN=m -CONFIG_IP_NF_MATCH_TTL=m -CONFIG_IP_NF_FILTER=m -CONFIG_IP_NF_TARGET_REJECT=m -CONFIG_IP_NF_NAT=m -CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_TARGET_NETMAP=m -CONFIG_IP_NF_TARGET_REDIRECT=m -CONFIG_IP_NF_MANGLE=m -CONFIG_IP_NF_TARGET_CLUSTERIP=m -CONFIG_IP_NF_TARGET_ECN=m -CONFIG_IP_NF_TARGET_TTL=m -CONFIG_IP_NF_RAW=m -CONFIG_IP_NF_ARPTABLES=m -CONFIG_IP_NF_ARPFILTER=m -CONFIG_IP_NF_ARP_MANGLE=m -CONFIG_IP6_NF_IPTABLES=m -CONFIG_IP6_NF_MATCH_AH=m -CONFIG_IP6_NF_MATCH_EUI64=m -CONFIG_IP6_NF_MATCH_FRAG=m -CONFIG_IP6_NF_MATCH_OPTS=m -CONFIG_IP6_NF_MATCH_HL=m -CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_MATCH_MH=m -CONFIG_IP6_NF_MATCH_RT=m -CONFIG_IP6_NF_TARGET_HL=m -CONFIG_IP6_NF_FILTER=m -CONFIG_IP6_NF_TARGET_REJECT=m -CONFIG_IP6_NF_MANGLE=m -CONFIG_IP6_NF_RAW=m -CONFIG_BT=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_BCSP=y -CONFIG_BT_HCIUART_LL=y -CONFIG_BT_HCIBCM203X=m -CONFIG_BT_HCIBPA10X=m -CONFIG_BT_HCIBFUSB=m -CONFIG_BT_HCIVHCI=m -CONFIG_CFG80211=m -CONFIG_MAC80211=m -CONFIG_MAC80211_MESH=y -CONFIG_MAC80211_LEDS=y -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_ROM=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_NAND_S3C2410=y -CONFIG_PARPORT=y -CONFIG_PARPORT_PC=m -CONFIG_PARPORT_AX88796=m -CONFIG_PARPORT_1284=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_NBD=m -CONFIG_BLK_DEV_RAM=y -CONFIG_ATA_OVER_ETH=m -CONFIG_EEPROM_AT24=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_ST=m -CONFIG_BLK_DEV_SR=y -CONFIG_CHR_DEV_SG=y -# CONFIG_BLK_DEV_BSG is not set -CONFIG_CHR_DEV_SCH=m -CONFIG_SCSI_CONSTANTS=y -CONFIG_SCSI_SCAN_ASYNC=y -CONFIG_ATA=y -CONFIG_PATA_PLATFORM=y -CONFIG_NETDEVICES=y -CONFIG_DM9000=y -CONFIG_INPUT_EVDEV=y -CONFIG_MOUSE_APPLETOUCH=m -CONFIG_MOUSE_BCM5974=m -CONFIG_INPUT_JOYSTICK=y -CONFIG_JOYSTICK_ANALOG=m -CONFIG_JOYSTICK_A3D=m -CONFIG_JOYSTICK_ADI=m -CONFIG_JOYSTICK_COBRA=m -CONFIG_JOYSTICK_GF2K=m -CONFIG_JOYSTICK_GRIP=m -CONFIG_JOYSTICK_GRIP_MP=m -CONFIG_JOYSTICK_GUILLEMOT=m -CONFIG_JOYSTICK_INTERACT=m -CONFIG_JOYSTICK_SIDEWINDER=m -CONFIG_JOYSTICK_TMDC=m -CONFIG_JOYSTICK_IFORCE=m -CONFIG_JOYSTICK_MAGELLAN=m -CONFIG_JOYSTICK_SPACEORB=m -CONFIG_JOYSTICK_SPACEBALL=m -CONFIG_JOYSTICK_STINGER=m -CONFIG_JOYSTICK_TWIDJOY=m -CONFIG_JOYSTICK_ZHENHUA=m -CONFIG_JOYSTICK_DB9=m -CONFIG_JOYSTICK_GAMECON=m -CONFIG_JOYSTICK_TURBOGRAFX=m -CONFIG_JOYSTICK_JOYDUMP=m -CONFIG_JOYSTICK_XPAD=m -CONFIG_JOYSTICK_XPAD_FF=y -CONFIG_JOYSTICK_XPAD_LEDS=y -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_USB_COMPOSITE=m -CONFIG_INPUT_MISC=y -CONFIG_INPUT_ATI_REMOTE2=m -CONFIG_INPUT_KEYSPAN_REMOTE=m -CONFIG_INPUT_POWERMATE=m -CONFIG_INPUT_YEALINK=m -CONFIG_INPUT_CM109=m -CONFIG_INPUT_UINPUT=m -CONFIG_INPUT_GPIO_ROTARY_ENCODER=m -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=8 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_SHARE_IRQ=y -CONFIG_SERIAL_SAMSUNG=y -CONFIG_SERIAL_SAMSUNG_CONSOLE=y -CONFIG_SERIAL_NONSTANDARD=y -CONFIG_SERIAL_DEV_BUS=m -CONFIG_PRINTER=y -CONFIG_PPDEV=y -CONFIG_HW_RANDOM=y -CONFIG_I2C_CHARDEV=m -CONFIG_I2C_S3C2410=y -CONFIG_I2C_SIMTEC=y -CONFIG_SPI=y -CONFIG_SPI_GPIO=m -CONFIG_SPI_S3C24XX=m -CONFIG_SPI_SPIDEV=m -CONFIG_SPI_TLE62X0=m -CONFIG_SENSORS_LM75=m -CONFIG_SENSORS_LM78=m -CONFIG_SENSORS_LM85=m -CONFIG_WATCHDOG=y -CONFIG_S3C2410_WATCHDOG=y -CONFIG_MFD_SM501=y -CONFIG_TPS65010=y -CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y -CONFIG_FB_MODE_HELPERS=y -CONFIG_FB_S3C2410=y -CONFIG_FB_SM501=y -CONFIG_BACKLIGHT_PWM=m -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_VERBOSE_PRINTK=y -CONFIG_SND_SEQUENCER=m -# CONFIG_SND_DRIVERS is not set -# CONFIG_SND_ARM is not set -# CONFIG_SND_SPI is not set -CONFIG_SND_USB_AUDIO=m -CONFIG_SND_USB_CAIAQ=m -CONFIG_SND_SOC=y -# CONFIG_USB_HID is not set -CONFIG_USB=y -CONFIG_USB_MON=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_ACM=m -CONFIG_USB_PRINTER=m -CONFIG_USB_WDM=m -CONFIG_USB_STORAGE=m -CONFIG_USB_STORAGE_DATAFAB=m -CONFIG_USB_STORAGE_FREECOM=m -CONFIG_USB_STORAGE_ISD200=m -CONFIG_USB_STORAGE_USBAT=m -CONFIG_USB_STORAGE_SDDR09=m -CONFIG_USB_STORAGE_SDDR55=m -CONFIG_USB_STORAGE_JUMPSHOT=m -CONFIG_USB_STORAGE_ALAUDA=m -CONFIG_USB_STORAGE_ONETOUCH=m -CONFIG_USB_STORAGE_KARMA=m -CONFIG_USB_STORAGE_CYPRESS_ATACB=m -CONFIG_USB_MDC800=m -CONFIG_USB_MICROTEK=m -CONFIG_USB_USS720=m -CONFIG_USB_SERIAL=y -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_FTDI_SIO=y -CONFIG_USB_SERIAL_NAVMAN=m -CONFIG_USB_SERIAL_PL2303=y -CONFIG_USB_SERIAL_OPTION=m -CONFIG_USB_EMI62=m -CONFIG_USB_EMI26=m -CONFIG_USB_ADUTUX=m -CONFIG_USB_SEVSEG=m -CONFIG_USB_LEGOTOWER=m -CONFIG_USB_LCD=m -CONFIG_USB_CYPRESS_CY7C63=m -CONFIG_USB_CYTHERM=m -CONFIG_USB_IDMOUSE=m -CONFIG_USB_FTDI_ELAN=m -CONFIG_USB_APPLEDISPLAY=m -CONFIG_USB_LD=m -CONFIG_USB_TRANCEVIBRATOR=m -CONFIG_USB_IOWARRIOR=m -CONFIG_USB_TEST=m -CONFIG_MMC=y -CONFIG_SDIO_UART=m -CONFIG_MMC_TEST=m -CONFIG_MMC_SDHCI=m -CONFIG_MMC_SPI=m -CONFIG_MMC_S3C=y -CONFIG_LEDS_S3C24XX=m -CONFIG_LEDS_PCA9532=m -CONFIG_LEDS_GPIO=m -CONFIG_LEDS_PCA955X=m -CONFIG_LEDS_DAC124S085=m -CONFIG_LEDS_PWM=m -CONFIG_LEDS_BD2802=m -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_HEARTBEAT=m -CONFIG_LEDS_TRIGGER_GPIO=m -CONFIG_LEDS_TRIGGER_DEFAULT_ON=m -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_S3C=y -CONFIG_DMADEVICES=y -CONFIG_S3C24XX_DMAC=y -CONFIG_PWM=y -CONFIG_PWM_SAMSUNG=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_AUTOFS4_FS=m -CONFIG_FUSE_FS=m -CONFIG_ISO9660_FS=y -CONFIG_JOLIET=y -CONFIG_UDF_FS=m -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_NTFS_FS=m -CONFIG_TMPFS=y -CONFIG_TMPFS_POSIX_ACL=y -CONFIG_CONFIGFS_FS=m -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_SUMMARY=y -CONFIG_CRAMFS=y -CONFIG_SQUASHFS=m -CONFIG_ROMFS_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3_ACL=y -CONFIG_ROOT_NFS=y -CONFIG_NFSD=m -CONFIG_NFSD_V3_ACL=y -CONFIG_NFSD_V4=y -CONFIG_CIFS=m -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_737=m -CONFIG_NLS_CODEPAGE_775=m -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_CODEPAGE_852=m -CONFIG_NLS_CODEPAGE_855=m -CONFIG_NLS_CODEPAGE_857=m -CONFIG_NLS_CODEPAGE_860=m -CONFIG_NLS_CODEPAGE_861=m -CONFIG_NLS_CODEPAGE_862=m -CONFIG_NLS_CODEPAGE_863=m -CONFIG_NLS_CODEPAGE_864=m -CONFIG_NLS_CODEPAGE_865=m -CONFIG_NLS_CODEPAGE_866=m -CONFIG_NLS_CODEPAGE_869=m -CONFIG_NLS_CODEPAGE_936=m -CONFIG_NLS_CODEPAGE_950=m -CONFIG_NLS_CODEPAGE_932=m -CONFIG_NLS_CODEPAGE_949=m -CONFIG_NLS_CODEPAGE_874=m -CONFIG_NLS_ISO8859_8=m -CONFIG_NLS_CODEPAGE_1250=m -CONFIG_NLS_CODEPAGE_1251=m -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_2=m -CONFIG_NLS_ISO8859_3=m -CONFIG_NLS_ISO8859_4=m -CONFIG_NLS_ISO8859_5=m -CONFIG_NLS_ISO8859_6=m -CONFIG_NLS_ISO8859_7=m -CONFIG_NLS_ISO8859_9=m -CONFIG_NLS_ISO8859_13=m -CONFIG_NLS_ISO8859_14=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_KOI8_R=m -CONFIG_NLS_KOI8_U=m -CONFIG_NLS_UTF8=m -CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y -CONFIG_DEBUG_KERNEL=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_MUTEXES=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/sama5_defconfig b/arch/arm/configs/sama5_defconfig index f89fd4e0d10a32fe40058b670856958d445d6765..c6aff6fb084d7a2d6eee9dc1bee6acbf12b587e5 100644 --- a/arch/arm/configs/sama5_defconfig +++ b/arch/arm/configs/sama5_defconfig @@ -233,6 +233,7 @@ CONFIG_NLS_CODEPAGE_437=y CONFIG_NLS_CODEPAGE_850=y CONFIG_NLS_ISO8859_1=y CONFIG_NLS_UTF8=y +CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_CBC=y CONFIG_CRYPTO_CFB=y CONFIG_CRYPTO_OFB=y @@ -240,7 +241,6 @@ CONFIG_CRYPTO_XTS=y CONFIG_CRYPTO_HMAC=y CONFIG_CRYPTO_SHA1=y CONFIG_CRYPTO_SHA512=y -CONFIG_CRYPTO_DES=y CONFIG_CRYPTO_USER_API_HASH=m CONFIG_CRYPTO_USER_API_SKCIPHER=m CONFIG_CRYPTO_DEV_ATMEL_AES=y diff --git a/arch/arm/configs/shannon_defconfig b/arch/arm/configs/shannon_defconfig deleted file mode 100644 index dfcea70b8034f8c6fde51ea93e1278929ba44e23..0000000000000000000000000000000000000000 --- a/arch/arm/configs/shannon_defconfig +++ /dev/null @@ -1,45 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_ARCH_MULTI_V4=y -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_SA1100=y -CONFIG_SA1100_SHANNON=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="console=ttySA0,9600 console=tty1 root=/dev/mtdblock2 init=/linuxrc" -CONFIG_FPE_NWFPE=y -CONFIG_MODULES=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -# CONFIG_IPV6 is not set -CONFIG_PCCARD=y -CONFIG_PCMCIA_SA1100=y -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_SA1100=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_NET_PCMCIA=y -CONFIG_PCMCIA_PCNET=y -CONFIG_PCMCIA_SMC91C92=y -CONFIG_SERIAL_SA1100=y -CONFIG_SERIAL_SA1100_CONSOLE=y -CONFIG_WATCHDOG=y -CONFIG_SA1100_WATCHDOG=y -CONFIG_FB=y -CONFIG_FB_SA1100=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_SOUND=y -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -CONFIG_JFFS2_FS=y -CONFIG_MINIX_FS=y -CONFIG_NFS_FS=y -CONFIG_DEBUG_USER=y diff --git a/arch/arm/configs/shmobile_defconfig b/arch/arm/configs/shmobile_defconfig index 452aef74cc5c1256128554802ab26139c2f3b60f..751d939fcb761b31d4a434d8e07ed269aa43a575 100644 --- a/arch/arm/configs/shmobile_defconfig +++ b/arch/arm/configs/shmobile_defconfig @@ -136,6 +136,7 @@ CONFIG_VIDEO_ADV7604_CEC=y CONFIG_VIDEO_ML86V7667=y CONFIG_DRM=y CONFIG_DRM_RCAR_DU=y +# CONFIG_DRM_RCAR_USE_MIPI_DSI is not set CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_EDP=y CONFIG_DRM_DISPLAY_CONNECTOR=y diff --git a/arch/arm/configs/simpad_defconfig b/arch/arm/configs/simpad_defconfig deleted file mode 100644 index 4e00a4c2c28788f5d43e0a5290a2c235a6f8d5c9..0000000000000000000000000000000000000000 --- a/arch/arm/configs/simpad_defconfig +++ /dev/null @@ -1,100 +0,0 @@ -CONFIG_LOCALVERSION="oe1" -CONFIG_SYSVIPC=y -CONFIG_PREEMPT=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_EXPERT=y -CONFIG_KALLSYMS_ALL=y -CONFIG_KALLSYMS_EXTRA_PASS=y -CONFIG_ARCH_MULTI_V4=y -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_SA1100=y -CONFIG_SA1100_SIMPAD=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="mtdparts=sa1100:512k(boot),1m(kernel),-(root) console=ttySA0 root=1f02 noinitrd mem=64M jffs2_orphaned_inodes=delete rootfstype=jffs2" -CONFIG_FPE_NWFPE=y -CONFIG_MODULES=y -CONFIG_BINFMT_MISC=m -CONFIG_PM=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IPV6 is not set -CONFIG_BT=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_PCCARD=y -CONFIG_PCMCIA_SA1100=y -CONFIG_MTD=y -CONFIG_MTD_CMDLINE_PARTS=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -# CONFIG_MTD_CFI_I2 is not set -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_RAM=y -CONFIG_MTD_SA1100=y -CONFIG_BLK_DEV_LOOP=m -CONFIG_BLK_DEV_RAM=m -CONFIG_BLK_DEV_RAM_SIZE=8192 -CONFIG_NETDEVICES=y -CONFIG_DUMMY=y -CONFIG_NET_ETHERNET=y -CONFIG_NET_PCI=y -CONFIG_NET_PCMCIA=y -CONFIG_PCMCIA_3C574=m -CONFIG_PCMCIA_3C589=m -CONFIG_PCMCIA_PCNET=m -CONFIG_PCMCIA_SMC91C92=m -CONFIG_PCMCIA_XIRC2PS=m -CONFIG_PPP=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_MULTILINK=y -CONFIG_PPPOE=m -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_INPUT_MOUSEDEV_SCREEN_X=800 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=600 -CONFIG_INPUT_EVDEV=m -CONFIG_INPUT_EVBUG=y -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_SERIO=m -CONFIG_SERIAL_SA1100=y -CONFIG_SERIAL_SA1100_CONSOLE=y -CONFIG_FB=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -CONFIG_SOUND=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=y -CONFIG_EXT2_FS=m -CONFIG_EXT3_FS=m -CONFIG_REISERFS_FS=m -CONFIG_REISERFS_PROC_INFO=y -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_JFFS2_FS=y -CONFIG_CRAMFS=m -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_SMB_FS=m -CONFIG_NLS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_ISO8859_1=y -CONFIG_NLS_ISO8859_15=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_USER=y -CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/spitz_defconfig b/arch/arm/configs/spitz_defconfig index 66d74653f3fbaa397c68a8f051279e47b816e4d2..10108b4a978e9c57133b67d1c0fb01b16b18ba4b 100644 --- a/arch/arm/configs/spitz_defconfig +++ b/arch/arm/configs/spitz_defconfig @@ -219,12 +219,7 @@ CONFIG_DEBUG_KERNEL=y CONFIG_CRYPTO_NULL=m CONFIG_CRYPTO_TEST=m CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_HMAC=y -CONFIG_CRYPTO_MD4=m -CONFIG_CRYPTO_MICHAEL_MIC=m CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_WP512=m CONFIG_CRYPTO_AES=m CONFIG_CRYPTO_ANUBIS=m CONFIG_CRYPTO_ARC4=m @@ -236,6 +231,11 @@ CONFIG_CRYPTO_SERPENT=m CONFIG_CRYPTO_TEA=m CONFIG_CRYPTO_TWOFISH=m # CONFIG_CRYPTO_ANSI_CPRNG is not set +CONFIG_CRYPTO_HMAC=y +CONFIG_CRYPTO_MD4=m +CONFIG_CRYPTO_MICHAEL_MIC=m +CONFIG_CRYPTO_SHA512=m +CONFIG_CRYPTO_WP512=m CONFIG_CRC_CCITT=y CONFIG_LIBCRC32C=m CONFIG_FONTS=y diff --git a/arch/arm/configs/tct_hammer_defconfig b/arch/arm/configs/tct_hammer_defconfig deleted file mode 100644 index 6bd38b6f22c411089e3d12053bdc4b22f77d3b95..0000000000000000000000000000000000000000 --- a/arch/arm/configs/tct_hammer_defconfig +++ /dev/null @@ -1,59 +0,0 @@ -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_SYSFS_DEPRECATED=y -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_ELF_CORE is not set -# CONFIG_SHMEM is not set -# CONFIG_BLK_DEV_BSG is not set -# CONFIG_KALLSYMS is not set -CONFIG_ARCH_MULTI_V4T=y -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_S3C24XX=y -CONFIG_MACH_TCT_HAMMER=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="mem=64M root=/dev/ram0 init=/linuxrc rw" -CONFIG_FPE_NWFPE=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -# CONFIG_SWAP is not set -CONFIG_SLUB=y -CONFIG_SLUB_TINY=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -CONFIG_MTD=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_PHYSMAP=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_SIZE=10240 -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_VT_CONSOLE is not set -# CONFIG_HW_RANDOM is not set -# CONFIG_HWMON is not set -CONFIG_USB=y -CONFIG_USB_MON=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_GADGET=y -CONFIG_USB_S3C2410=y -CONFIG_USB_ETH=m -CONFIG_EXT2_FS=y -# CONFIG_DNOTIFY is not set -CONFIG_MSDOS_FS=y -CONFIG_VFAT_FS=y -# CONFIG_PROC_SYSCTL is not set -CONFIG_JFFS2_FS=y -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_ISO8859_1=y -# CONFIG_ENABLE_MUST_CHECK is not set -CONFIG_CRC_CCITT=y -CONFIG_DEBUG_LL=y diff --git a/arch/arm/configs/trizeps4_defconfig b/arch/arm/configs/trizeps4_defconfig deleted file mode 100644 index 009abe1e49ef6e7f264fdadf0b1f455833c086f5..0000000000000000000000000000000000000000 --- a/arch/arm/configs/trizeps4_defconfig +++ /dev/null @@ -1,207 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_POSIX_MQUEUE=y -CONFIG_PREEMPT=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_BSD_PROCESS_ACCT_V3=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=14 -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -CONFIG_KALLSYMS_EXTRA_PASS=y -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_PXA=y -CONFIG_TRIZEPS_PXA=y -CONFIG_MACH_TRIZEPS4=y -CONFIG_AEABI=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="root=fe01 console=ttyS0,38400n8 loglevel=5" -CONFIG_FPE_NWFPE=y -CONFIG_FPE_NWFPE_XP=y -CONFIG_PM=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_FORCE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_LDM_PARTITION=y -CONFIG_SLAB=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_XFRM_USER=m -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_IPV6 is not set -CONFIG_NETFILTER=y -CONFIG_VLAN_8021Q=m -CONFIG_BT=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_BNEP_MC_FILTER=y -CONFIG_BT_BNEP_PROTO_FILTER=y -CONFIG_BT_HIDP=m -CONFIG_CFG80211=y -CONFIG_PCCARD=y -# CONFIG_PCMCIA_LOAD_CIS is not set -CONFIG_PCMCIA_PXA2XX=y -CONFIG_CONNECTOR=y -CONFIG_MTD=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_PARTS_UNALLOCATED=y -CONFIG_MTD_REDBOOT_PARTS_READONLY=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_LE_BYTE_SWAP=y -CONFIG_MTD_CFI_GEOMETRY=y -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_BLOCK2MTD=y -CONFIG_MTD_DOC2000=y -CONFIG_MTD_DOC2001=y -CONFIG_MTD_DOC2001PLUS=y -CONFIG_MTD_DOCPROBE_ADVANCED=y -CONFIG_MTD_DOCPROBE_ADDRESS=0x4000000 -CONFIG_MTD_DOCPROBE_HIGH=y -CONFIG_MTD_ONENAND=y -CONFIG_MTD_RAW_NAND=y -CONFIG_MTD_NAND_DISKONCHIP=y -CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADVANCED=y -CONFIG_MTD_NAND_DISKONCHIP_PROBE_ADDRESS=0x4000000 -CONFIG_MTD_NAND_DISKONCHIP_PROBE_HIGH=y -CONFIG_MTD_NAND_DISKONCHIP_BBTWRITE=y -CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_CRYPTOLOOP=m -CONFIG_BLK_DEV_NBD=y -CONFIG_BLK_DEV_RAM=y -CONFIG_BLK_DEV_RAM_COUNT=8 -CONFIG_SCSI=y -CONFIG_BLK_DEV_SD=y -CONFIG_CHR_DEV_SG=y -CONFIG_SCSI_MULTI_LUN=y -CONFIG_ATA=m -CONFIG_PATA_PCMCIA=m -CONFIG_PATA_PLATFORM=m -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_DM9000=y -CONFIG_PHYLIB=y -CONFIG_PPP=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_FILTER=y -CONFIG_PPP_MPPE=m -CONFIG_PPP_MULTILINK=y -CONFIG_PPP_ASYNC=m -CONFIG_PPP_SYNC_TTY=m -CONFIG_HOSTAP=y -CONFIG_HOSTAP_FIRMWARE=y -CONFIG_HOSTAP_FIRMWARE_NVRAM=y -CONFIG_HOSTAP_CS=y -CONFIG_HERMES=y -CONFIG_PCMCIA_HERMES=y -CONFIG_PCMCIA_SPECTRUM=y -CONFIG_INPUT_MOUSEDEV_SCREEN_X=640 -CONFIG_INPUT_MOUSEDEV_SCREEN_Y=480 -CONFIG_INPUT_EVDEV=y -CONFIG_KEYBOARD_ATKBD=m -# CONFIG_MOUSE_PS2 is not set -CONFIG_MOUSE_SERIAL=m -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_INPUT_MISC=y -CONFIG_INPUT_UINPUT=m -CONFIG_SERIO_LIBPS2=y -CONFIG_SERIAL_PXA=y -CONFIG_SERIAL_PXA_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -CONFIG_I2C_PXA=y -CONFIG_I2C_PXA_SLAVE=y -CONFIG_WATCHDOG=y -CONFIG_SA1100_WATCHDOG=y -CONFIG_FB=y -CONFIG_FIRMWARE_EDID=y -CONFIG_FB_PXA=y -CONFIG_LCD_CLASS_DEVICE=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -CONFIG_LOGO=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_MIXER_OSS=y -CONFIG_SND_PCM_OSS=y -CONFIG_SND_VERBOSE_PRINTK=y -CONFIG_SND_DEBUG=y -CONFIG_SND_SEQUENCER=y -CONFIG_SND_PXA2XX_AC97=y -CONFIG_SND_USB_AUDIO=m -# CONFIG_USB_HID is not set -CONFIG_USB=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_STORAGE=m -CONFIG_USB_SERIAL=m -CONFIG_USB_GADGET=m -CONFIG_USB_GADGET_DUMMY_HCD=y -CONFIG_MMC=y -CONFIG_MMC_PXA=y -CONFIG_NEW_LEDS=y -CONFIG_RTC_CLASS=y -# CONFIG_RTC_HCTOSYS is not set -CONFIG_RTC_DRV_PCF8583=m -CONFIG_RTC_DRV_PXA=y -CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_XATTR=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT2_FS_SECURITY=y -CONFIG_EXT3_FS=y -CONFIG_EXT3_FS_POSIX_ACL=y -CONFIG_EXT3_FS_SECURITY=y -CONFIG_AUTOFS4_FS=y -CONFIG_MSDOS_FS=m -CONFIG_VFAT_FS=m -CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-15" -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_COMPRESSION_OPTIONS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_NFS_V4=y -CONFIG_ROOT_NFS=y -CONFIG_NFSD=y -CONFIG_NFSD_V4=y -CONFIG_SMB_FS=m -CONFIG_CIFS=m -CONFIG_NLS_DEFAULT="iso8859-15" -CONFIG_NLS_CODEPAGE_437=y -CONFIG_NLS_CODEPAGE_850=y -CONFIG_NLS_ASCII=y -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_UTF8=m -CONFIG_KEYS=y -CONFIG_SECURITY=y -CONFIG_CRYPTO_PCBC=m -CONFIG_CRYPTO_SHA256=m -CONFIG_CRYPTO_SHA512=m -CONFIG_CRYPTO_DEFLATE=m -CONFIG_CRC_CCITT=y -CONFIG_CRC16=y -CONFIG_LIBCRC32C=y -CONFIG_FONTS=y -CONFIG_FONT_8x8=y -CONFIG_FONT_8x16=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_FS=y -CONFIG_DEBUG_USER=y diff --git a/arch/arm/configs/viper_defconfig b/arch/arm/configs/viper_defconfig deleted file mode 100644 index 02f9849893b2561216a15676b947b60d85792294..0000000000000000000000000000000000000000 --- a/arch/arm/configs/viper_defconfig +++ /dev/null @@ -1,160 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_LOG_BUF_SHIFT=13 -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_EXPERT=y -# CONFIG_ELF_CORE is not set -# CONFIG_SHMEM is not set -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_PXA=y -CONFIG_ARCH_VIPER=y -CONFIG_IWMMXT=y -CONFIG_AEABI=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="root=31:02 rootfstype=jffs2 ro console=ttyS0,115200" -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=m -CONFIG_CPU_FREQ_GOV_USERSPACE=m -CONFIG_CPU_FREQ_GOV_ONDEMAND=m -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m -CONFIG_FPE_FASTFPE=y -CONFIG_PM=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_PARTITION_ADVANCED=y -# CONFIG_SWAP is not set -CONFIG_SLAB=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_SYN_COOKIES=y -# CONFIG_IPV6 is not set -CONFIG_BT=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCSP=y -CONFIG_PCCARD=m -CONFIG_PCMCIA_PXA2XX=m -CONFIG_FW_LOADER=m -CONFIG_MTD=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_DIRECTORY_BLOCK=0 -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set -# CONFIG_MTD_CFI_I2 is not set -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_RAM=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PXA2XX=y -CONFIG_BLK_DEV_LOOP=m -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=m -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ATA=m -# CONFIG_SATA_PMP is not set -CONFIG_PATA_PCMCIA=m -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_SMC91X=y -CONFIG_PPP=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_ASYNC=m -CONFIG_USB_PEGASUS=m -CONFIG_USB_USBNET=m -# CONFIG_USB_NET_CDC_SUBSET is not set -CONFIG_NET_PCMCIA=y -CONFIG_INPUT_MOUSEDEV=m -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_EVDEV=m -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_FUJITSU=m -CONFIG_TOUCHSCREEN_ELO=m -CONFIG_TOUCHSCREEN_MTOUCH=m -CONFIG_TOUCHSCREEN_INEXIO=m -CONFIG_TOUCHSCREEN_HTCPEN=m -CONFIG_TOUCHSCREEN_PENMOUNT=m -CONFIG_TOUCHSCREEN_TOUCHRIGHT=m -CONFIG_TOUCHSCREEN_TOUCHWIN=m -CONFIG_TOUCHSCREEN_TOUCHIT213=m -CONFIG_INPUT_MISC=y -CONFIG_INPUT_UINPUT=m -# CONFIG_CONSOLE_TRANSLATIONS is not set -# CONFIG_VT_CONSOLE is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_8250=m -CONFIG_SERIAL_8250_NR_UARTS=5 -CONFIG_SERIAL_8250_RUNTIME_UARTS=5 -CONFIG_SERIAL_PXA=y -CONFIG_SERIAL_PXA_CONSOLE=y -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -# CONFIG_I2C_HELPER_AUTO is not set -CONFIG_I2C_PXA=y -CONFIG_GPIO_SYSFS=y -CONFIG_WATCHDOG=y -CONFIG_FB=y -CONFIG_FB_PXA=m -CONFIG_FB_PXA_PARAMETERS=y -CONFIG_BACKLIGHT_PWM=m -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -CONFIG_SOUND=m -CONFIG_SND=m -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -CONFIG_SND_PXA2XX_AC97=m -CONFIG_USB=m -CONFIG_USB_ISP116X_HCD=m -CONFIG_USB_SL811_HCD=m -CONFIG_USB_R8A66597_HCD=m -CONFIG_USB_ACM=m -CONFIG_USB_STORAGE=m -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_GADGET=m -CONFIG_USB_ETH=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_MASS_STORAGE=m -CONFIG_USB_G_SERIAL=m -CONFIG_USB_G_PRINTER=m -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_DS1307=m -CONFIG_RTC_DRV_SA1100=m -CONFIG_EXT2_FS=m -CONFIG_EXT3_FS=m -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_DNOTIFY is not set -CONFIG_VFAT_FS=m -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_NFSD=m -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_UTF8=m -CONFIG_CRC_T10DIF=m -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_KERNEL=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_FTRACE is not set -CONFIG_CRYPTO_ECB=m -CONFIG_CRYPTO_ARC4=m diff --git a/arch/arm/configs/wpcm450_defconfig b/arch/arm/configs/wpcm450_defconfig new file mode 100644 index 0000000000000000000000000000000000000000..45483deab034f8b69edf86bd9aa8b2bbb11ba093 --- /dev/null +++ b/arch/arm/configs/wpcm450_defconfig @@ -0,0 +1,211 @@ +CONFIG_SYSVIPC=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_PREEMPT=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_LOG_BUF_SHIFT=19 +CONFIG_CGROUPS=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_CC_OPTIMIZE_FOR_SIZE=y +CONFIG_PROFILING=y +# CONFIG_ARCH_MULTI_V7 is not set +CONFIG_ARCH_NPCM=y +CONFIG_ARCH_WPCM450=y +CONFIG_CPU_DCACHE_WRITETHROUGH=y +CONFIG_AEABI=y +CONFIG_UACCESS_WITH_MEMCPY=y +# CONFIG_ATAGS is not set +CONFIG_ARM_APPENDED_DTB=y +CONFIG_CPU_IDLE=y +CONFIG_KPROBES=y +CONFIG_JUMP_LABEL=y +CONFIG_STRICT_KERNEL_RWX=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_PACKET_DIAG=y +CONFIG_UNIX=y +CONFIG_UNIX_DIAG=y +CONFIG_INET=y +CONFIG_IP_MULTICAST=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_IP_PNP_BOOTP=y +CONFIG_NET_DSA=y +CONFIG_NET_DSA_TAG_DSA=y +CONFIG_NET_DSA_TAG_EDSA=y +CONFIG_NET_DSA_TAG_TRAILER=y +CONFIG_NET_PKTGEN=m +# CONFIG_WIRELESS is not set +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_MTD=y +CONFIG_MTD_CMDLINE_PARTS=y +CONFIG_MTD_BLOCK=y +CONFIG_MTD_SPI_NOR=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_BLOCK=y +CONFIG_BLK_DEV_LOOP=y +CONFIG_SRAM=y +CONFIG_EEPROM_AT24=y +CONFIG_SCSI=y +# CONFIG_SCSI_PROC_FS is not set +# CONFIG_SCSI_LOWLEVEL is not set +CONFIG_NETDEVICES=y +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CIRRUS is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_FARADAY is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_INTEL is not set +# CONFIG_NET_VENDOR_MARVELL is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROCHIP is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +CONFIG_REALTEK_PHY=y +# CONFIG_WLAN is not set +CONFIG_INPUT_FF_MEMLESS=y +CONFIG_INPUT_EVDEV=y +CONFIG_KEYBOARD_QT1070=m +CONFIG_KEYBOARD_GPIO=y +# CONFIG_INPUT_MOUSE is not set +CONFIG_VT_HW_CONSOLE_BINDING=y +CONFIG_LEGACY_PTY_COUNT=16 +# CONFIG_LEGACY_TIOCSTI is not set +CONFIG_SERIAL_8250=y +CONFIG_SERIAL_8250_CONSOLE=y +CONFIG_SERIAL_8250_NR_UARTS=6 +CONFIG_SERIAL_8250_RUNTIME_UARTS=6 +CONFIG_SERIAL_8250_EXTENDED=y +CONFIG_SERIAL_8250_MANY_PORTS=y +CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_NPCM7XX_KCS_IPMI_BMC=y +CONFIG_IPMI_KCS_BMC_CDEV_IPMI=y +CONFIG_IPMI_KCS_BMC_SERIO=y +CONFIG_HW_RANDOM=y +# CONFIG_HW_RANDOM_NPCM is not set +CONFIG_I2C=y +# CONFIG_I2C_COMPAT is not set +CONFIG_I2C_CHARDEV=y +CONFIG_I2C_MUX=y +CONFIG_I2C_NPCM=y +CONFIG_SPI=y +CONFIG_SPI_WPCM_FIU=y +CONFIG_SPI_NPCM_PSPI=y +CONFIG_PINCTRL_SINGLE=y +CONFIG_PINCTRL_WPCM450=y +CONFIG_POWER_SUPPLY=y +CONFIG_SENSORS_NPCM7XX=y +# CONFIG_THERMAL is not set +CONFIG_WATCHDOG=y +CONFIG_NPCM7XX_WATCHDOG=y +CONFIG_MFD_SYSCON=y +CONFIG_REGULATOR=y +CONFIG_REGULATOR_FIXED_VOLTAGE=y +CONFIG_FB=y +CONFIG_FB_MODE_HELPERS=y +# CONFIG_HID is not set +CONFIG_USB_CHIPIDEA=y +CONFIG_USB_CHIPIDEA_UDC=y +CONFIG_USB_GADGET=y +CONFIG_USB_CONFIGFS=y +CONFIG_USB_CONFIGFS_SERIAL=y +CONFIG_USB_CONFIGFS_ACM=y +CONFIG_USB_CONFIGFS_EEM=y +CONFIG_USB_CONFIGFS_MASS_STORAGE=y +CONFIG_USB_CONFIGFS_F_FS=y +CONFIG_USB_CONFIGFS_F_HID=y +CONFIG_NEW_LEDS=y +CONFIG_LEDS_CLASS=y +CONFIG_LEDS_GPIO=y +CONFIG_LEDS_TRIGGERS=y +CONFIG_LEDS_TRIGGER_TIMER=y +CONFIG_LEDS_TRIGGER_HEARTBEAT=y +CONFIG_LEDS_TRIGGER_DEFAULT_ON=y +CONFIG_DMADEVICES=y +CONFIG_SYNC_FILE=y +# CONFIG_VIRTIO_MENU is not set +# CONFIG_VHOST_MENU is not set +CONFIG_STAGING=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_PWM=y +CONFIG_GENERIC_PHY=y +CONFIG_PECI=y +CONFIG_PECI_CPU=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_UBIFS_FS=y +CONFIG_SQUASHFS=y +CONFIG_SQUASHFS_XZ=y +CONFIG_SQUASHFS_ZSTD=y +# CONFIG_NETWORK_FILESYSTEMS is not set +CONFIG_NLS_CODEPAGE_437=y +CONFIG_NLS_CODEPAGE_850=y +CONFIG_NLS_ISO8859_1=y +CONFIG_NLS_ISO8859_2=y +CONFIG_NLS_UTF8=y +CONFIG_KEYS=y +CONFIG_HARDENED_USERCOPY=y +CONFIG_FORTIFY_SOURCE=y +CONFIG_CRYPTO_RSA=y +CONFIG_CRYPTO_AES=y +CONFIG_CRYPTO_CBC=m +CONFIG_CRYPTO_PCBC=m +CONFIG_CRYPTO_CCM=y +CONFIG_CRYPTO_GCM=y +CONFIG_CRYPTO_CMAC=y +CONFIG_CRYPTO_SHA256=y +CONFIG_ASYMMETRIC_KEY_TYPE=y +CONFIG_ASYMMETRIC_PUBLIC_KEY_SUBTYPE=y +CONFIG_X509_CERTIFICATE_PARSER=y +CONFIG_PKCS7_MESSAGE_PARSER=y +CONFIG_SYSTEM_TRUSTED_KEYRING=y +CONFIG_CRC_CCITT=y +CONFIG_CRC_ITU_T=m +CONFIG_LIBCRC32C=y +CONFIG_PRINTK_TIME=y +CONFIG_DEBUG_KERNEL=y +CONFIG_MAGIC_SYSRQ=y +CONFIG_DEBUG_FS=y +# CONFIG_SCHED_DEBUG is not set +# CONFIG_DEBUG_PREEMPT is not set +# CONFIG_FTRACE is not set +CONFIG_IO_STRICT_DEVMEM=y +CONFIG_DEBUG_USER=y +CONFIG_DEBUG_LL=y +CONFIG_DEBUG_LL_UART_8250=y +CONFIG_DEBUG_UART_PHYS=0xb8000000 +CONFIG_DEBUG_UART_VIRT=0x0ff000000 +CONFIG_DEBUG_UART_8250_WORD=y +CONFIG_EARLY_PRINTK=y diff --git a/arch/arm/configs/xcep_defconfig b/arch/arm/configs/xcep_defconfig deleted file mode 100644 index 6bd9f71b71fc8d96894d36853bab0ec1bf642e62..0000000000000000000000000000000000000000 --- a/arch/arm/configs/xcep_defconfig +++ /dev/null @@ -1,90 +0,0 @@ -CONFIG_LOCALVERSION=".xcep-itech" -# CONFIG_LOCALVERSION_AUTO is not set -CONFIG_SYSVIPC=y -CONFIG_NO_HZ_IDLE=y -CONFIG_HIGH_RES_TIMERS=y -CONFIG_BSD_PROCESS_ACCT=y -CONFIG_IKCONFIG=y -CONFIG_IKCONFIG_PROC=y -CONFIG_LOG_BUF_SHIFT=16 -CONFIG_SYSFS_DEPRECATED_V2=y -CONFIG_BLK_DEV_INITRD=y -CONFIG_EXPERT=y -# CONFIG_UID16 is not set -# CONFIG_SHMEM is not set -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_PXA=y -CONFIG_MACH_XCEP=y -CONFIG_IWMMXT=y -CONFIG_AEABI=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="root=mtd4 rootfstype=jffs2 ro console=ttyS0,115200" -CONFIG_FPE_NWFPE=y -CONFIG_KPROBES=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_MODVERSIONS=y -CONFIG_MODULE_SRCVERSION_ALL=y -# CONFIG_BLOCK is not set -CONFIG_SLUB=y -CONFIG_SLUB_TINY=y -# CONFIG_COMPAT_BRK is not set -# CONFIG_VM_EVENT_COUNTERS is not set -CONFIG_NET=y -CONFIG_PACKET=m -CONFIG_UNIX=y -CONFIG_NET_KEY=y -CONFIG_INET=y -CONFIG_IP_MULTICAST=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_IP_PNP_BOOTP=y -# CONFIG_INET_XFRM_MODE_TRANSPORT is not set -# CONFIG_INET_XFRM_MODE_TUNNEL is not set -# CONFIG_INET_XFRM_MODE_BEET is not set -# CONFIG_INET_DIAG is not set -# CONFIG_IPV6 is not set -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -# CONFIG_FW_LOADER is not set -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_PXA2XX=y -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -# CONFIG_INPUT_MOUSEDEV is not set -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -# CONFIG_SERIO is not set -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_PXA=y -CONFIG_SERIAL_PXA_CONSOLE=y -# CONFIG_HW_RANDOM is not set -CONFIG_I2C=m -CONFIG_I2C_CHARDEV=m -CONFIG_I2C_PXA=m -CONFIG_HWMON=m -CONFIG_SENSORS_ADM1021=m -CONFIG_SENSORS_MAX6650=m -# CONFIG_VGA_CONSOLE is not set -# CONFIG_USB_SUPPORT is not set -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_SA1100=m -CONFIG_DMADEVICES=y -# CONFIG_DNOTIFY is not set -# CONFIG_INOTIFY_USER is not set -CONFIG_JFFS2_FS=y -CONFIG_JFFS2_FS_WBUF_VERIFY=y -CONFIG_NFS_FS=m -CONFIG_NFS_V3=y -CONFIG_NLS=m -CONFIG_NLS_DEFAULT="utf8" -CONFIG_NLS_UTF8=m -# CONFIG_CRYPTO_HW is not set -CONFIG_LIBCRC32C=m -CONFIG_PRINTK_TIME=y -# CONFIG_DEBUG_BUGVERBOSE is not set -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_KERNEL=y -# CONFIG_SCHED_DEBUG is not set -# CONFIG_FTRACE is not set -# CONFIG_ARM_UNWIND is not set -# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/arm/configs/zeus_defconfig b/arch/arm/configs/zeus_defconfig deleted file mode 100644 index c4535315e21634a711120d08299dd0fa9edcd0e0..0000000000000000000000000000000000000000 --- a/arch/arm/configs/zeus_defconfig +++ /dev/null @@ -1,173 +0,0 @@ -CONFIG_SYSVIPC=y -CONFIG_TINY_RCU=y -CONFIG_LOG_BUF_SHIFT=13 -# CONFIG_ARCH_MULTI_V7 is not set -CONFIG_ARCH_PXA=y -CONFIG_MACH_ARCOM_ZEUS=y -CONFIG_AEABI=y -CONFIG_UNUSED_BOARD_FILES=y -CONFIG_CMDLINE="root=31:02 rootfstype=jffs2 ro console=ttyS0,115200" -CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=m -CONFIG_CPU_FREQ_GOV_USERSPACE=m -CONFIG_CPU_FREQ_GOV_ONDEMAND=m -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m -CONFIG_FPE_NWFPE=y -CONFIG_PM=y -CONFIG_APM_EMULATION=y -CONFIG_MODULES=y -CONFIG_MODULE_UNLOAD=y -CONFIG_PARTITION_ADVANCED=y -CONFIG_NET=y -CONFIG_PACKET=y -CONFIG_UNIX=y -CONFIG_INET=y -CONFIG_IP_PNP=y -CONFIG_IP_PNP_DHCP=y -CONFIG_SYN_COOKIES=y -# CONFIG_IPV6 is not set -CONFIG_BT=m -CONFIG_BT_RFCOMM=m -CONFIG_BT_RFCOMM_TTY=y -CONFIG_BT_BNEP=m -CONFIG_BT_HCIUART=m -CONFIG_BT_HCIUART_H4=y -CONFIG_BT_HCIUART_BCSP=y -CONFIG_CFG80211=m -CONFIG_LIB80211=m -CONFIG_MAC80211=m -CONFIG_PCCARD=m -CONFIG_PCMCIA_PXA2XX=m -CONFIG_MTD=y -CONFIG_MTD_REDBOOT_PARTS=y -CONFIG_MTD_REDBOOT_PARTS_READONLY=y -CONFIG_MTD_BLOCK=y -CONFIG_MTD_CFI=y -CONFIG_MTD_JEDECPROBE=y -CONFIG_MTD_CFI_ADV_OPTIONS=y -CONFIG_MTD_CFI_GEOMETRY=y -# CONFIG_MTD_MAP_BANK_WIDTH_4 is not set -# CONFIG_MTD_CFI_I2 is not set -CONFIG_MTD_CFI_INTELEXT=y -CONFIG_MTD_CFI_AMDSTD=y -CONFIG_MTD_RAM=y -CONFIG_MTD_COMPLEX_MAPPINGS=y -CONFIG_MTD_PHYSMAP=y -CONFIG_MTD_PXA2XX=y -CONFIG_BLK_DEV_LOOP=m -CONFIG_EEPROM_AT24=m -# CONFIG_SCSI_PROC_FS is not set -CONFIG_BLK_DEV_SD=m -# CONFIG_BLK_DEV_BSG is not set -CONFIG_ATA=m -# CONFIG_SATA_PMP is not set -CONFIG_PATA_PCMCIA=m -CONFIG_NETDEVICES=y -CONFIG_NET_ETHERNET=y -CONFIG_DM9000=y -CONFIG_PPP=m -CONFIG_PPP_BSDCOMP=m -CONFIG_PPP_DEFLATE=m -CONFIG_PPP_ASYNC=m -CONFIG_HERMES=m -CONFIG_PCMCIA_HERMES=m -CONFIG_RT2X00=m -CONFIG_RT73USB=m -CONFIG_NET_PCMCIA=y -# CONFIG_INPUT_MOUSEDEV_PSAUX is not set -CONFIG_INPUT_EVDEV=m -# CONFIG_INPUT_KEYBOARD is not set -# CONFIG_INPUT_MOUSE is not set -CONFIG_INPUT_TOUCHSCREEN=y -CONFIG_TOUCHSCREEN_FUJITSU=m -CONFIG_TOUCHSCREEN_ELO=m -CONFIG_TOUCHSCREEN_MTOUCH=m -CONFIG_TOUCHSCREEN_INEXIO=m -CONFIG_TOUCHSCREEN_HTCPEN=m -CONFIG_TOUCHSCREEN_PENMOUNT=m -CONFIG_TOUCHSCREEN_TOUCHRIGHT=m -CONFIG_TOUCHSCREEN_TOUCHWIN=m -CONFIG_TOUCHSCREEN_TOUCHIT213=m -CONFIG_INPUT_MISC=y -CONFIG_INPUT_UINPUT=m -# CONFIG_LEGACY_PTYS is not set -CONFIG_SERIAL_8250=y -CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=7 -CONFIG_SERIAL_8250_RUNTIME_UARTS=7 -CONFIG_I2C=y -CONFIG_I2C_CHARDEV=y -# CONFIG_I2C_HELPER_AUTO is not set -CONFIG_I2C_GPIO=y -CONFIG_I2C_PXA=y -CONFIG_SPI=y -CONFIG_SPI_PXA2XX=y -CONFIG_GPIO_SYSFS=y -CONFIG_GPIO_PCA953X=y -CONFIG_SENSORS_LM75=m -CONFIG_WATCHDOG=y -CONFIG_FB=y -CONFIG_FB_PXA=m -CONFIG_FB_PXA_PARAMETERS=y -# CONFIG_VGA_CONSOLE is not set -CONFIG_FRAMEBUFFER_CONSOLE=y -CONFIG_LOGO=y -CONFIG_SOUND=m -CONFIG_SND=m -CONFIG_SND_MIXER_OSS=m -CONFIG_SND_PCM_OSS=m -# CONFIG_SND_SUPPORT_OLD_API is not set -CONFIG_SND_PXA2XX_AC97=m -# CONFIG_SND_SPI is not set -# CONFIG_SND_PCMCIA is not set -CONFIG_SND_SOC=m -CONFIG_SND_PXA2XX_SOC=m -CONFIG_USB=m -CONFIG_USB_OHCI_HCD=m -CONFIG_USB_ACM=m -CONFIG_USB_STORAGE=m -CONFIG_USB_SERIAL=m -CONFIG_USB_SERIAL_GENERIC=y -CONFIG_USB_SERIAL_MCT_U232=m -CONFIG_USB_GADGET=m -CONFIG_USB_PXA27X=y -CONFIG_USB_ETH=m -CONFIG_USB_GADGETFS=m -CONFIG_USB_MASS_STORAGE=m -CONFIG_USB_G_SERIAL=m -CONFIG_USB_G_PRINTER=m -CONFIG_MMC=y -CONFIG_MMC_PXA=y -CONFIG_NEW_LEDS=y -CONFIG_LEDS_CLASS=m -CONFIG_LEDS_GPIO=m -CONFIG_LEDS_TRIGGERS=y -CONFIG_LEDS_TRIGGER_TIMER=m -CONFIG_LEDS_TRIGGER_HEARTBEAT=m -CONFIG_LEDS_TRIGGER_BACKLIGHT=m -CONFIG_LEDS_TRIGGER_GPIO=m -CONFIG_LEDS_TRIGGER_DEFAULT_ON=m -CONFIG_RTC_CLASS=y -CONFIG_RTC_DRV_ISL1208=m -CONFIG_RTC_DRV_PXA=m -CONFIG_EXT2_FS=y -CONFIG_EXT3_FS=y -# CONFIG_EXT3_FS_XATTR is not set -# CONFIG_DNOTIFY is not set -CONFIG_VFAT_FS=m -CONFIG_TMPFS=y -CONFIG_JFFS2_FS=y -CONFIG_NFS_FS=y -CONFIG_NFS_V3=y -CONFIG_ROOT_NFS=y -CONFIG_NFSD=m -CONFIG_NLS_CODEPAGE_437=m -CONFIG_NLS_CODEPAGE_850=m -CONFIG_NLS_ISO8859_1=m -CONFIG_NLS_ISO8859_15=m -CONFIG_NLS_UTF8=m -CONFIG_CRC_T10DIF=m -CONFIG_DEBUG_KERNEL=y -CONFIG_MAGIC_SYSRQ=y -CONFIG_DEBUG_MUTEXES=y -# CONFIG_CRYPTO_ANSI_CPRNG is not set diff --git a/arch/arm/crypto/Kconfig b/arch/arm/crypto/Kconfig index 7b2b7d043d9be9e6f5c432badf2adb9938883eaf..847b7a0033569ccd8685bb859db02cf46f51511c 100644 --- a/arch/arm/crypto/Kconfig +++ b/arch/arm/crypto/Kconfig @@ -16,8 +16,10 @@ config CRYPTO_CURVE25519_NEON config CRYPTO_GHASH_ARM_CE tristate "Hash functions: GHASH (PMULL/NEON/ARMv8 Crypto Extensions)" depends on KERNEL_MODE_NEON + select CRYPTO_AEAD select CRYPTO_HASH select CRYPTO_CRYPTD + select CRYPTO_LIB_AES select CRYPTO_LIB_GF128MUL help GCM GHASH function (NIST SP800-38D) diff --git a/arch/arm/crypto/Makefile b/arch/arm/crypto/Makefile index 971e74546fb1bf31d6c25f3c74a326b3a51a0e2a..13e62c7c25dca8e103527f776f9fb094b7b350e7 100644 --- a/arch/arm/crypto/Makefile +++ b/arch/arm/crypto/Makefile @@ -53,7 +53,12 @@ $(obj)/%-core.S: $(src)/%-armv4.pl clean-files += poly1305-core.S sha256-core.S sha512-core.S +aflags-thumb2-$(CONFIG_THUMB2_KERNEL) := -U__thumb2__ -D__thumb2__=1 + +AFLAGS_sha256-core.o += $(aflags-thumb2-y) +AFLAGS_sha512-core.o += $(aflags-thumb2-y) + # massage the perlasm code a bit so we only get the NEON routine if we need it poly1305-aflags-$(CONFIG_CPU_V7) := -U__LINUX_ARM_ARCH__ -D__LINUX_ARM_ARCH__=5 poly1305-aflags-$(CONFIG_KERNEL_MODE_NEON) := -U__LINUX_ARM_ARCH__ -D__LINUX_ARM_ARCH__=7 -AFLAGS_poly1305-core.o += $(poly1305-aflags-y) +AFLAGS_poly1305-core.o += $(poly1305-aflags-y) $(aflags-thumb2-y) diff --git a/arch/arm/crypto/ghash-ce-core.S b/arch/arm/crypto/ghash-ce-core.S index 9f51e3fa45268de9a80b0b2a35cee13750957ad0..858c0d66798be109a62fda5cb8c8d5e57725f2c4 100644 --- a/arch/arm/crypto/ghash-ce-core.S +++ b/arch/arm/crypto/ghash-ce-core.S @@ -2,7 +2,8 @@ /* * Accelerated GHASH implementation with NEON/ARMv8 vmull.p8/64 instructions. * - * Copyright (C) 2015 - 2017 Linaro Ltd. + * Copyright (C) 2015 - 2017 Linaro Ltd. + * Copyright (C) 2023 Google LLC. */ #include @@ -44,7 +45,7 @@ t2q .req q7 t3q .req q8 t4q .req q9 - T2 .req q9 + XH2 .req q9 s1l .req d20 s1h .req d21 @@ -80,7 +81,7 @@ XL2 .req q5 XM2 .req q6 - XH2 .req q7 + T2 .req q7 T3 .req q8 XL2_L .req d10 @@ -192,9 +193,10 @@ vshr.u64 XL, XL, #1 .endm - .macro ghash_update, pn + .macro ghash_update, pn, enc, aggregate=1, head=1 vld1.64 {XL}, [r1] + .if \head /* do the head block first, if supplied */ ldr ip, [sp] teq ip, #0 @@ -202,13 +204,32 @@ vld1.64 {T1}, [ip] teq r0, #0 b 3f + .endif 0: .ifc \pn, p64 + .if \aggregate tst r0, #3 // skip until #blocks is a bne 2f // round multiple of 4 vld1.8 {XL2-XM2}, [r2]! -1: vld1.8 {T3-T2}, [r2]! +1: vld1.8 {T2-T3}, [r2]! + + .ifnb \enc + \enc\()_4x XL2, XM2, T2, T3 + + add ip, r3, #16 + vld1.64 {HH}, [ip, :128]! + vld1.64 {HH3-HH4}, [ip, :128] + + veor SHASH2_p64, SHASH_L, SHASH_H + veor SHASH2_H, HH_L, HH_H + veor HH34_L, HH3_L, HH3_H + veor HH34_H, HH4_L, HH4_H + + vmov.i8 MASK, #0xe1 + vshl.u64 MASK, MASK, #57 + .endif + vrev64.8 XL2, XL2 vrev64.8 XM2, XM2 @@ -218,8 +239,8 @@ veor XL2_H, XL2_H, XL_L veor XL, XL, T1 - vrev64.8 T3, T3 - vrev64.8 T1, T2 + vrev64.8 T1, T3 + vrev64.8 T3, T2 vmull.p64 XH, HH4_H, XL_H // a1 * b1 veor XL2_H, XL2_H, XL_H @@ -267,14 +288,22 @@ b 1b .endif + .endif + +2: vld1.8 {T1}, [r2]! + + .ifnb \enc + \enc\()_1x T1 + veor SHASH2_p64, SHASH_L, SHASH_H + vmov.i8 MASK, #0xe1 + vshl.u64 MASK, MASK, #57 + .endif -2: vld1.64 {T1}, [r2]! subs r0, r0, #1 3: /* multiply XL by SHASH in GF(2^128) */ -#ifndef CONFIG_CPU_BIG_ENDIAN vrev64.8 T1, T1 -#endif + vext.8 IN1, T1, T1, #8 veor T1_L, T1_L, XL_H veor XL, XL, IN1 @@ -293,9 +322,6 @@ veor XL, XL, T1 bne 0b - - vst1.64 {XL}, [r1] - bx lr .endm /* @@ -316,6 +342,9 @@ ENTRY(pmull_ghash_update_p64) vshl.u64 MASK, MASK, #57 ghash_update p64 + vst1.64 {XL}, [r1] + + bx lr ENDPROC(pmull_ghash_update_p64) ENTRY(pmull_ghash_update_p8) @@ -336,4 +365,331 @@ ENTRY(pmull_ghash_update_p8) vmov.i64 k48, #0xffffffffffff ghash_update p8 + vst1.64 {XL}, [r1] + + bx lr ENDPROC(pmull_ghash_update_p8) + + e0 .req q9 + e1 .req q10 + e2 .req q11 + e3 .req q12 + e0l .req d18 + e0h .req d19 + e2l .req d22 + e2h .req d23 + e3l .req d24 + e3h .req d25 + ctr .req q13 + ctr0 .req d26 + ctr1 .req d27 + + ek0 .req q14 + ek1 .req q15 + + .macro round, rk:req, regs:vararg + .irp r, \regs + aese.8 \r, \rk + aesmc.8 \r, \r + .endr + .endm + + .macro aes_encrypt, rkp, rounds, regs:vararg + vld1.8 {ek0-ek1}, [\rkp, :128]! + cmp \rounds, #12 + blt .L\@ // AES-128 + + round ek0, \regs + vld1.8 {ek0}, [\rkp, :128]! + round ek1, \regs + vld1.8 {ek1}, [\rkp, :128]! + + beq .L\@ // AES-192 + + round ek0, \regs + vld1.8 {ek0}, [\rkp, :128]! + round ek1, \regs + vld1.8 {ek1}, [\rkp, :128]! + +.L\@: .rept 4 + round ek0, \regs + vld1.8 {ek0}, [\rkp, :128]! + round ek1, \regs + vld1.8 {ek1}, [\rkp, :128]! + .endr + + round ek0, \regs + vld1.8 {ek0}, [\rkp, :128] + + .irp r, \regs + aese.8 \r, ek1 + .endr + .irp r, \regs + veor \r, \r, ek0 + .endr + .endm + +pmull_aes_encrypt: + add ip, r5, #4 + vld1.8 {ctr0}, [r5] // load 12 byte IV + vld1.8 {ctr1}, [ip] + rev r8, r7 + vext.8 ctr1, ctr1, ctr1, #4 + add r7, r7, #1 + vmov.32 ctr1[1], r8 + vmov e0, ctr + + add ip, r3, #64 + aes_encrypt ip, r6, e0 + bx lr +ENDPROC(pmull_aes_encrypt) + +pmull_aes_encrypt_4x: + add ip, r5, #4 + vld1.8 {ctr0}, [r5] + vld1.8 {ctr1}, [ip] + rev r8, r7 + vext.8 ctr1, ctr1, ctr1, #4 + add r7, r7, #1 + vmov.32 ctr1[1], r8 + rev ip, r7 + vmov e0, ctr + add r7, r7, #1 + vmov.32 ctr1[1], ip + rev r8, r7 + vmov e1, ctr + add r7, r7, #1 + vmov.32 ctr1[1], r8 + rev ip, r7 + vmov e2, ctr + add r7, r7, #1 + vmov.32 ctr1[1], ip + vmov e3, ctr + + add ip, r3, #64 + aes_encrypt ip, r6, e0, e1, e2, e3 + bx lr +ENDPROC(pmull_aes_encrypt_4x) + +pmull_aes_encrypt_final: + add ip, r5, #4 + vld1.8 {ctr0}, [r5] + vld1.8 {ctr1}, [ip] + rev r8, r7 + vext.8 ctr1, ctr1, ctr1, #4 + mov r7, #1 << 24 // BE #1 for the tag + vmov.32 ctr1[1], r8 + vmov e0, ctr + vmov.32 ctr1[1], r7 + vmov e1, ctr + + add ip, r3, #64 + aes_encrypt ip, r6, e0, e1 + bx lr +ENDPROC(pmull_aes_encrypt_final) + + .macro enc_1x, in0 + bl pmull_aes_encrypt + veor \in0, \in0, e0 + vst1.8 {\in0}, [r4]! + .endm + + .macro dec_1x, in0 + bl pmull_aes_encrypt + veor e0, e0, \in0 + vst1.8 {e0}, [r4]! + .endm + + .macro enc_4x, in0, in1, in2, in3 + bl pmull_aes_encrypt_4x + + veor \in0, \in0, e0 + veor \in1, \in1, e1 + veor \in2, \in2, e2 + veor \in3, \in3, e3 + + vst1.8 {\in0-\in1}, [r4]! + vst1.8 {\in2-\in3}, [r4]! + .endm + + .macro dec_4x, in0, in1, in2, in3 + bl pmull_aes_encrypt_4x + + veor e0, e0, \in0 + veor e1, e1, \in1 + veor e2, e2, \in2 + veor e3, e3, \in3 + + vst1.8 {e0-e1}, [r4]! + vst1.8 {e2-e3}, [r4]! + .endm + + /* + * void pmull_gcm_encrypt(int blocks, u64 dg[], const char *src, + * struct gcm_key const *k, char *dst, + * char *iv, int rounds, u32 counter) + */ +ENTRY(pmull_gcm_encrypt) + push {r4-r8, lr} + ldrd r4, r5, [sp, #24] + ldrd r6, r7, [sp, #32] + + vld1.64 {SHASH}, [r3] + + ghash_update p64, enc, head=0 + vst1.64 {XL}, [r1] + + pop {r4-r8, pc} +ENDPROC(pmull_gcm_encrypt) + + /* + * void pmull_gcm_decrypt(int blocks, u64 dg[], const char *src, + * struct gcm_key const *k, char *dst, + * char *iv, int rounds, u32 counter) + */ +ENTRY(pmull_gcm_decrypt) + push {r4-r8, lr} + ldrd r4, r5, [sp, #24] + ldrd r6, r7, [sp, #32] + + vld1.64 {SHASH}, [r3] + + ghash_update p64, dec, head=0 + vst1.64 {XL}, [r1] + + pop {r4-r8, pc} +ENDPROC(pmull_gcm_decrypt) + + /* + * void pmull_gcm_enc_final(int bytes, u64 dg[], char *tag, + * struct gcm_key const *k, char *head, + * char *iv, int rounds, u32 counter) + */ +ENTRY(pmull_gcm_enc_final) + push {r4-r8, lr} + ldrd r4, r5, [sp, #24] + ldrd r6, r7, [sp, #32] + + bl pmull_aes_encrypt_final + + cmp r0, #0 + beq .Lenc_final + + mov_l ip, .Lpermute + sub r4, r4, #16 + add r8, ip, r0 + add ip, ip, #32 + add r4, r4, r0 + sub ip, ip, r0 + + vld1.8 {e3}, [r8] // permute vector for key stream + vld1.8 {e2}, [ip] // permute vector for ghash input + + vtbl.8 e3l, {e0}, e3l + vtbl.8 e3h, {e0}, e3h + + vld1.8 {e0}, [r4] // encrypt tail block + veor e0, e0, e3 + vst1.8 {e0}, [r4] + + vtbl.8 T1_L, {e0}, e2l + vtbl.8 T1_H, {e0}, e2h + + vld1.64 {XL}, [r1] +.Lenc_final: + vld1.64 {SHASH}, [r3, :128] + vmov.i8 MASK, #0xe1 + veor SHASH2_p64, SHASH_L, SHASH_H + vshl.u64 MASK, MASK, #57 + mov r0, #1 + bne 3f // process head block first + ghash_update p64, aggregate=0, head=0 + + vrev64.8 XL, XL + vext.8 XL, XL, XL, #8 + veor XL, XL, e1 + + sub r2, r2, #16 // rewind src pointer + vst1.8 {XL}, [r2] // store tag + + pop {r4-r8, pc} +ENDPROC(pmull_gcm_enc_final) + + /* + * int pmull_gcm_dec_final(int bytes, u64 dg[], char *tag, + * struct gcm_key const *k, char *head, + * char *iv, int rounds, u32 counter, + * const char *otag, int authsize) + */ +ENTRY(pmull_gcm_dec_final) + push {r4-r8, lr} + ldrd r4, r5, [sp, #24] + ldrd r6, r7, [sp, #32] + + bl pmull_aes_encrypt_final + + cmp r0, #0 + beq .Ldec_final + + mov_l ip, .Lpermute + sub r4, r4, #16 + add r8, ip, r0 + add ip, ip, #32 + add r4, r4, r0 + sub ip, ip, r0 + + vld1.8 {e3}, [r8] // permute vector for key stream + vld1.8 {e2}, [ip] // permute vector for ghash input + + vtbl.8 e3l, {e0}, e3l + vtbl.8 e3h, {e0}, e3h + + vld1.8 {e0}, [r4] + + vtbl.8 T1_L, {e0}, e2l + vtbl.8 T1_H, {e0}, e2h + + veor e0, e0, e3 + vst1.8 {e0}, [r4] + + vld1.64 {XL}, [r1] +.Ldec_final: + vld1.64 {SHASH}, [r3] + vmov.i8 MASK, #0xe1 + veor SHASH2_p64, SHASH_L, SHASH_H + vshl.u64 MASK, MASK, #57 + mov r0, #1 + bne 3f // process head block first + ghash_update p64, aggregate=0, head=0 + + vrev64.8 XL, XL + vext.8 XL, XL, XL, #8 + veor XL, XL, e1 + + mov_l ip, .Lpermute + ldrd r2, r3, [sp, #40] // otag and authsize + vld1.8 {T1}, [r2] + add ip, ip, r3 + vceq.i8 T1, T1, XL // compare tags + vmvn T1, T1 // 0 for eq, -1 for ne + + vld1.8 {e0}, [ip] + vtbl.8 XL_L, {T1}, e0l // keep authsize bytes only + vtbl.8 XL_H, {T1}, e0h + + vpmin.s8 XL_L, XL_L, XL_H // take the minimum s8 across the vector + vpmin.s8 XL_L, XL_L, XL_L + vmov.32 r0, XL_L[0] // fail if != 0x0 + + pop {r4-r8, pc} +ENDPROC(pmull_gcm_dec_final) + + .section ".rodata", "a", %progbits + .align 5 +.Lpermute: + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07 + .byte 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + .byte 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff diff --git a/arch/arm/crypto/ghash-ce-glue.c b/arch/arm/crypto/ghash-ce-glue.c index f13401f3e6693211c95e266d9676c79710755ebf..3ddf05b4234d8e5c6540edf087906507769ac242 100644 --- a/arch/arm/crypto/ghash-ce-glue.c +++ b/arch/arm/crypto/ghash-ce-glue.c @@ -2,36 +2,53 @@ /* * Accelerated GHASH implementation with ARMv8 vmull.p64 instructions. * - * Copyright (C) 2015 - 2018 Linaro Ltd. + * Copyright (C) 2015 - 2018 Linaro Ltd. + * Copyright (C) 2023 Google LLC. */ #include #include #include #include +#include +#include #include #include +#include #include #include +#include #include +#include #include #include #include #include MODULE_DESCRIPTION("GHASH hash function using ARMv8 Crypto Extensions"); -MODULE_AUTHOR("Ard Biesheuvel "); -MODULE_LICENSE("GPL v2"); +MODULE_AUTHOR("Ard Biesheuvel "); +MODULE_LICENSE("GPL"); MODULE_ALIAS_CRYPTO("ghash"); +MODULE_ALIAS_CRYPTO("gcm(aes)"); +MODULE_ALIAS_CRYPTO("rfc4106(gcm(aes))"); #define GHASH_BLOCK_SIZE 16 #define GHASH_DIGEST_SIZE 16 +#define RFC4106_NONCE_SIZE 4 + struct ghash_key { be128 k; u64 h[][2]; }; +struct gcm_key { + u64 h[4][2]; + u32 rk[AES_MAX_KEYLENGTH_U32]; + int rounds; + u8 nonce[]; // for RFC4106 nonce +}; + struct ghash_desc_ctx { u64 digest[GHASH_DIGEST_SIZE/sizeof(u64)]; u8 buf[GHASH_BLOCK_SIZE]; @@ -344,6 +361,393 @@ static struct ahash_alg ghash_async_alg = { }, }; + +void pmull_gcm_encrypt(int blocks, u64 dg[], const char *src, + struct gcm_key const *k, char *dst, + const char *iv, int rounds, u32 counter); + +void pmull_gcm_enc_final(int blocks, u64 dg[], char *tag, + struct gcm_key const *k, char *head, + const char *iv, int rounds, u32 counter); + +void pmull_gcm_decrypt(int bytes, u64 dg[], const char *src, + struct gcm_key const *k, char *dst, + const char *iv, int rounds, u32 counter); + +int pmull_gcm_dec_final(int bytes, u64 dg[], char *tag, + struct gcm_key const *k, char *head, + const char *iv, int rounds, u32 counter, + const char *otag, int authsize); + +static int gcm_aes_setkey(struct crypto_aead *tfm, const u8 *inkey, + unsigned int keylen) +{ + struct gcm_key *ctx = crypto_aead_ctx(tfm); + struct crypto_aes_ctx aes_ctx; + be128 h, k; + int ret; + + ret = aes_expandkey(&aes_ctx, inkey, keylen); + if (ret) + return -EINVAL; + + aes_encrypt(&aes_ctx, (u8 *)&k, (u8[AES_BLOCK_SIZE]){}); + + memcpy(ctx->rk, aes_ctx.key_enc, sizeof(ctx->rk)); + ctx->rounds = 6 + keylen / 4; + + memzero_explicit(&aes_ctx, sizeof(aes_ctx)); + + ghash_reflect(ctx->h[0], &k); + + h = k; + gf128mul_lle(&h, &k); + ghash_reflect(ctx->h[1], &h); + + gf128mul_lle(&h, &k); + ghash_reflect(ctx->h[2], &h); + + gf128mul_lle(&h, &k); + ghash_reflect(ctx->h[3], &h); + + return 0; +} + +static int gcm_aes_setauthsize(struct crypto_aead *tfm, unsigned int authsize) +{ + return crypto_gcm_check_authsize(authsize); +} + +static void gcm_update_mac(u64 dg[], const u8 *src, int count, u8 buf[], + int *buf_count, struct gcm_key *ctx) +{ + if (*buf_count > 0) { + int buf_added = min(count, GHASH_BLOCK_SIZE - *buf_count); + + memcpy(&buf[*buf_count], src, buf_added); + + *buf_count += buf_added; + src += buf_added; + count -= buf_added; + } + + if (count >= GHASH_BLOCK_SIZE || *buf_count == GHASH_BLOCK_SIZE) { + int blocks = count / GHASH_BLOCK_SIZE; + + pmull_ghash_update_p64(blocks, dg, src, ctx->h, + *buf_count ? buf : NULL); + + src += blocks * GHASH_BLOCK_SIZE; + count %= GHASH_BLOCK_SIZE; + *buf_count = 0; + } + + if (count > 0) { + memcpy(buf, src, count); + *buf_count = count; + } +} + +static void gcm_calculate_auth_mac(struct aead_request *req, u64 dg[], u32 len) +{ + struct crypto_aead *aead = crypto_aead_reqtfm(req); + struct gcm_key *ctx = crypto_aead_ctx(aead); + u8 buf[GHASH_BLOCK_SIZE]; + struct scatter_walk walk; + int buf_count = 0; + + scatterwalk_start(&walk, req->src); + + do { + u32 n = scatterwalk_clamp(&walk, len); + u8 *p; + + if (!n) { + scatterwalk_start(&walk, sg_next(walk.sg)); + n = scatterwalk_clamp(&walk, len); + } + + p = scatterwalk_map(&walk); + gcm_update_mac(dg, p, n, buf, &buf_count, ctx); + scatterwalk_unmap(p); + + if (unlikely(len / SZ_4K > (len - n) / SZ_4K)) { + kernel_neon_end(); + kernel_neon_begin(); + } + + len -= n; + scatterwalk_advance(&walk, n); + scatterwalk_done(&walk, 0, len); + } while (len); + + if (buf_count) { + memset(&buf[buf_count], 0, GHASH_BLOCK_SIZE - buf_count); + pmull_ghash_update_p64(1, dg, buf, ctx->h, NULL); + } +} + +static int gcm_encrypt(struct aead_request *req, const u8 *iv, u32 assoclen) +{ + struct crypto_aead *aead = crypto_aead_reqtfm(req); + struct gcm_key *ctx = crypto_aead_ctx(aead); + struct skcipher_walk walk; + u8 buf[AES_BLOCK_SIZE]; + u32 counter = 2; + u64 dg[2] = {}; + be128 lengths; + const u8 *src; + u8 *tag, *dst; + int tail, err; + + if (WARN_ON_ONCE(!may_use_simd())) + return -EBUSY; + + err = skcipher_walk_aead_encrypt(&walk, req, false); + + kernel_neon_begin(); + + if (assoclen) + gcm_calculate_auth_mac(req, dg, assoclen); + + src = walk.src.virt.addr; + dst = walk.dst.virt.addr; + + while (walk.nbytes >= AES_BLOCK_SIZE) { + int nblocks = walk.nbytes / AES_BLOCK_SIZE; + + pmull_gcm_encrypt(nblocks, dg, src, ctx, dst, iv, + ctx->rounds, counter); + counter += nblocks; + + if (walk.nbytes == walk.total) { + src += nblocks * AES_BLOCK_SIZE; + dst += nblocks * AES_BLOCK_SIZE; + break; + } + + kernel_neon_end(); + + err = skcipher_walk_done(&walk, + walk.nbytes % AES_BLOCK_SIZE); + if (err) + return err; + + src = walk.src.virt.addr; + dst = walk.dst.virt.addr; + + kernel_neon_begin(); + } + + + lengths.a = cpu_to_be64(assoclen * 8); + lengths.b = cpu_to_be64(req->cryptlen * 8); + + tag = (u8 *)&lengths; + tail = walk.nbytes % AES_BLOCK_SIZE; + + /* + * Bounce via a buffer unless we are encrypting in place and src/dst + * are not pointing to the start of the walk buffer. In that case, we + * can do a NEON load/xor/store sequence in place as long as we move + * the plain/ciphertext and keystream to the start of the register. If + * not, do a memcpy() to the end of the buffer so we can reuse the same + * logic. + */ + if (unlikely(tail && (tail == walk.nbytes || src != dst))) + src = memcpy(buf + sizeof(buf) - tail, src, tail); + + pmull_gcm_enc_final(tail, dg, tag, ctx, (u8 *)src, iv, + ctx->rounds, counter); + kernel_neon_end(); + + if (unlikely(tail && src != dst)) + memcpy(dst, src, tail); + + if (walk.nbytes) { + err = skcipher_walk_done(&walk, 0); + if (err) + return err; + } + + /* copy authtag to end of dst */ + scatterwalk_map_and_copy(tag, req->dst, req->assoclen + req->cryptlen, + crypto_aead_authsize(aead), 1); + + return 0; +} + +static int gcm_decrypt(struct aead_request *req, const u8 *iv, u32 assoclen) +{ + struct crypto_aead *aead = crypto_aead_reqtfm(req); + struct gcm_key *ctx = crypto_aead_ctx(aead); + int authsize = crypto_aead_authsize(aead); + struct skcipher_walk walk; + u8 otag[AES_BLOCK_SIZE]; + u8 buf[AES_BLOCK_SIZE]; + u32 counter = 2; + u64 dg[2] = {}; + be128 lengths; + const u8 *src; + u8 *tag, *dst; + int tail, err, ret; + + if (WARN_ON_ONCE(!may_use_simd())) + return -EBUSY; + + scatterwalk_map_and_copy(otag, req->src, + req->assoclen + req->cryptlen - authsize, + authsize, 0); + + err = skcipher_walk_aead_decrypt(&walk, req, false); + + kernel_neon_begin(); + + if (assoclen) + gcm_calculate_auth_mac(req, dg, assoclen); + + src = walk.src.virt.addr; + dst = walk.dst.virt.addr; + + while (walk.nbytes >= AES_BLOCK_SIZE) { + int nblocks = walk.nbytes / AES_BLOCK_SIZE; + + pmull_gcm_decrypt(nblocks, dg, src, ctx, dst, iv, + ctx->rounds, counter); + counter += nblocks; + + if (walk.nbytes == walk.total) { + src += nblocks * AES_BLOCK_SIZE; + dst += nblocks * AES_BLOCK_SIZE; + break; + } + + kernel_neon_end(); + + err = skcipher_walk_done(&walk, + walk.nbytes % AES_BLOCK_SIZE); + if (err) + return err; + + src = walk.src.virt.addr; + dst = walk.dst.virt.addr; + + kernel_neon_begin(); + } + + lengths.a = cpu_to_be64(assoclen * 8); + lengths.b = cpu_to_be64((req->cryptlen - authsize) * 8); + + tag = (u8 *)&lengths; + tail = walk.nbytes % AES_BLOCK_SIZE; + + if (unlikely(tail && (tail == walk.nbytes || src != dst))) + src = memcpy(buf + sizeof(buf) - tail, src, tail); + + ret = pmull_gcm_dec_final(tail, dg, tag, ctx, (u8 *)src, iv, + ctx->rounds, counter, otag, authsize); + kernel_neon_end(); + + if (unlikely(tail && src != dst)) + memcpy(dst, src, tail); + + if (walk.nbytes) { + err = skcipher_walk_done(&walk, 0); + if (err) + return err; + } + + return ret ? -EBADMSG : 0; +} + +static int gcm_aes_encrypt(struct aead_request *req) +{ + return gcm_encrypt(req, req->iv, req->assoclen); +} + +static int gcm_aes_decrypt(struct aead_request *req) +{ + return gcm_decrypt(req, req->iv, req->assoclen); +} + +static int rfc4106_setkey(struct crypto_aead *tfm, const u8 *inkey, + unsigned int keylen) +{ + struct gcm_key *ctx = crypto_aead_ctx(tfm); + int err; + + keylen -= RFC4106_NONCE_SIZE; + err = gcm_aes_setkey(tfm, inkey, keylen); + if (err) + return err; + + memcpy(ctx->nonce, inkey + keylen, RFC4106_NONCE_SIZE); + return 0; +} + +static int rfc4106_setauthsize(struct crypto_aead *tfm, unsigned int authsize) +{ + return crypto_rfc4106_check_authsize(authsize); +} + +static int rfc4106_encrypt(struct aead_request *req) +{ + struct crypto_aead *aead = crypto_aead_reqtfm(req); + struct gcm_key *ctx = crypto_aead_ctx(aead); + u8 iv[GCM_AES_IV_SIZE]; + + memcpy(iv, ctx->nonce, RFC4106_NONCE_SIZE); + memcpy(iv + RFC4106_NONCE_SIZE, req->iv, GCM_RFC4106_IV_SIZE); + + return crypto_ipsec_check_assoclen(req->assoclen) ?: + gcm_encrypt(req, iv, req->assoclen - GCM_RFC4106_IV_SIZE); +} + +static int rfc4106_decrypt(struct aead_request *req) +{ + struct crypto_aead *aead = crypto_aead_reqtfm(req); + struct gcm_key *ctx = crypto_aead_ctx(aead); + u8 iv[GCM_AES_IV_SIZE]; + + memcpy(iv, ctx->nonce, RFC4106_NONCE_SIZE); + memcpy(iv + RFC4106_NONCE_SIZE, req->iv, GCM_RFC4106_IV_SIZE); + + return crypto_ipsec_check_assoclen(req->assoclen) ?: + gcm_decrypt(req, iv, req->assoclen - GCM_RFC4106_IV_SIZE); +} + +static struct aead_alg gcm_aes_algs[] = {{ + .ivsize = GCM_AES_IV_SIZE, + .chunksize = AES_BLOCK_SIZE, + .maxauthsize = AES_BLOCK_SIZE, + .setkey = gcm_aes_setkey, + .setauthsize = gcm_aes_setauthsize, + .encrypt = gcm_aes_encrypt, + .decrypt = gcm_aes_decrypt, + + .base.cra_name = "gcm(aes)", + .base.cra_driver_name = "gcm-aes-ce", + .base.cra_priority = 400, + .base.cra_blocksize = 1, + .base.cra_ctxsize = sizeof(struct gcm_key), + .base.cra_module = THIS_MODULE, +}, { + .ivsize = GCM_RFC4106_IV_SIZE, + .chunksize = AES_BLOCK_SIZE, + .maxauthsize = AES_BLOCK_SIZE, + .setkey = rfc4106_setkey, + .setauthsize = rfc4106_setauthsize, + .encrypt = rfc4106_encrypt, + .decrypt = rfc4106_decrypt, + + .base.cra_name = "rfc4106(gcm(aes))", + .base.cra_driver_name = "rfc4106-gcm-aes-ce", + .base.cra_priority = 400, + .base.cra_blocksize = 1, + .base.cra_ctxsize = sizeof(struct gcm_key) + RFC4106_NONCE_SIZE, + .base.cra_module = THIS_MODULE, +}}; + static int __init ghash_ce_mod_init(void) { int err; @@ -352,13 +756,17 @@ static int __init ghash_ce_mod_init(void) return -ENODEV; if (elf_hwcap2 & HWCAP2_PMULL) { + err = crypto_register_aeads(gcm_aes_algs, + ARRAY_SIZE(gcm_aes_algs)); + if (err) + return err; ghash_alg.base.cra_ctxsize += 3 * sizeof(u64[2]); static_branch_enable(&use_p64); } err = crypto_register_shash(&ghash_alg); if (err) - return err; + goto err_aead; err = crypto_register_ahash(&ghash_async_alg); if (err) goto err_shash; @@ -367,6 +775,10 @@ static int __init ghash_ce_mod_init(void) err_shash: crypto_unregister_shash(&ghash_alg); +err_aead: + if (elf_hwcap2 & HWCAP2_PMULL) + crypto_unregister_aeads(gcm_aes_algs, + ARRAY_SIZE(gcm_aes_algs)); return err; } @@ -374,6 +786,9 @@ static void __exit ghash_ce_mod_exit(void) { crypto_unregister_ahash(&ghash_async_alg); crypto_unregister_shash(&ghash_alg); + if (elf_hwcap2 & HWCAP2_PMULL) + crypto_unregister_aeads(gcm_aes_algs, + ARRAY_SIZE(gcm_aes_algs)); } module_init(ghash_ce_mod_init); diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h index f82a819eb0dbb49b54e64bd4b3cb3d506316212b..311e83038bdb374afcbb43ac74bba432abc943e6 100644 --- a/arch/arm/include/asm/arch_gicv3.h +++ b/arch/arm/include/asm/arch_gicv3.h @@ -252,5 +252,10 @@ static inline void gic_arch_enable_irqs(void) WARN_ON_ONCE(true); } +static inline bool gic_has_relaxed_pmr_sync(void) +{ + return false; +} + #endif /* !__ASSEMBLY__ */ #endif /* !__ASM_ARCH_GICV3_H */ diff --git a/arch/arm/include/asm/assembler.h b/arch/arm/include/asm/assembler.h index 28e18f79c300fd2ebc4d8b61770fdef8203c7dbc..06b48ce23e1ca245fb87d68d6a26213d6bff6dd5 100644 --- a/arch/arm/include/asm/assembler.h +++ b/arch/arm/include/asm/assembler.h @@ -236,21 +236,26 @@ THUMB( fpreg .req r7 ) sub \tmp, \tmp, #1 @ decrement it str \tmp, [\ti, #TI_PREEMPT] .endm - - .macro dec_preempt_count_ti, ti, tmp - get_thread_info \ti - dec_preempt_count \ti, \tmp - .endm #else .macro inc_preempt_count, ti, tmp .endm .macro dec_preempt_count, ti, tmp .endm +#endif + + .macro local_bh_disable, ti, tmp + ldr \tmp, [\ti, #TI_PREEMPT] + add \tmp, \tmp, #SOFTIRQ_DISABLE_OFFSET + str \tmp, [\ti, #TI_PREEMPT] + .endm - .macro dec_preempt_count_ti, ti, tmp + .macro local_bh_enable_ti, ti, tmp + get_thread_info \ti + ldr \tmp, [\ti, #TI_PREEMPT] + sub \tmp, \tmp, #SOFTIRQ_DISABLE_OFFSET + str \tmp, [\ti, #TI_PREEMPT] .endm -#endif #define USERL(l, x...) \ 9999: x; \ diff --git a/arch/arm/include/asm/simd.h b/arch/arm/include/asm/simd.h new file mode 100644 index 0000000000000000000000000000000000000000..82191dbd7e78a036423e0e1518dca767c536cb86 --- /dev/null +++ b/arch/arm/include/asm/simd.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0 */ + +#include + +static __must_check inline bool may_use_simd(void) +{ + return IS_ENABLED(CONFIG_KERNEL_MODE_NEON) && !in_hardirq(); +} diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h index aecc403b2880493d6925eed075bf405b77ee03cb..7f092cb55a4171548da8e4df3c72708512df9264 100644 --- a/arch/arm/include/asm/thread_info.h +++ b/arch/arm/include/asm/thread_info.h @@ -128,15 +128,16 @@ extern int vfp_restore_user_hwstate(struct user_vfp *, #define TIF_NEED_RESCHED 1 /* rescheduling necessary */ #define TIF_NOTIFY_RESUME 2 /* callback before returning to user */ #define TIF_UPROBE 3 /* breakpointed or singlestepping */ -#define TIF_SYSCALL_TRACE 4 /* syscall trace active */ -#define TIF_SYSCALL_AUDIT 5 /* syscall auditing active */ -#define TIF_SYSCALL_TRACEPOINT 6 /* syscall tracepoint instrumentation */ -#define TIF_SECCOMP 7 /* seccomp syscall filtering active */ -#define TIF_NOTIFY_SIGNAL 8 /* signal notifications exist */ +#define TIF_NOTIFY_SIGNAL 4 /* signal notifications exist */ #define TIF_USING_IWMMXT 17 #define TIF_MEMDIE 18 /* is terminating due to OOM killer */ -#define TIF_RESTORE_SIGMASK 20 +#define TIF_RESTORE_SIGMASK 19 +#define TIF_SYSCALL_TRACE 20 /* syscall trace active */ +#define TIF_SYSCALL_AUDIT 21 /* syscall auditing active */ +#define TIF_SYSCALL_TRACEPOINT 22 /* syscall tracepoint instrumentation */ +#define TIF_SECCOMP 23 /* seccomp syscall filtering active */ + #define _TIF_SIGPENDING (1 << TIF_SIGPENDING) #define _TIF_NEED_RESCHED (1 << TIF_NEED_RESCHED) diff --git a/arch/arm/include/asm/vmlinux.lds.h b/arch/arm/include/asm/vmlinux.lds.h index fad45c884e98890b4958ec9f71d377d14b0d4173..4c8632d5c432c3c7e9351ebae65a90ee9a4c31db 100644 --- a/arch/arm/include/asm/vmlinux.lds.h +++ b/arch/arm/include/asm/vmlinux.lds.h @@ -96,7 +96,6 @@ SOFTIRQENTRY_TEXT \ TEXT_TEXT \ SCHED_TEXT \ - CPUIDLE_TEXT \ LOCK_TEXT \ KPROBES_TEXT \ ARM_STUBS_TEXT \ diff --git a/arch/arm/include/debug/s3c24xx.S b/arch/arm/include/debug/s3c24xx.S index af873b5266778be070b0fde8cf3cbfd34debdad1..7ab5e577cd42283b80aac1e7a1962c056564364f 100644 --- a/arch/arm/include/debug/s3c24xx.S +++ b/arch/arm/include/debug/s3c24xx.S @@ -28,16 +28,6 @@ and \rd, \rd, #S3C2410_UFSTAT_TXMASK .endm -/* Select the correct implementation depending on the configuration. The - * S3C2440 will get selected by default, as these are the most widely - * used variants of these -*/ - -#if defined(CONFIG_DEBUG_S3C2410_UART) -#define fifo_full fifo_full_s3c2410 -#define fifo_level fifo_level_s3c2410 -#endif - /* include the reset of the code which will do the work */ #include diff --git a/arch/arm/kernel/asm-offsets.c b/arch/arm/kernel/asm-offsets.c index 2c8d76fd7c66298ad2fd8c10d471953fc930ad1c..38121c59cbc26cdd51afc30e3593b909e3890c18 100644 --- a/arch/arm/kernel/asm-offsets.c +++ b/arch/arm/kernel/asm-offsets.c @@ -56,6 +56,7 @@ int main(void) DEFINE(VFP_CPU, offsetof(union vfp_state, hard.cpu)); #endif #endif + DEFINE(SOFTIRQ_DISABLE_OFFSET,SOFTIRQ_DISABLE_OFFSET); #ifdef CONFIG_ARM_THUMBEE DEFINE(TI_THUMBEE_STATE, offsetof(struct thread_info, thumbee_state)); #endif diff --git a/arch/arm/kernel/cpuidle.c b/arch/arm/kernel/cpuidle.c index e1684623e1b2d8a0aaae7d7477ce05fe8a890983..437ff39f7808d13292efa05ec4bddcd5e1a7e103 100644 --- a/arch/arm/kernel/cpuidle.c +++ b/arch/arm/kernel/cpuidle.c @@ -26,8 +26,8 @@ static struct cpuidle_ops cpuidle_ops[NR_CPUS] __ro_after_init; * * Returns the index passed as parameter */ -int arm_cpuidle_simple_enter(struct cpuidle_device *dev, - struct cpuidle_driver *drv, int index) +__cpuidle int arm_cpuidle_simple_enter(struct cpuidle_device *dev, struct + cpuidle_driver *drv, int index) { cpu_do_idle(); diff --git a/arch/arm/kernel/entry-common.S b/arch/arm/kernel/entry-common.S index 405a607b754f4dd78627723661d2ab8d1b834e69..03d4c5578c5c98481539afb942565f7af0c0859f 100644 --- a/arch/arm/kernel/entry-common.S +++ b/arch/arm/kernel/entry-common.S @@ -16,15 +16,6 @@ .equ NR_syscalls, __NR_syscalls - .macro arch_ret_to_user, tmp -#ifdef CONFIG_ARCH_IOP32X - mrc p15, 0, \tmp, c15, c1, 0 - tst \tmp, #(1 << 6) - bicne \tmp, \tmp, #(1 << 6) - mcrne p15, 0, \tmp, c15, c1, 0 @ Disable cp6 access -#endif - .endm - #include "entry-header.S" saved_psr .req r8 @@ -55,10 +46,6 @@ __ret_fast_syscall: movs r1, r1, lsl #16 bne fast_work_pending - - /* perform architecture specific actions before user return */ - arch_ret_to_user r1 - restore_user_regs fast = 1, offset = S_OFF UNWIND(.fnend ) ENDPROC(ret_fast_syscall) @@ -129,8 +116,6 @@ ENTRY(ret_to_user_from_irq) no_work_pending: asm_trace_hardirqs_on save = 0 - /* perform architecture specific actions before user return */ - arch_ret_to_user r1 ct_user_enter save = 0 restore_user_regs fast = 0, offset = 0 diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S index 29e2900178a1f4c70888fc9e8164924b59a8821c..656991055bc17bc422e4084e990847b27d6cd324 100644 --- a/arch/arm/kernel/head.S +++ b/arch/arm/kernel/head.S @@ -344,7 +344,7 @@ __create_page_tables: ldr r7, [r10, #PROCINFO_IO_MMUFLAGS] @ io_mmuflags #endif -#if defined(CONFIG_ARCH_NETWINDER) || defined(CONFIG_ARCH_CATS) +#if defined(CONFIG_ARCH_NETWINDER) /* * If we're using the NetWinder or CATS, we also need to map * in the 16550-type serial port for the debug messages diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c index f811733a8fc574b4d178b93fd1e4d128601c25ac..c81e7be2b4eab32e29b89014d479e0370bcb9225 100644 --- a/arch/arm/kernel/process.c +++ b/arch/arm/kernel/process.c @@ -78,7 +78,6 @@ void arch_cpu_idle(void) arm_pm_idle(); else cpu_do_idle(); - raw_local_irq_enable(); } void arch_cpu_idle_prepare(void) diff --git a/arch/arm/kernel/smp.c b/arch/arm/kernel/smp.c index 36e6efad89f309076ef124f6ef139483ea6cccb1..0b8c25763adc3810fcfa99465a97718be6e7f7e7 100644 --- a/arch/arm/kernel/smp.c +++ b/arch/arm/kernel/smp.c @@ -638,7 +638,7 @@ static void do_handle_IPI(int ipinr) unsigned int cpu = smp_processor_id(); if ((unsigned)ipinr < NR_IPI) - trace_ipi_entry_rcuidle(ipi_types[ipinr]); + trace_ipi_entry(ipi_types[ipinr]); switch (ipinr) { case IPI_WAKEUP: @@ -685,7 +685,7 @@ static void do_handle_IPI(int ipinr) } if ((unsigned)ipinr < NR_IPI) - trace_ipi_exit_rcuidle(ipi_types[ipinr]); + trace_ipi_exit(ipi_types[ipinr]); } /* Legacy version, should go away once all irqchips have been converted */ @@ -708,7 +708,7 @@ static irqreturn_t ipi_handler(int irq, void *data) static void smp_cross_call(const struct cpumask *target, unsigned int ipinr) { - trace_ipi_raise_rcuidle(target, ipi_types[ipinr]); + trace_ipi_raise(target, ipi_types[ipinr]); __ipi_send_mask(ipi_desc[ipinr], target); } diff --git a/arch/arm/kernel/sys_oabi-compat.c b/arch/arm/kernel/sys_oabi-compat.c index 68112c172025c7a66fdebc8a32e8078f266beed9..006163195d67e486b9c7a3debc0d8626e53d6dfb 100644 --- a/arch/arm/kernel/sys_oabi-compat.c +++ b/arch/arm/kernel/sys_oabi-compat.c @@ -73,6 +73,7 @@ #include #include #include +#include #include #include #include diff --git a/arch/arm/mach-bcm/bcm63xx_smp.c b/arch/arm/mach-bcm/bcm63xx_smp.c index 641e1f8fcf5e7c9b92bc205f5a2414a7f67c1a2a..18d0ffc621aa98c099d06ea9bcd3ce518cbcc5b9 100644 --- a/arch/arm/mach-bcm/bcm63xx_smp.c +++ b/arch/arm/mach-bcm/bcm63xx_smp.c @@ -142,8 +142,7 @@ static int bcm63138_smp_boot_secondary(unsigned int cpu, */ ret = bcm63xx_pmb_power_on_cpu(dn); of_node_put(dn); - if (ret) - goto out; + out: iounmap(bootlut_base); diff --git a/arch/arm/mach-cns3xxx/Kconfig b/arch/arm/mach-cns3xxx/Kconfig deleted file mode 100644 index 1f85deff248637b54c2d53997fbf3686714c1c05..0000000000000000000000000000000000000000 --- a/arch/arm/mach-cns3xxx/Kconfig +++ /dev/null @@ -1,21 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -menuconfig ARCH_CNS3XXX - bool "Cavium Networks CNS3XXX family" - depends on ARCH_MULTI_V6 - depends on ATAGS && UNUSED_BOARD_FILES - select ARM_GIC - help - Support for Cavium Networks CNS3XXX platform. - -if ARCH_CNS3XXX - -config MACH_CNS3420VB - bool "Support for CNS3420 Validation Board" - depends on ATAGS - help - Include support for the Cavium Networks CNS3420 MPCore Platform - Baseboard. - This is a platform with an on-board ARM11 MPCore and has support - for USB, USB-OTG, MMC/SD/SDIO, SATA, PCI-E, etc. - -endif diff --git a/arch/arm/mach-cns3xxx/Makefile b/arch/arm/mach-cns3xxx/Makefile deleted file mode 100644 index 52ca6ed62304673dbf13c92d9c009cac1d750cdb..0000000000000000000000000000000000000000 --- a/arch/arm/mach-cns3xxx/Makefile +++ /dev/null @@ -1,6 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -obj-$(CONFIG_ARCH_CNS3XXX) += cns3xxx.o -cns3xxx-y += core.o pm.o -cns3xxx-$(CONFIG_ATAGS) += devices.o -cns3xxx-$(CONFIG_PCI) += pcie.o -cns3xxx-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o diff --git a/arch/arm/mach-cns3xxx/cns3420vb.c b/arch/arm/mach-cns3xxx/cns3420vb.c deleted file mode 100644 index 9099560aa4621ba6ed47bb9877d57e1e9fe10c5d..0000000000000000000000000000000000000000 --- a/arch/arm/mach-cns3xxx/cns3420vb.c +++ /dev/null @@ -1,252 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Cavium Networks CNS3420 Validation Board - * - * Copyright 2000 Deep Blue Solutions Ltd - * Copyright 2008 ARM Limited - * Copyright 2008 Cavium Networks - * Scott Shu - * Copyright 2010 MontaVista Software, LLC. - * Anton Vorontsov - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "cns3xxx.h" -#include "pm.h" -#include "core.h" -#include "devices.h" - -/* - * NOR Flash - */ -static struct mtd_partition cns3420_nor_partitions[] = { - { - .name = "uboot", - .size = 0x00040000, - .offset = 0, - .mask_flags = MTD_WRITEABLE, - }, { - .name = "kernel", - .size = 0x004C0000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "filesystem", - .size = 0x7000000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "filesystem2", - .size = 0x0AE0000, - .offset = MTDPART_OFS_APPEND, - }, { - .name = "ubootenv", - .size = MTDPART_SIZ_FULL, - .offset = MTDPART_OFS_APPEND, - }, -}; - -static struct physmap_flash_data cns3420_nor_pdata = { - .width = 2, - .parts = cns3420_nor_partitions, - .nr_parts = ARRAY_SIZE(cns3420_nor_partitions), -}; - -static struct resource cns3420_nor_res = { - .start = CNS3XXX_FLASH_BASE, - .end = CNS3XXX_FLASH_BASE + SZ_128M - 1, - .flags = IORESOURCE_MEM | IORESOURCE_MEM_32BIT, -}; - -static struct platform_device cns3420_nor_pdev = { - .name = "physmap-flash", - .id = 0, - .resource = &cns3420_nor_res, - .num_resources = 1, - .dev = { - .platform_data = &cns3420_nor_pdata, - }, -}; - -/* - * UART - */ -static void __init cns3420_early_serial_setup(void) -{ -#ifdef CONFIG_SERIAL_8250_CONSOLE - static struct uart_port cns3420_serial_port = { - .membase = (void __iomem *)CNS3XXX_UART0_BASE_VIRT, - .mapbase = CNS3XXX_UART0_BASE, - .irq = IRQ_CNS3XXX_UART0, - .iotype = UPIO_MEM, - .flags = UPF_BOOT_AUTOCONF | UPF_FIXED_TYPE, - .regshift = 2, - .uartclk = 24000000, - .line = 0, - .type = PORT_16550A, - .fifosize = 16, - }; - - early_serial_setup(&cns3420_serial_port); -#endif -} - -/* - * USB - */ -static struct resource cns3xxx_usb_ehci_resources[] = { - [0] = { - .start = CNS3XXX_USB_BASE, - .end = CNS3XXX_USB_BASE + SZ_16M - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CNS3XXX_USB_EHCI, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 cns3xxx_usb_ehci_dma_mask = DMA_BIT_MASK(32); - -static int csn3xxx_usb_power_on(struct platform_device *pdev) -{ - /* - * EHCI and OHCI share the same clock and power, - * resetting twice would cause the 1st controller been reset. - * Therefore only do power up at the first up device, and - * power down at the last down device. - * - * Set USB AHB INCR length to 16 - */ - if (atomic_inc_return(&usb_pwr_ref) == 1) { - cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); - cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); - cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); - __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), - MISC_CHIP_CONFIG_REG); - } - - return 0; -} - -static void csn3xxx_usb_power_off(struct platform_device *pdev) -{ - /* - * EHCI and OHCI share the same clock and power, - * resetting twice would cause the 1st controller been reset. - * Therefore only do power up at the first up device, and - * power down at the last down device. - */ - if (atomic_dec_return(&usb_pwr_ref) == 0) - cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); -} - -static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = { - .power_on = csn3xxx_usb_power_on, - .power_off = csn3xxx_usb_power_off, -}; - -static struct platform_device cns3xxx_usb_ehci_device = { - .name = "ehci-platform", - .num_resources = ARRAY_SIZE(cns3xxx_usb_ehci_resources), - .resource = cns3xxx_usb_ehci_resources, - .dev = { - .dma_mask = &cns3xxx_usb_ehci_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &cns3xxx_usb_ehci_pdata, - }, -}; - -static struct resource cns3xxx_usb_ohci_resources[] = { - [0] = { - .start = CNS3XXX_USB_OHCI_BASE, - .end = CNS3XXX_USB_OHCI_BASE + SZ_16M - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CNS3XXX_USB_OHCI, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 cns3xxx_usb_ohci_dma_mask = DMA_BIT_MASK(32); - -static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = { - .num_ports = 1, - .power_on = csn3xxx_usb_power_on, - .power_off = csn3xxx_usb_power_off, -}; - -static struct platform_device cns3xxx_usb_ohci_device = { - .name = "ohci-platform", - .num_resources = ARRAY_SIZE(cns3xxx_usb_ohci_resources), - .resource = cns3xxx_usb_ohci_resources, - .dev = { - .dma_mask = &cns3xxx_usb_ohci_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - .platform_data = &cns3xxx_usb_ohci_pdata, - }, -}; - -/* - * Initialization - */ -static struct platform_device *cns3420_pdevs[] __initdata = { - &cns3420_nor_pdev, - &cns3xxx_usb_ehci_device, - &cns3xxx_usb_ohci_device, -}; - -static void __init cns3420_init(void) -{ - cns3xxx_l2x0_init(); - - platform_add_devices(cns3420_pdevs, ARRAY_SIZE(cns3420_pdevs)); - - cns3xxx_ahci_init(); - cns3xxx_sdhci_init(); - - pm_power_off = cns3xxx_power_off; -} - -static struct map_desc cns3420_io_desc[] __initdata = { - { - .virtual = CNS3XXX_UART0_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_UART0_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, -}; - -static void __init cns3420_map_io(void) -{ - cns3xxx_map_io(); - iotable_init(cns3420_io_desc, ARRAY_SIZE(cns3420_io_desc)); - - cns3420_early_serial_setup(); -} - -MACHINE_START(CNS3420VB, "Cavium Networks CNS3420 Validation Board") - .atag_offset = 0x100, - .map_io = cns3420_map_io, - .init_irq = cns3xxx_init_irq, - .init_time = cns3xxx_timer_init, - .init_machine = cns3420_init, - .init_late = cns3xxx_pcie_init_late, - .restart = cns3xxx_restart, -MACHINE_END diff --git a/arch/arm/mach-cns3xxx/cns3xxx.h b/arch/arm/mach-cns3xxx/cns3xxx.h deleted file mode 100644 index cbb105a74f9078017cdd3e995480d81f6ed490bf..0000000000000000000000000000000000000000 --- a/arch/arm/mach-cns3xxx/cns3xxx.h +++ /dev/null @@ -1,593 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2008 Cavium Networks - */ - -#ifndef __MACH_BOARD_CNS3XXXH -#define __MACH_BOARD_CNS3XXXH - -/* - * Memory map - */ -#define CNS3XXX_FLASH_BASE 0x10000000 /* Flash/SRAM Memory Bank 0 */ -#define CNS3XXX_FLASH_SIZE SZ_256M - -#define CNS3XXX_DDR2SDRAM_BASE 0x20000000 /* DDR2 SDRAM Memory */ - -#define CNS3XXX_SPI_FLASH_BASE 0x60000000 /* SPI Serial Flash Memory */ - -#define CNS3XXX_SWITCH_BASE 0x70000000 /* Switch and HNAT Control */ - -#define CNS3XXX_PPE_BASE 0x70001000 /* HANT */ - -#define CNS3XXX_EMBEDDED_SRAM_BASE 0x70002000 /* HANT Embedded SRAM */ - -#define CNS3XXX_SSP_BASE 0x71000000 /* Synchronous Serial Port - SPI/PCM/I2C */ - -#define CNS3XXX_DMC_BASE 0x72000000 /* DMC Control (DDR2 SDRAM) */ - -#define CNS3XXX_SMC_BASE 0x73000000 /* SMC Control */ - -#define SMC_MEMC_STATUS_OFFSET 0x000 -#define SMC_MEMIF_CFG_OFFSET 0x004 -#define SMC_MEMC_CFG_SET_OFFSET 0x008 -#define SMC_MEMC_CFG_CLR_OFFSET 0x00C -#define SMC_DIRECT_CMD_OFFSET 0x010 -#define SMC_SET_CYCLES_OFFSET 0x014 -#define SMC_SET_OPMODE_OFFSET 0x018 -#define SMC_REFRESH_PERIOD_0_OFFSET 0x020 -#define SMC_REFRESH_PERIOD_1_OFFSET 0x024 -#define SMC_SRAM_CYCLES0_0_OFFSET 0x100 -#define SMC_NAND_CYCLES0_0_OFFSET 0x100 -#define SMC_OPMODE0_0_OFFSET 0x104 -#define SMC_SRAM_CYCLES0_1_OFFSET 0x120 -#define SMC_NAND_CYCLES0_1_OFFSET 0x120 -#define SMC_OPMODE0_1_OFFSET 0x124 -#define SMC_USER_STATUS_OFFSET 0x200 -#define SMC_USER_CONFIG_OFFSET 0x204 -#define SMC_ECC_STATUS_OFFSET 0x300 -#define SMC_ECC_MEMCFG_OFFSET 0x304 -#define SMC_ECC_MEMCOMMAND1_OFFSET 0x308 -#define SMC_ECC_MEMCOMMAND2_OFFSET 0x30C -#define SMC_ECC_ADDR0_OFFSET 0x310 -#define SMC_ECC_ADDR1_OFFSET 0x314 -#define SMC_ECC_VALUE0_OFFSET 0x318 -#define SMC_ECC_VALUE1_OFFSET 0x31C -#define SMC_ECC_VALUE2_OFFSET 0x320 -#define SMC_ECC_VALUE3_OFFSET 0x324 -#define SMC_PERIPH_ID_0_OFFSET 0xFE0 -#define SMC_PERIPH_ID_1_OFFSET 0xFE4 -#define SMC_PERIPH_ID_2_OFFSET 0xFE8 -#define SMC_PERIPH_ID_3_OFFSET 0xFEC -#define SMC_PCELL_ID_0_OFFSET 0xFF0 -#define SMC_PCELL_ID_1_OFFSET 0xFF4 -#define SMC_PCELL_ID_2_OFFSET 0xFF8 -#define SMC_PCELL_ID_3_OFFSET 0xFFC - -#define CNS3XXX_GPIOA_BASE 0x74000000 /* GPIO port A */ - -#define CNS3XXX_GPIOB_BASE 0x74800000 /* GPIO port B */ - -#define CNS3XXX_RTC_BASE 0x75000000 /* Real Time Clock */ - -#define RTC_SEC_OFFSET 0x00 -#define RTC_MIN_OFFSET 0x04 -#define RTC_HOUR_OFFSET 0x08 -#define RTC_DAY_OFFSET 0x0C -#define RTC_SEC_ALM_OFFSET 0x10 -#define RTC_MIN_ALM_OFFSET 0x14 -#define RTC_HOUR_ALM_OFFSET 0x18 -#define RTC_REC_OFFSET 0x1C -#define RTC_CTRL_OFFSET 0x20 -#define RTC_INTR_STS_OFFSET 0x34 - -#define CNS3XXX_MISC_BASE 0x76000000 /* Misc Control */ -#define CNS3XXX_MISC_BASE_VIRT 0xFB000000 /* Misc Control */ - -#define CNS3XXX_PM_BASE 0x77000000 /* Power Management Control */ -#define CNS3XXX_PM_BASE_VIRT 0xFB001000 - -#define PM_CLK_GATE_OFFSET 0x00 -#define PM_SOFT_RST_OFFSET 0x04 -#define PM_HS_CFG_OFFSET 0x08 -#define PM_CACTIVE_STA_OFFSET 0x0C -#define PM_PWR_STA_OFFSET 0x10 -#define PM_SYS_CLK_CTRL_OFFSET 0x14 -#define PM_PLL_LCD_I2S_CTRL_OFFSET 0x18 -#define PM_PLL_HM_PD_OFFSET 0x1C - -#define CNS3XXX_UART0_BASE 0x78000000 /* UART 0 */ -#define CNS3XXX_UART0_BASE_VIRT 0xFB002000 - -#define CNS3XXX_UART1_BASE 0x78400000 /* UART 1 */ - -#define CNS3XXX_UART2_BASE 0x78800000 /* UART 2 */ - -#define CNS3XXX_DMAC_BASE 0x79000000 /* Generic DMA Control */ - -#define CNS3XXX_CORESIGHT_BASE 0x7A000000 /* CoreSight */ - -#define CNS3XXX_CRYPTO_BASE 0x7B000000 /* Crypto */ - -#define CNS3XXX_I2S_BASE 0x7C000000 /* I2S */ - -#define CNS3XXX_TIMER1_2_3_BASE 0x7C800000 /* Timer */ -#define CNS3XXX_TIMER1_2_3_BASE_VIRT 0xFB003000 - -#define TIMER1_COUNTER_OFFSET 0x00 -#define TIMER1_AUTO_RELOAD_OFFSET 0x04 -#define TIMER1_MATCH_V1_OFFSET 0x08 -#define TIMER1_MATCH_V2_OFFSET 0x0C - -#define TIMER2_COUNTER_OFFSET 0x10 -#define TIMER2_AUTO_RELOAD_OFFSET 0x14 -#define TIMER2_MATCH_V1_OFFSET 0x18 -#define TIMER2_MATCH_V2_OFFSET 0x1C - -#define TIMER1_2_CONTROL_OFFSET 0x30 -#define TIMER1_2_INTERRUPT_STATUS_OFFSET 0x34 -#define TIMER1_2_INTERRUPT_MASK_OFFSET 0x38 - -#define TIMER_FREERUN_OFFSET 0x40 -#define TIMER_FREERUN_CONTROL_OFFSET 0x44 - -#define CNS3XXX_HCIE_BASE 0x7D000000 /* HCIE Control */ - -#define CNS3XXX_RAID_BASE 0x7E000000 /* RAID Control */ - -#define CNS3XXX_AXI_IXC_BASE 0x7F000000 /* AXI IXC */ - -#define CNS3XXX_CLCD_BASE 0x80000000 /* LCD Control */ - -#define CNS3XXX_USBOTG_BASE 0x81000000 /* USB OTG Control */ - -#define CNS3XXX_USB_BASE 0x82000000 /* USB Host Control */ - -#define CNS3XXX_SATA2_BASE 0x83000000 /* SATA */ -#define CNS3XXX_SATA2_SIZE SZ_16M - -#define CNS3XXX_CAMERA_BASE 0x84000000 /* Camera Interface */ - -#define CNS3XXX_SDIO_BASE 0x85000000 /* SDIO */ - -#define CNS3XXX_I2S_TDM_BASE 0x86000000 /* I2S TDM */ - -#define CNS3XXX_2DG_BASE 0x87000000 /* 2D Graphic Control */ - -#define CNS3XXX_USB_OHCI_BASE 0x88000000 /* USB OHCI */ - -#define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */ - -#define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */ - -#define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */ -#define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000 - -#define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */ - -#define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */ -#define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000 - -#define CNS3XXX_PCIE0_CFG1_BASE 0xAE000000 /* PCIe Port 0 CFG Type 1 */ -#define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000 - -#define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */ - -#define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */ - -#define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */ -#define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000 - -#define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */ - -#define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */ -#define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000 - -#define CNS3XXX_PCIE1_CFG1_BASE 0xBE000000 /* PCIe Port 1 CFG Type 1 */ -#define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000 - -#define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */ - -/* - * Testchip peripheral and fpga gic regions - */ -#define CNS3XXX_TC11MP_SCU_BASE 0x90000000 /* IRQ, Test chip */ -#define CNS3XXX_TC11MP_SCU_BASE_VIRT 0xFB004000 - -#define CNS3XXX_TC11MP_GIC_CPU_BASE 0x90000100 /* Test chip interrupt controller CPU interface */ -#define CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x100) - -#define CNS3XXX_TC11MP_TWD_BASE 0x90000600 -#define CNS3XXX_TC11MP_TWD_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x600) - -#define CNS3XXX_TC11MP_GIC_DIST_BASE 0x90001000 /* Test chip interrupt controller distributor */ -#define CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT (CNS3XXX_TC11MP_SCU_BASE_VIRT + 0x1000) - -#define CNS3XXX_TC11MP_L220_BASE 0x92002000 /* L220 registers */ - -/* - * Misc block - */ -#define MISC_MEM_MAP(offs) (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + (offs)) - -#define MISC_MEMORY_REMAP_REG MISC_MEM_MAP(0x00) -#define MISC_CHIP_CONFIG_REG MISC_MEM_MAP(0x04) -#define MISC_DEBUG_PROBE_DATA_REG MISC_MEM_MAP(0x08) -#define MISC_DEBUG_PROBE_SELECTION_REG MISC_MEM_MAP(0x0C) -#define MISC_IO_PIN_FUNC_SELECTION_REG MISC_MEM_MAP(0x10) -#define MISC_GPIOA_PIN_ENABLE_REG MISC_MEM_MAP(0x14) -#define MISC_GPIOB_PIN_ENABLE_REG MISC_MEM_MAP(0x18) -#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_A MISC_MEM_MAP(0x1C) -#define MISC_IO_PAD_DRIVE_STRENGTH_CTRL_B MISC_MEM_MAP(0x20) -#define MISC_GPIOA_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x24) -#define MISC_GPIOA_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x28) -#define MISC_GPIOB_15_0_PULL_CTRL_REG MISC_MEM_MAP(0x2C) -#define MISC_GPIOB_16_31_PULL_CTRL_REG MISC_MEM_MAP(0x30) -#define MISC_IO_PULL_CTRL_REG MISC_MEM_MAP(0x34) -#define MISC_E_FUSE_31_0_REG MISC_MEM_MAP(0x40) -#define MISC_E_FUSE_63_32_REG MISC_MEM_MAP(0x44) -#define MISC_E_FUSE_95_64_REG MISC_MEM_MAP(0x48) -#define MISC_E_FUSE_127_96_REG MISC_MEM_MAP(0x4C) -#define MISC_SOFTWARE_TEST_1_REG MISC_MEM_MAP(0x50) -#define MISC_SOFTWARE_TEST_2_REG MISC_MEM_MAP(0x54) - -#define MISC_SATA_POWER_MODE MISC_MEM_MAP(0x310) - -#define MISC_USB_CFG_REG MISC_MEM_MAP(0x800) -#define MISC_USB_STS_REG MISC_MEM_MAP(0x804) -#define MISC_USBPHY00_CFG_REG MISC_MEM_MAP(0x808) -#define MISC_USBPHY01_CFG_REG MISC_MEM_MAP(0x80c) -#define MISC_USBPHY10_CFG_REG MISC_MEM_MAP(0x810) -#define MISC_USBPHY11_CFG_REG MISC_MEM_MAP(0x814) - -#define MISC_PCIEPHY_CMCTL(x) MISC_MEM_MAP(0x900 + (x) * 0x004) -#define MISC_PCIEPHY_CTL(x) MISC_MEM_MAP(0x940 + (x) * 0x100) -#define MISC_PCIE_AXIS_AWMISC(x) MISC_MEM_MAP(0x944 + (x) * 0x100) -#define MISC_PCIE_AXIS_ARMISC(x) MISC_MEM_MAP(0x948 + (x) * 0x100) -#define MISC_PCIE_AXIS_RMISC(x) MISC_MEM_MAP(0x94C + (x) * 0x100) -#define MISC_PCIE_AXIS_BMISC(x) MISC_MEM_MAP(0x950 + (x) * 0x100) -#define MISC_PCIE_AXIM_RMISC(x) MISC_MEM_MAP(0x954 + (x) * 0x100) -#define MISC_PCIE_AXIM_BMISC(x) MISC_MEM_MAP(0x958 + (x) * 0x100) -#define MISC_PCIE_CTRL(x) MISC_MEM_MAP(0x95C + (x) * 0x100) -#define MISC_PCIE_PM_DEBUG(x) MISC_MEM_MAP(0x960 + (x) * 0x100) -#define MISC_PCIE_RFC_DEBUG(x) MISC_MEM_MAP(0x964 + (x) * 0x100) -#define MISC_PCIE_CXPL_DEBUGL(x) MISC_MEM_MAP(0x968 + (x) * 0x100) -#define MISC_PCIE_CXPL_DEBUGH(x) MISC_MEM_MAP(0x96C + (x) * 0x100) -#define MISC_PCIE_DIAG_DEBUGH(x) MISC_MEM_MAP(0x970 + (x) * 0x100) -#define MISC_PCIE_W1CLR(x) MISC_MEM_MAP(0x974 + (x) * 0x100) -#define MISC_PCIE_INT_MASK(x) MISC_MEM_MAP(0x978 + (x) * 0x100) -#define MISC_PCIE_INT_STATUS(x) MISC_MEM_MAP(0x97C + (x) * 0x100) - -/* - * Power management and clock control - */ -#define PMU_MEM_MAP(offs) (void __iomem *)(CNS3XXX_PM_BASE_VIRT + (offs)) - -#define PM_CLK_GATE_REG PMU_MEM_MAP(0x000) -#define PM_SOFT_RST_REG PMU_MEM_MAP(0x004) -#define PM_HS_CFG_REG PMU_MEM_MAP(0x008) -#define PM_CACTIVE_STA_REG PMU_MEM_MAP(0x00C) -#define PM_PWR_STA_REG PMU_MEM_MAP(0x010) -#define PM_CLK_CTRL_REG PMU_MEM_MAP(0x014) -#define PM_PLL_LCD_I2S_CTRL_REG PMU_MEM_MAP(0x018) -#define PM_PLL_HM_PD_CTRL_REG PMU_MEM_MAP(0x01C) -#define PM_REGULAT_CTRL_REG PMU_MEM_MAP(0x020) -#define PM_WDT_CTRL_REG PMU_MEM_MAP(0x024) -#define PM_WU_CTRL0_REG PMU_MEM_MAP(0x028) -#define PM_WU_CTRL1_REG PMU_MEM_MAP(0x02C) -#define PM_CSR_REG PMU_MEM_MAP(0x030) - -/* PM_CLK_GATE_REG */ -#define PM_CLK_GATE_REG_OFFSET_SDIO (25) -#define PM_CLK_GATE_REG_OFFSET_GPU (24) -#define PM_CLK_GATE_REG_OFFSET_CIM (23) -#define PM_CLK_GATE_REG_OFFSET_LCDC (22) -#define PM_CLK_GATE_REG_OFFSET_I2S (21) -#define PM_CLK_GATE_REG_OFFSET_RAID (20) -#define PM_CLK_GATE_REG_OFFSET_SATA (19) -#define PM_CLK_GATE_REG_OFFSET_PCIE(x) (17 + (x)) -#define PM_CLK_GATE_REG_OFFSET_USB_HOST (16) -#define PM_CLK_GATE_REG_OFFSET_USB_OTG (15) -#define PM_CLK_GATE_REG_OFFSET_TIMER (14) -#define PM_CLK_GATE_REG_OFFSET_CRYPTO (13) -#define PM_CLK_GATE_REG_OFFSET_HCIE (12) -#define PM_CLK_GATE_REG_OFFSET_SWITCH (11) -#define PM_CLK_GATE_REG_OFFSET_GPIO (10) -#define PM_CLK_GATE_REG_OFFSET_UART3 (9) -#define PM_CLK_GATE_REG_OFFSET_UART2 (8) -#define PM_CLK_GATE_REG_OFFSET_UART1 (7) -#define PM_CLK_GATE_REG_OFFSET_RTC (5) -#define PM_CLK_GATE_REG_OFFSET_GDMA (4) -#define PM_CLK_GATE_REG_OFFSET_SPI_PCM_I2C (3) -#define PM_CLK_GATE_REG_OFFSET_SMC_NFI (1) -#define PM_CLK_GATE_REG_MASK (0x03FFFFBA) - -/* PM_SOFT_RST_REG */ -#define PM_SOFT_RST_REG_OFFST_WARM_RST_FLAG (31) -#define PM_SOFT_RST_REG_OFFST_CPU1 (29) -#define PM_SOFT_RST_REG_OFFST_CPU0 (28) -#define PM_SOFT_RST_REG_OFFST_SDIO (25) -#define PM_SOFT_RST_REG_OFFST_GPU (24) -#define PM_SOFT_RST_REG_OFFST_CIM (23) -#define PM_SOFT_RST_REG_OFFST_LCDC (22) -#define PM_SOFT_RST_REG_OFFST_I2S (21) -#define PM_SOFT_RST_REG_OFFST_RAID (20) -#define PM_SOFT_RST_REG_OFFST_SATA (19) -#define PM_SOFT_RST_REG_OFFST_PCIE(x) (17 + (x)) -#define PM_SOFT_RST_REG_OFFST_USB_HOST (16) -#define PM_SOFT_RST_REG_OFFST_USB_OTG (15) -#define PM_SOFT_RST_REG_OFFST_TIMER (14) -#define PM_SOFT_RST_REG_OFFST_CRYPTO (13) -#define PM_SOFT_RST_REG_OFFST_HCIE (12) -#define PM_SOFT_RST_REG_OFFST_SWITCH (11) -#define PM_SOFT_RST_REG_OFFST_GPIO (10) -#define PM_SOFT_RST_REG_OFFST_UART3 (9) -#define PM_SOFT_RST_REG_OFFST_UART2 (8) -#define PM_SOFT_RST_REG_OFFST_UART1 (7) -#define PM_SOFT_RST_REG_OFFST_RTC (5) -#define PM_SOFT_RST_REG_OFFST_GDMA (4) -#define PM_SOFT_RST_REG_OFFST_SPI_PCM_I2C (3) -#define PM_SOFT_RST_REG_OFFST_DMC (2) -#define PM_SOFT_RST_REG_OFFST_SMC_NFI (1) -#define PM_SOFT_RST_REG_OFFST_GLOBAL (0) -#define PM_SOFT_RST_REG_MASK (0xF3FFFFBF) - -/* PMHS_CFG_REG */ -#define PM_HS_CFG_REG_OFFSET_SDIO (25) -#define PM_HS_CFG_REG_OFFSET_GPU (24) -#define PM_HS_CFG_REG_OFFSET_CIM (23) -#define PM_HS_CFG_REG_OFFSET_LCDC (22) -#define PM_HS_CFG_REG_OFFSET_I2S (21) -#define PM_HS_CFG_REG_OFFSET_RAID (20) -#define PM_HS_CFG_REG_OFFSET_SATA (19) -#define PM_HS_CFG_REG_OFFSET_PCIE1 (18) -#define PM_HS_CFG_REG_OFFSET_PCIE0 (17) -#define PM_HS_CFG_REG_OFFSET_USB_HOST (16) -#define PM_HS_CFG_REG_OFFSET_USB_OTG (15) -#define PM_HS_CFG_REG_OFFSET_TIMER (14) -#define PM_HS_CFG_REG_OFFSET_CRYPTO (13) -#define PM_HS_CFG_REG_OFFSET_HCIE (12) -#define PM_HS_CFG_REG_OFFSET_SWITCH (11) -#define PM_HS_CFG_REG_OFFSET_GPIO (10) -#define PM_HS_CFG_REG_OFFSET_UART3 (9) -#define PM_HS_CFG_REG_OFFSET_UART2 (8) -#define PM_HS_CFG_REG_OFFSET_UART1 (7) -#define PM_HS_CFG_REG_OFFSET_RTC (5) -#define PM_HS_CFG_REG_OFFSET_GDMA (4) -#define PM_HS_CFG_REG_OFFSET_SPI_PCM_I2S (3) -#define PM_HS_CFG_REG_OFFSET_DMC (2) -#define PM_HS_CFG_REG_OFFSET_SMC_NFI (1) -#define PM_HS_CFG_REG_MASK (0x03FFFFBE) -#define PM_HS_CFG_REG_MASK_SUPPORT (0x01100806) - -/* PM_CACTIVE_STA_REG */ -#define PM_CACTIVE_STA_REG_OFFSET_SDIO (25) -#define PM_CACTIVE_STA_REG_OFFSET_GPU (24) -#define PM_CACTIVE_STA_REG_OFFSET_CIM (23) -#define PM_CACTIVE_STA_REG_OFFSET_LCDC (22) -#define PM_CACTIVE_STA_REG_OFFSET_I2S (21) -#define PM_CACTIVE_STA_REG_OFFSET_RAID (20) -#define PM_CACTIVE_STA_REG_OFFSET_SATA (19) -#define PM_CACTIVE_STA_REG_OFFSET_PCIE1 (18) -#define PM_CACTIVE_STA_REG_OFFSET_PCIE0 (17) -#define PM_CACTIVE_STA_REG_OFFSET_USB_HOST (16) -#define PM_CACTIVE_STA_REG_OFFSET_USB_OTG (15) -#define PM_CACTIVE_STA_REG_OFFSET_TIMER (14) -#define PM_CACTIVE_STA_REG_OFFSET_CRYPTO (13) -#define PM_CACTIVE_STA_REG_OFFSET_HCIE (12) -#define PM_CACTIVE_STA_REG_OFFSET_SWITCH (11) -#define PM_CACTIVE_STA_REG_OFFSET_GPIO (10) -#define PM_CACTIVE_STA_REG_OFFSET_UART3 (9) -#define PM_CACTIVE_STA_REG_OFFSET_UART2 (8) -#define PM_CACTIVE_STA_REG_OFFSET_UART1 (7) -#define PM_CACTIVE_STA_REG_OFFSET_RTC (5) -#define PM_CACTIVE_STA_REG_OFFSET_GDMA (4) -#define PM_CACTIVE_STA_REG_OFFSET_SPI_PCM_I2S (3) -#define PM_CACTIVE_STA_REG_OFFSET_DMC (2) -#define PM_CACTIVE_STA_REG_OFFSET_SMC_NFI (1) -#define PM_CACTIVE_STA_REG_MASK (0x03FFFFBE) - -/* PM_PWR_STA_REG */ -#define PM_PWR_STA_REG_REG_OFFSET_SDIO (25) -#define PM_PWR_STA_REG_REG_OFFSET_GPU (24) -#define PM_PWR_STA_REG_REG_OFFSET_CIM (23) -#define PM_PWR_STA_REG_REG_OFFSET_LCDC (22) -#define PM_PWR_STA_REG_REG_OFFSET_I2S (21) -#define PM_PWR_STA_REG_REG_OFFSET_RAID (20) -#define PM_PWR_STA_REG_REG_OFFSET_SATA (19) -#define PM_PWR_STA_REG_REG_OFFSET_PCIE1 (18) -#define PM_PWR_STA_REG_REG_OFFSET_PCIE0 (17) -#define PM_PWR_STA_REG_REG_OFFSET_USB_HOST (16) -#define PM_PWR_STA_REG_REG_OFFSET_USB_OTG (15) -#define PM_PWR_STA_REG_REG_OFFSET_TIMER (14) -#define PM_PWR_STA_REG_REG_OFFSET_CRYPTO (13) -#define PM_PWR_STA_REG_REG_OFFSET_HCIE (12) -#define PM_PWR_STA_REG_REG_OFFSET_SWITCH (11) -#define PM_PWR_STA_REG_REG_OFFSET_GPIO (10) -#define PM_PWR_STA_REG_REG_OFFSET_UART3 (9) -#define PM_PWR_STA_REG_REG_OFFSET_UART2 (8) -#define PM_PWR_STA_REG_REG_OFFSET_UART1 (7) -#define PM_PWR_STA_REG_REG_OFFSET_RTC (5) -#define PM_PWR_STA_REG_REG_OFFSET_GDMA (4) -#define PM_PWR_STA_REG_REG_OFFSET_SPI_PCM_I2S (3) -#define PM_PWR_STA_REG_REG_OFFSET_DMC (2) -#define PM_PWR_STA_REG_REG_OFFSET_SMC_NFI (1) -#define PM_PWR_STA_REG_REG_MASK (0x03FFFFBE) - -/* PM_CLK_CTRL_REG */ -#define PM_CLK_CTRL_REG_OFFSET_I2S_MCLK (31) -#define PM_CLK_CTRL_REG_OFFSET_DDR2_CHG_EN (30) -#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF1_EN (29) -#define PM_CLK_CTRL_REG_OFFSET_PCIE_REF0_EN (28) -#define PM_CLK_CTRL_REG_OFFSET_TIMER_SIM_MODE (27) -#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_DIV (24) -#define PM_CLK_CTRL_REG_OFFSET_I2SCLK_SEL (22) -#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_DIV (20) -#define PM_CLK_CTRL_REG_OFFSET_CLKOUT_SEL (16) -#define PM_CLK_CTRL_REG_OFFSET_MDC_DIV (14) -#define PM_CLK_CTRL_REG_OFFSET_CRYPTO_CLK_SEL (12) -#define PM_CLK_CTRL_REG_OFFSET_CPU_PWR_MODE (9) -#define PM_CLK_CTRL_REG_OFFSET_PLL_DDR2_SEL (7) -#define PM_CLK_CTRL_REG_OFFSET_DIV_IMMEDIATE (6) -#define PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV (4) -#define PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL (0) - -#define PM_CPU_CLK_DIV(DIV) { \ - PM_CLK_CTRL_REG &= ~((0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \ - PM_CLK_CTRL_REG |= (((DIV)&0x3) << PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV); \ -} - -#define PM_PLL_CPU_SEL(CPU) { \ - PM_CLK_CTRL_REG &= ~((0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \ - PM_CLK_CTRL_REG |= (((CPU)&0xF) << PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL); \ -} - -/* PM_PLL_LCD_I2S_CTRL_REG */ -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_MCLK_SMC_DIV (22) -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_R_SEL (17) -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_P (11) -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_M (3) -#define PM_PLL_LCD_I2S_CTRL_REG_OFFSET_PLL_LCD_S (0) - -/* PM_PLL_HM_PD_CTRL_REG */ -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1 (11) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0 (10) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2SCD (6) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_I2S (5) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_LCD (4) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB (3) -#define PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_RGMII (2) -#define PM_PLL_HM_PD_CTRL_REG_MASK (0x00000C7C) - -/* PM_WDT_CTRL_REG */ -#define PM_WDT_CTRL_REG_OFFSET_RESET_CPU_ONLY (0) - -/* PM_CSR_REG - Clock Scaling Register*/ -#define PM_CSR_REG_OFFSET_CSR_EN (30) -#define PM_CSR_REG_OFFSET_CSR_NUM (0) - -#define CNS3XXX_PWR_CLK_EN(BLOCK) (0x1< -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "cns3xxx.h" -#include "core.h" -#include "pm.h" - -static struct map_desc cns3xxx_io_desc[] __initdata = { - { - .virtual = CNS3XXX_TC11MP_SCU_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_TC11MP_SCU_BASE), - .length = SZ_8K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_TIMER1_2_3_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_TIMER1_2_3_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_MISC_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_MISC_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_PM_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PM_BASE), - .length = SZ_4K, - .type = MT_DEVICE, -#ifdef CONFIG_PCI - }, { - .virtual = CNS3XXX_PCIE0_HOST_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE0_HOST_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_PCIE0_CFG0_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG0_BASE), - .length = SZ_64K, /* really 4 KiB at offset 32 KiB */ - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_PCIE0_CFG1_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE0_CFG1_BASE), - .length = SZ_16M, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_PCIE1_HOST_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE1_HOST_BASE), - .length = SZ_4K, - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_PCIE1_CFG0_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG0_BASE), - .length = SZ_64K, /* really 4 KiB at offset 32 KiB */ - .type = MT_DEVICE, - }, { - .virtual = CNS3XXX_PCIE1_CFG1_BASE_VIRT, - .pfn = __phys_to_pfn(CNS3XXX_PCIE1_CFG1_BASE), - .length = SZ_16M, - .type = MT_DEVICE, -#endif - }, -}; - -void __init cns3xxx_map_io(void) -{ - iotable_init(cns3xxx_io_desc, ARRAY_SIZE(cns3xxx_io_desc)); -} - -/* used by entry-macro.S */ -void __init cns3xxx_init_irq(void) -{ - gic_init(IOMEM(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT), - IOMEM(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT)); -} - -void cns3xxx_power_off(void) -{ - u32 __iomem *pm_base = IOMEM(CNS3XXX_PM_BASE_VIRT); - u32 clkctrl; - - printk(KERN_INFO "powering system down...\n"); - - clkctrl = readl(pm_base + PM_SYS_CLK_CTRL_OFFSET); - clkctrl &= 0xfffff1ff; - clkctrl |= (0x5 << 9); /* Hibernate */ - writel(clkctrl, pm_base + PM_SYS_CLK_CTRL_OFFSET); - -} - -/* - * Timer - */ -static void __iomem *cns3xxx_tmr1; - -static int cns3xxx_shutdown(struct clock_event_device *clk) -{ - writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - return 0; -} - -static int cns3xxx_set_oneshot(struct clock_event_device *clk) -{ - unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - - /* period set, and timer enabled in 'next_event' hook */ - ctrl |= (1 << 2) | (1 << 9); - writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - return 0; -} - -static int cns3xxx_set_periodic(struct clock_event_device *clk) -{ - unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - int pclk = cns3xxx_cpu_clock() / 8; - int reload; - - reload = pclk * 20 / (3 * HZ) * 0x25000; - writel(reload, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); - ctrl |= (1 << 0) | (1 << 2) | (1 << 9); - writel(ctrl, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - return 0; -} - -static int cns3xxx_timer_set_next_event(unsigned long evt, - struct clock_event_device *unused) -{ - unsigned long ctrl = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - - writel(evt, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); - writel(ctrl | (1 << 0), cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - - return 0; -} - -static struct clock_event_device cns3xxx_tmr1_clockevent = { - .name = "cns3xxx timer1", - .features = CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_ONESHOT, - .set_state_shutdown = cns3xxx_shutdown, - .set_state_periodic = cns3xxx_set_periodic, - .set_state_oneshot = cns3xxx_set_oneshot, - .tick_resume = cns3xxx_shutdown, - .set_next_event = cns3xxx_timer_set_next_event, - .rating = 350, - .cpumask = cpu_all_mask, -}; - -static void __init cns3xxx_clockevents_init(unsigned int timer_irq) -{ - cns3xxx_tmr1_clockevent.irq = timer_irq; - clockevents_config_and_register(&cns3xxx_tmr1_clockevent, - (cns3xxx_cpu_clock() >> 3) * 1000000, - 0xf, 0xffffffff); -} - -/* - * IRQ handler for the timer - */ -static irqreturn_t cns3xxx_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = &cns3xxx_tmr1_clockevent; - u32 __iomem *stat = cns3xxx_tmr1 + TIMER1_2_INTERRUPT_STATUS_OFFSET; - u32 val; - - /* Clear the interrupt */ - val = readl(stat); - writel(val & ~(1 << 2), stat); - - evt->event_handler(evt); - - return IRQ_HANDLED; -} - -/* - * Set up the clock source and clock events devices - */ -static void __init __cns3xxx_timer_init(unsigned int timer_irq) -{ - u32 val; - u32 irq_mask; - - /* - * Initialise to a known state (all timers off) - */ - - /* disable timer1 and timer2 */ - writel(0, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - /* stop free running timer3 */ - writel(0, cns3xxx_tmr1 + TIMER_FREERUN_CONTROL_OFFSET); - - /* timer1 */ - writel(0x5C800, cns3xxx_tmr1 + TIMER1_COUNTER_OFFSET); - writel(0x5C800, cns3xxx_tmr1 + TIMER1_AUTO_RELOAD_OFFSET); - - writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V1_OFFSET); - writel(0, cns3xxx_tmr1 + TIMER1_MATCH_V2_OFFSET); - - /* mask irq, non-mask timer1 overflow */ - irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); - irq_mask &= ~(1 << 2); - irq_mask |= 0x03; - writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); - - /* down counter */ - val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - val |= (1 << 9); - writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - - /* timer2 */ - writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V1_OFFSET); - writel(0, cns3xxx_tmr1 + TIMER2_MATCH_V2_OFFSET); - - /* mask irq */ - irq_mask = readl(cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); - irq_mask |= ((1 << 3) | (1 << 4) | (1 << 5)); - writel(irq_mask, cns3xxx_tmr1 + TIMER1_2_INTERRUPT_MASK_OFFSET); - - /* down counter */ - val = readl(cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - val |= (1 << 10); - writel(val, cns3xxx_tmr1 + TIMER1_2_CONTROL_OFFSET); - - /* Make irqs happen for the system timer */ - if (request_irq(timer_irq, cns3xxx_timer_interrupt, - IRQF_TIMER | IRQF_IRQPOLL, "timer", NULL)) - pr_err("Failed to request irq %d (timer)\n", timer_irq); - - cns3xxx_clockevents_init(timer_irq); -} - -void __init cns3xxx_timer_init(void) -{ - cns3xxx_tmr1 = IOMEM(CNS3XXX_TIMER1_2_3_BASE_VIRT); - - __cns3xxx_timer_init(IRQ_CNS3XXX_TIMER0); -} - -#ifdef CONFIG_CACHE_L2X0 - -void __init cns3xxx_l2x0_init(void) -{ - void __iomem *base = ioremap(CNS3XXX_L2C_BASE, SZ_4K); - u32 val; - - if (WARN_ON(!base)) - return; - - /* - * Tag RAM Control register - * - * bit[10:8] - 1 cycle of write accesses latency - * bit[6:4] - 1 cycle of read accesses latency - * bit[3:0] - 1 cycle of setup latency - * - * 1 cycle of latency for setup, read and write accesses - */ - val = readl(base + L310_TAG_LATENCY_CTRL); - val &= 0xfffff888; - writel(val, base + L310_TAG_LATENCY_CTRL); - - /* - * Data RAM Control register - * - * bit[10:8] - 1 cycles of write accesses latency - * bit[6:4] - 1 cycles of read accesses latency - * bit[3:0] - 1 cycle of setup latency - * - * 1 cycle of latency for setup, read and write accesses - */ - val = readl(base + L310_DATA_LATENCY_CTRL); - val &= 0xfffff888; - writel(val, base + L310_DATA_LATENCY_CTRL); - - /* 32 KiB, 8-way, parity disable */ - l2x0_init(base, 0x00500000, 0xfe0f0fff); -} - -#endif /* CONFIG_CACHE_L2X0 */ - -static int csn3xxx_usb_power_on(struct platform_device *pdev) -{ - /* - * EHCI and OHCI share the same clock and power, - * resetting twice would cause the 1st controller been reset. - * Therefore only do power up at the first up device, and - * power down at the last down device. - * - * Set USB AHB INCR length to 16 - */ - if (atomic_inc_return(&usb_pwr_ref) == 1) { - cns3xxx_pwr_power_up(1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_PLL_USB); - cns3xxx_pwr_clk_en(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); - cns3xxx_pwr_soft_rst(1 << PM_SOFT_RST_REG_OFFST_USB_HOST); - __raw_writel((__raw_readl(MISC_CHIP_CONFIG_REG) | (0X2 << 24)), - MISC_CHIP_CONFIG_REG); - } - - return 0; -} - -static void csn3xxx_usb_power_off(struct platform_device *pdev) -{ - /* - * EHCI and OHCI share the same clock and power, - * resetting twice would cause the 1st controller been reset. - * Therefore only do power up at the first up device, and - * power down at the last down device. - */ - if (atomic_dec_return(&usb_pwr_ref) == 0) - cns3xxx_pwr_clk_dis(1 << PM_CLK_GATE_REG_OFFSET_USB_HOST); -} - -static struct usb_ehci_pdata cns3xxx_usb_ehci_pdata = { - .power_on = csn3xxx_usb_power_on, - .power_off = csn3xxx_usb_power_off, -}; - -static struct usb_ohci_pdata cns3xxx_usb_ohci_pdata = { - .num_ports = 1, - .power_on = csn3xxx_usb_power_on, - .power_off = csn3xxx_usb_power_off, -}; - -static const struct of_dev_auxdata cns3xxx_auxdata[] __initconst = { - { "intel,usb-ehci", CNS3XXX_USB_BASE, "ehci-platform", &cns3xxx_usb_ehci_pdata }, - { "intel,usb-ohci", CNS3XXX_USB_OHCI_BASE, "ohci-platform", &cns3xxx_usb_ohci_pdata }, - { "cavium,cns3420-ahci", CNS3XXX_SATA2_BASE, "ahci", NULL }, - { "cavium,cns3420-sdhci", CNS3XXX_SDIO_BASE, "ahci", NULL }, - {}, -}; - -static void __init cns3xxx_init(void) -{ - struct device_node *dn; - - cns3xxx_l2x0_init(); - - dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-ahci"); - if (of_device_is_available(dn)) { - u32 tmp; - - tmp = __raw_readl(MISC_SATA_POWER_MODE); - tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */ - tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */ - __raw_writel(tmp, MISC_SATA_POWER_MODE); - - /* Enable SATA PHY */ - cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0); - cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1); - - /* Enable SATA Clock */ - cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA); - - /* De-Asscer SATA Reset */ - cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA)); - } - of_node_put(dn); - - dn = of_find_compatible_node(NULL, NULL, "cavium,cns3420-sdhci"); - if (of_device_is_available(dn)) { - u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014); - u32 gpioa_pins = __raw_readl(gpioa); - - /* MMC/SD pins share with GPIOA */ - gpioa_pins |= 0x1fff0004; - __raw_writel(gpioa_pins, gpioa); - - cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO)); - cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO)); - } - of_node_put(dn); - - pm_power_off = cns3xxx_power_off; - - of_platform_default_populate(NULL, cns3xxx_auxdata, NULL); -} - -static const char *const cns3xxx_dt_compat[] __initconst = { - "cavium,cns3410", - "cavium,cns3420", - NULL, -}; - -DT_MACHINE_START(CNS3XXX_DT, "Cavium Networks CNS3xxx") - .dt_compat = cns3xxx_dt_compat, - .map_io = cns3xxx_map_io, - .init_irq = cns3xxx_init_irq, - .init_time = cns3xxx_timer_init, - .init_machine = cns3xxx_init, - .init_late = cns3xxx_pcie_init_late, - .restart = cns3xxx_restart, -MACHINE_END diff --git a/arch/arm/mach-cns3xxx/core.h b/arch/arm/mach-cns3xxx/core.h deleted file mode 100644 index a96eabaea30170b70b97104d54eb87e14196b9b9..0000000000000000000000000000000000000000 --- a/arch/arm/mach-cns3xxx/core.h +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2000 Deep Blue Solutions Ltd - * Copyright 2004 ARM Limited - * Copyright 2008 Cavium Networks - */ - -#ifndef __CNS3XXX_CORE_H -#define __CNS3XXX_CORE_H - -#include - -extern void cns3xxx_timer_init(void); - -#ifdef CONFIG_CACHE_L2X0 -void __init cns3xxx_l2x0_init(void); -#else -static inline void cns3xxx_l2x0_init(void) {} -#endif /* CONFIG_CACHE_L2X0 */ - -#ifdef CONFIG_PCI -extern void __init cns3xxx_pcie_init_late(void); -#else -static inline void __init cns3xxx_pcie_init_late(void) {} -#endif - -void __init cns3xxx_map_io(void); -void __init cns3xxx_init_irq(void); -void cns3xxx_power_off(void); -void cns3xxx_restart(enum reboot_mode, const char *); - -#endif /* __CNS3XXX_CORE_H */ diff --git a/arch/arm/mach-cns3xxx/devices.c b/arch/arm/mach-cns3xxx/devices.c deleted file mode 100644 index 0f1ba8a0377dcea5b07f0d352d055f0d40a9f259..0000000000000000000000000000000000000000 --- a/arch/arm/mach-cns3xxx/devices.c +++ /dev/null @@ -1,108 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * CNS3xxx common devices - * - * Copyright 2008 Cavium Networks - * Scott Shu - * Copyright 2010 MontaVista Software, LLC. - * Anton Vorontsov - */ - -#include -#include -#include -#include -#include -#include "cns3xxx.h" -#include "pm.h" -#include "core.h" -#include "devices.h" - -/* - * AHCI - */ -static struct resource cns3xxx_ahci_resource[] = { - [0] = { - .start = CNS3XXX_SATA2_BASE, - .end = CNS3XXX_SATA2_BASE + CNS3XXX_SATA2_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CNS3XXX_SATA, - .end = IRQ_CNS3XXX_SATA, - .flags = IORESOURCE_IRQ, - }, -}; - -static u64 cns3xxx_ahci_dmamask = DMA_BIT_MASK(32); - -static struct platform_device cns3xxx_ahci_pdev = { - .name = "ahci", - .id = 0, - .resource = cns3xxx_ahci_resource, - .num_resources = ARRAY_SIZE(cns3xxx_ahci_resource), - .dev = { - .dma_mask = &cns3xxx_ahci_dmamask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, -}; - -void __init cns3xxx_ahci_init(void) -{ - u32 tmp; - - tmp = __raw_readl(MISC_SATA_POWER_MODE); - tmp |= 0x1 << 16; /* Disable SATA PHY 0 from SLUMBER Mode */ - tmp |= 0x1 << 17; /* Disable SATA PHY 1 from SLUMBER Mode */ - __raw_writel(tmp, MISC_SATA_POWER_MODE); - - /* Enable SATA PHY */ - cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY0); - cns3xxx_pwr_power_up(0x1 << PM_PLL_HM_PD_CTRL_REG_OFFSET_SATA_PHY1); - - /* Enable SATA Clock */ - cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_SATA); - - /* De-Asscer SATA Reset */ - cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SATA)); - - platform_device_register(&cns3xxx_ahci_pdev); -} - -/* - * SDHCI - */ -static struct resource cns3xxx_sdhci_resources[] = { - [0] = { - .start = CNS3XXX_SDIO_BASE, - .end = CNS3XXX_SDIO_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { - .start = IRQ_CNS3XXX_SDIO, - .end = IRQ_CNS3XXX_SDIO, - .flags = IORESOURCE_IRQ, - }, -}; - -static struct platform_device cns3xxx_sdhci_pdev = { - .name = "sdhci-cns3xxx", - .id = 0, - .num_resources = ARRAY_SIZE(cns3xxx_sdhci_resources), - .resource = cns3xxx_sdhci_resources, -}; - -void __init cns3xxx_sdhci_init(void) -{ - u32 __iomem *gpioa = IOMEM(CNS3XXX_MISC_BASE_VIRT + 0x0014); - u32 gpioa_pins = __raw_readl(gpioa); - - /* MMC/SD pins share with GPIOA */ - gpioa_pins |= 0x1fff0004; - __raw_writel(gpioa_pins, gpioa); - - cns3xxx_pwr_clk_en(CNS3XXX_PWR_CLK_EN(SDIO)); - cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(SDIO)); - - platform_device_register(&cns3xxx_sdhci_pdev); -} diff --git a/arch/arm/mach-cns3xxx/devices.h b/arch/arm/mach-cns3xxx/devices.h deleted file mode 100644 index ab16530d0116d4b167d9fc6bef548a66ba1d7eed..0000000000000000000000000000000000000000 --- a/arch/arm/mach-cns3xxx/devices.h +++ /dev/null @@ -1,17 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * CNS3xxx common devices - * - * Copyright 2008 Cavium Networks - * Scott Shu - * Copyright 2010 MontaVista Software, LLC. - * Anton Vorontsov - */ - -#ifndef __CNS3XXX_DEVICES_H_ -#define __CNS3XXX_DEVICES_H_ - -void __init cns3xxx_ahci_init(void); -void __init cns3xxx_sdhci_init(void); - -#endif /* __CNS3XXX_DEVICES_H_ */ diff --git a/arch/arm/mach-cns3xxx/pcie.c b/arch/arm/mach-cns3xxx/pcie.c deleted file mode 100644 index e92fbd679dfb9d1c821741853bb55ba51f9af2fc..0000000000000000000000000000000000000000 --- a/arch/arm/mach-cns3xxx/pcie.c +++ /dev/null @@ -1,290 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * PCI-E support for CNS3xxx - * - * Copyright 2008 Cavium Networks - * Richard Liu - * Copyright 2010 MontaVista Software, LLC. - * Anton Vorontsov - */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include "cns3xxx.h" -#include "core.h" - -struct cns3xxx_pcie { - void __iomem *host_regs; /* PCI config registers for host bridge */ - void __iomem *cfg0_regs; /* PCI Type 0 config registers */ - void __iomem *cfg1_regs; /* PCI Type 1 config registers */ - unsigned int irqs[2]; - struct resource res_io; - struct resource res_mem; - int port; - bool linked; -}; - -static struct cns3xxx_pcie *sysdata_to_cnspci(void *sysdata) -{ - struct pci_sys_data *root = sysdata; - - return root->private_data; -} - -static struct cns3xxx_pcie *pdev_to_cnspci(const struct pci_dev *dev) -{ - return sysdata_to_cnspci(dev->sysdata); -} - -static struct cns3xxx_pcie *pbus_to_cnspci(struct pci_bus *bus) -{ - return sysdata_to_cnspci(bus->sysdata); -} - -static void __iomem *cns3xxx_pci_map_bus(struct pci_bus *bus, - unsigned int devfn, int where) -{ - struct cns3xxx_pcie *cnspci = pbus_to_cnspci(bus); - int busno = bus->number; - int slot = PCI_SLOT(devfn); - void __iomem *base; - - /* If there is no link, just show the CNS PCI bridge. */ - if (!cnspci->linked && busno > 0) - return NULL; - - /* - * The CNS PCI bridge doesn't fit into the PCI hierarchy, though - * we still want to access it. - * We place the host bridge on bus 0, and the directly connected - * device on bus 1, slot 0. - */ - if (busno == 0) { /* internal PCIe bus, host bridge device */ - if (devfn == 0) /* device# and function# are ignored by hw */ - base = cnspci->host_regs; - else - return NULL; /* no such device */ - - } else if (busno == 1) { /* directly connected PCIe device */ - if (slot == 0) /* device# is ignored by hw */ - base = cnspci->cfg0_regs; - else - return NULL; /* no such device */ - } else /* remote PCI bus */ - base = cnspci->cfg1_regs + ((busno & 0xf) << 20); - - return base + where + (devfn << 12); -} - -static int cns3xxx_pci_read_config(struct pci_bus *bus, unsigned int devfn, - int where, int size, u32 *val) -{ - int ret; - u32 mask = (0x1ull << (size * 8)) - 1; - int shift = (where % 4) * 8; - - ret = pci_generic_config_read(bus, devfn, where, size, val); - - if (ret == PCIBIOS_SUCCESSFUL && !bus->number && !devfn && - (where & 0xffc) == PCI_CLASS_REVISION) - /* - * RC's class is 0xb, but Linux PCI driver needs 0x604 - * for a PCIe bridge. So we must fixup the class code - * to 0x604 here. - */ - *val = ((((*val << shift) & 0xff) | (0x604 << 16)) >> shift) & mask; - - return ret; -} - -static int cns3xxx_pci_setup(int nr, struct pci_sys_data *sys) -{ - struct cns3xxx_pcie *cnspci = sysdata_to_cnspci(sys); - struct resource *res_io = &cnspci->res_io; - struct resource *res_mem = &cnspci->res_mem; - - BUG_ON(request_resource(&iomem_resource, res_io) || - request_resource(&iomem_resource, res_mem)); - - pci_add_resource_offset(&sys->resources, res_io, sys->io_offset); - pci_add_resource_offset(&sys->resources, res_mem, sys->mem_offset); - - return 1; -} - -static struct pci_ops cns3xxx_pcie_ops = { - .map_bus = cns3xxx_pci_map_bus, - .read = cns3xxx_pci_read_config, - .write = pci_generic_config_write, -}; - -static int cns3xxx_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) -{ - struct cns3xxx_pcie *cnspci = pdev_to_cnspci(dev); - int irq = cnspci->irqs[!!dev->bus->number]; - - pr_info("PCIe map irq: %04d:%02x:%02x.%02x slot %d, pin %d, irq: %d\n", - pci_domain_nr(dev->bus), dev->bus->number, PCI_SLOT(dev->devfn), - PCI_FUNC(dev->devfn), slot, pin, irq); - - return irq; -} - -static struct cns3xxx_pcie cns3xxx_pcie[] = { - [0] = { - .host_regs = (void __iomem *)CNS3XXX_PCIE0_HOST_BASE_VIRT, - .cfg0_regs = (void __iomem *)CNS3XXX_PCIE0_CFG0_BASE_VIRT, - .cfg1_regs = (void __iomem *)CNS3XXX_PCIE0_CFG1_BASE_VIRT, - .res_io = { - .name = "PCIe0 I/O space", - .start = CNS3XXX_PCIE0_IO_BASE, - .end = CNS3XXX_PCIE0_CFG0_BASE - 1, /* 16 MiB */ - .flags = IORESOURCE_IO, - }, - .res_mem = { - .name = "PCIe0 non-prefetchable", - .start = CNS3XXX_PCIE0_MEM_BASE, - .end = CNS3XXX_PCIE0_HOST_BASE - 1, /* 176 MiB */ - .flags = IORESOURCE_MEM, - }, - .irqs = { IRQ_CNS3XXX_PCIE0_RC, IRQ_CNS3XXX_PCIE0_DEVICE, }, - .port = 0, - }, - [1] = { - .host_regs = (void __iomem *)CNS3XXX_PCIE1_HOST_BASE_VIRT, - .cfg0_regs = (void __iomem *)CNS3XXX_PCIE1_CFG0_BASE_VIRT, - .cfg1_regs = (void __iomem *)CNS3XXX_PCIE1_CFG1_BASE_VIRT, - .res_io = { - .name = "PCIe1 I/O space", - .start = CNS3XXX_PCIE1_IO_BASE, - .end = CNS3XXX_PCIE1_CFG0_BASE - 1, /* 16 MiB */ - .flags = IORESOURCE_IO, - }, - .res_mem = { - .name = "PCIe1 non-prefetchable", - .start = CNS3XXX_PCIE1_MEM_BASE, - .end = CNS3XXX_PCIE1_HOST_BASE - 1, /* 176 MiB */ - .flags = IORESOURCE_MEM, - }, - .irqs = { IRQ_CNS3XXX_PCIE1_RC, IRQ_CNS3XXX_PCIE1_DEVICE, }, - .port = 1, - }, -}; - -static void __init cns3xxx_pcie_check_link(struct cns3xxx_pcie *cnspci) -{ - int port = cnspci->port; - u32 reg; - unsigned long time; - - reg = __raw_readl(MISC_PCIE_CTRL(port)); - /* - * Enable Application Request to 1, it will exit L1 automatically, - * but when chip back, it will use another clock, still can use 0x1. - */ - reg |= 0x3; - __raw_writel(reg, MISC_PCIE_CTRL(port)); - - pr_info("PCIe: Port[%d] Enable PCIe LTSSM\n", port); - pr_info("PCIe: Port[%d] Check data link layer...", port); - - time = jiffies; - while (1) { - reg = __raw_readl(MISC_PCIE_PM_DEBUG(port)); - if (reg & 0x1) { - pr_info("Link up.\n"); - cnspci->linked = 1; - break; - } else if (time_after(jiffies, time + 50)) { - pr_info("Device not found.\n"); - break; - } - } -} - -static void cns3xxx_write_config(struct cns3xxx_pcie *cnspci, - int where, int size, u32 val) -{ - void __iomem *base = cnspci->host_regs + (where & 0xffc); - u32 v; - u32 mask = (0x1ull << (size * 8)) - 1; - int shift = (where % 4) * 8; - - v = readl_relaxed(base); - - v &= ~(mask << shift); - v |= (val & mask) << shift; - - writel_relaxed(v, base); - readl_relaxed(base); -} - -static void __init cns3xxx_pcie_hw_init(struct cns3xxx_pcie *cnspci) -{ - u16 mem_base = cnspci->res_mem.start >> 16; - u16 mem_limit = cnspci->res_mem.end >> 16; - u16 io_base = cnspci->res_io.start >> 16; - u16 io_limit = cnspci->res_io.end >> 16; - - cns3xxx_write_config(cnspci, PCI_PRIMARY_BUS, 1, 0); - cns3xxx_write_config(cnspci, PCI_SECONDARY_BUS, 1, 1); - cns3xxx_write_config(cnspci, PCI_SUBORDINATE_BUS, 1, 1); - cns3xxx_write_config(cnspci, PCI_MEMORY_BASE, 2, mem_base); - cns3xxx_write_config(cnspci, PCI_MEMORY_LIMIT, 2, mem_limit); - cns3xxx_write_config(cnspci, PCI_IO_BASE_UPPER16, 2, io_base); - cns3xxx_write_config(cnspci, PCI_IO_LIMIT_UPPER16, 2, io_limit); - - if (!cnspci->linked) - return; - - /* Set Device Max_Read_Request_Size to 128 byte */ - pcie_bus_config = PCIE_BUS_PEER2PEER; - - /* Disable PCIe0 Interrupt Mask INTA to INTD */ - __raw_writel(~0x3FFF, MISC_PCIE_INT_MASK(cnspci->port)); -} - -static int cns3xxx_pcie_abort_handler(unsigned long addr, unsigned int fsr, - struct pt_regs *regs) -{ - if (fsr & (1 << 10)) - regs->ARM_pc += 4; - return 0; -} - -void __init cns3xxx_pcie_init_late(void) -{ - int i; - void *private_data; - struct hw_pci hw_pci = { - .nr_controllers = 1, - .ops = &cns3xxx_pcie_ops, - .setup = cns3xxx_pci_setup, - .map_irq = cns3xxx_pcie_map_irq, - .private_data = &private_data, - }; - - pcibios_min_io = 0; - pcibios_min_mem = 0; - - hook_fault_code(16 + 6, cns3xxx_pcie_abort_handler, SIGBUS, 0, - "imprecise external abort"); - - for (i = 0; i < ARRAY_SIZE(cns3xxx_pcie); i++) { - cns3xxx_pwr_clk_en(0x1 << PM_CLK_GATE_REG_OFFSET_PCIE(i)); - cns3xxx_pwr_soft_rst(0x1 << PM_SOFT_RST_REG_OFFST_PCIE(i)); - cns3xxx_pcie_check_link(&cns3xxx_pcie[i]); - cns3xxx_pcie_hw_init(&cns3xxx_pcie[i]); - private_data = &cns3xxx_pcie[i]; - pci_common_init(&hw_pci); - } - - pci_assign_unassigned_resources(); -} diff --git a/arch/arm/mach-cns3xxx/pm.c b/arch/arm/mach-cns3xxx/pm.c deleted file mode 100644 index 72e8a7ec7a38c393bcdda4f30eec3f407891d344..0000000000000000000000000000000000000000 --- a/arch/arm/mach-cns3xxx/pm.c +++ /dev/null @@ -1,120 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Copyright 2008 Cavium Networks - */ - -#include -#include -#include -#include -#include -#include "cns3xxx.h" -#include "pm.h" -#include "core.h" - -void cns3xxx_pwr_clk_en(unsigned int block) -{ - u32 reg = __raw_readl(PM_CLK_GATE_REG); - - reg |= (block & PM_CLK_GATE_REG_MASK); - __raw_writel(reg, PM_CLK_GATE_REG); -} -EXPORT_SYMBOL(cns3xxx_pwr_clk_en); - -void cns3xxx_pwr_clk_dis(unsigned int block) -{ - u32 reg = __raw_readl(PM_CLK_GATE_REG); - - reg &= ~(block & PM_CLK_GATE_REG_MASK); - __raw_writel(reg, PM_CLK_GATE_REG); -} -EXPORT_SYMBOL(cns3xxx_pwr_clk_dis); - -void cns3xxx_pwr_power_up(unsigned int block) -{ - u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); - - reg &= ~(block & CNS3XXX_PWR_PLL_ALL); - __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); - - /* Wait for 300us for the PLL output clock locked. */ - udelay(300); -}; -EXPORT_SYMBOL(cns3xxx_pwr_power_up); - -void cns3xxx_pwr_power_down(unsigned int block) -{ - u32 reg = __raw_readl(PM_PLL_HM_PD_CTRL_REG); - - /* write '1' to power down */ - reg |= (block & CNS3XXX_PWR_PLL_ALL); - __raw_writel(reg, PM_PLL_HM_PD_CTRL_REG); -}; -EXPORT_SYMBOL(cns3xxx_pwr_power_down); - -static void cns3xxx_pwr_soft_rst_force(unsigned int block) -{ - u32 reg = __raw_readl(PM_SOFT_RST_REG); - - /* - * bit 0, 28, 29 => program low to reset, - * the other else program low and then high - */ - if (block & 0x30000001) { - reg &= ~(block & PM_SOFT_RST_REG_MASK); - } else { - reg &= ~(block & PM_SOFT_RST_REG_MASK); - __raw_writel(reg, PM_SOFT_RST_REG); - reg |= (block & PM_SOFT_RST_REG_MASK); - } - - __raw_writel(reg, PM_SOFT_RST_REG); -} - -void cns3xxx_pwr_soft_rst(unsigned int block) -{ - static unsigned int soft_reset; - - if (soft_reset & block) { - /* SPI/I2C/GPIO use the same block, reset once. */ - return; - } else { - soft_reset |= block; - } - cns3xxx_pwr_soft_rst_force(block); -} -EXPORT_SYMBOL(cns3xxx_pwr_soft_rst); - -void cns3xxx_restart(enum reboot_mode mode, const char *cmd) -{ - /* - * To reset, we hit the on-board reset register - * in the system FPGA. - */ - cns3xxx_pwr_soft_rst(CNS3XXX_PWR_SOFTWARE_RST(GLOBAL)); -} - -/* - * cns3xxx_cpu_clock - return CPU/L2 clock - * aclk: cpu clock/2 - * hclk: cpu clock/4 - * pclk: cpu clock/8 - */ -int cns3xxx_cpu_clock(void) -{ - u32 reg = __raw_readl(PM_CLK_CTRL_REG); - int cpu; - int cpu_sel; - int div_sel; - - cpu_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_PLL_CPU_SEL) & 0xf; - div_sel = (reg >> PM_CLK_CTRL_REG_OFFSET_CPU_CLK_DIV) & 0x3; - - cpu = (300 + ((cpu_sel / 3) * 100) + ((cpu_sel % 3) * 33)) >> div_sel; - - return cpu; -} -EXPORT_SYMBOL(cns3xxx_cpu_clock); - -atomic_t usb_pwr_ref = ATOMIC_INIT(0); -EXPORT_SYMBOL(usb_pwr_ref); diff --git a/arch/arm/mach-cns3xxx/pm.h b/arch/arm/mach-cns3xxx/pm.h deleted file mode 100644 index 61b73e59f0ffb55f71a3645c490b87e28c0ef465..0000000000000000000000000000000000000000 --- a/arch/arm/mach-cns3xxx/pm.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ -/* - * Copyright 2000 Deep Blue Solutions Ltd - * Copyright 2004 ARM Limited - * Copyright 2008 Cavium Networks - */ - -#ifndef __CNS3XXX_PM_H -#define __CNS3XXX_PM_H - -#include - -void cns3xxx_pwr_clk_en(unsigned int block); -void cns3xxx_pwr_clk_dis(unsigned int block); -void cns3xxx_pwr_power_up(unsigned int block); -void cns3xxx_pwr_power_down(unsigned int block); - -extern atomic_t usb_pwr_ref; - -#endif /* __CNS3XXX_PM_H */ diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig index c8cbd9a3079145f5ef89082f8fbbe7ed3524757d..4316e1370627cf9ecfdd0c2b08a1c86d98f8a9c9 100644 --- a/arch/arm/mach-davinci/Kconfig +++ b/arch/arm/mach-davinci/Kconfig @@ -14,21 +14,10 @@ menuconfig ARCH_DAVINCI if ARCH_DAVINCI -config ARCH_DAVINCI_DMx - bool - comment "DaVinci Core Type" -config ARCH_DAVINCI_DM355 - bool "DaVinci 355 based system" - depends on ATAGS && UNUSED_BOARD_FILES - select DAVINCI_AINTC - select ARCH_DAVINCI_DMx - config ARCH_DAVINCI_DA830 bool "DA830/OMAP-L137/AM17x based system" - depends on !ARCH_DAVINCI_DMx || (AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT) - depends on ATAGS select ARCH_DAVINCI_DA8XX # needed on silicon revs 1.0, 1.1: select CPU_DCACHE_WRITETHROUGH if !CPU_DCACHE_DISABLE @@ -36,142 +25,11 @@ config ARCH_DAVINCI_DA830 config ARCH_DAVINCI_DA850 bool "DA850/OMAP-L138/AM18x based system" - depends on !ARCH_DAVINCI_DMx || (AUTO_ZRELADDR && ARM_PATCH_PHYS_VIRT) - depends on ATAGS - select ARCH_DAVINCI_DA8XX select DAVINCI_CP_INTC config ARCH_DAVINCI_DA8XX bool -config ARCH_DAVINCI_DM365 - bool "DaVinci 365 based system" - depends on ATAGS && UNUSED_BOARD_FILES - select DAVINCI_AINTC - select ARCH_DAVINCI_DMx - -comment "DaVinci Board Type" - -config MACH_DA8XX_DT - bool "Support DA8XX platforms using device tree" - default y - depends on ARCH_DAVINCI_DA850 - select PINCTRL - help - Say y here to include support for TI DaVinci DA850 based using - Flattened Device Tree. More information at Documentation/devicetree - -config MACH_DAVINCI_DM355_EVM - bool "TI DM355 EVM" - default ARCH_DAVINCI_DM355 - depends on ARCH_DAVINCI_DM355 - help - Configure this option to specify the whether the board used - for development is a DM355 EVM - -config MACH_DM355_LEOPARD - bool "DM355 Leopard board" - depends on ARCH_DAVINCI_DM355 - help - Configure this option to specify the whether the board used - for development is a DM355 Leopard board. - -config MACH_DAVINCI_DM365_EVM - bool "TI DM365 EVM" - default ARCH_DAVINCI_DM365 - depends on ARCH_DAVINCI_DM365 - help - Configure this option to specify whether the board used - for development is a DM365 EVM - -config MACH_DAVINCI_DA830_EVM - bool "TI DA830/OMAP-L137/AM17x Reference Platform" - default ARCH_DAVINCI_DA830 - depends on ATAGS && UNUSED_BOARD_FILES - depends on ARCH_DAVINCI_DA830 - select GPIO_PCF857X if I2C - help - Say Y here to select the TI DA830/OMAP-L137/AM17x Evaluation Module. - -choice - prompt "Select DA830/OMAP-L137/AM17x UI board peripheral" - depends on MACH_DAVINCI_DA830_EVM - help - The presence of UI card on the DA830/OMAP-L137/AM17x EVM is - detected automatically based on successful probe of the I2C - based GPIO expander on that board. This option selected in this - menu has an effect only in case of a successful UI card detection. - -config DA830_UI_LCD - bool "LCD" - help - Say Y here to use the LCD as a framebuffer or simple character - display. - -config DA830_UI_NAND - bool "NAND flash" - help - Say Y here to use the NAND flash. Do not forget to setup - the switch correctly. -endchoice - -config MACH_DAVINCI_DA850_EVM - bool "TI DA850/OMAP-L138/AM18x Reference Platform" - depends on ATAGS && UNUSED_BOARD_FILES - default ARCH_DAVINCI_DA850 - depends on ARCH_DAVINCI_DA850 - help - Say Y here to select the TI DA850/OMAP-L138/AM18x Evaluation Module. - -choice - prompt "Select peripherals connected to expander on UI board" - depends on MACH_DAVINCI_DA850_EVM - help - The presence of User Interface (UI) card on the DA850/OMAP-L138/AM18x - EVM is detected automatically based on successful probe of the I2C - based GPIO expander on that card. This option selected in this - menu has an effect only in case of a successful UI card detection. - -config DA850_UI_NONE - bool "No peripheral is enabled" - help - Say Y if you do not want to enable any of the peripherals connected - to TCA6416 expander on DA850/OMAP-L138/AM18x EVM UI card - -config DA850_UI_RMII - bool "RMII Ethernet PHY" - help - Say Y if you want to use the RMII PHY on the DA850/OMAP-L138/AM18x - EVM. This PHY is found on the UI daughter card that is supplied with - the EVM. - NOTE: Please take care while choosing this option, MII PHY will - not be functional if RMII mode is selected. - -config DA850_UI_SD_VIDEO_PORT - bool "Video Port Interface" - help - Say Y if you want to use Video Port Interface (VPIF) on the - DA850/OMAP-L138 EVM. The Video decoders/encoders are found on the - UI daughter card that is supplied with the EVM. - -endchoice - -config MACH_MITYOMAPL138 - bool "Critical Link MityDSP-L138/MityARM-1808 SoM" - depends on ARCH_DAVINCI_DA850 - depends on ATAGS && UNUSED_BOARD_FILES - help - Say Y here to select the Critical Link MityDSP-L138/MityARM-1808 - System on Module. Information on this SoM may be found at - https://www.mitydsp.com - -config MACH_OMAPL138_HAWKBOARD - bool "TI AM1808 / OMAPL-138 Hawkboard platform" - depends on ARCH_DAVINCI_DA850 - depends on ATAGS && UNUSED_BOARD_FILES - help - Say Y here to select the TI AM1808 / OMAPL-138 Hawkboard platform . - config DAVINCI_MUX bool "DAVINCI multiplexing support" depends on ARCH_DAVINCI diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile index 3f4894aa7528dac29d76da0c24f971acca08e2e9..450883ea0e73644d1bd253ac5362c0b5d5f17065 100644 --- a/arch/arm/mach-davinci/Makefile +++ b/arch/arm/mach-davinci/Makefile @@ -5,25 +5,15 @@ # # # Common objects -obj-y := serial.o usb.o common.o sram.o +obj-y := common.o sram.o devices-da8xx.o obj-$(CONFIG_DAVINCI_MUX) += mux.o # Chip specific -obj-$(CONFIG_ARCH_DAVINCI_DM355) += dm355.o devices.o -obj-$(CONFIG_ARCH_DAVINCI_DM365) += dm365.o devices.o -obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o devices-da8xx.o usb-da8xx.o -obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o devices-da8xx.o usb-da8xx.o +obj-$(CONFIG_ARCH_DAVINCI_DA830) += da830.o +obj-$(CONFIG_ARCH_DAVINCI_DA850) += da850.o pdata-quirks.o -# Board specific -obj-$(CONFIG_MACH_DA8XX_DT) += da8xx-dt.o pdata-quirks.o -obj-$(CONFIG_MACH_DAVINCI_DM355_EVM) += board-dm355-evm.o -obj-$(CONFIG_MACH_DM355_LEOPARD) += board-dm355-leopard.o -obj-$(CONFIG_MACH_DAVINCI_DM365_EVM) += board-dm365-evm.o -obj-$(CONFIG_MACH_DAVINCI_DA830_EVM) += board-da830-evm.o -obj-$(CONFIG_MACH_DAVINCI_DA850_EVM) += board-da850-evm.o -obj-$(CONFIG_MACH_MITYOMAPL138) += board-mityomapl138.o -obj-$(CONFIG_MACH_OMAPL138_HAWKBOARD) += board-omapl138-hawk.o +obj-y += da8xx-dt.o # Power Management obj-$(CONFIG_CPU_IDLE) += cpuidle.o diff --git a/arch/arm/mach-davinci/asp.h b/arch/arm/mach-davinci/asp.h deleted file mode 100644 index d0ecd1d0f08476295528bbfe9bc795d8cda60b57..0000000000000000000000000000000000000000 --- a/arch/arm/mach-davinci/asp.h +++ /dev/null @@ -1,57 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * TI DaVinci Audio definitions - */ -#ifndef __ASM_ARCH_DAVINCI_ASP_H -#define __ASM_ARCH_DAVINCI_ASP_H - -/* Bases of dm644x and dm355 register banks */ -#define DAVINCI_ASP0_BASE 0x01E02000 -#define DAVINCI_ASP1_BASE 0x01E04000 - -/* Bases of dm365 register banks */ -#define DAVINCI_DM365_ASP0_BASE 0x01D02000 - -/* Bases of dm646x register banks */ -#define DAVINCI_DM646X_MCASP0_REG_BASE 0x01D01000 -#define DAVINCI_DM646X_MCASP1_REG_BASE 0x01D01800 - -/* Bases of da850/da830 McASP0 register banks */ -#define DAVINCI_DA8XX_MCASP0_REG_BASE 0x01D00000 - -/* Bases of da830 McASP1 register banks */ -#define DAVINCI_DA830_MCASP1_REG_BASE 0x01D04000 - -/* Bases of da830 McASP2 register banks */ -#define DAVINCI_DA830_MCASP2_REG_BASE 0x01D08000 - -/* EDMA channels of dm644x and dm355 */ -#define DAVINCI_DMA_ASP0_TX 2 -#define DAVINCI_DMA_ASP0_RX 3 -#define DAVINCI_DMA_ASP1_TX 8 -#define DAVINCI_DMA_ASP1_RX 9 - -/* EDMA channels of dm646x */ -#define DAVINCI_DM646X_DMA_MCASP0_AXEVT0 6 -#define DAVINCI_DM646X_DMA_MCASP0_AREVT0 9 -#define DAVINCI_DM646X_DMA_MCASP1_AXEVT1 12 - -/* EDMA channels of da850/da830 McASP0 */ -#define DAVINCI_DA8XX_DMA_MCASP0_AREVT 0 -#define DAVINCI_DA8XX_DMA_MCASP0_AXEVT 1 - -/* EDMA channels of da830 McASP1 */ -#define DAVINCI_DA830_DMA_MCASP1_AREVT 2 -#define DAVINCI_DA830_DMA_MCASP1_AXEVT 3 - -/* EDMA channels of da830 McASP2 */ -#define DAVINCI_DA830_DMA_MCASP2_AREVT 4 -#define DAVINCI_DA830_DMA_MCASP2_AXEVT 5 - -/* Interrupts */ -#define DAVINCI_ASP0_RX_INT DAVINCI_INTC_IRQ(IRQ_MBRINT) -#define DAVINCI_ASP0_TX_INT DAVINCI_INTC_IRQ(IRQ_MBXINT) -#define DAVINCI_ASP1_RX_INT DAVINCI_INTC_IRQ(IRQ_MBRINT) -#define DAVINCI_ASP1_TX_INT DAVINCI_INTC_IRQ(IRQ_MBXINT) - -#endif /* __ASM_ARCH_DAVINCI_ASP_H */ diff --git a/arch/arm/mach-davinci/board-da830-evm.c b/arch/arm/mach-davinci/board-da830-evm.c deleted file mode 100644 index 6299e5c8f4ea6a83378897f8f31dd53691b2c468..0000000000000000000000000000000000000000 --- a/arch/arm/mach-davinci/board-da830-evm.c +++ /dev/null @@ -1,690 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * TI DA830/OMAP L137 EVM board - * - * Author: Mark A. Greer - * Derived from: arch/arm/mach-davinci/board-dm644x-evm.c - * - * 2007, 2009 (c) MontaVista Software, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "common.h" -#include "mux.h" -#include "da8xx.h" -#include "irqs.h" - -#define DA830_EVM_PHY_ID "" -/* - * USB1 VBUS is controlled by GPIO1[15], over-current is reported on GPIO2[4]. - */ -#define ON_BD_USB_DRV GPIO_TO_PIN(1, 15) -#define ON_BD_USB_OVC GPIO_TO_PIN(2, 4) - -static const short da830_evm_usb11_pins[] = { - DA830_GPIO1_15, DA830_GPIO2_4, - -1 -}; - -static struct regulator_consumer_supply da830_evm_usb_supplies[] = { - REGULATOR_SUPPLY("vbus", NULL), -}; - -static struct regulator_init_data da830_evm_usb_vbus_data = { - .consumer_supplies = da830_evm_usb_supplies, - .num_consumer_supplies = ARRAY_SIZE(da830_evm_usb_supplies), - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, -}; - -static struct fixed_voltage_config da830_evm_usb_vbus = { - .supply_name = "vbus", - .microvolts = 33000000, - .init_data = &da830_evm_usb_vbus_data, -}; - -static struct platform_device da830_evm_usb_vbus_device = { - .name = "reg-fixed-voltage", - .id = 0, - .dev = { - .platform_data = &da830_evm_usb_vbus, - }, -}; - -static struct gpiod_lookup_table da830_evm_usb_oc_gpio_lookup = { - .dev_id = "ohci-da8xx", - .table = { - GPIO_LOOKUP("davinci_gpio", ON_BD_USB_OVC, "oc", 0), - { } - }, -}; - -static struct gpiod_lookup_table da830_evm_usb_vbus_gpio_lookup = { - .dev_id = "reg-fixed-voltage.0", - .table = { - GPIO_LOOKUP("davinci_gpio", ON_BD_USB_DRV, NULL, 0), - { } - }, -}; - -static struct gpiod_lookup_table *da830_evm_usb_gpio_lookups[] = { - &da830_evm_usb_oc_gpio_lookup, - &da830_evm_usb_vbus_gpio_lookup, -}; - -static struct da8xx_ohci_root_hub da830_evm_usb11_pdata = { - /* TPS2065 switch @ 5V */ - .potpgt = (3 + 1) / 2, /* 3 ms max */ -}; - -static __init void da830_evm_usb_init(void) -{ - int ret; - - ret = da8xx_register_usb_phy_clocks(); - if (ret) - pr_warn("%s: USB PHY CLK registration failed: %d\n", - __func__, ret); - - gpiod_add_lookup_tables(da830_evm_usb_gpio_lookups, - ARRAY_SIZE(da830_evm_usb_gpio_lookups)); - - ret = da8xx_register_usb_phy(); - if (ret) - pr_warn("%s: USB PHY registration failed: %d\n", - __func__, ret); - - ret = davinci_cfg_reg(DA830_USB0_DRVVBUS); - if (ret) - pr_warn("%s: USB 2.0 PinMux setup failed: %d\n", __func__, ret); - else { - /* - * TPS2065 switch @ 5V supplies 1 A (sustains 1.5 A), - * with the power on to power good time of 3 ms. - */ - ret = da8xx_register_usb20(1000, 3); - if (ret) - pr_warn("%s: USB 2.0 registration failed: %d\n", - __func__, ret); - } - - ret = davinci_cfg_reg_list(da830_evm_usb11_pins); - if (ret) { - pr_warn("%s: USB 1.1 PinMux setup failed: %d\n", __func__, ret); - return; - } - - ret = platform_device_register(&da830_evm_usb_vbus_device); - if (ret) { - pr_warn("%s: Unable to register the vbus supply\n", __func__); - return; - } - - ret = da8xx_register_usb11(&da830_evm_usb11_pdata); - if (ret) - pr_warn("%s: USB 1.1 registration failed: %d\n", __func__, ret); -} - -static const short da830_evm_mcasp1_pins[] = { - DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, DA830_AHCLKR1, DA830_AFSR1, - DA830_AMUTE1, DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_5, - DA830_ACLKR1, DA830_AXR1_6, DA830_AXR1_7, DA830_AXR1_8, DA830_AXR1_10, - DA830_AXR1_11, - -1 -}; - -static u8 da830_iis_serializer_direction[] = { - RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, - INACTIVE_MODE, TX_MODE, INACTIVE_MODE, INACTIVE_MODE, - INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, -}; - -static struct snd_platform_data da830_evm_snd_data = { - .tx_dma_offset = 0x2000, - .rx_dma_offset = 0x2000, - .op_mode = DAVINCI_MCASP_IIS_MODE, - .num_serializer = ARRAY_SIZE(da830_iis_serializer_direction), - .tdm_slots = 2, - .serial_dir = da830_iis_serializer_direction, - .asp_chan_q = EVENTQ_0, - .version = MCASP_VERSION_2, - .txnumevt = 1, - .rxnumevt = 1, -}; - -/* - * GPIO2[1] is used as MMC_SD_WP and GPIO2[2] as MMC_SD_INS. - */ -static const short da830_evm_mmc_sd_pins[] = { - DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2, - DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5, - DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK, - DA830_MMCSD_CMD, DA830_GPIO2_1, DA830_GPIO2_2, - -1 -}; - -#define DA830_MMCSD_WP_PIN GPIO_TO_PIN(2, 1) -#define DA830_MMCSD_CD_PIN GPIO_TO_PIN(2, 2) - -static struct gpiod_lookup_table mmc_gpios_table = { - .dev_id = "da830-mmc.0", - .table = { - /* gpio chip 1 contains gpio range 32-63 */ - GPIO_LOOKUP("davinci_gpio", DA830_MMCSD_CD_PIN, "cd", - GPIO_ACTIVE_LOW), - GPIO_LOOKUP("davinci_gpio", DA830_MMCSD_WP_PIN, "wp", - GPIO_ACTIVE_LOW), - { } - }, -}; - -static struct davinci_mmc_config da830_evm_mmc_config = { - .wires = 8, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -static inline void da830_evm_init_mmc(void) -{ - int ret; - - ret = davinci_cfg_reg_list(da830_evm_mmc_sd_pins); - if (ret) { - pr_warn("%s: mmc/sd mux setup failed: %d\n", __func__, ret); - return; - } - - gpiod_add_lookup_table(&mmc_gpios_table); - - ret = da8xx_register_mmcsd0(&da830_evm_mmc_config); - if (ret) { - pr_warn("%s: mmc/sd registration failed: %d\n", __func__, ret); - gpiod_remove_lookup_table(&mmc_gpios_table); - } -} - -#define HAS_MMC IS_ENABLED(CONFIG_MMC_DAVINCI) - -#ifdef CONFIG_DA830_UI_NAND -static struct mtd_partition da830_evm_nand_partitions[] = { - /* bootloader (U-Boot, etc) in first sector */ - [0] = { - .name = "bootloader", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* bootloader params in the next sector */ - [1] = { - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, - /* kernel */ - [2] = { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0, - }, - /* file system */ - [3] = { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - } -}; - -/* flash bbt descriptors */ -static uint8_t da830_evm_nand_bbt_pattern[] = { 'B', 'b', 't', '0' }; -static uint8_t da830_evm_nand_mirror_pattern[] = { '1', 't', 'b', 'B' }; - -static struct nand_bbt_descr da830_evm_nand_bbt_main_descr = { - .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | - NAND_BBT_WRITE | NAND_BBT_2BIT | - NAND_BBT_VERSION | NAND_BBT_PERCHIP, - .offs = 2, - .len = 4, - .veroffs = 16, - .maxblocks = 4, - .pattern = da830_evm_nand_bbt_pattern -}; - -static struct nand_bbt_descr da830_evm_nand_bbt_mirror_descr = { - .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | - NAND_BBT_WRITE | NAND_BBT_2BIT | - NAND_BBT_VERSION | NAND_BBT_PERCHIP, - .offs = 2, - .len = 4, - .veroffs = 16, - .maxblocks = 4, - .pattern = da830_evm_nand_mirror_pattern -}; - -static struct davinci_aemif_timing da830_evm_nandflash_timing = { - .wsetup = 24, - .wstrobe = 21, - .whold = 14, - .rsetup = 19, - .rstrobe = 50, - .rhold = 0, - .ta = 20, -}; - -static struct davinci_nand_pdata da830_evm_nand_pdata = { - .core_chipsel = 1, - .parts = da830_evm_nand_partitions, - .nr_parts = ARRAY_SIZE(da830_evm_nand_partitions), - .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, - .ecc_bits = 4, - .bbt_options = NAND_BBT_USE_FLASH, - .bbt_td = &da830_evm_nand_bbt_main_descr, - .bbt_md = &da830_evm_nand_bbt_mirror_descr, - .timing = &da830_evm_nandflash_timing, -}; - -static struct resource da830_evm_nand_resources[] = { - [0] = { /* First memory resource is NAND I/O window */ - .start = DA8XX_AEMIF_CS3_BASE, - .end = DA8XX_AEMIF_CS3_BASE + PAGE_SIZE - 1, - .flags = IORESOURCE_MEM, - }, - [1] = { /* Second memory resource is AEMIF control registers */ - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device da830_evm_aemif_devices[] = { - { - .name = "davinci_nand", - .id = 1, - .dev = { - .platform_data = &da830_evm_nand_pdata, - }, - .num_resources = ARRAY_SIZE(da830_evm_nand_resources), - .resource = da830_evm_nand_resources, - }, -}; - -static struct resource da830_evm_aemif_resource[] = { - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct aemif_abus_data da830_evm_aemif_abus_data[] = { - { - .cs = 3, - }, -}; - -static struct aemif_platform_data da830_evm_aemif_pdata = { - .abus_data = da830_evm_aemif_abus_data, - .num_abus_data = ARRAY_SIZE(da830_evm_aemif_abus_data), - .sub_devices = da830_evm_aemif_devices, - .num_sub_devices = ARRAY_SIZE(da830_evm_aemif_devices), - .cs_offset = 2, -}; - -static struct platform_device da830_evm_aemif_device = { - .name = "ti-aemif", - .id = -1, - .dev = { - .platform_data = &da830_evm_aemif_pdata, - }, - .resource = da830_evm_aemif_resource, - .num_resources = ARRAY_SIZE(da830_evm_aemif_resource), -}; - -/* - * UI board NAND/NOR flashes only use 8-bit data bus. - */ -static const short da830_evm_emif25_pins[] = { - DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3, - DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7, - DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3, - DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7, - DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11, - DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_NEMA_WE, - DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, DA830_EMA_WAIT_0, - -1 -}; - -static inline void da830_evm_init_nand(int mux_mode) -{ - int ret; - - if (HAS_MMC) { - pr_warn("WARNING: both MMC/SD and NAND are enabled, but they share AEMIF pins\n" - "\tDisable MMC/SD for NAND support\n"); - return; - } - - ret = davinci_cfg_reg_list(da830_evm_emif25_pins); - if (ret) - pr_warn("%s: emif25 mux setup failed: %d\n", __func__, ret); - - ret = platform_device_register(&da830_evm_aemif_device); - if (ret) - pr_warn("%s: AEMIF device not registered\n", __func__); - - gpio_direction_output(mux_mode, 1); -} -#else -static inline void da830_evm_init_nand(int mux_mode) { } -#endif - -#ifdef CONFIG_DA830_UI_LCD -static inline void da830_evm_init_lcdc(int mux_mode) -{ - int ret; - - ret = davinci_cfg_reg_list(da830_lcdcntl_pins); - if (ret) - pr_warn("%s: lcdcntl mux setup failed: %d\n", __func__, ret); - - ret = da8xx_register_lcdc(&sharp_lcd035q3dg01_pdata); - if (ret) - pr_warn("%s: lcd setup failed: %d\n", __func__, ret); - - gpio_direction_output(mux_mode, 0); -} -#else -static inline void da830_evm_init_lcdc(int mux_mode) { } -#endif - -static struct nvmem_cell_info da830_evm_nvmem_cells[] = { - { - .name = "macaddr", - .offset = 0x7f00, - .bytes = ETH_ALEN, - } -}; - -static struct nvmem_cell_table da830_evm_nvmem_cell_table = { - .nvmem_name = "1-00500", - .cells = da830_evm_nvmem_cells, - .ncells = ARRAY_SIZE(da830_evm_nvmem_cells), -}; - -static struct nvmem_cell_lookup da830_evm_nvmem_cell_lookup = { - .nvmem_name = "1-00500", - .cell_name = "macaddr", - .dev_id = "davinci_emac.1", - .con_id = "mac-address", -}; - -static const struct property_entry da830_evm_i2c_eeprom_properties[] = { - PROPERTY_ENTRY_U32("pagesize", 64), - { } -}; - -static const struct software_node da830_evm_i2c_eeprom_node = { - .properties = da830_evm_i2c_eeprom_properties, -}; - -static int __init da830_evm_ui_expander_setup(struct i2c_client *client, - int gpio, unsigned ngpio, void *context) -{ - gpio_request(gpio + 6, "UI MUX_MODE"); - - /* Drive mux mode low to match the default without UI card */ - gpio_direction_output(gpio + 6, 0); - - da830_evm_init_lcdc(gpio + 6); - - da830_evm_init_nand(gpio + 6); - - return 0; -} - -static void da830_evm_ui_expander_teardown(struct i2c_client *client, int gpio, - unsigned ngpio, void *context) -{ - gpio_free(gpio + 6); -} - -static struct pcf857x_platform_data __initdata da830_evm_ui_expander_info = { - .gpio_base = DAVINCI_N_GPIO, - .setup = da830_evm_ui_expander_setup, - .teardown = da830_evm_ui_expander_teardown, -}; - -static struct i2c_board_info __initdata da830_evm_i2c_devices[] = { - { - I2C_BOARD_INFO("24c256", 0x50), - .swnode = &da830_evm_i2c_eeprom_node, - }, - { - I2C_BOARD_INFO("tlv320aic3x", 0x18), - }, - { - I2C_BOARD_INFO("pcf8574", 0x3f), - .platform_data = &da830_evm_ui_expander_info, - }, -}; - -static struct davinci_i2c_platform_data da830_evm_i2c_0_pdata = { - .bus_freq = 100, /* kHz */ - .bus_delay = 0, /* usec */ -}; - -/* - * The following EDMA channels/slots are not being used by drivers (for - * example: Timer, GPIO, UART events etc) on da830/omap-l137 EVM, hence - * they are being reserved for codecs on the DSP side. - */ -static const s16 da830_dma_rsv_chans[][2] = { - /* (offset, number) */ - { 8, 2}, - {12, 2}, - {24, 4}, - {30, 2}, - {-1, -1} -}; - -static const s16 da830_dma_rsv_slots[][2] = { - /* (offset, number) */ - { 8, 2}, - {12, 2}, - {24, 4}, - {30, 26}, - {-1, -1} -}; - -static struct edma_rsv_info da830_edma_rsv[] = { - { - .rsv_chans = da830_dma_rsv_chans, - .rsv_slots = da830_dma_rsv_slots, - }, -}; - -static struct mtd_partition da830evm_spiflash_part[] = { - [0] = { - .name = "DSP-UBL", - .offset = 0, - .size = SZ_8K, - .mask_flags = MTD_WRITEABLE, - }, - [1] = { - .name = "ARM-UBL", - .offset = MTDPART_OFS_APPEND, - .size = SZ_16K + SZ_8K, - .mask_flags = MTD_WRITEABLE, - }, - [2] = { - .name = "U-Boot", - .offset = MTDPART_OFS_APPEND, - .size = SZ_256K - SZ_32K, - .mask_flags = MTD_WRITEABLE, - }, - [3] = { - .name = "U-Boot-Environment", - .offset = MTDPART_OFS_APPEND, - .size = SZ_16K, - .mask_flags = 0, - }, - [4] = { - .name = "Kernel", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - }, -}; - -static struct flash_platform_data da830evm_spiflash_data = { - .name = "m25p80", - .parts = da830evm_spiflash_part, - .nr_parts = ARRAY_SIZE(da830evm_spiflash_part), - .type = "w25x32", -}; - -static struct davinci_spi_config da830evm_spiflash_cfg = { - .io_type = SPI_IO_TYPE_DMA, - .c2tdelay = 8, - .t2cdelay = 8, -}; - -static struct spi_board_info da830evm_spi_info[] = { - { - .modalias = "m25p80", - .platform_data = &da830evm_spiflash_data, - .controller_data = &da830evm_spiflash_cfg, - .mode = SPI_MODE_0, - .max_speed_hz = 30000000, - .bus_num = 0, - .chip_select = 0, - }, -}; - -static __init void da830_evm_init(void) -{ - struct davinci_soc_info *soc_info = &davinci_soc_info; - int ret; - - da830_register_clocks(); - - ret = da830_register_gpio(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - - ret = da830_register_edma(da830_edma_rsv); - if (ret) - pr_warn("%s: edma registration failed: %d\n", __func__, ret); - - ret = davinci_cfg_reg_list(da830_i2c0_pins); - if (ret) - pr_warn("%s: i2c0 mux setup failed: %d\n", __func__, ret); - - ret = da8xx_register_i2c(0, &da830_evm_i2c_0_pdata); - if (ret) - pr_warn("%s: i2c0 registration failed: %d\n", __func__, ret); - - da830_evm_usb_init(); - - soc_info->emac_pdata->rmii_en = 1; - soc_info->emac_pdata->phy_id = DA830_EVM_PHY_ID; - - ret = davinci_cfg_reg_list(da830_cpgmac_pins); - if (ret) - pr_warn("%s: cpgmac mux setup failed: %d\n", __func__, ret); - - ret = da8xx_register_emac(); - if (ret) - pr_warn("%s: emac registration failed: %d\n", __func__, ret); - - ret = da8xx_register_watchdog(); - if (ret) - pr_warn("%s: watchdog registration failed: %d\n", - __func__, ret); - - davinci_serial_init(da8xx_serial_device); - - nvmem_add_cell_table(&da830_evm_nvmem_cell_table); - nvmem_add_cell_lookups(&da830_evm_nvmem_cell_lookup, 1); - - i2c_register_board_info(1, da830_evm_i2c_devices, - ARRAY_SIZE(da830_evm_i2c_devices)); - - ret = davinci_cfg_reg_list(da830_evm_mcasp1_pins); - if (ret) - pr_warn("%s: mcasp1 mux setup failed: %d\n", __func__, ret); - - da8xx_register_mcasp(1, &da830_evm_snd_data); - - da830_evm_init_mmc(); - - ret = da8xx_register_rtc(); - if (ret) - pr_warn("%s: rtc setup failed: %d\n", __func__, ret); - - ret = spi_register_board_info(da830evm_spi_info, - ARRAY_SIZE(da830evm_spi_info)); - if (ret) - pr_warn("%s: spi info registration failed: %d\n", - __func__, ret); - - ret = da8xx_register_spi_bus(0, ARRAY_SIZE(da830evm_spi_info)); - if (ret) - pr_warn("%s: spi 0 registration failed: %d\n", __func__, ret); - - regulator_has_full_constraints(); -} - -#ifdef CONFIG_SERIAL_8250_CONSOLE -static int __init da830_evm_console_init(void) -{ - if (!machine_is_davinci_da830_evm()) - return 0; - - return add_preferred_console("ttyS", 2, "115200"); -} -console_initcall(da830_evm_console_init); -#endif - -static void __init da830_evm_map_io(void) -{ - da830_init(); -} - -MACHINE_START(DAVINCI_DA830_EVM, "DaVinci DA830/OMAP-L137/AM17x EVM") - .atag_offset = 0x100, - .map_io = da830_evm_map_io, - .init_irq = da830_init_irq, - .init_time = da830_init_time, - .init_machine = da830_evm_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, -MACHINE_END diff --git a/arch/arm/mach-davinci/board-da850-evm.c b/arch/arm/mach-davinci/board-da850-evm.c deleted file mode 100644 index d752ee2b30ff94919020e4343de9a1af5d4aeffb..0000000000000000000000000000000000000000 --- a/arch/arm/mach-davinci/board-da850-evm.c +++ /dev/null @@ -1,1550 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * TI DA850/OMAP-L138 EVM board - * - * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com/ - * - * Derived from: arch/arm/mach-davinci/board-da830-evm.c - * Original Copyrights follow: - * - * 2007, 2009 (c) MontaVista Software, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include "common.h" -#include "da8xx.h" -#include "mux.h" -#include "irqs.h" -#include "sram.h" - -#include -#include -#include - -#include -#include - -#define DA850_EVM_PHY_ID "davinci_mdio-0:00" -#define DA850_LCD_PWR_PIN GPIO_TO_PIN(2, 8) -#define DA850_LCD_BL_PIN GPIO_TO_PIN(2, 15) - -#define DA850_MII_MDIO_CLKEN_PIN GPIO_TO_PIN(2, 6) - -static struct mtd_partition da850evm_spiflash_part[] = { - [0] = { - .name = "UBL", - .offset = 0, - .size = SZ_64K, - .mask_flags = MTD_WRITEABLE, - }, - [1] = { - .name = "U-Boot", - .offset = MTDPART_OFS_APPEND, - .size = SZ_512K, - .mask_flags = MTD_WRITEABLE, - }, - [2] = { - .name = "U-Boot-Env", - .offset = MTDPART_OFS_APPEND, - .size = SZ_64K, - .mask_flags = MTD_WRITEABLE, - }, - [3] = { - .name = "Kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M + SZ_512K, - .mask_flags = 0, - }, - [4] = { - .name = "Filesystem", - .offset = MTDPART_OFS_APPEND, - .size = SZ_4M, - .mask_flags = 0, - }, - [5] = { - .name = "MAC-Address", - .offset = SZ_8M - SZ_64K, - .size = SZ_64K, - .mask_flags = MTD_WRITEABLE, - }, -}; - -static struct nvmem_cell_info da850evm_nvmem_cells[] = { - { - .name = "macaddr", - .offset = 0x0, - .bytes = ETH_ALEN, - } -}; - -static struct nvmem_cell_table da850evm_nvmem_cell_table = { - /* - * The nvmem name differs from the partition name because of the - * internal works of the nvmem framework. - */ - .nvmem_name = "MAC-Address0", - .cells = da850evm_nvmem_cells, - .ncells = ARRAY_SIZE(da850evm_nvmem_cells), -}; - -static struct nvmem_cell_lookup da850evm_nvmem_cell_lookup = { - .nvmem_name = "MAC-Address0", - .cell_name = "macaddr", - .dev_id = "davinci_emac.1", - .con_id = "mac-address", -}; - -static struct flash_platform_data da850evm_spiflash_data = { - .name = "m25p80", - .parts = da850evm_spiflash_part, - .nr_parts = ARRAY_SIZE(da850evm_spiflash_part), - .type = "m25p64", -}; - -static struct davinci_spi_config da850evm_spiflash_cfg = { - .io_type = SPI_IO_TYPE_DMA, - .c2tdelay = 8, - .t2cdelay = 8, -}; - -static struct spi_board_info da850evm_spi_info[] = { - { - .modalias = "m25p80", - .platform_data = &da850evm_spiflash_data, - .controller_data = &da850evm_spiflash_cfg, - .mode = SPI_MODE_0, - .max_speed_hz = 30000000, - .bus_num = 1, - .chip_select = 0, - }, -}; - -static struct mtd_partition da850_evm_norflash_partition[] = { - { - .name = "bootloaders + env", - .offset = 0, - .size = SZ_512K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - .mask_flags = 0, - }, - { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - }, -}; - -static struct physmap_flash_data da850_evm_norflash_data = { - .width = 2, - .parts = da850_evm_norflash_partition, - .nr_parts = ARRAY_SIZE(da850_evm_norflash_partition), -}; - -static struct resource da850_evm_norflash_resource[] = { - { - .start = DA8XX_AEMIF_CS2_BASE, - .end = DA8XX_AEMIF_CS2_BASE + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, -}; - -/* DA850/OMAP-L138 EVM includes a 512 MByte large-page NAND flash - * (128K blocks). It may be used instead of the (default) SPI flash - * to boot, using TI's tools to install the secondary boot loader - * (UBL) and U-Boot. - */ -static struct mtd_partition da850_evm_nandflash_partition[] = { - { - .name = "u-boot env", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "UBL", - .offset = MTDPART_OFS_APPEND, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "u-boot", - .offset = MTDPART_OFS_APPEND, - .size = 4 * SZ_128K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "kernel", - .offset = 0x200000, - .size = SZ_2M, - .mask_flags = 0, - }, - { - .name = "filesystem", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - }, -}; - -static struct davinci_aemif_timing da850_evm_nandflash_timing = { - .wsetup = 24, - .wstrobe = 21, - .whold = 14, - .rsetup = 19, - .rstrobe = 50, - .rhold = 0, - .ta = 20, -}; - -static struct davinci_nand_pdata da850_evm_nandflash_data = { - .core_chipsel = 1, - .parts = da850_evm_nandflash_partition, - .nr_parts = ARRAY_SIZE(da850_evm_nandflash_partition), - .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, - .ecc_bits = 4, - .bbt_options = NAND_BBT_USE_FLASH, - .timing = &da850_evm_nandflash_timing, -}; - -static struct resource da850_evm_nandflash_resource[] = { - { - .start = DA8XX_AEMIF_CS3_BASE, - .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource da850_evm_aemif_resource[] = { - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K, - .flags = IORESOURCE_MEM, - } -}; - -static struct aemif_abus_data da850_evm_aemif_abus_data[] = { - { - .cs = 3, - } -}; - -static struct platform_device da850_evm_aemif_devices[] = { - { - .name = "davinci_nand", - .id = 1, - .dev = { - .platform_data = &da850_evm_nandflash_data, - }, - .num_resources = ARRAY_SIZE(da850_evm_nandflash_resource), - .resource = da850_evm_nandflash_resource, - }, - { - .name = "physmap-flash", - .id = 0, - .dev = { - .platform_data = &da850_evm_norflash_data, - }, - .num_resources = 1, - .resource = da850_evm_norflash_resource, - } -}; - -static struct aemif_platform_data da850_evm_aemif_pdata = { - .cs_offset = 2, - .abus_data = da850_evm_aemif_abus_data, - .num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data), - .sub_devices = da850_evm_aemif_devices, - .num_sub_devices = ARRAY_SIZE(da850_evm_aemif_devices), -}; - -static struct platform_device da850_evm_aemif_device = { - .name = "ti-aemif", - .id = -1, - .dev = { - .platform_data = &da850_evm_aemif_pdata, - }, - .resource = da850_evm_aemif_resource, - .num_resources = ARRAY_SIZE(da850_evm_aemif_resource), -}; - -static const short da850_evm_nand_pins[] = { - DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3, - DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7, - DA850_EMA_A_1, DA850_EMA_A_2, DA850_NEMA_CS_3, DA850_NEMA_CS_4, - DA850_NEMA_WE, DA850_NEMA_OE, - -1 -}; - -static const short da850_evm_nor_pins[] = { - DA850_EMA_BA_1, DA850_EMA_CLK, DA850_EMA_WAIT_1, DA850_NEMA_CS_2, - DA850_NEMA_WE, DA850_NEMA_OE, DA850_EMA_D_0, DA850_EMA_D_1, - DA850_EMA_D_2, DA850_EMA_D_3, DA850_EMA_D_4, DA850_EMA_D_5, - DA850_EMA_D_6, DA850_EMA_D_7, DA850_EMA_D_8, DA850_EMA_D_9, - DA850_EMA_D_10, DA850_EMA_D_11, DA850_EMA_D_12, DA850_EMA_D_13, - DA850_EMA_D_14, DA850_EMA_D_15, DA850_EMA_A_0, DA850_EMA_A_1, - DA850_EMA_A_2, DA850_EMA_A_3, DA850_EMA_A_4, DA850_EMA_A_5, - DA850_EMA_A_6, DA850_EMA_A_7, DA850_EMA_A_8, DA850_EMA_A_9, - DA850_EMA_A_10, DA850_EMA_A_11, DA850_EMA_A_12, DA850_EMA_A_13, - DA850_EMA_A_14, DA850_EMA_A_15, DA850_EMA_A_16, DA850_EMA_A_17, - DA850_EMA_A_18, DA850_EMA_A_19, DA850_EMA_A_20, DA850_EMA_A_21, - DA850_EMA_A_22, DA850_EMA_A_23, - -1 -}; - -#define HAS_MMC IS_ENABLED(CONFIG_MMC_DAVINCI) - -static inline void da850_evm_setup_nor_nand(void) -{ - int ret = 0; - - if (!HAS_MMC) { - ret = davinci_cfg_reg_list(da850_evm_nand_pins); - if (ret) - pr_warn("%s: NAND mux setup failed: %d\n", - __func__, ret); - - ret = davinci_cfg_reg_list(da850_evm_nor_pins); - if (ret) - pr_warn("%s: NOR mux setup failed: %d\n", - __func__, ret); - - ret = platform_device_register(&da850_evm_aemif_device); - if (ret) - pr_warn("%s: registering aemif failed: %d\n", - __func__, ret); - } -} - -#ifdef CONFIG_DA850_UI_RMII -static inline void da850_evm_setup_emac_rmii(int rmii_sel) -{ - struct davinci_soc_info *soc_info = &davinci_soc_info; - - soc_info->emac_pdata->rmii_en = 1; - gpio_set_value_cansleep(rmii_sel, 0); -} -#else -static inline void da850_evm_setup_emac_rmii(int rmii_sel) { } -#endif - - -#define DA850_KEYS_DEBOUNCE_MS 10 -/* - * At 200ms polling interval it is possible to miss an - * event by tapping very lightly on the push button but most - * pushes do result in an event; longer intervals require the - * user to hold the button whereas shorter intervals require - * more CPU time for polling. - */ -#define DA850_GPIO_KEYS_POLL_MS 200 - -enum da850_evm_ui_exp_pins { - DA850_EVM_UI_EXP_SEL_C = 5, - DA850_EVM_UI_EXP_SEL_B, - DA850_EVM_UI_EXP_SEL_A, - DA850_EVM_UI_EXP_PB8, - DA850_EVM_UI_EXP_PB7, - DA850_EVM_UI_EXP_PB6, - DA850_EVM_UI_EXP_PB5, - DA850_EVM_UI_EXP_PB4, - DA850_EVM_UI_EXP_PB3, - DA850_EVM_UI_EXP_PB2, - DA850_EVM_UI_EXP_PB1, -}; - -static const char * const da850_evm_ui_exp[] = { - [DA850_EVM_UI_EXP_SEL_C] = "sel_c", - [DA850_EVM_UI_EXP_SEL_B] = "sel_b", - [DA850_EVM_UI_EXP_SEL_A] = "sel_a", - [DA850_EVM_UI_EXP_PB8] = "pb8", - [DA850_EVM_UI_EXP_PB7] = "pb7", - [DA850_EVM_UI_EXP_PB6] = "pb6", - [DA850_EVM_UI_EXP_PB5] = "pb5", - [DA850_EVM_UI_EXP_PB4] = "pb4", - [DA850_EVM_UI_EXP_PB3] = "pb3", - [DA850_EVM_UI_EXP_PB2] = "pb2", - [DA850_EVM_UI_EXP_PB1] = "pb1", -}; - -#define DA850_N_UI_PB 8 - -static struct gpio_keys_button da850_evm_ui_keys[] = { - [0 ... DA850_N_UI_PB - 1] = { - .type = EV_KEY, - .active_low = 1, - .wakeup = 0, - .debounce_interval = DA850_KEYS_DEBOUNCE_MS, - .code = -1, /* assigned at runtime */ - .gpio = -1, /* assigned at runtime */ - .desc = NULL, /* assigned at runtime */ - }, -}; - -static struct gpio_keys_platform_data da850_evm_ui_keys_pdata = { - .buttons = da850_evm_ui_keys, - .nbuttons = ARRAY_SIZE(da850_evm_ui_keys), - .poll_interval = DA850_GPIO_KEYS_POLL_MS, -}; - -static struct platform_device da850_evm_ui_keys_device = { - .name = "gpio-keys-polled", - .id = 0, - .dev = { - .platform_data = &da850_evm_ui_keys_pdata - }, -}; - -static void da850_evm_ui_keys_init(unsigned gpio) -{ - int i; - struct gpio_keys_button *button; - - for (i = 0; i < DA850_N_UI_PB; i++) { - button = &da850_evm_ui_keys[i]; - button->code = KEY_F8 - i; - button->desc = da850_evm_ui_exp[DA850_EVM_UI_EXP_PB8 + i]; - button->gpio = gpio + DA850_EVM_UI_EXP_PB8 + i; - } -} - -#ifdef CONFIG_DA850_UI_SD_VIDEO_PORT -static inline void da850_evm_setup_video_port(int video_sel) -{ - gpio_set_value_cansleep(video_sel, 0); -} -#else -static inline void da850_evm_setup_video_port(int video_sel) { } -#endif - -static int da850_evm_ui_expander_setup(struct i2c_client *client, unsigned gpio, - unsigned ngpio, void *c) -{ - int sel_a, sel_b, sel_c, ret; - - sel_a = gpio + DA850_EVM_UI_EXP_SEL_A; - sel_b = gpio + DA850_EVM_UI_EXP_SEL_B; - sel_c = gpio + DA850_EVM_UI_EXP_SEL_C; - - ret = gpio_request(sel_a, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_A]); - if (ret) { - pr_warn("Cannot open UI expander pin %d\n", sel_a); - goto exp_setup_sela_fail; - } - - ret = gpio_request(sel_b, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_B]); - if (ret) { - pr_warn("Cannot open UI expander pin %d\n", sel_b); - goto exp_setup_selb_fail; - } - - ret = gpio_request(sel_c, da850_evm_ui_exp[DA850_EVM_UI_EXP_SEL_C]); - if (ret) { - pr_warn("Cannot open UI expander pin %d\n", sel_c); - goto exp_setup_selc_fail; - } - - /* deselect all functionalities */ - gpio_direction_output(sel_a, 1); - gpio_direction_output(sel_b, 1); - gpio_direction_output(sel_c, 1); - - da850_evm_ui_keys_init(gpio); - ret = platform_device_register(&da850_evm_ui_keys_device); - if (ret) { - pr_warn("Could not register UI GPIO expander push-buttons"); - goto exp_setup_keys_fail; - } - - pr_info("DA850/OMAP-L138 EVM UI card detected\n"); - - da850_evm_setup_nor_nand(); - - da850_evm_setup_emac_rmii(sel_a); - - da850_evm_setup_video_port(sel_c); - - return 0; - -exp_setup_keys_fail: - gpio_free(sel_c); -exp_setup_selc_fail: - gpio_free(sel_b); -exp_setup_selb_fail: - gpio_free(sel_a); -exp_setup_sela_fail: - return ret; -} - -static void da850_evm_ui_expander_teardown(struct i2c_client *client, - unsigned gpio, unsigned ngpio, void *c) -{ - platform_device_unregister(&da850_evm_ui_keys_device); - - /* deselect all functionalities */ - gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_C, 1); - gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_B, 1); - gpio_set_value_cansleep(gpio + DA850_EVM_UI_EXP_SEL_A, 1); - - gpio_free(gpio + DA850_EVM_UI_EXP_SEL_C); - gpio_free(gpio + DA850_EVM_UI_EXP_SEL_B); - gpio_free(gpio + DA850_EVM_UI_EXP_SEL_A); -} - -/* assign the baseboard expander's GPIOs after the UI board's */ -#define DA850_UI_EXPANDER_N_GPIOS ARRAY_SIZE(da850_evm_ui_exp) -#define DA850_BB_EXPANDER_GPIO_BASE (DAVINCI_N_GPIO + DA850_UI_EXPANDER_N_GPIOS) - -enum da850_evm_bb_exp_pins { - DA850_EVM_BB_EXP_DEEP_SLEEP_EN = 0, - DA850_EVM_BB_EXP_SW_RST, - DA850_EVM_BB_EXP_TP_23, - DA850_EVM_BB_EXP_TP_22, - DA850_EVM_BB_EXP_TP_21, - DA850_EVM_BB_EXP_USER_PB1, - DA850_EVM_BB_EXP_USER_LED2, - DA850_EVM_BB_EXP_USER_LED1, - DA850_EVM_BB_EXP_USER_SW1, - DA850_EVM_BB_EXP_USER_SW2, - DA850_EVM_BB_EXP_USER_SW3, - DA850_EVM_BB_EXP_USER_SW4, - DA850_EVM_BB_EXP_USER_SW5, - DA850_EVM_BB_EXP_USER_SW6, - DA850_EVM_BB_EXP_USER_SW7, - DA850_EVM_BB_EXP_USER_SW8 -}; - -static const char * const da850_evm_bb_exp[] = { - [DA850_EVM_BB_EXP_DEEP_SLEEP_EN] = "deep_sleep_en", - [DA850_EVM_BB_EXP_SW_RST] = "sw_rst", - [DA850_EVM_BB_EXP_TP_23] = "tp_23", - [DA850_EVM_BB_EXP_TP_22] = "tp_22", - [DA850_EVM_BB_EXP_TP_21] = "tp_21", - [DA850_EVM_BB_EXP_USER_PB1] = "user_pb1", - [DA850_EVM_BB_EXP_USER_LED2] = "user_led2", - [DA850_EVM_BB_EXP_USER_LED1] = "user_led1", - [DA850_EVM_BB_EXP_USER_SW1] = "user_sw1", - [DA850_EVM_BB_EXP_USER_SW2] = "user_sw2", - [DA850_EVM_BB_EXP_USER_SW3] = "user_sw3", - [DA850_EVM_BB_EXP_USER_SW4] = "user_sw4", - [DA850_EVM_BB_EXP_USER_SW5] = "user_sw5", - [DA850_EVM_BB_EXP_USER_SW6] = "user_sw6", - [DA850_EVM_BB_EXP_USER_SW7] = "user_sw7", - [DA850_EVM_BB_EXP_USER_SW8] = "user_sw8", -}; - -#define DA850_N_BB_USER_SW 8 - -static struct gpio_keys_button da850_evm_bb_keys[] = { - [0] = { - .type = EV_KEY, - .active_low = 1, - .wakeup = 0, - .debounce_interval = DA850_KEYS_DEBOUNCE_MS, - .code = KEY_PROG1, - .desc = NULL, /* assigned at runtime */ - .gpio = -1, /* assigned at runtime */ - }, - [1 ... DA850_N_BB_USER_SW] = { - .type = EV_SW, - .active_low = 1, - .wakeup = 0, - .debounce_interval = DA850_KEYS_DEBOUNCE_MS, - .code = -1, /* assigned at runtime */ - .desc = NULL, /* assigned at runtime */ - .gpio = -1, /* assigned at runtime */ - }, -}; - -static struct gpio_keys_platform_data da850_evm_bb_keys_pdata = { - .buttons = da850_evm_bb_keys, - .nbuttons = ARRAY_SIZE(da850_evm_bb_keys), - .poll_interval = DA850_GPIO_KEYS_POLL_MS, -}; - -static struct platform_device da850_evm_bb_keys_device = { - .name = "gpio-keys-polled", - .id = 1, - .dev = { - .platform_data = &da850_evm_bb_keys_pdata - }, -}; - -static void da850_evm_bb_keys_init(unsigned gpio) -{ - int i; - struct gpio_keys_button *button; - - button = &da850_evm_bb_keys[0]; - button->desc = da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_PB1]; - button->gpio = gpio + DA850_EVM_BB_EXP_USER_PB1; - - for (i = 0; i < DA850_N_BB_USER_SW; i++) { - button = &da850_evm_bb_keys[i + 1]; - button->code = SW_LID + i; - button->desc = da850_evm_bb_exp[DA850_EVM_BB_EXP_USER_SW1 + i]; - button->gpio = gpio + DA850_EVM_BB_EXP_USER_SW1 + i; - } -} - -static struct gpio_led da850_evm_bb_leds[] = { - { - .name = "user_led2", - }, - { - .name = "user_led1", - }, -}; - -static struct gpio_led_platform_data da850_evm_bb_leds_pdata = { - .leds = da850_evm_bb_leds, - .num_leds = ARRAY_SIZE(da850_evm_bb_leds), -}; - -static struct gpiod_lookup_table da850_evm_bb_leds_gpio_table = { - .dev_id = "leds-gpio", - .table = { - GPIO_LOOKUP_IDX("i2c-bb-expander", - DA850_EVM_BB_EXP_USER_LED2, NULL, - 0, GPIO_ACTIVE_LOW), - GPIO_LOOKUP_IDX("i2c-bb-expander", - DA850_EVM_BB_EXP_USER_LED2 + 1, NULL, - 1, GPIO_ACTIVE_LOW), - - { }, - }, -}; - -static struct platform_device da850_evm_bb_leds_device = { - .name = "leds-gpio", - .id = -1, - .dev = { - .platform_data = &da850_evm_bb_leds_pdata - } -}; - -static int da850_evm_bb_expander_setup(struct i2c_client *client, - unsigned gpio, unsigned ngpio, - void *c) -{ - int ret; - - /* - * Register the switches and pushbutton on the baseboard as a gpio-keys - * device. - */ - da850_evm_bb_keys_init(gpio); - ret = platform_device_register(&da850_evm_bb_keys_device); - if (ret) { - pr_warn("Could not register baseboard GPIO expander keys"); - goto io_exp_setup_sw_fail; - } - - gpiod_add_lookup_table(&da850_evm_bb_leds_gpio_table); - ret = platform_device_register(&da850_evm_bb_leds_device); - if (ret) { - pr_warn("Could not register baseboard GPIO expander LEDs"); - goto io_exp_setup_leds_fail; - } - - return 0; - -io_exp_setup_leds_fail: - platform_device_unregister(&da850_evm_bb_keys_device); -io_exp_setup_sw_fail: - return ret; -} - -static void da850_evm_bb_expander_teardown(struct i2c_client *client, - unsigned gpio, unsigned ngpio, void *c) -{ - platform_device_unregister(&da850_evm_bb_leds_device); - platform_device_unregister(&da850_evm_bb_keys_device); -} - -static struct pca953x_platform_data da850_evm_ui_expander_info = { - .gpio_base = DAVINCI_N_GPIO, - .setup = da850_evm_ui_expander_setup, - .teardown = da850_evm_ui_expander_teardown, - .names = da850_evm_ui_exp, -}; - -static struct pca953x_platform_data da850_evm_bb_expander_info = { - .gpio_base = DA850_BB_EXPANDER_GPIO_BASE, - .setup = da850_evm_bb_expander_setup, - .teardown = da850_evm_bb_expander_teardown, - .names = da850_evm_bb_exp, -}; - -static struct i2c_board_info __initdata da850_evm_i2c_devices[] = { - { - I2C_BOARD_INFO("tlv320aic3x", 0x18), - }, - { - I2C_BOARD_INFO("tca6416", 0x20), - .dev_name = "ui-expander", - .platform_data = &da850_evm_ui_expander_info, - }, - { - I2C_BOARD_INFO("tca6416", 0x21), - .dev_name = "bb-expander", - .platform_data = &da850_evm_bb_expander_info, - }, -}; - -static struct davinci_i2c_platform_data da850_evm_i2c_0_pdata = { - .bus_freq = 100, /* kHz */ - .bus_delay = 0, /* usec */ -}; - -/* davinci da850 evm audio machine driver */ -static u8 da850_iis_serializer_direction[] = { - INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, - INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, - INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, TX_MODE, - RX_MODE, INACTIVE_MODE, INACTIVE_MODE, INACTIVE_MODE, -}; - -static struct snd_platform_data da850_evm_snd_data = { - .tx_dma_offset = 0x2000, - .rx_dma_offset = 0x2000, - .op_mode = DAVINCI_MCASP_IIS_MODE, - .num_serializer = ARRAY_SIZE(da850_iis_serializer_direction), - .tdm_slots = 2, - .serial_dir = da850_iis_serializer_direction, - .asp_chan_q = EVENTQ_0, - .ram_chan_q = EVENTQ_1, - .version = MCASP_VERSION_2, - .txnumevt = 1, - .rxnumevt = 1, - .sram_size_playback = SZ_8K, - .sram_size_capture = SZ_8K, -}; - -static const short da850_evm_mcasp_pins[] __initconst = { - DA850_AHCLKX, DA850_ACLKX, DA850_AFSX, - DA850_AHCLKR, DA850_ACLKR, DA850_AFSR, DA850_AMUTE, - DA850_AXR_11, DA850_AXR_12, - -1 -}; - -#define DA850_MMCSD_CD_PIN GPIO_TO_PIN(4, 0) -#define DA850_MMCSD_WP_PIN GPIO_TO_PIN(4, 1) - -static struct gpiod_lookup_table mmc_gpios_table = { - .dev_id = "da830-mmc.0", - .table = { - /* gpio chip 2 contains gpio range 64-95 */ - GPIO_LOOKUP("davinci_gpio", DA850_MMCSD_CD_PIN, "cd", - GPIO_ACTIVE_LOW), - GPIO_LOOKUP("davinci_gpio", DA850_MMCSD_WP_PIN, "wp", - GPIO_ACTIVE_HIGH), - { } - }, -}; - -static struct davinci_mmc_config da850_mmc_config = { - .wires = 4, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -static const short da850_evm_mmcsd0_pins[] __initconst = { - DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2, - DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD, - DA850_GPIO4_0, DA850_GPIO4_1, - -1 -}; - -static struct property_entry da850_lcd_backlight_props[] = { - PROPERTY_ENTRY_BOOL("default-on"), - { } -}; - -static struct gpiod_lookup_table da850_lcd_backlight_gpio_table = { - .dev_id = "gpio-backlight", - .table = { - GPIO_LOOKUP("davinci_gpio", DA850_LCD_BL_PIN, NULL, 0), - { } - }, -}; - -static const struct platform_device_info da850_lcd_backlight_info = { - .name = "gpio-backlight", - .id = PLATFORM_DEVID_NONE, - .properties = da850_lcd_backlight_props, -}; - -static struct regulator_consumer_supply da850_lcd_supplies[] = { - REGULATOR_SUPPLY("lcd", NULL), -}; - -static struct regulator_init_data da850_lcd_supply_data = { - .consumer_supplies = da850_lcd_supplies, - .num_consumer_supplies = ARRAY_SIZE(da850_lcd_supplies), - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, -}; - -static struct fixed_voltage_config da850_lcd_supply = { - .supply_name = "lcd", - .microvolts = 33000000, - .init_data = &da850_lcd_supply_data, -}; - -static struct platform_device da850_lcd_supply_device = { - .name = "reg-fixed-voltage", - .id = 1, /* Dummy fixed regulator is 0 */ - .dev = { - .platform_data = &da850_lcd_supply, - }, -}; - -static struct gpiod_lookup_table da850_lcd_supply_gpio_table = { - .dev_id = "reg-fixed-voltage.1", - .table = { - GPIO_LOOKUP("davinci_gpio", DA850_LCD_PWR_PIN, NULL, 0), - { } - }, -}; - -static struct gpiod_lookup_table *da850_lcd_gpio_lookups[] = { - &da850_lcd_backlight_gpio_table, - &da850_lcd_supply_gpio_table, -}; - -static int da850_lcd_hw_init(void) -{ - struct platform_device *backlight; - int status; - - gpiod_add_lookup_tables(da850_lcd_gpio_lookups, - ARRAY_SIZE(da850_lcd_gpio_lookups)); - - backlight = platform_device_register_full(&da850_lcd_backlight_info); - if (IS_ERR(backlight)) - return PTR_ERR(backlight); - - status = platform_device_register(&da850_lcd_supply_device); - if (status) - return status; - - return 0; -} - -/* Fixed regulator support */ -static struct regulator_consumer_supply fixed_supplies[] = { - /* Baseboard 3.3V: 5V -> TPS73701DCQ -> 3.3V */ - REGULATOR_SUPPLY("AVDD", "1-0018"), - REGULATOR_SUPPLY("DRVDD", "1-0018"), - - /* Baseboard 1.8V: 5V -> TPS73701DCQ -> 1.8V */ - REGULATOR_SUPPLY("DVDD", "1-0018"), - - /* UI card 3.3V: 5V -> TPS73701DCQ -> 3.3V */ - REGULATOR_SUPPLY("vcc", "1-0020"), -}; - -/* TPS65070 voltage regulator support */ - -/* 3.3V */ -static struct regulator_consumer_supply tps65070_dcdc1_consumers[] = { - { - .supply = "usb0_vdda33", - }, - { - .supply = "usb1_vdda33", - }, -}; - -/* 3.3V or 1.8V */ -static struct regulator_consumer_supply tps65070_dcdc2_consumers[] = { - { - .supply = "dvdd3318_a", - }, - { - .supply = "dvdd3318_b", - }, - { - .supply = "dvdd3318_c", - }, - REGULATOR_SUPPLY("IOVDD", "1-0018"), -}; - -/* 1.2V */ -static struct regulator_consumer_supply tps65070_dcdc3_consumers[] = { - { - .supply = "cvdd", - }, -}; - -/* 1.8V LDO */ -static struct regulator_consumer_supply tps65070_ldo1_consumers[] = { - { - .supply = "sata_vddr", - }, - { - .supply = "usb0_vdda18", - }, - { - .supply = "usb1_vdda18", - }, - { - .supply = "ddr_dvdd18", - }, -}; - -/* 1.2V LDO */ -static struct regulator_consumer_supply tps65070_ldo2_consumers[] = { - { - .supply = "sata_vdd", - }, - { - .supply = "pll0_vdda", - }, - { - .supply = "pll1_vdda", - }, - { - .supply = "usbs_cvdd", - }, - { - .supply = "vddarnwa1", - }, -}; - -/* We take advantage of the fact that both defdcdc{2,3} are tied high */ -static struct tps6507x_reg_platform_data tps6507x_platform_data = { - .defdcdc_default = true, -}; - -static struct regulator_init_data tps65070_regulator_data[] = { - /* dcdc1 */ - { - .constraints = { - .min_uV = 3150000, - .max_uV = 3450000, - .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS), - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc1_consumers), - .consumer_supplies = tps65070_dcdc1_consumers, - }, - - /* dcdc2 */ - { - .constraints = { - .min_uV = 1710000, - .max_uV = 3450000, - .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS), - .boot_on = 1, - .always_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc2_consumers), - .consumer_supplies = tps65070_dcdc2_consumers, - .driver_data = &tps6507x_platform_data, - }, - - /* dcdc3 */ - { - .constraints = { - .min_uV = 950000, - .max_uV = 1350000, - .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS), - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65070_dcdc3_consumers), - .consumer_supplies = tps65070_dcdc3_consumers, - .driver_data = &tps6507x_platform_data, - }, - - /* ldo1 */ - { - .constraints = { - .min_uV = 1710000, - .max_uV = 1890000, - .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS), - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo1_consumers), - .consumer_supplies = tps65070_ldo1_consumers, - }, - - /* ldo2 */ - { - .constraints = { - .min_uV = 1140000, - .max_uV = 1320000, - .valid_ops_mask = (REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS), - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65070_ldo2_consumers), - .consumer_supplies = tps65070_ldo2_consumers, - }, -}; - -static struct touchscreen_init_data tps6507x_touchscreen_data = { - .poll_period = 30, /* ms between touch samples */ - .min_pressure = 0x30, /* minimum pressure to trigger touch */ - .vendor = 0, /* /sys/class/input/input?/id/vendor */ - .product = 65070, /* /sys/class/input/input?/id/product */ - .version = 0x100, /* /sys/class/input/input?/id/version */ -}; - -static struct tps6507x_board tps_board = { - .tps6507x_pmic_init_data = &tps65070_regulator_data[0], - .tps6507x_ts_init_data = &tps6507x_touchscreen_data, -}; - -static struct i2c_board_info __initdata da850_evm_tps65070_info[] = { - { - I2C_BOARD_INFO("tps6507x", 0x48), - .platform_data = &tps_board, - }, -}; - -static int __init pmic_tps65070_init(void) -{ - return i2c_register_board_info(1, da850_evm_tps65070_info, - ARRAY_SIZE(da850_evm_tps65070_info)); -} - -static const short da850_evm_lcdc_pins[] = { - DA850_GPIO2_8, DA850_GPIO2_15, - -1 -}; - -static const short da850_evm_mii_pins[] = { - DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, - DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, - DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, - DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, - DA850_MDIO_D, - -1 -}; - -static const short da850_evm_rmii_pins[] = { - DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN, - DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, - DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK, - DA850_MDIO_D, - -1 -}; - -static struct gpiod_hog da850_evm_emac_gpio_hogs[] = { - { - .chip_label = "davinci_gpio", - .chip_hwnum = DA850_MII_MDIO_CLKEN_PIN, - .line_name = "mdio_clk_en", - .lflags = 0, - /* dflags set in da850_evm_config_emac() */ - }, - { } -}; - -static int __init da850_evm_config_emac(void) -{ - void __iomem *cfg_chip3_base; - int ret; - u32 val; - struct davinci_soc_info *soc_info = &davinci_soc_info; - u8 rmii_en; - - if (!machine_is_davinci_da850_evm()) - return 0; - - rmii_en = soc_info->emac_pdata->rmii_en; - - cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); - - val = __raw_readl(cfg_chip3_base); - - if (rmii_en) { - val |= BIT(8); - ret = davinci_cfg_reg_list(da850_evm_rmii_pins); - pr_info("EMAC: RMII PHY configured, MII PHY will not be" - " functional\n"); - } else { - val &= ~BIT(8); - ret = davinci_cfg_reg_list(da850_evm_mii_pins); - pr_info("EMAC: MII PHY configured, RMII PHY will not be" - " functional\n"); - } - - if (ret) - pr_warn("%s: CPGMAC/RMII mux setup failed: %d\n", - __func__, ret); - - /* configure the CFGCHIP3 register for RMII or MII */ - __raw_writel(val, cfg_chip3_base); - - ret = davinci_cfg_reg(DA850_GPIO2_6); - if (ret) - pr_warn("%s:GPIO(2,6) mux setup failed\n", __func__); - - da850_evm_emac_gpio_hogs[0].dflags = rmii_en ? GPIOD_OUT_HIGH - : GPIOD_OUT_LOW; - gpiod_add_hogs(da850_evm_emac_gpio_hogs); - - soc_info->emac_pdata->phy_id = DA850_EVM_PHY_ID; - - ret = da8xx_register_emac(); - if (ret) - pr_warn("%s: EMAC registration failed: %d\n", __func__, ret); - - return 0; -} -device_initcall(da850_evm_config_emac); - -/* - * The following EDMA channels/slots are not being used by drivers (for - * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM, hence - * they are being reserved for codecs on the DSP side. - */ -static const s16 da850_dma0_rsv_chans[][2] = { - /* (offset, number) */ - { 8, 6}, - {24, 4}, - {30, 2}, - {-1, -1} -}; - -static const s16 da850_dma0_rsv_slots[][2] = { - /* (offset, number) */ - { 8, 6}, - {24, 4}, - {30, 50}, - {-1, -1} -}; - -static const s16 da850_dma1_rsv_chans[][2] = { - /* (offset, number) */ - { 0, 28}, - {30, 2}, - {-1, -1} -}; - -static const s16 da850_dma1_rsv_slots[][2] = { - /* (offset, number) */ - { 0, 28}, - {30, 90}, - {-1, -1} -}; - -static struct edma_rsv_info da850_edma_cc0_rsv = { - .rsv_chans = da850_dma0_rsv_chans, - .rsv_slots = da850_dma0_rsv_slots, -}; - -static struct edma_rsv_info da850_edma_cc1_rsv = { - .rsv_chans = da850_dma1_rsv_chans, - .rsv_slots = da850_dma1_rsv_slots, -}; - -static struct edma_rsv_info *da850_edma_rsv[2] = { - &da850_edma_cc0_rsv, - &da850_edma_cc1_rsv, -}; - -#ifdef CONFIG_CPU_FREQ -static __init int da850_evm_init_cpufreq(void) -{ - switch (system_rev & 0xF) { - case 3: - da850_max_speed = 456000; - break; - case 2: - da850_max_speed = 408000; - break; - case 1: - da850_max_speed = 372000; - break; - } - - return da850_register_cpufreq("pll0_sysclk3"); -} -#else -static __init int da850_evm_init_cpufreq(void) { return 0; } -#endif - -#if defined(CONFIG_DA850_UI_SD_VIDEO_PORT) - -#define TVP5147_CH0 "tvp514x-0" -#define TVP5147_CH1 "tvp514x-1" - -/* VPIF capture configuration */ -static struct tvp514x_platform_data tvp5146_pdata = { - .clk_polarity = 0, - .hs_polarity = 1, - .vs_polarity = 1, -}; - -#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) - -static struct vpif_input da850_ch0_inputs[] = { - { - .input = { - .index = 0, - .name = "Composite", - .type = V4L2_INPUT_TYPE_CAMERA, - .capabilities = V4L2_IN_CAP_STD, - .std = TVP514X_STD_ALL, - }, - .input_route = INPUT_CVBS_VI2B, - .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC, - .subdev_name = TVP5147_CH0, - }, -}; - -static struct vpif_input da850_ch1_inputs[] = { - { - .input = { - .index = 0, - .name = "S-Video", - .type = V4L2_INPUT_TYPE_CAMERA, - .capabilities = V4L2_IN_CAP_STD, - .std = TVP514X_STD_ALL, - }, - .input_route = INPUT_SVIDEO_VI2C_VI1C, - .output_route = OUTPUT_10BIT_422_EMBEDDED_SYNC, - .subdev_name = TVP5147_CH1, - }, -}; - -static struct vpif_subdev_info da850_vpif_capture_sdev_info[] = { - { - .name = TVP5147_CH0, - .board_info = { - I2C_BOARD_INFO("tvp5146", 0x5d), - .platform_data = &tvp5146_pdata, - }, - }, - { - .name = TVP5147_CH1, - .board_info = { - I2C_BOARD_INFO("tvp5146", 0x5c), - .platform_data = &tvp5146_pdata, - }, - }, -}; - -static struct vpif_capture_config da850_vpif_capture_config = { - .subdev_info = da850_vpif_capture_sdev_info, - .subdev_count = ARRAY_SIZE(da850_vpif_capture_sdev_info), - .i2c_adapter_id = 1, - .chan_config[0] = { - .inputs = da850_ch0_inputs, - .input_count = ARRAY_SIZE(da850_ch0_inputs), - .vpif_if = { - .if_type = VPIF_IF_BT656, - .hd_pol = 1, - .vd_pol = 1, - .fid_pol = 0, - }, - }, - .chan_config[1] = { - .inputs = da850_ch1_inputs, - .input_count = ARRAY_SIZE(da850_ch1_inputs), - .vpif_if = { - .if_type = VPIF_IF_BT656, - .hd_pol = 1, - .vd_pol = 1, - .fid_pol = 0, - }, - }, - .card_name = "DA850/OMAP-L138 Video Capture", -}; - -/* VPIF display configuration */ - -static struct adv7343_platform_data adv7343_pdata = { - .mode_config = { - .dac = { 1, 1, 1 }, - }, - .sd_config = { - .sd_dac_out = { 1 }, - }, -}; - -static struct vpif_subdev_info da850_vpif_subdev[] = { - { - .name = "adv7343", - .board_info = { - I2C_BOARD_INFO("adv7343", 0x2a), - .platform_data = &adv7343_pdata, - }, - }, -}; - -static const struct vpif_output da850_ch0_outputs[] = { - { - .output = { - .index = 0, - .name = "Composite", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .capabilities = V4L2_OUT_CAP_STD, - .std = V4L2_STD_ALL, - }, - .subdev_name = "adv7343", - .output_route = ADV7343_COMPOSITE_ID, - }, - { - .output = { - .index = 1, - .name = "S-Video", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .capabilities = V4L2_OUT_CAP_STD, - .std = V4L2_STD_ALL, - }, - .subdev_name = "adv7343", - .output_route = ADV7343_SVIDEO_ID, - }, -}; - -static struct vpif_display_config da850_vpif_display_config = { - .subdevinfo = da850_vpif_subdev, - .subdev_count = ARRAY_SIZE(da850_vpif_subdev), - .chan_config[0] = { - .outputs = da850_ch0_outputs, - .output_count = ARRAY_SIZE(da850_ch0_outputs), - }, - .card_name = "DA850/OMAP-L138 Video Display", - .i2c_adapter_id = 1, -}; - -static __init void da850_vpif_init(void) -{ - int ret; - - ret = da850_register_vpif(); - if (ret) - pr_warn("da850_evm_init: VPIF setup failed: %d\n", ret); - - ret = davinci_cfg_reg_list(da850_vpif_capture_pins); - if (ret) - pr_warn("da850_evm_init: VPIF capture mux setup failed: %d\n", - ret); - - ret = da850_register_vpif_capture(&da850_vpif_capture_config); - if (ret) - pr_warn("da850_evm_init: VPIF capture setup failed: %d\n", ret); - - ret = davinci_cfg_reg_list(da850_vpif_display_pins); - if (ret) - pr_warn("da850_evm_init: VPIF display mux setup failed: %d\n", - ret); - - ret = da850_register_vpif_display(&da850_vpif_display_config); - if (ret) - pr_warn("da850_evm_init: VPIF display setup failed: %d\n", ret); -} - -#else -static __init void da850_vpif_init(void) {} -#endif - -#define DA850EVM_SATA_REFCLKPN_RATE (100 * 1000 * 1000) - -static __init void da850_evm_init(void) -{ - int ret; - - da850_register_clocks(); - - ret = da850_register_gpio(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - - regulator_register_fixed(0, fixed_supplies, ARRAY_SIZE(fixed_supplies)); - - ret = pmic_tps65070_init(); - if (ret) - pr_warn("%s: TPS65070 PMIC init failed: %d\n", __func__, ret); - - ret = da850_register_edma(da850_edma_rsv); - if (ret) - pr_warn("%s: EDMA registration failed: %d\n", __func__, ret); - - ret = davinci_cfg_reg_list(da850_i2c0_pins); - if (ret) - pr_warn("%s: I2C0 mux setup failed: %d\n", __func__, ret); - - ret = da8xx_register_i2c(0, &da850_evm_i2c_0_pdata); - if (ret) - pr_warn("%s: I2C0 registration failed: %d\n", __func__, ret); - - - ret = da8xx_register_watchdog(); - if (ret) - pr_warn("%s: watchdog registration failed: %d\n", - __func__, ret); - - if (HAS_MMC) { - ret = davinci_cfg_reg_list(da850_evm_mmcsd0_pins); - if (ret) - pr_warn("%s: MMCSD0 mux setup failed: %d\n", - __func__, ret); - - gpiod_add_lookup_table(&mmc_gpios_table); - - ret = da8xx_register_mmcsd0(&da850_mmc_config); - if (ret) - pr_warn("%s: MMCSD0 registration failed: %d\n", - __func__, ret); - } - - davinci_serial_init(da8xx_serial_device); - - nvmem_add_cell_table(&da850evm_nvmem_cell_table); - nvmem_add_cell_lookups(&da850evm_nvmem_cell_lookup, 1); - - i2c_register_board_info(1, da850_evm_i2c_devices, - ARRAY_SIZE(da850_evm_i2c_devices)); - - /* - * shut down uart 0 and 1; they are not used on the board and - * accessing them causes endless "too much work in irq53" messages - * with arago fs - */ - __raw_writel(0, IO_ADDRESS(DA8XX_UART1_BASE) + 0x30); - __raw_writel(0, IO_ADDRESS(DA8XX_UART0_BASE) + 0x30); - - ret = davinci_cfg_reg_list(da850_evm_mcasp_pins); - if (ret) - pr_warn("%s: McASP mux setup failed: %d\n", __func__, ret); - - da850_evm_snd_data.sram_pool = sram_get_gen_pool(); - da8xx_register_mcasp(0, &da850_evm_snd_data); - - ret = davinci_cfg_reg_list(da850_lcdcntl_pins); - if (ret) - pr_warn("%s: LCDC mux setup failed: %d\n", __func__, ret); - - ret = da8xx_register_uio_pruss(); - if (ret) - pr_warn("da850_evm_init: pruss initialization failed: %d\n", - ret); - - /* Handle board specific muxing for LCD here */ - ret = davinci_cfg_reg_list(da850_evm_lcdc_pins); - if (ret) - pr_warn("%s: EVM specific LCD mux setup failed: %d\n", - __func__, ret); - - ret = da850_lcd_hw_init(); - if (ret) - pr_warn("%s: LCD initialization failed: %d\n", __func__, ret); - - ret = da8xx_register_lcdc(&sharp_lk043t1dg01_pdata); - if (ret) - pr_warn("%s: LCDC registration failed: %d\n", __func__, ret); - - ret = da8xx_register_rtc(); - if (ret) - pr_warn("%s: RTC setup failed: %d\n", __func__, ret); - - ret = da850_evm_init_cpufreq(); - if (ret) - pr_warn("%s: cpufreq registration failed: %d\n", __func__, ret); - - ret = da8xx_register_cpuidle(); - if (ret) - pr_warn("%s: cpuidle registration failed: %d\n", __func__, ret); - - davinci_pm_init(); - da850_vpif_init(); - - ret = spi_register_board_info(da850evm_spi_info, - ARRAY_SIZE(da850evm_spi_info)); - if (ret) - pr_warn("%s: spi info registration failed: %d\n", __func__, - ret); - - ret = da8xx_register_spi_bus(1, ARRAY_SIZE(da850evm_spi_info)); - if (ret) - pr_warn("%s: SPI 1 registration failed: %d\n", __func__, ret); - - ret = da850_register_sata(DA850EVM_SATA_REFCLKPN_RATE); - if (ret) - pr_warn("%s: SATA registration failed: %d\n", __func__, ret); - - ret = da8xx_register_rproc(); - if (ret) - pr_warn("%s: dsp/rproc registration failed: %d\n", - __func__, ret); - - regulator_has_full_constraints(); -} - -#ifdef CONFIG_SERIAL_8250_CONSOLE -static int __init da850_evm_console_init(void) -{ - if (!machine_is_davinci_da850_evm()) - return 0; - - return add_preferred_console("ttyS", 2, "115200"); -} -console_initcall(da850_evm_console_init); -#endif - -static void __init da850_evm_map_io(void) -{ - da850_init(); -} - -MACHINE_START(DAVINCI_DA850_EVM, "DaVinci DA850/OMAP-L138/AM18x EVM") - .atag_offset = 0x100, - .map_io = da850_evm_map_io, - .init_irq = da850_init_irq, - .init_time = da850_init_time, - .init_machine = da850_evm_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, - .reserve = da8xx_rproc_reserve_cma, -MACHINE_END diff --git a/arch/arm/mach-davinci/board-dm355-evm.c b/arch/arm/mach-davinci/board-dm355-evm.c deleted file mode 100644 index b48ab1c3e48b8f0e7d5aa789d7e4ef66881a9929..0000000000000000000000000000000000000000 --- a/arch/arm/mach-davinci/board-dm355-evm.c +++ /dev/null @@ -1,444 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * TI DaVinci EVM board support - * - * Author: Kevin Hilman, Deep Root Systems, LLC - * - * 2007 (c) MontaVista Software, Inc. - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "serial.h" -#include "common.h" -#include "davinci.h" - -/* NOTE: this is geared for the standard config, with a socketed - * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you - * swap chips, maybe with a different block size, partitioning may - * need to be changed. - */ -#define NAND_BLOCK_SIZE SZ_128K - -static struct mtd_partition davinci_nand_partitions[] = { - { - /* UBL (a few copies) plus U-Boot */ - .name = "bootloader", - .offset = 0, - .size = 15 * NAND_BLOCK_SIZE, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, { - /* U-Boot environment */ - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = 1 * NAND_BLOCK_SIZE, - .mask_flags = 0, - }, { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_4M, - .mask_flags = 0, - }, { - .name = "filesystem1", - .offset = MTDPART_OFS_APPEND, - .size = SZ_512M, - .mask_flags = 0, - }, { - .name = "filesystem2", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - } - /* two blocks with bad block table (and mirror) at the end */ -}; - -static struct davinci_nand_pdata davinci_nand_data = { - .core_chipsel = 0, - .mask_chipsel = BIT(14), - .parts = davinci_nand_partitions, - .nr_parts = ARRAY_SIZE(davinci_nand_partitions), - .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, - .bbt_options = NAND_BBT_USE_FLASH, - .ecc_bits = 4, -}; - -static struct resource davinci_nand_resources[] = { - { - .start = DM355_ASYNC_EMIF_DATA_CE0_BASE, - .end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, { - .start = DM355_ASYNC_EMIF_CONTROL_BASE, - .end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device davinci_nand_device = { - .name = "davinci_nand", - .id = 0, - - .num_resources = ARRAY_SIZE(davinci_nand_resources), - .resource = davinci_nand_resources, - - .dev = { - .platform_data = &davinci_nand_data, - }, -}; - -#define DM355_I2C_SDA_PIN GPIO_TO_PIN(0, 15) -#define DM355_I2C_SCL_PIN GPIO_TO_PIN(0, 14) - -static struct gpiod_lookup_table i2c_recovery_gpiod_table = { - .dev_id = "i2c_davinci.1", - .table = { - GPIO_LOOKUP("davinci_gpio", DM355_I2C_SDA_PIN, "sda", - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - GPIO_LOOKUP("davinci_gpio", DM355_I2C_SCL_PIN, "scl", - GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN), - { } - }, -}; - -static struct davinci_i2c_platform_data i2c_pdata = { - .bus_freq = 400 /* kHz */, - .bus_delay = 0 /* usec */, - .gpio_recovery = true, -}; - -static int dm355evm_mmc_gpios = -EINVAL; - -static void dm355evm_mmcsd_gpios(unsigned gpio) -{ - gpio_request(gpio + 0, "mmc0_ro"); - gpio_request(gpio + 1, "mmc0_cd"); - gpio_request(gpio + 2, "mmc1_ro"); - gpio_request(gpio + 3, "mmc1_cd"); - - /* we "know" these are input-only so we don't - * need to call gpio_direction_input() - */ - - dm355evm_mmc_gpios = gpio; -} - -static struct i2c_board_info dm355evm_i2c_info[] = { - { I2C_BOARD_INFO("dm355evm_msp", 0x25), - .platform_data = dm355evm_mmcsd_gpios, - }, - /* { plus irq }, */ - { I2C_BOARD_INFO("tlv320aic33", 0x1b), }, -}; - -static void __init evm_init_i2c(void) -{ - gpiod_add_lookup_table(&i2c_recovery_gpiod_table); - davinci_init_i2c(&i2c_pdata); - - gpio_request(5, "dm355evm_msp"); - gpio_direction_input(5); - dm355evm_i2c_info[0].irq = gpio_to_irq(5); - - i2c_register_board_info(1, dm355evm_i2c_info, - ARRAY_SIZE(dm355evm_i2c_info)); -} - -static struct resource dm355evm_dm9000_rsrc[] = { - { - /* addr */ - .start = 0x04014000, - .end = 0x04014001, - .flags = IORESOURCE_MEM, - }, { - /* data */ - .start = 0x04014002, - .end = 0x04014003, - .flags = IORESOURCE_MEM, - }, { - .flags = IORESOURCE_IRQ - | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */, - }, -}; - -static struct dm9000_plat_data dm335evm_dm9000_platdata; - -static struct platform_device dm355evm_dm9000 = { - .name = "dm9000", - .id = -1, - .resource = dm355evm_dm9000_rsrc, - .num_resources = ARRAY_SIZE(dm355evm_dm9000_rsrc), - .dev = { - .platform_data = &dm335evm_dm9000_platdata, - }, -}; - -static struct tvp514x_platform_data tvp5146_pdata = { - .clk_polarity = 0, - .hs_polarity = 1, - .vs_polarity = 1 -}; - -#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) -/* Inputs available at the TVP5146 */ -static struct v4l2_input tvp5146_inputs[] = { - { - .index = 0, - .name = "Composite", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = TVP514X_STD_ALL, - }, - { - .index = 1, - .name = "S-Video", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = TVP514X_STD_ALL, - }, -}; - -/* - * this is the route info for connecting each input to decoder - * ouput that goes to vpfe. There is a one to one correspondence - * with tvp5146_inputs - */ -static struct vpfe_route tvp5146_routes[] = { - { - .input = INPUT_CVBS_VI2B, - .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, - }, - { - .input = INPUT_SVIDEO_VI2C_VI1C, - .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, - }, -}; - -static struct vpfe_subdev_info vpfe_sub_devs[] = { - { - .name = "tvp5146", - .grp_id = 0, - .num_inputs = ARRAY_SIZE(tvp5146_inputs), - .inputs = tvp5146_inputs, - .routes = tvp5146_routes, - .can_route = 1, - .ccdc_if_params = { - .if_type = VPFE_BT656, - .hdpol = VPFE_PINPOL_POSITIVE, - .vdpol = VPFE_PINPOL_POSITIVE, - }, - .board_info = { - I2C_BOARD_INFO("tvp5146", 0x5d), - .platform_data = &tvp5146_pdata, - }, - } -}; - -static struct vpfe_config vpfe_cfg = { - .num_subdevs = ARRAY_SIZE(vpfe_sub_devs), - .i2c_adapter_id = 1, - .sub_devs = vpfe_sub_devs, - .card_name = "DM355 EVM", - .ccdc = "DM355 CCDC", -}; - -/* venc standards timings */ -static struct vpbe_enc_mode_info dm355evm_enc_preset_timing[] = { - { - .name = "ntsc", - .timings_type = VPBE_ENC_STD, - .std_id = V4L2_STD_NTSC, - .interlaced = 1, - .xres = 720, - .yres = 480, - .aspect = {11, 10}, - .fps = {30000, 1001}, - .left_margin = 0x79, - .upper_margin = 0x10, - }, - { - .name = "pal", - .timings_type = VPBE_ENC_STD, - .std_id = V4L2_STD_PAL, - .interlaced = 1, - .xres = 720, - .yres = 576, - .aspect = {54, 59}, - .fps = {25, 1}, - .left_margin = 0x7E, - .upper_margin = 0x16 - }, -}; - -#define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) - -/* - * The outputs available from VPBE + ecnoders. Keep the - * the order same as that of encoders. First those from venc followed by that - * from encoders. Index in the output refers to index on a particular encoder. - * Driver uses this index to pass it to encoder when it supports more than - * one output. Application uses index of the array to set an output. - */ -static struct vpbe_output dm355evm_vpbe_outputs[] = { - { - .output = { - .index = 0, - .name = "Composite", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .std = VENC_STD_ALL, - .capabilities = V4L2_OUT_CAP_STD, - }, - .subdev_name = DM355_VPBE_VENC_SUBDEV_NAME, - .default_mode = "ntsc", - .num_modes = ARRAY_SIZE(dm355evm_enc_preset_timing), - .modes = dm355evm_enc_preset_timing, - .if_params = MEDIA_BUS_FMT_FIXED, - }, -}; - -static struct vpbe_config dm355evm_display_cfg = { - .module_name = "dm355-vpbe-display", - .i2c_adapter_id = 1, - .osd = { - .module_name = DM355_VPBE_OSD_SUBDEV_NAME, - }, - .venc = { - .module_name = DM355_VPBE_VENC_SUBDEV_NAME, - }, - .num_outputs = ARRAY_SIZE(dm355evm_vpbe_outputs), - .outputs = dm355evm_vpbe_outputs, -}; - -static struct platform_device *davinci_evm_devices[] __initdata = { - &dm355evm_dm9000, - &davinci_nand_device, -}; - -static void __init dm355_evm_map_io(void) -{ - dm355_init(); -} - -static int dm355evm_mmc_get_cd(int module) -{ - if (!gpio_is_valid(dm355evm_mmc_gpios)) - return -ENXIO; - /* low == card present */ - return !gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 1); -} - -static int dm355evm_mmc_get_ro(int module) -{ - if (!gpio_is_valid(dm355evm_mmc_gpios)) - return -ENXIO; - /* high == card's write protect switch active */ - return gpio_get_value_cansleep(dm355evm_mmc_gpios + 2 * module + 0); -} - -static struct davinci_mmc_config dm355evm_mmc_config = { - .get_cd = dm355evm_mmc_get_cd, - .get_ro = dm355evm_mmc_get_ro, - .wires = 4, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -/* Don't connect anything to J10 unless you're only using USB host - * mode *and* have to do so with some kind of gender-bender. If - * you have proper Mini-B or Mini-A cables (or Mini-A adapters) - * the ID pin won't need any help. - */ -#define USB_ID_VALUE 1 /* ID pulled low */ - -static struct spi_eeprom at25640a = { - .byte_len = SZ_64K / 8, - .name = "at25640a", - .page_size = 32, - .flags = EE_ADDR2, -}; - -static const struct spi_board_info dm355_evm_spi_info[] __initconst = { - { - .modalias = "at25", - .platform_data = &at25640a, - .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ - .bus_num = 0, - .chip_select = 0, - .mode = SPI_MODE_0, - }, -}; - -static __init void dm355_evm_init(void) -{ - struct clk *aemif; - int ret; - - dm355_register_clocks(); - - ret = dm355_gpio_register(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - - gpio_request(1, "dm9000"); - gpio_direction_input(1); - dm355evm_dm9000_rsrc[2].start = gpio_to_irq(1); - - aemif = clk_get(&dm355evm_dm9000.dev, "aemif"); - if (!WARN(IS_ERR(aemif), "unable to get AEMIF clock\n")) - clk_prepare_enable(aemif); - - platform_add_devices(davinci_evm_devices, - ARRAY_SIZE(davinci_evm_devices)); - evm_init_i2c(); - davinci_serial_init(dm355_serial_device); - - /* NOTE: NAND flash timings set by the UBL are slower than - * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 - * but could be 0x0400008c for about 25% faster page reads. - */ - - gpio_request(2, "usb_id_toggle"); - gpio_direction_output(2, USB_ID_VALUE); - /* irlml6401 switches over 1A in under 8 msec */ - davinci_setup_usb(1000, 8); - - davinci_setup_mmc(0, &dm355evm_mmc_config); - davinci_setup_mmc(1, &dm355evm_mmc_config); - - dm355_init_video(&vpfe_cfg, &dm355evm_display_cfg); - - dm355_init_spi0(BIT(0), dm355_evm_spi_info, - ARRAY_SIZE(dm355_evm_spi_info)); - - /* DM335 EVM uses ASP1; line-out is a stereo mini-jack */ - dm355_init_asp1(ASP1_TX_EVT_EN | ASP1_RX_EVT_EN); -} - -MACHINE_START(DAVINCI_DM355_EVM, "DaVinci DM355 EVM") - .atag_offset = 0x100, - .map_io = dm355_evm_map_io, - .init_irq = dm355_init_irq, - .init_time = dm355_init_time, - .init_machine = dm355_evm_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, -MACHINE_END diff --git a/arch/arm/mach-davinci/board-dm355-leopard.c b/arch/arm/mach-davinci/board-dm355-leopard.c deleted file mode 100644 index 32b9d607d025df72f1584cf926f815740ef6fe15..0000000000000000000000000000000000000000 --- a/arch/arm/mach-davinci/board-dm355-leopard.c +++ /dev/null @@ -1,278 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * DM355 leopard board support - * - * Based on board-dm355-evm.c - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "common.h" -#include "serial.h" -#include "davinci.h" - -/* NOTE: this is geared for the standard config, with a socketed - * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you - * swap chips, maybe with a different block size, partitioning may - * need to be changed. - */ -#define NAND_BLOCK_SIZE SZ_128K - -static struct mtd_partition davinci_nand_partitions[] = { - { - /* UBL (a few copies) plus U-Boot */ - .name = "bootloader", - .offset = 0, - .size = 15 * NAND_BLOCK_SIZE, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, { - /* U-Boot environment */ - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = 1 * NAND_BLOCK_SIZE, - .mask_flags = 0, - }, { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_4M, - .mask_flags = 0, - }, { - .name = "filesystem1", - .offset = MTDPART_OFS_APPEND, - .size = SZ_512M, - .mask_flags = 0, - }, { - .name = "filesystem2", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - } - /* two blocks with bad block table (and mirror) at the end */ -}; - -static struct davinci_nand_pdata davinci_nand_data = { - .core_chipsel = 0, - .mask_chipsel = BIT(14), - .parts = davinci_nand_partitions, - .nr_parts = ARRAY_SIZE(davinci_nand_partitions), - .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, - .ecc_placement = NAND_ECC_PLACEMENT_INTERLEAVED, - .ecc_bits = 4, - .bbt_options = NAND_BBT_USE_FLASH, -}; - -static struct resource davinci_nand_resources[] = { - { - .start = DM355_ASYNC_EMIF_DATA_CE0_BASE, - .end = DM355_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, { - .start = DM355_ASYNC_EMIF_CONTROL_BASE, - .end = DM355_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device davinci_nand_device = { - .name = "davinci_nand", - .id = 0, - - .num_resources = ARRAY_SIZE(davinci_nand_resources), - .resource = davinci_nand_resources, - - .dev = { - .platform_data = &davinci_nand_data, - }, -}; - -static struct davinci_i2c_platform_data i2c_pdata = { - .bus_freq = 400 /* kHz */, - .bus_delay = 0 /* usec */, -}; - -static int leopard_mmc_gpio = -EINVAL; - -static void dm355leopard_mmcsd_gpios(unsigned gpio) -{ - gpio_request(gpio + 0, "mmc0_ro"); - gpio_request(gpio + 1, "mmc0_cd"); - gpio_request(gpio + 2, "mmc1_ro"); - gpio_request(gpio + 3, "mmc1_cd"); - - /* we "know" these are input-only so we don't - * need to call gpio_direction_input() - */ - - leopard_mmc_gpio = gpio; -} - -static struct i2c_board_info dm355leopard_i2c_info[] = { - { I2C_BOARD_INFO("dm355leopard_msp", 0x25), - .platform_data = dm355leopard_mmcsd_gpios, - /* plus irq */ }, - /* { I2C_BOARD_INFO("tlv320aic3x", 0x1b), }, */ - /* { I2C_BOARD_INFO("tvp5146", 0x5d), }, */ -}; - -static void __init leopard_init_i2c(void) -{ - davinci_init_i2c(&i2c_pdata); - - gpio_request(5, "dm355leopard_msp"); - gpio_direction_input(5); - dm355leopard_i2c_info[0].irq = gpio_to_irq(5); - - i2c_register_board_info(1, dm355leopard_i2c_info, - ARRAY_SIZE(dm355leopard_i2c_info)); -} - -static struct resource dm355leopard_dm9000_rsrc[] = { - { - /* addr */ - .start = 0x04000000, - .end = 0x04000001, - .flags = IORESOURCE_MEM, - }, { - /* data */ - .start = 0x04000016, - .end = 0x04000017, - .flags = IORESOURCE_MEM, - }, { - .flags = IORESOURCE_IRQ - | IORESOURCE_IRQ_HIGHEDGE /* rising (active high) */, - }, -}; - -static struct platform_device dm355leopard_dm9000 = { - .name = "dm9000", - .id = -1, - .resource = dm355leopard_dm9000_rsrc, - .num_resources = ARRAY_SIZE(dm355leopard_dm9000_rsrc), -}; - -static struct platform_device *davinci_leopard_devices[] __initdata = { - &dm355leopard_dm9000, - &davinci_nand_device, -}; - -static void __init dm355_leopard_map_io(void) -{ - dm355_init(); -} - -static int dm355leopard_mmc_get_cd(int module) -{ - if (!gpio_is_valid(leopard_mmc_gpio)) - return -ENXIO; - /* low == card present */ - return !gpio_get_value_cansleep(leopard_mmc_gpio + 2 * module + 1); -} - -static int dm355leopard_mmc_get_ro(int module) -{ - if (!gpio_is_valid(leopard_mmc_gpio)) - return -ENXIO; - /* high == card's write protect switch active */ - return gpio_get_value_cansleep(leopard_mmc_gpio + 2 * module + 0); -} - -static struct davinci_mmc_config dm355leopard_mmc_config = { - .get_cd = dm355leopard_mmc_get_cd, - .get_ro = dm355leopard_mmc_get_ro, - .wires = 4, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -/* Don't connect anything to J10 unless you're only using USB host - * mode *and* have to do so with some kind of gender-bender. If - * you have proper Mini-B or Mini-A cables (or Mini-A adapters) - * the ID pin won't need any help. - */ -#define USB_ID_VALUE 1 /* ID pulled low */ - -static struct spi_eeprom at25640a = { - .byte_len = SZ_64K / 8, - .name = "at25640a", - .page_size = 32, - .flags = EE_ADDR2, -}; - -static const struct spi_board_info dm355_leopard_spi_info[] __initconst = { - { - .modalias = "at25", - .platform_data = &at25640a, - .max_speed_hz = 10 * 1000 * 1000, /* at 3v3 */ - .bus_num = 0, - .chip_select = 0, - .mode = SPI_MODE_0, - }, -}; - -static __init void dm355_leopard_init(void) -{ - struct clk *aemif; - int ret; - - dm355_register_clocks(); - - ret = dm355_gpio_register(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - - gpio_request(9, "dm9000"); - gpio_direction_input(9); - dm355leopard_dm9000_rsrc[2].start = gpio_to_irq(9); - - aemif = clk_get(&dm355leopard_dm9000.dev, "aemif"); - if (!WARN(IS_ERR(aemif), "unable to get AEMIF clock\n")) - clk_prepare_enable(aemif); - - platform_add_devices(davinci_leopard_devices, - ARRAY_SIZE(davinci_leopard_devices)); - leopard_init_i2c(); - davinci_serial_init(dm355_serial_device); - - /* NOTE: NAND flash timings set by the UBL are slower than - * needed by MT29F16G08FAA chips ... EMIF.A1CR is 0x40400204 - * but could be 0x0400008c for about 25% faster page reads. - */ - - gpio_request(2, "usb_id_toggle"); - gpio_direction_output(2, USB_ID_VALUE); - /* irlml6401 switches over 1A in under 8 msec */ - davinci_setup_usb(1000, 8); - - davinci_setup_mmc(0, &dm355leopard_mmc_config); - davinci_setup_mmc(1, &dm355leopard_mmc_config); - - dm355_init_spi0(BIT(0), dm355_leopard_spi_info, - ARRAY_SIZE(dm355_leopard_spi_info)); -} - -MACHINE_START(DM355_LEOPARD, "DaVinci DM355 leopard") - .atag_offset = 0x100, - .map_io = dm355_leopard_map_io, - .init_irq = dm355_init_irq, - .init_time = dm355_init_time, - .init_machine = dm355_leopard_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, -MACHINE_END diff --git a/arch/arm/mach-davinci/board-dm365-evm.c b/arch/arm/mach-davinci/board-dm365-evm.c deleted file mode 100644 index d8c6c360818b24f10b0a44ad01170d39df441915..0000000000000000000000000000000000000000 --- a/arch/arm/mach-davinci/board-dm365-evm.c +++ /dev/null @@ -1,855 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * TI DaVinci DM365 EVM board support - * - * Copyright (C) 2009 Texas Instruments Incorporated - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include -#include -#include -#include - -#include -#include - -#include "mux.h" -#include "common.h" -#include "serial.h" -#include "davinci.h" - -static inline int have_imager(void) -{ - /* REVISIT when it's supported, trigger via Kconfig */ - return 0; -} - -static inline int have_tvp7002(void) -{ - /* REVISIT when it's supported, trigger via Kconfig */ - return 0; -} - -#define DM365_EVM_PHY_ID "davinci_mdio-0:01" -/* - * A MAX-II CPLD is used for various board control functions. - */ -#define CPLD_OFFSET(a13a8,a2a1) (((a13a8) << 10) + ((a2a1) << 3)) - -#define CPLD_VERSION CPLD_OFFSET(0,0) /* r/o */ -#define CPLD_TEST CPLD_OFFSET(0,1) -#define CPLD_LEDS CPLD_OFFSET(0,2) -#define CPLD_MUX CPLD_OFFSET(0,3) -#define CPLD_SWITCH CPLD_OFFSET(1,0) /* r/o */ -#define CPLD_POWER CPLD_OFFSET(1,1) -#define CPLD_VIDEO CPLD_OFFSET(1,2) -#define CPLD_CARDSTAT CPLD_OFFSET(1,3) /* r/o */ - -#define CPLD_DILC_OUT CPLD_OFFSET(2,0) -#define CPLD_DILC_IN CPLD_OFFSET(2,1) /* r/o */ - -#define CPLD_IMG_DIR0 CPLD_OFFSET(2,2) -#define CPLD_IMG_MUX0 CPLD_OFFSET(2,3) -#define CPLD_IMG_MUX1 CPLD_OFFSET(3,0) -#define CPLD_IMG_DIR1 CPLD_OFFSET(3,1) -#define CPLD_IMG_MUX2 CPLD_OFFSET(3,2) -#define CPLD_IMG_MUX3 CPLD_OFFSET(3,3) -#define CPLD_IMG_DIR2 CPLD_OFFSET(4,0) -#define CPLD_IMG_MUX4 CPLD_OFFSET(4,1) -#define CPLD_IMG_MUX5 CPLD_OFFSET(4,2) - -#define CPLD_RESETS CPLD_OFFSET(4,3) - -#define CPLD_CCD_DIR1 CPLD_OFFSET(0x3e,0) -#define CPLD_CCD_IO1 CPLD_OFFSET(0x3e,1) -#define CPLD_CCD_DIR2 CPLD_OFFSET(0x3e,2) -#define CPLD_CCD_IO2 CPLD_OFFSET(0x3e,3) -#define CPLD_CCD_DIR3 CPLD_OFFSET(0x3f,0) -#define CPLD_CCD_IO3 CPLD_OFFSET(0x3f,1) - -static void __iomem *cpld; - - -/* NOTE: this is geared for the standard config, with a socketed - * 2 GByte Micron NAND (MT29F16G08FAA) using 128KB sectors. If you - * swap chips with a different block size, partitioning will - * need to be changed. This NAND chip MT29F16G08FAA is the default - * NAND shipped with the Spectrum Digital DM365 EVM - */ -#define NAND_BLOCK_SIZE SZ_128K - -static struct mtd_partition davinci_nand_partitions[] = { - { - /* UBL (a few copies) plus U-Boot */ - .name = "bootloader", - .offset = 0, - .size = 30 * NAND_BLOCK_SIZE, - .mask_flags = MTD_WRITEABLE, /* force read-only */ - }, { - /* U-Boot environment */ - .name = "params", - .offset = MTDPART_OFS_APPEND, - .size = 2 * NAND_BLOCK_SIZE, - .mask_flags = 0, - }, { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_4M, - .mask_flags = 0, - }, { - .name = "filesystem1", - .offset = MTDPART_OFS_APPEND, - .size = SZ_512M, - .mask_flags = 0, - }, { - .name = "filesystem2", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - } - /* two blocks with bad block table (and mirror) at the end */ -}; - -static struct davinci_nand_pdata davinci_nand_data = { - .core_chipsel = 0, - .mask_chipsel = BIT(14), - .parts = davinci_nand_partitions, - .nr_parts = ARRAY_SIZE(davinci_nand_partitions), - .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, - .bbt_options = NAND_BBT_USE_FLASH, - .ecc_bits = 4, -}; - -static struct resource davinci_nand_resources[] = { - { - .start = DM365_ASYNC_EMIF_DATA_CE0_BASE, - .end = DM365_ASYNC_EMIF_DATA_CE0_BASE + SZ_32M - 1, - .flags = IORESOURCE_MEM, - }, { - .start = DM365_ASYNC_EMIF_CONTROL_BASE, - .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device davinci_aemif_devices[] = { - { - .name = "davinci_nand", - .id = 0, - .num_resources = ARRAY_SIZE(davinci_nand_resources), - .resource = davinci_nand_resources, - .dev = { - .platform_data = &davinci_nand_data, - }, - } -}; - -static struct resource davinci_aemif_resources[] = { - { - .start = DM365_ASYNC_EMIF_CONTROL_BASE, - .end = DM365_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct aemif_abus_data da850_evm_aemif_abus_data[] = { - { - .cs = 1, - }, -}; - -static struct aemif_platform_data davinci_aemif_pdata = { - .abus_data = da850_evm_aemif_abus_data, - .num_abus_data = ARRAY_SIZE(da850_evm_aemif_abus_data), - .sub_devices = davinci_aemif_devices, - .num_sub_devices = ARRAY_SIZE(davinci_aemif_devices), -}; - -static struct platform_device davinci_aemif_device = { - .name = "ti-aemif", - .id = -1, - .dev = { - .platform_data = &davinci_aemif_pdata, - }, - .resource = davinci_aemif_resources, - .num_resources = ARRAY_SIZE(davinci_aemif_resources), -}; - -static struct nvmem_cell_info davinci_nvmem_cells[] = { - { - .name = "macaddr", - .offset = 0x7f00, - .bytes = ETH_ALEN, - } -}; - -static struct nvmem_cell_table davinci_nvmem_cell_table = { - .nvmem_name = "1-00500", - .cells = davinci_nvmem_cells, - .ncells = ARRAY_SIZE(davinci_nvmem_cells), -}; - -static struct nvmem_cell_lookup davinci_nvmem_cell_lookup = { - .nvmem_name = "1-00500", - .cell_name = "macaddr", - .dev_id = "davinci_emac.1", - .con_id = "mac-address", -}; - -static const struct property_entry eeprom_properties[] = { - PROPERTY_ENTRY_U32("pagesize", 64), - { } -}; - -static const struct software_node eeprom_node = { - .properties = eeprom_properties, -}; - -static struct i2c_board_info i2c_info[] = { - { - I2C_BOARD_INFO("24c256", 0x50), - .swnode = &eeprom_node, - }, - { - I2C_BOARD_INFO("tlv320aic3x", 0x18), - }, -}; - -static struct davinci_i2c_platform_data i2c_pdata = { - .bus_freq = 400 /* kHz */, - .bus_delay = 0 /* usec */, -}; - -/* Fixed regulator support */ -static struct regulator_consumer_supply fixed_supplies_3_3v[] = { - /* Baseboard 3.3V: 5V -> TPS767D301 -> 3.3V */ - REGULATOR_SUPPLY("AVDD", "1-0018"), - REGULATOR_SUPPLY("DRVDD", "1-0018"), - REGULATOR_SUPPLY("IOVDD", "1-0018"), -}; - -static struct regulator_consumer_supply fixed_supplies_1_8v[] = { - /* Baseboard 1.8V: 5V -> TPS767D301 -> 1.8V */ - REGULATOR_SUPPLY("DVDD", "1-0018"), -}; - -static int dm365evm_keyscan_enable(struct device *dev) -{ - return davinci_cfg_reg(DM365_KEYSCAN); -} - -static unsigned short dm365evm_keymap[] = { - KEY_KP2, - KEY_LEFT, - KEY_EXIT, - KEY_DOWN, - KEY_ENTER, - KEY_UP, - KEY_KP1, - KEY_RIGHT, - KEY_MENU, - KEY_RECORD, - KEY_REWIND, - KEY_KPMINUS, - KEY_STOP, - KEY_FASTFORWARD, - KEY_KPPLUS, - KEY_PLAYPAUSE, - 0 -}; - -static struct davinci_ks_platform_data dm365evm_ks_data = { - .device_enable = dm365evm_keyscan_enable, - .keymap = dm365evm_keymap, - .keymapsize = ARRAY_SIZE(dm365evm_keymap), - .rep = 1, - /* Scan period = strobe + interval */ - .strobe = 0x5, - .interval = 0x2, - .matrix_type = DAVINCI_KEYSCAN_MATRIX_4X4, -}; - -static int cpld_mmc_get_cd(int module) -{ - if (!cpld) - return -ENXIO; - - /* low == card present */ - return !(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 4 : 0)); -} - -static int cpld_mmc_get_ro(int module) -{ - if (!cpld) - return -ENXIO; - - /* high == card's write protect switch active */ - return !!(__raw_readb(cpld + CPLD_CARDSTAT) & BIT(module ? 5 : 1)); -} - -static struct davinci_mmc_config dm365evm_mmc_config = { - .get_cd = cpld_mmc_get_cd, - .get_ro = cpld_mmc_get_ro, - .wires = 4, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -static void dm365evm_emac_configure(void) -{ - /* - * EMAC pins are multiplexed with GPIO and UART - * Further details are available at the DM365 ARM - * Subsystem Users Guide(sprufg5.pdf) pages 125 - 127 - */ - davinci_cfg_reg(DM365_EMAC_TX_EN); - davinci_cfg_reg(DM365_EMAC_TX_CLK); - davinci_cfg_reg(DM365_EMAC_COL); - davinci_cfg_reg(DM365_EMAC_TXD3); - davinci_cfg_reg(DM365_EMAC_TXD2); - davinci_cfg_reg(DM365_EMAC_TXD1); - davinci_cfg_reg(DM365_EMAC_TXD0); - davinci_cfg_reg(DM365_EMAC_RXD3); - davinci_cfg_reg(DM365_EMAC_RXD2); - davinci_cfg_reg(DM365_EMAC_RXD1); - davinci_cfg_reg(DM365_EMAC_RXD0); - davinci_cfg_reg(DM365_EMAC_RX_CLK); - davinci_cfg_reg(DM365_EMAC_RX_DV); - davinci_cfg_reg(DM365_EMAC_RX_ER); - davinci_cfg_reg(DM365_EMAC_CRS); - davinci_cfg_reg(DM365_EMAC_MDIO); - davinci_cfg_reg(DM365_EMAC_MDCLK); - - /* - * EMAC interrupts are multiplexed with GPIO interrupts - * Details are available at the DM365 ARM - * Subsystem Users Guide(sprufg5.pdf) pages 133 - 134 - */ - davinci_cfg_reg(DM365_INT_EMAC_RXTHRESH); - davinci_cfg_reg(DM365_INT_EMAC_RXPULSE); - davinci_cfg_reg(DM365_INT_EMAC_TXPULSE); - davinci_cfg_reg(DM365_INT_EMAC_MISCPULSE); -} - -static void dm365evm_mmc_configure(void) -{ - /* - * MMC/SD pins are multiplexed with GPIO and EMIF - * Further details are available at the DM365 ARM - * Subsystem Users Guide(sprufg5.pdf) pages 118, 128 - 131 - */ - davinci_cfg_reg(DM365_SD1_CLK); - davinci_cfg_reg(DM365_SD1_CMD); - davinci_cfg_reg(DM365_SD1_DATA3); - davinci_cfg_reg(DM365_SD1_DATA2); - davinci_cfg_reg(DM365_SD1_DATA1); - davinci_cfg_reg(DM365_SD1_DATA0); -} - -static struct tvp514x_platform_data tvp5146_pdata = { - .clk_polarity = 0, - .hs_polarity = 1, - .vs_polarity = 1 -}; - -#define TVP514X_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) -/* Inputs available at the TVP5146 */ -static struct v4l2_input tvp5146_inputs[] = { - { - .index = 0, - .name = "Composite", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = TVP514X_STD_ALL, - }, - { - .index = 1, - .name = "S-Video", - .type = V4L2_INPUT_TYPE_CAMERA, - .std = TVP514X_STD_ALL, - }, -}; - -/* - * this is the route info for connecting each input to decoder - * ouput that goes to vpfe. There is a one to one correspondence - * with tvp5146_inputs - */ -static struct vpfe_route tvp5146_routes[] = { - { - .input = INPUT_CVBS_VI2B, - .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, - }, -{ - .input = INPUT_SVIDEO_VI2C_VI1C, - .output = OUTPUT_10BIT_422_EMBEDDED_SYNC, - }, -}; - -static struct vpfe_subdev_info vpfe_sub_devs[] = { - { - .name = "tvp5146", - .grp_id = 0, - .num_inputs = ARRAY_SIZE(tvp5146_inputs), - .inputs = tvp5146_inputs, - .routes = tvp5146_routes, - .can_route = 1, - .ccdc_if_params = { - .if_type = VPFE_BT656, - .hdpol = VPFE_PINPOL_POSITIVE, - .vdpol = VPFE_PINPOL_POSITIVE, - }, - .board_info = { - I2C_BOARD_INFO("tvp5146", 0x5d), - .platform_data = &tvp5146_pdata, - }, - }, -}; - -static struct vpfe_config vpfe_cfg = { - .num_subdevs = ARRAY_SIZE(vpfe_sub_devs), - .sub_devs = vpfe_sub_devs, - .i2c_adapter_id = 1, - .card_name = "DM365 EVM", - .ccdc = "ISIF", -}; - -/* venc standards timings */ -static struct vpbe_enc_mode_info dm365evm_enc_std_timing[] = { - { - .name = "ntsc", - .timings_type = VPBE_ENC_STD, - .std_id = V4L2_STD_NTSC, - .interlaced = 1, - .xres = 720, - .yres = 480, - .aspect = {11, 10}, - .fps = {30000, 1001}, - .left_margin = 0x79, - .upper_margin = 0x10, - }, - { - .name = "pal", - .timings_type = VPBE_ENC_STD, - .std_id = V4L2_STD_PAL, - .interlaced = 1, - .xres = 720, - .yres = 576, - .aspect = {54, 59}, - .fps = {25, 1}, - .left_margin = 0x7E, - .upper_margin = 0x16, - }, -}; - -/* venc dv timings */ -static struct vpbe_enc_mode_info dm365evm_enc_preset_timing[] = { - { - .name = "480p59_94", - .timings_type = VPBE_ENC_DV_TIMINGS, - .dv_timings = V4L2_DV_BT_CEA_720X480P59_94, - .interlaced = 0, - .xres = 720, - .yres = 480, - .aspect = {1, 1}, - .fps = {5994, 100}, - .left_margin = 0x8F, - .upper_margin = 0x2D, - }, - { - .name = "576p50", - .timings_type = VPBE_ENC_DV_TIMINGS, - .dv_timings = V4L2_DV_BT_CEA_720X576P50, - .interlaced = 0, - .xres = 720, - .yres = 576, - .aspect = {1, 1}, - .fps = {50, 1}, - .left_margin = 0x8C, - .upper_margin = 0x36, - }, - { - .name = "720p60", - .timings_type = VPBE_ENC_DV_TIMINGS, - .dv_timings = V4L2_DV_BT_CEA_1280X720P60, - .interlaced = 0, - .xres = 1280, - .yres = 720, - .aspect = {1, 1}, - .fps = {60, 1}, - .left_margin = 0x117, - .right_margin = 70, - .upper_margin = 38, - .lower_margin = 3, - .hsync_len = 80, - .vsync_len = 5, - }, - { - .name = "1080i60", - .timings_type = VPBE_ENC_DV_TIMINGS, - .dv_timings = V4L2_DV_BT_CEA_1920X1080I60, - .interlaced = 1, - .xres = 1920, - .yres = 1080, - .aspect = {1, 1}, - .fps = {30, 1}, - .left_margin = 0xc9, - .right_margin = 80, - .upper_margin = 30, - .lower_margin = 3, - .hsync_len = 88, - .vsync_len = 5, - }, -}; - -#define VENC_STD_ALL (V4L2_STD_NTSC | V4L2_STD_PAL) - -/* - * The outputs available from VPBE + ecnoders. Keep the - * the order same as that of encoders. First those from venc followed by that - * from encoders. Index in the output refers to index on a particular - * encoder.Driver uses this index to pass it to encoder when it supports more - * than one output. Application uses index of the array to set an output. - */ -static struct vpbe_output dm365evm_vpbe_outputs[] = { - { - .output = { - .index = 0, - .name = "Composite", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .std = VENC_STD_ALL, - .capabilities = V4L2_OUT_CAP_STD, - }, - .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME, - .default_mode = "ntsc", - .num_modes = ARRAY_SIZE(dm365evm_enc_std_timing), - .modes = dm365evm_enc_std_timing, - .if_params = MEDIA_BUS_FMT_FIXED, - }, - { - .output = { - .index = 1, - .name = "Component", - .type = V4L2_OUTPUT_TYPE_ANALOG, - .capabilities = V4L2_OUT_CAP_DV_TIMINGS, - }, - .subdev_name = DM365_VPBE_VENC_SUBDEV_NAME, - .default_mode = "480p59_94", - .num_modes = ARRAY_SIZE(dm365evm_enc_preset_timing), - .modes = dm365evm_enc_preset_timing, - .if_params = MEDIA_BUS_FMT_FIXED, - }, -}; - -/* - * Amplifiers on the board - */ -static struct ths7303_platform_data ths7303_pdata = { - .ch_1 = 3, - .ch_2 = 3, - .ch_3 = 3, -}; - -static struct amp_config_info vpbe_amp = { - .module_name = "ths7303", - .is_i2c = 1, - .board_info = { - I2C_BOARD_INFO("ths7303", 0x2c), - .platform_data = &ths7303_pdata, - } -}; - -static struct vpbe_config dm365evm_display_cfg = { - .module_name = "dm365-vpbe-display", - .i2c_adapter_id = 1, - .amp = &vpbe_amp, - .osd = { - .module_name = DM365_VPBE_OSD_SUBDEV_NAME, - }, - .venc = { - .module_name = DM365_VPBE_VENC_SUBDEV_NAME, - }, - .num_outputs = ARRAY_SIZE(dm365evm_vpbe_outputs), - .outputs = dm365evm_vpbe_outputs, -}; - -static void __init evm_init_i2c(void) -{ - davinci_init_i2c(&i2c_pdata); - i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info)); -} - -static inline int have_leds(void) -{ -#ifdef CONFIG_LEDS_CLASS - return 1; -#else - return 0; -#endif -} - -struct cpld_led { - struct led_classdev cdev; - u8 mask; -}; - -static const struct { - const char *name; - const char *trigger; -} cpld_leds[] = { - { "dm365evm::ds2", }, - { "dm365evm::ds3", }, - { "dm365evm::ds4", }, - { "dm365evm::ds5", }, - { "dm365evm::ds6", "nand-disk", }, - { "dm365evm::ds7", "mmc1", }, - { "dm365evm::ds8", "mmc0", }, - { "dm365evm::ds9", "heartbeat", }, -}; - -static void cpld_led_set(struct led_classdev *cdev, enum led_brightness b) -{ - struct cpld_led *led = container_of(cdev, struct cpld_led, cdev); - u8 reg = __raw_readb(cpld + CPLD_LEDS); - - if (b != LED_OFF) - reg &= ~led->mask; - else - reg |= led->mask; - __raw_writeb(reg, cpld + CPLD_LEDS); -} - -static enum led_brightness cpld_led_get(struct led_classdev *cdev) -{ - struct cpld_led *led = container_of(cdev, struct cpld_led, cdev); - u8 reg = __raw_readb(cpld + CPLD_LEDS); - - return (reg & led->mask) ? LED_OFF : LED_FULL; -} - -static int __init cpld_leds_init(void) -{ - int i; - - if (!have_leds() || !cpld) - return 0; - - /* setup LEDs */ - __raw_writeb(0xff, cpld + CPLD_LEDS); - for (i = 0; i < ARRAY_SIZE(cpld_leds); i++) { - struct cpld_led *led; - - led = kzalloc(sizeof(*led), GFP_KERNEL); - if (!led) - break; - - led->cdev.name = cpld_leds[i].name; - led->cdev.brightness_set = cpld_led_set; - led->cdev.brightness_get = cpld_led_get; - led->cdev.default_trigger = cpld_leds[i].trigger; - led->mask = BIT(i); - - if (led_classdev_register(NULL, &led->cdev) < 0) { - kfree(led); - break; - } - } - - return 0; -} -/* run after subsys_initcall() for LEDs */ -fs_initcall(cpld_leds_init); - - -static void __init evm_init_cpld(void) -{ - u8 mux, resets; - const char *label; - struct clk *aemif_clk; - int rc; - - /* Make sure we can configure the CPLD through CS1. Then - * leave it on for later access to MMC and LED registers. - */ - aemif_clk = clk_get(NULL, "aemif"); - if (IS_ERR(aemif_clk)) - return; - clk_prepare_enable(aemif_clk); - - if (request_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE, - "cpld") == NULL) - goto fail; - cpld = ioremap(DM365_ASYNC_EMIF_DATA_CE1_BASE, SECTION_SIZE); - if (!cpld) { - release_mem_region(DM365_ASYNC_EMIF_DATA_CE1_BASE, - SECTION_SIZE); -fail: - pr_err("ERROR: can't map CPLD\n"); - clk_disable_unprepare(aemif_clk); - return; - } - - /* External muxing for some signals */ - mux = 0; - - /* Read SW5 to set up NAND + keypad _or_ OneNAND (sync read). - * NOTE: SW4 bus width setting must match! - */ - if ((__raw_readb(cpld + CPLD_SWITCH) & BIT(5)) == 0) { - /* external keypad mux */ - mux |= BIT(7); - - rc = platform_device_register(&davinci_aemif_device); - if (rc) - pr_warn("%s(): error registering the aemif device: %d\n", - __func__, rc); - } else { - /* no OneNAND support yet */ - } - - /* Leave external chips in reset when unused. */ - resets = BIT(3) | BIT(2) | BIT(1) | BIT(0); - - /* Static video input config with SN74CBT16214 1-of-3 mux: - * - port b1 == tvp7002 (mux lowbits == 1 or 6) - * - port b2 == imager (mux lowbits == 2 or 7) - * - port b3 == tvp5146 (mux lowbits == 5) - * - * Runtime switching could work too, with limitations. - */ - if (have_imager()) { - label = "HD imager"; - mux |= 2; - - /* externally mux MMC1/ENET/AIC33 to imager */ - mux |= BIT(6) | BIT(5) | BIT(3); - } else { - struct davinci_soc_info *soc_info = &davinci_soc_info; - - /* we can use MMC1 ... */ - dm365evm_mmc_configure(); - davinci_setup_mmc(1, &dm365evm_mmc_config); - - /* ... and ENET ... */ - dm365evm_emac_configure(); - soc_info->emac_pdata->phy_id = DM365_EVM_PHY_ID; - resets &= ~BIT(3); - - /* ... and AIC33 */ - resets &= ~BIT(1); - - if (have_tvp7002()) { - mux |= 1; - resets &= ~BIT(2); - label = "tvp7002 HD"; - } else { - /* default to tvp5146 */ - mux |= 5; - resets &= ~BIT(0); - label = "tvp5146 SD"; - } - } - __raw_writeb(mux, cpld + CPLD_MUX); - __raw_writeb(resets, cpld + CPLD_RESETS); - pr_info("EVM: %s video input\n", label); - - /* REVISIT export switches: NTSC/PAL (SW5.6), EXTRA1 (SW5.2), etc */ -} - -static void __init dm365_evm_map_io(void) -{ - dm365_init(); -} - -static struct spi_eeprom at25640 = { - .byte_len = SZ_64K / 8, - .name = "at25640", - .page_size = 32, - .flags = EE_ADDR2, -}; - -static const struct spi_board_info dm365_evm_spi_info[] __initconst = { - { - .modalias = "at25", - .platform_data = &at25640, - .max_speed_hz = 10 * 1000 * 1000, - .bus_num = 0, - .chip_select = 0, - .mode = SPI_MODE_0, - }, -}; - -static __init void dm365_evm_init(void) -{ - int ret; - - dm365_register_clocks(); - - ret = dm365_gpio_register(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - - regulator_register_always_on(0, "fixed-dummy", fixed_supplies_1_8v, - ARRAY_SIZE(fixed_supplies_1_8v), 1800000); - regulator_register_always_on(1, "fixed-dummy", fixed_supplies_3_3v, - ARRAY_SIZE(fixed_supplies_3_3v), 3300000); - - nvmem_add_cell_table(&davinci_nvmem_cell_table); - nvmem_add_cell_lookups(&davinci_nvmem_cell_lookup, 1); - - evm_init_i2c(); - davinci_serial_init(dm365_serial_device); - - dm365evm_emac_configure(); - dm365evm_mmc_configure(); - - davinci_setup_mmc(0, &dm365evm_mmc_config); - - dm365_init_video(&vpfe_cfg, &dm365evm_display_cfg); - - /* maybe setup mmc1/etc ... _after_ mmc0 */ - evm_init_cpld(); - -#ifdef CONFIG_SND_SOC_DM365_AIC3X_CODEC - dm365_init_asp(); -#elif defined(CONFIG_SND_SOC_DM365_VOICE_CODEC) - dm365_init_vc(); -#endif - dm365_init_rtc(); - dm365_init_ks(&dm365evm_ks_data); - - dm365_init_spi0(BIT(0), dm365_evm_spi_info, - ARRAY_SIZE(dm365_evm_spi_info)); -} - -MACHINE_START(DAVINCI_DM365_EVM, "DaVinci DM365 EVM") - .atag_offset = 0x100, - .map_io = dm365_evm_map_io, - .init_irq = dm365_init_irq, - .init_time = dm365_init_time, - .init_machine = dm365_evm_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, -MACHINE_END diff --git a/arch/arm/mach-davinci/board-mityomapl138.c b/arch/arm/mach-davinci/board-mityomapl138.c deleted file mode 100644 index a46e7b9ff8e08c879f84ce88a9ca147ebfe7c72b..0000000000000000000000000000000000000000 --- a/arch/arm/mach-davinci/board-mityomapl138.c +++ /dev/null @@ -1,638 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Critical Link MityOMAP-L138 SoM - * - * Copyright (C) 2010 Critical Link LLC - https://www.criticallink.com - */ - -#define pr_fmt(fmt) "MityOMAPL138: " fmt - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#include "common.h" -#include "da8xx.h" -#include "mux.h" - -#include -#include -#include -#include - -#define MITYOMAPL138_PHY_ID "" - -#define FACTORY_CONFIG_MAGIC 0x012C0138 -#define FACTORY_CONFIG_VERSION 0x00010001 - -/* Data Held in On-Board I2C device */ -struct factory_config { - u32 magic; - u32 version; - u8 mac[6]; - u32 fpga_type; - u32 spare; - u32 serialnumber; - char partnum[32]; -}; - -static struct factory_config factory_config; - -#ifdef CONFIG_CPU_FREQ -struct part_no_info { - const char *part_no; /* part number string of interest */ - int max_freq; /* khz */ -}; - -static struct part_no_info mityomapl138_pn_info[] = { - { - .part_no = "L138-C", - .max_freq = 300000, - }, - { - .part_no = "L138-D", - .max_freq = 375000, - }, - { - .part_no = "L138-F", - .max_freq = 456000, - }, - { - .part_no = "1808-C", - .max_freq = 300000, - }, - { - .part_no = "1808-D", - .max_freq = 375000, - }, - { - .part_no = "1808-F", - .max_freq = 456000, - }, - { - .part_no = "1810-D", - .max_freq = 375000, - }, -}; - -static void mityomapl138_cpufreq_init(const char *partnum) -{ - int i, ret; - - for (i = 0; partnum && i < ARRAY_SIZE(mityomapl138_pn_info); i++) { - /* - * the part number has additional characters beyond what is - * stored in the table. This information is not needed for - * determining the speed grade, and would require several - * more table entries. Only check the first N characters - * for a match. - */ - if (!strncmp(partnum, mityomapl138_pn_info[i].part_no, - strlen(mityomapl138_pn_info[i].part_no))) { - da850_max_speed = mityomapl138_pn_info[i].max_freq; - break; - } - } - - ret = da850_register_cpufreq("pll0_sysclk3"); - if (ret) - pr_warn("cpufreq registration failed: %d\n", ret); -} -#else -static void mityomapl138_cpufreq_init(const char *partnum) { } -#endif - -static int read_factory_config(struct notifier_block *nb, - unsigned long event, void *data) -{ - int ret; - const char *partnum = NULL; - struct nvmem_device *nvmem = data; - - if (strcmp(nvmem_dev_name(nvmem), "1-00500") != 0) - return NOTIFY_DONE; - - if (!IS_BUILTIN(CONFIG_NVMEM)) { - pr_warn("Factory Config not available without CONFIG_NVMEM\n"); - goto bad_config; - } - - ret = nvmem_device_read(nvmem, 0, sizeof(factory_config), - &factory_config); - if (ret != sizeof(struct factory_config)) { - pr_warn("Read Factory Config Failed: %d\n", ret); - goto bad_config; - } - - if (factory_config.magic != FACTORY_CONFIG_MAGIC) { - pr_warn("Factory Config Magic Wrong (%X)\n", - factory_config.magic); - goto bad_config; - } - - if (factory_config.version != FACTORY_CONFIG_VERSION) { - pr_warn("Factory Config Version Wrong (%X)\n", - factory_config.version); - goto bad_config; - } - - partnum = factory_config.partnum; - pr_info("Part Number = %s\n", partnum); - -bad_config: - /* default maximum speed is valid for all platforms */ - mityomapl138_cpufreq_init(partnum); - - return NOTIFY_STOP; -} - -static struct notifier_block mityomapl138_nvmem_notifier = { - .notifier_call = read_factory_config, -}; - -/* - * We don't define a cell for factory config as it will be accessed from the - * board file using the nvmem notifier chain. - */ -static struct nvmem_cell_info mityomapl138_nvmem_cells[] = { - { - .name = "macaddr", - .offset = 0x64, - .bytes = ETH_ALEN, - } -}; - -static struct nvmem_cell_table mityomapl138_nvmem_cell_table = { - .nvmem_name = "1-00500", - .cells = mityomapl138_nvmem_cells, - .ncells = ARRAY_SIZE(mityomapl138_nvmem_cells), -}; - -static struct nvmem_cell_lookup mityomapl138_nvmem_cell_lookup = { - .nvmem_name = "1-00500", - .cell_name = "macaddr", - .dev_id = "davinci_emac.1", - .con_id = "mac-address", -}; - -static const struct property_entry mityomapl138_fd_chip_properties[] = { - PROPERTY_ENTRY_U32("pagesize", 8), - PROPERTY_ENTRY_BOOL("read-only"), - { } -}; - -static const struct software_node mityomapl138_fd_chip_node = { - .properties = mityomapl138_fd_chip_properties, -}; - -static struct davinci_i2c_platform_data mityomap_i2c_0_pdata = { - .bus_freq = 100, /* kHz */ - .bus_delay = 0, /* usec */ -}; - -/* TPS65023 voltage regulator support */ -/* 1.2V Core */ -static struct regulator_consumer_supply tps65023_dcdc1_consumers[] = { - { - .supply = "cvdd", - }, -}; - -/* 1.8V */ -static struct regulator_consumer_supply tps65023_dcdc2_consumers[] = { - { - .supply = "usb0_vdda18", - }, - { - .supply = "usb1_vdda18", - }, - { - .supply = "ddr_dvdd18", - }, - { - .supply = "sata_vddr", - }, -}; - -/* 1.2V */ -static struct regulator_consumer_supply tps65023_dcdc3_consumers[] = { - { - .supply = "sata_vdd", - }, - { - .supply = "usb_cvdd", - }, - { - .supply = "pll0_vdda", - }, - { - .supply = "pll1_vdda", - }, -}; - -/* 1.8V Aux LDO, not used */ -static struct regulator_consumer_supply tps65023_ldo1_consumers[] = { - { - .supply = "1.8v_aux", - }, -}; - -/* FPGA VCC Aux (2.5 or 3.3) LDO */ -static struct regulator_consumer_supply tps65023_ldo2_consumers[] = { - { - .supply = "vccaux", - }, -}; - -static struct regulator_init_data tps65023_regulator_data[] = { - /* dcdc1 */ - { - .constraints = { - .min_uV = 1150000, - .max_uV = 1350000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc1_consumers), - .consumer_supplies = tps65023_dcdc1_consumers, - }, - /* dcdc2 */ - { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc2_consumers), - .consumer_supplies = tps65023_dcdc2_consumers, - }, - /* dcdc3 */ - { - .constraints = { - .min_uV = 1200000, - .max_uV = 1200000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65023_dcdc3_consumers), - .consumer_supplies = tps65023_dcdc3_consumers, - }, - /* ldo1 */ - { - .constraints = { - .min_uV = 1800000, - .max_uV = 1800000, - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo1_consumers), - .consumer_supplies = tps65023_ldo1_consumers, - }, - /* ldo2 */ - { - .constraints = { - .min_uV = 2500000, - .max_uV = 3300000, - .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE | - REGULATOR_CHANGE_STATUS, - .boot_on = 1, - }, - .num_consumer_supplies = ARRAY_SIZE(tps65023_ldo2_consumers), - .consumer_supplies = tps65023_ldo2_consumers, - }, -}; - -static struct i2c_board_info __initdata mityomap_tps65023_info[] = { - { - I2C_BOARD_INFO("tps65023", 0x48), - .platform_data = &tps65023_regulator_data[0], - }, - { - I2C_BOARD_INFO("24c02", 0x50), - .swnode = &mityomapl138_fd_chip_node, - }, -}; - -static int __init pmic_tps65023_init(void) -{ - return i2c_register_board_info(1, mityomap_tps65023_info, - ARRAY_SIZE(mityomap_tps65023_info)); -} - -/* - * SPI Devices: - * SPI1_CS0: 8M Flash ST-M25P64-VME6G - */ -static struct mtd_partition spi_flash_partitions[] = { - [0] = { - .name = "ubl", - .offset = 0, - .size = SZ_64K, - .mask_flags = MTD_WRITEABLE, - }, - [1] = { - .name = "u-boot", - .offset = MTDPART_OFS_APPEND, - .size = SZ_512K, - .mask_flags = MTD_WRITEABLE, - }, - [2] = { - .name = "u-boot-env", - .offset = MTDPART_OFS_APPEND, - .size = SZ_64K, - .mask_flags = MTD_WRITEABLE, - }, - [3] = { - .name = "periph-config", - .offset = MTDPART_OFS_APPEND, - .size = SZ_64K, - .mask_flags = MTD_WRITEABLE, - }, - [4] = { - .name = "reserved", - .offset = MTDPART_OFS_APPEND, - .size = SZ_256K + SZ_64K, - }, - [5] = { - .name = "kernel", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M + SZ_1M, - }, - [6] = { - .name = "fpga", - .offset = MTDPART_OFS_APPEND, - .size = SZ_2M, - }, - [7] = { - .name = "spare", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - }, -}; - -static struct flash_platform_data mityomapl138_spi_flash_data = { - .name = "m25p80", - .parts = spi_flash_partitions, - .nr_parts = ARRAY_SIZE(spi_flash_partitions), - .type = "m24p64", -}; - -static struct davinci_spi_config spi_eprom_config = { - .io_type = SPI_IO_TYPE_DMA, - .c2tdelay = 8, - .t2cdelay = 8, -}; - -static struct spi_board_info mityomapl138_spi_flash_info[] = { - { - .modalias = "m25p80", - .platform_data = &mityomapl138_spi_flash_data, - .controller_data = &spi_eprom_config, - .mode = SPI_MODE_0, - .max_speed_hz = 30000000, - .bus_num = 1, - .chip_select = 0, - }, -}; - -/* - * MityDSP-L138 includes a 256 MByte large-page NAND flash - * (128K blocks). - */ -static struct mtd_partition mityomapl138_nandflash_partition[] = { - { - .name = "rootfs", - .offset = 0, - .size = SZ_128M, - .mask_flags = 0, /* MTD_WRITEABLE, */ - }, - { - .name = "homefs", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - }, -}; - -static struct davinci_nand_pdata mityomapl138_nandflash_data = { - .core_chipsel = 1, - .parts = mityomapl138_nandflash_partition, - .nr_parts = ARRAY_SIZE(mityomapl138_nandflash_partition), - .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, - .bbt_options = NAND_BBT_USE_FLASH, - .options = NAND_BUSWIDTH_16, - .ecc_bits = 1, /* 4 bit mode is not supported with 16 bit NAND */ -}; - -static struct resource mityomapl138_nandflash_resource[] = { - { - .start = DA8XX_AEMIF_CS3_BASE, - .end = DA8XX_AEMIF_CS3_BASE + SZ_512K + 2 * SZ_1K - 1, - .flags = IORESOURCE_MEM, - }, - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device mityomapl138_aemif_devices[] = { - { - .name = "davinci_nand", - .id = 1, - .dev = { - .platform_data = &mityomapl138_nandflash_data, - }, - .num_resources = ARRAY_SIZE(mityomapl138_nandflash_resource), - .resource = mityomapl138_nandflash_resource, - }, -}; - -static struct resource mityomapl138_aemif_resources[] = { - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct aemif_abus_data mityomapl138_aemif_abus_data[] = { - { - .cs = 1, - }, -}; - -static struct aemif_platform_data mityomapl138_aemif_pdata = { - .abus_data = mityomapl138_aemif_abus_data, - .num_abus_data = ARRAY_SIZE(mityomapl138_aemif_abus_data), - .sub_devices = mityomapl138_aemif_devices, - .num_sub_devices = ARRAY_SIZE(mityomapl138_aemif_devices), -}; - -static struct platform_device mityomapl138_aemif_device = { - .name = "ti-aemif", - .id = -1, - .dev = { - .platform_data = &mityomapl138_aemif_pdata, - }, - .resource = mityomapl138_aemif_resources, - .num_resources = ARRAY_SIZE(mityomapl138_aemif_resources), -}; - -static void __init mityomapl138_setup_nand(void) -{ - if (platform_device_register(&mityomapl138_aemif_device)) - pr_warn("%s: Cannot register AEMIF device\n", __func__); -} - -static const short mityomap_mii_pins[] = { - DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, - DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, - DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, - DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, - DA850_MDIO_D, - -1 -}; - -static const short mityomap_rmii_pins[] = { - DA850_RMII_TXD_0, DA850_RMII_TXD_1, DA850_RMII_TXEN, - DA850_RMII_CRS_DV, DA850_RMII_RXD_0, DA850_RMII_RXD_1, - DA850_RMII_RXER, DA850_RMII_MHZ_50_CLK, DA850_MDIO_CLK, - DA850_MDIO_D, - -1 -}; - -static void __init mityomapl138_config_emac(void) -{ - void __iomem *cfg_chip3_base; - int ret; - u32 val; - struct davinci_soc_info *soc_info = &davinci_soc_info; - - soc_info->emac_pdata->rmii_en = 0; /* hardcoded for now */ - - cfg_chip3_base = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); - val = __raw_readl(cfg_chip3_base); - - if (soc_info->emac_pdata->rmii_en) { - val |= BIT(8); - ret = davinci_cfg_reg_list(mityomap_rmii_pins); - pr_info("RMII PHY configured\n"); - } else { - val &= ~BIT(8); - ret = davinci_cfg_reg_list(mityomap_mii_pins); - pr_info("MII PHY configured\n"); - } - - if (ret) { - pr_warn("mii/rmii mux setup failed: %d\n", ret); - return; - } - - /* configure the CFGCHIP3 register for RMII or MII */ - __raw_writel(val, cfg_chip3_base); - - soc_info->emac_pdata->phy_id = MITYOMAPL138_PHY_ID; - - ret = da8xx_register_emac(); - if (ret) - pr_warn("emac registration failed: %d\n", ret); -} - -static void __init mityomapl138_init(void) -{ - int ret; - - da850_register_clocks(); - - /* for now, no special EDMA channels are reserved */ - ret = da850_register_edma(NULL); - if (ret) - pr_warn("edma registration failed: %d\n", ret); - - ret = da8xx_register_watchdog(); - if (ret) - pr_warn("watchdog registration failed: %d\n", ret); - - davinci_serial_init(da8xx_serial_device); - - nvmem_register_notifier(&mityomapl138_nvmem_notifier); - nvmem_add_cell_table(&mityomapl138_nvmem_cell_table); - nvmem_add_cell_lookups(&mityomapl138_nvmem_cell_lookup, 1); - - ret = da8xx_register_i2c(0, &mityomap_i2c_0_pdata); - if (ret) - pr_warn("i2c0 registration failed: %d\n", ret); - - ret = pmic_tps65023_init(); - if (ret) - pr_warn("TPS65023 PMIC init failed: %d\n", ret); - - mityomapl138_setup_nand(); - - ret = spi_register_board_info(mityomapl138_spi_flash_info, - ARRAY_SIZE(mityomapl138_spi_flash_info)); - if (ret) - pr_warn("spi info registration failed: %d\n", ret); - - ret = da8xx_register_spi_bus(1, - ARRAY_SIZE(mityomapl138_spi_flash_info)); - if (ret) - pr_warn("spi 1 registration failed: %d\n", ret); - - mityomapl138_config_emac(); - - ret = da8xx_register_rtc(); - if (ret) - pr_warn("rtc setup failed: %d\n", ret); - - ret = da8xx_register_cpuidle(); - if (ret) - pr_warn("cpuidle registration failed: %d\n", ret); - - davinci_pm_init(); -} - -#ifdef CONFIG_SERIAL_8250_CONSOLE -static int __init mityomapl138_console_init(void) -{ - if (!machine_is_mityomapl138()) - return 0; - - return add_preferred_console("ttyS", 1, "115200"); -} -console_initcall(mityomapl138_console_init); -#endif - -static void __init mityomapl138_map_io(void) -{ - da850_init(); -} - -MACHINE_START(MITYOMAPL138, "MityDSP-L138/MityARM-1808") - .atag_offset = 0x100, - .map_io = mityomapl138_map_io, - .init_irq = da850_init_irq, - .init_time = da850_init_time, - .init_machine = mityomapl138_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, -MACHINE_END diff --git a/arch/arm/mach-davinci/board-omapl138-hawk.c b/arch/arm/mach-davinci/board-omapl138-hawk.c deleted file mode 100644 index 8a80115999ad71d3a744ac5341c54ccef2d585eb..0000000000000000000000000000000000000000 --- a/arch/arm/mach-davinci/board-omapl138-hawk.c +++ /dev/null @@ -1,451 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0-only -/* - * Hawkboard.org based on TI's OMAP-L138 Platform - * - * Initial code: Syed Mohammed Khasim - * - * Copyright (C) 2009 Texas Instruments Incorporated - https://www.ti.com - */ -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -#include "common.h" -#include "da8xx.h" -#include "mux.h" - -#define HAWKBOARD_PHY_ID "davinci_mdio-0:07" - -#define DA850_USB1_VBUS_PIN GPIO_TO_PIN(2, 4) -#define DA850_USB1_OC_PIN GPIO_TO_PIN(6, 13) - -static short omapl138_hawk_mii_pins[] __initdata = { - DA850_MII_TXEN, DA850_MII_TXCLK, DA850_MII_COL, DA850_MII_TXD_3, - DA850_MII_TXD_2, DA850_MII_TXD_1, DA850_MII_TXD_0, DA850_MII_RXER, - DA850_MII_CRS, DA850_MII_RXCLK, DA850_MII_RXDV, DA850_MII_RXD_3, - DA850_MII_RXD_2, DA850_MII_RXD_1, DA850_MII_RXD_0, DA850_MDIO_CLK, - DA850_MDIO_D, - -1 -}; - -static __init void omapl138_hawk_config_emac(void) -{ - void __iomem *cfgchip3 = DA8XX_SYSCFG0_VIRT(DA8XX_CFGCHIP3_REG); - int ret; - u32 val; - struct davinci_soc_info *soc_info = &davinci_soc_info; - - val = __raw_readl(cfgchip3); - val &= ~BIT(8); - ret = davinci_cfg_reg_list(omapl138_hawk_mii_pins); - if (ret) { - pr_warn("%s: CPGMAC/MII mux setup failed: %d\n", __func__, ret); - return; - } - - /* configure the CFGCHIP3 register for MII */ - __raw_writel(val, cfgchip3); - pr_info("EMAC: MII PHY configured\n"); - - soc_info->emac_pdata->phy_id = HAWKBOARD_PHY_ID; - - ret = da8xx_register_emac(); - if (ret) - pr_warn("%s: EMAC registration failed: %d\n", __func__, ret); -} - -/* - * The following EDMA channels/slots are not being used by drivers (for - * example: Timer, GPIO, UART events etc) on da850/omap-l138 EVM/Hawkboard, - * hence they are being reserved for codecs on the DSP side. - */ -static const s16 da850_dma0_rsv_chans[][2] = { - /* (offset, number) */ - { 8, 6}, - {24, 4}, - {30, 2}, - {-1, -1} -}; - -static const s16 da850_dma0_rsv_slots[][2] = { - /* (offset, number) */ - { 8, 6}, - {24, 4}, - {30, 50}, - {-1, -1} -}; - -static const s16 da850_dma1_rsv_chans[][2] = { - /* (offset, number) */ - { 0, 28}, - {30, 2}, - {-1, -1} -}; - -static const s16 da850_dma1_rsv_slots[][2] = { - /* (offset, number) */ - { 0, 28}, - {30, 90}, - {-1, -1} -}; - -static struct edma_rsv_info da850_edma_cc0_rsv = { - .rsv_chans = da850_dma0_rsv_chans, - .rsv_slots = da850_dma0_rsv_slots, -}; - -static struct edma_rsv_info da850_edma_cc1_rsv = { - .rsv_chans = da850_dma1_rsv_chans, - .rsv_slots = da850_dma1_rsv_slots, -}; - -static struct edma_rsv_info *da850_edma_rsv[2] = { - &da850_edma_cc0_rsv, - &da850_edma_cc1_rsv, -}; - -static const short hawk_mmcsd0_pins[] = { - DA850_MMCSD0_DAT_0, DA850_MMCSD0_DAT_1, DA850_MMCSD0_DAT_2, - DA850_MMCSD0_DAT_3, DA850_MMCSD0_CLK, DA850_MMCSD0_CMD, - DA850_GPIO3_12, DA850_GPIO3_13, - -1 -}; - -#define DA850_HAWK_MMCSD_CD_PIN GPIO_TO_PIN(3, 12) -#define DA850_HAWK_MMCSD_WP_PIN GPIO_TO_PIN(3, 13) - -static struct gpiod_lookup_table mmc_gpios_table = { - .dev_id = "da830-mmc.0", - .table = { - GPIO_LOOKUP("davinci_gpio", DA850_HAWK_MMCSD_CD_PIN, "cd", - GPIO_ACTIVE_LOW), - GPIO_LOOKUP("davinci_gpio", DA850_HAWK_MMCSD_WP_PIN, "wp", - GPIO_ACTIVE_LOW), - }, -}; - -static struct davinci_mmc_config da850_mmc_config = { - .wires = 4, - .max_freq = 50000000, - .caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED, -}; - -static __init void omapl138_hawk_mmc_init(void) -{ - int ret; - - ret = davinci_cfg_reg_list(hawk_mmcsd0_pins); - if (ret) { - pr_warn("%s: MMC/SD0 mux setup failed: %d\n", __func__, ret); - return; - } - - gpiod_add_lookup_table(&mmc_gpios_table); - - ret = da8xx_register_mmcsd0(&da850_mmc_config); - if (ret) { - pr_warn("%s: MMC/SD0 registration failed: %d\n", __func__, ret); - goto mmc_setup_mmcsd_fail; - } - - return; - -mmc_setup_mmcsd_fail: - gpiod_remove_lookup_table(&mmc_gpios_table); -} - -static struct mtd_partition omapl138_hawk_nandflash_partition[] = { - { - .name = "u-boot env", - .offset = 0, - .size = SZ_128K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "u-boot", - .offset = MTDPART_OFS_APPEND, - .size = SZ_512K, - .mask_flags = MTD_WRITEABLE, - }, - { - .name = "free space", - .offset = MTDPART_OFS_APPEND, - .size = MTDPART_SIZ_FULL, - .mask_flags = 0, - }, -}; - -static struct davinci_aemif_timing omapl138_hawk_nandflash_timing = { - .wsetup = 24, - .wstrobe = 21, - .whold = 14, - .rsetup = 19, - .rstrobe = 50, - .rhold = 0, - .ta = 20, -}; - -static struct davinci_nand_pdata omapl138_hawk_nandflash_data = { - .core_chipsel = 1, - .parts = omapl138_hawk_nandflash_partition, - .nr_parts = ARRAY_SIZE(omapl138_hawk_nandflash_partition), - .engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST, - .ecc_bits = 4, - .bbt_options = NAND_BBT_USE_FLASH, - .options = NAND_BUSWIDTH_16, - .timing = &omapl138_hawk_nandflash_timing, - .mask_chipsel = 0, - .mask_ale = 0, - .mask_cle = 0, -}; - -static struct resource omapl138_hawk_nandflash_resource[] = { - { - .start = DA8XX_AEMIF_CS3_BASE, - .end = DA8XX_AEMIF_CS3_BASE + SZ_32M, - .flags = IORESOURCE_MEM, - }, - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K, - .flags = IORESOURCE_MEM, - }, -}; - -static struct resource omapl138_hawk_aemif_resource[] = { - { - .start = DA8XX_AEMIF_CTL_BASE, - .end = DA8XX_AEMIF_CTL_BASE + SZ_32K, - .flags = IORESOURCE_MEM, - } -}; - -static struct aemif_abus_data omapl138_hawk_aemif_abus_data[] = { - { - .cs = 3, - } -}; - -static struct platform_device omapl138_hawk_aemif_devices[] = { - { - .name = "davinci_nand", - .id = -1, - .dev = { - .platform_data = &omapl138_hawk_nandflash_data, - }, - .resource = omapl138_hawk_nandflash_resource, - .num_resources = ARRAY_SIZE(omapl138_hawk_nandflash_resource), - } -}; - -static struct aemif_platform_data omapl138_hawk_aemif_pdata = { - .cs_offset = 2, - .abus_data = omapl138_hawk_aemif_abus_data, - .num_abus_data = ARRAY_SIZE(omapl138_hawk_aemif_abus_data), - .sub_devices = omapl138_hawk_aemif_devices, - .num_sub_devices = ARRAY_SIZE(omapl138_hawk_aemif_devices), -}; - -static struct platform_device omapl138_hawk_aemif_device = { - .name = "ti-aemif", - .id = -1, - .dev = { - .platform_data = &omapl138_hawk_aemif_pdata, - }, - .resource = omapl138_hawk_aemif_resource, - .num_resources = ARRAY_SIZE(omapl138_hawk_aemif_resource), -}; - -static const short omapl138_hawk_nand_pins[] = { - DA850_EMA_WAIT_1, DA850_NEMA_OE, DA850_NEMA_WE, DA850_NEMA_CS_3, - DA850_EMA_D_0, DA850_EMA_D_1, DA850_EMA_D_2, DA850_EMA_D_3, - DA850_EMA_D_4, DA850_EMA_D_5, DA850_EMA_D_6, DA850_EMA_D_7, - DA850_EMA_D_8, DA850_EMA_D_9, DA850_EMA_D_10, DA850_EMA_D_11, - DA850_EMA_D_12, DA850_EMA_D_13, DA850_EMA_D_14, DA850_EMA_D_15, - DA850_EMA_A_1, DA850_EMA_A_2, - -1 -}; - -static int omapl138_hawk_register_aemif(void) -{ - int ret; - - ret = davinci_cfg_reg_list(omapl138_hawk_nand_pins); - if (ret) - pr_warn("%s: NAND mux setup failed: %d\n", __func__, ret); - - return platform_device_register(&omapl138_hawk_aemif_device); -} - -static const short da850_hawk_usb11_pins[] = { - DA850_GPIO2_4, DA850_GPIO6_13, - -1 -}; - -static struct regulator_consumer_supply hawk_usb_supplies[] = { - REGULATOR_SUPPLY("vbus", NULL), -}; - -static struct regulator_init_data hawk_usb_vbus_data = { - .consumer_supplies = hawk_usb_supplies, - .num_consumer_supplies = ARRAY_SIZE(hawk_usb_supplies), - .constraints = { - .valid_ops_mask = REGULATOR_CHANGE_STATUS, - }, -}; - -static struct fixed_voltage_config hawk_usb_vbus = { - .supply_name = "vbus", - .microvolts = 3300000, - .init_data = &hawk_usb_vbus_data, -}; - -static struct platform_device hawk_usb_vbus_device = { - .name = "reg-fixed-voltage", - .id = 0, - .dev = { - .platform_data = &hawk_usb_vbus, - }, -}; - -static struct gpiod_lookup_table hawk_usb_oc_gpio_lookup = { - .dev_id = "ohci-da8xx", - .table = { - GPIO_LOOKUP("davinci_gpio", DA850_USB1_OC_PIN, "oc", 0), - { } - }, -}; - -static struct gpiod_lookup_table hawk_usb_vbus_gpio_lookup = { - .dev_id = "reg-fixed-voltage.0", - .table = { - GPIO_LOOKUP("davinci_gpio", DA850_USB1_VBUS_PIN, NULL, 0), - { } - }, -}; - -static struct gpiod_lookup_table *hawk_usb_gpio_lookups[] = { - &hawk_usb_oc_gpio_lookup, - &hawk_usb_vbus_gpio_lookup, -}; - -static struct da8xx_ohci_root_hub omapl138_hawk_usb11_pdata = { - /* TPS2087 switch @ 5V */ - .potpgt = (3 + 1) / 2, /* 3 ms max */ -}; - -static __init void omapl138_hawk_usb_init(void) -{ - int ret; - - ret = davinci_cfg_reg_list(da850_hawk_usb11_pins); - if (ret) { - pr_warn("%s: USB 1.1 PinMux setup failed: %d\n", __func__, ret); - return; - } - - ret = da8xx_register_usb_phy_clocks(); - if (ret) - pr_warn("%s: USB PHY CLK registration failed: %d\n", - __func__, ret); - - gpiod_add_lookup_tables(hawk_usb_gpio_lookups, - ARRAY_SIZE(hawk_usb_gpio_lookups)); - - ret = da8xx_register_usb_phy(); - if (ret) - pr_warn("%s: USB PHY registration failed: %d\n", - __func__, ret); - - ret = platform_device_register(&hawk_usb_vbus_device); - if (ret) { - pr_warn("%s: Unable to register the vbus supply\n", __func__); - return; - } - - ret = da8xx_register_usb11(&omapl138_hawk_usb11_pdata); - if (ret) - pr_warn("%s: USB 1.1 registration failed: %d\n", __func__, ret); - - return; -} - -static __init void omapl138_hawk_init(void) -{ - int ret; - - da850_register_clocks(); - - ret = da850_register_gpio(); - if (ret) - pr_warn("%s: GPIO init failed: %d\n", __func__, ret); - - davinci_serial_init(da8xx_serial_device); - - omapl138_hawk_config_emac(); - - ret = da850_register_edma(da850_edma_rsv); - if (ret) - pr_warn("%s: EDMA registration failed: %d\n", __func__, ret); - - omapl138_hawk_mmc_init(); - - omapl138_hawk_usb_init(); - - ret = omapl138_hawk_register_aemif(); - if (ret) - pr_warn("%s: aemif registration failed: %d\n", __func__, ret); - - ret = da8xx_register_watchdog(); - if (ret) - pr_warn("%s: watchdog registration failed: %d\n", - __func__, ret); - - ret = da8xx_register_rproc(); - if (ret) - pr_warn("%s: dsp/rproc registration failed: %d\n", - __func__, ret); - - regulator_has_full_constraints(); -} - -#ifdef CONFIG_SERIAL_8250_CONSOLE -static int __init omapl138_hawk_console_init(void) -{ - if (!machine_is_omapl138_hawkboard()) - return 0; - - return add_preferred_console("ttyS", 2, "115200"); -} -console_initcall(omapl138_hawk_console_init); -#endif - -static void __init omapl138_hawk_map_io(void) -{ - da850_init(); -} - -MACHINE_START(OMAPL138_HAWKBOARD, "AM18x/OMAP-L138 Hawkboard") - .atag_offset = 0x100, - .map_io = omapl138_hawk_map_io, - .init_irq = da850_init_irq, - .init_time = da850_init_time, - .init_machine = omapl138_hawk_init, - .init_late = davinci_init_late, - .dma_zone_size = SZ_128M, - .reserve = da8xx_rproc_reserve_cma, -MACHINE_END diff --git a/arch/arm/mach-davinci/common.h b/arch/arm/mach-davinci/common.h index 772b51e0ac5ebe15270a5292689679cd53b2de3e..b4fd0e9acf6c60378b451bc07c9c48bee37dcd69 100644 --- a/arch/arm/mach-davinci/common.h +++ b/arch/arm/mach-davinci/common.h @@ -17,8 +17,8 @@ #include -#define DAVINCI_INTC_START NR_IRQS -#define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum)) +#define DAVINCI_INTC_START NR_IRQS +#define DAVINCI_INTC_IRQ(_irqnum) (DAVINCI_INTC_START + (_irqnum)) struct davinci_gpio_controller; @@ -45,9 +45,6 @@ struct davinci_soc_info { unsigned gpio_num; unsigned gpio_irq; unsigned gpio_unbanked; - struct davinci_gpio_controller *gpio_ctlrs; - int gpio_ctlrs_num; - struct emac_platform_data *emac_pdata; dma_addr_t sram_dma; unsigned sram_len; }; diff --git a/arch/arm/mach-davinci/cpuidle.c b/arch/arm/mach-davinci/cpuidle.c index dd38785536d51e933dc98f4d2c3ff0ae1f74741d..78a1575c387d9f84c1e89b01aad0e1ea5f705c7b 100644 --- a/arch/arm/mach-davinci/cpuidle.c +++ b/arch/arm/mach-davinci/cpuidle.c @@ -44,8 +44,8 @@ static void davinci_save_ddr_power(int enter, bool pdown) } /* Actual code that puts the SoC in different idle states */ -static int davinci_enter_idle(struct cpuidle_device *dev, - struct cpuidle_driver *drv, int index) +static __cpuidle int davinci_enter_idle(struct cpuidle_device *dev, + struct cpuidle_driver *drv, int index) { davinci_save_ddr_power(1, ddr2_pdown); cpu_do_idle(); diff --git a/arch/arm/mach-davinci/cputype.h b/arch/arm/mach-davinci/cputype.h index 4590afdbe449ec5e5f0f825ef28a9bccef78ec0a..148a738391dc97d0efd9eece3f54d097c1d58e49 100644 --- a/arch/arm/mach-davinci/cputype.h +++ b/arch/arm/mach-davinci/cputype.h @@ -25,60 +25,7 @@ struct davinci_id { }; /* Can use lower 16 bits of cpu id for a variant when required */ -#define DAVINCI_CPU_ID_DM6446 0x64460000 -#define DAVINCI_CPU_ID_DM6467 0x64670000 -#define DAVINCI_CPU_ID_DM355 0x03550000 -#define DAVINCI_CPU_ID_DM365 0x03650000 #define DAVINCI_CPU_ID_DA830 0x08300000 #define DAVINCI_CPU_ID_DA850 0x08500000 -#define IS_DAVINCI_CPU(type, id) \ -static inline int is_davinci_ ##type(void) \ -{ \ - return (davinci_soc_info.cpu_id == (id)); \ -} - -IS_DAVINCI_CPU(dm644x, DAVINCI_CPU_ID_DM6446) -IS_DAVINCI_CPU(dm646x, DAVINCI_CPU_ID_DM6467) -IS_DAVINCI_CPU(dm355, DAVINCI_CPU_ID_DM355) -IS_DAVINCI_CPU(dm365, DAVINCI_CPU_ID_DM365) -IS_DAVINCI_CPU(da830, DAVINCI_CPU_ID_DA830) -IS_DAVINCI_CPU(da850, DAVINCI_CPU_ID_DA850) - -#ifdef CONFIG_ARCH_DAVINCI_DM644x -#define cpu_is_davinci_dm644x() is_davinci_dm644x() -#else -#define cpu_is_davinci_dm644x() 0 -#endif - -#ifdef CONFIG_ARCH_DAVINCI_DM646x -#define cpu_is_davinci_dm646x() is_davinci_dm646x() -#else -#define cpu_is_davinci_dm646x() 0 -#endif - -#ifdef CONFIG_ARCH_DAVINCI_DM355 -#define cpu_is_davinci_dm355() is_davinci_dm355() -#else -#define cpu_is_davinci_dm355() 0 -#endif - -#ifdef CONFIG_ARCH_DAVINCI_DM365 -#define cpu_is_davinci_dm365() is_davinci_dm365() -#else -#define cpu_is_davinci_dm365() 0 -#endif - -#ifdef CONFIG_ARCH_DAVINCI_DA830 -#define cpu_is_davinci_da830() is_davinci_da830() -#else -#define cpu_is_davinci_da830() 0 -#endif - -#ifdef CONFIG_ARCH_DAVINCI_DA850 -#define cpu_is_davinci_da850() is_davinci_da850() -#else -#define cpu_is_davinci_da850() 0 -#endif - #endif diff --git a/arch/arm/mach-davinci/da830.c b/arch/arm/mach-davinci/da830.c index eab5fac188065232bcc0f6c67cae4571001a26a5..2e497745b6246c21f225f574c4baeaa5edd93d78 100644 --- a/arch/arm/mach-davinci/da830.c +++ b/arch/arm/mach-davinci/da830.c @@ -12,7 +12,6 @@ #include #include #include -#include #include @@ -448,181 +447,6 @@ static const struct mux_config da830_pins[] = { #endif }; -const short da830_emif25_pins[] __initconst = { - DA830_EMA_D_0, DA830_EMA_D_1, DA830_EMA_D_2, DA830_EMA_D_3, - DA830_EMA_D_4, DA830_EMA_D_5, DA830_EMA_D_6, DA830_EMA_D_7, - DA830_EMA_D_8, DA830_EMA_D_9, DA830_EMA_D_10, DA830_EMA_D_11, - DA830_EMA_D_12, DA830_EMA_D_13, DA830_EMA_D_14, DA830_EMA_D_15, - DA830_EMA_A_0, DA830_EMA_A_1, DA830_EMA_A_2, DA830_EMA_A_3, - DA830_EMA_A_4, DA830_EMA_A_5, DA830_EMA_A_6, DA830_EMA_A_7, - DA830_EMA_A_8, DA830_EMA_A_9, DA830_EMA_A_10, DA830_EMA_A_11, - DA830_EMA_A_12, DA830_EMA_BA_0, DA830_EMA_BA_1, DA830_EMA_CLK, - DA830_EMA_SDCKE, DA830_NEMA_CS_4, DA830_NEMA_CS_5, DA830_NEMA_WE, - DA830_NEMA_CS_0, DA830_NEMA_CS_2, DA830_NEMA_CS_3, DA830_NEMA_OE, - DA830_NEMA_WE_DQM_1, DA830_NEMA_WE_DQM_0, DA830_EMA_WAIT_0, - -1 -}; - -const short da830_spi0_pins[] __initconst = { - DA830_SPI0_SOMI_0, DA830_SPI0_SIMO_0, DA830_SPI0_CLK, DA830_NSPI0_ENA, - DA830_NSPI0_SCS_0, - -1 -}; - -const short da830_spi1_pins[] __initconst = { - DA830_SPI1_SOMI_0, DA830_SPI1_SIMO_0, DA830_SPI1_CLK, DA830_NSPI1_ENA, - DA830_NSPI1_SCS_0, - -1 -}; - -const short da830_mmc_sd_pins[] __initconst = { - DA830_MMCSD_DAT_0, DA830_MMCSD_DAT_1, DA830_MMCSD_DAT_2, - DA830_MMCSD_DAT_3, DA830_MMCSD_DAT_4, DA830_MMCSD_DAT_5, - DA830_MMCSD_DAT_6, DA830_MMCSD_DAT_7, DA830_MMCSD_CLK, - DA830_MMCSD_CMD, - -1 -}; - -const short da830_uart0_pins[] __initconst = { - DA830_NUART0_CTS, DA830_NUART0_RTS, DA830_UART0_RXD, DA830_UART0_TXD, - -1 -}; - -const short da830_uart1_pins[] __initconst = { - DA830_UART1_RXD, DA830_UART1_TXD, - -1 -}; - -const short da830_uart2_pins[] __initconst = { - DA830_UART2_RXD, DA830_UART2_TXD, - -1 -}; - -const short da830_usb20_pins[] __initconst = { - DA830_USB0_DRVVBUS, DA830_USB_REFCLKIN, - -1 -}; - -const short da830_usb11_pins[] __initconst = { - DA830_USB_REFCLKIN, - -1 -}; - -const short da830_uhpi_pins[] __initconst = { - DA830_UHPI_HD_0, DA830_UHPI_HD_1, DA830_UHPI_HD_2, DA830_UHPI_HD_3, - DA830_UHPI_HD_4, DA830_UHPI_HD_5, DA830_UHPI_HD_6, DA830_UHPI_HD_7, - DA830_UHPI_HD_8, DA830_UHPI_HD_9, DA830_UHPI_HD_10, DA830_UHPI_HD_11, - DA830_UHPI_HD_12, DA830_UHPI_HD_13, DA830_UHPI_HD_14, DA830_UHPI_HD_15, - DA830_UHPI_HCNTL0, DA830_UHPI_HCNTL1, DA830_UHPI_HHWIL, DA830_UHPI_HRNW, - DA830_NUHPI_HAS, DA830_NUHPI_HCS, DA830_NUHPI_HDS1, DA830_NUHPI_HDS2, - DA830_NUHPI_HINT, DA830_NUHPI_HRDY, - -1 -}; - -const short da830_cpgmac_pins[] __initconst = { - DA830_RMII_TXD_0, DA830_RMII_TXD_1, DA830_RMII_TXEN, DA830_RMII_CRS_DV, - DA830_RMII_RXD_0, DA830_RMII_RXD_1, DA830_RMII_RXER, DA830_MDIO_CLK, - DA830_MDIO_D, - -1 -}; - -const short da830_emif3c_pins[] __initconst = { - DA830_EMB_SDCKE, DA830_EMB_CLK_GLUE, DA830_EMB_CLK, DA830_NEMB_CS_0, - DA830_NEMB_CAS, DA830_NEMB_RAS, DA830_NEMB_WE, DA830_EMB_BA_1, - DA830_EMB_BA_0, DA830_EMB_A_0, DA830_EMB_A_1, DA830_EMB_A_2, - DA830_EMB_A_3, DA830_EMB_A_4, DA830_EMB_A_5, DA830_EMB_A_6, - DA830_EMB_A_7, DA830_EMB_A_8, DA830_EMB_A_9, DA830_EMB_A_10, - DA830_EMB_A_11, DA830_EMB_A_12, DA830_NEMB_WE_DQM_3, - DA830_NEMB_WE_DQM_2, DA830_EMB_D_0, DA830_EMB_D_1, DA830_EMB_D_2, - DA830_EMB_D_3, DA830_EMB_D_4, DA830_EMB_D_5, DA830_EMB_D_6, - DA830_EMB_D_7, DA830_EMB_D_8, DA830_EMB_D_9, DA830_EMB_D_10, - DA830_EMB_D_11, DA830_EMB_D_12, DA830_EMB_D_13, DA830_EMB_D_14, - DA830_EMB_D_15, DA830_EMB_D_16, DA830_EMB_D_17, DA830_EMB_D_18, - DA830_EMB_D_19, DA830_EMB_D_20, DA830_EMB_D_21, DA830_EMB_D_22, - DA830_EMB_D_23, DA830_EMB_D_24, DA830_EMB_D_25, DA830_EMB_D_26, - DA830_EMB_D_27, DA830_EMB_D_28, DA830_EMB_D_29, DA830_EMB_D_30, - DA830_EMB_D_31, DA830_NEMB_WE_DQM_1, DA830_NEMB_WE_DQM_0, - -1 -}; - -const short da830_mcasp0_pins[] __initconst = { - DA830_AHCLKX0, DA830_ACLKX0, DA830_AFSX0, - DA830_AHCLKR0, DA830_ACLKR0, DA830_AFSR0, DA830_AMUTE0, - DA830_AXR0_0, DA830_AXR0_1, DA830_AXR0_2, DA830_AXR0_3, - DA830_AXR0_4, DA830_AXR0_5, DA830_AXR0_6, DA830_AXR0_7, - DA830_AXR0_8, DA830_AXR0_9, DA830_AXR0_10, DA830_AXR0_11, - DA830_AXR0_12, DA830_AXR0_13, DA830_AXR0_14, DA830_AXR0_15, - -1 -}; - -const short da830_mcasp1_pins[] __initconst = { - DA830_AHCLKX1, DA830_ACLKX1, DA830_AFSX1, - DA830_AHCLKR1, DA830_ACLKR1, DA830_AFSR1, DA830_AMUTE1, - DA830_AXR1_0, DA830_AXR1_1, DA830_AXR1_2, DA830_AXR1_3, - DA830_AXR1_4, DA830_AXR1_5, DA830_AXR1_6, DA830_AXR1_7, - DA830_AXR1_8, DA830_AXR1_9, DA830_AXR1_10, DA830_AXR1_11, - -1 -}; - -const short da830_mcasp2_pins[] __initconst = { - DA830_AHCLKX2, DA830_ACLKX2, DA830_AFSX2, - DA830_AHCLKR2, DA830_ACLKR2, DA830_AFSR2, DA830_AMUTE2, - DA830_AXR2_0, DA830_AXR2_1, DA830_AXR2_2, DA830_AXR2_3, - -1 -}; - -const short da830_i2c0_pins[] __initconst = { - DA830_I2C0_SDA, DA830_I2C0_SCL, - -1 -}; - -const short da830_i2c1_pins[] __initconst = { - DA830_I2C1_SCL, DA830_I2C1_SDA, - -1 -}; - -const short da830_lcdcntl_pins[] __initconst = { - DA830_LCD_D_0, DA830_LCD_D_1, DA830_LCD_D_2, DA830_LCD_D_3, - DA830_LCD_D_4, DA830_LCD_D_5, DA830_LCD_D_6, DA830_LCD_D_7, - DA830_LCD_D_8, DA830_LCD_D_9, DA830_LCD_D_10, DA830_LCD_D_11, - DA830_LCD_D_12, DA830_LCD_D_13, DA830_LCD_D_14, DA830_LCD_D_15, - DA830_LCD_PCLK, DA830_LCD_HSYNC, DA830_LCD_VSYNC, DA830_NLCD_AC_ENB_CS, - DA830_LCD_MCLK, - -1 -}; - -const short da830_pwm_pins[] __initconst = { - DA830_ECAP0_APWM0, DA830_ECAP1_APWM1, DA830_EPWM0B, DA830_EPWM0A, - DA830_EPWMSYNCI, DA830_EPWMSYNC0, DA830_ECAP2_APWM2, DA830_EHRPWMGLUETZ, - DA830_EPWM2B, DA830_EPWM2A, DA830_EPWM1B, DA830_EPWM1A, - -1 -}; - -const short da830_ecap0_pins[] __initconst = { - DA830_ECAP0_APWM0, - -1 -}; - -const short da830_ecap1_pins[] __initconst = { - DA830_ECAP1_APWM1, - -1 -}; - -const short da830_ecap2_pins[] __initconst = { - DA830_ECAP2_APWM2, - -1 -}; - -const short da830_eqep0_pins[] __initconst = { - DA830_EQEP0I, DA830_EQEP0S, DA830_EQEP0A, DA830_EQEP0B, - -1 -}; - -const short da830_eqep1_pins[] __initconst = { - DA830_EQEP1I, DA830_EQEP1S, DA830_EQEP1A, DA830_EQEP1B, - -1 -}; - static struct map_desc da830_io_desc[] = { { .virtual = IO_VIRT, @@ -663,30 +487,6 @@ static struct davinci_id da830_ids[] = { }, }; -static struct davinci_gpio_platform_data da830_gpio_platform_data = { - .no_auto_base = true, - .base = 0, - .ngpio = 128, -}; - -int __init da830_register_gpio(void) -{ - return da8xx_register_gpio(&da830_gpio_platform_data); -} - -/* - * Bottom half of timer0 is used both for clock even and clocksource. - * Top half is used by DSP. - */ -static const struct davinci_timer_cfg da830_timer_cfg = { - .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K), - .irq = { - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA830_T12CMPINT0_0)), - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)), - }, - .cmp_off = DA830_CMP12_0, -}; - static const struct davinci_soc_info davinci_soc_info_da830 = { .io_desc = da830_io_desc, .io_desc_num = ARRAY_SIZE(da830_io_desc), @@ -696,7 +496,6 @@ static const struct davinci_soc_info davinci_soc_info_da830 = { .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, .pinmux_pins = da830_pins, .pinmux_pins_num = ARRAY_SIZE(da830_pins), - .emac_pdata = &da8xx_emac_pdata, }; void __init da830_init(void) @@ -706,76 +505,3 @@ void __init da830_init(void) da8xx_syscfg0_base = ioremap(DA8XX_SYSCFG0_BASE, SZ_4K); WARN(!da8xx_syscfg0_base, "Unable to map syscfg0 module"); } - -static const struct davinci_cp_intc_config da830_cp_intc_config = { - .reg = { - .start = DA8XX_CP_INTC_BASE, - .end = DA8XX_CP_INTC_BASE + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, - .num_irqs = DA830_N_CP_INTC_IRQ, -}; - -void __init da830_init_irq(void) -{ - davinci_cp_intc_init(&da830_cp_intc_config); -} - -void __init da830_init_time(void) -{ - void __iomem *pll; - struct clk *clk; - int rv; - - clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA830_REF_FREQ); - - pll = ioremap(DA8XX_PLL0_BASE, SZ_4K); - - da830_pll_init(NULL, pll, NULL); - - clk = clk_get(NULL, "timer0"); - if (WARN_ON(IS_ERR(clk))) { - pr_err("Unable to get the timer clock\n"); - return; - } - - rv = davinci_timer_register(clk, &da830_timer_cfg); - WARN(rv, "Unable to register the timer: %d\n", rv); -} - -static struct resource da830_psc0_resources[] = { - { - .start = DA8XX_PSC0_BASE, - .end = DA8XX_PSC0_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device da830_psc0_device = { - .name = "da830-psc0", - .id = -1, - .resource = da830_psc0_resources, - .num_resources = ARRAY_SIZE(da830_psc0_resources), -}; - -static struct resource da830_psc1_resources[] = { - { - .start = DA8XX_PSC1_BASE, - .end = DA8XX_PSC1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device da830_psc1_device = { - .name = "da830-psc1", - .id = -1, - .resource = da830_psc1_resources, - .num_resources = ARRAY_SIZE(da830_psc1_resources), -}; - -void __init da830_register_clocks(void) -{ - /* PLL is registered in da830_init_time() */ - platform_device_register(&da830_psc0_device); - platform_device_register(&da830_psc1_device); -} diff --git a/arch/arm/mach-davinci/da850.c b/arch/arm/mach-davinci/da850.c index 635e88daf5ddf7000233efeaba917f618599f1e9..287dd987908e53429cb5cb39221facd1a5498d03 100644 --- a/arch/arm/mach-davinci/da850.c +++ b/arch/arm/mach-davinci/da850.c @@ -10,19 +10,10 @@ * 2009 (c) MontaVista Software, Inc. */ -#include -#include -#include -#include #include #include #include -#include #include -#include -#include -#include -#include #include #include #include @@ -33,6 +24,7 @@ #include "common.h" #include "cputype.h" #include "da8xx.h" +#include "hardware.h" #include "pm.h" #include "irqs.h" #include "mux.h" @@ -258,45 +250,6 @@ static const struct mux_config da850_pins[] = { #endif }; -const short da850_i2c0_pins[] __initconst = { - DA850_I2C0_SDA, DA850_I2C0_SCL, - -1 -}; - -const short da850_i2c1_pins[] __initconst = { - DA850_I2C1_SCL, DA850_I2C1_SDA, - -1 -}; - -const short da850_lcdcntl_pins[] __initconst = { - DA850_LCD_D_0, DA850_LCD_D_1, DA850_LCD_D_2, DA850_LCD_D_3, - DA850_LCD_D_4, DA850_LCD_D_5, DA850_LCD_D_6, DA850_LCD_D_7, - DA850_LCD_D_8, DA850_LCD_D_9, DA850_LCD_D_10, DA850_LCD_D_11, - DA850_LCD_D_12, DA850_LCD_D_13, DA850_LCD_D_14, DA850_LCD_D_15, - DA850_LCD_PCLK, DA850_LCD_HSYNC, DA850_LCD_VSYNC, DA850_NLCD_AC_ENB_CS, - -1 -}; - -const short da850_vpif_capture_pins[] __initconst = { - DA850_VPIF_DIN0, DA850_VPIF_DIN1, DA850_VPIF_DIN2, DA850_VPIF_DIN3, - DA850_VPIF_DIN4, DA850_VPIF_DIN5, DA850_VPIF_DIN6, DA850_VPIF_DIN7, - DA850_VPIF_DIN8, DA850_VPIF_DIN9, DA850_VPIF_DIN10, DA850_VPIF_DIN11, - DA850_VPIF_DIN12, DA850_VPIF_DIN13, DA850_VPIF_DIN14, DA850_VPIF_DIN15, - DA850_VPIF_CLKIN0, DA850_VPIF_CLKIN1, DA850_VPIF_CLKIN2, - DA850_VPIF_CLKIN3, - -1 -}; - -const short da850_vpif_display_pins[] __initconst = { - DA850_VPIF_DOUT0, DA850_VPIF_DOUT1, DA850_VPIF_DOUT2, DA850_VPIF_DOUT3, - DA850_VPIF_DOUT4, DA850_VPIF_DOUT5, DA850_VPIF_DOUT6, DA850_VPIF_DOUT7, - DA850_VPIF_DOUT8, DA850_VPIF_DOUT9, DA850_VPIF_DOUT10, - DA850_VPIF_DOUT11, DA850_VPIF_DOUT12, DA850_VPIF_DOUT13, - DA850_VPIF_DOUT14, DA850_VPIF_DOUT15, DA850_VPIF_CLKO2, - DA850_VPIF_CLKO3, - -1 -}; - static struct map_desc da850_io_desc[] = { { .virtual = IO_VIRT, @@ -330,204 +283,9 @@ static struct davinci_id da850_ids[] = { }, }; -/* - * Bottom half of timer 0 is used for clock_event, top half for - * clocksource. - */ -static const struct davinci_timer_cfg da850_timer_cfg = { - .reg = DEFINE_RES_IO(DA8XX_TIMER64P0_BASE, SZ_4K), - .irq = { - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT12_0)), - DEFINE_RES_IRQ(DAVINCI_INTC_IRQ(IRQ_DA8XX_TINT34_0)), - }, -}; - -#ifdef CONFIG_CPU_FREQ -/* - * Notes: - * According to the TRM, minimum PLLM results in maximum power savings. - * The OPP definitions below should keep the PLLM as low as possible. - * - * The output of the PLLM must be between 300 to 600 MHz. - */ -struct da850_opp { - unsigned int freq; /* in KHz */ - unsigned int prediv; - unsigned int mult; - unsigned int postdiv; - unsigned int cvdd_min; /* in uV */ - unsigned int cvdd_max; /* in uV */ -}; - -static const struct da850_opp da850_opp_456 = { - .freq = 456000, - .prediv = 1, - .mult = 19, - .postdiv = 1, - .cvdd_min = 1300000, - .cvdd_max = 1350000, -}; - -static const struct da850_opp da850_opp_408 = { - .freq = 408000, - .prediv = 1, - .mult = 17, - .postdiv = 1, - .cvdd_min = 1300000, - .cvdd_max = 1350000, -}; - -static const struct da850_opp da850_opp_372 = { - .freq = 372000, - .prediv = 2, - .mult = 31, - .postdiv = 1, - .cvdd_min = 1200000, - .cvdd_max = 1320000, -}; - -static const struct da850_opp da850_opp_300 = { - .freq = 300000, - .prediv = 1, - .mult = 25, - .postdiv = 2, - .cvdd_min = 1200000, - .cvdd_max = 1320000, -}; - -static const struct da850_opp da850_opp_200 = { - .freq = 200000, - .prediv = 1, - .mult = 25, - .postdiv = 3, - .cvdd_min = 1100000, - .cvdd_max = 1160000, -}; - -static const struct da850_opp da850_opp_96 = { - .freq = 96000, - .prediv = 1, - .mult = 20, - .postdiv = 5, - .cvdd_min = 1000000, - .cvdd_max = 1050000, -}; - -#define OPP(freq) \ - { \ - .driver_data = (unsigned int) &da850_opp_##freq, \ - .frequency = freq * 1000, \ - } - -static struct cpufreq_frequency_table da850_freq_table[] = { - OPP(456), - OPP(408), - OPP(372), - OPP(300), - OPP(200), - OPP(96), - { - .driver_data = 0, - .frequency = CPUFREQ_TABLE_END, - }, -}; - -#ifdef CONFIG_REGULATOR -static int da850_set_voltage(unsigned int index); -static int da850_regulator_init(void); -#endif - -static struct davinci_cpufreq_config cpufreq_info = { - .freq_table = da850_freq_table, -#ifdef CONFIG_REGULATOR - .init = da850_regulator_init, - .set_voltage = da850_set_voltage, -#endif -}; - -#ifdef CONFIG_REGULATOR -static struct regulator *cvdd; - -static int da850_set_voltage(unsigned int index) -{ - struct da850_opp *opp; - - if (!cvdd) - return -ENODEV; - - opp = (struct da850_opp *) cpufreq_info.freq_table[index].driver_data; - - return regulator_set_voltage(cvdd, opp->cvdd_min, opp->cvdd_max); -} - -static int da850_regulator_init(void) -{ - cvdd = regulator_get(NULL, "cvdd"); - if (WARN(IS_ERR(cvdd), "Unable to obtain voltage regulator for CVDD;" - " voltage scaling unsupported\n")) { - return PTR_ERR(cvdd); - } - - return 0; -} -#endif - -static struct platform_device da850_cpufreq_device = { - .name = "cpufreq-davinci", - .dev = { - .platform_data = &cpufreq_info, - }, - .id = -1, -}; - -unsigned int da850_max_speed = 300000; - -int da850_register_cpufreq(char *async_clk) -{ - int i; - - /* cpufreq driver can help keep an "async" clock constant */ - if (async_clk) - clk_add_alias("async", da850_cpufreq_device.name, - async_clk, NULL); - for (i = 0; i < ARRAY_SIZE(da850_freq_table); i++) { - if (da850_freq_table[i].frequency <= da850_max_speed) { - cpufreq_info.freq_table = &da850_freq_table[i]; - break; - } - } - - return platform_device_register(&da850_cpufreq_device); -} -#else -int __init da850_register_cpufreq(char *async_clk) -{ - return 0; -} -#endif - /* VPIF resource, platform data */ static u64 da850_vpif_dma_mask = DMA_BIT_MASK(32); -static struct resource da850_vpif_resource[] = { - { - .start = DA8XX_VPIF_BASE, - .end = DA8XX_VPIF_BASE + 0xfff, - .flags = IORESOURCE_MEM, - } -}; - -static struct platform_device da850_vpif_dev = { - .name = "vpif", - .id = -1, - .dev = { - .dma_mask = &da850_vpif_dma_mask, - .coherent_dma_mask = DMA_BIT_MASK(32), - }, - .resource = da850_vpif_resource, - .num_resources = ARRAY_SIZE(da850_vpif_resource), -}; - static struct resource da850_vpif_display_resource[] = { { .start = DAVINCI_INTC_IRQ(IRQ_DA850_VPIFINT), @@ -571,11 +329,6 @@ static struct platform_device da850_vpif_capture_dev = { .num_resources = ARRAY_SIZE(da850_vpif_capture_resource), }; -int __init da850_register_vpif(void) -{ - return platform_device_register(&da850_vpif_dev); -} - int __init da850_register_vpif_display(struct vpif_display_config *display_config) { @@ -590,17 +343,6 @@ int __init da850_register_vpif_capture(struct vpif_capture_config return platform_device_register(&da850_vpif_capture_dev); } -static struct davinci_gpio_platform_data da850_gpio_platform_data = { - .no_auto_base = true, - .base = 0, - .ngpio = 144, -}; - -int __init da850_register_gpio(void) -{ - return da8xx_register_gpio(&da850_gpio_platform_data); -} - static const struct davinci_soc_info davinci_soc_info_da850 = { .io_desc = da850_io_desc, .io_desc_num = ARRAY_SIZE(da850_io_desc), @@ -610,7 +352,6 @@ static const struct davinci_soc_info davinci_soc_info_da850 = { .pinmux_base = DA8XX_SYSCFG0_BASE + 0x120, .pinmux_pins = da850_pins, .pinmux_pins_num = ARRAY_SIZE(da850_pins), - .emac_pdata = &da8xx_emac_pdata, .sram_dma = DA8XX_SHARED_RAM_BASE, .sram_len = SZ_128K, }; @@ -626,142 +367,3 @@ void __init da850_init(void) da8xx_syscfg1_base = ioremap(DA8XX_SYSCFG1_BASE, SZ_4K); WARN(!da8xx_syscfg1_base, "Unable to map syscfg1 module"); } - -static const struct davinci_cp_intc_config da850_cp_intc_config = { - .reg = { - .start = DA8XX_CP_INTC_BASE, - .end = DA8XX_CP_INTC_BASE + SZ_8K - 1, - .flags = IORESOURCE_MEM, - }, - .num_irqs = DA850_N_CP_INTC_IRQ, -}; - -void __init da850_init_irq(void) -{ - davinci_cp_intc_init(&da850_cp_intc_config); -} - -void __init da850_init_time(void) -{ - void __iomem *pll0; - struct regmap *cfgchip; - struct clk *clk; - int rv; - - clk_register_fixed_rate(NULL, "ref_clk", NULL, 0, DA850_REF_FREQ); - - pll0 = ioremap(DA8XX_PLL0_BASE, SZ_4K); - cfgchip = da8xx_get_cfgchip(); - - da850_pll0_init(NULL, pll0, cfgchip); - - clk = clk_get(NULL, "timer0"); - if (WARN_ON(IS_ERR(clk))) { - pr_err("Unable to get the timer clock\n"); - return; - } - - rv = davinci_timer_register(clk, &da850_timer_cfg); - WARN(rv, "Unable to register the timer: %d\n", rv); -} - -static struct resource da850_pll1_resources[] = { - { - .start = DA850_PLL1_BASE, - .end = DA850_PLL1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct davinci_pll_platform_data da850_pll1_pdata; - -static struct platform_device da850_pll1_device = { - .name = "da850-pll1", - .id = -1, - .resource = da850_pll1_resources, - .num_resources = ARRAY_SIZE(da850_pll1_resources), - .dev = { - .platform_data = &da850_pll1_pdata, - }, -}; - -static struct resource da850_psc0_resources[] = { - { - .start = DA8XX_PSC0_BASE, - .end = DA8XX_PSC0_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device da850_psc0_device = { - .name = "da850-psc0", - .id = -1, - .resource = da850_psc0_resources, - .num_resources = ARRAY_SIZE(da850_psc0_resources), -}; - -static struct resource da850_psc1_resources[] = { - { - .start = DA8XX_PSC1_BASE, - .end = DA8XX_PSC1_BASE + SZ_4K - 1, - .flags = IORESOURCE_MEM, - }, -}; - -static struct platform_device da850_psc1_device = { - .name = "da850-psc1", - .id = -1, - .resource = da850_psc1_resources, - .num_resources = ARRAY_SIZE(da850_psc1_resources), -}; - -static struct da8xx_cfgchip_clk_platform_data da850_async1_pdata; - -static struct platform_device da850_async1_clksrc_device = { - .name = "da850-async1-clksrc", - .id = -1, - .dev = { - .platform_data = &da850_async1_pdata, - }, -}; - -static struct da8xx_cfgchip_clk_platform_data da850_async3_pdata; - -static struct platform_device da850_async3_clksrc_device = { - .name = "da850-async3-clksrc", - .id = -1, - .dev = { - .platform_data = &da850_async3_pdata, - }, -}; - -static struct da8xx_cfgchip_clk_platform_data da850_tbclksync_pdata; - -static struct platform_device da850_tbclksync_device = { - .name = "da830-tbclksync", - .id = -1, - .dev = { - .platform_data = &da850_tbclksync_pdata, - }, -}; - -void __init da850_register_clocks(void) -{ - /* PLL0 is registered in da850_init_time() */ - - da850_pll1_pdata.cfgchip = da8xx_get_cfgchip(); - platform_device_register(&da850_pll1_device); - - da850_async1_pdata.cfgchip = da8xx_get_cfgchip(); - platform_device_register(&da850_async1_clksrc_device); - - da850_async3_pdata.cfgchip = da8xx_get_cfgchip(); - platform_device_register(&da850_async3_clksrc_device); - - platform_device_register(&da850_psc0_device); - - platform_device_register(&da850_psc1_device); - - da850_tbclksync_pdata.cfgchip = da8xx_get_cfgchip(); - platform_device_register(&da850_tbclksync_device); -} diff --git a/arch/arm/mach-davinci/da8xx.h b/arch/arm/mach-davinci/da8xx.h index 382811dbbc3b3bd5a13b75683a2a680ed1861765..54a255b8d8d8113ab4a820302b16fb4531fa81a7 100644 --- a/arch/arm/mach-davinci/da8xx.h +++ b/arch/arm/mach-davinci/da8xx.h @@ -9,38 +9,20 @@ #ifndef __ASM_ARCH_DAVINCI_DA8XX_H #define __ASM_ARCH_DAVINCI_DA8XX_H -#include