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Commit 32cae024 authored by Abhishek Sahu's avatar Abhishek Sahu Committed by Stephen Boyd
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clk: qcom: ipq8074: fix missing GPLL0 divider width 



GPLL0 uses 4 bits post divider which should be specified
in clock driver structure.

Signed-off-by: default avatarAbhishek Sahu <absahu@codeaurora.org>
Signed-off-by: default avatarStephen Boyd <sboyd@codeaurora.org>
parent df964016
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