Skip to content
Commit 3a3c9dc4 authored by Max Filippov's avatar Max Filippov
Browse files

target-xtensa: implement RER/WER instructions 



RER and WER are privileged instructions for accessing external
registers. External register address space is local to processor core.
There's no alignment requirements, addressable units are 32-bit wide
registers.

Signed-off-by: default avatarMax Filippov <jcmvbkbc@gmail.com>
parent 8b912ff0
Show whitespace changes
Inline Side-by-side
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Please register or to comment